Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into drm-next
authorDave Airlie <airlied@redhat.com>
Thu, 31 Jan 2019 23:51:23 +0000 (09:51 +1000)
committerDave Airlie <airlied@redhat.com>
Fri, 1 Feb 2019 00:01:50 +0000 (10:01 +1000)
This pull includes the new Arm "komeda" DRM driver. It is currently hosted
in the same repo as the other "mali-dp" driver because it is the next
iteration of the IP.

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Liviu Dudau <Liviu.Dudau@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190131173600.GN25147@e110455-lin.cambridge.arm.com
662 files changed:
Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt
Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
Documentation/devicetree/bindings/display/bridge/thine,thc63lvdm83d.txt
Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt [new file with mode: 0644]
Documentation/devicetree/bindings/display/panel/auo,g101evn010.txt [moved from Documentation/devicetree/bindings/display/panel/auo,g101evn010 with 100% similarity]
Documentation/devicetree/bindings/display/renesas,du.txt
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
Documentation/gpu/dp-mst/topology-figure-1.dot [new file with mode: 0644]
Documentation/gpu/dp-mst/topology-figure-2.dot [new file with mode: 0644]
Documentation/gpu/dp-mst/topology-figure-3.dot [new file with mode: 0644]
Documentation/gpu/drm-internals.rst
Documentation/gpu/drm-kms-helpers.rst
Documentation/gpu/todo.rst
MAINTAINERS
drivers/acpi/pmic/intel_pmic.c
drivers/acpi/pmic/intel_pmic.h
drivers/acpi/pmic/intel_pmic_chtwc.c
drivers/acpi/pmic/intel_pmic_xpower.c
drivers/dma-buf/dma-buf.c
drivers/dma-buf/dma-fence.c
drivers/dma-buf/sw_sync.c
drivers/dma-buf/sync_debug.c
drivers/dma-buf/sync_file.c
drivers/gpu/drm/Kconfig
drivers/gpu/drm/amd/amdgpu/Makefile
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
drivers/gpu/drm/amd/amdgpu/atom.c
drivers/gpu/drm/amd/amdgpu/ci_dpm.c [deleted file]
drivers/gpu/drm/amd/amdgpu/ci_dpm.h [deleted file]
drivers/gpu/drm/amd/amdgpu/ci_smc.c [deleted file]
drivers/gpu/drm/amd/amdgpu/cik.c
drivers/gpu/drm/amd/amdgpu/cik_dpm.h
drivers/gpu/drm/amd/amdgpu/cik_ih.c
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/cz_ih.c
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
drivers/gpu/drm/amd/amdgpu/dce_virtual.c
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/amdgpu/iceland_ih.c
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/si.c
drivers/gpu/drm/amd/amdgpu/si_dma.c
drivers/gpu/drm/amd/amdgpu/si_ih.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/amdgpu/tonga_ih.c
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
drivers/gpu/drm/amd/amdgpu/vi.c
drivers/gpu/drm/amd/amdkfd/Kconfig
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
drivers/gpu/drm/amd/amdkfd/kfd_module.c
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
drivers/gpu/drm/amd/display/dc/Makefile
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
drivers/gpu/drm/amd/display/dc/bios/command_table.c
drivers/gpu/drm/amd/display/dc/bios/command_table.h
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
drivers/gpu/drm/amd/display/dc/bios/command_table2.h
drivers/gpu/drm/amd/display/dc/calcs/Makefile
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
drivers/gpu/drm/amd/display/dc/core/dc.c
drivers/gpu/drm/amd/display/dc/core/dc_link.c
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/dc.h
drivers/gpu/drm/amd/display/dc/dc_bios_types.h
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
drivers/gpu/drm/amd/display/dc/dc_helper.c
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
drivers/gpu/drm/amd/display/dc/dc_link.h
drivers/gpu/drm/amd/display/dc/dc_stream.h
drivers/gpu/drm/amd/display/dc/dc_types.h
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
drivers/gpu/drm/amd/display/dc/dm_services_types.h
drivers/gpu/drm/amd/display/dc/dml/Makefile
drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
drivers/gpu/drm/amd/display/dc/i2caux/Makefile [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/engine.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c [deleted file]
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h [deleted file]
drivers/gpu/drm/amd/display/dc/inc/clock_source.h
drivers/gpu/drm/amd/display/dc/inc/core_status.h
drivers/gpu/drm/amd/display/dc/inc/core_types.h
drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h [moved from drivers/gpu/drm/amd/display/dc/i2caux/engine_base.c with 63% similarity]
drivers/gpu/drm/amd/display/dc/inc/vm_helper.h [moved from drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.h with 65% similarity]
drivers/gpu/drm/amd/display/include/bios_parser_types.h
drivers/gpu/drm/amd/display/include/i2caux_interface.h
drivers/gpu/drm/amd/display/modules/color/color_gamma.c
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
drivers/gpu/drm/amd/display/modules/power/power_helpers.c
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
drivers/gpu/drm/amd/include/atombios.h
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
drivers/gpu/drm/amd/include/kgd_pp_interface.h
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h [moved from drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.h with 65% similarity]
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h [moved from drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.h with 74% similarity]
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h [moved from drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h with 73% similarity]
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
drivers/gpu/drm/arc/arcpgu_crtc.c
drivers/gpu/drm/arc/arcpgu_drv.c
drivers/gpu/drm/arc/arcpgu_sim.c
drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c
drivers/gpu/drm/armada/armada_crtc.c
drivers/gpu/drm/ast/ast_fb.c
drivers/gpu/drm/ati_pcigart.c
drivers/gpu/drm/bochs/Makefile
drivers/gpu/drm/bochs/bochs.h
drivers/gpu/drm/bochs/bochs_drv.c
drivers/gpu/drm/bochs/bochs_fbdev.c [deleted file]
drivers/gpu/drm/bochs/bochs_hw.c
drivers/gpu/drm/bochs/bochs_kms.c
drivers/gpu/drm/bochs/bochs_mm.c
drivers/gpu/drm/bridge/adv7511/adv7511.h
drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
drivers/gpu/drm/bridge/adv7511/adv7533.c
drivers/gpu/drm/bridge/analogix-anx78xx.c
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
drivers/gpu/drm/bridge/lvds-encoder.c
drivers/gpu/drm/bridge/panel.c
drivers/gpu/drm/bridge/sii902x.c
drivers/gpu/drm/bridge/sil-sii8620.c
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
drivers/gpu/drm/bridge/tc358767.c
drivers/gpu/drm/cirrus/cirrus_fbdev.c
drivers/gpu/drm/drm_atomic.c
drivers/gpu/drm/drm_bridge.c
drivers/gpu/drm/drm_bufs.c
drivers/gpu/drm/drm_color_mgmt.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/drm_context.c
drivers/gpu/drm/drm_crtc.c
drivers/gpu/drm/drm_crtc_helper.c
drivers/gpu/drm/drm_crtc_internal.h
drivers/gpu/drm/drm_damage_helper.c
drivers/gpu/drm/drm_dp_helper.c
drivers/gpu/drm/drm_dp_mst_topology.c
drivers/gpu/drm/drm_drv.c
drivers/gpu/drm/drm_edid.c
drivers/gpu/drm/drm_fb_cma_helper.c
drivers/gpu/drm/drm_fb_helper.c
drivers/gpu/drm/drm_flip_work.c
drivers/gpu/drm/drm_framebuffer.c
drivers/gpu/drm/drm_gem.c
drivers/gpu/drm/drm_gem_framebuffer_helper.c
drivers/gpu/drm/drm_internal.h
drivers/gpu/drm/drm_lease.c
drivers/gpu/drm/drm_mode_config.c
drivers/gpu/drm/drm_mode_object.c
drivers/gpu/drm/drm_modes.c
drivers/gpu/drm/drm_modeset_lock.c
drivers/gpu/drm/drm_of.c
drivers/gpu/drm/drm_panel.c
drivers/gpu/drm/drm_plane.c
drivers/gpu/drm/drm_syncobj.c
drivers/gpu/drm/drm_vblank.c
drivers/gpu/drm/etnaviv/etnaviv_gem.c
drivers/gpu/drm/etnaviv/etnaviv_sched.c
drivers/gpu/drm/exynos/exynos_drm_mic.c
drivers/gpu/drm/exynos/exynos_hdmi.c
drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h
drivers/gpu/drm/i2c/ch7006_drv.c
drivers/gpu/drm/i2c/tda998x_drv.c
drivers/gpu/drm/i915/Kconfig.debug
drivers/gpu/drm/i915/Makefile
drivers/gpu/drm/i915/dvo.h
drivers/gpu/drm/i915/gvt/Makefile
drivers/gpu/drm/i915/gvt/aperture_gm.c
drivers/gpu/drm/i915/gvt/cmd_parser.c
drivers/gpu/drm/i915/gvt/display.c
drivers/gpu/drm/i915/gvt/dmabuf.c
drivers/gpu/drm/i915/gvt/edid.c
drivers/gpu/drm/i915/gvt/fb_decoder.c
drivers/gpu/drm/i915/gvt/gvt.c
drivers/gpu/drm/i915/gvt/gvt.h
drivers/gpu/drm/i915/gvt/handlers.c
drivers/gpu/drm/i915/gvt/hypercall.h
drivers/gpu/drm/i915/gvt/interrupt.c
drivers/gpu/drm/i915/gvt/kvmgt.c
drivers/gpu/drm/i915/gvt/mmio.c
drivers/gpu/drm/i915/gvt/mmio.h
drivers/gpu/drm/i915/gvt/mmio_context.c
drivers/gpu/drm/i915/gvt/mpt.h
drivers/gpu/drm/i915/gvt/sched_policy.c
drivers/gpu/drm/i915/gvt/scheduler.c
drivers/gpu/drm/i915/gvt/scheduler.h
drivers/gpu/drm/i915/gvt/trace.h
drivers/gpu/drm/i915/gvt/vgpu.c
drivers/gpu/drm/i915/i915_cmd_parser.c
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_context.c
drivers/gpu/drm/i915/i915_gem_context.h
drivers/gpu/drm/i915/i915_gem_dmabuf.c
drivers/gpu/drm/i915/i915_gem_evict.c
drivers/gpu/drm/i915/i915_gem_execbuffer.c
drivers/gpu/drm/i915/i915_gem_fence_reg.c
drivers/gpu/drm/i915/i915_gem_gtt.c
drivers/gpu/drm/i915/i915_gem_gtt.h
drivers/gpu/drm/i915/i915_gem_internal.c
drivers/gpu/drm/i915/i915_gem_object.h
drivers/gpu/drm/i915/i915_gem_shrinker.c
drivers/gpu/drm/i915/i915_gem_stolen.c
drivers/gpu/drm/i915/i915_gem_tiling.c
drivers/gpu/drm/i915/i915_gem_userptr.c
drivers/gpu/drm/i915/i915_gpu_error.c
drivers/gpu/drm/i915/i915_gpu_error.h
drivers/gpu/drm/i915/i915_ioc32.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_params.c
drivers/gpu/drm/i915/i915_params.h
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/i915_perf.c
drivers/gpu/drm/i915/i915_pmu.c
drivers/gpu/drm/i915/i915_query.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/i915_request.c
drivers/gpu/drm/i915/i915_request.h
drivers/gpu/drm/i915/i915_reset.c [new file with mode: 0644]
drivers/gpu/drm/i915/i915_reset.h [new file with mode: 0644]
drivers/gpu/drm/i915/i915_suspend.c
drivers/gpu/drm/i915/i915_sw_fence.c
drivers/gpu/drm/i915/i915_sysfs.c
drivers/gpu/drm/i915/i915_timeline.h
drivers/gpu/drm/i915/i915_trace.h
drivers/gpu/drm/i915/icl_dsi.c
drivers/gpu/drm/i915/intel_acpi.c
drivers/gpu/drm/i915/intel_atomic.c
drivers/gpu/drm/i915/intel_atomic_plane.c
drivers/gpu/drm/i915/intel_audio.c
drivers/gpu/drm/i915/intel_bios.c
drivers/gpu/drm/i915/intel_breadcrumbs.c
drivers/gpu/drm/i915/intel_cdclk.c
drivers/gpu/drm/i915/intel_color.c
drivers/gpu/drm/i915/intel_connector.c
drivers/gpu/drm/i915/intel_crt.c
drivers/gpu/drm/i915/intel_csr.c
drivers/gpu/drm/i915/intel_ddi.c
drivers/gpu/drm/i915/intel_device_info.c
drivers/gpu/drm/i915/intel_device_info.h
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_display.h
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_dp_link_training.c
drivers/gpu/drm/i915/intel_dp_mst.c
drivers/gpu/drm/i915/intel_dpio_phy.c
drivers/gpu/drm/i915/intel_dpll_mgr.c
drivers/gpu/drm/i915/intel_dpll_mgr.h
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_dsi.h
drivers/gpu/drm/i915/intel_dsi_vbt.c
drivers/gpu/drm/i915/intel_dvo.c
drivers/gpu/drm/i915/intel_engine_cs.c
drivers/gpu/drm/i915/intel_fbc.c
drivers/gpu/drm/i915/intel_fbdev.c
drivers/gpu/drm/i915/intel_fifo_underrun.c
drivers/gpu/drm/i915/intel_frontbuffer.c
drivers/gpu/drm/i915/intel_guc.h
drivers/gpu/drm/i915/intel_guc_fw.c
drivers/gpu/drm/i915/intel_guc_log.c
drivers/gpu/drm/i915/intel_guc_submission.c
drivers/gpu/drm/i915/intel_gvt.c
drivers/gpu/drm/i915/intel_hangcheck.c
drivers/gpu/drm/i915/intel_hdcp.c
drivers/gpu/drm/i915/intel_hdmi.c
drivers/gpu/drm/i915/intel_hotplug.c
drivers/gpu/drm/i915/intel_huc.c
drivers/gpu/drm/i915/intel_huc_fw.c
drivers/gpu/drm/i915/intel_i2c.c
drivers/gpu/drm/i915/intel_lrc.c
drivers/gpu/drm/i915/intel_lrc.h
drivers/gpu/drm/i915/intel_lspcon.c
drivers/gpu/drm/i915/intel_lvds.c
drivers/gpu/drm/i915/intel_mocs.c
drivers/gpu/drm/i915/intel_mocs.h
drivers/gpu/drm/i915/intel_opregion.c
drivers/gpu/drm/i915/intel_overlay.c
drivers/gpu/drm/i915/intel_panel.c
drivers/gpu/drm/i915/intel_pipe_crc.c
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_psr.c
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_ringbuffer.h
drivers/gpu/drm/i915/intel_runtime_pm.c
drivers/gpu/drm/i915/intel_sdvo.c
drivers/gpu/drm/i915/intel_sprite.c
drivers/gpu/drm/i915/intel_tv.c
drivers/gpu/drm/i915/intel_uc.c
drivers/gpu/drm/i915/intel_uc.h
drivers/gpu/drm/i915/intel_uc_fw.c
drivers/gpu/drm/i915/intel_uncore.c
drivers/gpu/drm/i915/intel_vdsc.c
drivers/gpu/drm/i915/intel_wopcm.c
drivers/gpu/drm/i915/intel_workarounds.c
drivers/gpu/drm/i915/selftests/huge_pages.c
drivers/gpu/drm/i915/selftests/i915_gem.c
drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
drivers/gpu/drm/i915/selftests/i915_gem_context.c
drivers/gpu/drm/i915/selftests/i915_gem_evict.c
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
drivers/gpu/drm/i915/selftests/i915_gem_object.c
drivers/gpu/drm/i915/selftests/i915_request.c
drivers/gpu/drm/i915/selftests/i915_vma.c
drivers/gpu/drm/i915/selftests/igt_live_test.c [new file with mode: 0644]
drivers/gpu/drm/i915/selftests/igt_live_test.h [new file with mode: 0644]
drivers/gpu/drm/i915/selftests/igt_spinner.c
drivers/gpu/drm/i915/selftests/intel_guc.c
drivers/gpu/drm/i915/selftests/intel_hangcheck.c
drivers/gpu/drm/i915/selftests/intel_lrc.c
drivers/gpu/drm/i915/selftests/intel_workarounds.c
drivers/gpu/drm/i915/selftests/mock_context.c
drivers/gpu/drm/i915/selftests/mock_engine.c
drivers/gpu/drm/i915/selftests/mock_gem_device.c
drivers/gpu/drm/i915/selftests/mock_gtt.c
drivers/gpu/drm/i915/selftests/mock_gtt.h
drivers/gpu/drm/i915/vlv_dsi.c
drivers/gpu/drm/i915/vlv_dsi_pll.c
drivers/gpu/drm/mediatek/mtk_hdmi.c
drivers/gpu/drm/meson/meson_drv.c
drivers/gpu/drm/meson/meson_dw_hdmi.c
drivers/gpu/drm/mgag200/mgag200_fb.c
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c
drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c
drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
drivers/gpu/drm/msm/dsi/dsi.h
drivers/gpu/drm/msm/dsi/dsi_host.c
drivers/gpu/drm/msm/dsi/dsi_manager.c
drivers/gpu/drm/msm/edp/edp_bridge.c
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
drivers/gpu/drm/msm/msm_gem.c
drivers/gpu/drm/mxsfb/mxsfb_drv.c
drivers/gpu/drm/mxsfb/mxsfb_drv.h
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
drivers/gpu/drm/nouveau/dispnv50/disp.c
drivers/gpu/drm/nouveau/nouveau_display.c
drivers/gpu/drm/omapdrm/omap_connector.c
drivers/gpu/drm/omapdrm/omap_crtc.c
drivers/gpu/drm/omapdrm/omap_encoder.c
drivers/gpu/drm/omapdrm/omap_fbdev.c
drivers/gpu/drm/panel/Kconfig
drivers/gpu/drm/panel/Makefile
drivers/gpu/drm/panel/panel-innolux-p079zca.c
drivers/gpu/drm/panel/panel-tpo-tpg110.c [new file with mode: 0644]
drivers/gpu/drm/qxl/qxl_cmd.c
drivers/gpu/drm/qxl/qxl_display.c
drivers/gpu/drm/r128/r128_cce.c
drivers/gpu/drm/radeon/atom.c
drivers/gpu/drm/radeon/ci_dpm.c
drivers/gpu/drm/radeon/radeon_audio.c
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_dp_mst.c
drivers/gpu/drm/radeon/radeon_legacy_encoders.c
drivers/gpu/drm/radeon/si_dpm.c
drivers/gpu/drm/rcar-du/rcar_du_crtc.c
drivers/gpu/drm/rcar-du/rcar_du_crtc.h
drivers/gpu/drm/rcar-du/rcar_du_drv.c
drivers/gpu/drm/rcar-du/rcar_du_drv.h
drivers/gpu/drm/rcar-du/rcar_du_encoder.c
drivers/gpu/drm/rcar-du/rcar_du_encoder.h
drivers/gpu/drm/rcar-du/rcar_du_group.c
drivers/gpu/drm/rcar-du/rcar_du_kms.c
drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7790.dts
drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7791.dts
drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7793.dts
drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7795.dts
drivers/gpu/drm/rcar-du/rcar_du_of_lvds_r8a7796.dts
drivers/gpu/drm/rcar-du/rcar_du_plane.c
drivers/gpu/drm/rcar-du/rcar_du_plane.h
drivers/gpu/drm/rcar-du/rcar_du_vsp.c
drivers/gpu/drm/rcar-du/rcar_du_vsp.h
drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c
drivers/gpu/drm/rcar-du/rcar_lvds.c
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
drivers/gpu/drm/rockchip/inno_hdmi.c
drivers/gpu/drm/rockchip/rockchip_drm_fb.c
drivers/gpu/drm/rockchip/rockchip_drm_psr.c
drivers/gpu/drm/rockchip/rockchip_drm_psr.h
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
drivers/gpu/drm/scheduler/sched_main.c
drivers/gpu/drm/shmobile/shmob_drm_drv.c
drivers/gpu/drm/sti/sti_crtc.c
drivers/gpu/drm/sti/sti_dvo.c
drivers/gpu/drm/sti/sti_hda.c
drivers/gpu/drm/sti/sti_hdmi.c
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
drivers/gpu/drm/stm/ltdc.c
drivers/gpu/drm/sun4i/sun4i_backend.c
drivers/gpu/drm/sun4i/sun4i_drv.c
drivers/gpu/drm/sun4i/sun4i_frontend.c
drivers/gpu/drm/sun4i/sun4i_frontend.h
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
drivers/gpu/drm/sun4i/sun4i_layer.c
drivers/gpu/drm/tegra/hdmi.c
drivers/gpu/drm/tegra/hub.c
drivers/gpu/drm/tegra/sor.c
drivers/gpu/drm/tilcdc/tilcdc_drv.c
drivers/gpu/drm/tinydrm/core/tinydrm-core.c
drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c
drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c
drivers/gpu/drm/tinydrm/hx8357d.c
drivers/gpu/drm/tinydrm/ili9225.c
drivers/gpu/drm/tinydrm/ili9341.c
drivers/gpu/drm/tinydrm/mi0283qt.c
drivers/gpu/drm/tinydrm/mipi-dbi.c
drivers/gpu/drm/tinydrm/repaper.c
drivers/gpu/drm/tinydrm/st7586.c
drivers/gpu/drm/tinydrm/st7735r.c
drivers/gpu/drm/ttm/ttm_bo.c
drivers/gpu/drm/ttm/ttm_bo_vm.c
drivers/gpu/drm/v3d/v3d_drv.h
drivers/gpu/drm/v3d/v3d_gem.c
drivers/gpu/drm/v3d/v3d_sched.c
drivers/gpu/drm/vc4/vc4_crtc.c
drivers/gpu/drm/vc4/vc4_drv.h
drivers/gpu/drm/vc4/vc4_hdmi.c
drivers/gpu/drm/vc4/vc4_kms.c
drivers/gpu/drm/vc4/vc4_plane.c
drivers/gpu/drm/vgem/vgem_fence.c
drivers/gpu/drm/virtio/Makefile
drivers/gpu/drm/virtio/virtgpu_display.c
drivers/gpu/drm/virtio/virtgpu_drm_bus.c [deleted file]
drivers/gpu/drm/virtio/virtgpu_drv.c
drivers/gpu/drm/virtio/virtgpu_drv.h
drivers/gpu/drm/virtio/virtgpu_fb.c
drivers/gpu/drm/virtio/virtgpu_fence.c
drivers/gpu/drm/virtio/virtgpu_ioctl.c
drivers/gpu/drm/virtio/virtgpu_kms.c
drivers/gpu/drm/virtio/virtgpu_plane.c
drivers/gpu/drm/virtio/virtgpu_vq.c
drivers/gpu/drm/vkms/vkms_drv.c
drivers/gpu/drm/xen/xen_drm_front_conn.c
drivers/gpu/drm/zte/zx_hdmi.c
drivers/staging/vboxvideo/vbox_fb.c
include/drm/bridge/dw_hdmi.h
include/drm/bridge/dw_mipi_dsi.h
include/drm/drmP.h
include/drm/drm_atomic.h
include/drm/drm_bridge.h
include/drm/drm_color_mgmt.h
include/drm/drm_connector.h
include/drm/drm_crtc.h
include/drm/drm_crtc_helper.h
include/drm/drm_damage_helper.h
include/drm/drm_device.h
include/drm/drm_dp_helper.h
include/drm/drm_dp_mst_helper.h
include/drm/drm_edid.h
include/drm/drm_encoder_slave.h
include/drm/drm_fb_cma_helper.h
include/drm/drm_file.h
include/drm/drm_fourcc.h
include/drm/drm_framebuffer.h
include/drm/drm_gem_cma_helper.h
include/drm/drm_gem_framebuffer_helper.h
include/drm/drm_hdcp.h
include/drm/drm_legacy.h
include/drm/drm_mode_config.h
include/drm/drm_modes.h
include/drm/drm_syncobj.h
include/drm/drm_util.h
include/drm/drm_vblank.h
include/drm/gpu_scheduler.h
include/drm/i915_pciids.h
include/drm/intel-gtt.h
include/drm/tinydrm/mipi-dbi.h
include/drm/tinydrm/tinydrm-helpers.h
include/drm/tinydrm/tinydrm.h
include/drm/ttm/ttm_bo_driver.h
include/linux/dma-fence-array.h
include/linux/dma-fence.h
include/linux/mfd/intel_soc_pmic.h
include/uapi/drm/drm_fourcc.h
include/uapi/drm/v3d_drm.h

index 50220190c20330a47a1425e2e2798e59c8f1652b..60091db5dfa5218958ff35133df0e3c02b4fdc5c 100644 (file)
@@ -22,13 +22,11 @@ among others.
 
 Required properties:
 
-- compatible: Must be one or more of the following
-  - "ti,ds90c185" for the TI DS90C185 FPD-Link Serializer
-  - "lvds-encoder" for a generic LVDS encoder device
+- compatible: Must be "lvds-encoder"
 
-  When compatible with the generic version, nodes must list the
-  device-specific version corresponding to the device first
-  followed by the generic version.
+  Any encoder compatible with this generic binding, but with additional
+  properties not listed here, must list a device specific compatible first
+  followed by this generic compatible.
 
 Required nodes:
 
@@ -44,8 +42,6 @@ Example
 
 lvds-encoder {
        compatible = "lvds-encoder";
-       #address-cells = <1>;
-       #size-cells = <0>;
 
        ports {
                #address-cells = <1>;
index ba5469dd09f35393e339af8000d6ca776d1c2f31..27a054e1bb5fb82ccd4bbc2d3120ac56a9b98e49 100644 (file)
@@ -8,6 +8,7 @@ Required properties:
 
 - compatible : Shall contain one of
   - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
+  - "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
   - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
   - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
   - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
@@ -25,7 +26,7 @@ Required properties:
 - clock-names: Name of the clocks. This property is model-dependent.
   - The functional clock, which mandatory for all models, shall be listed
     first, and shall be named "fck".
-  - On R8A77990 and R8A77995, the LVDS encoder can use the EXTAL or
+  - On R8A77990, R8A77995 and R8A774C0, the LVDS encoder can use the EXTAL or
     DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be
     named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN
     numerical index.
index 527e236e9a2a126dcdd814e3b50c972a7145fe44..fee3c88e1a176e6388a49806ed65dca4471e7d42 100644 (file)
@@ -10,7 +10,7 @@ Required properties:
 
 Optional properties:
 
-- pwdn-gpios: Power down control GPIO
+- powerdown-gpios: Power down control GPIO (the /PWDN pin, active low).
 
 Required nodes:
 
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt b/Documentation/devicetree/bindings/display/bridge/ti,ds90c185.txt
new file mode 100644 (file)
index 0000000..e575f99
--- /dev/null
@@ -0,0 +1,55 @@
+Texas Instruments FPD-Link (LVDS) Serializer
+--------------------------------------------
+
+The DS90C185 and DS90C187 are low-power serializers for portable
+battery-powered applications that reduces the size of the RGB
+interface between the host GPU and the display.
+
+Required properties:
+
+- compatible: Should be
+  "ti,ds90c185", "lvds-encoder"  for the TI DS90C185 FPD-Link Serializer
+  "ti,ds90c187", "lvds-encoder"  for the TI DS90C187 FPD-Link Serializer
+
+Optional properties:
+
+- powerdown-gpios: Power down control GPIO (the PDB pin, active-low)
+
+Required nodes:
+
+The devices have two video ports. Their connections are modeled using the OF
+graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 for parallel input
+- Video port 1 for LVDS output
+
+
+Example
+-------
+
+lvds-encoder {
+       compatible = "ti,ds90c185", "lvds-encoder";
+
+       powerdown-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+
+                       lvds_enc_in: endpoint {
+                               remote-endpoint = <&lcdc_out_rgb>;
+                       };
+               };
+
+               port@1 {
+                       reg = <1>;
+
+                       lvds_enc_out: endpoint {
+                               remote-endpoint = <&lvds_panel_in>;
+                       };
+               };
+       };
+};
index 3c855d9f27193bcb03f365cc8c4a3a78a5d478a0..aedb22b4d1613d1ff69b833a5babd227892538e0 100644 (file)
@@ -7,6 +7,7 @@ Required Properties:
     - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
     - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
     - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
+    - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
     - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
     - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
     - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
@@ -57,6 +58,7 @@ corresponding to each DU output.
  R8A7744 (RZ/G1N)       DPAD 0         LVDS 0         -              -
  R8A7745 (RZ/G1E)       DPAD 0         DPAD 1         -              -
  R8A77470 (RZ/G1C)      DPAD 0         DPAD 1         LVDS 0         -
+ R8A774C0 (RZ/G2E)      DPAD 0         LVDS 0         LVDS 1         -
  R8A7779 (R-Car H1)     DPAD 0         DPAD 1         -              -
  R8A7790 (R-Car H2)     DPAD 0         LVDS 0         LVDS 1         -
  R8A7791 (R-Car M2-W)   DPAD 0         LVDS 0         -              -
index b79e5769f0ae7d1b28835d73f9886d83d42fb389..4f58c5a2d19501c92b4388dbb9acaacac8001759 100644 (file)
@@ -10,6 +10,7 @@ Required properties:
                "rockchip,rk3126-vop";
                "rockchip,px30-vop-lit";
                "rockchip,px30-vop-big";
+               "rockchip,rk3066-vop";
                "rockchip,rk3188-vop";
                "rockchip,rk3288-vop";
                "rockchip,rk3368-vop";
diff --git a/Documentation/gpu/dp-mst/topology-figure-1.dot b/Documentation/gpu/dp-mst/topology-figure-1.dot
new file mode 100644 (file)
index 0000000..157e17c
--- /dev/null
@@ -0,0 +1,52 @@
+digraph T {
+    /* Make sure our payloads are always drawn below the driver node */
+    subgraph cluster_driver {
+        fillcolor = grey;
+        style = filled;
+        driver -> {payload1, payload2} [dir=none];
+    }
+
+    /* Driver malloc references */
+    edge [style=dashed];
+    driver -> port1;
+    driver -> port2;
+    driver -> port3:e;
+    driver -> port4;
+
+    payload1:s -> port1:e;
+    payload2:s -> port3:e;
+    edge [style=""];
+
+    subgraph cluster_topology {
+        label="Topology Manager";
+        labelloc=bottom;
+
+        /* Topology references */
+        mstb1 -> {port1, port2};
+        port1 -> mstb2;
+        port2 -> mstb3 -> {port3, port4};
+        port3 -> mstb4;
+
+        /* Malloc references */
+        edge [style=dashed;dir=back];
+        mstb1 -> {port1, port2};
+        port1 -> mstb2;
+        port2 -> mstb3 -> {port3, port4};
+        port3 -> mstb4;
+    }
+
+    driver [label="DRM driver";style=filled;shape=box;fillcolor=lightblue];
+
+    payload1 [label="Payload #1";style=filled;shape=box;fillcolor=lightblue];
+    payload2 [label="Payload #2";style=filled;shape=box;fillcolor=lightblue];
+
+    mstb1 [label="MSTB #1";style=filled;fillcolor=palegreen;shape=oval];
+    mstb2 [label="MSTB #2";style=filled;fillcolor=palegreen;shape=oval];
+    mstb3 [label="MSTB #3";style=filled;fillcolor=palegreen;shape=oval];
+    mstb4 [label="MSTB #4";style=filled;fillcolor=palegreen;shape=oval];
+
+    port1 [label="Port #1";shape=oval];
+    port2 [label="Port #2";shape=oval];
+    port3 [label="Port #3";shape=oval];
+    port4 [label="Port #4";shape=oval];
+}
diff --git a/Documentation/gpu/dp-mst/topology-figure-2.dot b/Documentation/gpu/dp-mst/topology-figure-2.dot
new file mode 100644 (file)
index 0000000..4243dd1
--- /dev/null
@@ -0,0 +1,56 @@
+digraph T {
+    /* Make sure our payloads are always drawn below the driver node */
+    subgraph cluster_driver {
+        fillcolor = grey;
+        style = filled;
+        driver -> {payload1, payload2} [dir=none];
+    }
+
+    /* Driver malloc references */
+    edge [style=dashed];
+    driver -> port1;
+    driver -> port2;
+    driver -> port3:e;
+    driver -> port4 [color=red];
+
+    payload1:s -> port1:e;
+    payload2:s -> port3:e;
+    edge [style=""];
+
+    subgraph cluster_topology {
+        label="Topology Manager";
+        labelloc=bottom;
+
+        /* Topology references */
+        mstb1 -> {port1, port2};
+        port1 -> mstb2;
+        edge [color=red];
+        port2 -> mstb3 -> {port3, port4};
+        port3 -> mstb4;
+        edge [color=""];
+
+        /* Malloc references */
+        edge [style=dashed;dir=back];
+        mstb1 -> {port1, port2};
+        port1 -> mstb2;
+        port2 -> mstb3 -> port3;
+        edge [color=red];
+        mstb3 -> port4;
+        port3 -> mstb4;
+    }
+
+    mstb1 [label="MSTB #1";style=filled;fillcolor=palegreen];
+    mstb2 [label="MSTB #2";style=filled;fillcolor=palegreen];
+    mstb3 [label="MSTB #3";style=filled;fillcolor=palegreen];
+    mstb4 [label="MSTB #4";style=filled;fillcolor=grey];
+
+    port1 [label="Port #1"];
+    port2 [label="Port #2"];
+    port3 [label="Port #3"];
+    port4 [label="Port #4";style=filled;fillcolor=grey];
+
+    driver [label="DRM driver";style=filled;shape=box;fillcolor=lightblue];
+
+    payload1 [label="Payload #1";style=filled;shape=box;fillcolor=lightblue];
+    payload2 [label="Payload #2";style=filled;shape=box;fillcolor=lightblue];
+}
diff --git a/Documentation/gpu/dp-mst/topology-figure-3.dot b/Documentation/gpu/dp-mst/topology-figure-3.dot
new file mode 100644 (file)
index 0000000..6cd78d0
--- /dev/null
@@ -0,0 +1,59 @@
+digraph T {
+    /* Make sure our payloads are always drawn below the driver node */
+    subgraph cluster_driver {
+        fillcolor = grey;
+        style = filled;
+        edge [dir=none];
+        driver -> payload1;
+        driver -> payload2 [penwidth=3];
+        edge [dir=""];
+    }
+
+    /* Driver malloc references */
+    edge [style=dashed];
+    driver -> port1;
+    driver -> port2;
+    driver -> port3:e;
+    driver -> port4 [color=grey];
+    payload1:s -> port1:e;
+    payload2:s -> port3:e [penwidth=3];
+    edge [style=""];
+
+    subgraph cluster_topology {
+        label="Topology Manager";
+        labelloc=bottom;
+
+        /* Topology references */
+        mstb1 -> {port1, port2};
+        port1 -> mstb2;
+        edge [color=grey];
+        port2 -> mstb3 -> {port3, port4};
+        port3 -> mstb4;
+        edge [color=""];
+
+        /* Malloc references */
+        edge [style=dashed;dir=back];
+        mstb1 -> {port1, port2};
+        port1 -> mstb2;
+        port2 -> mstb3 [penwidth=3];
+        mstb3 -> port3 [penwidth=3];
+        edge [color=grey];
+        mstb3 -> port4;
+        port3 -> mstb4;
+    }
+
+    mstb1 [label="MSTB #1";style=filled;fillcolor=palegreen];
+    mstb2 [label="MSTB #2";style=filled;fillcolor=palegreen];
+    mstb3 [label="MSTB #3";style=filled;fillcolor=palegreen;penwidth=3];
+    mstb4 [label="MSTB #4";style=filled;fillcolor=grey];
+
+    port1 [label="Port #1"];
+    port2 [label="Port #2";penwidth=5];
+    port3 [label="Port #3";penwidth=3];
+    port4 [label="Port #4";style=filled;fillcolor=grey];
+
+    driver [label="DRM driver";style=filled;shape=box;fillcolor=lightblue];
+
+    payload1 [label="Payload #1";style=filled;shape=box;fillcolor=lightblue];
+    payload2 [label="Payload #2";style=filled;shape=box;fillcolor=lightblue;penwidth=3];
+}
index 5ee9674fb9e981db2c17c0b6f1a08402b5ab5290..2caf21effd281d28805a64a27f921235e489ba66 100644 (file)
@@ -143,6 +143,9 @@ Device Instance and Driver Handling
 .. kernel-doc:: drivers/gpu/drm/drm_drv.c
    :doc: driver instance overview
 
+.. kernel-doc:: include/drm/drm_device.h
+   :internal:
+
 .. kernel-doc:: include/drm/drm_drv.h
    :internal:
 
@@ -230,6 +233,15 @@ Printer
 .. kernel-doc:: drivers/gpu/drm/drm_print.c
    :export:
 
+Utilities
+---------
+
+.. kernel-doc:: include/drm/drm_util.h
+   :doc: drm utils
+
+.. kernel-doc:: include/drm/drm_util.h
+   :internal:
+
 
 Legacy Support Code
 ===================
index b422eb8edf1627baba10a231560eca754e31e846..fbd11b2fe5b5729eab7f3ee0ed112ced354d1f19 100644 (file)
@@ -116,8 +116,6 @@ Framebuffer CMA Helper Functions Reference
 .. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c
    :export:
 
-.. _drm_bridges:
-
 Framebuffer GEM Helper Reference
 ================================
 
@@ -127,6 +125,8 @@ Framebuffer GEM Helper Reference
 .. kernel-doc:: drivers/gpu/drm/drm_gem_framebuffer_helper.c
    :export:
 
+.. _drm_bridges:
+
 Bridges
 =======
 
@@ -208,18 +208,40 @@ Display Port Dual Mode Adaptor Helper Functions Reference
 .. kernel-doc:: drivers/gpu/drm/drm_dp_dual_mode_helper.c
    :export:
 
-Display Port MST Helper Functions Reference
-===========================================
+Display Port MST Helpers
+========================
+
+Overview
+--------
 
 .. kernel-doc:: drivers/gpu/drm/drm_dp_mst_topology.c
    :doc: dp mst helper
 
+.. kernel-doc:: drivers/gpu/drm/drm_dp_mst_topology.c
+   :doc: Branch device and port refcounting
+
+Functions Reference
+-------------------
+
 .. kernel-doc:: include/drm/drm_dp_mst_helper.h
    :internal:
 
 .. kernel-doc:: drivers/gpu/drm/drm_dp_mst_topology.c
    :export:
 
+Topology Lifetime Internals
+---------------------------
+
+These functions aren't exported to drivers, but are documented here to help make
+the MST topology helpers easier to understand
+
+.. kernel-doc:: drivers/gpu/drm/drm_dp_mst_topology.c
+   :functions: drm_dp_mst_topology_try_get_mstb drm_dp_mst_topology_get_mstb
+               drm_dp_mst_topology_put_mstb
+               drm_dp_mst_topology_try_get_port drm_dp_mst_topology_get_port
+               drm_dp_mst_topology_put_port
+               drm_dp_mst_get_mstb_malloc drm_dp_mst_put_mstb_malloc
+
 MIPI DSI Helper Functions Reference
 ===================================
 
index 14191b64446df0eadae3215f690e07ec4a09885b..38360ede12215e6fa0d012d5498436966b38c8c9 100644 (file)
@@ -82,30 +82,6 @@ events for atomic commits correctly. But fixing these bugs is good anyway.
 
 Contact: Daniel Vetter, respective driver maintainers
 
-Better manual-upload support for atomic
----------------------------------------
-
-This would be especially useful for tinydrm:
-
-- Add a struct drm_rect dirty_clip to drm_crtc_state. When duplicating the
-  crtc state, clear that to the max values, x/y = 0 and w/h = MAX_INT, in
-  __drm_atomic_helper_crtc_duplicate_state().
-
-- Move tinydrm_merge_clips into drm_framebuffer.c, dropping the tinydrm\_
-  prefix ofc and using drm_fb\_. drm_framebuffer.c makes sense since this
-  is a function useful to implement the fb->dirty function.
-
-- Create a new drm_fb_dirty function which does essentially what e.g.
-  mipi_dbi_fb_dirty does. You can use e.g. drm_atomic_helper_update_plane as the
-  template. But instead of doing a simple full-screen plane update, this new
-  helper also sets crtc_state->dirty_clip to the right coordinates. And of
-  course it needs to check whether the fb is actually active (and maybe where),
-  so there's some book-keeping involved. There's also some good fun involved in
-  scaling things appropriately. For that case we might simply give up and
-  declare the entire area covered by the plane as dirty.
-
-Contact: Noralf Trønnes, Daniel Vetter
-
 Fallout from atomic KMS
 -----------------------
 
@@ -209,6 +185,36 @@ Would be great to refactor this all into a set of small common helpers.
 
 Contact: Daniel Vetter
 
+Generic fbdev defio support
+---------------------------
+
+The defio support code in the fbdev core has some very specific requirements,
+which means drivers need to have a special framebuffer for fbdev. Which prevents
+us from using the generic fbdev emulation code everywhere. The main issue is
+that it uses some fields in struct page itself, which breaks shmem gem objects
+(and other things).
+
+Possible solution would be to write our own defio mmap code in the drm fbdev
+emulation. It would need to fully wrap the existing mmap ops, forwarding
+everything after it has done the write-protect/mkwrite trickery:
+
+- In the drm_fbdev_fb_mmap helper, if we need defio, change the
+  default page prots to write-protected with something like this::
+
+      vma->vm_page_prot = pgprot_wrprotect(vma->vm_page_prot);
+
+- Set the mkwrite and fsync callbacks with similar implementions to the core
+  fbdev defio stuff. These should all work on plain ptes, they don't actually
+  require a struct page.  uff. These should all work on plain ptes, they don't
+  actually require a struct page.
+
+- Track the dirty pages in a separate structure (bitfield with one bit per page
+  should work) to avoid clobbering struct page.
+
+Might be good to also have some igt testcases for this.
+
+Contact: Daniel Vetter, Noralf Tronnes
+
 Put a reservation_object into drm_gem_object
 --------------------------------------------
 
@@ -354,9 +360,6 @@ KMS cleanups
 
 Some of these date from the very introduction of KMS in 2008 ...
 
-- drm_mode_config.crtc_idr is misnamed, since it contains all KMS object. Should
-  be renamed to drm_mode_config.object_idr.
-
 - drm_display_mode doesn't need to be derived from drm_mode_object. That's
   leftovers from older (never merged into upstream) KMS designs where modes
   where set using their ID, including support to add/remove modes.
@@ -432,21 +435,10 @@ those drivers as simple as possible, so lots of room for refactoring:
   one of the ideas for having a shared dsi/dbi helper, abstracting away the
   transport details more.
 
-- tinydrm_gem_cma_prime_import_sg_table should probably go into the cma
-  helpers, as a _vmapped variant (since not every driver needs the vmap).
-  And tinydrm_gem_cma_free_object could the be merged into
-  drm_gem_cma_free_object().
-
-- tinydrm_fb_create we could move into drm_simple_pipe, only need to add
-  the fb_create hook to drm_simple_pipe_funcs, which would again simplify a
-  bunch of things (since it gives you a one-stop vfunc for simple drivers).
-
 - Quick aside: The unregister devm stuff is kinda getting the lifetimes of
   a drm_device wrong. Doesn't matter, since everyone else gets it wrong
   too :-)
 
-- also rework the drm_framebuffer_funcs->dirty hook wire-up, see above.
-
 Contact: Noralf Trønnes, Daniel Vetter
 
 AMD DC Display Driver
index e5e741714462e15099595697355a18cd4ce36c97..4b752571fe03b7e7aa94bf19281f304cfd4316b7 100644 (file)
@@ -4886,6 +4886,7 @@ DRM DRIVER FOR QXL VIRTUAL GPU
 M:     Dave Airlie <airlied@redhat.com>
 M:     Gerd Hoffmann <kraxel@redhat.com>
 L:     virtualization@lists.linux-foundation.org
+L:     spice-devel@lists.freedesktop.org
 T:     git git://anongit.freedesktop.org/drm/drm-misc
 S:     Maintained
 F:     drivers/gpu/drm/qxl/
@@ -4922,6 +4923,13 @@ DRM DRIVER FOR TDFX VIDEO CARDS
 S:     Orphan / Obsolete
 F:     drivers/gpu/drm/tdfx/
 
+DRM DRIVER FOR TPO TPG110 PANELS
+M:     Linus Walleij <linus.walleij@linaro.org>
+T:     git git://anongit.freedesktop.org/drm/drm-misc
+S:     Maintained
+F:     drivers/gpu/drm/panel/panel-tpo-tpg110.c
+F:     Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt
+
 DRM DRIVER FOR USB DISPLAYLINK VIDEO ADAPTERS
 M:     Dave Airlie <airlied@redhat.com>
 R:     Sean Paul <sean@poorly.run>
@@ -4930,6 +4938,16 @@ S:       Odd Fixes
 F:     drivers/gpu/drm/udl/
 T:     git git://anongit.freedesktop.org/drm/drm-misc
 
+DRM DRIVER FOR VIRTUAL KERNEL MODESETTING (VKMS)
+M:     Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
+R:     Haneen Mohammed <hamohammed.sa@gmail.com>
+R:     Daniel Vetter <daniel@ffwll.ch>
+T:     git git://anongit.freedesktop.org/drm/drm-misc
+S:     Maintained
+L:     dri-devel@lists.freedesktop.org
+F:     drivers/gpu/drm/vkms/
+F:     Documentation/gpu/vkms.rst
+
 DRM DRIVER FOR VMWARE VIRTUAL GPU
 M:     "VMware Graphics" <linux-graphics-maintainer@vmware.com>
 M:     Thomas Hellstrom <thellstrom@vmware.com>
@@ -4999,7 +5017,6 @@ F:        Documentation/devicetree/bindings/display/atmel/
 T:     git git://anongit.freedesktop.org/drm/drm-misc
 
 DRM DRIVERS FOR BRIDGE CHIPS
-M:     Archit Taneja <architt@codeaurora.org>
 M:     Andrzej Hajda <a.hajda@samsung.com>
 R:     Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
 S:     Maintained
index ca18e0d23df9775e0a9c342d5a22ac9257d6ee3a..c14cfaea92e25683e26970c24576a47ad3f8b927 100644 (file)
@@ -15,6 +15,7 @@
 
 #include <linux/export.h>
 #include <linux/acpi.h>
+#include <linux/mfd/intel_soc_pmic.h>
 #include <linux/regmap.h>
 #include <acpi/acpi_lpat.h>
 #include "intel_pmic.h"
@@ -36,6 +37,8 @@ struct intel_pmic_opregion {
        struct intel_pmic_regs_handler_ctx ctx;
 };
 
+static struct intel_pmic_opregion *intel_pmic_opregion;
+
 static int pmic_get_reg_bit(int address, struct pmic_table *table,
                            int count, int *reg, int *bit)
 {
@@ -304,6 +307,7 @@ int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
        }
 
        opregion->data = d;
+       intel_pmic_opregion = opregion;
        return 0;
 
 out_remove_thermal_handler:
@@ -319,3 +323,60 @@ out_error:
        return ret;
 }
 EXPORT_SYMBOL_GPL(intel_pmic_install_opregion_handler);
+
+/**
+ * intel_soc_pmic_exec_mipi_pmic_seq_element - Execute PMIC MIPI sequence
+ * @i2c_address:  I2C client address for the PMIC
+ * @reg_address:  PMIC register address
+ * @value:        New value for the register bits to change
+ * @mask:         Mask indicating which register bits to change
+ *
+ * DSI LCD panels describe an initialization sequence in the i915 VBT (Video
+ * BIOS Tables) using so called MIPI sequences. One possible element in these
+ * sequences is a PMIC specific element of 15 bytes.
+ *
+ * This function executes these PMIC specific elements sending the embedded
+ * commands to the PMIC.
+ *
+ * Return 0 on success, < 0 on failure.
+ */
+int intel_soc_pmic_exec_mipi_pmic_seq_element(u16 i2c_address, u32 reg_address,
+                                             u32 value, u32 mask)
+{
+       struct intel_pmic_opregion_data *d;
+       int ret;
+
+       if (!intel_pmic_opregion) {
+               pr_warn("%s: No PMIC registered\n", __func__);
+               return -ENXIO;
+       }
+
+       d = intel_pmic_opregion->data;
+
+       mutex_lock(&intel_pmic_opregion->lock);
+
+       if (d->exec_mipi_pmic_seq_element) {
+               ret = d->exec_mipi_pmic_seq_element(intel_pmic_opregion->regmap,
+                                                   i2c_address, reg_address,
+                                                   value, mask);
+       } else if (d->pmic_i2c_address) {
+               if (i2c_address == d->pmic_i2c_address) {
+                       ret = regmap_update_bits(intel_pmic_opregion->regmap,
+                                                reg_address, mask, value);
+               } else {
+                       pr_err("%s: Unexpected i2c-addr: 0x%02x (reg-addr 0x%x value 0x%x mask 0x%x)\n",
+                              __func__, i2c_address, reg_address, value, mask);
+                       ret = -ENXIO;
+               }
+       } else {
+               pr_warn("%s: Not implemented\n", __func__);
+               pr_warn("%s: i2c-addr: 0x%x reg-addr 0x%x value 0x%x mask 0x%x\n",
+                       __func__, i2c_address, reg_address, value, mask);
+               ret = -EOPNOTSUPP;
+       }
+
+       mutex_unlock(&intel_pmic_opregion->lock);
+
+       return ret;
+}
+EXPORT_SYMBOL_GPL(intel_soc_pmic_exec_mipi_pmic_seq_element);
index 095afc96952ee5acf03b19df763343f121e91ff7..89379476a1df61f255a03195f5663f3d07df5241 100644 (file)
@@ -15,10 +15,14 @@ struct intel_pmic_opregion_data {
        int (*update_aux)(struct regmap *r, int reg, int raw_temp);
        int (*get_policy)(struct regmap *r, int reg, int bit, u64 *value);
        int (*update_policy)(struct regmap *r, int reg, int bit, int enable);
+       int (*exec_mipi_pmic_seq_element)(struct regmap *r, u16 i2c_address,
+                                         u32 reg_address, u32 value, u32 mask);
        struct pmic_table *power_table;
        int power_table_count;
        struct pmic_table *thermal_table;
        int thermal_table_count;
+       /* For generic exec_mipi_pmic_seq_element handling */
+       int pmic_i2c_address;
 };
 
 int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle, struct regmap *regmap, struct intel_pmic_opregion_data *d);
index 078b0448f30a001f90dbc62deb63eafebb78a1ec..7ffd5624b8e15f9734aa3f301e4a3136a8633887 100644 (file)
@@ -231,6 +231,24 @@ static int intel_cht_wc_pmic_update_power(struct regmap *regmap, int reg,
        return regmap_update_bits(regmap, reg, bitmask, on ? 1 : 0);
 }
 
+static int intel_cht_wc_exec_mipi_pmic_seq_element(struct regmap *regmap,
+                                                  u16 i2c_client_address,
+                                                  u32 reg_address,
+                                                  u32 value, u32 mask)
+{
+       u32 address;
+
+       if (i2c_client_address > 0xff || reg_address > 0xff) {
+               pr_warn("%s warning addresses too big client 0x%x reg 0x%x\n",
+                       __func__, i2c_client_address, reg_address);
+               return -ERANGE;
+       }
+
+       address = (i2c_client_address << 8) | reg_address;
+
+       return regmap_update_bits(regmap, address, mask, value);
+}
+
 /*
  * The thermal table and ops are empty, we do not support the Thermal opregion
  * (DPTF) due to lacking documentation.
@@ -238,6 +256,7 @@ static int intel_cht_wc_pmic_update_power(struct regmap *regmap, int reg,
 static struct intel_pmic_opregion_data intel_cht_wc_pmic_opregion_data = {
        .get_power              = intel_cht_wc_pmic_get_power,
        .update_power           = intel_cht_wc_pmic_update_power,
+       .exec_mipi_pmic_seq_element = intel_cht_wc_exec_mipi_pmic_seq_element,
        .power_table            = power_table,
        .power_table_count      = ARRAY_SIZE(power_table),
 };
index 2579675b7082b76e593a095771f50e9c8e07bca9..1b49cbb1e21e85377e7474b7b2f00231e5ed2dce 100644 (file)
@@ -240,6 +240,7 @@ static struct intel_pmic_opregion_data intel_xpower_pmic_opregion_data = {
        .power_table_count = ARRAY_SIZE(power_table),
        .thermal_table = thermal_table,
        .thermal_table_count = ARRAY_SIZE(thermal_table),
+       .pmic_i2c_address = 0x34,
 };
 
 static acpi_status intel_xpower_pmic_gpio_handler(u32 function,
index 02f7f9a899797467968ee7894ccd94797a971366..7c858020d14b8e91a1af439193873f3bd5434f88 100644 (file)
@@ -1093,17 +1093,7 @@ static int dma_buf_debug_show(struct seq_file *s, void *unused)
        return 0;
 }
 
-static int dma_buf_debug_open(struct inode *inode, struct file *file)
-{
-       return single_open(file, dma_buf_debug_show, NULL);
-}
-
-static const struct file_operations dma_buf_debug_fops = {
-       .open           = dma_buf_debug_open,
-       .read           = seq_read,
-       .llseek         = seq_lseek,
-       .release        = single_release,
-};
+DEFINE_SHOW_ATTRIBUTE(dma_buf_debug);
 
 static struct dentry *dma_buf_debugfs_dir;
 
index 136ec04d683f1c5b80598301f8fab897cd99b5e4..3aa8733f832af9596f664b0f525de3620babf8fc 100644 (file)
@@ -649,7 +649,7 @@ EXPORT_SYMBOL(dma_fence_wait_any_timeout);
  */
 void
 dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops,
-              spinlock_t *lock, u64 context, unsigned seqno)
+              spinlock_t *lock, u64 context, u64 seqno)
 {
        BUG_ON(!lock);
        BUG_ON(!ops || !ops->get_driver_name || !ops->get_timeline_name);
index 53c1d6d36a642f04ec49aa0e3cfeabeb84205609..32dcf7b4c9356833ceb23e33af61a7725493e664 100644 (file)
@@ -172,7 +172,7 @@ static bool timeline_fence_enable_signaling(struct dma_fence *fence)
 static void timeline_fence_value_str(struct dma_fence *fence,
                                    char *str, int size)
 {
-       snprintf(str, size, "%d", fence->seqno);
+       snprintf(str, size, "%lld", fence->seqno);
 }
 
 static void timeline_fence_timeline_value_str(struct dma_fence *fence,
index c4c8ecb24aa9b4e9eb233847dd9a7bbfa1cb7fe4..c0abf37df88bbe25d2331249e902fa47a5c0c7a3 100644 (file)
@@ -147,7 +147,7 @@ static void sync_print_sync_file(struct seq_file *s,
        }
 }
 
-static int sync_debugfs_show(struct seq_file *s, void *unused)
+static int sync_info_debugfs_show(struct seq_file *s, void *unused)
 {
        struct list_head *pos;
 
@@ -178,17 +178,7 @@ static int sync_debugfs_show(struct seq_file *s, void *unused)
        return 0;
 }
 
-static int sync_info_debugfs_open(struct inode *inode, struct file *file)
-{
-       return single_open(file, sync_debugfs_show, inode->i_private);
-}
-
-static const struct file_operations sync_info_debugfs_fops = {
-       .open           = sync_info_debugfs_open,
-       .read           = seq_read,
-       .llseek         = seq_lseek,
-       .release        = single_release,
-};
+DEFINE_SHOW_ATTRIBUTE(sync_info_debugfs);
 
 static __init int sync_debugfs_init(void)
 {
@@ -218,7 +208,7 @@ void sync_dump(void)
        };
        int i;
 
-       sync_debugfs_show(&s, NULL);
+       sync_info_debugfs_show(&s, NULL);
 
        for (i = 0; i < s.count; i += DUMP_CHUNK) {
                if ((s.count - i) > DUMP_CHUNK) {
index 35dd06479867fad9636db14fc58747ee60dbf198..4f6305ca52c8e96c006b29516486a4e0ba7d12f4 100644 (file)
@@ -144,7 +144,7 @@ char *sync_file_get_name(struct sync_file *sync_file, char *buf, int len)
        } else {
                struct dma_fence *fence = sync_file->fence;
 
-               snprintf(buf, len, "%s-%s%llu-%d",
+               snprintf(buf, len, "%s-%s%llu-%lld",
                         fence->ops->get_driver_name(fence),
                         fence->ops->get_timeline_name(fence),
                         fence->context,
@@ -258,7 +258,7 @@ static struct sync_file *sync_file_merge(const char *name, struct sync_file *a,
 
                        i_b++;
                } else {
-                       if (pt_a->seqno - pt_b->seqno <= INT_MAX)
+                       if (__dma_fence_is_later(pt_a->seqno, pt_b->seqno))
                                add_fence(fences, &i, pt_a);
                        else
                                add_fence(fences, &i, pt_b);
index 4385f00e1d055583df06ae4b7be0e6a6a68adc51..bd943a71756ca81bb8fe38836ef07980a26dd324 100644 (file)
@@ -170,10 +170,6 @@ config DRM_KMS_CMA_HELPER
        bool
        depends on DRM
        select DRM_GEM_CMA_HELPER
-       select DRM_KMS_FB_HELPER
-       select FB_SYS_FILLRECT
-       select FB_SYS_COPYAREA
-       select FB_SYS_IMAGEBLIT
        help
          Choose this if you need the KMS CMA helper functions
 
index f76bcb9c45e488a07d1f17dc7125d831563c76fc..466da5954a682de002582e2759ef07a33a775ecd 100644 (file)
@@ -57,7 +57,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
 
 # add asic specific block
 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
-       ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o
+       dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o
 
 amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
 
index bcef6ea4bcf9f83d49f6c3739406b52eb8a196b0..9efa681d08781162b3e51c52564adc176f30081d 100644 (file)
@@ -542,6 +542,11 @@ struct amdgpu_asic_funcs {
        bool (*need_full_reset)(struct amdgpu_device *adev);
        /* initialize doorbell layout for specific asic*/
        void (*init_doorbell_index)(struct amdgpu_device *adev);
+       /* PCIe bandwidth usage */
+       void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
+                              uint64_t *count1);
+       /* do we need to reset the asic at init time (e.g., kexec) */
+       bool (*need_reset_on_init)(struct amdgpu_device *adev);
 };
 
 /*
@@ -634,7 +639,7 @@ struct amdgpu_nbio_funcs {
        void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
        u32 (*get_memsize)(struct amdgpu_device *adev);
        void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
-                                   bool use_doorbell, int doorbell_index);
+                       bool use_doorbell, int doorbell_index, int doorbell_size);
        void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
                                         bool enable);
        void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
@@ -1042,6 +1047,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
+#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
+#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
 
 /* Common functions */
 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
index 2dfaf158ef073340e778c9f51a9e6bc905f3f48d..e957e42c539a8e7d73d6e26c3a35f145d8da4e7f 100644 (file)
@@ -28,8 +28,6 @@
 #include <linux/module.h>
 #include <linux/dma-buf.h>
 
-const struct kgd2kfd_calls *kgd2kfd;
-
 static const unsigned int compute_vmid_bitmap = 0xFF00;
 
 /* Total memory size in system memory and all GPU VRAM. Used to
@@ -47,12 +45,9 @@ int amdgpu_amdkfd_init(void)
        amdgpu_amdkfd_total_mem_size *= si.mem_unit;
 
 #ifdef CONFIG_HSA_AMD
-       ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
-       if (ret)
-               kgd2kfd = NULL;
+       ret = kgd2kfd_init();
        amdgpu_amdkfd_gpuvm_init_mem_limits();
 #else
-       kgd2kfd = NULL;
        ret = -ENOENT;
 #endif
 
@@ -61,17 +56,13 @@ int amdgpu_amdkfd_init(void)
 
 void amdgpu_amdkfd_fini(void)
 {
-       if (kgd2kfd)
-               kgd2kfd->exit();
+       kgd2kfd_exit();
 }
 
 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
 {
        const struct kfd2kgd_calls *kfd2kgd;
 
-       if (!kgd2kfd)
-               return;
-
        switch (adev->asic_type) {
 #ifdef CONFIG_DRM_AMDGPU_CIK
        case CHIP_KAVERI:
@@ -98,8 +89,8 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
                return;
        }
 
-       adev->kfd.dev = kgd2kfd->probe((struct kgd_dev *)adev,
-                                      adev->pdev, kfd2kgd);
+       adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
+                                     adev->pdev, kfd2kgd);
 
        if (adev->kfd.dev)
                amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
@@ -182,7 +173,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                                &gpu_resources.doorbell_start_offset);
 
                if (adev->asic_type < CHIP_VEGA10) {
-                       kgd2kfd->device_init(adev->kfd.dev, &gpu_resources);
+                       kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
                        return;
                }
 
@@ -197,13 +188,13 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                         * can use each doorbell assignment twice.
                         */
                        gpu_resources.sdma_doorbell[0][i] =
-                               adev->doorbell_index.sdma_engine0 + (i >> 1);
+                               adev->doorbell_index.sdma_engine[0] + (i >> 1);
                        gpu_resources.sdma_doorbell[0][i+1] =
-                               adev->doorbell_index.sdma_engine0 + 0x200 + (i >> 1);
+                               adev->doorbell_index.sdma_engine[0] + 0x200 + (i >> 1);
                        gpu_resources.sdma_doorbell[1][i] =
-                               adev->doorbell_index.sdma_engine1 + (i >> 1);
+                               adev->doorbell_index.sdma_engine[1] + (i >> 1);
                        gpu_resources.sdma_doorbell[1][i+1] =
-                               adev->doorbell_index.sdma_engine1 + 0x200 + (i >> 1);
+                               adev->doorbell_index.sdma_engine[1] + 0x200 + (i >> 1);
                }
                /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
                 * SDMA, IH and VCN. So don't use them for the CP.
@@ -211,14 +202,14 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                gpu_resources.reserved_doorbell_mask = 0x1e0;
                gpu_resources.reserved_doorbell_val  = 0x0e0;
 
-               kgd2kfd->device_init(adev->kfd.dev, &gpu_resources);
+               kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
        }
 }
 
 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
 {
        if (adev->kfd.dev) {
-               kgd2kfd->device_exit(adev->kfd.dev);
+               kgd2kfd_device_exit(adev->kfd.dev);
                adev->kfd.dev = NULL;
        }
 }
@@ -227,13 +218,13 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
                const void *ih_ring_entry)
 {
        if (adev->kfd.dev)
-               kgd2kfd->interrupt(adev->kfd.dev, ih_ring_entry);
+               kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
 }
 
 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
 {
        if (adev->kfd.dev)
-               kgd2kfd->suspend(adev->kfd.dev);
+               kgd2kfd_suspend(adev->kfd.dev);
 }
 
 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
@@ -241,7 +232,7 @@ int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
        int r = 0;
 
        if (adev->kfd.dev)
-               r = kgd2kfd->resume(adev->kfd.dev);
+               r = kgd2kfd_resume(adev->kfd.dev);
 
        return r;
 }
@@ -251,7 +242,7 @@ int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
        int r = 0;
 
        if (adev->kfd.dev)
-               r = kgd2kfd->pre_reset(adev->kfd.dev);
+               r = kgd2kfd_pre_reset(adev->kfd.dev);
 
        return r;
 }
@@ -261,7 +252,7 @@ int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
        int r = 0;
 
        if (adev->kfd.dev)
-               r = kgd2kfd->post_reset(adev->kfd.dev);
+               r = kgd2kfd_post_reset(adev->kfd.dev);
 
        return r;
 }
@@ -619,4 +610,47 @@ struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
 {
        return NULL;
 }
+
+struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
+                             const struct kfd2kgd_calls *f2g)
+{
+       return NULL;
+}
+
+bool kgd2kfd_device_init(struct kfd_dev *kfd,
+                        const struct kgd2kfd_shared_resources *gpu_resources)
+{
+       return false;
+}
+
+void kgd2kfd_device_exit(struct kfd_dev *kfd)
+{
+}
+
+void kgd2kfd_exit(void)
+{
+}
+
+void kgd2kfd_suspend(struct kfd_dev *kfd)
+{
+}
+
+int kgd2kfd_resume(struct kfd_dev *kfd)
+{
+       return 0;
+}
+
+int kgd2kfd_pre_reset(struct kfd_dev *kfd)
+{
+       return 0;
+}
+
+int kgd2kfd_post_reset(struct kfd_dev *kfd)
+{
+       return 0;
+}
+
+void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
+{
+}
 #endif
index 70429f7aa9a84c0189ce3e3748a55f4b3549b08b..0b31a1859023c76403081277c6f3aa5941bee0ce 100644 (file)
@@ -33,7 +33,6 @@
 #include "amdgpu_sync.h"
 #include "amdgpu_vm.h"
 
-extern const struct kgd2kfd_calls *kgd2kfd;
 extern uint64_t amdgpu_amdkfd_total_mem_size;
 
 struct amdgpu_device;
@@ -214,4 +213,22 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
 void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo);
 
+/* KGD2KFD callbacks */
+int kgd2kfd_init(void);
+void kgd2kfd_exit(void);
+struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
+                             const struct kfd2kgd_calls *f2g);
+bool kgd2kfd_device_init(struct kfd_dev *kfd,
+                        const struct kgd2kfd_shared_resources *gpu_resources);
+void kgd2kfd_device_exit(struct kfd_dev *kfd);
+void kgd2kfd_suspend(struct kfd_dev *kfd);
+int kgd2kfd_resume(struct kfd_dev *kfd);
+int kgd2kfd_pre_reset(struct kfd_dev *kfd);
+int kgd2kfd_post_reset(struct kfd_dev *kfd);
+void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
+int kgd2kfd_quiesce_mm(struct mm_struct *mm);
+int kgd2kfd_resume_mm(struct mm_struct *mm);
+int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
+                                              struct dma_fence *fence);
+
 #endif /* AMDGPU_AMDKFD_H_INCLUDED */
index 574c1181ae9a22c1e63f37a5919c47a3b2d9c476..3107b9575929184bbf624d579bdcf3589116efdc 100644 (file)
@@ -122,7 +122,7 @@ static bool amdkfd_fence_enable_signaling(struct dma_fence *f)
        if (dma_fence_is_signaled(f))
                return true;
 
-       if (!kgd2kfd->schedule_evict_and_restore_process(fence->mm, f))
+       if (!kgd2kfd_schedule_evict_and_restore_process(fence->mm, f))
                return true;
 
        return false;
index be1ab43473c6c727bd1832efa3d5b7c09edffed2..d7b10d79f1debdcb5e8f254dd69c7d0b7119e730 100644 (file)
@@ -1790,7 +1790,7 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
        evicted_bos = atomic_inc_return(&process_info->evicted_bos);
        if (evicted_bos == 1) {
                /* First eviction, stop the queues */
-               r = kgd2kfd->quiesce_mm(mm);
+               r = kgd2kfd_quiesce_mm(mm);
                if (r)
                        pr_err("Failed to quiesce KFD\n");
                schedule_delayed_work(&process_info->restore_userptr_work,
@@ -2082,7 +2082,7 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
            evicted_bos)
                goto unlock_out;
        evicted_bos = 0;
-       if (kgd2kfd->resume_mm(mm)) {
+       if (kgd2kfd_resume_mm(mm)) {
                pr_err("%s: Failed to resume KFD\n", __func__);
                /* No recovery from this failure. Probably the CP is
                 * hanging. No point trying again.
index a028661d9e2013dd2a6e5611448438c7590fec82..92b11de1958132c28e4ffd68e1fd782a8e2e5771 100644 (file)
@@ -576,6 +576,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
        { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
        { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
        { 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX },
+       { 0x1002, 0x6900, 0x17AA, 0x3806, AMDGPU_PX_QUIRK_FORCE_ATPX },
        { 0, 0, 0, 0, 0 },
 };
 
index 8a078f4ae73dd17cc43384e605d28e4c613e7c37..c898b19f335a3549fe5ed0331b3a511b93b1d7a2 100644 (file)
@@ -1645,7 +1645,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
                if (r) {
                        DRM_ERROR("sw_init of IP block <%s> failed %d\n",
                                  adev->ip_blocks[i].version->funcs->name, r);
-                       return r;
+                       goto init_failed;
                }
                adev->ip_blocks[i].status.sw = true;
 
@@ -1654,17 +1654,17 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
                        r = amdgpu_device_vram_scratch_init(adev);
                        if (r) {
                                DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
-                               return r;
+                               goto init_failed;
                        }
                        r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
                        if (r) {
                                DRM_ERROR("hw_init %d failed %d\n", i, r);
-                               return r;
+                               goto init_failed;
                        }
                        r = amdgpu_device_wb_init(adev);
                        if (r) {
                                DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
-                               return r;
+                               goto init_failed;
                        }
                        adev->ip_blocks[i].status.hw = true;
 
@@ -1675,7 +1675,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
                                                                AMDGPU_CSA_SIZE);
                                if (r) {
                                        DRM_ERROR("allocate CSA failed %d\n", r);
-                                       return r;
+                                       goto init_failed;
                                }
                        }
                }
@@ -1683,28 +1683,32 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
 
        r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
        if (r)
-               return r;
+               goto init_failed;
 
        r = amdgpu_device_ip_hw_init_phase1(adev);
        if (r)
-               return r;
+               goto init_failed;
 
        r = amdgpu_device_fw_loading(adev);
        if (r)
-               return r;
+               goto init_failed;
 
        r = amdgpu_device_ip_hw_init_phase2(adev);
        if (r)
-               return r;
+               goto init_failed;
 
        if (adev->gmc.xgmi.num_physical_nodes > 1)
                amdgpu_xgmi_add_device(adev);
        amdgpu_amdkfd_device_init(adev);
 
-       if (amdgpu_sriov_vf(adev))
+init_failed:
+       if (amdgpu_sriov_vf(adev)) {
+               if (!r)
+                       amdgpu_virt_init_data_exchange(adev);
                amdgpu_virt_release_full_gpu(adev, true);
+       }
 
-       return 0;
+       return r;
 }
 
 /**
@@ -2131,7 +2135,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
                                continue;
 
                        r = block->version->funcs->hw_init(adev);
-                       DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+                       DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
                        if (r)
                                return r;
                }
@@ -2165,7 +2169,7 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
                                continue;
 
                        r = block->version->funcs->hw_init(adev);
-                       DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+                       DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
                        if (r)
                                return r;
                }
@@ -2546,6 +2550,17 @@ int amdgpu_device_init(struct amdgpu_device *adev,
        /* detect if we are with an SRIOV vbios */
        amdgpu_device_detect_sriov_bios(adev);
 
+       /* check if we need to reset the asic
+        *  E.g., driver was not cleanly unloaded previously, etc.
+        */
+       if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
+               r = amdgpu_asic_reset(adev);
+               if (r) {
+                       dev_err(adev->dev, "asic reset on init failed\n");
+                       goto failed;
+               }
+       }
+
        /* Post card if necessary */
        if (amdgpu_device_need_post(adev)) {
                if (!adev->bios) {
@@ -2610,6 +2625,8 @@ fence_driver_init:
                }
                dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
                amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
+               if (amdgpu_virt_request_full_gpu(adev, false))
+                       amdgpu_virt_release_full_gpu(adev, false);
                goto failed;
        }
 
@@ -2632,9 +2649,6 @@ fence_driver_init:
                goto failed;
        }
 
-       if (amdgpu_sriov_vf(adev))
-               amdgpu_virt_init_data_exchange(adev);
-
        amdgpu_fbdev_init(adev);
 
        r = amdgpu_pm_sysfs_init(adev);
@@ -2708,7 +2722,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
        amdgpu_irq_disable_all(adev);
        if (adev->mode_info.mode_config_initialized){
                if (!amdgpu_device_has_dc_support(adev))
-                       drm_crtc_force_disable_all(adev->ddev);
+                       drm_helper_force_disable_all(adev->ddev);
                else
                        drm_atomic_helper_shutdown(adev->ddev);
        }
@@ -2798,7 +2812,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
                        struct drm_framebuffer *fb = crtc->primary->fb;
                        struct amdgpu_bo *robj;
 
-                       if (amdgpu_crtc->cursor_bo) {
+                       if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
                                struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
                                r = amdgpu_bo_reserve(aobj, true);
                                if (r == 0) {
@@ -2906,7 +2920,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
                list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 
-                       if (amdgpu_crtc->cursor_bo) {
+                       if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
                                struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
                                r = amdgpu_bo_reserve(aobj, true);
                                if (r == 0) {
@@ -3226,6 +3240,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
        r = amdgpu_ib_ring_tests(adev);
 
 error:
+       amdgpu_virt_init_data_exchange(adev);
        amdgpu_virt_release_full_gpu(adev, true);
        if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
                atomic_inc(&adev->vram_lost_counter);
@@ -3298,17 +3313,15 @@ static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
                if (!ring || !ring->sched.thread)
                        continue;
 
-               kthread_park(ring->sched.thread);
-
-               if (job && job->base.sched != &ring->sched)
-                       continue;
-
-               drm_sched_hw_job_reset(&ring->sched, job ? &job->base : NULL);
+               drm_sched_stop(&ring->sched);
 
                /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
                amdgpu_fence_driver_force_completion(ring);
        }
 
+       if(job)
+               drm_sched_increase_karma(&job->base);
+
 
 
        if (!amdgpu_sriov_vf(adev)) {
@@ -3454,14 +3467,10 @@ static void amdgpu_device_post_asic_reset(struct amdgpu_device *adev,
                if (!ring || !ring->sched.thread)
                        continue;
 
-               /* only need recovery sched of the given job's ring
-                * or all rings (in the case @job is NULL)
-                * after above amdgpu_reset accomplished
-                */
-               if ((!job || job->base.sched == &ring->sched) && !adev->asic_reset_res)
-                       drm_sched_job_recovery(&ring->sched);
+               if (!adev->asic_reset_res)
+                       drm_sched_resubmit_jobs(&ring->sched);
 
-               kthread_unpark(ring->sched.thread);
+               drm_sched_start(&ring->sched, !adev->asic_reset_res);
        }
 
        if (!amdgpu_device_has_dc_support(adev)) {
@@ -3521,9 +3530,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
         * by different nodes. No point also since the one node already executing
         * reset will also reset all the other nodes in the hive.
         */
-       hive = amdgpu_get_xgmi_hive(adev);
+       hive = amdgpu_get_xgmi_hive(adev, 0);
        if (hive && adev->gmc.xgmi.num_physical_nodes > 1 &&
-           !mutex_trylock(&hive->hive_lock))
+           !mutex_trylock(&hive->reset_lock))
                return 0;
 
        /* Start with adev pre asic reset first for soft reset check.*/
@@ -3602,7 +3611,7 @@ retry:    /* Rest of adevs pre asic reset from XGMI hive. */
        }
 
        if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
-               mutex_unlock(&hive->hive_lock);
+               mutex_unlock(&hive->reset_lock);
 
        if (r)
                dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
index 15ce7e681d67c1776be90449a6d61bc0dfd02aa5..b083b219b1a966e9e38c318cb30c91e478f650c7 100644 (file)
@@ -188,10 +188,12 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
                goto cleanup;
        }
 
-       r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
-       if (unlikely(r != 0)) {
-               DRM_ERROR("failed to pin new abo buffer before flip\n");
-               goto unreserve;
+       if (!adev->enable_virtual_display) {
+               r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
+               if (unlikely(r != 0)) {
+                       DRM_ERROR("failed to pin new abo buffer before flip\n");
+                       goto unreserve;
+               }
        }
 
        r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
@@ -211,7 +213,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
        amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
        amdgpu_bo_unreserve(new_abo);
 
-       work->base = amdgpu_bo_gpu_offset(new_abo);
+       if (!adev->enable_virtual_display)
+               work->base = amdgpu_bo_gpu_offset(new_abo);
        work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
                amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
 
@@ -242,9 +245,10 @@ pflip_cleanup:
                goto cleanup;
        }
 unpin:
-       if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) {
-               DRM_ERROR("failed to unpin new abo in error path\n");
-       }
+       if (!adev->enable_virtual_display)
+               if (unlikely(amdgpu_bo_unpin(new_abo) != 0))
+                       DRM_ERROR("failed to unpin new abo in error path\n");
+
 unreserve:
        amdgpu_bo_unreserve(new_abo);
 
index be620b29f4aaa6b96e378955cf2831c75fbb223e..1cfec06f81d4049a35534f73f90defa303bcad2e 100644 (file)
@@ -51,14 +51,7 @@ struct amdgpu_doorbell_index {
        uint32_t userqueue_start;
        uint32_t userqueue_end;
        uint32_t gfx_ring0;
-       uint32_t sdma_engine0;
-       uint32_t sdma_engine1;
-       uint32_t sdma_engine2;
-       uint32_t sdma_engine3;
-       uint32_t sdma_engine4;
-       uint32_t sdma_engine5;
-       uint32_t sdma_engine6;
-       uint32_t sdma_engine7;
+       uint32_t sdma_engine[8];
        uint32_t ih;
        union {
                struct {
@@ -79,6 +72,8 @@ struct amdgpu_doorbell_index {
                } uvd_vce;
        };
        uint32_t max_assignment;
+       /* Per engine SDMA doorbell size in dword */
+       uint32_t sdma_doorbell_range;
 };
 
 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
index f972cd156795ab60ed786ee198b8d0048b90fc95..2f61e9edb1c1a10f69322807bb3f75d76a5ae97b 100644 (file)
@@ -364,6 +364,14 @@ enum amdgpu_pcie_gen {
                ((adev)->powerplay.pp_funcs->enable_mgpu_fan_boost(\
                        (adev)->powerplay.pp_handle))
 
+#define amdgpu_dpm_get_ppfeature_status(adev, buf) \
+               ((adev)->powerplay.pp_funcs->get_ppfeature_status(\
+                       (adev)->powerplay.pp_handle, (buf)))
+
+#define amdgpu_dpm_set_ppfeature_status(adev, ppfeatures) \
+               ((adev)->powerplay.pp_funcs->set_ppfeature_status(\
+                       (adev)->powerplay.pp_handle, (ppfeatures)))
+
 struct amdgpu_dpm {
        struct amdgpu_ps        *ps;
        /* number of valid power states */
index c48207b377bc5f5c64549eca69662896285971e5..0b8ef2d27d6b2b8e60e0959f0cb8e742e4de3c7f 100644 (file)
@@ -202,12 +202,12 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                        amdgpu_asic_flush_hdp(adev, ring);
        }
 
+       if (need_ctx_switch)
+               status |= AMDGPU_HAVE_CTX_SWITCH;
+
        skip_preamble = ring->current_ctx == fence_ctx;
        if (job && ring->funcs->emit_cntxcntl) {
-               if (need_ctx_switch)
-                       status |= AMDGPU_HAVE_CTX_SWITCH;
                status |= job->preamble_status;
-
                amdgpu_ring_emit_cntxcntl(ring, status);
        }
 
@@ -221,8 +221,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                        !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
                        continue;
 
-               amdgpu_ring_emit_ib(ring, job, ib, need_ctx_switch);
-               need_ctx_switch = false;
+               amdgpu_ring_emit_ib(ring, job, ib, status);
+               status &= ~AMDGPU_HAVE_CTX_SWITCH;
        }
 
        if (ring->funcs->emit_tmz)
index 8af67f6496608e04ed69de5e69930877c6029fea..d0a5db777b6d24c0b505a3ea827877ee91728ccf 100644 (file)
@@ -52,6 +52,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
        ih->use_bus_addr = use_bus_addr;
 
        if (use_bus_addr) {
+               dma_addr_t dma_addr;
+
                if (ih->ring)
                        return 0;
 
@@ -59,21 +61,26 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
                 * add them to the end of the ring allocation.
                 */
                ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
-                                             &ih->rb_dma_addr, GFP_KERNEL);
+                                             &dma_addr, GFP_KERNEL);
                if (ih->ring == NULL)
                        return -ENOMEM;
 
                memset((void *)ih->ring, 0, ih->ring_size + 8);
-               ih->wptr_offs = (ih->ring_size / 4) + 0;
-               ih->rptr_offs = (ih->ring_size / 4) + 1;
+               ih->gpu_addr = dma_addr;
+               ih->wptr_addr = dma_addr + ih->ring_size;
+               ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
+               ih->rptr_addr = dma_addr + ih->ring_size + 4;
+               ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
        } else {
-               r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
+               unsigned wptr_offs, rptr_offs;
+
+               r = amdgpu_device_wb_get(adev, &wptr_offs);
                if (r)
                        return r;
 
-               r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
+               r = amdgpu_device_wb_get(adev, &rptr_offs);
                if (r) {
-                       amdgpu_device_wb_free(adev, ih->wptr_offs);
+                       amdgpu_device_wb_free(adev, wptr_offs);
                        return r;
                }
 
@@ -82,10 +89,15 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
                                            &ih->ring_obj, &ih->gpu_addr,
                                            (void **)&ih->ring);
                if (r) {
-                       amdgpu_device_wb_free(adev, ih->rptr_offs);
-                       amdgpu_device_wb_free(adev, ih->wptr_offs);
+                       amdgpu_device_wb_free(adev, rptr_offs);
+                       amdgpu_device_wb_free(adev, wptr_offs);
                        return r;
                }
+
+               ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
+               ih->wptr_cpu = &adev->wb.wb[wptr_offs];
+               ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
+               ih->rptr_cpu = &adev->wb.wb[rptr_offs];
        }
        return 0;
 }
@@ -109,13 +121,13 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
                 * add them to the end of the ring allocation.
                 */
                dma_free_coherent(adev->dev, ih->ring_size + 8,
-                                 (void *)ih->ring, ih->rb_dma_addr);
+                                 (void *)ih->ring, ih->gpu_addr);
                ih->ring = NULL;
        } else {
                amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
                                      (void **)&ih->ring);
-               amdgpu_device_wb_free(adev, ih->wptr_offs);
-               amdgpu_device_wb_free(adev, ih->rptr_offs);
+               amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
+               amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
        }
 }
 
@@ -137,7 +149,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
        if (!ih->enabled || adev->shutdown)
                return IRQ_NONE;
 
-       wptr = amdgpu_ih_get_wptr(adev);
+       wptr = amdgpu_ih_get_wptr(adev, ih);
 
 restart_ih:
        /* is somebody else already processing irqs? */
@@ -154,11 +166,11 @@ restart_ih:
                ih->rptr &= ih->ptr_mask;
        }
 
-       amdgpu_ih_set_rptr(adev);
+       amdgpu_ih_set_rptr(adev, ih);
        atomic_set(&ih->lock, 0);
 
        /* make sure wptr hasn't changed while processing */
-       wptr = amdgpu_ih_get_wptr(adev);
+       wptr = amdgpu_ih_get_wptr(adev, ih);
        if (wptr != ih->rptr)
                goto restart_ih;
 
index f877bb78d10a31b11ebb9d8563d7b86055390966..1ccb1831382a2699a91d69a8a441f0e4fc60bfbb 100644 (file)
@@ -31,34 +31,40 @@ struct amdgpu_iv_entry;
  * R6xx+ IH ring
  */
 struct amdgpu_ih_ring {
-       struct amdgpu_bo        *ring_obj;
-       volatile uint32_t       *ring;
-       unsigned                rptr;
        unsigned                ring_size;
-       uint64_t                gpu_addr;
        uint32_t                ptr_mask;
-       atomic_t                lock;
-       bool                    enabled;
-       unsigned                wptr_offs;
-       unsigned                rptr_offs;
        u32                     doorbell_index;
        bool                    use_doorbell;
        bool                    use_bus_addr;
-       dma_addr_t              rb_dma_addr; /* only used when use_bus_addr = true */
+
+       struct amdgpu_bo        *ring_obj;
+       volatile uint32_t       *ring;
+       uint64_t                gpu_addr;
+
+       uint64_t                wptr_addr;
+       volatile uint32_t       *wptr_cpu;
+
+       uint64_t                rptr_addr;
+       volatile uint32_t       *rptr_cpu;
+
+       bool                    enabled;
+       unsigned                rptr;
+       atomic_t                lock;
 };
 
 /* provided by the ih block */
 struct amdgpu_ih_funcs {
        /* ring read/write ptr handling, called from interrupt context */
-       u32 (*get_wptr)(struct amdgpu_device *adev);
-       void (*decode_iv)(struct amdgpu_device *adev,
+       u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
+       void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
                          struct amdgpu_iv_entry *entry);
-       void (*set_rptr)(struct amdgpu_device *adev);
+       void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
 };
 
-#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
-#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
-#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
+#define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
+#define amdgpu_ih_decode_iv(adev, iv) \
+       (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
+#define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih))
 
 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
                        unsigned ring_size, bool use_bus_addr);
index b7968f4268625e99f7dc62fdddf3b44a896edae5..8bfb3dab46f711029018729db41bbf808c34261e 100644 (file)
@@ -148,6 +148,8 @@ static void amdgpu_irq_callback(struct amdgpu_device *adev,
        entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
        amdgpu_ih_decode_iv(adev, &entry);
 
+       trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
+
        amdgpu_irq_dispatch(adev, &entry);
 }
 
@@ -174,6 +176,36 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
        return ret;
 }
 
+/**
+ * amdgpu_irq_handle_ih1 - kick of processing for IH1
+ *
+ * @work: work structure in struct amdgpu_irq
+ *
+ * Kick of processing IH ring 1.
+ */
+static void amdgpu_irq_handle_ih1(struct work_struct *work)
+{
+       struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+                                                 irq.ih1_work);
+
+       amdgpu_ih_process(adev, &adev->irq.ih1, amdgpu_irq_callback);
+}
+
+/**
+ * amdgpu_irq_handle_ih2 - kick of processing for IH2
+ *
+ * @work: work structure in struct amdgpu_irq
+ *
+ * Kick of processing IH ring 2.
+ */
+static void amdgpu_irq_handle_ih2(struct work_struct *work)
+{
+       struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+                                                 irq.ih2_work);
+
+       amdgpu_ih_process(adev, &adev->irq.ih2, amdgpu_irq_callback);
+}
+
 /**
  * amdgpu_msi_ok - check whether MSI functionality is enabled
  *
@@ -238,6 +270,9 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
                                amdgpu_hotplug_work_func);
        }
 
+       INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
+       INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
+
        adev->irq.installed = true;
        r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
        if (r) {
@@ -367,8 +402,6 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
        bool handled = false;
        int r;
 
-       trace_amdgpu_iv(entry);
-
        if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
                DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
 
index f6ce171cb8aa76a3ba38ba396ee0ad2d7b5b153d..c27decfda494d7f6caaa430225ec584f74b30240 100644 (file)
@@ -87,9 +87,11 @@ struct amdgpu_irq {
        /* status, etc. */
        bool                            msi_enabled; /* msi enabled */
 
-       /* interrupt ring */
-       struct amdgpu_ih_ring           ih;
-       const struct amdgpu_ih_funcs    *ih_funcs;
+       /* interrupt rings */
+       struct amdgpu_ih_ring           ih, ih1, ih2;
+       const struct amdgpu_ih_funcs    *ih_funcs;
+       struct work_struct              ih1_work, ih2_work;
+       struct amdgpu_irq_src           self_irq;
 
        /* gen irq stuff */
        struct irq_domain               *domain; /* GPU irq controller domain */
index 1f61ed95727ce3083faa9036c0d05f2d16641a5c..a7adb7b6bd98ab7b615a1d8c103551f2ffa46d1c 100644 (file)
@@ -626,11 +626,71 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 }
 
 /**
- * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
+ * DOC: ppfeatures
+ *
+ * The amdgpu driver provides a sysfs API for adjusting what powerplay
+ * features to be enabled. The file ppfeatures is used for this. And
+ * this is only available for Vega10 and later dGPUs.
+ *
+ * Reading back the file will show you the followings:
+ * - Current ppfeature masks
+ * - List of the all supported powerplay features with their naming,
+ *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
+ *
+ * To manually enable or disable a specific feature, just set or clear
+ * the corresponding bit from original ppfeature masks and input the
+ * new ppfeature masks.
+ */
+static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+               struct device_attribute *attr,
+               const char *buf,
+               size_t count)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = ddev->dev_private;
+       uint64_t featuremask;
+       int ret;
+
+       ret = kstrtou64(buf, 0, &featuremask);
+       if (ret)
+               return -EINVAL;
+
+       pr_debug("featuremask = 0x%llx\n", featuremask);
+
+       if (adev->powerplay.pp_funcs->set_ppfeature_status) {
+               ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
+               if (ret)
+                       return -EINVAL;
+       }
+
+       return count;
+}
+
+static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+               struct device_attribute *attr,
+               char *buf)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = ddev->dev_private;
+
+       if (adev->powerplay.pp_funcs->get_ppfeature_status)
+               return amdgpu_dpm_get_ppfeature_status(adev, buf);
+
+       return snprintf(buf, PAGE_SIZE, "\n");
+}
+
+/**
+ * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
+ * pp_dpm_pcie
  *
  * The amdgpu driver provides a sysfs API for adjusting what power levels
  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
- * and pp_dpm_pcie are used for this.
+ * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
+ * this.
+ *
+ * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
+ * Vega10 and later ASICs.
+ * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
  *
  * Reading back the files will show you the available power levels within
  * the power state and the clock information for those levels.
@@ -640,6 +700,8 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * Secondly,Enter a new value for each level by inputing a string that
  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
+ *
+ * NOTE: change to the dcefclk max dpm level is not supported now
  */
 
 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
@@ -750,6 +812,114 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
        return count;
 }
 
+static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
+               struct device_attribute *attr,
+               char *buf)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = ddev->dev_private;
+
+       if (adev->powerplay.pp_funcs->print_clock_levels)
+               return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
+       else
+               return snprintf(buf, PAGE_SIZE, "\n");
+}
+
+static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
+               struct device_attribute *attr,
+               const char *buf,
+               size_t count)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = ddev->dev_private;
+       int ret;
+       uint32_t mask = 0;
+
+       ret = amdgpu_read_mask(buf, count, &mask);
+       if (ret)
+               return ret;
+
+       if (adev->powerplay.pp_funcs->force_clock_level)
+               ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
+
+       if (ret)
+               return -EINVAL;
+
+       return count;
+}
+
+static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
+               struct device_attribute *attr,
+               char *buf)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = ddev->dev_private;
+
+       if (adev->powerplay.pp_funcs->print_clock_levels)
+               return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
+       else
+               return snprintf(buf, PAGE_SIZE, "\n");
+}
+
+static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
+               struct device_attribute *attr,
+               const char *buf,
+               size_t count)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = ddev->dev_private;
+       int ret;
+       uint32_t mask = 0;
+
+       ret = amdgpu_read_mask(buf, count, &mask);
+       if (ret)
+               return ret;
+
+       if (adev->powerplay.pp_funcs->force_clock_level)
+               ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
+
+       if (ret)
+               return -EINVAL;
+
+       return count;
+}
+
+static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
+               struct device_attribute *attr,
+               char *buf)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = ddev->dev_private;
+
+       if (adev->powerplay.pp_funcs->print_clock_levels)
+               return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
+       else
+               return snprintf(buf, PAGE_SIZE, "\n");
+}
+
+static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
+               struct device_attribute *attr,
+               const char *buf,
+               size_t count)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = ddev->dev_private;
+       int ret;
+       uint32_t mask = 0;
+
+       ret = amdgpu_read_mask(buf, count, &mask);
+       if (ret)
+               return ret;
+
+       if (adev->powerplay.pp_funcs->force_clock_level)
+               ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
+
+       if (ret)
+               return -EINVAL;
+
+       return count;
+}
+
 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
                struct device_attribute *attr,
                char *buf)
@@ -990,6 +1160,31 @@ static ssize_t amdgpu_get_busy_percent(struct device *dev,
        return snprintf(buf, PAGE_SIZE, "%d\n", value);
 }
 
+/**
+ * DOC: pcie_bw
+ *
+ * The amdgpu driver provides a sysfs API for estimating how much data
+ * has been received and sent by the GPU in the last second through PCIe.
+ * The file pcie_bw is used for this.
+ * The Perf counters count the number of received and sent messages and return
+ * those values, as well as the maximum payload size of a PCIe packet (mps).
+ * Note that it is not possible to easily and quickly obtain the size of each
+ * packet transmitted, so we output the max payload size (mps) to allow for
+ * quick estimation of the PCIe bandwidth usage
+ */
+static ssize_t amdgpu_get_pcie_bw(struct device *dev,
+               struct device_attribute *attr,
+               char *buf)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = ddev->dev_private;
+       uint64_t count0, count1;
+
+       amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
+       return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
+                       count0, count1, pcie_get_mps(adev->pdev));
+}
+
 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
                   amdgpu_get_dpm_forced_performance_level,
@@ -1008,6 +1203,15 @@ static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
                amdgpu_get_pp_dpm_mclk,
                amdgpu_set_pp_dpm_mclk);
+static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
+               amdgpu_get_pp_dpm_socclk,
+               amdgpu_set_pp_dpm_socclk);
+static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
+               amdgpu_get_pp_dpm_fclk,
+               amdgpu_set_pp_dpm_fclk);
+static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
+               amdgpu_get_pp_dpm_dcefclk,
+               amdgpu_set_pp_dpm_dcefclk);
 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
                amdgpu_get_pp_dpm_pcie,
                amdgpu_set_pp_dpm_pcie);
@@ -1025,6 +1229,10 @@ static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
                amdgpu_set_pp_od_clk_voltage);
 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
                amdgpu_get_busy_percent, NULL);
+static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
+static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
+               amdgpu_get_ppfeature_status,
+               amdgpu_set_ppfeature_status);
 
 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
                                      struct device_attribute *attr,
@@ -1516,6 +1724,75 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
        return count;
 }
 
+static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
+                                     struct device_attribute *attr,
+                                     char *buf)
+{
+       struct amdgpu_device *adev = dev_get_drvdata(dev);
+       struct drm_device *ddev = adev->ddev;
+       uint32_t sclk;
+       int r, size = sizeof(sclk);
+
+       /* Can't get voltage when the card is off */
+       if  ((adev->flags & AMD_IS_PX) &&
+            (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+               return -EINVAL;
+
+       /* sanity check PP is enabled */
+       if (!(adev->powerplay.pp_funcs &&
+             adev->powerplay.pp_funcs->read_sensor))
+             return -EINVAL;
+
+       /* get the sclk */
+       r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
+                                  (void *)&sclk, &size);
+       if (r)
+               return r;
+
+       return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
+}
+
+static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
+                                           struct device_attribute *attr,
+                                           char *buf)
+{
+       return snprintf(buf, PAGE_SIZE, "sclk\n");
+}
+
+static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
+                                     struct device_attribute *attr,
+                                     char *buf)
+{
+       struct amdgpu_device *adev = dev_get_drvdata(dev);
+       struct drm_device *ddev = adev->ddev;
+       uint32_t mclk;
+       int r, size = sizeof(mclk);
+
+       /* Can't get voltage when the card is off */
+       if  ((adev->flags & AMD_IS_PX) &&
+            (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+               return -EINVAL;
+
+       /* sanity check PP is enabled */
+       if (!(adev->powerplay.pp_funcs &&
+             adev->powerplay.pp_funcs->read_sensor))
+             return -EINVAL;
+
+       /* get the sclk */
+       r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
+                                  (void *)&mclk, &size);
+       if (r)
+               return r;
+
+       return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
+}
+
+static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
+                                           struct device_attribute *attr,
+                                           char *buf)
+{
+       return snprintf(buf, PAGE_SIZE, "mclk\n");
+}
 
 /**
  * DOC: hwmon
@@ -1532,6 +1809,10 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
  *
  * - GPU fan
  *
+ * - GPU gfx/compute engine clock
+ *
+ * - GPU memory clock (dGPU only)
+ *
  * hwmon interfaces for GPU temperature:
  *
  * - temp1_input: the on die GPU temperature in millidegrees Celsius
@@ -1576,6 +1857,12 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
  *
  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
  *
+ * hwmon interfaces for GPU clocks:
+ *
+ * - freq1_input: the gfx/compute clock in hertz
+ *
+ * - freq2_input: the memory clock in hertz
+ *
  * You can use hwmon tools like sensors to view this information on your system.
  *
  */
@@ -1600,6 +1887,10 @@ static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg,
 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
+static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
+static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
+static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
+static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
 
 static struct attribute *hwmon_attributes[] = {
        &sensor_dev_attr_temp1_input.dev_attr.attr,
@@ -1622,6 +1913,10 @@ static struct attribute *hwmon_attributes[] = {
        &sensor_dev_attr_power1_cap_max.dev_attr.attr,
        &sensor_dev_attr_power1_cap_min.dev_attr.attr,
        &sensor_dev_attr_power1_cap.dev_attr.attr,
+       &sensor_dev_attr_freq1_input.dev_attr.attr,
+       &sensor_dev_attr_freq1_label.dev_attr.attr,
+       &sensor_dev_attr_freq2_input.dev_attr.attr,
+       &sensor_dev_attr_freq2_label.dev_attr.attr,
        NULL
 };
 
@@ -1686,7 +1981,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
                effective_mode &= ~S_IWUSR;
 
        if ((adev->flags & AMD_IS_APU) &&
-           (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
+           (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
+            attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
             attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
             attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
                return 0;
@@ -1712,6 +2008,12 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
             attr == &sensor_dev_attr_in1_label.dev_attr.attr))
                return 0;
 
+       /* no mclk on APUs */
+       if ((adev->flags & AMD_IS_APU) &&
+           (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
+            attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
+               return 0;
+
        return effective_mode;
 }
 
@@ -2008,6 +2310,7 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
 
 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 {
+       struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
        int ret;
 
        if (adev->pm.sysfs_initialized)
@@ -2069,6 +2372,25 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                DRM_ERROR("failed to create device file pp_dpm_mclk\n");
                return ret;
        }
+       if (adev->asic_type >= CHIP_VEGA10) {
+               ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
+               if (ret) {
+                       DRM_ERROR("failed to create device file pp_dpm_socclk\n");
+                       return ret;
+               }
+               ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+               if (ret) {
+                       DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
+                       return ret;
+               }
+       }
+       if (adev->asic_type >= CHIP_VEGA20) {
+               ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
+               if (ret) {
+                       DRM_ERROR("failed to create device file pp_dpm_fclk\n");
+                       return ret;
+               }
+       }
        ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
        if (ret) {
                DRM_ERROR("failed to create device file pp_dpm_pcie\n");
@@ -2091,12 +2413,14 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                                "pp_power_profile_mode\n");
                return ret;
        }
-       ret = device_create_file(adev->dev,
-                       &dev_attr_pp_od_clk_voltage);
-       if (ret) {
-               DRM_ERROR("failed to create device file "
-                               "pp_od_clk_voltage\n");
-               return ret;
+       if (hwmgr->od_enabled) {
+               ret = device_create_file(adev->dev,
+                               &dev_attr_pp_od_clk_voltage);
+               if (ret) {
+                       DRM_ERROR("failed to create device file "
+                                       "pp_od_clk_voltage\n");
+                       return ret;
+               }
        }
        ret = device_create_file(adev->dev,
                        &dev_attr_gpu_busy_percent);
@@ -2105,12 +2429,31 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                                "gpu_busy_level\n");
                return ret;
        }
+       /* PCIe Perf counters won't work on APU nodes */
+       if (!(adev->flags & AMD_IS_APU)) {
+               ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
+               if (ret) {
+                       DRM_ERROR("failed to create device file pcie_bw\n");
+                       return ret;
+               }
+       }
        ret = amdgpu_debugfs_pm_init(adev);
        if (ret) {
                DRM_ERROR("Failed to register debugfs file for dpm!\n");
                return ret;
        }
 
+       if ((adev->asic_type >= CHIP_VEGA10) &&
+           !(adev->flags & AMD_IS_APU)) {
+               ret = device_create_file(adev->dev,
+                               &dev_attr_ppfeatures);
+               if (ret) {
+                       DRM_ERROR("failed to create device file "
+                                       "ppfeatures\n");
+                       return ret;
+               }
+       }
+
        adev->pm.sysfs_initialized = true;
 
        return 0;
@@ -2118,6 +2461,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 
 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 {
+       struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
+
        if (adev->pm.dpm_enabled == 0)
                return;
 
@@ -2133,14 +2478,26 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 
        device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
        device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
+       if (adev->asic_type >= CHIP_VEGA10) {
+               device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
+               device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+       }
        device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
+       if (adev->asic_type >= CHIP_VEGA20)
+               device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
        device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
        device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
        device_remove_file(adev->dev,
                        &dev_attr_pp_power_profile_mode);
-       device_remove_file(adev->dev,
-                       &dev_attr_pp_od_clk_voltage);
+       if (hwmgr->od_enabled)
+               device_remove_file(adev->dev,
+                               &dev_attr_pp_od_clk_voltage);
        device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
+       if (!(adev->flags & AMD_IS_APU))
+               device_remove_file(adev->dev, &dev_attr_pcie_bw);
+       if ((adev->asic_type >= CHIP_VEGA10) &&
+           !(adev->flags & AMD_IS_APU))
+               device_remove_file(adev->dev, &dev_attr_ppfeatures);
 }
 
 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
index 8fab0d637ee51f96fa31cb5d81178d60f52db458..d87f165e3a23dd2de261c4489d229134962e756d 100644 (file)
@@ -67,9 +67,6 @@ static int psp_sw_init(void *handle)
 
        psp->adev = adev;
 
-       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-               return 0;
-
        ret = psp_init_microcode(psp);
        if (ret) {
                DRM_ERROR("Failed to load psp firmware!\n");
@@ -83,9 +80,6 @@ static int psp_sw_fini(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-               return 0;
-
        release_firmware(adev->psp.sos_fw);
        adev->psp.sos_fw = NULL;
        release_firmware(adev->psp.asd_fw);
@@ -140,13 +134,24 @@ psp_cmd_submit_buf(struct psp_context *psp,
        while (*((unsigned int *)psp->fence_buf) != index)
                msleep(1);
 
-       /* the status field must be 0 after FW is loaded */
-       if (ucode && psp->cmd_buf_mem->resp.status) {
-               DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n",
-                         psp->cmd_buf_mem->resp.status, ucode->ucode_id);
-               return -EINVAL;
+       /* In some cases, psp response status is not 0 even there is no
+        * problem while the command is submitted. Some version of PSP FW
+        * doesn't write 0 to that field.
+        * So here we would like to only print a warning instead of an error
+        * during psp initialization to avoid breaking hw_init and it doesn't
+        * return -EINVAL.
+        */
+       if (psp->cmd_buf_mem->resp.status) {
+               if (ucode)
+                       DRM_WARN("failed to load ucode id (%d) ",
+                                 ucode->ucode_id);
+               DRM_WARN("psp command failed and response status is (%d)\n",
+                         psp->cmd_buf_mem->resp.status);
        }
 
+       /* get xGMI session id from response buffer */
+       cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
+
        if (ucode) {
                ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
                ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
@@ -495,6 +500,98 @@ static int psp_hw_start(struct psp_context *psp)
        return 0;
 }
 
+static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
+                          enum psp_gfx_fw_type *type)
+{
+       switch (ucode->ucode_id) {
+       case AMDGPU_UCODE_ID_SDMA0:
+               *type = GFX_FW_TYPE_SDMA0;
+               break;
+       case AMDGPU_UCODE_ID_SDMA1:
+               *type = GFX_FW_TYPE_SDMA1;
+               break;
+       case AMDGPU_UCODE_ID_CP_CE:
+               *type = GFX_FW_TYPE_CP_CE;
+               break;
+       case AMDGPU_UCODE_ID_CP_PFP:
+               *type = GFX_FW_TYPE_CP_PFP;
+               break;
+       case AMDGPU_UCODE_ID_CP_ME:
+               *type = GFX_FW_TYPE_CP_ME;
+               break;
+       case AMDGPU_UCODE_ID_CP_MEC1:
+               *type = GFX_FW_TYPE_CP_MEC;
+               break;
+       case AMDGPU_UCODE_ID_CP_MEC1_JT:
+               *type = GFX_FW_TYPE_CP_MEC_ME1;
+               break;
+       case AMDGPU_UCODE_ID_CP_MEC2:
+               *type = GFX_FW_TYPE_CP_MEC;
+               break;
+       case AMDGPU_UCODE_ID_CP_MEC2_JT:
+               *type = GFX_FW_TYPE_CP_MEC_ME2;
+               break;
+       case AMDGPU_UCODE_ID_RLC_G:
+               *type = GFX_FW_TYPE_RLC_G;
+               break;
+       case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
+               *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
+               break;
+       case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
+               *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
+               break;
+       case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
+               *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
+               break;
+       case AMDGPU_UCODE_ID_SMC:
+               *type = GFX_FW_TYPE_SMU;
+               break;
+       case AMDGPU_UCODE_ID_UVD:
+               *type = GFX_FW_TYPE_UVD;
+               break;
+       case AMDGPU_UCODE_ID_UVD1:
+               *type = GFX_FW_TYPE_UVD1;
+               break;
+       case AMDGPU_UCODE_ID_VCE:
+               *type = GFX_FW_TYPE_VCE;
+               break;
+       case AMDGPU_UCODE_ID_VCN:
+               *type = GFX_FW_TYPE_VCN;
+               break;
+       case AMDGPU_UCODE_ID_DMCU_ERAM:
+               *type = GFX_FW_TYPE_DMCU_ERAM;
+               break;
+       case AMDGPU_UCODE_ID_DMCU_INTV:
+               *type = GFX_FW_TYPE_DMCU_ISR;
+               break;
+       case AMDGPU_UCODE_ID_MAXIMUM:
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
+                                      struct psp_gfx_cmd_resp *cmd)
+{
+       int ret;
+       uint64_t fw_mem_mc_addr = ucode->mc_addr;
+
+       memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
+
+       cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
+       cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
+       cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
+       cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
+
+       ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
+       if (ret)
+               DRM_ERROR("Unknown firmware type\n");
+
+       return ret;
+}
+
 static int psp_np_fw_load(struct psp_context *psp)
 {
        int i, ret;
@@ -516,7 +613,7 @@ static int psp_np_fw_load(struct psp_context *psp)
                        /*skip ucode loading in SRIOV VF */
                        continue;
 
-               ret = psp_prep_cmd_buf(ucode, psp->cmd);
+               ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
                if (ret)
                        return ret;
 
@@ -541,7 +638,7 @@ static int psp_load_fw(struct amdgpu_device *adev)
        struct psp_context *psp = &adev->psp;
 
        if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
-               psp_ring_destroy(psp, PSP_RING_TYPE__KM);
+               psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
                goto skip_memalloc;
        }
 
@@ -618,10 +715,6 @@ static int psp_hw_init(void *handle)
        int ret;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-
-       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-               return 0;
-
        mutex_lock(&adev->firmware.mutex);
        /*
         * This sequence is just used on hw_init only once, no need on
@@ -651,9 +744,6 @@ static int psp_hw_fini(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct psp_context *psp = &adev->psp;
 
-       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-               return 0;
-
        if (adev->gmc.xgmi.num_physical_nodes > 1 &&
            psp->xgmi_context.initialized == 1)
                 psp_xgmi_terminate(psp);
@@ -682,9 +772,6 @@ static int psp_suspend(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct psp_context *psp = &adev->psp;
 
-       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-               return 0;
-
        if (adev->gmc.xgmi.num_physical_nodes > 1 &&
            psp->xgmi_context.initialized == 1) {
                ret = psp_xgmi_terminate(psp);
@@ -709,9 +796,6 @@ static int psp_resume(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct psp_context *psp = &adev->psp;
 
-       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-               return 0;
-
        DRM_INFO("PSP is resuming...\n");
 
        mutex_lock(&adev->firmware.mutex);
@@ -747,11 +831,6 @@ static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 {
        struct amdgpu_firmware_info *ucode = NULL;
 
-       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
-               DRM_INFO("firmware is not loaded by PSP\n");
-               return true;
-       }
-
        if (!adev->firmware.fw_size)
                return false;
 
index 3ee573b4016e2118b208ec0fb466a63ed9722eb1..2ef98cc755d6e0438c551803a14f28570b827333 100644 (file)
@@ -65,8 +65,6 @@ struct psp_funcs
        int (*init_microcode)(struct psp_context *psp);
        int (*bootloader_load_sysdrv)(struct psp_context *psp);
        int (*bootloader_load_sos)(struct psp_context *psp);
-       int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
-                           struct psp_gfx_cmd_resp *cmd);
        int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
        int (*ring_create)(struct psp_context *psp,
                           enum psp_ring_type ring_type);
@@ -176,7 +174,6 @@ struct psp_xgmi_topology_info {
        struct psp_xgmi_node_info       nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
 };
 
-#define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type))
 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
index d87e828a084b959ee6651ad080c698eb7f2b3bca..d7fae2676269478b66fb0fd45dfd450ed37de86f 100644 (file)
@@ -131,7 +131,7 @@ struct amdgpu_ring_funcs {
        void (*emit_ib)(struct amdgpu_ring *ring,
                        struct amdgpu_job *job,
                        struct amdgpu_ib *ib,
-                       bool ctx_switch);
+                       uint32_t flags);
        void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
                           uint64_t seq, unsigned flags);
        void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
@@ -229,7 +229,7 @@ struct amdgpu_ring {
 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
-#define amdgpu_ring_emit_ib(r, job, ib, c) ((r)->funcs->emit_ib((r), (job), (ib), (c)))
+#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
index 12f2bf97611fb9c6dec30f8569c3f11caebffc7a..bfaf5c6323becc187c4b174207bbeb07abad6e8e 100644 (file)
@@ -388,7 +388,7 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
                           soffset, eoffset, eoffset - soffset);
 
                if (i->fence)
-                       seq_printf(m, " protected by 0x%08x on context %llu",
+                       seq_printf(m, " protected by 0x%016llx on context %llu",
                                   i->fence->seqno, i->fence->context);
 
                seq_printf(m, "\n");
index 626abca770a0367b853000358b580fdc7c82ff22..d3ca2424b5fe9a153a67eb6d77d1f59bcb7ba729 100644 (file)
@@ -76,9 +76,10 @@ TRACE_EVENT(amdgpu_mm_wreg,
 );
 
 TRACE_EVENT(amdgpu_iv,
-           TP_PROTO(struct amdgpu_iv_entry *iv),
-           TP_ARGS(iv),
+           TP_PROTO(unsigned ih, struct amdgpu_iv_entry *iv),
+           TP_ARGS(ih, iv),
            TP_STRUCT__entry(
+                            __field(unsigned, ih)
                             __field(unsigned, client_id)
                             __field(unsigned, src_id)
                             __field(unsigned, ring_id)
@@ -90,6 +91,7 @@ TRACE_EVENT(amdgpu_iv,
                             __array(unsigned, src_data, 4)
                            ),
            TP_fast_assign(
+                          __entry->ih = ih;
                           __entry->client_id = iv->client_id;
                           __entry->src_id = iv->src_id;
                           __entry->ring_id = iv->ring_id;
@@ -103,8 +105,9 @@ TRACE_EVENT(amdgpu_iv,
                           __entry->src_data[2] = iv->src_data[2];
                           __entry->src_data[3] = iv->src_data[3];
                           ),
-           TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x",
-                     __entry->client_id, __entry->src_id,
+           TP_printk("ih:%u client_id:%u src_id:%u ring:%u vmid:%u "
+                     "timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x",
+                     __entry->ih, __entry->client_id, __entry->src_id,
                      __entry->ring_id, __entry->vmid,
                      __entry->timestamp, __entry->pasid,
                      __entry->src_data[0], __entry->src_data[1],
index c91ec3101d00b5d06e48db30c71b3cf938d95b63..b852abb9db0f21b3e56400eb4facbf7eb85e9653 100644 (file)
@@ -1546,7 +1546,8 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
        .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
        .io_mem_free = &amdgpu_ttm_io_mem_free,
        .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
-       .access_memory = &amdgpu_ttm_access_memory
+       .access_memory = &amdgpu_ttm_access_memory,
+       .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
 };
 
 /*
index 98a1b2ce2b9d38cec778dc2c9a8097661eca27b0..c021b114c8a44ec04c6ca3bccc4479c141218232 100644 (file)
@@ -1035,7 +1035,7 @@ out:
 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring,
                                struct amdgpu_job *job,
                                struct amdgpu_ib *ib,
-                               bool ctx_switch)
+                               uint32_t flags)
 {
        amdgpu_ring_write(ring, VCE_CMD_IB);
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
index 50293652af148cc3c8fa2d04d8b7723e8b744e32..30ea54dd91173b57dbf48e9a9d12915f752d0e13 100644 (file)
@@ -66,7 +66,7 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
-                               struct amdgpu_ib *ib, bool ctx_switch);
+                               struct amdgpu_ib *ib, uint32_t flags);
 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
                                unsigned flags);
 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
index e73d152659a2f236f83b38996290facc7981581c..0bc6f553dc081700e58076685aa3314d95948680 100644 (file)
@@ -623,6 +623,28 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
        list_add(&entry->tv.head, validated);
 }
 
+void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
+{
+       struct amdgpu_bo *abo;
+       struct amdgpu_vm_bo_base *bo_base;
+
+       if (!amdgpu_bo_is_amdgpu_bo(bo))
+               return;
+
+       if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)
+               return;
+
+       abo = ttm_to_amdgpu_bo(bo);
+       if (!abo->parent)
+               return;
+       for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
+               struct amdgpu_vm *vm = bo_base->vm;
+
+               if (abo->tbo.resv == vm->root.base.bo->tbo.resv)
+                       vm->bulk_moveable = false;
+       }
+
+}
 /**
  * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
  *
@@ -799,9 +821,16 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
                addr += ats_entries * 8;
        }
 
-       if (entries)
+       if (entries) {
+               uint64_t value = 0;
+
+               /* Workaround for fault priority problem on GMC9 */
+               if (level == AMDGPU_VM_PTB && adev->asic_type >= CHIP_VEGA10)
+                       value = AMDGPU_PTE_EXECUTABLE;
+
                amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
-                                     entries, 0, 0);
+                                     entries, 0, value);
+       }
 
        amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 
@@ -847,9 +876,6 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
        bp->size = amdgpu_vm_bo_size(adev, level);
        bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
        bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
-       if (bp->size <= PAGE_SIZE && adev->asic_type >= CHIP_VEGA10 &&
-           adev->flags & AMD_IS_APU)
-               bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
        bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
        bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
                AMDGPU_GEM_CREATE_CPU_GTT_USWC;
@@ -1506,20 +1532,27 @@ error:
 }
 
 /**
- * amdgpu_vm_update_huge - figure out parameters for PTE updates
+ * amdgpu_vm_update_flags - figure out flags for PTE updates
  *
  * Make sure to set the right flags for the PTEs at the desired level.
  */
-static void amdgpu_vm_update_huge(struct amdgpu_pte_update_params *params,
-                                 struct amdgpu_bo *bo, unsigned level,
-                                 uint64_t pe, uint64_t addr,
-                                 unsigned count, uint32_t incr,
-                                 uint64_t flags)
+static void amdgpu_vm_update_flags(struct amdgpu_pte_update_params *params,
+                                  struct amdgpu_bo *bo, unsigned level,
+                                  uint64_t pe, uint64_t addr,
+                                  unsigned count, uint32_t incr,
+                                  uint64_t flags)
 
 {
        if (level != AMDGPU_VM_PTB) {
                flags |= AMDGPU_PDE_PTE;
                amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
+
+       } else if (params->adev->asic_type >= CHIP_VEGA10 &&
+                  !(flags & AMDGPU_PTE_VALID) &&
+                  !(flags & AMDGPU_PTE_PRT)) {
+
+               /* Workaround for fault priority problem on GMC9 */
+               flags |= AMDGPU_PTE_EXECUTABLE;
        }
 
        amdgpu_vm_update_func(params, bo, pe, addr, count, incr, flags);
@@ -1676,9 +1709,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
                        uint64_t upd_end = min(entry_end, frag_end);
                        unsigned nptes = (upd_end - frag_start) >> shift;
 
-                       amdgpu_vm_update_huge(params, pt, cursor.level,
-                                             pe_start, dst, nptes, incr,
-                                             flags | AMDGPU_PTE_FRAG(frag));
+                       amdgpu_vm_update_flags(params, pt, cursor.level,
+                                              pe_start, dst, nptes, incr,
+                                              flags | AMDGPU_PTE_FRAG(frag));
 
                        pe_start += nptes * 8;
                        dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
@@ -3006,7 +3039,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
        }
        DRM_DEBUG_DRIVER("VM update mode is %s\n",
                         vm->use_cpu_for_update ? "CPU" : "SDMA");
-       WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
+       WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
                  "CPU update of VM recommended only for large BAR system\n");
        vm->last_update = NULL;
 
@@ -3136,7 +3169,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, uns
        vm->pte_support_ats = pte_support_ats;
        DRM_DEBUG_DRIVER("VM update mode is %s\n",
                         vm->use_cpu_for_update ? "CPU" : "SDMA");
-       WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
+       WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
                  "CPU update of VM recommended only for large BAR system\n");
 
        if (vm->pasid) {
index e8dcfd59fc93353468aaada4c42e6ab4ca6d85a5..81ff8177f09208183c96818bfaff38d81b0af67b 100644 (file)
@@ -363,4 +363,6 @@ int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key)
 
 void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key);
 
+void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
+
 #endif
index 8a8bc60cb6b4d482e216a0a32522cf0c1f47d881..dac187454b3359cd38508f88319b25ebe8f21d45 100644 (file)
@@ -40,26 +40,40 @@ void *amdgpu_xgmi_hive_try_lock(struct amdgpu_hive_info *hive)
        return &hive->device_list;
 }
 
-struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
+struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int lock)
 {
        int i;
        struct amdgpu_hive_info *tmp;
 
        if (!adev->gmc.xgmi.hive_id)
                return NULL;
+
+       mutex_lock(&xgmi_mutex);
+
        for (i = 0 ; i < hive_count; ++i) {
                tmp = &xgmi_hives[i];
-               if (tmp->hive_id == adev->gmc.xgmi.hive_id)
+               if (tmp->hive_id == adev->gmc.xgmi.hive_id) {
+                       if (lock)
+                               mutex_lock(&tmp->hive_lock);
+                       mutex_unlock(&xgmi_mutex);
                        return tmp;
+               }
        }
-       if (i >= AMDGPU_MAX_XGMI_HIVE)
+       if (i >= AMDGPU_MAX_XGMI_HIVE) {
+               mutex_unlock(&xgmi_mutex);
                return NULL;
+       }
 
        /* initialize new hive if not exist */
        tmp = &xgmi_hives[hive_count++];
        tmp->hive_id = adev->gmc.xgmi.hive_id;
        INIT_LIST_HEAD(&tmp->device_list);
        mutex_init(&tmp->hive_lock);
+       mutex_init(&tmp->reset_lock);
+       if (lock)
+               mutex_lock(&tmp->hive_lock);
+
+       mutex_unlock(&xgmi_mutex);
 
        return tmp;
 }
@@ -111,10 +125,14 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
                return ret;
        }
 
-       mutex_lock(&xgmi_mutex);
-       hive = amdgpu_get_xgmi_hive(adev);
-       if (!hive)
+       hive = amdgpu_get_xgmi_hive(adev, 1);
+       if (!hive) {
+               ret = -EINVAL;
+               dev_err(adev->dev,
+                       "XGMI: node 0x%llx, can not matech hive 0x%llx in the hive list.\n",
+                       adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
                goto exit;
+       }
 
        hive_topology = &hive->topology_info;
 
@@ -142,8 +160,8 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
                        break;
        }
 
+       mutex_unlock(&hive->hive_lock);
 exit:
-       mutex_unlock(&xgmi_mutex);
        return ret;
 }
 
@@ -154,15 +172,14 @@ void amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
        if (!adev->gmc.xgmi.supported)
                return;
 
-       mutex_lock(&xgmi_mutex);
-
-       hive = amdgpu_get_xgmi_hive(adev);
+       hive = amdgpu_get_xgmi_hive(adev, 1);
        if (!hive)
-               goto exit;
+               return;
 
-       if (!(hive->number_devices--))
+       if (!(hive->number_devices--)) {
                mutex_destroy(&hive->hive_lock);
-
-exit:
-       mutex_unlock(&xgmi_mutex);
+               mutex_destroy(&hive->reset_lock);
+       } else {
+               mutex_unlock(&hive->hive_lock);
+       }
 }
index 6151eb9c8ad30bbcaf54eacbcd67b649a7b4fa5a..14bc606641590d5845f4dec5c4dcc453b658862b 100644 (file)
@@ -29,10 +29,11 @@ struct amdgpu_hive_info {
        struct list_head        device_list;
        struct psp_xgmi_topology_info   topology_info;
        int number_devices;
-       struct mutex hive_lock;
+       struct mutex hive_lock,
+                    reset_lock;
 };
 
-struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
+struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int lock);
 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
 int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
 void amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
index e9934de1b9cf8127eb2b770e4301d6ee90c98223..dd30f4e61a8cd97c73c06dc756177dbc33a79d52 100644 (file)
@@ -27,6 +27,8 @@
 #include <linux/slab.h>
 #include <asm/unaligned.h>
 
+#include <drm/drm_util.h>
+
 #define ATOM_DEBUG
 
 #include "atom.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
deleted file mode 100644 (file)
index 86e14c7..0000000
+++ /dev/null
@@ -1,6844 +0,0 @@
-/*
- * Copyright 2013 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include <linux/firmware.h>
-#include <drm/drmP.h>
-#include "amdgpu.h"
-#include "amdgpu_pm.h"
-#include "amdgpu_ucode.h"
-#include "cikd.h"
-#include "amdgpu_dpm.h"
-#include "ci_dpm.h"
-#include "gfx_v7_0.h"
-#include "atom.h"
-#include "amd_pcie.h"
-#include <linux/seq_file.h>
-
-#include "smu/smu_7_0_1_d.h"
-#include "smu/smu_7_0_1_sh_mask.h"
-
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
-#include "bif/bif_4_1_d.h"
-#include "bif/bif_4_1_sh_mask.h"
-
-#include "gca/gfx_7_2_d.h"
-#include "gca/gfx_7_2_sh_mask.h"
-
-#include "gmc/gmc_7_1_d.h"
-#include "gmc/gmc_7_1_sh_mask.h"
-
-MODULE_FIRMWARE("amdgpu/bonaire_smc.bin");
-MODULE_FIRMWARE("amdgpu/bonaire_k_smc.bin");
-MODULE_FIRMWARE("amdgpu/hawaii_smc.bin");
-MODULE_FIRMWARE("amdgpu/hawaii_k_smc.bin");
-
-#define MC_CG_ARB_FREQ_F0           0x0a
-#define MC_CG_ARB_FREQ_F1           0x0b
-#define MC_CG_ARB_FREQ_F2           0x0c
-#define MC_CG_ARB_FREQ_F3           0x0d
-
-#define SMC_RAM_END 0x40000
-
-#define VOLTAGE_SCALE               4
-#define VOLTAGE_VID_OFFSET_SCALE1    625
-#define VOLTAGE_VID_OFFSET_SCALE2    100
-
-static const struct amd_pm_funcs ci_dpm_funcs;
-
-static const struct ci_pt_defaults defaults_hawaii_xt =
-{
-       1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
-       { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
-       { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
-};
-
-static const struct ci_pt_defaults defaults_hawaii_pro =
-{
-       1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
-       { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
-       { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
-};
-
-static const struct ci_pt_defaults defaults_bonaire_xt =
-{
-       1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
-       { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
-       { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
-};
-
-#if 0
-static const struct ci_pt_defaults defaults_bonaire_pro =
-{
-       1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
-       { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
-       { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
-};
-#endif
-
-static const struct ci_pt_defaults defaults_saturn_xt =
-{
-       1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
-       { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
-       { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
-};
-
-#if 0
-static const struct ci_pt_defaults defaults_saturn_pro =
-{
-       1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
-       { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
-       { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
-};
-#endif
-
-static const struct ci_pt_config_reg didt_config_ci[] =
-{
-       { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-       {&nbs