drivers/irqchip/irq-gic-v3-its.c

   1 /*
   2  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/acpi.h>
  19 #include <linux/acpi_iort.h>
  20 #include <linux/bitmap.h>
  21 #include <linux/cpu.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-iommu.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/log2.h>
  27 #include <linux/mm.h>
  28 #include <linux/msi.h>
  29 #include <linux/of.h>
  30 #include <linux/of_address.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/of_pci.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/percpu.h>
  35 #include <linux/slab.h>
  36 #include <linux/syscore_ops.h>
  37
  38 #include <linux/irqchip.h>
  39 #include <linux/irqchip/arm-gic-v3.h>
  40 #include <linux/irqchip/arm-gic-v4.h>
  41
  42 #include <asm/cputype.h>
  43 #include <asm/exception.h>
  44
  45 #include "irq-gic-common.h"
  46
  47 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1ULL << 0)
  48 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375       (1ULL << 1)
  49 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144       (1ULL << 2)
  50 #define ITS_FLAGS_SAVE_SUSPEND_STATE            (1ULL << 3)
  51
  52 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
  53
  54 static u32 lpi_id_bits;
  55
  56 /*
  57  * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
  58  * deal with (one configuration byte per interrupt). PENDBASE has to
  59  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
  60  */
  61 #define LPI_NRBITS              lpi_id_bits
  62 #define LPI_PROPBASE_SZ         ALIGN(BIT(LPI_NRBITS), SZ_64K)
  63 #define LPI_PENDBASE_SZ         ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
  64
  65 #define LPI_PROP_DEFAULT_PRIO   0xa0
  66
  67 /*
  68  * Collection structure - just an ID, and a redistributor address to
  69  * ping. We use one per CPU as a bag of interrupts assigned to this
  70  * CPU.
  71  */
  72 struct its_collection {
  73         u64                     target_address;
  74         u16                     col_id;
  75 };
  76
  77 /*
  78  * The ITS_BASER structure - contains memory information, cached
  79  * value of BASER register configuration and ITS page size.
  80  */
  81 struct its_baser {
  82         void            *base;
  83         u64             val;
  84         u32             order;
  85         u32             psz;
  86 };
  87
  88 struct its_device;
  89
  90 /*
  91  * The ITS structure - contains most of the infrastructure, with the
  92  * top-level MSI domain, the command queue, the collections, and the
  93  * list of devices writing to it.
  94  */
  95 struct its_node {
  96         raw_spinlock_t          lock;
  97         struct list_head        entry;
  98         void __iomem            *base;
  99         phys_addr_t             phys_base;
 100         struct its_cmd_block    *cmd_base;
 101         struct its_cmd_block    *cmd_write;
 102         struct its_baser        tables[GITS_BASER_NR_REGS];
 103         struct its_collection   *collections;
 104         struct fwnode_handle    *fwnode_handle;
 105         u64                     (*get_msi_base)(struct its_device *its_dev);
 106         u64                     cbaser_save;
 107         u32                     ctlr_save;
 108         struct list_head        its_device_list;
 109         u64                     flags;
 110         unsigned long           list_nr;
 111         u32                     ite_size;
 112         u32                     device_ids;
 113         int                     numa_node;
 114         unsigned int            msi_domain_flags;
 115         u32                     pre_its_base; /* for Socionext Synquacer */
 116         bool                    is_v4;
 117         int                     vlpi_redist_offset;
 118 };
 119
 120 #define ITS_ITT_ALIGN           SZ_256
 121
 122 /* The maximum number of VPEID bits supported by VLPI commands */
 123 #define ITS_MAX_VPEID_BITS      (16)
 124 #define ITS_MAX_VPEID           (1 << (ITS_MAX_VPEID_BITS))
 125
 126 /* Convert page order to size in bytes */
 127 #define PAGE_ORDER_TO_SIZE(o)   (PAGE_SIZE << (o))
 128
 129 struct event_lpi_map {
 130         unsigned long           *lpi_map;
 131         u16                     *col_map;
 132         irq_hw_number_t         lpi_base;
 133         int                     nr_lpis;
 134         struct mutex            vlpi_lock;
 135         struct its_vm           *vm;
 136         struct its_vlpi_map     *vlpi_maps;
 137         int                     nr_vlpis;
 138 };
 139
 140 /*
 141  * The ITS view of a device - belongs to an ITS, owns an interrupt
 142  * translation table, and a list of interrupts.  If it some of its
 143  * LPIs are injected into a guest (GICv4), the event_map.vm field
 144  * indicates which one.
 145  */
 146 struct its_device {
 147         struct list_head        entry;
 148         struct its_node         *its;
 149         struct event_lpi_map    event_map;
 150         void                    *itt;
 151         u32                     nr_ites;
 152         u32                     device_id;
 153 };
 154
 155 static struct {
 156         raw_spinlock_t          lock;
 157         struct its_device       *dev;
 158         struct its_vpe          **vpes;
 159         int                     next_victim;
 160 } vpe_proxy;
 161
 162 static LIST_HEAD(its_nodes);
 163 static DEFINE_SPINLOCK(its_lock);
 164 static struct rdists *gic_rdists;
 165 static struct irq_domain *its_parent;
 166
 167 static unsigned long its_list_map;
 168 static u16 vmovp_seq_num;
 169 static DEFINE_RAW_SPINLOCK(vmovp_lock);
 170
 171 static DEFINE_IDA(its_vpeid_ida);
 172
 173 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
 174 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 175 #define gic_data_rdist_vlpi_base()      (gic_data_rdist_rd_base() + SZ_128K)
 176
 177 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
 178                                                u32 event)
 179 {
 180         struct its_node *its = its_dev->its;
 181
 182         return its->collections + its_dev->event_map.col_map[event];
 183 }
 184
 185 /*
 186  * ITS command descriptors - parameters to be encoded in a command
 187  * block.
 188  */
 189 struct its_cmd_desc {
 190         union {
 191                 struct {
 192                         struct its_device *dev;
 193                         u32 event_id;
 194                 } its_inv_cmd;
 195
 196                 struct {
 197                         struct its_device *dev;
 198                         u32 event_id;
 199                 } its_clear_cmd;
 200
 201                 struct {
 202                         struct its_device *dev;
 203                         u32 event_id;
 204                 } its_int_cmd;
 205
 206                 struct {
 207                         struct its_device *dev;
 208                         int valid;
 209                 } its_mapd_cmd;
 210
 211                 struct {
 212                         struct its_collection *col;
 213                         int valid;
 214                 } its_mapc_cmd;
 215
 216                 struct {
 217                         struct its_device *dev;
 218                         u32 phys_id;
 219                         u32 event_id;
 220                 } its_mapti_cmd;
 221
 222                 struct {
 223                         struct its_device *dev;
 224                         struct its_collection *col;
 225                         u32 event_id;
 226                 } its_movi_cmd;
 227
 228                 struct {
 229                         struct its_device *dev;
 230                         u32 event_id;
 231                 } its_discard_cmd;
 232
 233                 struct {
 234                         struct its_collection *col;
 235                 } its_invall_cmd;
 236
 237                 struct {
 238                         struct its_vpe *vpe;
 239                 } its_vinvall_cmd;
 240
 241                 struct {
 242                         struct its_vpe *vpe;
 243                         struct its_collection *col;
 244                         bool valid;
 245                 } its_vmapp_cmd;
 246
 247                 struct {
 248                         struct its_vpe *vpe;
 249                         struct its_device *dev;
 250                         u32 virt_id;
 251                         u32 event_id;
 252                         bool db_enabled;
 253                 } its_vmapti_cmd;
 254
 255                 struct {
 256                         struct its_vpe *vpe;
 257                         struct its_device *dev;
 258                         u32 event_id;
 259                         bool db_enabled;
 260                 } its_vmovi_cmd;
 261
 262                 struct {
 263                         struct its_vpe *vpe;
 264                         struct its_collection *col;
 265                         u16 seq_num;
 266                         u16 its_list;
 267                 } its_vmovp_cmd;
 268         };
 269 };
 270
 271 /*
 272  * The ITS command block, which is what the ITS actually parses.
 273  */
 274 struct its_cmd_block {
 275         u64     raw_cmd[4];
 276 };
 277
 278 #define ITS_CMD_QUEUE_SZ                SZ_64K
 279 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
 280
 281 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
 282                                                     struct its_cmd_block *,
 283                                                     struct its_cmd_desc *);
 284
 285 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
 286                                               struct its_cmd_block *,
 287                                               struct its_cmd_desc *);
 288
 289 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
 290 {
 291         u64 mask = GENMASK_ULL(h, l);
 292         *raw_cmd &= ~mask;
 293         *raw_cmd |= (val << l) & mask;
 294 }
 295
 296 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
 297 {
 298         its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
 299 }
 300
 301 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
 302 {
 303         its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
 304 }
 305
 306 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
 307 {
 308         its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
 309 }
 310
 311 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
 312 {
 313         its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
 314 }
 315
 316 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
 317 {
 318         its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
 319 }
 320
 321 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
 322 {
 323         its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
 324 }
 325
 326 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
 327 {
 328         its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
 329 }
 330
 331 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
 332 {
 333         its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
 334 }
 335
 336 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
 337 {
 338         its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
 339 }
 340
 341 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
 342 {
 343         its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
 344 }
 345
 346 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
 347 {
 348         its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
 349 }
 350
 351 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
 352 {
 353         its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
 354 }
 355
 356 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
 357 {
 358         its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
 359 }
 360
 361 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
 362 {
 363         its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
 364 }
 365
 366 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
 367 {
 368         its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
 369 }
 370
 371 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
 372 {
 373         its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
 374 }
 375
 376 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
 377 {
 378         its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
 379 }
 380
 381 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
 382 {
 383         /* Let's fixup BE commands */
 384         cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
 385         cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
 386         cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
 387         cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
 388 }
 389
 390 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
 391                                                  struct its_cmd_block *cmd,
 392                                                  struct its_cmd_desc *desc)
 393 {
 394         unsigned long itt_addr;
 395         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
 396
 397         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
 398         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
 399
 400         its_encode_cmd(cmd, GITS_CMD_MAPD);
 401         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
 402         its_encode_size(cmd, size - 1);
 403         its_encode_itt(cmd, itt_addr);
 404         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
 405
 406         its_fixup_cmd(cmd);
 407
 408         return NULL;
 409 }
 410
 411 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
 412                                                  struct its_cmd_block *cmd,
 413                                                  struct its_cmd_desc *desc)
 414 {
 415         its_encode_cmd(cmd, GITS_CMD_MAPC);
 416         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 417         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
 418         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
 419
 420         its_fixup_cmd(cmd);
 421
 422         return desc->its_mapc_cmd.col;
 423 }
 424
 425 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
 426                                                   struct its_cmd_block *cmd,
 427                                                   struct its_cmd_desc *desc)
 428 {
 429         struct its_collection *col;
 430
 431         col = dev_event_to_col(desc->its_mapti_cmd.dev,
 432                                desc->its_mapti_cmd.event_id);
 433
 434         its_encode_cmd(cmd, GITS_CMD_MAPTI);
 435         its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
 436         its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
 437         its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
 438         its_encode_collection(cmd, col->col_id);
 439
 440         its_fixup_cmd(cmd);
 441
 442         return col;
 443 }
 444
 445 static struct its_collection *its_build_movi_cmd(struct its_node *its,
 446                                                  struct its_cmd_block *cmd,
 447                                                  struct its_cmd_desc *desc)
 448 {
 449         struct its_collection *col;
 450
 451         col = dev_event_to_col(desc->its_movi_cmd.dev,
 452                                desc->its_movi_cmd.event_id);
 453
 454         its_encode_cmd(cmd, GITS_CMD_MOVI);
 455         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
 456         its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
 457         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
 458
 459         its_fixup_cmd(cmd);
 460
 461         return col;
 462 }
 463
 464 static struct its_collection *its_build_discard_cmd(struct its_node *its,
 465                                                     struct its_cmd_block *cmd,
 466                                                     struct its_cmd_desc *desc)
 467 {
 468         struct its_collection *col;
 469
 470         col = dev_event_to_col(desc->its_discard_cmd.dev,
 471                                desc->its_discard_cmd.event_id);
 472
 473         its_encode_cmd(cmd, GITS_CMD_DISCARD);
 474         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
 475         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
 476
 477         its_fixup_cmd(cmd);
 478
 479         return col;
 480 }
 481
 482 static struct its_collection *its_build_inv_cmd(struct its_node *its,
 483                                                 struct its_cmd_block *cmd,
 484                                                 struct its_cmd_desc *desc)
 485 {
 486         struct its_collection *col;
 487
 488         col = dev_event_to_col(desc->its_inv_cmd.dev,
 489                                desc->its_inv_cmd.event_id);
 490
 491         its_encode_cmd(cmd, GITS_CMD_INV);
 492         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 493         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 494
 495         its_fixup_cmd(cmd);
 496
 497         return col;
 498 }
 499
 500 static struct its_collection *its_build_int_cmd(struct its_node *its,
 501                                                 struct its_cmd_block *cmd,
 502                                                 struct its_cmd_desc *desc)
 503 {
 504         struct its_collection *col;
 505
 506         col = dev_event_to_col(desc->its_int_cmd.dev,
 507                                desc->its_int_cmd.event_id);
 508
 509         its_encode_cmd(cmd, GITS_CMD_INT);
 510         its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
 511         its_encode_event_id(cmd, desc->its_int_cmd.event_id);
 512
 513         its_fixup_cmd(cmd);
 514
 515         return col;
 516 }
 517
 518 static struct its_collection *its_build_clear_cmd(struct its_node *its,
 519                                                   struct its_cmd_block *cmd,
 520                                                   struct its_cmd_desc *desc)
 521 {
 522         struct its_collection *col;
 523
 524         col = dev_event_to_col(desc->its_clear_cmd.dev,
 525                                desc->its_clear_cmd.event_id);
 526
 527         its_encode_cmd(cmd, GITS_CMD_CLEAR);
 528         its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
 529         its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
 530
 531         its_fixup_cmd(cmd);
 532
 533         return col;
 534 }
 535
 536 static struct its_collection *its_build_invall_cmd(struct its_node *its,
 537                                                    struct its_cmd_block *cmd,
 538                                                    struct its_cmd_desc *desc)
 539 {
 540         its_encode_cmd(cmd, GITS_CMD_INVALL);
 541         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 542
 543         its_fixup_cmd(cmd);
 544
 545         return NULL;
 546 }
 547
 548 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
 549                                              struct its_cmd_block *cmd,
 550                                              struct its_cmd_desc *desc)
 551 {
 552         its_encode_cmd(cmd, GITS_CMD_VINVALL);
 553         its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
 554
 555         its_fixup_cmd(cmd);
 556
 557         return desc->its_vinvall_cmd.vpe;
 558 }
 559
 560 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
 561                                            struct its_cmd_block *cmd,
 562                                            struct its_cmd_desc *desc)
 563 {
 564         unsigned long vpt_addr;
 565         u64 target;
 566
 567         vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
 568         target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
 569
 570         its_encode_cmd(cmd, GITS_CMD_VMAPP);
 571         its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
 572         its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
 573         its_encode_target(cmd, target);
 574         its_encode_vpt_addr(cmd, vpt_addr);
 575         its_encode_vpt_size(cmd, LPI_NRBITS - 1);
 576
 577         its_fixup_cmd(cmd);
 578
 579         return desc->its_vmapp_cmd.vpe;
 580 }
 581
 582 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
 583                                             struct its_cmd_block *cmd,
 584                                             struct its_cmd_desc *desc)
 585 {
 586         u32 db;
 587
 588         if (desc->its_vmapti_cmd.db_enabled)
 589                 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
 590         else
 591                 db = 1023;
 592
 593         its_encode_cmd(cmd, GITS_CMD_VMAPTI);
 594         its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
 595         its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
 596         its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
 597         its_encode_db_phys_id(cmd, db);
 598         its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
 599
 600         its_fixup_cmd(cmd);
 601
 602         return desc->its_vmapti_cmd.vpe;
 603 }
 604
 605 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
 606                                            struct its_cmd_block *cmd,
 607                                            struct its_cmd_desc *desc)
 608 {
 609         u32 db;
 610
 611         if (desc->its_vmovi_cmd.db_enabled)
 612                 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
 613         else
 614                 db = 1023;
 615
 616         its_encode_cmd(cmd, GITS_CMD_VMOVI);
 617         its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
 618         its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
 619         its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
 620         its_encode_db_phys_id(cmd, db);
 621         its_encode_db_valid(cmd, true);
 622
 623         its_fixup_cmd(cmd);
 624
 625         return desc->its_vmovi_cmd.vpe;
 626 }
 627
 628 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
 629                                            struct its_cmd_block *cmd,
 630                                            struct its_cmd_desc *desc)
 631 {
 632         u64 target;
 633
 634         target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
 635         its_encode_cmd(cmd, GITS_CMD_VMOVP);
 636         its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
 637         its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
 638         its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
 639         its_encode_target(cmd, target);
 640
 641         its_fixup_cmd(cmd);
 642
 643         return desc->its_vmovp_cmd.vpe;
 644 }
 645
 646 static u64 its_cmd_ptr_to_offset(struct its_node *its,
 647                                  struct its_cmd_block *ptr)
 648 {
 649         return (ptr - its->cmd_base) * sizeof(*ptr);
 650 }
 651
 652 static int its_queue_full(struct its_node *its)
 653 {
 654         int widx;
 655         int ridx;
 656
 657         widx = its->cmd_write - its->cmd_base;
 658         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
 659
 660         /* This is incredibly unlikely to happen, unless the ITS locks up. */
 661         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
 662                 return 1;
 663
 664         return 0;
 665 }
 666
 667 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
 668 {
 669         struct its_cmd_block *cmd;
 670         u32 count = 1000000;    /* 1s! */
 671
 672         while (its_queue_full(its)) {
 673                 count--;
 674                 if (!count) {
 675                         pr_err_ratelimited("ITS queue not draining\n");
 676                         return NULL;
 677                 }
 678                 cpu_relax();
 679                 udelay(1);
 680         }
 681
 682         cmd = its->cmd_write++;
 683
 684         /* Handle queue wrapping */
 685         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
 686                 its->cmd_write = its->cmd_base;
 687
 688         /* Clear command  */
 689         cmd->raw_cmd[0] = 0;
 690         cmd->raw_cmd[1] = 0;
 691         cmd->raw_cmd[2] = 0;
 692         cmd->raw_cmd[3] = 0;
 693
 694         return cmd;
 695 }
 696
 697 static struct its_cmd_block *its_post_commands(struct its_node *its)
 698 {
 699         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
 700
 701         writel_relaxed(wr, its->base + GITS_CWRITER);
 702
 703         return its->cmd_write;
 704 }
 705
 706 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
 707 {
 708         /*
 709          * Make sure the commands written to memory are observable by
 710          * the ITS.
 711          */
 712         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
 713                 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
 714         else
 715                 dsb(ishst);
 716 }
 717
 718 static int its_wait_for_range_completion(struct its_node *its,
 719                                          struct its_cmd_block *from,
 720                                          struct its_cmd_block *to)
 721 {
 722         u64 rd_idx, from_idx, to_idx;
 723         u32 count = 1000000;    /* 1s! */
 724
 725         from_idx = its_cmd_ptr_to_offset(its, from);
 726         to_idx = its_cmd_ptr_to_offset(its, to);
 727
 728         while (1) {
 729                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
 730
 731                 /* Direct case */
 732                 if (from_idx < to_idx && rd_idx >= to_idx)
 733                         break;
 734
 735                 /* Wrapped case */
 736                 if (from_idx >= to_idx && rd_idx >= to_idx && rd_idx < from_idx)
 737                         break;
 738
 739                 count--;
 740                 if (!count) {
 741                         pr_err_ratelimited("ITS queue timeout (%llu %llu %llu)\n",
 742                                            from_idx, to_idx, rd_idx);
 743                         return -1;
 744                 }
 745                 cpu_relax();
 746                 udelay(1);
 747         }
 748
 749         return 0;
 750 }
 751
 752 /* Warning, macro hell follows */
 753 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn)       \
 754 void name(struct its_node *its,                                         \
 755           buildtype builder,                                            \
 756           struct its_cmd_desc *desc)                                    \
 757 {                                                                       \
 758         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;                \
 759         synctype *sync_obj;                                             \
 760         unsigned long flags;                                            \
 761                                                                         \
 762         raw_spin_lock_irqsave(&its->lock, flags);                       \
 763                                                                         \
 764         cmd = its_allocate_entry(its);                                  \
 765         if (!cmd) {             /* We're soooooo screewed... */         \
 766                 raw_spin_unlock_irqrestore(&its->lock, flags);          \
 767                 return;                                                 \
 768         }                                                               \
 769         sync_obj = builder(its, cmd, desc);                             \
 770         its_flush_cmd(its, cmd);                                        \
 771                                                                         \
 772         if (sync_obj) {                                                 \
 773                 sync_cmd = its_allocate_entry(its);                     \
 774                 if (!sync_cmd)                                          \
 775                         goto post;                                      \
 776                                                                         \
 777                 buildfn(its, sync_cmd, sync_obj);                       \
 778                 its_flush_cmd(its, sync_cmd);                           \
 779         }                                                               \
 780                                                                         \
 781 post:                                                                   \
 782         next_cmd = its_post_commands(its);                              \
 783         raw_spin_unlock_irqrestore(&its->lock, flags);                  \
 784                                                                         \
 785         if (its_wait_for_range_completion(its, cmd, next_cmd))          \
 786                 pr_err_ratelimited("ITS cmd %ps failed\n", builder);    \
 787 }
 788
 789 static void its_build_sync_cmd(struct its_node *its,
 790                                struct its_cmd_block *sync_cmd,
 791                                struct its_collection *sync_col)
 792 {
 793         its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
 794         its_encode_target(sync_cmd, sync_col->target_address);
 795
 796         its_fixup_cmd(sync_cmd);
 797 }
 798
 799 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
 800                              struct its_collection, its_build_sync_cmd)
 801
 802 static void its_build_vsync_cmd(struct its_node *its,
 803                                 struct its_cmd_block *sync_cmd,
 804                                 struct its_vpe *sync_vpe)
 805 {
 806         its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
 807         its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
 808
 809         its_fixup_cmd(sync_cmd);
 810 }
 811
 812 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
 813                              struct its_vpe, its_build_vsync_cmd)
 814
 815 static void its_send_int(struct its_device *dev, u32 event_id)
 816 {
 817         struct its_cmd_desc desc;
 818
 819         desc.its_int_cmd.dev = dev;
 820         desc.its_int_cmd.event_id = event_id;
 821
 822         its_send_single_command(dev->its, its_build_int_cmd, &desc);
 823 }
 824
 825 static void its_send_clear(struct its_device *dev, u32 event_id)
 826 {
 827         struct its_cmd_desc desc;
 828
 829         desc.its_clear_cmd.dev = dev;
 830         desc.its_clear_cmd.event_id = event_id;
 831
 832         its_send_single_command(dev->its, its_build_clear_cmd, &desc);
 833 }
 834
 835 static void its_send_inv(struct its_device *dev, u32 event_id)
 836 {
 837         struct its_cmd_desc desc;
 838
 839         desc.its_inv_cmd.dev = dev;
 840         desc.its_inv_cmd.event_id = event_id;
 841
 842         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
 843 }
 844
 845 static void its_send_mapd(struct its_device *dev, int valid)
 846 {
 847         struct its_cmd_desc desc;
 848
 849         desc.its_mapd_cmd.dev = dev;
 850         desc.its_mapd_cmd.valid = !!valid;
 851
 852         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
 853 }
 854
 855 static void its_send_mapc(struct its_node *its, struct its_collection *col,
 856                           int valid)
 857 {
 858         struct its_cmd_desc desc;
 859
 860         desc.its_mapc_cmd.col = col;
 861         desc.its_mapc_cmd.valid = !!valid;
 862
 863         its_send_single_command(its, its_build_mapc_cmd, &desc);
 864 }
 865
 866 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
 867 {
 868         struct its_cmd_desc desc;
 869
 870         desc.its_mapti_cmd.dev = dev;
 871         desc.its_mapti_cmd.phys_id = irq_id;
 872         desc.its_mapti_cmd.event_id = id;
 873
 874         its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
 875 }
 876
 877 static void its_send_movi(struct its_device *dev,
 878                           struct its_collection *col, u32 id)
 879 {
 880         struct its_cmd_desc desc;
 881
 882         desc.its_movi_cmd.dev = dev;
 883         desc.its_movi_cmd.col = col;
 884         desc.its_movi_cmd.event_id = id;
 885
 886         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
 887 }
 888
 889 static void its_send_discard(struct its_device *dev, u32 id)
 890 {
 891         struct its_cmd_desc desc;
 892
 893         desc.its_discard_cmd.dev = dev;
 894         desc.its_discard_cmd.event_id = id;
 895
 896         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
 897 }
 898
 899 static void its_send_invall(struct its_node *its, struct its_collection *col)
 900 {
 901         struct its_cmd_desc desc;
 902
 903         desc.its_invall_cmd.col = col;
 904
 905         its_send_single_command(its, its_build_invall_cmd, &desc);
 906 }
 907
 908 static void its_send_vmapti(struct its_device *dev, u32 id)
 909 {
 910         struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
 911         struct its_cmd_desc desc;
 912
 913         desc.its_vmapti_cmd.vpe = map->vpe;
 914         desc.its_vmapti_cmd.dev = dev;
 915         desc.its_vmapti_cmd.virt_id = map->vintid;
 916         desc.its_vmapti_cmd.event_id = id;
 917         desc.its_vmapti_cmd.db_enabled = map->db_enabled;
 918
 919         its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
 920 }
 921
 922 static void its_send_vmovi(struct its_device *dev, u32 id)
 923 {
 924         struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
 925         struct its_cmd_desc desc;
 926
 927         desc.its_vmovi_cmd.vpe = map->vpe;
 928         desc.its_vmovi_cmd.dev = dev;
 929         desc.its_vmovi_cmd.event_id = id;
 930         desc.its_vmovi_cmd.db_enabled = map->db_enabled;
 931
 932         its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
 933 }
 934
 935 static void its_send_vmapp(struct its_node *its,
 936                            struct its_vpe *vpe, bool valid)
 937 {
 938         struct its_cmd_desc desc;
 939
 940         desc.its_vmapp_cmd.vpe = vpe;
 941         desc.its_vmapp_cmd.valid = valid;
 942         desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
 943
 944         its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
 945 }
 946
 947 static void its_send_vmovp(struct its_vpe *vpe)
 948 {
 949         struct its_cmd_desc desc;
 950         struct its_node *its;
 951         unsigned long flags;
 952         int col_id = vpe->col_idx;
 953
 954         desc.its_vmovp_cmd.vpe = vpe;
 955         desc.its_vmovp_cmd.its_list = (u16)its_list_map;
 956
 957         if (!its_list_map) {
 958                 its = list_first_entry(&its_nodes, struct its_node, entry);
 959                 desc.its_vmovp_cmd.seq_num = 0;
 960                 desc.its_vmovp_cmd.col = &its->collections[col_id];
 961                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
 962                 return;
 963         }
 964
 965         /*
 966          * Yet another marvel of the architecture. If using the
 967          * its_list "feature", we need to make sure that all ITSs
 968          * receive all VMOVP commands in the same order. The only way
 969          * to guarantee this is to make vmovp a serialization point.
 970          *
 971          * Wall <-- Head.
 972          */
 973         raw_spin_lock_irqsave(&vmovp_lock, flags);
 974
 975         desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
 976
 977         /* Emit VMOVPs */
 978         list_for_each_entry(its, &its_nodes, entry) {
 979                 if (!its->is_v4)
 980                         continue;
 981
 982                 if (!vpe->its_vm->vlpi_count[its->list_nr])
 983                         continue;
 984
 985                 desc.its_vmovp_cmd.col = &its->collections[col_id];
 986                 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
 987         }
 988
 989         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
 990 }
 991
 992 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
 993 {
 994         struct its_cmd_desc desc;
 995
 996         desc.its_vinvall_cmd.vpe = vpe;
 997         its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
 998 }
 999
1000 /*
1001  * irqchip functions - assumes MSI, mostly.
1002  */
1003
1004 static inline u32 its_get_event_id(struct irq_data *d)
1005 {
1006         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1007         return d->hwirq - its_dev->event_map.lpi_base;
1008 }
1009
1010 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1011 {
1012         irq_hw_number_t hwirq;
1013         struct page *prop_page;
1014         u8 *cfg;
1015
1016         if (irqd_is_forwarded_to_vcpu(d)) {
1017                 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1018                 u32 event = its_get_event_id(d);
1019                 struct its_vlpi_map *map;
1020
1021                 prop_page = its_dev->event_map.vm->vprop_page;
1022                 map = &its_dev->event_map.vlpi_maps[event];
1023                 hwirq = map->vintid;
1024
1025                 /* Remember the updated property */
1026                 map->properties &= ~clr;
1027                 map->properties |= set | LPI_PROP_GROUP1;
1028         } else {
1029                 prop_page = gic_rdists->prop_page;
1030                 hwirq = d->hwirq;
1031         }
1032
1033         cfg = page_address(prop_page) + hwirq - 8192;
1034         *cfg &= ~clr;
1035         *cfg |= set | LPI_PROP_GROUP1;
1036
1037         /*
1038          * Make the above write visible to the redistributors.
1039          * And yes, we're flushing exactly: One. Single. Byte.
1040          * Humpf...
1041          */
1042         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1043                 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1044         else
1045                 dsb(ishst);
1046 }
1047
1048 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1049 {
1050         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1051
1052         lpi_write_config(d, clr, set);
1053         its_send_inv(its_dev, its_get_event_id(d));
1054 }
1055
1056 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1057 {
1058         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1059         u32 event = its_get_event_id(d);
1060
1061         if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1062                 return;
1063
1064         its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1065
1066         /*
1067          * More fun with the architecture:
1068          *
1069          * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1070          * value or to 1023, depending on the enable bit. But that
1071          * would be issueing a mapping for an /existing/ DevID+EventID
1072          * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1073          * to the /same/ vPE, using this opportunity to adjust the
1074          * doorbell. Mouahahahaha. We loves it, Precious.
1075          */
1076         its_send_vmovi(its_dev, event);
1077 }
1078
1079 static void its_mask_irq(struct irq_data *d)
1080 {
1081         if (irqd_is_forwarded_to_vcpu(d))
1082                 its_vlpi_set_doorbell(d, false);
1083
1084         lpi_update_config(d, LPI_PROP_ENABLED, 0);
1085 }
1086
1087 static void its_unmask_irq(struct irq_data *d)
1088 {
1089         if (irqd_is_forwarded_to_vcpu(d))
1090                 its_vlpi_set_doorbell(d, true);
1091
1092         lpi_update_config(d, 0, LPI_PROP_ENABLED);
1093 }
1094
1095 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1096                             bool force)
1097 {
1098         unsigned int cpu;
1099         const struct cpumask *cpu_mask = cpu_online_mask;
1100         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1101         struct its_collection *target_col;
1102         u32 id = its_get_event_id(d);
1103
1104         /* A forwarded interrupt should use irq_set_vcpu_affinity */
1105         if (irqd_is_forwarded_to_vcpu(d))
1106                 return -EINVAL;
1107
1108        /* lpi cannot be routed to a redistributor that is on a foreign node */
1109         if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1110                 if (its_dev->its->numa_node >= 0) {
1111                         cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1112                         if (!cpumask_intersects(mask_val, cpu_mask))
1113                                 return -EINVAL;
1114                 }
1115         }
1116
1117         cpu = cpumask_any_and(mask_val, cpu_mask);
1118
1119         if (cpu >= nr_cpu_ids)
1120                 return -EINVAL;
1121
1122         /* don't set the affinity when the target cpu is same as current one */
1123         if (cpu != its_dev->event_map.col_map[id]) {
1124                 target_col = &its_dev->its->collections[cpu];
1125                 its_send_movi(its_dev, target_col, id);
1126                 its_dev->event_map.col_map[id] = cpu;
1127                 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1128         }
1129
1130         return IRQ_SET_MASK_OK_DONE;
1131 }
1132
1133 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1134 {
1135         struct its_node *its = its_dev->its;
1136
1137         return its->phys_base + GITS_TRANSLATER;
1138 }
1139
1140 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1141 {
1142         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1143         struct its_node *its;
1144         u64 addr;
1145
1146         its = its_dev->its;
1147         addr = its->get_msi_base(its_dev);
1148
1149         msg->address_lo         = lower_32_bits(addr);
1150         msg->address_hi         = upper_32_bits(addr);
1151         msg->data               = its_get_event_id(d);
1152
1153         iommu_dma_map_msi_msg(d->irq, msg);
1154 }
1155
1156 static int its_irq_set_irqchip_state(struct irq_data *d,
1157                                      enum irqchip_irq_state which,
1158                                      bool state)
1159 {
1160         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1161         u32 event = its_get_event_id(d);
1162
1163         if (which != IRQCHIP_STATE_PENDING)
1164                 return -EINVAL;
1165
1166         if (state)
1167                 its_send_int(its_dev, event);
1168         else
1169                 its_send_clear(its_dev, event);
1170
1171         return 0;
1172 }
1173
1174 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1175 {
1176         unsigned long flags;
1177
1178         /* Not using the ITS list? Everything is always mapped. */
1179         if (!its_list_map)
1180                 return;
1181
1182         raw_spin_lock_irqsave(&vmovp_lock, flags);
1183
1184         /*
1185          * If the VM wasn't mapped yet, iterate over the vpes and get
1186          * them mapped now.
1187          */
1188         vm->vlpi_count[its->list_nr]++;
1189
1190         if (vm->vlpi_count[its->list_nr] == 1) {
1191                 int i;
1192
1193                 for (i = 0; i < vm->nr_vpes; i++) {
1194                         struct its_vpe *vpe = vm->vpes[i];
1195                         struct irq_data *d = irq_get_irq_data(vpe->irq);
1196
1197                         /* Map the VPE to the first possible CPU */
1198                         vpe->col_idx = cpumask_first(cpu_online_mask);
1199                         its_send_vmapp(its, vpe, true);
1200                         its_send_vinvall(its, vpe);
1201                         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1202                 }
1203         }
1204
1205         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1206 }
1207
1208 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1209 {
1210         unsigned long flags;
1211
1212         /* Not using the ITS list? Everything is always mapped. */
1213         if (!its_list_map)
1214                 return;
1215
1216         raw_spin_lock_irqsave(&vmovp_lock, flags);
1217
1218         if (!--vm->vlpi_count[its->list_nr]) {
1219                 int i;
1220
1221                 for (i = 0; i < vm->nr_vpes; i++)
1222                         its_send_vmapp(its, vm->vpes[i], false);
1223         }
1224
1225         raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1226 }
1227
1228 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1229 {
1230         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1231         u32 event = its_get_event_id(d);
1232         int ret = 0;
1233
1234         if (!info->map)
1235                 return -EINVAL;
1236
1237         mutex_lock(&its_dev->event_map.vlpi_lock);
1238
1239         if (!its_dev->event_map.vm) {
1240                 struct its_vlpi_map *maps;
1241
1242                 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1243                                GFP_KERNEL);
1244                 if (!maps) {
1245                         ret = -ENOMEM;
1246                         goto out;
1247                 }
1248
1249                 its_dev->event_map.vm = info->map->vm;
1250                 its_dev->event_map.vlpi_maps = maps;
1251         } else if (its_dev->event_map.vm != info->map->vm) {
1252                 ret = -EINVAL;
1253                 goto out;
1254         }
1255
1256         /* Get our private copy of the mapping information */
1257         its_dev->event_map.vlpi_maps[event] = *info->map;
1258
1259         if (irqd_is_forwarded_to_vcpu(d)) {
1260                 /* Already mapped, move it around */
1261                 its_send_vmovi(its_dev, event);
1262         } else {
1263                 /* Ensure all the VPEs are mapped on this ITS */
1264                 its_map_vm(its_dev->its, info->map->vm);
1265
1266                 /*
1267                  * Flag the interrupt as forwarded so that we can
1268                  * start poking the virtual property table.
1269                  */
1270                 irqd_set_forwarded_to_vcpu(d);
1271
1272                 /* Write out the property to the prop table */
1273                 lpi_write_config(d, 0xff, info->map->properties);
1274
1275                 /* Drop the physical mapping */
1276                 its_send_discard(its_dev, event);
1277
1278                 /* and install the virtual one */
1279                 its_send_vmapti(its_dev, event);
1280
1281                 /* Increment the number of VLPIs */
1282                 its_dev->event_map.nr_vlpis++;
1283         }
1284
1285 out:
1286         mutex_unlock(&its_dev->event_map.vlpi_lock);
1287         return ret;
1288 }
1289
1290 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1291 {
1292         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1293         u32 event = its_get_event_id(d);
1294         int ret = 0;
1295
1296         mutex_lock(&its_dev->event_map.vlpi_lock);
1297
1298         if (!its_dev->event_map.vm ||
1299             !its_dev->event_map.vlpi_maps[event].vm) {
1300                 ret = -EINVAL;
1301                 goto out;
1302         }
1303
1304         /* Copy our mapping information to the incoming request */
1305         *info->map = its_dev->event_map.vlpi_maps[event];
1306
1307 out:
1308         mutex_unlock(&its_dev->event_map.vlpi_lock);
1309         return ret;
1310 }
1311
1312 static int its_vlpi_unmap(struct irq_data *d)
1313 {
1314         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1315         u32 event = its_get_event_id(d);
1316         int ret = 0;
1317
1318         mutex_lock(&its_dev->event_map.vlpi_lock);
1319
1320         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1321                 ret = -EINVAL;
1322                 goto out;
1323         }
1324
1325         /* Drop the virtual mapping */
1326         its_send_discard(its_dev, event);
1327
1328         /* and restore the physical one */
1329         irqd_clr_forwarded_to_vcpu(d);
1330         its_send_mapti(its_dev, d->hwirq, event);
1331         lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1332                                     LPI_PROP_ENABLED |
1333                                     LPI_PROP_GROUP1));
1334
1335         /* Potentially unmap the VM from this ITS */
1336         its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1337
1338         /*
1339          * Drop the refcount and make the device available again if
1340          * this was the last VLPI.
1341          */
1342         if (!--its_dev->event_map.nr_vlpis) {
1343                 its_dev->event_map.vm = NULL;
1344                 kfree(its_dev->event_map.vlpi_maps);
1345         }
1346
1347 out:
1348         mutex_unlock(&its_dev->event_map.vlpi_lock);
1349         return ret;
1350 }
1351
1352 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1353 {
1354         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1355
1356         if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1357                 return -EINVAL;
1358
1359         if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1360                 lpi_update_config(d, 0xff, info->config);
1361         else
1362                 lpi_write_config(d, 0xff, info->config);
1363         its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1364
1365         return 0;
1366 }
1367
1368 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1369 {
1370         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1371         struct its_cmd_info *info = vcpu_info;
1372
1373         /* Need a v4 ITS */
1374         if (!its_dev->its->is_v4)
1375                 return -EINVAL;
1376
1377         /* Unmap request? */
1378         if (!info)
1379                 return its_vlpi_unmap(d);
1380
1381         switch (info->cmd_type) {
1382         case MAP_VLPI:
1383                 return its_vlpi_map(d, info);
1384
1385         case GET_VLPI:
1386                 return its_vlpi_get(d, info);
1387
1388         case PROP_UPDATE_VLPI:
1389         case PROP_UPDATE_AND_INV_VLPI:
1390                 return its_vlpi_prop_update(d, info);
1391
1392         default:
1393                 return -EINVAL;
1394         }
1395 }
1396
1397 static struct irq_chip its_irq_chip = {
1398         .name                   = "ITS",
1399         .irq_mask               = its_mask_irq,
1400         .irq_unmask             = its_unmask_irq,
1401         .irq_eoi                = irq_chip_eoi_parent,
1402         .irq_set_affinity       = its_set_affinity,
1403         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
1404         .irq_set_irqchip_state  = its_irq_set_irqchip_state,
1405         .irq_set_vcpu_affinity  = its_irq_set_vcpu_affinity,
1406 };
1407
1408 /*
1409  * How we allocate LPIs:
1410  *
1411  * The GIC has id_bits bits for interrupt identifiers. From there, we
1412  * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
1413  * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
1414  * bits to the right.
1415  *
1416  * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
1417  */
1418 #define IRQS_PER_CHUNK_SHIFT    5
1419 #define IRQS_PER_CHUNK          (1UL << IRQS_PER_CHUNK_SHIFT)
1420 #define ITS_MAX_LPI_NRBITS      16 /* 64K LPIs */
1421
1422 static unsigned long *lpi_bitmap;
1423 static u32 lpi_chunks;
1424 static DEFINE_SPINLOCK(lpi_lock);
1425
1426 static int its_lpi_to_chunk(int lpi)
1427 {
1428         return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
1429 }
1430
1431 static int its_chunk_to_lpi(int chunk)
1432 {
1433         return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
1434 }
1435
1436 static int __init its_lpi_init(u32 id_bits)
1437 {
1438         lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
1439
1440         lpi_bitmap = kcalloc(BITS_TO_LONGS(lpi_chunks), sizeof(long),
1441                              GFP_KERNEL);
1442         if (!lpi_bitmap) {
1443                 lpi_chunks = 0;
1444                 return -ENOMEM;
1445         }
1446
1447         pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
1448         return 0;
1449 }
1450
1451 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
1452 {
1453         unsigned long *bitmap = NULL;
1454         int chunk_id;
1455         int nr_chunks;
1456         int i;
1457
1458         nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
1459
1460         spin_lock(&lpi_lock);
1461
1462         do {
1463                 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
1464                                                       0, nr_chunks, 0);
1465                 if (chunk_id < lpi_chunks)
1466                         break;
1467
1468                 nr_chunks--;
1469         } while (nr_chunks > 0);
1470
1471         if (!nr_chunks)
1472                 goto out;
1473
1474         bitmap = kcalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK),
1475                          sizeof(long),
1476                          GFP_ATOMIC);
1477         if (!bitmap)
1478                 goto out;
1479
1480         for (i = 0; i < nr_chunks; i++)
1481                 set_bit(chunk_id + i, lpi_bitmap);
1482
1483         *base = its_chunk_to_lpi(chunk_id);
1484         *nr_ids = nr_chunks * IRQS_PER_CHUNK;
1485
1486 out:
1487         spin_unlock(&lpi_lock);
1488
1489         if (!bitmap)
1490                 *base = *nr_ids = 0;
1491
1492         return bitmap;
1493 }
1494
1495 static void its_lpi_free_chunks(unsigned long *bitmap, int base, int nr_ids)
1496 {
1497         int lpi;
1498
1499         spin_lock(&lpi_lock);
1500
1501         for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
1502                 int chunk = its_lpi_to_chunk(lpi);
1503
1504                 BUG_ON(chunk > lpi_chunks);
1505                 if (test_bit(chunk, lpi_bitmap)) {
1506                         clear_bit(chunk, lpi_bitmap);
1507                 } else {
1508                         pr_err("Bad LPI chunk %d\n", chunk);
1509                 }
1510         }
1511
1512         spin_unlock(&lpi_lock);
1513
1514         kfree(bitmap);
1515 }
1516
1517 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1518 {
1519         struct page *prop_page;
1520
1521         prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1522         if (!prop_page)
1523                 return NULL;
1524
1525         /* Priority 0xa0, Group-1, disabled */
1526         memset(page_address(prop_page),
1527                LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
1528                LPI_PROPBASE_SZ);
1529
1530         /* Make sure the GIC will observe the written configuration */
1531         gic_flush_dcache_to_poc(page_address(prop_page), LPI_PROPBASE_SZ);
1532
1533         return prop_page;
1534 }
1535
1536 static void its_free_prop_table(struct page *prop_page)
1537 {
1538         free_pages((unsigned long)page_address(prop_page),
1539                    get_order(LPI_PROPBASE_SZ));
1540 }
1541
1542 static int __init its_alloc_lpi_tables(void)
1543 {
1544         phys_addr_t paddr;
1545
1546         lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS);
1547         gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT);
1548         if (!gic_rdists->prop_page) {
1549                 pr_err("Failed to allocate PROPBASE\n");
1550                 return -ENOMEM;
1551         }
1552
1553         paddr = page_to_phys(gic_rdists->prop_page);
1554         pr_info("GIC: using LPI property table @%pa\n", &paddr);
1555
1556         return its_lpi_init(lpi_id_bits);
1557 }
1558
1559 static const char *its_base_type_string[] = {
1560         [GITS_BASER_TYPE_DEVICE]        = "Devices",
1561         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
1562         [GITS_BASER_TYPE_RESERVED3]     = "Reserved (3)",
1563         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
1564         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
1565         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
1566         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
1567 };
1568
1569 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1570 {
1571         u32 idx = baser - its->tables;
1572
1573         return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1574 }
1575
1576 static void its_write_baser(struct its_node *its, struct its_baser *baser,
1577                             u64 val)
1578 {
1579         u32 idx = baser - its->tables;
1580
1581         gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1582         baser->val = its_read_baser(its, baser);
1583 }
1584
1585 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1586                            u64 cache, u64 shr, u32 psz, u32 order,
1587                            bool indirect)
1588 {
1589         u64 val = its_read_baser(its, baser);
1590         u64 esz = GITS_BASER_ENTRY_SIZE(val);
1591         u64 type = GITS_BASER_TYPE(val);
1592         u64 baser_phys, tmp;
1593         u32 alloc_pages;
1594         void *base;
1595
1596 retry_alloc_baser:
1597         alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1598         if (alloc_pages > GITS_BASER_PAGES_MAX) {
1599                 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1600                         &its->phys_base, its_base_type_string[type],
1601                         alloc_pages, GITS_BASER_PAGES_MAX);
1602                 alloc_pages = GITS_BASER_PAGES_MAX;
1603                 order = get_order(GITS_BASER_PAGES_MAX * psz);
1604         }
1605
1606         base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
1607         if (!base)
1608                 return -ENOMEM;
1609
1610         baser_phys = virt_to_phys(base);
1611
1612         /* Check if the physical address of the memory is above 48bits */
1613         if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1614
1615                 /* 52bit PA is supported only when PageSize=64K */
1616                 if (psz != SZ_64K) {
1617                         pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1618                         free_pages((unsigned long)base, order);
1619                         return -ENXIO;
1620                 }
1621
1622                 /* Convert 52bit PA to 48bit field */
1623                 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1624         }
1625
1626 retry_baser:
1627         val = (baser_phys                                        |
1628                 (type << GITS_BASER_TYPE_SHIFT)                  |
1629                 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)       |
1630                 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT)    |
1631                 cache                                            |
1632                 shr                                              |
1633                 GITS_BASER_VALID);
1634
1635         val |=  indirect ? GITS_BASER_INDIRECT : 0x0;
1636
1637         switch (psz) {
1638         case SZ_4K:
1639                 val |= GITS_BASER_PAGE_SIZE_4K;
1640                 break;
1641         case SZ_16K:
1642                 val |= GITS_BASER_PAGE_SIZE_16K;
1643                 break;
1644         case SZ_64K:
1645                 val |= GITS_BASER_PAGE_SIZE_64K;
1646                 break;
1647         }
1648
1649         its_write_baser(its, baser, val);
1650         tmp = baser->val;
1651
1652         if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1653                 /*
1654                  * Shareability didn't stick. Just use
1655                  * whatever the read reported, which is likely
1656                  * to be the only thing this redistributor
1657                  * supports. If that's zero, make it
1658                  * non-cacheable as well.
1659                  */
1660                 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1661                 if (!shr) {
1662                         cache = GITS_BASER_nC;
1663                         gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1664                 }
1665                 goto retry_baser;
1666         }
1667
1668         if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1669                 /*
1670                  * Page size didn't stick. Let's try a smaller
1671                  * size and retry. If we reach 4K, then
1672                  * something is horribly wrong...
1673                  */
1674                 free_pages((unsigned long)base, order);
1675                 baser->base = NULL;
1676
1677                 switch (psz) {
1678                 case SZ_16K:
1679                         psz = SZ_4K;
1680                         goto retry_alloc_baser;
1681                 case SZ_64K:
1682                         psz = SZ_16K;
1683                         goto retry_alloc_baser;
1684                 }
1685         }
1686
1687         if (val != tmp) {
1688                 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1689                        &its->phys_base, its_base_type_string[type],
1690                        val, tmp);
1691                 free_pages((unsigned long)base, order);
1692                 return -ENXIO;
1693         }
1694
1695         baser->order = order;
1696         baser->base = base;
1697         baser->psz = psz;
1698         tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1699
1700         pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1701                 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1702                 its_base_type_string[type],
1703                 (unsigned long)virt_to_phys(base),
1704                 indirect ? "indirect" : "flat", (int)esz,
1705                 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1706
1707         return 0;
1708 }
1709
1710 static bool its_parse_indirect_baser(struct its_node *its,
1711                                      struct its_baser *baser,
1712                                      u32 psz, u32 *order, u32 ids)
1713 {
1714         u64 tmp = its_read_baser(its, baser);
1715         u64 type = GITS_BASER_TYPE(tmp);
1716         u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1717         u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1718         u32 new_order = *order;
1719         bool indirect = false;
1720
1721         /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1722         if ((esz << ids) > (psz * 2)) {
1723                 /*
1724                  * Find out whether hw supports a single or two-level table by
1725                  * table by reading bit at offset '62' after writing '1' to it.
1726                  */
1727                 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1728                 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1729
1730                 if (indirect) {
1731                         /*
1732                          * The size of the lvl2 table is equal to ITS page size
1733                          * which is 'psz'. For computing lvl1 table size,
1734                          * subtract ID bits that sparse lvl2 table from 'ids'
1735                          * which is reported by ITS hardware times lvl1 table
1736                          * entry size.
1737                          */
1738                         ids -= ilog2(psz / (int)esz);
1739                         esz = GITS_LVL1_ENTRY_SIZE;
1740                 }
1741         }
1742
1743         /*
1744          * Allocate as many entries as required to fit the
1745          * range of device IDs that the ITS can grok... The ID
1746          * space being incredibly sparse, this results in a
1747          * massive waste of memory if two-level device table
1748          * feature is not supported by hardware.
1749          */
1750         new_order = max_t(u32, get_order(esz << ids), new_order);
1751         if (new_order >= MAX_ORDER) {
1752                 new_order = MAX_ORDER - 1;
1753                 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1754                 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1755                         &its->phys_base, its_base_type_string[type],
1756                         its->device_ids, ids);
1757         }
1758
1759         *order = new_order;
1760
1761         return indirect;
1762 }
1763
1764 static void its_free_tables(struct its_node *its)
1765 {
1766         int i;
1767
1768         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1769                 if (its->tables[i].base) {
1770                         free_pages((unsigned long)its->tables[i].base,
1771                                    its->tables[i].order);
1772                         its->tables[i].base = NULL;
1773                 }
1774         }
1775 }
1776
1777 static int its_alloc_tables(struct its_node *its)
1778 {
1779         u64 shr = GITS_BASER_InnerShareable;
1780         u64 cache = GITS_BASER_RaWaWb;
1781         u32 psz = SZ_64K;
1782         int err, i;
1783
1784         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1785                 /* erratum 24313: ignore memory access type */
1786                 cache = GITS_BASER_nCnB;
1787
1788         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1789                 struct its_baser *baser = its->tables + i;
1790                 u64 val = its_read_baser(its, baser);
1791                 u64 type = GITS_BASER_TYPE(val);
1792                 u32 order = get_order(psz);
1793                 bool indirect = false;
1794
1795                 switch (type) {
1796                 case GITS_BASER_TYPE_NONE:
1797                         continue;
1798
1799                 case GITS_BASER_TYPE_DEVICE:
1800                         indirect = its_parse_indirect_baser(its, baser,
1801                                                             psz, &order,
1802                                                             its->device_ids);
1803                 case GITS_BASER_TYPE_VCPU:
1804                         indirect = its_parse_indirect_baser(its, baser,
1805                                                             psz, &order,
1806                                                             ITS_MAX_VPEID_BITS);
1807                         break;
1808                 }
1809
1810                 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1811                 if (err < 0) {
1812                         its_free_tables(its);
1813                         return err;
1814                 }
1815
1816                 /* Update settings which will be used for next BASERn */
1817                 psz = baser->psz;
1818                 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1819                 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1820         }
1821
1822         return 0;
1823 }
1824
1825 static int its_alloc_collections(struct its_node *its)
1826 {
1827         its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
1828                                    GFP_KERNEL);
1829         if (!its->collections)
1830                 return -ENOMEM;
1831
1832         return 0;
1833 }
1834
1835 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
1836 {
1837         struct page *pend_page;
1838         /*
1839          * The pending pages have to be at least 64kB aligned,
1840          * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1841          */
1842         pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
1843                                 get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
1844         if (!pend_page)
1845                 return NULL;
1846
1847         /* Make sure the GIC will observe the zero-ed page */
1848         gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
1849
1850         return pend_page;
1851 }
1852
1853 static void its_free_pending_table(struct page *pt)
1854 {
1855         free_pages((unsigned long)page_address(pt),
1856                    get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
1857 }
1858
1859 static void its_cpu_init_lpis(void)
1860 {
1861         void __iomem *rbase = gic_data_rdist_rd_base();
1862         struct page *pend_page;
1863         u64 val, tmp;
1864
1865         /* If we didn't allocate the pending table yet, do it now */
1866         pend_page = gic_data_rdist()->pend_page;
1867         if (!pend_page) {
1868                 phys_addr_t paddr;
1869
1870                 pend_page = its_allocate_pending_table(GFP_NOWAIT);
1871                 if (!pend_page) {
1872                         pr_err("Failed to allocate PENDBASE for CPU%d\n",
1873                                smp_processor_id());
1874                         return;
1875                 }
1876
1877                 paddr = page_to_phys(pend_page);
1878                 pr_info("CPU%d: using LPI pending table @%pa\n",
1879                         smp_processor_id(), &paddr);
1880                 gic_data_rdist()->pend_page = pend_page;
1881         }
1882
1883         /* set PROPBASE */
1884         val = (page_to_phys(gic_rdists->prop_page) |
1885                GICR_PROPBASER_InnerShareable |
1886                GICR_PROPBASER_RaWaWb |
1887                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1888
1889         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
1890         tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
1891
1892         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1893                 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1894                         /*
1895                          * The HW reports non-shareable, we must
1896                          * remove the cacheability attributes as
1897                          * well.
1898                          */
1899                         val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1900                                  GICR_PROPBASER_CACHEABILITY_MASK);
1901                         val |= GICR_PROPBASER_nC;
1902                         gicr_write_propbaser(val, rbase + GICR_PROPBASER);
1903                 }
1904                 pr_info_once("GIC: using cache flushing for LPI property table\n");
1905                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1906         }
1907
1908         /* set PENDBASE */
1909         val = (page_to_phys(pend_page) |
1910                GICR_PENDBASER_InnerShareable |
1911                GICR_PENDBASER_RaWaWb);
1912
1913         gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
1914         tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
1915
1916         if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1917                 /*
1918                  * The HW reports non-shareable, we must remove the
1919                  * cacheability attributes as well.
1920                  */
1921                 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1922                          GICR_PENDBASER_CACHEABILITY_MASK);
1923                 val |= GICR_PENDBASER_nC;
1924                 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
1925         }
1926
1927         /* Enable LPIs */
1928         val = readl_relaxed(rbase + GICR_CTLR);
1929         val |= GICR_CTLR_ENABLE_LPIS;
1930         writel_relaxed(val, rbase + GICR_CTLR);
1931
1932         /* Make sure the GIC has seen the above */
1933         dsb(sy);
1934 }
1935
1936 static void its_cpu_init_collection(struct its_node *its)
1937 {
1938         int cpu = smp_processor_id();
1939         u64 target;
1940
1941         /* avoid cross node collections and its mapping */
1942         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1943                 struct device_node *cpu_node;
1944
1945                 cpu_node = of_get_cpu_node(cpu, NULL);
1946                 if (its->numa_node != NUMA_NO_NODE &&
1947                         its->numa_node != of_node_to_nid(cpu_node))
1948                         return;
1949         }
1950
1951         /*
1952          * We now have to bind each collection to its target
1953          * redistributor.
1954          */
1955         if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1956                 /*
1957                  * This ITS wants the physical address of the
1958                  * redistributor.
1959                  */
1960                 target = gic_data_rdist()->phys_base;
1961         } else {
1962                 /* This ITS wants a linear CPU number. */
1963                 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
1964                 target = GICR_TYPER_CPU_NUMBER(target) << 16;
1965         }
1966
1967         /* Perform collection mapping */
1968         its->collections[cpu].target_address = target;
1969         its->collections[cpu].col_id = cpu;
1970
1971         its_send_mapc(its, &its->collections[cpu], 1);
1972         its_send_invall(its, &its->collections[cpu]);
1973 }
1974
1975 static void its_cpu_init_collections(void)
1976 {
1977         struct its_node *its;
1978
1979         spin_lock(&its_lock);
1980
1981         list_for_each_entry(its, &its_nodes, entry)
1982                 its_cpu_init_collection(its);
1983
1984         spin_unlock(&its_lock);
1985 }
1986
1987 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1988 {
1989         struct its_device *its_dev = NULL, *tmp;
1990         unsigned long flags;
1991
1992         raw_spin_lock_irqsave(&its->lock, flags);
1993
1994         list_for_each_entry(tmp, &its->its_device_list, entry) {
1995                 if (tmp->device_id == dev_id) {
1996                         its_dev = tmp;
1997                         break;
1998                 }
1999         }
2000
2001         raw_spin_unlock_irqrestore(&its->lock, flags);
2002
2003         return its_dev;
2004 }
2005
2006 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2007 {
2008         int i;
2009
2010         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2011                 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2012                         return &its->tables[i];
2013         }
2014
2015         return NULL;
2016 }
2017
2018 static bool its_alloc_table_entry(struct its_baser *baser, u32 id)
2019 {
2020         struct page *page;
2021         u32 esz, idx;
2022         __le64 *table;
2023
2024         /* Don't allow device id that exceeds single, flat table limit */
2025         esz = GITS_BASER_ENTRY_SIZE(baser->val);
2026         if (!(baser->val & GITS_BASER_INDIRECT))
2027                 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2028
2029         /* Compute 1st level table index & check if that exceeds table limit */
2030         idx = id >> ilog2(baser->psz / esz);
2031         if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2032                 return false;
2033
2034         table = baser->base;
2035
2036         /* Allocate memory for 2nd level table */
2037         if (!table[idx]) {
2038                 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz));
2039                 if (!page)
2040                         return false;
2041
2042                 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2043                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2044                         gic_flush_dcache_to_poc(page_address(page), baser->psz);
2045
2046                 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2047
2048                 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2049                 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2050                         gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2051
2052                 /* Ensure updated table contents are visible to ITS hardware */
2053                 dsb(sy);
2054         }
2055
2056         return true;
2057 }
2058
2059 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2060 {
2061         struct its_baser *baser;
2062
2063         baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2064
2065         /* Don't allow device id that exceeds ITS hardware limit */
2066         if (!baser)
2067                 return (ilog2(dev_id) < its->device_ids);
2068
2069         return its_alloc_table_entry(baser, dev_id);
2070 }
2071
2072 static bool its_alloc_vpe_table(u32 vpe_id)
2073 {
2074         struct its_node *its;
2075
2076         /*
2077          * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2078          * could try and only do it on ITSs corresponding to devices
2079          * that have interrupts targeted at this VPE, but the
2080          * complexity becomes crazy (and you have tons of memory
2081          * anyway, right?).
2082          */
2083         list_for_each_entry(its, &its_nodes, entry) {
2084                 struct its_baser *baser;
2085
2086                 if (!its->is_v4)
2087                         continue;
2088
2089                 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2090                 if (!baser)
2091                         return false;
2092
2093                 if (!its_alloc_table_entry(baser, vpe_id))
2094                         return false;
2095         }
2096
2097         return true;
2098 }
2099
2100 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2101                                             int nvecs, bool alloc_lpis)
2102 {
2103         struct its_device *dev;
2104         unsigned long *lpi_map = NULL;
2105         unsigned long flags;
2106         u16 *col_map = NULL;
2107         void *itt;
2108         int lpi_base;
2109         int nr_lpis;
2110         int nr_ites;
2111         int sz;
2112
2113         if (!its_alloc_device_table(its, dev_id))
2114                 return NULL;
2115
2116         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2117         /*
2118          * We allocate at least one chunk worth of LPIs bet device,
2119          * and thus that many ITEs. The device may require less though.
2120          */
2121         nr_ites = max(IRQS_PER_CHUNK, roundup_pow_of_two(nvecs));
2122         sz = nr_ites * its->ite_size;
2123         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2124         itt = kzalloc(sz, GFP_KERNEL);
2125         if (alloc_lpis) {
2126                 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
2127                 if (lpi_map)
2128                         col_map = kcalloc(nr_lpis, sizeof(*col_map),
2129                                           GFP_KERNEL);
2130         } else {
2131                 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
2132                 nr_lpis = 0;
2133                 lpi_base = 0;
2134         }
2135
2136         if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
2137                 kfree(dev);
2138                 kfree(itt);
2139                 kfree(lpi_map);
2140                 kfree(col_map);
2141                 return NULL;
2142         }
2143
2144         gic_flush_dcache_to_poc(itt, sz);
2145
2146         dev->its = its;
2147         dev->itt = itt;
2148         dev->nr_ites = nr_ites;
2149         dev->event_map.lpi_map = lpi_map;
2150         dev->event_map.col_map = col_map;
2151         dev->event_map.lpi_base = lpi_base;
2152         dev->event_map.nr_lpis = nr_lpis;
2153         mutex_init(&dev->event_map.vlpi_lock);
2154         dev->device_id = dev_id;
2155         INIT_LIST_HEAD(&dev->entry);
2156
2157         raw_spin_lock_irqsave(&its->lock, flags);
2158         list_add(&dev->entry, &its->its_device_list);
2159         raw_spin_unlock_irqrestore(&its->lock, flags);
2160
2161         /* Map device to its ITT */
2162         its_send_mapd(dev, 1);
2163
2164         return dev;
2165 }
2166
2167 static void its_free_device(struct its_device *its_dev)
2168 {
2169         unsigned long flags;
2170
2171         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2172         list_del(&its_dev->entry);
2173         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2174         kfree(its_dev->itt);
2175         kfree(its_dev);
2176 }
2177
2178 static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
2179 {
2180         int idx;
2181
2182         idx = find_first_zero_bit(dev->event_map.lpi_map,
2183                                   dev->event_map.nr_lpis);
2184         if (idx == dev->event_map.nr_lpis)
2185                 return -ENOSPC;
2186
2187         *hwirq = dev->event_map.lpi_base + idx;
2188         set_bit(idx, dev->event_map.lpi_map);
2189
2190         return 0;
2191 }
2192
2193 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2194                            int nvec, msi_alloc_info_t *info)
2195 {
2196         struct its_node *its;
2197         struct its_device *its_dev;
2198         struct msi_domain_info *msi_info;
2199         u32 dev_id;
2200
2201         /*
2202          * We ignore "dev" entierely, and rely on the dev_id that has
2203          * been passed via the scratchpad. This limits this domain's
2204          * usefulness to upper layers that definitely know that they
2205          * are built on top of the ITS.
2206          */
2207         dev_id = info->scratchpad[0].ul;
2208
2209         msi_info = msi_get_domain_info(domain);
2210         its = msi_info->data;
2211
2212         if (!gic_rdists->has_direct_lpi &&
2213             vpe_proxy.dev &&
2214             vpe_proxy.dev->its == its &&
2215             dev_id == vpe_proxy.dev->device_id) {
2216                 /* Bad luck. Get yourself a better implementation */
2217                 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2218                           dev_id);
2219                 return -EINVAL;
2220         }
2221
2222         its_dev = its_find_device(its, dev_id);
2223         if (its_dev) {
2224                 /*
2225                  * We already have seen this ID, probably through
2226                  * another alias (PCI bridge of some sort). No need to
2227                  * create the device.
2228                  */
2229                 pr_debug("Reusing ITT for devID %x\n", dev_id);
2230                 goto out;
2231         }
2232
2233         its_dev = its_create_device(its, dev_id, nvec, true);
2234         if (!its_dev)
2235                 return -ENOMEM;
2236
2237         pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2238 out:
2239         info->scratchpad[0].ptr = its_dev;
2240         return 0;
2241 }
2242
2243 static struct msi_domain_ops its_msi_domain_ops = {
2244         .msi_prepare    = its_msi_prepare,
2245 };
2246
2247 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2248                                     unsigned int virq,
2249                                     irq_hw_number_t hwirq)
2250 {
2251         struct irq_fwspec fwspec;
2252
2253         if (irq_domain_get_of_node(domain->parent)) {
2254                 fwspec.fwnode = domain->parent->fwnode;
2255                 fwspec.param_count = 3;
2256                 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2257                 fwspec.param[1] = hwirq;
2258                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2259         } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2260                 fwspec.fwnode = domain->parent->fwnode;
2261                 fwspec.param_count = 2;
2262                 fwspec.param[0] = hwirq;
2263                 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2264         } else {
2265                 return -EINVAL;
2266         }
2267
2268         return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2269 }
2270
2271 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2272                                 unsigned int nr_irqs, void *args)
2273 {
2274         msi_alloc_info_t *info = args;
2275         struct its_device *its_dev = info->scratchpad[0].ptr;
2276         irq_hw_number_t hwirq;
2277         int err;
2278         int i;
2279
2280         for (i = 0; i < nr_irqs; i++) {
2281                 err = its_alloc_device_irq(its_dev, &hwirq);
2282                 if (err)
2283                         return err;
2284
2285                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
2286                 if (err)
2287                         return err;
2288
2289                 irq_domain_set_hwirq_and_chip(domain, virq + i,
2290                                               hwirq, &its_irq_chip, its_dev);
2291                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2292                 pr_debug("ID:%d pID:%d vID:%d\n",
2293                          (int)(hwirq - its_dev->event_map.lpi_base),
2294                          (int) hwirq, virq + i);
2295         }
2296
2297         return 0;
2298 }
2299
2300 static int its_irq_domain_activate(struct irq_domain *domain,
2301                                    struct irq_data *d, bool reserve)
2302 {
2303         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2304         u32 event = its_get_event_id(d);
2305         const struct cpumask *cpu_mask = cpu_online_mask;
2306         int cpu;
2307
2308         /* get the cpu_mask of local node */
2309         if (its_dev->its->numa_node >= 0)
2310                 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2311
2312         /* Bind the LPI to the first possible CPU */
2313         cpu = cpumask_first(cpu_mask);
2314         its_dev->event_map.col_map[event] = cpu;
2315         irq_data_update_effective_affinity(d, cpumask_of(cpu));
2316
2317         /* Map the GIC IRQ and event to the device */
2318         its_send_mapti(its_dev, d->hwirq, event);
2319         return 0;
2320 }
2321
2322 static void its_irq_domain_deactivate(struct irq_domain *domain,
2323                                       struct irq_data *d)
2324 {
2325         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2326         u32 event = its_get_event_id(d);
2327
2328         /* Stop the delivery of interrupts */
2329         its_send_discard(its_dev, event);
2330 }
2331
2332 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2333                                 unsigned int nr_irqs)
2334 {
2335         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2336         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2337         int i;
2338
2339         for (i = 0; i < nr_irqs; i++) {
2340                 struct irq_data *data = irq_domain_get_irq_data(domain,
2341                                                                 virq + i);
2342                 u32 event = its_get_event_id(data);
2343
2344                 /* Mark interrupt index as unused */
2345                 clear_bit(event, its_dev->event_map.lpi_map);
2346
2347                 /* Nuke the entry in the domain */
2348                 irq_domain_reset_irq_data(data);
2349         }
2350
2351         /* If all interrupts have been freed, start mopping the floor */
2352         if (bitmap_empty(its_dev->event_map.lpi_map,
2353                          its_dev->event_map.nr_lpis)) {
2354                 its_lpi_free_chunks(its_dev->event_map.lpi_map,
2355                                     its_dev->event_map.lpi_base,
2356                                     its_dev->event_map.nr_lpis);
2357                 kfree(its_dev->event_map.col_map);
2358
2359                 /* Unmap device/itt */
2360                 its_send_mapd(its_dev, 0);
2361                 its_free_device(its_dev);
2362         }
2363
2364         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2365 }
2366
2367 static const struct irq_domain_ops its_domain_ops = {
2368         .alloc                  = its_irq_domain_alloc,
2369         .free                   = its_irq_domain_free,
2370         .activate               = its_irq_domain_activate,
2371         .deactivate             = its_irq_domain_deactivate,
2372 };
2373
2374 /*
2375  * This is insane.
2376  *
2377  * If a GICv4 doesn't implement Direct LPIs (which is extremely
2378  * likely), the only way to perform an invalidate is to use a fake
2379  * device to issue an INV command, implying that the LPI has first
2380  * been mapped to some event on that device. Since this is not exactly
2381  * cheap, we try to keep that mapping around as long as possible, and
2382  * only issue an UNMAP if we're short on available slots.
2383  *
2384  * Broken by design(tm).
2385  */
2386 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2387 {
2388         /* Already unmapped? */
2389         if (vpe->vpe_proxy_event == -1)
2390                 return;
2391
2392         its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2393         vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2394
2395         /*
2396          * We don't track empty slots at all, so let's move the
2397          * next_victim pointer if we can quickly reuse that slot
2398          * instead of nuking an existing entry. Not clear that this is
2399          * always a win though, and this might just generate a ripple
2400          * effect... Let's just hope VPEs don't migrate too often.
2401          */
2402         if (vpe_proxy.vpes[vpe_proxy.next_victim])
2403                 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2404
2405         vpe->vpe_proxy_event = -1;
2406 }
2407
2408 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2409 {
2410         if (!gic_rdists->has_direct_lpi) {
2411                 unsigned long flags;
2412
2413                 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2414                 its_vpe_db_proxy_unmap_locked(vpe);
2415                 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2416         }
2417 }
2418
2419 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2420 {
2421         /* Already mapped? */
2422         if (vpe->vpe_proxy_event != -1)
2423                 return;
2424
2425         /* This slot was already allocated. Kick the other VPE out. */
2426         if (vpe_proxy.vpes[vpe_proxy.next_victim])
2427                 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2428
2429         /* Map the new VPE instead */
2430         vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2431         vpe->vpe_proxy_event = vpe_proxy.next_victim;
2432         vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2433
2434         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2435         its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2436 }
2437
2438 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2439 {
2440         unsigned long flags;
2441         struct its_collection *target_col;
2442
2443         if (gic_rdists->has_direct_lpi) {
2444                 void __iomem *rdbase;
2445
2446                 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2447                 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2448                 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2449                         cpu_relax();
2450
2451                 return;
2452         }
2453
2454         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2455
2456         its_vpe_db_proxy_map_locked(vpe);
2457
2458         target_col = &vpe_proxy.dev->its->collections[to];
2459         its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2460         vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2461
2462         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2463 }
2464
2465 static int its_vpe_set_affinity(struct irq_data *d,
2466                                 const struct cpumask *mask_val,
2467                                 bool force)
2468 {
2469         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2470         int cpu = cpumask_first(mask_val);
2471
2472         /*
2473          * Changing affinity is mega expensive, so let's be as lazy as
2474          * we can and only do it if we really have to. Also, if mapped
2475          * into the proxy device, we need to move the doorbell
2476          * interrupt to its new location.
2477          */
2478         if (vpe->col_idx != cpu) {
2479                 int from = vpe->col_idx;
2480
2481                 vpe->col_idx = cpu;
2482                 its_send_vmovp(vpe);
2483                 its_vpe_db_proxy_move(vpe, from, cpu);
2484         }
2485
2486         irq_data_update_effective_affinity(d, cpumask_of(cpu));
2487
2488         return IRQ_SET_MASK_OK_DONE;
2489 }
2490
2491 static void its_vpe_schedule(struct its_vpe *vpe)
2492 {
2493         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2494         u64 val;
2495
2496         /* Schedule the VPE */
2497         val  = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2498                 GENMASK_ULL(51, 12);
2499         val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2500         val |= GICR_VPROPBASER_RaWb;
2501         val |= GICR_VPROPBASER_InnerShareable;
2502         gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2503
2504         val  = virt_to_phys(page_address(vpe->vpt_page)) &
2505                 GENMASK_ULL(51, 16);
2506         val |= GICR_VPENDBASER_RaWaWb;
2507         val |= GICR_VPENDBASER_NonShareable;
2508         /*
2509          * There is no good way of finding out if the pending table is
2510          * empty as we can race against the doorbell interrupt very
2511          * easily. So in the end, vpe->pending_last is only an
2512          * indication that the vcpu has something pending, not one
2513          * that the pending table is empty. A good implementation
2514          * would be able to read its coarse map pretty quickly anyway,
2515          * making this a tolerable issue.
2516          */
2517         val |= GICR_VPENDBASER_PendingLast;
2518         val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2519         val |= GICR_VPENDBASER_Valid;
2520         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2521 }
2522
2523 static void its_vpe_deschedule(struct its_vpe *vpe)
2524 {
2525         void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2526         u32 count = 1000000;    /* 1s! */
2527         bool clean;
2528         u64 val;
2529
2530         /* We're being scheduled out */
2531         val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2532         val &= ~GICR_VPENDBASER_Valid;
2533         gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2534
2535         do {
2536                 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2537                 clean = !(val & GICR_VPENDBASER_Dirty);
2538                 if (!clean) {
2539                         count--;
2540                         cpu_relax();
2541                         udelay(1);
2542                 }
2543         } while (!clean && count);
2544
2545         if (unlikely(!clean && !count)) {
2546                 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2547                 vpe->idai = false;
2548                 vpe->pending_last = true;
2549         } else {
2550                 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2551                 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2552         }
2553 }
2554
2555 static void its_vpe_invall(struct its_vpe *vpe)
2556 {
2557         struct its_node *its;
2558
2559         list_for_each_entry(its, &its_nodes, entry) {
2560                 if (!its->is_v4)
2561                         continue;
2562
2563                 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2564                         continue;
2565
2566                 /*
2567                  * Sending a VINVALL to a single ITS is enough, as all
2568                  * we need is to reach the redistributors.
2569                  */
2570                 its_send_vinvall(its, vpe);
2571                 return;
2572         }
2573 }
2574
2575 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2576 {
2577         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2578         struct its_cmd_info *info = vcpu_info;
2579
2580         switch (info->cmd_type) {
2581         case SCHEDULE_VPE:
2582                 its_vpe_schedule(vpe);
2583                 return 0;
2584
2585         case DESCHEDULE_VPE:
2586                 its_vpe_deschedule(vpe);
2587                 return 0;
2588
2589         case INVALL_VPE:
2590                 its_vpe_invall(vpe);
2591                 return 0;
2592
2593         default:
2594                 return -EINVAL;
2595         }
2596 }
2597
2598 static void its_vpe_send_cmd(struct its_vpe *vpe,
2599                              void (*cmd)(struct its_device *, u32))
2600 {
2601         unsigned long flags;
2602
2603         raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2604
2605         its_vpe_db_proxy_map_locked(vpe);
2606         cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2607
2608         raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2609 }
2610
2611 static void its_vpe_send_inv(struct irq_data *d)
2612 {
2613         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2614
2615         if (gic_rdists->has_direct_lpi) {
2616                 void __iomem *rdbase;
2617
2618                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2619                 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2620                 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2621                         cpu_relax();
2622         } else {
2623                 its_vpe_send_cmd(vpe, its_send_inv);
2624         }
2625 }
2626
2627 static void its_vpe_mask_irq(struct irq_data *d)
2628 {
2629         /*
2630          * We need to unmask the LPI, which is described by the parent
2631          * irq_data. Instead of calling into the parent (which won't
2632          * exactly do the right thing, let's simply use the
2633          * parent_data pointer. Yes, I'm naughty.
2634          */
2635         lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2636         its_vpe_send_inv(d);
2637 }
2638
2639 static void its_vpe_unmask_irq(struct irq_data *d)
2640 {
2641         /* Same hack as above... */
2642         lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2643         its_vpe_send_inv(d);
2644 }
2645
2646 static int its_vpe_set_irqchip_state(struct irq_data *d,
2647                                      enum irqchip_irq_state which,
2648                                      bool state)
2649 {
2650         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2651
2652         if (which != IRQCHIP_STATE_PENDING)
2653                 return -EINVAL;
2654
2655         if (gic_rdists->has_direct_lpi) {
2656                 void __iomem *rdbase;
2657
2658                 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2659                 if (state) {
2660                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2661                 } else {
2662                         gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2663                         while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2664                                 cpu_relax();
2665                 }
2666         } else {
2667                 if (state)
2668                         its_vpe_send_cmd(vpe, its_send_int);
2669                 else
2670                         its_vpe_send_cmd(vpe, its_send_clear);
2671         }
2672
2673         return 0;
2674 }
2675
2676 static struct irq_chip its_vpe_irq_chip = {
2677         .name                   = "GICv4-vpe",
2678         .irq_mask               = its_vpe_mask_irq,
2679         .irq_unmask             = its_vpe_unmask_irq,
2680         .irq_eoi                = irq_chip_eoi_parent,
2681         .irq_set_affinity       = its_vpe_set_affinity,
2682         .irq_set_irqchip_state  = its_vpe_set_irqchip_state,
2683         .irq_set_vcpu_affinity  = its_vpe_set_vcpu_affinity,
2684 };
2685
2686 static int its_vpe_id_alloc(void)
2687 {
2688         return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
2689 }
2690
2691 static void its_vpe_id_free(u16 id)
2692 {
2693         ida_simple_remove(&its_vpeid_ida, id);
2694 }
2695
2696 static int its_vpe_init(struct its_vpe *vpe)
2697 {
2698         struct page *vpt_page;
2699         int vpe_id;
2700
2701         /* Allocate vpe_id */
2702         vpe_id = its_vpe_id_alloc();
2703         if (vpe_id < 0)
2704                 return vpe_id;
2705
2706         /* Allocate VPT */
2707         vpt_page = its_allocate_pending_table(GFP_KERNEL);
2708         if (!vpt_page) {
2709                 its_vpe_id_free(vpe_id);
2710                 return -ENOMEM;
2711         }
2712
2713         if (!its_alloc_vpe_table(vpe_id)) {
2714                 its_vpe_id_free(vpe_id);
2715                 its_free_pending_table(vpe->vpt_page);
2716                 return -ENOMEM;
2717         }
2718
2719         vpe->vpe_id = vpe_id;
2720         vpe->vpt_page = vpt_page;
2721         vpe->vpe_proxy_event = -1;
2722
2723         return 0;
2724 }
2725
2726 static void its_vpe_teardown(struct its_vpe *vpe)
2727 {
2728         its_vpe_db_proxy_unmap(vpe);
2729         its_vpe_id_free(vpe->vpe_id);
2730         its_free_pending_table(vpe->vpt_page);
2731 }
2732
2733 static void its_vpe_irq_domain_free(struct irq_domain *domain,
2734                                     unsigned int virq,
2735                                     unsigned int nr_irqs)
2736 {
2737         struct its_vm *vm = domain->host_data;
2738         int i;
2739
2740         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2741
2742         for (i = 0; i < nr_irqs; i++) {
2743                 struct irq_data *data = irq_domain_get_irq_data(domain,
2744                                                                 virq + i);
2745                 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
2746
2747                 BUG_ON(vm != vpe->its_vm);
2748
2749                 clear_bit(data->hwirq, vm->db_bitmap);
2750                 its_vpe_teardown(vpe);
2751                 irq_domain_reset_irq_data(data);
2752         }
2753
2754         if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
2755                 its_lpi_free_chunks(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
2756                 its_free_prop_table(vm->vprop_page);
2757         }
2758 }
2759
2760 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2761                                     unsigned int nr_irqs, void *args)
2762 {
2763         struct its_vm *vm = args;
2764         unsigned long *bitmap;
2765         struct page *vprop_page;
2766         int base, nr_ids, i, err = 0;
2767
2768         BUG_ON(!vm);
2769
2770         bitmap = its_lpi_alloc_chunks(nr_irqs, &base, &nr_ids);
2771         if (!bitmap)
2772                 return -ENOMEM;
2773
2774         if (nr_ids < nr_irqs) {
2775                 its_lpi_free_chunks(bitmap, base, nr_ids);
2776                 return -ENOMEM;
2777         }
2778
2779         vprop_page = its_allocate_prop_table(GFP_KERNEL);
2780         if (!vprop_page) {
2781                 its_lpi_free_chunks(bitmap, base, nr_ids);
2782                 return -ENOMEM;
2783         }
2784
2785         vm->db_bitmap = bitmap;
2786         vm->db_lpi_base = base;
2787         vm->nr_db_lpis = nr_ids;
2788         vm->vprop_page = vprop_page;
2789
2790         for (i = 0; i < nr_irqs; i++) {
2791                 vm->vpes[i]->vpe_db_lpi = base + i;
2792                 err = its_vpe_init(vm->vpes[i]);
2793                 if (err)
2794                         break;
2795                 err = its_irq_gic_domain_alloc(domain, virq + i,
2796                                                vm->vpes[i]->vpe_db_lpi);
2797                 if (err)
2798                         break;
2799                 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
2800                                               &its_vpe_irq_chip, vm->vpes[i]);
2801                 set_bit(i, bitmap);
2802         }
2803
2804         if (err) {
2805                 if (i > 0)
2806                         its_vpe_irq_domain_free(domain, virq, i - 1);
2807
2808                 its_lpi_free_chunks(bitmap, base, nr_ids);
2809                 its_free_prop_table(vprop_page);
2810         }
2811
2812         return err;
2813 }
2814
2815 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
2816                                        struct irq_data *d, bool reserve)
2817 {
2818         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2819         struct its_node *its;
2820
2821         /* If we use the list map, we issue VMAPP on demand... */
2822         if (its_list_map)
2823                 return 0;
2824
2825         /* Map the VPE to the first possible CPU */
2826         vpe->col_idx = cpumask_first(cpu_online_mask);
2827
2828         list_for_each_entry(its, &its_nodes, entry) {
2829                 if (!its->is_v4)
2830                         continue;
2831
2832                 its_send_vmapp(its, vpe, true);
2833                 its_send_vinvall(its, vpe);
2834         }
2835
2836         irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
2837
2838         return 0;
2839 }
2840
2841 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
2842                                           struct irq_data *d)
2843 {
2844         struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2845         struct its_node *its;
2846
2847         /*
2848          * If we use the list map, we unmap the VPE once no VLPIs are
2849          * associated with the VM.
2850          */
2851         if (its_list_map)
2852                 return;
2853
2854         list_for_each_entry(its, &its_nodes, entry) {
2855                 if (!its->is_v4)
2856                         continue;
2857
2858                 its_send_vmapp(its, vpe, false);
2859         }
2860 }
2861
2862 static const struct irq_domain_ops its_vpe_domain_ops = {
2863         .alloc                  = its_vpe_irq_domain_alloc,
2864         .free                   = its_vpe_irq_domain_free,
2865         .activate               = its_vpe_irq_domain_activate,
2866         .deactivate             = its_vpe_irq_domain_deactivate,
2867 };
2868
2869 static int its_force_quiescent(void __iomem *base)
2870 {
2871         u32 count = 1000000;    /* 1s */
2872         u32 val;
2873
2874         val = readl_relaxed(base + GITS_CTLR);
2875         /*
2876          * GIC architecture specification requires the ITS to be both
2877          * disabled and quiescent for writes to GITS_BASER<n> or
2878          * GITS_CBASER to not have UNPREDICTABLE results.
2879          */
2880         if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
2881                 return 0;
2882
2883         /* Disable the generation of all interrupts to this ITS */
2884         val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
2885         writel_relaxed(val, base + GITS_CTLR);
2886
2887         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
2888         while (1) {
2889                 val = readl_relaxed(base + GITS_CTLR);
2890                 if (val & GITS_CTLR_QUIESCENT)
2891                         return 0;
2892
2893                 count--;
2894                 if (!count)
2895                         return -EBUSY;
2896
2897                 cpu_relax();
2898                 udelay(1);
2899         }
2900 }
2901
2902 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
2903 {
2904         struct its_node *its = data;
2905
2906         /* erratum 22375: only alloc 8MB table size */
2907         its->device_ids = 0x14;         /* 20 bits, 8MB */
2908         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
2909
2910         return true;
2911 }
2912
2913 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
2914 {
2915         struct its_node *its = data;
2916
2917         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
2918
2919         return true;
2920 }
2921
2922 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
2923 {
2924         struct its_node *its = data;
2925
2926         /* On QDF2400, the size of the ITE is 16Bytes */
2927         its->ite_size = 16;
2928
2929         return true;
2930 }
2931
2932 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
2933 {
2934         struct its_node *its = its_dev->its;
2935
2936         /*
2937          * The Socionext Synquacer SoC has a so-called 'pre-ITS',
2938          * which maps 32-bit writes targeted at a separate window of
2939          * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
2940          * with device ID taken from bits [device_id_bits + 1:2] of
2941          * the window offset.
2942          */
2943         return its->pre_its_base + (its_dev->device_id << 2);
2944 }
2945
2946 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
2947 {
2948         struct its_node *its = data;
2949         u32 pre_its_window[2];
2950         u32 ids;
2951
2952         if (!fwnode_property_read_u32_array(its->fwnode_handle,
2953                                            "socionext,synquacer-pre-its",
2954                                            pre_its_window,
2955                                            ARRAY_SIZE(pre_its_window))) {
2956
2957                 its->pre_its_base = pre_its_window[0];
2958                 its->get_msi_base = its_irq_get_msi_base_pre_its;
2959
2960                 ids = ilog2(pre_its_window[1]) - 2;
2961                 if (its->device_ids > ids)
2962                         its->device_ids = ids;
2963
2964                 /* the pre-ITS breaks isolation, so disable MSI remapping */
2965                 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
2966                 return true;
2967         }
2968         return false;
2969 }
2970
2971 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
2972 {
2973         struct its_node *its = data;
2974
2975         /*
2976          * Hip07 insists on using the wrong address for the VLPI
2977          * page. Trick it into doing the right thing...
2978          */
2979         its->vlpi_redist_offset = SZ_128K;
2980         return true;
2981 }
2982
2983 static const struct gic_quirk its_quirks[] = {
2984 #ifdef CONFIG_CAVIUM_ERRATUM_22375
2985         {
2986                 .desc   = "ITS: Cavium errata 22375, 24313",
2987                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
2988                 .mask   = 0xffff0fff,
2989                 .init   = its_enable_quirk_cavium_22375,
2990         },
2991 #endif
2992 #ifdef CONFIG_CAVIUM_ERRATUM_23144
2993         {
2994                 .desc   = "ITS: Cavium erratum 23144",
2995                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
2996                 .mask   = 0xffff0fff,
2997                 .init   = its_enable_quirk_cavium_23144,
2998         },
2999 #endif
3000 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3001         {
3002                 .desc   = "ITS: QDF2400 erratum 0065",
3003                 .iidr   = 0x00001070, /* QDF2400 ITS rev 1.x */
3004                 .mask   = 0xffffffff,
3005                 .init   = its_enable_quirk_qdf2400_e0065,
3006         },
3007 #endif
3008 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3009         {
3010                 /*
3011                  * The Socionext Synquacer SoC incorporates ARM's own GIC-500
3012                  * implementation, but with a 'pre-ITS' added that requires
3013                  * special handling in software.
3014                  */
3015                 .desc   = "ITS: Socionext Synquacer pre-ITS",
3016                 .iidr   = 0x0001143b,
3017                 .mask   = 0xffffffff,
3018                 .init   = its_enable_quirk_socionext_synquacer,
3019         },
3020 #endif
3021 #ifdef CONFIG_HISILICON_ERRATUM_161600802
3022         {
3023                 .desc   = "ITS: Hip07 erratum 161600802",
3024                 .iidr   = 0x00000004,
3025                 .mask   = 0xffffffff,
3026                 .init   = its_enable_quirk_hip07_161600802,
3027         },
3028 #endif
3029         {
3030         }
3031 };
3032
3033 static void its_enable_quirks(struct its_node *its)
3034 {
3035         u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3036
3037         gic_enable_quirks(iidr, its_quirks, its);
3038 }
3039
3040 static int its_save_disable(void)
3041 {
3042         struct its_node *its;
3043         int err = 0;
3044
3045         spin_lock(&its_lock);
3046         list_for_each_entry(its, &its_nodes, entry) {
3047                 void __iomem *base;
3048
3049                 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3050                         continue;
3051
3052                 base = its->base;
3053                 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3054                 err = its_force_quiescent(base);
3055                 if (err) {
3056                         pr_err("ITS@%pa: failed to quiesce: %d\n",
3057                                &its->phys_base, err);
3058                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3059                         goto err;
3060                 }
3061
3062                 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3063         }
3064
3065 err:
3066         if (err) {
3067                 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3068                         void __iomem *base;
3069
3070                         if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3071                                 continue;
3072
3073                         base = its->base;
3074                         writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3075                 }
3076         }
3077         spin_unlock(&its_lock);
3078
3079         return err;
3080 }
3081
3082 static void its_restore_enable(void)
3083 {
3084         struct its_node *its;
3085         int ret;
3086
3087         spin_lock(&its_lock);
3088         list_for_each_entry(its, &its_nodes, entry) {
3089                 void __iomem *base;
3090                 int i;
3091
3092                 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3093                         continue;
3094
3095                 base = its->base;
3096
3097                 /*
3098                  * Make sure that the ITS is disabled. If it fails to quiesce,
3099                  * don't restore it since writing to CBASER or BASER<n>
3100                  * registers is undefined according to the GIC v3 ITS
3101                  * Specification.
3102                  */
3103                 ret = its_force_quiescent(base);
3104                 if (ret) {
3105                         pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3106                                &its->phys_base, ret);
3107                         continue;
3108                 }
3109
3110                 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3111
3112                 /*
3113                  * Writing CBASER resets CREADR to 0, so make CWRITER and
3114                  * cmd_write line up with it.
3115                  */
3116                 its->cmd_write = its->cmd_base;
3117                 gits_write_cwriter(0, base + GITS_CWRITER);
3118
3119                 /* Restore GITS_BASER from the value cache. */
3120                 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3121                         struct its_baser *baser = &its->tables[i];
3122
3123                         if (!(baser->val & GITS_BASER_VALID))
3124                                 continue;
3125
3126                         its_write_baser(its, baser, baser->val);
3127                 }
3128                 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3129
3130                 /*
3131                  * Reinit the collection if it's stored in the ITS. This is
3132                  * indicated by the col_id being less than the HCC field.
3133                  * CID < HCC as specified in the GIC v3 Documentation.
3134                  */
3135                 if (its->collections[smp_processor_id()].col_id <
3136                     GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3137                         its_cpu_init_collection(its);
3138         }
3139         spin_unlock(&its_lock);
3140 }
3141
3142 static struct syscore_ops its_syscore_ops = {
3143         .suspend = its_save_disable,
3144         .resume = its_restore_enable,
3145 };
3146
3147 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3148 {
3149         struct irq_domain *inner_domain;
3150         struct msi_domain_info *info;
3151
3152         info = kzalloc(sizeof(*info), GFP_KERNEL);
3153         if (!info)
3154                 return -ENOMEM;
3155
3156         inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3157         if (!inner_domain) {
3158                 kfree(info);
3159                 return -ENOMEM;
3160         }
3161
3162         inner_domain->parent = its_parent;
3163         irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3164         inner_domain->flags |= its->msi_domain_flags;
3165         info->ops = &its_msi_domain_ops;
3166         info->data = its;
3167         inner_domain->host_data = info;
3168
3169         return 0;
3170 }
3171
3172 static int its_init_vpe_domain(void)
3173 {
3174         struct its_node *its;
3175         u32 devid;
3176         int entries;
3177
3178         if (gic_rdists->has_direct_lpi) {
3179                 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3180                 return 0;
3181         }
3182
3183         /* Any ITS will do, even if not v4 */
3184         its = list_first_entry(&its_nodes, struct its_node, entry);
3185
3186         entries = roundup_pow_of_two(nr_cpu_ids);
3187         vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
3188                                  GFP_KERNEL);
3189         if (!vpe_proxy.vpes) {
3190                 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3191                 return -ENOMEM;
3192         }
3193
3194         /* Use the last possible DevID */
3195         devid = GENMASK(its->device_ids - 1, 0);
3196         vpe_proxy.dev = its_create_device(its, devid, entries, false);
3197         if (!vpe_proxy.dev) {
3198                 kfree(vpe_proxy.vpes);
3199                 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3200                 return -ENOMEM;
3201         }
3202
3203         BUG_ON(entries > vpe_proxy.dev->nr_ites);
3204
3205         raw_spin_lock_init(&vpe_proxy.lock);
3206         vpe_proxy.next_victim = 0;
3207         pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3208                 devid, vpe_proxy.dev->nr_ites);
3209
3210         return 0;
3211 }
3212
3213 static int __init its_compute_its_list_map(struct resource *res,
3214                                            void __iomem *its_base)
3215 {
3216         int its_number;
3217         u32 ctlr;
3218
3219         /*
3220          * This is assumed to be done early enough that we're
3221          * guaranteed to be single-threaded, hence no
3222          * locking. Should this change, we should address
3223          * this.
3224          */
3225         its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3226         if (its_number >= GICv4_ITS_LIST_MAX) {
3227                 pr_err("ITS@%pa: No ITSList entry available!\n",
3228                        &res->start);
3229                 return -EINVAL;
3230         }
3231
3232         ctlr = readl_relaxed(its_base + GITS_CTLR);
3233         ctlr &= ~GITS_CTLR_ITS_NUMBER;
3234         ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3235         writel_relaxed(ctlr, its_base + GITS_CTLR);
3236         ctlr = readl_relaxed(its_base + GITS_CTLR);
3237         if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3238                 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3239                 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3240         }
3241
3242         if (test_and_set_bit(its_number, &its_list_map)) {
3243                 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3244                        &res->start, its_number);
3245                 return -EINVAL;
3246         }
3247
3248         return its_number;
3249 }
3250
3251 static int __init its_probe_one(struct resource *res,
3252                                 struct fwnode_handle *handle, int numa_node)
3253 {
3254         struct its_node *its;
3255         void __iomem *its_base;
3256         u32 val, ctlr;
3257         u64 baser, tmp, typer;
3258         int err;
3259
3260         its_base = ioremap(res->start, resource_size(res));
3261         if (!its_base) {
3262                 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3263                 return -ENOMEM;
3264         }
3265
3266         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3267         if (val != 0x30 && val != 0x40) {
3268                 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3269                 err = -ENODEV;
3270                 goto out_unmap;
3271         }
3272
3273         err = its_force_quiescent(its_base);
3274         if (err) {
3275                 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3276                 goto out_unmap;
3277         }
3278
3279         pr_info("ITS %pR\n", res);
3280
3281         its = kzalloc(sizeof(*its), GFP_KERNEL);
3282         if (!its) {
3283                 err = -ENOMEM;
3284                 goto out_unmap;
3285         }
3286
3287         raw_spin_lock_init(&its->lock);
3288         INIT_LIST_HEAD(&its->entry);
3289         INIT_LIST_HEAD(&its->its_device_list);
3290         typer = gic_read_typer(its_base + GITS_TYPER);
3291         its->base = its_base;
3292         its->phys_base = res->start;
3293         its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3294         its->device_ids = GITS_TYPER_DEVBITS(typer);
3295         its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
3296         if (its->is_v4) {
3297                 if (!(typer & GITS_TYPER_VMOVP)) {
3298                         err = its_compute_its_list_map(res, its_base);
3299                         if (err < 0)
3300                                 goto out_free_its;
3301
3302                         its->list_nr = err;
3303
3304                         pr_info("ITS@%pa: Using ITS number %d\n",
3305                                 &res->start, err);
3306                 } else {
3307                         pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3308                 }
3309         }
3310
3311         its->numa_node = numa_node;
3312
3313         its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
3314                                                 get_order(ITS_CMD_QUEUE_SZ));
3315         if (!its->cmd_base) {
3316                 err = -ENOMEM;
3317                 goto out_free_its;
3318         }
3319         its->cmd_write = its->cmd_base;
3320         its->fwnode_handle = handle;
3321         its->get_msi_base = its_irq_get_msi_base;
3322         its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3323
3324         its_enable_quirks(its);
3325
3326         err = its_alloc_tables(its);
3327         if (err)
3328                 goto out_free_cmd;
3329
3330         err = its_alloc_collections(its);
3331         if (err)
3332                 goto out_free_tables;
3333
3334         baser = (virt_to_phys(its->cmd_base)    |
3335                  GITS_CBASER_RaWaWb             |
3336                  GITS_CBASER_InnerShareable     |
3337                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3338                  GITS_CBASER_VALID);
3339
3340         gits_write_cbaser(baser, its->base + GITS_CBASER);
3341         tmp = gits_read_cbaser(its->base + GITS_CBASER);
3342
3343         if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3344                 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3345                         /*
3346                          * The HW reports non-shareable, we must
3347                          * remove the cacheability attributes as
3348                          * well.
3349                          */
3350                         baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3351                                    GITS_CBASER_CACHEABILITY_MASK);
3352                         baser |= GITS_CBASER_nC;
3353                         gits_write_cbaser(baser, its->base + GITS_CBASER);
3354                 }
3355                 pr_info("ITS: using cache flushing for cmd queue\n");
3356                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3357         }
3358
3359         gits_write_cwriter(0, its->base + GITS_CWRITER);
3360         ctlr = readl_relaxed(its->base + GITS_CTLR);
3361         ctlr |= GITS_CTLR_ENABLE;
3362         if (its->is_v4)
3363                 ctlr |= GITS_CTLR_ImDe;
3364         writel_relaxed(ctlr, its->base + GITS_CTLR);
3365
3366         if (GITS_TYPER_HCC(typer))
3367                 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
3368
3369         err = its_init_domain(handle, its);
3370         if (err)
3371                 goto out_free_tables;
3372
3373         spin_lock(&its_lock);
3374         list_add(&its->entry, &its_nodes);
3375         spin_unlock(&its_lock);
3376
3377         return 0;
3378
3379 out_free_tables:
3380         its_free_tables(its);
3381 out_free_cmd:
3382         free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3383 out_free_its:
3384         kfree(its);
3385 out_unmap:
3386         iounmap(its_base);
3387         pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3388         return err;
3389 }
3390
3391 static bool gic_rdists_supports_plpis(void)
3392 {
3393         return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3394 }
3395
3396 static int redist_disable_lpis(void)
3397 {
3398         void __iomem *rbase = gic_data_rdist_rd_base();
3399         u64 timeout = USEC_PER_SEC;
3400         u64 val;
3401
3402         if (!gic_rdists_supports_plpis()) {
3403                 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3404                 return -ENXIO;
3405         }
3406
3407         val = readl_relaxed(rbase + GICR_CTLR);
3408         if (!(val & GICR_CTLR_ENABLE_LPIS))
3409                 return 0;
3410
3411         pr_warn("CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3412                 smp_processor_id());
3413         add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3414
3415         /* Disable LPIs */
3416         val &= ~GICR_CTLR_ENABLE_LPIS;
3417         writel_relaxed(val, rbase + GICR_CTLR);
3418
3419         /* Make sure any change to GICR_CTLR is observable by the GIC */
3420         dsb(sy);
3421
3422         /*
3423          * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
3424          * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
3425          * Error out if we time out waiting for RWP to clear.
3426          */
3427         while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
3428                 if (!timeout) {
3429                         pr_err("CPU%d: Timeout while disabling LPIs\n",
3430                                smp_processor_id());
3431                         return -ETIMEDOUT;
3432                 }
3433                 udelay(1);
3434                 timeout--;
3435         }
3436
3437         /*
3438          * After it has been written to 1, it is IMPLEMENTATION
3439          * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
3440          * cleared to 0. Error out if clearing the bit failed.
3441          */
3442         if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
3443                 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
3444                 return -EBUSY;
3445         }
3446
3447         return 0;
3448 }
3449
3450 int its_cpu_init(void)
3451 {
3452         if (!list_empty(&its_nodes)) {
3453                 int ret;
3454
3455                 ret = redist_disable_lpis();
3456                 if (ret)
3457                         return ret;
3458
3459                 its_cpu_init_lpis();
3460                 its_cpu_init_collections();
3461         }
3462
3463         return 0;
3464 }
3465
3466 static const struct of_device_id its_device_id[] = {
3467         {       .compatible     = "arm,gic-v3-its",     },
3468         {},
3469 };
3470
3471 static int __init its_of_probe(struct device_node *node)
3472 {
3473         struct device_node *np;
3474         struct resource res;
3475
3476         for (np = of_find_matching_node(node, its_device_id); np;
3477              np = of_find_matching_node(np, its_device_id)) {
3478                 if (!of_device_is_available(np))
3479                         continue;
3480                 if (!of_property_read_bool(np, "msi-controller")) {
3481                         pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3482                                 np);
3483                         continue;
3484                 }
3485
3486                 if (of_address_to_resource(np, 0, &res)) {
3487                         pr_warn("%pOF: no regs?\n", np);
3488                         continue;
3489                 }
3490
3491                 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3492         }
3493         return 0;
3494 }
3495
3496 #ifdef CONFIG_ACPI
3497
3498 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3499
3500 #ifdef CONFIG_ACPI_NUMA
3501 struct its_srat_map {
3502         /* numa node id */
3503         u32     numa_node;
3504         /* GIC ITS ID */
3505         u32     its_id;
3506 };
3507
3508 static struct its_srat_map *its_srat_maps __initdata;
3509 static int its_in_srat __initdata;
3510
3511 static int __init acpi_get_its_numa_node(u32 its_id)
3512 {
3513         int i;
3514
3515         for (i = 0; i < its_in_srat; i++) {
3516                 if (its_id == its_srat_maps[i].its_id)
3517                         return its_srat_maps[i].numa_node;
3518         }
3519         return NUMA_NO_NODE;
3520 }
3521
3522 static int __init gic_acpi_match_srat_its(struct acpi_subtable_header *header,
3523                                           const unsigned long end)
3524 {
3525         return 0;
3526 }
3527
3528 static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header,
3529                          const unsigned long end)
3530 {
3531         int node;
3532         struct acpi_srat_gic_its_affinity *its_affinity;
3533
3534         its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3535         if (!its_affinity)
3536                 return -EINVAL;
3537
3538         if (its_affinity->header.length < sizeof(*its_affinity)) {
3539                 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3540                         its_affinity->header.length);
3541                 return -EINVAL;
3542         }
3543
3544         node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3545
3546         if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3547                 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3548                 return 0;
3549         }
3550
3551         its_srat_maps[its_in_srat].numa_node = node;
3552         its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3553         its_in_srat++;
3554         pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3555                 its_affinity->proximity_domain, its_affinity->its_id, node);
3556
3557         return 0;
3558 }
3559
3560 static void __init acpi_table_parse_srat_its(void)
3561 {
3562         int count;
3563
3564         count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3565                         sizeof(struct acpi_table_srat),
3566                         ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3567                         gic_acpi_match_srat_its, 0);
3568         if (count <= 0)
3569                 return;
3570
3571         its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
3572                                       GFP_KERNEL);
3573         if (!its_srat_maps) {
3574                 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3575                 return;
3576         }
3577
3578         acpi_table_parse_entries(ACPI_SIG_SRAT,
3579                         sizeof(struct acpi_table_srat),
3580                         ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3581                         gic_acpi_parse_srat_its, 0);
3582 }
3583
3584 /* free the its_srat_maps after ITS probing */
3585 static void __init acpi_its_srat_maps_free(void)
3586 {
3587         kfree(its_srat_maps);
3588 }
3589 #else
3590 static void __init acpi_table_parse_srat_its(void)      { }
3591 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3592 static void __init acpi_its_srat_maps_free(void) { }
3593 #endif
3594
3595 static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
3596                                           const unsigned long end)
3597 {
3598         struct acpi_madt_generic_translator *its_entry;
3599         struct fwnode_handle *dom_handle;
3600         struct resource res;
3601         int err;
3602
3603         its_entry = (struct acpi_madt_generic_translator *)header;
3604         memset(&res, 0, sizeof(res));
3605         res.start = its_entry->base_address;
3606         res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3607         res.flags = IORESOURCE_MEM;
3608
3609         dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address);
3610         if (!dom_handle) {
3611                 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3612                        &res.start);
3613                 return -ENOMEM;
3614         }
3615
3616         err = iort_register_domain_token(its_entry->translation_id, res.start,
3617                                          dom_handle);
3618         if (err) {
3619                 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3620                        &res.start, its_entry->translation_id);
3621                 goto dom_err;
3622         }
3623
3624         err = its_probe_one(&res, dom_handle,
3625                         acpi_get_its_numa_node(its_entry->translation_id));
3626         if (!err)
3627                 return 0;
3628
3629         iort_deregister_domain_token(its_entry->translation_id);
3630 dom_err:
3631         irq_domain_free_fwnode(dom_handle);
3632         return err;
3633 }
3634
3635 static void __init its_acpi_probe(void)
3636 {
3637         acpi_table_parse_srat_its();
3638         acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
3639                               gic_acpi_parse_madt_its, 0);
3640         acpi_its_srat_maps_free();
3641 }
3642 #else
3643 static void __init its_acpi_probe(void) { }
3644 #endif
3645
3646 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
3647                     struct irq_domain *parent_domain)
3648 {
3649         struct device_node *of_node;
3650         struct its_node *its;
3651         bool has_v4 = false;
3652         int err;
3653
3654         its_parent = parent_domain;
3655         of_node = to_of_node(handle);
3656         if (of_node)
3657                 its_of_probe(of_node);
3658         else
3659                 its_acpi_probe();
3660
3661         if (list_empty(&its_nodes)) {
3662                 pr_warn("ITS: No ITS available, not enabling LPIs\n");
3663                 return -ENXIO;
3664         }
3665
3666         gic_rdists = rdists;
3667         err = its_alloc_lpi_tables();
3668         if (err)
3669                 return err;
3670
3671         list_for_each_entry(its, &its_nodes, entry)
3672                 has_v4 |= its->is_v4;
3673
3674         if (has_v4 & rdists->has_vlpis) {
3675                 if (its_init_vpe_domain() ||
3676                     its_init_v4(parent_domain, &its_vpe_domain_ops)) {
3677                         rdists->has_vlpis = false;
3678                         pr_err("ITS: Disabling GICv4 support\n");
3679                 }
3680         }
3681
3682         register_syscore_ops(&its_syscore_ops);
3683
3684         return 0;
3685 }