drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "amdgpu.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  51                              struct ttm_mem_reg *mem, unsigned num_pages,
  52                              uint64_t offset, unsigned window,
  53                              struct amdgpu_ring *ring,
  54                              uint64_t *addr);
  55
  56 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  57 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  58
  59 /*
  60  * Global memory.
  61  */
  62 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  63 {
  64         return ttm_mem_global_init(ref->object);
  65 }
  66
  67 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  68 {
  69         ttm_mem_global_release(ref->object);
  70 }
  71
  72 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  73 {
  74         struct drm_global_reference *global_ref;
  75         struct amdgpu_ring *ring;
  76         struct amd_sched_rq *rq;
  77         int r;
  78
  79         adev->mman.mem_global_referenced = false;
  80         global_ref = &adev->mman.mem_global_ref;
  81         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  82         global_ref->size = sizeof(struct ttm_mem_global);
  83         global_ref->init = &amdgpu_ttm_mem_global_init;
  84         global_ref->release = &amdgpu_ttm_mem_global_release;
  85         r = drm_global_item_ref(global_ref);
  86         if (r) {
  87                 DRM_ERROR("Failed setting up TTM memory accounting "
  88                           "subsystem.\n");
  89                 goto error_mem;
  90         }
  91
  92         adev->mman.bo_global_ref.mem_glob =
  93                 adev->mman.mem_global_ref.object;
  94         global_ref = &adev->mman.bo_global_ref.ref;
  95         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  96         global_ref->size = sizeof(struct ttm_bo_global);
  97         global_ref->init = &ttm_bo_global_init;
  98         global_ref->release = &ttm_bo_global_release;
  99         r = drm_global_item_ref(global_ref);
 100         if (r) {
 101                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 102                 goto error_bo;
 103         }
 104
 105         mutex_init(&adev->mman.gtt_window_lock);
 106
 107         ring = adev->mman.buffer_funcs_ring;
 108         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 109         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 110                                   rq, amdgpu_sched_jobs);
 111         if (r) {
 112                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 113                 goto error_entity;
 114         }
 115
 116         adev->mman.mem_global_referenced = true;
 117
 118         return 0;
 119
 120 error_entity:
 121         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 122 error_bo:
 123         drm_global_item_unref(&adev->mman.mem_global_ref);
 124 error_mem:
 125         return r;
 126 }
 127
 128 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 129 {
 130         if (adev->mman.mem_global_referenced) {
 131                 amd_sched_entity_fini(adev->mman.entity.sched,
 132                                       &adev->mman.entity);
 133                 mutex_destroy(&adev->mman.gtt_window_lock);
 134                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 135                 drm_global_item_unref(&adev->mman.mem_global_ref);
 136                 adev->mman.mem_global_referenced = false;
 137         }
 138 }
 139
 140 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 141 {
 142         return 0;
 143 }
 144
 145 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 146                                 struct ttm_mem_type_manager *man)
 147 {
 148         struct amdgpu_device *adev;
 149
 150         adev = amdgpu_ttm_adev(bdev);
 151
 152         switch (type) {
 153         case TTM_PL_SYSTEM:
 154                 /* System memory */
 155                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 156                 man->available_caching = TTM_PL_MASK_CACHING;
 157                 man->default_caching = TTM_PL_FLAG_CACHED;
 158                 break;
 159         case TTM_PL_TT:
 160                 man->func = &amdgpu_gtt_mgr_func;
 161                 man->gpu_offset = adev->mc.gart_start;
 162                 man->available_caching = TTM_PL_MASK_CACHING;
 163                 man->default_caching = TTM_PL_FLAG_CACHED;
 164                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 165                 break;
 166         case TTM_PL_VRAM:
 167                 /* "On-card" video ram */
 168                 man->func = &amdgpu_vram_mgr_func;
 169                 man->gpu_offset = adev->mc.vram_start;
 170                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 171                              TTM_MEMTYPE_FLAG_MAPPABLE;
 172                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 173                 man->default_caching = TTM_PL_FLAG_WC;
 174                 break;
 175         case AMDGPU_PL_GDS:
 176         case AMDGPU_PL_GWS:
 177         case AMDGPU_PL_OA:
 178                 /* On-chip GDS memory*/
 179                 man->func = &ttm_bo_manager_func;
 180                 man->gpu_offset = 0;
 181                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 182                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 183                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 184                 break;
 185         default:
 186                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 187                 return -EINVAL;
 188         }
 189         return 0;
 190 }
 191
 192 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 193                                 struct ttm_placement *placement)
 194 {
 195         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 196         struct amdgpu_bo *abo;
 197         static const struct ttm_place placements = {
 198                 .fpfn = 0,
 199                 .lpfn = 0,
 200                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 201         };
 202
 203         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 204                 placement->placement = &placements;
 205                 placement->busy_placement = &placements;
 206                 placement->num_placement = 1;
 207                 placement->num_busy_placement = 1;
 208                 return;
 209         }
 210         abo = container_of(bo, struct amdgpu_bo, tbo);
 211         switch (bo->mem.mem_type) {
 212         case TTM_PL_VRAM:
 213                 if (adev->mman.buffer_funcs &&
 214                     adev->mman.buffer_funcs_ring &&
 215                     adev->mman.buffer_funcs_ring->ready == false) {
 216                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 217                 } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 218                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 219                         unsigned fpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 220                         struct drm_mm_node *node = bo->mem.mm_node;
 221                         unsigned long pages_left;
 222
 223                         for (pages_left = bo->mem.num_pages;
 224                              pages_left;
 225                              pages_left -= node->size, node++) {
 226                                 if (node->start < fpfn)
 227                                         break;
 228                         }
 229
 230                         if (!pages_left)
 231                                 goto gtt;
 232
 233                         /* Try evicting to the CPU inaccessible part of VRAM
 234                          * first, but only set GTT as busy placement, so this
 235                          * BO will be evicted to GTT rather than causing other
 236                          * BOs to be evicted from VRAM
 237                          */
 238                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 239                                                          AMDGPU_GEM_DOMAIN_GTT);
 240                         abo->placements[0].fpfn = fpfn;
 241                         abo->placements[0].lpfn = 0;
 242                         abo->placement.busy_placement = &abo->placements[1];
 243                         abo->placement.num_busy_placement = 1;
 244                 } else {
 245 gtt:
 246                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 247                 }
 248                 break;
 249         case TTM_PL_TT:
 250         default:
 251                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 252         }
 253         *placement = abo->placement;
 254 }
 255
 256 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 257 {
 258         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
 259
 260         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 261                 return -EPERM;
 262         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 263                                           filp->private_data);
 264 }
 265
 266 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 267                              struct ttm_mem_reg *new_mem)
 268 {
 269         struct ttm_mem_reg *old_mem = &bo->mem;
 270
 271         BUG_ON(old_mem->mm_node != NULL);
 272         *old_mem = *new_mem;
 273         new_mem->mm_node = NULL;
 274 }
 275
 276 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 277                                     struct drm_mm_node *mm_node,
 278                                     struct ttm_mem_reg *mem)
 279 {
 280         uint64_t addr = 0;
 281
 282         if (mem->mem_type != TTM_PL_TT ||
 283             amdgpu_gtt_mgr_is_allocated(mem)) {
 284                 addr = mm_node->start << PAGE_SHIFT;
 285                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 286         }
 287         return addr;
 288 }
 289
 290 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 291                             bool evict, bool no_wait_gpu,
 292                             struct ttm_mem_reg *new_mem,
 293                             struct ttm_mem_reg *old_mem)
 294 {
 295         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 296         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 297
 298         struct drm_mm_node *old_mm, *new_mm;
 299         uint64_t old_start, old_size, new_start, new_size;
 300         unsigned long num_pages;
 301         struct dma_fence *fence = NULL;
 302         int r;
 303
 304         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 305
 306         if (!ring->ready) {
 307                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 308                 return -EINVAL;
 309         }
 310
 311         old_mm = old_mem->mm_node;
 312         old_size = old_mm->size;
 313         old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
 314
 315         new_mm = new_mem->mm_node;
 316         new_size = new_mm->size;
 317         new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
 318
 319         num_pages = new_mem->num_pages;
 320         mutex_lock(&adev->mman.gtt_window_lock);
 321         while (num_pages) {
 322                 unsigned long cur_pages = min(min(old_size, new_size),
 323                                               (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
 324                 uint64_t from = old_start, to = new_start;
 325                 struct dma_fence *next;
 326
 327                 if (old_mem->mem_type == TTM_PL_TT &&
 328                     !amdgpu_gtt_mgr_is_allocated(old_mem)) {
 329                         r = amdgpu_map_buffer(bo, old_mem, cur_pages,
 330                                               old_start, 0, ring, &from);
 331                         if (r)
 332                                 goto error;
 333                 }
 334
 335                 if (new_mem->mem_type == TTM_PL_TT &&
 336                     !amdgpu_gtt_mgr_is_allocated(new_mem)) {
 337                         r = amdgpu_map_buffer(bo, new_mem, cur_pages,
 338                                               new_start, 1, ring, &to);
 339                         if (r)
 340                                 goto error;
 341                 }
 342
 343                 r = amdgpu_copy_buffer(ring, from, to,
 344                                        cur_pages * PAGE_SIZE,
 345                                        bo->resv, &next, false, true);
 346                 if (r)
 347                         goto error;
 348
 349                 dma_fence_put(fence);
 350                 fence = next;
 351
 352                 num_pages -= cur_pages;
 353                 if (!num_pages)
 354                         break;
 355
 356                 old_size -= cur_pages;
 357                 if (!old_size) {
 358                         old_start = amdgpu_mm_node_addr(bo, ++old_mm, old_mem);
 359                         old_size = old_mm->size;
 360                 } else {
 361                         old_start += cur_pages * PAGE_SIZE;
 362                 }
 363
 364                 new_size -= cur_pages;
 365                 if (!new_size) {
 366                         new_start = amdgpu_mm_node_addr(bo, ++new_mm, new_mem);
 367                         new_size = new_mm->size;
 368                 } else {
 369                         new_start += cur_pages * PAGE_SIZE;
 370                 }
 371         }
 372         mutex_unlock(&adev->mman.gtt_window_lock);
 373
 374         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 375         dma_fence_put(fence);
 376         return r;
 377
 378 error:
 379         mutex_unlock(&adev->mman.gtt_window_lock);
 380
 381         if (fence)
 382                 dma_fence_wait(fence, false);
 383         dma_fence_put(fence);
 384         return r;
 385 }
 386
 387 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 388                                 bool evict, bool interruptible,
 389                                 bool no_wait_gpu,
 390                                 struct ttm_mem_reg *new_mem)
 391 {
 392         struct amdgpu_device *adev;
 393         struct ttm_mem_reg *old_mem = &bo->mem;
 394         struct ttm_mem_reg tmp_mem;
 395         struct ttm_place placements;
 396         struct ttm_placement placement;
 397         int r;
 398
 399         adev = amdgpu_ttm_adev(bo->bdev);
 400         tmp_mem = *new_mem;
 401         tmp_mem.mm_node = NULL;
 402         placement.num_placement = 1;
 403         placement.placement = &placements;
 404         placement.num_busy_placement = 1;
 405         placement.busy_placement = &placements;
 406         placements.fpfn = 0;
 407         placements.lpfn = 0;
 408         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 409         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 410                              interruptible, no_wait_gpu);
 411         if (unlikely(r)) {
 412                 return r;
 413         }
 414
 415         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 416         if (unlikely(r)) {
 417                 goto out_cleanup;
 418         }
 419
 420         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 421         if (unlikely(r)) {
 422                 goto out_cleanup;
 423         }
 424         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 425         if (unlikely(r)) {
 426                 goto out_cleanup;
 427         }
 428         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 429 out_cleanup:
 430         ttm_bo_mem_put(bo, &tmp_mem);
 431         return r;
 432 }
 433
 434 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 435                                 bool evict, bool interruptible,
 436                                 bool no_wait_gpu,
 437                                 struct ttm_mem_reg *new_mem)
 438 {
 439         struct amdgpu_device *adev;
 440         struct ttm_mem_reg *old_mem = &bo->mem;
 441         struct ttm_mem_reg tmp_mem;
 442         struct ttm_placement placement;
 443         struct ttm_place placements;
 444         int r;
 445
 446         adev = amdgpu_ttm_adev(bo->bdev);
 447         tmp_mem = *new_mem;
 448         tmp_mem.mm_node = NULL;
 449         placement.num_placement = 1;
 450         placement.placement = &placements;
 451         placement.num_busy_placement = 1;
 452         placement.busy_placement = &placements;
 453         placements.fpfn = 0;
 454         placements.lpfn = 0;
 455         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 456         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 457                              interruptible, no_wait_gpu);
 458         if (unlikely(r)) {
 459                 return r;
 460         }
 461         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 462         if (unlikely(r)) {
 463                 goto out_cleanup;
 464         }
 465         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 466         if (unlikely(r)) {
 467                 goto out_cleanup;
 468         }
 469 out_cleanup:
 470         ttm_bo_mem_put(bo, &tmp_mem);
 471         return r;
 472 }
 473
 474 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 475                         bool evict, bool interruptible,
 476                         bool no_wait_gpu,
 477                         struct ttm_mem_reg *new_mem)
 478 {
 479         struct amdgpu_device *adev;
 480         struct amdgpu_bo *abo;
 481         struct ttm_mem_reg *old_mem = &bo->mem;
 482         int r;
 483
 484         /* Can't move a pinned BO */
 485         abo = container_of(bo, struct amdgpu_bo, tbo);
 486         if (WARN_ON_ONCE(abo->pin_count > 0))
 487                 return -EINVAL;
 488
 489         adev = amdgpu_ttm_adev(bo->bdev);
 490
 491         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 492                 amdgpu_move_null(bo, new_mem);
 493                 return 0;
 494         }
 495         if ((old_mem->mem_type == TTM_PL_TT &&
 496              new_mem->mem_type == TTM_PL_SYSTEM) ||
 497             (old_mem->mem_type == TTM_PL_SYSTEM &&
 498              new_mem->mem_type == TTM_PL_TT)) {
 499                 /* bind is enough */
 500                 amdgpu_move_null(bo, new_mem);
 501                 return 0;
 502         }
 503         if (adev->mman.buffer_funcs == NULL ||
 504             adev->mman.buffer_funcs_ring == NULL ||
 505             !adev->mman.buffer_funcs_ring->ready) {
 506                 /* use memcpy */
 507                 goto memcpy;
 508         }
 509
 510         if (old_mem->mem_type == TTM_PL_VRAM &&
 511             new_mem->mem_type == TTM_PL_SYSTEM) {
 512                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 513                                         no_wait_gpu, new_mem);
 514         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 515                    new_mem->mem_type == TTM_PL_VRAM) {
 516                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 517                                             no_wait_gpu, new_mem);
 518         } else {
 519                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 520         }
 521
 522         if (r) {
 523 memcpy:
 524                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 525                 if (r) {
 526                         return r;
 527                 }
 528         }
 529
 530         if (bo->type == ttm_bo_type_device &&
 531             new_mem->mem_type == TTM_PL_VRAM &&
 532             old_mem->mem_type != TTM_PL_VRAM) {
 533                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 534                  * accesses the BO after it's moved.
 535                  */
 536                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 537         }
 538
 539         /* update statistics */
 540         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 541         return 0;
 542 }
 543
 544 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 545 {
 546         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 547         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 548
 549         mem->bus.addr = NULL;
 550         mem->bus.offset = 0;
 551         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 552         mem->bus.base = 0;
 553         mem->bus.is_iomem = false;
 554         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 555                 return -EINVAL;
 556         switch (mem->mem_type) {
 557         case TTM_PL_SYSTEM:
 558                 /* system memory */
 559                 return 0;
 560         case TTM_PL_TT:
 561                 break;
 562         case TTM_PL_VRAM:
 563                 mem->bus.offset = mem->start << PAGE_SHIFT;
 564                 /* check if it's visible */
 565                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 566                         return -EINVAL;
 567                 mem->bus.base = adev->mc.aper_base;
 568                 mem->bus.is_iomem = true;
 569                 break;
 570         default:
 571                 return -EINVAL;
 572         }
 573         return 0;
 574 }
 575
 576 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 577 {
 578 }
 579
 580 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 581                                            unsigned long page_offset)
 582 {
 583         struct drm_mm_node *mm = bo->mem.mm_node;
 584         uint64_t size = mm->size;
 585         uint64_t offset = page_offset;
 586
 587         page_offset = do_div(offset, size);
 588         mm += offset;
 589         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
 590 }
 591
 592 /*
 593  * TTM backend functions.
 594  */
 595 struct amdgpu_ttm_gup_task_list {
 596         struct list_head        list;
 597         struct task_struct      *task;
 598 };
 599
 600 struct amdgpu_ttm_tt {
 601         struct ttm_dma_tt       ttm;
 602         struct amdgpu_device    *adev;
 603         u64                     offset;
 604         uint64_t                userptr;
 605         struct mm_struct        *usermm;
 606         uint32_t                userflags;
 607         spinlock_t              guptasklock;
 608         struct list_head        guptasks;
 609         atomic_t                mmu_invalidations;
 610         struct list_head        list;
 611 };
 612
 613 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 614 {
 615         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 616         unsigned int flags = 0;
 617         unsigned pinned = 0;
 618         int r;
 619
 620         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 621                 flags |= FOLL_WRITE;
 622
 623         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 624                 /* check that we only use anonymous memory
 625                    to prevent problems with writeback */
 626                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 627                 struct vm_area_struct *vma;
 628
 629                 vma = find_vma(gtt->usermm, gtt->userptr);
 630                 if (!vma || vma->vm_file || vma->vm_end < end)
 631                         return -EPERM;
 632         }
 633
 634         do {
 635                 unsigned num_pages = ttm->num_pages - pinned;
 636                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 637                 struct page **p = pages + pinned;
 638                 struct amdgpu_ttm_gup_task_list guptask;
 639
 640                 guptask.task = current;
 641                 spin_lock(&gtt->guptasklock);
 642                 list_add(&guptask.list, &gtt->guptasks);
 643                 spin_unlock(&gtt->guptasklock);
 644
 645                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 646
 647                 spin_lock(&gtt->guptasklock);
 648                 list_del(&guptask.list);
 649                 spin_unlock(&gtt->guptasklock);
 650
 651                 if (r < 0)
 652                         goto release_pages;
 653
 654                 pinned += r;
 655
 656         } while (pinned < ttm->num_pages);
 657
 658         return 0;
 659
 660 release_pages:
 661         release_pages(pages, pinned, 0);
 662         return r;
 663 }
 664
 665 /* prepare the sg table with the user pages */
 666 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 667 {
 668         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 669         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 670         unsigned nents;
 671         int r;
 672
 673         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 674         enum dma_data_direction direction = write ?
 675                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 676
 677         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 678                                       ttm->num_pages << PAGE_SHIFT,
 679                                       GFP_KERNEL);
 680         if (r)
 681                 goto release_sg;
 682
 683         r = -ENOMEM;
 684         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 685         if (nents != ttm->sg->nents)
 686                 goto release_sg;
 687
 688         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 689                                          gtt->ttm.dma_address, ttm->num_pages);
 690
 691         return 0;
 692
 693 release_sg:
 694         kfree(ttm->sg);
 695         return r;
 696 }
 697
 698 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 699 {
 700         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 701         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 702         struct sg_page_iter sg_iter;
 703
 704         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 705         enum dma_data_direction direction = write ?
 706                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 707
 708         /* double check that we don't free the table twice */
 709         if (!ttm->sg->sgl)
 710                 return;
 711
 712         /* free the sg table and pages again */
 713         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 714
 715         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 716                 struct page *page = sg_page_iter_page(&sg_iter);
 717                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 718                         set_page_dirty(page);
 719
 720                 mark_page_accessed(page);
 721                 put_page(page);
 722         }
 723
 724         sg_free_table(ttm->sg);
 725 }
 726
 727 static int amdgpu_ttm_do_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
 728 {
 729         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 730         uint64_t flags;
 731         int r;
 732
 733         spin_lock(&gtt->adev->gtt_list_lock);
 734         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, mem);
 735         gtt->offset = (u64)mem->start << PAGE_SHIFT;
 736         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 737                 ttm->pages, gtt->ttm.dma_address, flags);
 738
 739         if (r) {
 740                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 741                           ttm->num_pages, gtt->offset);
 742                 goto error_gart_bind;
 743         }
 744
 745         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 746 error_gart_bind:
 747         spin_unlock(&gtt->adev->gtt_list_lock);
 748         return r;
 749
 750 }
 751
 752 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 753                                    struct ttm_mem_reg *bo_mem)
 754 {
 755         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 756         int r;
 757
 758         if (gtt->userptr) {
 759                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 760                 if (r) {
 761                         DRM_ERROR("failed to pin userptr\n");
 762                         return r;
 763                 }
 764         }
 765         if (!ttm->num_pages) {
 766                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 767                      ttm->num_pages, bo_mem, ttm);
 768         }
 769
 770         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 771             bo_mem->mem_type == AMDGPU_PL_GWS ||
 772             bo_mem->mem_type == AMDGPU_PL_OA)
 773                 return -EINVAL;
 774
 775         if (amdgpu_gtt_mgr_is_allocated(bo_mem))
 776             r = amdgpu_ttm_do_bind(ttm, bo_mem);
 777
 778         return r;
 779 }
 780
 781 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 782 {
 783         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 784
 785         return gtt && !list_empty(&gtt->list);
 786 }
 787
 788 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 789 {
 790         struct ttm_tt *ttm = bo->ttm;
 791         int r;
 792
 793         if (!ttm || amdgpu_ttm_is_bound(ttm))
 794                 return 0;
 795
 796         r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
 797                                  NULL, bo_mem);
 798         if (r) {
 799                 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
 800                 return r;
 801         }
 802
 803         return amdgpu_ttm_do_bind(ttm, bo_mem);
 804 }
 805
 806 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 807 {
 808         struct amdgpu_ttm_tt *gtt, *tmp;
 809         struct ttm_mem_reg bo_mem;
 810         uint64_t flags;
 811         int r;
 812
 813         bo_mem.mem_type = TTM_PL_TT;
 814         spin_lock(&adev->gtt_list_lock);
 815         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 816                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 817                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 818                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 819                                      flags);
 820                 if (r) {
 821                         spin_unlock(&adev->gtt_list_lock);
 822                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 823                                   gtt->ttm.ttm.num_pages, gtt->offset);
 824                         return r;
 825                 }
 826         }
 827         spin_unlock(&adev->gtt_list_lock);
 828         return 0;
 829 }
 830
 831 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 832 {
 833         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 834         int r;
 835
 836         if (gtt->userptr)
 837                 amdgpu_ttm_tt_unpin_userptr(ttm);
 838
 839         if (!amdgpu_ttm_is_bound(ttm))
 840                 return 0;
 841
 842         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 843         spin_lock(&gtt->adev->gtt_list_lock);
 844         r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 845         if (r) {
 846                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
 847                           gtt->ttm.ttm.num_pages, gtt->offset);
 848                 goto error_unbind;
 849         }
 850         list_del_init(&gtt->list);
 851 error_unbind:
 852         spin_unlock(&gtt->adev->gtt_list_lock);
 853         return r;
 854 }
 855
 856 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 857 {
 858         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 859
 860         ttm_dma_tt_fini(&gtt->ttm);
 861         kfree(gtt);
 862 }
 863
 864 static struct ttm_backend_func amdgpu_backend_func = {
 865         .bind = &amdgpu_ttm_backend_bind,
 866         .unbind = &amdgpu_ttm_backend_unbind,
 867         .destroy = &amdgpu_ttm_backend_destroy,
 868 };
 869
 870 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 871                                     unsigned long size, uint32_t page_flags,
 872                                     struct page *dummy_read_page)
 873 {
 874         struct amdgpu_device *adev;
 875         struct amdgpu_ttm_tt *gtt;
 876
 877         adev = amdgpu_ttm_adev(bdev);
 878
 879         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 880         if (gtt == NULL) {
 881                 return NULL;
 882         }
 883         gtt->ttm.ttm.func = &amdgpu_backend_func;
 884         gtt->adev = adev;
 885         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 886                 kfree(gtt);
 887                 return NULL;
 888         }
 889         INIT_LIST_HEAD(&gtt->list);
 890         return &gtt->ttm.ttm;
 891 }
 892
 893 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 894 {
 895         struct amdgpu_device *adev;
 896         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 897         unsigned i;
 898         int r;
 899         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 900
 901         if (ttm->state != tt_unpopulated)
 902                 return 0;
 903
 904         if (gtt && gtt->userptr) {
 905                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 906                 if (!ttm->sg)
 907                         return -ENOMEM;
 908
 909                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 910                 ttm->state = tt_unbound;
 911                 return 0;
 912         }
 913
 914         if (slave && ttm->sg) {
 915                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 916                                                  gtt->ttm.dma_address, ttm->num_pages);
 917                 ttm->state = tt_unbound;
 918                 return 0;
 919         }
 920
 921         adev = amdgpu_ttm_adev(ttm->bdev);
 922
 923 #ifdef CONFIG_SWIOTLB
 924         if (swiotlb_nr_tbl()) {
 925                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 926         }
 927 #endif
 928
 929         r = ttm_pool_populate(ttm);
 930         if (r) {
 931                 return r;
 932         }
 933
 934         for (i = 0; i < ttm->num_pages; i++) {
 935                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 936                                                        0, PAGE_SIZE,
 937                                                        PCI_DMA_BIDIRECTIONAL);
 938                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 939                         while (i--) {
 940                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 941                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 942                                 gtt->ttm.dma_address[i] = 0;
 943                         }
 944                         ttm_pool_unpopulate(ttm);
 945                         return -EFAULT;
 946                 }
 947         }
 948         return 0;
 949 }
 950
 951 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 952 {
 953         struct amdgpu_device *adev;
 954         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 955         unsigned i;
 956         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 957
 958         if (gtt && gtt->userptr) {
 959                 kfree(ttm->sg);
 960                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 961                 return;
 962         }
 963
 964         if (slave)
 965                 return;
 966
 967         adev = amdgpu_ttm_adev(ttm->bdev);
 968
 969 #ifdef CONFIG_SWIOTLB
 970         if (swiotlb_nr_tbl()) {
 971                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 972                 return;
 973         }
 974 #endif
 975
 976         for (i = 0; i < ttm->num_pages; i++) {
 977                 if (gtt->ttm.dma_address[i]) {
 978                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 979                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 980                 }
 981         }
 982
 983         ttm_pool_unpopulate(ttm);
 984 }
 985
 986 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 987                               uint32_t flags)
 988 {
 989         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 990
 991         if (gtt == NULL)
 992                 return -EINVAL;
 993
 994         gtt->userptr = addr;
 995         gtt->usermm = current->mm;
 996         gtt->userflags = flags;
 997         spin_lock_init(&gtt->guptasklock);
 998         INIT_LIST_HEAD(&gtt->guptasks);
 999         atomic_set(&gtt->mmu_invalidations, 0);
1000
1001         return 0;
1002 }
1003
1004 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1005 {
1006         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1007
1008         if (gtt == NULL)
1009                 return NULL;
1010
1011         return gtt->usermm;
1012 }
1013
1014 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1015                                   unsigned long end)
1016 {
1017         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1018         struct amdgpu_ttm_gup_task_list *entry;
1019         unsigned long size;
1020
1021         if (gtt == NULL || !gtt->userptr)
1022                 return false;
1023
1024         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1025         if (gtt->userptr > end || gtt->userptr + size <= start)
1026                 return false;
1027
1028         spin_lock(&gtt->guptasklock);
1029         list_for_each_entry(entry, &gtt->guptasks, list) {
1030                 if (entry->task == current) {
1031                         spin_unlock(&gtt->guptasklock);
1032                         return false;
1033                 }
1034         }
1035         spin_unlock(&gtt->guptasklock);
1036
1037         atomic_inc(&gtt->mmu_invalidations);
1038
1039         return true;
1040 }
1041
1042 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1043                                        int *last_invalidated)
1044 {
1045         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1046         int prev_invalidated = *last_invalidated;
1047
1048         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1049         return prev_invalidated != *last_invalidated;
1050 }
1051
1052 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1053 {
1054         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1055
1056         if (gtt == NULL)
1057                 return false;
1058
1059         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1060 }
1061
1062 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1063                                  struct ttm_mem_reg *mem)
1064 {
1065         uint64_t flags = 0;
1066
1067         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1068                 flags |= AMDGPU_PTE_VALID;
1069
1070         if (mem && mem->mem_type == TTM_PL_TT) {
1071                 flags |= AMDGPU_PTE_SYSTEM;
1072
1073                 if (ttm->caching_state == tt_cached)
1074                         flags |= AMDGPU_PTE_SNOOPED;
1075         }
1076
1077         flags |= adev->gart.gart_pte_flags;
1078         flags |= AMDGPU_PTE_READABLE;
1079
1080         if (!amdgpu_ttm_tt_is_readonly(ttm))
1081                 flags |= AMDGPU_PTE_WRITEABLE;
1082
1083         return flags;
1084 }
1085
1086 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1087                                             const struct ttm_place *place)
1088 {
1089         unsigned long num_pages = bo->mem.num_pages;
1090         struct drm_mm_node *node = bo->mem.mm_node;
1091
1092         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1093                 return ttm_bo_eviction_valuable(bo, place);
1094
1095         switch (bo->mem.mem_type) {
1096         case TTM_PL_TT:
1097                 return true;
1098
1099         case TTM_PL_VRAM:
1100                 /* Check each drm MM node individually */
1101                 while (num_pages) {
1102                         if (place->fpfn < (node->start + node->size) &&
1103                             !(place->lpfn && place->lpfn <= node->start))
1104                                 return true;
1105
1106                         num_pages -= node->size;
1107                         ++node;
1108                 }
1109                 break;
1110
1111         default:
1112                 break;
1113         }
1114
1115         return ttm_bo_eviction_valuable(bo, place);
1116 }
1117
1118 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1119                                     unsigned long offset,
1120                                     void *buf, int len, int write)
1121 {
1122         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
1123         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1124         struct drm_mm_node *nodes = abo->tbo.mem.mm_node;
1125         uint32_t value = 0;
1126         int ret = 0;
1127         uint64_t pos;
1128         unsigned long flags;
1129
1130         if (bo->mem.mem_type != TTM_PL_VRAM)
1131                 return -EIO;
1132
1133         while (offset >= (nodes->size << PAGE_SHIFT)) {
1134                 offset -= nodes->size << PAGE_SHIFT;
1135                 ++nodes;
1136         }
1137         pos = (nodes->start << PAGE_SHIFT) + offset;
1138
1139         while (len && pos < adev->mc.mc_vram_size) {
1140                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1141                 uint32_t bytes = 4 - (pos & 3);
1142                 uint32_t shift = (pos & 3) * 8;
1143                 uint32_t mask = 0xffffffff << shift;
1144
1145                 if (len < bytes) {
1146                         mask &= 0xffffffff >> (bytes - len) * 8;
1147                         bytes = len;
1148                 }
1149
1150                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1151                 WREG32(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1152                 WREG32(mmMM_INDEX_HI, aligned_pos >> 31);
1153                 if (!write || mask != 0xffffffff)
1154                         value = RREG32(mmMM_DATA);
1155                 if (write) {
1156                         value &= ~mask;
1157                         value |= (*(uint32_t *)buf << shift) & mask;
1158                         WREG32(mmMM_DATA, value);
1159                 }
1160                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1161                 if (!write) {
1162                         value = (value & mask) >> shift;
1163                         memcpy(buf, &value, bytes);
1164                 }
1165
1166                 ret += bytes;
1167                 buf = (uint8_t *)buf + bytes;
1168                 pos += bytes;
1169                 len -= bytes;
1170                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1171                         ++nodes;
1172                         pos = (nodes->start << PAGE_SHIFT);
1173                 }
1174         }
1175
1176         return ret;
1177 }
1178
1179 static struct ttm_bo_driver amdgpu_bo_driver = {
1180         .ttm_tt_create = &amdgpu_ttm_tt_create,
1181         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1182         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1183         .invalidate_caches = &amdgpu_invalidate_caches,
1184         .init_mem_type = &amdgpu_init_mem_type,
1185         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1186         .evict_flags = &amdgpu_evict_flags,
1187         .move = &amdgpu_bo_move,
1188         .verify_access = &amdgpu_verify_access,
1189         .move_notify = &amdgpu_bo_move_notify,
1190         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1191         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1192         .io_mem_free = &amdgpu_ttm_io_mem_free,
1193         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1194         .access_memory = &amdgpu_ttm_access_memory
1195 };
1196
1197 int amdgpu_ttm_init(struct amdgpu_device *adev)
1198 {
1199         uint64_t gtt_size;
1200         int r;
1201         u64 vis_vram_limit;
1202
1203         r = amdgpu_ttm_global_init(adev);
1204         if (r) {
1205                 return r;
1206         }
1207         /* No others user of address space so set it to 0 */
1208         r = ttm_bo_device_init(&adev->mman.bdev,
1209                                adev->mman.bo_global_ref.ref.object,
1210                                &amdgpu_bo_driver,
1211                                adev->ddev->anon_inode->i_mapping,
1212                                DRM_FILE_PAGE_OFFSET,
1213                                adev->need_dma32);
1214         if (r) {
1215                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1216                 return r;
1217         }
1218         adev->mman.initialized = true;
1219         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1220                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1221         if (r) {
1222                 DRM_ERROR("Failed initializing VRAM heap.\n");
1223                 return r;
1224         }
1225
1226         /* Reduce size of CPU-visible VRAM if requested */
1227         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1228         if (amdgpu_vis_vram_limit > 0 &&
1229             vis_vram_limit <= adev->mc.visible_vram_size)
1230                 adev->mc.visible_vram_size = vis_vram_limit;
1231
1232         /* Change the size here instead of the init above so only lpfn is affected */
1233         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1234
1235         r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
1236                                     AMDGPU_GEM_DOMAIN_VRAM,
1237                                     &adev->stollen_vga_memory,
1238                                     NULL, NULL);
1239         if (r)
1240                 return r;
1241         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1242                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1243
1244         if (amdgpu_gtt_size == -1)
1245                 gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1246                                adev->mc.mc_vram_size);
1247         else
1248                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1249         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1250         if (r) {
1251                 DRM_ERROR("Failed initializing GTT heap.\n");
1252                 return r;
1253         }
1254         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1255                  (unsigned)(gtt_size / (1024 * 1024)));
1256
1257         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1258         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1259         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1260         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1261         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1262         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1263         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1264         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1265         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1266         /* GDS Memory */
1267         if (adev->gds.mem.total_size) {
1268                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1269                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1270                 if (r) {
1271                         DRM_ERROR("Failed initializing GDS heap.\n");
1272                         return r;
1273                 }
1274         }
1275
1276         /* GWS */
1277         if (adev->gds.gws.total_size) {
1278                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1279                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1280                 if (r) {
1281                         DRM_ERROR("Failed initializing gws heap.\n");
1282                         return r;
1283                 }
1284         }
1285
1286         /* OA */
1287         if (adev->gds.oa.total_size) {
1288                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1289                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1290                 if (r) {
1291                         DRM_ERROR("Failed initializing oa heap.\n");
1292                         return r;
1293                 }
1294         }
1295
1296         r = amdgpu_ttm_debugfs_init(adev);
1297         if (r) {
1298                 DRM_ERROR("Failed to init debugfs\n");
1299                 return r;
1300         }
1301         return 0;
1302 }
1303
1304 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1305 {
1306         int r;
1307
1308         if (!adev->mman.initialized)
1309                 return;
1310         amdgpu_ttm_debugfs_fini(adev);
1311         if (adev->stollen_vga_memory) {
1312                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, true);
1313                 if (r == 0) {
1314                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1315                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1316                 }
1317                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1318         }
1319         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1320         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1321         if (adev->gds.mem.total_size)
1322                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1323         if (adev->gds.gws.total_size)
1324                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1325         if (adev->gds.oa.total_size)
1326                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1327         ttm_bo_device_release(&adev->mman.bdev);
1328         amdgpu_gart_fini(adev);
1329         amdgpu_ttm_global_fini(adev);
1330         adev->mman.initialized = false;
1331         DRM_INFO("amdgpu: ttm finalized\n");
1332 }
1333
1334 /* this should only be called at bootup or when userspace
1335  * isn't running */
1336 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1337 {
1338         struct ttm_mem_type_manager *man;
1339
1340         if (!adev->mman.initialized)
1341                 return;
1342
1343         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1344         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1345         man->size = size >> PAGE_SHIFT;
1346 }
1347
1348 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1349 {
1350         struct drm_file *file_priv;
1351         struct amdgpu_device *adev;
1352
1353         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1354                 return -EINVAL;
1355
1356         file_priv = filp->private_data;
1357         adev = file_priv->minor->dev->dev_private;
1358         if (adev == NULL)
1359                 return -EINVAL;
1360
1361         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1362 }
1363
1364 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1365                              struct ttm_mem_reg *mem, unsigned num_pages,
1366                              uint64_t offset, unsigned window,
1367                              struct amdgpu_ring *ring,
1368                              uint64_t *addr)
1369 {
1370         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1371         struct amdgpu_device *adev = ring->adev;
1372         struct ttm_tt *ttm = bo->ttm;
1373         struct amdgpu_job *job;
1374         unsigned num_dw, num_bytes;
1375         dma_addr_t *dma_address;
1376         struct dma_fence *fence;
1377         uint64_t src_addr, dst_addr;
1378         uint64_t flags;
1379         int r;
1380
1381         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1382                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1383
1384         *addr = adev->mc.gart_start;
1385         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1386                 AMDGPU_GPU_PAGE_SIZE;
1387
1388         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1389         while (num_dw & 0x7)
1390                 num_dw++;
1391
1392         num_bytes = num_pages * 8;
1393
1394         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1395         if (r)
1396                 return r;
1397
1398         src_addr = num_dw * 4;
1399         src_addr += job->ibs[0].gpu_addr;
1400
1401         dst_addr = adev->gart.table_addr;
1402         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1403         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1404                                 dst_addr, num_bytes);
1405
1406         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1407         WARN_ON(job->ibs[0].length_dw > num_dw);
1408
1409         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1410         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1411         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1412                             &job->ibs[0].ptr[num_dw]);
1413         if (r)
1414                 goto error_free;
1415
1416         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1417                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1418         if (r)
1419                 goto error_free;
1420
1421         dma_fence_put(fence);
1422
1423         return r;
1424
1425 error_free:
1426         amdgpu_job_free(job);
1427         return r;
1428 }
1429
1430 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1431                        uint64_t dst_offset, uint32_t byte_count,
1432                        struct reservation_object *resv,
1433                        struct dma_fence **fence, bool direct_submit,
1434                        bool vm_needs_flush)
1435 {
1436         struct amdgpu_device *adev = ring->adev;
1437         struct amdgpu_job *job;
1438
1439         uint32_t max_bytes;
1440         unsigned num_loops, num_dw;
1441         unsigned i;
1442         int r;
1443
1444         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1445         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1446         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1447
1448         /* for IB padding */
1449         while (num_dw & 0x7)
1450                 num_dw++;
1451
1452         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1453         if (r)
1454                 return r;
1455
1456         job->vm_needs_flush = vm_needs_flush;
1457         if (resv) {
1458                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1459                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1460                 if (r) {
1461                         DRM_ERROR("sync failed (%d).\n", r);
1462                         goto error_free;
1463                 }
1464         }
1465
1466         for (i = 0; i < num_loops; i++) {
1467                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1468
1469                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1470                                         dst_offset, cur_size_in_bytes);
1471
1472                 src_offset += cur_size_in_bytes;
1473                 dst_offset += cur_size_in_bytes;
1474                 byte_count -= cur_size_in_bytes;
1475         }
1476
1477         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1478         WARN_ON(job->ibs[0].length_dw > num_dw);
1479         if (direct_submit) {
1480                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1481                                        NULL, fence);
1482                 job->fence = dma_fence_get(*fence);
1483                 if (r)
1484                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1485                 amdgpu_job_free(job);
1486         } else {
1487                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1488                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1489                 if (r)
1490                         goto error_free;
1491         }
1492
1493         return r;
1494
1495 error_free:
1496         amdgpu_job_free(job);
1497         return r;
1498 }
1499
1500 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1501                        uint64_t src_data,
1502                        struct reservation_object *resv,
1503                        struct dma_fence **fence)
1504 {
1505         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1506         /* max_bytes applies to SDMA_OP_PTEPDE as well as SDMA_OP_CONST_FILL*/
1507         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1508         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1509
1510         struct drm_mm_node *mm_node;
1511         unsigned long num_pages;
1512         unsigned int num_loops, num_dw;
1513
1514         struct amdgpu_job *job;
1515         int r;
1516
1517         if (!ring->ready) {
1518                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1519                 return -EINVAL;
1520         }
1521
1522         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1523                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1524                 if (r)
1525                         return r;
1526         }
1527
1528         num_pages = bo->tbo.num_pages;
1529         mm_node = bo->tbo.mem.mm_node;
1530         num_loops = 0;
1531         while (num_pages) {
1532                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1533
1534                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1535                 num_pages -= mm_node->size;
1536                 ++mm_node;
1537         }
1538
1539         /* 10 double words for each SDMA_OP_PTEPDE cmd */
1540         num_dw = num_loops * 10;
1541
1542         /* for IB padding */
1543         num_dw += 64;
1544
1545         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1546         if (r)
1547                 return r;
1548
1549         if (resv) {
1550                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1551                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1552                 if (r) {
1553                         DRM_ERROR("sync failed (%d).\n", r);
1554                         goto error_free;
1555                 }
1556         }
1557
1558         num_pages = bo->tbo.num_pages;
1559         mm_node = bo->tbo.mem.mm_node;
1560
1561         while (num_pages) {
1562                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1563                 uint64_t dst_addr;
1564
1565                 WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8");
1566
1567                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1568                 while (byte_count) {
1569                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1570
1571                         amdgpu_vm_set_pte_pde(adev, &job->ibs[0],
1572                                         dst_addr, 0,
1573                                         cur_size_in_bytes >> 3, 0,
1574                                         src_data);
1575
1576                         dst_addr += cur_size_in_bytes;
1577                         byte_count -= cur_size_in_bytes;
1578                 }
1579
1580                 num_pages -= mm_node->size;
1581                 ++mm_node;
1582         }
1583
1584         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1585         WARN_ON(job->ibs[0].length_dw > num_dw);
1586         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1587                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1588         if (r)
1589                 goto error_free;
1590
1591         return 0;
1592
1593 error_free:
1594         amdgpu_job_free(job);
1595         return r;
1596 }
1597
1598 #if defined(CONFIG_DEBUG_FS)
1599
1600 extern void amdgpu_gtt_mgr_print(struct seq_file *m, struct ttm_mem_type_manager
1601                                  *man);
1602 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1603 {
1604         struct drm_info_node *node = (struct drm_info_node *)m->private;
1605         unsigned ttm_pl = *(int *)node->info_ent->data;
1606         struct drm_device *dev = node->minor->dev;
1607         struct amdgpu_device *adev = dev->dev_private;
1608         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1609         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1610         struct drm_printer p = drm_seq_file_printer(m);
1611
1612         spin_lock(&glob->lru_lock);
1613         drm_mm_print(mm, &p);
1614         spin_unlock(&glob->lru_lock);
1615         switch (ttm_pl) {
1616         case TTM_PL_VRAM:
1617                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1618                            adev->mman.bdev.man[ttm_pl].size,
1619                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1620                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1621                 break;
1622         case TTM_PL_TT:
1623                 amdgpu_gtt_mgr_print(m, &adev->mman.bdev.man[TTM_PL_TT]);
1624                 break;
1625         }
1626         return 0;
1627 }
1628
1629 static int ttm_pl_vram = TTM_PL_VRAM;
1630 static int ttm_pl_tt = TTM_PL_TT;
1631
1632 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1633         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1634         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1635         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1636 #ifdef CONFIG_SWIOTLB
1637         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1638 #endif
1639 };
1640
1641 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1642                                     size_t size, loff_t *pos)
1643 {
1644         struct amdgpu_device *adev = file_inode(f)->i_private;
1645         ssize_t result = 0;
1646         int r;
1647
1648         if (size & 0x3 || *pos & 0x3)
1649                 return -EINVAL;
1650
1651         if (*pos >= adev->mc.mc_vram_size)
1652                 return -ENXIO;
1653
1654         while (size) {
1655                 unsigned long flags;
1656                 uint32_t value;
1657
1658                 if (*pos >= adev->mc.mc_vram_size)
1659                         return result;
1660
1661                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1662                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1663                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1664                 value = RREG32(mmMM_DATA);
1665                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1666
1667                 r = put_user(value, (uint32_t *)buf);
1668                 if (r)
1669                         return r;
1670
1671                 result += 4;
1672                 buf += 4;
1673                 *pos += 4;
1674                 size -= 4;
1675         }
1676
1677         return result;
1678 }
1679
1680 static const struct file_operations amdgpu_ttm_vram_fops = {
1681         .owner = THIS_MODULE,
1682         .read = amdgpu_ttm_vram_read,
1683         .llseek = default_llseek
1684 };
1685
1686 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1687
1688 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1689                                    size_t size, loff_t *pos)
1690 {
1691         struct amdgpu_device *adev = file_inode(f)->i_private;
1692         ssize_t result = 0;
1693         int r;
1694
1695         while (size) {
1696                 loff_t p = *pos / PAGE_SIZE;
1697                 unsigned off = *pos & ~PAGE_MASK;
1698                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1699                 struct page *page;
1700                 void *ptr;
1701
1702                 if (p >= adev->gart.num_cpu_pages)
1703                         return result;
1704
1705                 page = adev->gart.pages[p];
1706                 if (page) {
1707                         ptr = kmap(page);
1708                         ptr += off;
1709
1710                         r = copy_to_user(buf, ptr, cur_size);
1711                         kunmap(adev->gart.pages[p]);
1712                 } else
1713                         r = clear_user(buf, cur_size);
1714
1715                 if (r)
1716                         return -EFAULT;
1717
1718                 result += cur_size;
1719                 buf += cur_size;
1720                 *pos += cur_size;
1721                 size -= cur_size;
1722         }
1723
1724         return result;
1725 }
1726
1727 static const struct file_operations amdgpu_ttm_gtt_fops = {
1728         .owner = THIS_MODULE,
1729         .read = amdgpu_ttm_gtt_read,
1730         .llseek = default_llseek
1731 };
1732
1733 #endif
1734
1735 #endif
1736
1737 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1738 {
1739 #if defined(CONFIG_DEBUG_FS)
1740         unsigned count;
1741
1742         struct drm_minor *minor = adev->ddev->primary;
1743         struct dentry *ent, *root = minor->debugfs_root;
1744
1745         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1746                                   adev, &amdgpu_ttm_vram_fops);
1747         if (IS_ERR(ent))
1748                 return PTR_ERR(ent);
1749         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1750         adev->mman.vram = ent;
1751
1752 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1753         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1754                                   adev, &amdgpu_ttm_gtt_fops);
1755         if (IS_ERR(ent))
1756                 return PTR_ERR(ent);
1757         i_size_write(ent->d_inode, adev->mc.gart_size);
1758         adev->mman.gtt = ent;
1759
1760 #endif
1761         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1762
1763 #ifdef CONFIG_SWIOTLB
1764         if (!swiotlb_nr_tbl())
1765                 --count;
1766 #endif
1767
1768         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1769 #else
1770
1771         return 0;
1772 #endif
1773 }
1774
1775 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1776 {
1777 #if defined(CONFIG_DEBUG_FS)
1778
1779         debugfs_remove(adev->mman.vram);
1780         adev->mman.vram = NULL;
1781
1782 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1783         debugfs_remove(adev->mman.gtt);
1784         adev->mman.gtt = NULL;
1785 #endif
1786
1787 #endif
1788 }