arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3328-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50
  51 / {
  52         compatible = "rockchip,rk3328";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 serial0 = &uart0;
  60                 serial1 = &uart1;
  61                 serial2 = &uart2;
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 ethernet0 = &gmac2io;
  67                 ethernet1 = &gmac2phy;
  68         };
  69
  70         cpus {
  71                 #address-cells = <2>;
  72                 #size-cells = <0>;
  73
  74                 cpu0: cpu@0 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53", "arm,armv8";
  77                         reg = <0x0 0x0>;
  78                         clocks = <&cru ARMCLK>;
  79                         enable-method = "psci";
  80                         next-level-cache = <&l2>;
  81                 };
  82
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53", "arm,armv8";
  86                         reg = <0x0 0x1>;
  87                         clocks = <&cru ARMCLK>;
  88                         enable-method = "psci";
  89                         next-level-cache = <&l2>;
  90                 };
  91
  92                 cpu2: cpu@2 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a53", "arm,armv8";
  95                         reg = <0x0 0x2>;
  96                         clocks = <&cru ARMCLK>;
  97                         enable-method = "psci";
  98                         next-level-cache = <&l2>;
  99                 };
 100
 101                 cpu3: cpu@3 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53", "arm,armv8";
 104                         reg = <0x0 0x3>;
 105                         clocks = <&cru ARMCLK>;
 106                         enable-method = "psci";
 107                         next-level-cache = <&l2>;
 108                 };
 109
 110                 l2: l2-cache0 {
 111                         compatible = "cache";
 112                 };
 113         };
 114
 115         amba {
 116                 compatible = "simple-bus";
 117                 #address-cells = <2>;
 118                 #size-cells = <2>;
 119                 ranges;
 120
 121                 dmac: dmac@ff1f0000 {
 122                         compatible = "arm,pl330", "arm,primecell";
 123                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 124                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 125                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 126                         clocks = <&cru ACLK_DMAC>;
 127                         clock-names = "apb_pclk";
 128                         #dma-cells = <1>;
 129                 };
 130         };
 131
 132         arm-pmu {
 133                 compatible = "arm,cortex-a53-pmu";
 134                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 135                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 136                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 137                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 138                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 139         };
 140
 141         psci {
 142                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 143                 method = "smc";
 144         };
 145
 146         timer {
 147                 compatible = "arm,armv8-timer";
 148                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 149                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 150                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 151                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 152         };
 153
 154         xin24m: xin24m {
 155                 compatible = "fixed-clock";
 156                 #clock-cells = <0>;
 157                 clock-frequency = <24000000>;
 158                 clock-output-names = "xin24m";
 159         };
 160
 161         grf: syscon@ff100000 {
 162                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 163                 reg = <0x0 0xff100000 0x0 0x1000>;
 164                 #address-cells = <1>;
 165                 #size-cells = <1>;
 166
 167                 power: power-controller {
 168                         compatible = "rockchip,rk3328-power-controller";
 169                         #power-domain-cells = <1>;
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172
 173                         pd_hevc@RK3328_PD_HEVC {
 174                                 reg = <RK3328_PD_HEVC>;
 175                         };
 176                         pd_video@RK3328_PD_VIDEO {
 177                                 reg = <RK3328_PD_VIDEO>;
 178                         };
 179                         pd_vpu@RK3328_PD_VPU {
 180                                 reg = <RK3328_PD_VPU>;
 181                         };
 182                 };
 183
 184                 reboot-mode {
 185                         compatible = "syscon-reboot-mode";
 186                         offset = <0x5c8>;
 187                         mode-normal = <BOOT_NORMAL>;
 188                         mode-recovery = <BOOT_RECOVERY>;
 189                         mode-bootloader = <BOOT_FASTBOOT>;
 190                         mode-loader = <BOOT_BL_DOWNLOAD>;
 191                 };
 192
 193         };
 194
 195         uart0: serial@ff110000 {
 196                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 197                 reg = <0x0 0xff110000 0x0 0x100>;
 198                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 200                 clock-names = "baudclk", "apb_pclk";
 201                 dmas = <&dmac 2>, <&dmac 3>;
 202                 #dma-cells = <2>;
 203                 pinctrl-names = "default";
 204                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 205                 reg-io-width = <4>;
 206                 reg-shift = <2>;
 207                 status = "disabled";
 208         };
 209
 210         uart1: serial@ff120000 {
 211                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 212                 reg = <0x0 0xff120000 0x0 0x100>;
 213                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 215                 clock-names = "sclk_uart", "pclk_uart";
 216                 dmas = <&dmac 4>, <&dmac 5>;
 217                 #dma-cells = <2>;
 218                 pinctrl-names = "default";
 219                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 220                 reg-io-width = <4>;
 221                 reg-shift = <2>;
 222                 status = "disabled";
 223         };
 224
 225         uart2: serial@ff130000 {
 226                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 227                 reg = <0x0 0xff130000 0x0 0x100>;
 228                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 230                 clock-names = "baudclk", "apb_pclk";
 231                 dmas = <&dmac 6>, <&dmac 7>;
 232                 #dma-cells = <2>;
 233                 pinctrl-names = "default";
 234                 pinctrl-0 = <&uart2m1_xfer>;
 235                 reg-io-width = <4>;
 236                 reg-shift = <2>;
 237                 status = "disabled";
 238         };
 239
 240         i2c0: i2c@ff150000 {
 241                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 242                 reg = <0x0 0xff150000 0x0 0x1000>;
 243                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 244                 #address-cells = <1>;
 245                 #size-cells = <0>;
 246                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 247                 clock-names = "i2c", "pclk";
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&i2c0_xfer>;
 250                 status = "disabled";
 251         };
 252
 253         i2c1: i2c@ff160000 {
 254                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 255                 reg = <0x0 0xff160000 0x0 0x1000>;
 256                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 257                 #address-cells = <1>;
 258                 #size-cells = <0>;
 259                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 260                 clock-names = "i2c", "pclk";
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&i2c1_xfer>;
 263                 status = "disabled";
 264         };
 265
 266         i2c2: i2c@ff170000 {
 267                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 268                 reg = <0x0 0xff170000 0x0 0x1000>;
 269                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 270                 #address-cells = <1>;
 271                 #size-cells = <0>;
 272                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 273                 clock-names = "i2c", "pclk";
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&i2c2_xfer>;
 276                 status = "disabled";
 277         };
 278
 279         i2c3: i2c@ff180000 {
 280                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 281                 reg = <0x0 0xff180000 0x0 0x1000>;
 282                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 286                 clock-names = "i2c", "pclk";
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&i2c3_xfer>;
 289                 status = "disabled";
 290         };
 291
 292         spi0: spi@ff190000 {
 293                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 294                 reg = <0x0 0xff190000 0x0 0x1000>;
 295                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 296                 #address-cells = <1>;
 297                 #size-cells = <0>;
 298                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 299                 clock-names = "spiclk", "apb_pclk";
 300                 dmas = <&dmac 8>, <&dmac 9>;
 301                 dma-names = "tx", "rx";
 302                 pinctrl-names = "default";
 303                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 304                 status = "disabled";
 305         };
 306
 307         wdt: watchdog@ff1a0000 {
 308                 compatible = "snps,dw-wdt";
 309                 reg = <0x0 0xff1a0000 0x0 0x100>;
 310                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 311         };
 312
 313         saradc: adc@ff280000 {
 314                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 315                 reg = <0x0 0xff280000 0x0 0x100>;
 316                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 317                 #io-channel-cells = <1>;
 318                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 319                 clock-names = "saradc", "apb_pclk";
 320                 resets = <&cru SRST_SARADC_P>;
 321                 reset-names = "saradc-apb";
 322                 status = "disabled";
 323         };
 324
 325         cru: clock-controller@ff440000 {
 326                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 327                 reg = <0x0 0xff440000 0x0 0x1000>;
 328                 rockchip,grf = <&grf>;
 329                 #clock-cells = <1>;
 330                 #reset-cells = <1>;
 331                 assigned-clocks =
 332                         /*
 333                          * CPLL should run at 1200, but that is to high for
 334                          * the initial dividers of most of its children.
 335                          * We need set cpll child clk div first,
 336                          * and then set the cpll frequency.
 337                          */
 338                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 339                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 340                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 341                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 342                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 343                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 344                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 345                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 346                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 347                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 348                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 349                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 350                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 351                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 352                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 353                         <&cru SCLK_RTC32K>;
 354                 assigned-clock-parents =
 355                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 356                         <&cru PLL_GPLL>, <&xin24m>,
 357                         <&xin24m>, <&xin24m>;
 358                 assigned-clock-rates =
 359                         <0>, <61440000>,
 360                         <0>, <24000000>,
 361                         <24000000>, <24000000>,
 362                         <15000000>, <15000000>,
 363                         <100000000>, <100000000>,
 364                         <100000000>, <100000000>,
 365                         <50000000>, <100000000>,
 366                         <100000000>, <100000000>,
 367                         <50000000>, <50000000>,
 368                         <50000000>, <50000000>,
 369                         <24000000>, <600000000>,
 370                         <491520000>, <1200000000>,
 371                         <150000000>, <75000000>,
 372                         <75000000>, <150000000>,
 373                         <75000000>, <75000000>,
 374                         <32768>;
 375         };
 376
 377         sdmmc: dwmmc@ff500000 {
 378                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 379                 reg = <0x0 0xff500000 0x0 0x4000>;
 380                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 382                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 383                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 384                 fifo-depth = <0x100>;
 385                 status = "disabled";
 386         };
 387
 388         sdio: dwmmc@ff510000 {
 389                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 390                 reg = <0x0 0xff510000 0x0 0x4000>;
 391                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 392                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 393                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 394                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 395                 fifo-depth = <0x100>;
 396                 status = "disabled";
 397         };
 398
 399         emmc: dwmmc@ff520000 {
 400                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 401                 reg = <0x0 0xff520000 0x0 0x4000>;
 402                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 403                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 404                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 405                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 406                 fifo-depth = <0x100>;
 407                 status = "disabled";
 408         };
 409
 410         gmac2io: ethernet@ff540000 {
 411                 compatible = "rockchip,rk3328-gmac";
 412                 reg = <0x0 0xff540000 0x0 0x10000>;
 413                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 414                 interrupt-names = "macirq";
 415                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 416                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 417                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 418                          <&cru PCLK_MAC2IO>;
 419                 clock-names = "stmmaceth", "mac_clk_rx",
 420                               "mac_clk_tx", "clk_mac_ref",
 421                               "clk_mac_refout", "aclk_mac",
 422                               "pclk_mac";
 423                 resets = <&cru SRST_GMAC2IO_A>;
 424                 reset-names = "stmmaceth";
 425                 rockchip,grf = <&grf>;
 426                 status = "disabled";
 427         };
 428
 429         gmac2phy: ethernet@ff550000 {
 430                 compatible = "rockchip,rk3328-gmac";
 431                 reg = <0x0 0xff550000 0x0 0x10000>;
 432                 rockchip,grf = <&grf>;
 433                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 434                 interrupt-names = "macirq";
 435                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 436                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 437                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 438                          <&cru SCLK_MAC2PHY_OUT>;
 439                 clock-names = "stmmaceth", "mac_clk_rx",
 440                               "mac_clk_tx", "clk_mac_ref",
 441                               "aclk_mac", "pclk_mac",
 442                               "clk_macphy";
 443                 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
 444                 reset-names = "stmmaceth", "mac-phy";
 445                 phy-mode = "rmii";
 446                 phy-handle = <&phy>;
 447                 status = "disabled";
 448
 449                 mdio {
 450                         compatible = "snps,dwmac-mdio";
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453
 454                         phy: phy@0 {
 455                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 456                                 reg = <0>;
 457                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
 458                                 resets = <&cru SRST_MACPHY>;
 459                                 pinctrl-names = "default";
 460                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 461                                 phy-is-integrated;
 462                         };
 463                 };
 464         };
 465
 466         gic: interrupt-controller@ff811000 {
 467                 compatible = "arm,gic-400";
 468                 #interrupt-cells = <3>;
 469                 #address-cells = <0>;
 470                 interrupt-controller;
 471                 reg = <0x0 0xff811000 0 0x1000>,
 472                       <0x0 0xff812000 0 0x2000>,
 473                       <0x0 0xff814000 0 0x2000>,
 474                       <0x0 0xff816000 0 0x2000>;
 475                 interrupts = <GIC_PPI 9
 476                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 477         };
 478
 479         pinctrl: pinctrl {
 480                 compatible = "rockchip,rk3328-pinctrl";
 481                 rockchip,grf = <&grf>;
 482                 #address-cells = <2>;
 483                 #size-cells = <2>;
 484                 ranges;
 485
 486                 gpio0: gpio0@ff210000 {
 487                         compatible = "rockchip,gpio-bank";
 488                         reg = <0x0 0xff210000 0x0 0x100>;
 489                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&cru PCLK_GPIO0>;
 491
 492                         gpio-controller;
 493                         #gpio-cells = <2>;
 494
 495                         interrupt-controller;
 496                         #interrupt-cells = <2>;
 497                 };
 498
 499                 gpio1: gpio1@ff220000 {
 500                         compatible = "rockchip,gpio-bank";
 501                         reg = <0x0 0xff220000 0x0 0x100>;
 502                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 503                         clocks = <&cru PCLK_GPIO1>;
 504
 505                         gpio-controller;
 506                         #gpio-cells = <2>;
 507
 508                         interrupt-controller;
 509                         #interrupt-cells = <2>;
 510                 };
 511
 512                 gpio2: gpio2@ff230000 {
 513                         compatible = "rockchip,gpio-bank";
 514                         reg = <0x0 0xff230000 0x0 0x100>;
 515                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&cru PCLK_GPIO2>;
 517
 518                         gpio-controller;
 519                         #gpio-cells = <2>;
 520
 521                         interrupt-controller;
 522                         #interrupt-cells = <2>;
 523                 };
 524
 525                 gpio3: gpio3@ff240000 {
 526                         compatible = "rockchip,gpio-bank";
 527                         reg = <0x0 0xff240000 0x0 0x100>;
 528                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&cru PCLK_GPIO3>;
 530
 531                         gpio-controller;
 532                         #gpio-cells = <2>;
 533
 534                         interrupt-controller;
 535                         #interrupt-cells = <2>;
 536                 };
 537
 538                 pcfg_pull_up: pcfg-pull-up {
 539                         bias-pull-up;
 540                 };
 541
 542                 pcfg_pull_down: pcfg-pull-down {
 543                         bias-pull-down;
 544                 };
 545
 546                 pcfg_pull_none: pcfg-pull-none {
 547                         bias-disable;
 548                 };
 549
 550                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 551                         bias-disable;
 552                         drive-strength = <2>;
 553                 };
 554
 555                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 556                         bias-pull-up;
 557                         drive-strength = <2>;
 558                 };
 559
 560                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 561                         bias-pull-up;
 562                         drive-strength = <4>;
 563                 };
 564
 565                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 566                         bias-disable;
 567                         drive-strength = <4>;
 568                 };
 569
 570                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 571                         bias-pull-down;
 572                         drive-strength = <4>;
 573                 };
 574
 575                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 576                         bias-disable;
 577                         drive-strength = <8>;
 578                 };
 579
 580                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 581                         bias-pull-up;
 582                         drive-strength = <8>;
 583                 };
 584
 585                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 586                         bias-disable;
 587                         drive-strength = <12>;
 588                 };
 589
 590                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 591                         bias-pull-up;
 592                         drive-strength = <12>;
 593                 };
 594
 595                 pcfg_output_high: pcfg-output-high {
 596                         output-high;
 597                 };
 598
 599                 pcfg_output_low: pcfg-output-low {
 600                         output-low;
 601                 };
 602
 603                 pcfg_input_high: pcfg-input-high {
 604                         bias-pull-up;
 605                         input-enable;
 606                 };
 607
 608                 pcfg_input: pcfg-input {
 609                         input-enable;
 610                 };
 611
 612                 i2c0 {
 613                         i2c0_xfer: i2c0-xfer {
 614                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
 615                                                 <2 RK_PD1 1 &pcfg_pull_none>;
 616                         };
 617                 };
 618
 619                 i2c1 {
 620                         i2c1_xfer: i2c1-xfer {
 621                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
 622                                                 <2 RK_PA5 2 &pcfg_pull_none>;
 623                         };
 624                 };
 625
 626                 i2c2 {
 627                         i2c2_xfer: i2c2-xfer {
 628                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
 629                                                 <2 RK_PB6 1 &pcfg_pull_none>;
 630                         };
 631                 };
 632
 633                 i2c3 {
 634                         i2c3_xfer: i2c3-xfer {
 635                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
 636                                                 <0 RK_PA6 2 &pcfg_pull_none>;
 637                         };
 638                         i2c3_gpio: i2c3-gpio {
 639                                 rockchip,pins =
 640                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
 641                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
 642                         };
 643                 };
 644
 645                 hdmi_i2c {
 646                         hdmii2c_xfer: hdmii2c-xfer {
 647                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
 648                                                 <0 RK_PA6 1 &pcfg_pull_none>;
 649                         };
 650                 };
 651
 652                 tsadc {
 653                         otp_gpio: otp-gpio {
 654                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
 655                         };
 656
 657                         otp_out: otp-out {
 658                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
 659                         };
 660                 };
 661
 662                 uart0 {
 663                         uart0_xfer: uart0-xfer {
 664                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
 665                                                 <1 RK_PB0 1 &pcfg_pull_none>;
 666                         };
 667
 668                         uart0_cts: uart0-cts {
 669                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
 670                         };
 671
 672                         uart0_rts: uart0-rts {
 673                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
 674                         };
 675
 676                         uart0_rts_gpio: uart0-rts-gpio {
 677                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
 678                         };
 679                 };
 680
 681                 uart1 {
 682                         uart1_xfer: uart1-xfer {
 683                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
 684                                                 <3 RK_PA6 4 &pcfg_pull_none>;
 685                         };
 686
 687                         uart1_cts: uart1-cts {
 688                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
 689                         };
 690
 691                         uart1_rts: uart1-rts {
 692                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
 693                         };
 694
 695                         uart1_rts_gpio: uart1-rts-gpio {
 696                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
 697                         };
 698                 };
 699
 700                 uart2-0 {
 701                         uart2m0_xfer: uart2m0-xfer {
 702                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
 703                                                 <1 RK_PA1 2 &pcfg_pull_none>;
 704                         };
 705                 };
 706
 707                 uart2-1 {
 708                         uart2m1_xfer: uart2m1-xfer {
 709                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
 710                                                 <2 RK_PA1 1 &pcfg_pull_none>;
 711                         };
 712                 };
 713
 714                 spi0-0 {
 715                         spi0m0_clk: spi0m0-clk {
 716                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
 717                         };
 718
 719                         spi0m0_cs0: spi0m0-cs0 {
 720                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
 721                         };
 722
 723                         spi0m0_tx: spi0m0-tx {
 724                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
 725                         };
 726
 727                         spi0m0_rx: spi0m0-rx {
 728                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
 729                         };
 730
 731                         spi0m0_cs1: spi0m0-cs1 {
 732                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
 733                         };
 734                 };
 735
 736                 spi0-1 {
 737                         spi0m1_clk: spi0m1-clk {
 738                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
 739                         };
 740
 741                         spi0m1_cs0: spi0m1-cs0 {
 742                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
 743                         };
 744
 745                         spi0m1_tx: spi0m1-tx {
 746                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
 747                         };
 748
 749                         spi0m1_rx: spi0m1-rx {
 750                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
 751                         };
 752
 753                         spi0m1_cs1: spi0m1-cs1 {
 754                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
 755                         };
 756                 };
 757
 758                 spi0-2 {
 759                         spi0m2_clk: spi0m2-clk {
 760                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
 761                         };
 762
 763                         spi0m2_cs0: spi0m2-cs0 {
 764                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
 765                         };
 766
 767                         spi0m2_tx: spi0m2-tx {
 768                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
 769                         };
 770
 771                         spi0m2_rx: spi0m2-rx {
 772                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
 773                         };
 774                 };
 775
 776                 i2s1 {
 777                         i2s1_mclk: i2s1-mclk {
 778                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
 779                         };
 780
 781                         i2s1_sclk: i2s1-sclk {
 782                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
 783                         };
 784
 785                         i2s1_lrckrx: i2s1-lrckrx {
 786                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
 787                         };
 788
 789                         i2s1_lrcktx: i2s1-lrcktx {
 790                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
 791                         };
 792
 793                         i2s1_sdi: i2s1-sdi {
 794                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
 795                         };
 796
 797                         i2s1_sdo: i2s1-sdo {
 798                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
 799                         };
 800
 801                         i2s1_sdio1: i2s1-sdio1 {
 802                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
 803                         };
 804
 805                         i2s1_sdio2: i2s1-sdio2 {
 806                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
 807                         };
 808
 809                         i2s1_sdio3: i2s1-sdio3 {
 810                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
 811                         };
 812
 813                         i2s1_sleep: i2s1-sleep {
 814                                 rockchip,pins =
 815                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
 816                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
 817                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
 818                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
 819                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
 820                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
 821                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
 822                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
 823                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
 824                         };
 825                 };
 826
 827                 i2s2-0 {
 828                         i2s2m0_mclk: i2s2m0-mclk {
 829                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
 830                         };
 831
 832                         i2s2m0_sclk: i2s2m0-sclk {
 833                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
 834                         };
 835
 836                         i2s2m0_lrckrx: i2s2m0-lrckrx {
 837                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
 838                         };
 839
 840                         i2s2m0_lrcktx: i2s2m0-lrcktx {
 841                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
 842                         };
 843
 844                         i2s2m0_sdi: i2s2m0-sdi {
 845                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
 846                         };
 847
 848                         i2s2m0_sdo: i2s2m0-sdo {
 849                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
 850                         };
 851
 852                         i2s2m0_sleep: i2s2m0-sleep {
 853                                 rockchip,pins =
 854                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
 855                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
 856                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
 857                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
 858                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
 859                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
 860                         };
 861                 };
 862
 863                 i2s2-1 {
 864                         i2s2m1_mclk: i2s2m1-mclk {
 865                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
 866                         };
 867
 868                         i2s2m1_sclk: i2s2m1-sclk {
 869                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
 870                         };
 871
 872                         i2s2m1_lrckrx: i2sm1-lrckrx {
 873                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
 874                         };
 875
 876                         i2s2m1_lrcktx: i2s2m1-lrcktx {
 877                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
 878                         };
 879
 880                         i2s2m1_sdi: i2s2m1-sdi {
 881                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
 882                         };
 883
 884                         i2s2m1_sdo: i2s2m1-sdo {
 885                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
 886                         };
 887
 888                         i2s2m1_sleep: i2s2m1-sleep {
 889                                 rockchip,pins =
 890                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
 891                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
 892                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
 893                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
 894                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
 895                         };
 896                 };
 897
 898                 spdif-0 {
 899                         spdifm0_tx: spdifm0-tx {
 900                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
 901                         };
 902                 };
 903
 904                 spdif-1 {
 905                         spdifm1_tx: spdifm1-tx {
 906                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
 907                         };
 908                 };
 909
 910                 spdif-2 {
 911                         spdifm2_tx: spdifm2-tx {
 912                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
 913                         };
 914                 };
 915
 916                 sdmmc0-0 {
 917                         sdmmc0m0_pwren: sdmmc0m0-pwren {
 918                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
 919                         };
 920
 921                         sdmmc0m0_gpio: sdmmc0m0-gpio {
 922                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
 923                         };
 924                 };
 925
 926                 sdmmc0-1 {
 927                         sdmmc0m1_pwren: sdmmc0m1-pwren {
 928                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
 929                         };
 930
 931                         sdmmc0m1_gpio: sdmmc0m1-gpio {
 932                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
 933                         };
 934                 };
 935
 936                 sdmmc0 {
 937                         sdmmc0_clk: sdmmc0-clk {
 938                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
 939                         };
 940
 941                         sdmmc0_cmd: sdmmc0-cmd {
 942                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
 943                         };
 944
 945                         sdmmc0_dectn: sdmmc0-dectn {
 946                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
 947                         };
 948
 949                         sdmmc0_wrprt: sdmmc0-wrprt {
 950                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
 951                         };
 952
 953                         sdmmc0_bus1: sdmmc0-bus1 {
 954                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
 955                         };
 956
 957                         sdmmc0_bus4: sdmmc0-bus4 {
 958                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
 959                                                 <1 RK_PA1 1 &pcfg_pull_up_4ma>,
 960                                                 <1 RK_PA2 1 &pcfg_pull_up_4ma>,
 961                                                 <1 RK_PA3 1 &pcfg_pull_up_4ma>;
 962                         };
 963
 964                         sdmmc0_gpio: sdmmc0-gpio {
 965                                 rockchip,pins =
 966                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
 967                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
 968                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
 969                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
 970                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
 971                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
 972                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
 973                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
 974                         };
 975                 };
 976
 977                 sdmmc0ext {
 978                         sdmmc0ext_clk: sdmmc0ext-clk {
 979                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
 980                         };
 981
 982                         sdmmc0ext_cmd: sdmmc0ext-cmd {
 983                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
 984                         };
 985
 986                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
 987                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
 988                         };
 989
 990                         sdmmc0ext_dectn: sdmmc0ext-dectn {
 991                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
 992                         };
 993
 994                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
 995                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
 996                         };
 997
 998                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
 999                                 rockchip,pins =
1000                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1001                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1002                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1003                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1004                         };
1005
1006                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1007                                 rockchip,pins =
1008                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1009                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1010                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1011                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1012                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1013                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1014                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1015                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1016                         };
1017                 };
1018
1019                 sdmmc1 {
1020                         sdmmc1_clk: sdmmc1-clk {
1021                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1022                         };
1023
1024                         sdmmc1_cmd: sdmmc1-cmd {
1025                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1026                         };
1027
1028                         sdmmc1_pwren: sdmmc1-pwren {
1029                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1030                         };
1031
1032                         sdmmc1_wrprt: sdmmc1-wrprt {
1033                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1034                         };
1035
1036                         sdmmc1_dectn: sdmmc1-dectn {
1037                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1038                         };
1039
1040                         sdmmc1_bus1: sdmmc1-bus1 {
1041                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1042                         };
1043
1044                         sdmmc1_bus4: sdmmc1-bus4 {
1045                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1046                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1047                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1048                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1049                         };
1050
1051                         sdmmc1_gpio: sdmmc1-gpio {
1052                                 rockchip,pins =
1053                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1054                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1055                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1056                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1057                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1058                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1059                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1060                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1061                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1062                         };
1063                 };
1064
1065                 emmc {
1066                         emmc_clk: emmc-clk {
1067                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1068                         };
1069
1070                         emmc_cmd: emmc-cmd {
1071                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1072                         };
1073
1074                         emmc_pwren: emmc-pwren {
1075                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1076                         };
1077
1078                         emmc_rstnout: emmc-rstnout {
1079                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1080                         };
1081
1082                         emmc_bus1: emmc-bus1 {
1083                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1084                         };
1085
1086                         emmc_bus4: emmc-bus4 {
1087                                 rockchip,pins =
1088                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1089                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1090                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1091                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1092                         };
1093
1094                         emmc_bus8: emmc-bus8 {
1095                                 rockchip,pins =
1096                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1097                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1098                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1099                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1100                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1101                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1102                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1103                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1104                         };
1105                 };
1106
1107                 pwm0 {
1108                         pwm0_pin: pwm0-pin {
1109                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1110                         };
1111                 };
1112
1113                 pwm1 {
1114                         pwm1_pin: pwm1-pin {
1115                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1116                         };
1117                 };
1118
1119                 pwm2 {
1120                         pwm2_pin: pwm2-pin {
1121                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1122                         };
1123                 };
1124
1125                 pwmir {
1126                         pwmir_pin: pwmir-pin {
1127                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1128                         };
1129                 };
1130
1131                 gmac-1 {
1132                         rgmiim1_pins: rgmiim1-pins {
1133                                 rockchip,pins =
1134                                         /* mac_txclk */
1135                                         <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1136                                         /* mac_rxclk */
1137                                         <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1138                                         /* mac_mdio */
1139                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1140                                         /* mac_txen */
1141                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1142                                         /* mac_clk */
1143                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1144                                         /* mac_rxdv */
1145                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1146                                         /* mac_mdc */
1147                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1148                                         /* mac_rxd1 */
1149                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1150                                         /* mac_rxd0 */
1151                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1152                                         /* mac_txd1 */
1153                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1154                                         /* mac_txd0 */
1155                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1156                                         /* mac_rxd3 */
1157                                         <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1158                                         /* mac_rxd2 */
1159                                         <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1160                                         /* mac_txd3 */
1161                                         <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1162                                         /* mac_txd2 */
1163                                         <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1164
1165                                         /* mac_txclk */
1166                                         <0 RK_PB0 1 &pcfg_pull_none>,
1167                                         /* mac_txen */
1168                                         <0 RK_PB4 1 &pcfg_pull_none>,
1169                                         /* mac_clk */
1170                                         <0 RK_PD0 1 &pcfg_pull_none>,
1171                                         /* mac_txd1 */
1172                                         <0 RK_PC0 1 &pcfg_pull_none>,
1173                                         /* mac_txd0 */
1174                                         <0 RK_PC1 1 &pcfg_pull_none>,
1175                                         /* mac_txd3 */
1176                                         <0 RK_PC7 1 &pcfg_pull_none>,
1177                                         /* mac_txd2 */
1178                                         <0 RK_PC6 1 &pcfg_pull_none>;
1179                         };
1180
1181                         rmiim1_pins: rmiim1-pins {
1182                                 rockchip,pins =
1183                                         /* mac_mdio */
1184                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1185                                         /* mac_txen */
1186                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1187                                         /* mac_clk */
1188                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1189                                         /* mac_rxer */
1190                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1191                                         /* mac_rxdv */
1192                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1193                                         /* mac_mdc */
1194                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1195                                         /* mac_rxd1 */
1196                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1197                                         /* mac_rxd0 */
1198                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1199                                         /* mac_txd1 */
1200                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1201                                         /* mac_txd0 */
1202                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1203
1204                                         /* mac_mdio */
1205                                         <0 RK_PB3 1 &pcfg_pull_none>,
1206                                         /* mac_txen */
1207                                         <0 RK_PB4 1 &pcfg_pull_none>,
1208                                         /* mac_clk */
1209                                         <0 RK_PD0 1 &pcfg_pull_none>,
1210                                         /* mac_mdc */
1211                                         <0 RK_PC3 1 &pcfg_pull_none>,
1212                                         /* mac_txd1 */
1213                                         <0 RK_PC0 1 &pcfg_pull_none>,
1214                                         /* mac_txd0 */
1215                                         <0 RK_PC1 1 &pcfg_pull_none>;
1216                         };
1217                 };
1218
1219                 gmac2phy {
1220                         fephyled_speed100: fephyled-speed100 {
1221                                 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1222                         };
1223
1224                         fephyled_speed10: fephyled-speed10 {
1225                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1226                         };
1227
1228                         fephyled_duplex: fephyled-duplex {
1229                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1230                         };
1231
1232                         fephyled_rxm0: fephyled-rxm0 {
1233                                 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1234                         };
1235
1236                         fephyled_txm0: fephyled-txm0 {
1237                                 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1238                         };
1239
1240                         fephyled_linkm0: fephyled-linkm0 {
1241                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1242                         };
1243
1244                         fephyled_rxm1: fephyled-rxm1 {
1245                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1246                         };
1247
1248                         fephyled_txm1: fephyled-txm1 {
1249                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1250                         };
1251
1252                         fephyled_linkm1: fephyled-linkm1 {
1253                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1254                         };
1255                 };
1256
1257                 tsadc_pin {
1258                         tsadc_int: tsadc-int {
1259                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1260                         };
1261                         tsadc_gpio: tsadc-gpio {
1262                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1263                         };
1264                 };
1265
1266                 hdmi_pin {
1267                         hdmi_cec: hdmi-cec {
1268                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1269                         };
1270
1271                         hdmi_hpd: hdmi-hpd {
1272                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1273                         };
1274                 };
1275
1276                 cif-0 {
1277                         dvp_d2d9_m0:dvp-d2d9-m0 {
1278                                 rockchip,pins =
1279                                         /* cif_d0 */
1280                                         <3 RK_PA4 2 &pcfg_pull_none>,
1281                                         /* cif_d1 */
1282                                         <3 RK_PA5 2 &pcfg_pull_none>,
1283                                         /* cif_d2 */
1284                                         <3 RK_PA6 2 &pcfg_pull_none>,
1285                                         /* cif_d3 */
1286                                         <3 RK_PA7 2 &pcfg_pull_none>,
1287                                         /* cif_d4 */
1288                                         <3 RK_PB0 2 &pcfg_pull_none>,
1289                                         /* cif_d5m0 */
1290                                         <3 RK_PB1 2 &pcfg_pull_none>,
1291                                         /* cif_d6m0 */
1292                                         <3 RK_PB2 2 &pcfg_pull_none>,
1293                                         /* cif_d7m0 */
1294                                         <3 RK_PB3 2 &pcfg_pull_none>,
1295                                         /* cif_href */
1296                                         <3 RK_PA1 2 &pcfg_pull_none>,
1297                                         /* cif_vsync */
1298                                         <3 RK_PA0 2 &pcfg_pull_none>,
1299                                         /* cif_clkoutm0 */
1300                                         <3 RK_PA3 2 &pcfg_pull_none>,
1301                                         /* cif_clkin */
1302                                         <3 RK_PA2 2 &pcfg_pull_none>;
1303                         };
1304                 };
1305
1306                 cif-1 {
1307                         dvp_d2d9_m1:dvp-d2d9-m1 {
1308                                 rockchip,pins =
1309                                         /* cif_d0 */
1310                                         <3 RK_PA4 2 &pcfg_pull_none>,
1311                                         /* cif_d1 */
1312                                         <3 RK_PA5 2 &pcfg_pull_none>,
1313                                         /* cif_d2 */
1314                                         <3 RK_PA6 2 &pcfg_pull_none>,
1315                                         /* cif_d3 */
1316                                         <3 RK_PA7 2 &pcfg_pull_none>,
1317                                         /* cif_d4 */
1318                                         <3 RK_PB0 2 &pcfg_pull_none>,
1319                                         /* cif_d5m1 */
1320                                         <2 RK_PC0 4 &pcfg_pull_none>,
1321                                         /* cif_d6m1 */
1322                                         <2 RK_PC1 4 &pcfg_pull_none>,
1323                                         /* cif_d7m1 */
1324                                         <2 RK_PC2 4 &pcfg_pull_none>,
1325                                         /* cif_href */
1326                                         <3 RK_PA1 2 &pcfg_pull_none>,
1327                                         /* cif_vsync */
1328                                         <3 RK_PA0 2 &pcfg_pull_none>,
1329                                         /* cif_clkoutm1 */
1330                                         <2 RK_PB7 4 &pcfg_pull_none>,
1331                                         /* cif_clkin */
1332                                         <3 RK_PA2 2 &pcfg_pull_none>;
1333                         };
1334                 };
1335         };
1336 };