arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3328-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3328-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3328";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 gpio0 = &gpio0;
  24                 gpio1 = &gpio1;
  25                 gpio2 = &gpio2;
  26                 gpio3 = &gpio3;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 i2c0 = &i2c0;
  31                 i2c1 = &i2c1;
  32                 i2c2 = &i2c2;
  33                 i2c3 = &i2c3;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 cpu0: cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53";
  43                         reg = <0x0 0x0>;
  44                         clocks = <&cru ARMCLK>;
  45                         #cooling-cells = <2>;
  46                         cpu-idle-states = <&CPU_SLEEP>;
  47                         dynamic-power-coefficient = <120>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&l2>;
  50                         operating-points-v2 = <&cpu0_opp_table>;
  51                 };
  52
  53                 cpu1: cpu@1 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53";
  56                         reg = <0x0 0x1>;
  57                         clocks = <&cru ARMCLK>;
  58                         #cooling-cells = <2>;
  59                         cpu-idle-states = <&CPU_SLEEP>;
  60                         dynamic-power-coefficient = <120>;
  61                         enable-method = "psci";
  62                         next-level-cache = <&l2>;
  63                         operating-points-v2 = <&cpu0_opp_table>;
  64                 };
  65
  66                 cpu2: cpu@2 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a53";
  69                         reg = <0x0 0x2>;
  70                         clocks = <&cru ARMCLK>;
  71                         #cooling-cells = <2>;
  72                         cpu-idle-states = <&CPU_SLEEP>;
  73                         dynamic-power-coefficient = <120>;
  74                         enable-method = "psci";
  75                         next-level-cache = <&l2>;
  76                         operating-points-v2 = <&cpu0_opp_table>;
  77                 };
  78
  79                 cpu3: cpu@3 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53";
  82                         reg = <0x0 0x3>;
  83                         clocks = <&cru ARMCLK>;
  84                         #cooling-cells = <2>;
  85                         cpu-idle-states = <&CPU_SLEEP>;
  86                         dynamic-power-coefficient = <120>;
  87                         enable-method = "psci";
  88                         next-level-cache = <&l2>;
  89                         operating-points-v2 = <&cpu0_opp_table>;
  90                 };
  91
  92                 idle-states {
  93                         entry-method = "psci";
  94
  95                         CPU_SLEEP: cpu-sleep {
  96                                 compatible = "arm,idle-state";
  97                                 local-timer-stop;
  98                                 arm,psci-suspend-param = <0x0010000>;
  99                                 entry-latency-us = <120>;
 100                                 exit-latency-us = <250>;
 101                                 min-residency-us = <900>;
 102                         };
 103                 };
 104
 105                 l2: l2-cache0 {
 106                         compatible = "cache";
 107                         cache-level = <2>;
 108                         cache-unified;
 109                 };
 110         };
 111
 112         cpu0_opp_table: opp-table-0 {
 113                 compatible = "operating-points-v2";
 114                 opp-shared;
 115
 116                 opp-408000000 {
 117                         opp-hz = /bits/ 64 <408000000>;
 118                         opp-microvolt = <950000>;
 119                         clock-latency-ns = <40000>;
 120                         opp-suspend;
 121                 };
 122                 opp-600000000 {
 123                         opp-hz = /bits/ 64 <600000000>;
 124                         opp-microvolt = <950000>;
 125                         clock-latency-ns = <40000>;
 126                 };
 127                 opp-816000000 {
 128                         opp-hz = /bits/ 64 <816000000>;
 129                         opp-microvolt = <1000000>;
 130                         clock-latency-ns = <40000>;
 131                 };
 132                 opp-1008000000 {
 133                         opp-hz = /bits/ 64 <1008000000>;
 134                         opp-microvolt = <1100000>;
 135                         clock-latency-ns = <40000>;
 136                 };
 137                 opp-1200000000 {
 138                         opp-hz = /bits/ 64 <1200000000>;
 139                         opp-microvolt = <1225000>;
 140                         clock-latency-ns = <40000>;
 141                 };
 142                 opp-1296000000 {
 143                         opp-hz = /bits/ 64 <1296000000>;
 144                         opp-microvolt = <1300000>;
 145                         clock-latency-ns = <40000>;
 146                 };
 147         };
 148
 149         analog_sound: analog-sound {
 150                 compatible = "simple-audio-card";
 151                 simple-audio-card,format = "i2s";
 152                 simple-audio-card,mclk-fs = <256>;
 153                 simple-audio-card,name = "Analog";
 154                 status = "disabled";
 155
 156                 simple-audio-card,cpu {
 157                         sound-dai = <&i2s1>;
 158                 };
 159
 160                 simple-audio-card,codec {
 161                         sound-dai = <&codec>;
 162                 };
 163         };
 164
 165         arm-pmu {
 166                 compatible = "arm,cortex-a53-pmu";
 167                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 171                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 172         };
 173
 174         display_subsystem: display-subsystem {
 175                 compatible = "rockchip,display-subsystem";
 176                 ports = <&vop_out>;
 177         };
 178
 179         hdmi_sound: hdmi-sound {
 180                 compatible = "simple-audio-card";
 181                 simple-audio-card,format = "i2s";
 182                 simple-audio-card,mclk-fs = <128>;
 183                 simple-audio-card,name = "HDMI";
 184                 status = "disabled";
 185
 186                 simple-audio-card,cpu {
 187                         sound-dai = <&i2s0>;
 188                 };
 189
 190                 simple-audio-card,codec {
 191                         sound-dai = <&hdmi>;
 192                 };
 193         };
 194
 195         psci {
 196                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 197                 method = "smc";
 198         };
 199
 200         timer {
 201                 compatible = "arm,armv8-timer";
 202                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 203                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 204                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 205                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 206         };
 207
 208         xin24m: xin24m {
 209                 compatible = "fixed-clock";
 210                 #clock-cells = <0>;
 211                 clock-frequency = <24000000>;
 212                 clock-output-names = "xin24m";
 213         };
 214
 215         i2s0: i2s@ff000000 {
 216                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 217                 reg = <0x0 0xff000000 0x0 0x1000>;
 218                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 220                 clock-names = "i2s_clk", "i2s_hclk";
 221                 dmas = <&dmac 11>, <&dmac 12>;
 222                 dma-names = "tx", "rx";
 223                 #sound-dai-cells = <0>;
 224                 status = "disabled";
 225         };
 226
 227         i2s1: i2s@ff010000 {
 228                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 229                 reg = <0x0 0xff010000 0x0 0x1000>;
 230                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 231                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 232                 clock-names = "i2s_clk", "i2s_hclk";
 233                 dmas = <&dmac 14>, <&dmac 15>;
 234                 dma-names = "tx", "rx";
 235                 #sound-dai-cells = <0>;
 236                 status = "disabled";
 237         };
 238
 239         i2s2: i2s@ff020000 {
 240                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 241                 reg = <0x0 0xff020000 0x0 0x1000>;
 242                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 244                 clock-names = "i2s_clk", "i2s_hclk";
 245                 dmas = <&dmac 0>, <&dmac 1>;
 246                 dma-names = "tx", "rx";
 247                 #sound-dai-cells = <0>;
 248                 status = "disabled";
 249         };
 250
 251         spdif: spdif@ff030000 {
 252                 compatible = "rockchip,rk3328-spdif";
 253                 reg = <0x0 0xff030000 0x0 0x1000>;
 254                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 256                 clock-names = "mclk", "hclk";
 257                 dmas = <&dmac 10>;
 258                 dma-names = "tx";
 259                 pinctrl-names = "default";
 260                 pinctrl-0 = <&spdifm2_tx>;
 261                 #sound-dai-cells = <0>;
 262                 status = "disabled";
 263         };
 264
 265         pdm: pdm@ff040000 {
 266                 compatible = "rockchip,pdm";
 267                 reg = <0x0 0xff040000 0x0 0x1000>;
 268                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 269                 clock-names = "pdm_clk", "pdm_hclk";
 270                 dmas = <&dmac 16>;
 271                 dma-names = "rx";
 272                 pinctrl-names = "default", "sleep";
 273                 pinctrl-0 = <&pdmm0_clk
 274                              &pdmm0_sdi0
 275                              &pdmm0_sdi1
 276                              &pdmm0_sdi2
 277                              &pdmm0_sdi3>;
 278                 pinctrl-1 = <&pdmm0_clk_sleep
 279                              &pdmm0_sdi0_sleep
 280                              &pdmm0_sdi1_sleep
 281                              &pdmm0_sdi2_sleep
 282                              &pdmm0_sdi3_sleep>;
 283                 status = "disabled";
 284         };
 285
 286         grf: syscon@ff100000 {
 287                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 288                 reg = <0x0 0xff100000 0x0 0x1000>;
 289
 290                 io_domains: io-domains {
 291                         compatible = "rockchip,rk3328-io-voltage-domain";
 292                         status = "disabled";
 293                 };
 294
 295                 grf_gpio: gpio {
 296                         compatible = "rockchip,rk3328-grf-gpio";
 297                         gpio-controller;
 298                         #gpio-cells = <2>;
 299                 };
 300
 301                 power: power-controller {
 302                         compatible = "rockchip,rk3328-power-controller";
 303                         #power-domain-cells = <1>;
 304                         #address-cells = <1>;
 305                         #size-cells = <0>;
 306
 307                         power-domain@RK3328_PD_HEVC {
 308                                 reg = <RK3328_PD_HEVC>;
 309                                 #power-domain-cells = <0>;
 310                         };
 311                         power-domain@RK3328_PD_VIDEO {
 312                                 reg = <RK3328_PD_VIDEO>;
 313                                 clocks = <&cru ACLK_RKVDEC>,
 314                                          <&cru HCLK_RKVDEC>,
 315                                          <&cru SCLK_VDEC_CABAC>,
 316                                          <&cru SCLK_VDEC_CORE>;
 317                                 #power-domain-cells = <0>;
 318                         };
 319                         power-domain@RK3328_PD_VPU {
 320                                 reg = <RK3328_PD_VPU>;
 321                                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 322                                 #power-domain-cells = <0>;
 323                         };
 324                 };
 325
 326                 reboot-mode {
 327                         compatible = "syscon-reboot-mode";
 328                         offset = <0x5c8>;
 329                         mode-normal = <BOOT_NORMAL>;
 330                         mode-recovery = <BOOT_RECOVERY>;
 331                         mode-bootloader = <BOOT_FASTBOOT>;
 332                         mode-loader = <BOOT_BL_DOWNLOAD>;
 333                 };
 334         };
 335
 336         uart0: serial@ff110000 {
 337                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 338                 reg = <0x0 0xff110000 0x0 0x100>;
 339                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 341                 clock-names = "baudclk", "apb_pclk";
 342                 dmas = <&dmac 2>, <&dmac 3>;
 343                 dma-names = "tx", "rx";
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 346                 reg-io-width = <4>;
 347                 reg-shift = <2>;
 348                 status = "disabled";
 349         };
 350
 351         uart1: serial@ff120000 {
 352                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 353                 reg = <0x0 0xff120000 0x0 0x100>;
 354                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 355                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 356                 clock-names = "baudclk", "apb_pclk";
 357                 dmas = <&dmac 4>, <&dmac 5>;
 358                 dma-names = "tx", "rx";
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 361                 reg-io-width = <4>;
 362                 reg-shift = <2>;
 363                 status = "disabled";
 364         };
 365
 366         uart2: serial@ff130000 {
 367                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 368                 reg = <0x0 0xff130000 0x0 0x100>;
 369                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 370                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 371                 clock-names = "baudclk", "apb_pclk";
 372                 dmas = <&dmac 6>, <&dmac 7>;
 373                 dma-names = "tx", "rx";
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&uart2m1_xfer>;
 376                 reg-io-width = <4>;
 377                 reg-shift = <2>;
 378                 status = "disabled";
 379         };
 380
 381         i2c0: i2c@ff150000 {
 382                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 383                 reg = <0x0 0xff150000 0x0 0x1000>;
 384                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 388                 clock-names = "i2c", "pclk";
 389                 pinctrl-names = "default";
 390                 pinctrl-0 = <&i2c0_xfer>;
 391                 status = "disabled";
 392         };
 393
 394         i2c1: i2c@ff160000 {
 395                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 396                 reg = <0x0 0xff160000 0x0 0x1000>;
 397                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 401                 clock-names = "i2c", "pclk";
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&i2c1_xfer>;
 404                 status = "disabled";
 405         };
 406
 407         i2c2: i2c@ff170000 {
 408                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 409                 reg = <0x0 0xff170000 0x0 0x1000>;
 410                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 414                 clock-names = "i2c", "pclk";
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&i2c2_xfer>;
 417                 status = "disabled";
 418         };
 419
 420         i2c3: i2c@ff180000 {
 421                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 422                 reg = <0x0 0xff180000 0x0 0x1000>;
 423                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 427                 clock-names = "i2c", "pclk";
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&i2c3_xfer>;
 430                 status = "disabled";
 431         };
 432
 433         spi0: spi@ff190000 {
 434                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 435                 reg = <0x0 0xff190000 0x0 0x1000>;
 436                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 440                 clock-names = "spiclk", "apb_pclk";
 441                 dmas = <&dmac 8>, <&dmac 9>;
 442                 dma-names = "tx", "rx";
 443                 pinctrl-names = "default";
 444                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 445                 status = "disabled";
 446         };
 447
 448         wdt: watchdog@ff1a0000 {
 449                 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
 450                 reg = <0x0 0xff1a0000 0x0 0x100>;
 451                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 452                 clocks = <&cru PCLK_WDT>;
 453         };
 454
 455         pwm0: pwm@ff1b0000 {
 456                 compatible = "rockchip,rk3328-pwm";
 457                 reg = <0x0 0xff1b0000 0x0 0x10>;
 458                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 459                 clock-names = "pwm", "pclk";
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&pwm0_pin>;
 462                 #pwm-cells = <3>;
 463                 status = "disabled";
 464         };
 465
 466         pwm1: pwm@ff1b0010 {
 467                 compatible = "rockchip,rk3328-pwm";
 468                 reg = <0x0 0xff1b0010 0x0 0x10>;
 469                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 470                 clock-names = "pwm", "pclk";
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&pwm1_pin>;
 473                 #pwm-cells = <3>;
 474                 status = "disabled";
 475         };
 476
 477         pwm2: pwm@ff1b0020 {
 478                 compatible = "rockchip,rk3328-pwm";
 479                 reg = <0x0 0xff1b0020 0x0 0x10>;
 480                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 481                 clock-names = "pwm", "pclk";
 482                 pinctrl-names = "default";
 483                 pinctrl-0 = <&pwm2_pin>;
 484                 #pwm-cells = <3>;
 485                 status = "disabled";
 486         };
 487
 488         pwm3: pwm@ff1b0030 {
 489                 compatible = "rockchip,rk3328-pwm";
 490                 reg = <0x0 0xff1b0030 0x0 0x10>;
 491                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 492                 clock-names = "pwm", "pclk";
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&pwmir_pin>;
 495                 #pwm-cells = <3>;
 496                 status = "disabled";
 497         };
 498
 499         dmac: dma-controller@ff1f0000 {
 500                 compatible = "arm,pl330", "arm,primecell";
 501                 reg = <0x0 0xff1f0000 0x0 0x4000>;
 502                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 503                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 504                 arm,pl330-periph-burst;
 505                 clocks = <&cru ACLK_DMAC>;
 506                 clock-names = "apb_pclk";
 507                 #dma-cells = <1>;
 508         };
 509
 510         thermal-zones {
 511                 soc_thermal: soc-thermal {
 512                         polling-delay-passive = <20>;
 513                         polling-delay = <1000>;
 514                         sustainable-power = <1000>;
 515
 516                         thermal-sensors = <&tsadc 0>;
 517
 518                         trips {
 519                                 threshold: trip-point0 {
 520                                         temperature = <70000>;
 521                                         hysteresis = <2000>;
 522                                         type = "passive";
 523                                 };
 524                                 target: trip-point1 {
 525                                         temperature = <85000>;
 526                                         hysteresis = <2000>;
 527                                         type = "passive";
 528                                 };
 529                                 soc_crit: soc-crit {
 530                                         temperature = <95000>;
 531                                         hysteresis = <2000>;
 532                                         type = "critical";
 533                                 };
 534                         };
 535
 536                         cooling-maps {
 537                                 map0 {
 538                                         trip = <&target>;
 539                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 540                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 541                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 542                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 543                                         contribution = <4096>;
 544                                 };
 545                         };
 546                 };
 547
 548         };
 549
 550         tsadc: tsadc@ff250000 {
 551                 compatible = "rockchip,rk3328-tsadc";
 552                 reg = <0x0 0xff250000 0x0 0x100>;
 553                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 554                 assigned-clocks = <&cru SCLK_TSADC>;
 555                 assigned-clock-rates = <50000>;
 556                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 557                 clock-names = "tsadc", "apb_pclk";
 558                 pinctrl-names = "init", "default", "sleep";
 559                 pinctrl-0 = <&otp_pin>;
 560                 pinctrl-1 = <&otp_out>;
 561                 pinctrl-2 = <&otp_pin>;
 562                 resets = <&cru SRST_TSADC>;
 563                 reset-names = "tsadc-apb";
 564                 rockchip,grf = <&grf>;
 565                 rockchip,hw-tshut-temp = <100000>;
 566                 #thermal-sensor-cells = <1>;
 567                 status = "disabled";
 568         };
 569
 570         efuse: efuse@ff260000 {
 571                 compatible = "rockchip,rk3328-efuse";
 572                 reg = <0x0 0xff260000 0x0 0x50>;
 573                 #address-cells = <1>;
 574                 #size-cells = <1>;
 575                 clocks = <&cru SCLK_EFUSE>;
 576                 clock-names = "pclk_efuse";
 577                 rockchip,efuse-size = <0x20>;
 578
 579                 /* Data cells */
 580                 efuse_id: id@7 {
 581                         reg = <0x07 0x10>;
 582                 };
 583                 cpu_leakage: cpu-leakage@17 {
 584                         reg = <0x17 0x1>;
 585                 };
 586                 logic_leakage: logic-leakage@19 {
 587                         reg = <0x19 0x1>;
 588                 };
 589                 efuse_cpu_version: cpu-version@1a {
 590                         reg = <0x1a 0x1>;
 591                         bits = <3 3>;
 592                 };
 593         };
 594
 595         saradc: adc@ff280000 {
 596                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 597                 reg = <0x0 0xff280000 0x0 0x100>;
 598                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 599                 #io-channel-cells = <1>;
 600                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 601                 clock-names = "saradc", "apb_pclk";
 602                 resets = <&cru SRST_SARADC_P>;
 603                 reset-names = "saradc-apb";
 604                 status = "disabled";
 605         };
 606
 607         gpu: gpu@ff300000 {
 608                 compatible = "rockchip,rk3328-mali", "arm,mali-450";
 609                 reg = <0x0 0xff300000 0x0 0x30000>;
 610                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 611                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 612                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 613                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 614                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 615                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 616                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 617                 interrupt-names = "gp",
 618                                   "gpmmu",
 619                                   "pp",
 620                                   "pp0",
 621                                   "ppmmu0",
 622                                   "pp1",
 623                                   "ppmmu1";
 624                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 625                 clock-names = "bus", "core";
 626                 resets = <&cru SRST_GPU_A>;
 627         };
 628
 629         h265e_mmu: iommu@ff330200 {
 630                 compatible = "rockchip,iommu";
 631                 reg = <0x0 0xff330200 0 0x100>;
 632                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 633                 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
 634                 clock-names = "aclk", "iface";
 635                 #iommu-cells = <0>;
 636                 status = "disabled";
 637         };
 638
 639         vepu_mmu: iommu@ff340800 {
 640                 compatible = "rockchip,iommu";
 641                 reg = <0x0 0xff340800 0x0 0x40>;
 642                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 643                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 644                 clock-names = "aclk", "iface";
 645                 #iommu-cells = <0>;
 646                 status = "disabled";
 647         };
 648
 649         vpu: video-codec@ff350000 {
 650                 compatible = "rockchip,rk3328-vpu";
 651                 reg = <0x0 0xff350000 0x0 0x800>;
 652                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 653                 interrupt-names = "vdpu";
 654                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 655                 clock-names = "aclk", "hclk";
 656                 iommus = <&vpu_mmu>;
 657                 power-domains = <&power RK3328_PD_VPU>;
 658         };
 659
 660         vpu_mmu: iommu@ff350800 {
 661                 compatible = "rockchip,iommu";
 662                 reg = <0x0 0xff350800 0x0 0x40>;
 663                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 664                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 665                 clock-names = "aclk", "iface";
 666                 #iommu-cells = <0>;
 667                 power-domains = <&power RK3328_PD_VPU>;
 668         };
 669
 670         vdec: video-codec@ff360000 {
 671                 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
 672                 reg = <0x0 0xff360000 0x0 0x480>;
 673                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 674                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
 675                          <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
 676                 clock-names = "axi", "ahb", "cabac", "core";
 677                 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
 678                                   <&cru SCLK_VDEC_CORE>;
 679                 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
 680                 iommus = <&vdec_mmu>;
 681                 power-domains = <&power RK3328_PD_VIDEO>;
 682         };
 683
 684         vdec_mmu: iommu@ff360480 {
 685                 compatible = "rockchip,iommu";
 686                 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
 687                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 688                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 689                 clock-names = "aclk", "iface";
 690                 #iommu-cells = <0>;
 691                 power-domains = <&power RK3328_PD_VIDEO>;
 692         };
 693
 694         vop: vop@ff370000 {
 695                 compatible = "rockchip,rk3328-vop";
 696                 reg = <0x0 0xff370000 0x0 0x3efc>;
 697                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 698                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 699                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 700                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 701                 reset-names = "axi", "ahb", "dclk";
 702                 iommus = <&vop_mmu>;
 703                 status = "disabled";
 704
 705                 vop_out: port {
 706                         #address-cells = <1>;
 707                         #size-cells = <0>;
 708
 709                         vop_out_hdmi: endpoint@0 {
 710                                 reg = <0>;
 711                                 remote-endpoint = <&hdmi_in_vop>;
 712                         };
 713                 };
 714         };
 715
 716         vop_mmu: iommu@ff373f00 {
 717                 compatible = "rockchip,iommu";
 718                 reg = <0x0 0xff373f00 0x0 0x100>;
 719                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 720                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 721                 clock-names = "aclk", "iface";
 722                 #iommu-cells = <0>;
 723                 status = "disabled";
 724         };
 725
 726         hdmi: hdmi@ff3c0000 {
 727                 compatible = "rockchip,rk3328-dw-hdmi";
 728                 reg = <0x0 0xff3c0000 0x0 0x20000>;
 729                 reg-io-width = <4>;
 730                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 731                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 732                 clocks = <&cru PCLK_HDMI>,
 733                          <&cru SCLK_HDMI_SFC>,
 734                          <&cru SCLK_RTC32K>;
 735                 clock-names = "iahb",
 736                               "isfr",
 737                               "cec";
 738                 phys = <&hdmiphy>;
 739                 phy-names = "hdmi";
 740                 pinctrl-names = "default";
 741                 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
 742                 rockchip,grf = <&grf>;
 743                 #sound-dai-cells = <0>;
 744                 status = "disabled";
 745
 746                 ports {
 747                         #address-cells = <1>;
 748                         #size-cells = <0>;
 749
 750                         hdmi_in: port@0 {
 751                                 reg = <0>;
 752
 753                                 hdmi_in_vop: endpoint {
 754                                         remote-endpoint = <&vop_out_hdmi>;
 755                                 };
 756                         };
 757
 758                         hdmi_out: port@1 {
 759                                 reg = <1>;
 760                         };
 761                 };
 762         };
 763
 764         codec: codec@ff410000 {
 765                 compatible = "rockchip,rk3328-codec";
 766                 reg = <0x0 0xff410000 0x0 0x1000>;
 767                 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
 768                 clock-names = "pclk", "mclk";
 769                 rockchip,grf = <&grf>;
 770                 #sound-dai-cells = <0>;
 771                 status = "disabled";
 772         };
 773
 774         hdmiphy: phy@ff430000 {
 775                 compatible = "rockchip,rk3328-hdmi-phy";
 776                 reg = <0x0 0xff430000 0x0 0x10000>;
 777                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 778                 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
 779                 clock-names = "sysclk", "refoclk", "refpclk";
 780                 clock-output-names = "hdmi_phy";
 781                 #clock-cells = <0>;
 782                 nvmem-cells = <&efuse_cpu_version>;
 783                 nvmem-cell-names = "cpu-version";
 784                 #phy-cells = <0>;
 785                 status = "disabled";
 786         };
 787
 788         cru: clock-controller@ff440000 {
 789                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 790                 reg = <0x0 0xff440000 0x0 0x1000>;
 791                 rockchip,grf = <&grf>;
 792                 #clock-cells = <1>;
 793                 #reset-cells = <1>;
 794                 assigned-clocks =
 795                         /*
 796                          * CPLL should run at 1200, but that is to high for
 797                          * the initial dividers of most of its children.
 798                          * We need set cpll child clk div first,
 799                          * and then set the cpll frequency.
 800                          */
 801                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 802                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 803                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 804                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 805                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 806                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 807                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 808                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 809                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 810                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 811                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 812                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 813                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 814                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 815                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 816                         <&cru SCLK_RTC32K>;
 817                 assigned-clock-parents =
 818                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 819                         <&cru PLL_GPLL>, <&xin24m>,
 820                         <&xin24m>, <&xin24m>;
 821                 assigned-clock-rates =
 822                         <0>, <61440000>,
 823                         <0>, <24000000>,
 824                         <24000000>, <24000000>,
 825                         <15000000>, <15000000>,
 826                         <100000000>, <100000000>,
 827                         <100000000>, <100000000>,
 828                         <50000000>, <100000000>,
 829                         <100000000>, <100000000>,
 830                         <50000000>, <50000000>,
 831                         <50000000>, <50000000>,
 832                         <24000000>, <600000000>,
 833                         <491520000>, <1200000000>,
 834                         <150000000>, <75000000>,
 835                         <75000000>, <150000000>,
 836                         <75000000>, <75000000>,
 837                         <32768>;
 838         };
 839
 840         usb2phy_grf: syscon@ff450000 {
 841                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 842                              "simple-mfd";
 843                 reg = <0x0 0xff450000 0x0 0x10000>;
 844                 #address-cells = <1>;
 845                 #size-cells = <1>;
 846
 847                 u2phy: usb2phy@100 {
 848                         compatible = "rockchip,rk3328-usb2phy";
 849                         reg = <0x100 0x10>;
 850                         clocks = <&xin24m>;
 851                         clock-names = "phyclk";
 852                         clock-output-names = "usb480m_phy";
 853                         #clock-cells = <0>;
 854                         assigned-clocks = <&cru USB480M>;
 855                         assigned-clock-parents = <&u2phy>;
 856                         status = "disabled";
 857
 858                         u2phy_otg: otg-port {
 859                                 #phy-cells = <0>;
 860                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 861                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 862                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 863                                 interrupt-names = "otg-bvalid", "otg-id",
 864                                                   "linestate";
 865                                 status = "disabled";
 866                         };
 867
 868                         u2phy_host: host-port {
 869                                 #phy-cells = <0>;
 870                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 871                                 interrupt-names = "linestate";
 872                                 status = "disabled";
 873                         };
 874                 };
 875         };
 876
 877         sdmmc: mmc@ff500000 {
 878                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 879                 reg = <0x0 0xff500000 0x0 0x4000>;
 880                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 881                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 882                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 883                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 884                 fifo-depth = <0x100>;
 885                 max-frequency = <150000000>;
 886                 status = "disabled";
 887         };
 888
 889         sdio: mmc@ff510000 {
 890                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 891                 reg = <0x0 0xff510000 0x0 0x4000>;
 892                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 893                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 894                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 895                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 896                 fifo-depth = <0x100>;
 897                 max-frequency = <150000000>;
 898                 status = "disabled";
 899         };
 900
 901         emmc: mmc@ff520000 {
 902                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 903                 reg = <0x0 0xff520000 0x0 0x4000>;
 904                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 905                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 906                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 907                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 908                 fifo-depth = <0x100>;
 909                 max-frequency = <150000000>;
 910                 status = "disabled";
 911         };
 912
 913         gmac2io: ethernet@ff540000 {
 914                 compatible = "rockchip,rk3328-gmac";
 915                 reg = <0x0 0xff540000 0x0 0x10000>;
 916                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 917                 interrupt-names = "macirq";
 918                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 919                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 920                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 921                          <&cru PCLK_MAC2IO>;
 922                 clock-names = "stmmaceth", "mac_clk_rx",
 923                               "mac_clk_tx", "clk_mac_ref",
 924                               "clk_mac_refout", "aclk_mac",
 925                               "pclk_mac";
 926                 resets = <&cru SRST_GMAC2IO_A>;
 927                 reset-names = "stmmaceth";
 928                 rockchip,grf = <&grf>;
 929                 tx-fifo-depth = <2048>;
 930                 rx-fifo-depth = <4096>;
 931                 snps,txpbl = <0x4>;
 932                 status = "disabled";
 933         };
 934
 935         gmac2phy: ethernet@ff550000 {
 936                 compatible = "rockchip,rk3328-gmac";
 937                 reg = <0x0 0xff550000 0x0 0x10000>;
 938                 rockchip,grf = <&grf>;
 939                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 940                 interrupt-names = "macirq";
 941                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 942                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 943                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 944                          <&cru SCLK_MAC2PHY_OUT>;
 945                 clock-names = "stmmaceth", "mac_clk_rx",
 946                               "mac_clk_tx", "clk_mac_ref",
 947                               "aclk_mac", "pclk_mac",
 948                               "clk_macphy";
 949                 resets = <&cru SRST_GMAC2PHY_A>;
 950                 reset-names = "stmmaceth";
 951                 phy-mode = "rmii";
 952                 phy-handle = <&phy>;
 953                 tx-fifo-depth = <2048>;
 954                 rx-fifo-depth = <4096>;
 955                 snps,txpbl = <0x4>;
 956                 clock_in_out = "output";
 957                 status = "disabled";
 958
 959                 mdio {
 960                         compatible = "snps,dwmac-mdio";
 961                         #address-cells = <1>;
 962                         #size-cells = <0>;
 963
 964                         phy: ethernet-phy@0 {
 965                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 966                                 reg = <0>;
 967                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
 968                                 resets = <&cru SRST_MACPHY>;
 969                                 pinctrl-names = "default";
 970                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 971                                 phy-is-integrated;
 972                         };
 973                 };
 974         };
 975
 976         usb20_otg: usb@ff580000 {
 977                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 978                              "snps,dwc2";
 979                 reg = <0x0 0xff580000 0x0 0x40000>;
 980                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 981                 clocks = <&cru HCLK_OTG>;
 982                 clock-names = "otg";
 983                 dr_mode = "otg";
 984                 g-np-tx-fifo-size = <16>;
 985                 g-rx-fifo-size = <280>;
 986                 g-tx-fifo-size = <256 128 128 64 32 16>;
 987                 phys = <&u2phy_otg>;
 988                 phy-names = "usb2-phy";
 989                 status = "disabled";
 990         };
 991
 992         usb_host0_ehci: usb@ff5c0000 {
 993                 compatible = "generic-ehci";
 994                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 995                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 996                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 997                 phys = <&u2phy_host>;
 998                 phy-names = "usb";
 999                 status = "disabled";
1000         };
1001
1002         usb_host0_ohci: usb@ff5d0000 {
1003                 compatible = "generic-ohci";
1004                 reg = <0x0 0xff5d0000 0x0 0x10000>;
1005                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1006                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1007                 phys = <&u2phy_host>;
1008                 phy-names = "usb";
1009                 status = "disabled";
1010         };
1011
1012         usbdrd3: usb@ff600000 {
1013                 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1014                 reg = <0x0 0xff600000 0x0 0x100000>;
1015                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1016                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1017                          <&cru ACLK_USB3OTG>;
1018                 clock-names = "ref_clk", "suspend_clk",
1019                               "bus_clk";
1020                 dr_mode = "otg";
1021                 phy_type = "utmi_wide";
1022                 snps,dis-del-phy-power-chg-quirk;
1023                 snps,dis_enblslpm_quirk;
1024                 snps,dis-tx-ipgap-linecheck-quirk;
1025                 snps,dis-u2-freeclk-exists-quirk;
1026                 snps,dis_u2_susphy_quirk;
1027                 snps,dis_u3_susphy_quirk;
1028                 status = "disabled";
1029         };
1030
1031         gic: interrupt-controller@ff811000 {
1032                 compatible = "arm,gic-400";
1033                 #interrupt-cells = <3>;
1034                 #address-cells = <0>;
1035                 interrupt-controller;
1036                 reg = <0x0 0xff811000 0 0x1000>,
1037                       <0x0 0xff812000 0 0x2000>,
1038                       <0x0 0xff814000 0 0x2000>,
1039                       <0x0 0xff816000 0 0x2000>;
1040                 interrupts = <GIC_PPI 9
1041                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1042         };
1043
1044         crypto: crypto@ff060000 {
1045                 compatible = "rockchip,rk3328-crypto";
1046                 reg = <0x0 0xff060000 0x0 0x4000>;
1047                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1048                 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
1049                          <&cru SCLK_CRYPTO>;
1050                 clock-names = "hclk_master", "hclk_slave", "sclk";
1051                 resets = <&cru SRST_CRYPTO>;
1052                 reset-names = "crypto-rst";
1053         };
1054
1055         pinctrl: pinctrl {
1056                 compatible = "rockchip,rk3328-pinctrl";
1057                 rockchip,grf = <&grf>;
1058                 #address-cells = <2>;
1059                 #size-cells = <2>;
1060                 ranges;
1061
1062                 gpio0: gpio@ff210000 {
1063                         compatible = "rockchip,gpio-bank";
1064                         reg = <0x0 0xff210000 0x0 0x100>;
1065                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1066                         clocks = <&cru PCLK_GPIO0>;
1067
1068                         gpio-controller;
1069                         #gpio-cells = <2>;
1070
1071                         interrupt-controller;
1072                         #interrupt-cells = <2>;
1073                 };
1074
1075                 gpio1: gpio@ff220000 {
1076                         compatible = "rockchip,gpio-bank";
1077                         reg = <0x0 0xff220000 0x0 0x100>;
1078                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1079                         clocks = <&cru PCLK_GPIO1>;
1080
1081                         gpio-controller;
1082                         #gpio-cells = <2>;
1083
1084                         interrupt-controller;
1085                         #interrupt-cells = <2>;
1086                 };
1087
1088                 gpio2: gpio@ff230000 {
1089                         compatible = "rockchip,gpio-bank";
1090                         reg = <0x0 0xff230000 0x0 0x100>;
1091                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1092                         clocks = <&cru PCLK_GPIO2>;
1093
1094                         gpio-controller;
1095                         #gpio-cells = <2>;
1096
1097                         interrupt-controller;
1098                         #interrupt-cells = <2>;
1099                 };
1100
1101                 gpio3: gpio@ff240000 {
1102                         compatible = "rockchip,gpio-bank";
1103                         reg = <0x0 0xff240000 0x0 0x100>;
1104                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1105                         clocks = <&cru PCLK_GPIO3>;
1106
1107                         gpio-controller;
1108                         #gpio-cells = <2>;
1109
1110                         interrupt-controller;
1111                         #interrupt-cells = <2>;
1112                 };
1113
1114                 pcfg_pull_up: pcfg-pull-up {
1115                         bias-pull-up;
1116                 };
1117
1118                 pcfg_pull_down: pcfg-pull-down {
1119                         bias-pull-down;
1120                 };
1121
1122                 pcfg_pull_none: pcfg-pull-none {
1123                         bias-disable;
1124                 };
1125
1126                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1127                         bias-disable;
1128                         drive-strength = <2>;
1129                 };
1130
1131                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1132                         bias-pull-up;
1133                         drive-strength = <2>;
1134                 };
1135
1136                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1137                         bias-pull-up;
1138                         drive-strength = <4>;
1139                 };
1140
1141                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1142                         bias-disable;
1143                         drive-strength = <4>;
1144                 };
1145
1146                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1147                         bias-pull-down;
1148                         drive-strength = <4>;
1149                 };
1150
1151                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1152                         bias-disable;
1153                         drive-strength = <8>;
1154                 };
1155
1156                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1157                         bias-pull-up;
1158                         drive-strength = <8>;
1159                 };
1160
1161                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1162                         bias-disable;
1163                         drive-strength = <12>;
1164                 };
1165
1166                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1167                         bias-pull-up;
1168                         drive-strength = <12>;
1169                 };
1170
1171                 pcfg_output_high: pcfg-output-high {
1172                         output-high;
1173                 };
1174
1175                 pcfg_output_low: pcfg-output-low {
1176                         output-low;
1177                 };
1178
1179                 pcfg_input_high: pcfg-input-high {
1180                         bias-pull-up;
1181                         input-enable;
1182                 };
1183
1184                 pcfg_input: pcfg-input {
1185                         input-enable;
1186                 };
1187
1188                 i2c0 {
1189                         i2c0_xfer: i2c0-xfer {
1190                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1191                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1192                         };
1193                 };
1194
1195                 i2c1 {
1196                         i2c1_xfer: i2c1-xfer {
1197                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1198                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1199                         };
1200                 };
1201
1202                 i2c2 {
1203                         i2c2_xfer: i2c2-xfer {
1204                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1205                                                 <2 RK_PB6 1 &pcfg_pull_none>;
1206                         };
1207                 };
1208
1209                 i2c3 {
1210                         i2c3_xfer: i2c3-xfer {
1211                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1212                                                 <0 RK_PA6 2 &pcfg_pull_none>;
1213                         };
1214                         i2c3_pins: i2c3-pins {
1215                                 rockchip,pins =
1216                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1217                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1218                         };
1219                 };
1220
1221                 hdmi_i2c {
1222                         hdmii2c_xfer: hdmii2c-xfer {
1223                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1224                                                 <0 RK_PA6 1 &pcfg_pull_none>;
1225                         };
1226                 };
1227
1228                 pdm-0 {
1229                         pdmm0_clk: pdmm0-clk {
1230                                 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1231                         };
1232
1233                         pdmm0_fsync: pdmm0-fsync {
1234                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1235                         };
1236
1237                         pdmm0_sdi0: pdmm0-sdi0 {
1238                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1239                         };
1240
1241                         pdmm0_sdi1: pdmm0-sdi1 {
1242                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1243                         };
1244
1245                         pdmm0_sdi2: pdmm0-sdi2 {
1246                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1247                         };
1248
1249                         pdmm0_sdi3: pdmm0-sdi3 {
1250                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1251                         };
1252
1253                         pdmm0_clk_sleep: pdmm0-clk-sleep {
1254                                 rockchip,pins =
1255                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1256                         };
1257
1258                         pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1259                                 rockchip,pins =
1260                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1261                         };
1262
1263                         pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1264                                 rockchip,pins =
1265                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1266                         };
1267
1268                         pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1269                                 rockchip,pins =
1270                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1271                         };
1272
1273                         pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1274                                 rockchip,pins =
1275                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1276                         };
1277
1278                         pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1279                                 rockchip,pins =
1280                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1281                         };
1282                 };
1283
1284                 tsadc {
1285                         otp_pin: otp-pin {
1286                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1287                         };
1288
1289                         otp_out: otp-out {
1290                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1291                         };
1292                 };
1293
1294                 uart0 {
1295                         uart0_xfer: uart0-xfer {
1296                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1297                                                 <1 RK_PB0 1 &pcfg_pull_up>;
1298                         };
1299
1300                         uart0_cts: uart0-cts {
1301                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1302                         };
1303
1304                         uart0_rts: uart0-rts {
1305                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1306                         };
1307
1308                         uart0_rts_pin: uart0-rts-pin {
1309                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1310                         };
1311                 };
1312
1313                 uart1 {
1314                         uart1_xfer: uart1-xfer {
1315                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1316                                                 <3 RK_PA6 4 &pcfg_pull_up>;
1317                         };
1318
1319                         uart1_cts: uart1-cts {
1320                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1321                         };
1322
1323                         uart1_rts: uart1-rts {
1324                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1325                         };
1326
1327                         uart1_rts_pin: uart1-rts-pin {
1328                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1329                         };
1330                 };
1331
1332                 uart2-0 {
1333                         uart2m0_xfer: uart2m0-xfer {
1334                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1335                                                 <1 RK_PA1 2 &pcfg_pull_up>;
1336                         };
1337                 };
1338
1339                 uart2-1 {
1340                         uart2m1_xfer: uart2m1-xfer {
1341                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1342                                                 <2 RK_PA1 1 &pcfg_pull_up>;
1343                         };
1344                 };
1345
1346                 spi0-0 {
1347                         spi0m0_clk: spi0m0-clk {
1348                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1349                         };
1350
1351                         spi0m0_cs0: spi0m0-cs0 {
1352                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1353                         };
1354
1355                         spi0m0_tx: spi0m0-tx {
1356                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1357                         };
1358
1359                         spi0m0_rx: spi0m0-rx {
1360                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1361                         };
1362
1363                         spi0m0_cs1: spi0m0-cs1 {
1364                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1365                         };
1366                 };
1367
1368                 spi0-1 {
1369                         spi0m1_clk: spi0m1-clk {
1370                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1371                         };
1372
1373                         spi0m1_cs0: spi0m1-cs0 {
1374                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1375                         };
1376
1377                         spi0m1_tx: spi0m1-tx {
1378                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1379                         };
1380
1381                         spi0m1_rx: spi0m1-rx {
1382                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1383                         };
1384
1385                         spi0m1_cs1: spi0m1-cs1 {
1386                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1387                         };
1388                 };
1389
1390                 spi0-2 {
1391                         spi0m2_clk: spi0m2-clk {
1392                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1393                         };
1394
1395                         spi0m2_cs0: spi0m2-cs0 {
1396                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1397                         };
1398
1399                         spi0m2_tx: spi0m2-tx {
1400                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1401                         };
1402
1403                         spi0m2_rx: spi0m2-rx {
1404                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1405                         };
1406                 };
1407
1408                 i2s1 {
1409                         i2s1_mclk: i2s1-mclk {
1410                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1411                         };
1412
1413                         i2s1_sclk: i2s1-sclk {
1414                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1415                         };
1416
1417                         i2s1_lrckrx: i2s1-lrckrx {
1418                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1419                         };
1420
1421                         i2s1_lrcktx: i2s1-lrcktx {
1422                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1423                         };
1424
1425                         i2s1_sdi: i2s1-sdi {
1426                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1427                         };
1428
1429                         i2s1_sdo: i2s1-sdo {
1430                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1431                         };
1432
1433                         i2s1_sdio1: i2s1-sdio1 {
1434                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1435                         };
1436
1437                         i2s1_sdio2: i2s1-sdio2 {
1438                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1439                         };
1440
1441                         i2s1_sdio3: i2s1-sdio3 {
1442                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1443                         };
1444
1445                         i2s1_sleep: i2s1-sleep {
1446                                 rockchip,pins =
1447                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1448                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1449                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1450                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1451                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1452                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1453                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1454                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1455                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1456                         };
1457                 };
1458
1459                 i2s2-0 {
1460                         i2s2m0_mclk: i2s2m0-mclk {
1461                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1462                         };
1463
1464                         i2s2m0_sclk: i2s2m0-sclk {
1465                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1466                         };
1467
1468                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1469                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1470                         };
1471
1472                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1473                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1474                         };
1475
1476                         i2s2m0_sdi: i2s2m0-sdi {
1477                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1478                         };
1479
1480                         i2s2m0_sdo: i2s2m0-sdo {
1481                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1482                         };
1483
1484                         i2s2m0_sleep: i2s2m0-sleep {
1485                                 rockchip,pins =
1486                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1487                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1488                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1489                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1490                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1491                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1492                         };
1493                 };
1494
1495                 i2s2-1 {
1496                         i2s2m1_mclk: i2s2m1-mclk {
1497                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1498                         };
1499
1500                         i2s2m1_sclk: i2s2m1-sclk {
1501                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1502                         };
1503
1504                         i2s2m1_lrckrx: i2sm1-lrckrx {
1505                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1506                         };
1507
1508                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1509                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1510                         };
1511
1512                         i2s2m1_sdi: i2s2m1-sdi {
1513                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1514                         };
1515
1516                         i2s2m1_sdo: i2s2m1-sdo {
1517                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1518                         };
1519
1520                         i2s2m1_sleep: i2s2m1-sleep {
1521                                 rockchip,pins =
1522                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1523                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1524                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1525                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1526                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1527                         };
1528                 };
1529
1530                 spdif-0 {
1531                         spdifm0_tx: spdifm0-tx {
1532                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1533                         };
1534                 };
1535
1536                 spdif-1 {
1537                         spdifm1_tx: spdifm1-tx {
1538                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1539                         };
1540                 };
1541
1542                 spdif-2 {
1543                         spdifm2_tx: spdifm2-tx {
1544                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1545                         };
1546                 };
1547
1548                 sdmmc0-0 {
1549                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1550                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1551                         };
1552
1553                         sdmmc0m0_pin: sdmmc0m0-pin {
1554                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1555                         };
1556                 };
1557
1558                 sdmmc0-1 {
1559                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1560                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1561                         };
1562
1563                         sdmmc0m1_pin: sdmmc0m1-pin {
1564                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1565                         };
1566                 };
1567
1568                 sdmmc0 {
1569                         sdmmc0_clk: sdmmc0-clk {
1570                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1571                         };
1572
1573                         sdmmc0_cmd: sdmmc0-cmd {
1574                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1575                         };
1576
1577                         sdmmc0_dectn: sdmmc0-dectn {
1578                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1579                         };
1580
1581                         sdmmc0_wrprt: sdmmc0-wrprt {
1582                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1583                         };
1584
1585                         sdmmc0_bus1: sdmmc0-bus1 {
1586                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1587                         };
1588
1589                         sdmmc0_bus4: sdmmc0-bus4 {
1590                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1591                                                 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1592                                                 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1593                                                 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1594                         };
1595
1596                         sdmmc0_pins: sdmmc0-pins {
1597                                 rockchip,pins =
1598                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1599                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1600                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1601                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1602                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1603                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1604                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1605                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1606                         };
1607                 };
1608
1609                 sdmmc0ext {
1610                         sdmmc0ext_clk: sdmmc0ext-clk {
1611                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1612                         };
1613
1614                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1615                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1616                         };
1617
1618                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1619                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1620                         };
1621
1622                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1623                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1624                         };
1625
1626                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1627                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1628                         };
1629
1630                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1631                                 rockchip,pins =
1632                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1633                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1634                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1635                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1636                         };
1637
1638                         sdmmc0ext_pins: sdmmc0ext-pins {
1639                                 rockchip,pins =
1640                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1641                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1642                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1643                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1644                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1645                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1646                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1647                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1648                         };
1649                 };
1650
1651                 sdmmc1 {
1652                         sdmmc1_clk: sdmmc1-clk {
1653                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1654                         };
1655
1656                         sdmmc1_cmd: sdmmc1-cmd {
1657                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1658                         };
1659
1660                         sdmmc1_pwren: sdmmc1-pwren {
1661                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1662                         };
1663
1664                         sdmmc1_wrprt: sdmmc1-wrprt {
1665                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1666                         };
1667
1668                         sdmmc1_dectn: sdmmc1-dectn {
1669                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1670                         };
1671
1672                         sdmmc1_bus1: sdmmc1-bus1 {
1673                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1674                         };
1675
1676                         sdmmc1_bus4: sdmmc1-bus4 {
1677                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1678                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1679                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1680                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1681                         };
1682
1683                         sdmmc1_pins: sdmmc1-pins {
1684                                 rockchip,pins =
1685                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1686                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1687                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1688                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1689                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1690                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1691                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1692                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1693                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1694                         };
1695                 };
1696
1697                 emmc {
1698                         emmc_clk: emmc-clk {
1699                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1700                         };
1701
1702                         emmc_cmd: emmc-cmd {
1703                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1704                         };
1705
1706                         emmc_pwren: emmc-pwren {
1707                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1708                         };
1709
1710                         emmc_rstnout: emmc-rstnout {
1711                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1712                         };
1713
1714                         emmc_bus1: emmc-bus1 {
1715                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1716                         };
1717
1718                         emmc_bus4: emmc-bus4 {
1719                                 rockchip,pins =
1720                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1721                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1722                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1723                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1724                         };
1725
1726                         emmc_bus8: emmc-bus8 {
1727                                 rockchip,pins =
1728                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1729                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1730                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1731                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1732                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1733                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1734                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1735                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1736                         };
1737                 };
1738
1739                 pwm0 {
1740                         pwm0_pin: pwm0-pin {
1741                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1742                         };
1743                 };
1744
1745                 pwm1 {
1746                         pwm1_pin: pwm1-pin {
1747                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1748                         };
1749                 };
1750
1751                 pwm2 {
1752                         pwm2_pin: pwm2-pin {
1753                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1754                         };
1755                 };
1756
1757                 pwmir {
1758                         pwmir_pin: pwmir-pin {
1759                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1760                         };
1761                 };
1762
1763                 gmac-1 {
1764                         rgmiim1_pins: rgmiim1-pins {
1765                                 rockchip,pins =
1766                                         /* mac_txclk */
1767                                         <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1768                                         /* mac_rxclk */
1769                                         <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1770                                         /* mac_mdio */
1771                                         <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1772                                         /* mac_txen */
1773                                         <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1774                                         /* mac_clk */
1775                                         <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1776                                         /* mac_rxdv */
1777                                         <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1778                                         /* mac_mdc */
1779                                         <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1780                                         /* mac_rxd1 */
1781                                         <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1782                                         /* mac_rxd0 */
1783                                         <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1784                                         /* mac_txd1 */
1785                                         <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1786                                         /* mac_txd0 */
1787                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1788                                         /* mac_rxd3 */
1789                                         <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1790                                         /* mac_rxd2 */
1791                                         <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1792                                         /* mac_txd3 */
1793                                         <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1794                                         /* mac_txd2 */
1795                                         <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1796
1797                                         /* mac_txclk */
1798                                         <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1799                                         /* mac_txen */
1800                                         <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1801                                         /* mac_clk */
1802                                         <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1803                                         /* mac_txd1 */
1804                                         <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1805                                         /* mac_txd0 */
1806                                         <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1807                                         /* mac_txd3 */
1808                                         <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1809                                         /* mac_txd2 */
1810                                         <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1811                         };
1812
1813                         rmiim1_pins: rmiim1-pins {
1814                                 rockchip,pins =
1815                                         /* mac_mdio */
1816                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1817                                         /* mac_txen */
1818                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1819                                         /* mac_clk */
1820                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1821                                         /* mac_rxer */
1822                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1823                                         /* mac_rxdv */
1824                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1825                                         /* mac_mdc */
1826                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1827                                         /* mac_rxd1 */
1828                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1829                                         /* mac_rxd0 */
1830                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1831                                         /* mac_txd1 */
1832                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1833                                         /* mac_txd0 */
1834                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1835
1836                                         /* mac_mdio */
1837                                         <0 RK_PB3 1 &pcfg_pull_none>,
1838                                         /* mac_txen */
1839                                         <0 RK_PB4 1 &pcfg_pull_none>,
1840                                         /* mac_clk */
1841                                         <0 RK_PD0 1 &pcfg_pull_none>,
1842                                         /* mac_mdc */
1843                                         <0 RK_PC3 1 &pcfg_pull_none>,
1844                                         /* mac_txd1 */
1845                                         <0 RK_PC0 1 &pcfg_pull_none>,
1846                                         /* mac_txd0 */
1847                                         <0 RK_PC1 1 &pcfg_pull_none>;
1848                         };
1849                 };
1850
1851                 gmac2phy {
1852                         fephyled_speed10: fephyled-speed10 {
1853                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1854                         };
1855
1856                         fephyled_duplex: fephyled-duplex {
1857                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1858                         };
1859
1860                         fephyled_rxm1: fephyled-rxm1 {
1861                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1862                         };
1863
1864                         fephyled_txm1: fephyled-txm1 {
1865                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1866                         };
1867
1868                         fephyled_linkm1: fephyled-linkm1 {
1869                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1870                         };
1871                 };
1872
1873                 tsadc_pin {
1874                         tsadc_int: tsadc-int {
1875                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1876                         };
1877                         tsadc_pin: tsadc-pin {
1878                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1879                         };
1880                 };
1881
1882                 hdmi_pin {
1883                         hdmi_cec: hdmi-cec {
1884                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1885                         };
1886
1887                         hdmi_hpd: hdmi-hpd {
1888                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1889                         };
1890                 };
1891
1892                 cif-0 {
1893                         dvp_d2d9_m0:dvp-d2d9-m0 {
1894                                 rockchip,pins =
1895                                         /* cif_d0 */
1896                                         <3 RK_PA4 2 &pcfg_pull_none>,
1897                                         /* cif_d1 */
1898                                         <3 RK_PA5 2 &pcfg_pull_none>,
1899                                         /* cif_d2 */
1900                                         <3 RK_PA6 2 &pcfg_pull_none>,
1901                                         /* cif_d3 */
1902                                         <3 RK_PA7 2 &pcfg_pull_none>,
1903                                         /* cif_d4 */
1904                                         <3 RK_PB0 2 &pcfg_pull_none>,
1905                                         /* cif_d5m0 */
1906                                         <3 RK_PB1 2 &pcfg_pull_none>,
1907                                         /* cif_d6m0 */
1908                                         <3 RK_PB2 2 &pcfg_pull_none>,
1909                                         /* cif_d7m0 */
1910                                         <3 RK_PB3 2 &pcfg_pull_none>,
1911                                         /* cif_href */
1912                                         <3 RK_PA1 2 &pcfg_pull_none>,
1913                                         /* cif_vsync */
1914                                         <3 RK_PA0 2 &pcfg_pull_none>,
1915                                         /* cif_clkoutm0 */
1916                                         <3 RK_PA3 2 &pcfg_pull_none>,
1917                                         /* cif_clkin */
1918                                         <3 RK_PA2 2 &pcfg_pull_none>;
1919                         };
1920                 };
1921
1922                 cif-1 {
1923                         dvp_d2d9_m1:dvp-d2d9-m1 {
1924                                 rockchip,pins =
1925                                         /* cif_d0 */
1926                                         <3 RK_PA4 2 &pcfg_pull_none>,
1927                                         /* cif_d1 */
1928                                         <3 RK_PA5 2 &pcfg_pull_none>,
1929                                         /* cif_d2 */
1930                                         <3 RK_PA6 2 &pcfg_pull_none>,
1931                                         /* cif_d3 */
1932                                         <3 RK_PA7 2 &pcfg_pull_none>,
1933                                         /* cif_d4 */
1934                                         <3 RK_PB0 2 &pcfg_pull_none>,
1935                                         /* cif_d5m1 */
1936                                         <2 RK_PC0 4 &pcfg_pull_none>,
1937                                         /* cif_d6m1 */
1938                                         <2 RK_PC1 4 &pcfg_pull_none>,
1939                                         /* cif_d7m1 */
1940                                         <2 RK_PC2 4 &pcfg_pull_none>,
1941                                         /* cif_href */
1942                                         <3 RK_PA1 2 &pcfg_pull_none>,
1943                                         /* cif_vsync */
1944                                         <3 RK_PA0 2 &pcfg_pull_none>,
1945                                         /* cif_clkoutm1 */
1946                                         <2 RK_PB7 4 &pcfg_pull_none>,
1947                                         /* cif_clkin */
1948                                         <3 RK_PA2 2 &pcfg_pull_none>;
1949                         };
1950                 };
1951         };
1952 };