arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3328-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3328-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3328";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 serial0 = &uart0;
  24                 serial1 = &uart1;
  25                 serial2 = &uart2;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 ethernet0 = &gmac2io;
  31                 ethernet1 = &gmac2phy;
  32         };
  33
  34         cpus {
  35                 #address-cells = <2>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53", "arm,armv8";
  41                         reg = <0x0 0x0>;
  42                         clocks = <&cru ARMCLK>;
  43                         #cooling-cells = <2>;
  44                         dynamic-power-coefficient = <120>;
  45                         enable-method = "psci";
  46                         next-level-cache = <&l2>;
  47                         operating-points-v2 = <&cpu0_opp_table>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53", "arm,armv8";
  53                         reg = <0x0 0x1>;
  54                         clocks = <&cru ARMCLK>;
  55                         #cooling-cells = <2>;
  56                         dynamic-power-coefficient = <120>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&l2>;
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                 };
  61
  62                 cpu2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x0 0x2>;
  66                         clocks = <&cru ARMCLK>;
  67                         #cooling-cells = <2>;
  68                         dynamic-power-coefficient = <120>;
  69                         enable-method = "psci";
  70                         next-level-cache = <&l2>;
  71                         operating-points-v2 = <&cpu0_opp_table>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53", "arm,armv8";
  77                         reg = <0x0 0x3>;
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>;
  80                         dynamic-power-coefficient = <120>;
  81                         enable-method = "psci";
  82                         next-level-cache = <&l2>;
  83                         operating-points-v2 = <&cpu0_opp_table>;
  84                 };
  85
  86                 l2: l2-cache0 {
  87                         compatible = "cache";
  88                 };
  89         };
  90
  91         cpu0_opp_table: opp_table0 {
  92                 compatible = "operating-points-v2";
  93                 opp-shared;
  94
  95                 opp-408000000 {
  96                         opp-hz = /bits/ 64 <408000000>;
  97                         opp-microvolt = <950000>;
  98                         clock-latency-ns = <40000>;
  99                         opp-suspend;
 100                 };
 101                 opp-600000000 {
 102                         opp-hz = /bits/ 64 <600000000>;
 103                         opp-microvolt = <950000>;
 104                         clock-latency-ns = <40000>;
 105                 };
 106                 opp-816000000 {
 107                         opp-hz = /bits/ 64 <816000000>;
 108                         opp-microvolt = <1000000>;
 109                         clock-latency-ns = <40000>;
 110                 };
 111                 opp-1008000000 {
 112                         opp-hz = /bits/ 64 <1008000000>;
 113                         opp-microvolt = <1100000>;
 114                         clock-latency-ns = <40000>;
 115                 };
 116                 opp-1200000000 {
 117                         opp-hz = /bits/ 64 <1200000000>;
 118                         opp-microvolt = <1225000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp-1296000000 {
 122                         opp-hz = /bits/ 64 <1296000000>;
 123                         opp-microvolt = <1300000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126         };
 127
 128         amba {
 129                 compatible = "simple-bus";
 130                 #address-cells = <2>;
 131                 #size-cells = <2>;
 132                 ranges;
 133
 134                 dmac: dmac@ff1f0000 {
 135                         compatible = "arm,pl330", "arm,primecell";
 136                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 137                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 139                         clocks = <&cru ACLK_DMAC>;
 140                         clock-names = "apb_pclk";
 141                         #dma-cells = <1>;
 142                 };
 143         };
 144
 145         arm-pmu {
 146                 compatible = "arm,cortex-a53-pmu";
 147                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 151                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 152         };
 153
 154         psci {
 155                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 156                 method = "smc";
 157         };
 158
 159         timer {
 160                 compatible = "arm,armv8-timer";
 161                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 162                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 163                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 164                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 165         };
 166
 167         xin24m: xin24m {
 168                 compatible = "fixed-clock";
 169                 #clock-cells = <0>;
 170                 clock-frequency = <24000000>;
 171                 clock-output-names = "xin24m";
 172         };
 173
 174         i2s0: i2s@ff000000 {
 175                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 176                 reg = <0x0 0xff000000 0x0 0x1000>;
 177                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 178                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 179                 clock-names = "i2s_clk", "i2s_hclk";
 180                 dmas = <&dmac 11>, <&dmac 12>;
 181                 dma-names = "tx", "rx";
 182                 status = "disabled";
 183         };
 184
 185         i2s1: i2s@ff010000 {
 186                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 187                 reg = <0x0 0xff010000 0x0 0x1000>;
 188                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 190                 clock-names = "i2s_clk", "i2s_hclk";
 191                 dmas = <&dmac 14>, <&dmac 15>;
 192                 dma-names = "tx", "rx";
 193                 status = "disabled";
 194         };
 195
 196         i2s2: i2s@ff020000 {
 197                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 198                 reg = <0x0 0xff020000 0x0 0x1000>;
 199                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 201                 clock-names = "i2s_clk", "i2s_hclk";
 202                 dmas = <&dmac 0>, <&dmac 1>;
 203                 dma-names = "tx", "rx";
 204                 status = "disabled";
 205         };
 206
 207         spdif: spdif@ff030000 {
 208                 compatible = "rockchip,rk3328-spdif";
 209                 reg = <0x0 0xff030000 0x0 0x1000>;
 210                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 211                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 212                 clock-names = "mclk", "hclk";
 213                 dmas = <&dmac 10>;
 214                 dma-names = "tx";
 215                 pinctrl-names = "default";
 216                 pinctrl-0 = <&spdifm2_tx>;
 217                 status = "disabled";
 218         };
 219
 220         pdm: pdm@ff040000 {
 221                 compatible = "rockchip,pdm";
 222                 reg = <0x0 0xff040000 0x0 0x1000>;
 223                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 224                 clock-names = "pdm_clk", "pdm_hclk";
 225                 dmas = <&dmac 16>;
 226                 dma-names = "rx";
 227                 pinctrl-names = "default", "sleep";
 228                 pinctrl-0 = <&pdmm0_clk
 229                              &pdmm0_sdi0
 230                              &pdmm0_sdi1
 231                              &pdmm0_sdi2
 232                              &pdmm0_sdi3>;
 233                 pinctrl-1 = <&pdmm0_clk_sleep
 234                              &pdmm0_sdi0_sleep
 235                              &pdmm0_sdi1_sleep
 236                              &pdmm0_sdi2_sleep
 237                              &pdmm0_sdi3_sleep>;
 238                 status = "disabled";
 239         };
 240
 241         grf: syscon@ff100000 {
 242                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 243                 reg = <0x0 0xff100000 0x0 0x1000>;
 244                 #address-cells = <1>;
 245                 #size-cells = <1>;
 246
 247                 io_domains: io-domains {
 248                         compatible = "rockchip,rk3328-io-voltage-domain";
 249                         status = "disabled";
 250                 };
 251
 252                 grf_gpio: grf-gpio {
 253                         compatible = "rockchip,rk3328-grf-gpio";
 254                         gpio-controller;
 255                         #gpio-cells = <2>;
 256                 };
 257
 258                 power: power-controller {
 259                         compatible = "rockchip,rk3328-power-controller";
 260                         #power-domain-cells = <1>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263
 264                         pd_hevc@RK3328_PD_HEVC {
 265                                 reg = <RK3328_PD_HEVC>;
 266                         };
 267                         pd_video@RK3328_PD_VIDEO {
 268                                 reg = <RK3328_PD_VIDEO>;
 269                         };
 270                         pd_vpu@RK3328_PD_VPU {
 271                                 reg = <RK3328_PD_VPU>;
 272                         };
 273                 };
 274
 275                 reboot-mode {
 276                         compatible = "syscon-reboot-mode";
 277                         offset = <0x5c8>;
 278                         mode-normal = <BOOT_NORMAL>;
 279                         mode-recovery = <BOOT_RECOVERY>;
 280                         mode-bootloader = <BOOT_FASTBOOT>;
 281                         mode-loader = <BOOT_BL_DOWNLOAD>;
 282                 };
 283         };
 284
 285         uart0: serial@ff110000 {
 286                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 287                 reg = <0x0 0xff110000 0x0 0x100>;
 288                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 289                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 290                 clock-names = "baudclk", "apb_pclk";
 291                 dmas = <&dmac 2>, <&dmac 3>;
 292                 dma-names = "tx", "rx";
 293                 pinctrl-names = "default";
 294                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 295                 reg-io-width = <4>;
 296                 reg-shift = <2>;
 297                 status = "disabled";
 298         };
 299
 300         uart1: serial@ff120000 {
 301                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 302                 reg = <0x0 0xff120000 0x0 0x100>;
 303                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 305                 clock-names = "baudclk", "apb_pclk";
 306                 dmas = <&dmac 4>, <&dmac 5>;
 307                 dma-names = "tx", "rx";
 308                 pinctrl-names = "default";
 309                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 310                 reg-io-width = <4>;
 311                 reg-shift = <2>;
 312                 status = "disabled";
 313         };
 314
 315         uart2: serial@ff130000 {
 316                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 317                 reg = <0x0 0xff130000 0x0 0x100>;
 318                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 320                 clock-names = "baudclk", "apb_pclk";
 321                 dmas = <&dmac 6>, <&dmac 7>;
 322                 dma-names = "tx", "rx";
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&uart2m1_xfer>;
 325                 reg-io-width = <4>;
 326                 reg-shift = <2>;
 327                 status = "disabled";
 328         };
 329
 330         i2c0: i2c@ff150000 {
 331                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 332                 reg = <0x0 0xff150000 0x0 0x1000>;
 333                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 337                 clock-names = "i2c", "pclk";
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&i2c0_xfer>;
 340                 status = "disabled";
 341         };
 342
 343         i2c1: i2c@ff160000 {
 344                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 345                 reg = <0x0 0xff160000 0x0 0x1000>;
 346                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 350                 clock-names = "i2c", "pclk";
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&i2c1_xfer>;
 353                 status = "disabled";
 354         };
 355
 356         i2c2: i2c@ff170000 {
 357                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 358                 reg = <0x0 0xff170000 0x0 0x1000>;
 359                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 363                 clock-names = "i2c", "pclk";
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&i2c2_xfer>;
 366                 status = "disabled";
 367         };
 368
 369         i2c3: i2c@ff180000 {
 370                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 371                 reg = <0x0 0xff180000 0x0 0x1000>;
 372                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 376                 clock-names = "i2c", "pclk";
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&i2c3_xfer>;
 379                 status = "disabled";
 380         };
 381
 382         spi0: spi@ff190000 {
 383                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 384                 reg = <0x0 0xff190000 0x0 0x1000>;
 385                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 389                 clock-names = "spiclk", "apb_pclk";
 390                 dmas = <&dmac 8>, <&dmac 9>;
 391                 dma-names = "tx", "rx";
 392                 pinctrl-names = "default";
 393                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 394                 status = "disabled";
 395         };
 396
 397         wdt: watchdog@ff1a0000 {
 398                 compatible = "snps,dw-wdt";
 399                 reg = <0x0 0xff1a0000 0x0 0x100>;
 400                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 401         };
 402
 403         pwm0: pwm@ff1b0000 {
 404                 compatible = "rockchip,rk3328-pwm";
 405                 reg = <0x0 0xff1b0000 0x0 0x10>;
 406                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 407                 clock-names = "pwm", "pclk";
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&pwm0_pin>;
 410                 #pwm-cells = <3>;
 411                 status = "disabled";
 412         };
 413
 414         pwm1: pwm@ff1b0010 {
 415                 compatible = "rockchip,rk3328-pwm";
 416                 reg = <0x0 0xff1b0010 0x0 0x10>;
 417                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 418                 clock-names = "pwm", "pclk";
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&pwm1_pin>;
 421                 #pwm-cells = <3>;
 422                 status = "disabled";
 423         };
 424
 425         pwm2: pwm@ff1b0020 {
 426                 compatible = "rockchip,rk3328-pwm";
 427                 reg = <0x0 0xff1b0020 0x0 0x10>;
 428                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 429                 clock-names = "pwm", "pclk";
 430                 pinctrl-names = "default";
 431                 pinctrl-0 = <&pwm2_pin>;
 432                 #pwm-cells = <3>;
 433                 status = "disabled";
 434         };
 435
 436         pwm3: pwm@ff1b0030 {
 437                 compatible = "rockchip,rk3328-pwm";
 438                 reg = <0x0 0xff1b0030 0x0 0x10>;
 439                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 440                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 441                 clock-names = "pwm", "pclk";
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&pwmir_pin>;
 444                 #pwm-cells = <3>;
 445                 status = "disabled";
 446         };
 447
 448         thermal-zones {
 449                 soc_thermal: soc-thermal {
 450                         polling-delay-passive = <20>;
 451                         polling-delay = <1000>;
 452                         sustainable-power = <1000>;
 453
 454                         thermal-sensors = <&tsadc 0>;
 455
 456                         trips {
 457                                 threshold: trip-point0 {
 458                                         temperature = <70000>;
 459                                         hysteresis = <2000>;
 460                                         type = "passive";
 461                                 };
 462                                 target: trip-point1 {
 463                                         temperature = <85000>;
 464                                         hysteresis = <2000>;
 465                                         type = "passive";
 466                                 };
 467                                 soc_crit: soc-crit {
 468                                         temperature = <95000>;
 469                                         hysteresis = <2000>;
 470                                         type = "critical";
 471                                 };
 472                         };
 473
 474                         cooling-maps {
 475                                 map0 {
 476                                         trip = <&target>;
 477                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 478                                         contribution = <4096>;
 479                                 };
 480                         };
 481                 };
 482
 483         };
 484
 485         tsadc: tsadc@ff250000 {
 486                 compatible = "rockchip,rk3328-tsadc";
 487                 reg = <0x0 0xff250000 0x0 0x100>;
 488                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 489                 assigned-clocks = <&cru SCLK_TSADC>;
 490                 assigned-clock-rates = <50000>;
 491                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 492                 clock-names = "tsadc", "apb_pclk";
 493                 pinctrl-names = "init", "default", "sleep";
 494                 pinctrl-0 = <&otp_gpio>;
 495                 pinctrl-1 = <&otp_out>;
 496                 pinctrl-2 = <&otp_gpio>;
 497                 resets = <&cru SRST_TSADC>;
 498                 reset-names = "tsadc-apb";
 499                 rockchip,grf = <&grf>;
 500                 rockchip,hw-tshut-temp = <100000>;
 501                 #thermal-sensor-cells = <1>;
 502                 status = "disabled";
 503         };
 504
 505         efuse: efuse@ff260000 {
 506                 compatible = "rockchip,rk3328-efuse";
 507                 reg = <0x0 0xff260000 0x0 0x50>;
 508                 #address-cells = <1>;
 509                 #size-cells = <1>;
 510                 clocks = <&cru SCLK_EFUSE>;
 511                 clock-names = "pclk_efuse";
 512                 rockchip,efuse-size = <0x20>;
 513
 514                 /* Data cells */
 515                 efuse_id: id@7 {
 516                         reg = <0x07 0x10>;
 517                 };
 518                 cpu_leakage: cpu-leakage@17 {
 519                         reg = <0x17 0x1>;
 520                 };
 521                 logic_leakage: logic-leakage@19 {
 522                         reg = <0x19 0x1>;
 523                 };
 524                 efuse_cpu_version: cpu-version@1a {
 525                         reg = <0x1a 0x1>;
 526                         bits = <3 3>;
 527                 };
 528         };
 529
 530         saradc: adc@ff280000 {
 531                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 532                 reg = <0x0 0xff280000 0x0 0x100>;
 533                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 534                 #io-channel-cells = <1>;
 535                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 536                 clock-names = "saradc", "apb_pclk";
 537                 resets = <&cru SRST_SARADC_P>;
 538                 reset-names = "saradc-apb";
 539                 status = "disabled";
 540         };
 541
 542         gpu: gpu@ff300000 {
 543                 compatible = "rockchip,rk3328-mali", "arm,mali-450";
 544                 reg = <0x0 0xff300000 0x0 0x40000>;
 545                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 546                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 547                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 548                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 549                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 550                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 551                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 552                 interrupt-names = "gp",
 553                                   "gpmmu",
 554                                   "pp",
 555                                   "pp0",
 556                                   "ppmmu0",
 557                                   "pp1",
 558                                   "ppmmu1";
 559                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 560                 clock-names = "bus", "core";
 561                 resets = <&cru SRST_GPU_A>;
 562         };
 563
 564         h265e_mmu: iommu@ff330200 {
 565                 compatible = "rockchip,iommu";
 566                 reg = <0x0 0xff330200 0 0x100>;
 567                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 568                 interrupt-names = "h265e_mmu";
 569                 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
 570                 clock-names = "aclk", "iface";
 571                 #iommu-cells = <0>;
 572                 status = "disabled";
 573         };
 574
 575         vepu_mmu: iommu@ff340800 {
 576                 compatible = "rockchip,iommu";
 577                 reg = <0x0 0xff340800 0x0 0x40>;
 578                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 579                 interrupt-names = "vepu_mmu";
 580                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 581                 clock-names = "aclk", "iface";
 582                 #iommu-cells = <0>;
 583                 status = "disabled";
 584         };
 585
 586         vpu_mmu: iommu@ff350800 {
 587                 compatible = "rockchip,iommu";
 588                 reg = <0x0 0xff350800 0x0 0x40>;
 589                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 590                 interrupt-names = "vpu_mmu";
 591                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 592                 clock-names = "aclk", "iface";
 593                 #iommu-cells = <0>;
 594                 status = "disabled";
 595         };
 596
 597         rkvdec_mmu: iommu@ff360480 {
 598                 compatible = "rockchip,iommu";
 599                 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
 600                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 601                 interrupt-names = "rkvdec_mmu";
 602                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 603                 clock-names = "aclk", "iface";
 604                 #iommu-cells = <0>;
 605                 status = "disabled";
 606         };
 607
 608         vop_mmu: iommu@ff373f00 {
 609                 compatible = "rockchip,iommu";
 610                 reg = <0x0 0xff373f00 0x0 0x100>;
 611                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 612                 interrupt-names = "vop_mmu";
 613                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 614                 clock-names = "aclk", "iface";
 615                 #iommu-cells = <0>;
 616                 status = "disabled";
 617         };
 618
 619         cru: clock-controller@ff440000 {
 620                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 621                 reg = <0x0 0xff440000 0x0 0x1000>;
 622                 rockchip,grf = <&grf>;
 623                 #clock-cells = <1>;
 624                 #reset-cells = <1>;
 625                 assigned-clocks =
 626                         /*
 627                          * CPLL should run at 1200, but that is to high for
 628                          * the initial dividers of most of its children.
 629                          * We need set cpll child clk div first,
 630                          * and then set the cpll frequency.
 631                          */
 632                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 633                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 634                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 635                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 636                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 637                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 638                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 639                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 640                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 641                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 642                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 643                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 644                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 645                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 646                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 647                         <&cru SCLK_RTC32K>;
 648                 assigned-clock-parents =
 649                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 650                         <&cru PLL_GPLL>, <&xin24m>,
 651                         <&xin24m>, <&xin24m>;
 652                 assigned-clock-rates =
 653                         <0>, <61440000>,
 654                         <0>, <24000000>,
 655                         <24000000>, <24000000>,
 656                         <15000000>, <15000000>,
 657                         <100000000>, <100000000>,
 658                         <100000000>, <100000000>,
 659                         <50000000>, <100000000>,
 660                         <100000000>, <100000000>,
 661                         <50000000>, <50000000>,
 662                         <50000000>, <50000000>,
 663                         <24000000>, <600000000>,
 664                         <491520000>, <1200000000>,
 665                         <150000000>, <75000000>,
 666                         <75000000>, <150000000>,
 667                         <75000000>, <75000000>,
 668                         <32768>;
 669         };
 670
 671         usb2phy_grf: syscon@ff450000 {
 672                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 673                              "simple-mfd";
 674                 reg = <0x0 0xff450000 0x0 0x10000>;
 675                 #address-cells = <1>;
 676                 #size-cells = <1>;
 677
 678                 u2phy: usb2-phy@100 {
 679                         compatible = "rockchip,rk3328-usb2phy";
 680                         reg = <0x100 0x10>;
 681                         clocks = <&xin24m>;
 682                         clock-names = "phyclk";
 683                         clock-output-names = "usb480m_phy";
 684                         #clock-cells = <0>;
 685                         assigned-clocks = <&cru USB480M>;
 686                         assigned-clock-parents = <&u2phy>;
 687                         status = "disabled";
 688
 689                         u2phy_otg: otg-port {
 690                                 #phy-cells = <0>;
 691                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 692                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 693                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 694                                 interrupt-names = "otg-bvalid", "otg-id",
 695                                                   "linestate";
 696                                 status = "disabled";
 697                         };
 698
 699                         u2phy_host: host-port {
 700                                 #phy-cells = <0>;
 701                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 702                                 interrupt-names = "linestate";
 703                                 status = "disabled";
 704                         };
 705                 };
 706         };
 707
 708         sdmmc: dwmmc@ff500000 {
 709                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 710                 reg = <0x0 0xff500000 0x0 0x4000>;
 711                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 712                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 713                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 714                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 715                 fifo-depth = <0x100>;
 716                 status = "disabled";
 717         };
 718
 719         sdio: dwmmc@ff510000 {
 720                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 721                 reg = <0x0 0xff510000 0x0 0x4000>;
 722                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 723                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 724                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 725                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 726                 fifo-depth = <0x100>;
 727                 status = "disabled";
 728         };
 729
 730         emmc: dwmmc@ff520000 {
 731                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 732                 reg = <0x0 0xff520000 0x0 0x4000>;
 733                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 734                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 735                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 736                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 737                 fifo-depth = <0x100>;
 738                 status = "disabled";
 739         };
 740
 741         gmac2io: ethernet@ff540000 {
 742                 compatible = "rockchip,rk3328-gmac";
 743                 reg = <0x0 0xff540000 0x0 0x10000>;
 744                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 745                 interrupt-names = "macirq";
 746                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 747                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 748                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 749                          <&cru PCLK_MAC2IO>;
 750                 clock-names = "stmmaceth", "mac_clk_rx",
 751                               "mac_clk_tx", "clk_mac_ref",
 752                               "clk_mac_refout", "aclk_mac",
 753                               "pclk_mac";
 754                 resets = <&cru SRST_GMAC2IO_A>;
 755                 reset-names = "stmmaceth";
 756                 rockchip,grf = <&grf>;
 757                 status = "disabled";
 758         };
 759
 760         gmac2phy: ethernet@ff550000 {
 761                 compatible = "rockchip,rk3328-gmac";
 762                 reg = <0x0 0xff550000 0x0 0x10000>;
 763                 rockchip,grf = <&grf>;
 764                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 765                 interrupt-names = "macirq";
 766                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 767                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 768                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 769                          <&cru SCLK_MAC2PHY_OUT>;
 770                 clock-names = "stmmaceth", "mac_clk_rx",
 771                               "mac_clk_tx", "clk_mac_ref",
 772                               "aclk_mac", "pclk_mac",
 773                               "clk_macphy";
 774                 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
 775                 reset-names = "stmmaceth", "mac-phy";
 776                 phy-mode = "rmii";
 777                 phy-handle = <&phy>;
 778                 status = "disabled";
 779
 780                 mdio {
 781                         compatible = "snps,dwmac-mdio";
 782                         #address-cells = <1>;
 783                         #size-cells = <0>;
 784
 785                         phy: phy@0 {
 786                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 787                                 reg = <0>;
 788                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
 789                                 resets = <&cru SRST_MACPHY>;
 790                                 pinctrl-names = "default";
 791                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 792                                 phy-is-integrated;
 793                         };
 794                 };
 795         };
 796
 797         usb20_otg: usb@ff580000 {
 798                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 799                              "snps,dwc2";
 800                 reg = <0x0 0xff580000 0x0 0x40000>;
 801                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 802                 clocks = <&cru HCLK_OTG>;
 803                 clock-names = "otg";
 804                 dr_mode = "otg";
 805                 g-np-tx-fifo-size = <16>;
 806                 g-rx-fifo-size = <280>;
 807                 g-tx-fifo-size = <256 128 128 64 32 16>;
 808                 g-use-dma;
 809                 phys = <&u2phy_otg>;
 810                 phy-names = "usb2-phy";
 811                 status = "disabled";
 812         };
 813
 814         usb_host0_ehci: usb@ff5c0000 {
 815                 compatible = "generic-ehci";
 816                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 817                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 818                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 819                 clock-names = "usbhost", "utmi";
 820                 phys = <&u2phy_host>;
 821                 phy-names = "usb";
 822                 status = "disabled";
 823         };
 824
 825         usb_host0_ohci: usb@ff5d0000 {
 826                 compatible = "generic-ohci";
 827                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 828                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 829                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 830                 clock-names = "usbhost", "utmi";
 831                 phys = <&u2phy_host>;
 832                 phy-names = "usb";
 833                 status = "disabled";
 834         };
 835
 836         gic: interrupt-controller@ff811000 {
 837                 compatible = "arm,gic-400";
 838                 #interrupt-cells = <3>;
 839                 #address-cells = <0>;
 840                 interrupt-controller;
 841                 reg = <0x0 0xff811000 0 0x1000>,
 842                       <0x0 0xff812000 0 0x2000>,
 843                       <0x0 0xff814000 0 0x2000>,
 844                       <0x0 0xff816000 0 0x2000>;
 845                 interrupts = <GIC_PPI 9
 846                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 847         };
 848
 849         pinctrl: pinctrl {
 850                 compatible = "rockchip,rk3328-pinctrl";
 851                 rockchip,grf = <&grf>;
 852                 #address-cells = <2>;
 853                 #size-cells = <2>;
 854                 ranges;
 855
 856                 gpio0: gpio0@ff210000 {
 857                         compatible = "rockchip,gpio-bank";
 858                         reg = <0x0 0xff210000 0x0 0x100>;
 859                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 860                         clocks = <&cru PCLK_GPIO0>;
 861
 862                         gpio-controller;
 863                         #gpio-cells = <2>;
 864
 865                         interrupt-controller;
 866                         #interrupt-cells = <2>;
 867                 };
 868
 869                 gpio1: gpio1@ff220000 {
 870                         compatible = "rockchip,gpio-bank";
 871                         reg = <0x0 0xff220000 0x0 0x100>;
 872                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 873                         clocks = <&cru PCLK_GPIO1>;
 874
 875                         gpio-controller;
 876                         #gpio-cells = <2>;
 877
 878                         interrupt-controller;
 879                         #interrupt-cells = <2>;
 880                 };
 881
 882                 gpio2: gpio2@ff230000 {
 883                         compatible = "rockchip,gpio-bank";
 884                         reg = <0x0 0xff230000 0x0 0x100>;
 885                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 886                         clocks = <&cru PCLK_GPIO2>;
 887
 888                         gpio-controller;
 889                         #gpio-cells = <2>;
 890
 891                         interrupt-controller;
 892                         #interrupt-cells = <2>;
 893                 };
 894
 895                 gpio3: gpio3@ff240000 {
 896                         compatible = "rockchip,gpio-bank";
 897                         reg = <0x0 0xff240000 0x0 0x100>;
 898                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 899                         clocks = <&cru PCLK_GPIO3>;
 900
 901                         gpio-controller;
 902                         #gpio-cells = <2>;
 903
 904                         interrupt-controller;
 905                         #interrupt-cells = <2>;
 906                 };
 907
 908                 pcfg_pull_up: pcfg-pull-up {
 909                         bias-pull-up;
 910                 };
 911
 912                 pcfg_pull_down: pcfg-pull-down {
 913                         bias-pull-down;
 914                 };
 915
 916                 pcfg_pull_none: pcfg-pull-none {
 917                         bias-disable;
 918                 };
 919
 920                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 921                         bias-disable;
 922                         drive-strength = <2>;
 923                 };
 924
 925                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 926                         bias-pull-up;
 927                         drive-strength = <2>;
 928                 };
 929
 930                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 931                         bias-pull-up;
 932                         drive-strength = <4>;
 933                 };
 934
 935                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 936                         bias-disable;
 937                         drive-strength = <4>;
 938                 };
 939
 940                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 941                         bias-pull-down;
 942                         drive-strength = <4>;
 943                 };
 944
 945                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 946                         bias-disable;
 947                         drive-strength = <8>;
 948                 };
 949
 950                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 951                         bias-pull-up;
 952                         drive-strength = <8>;
 953                 };
 954
 955                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 956                         bias-disable;
 957                         drive-strength = <12>;
 958                 };
 959
 960                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 961                         bias-pull-up;
 962                         drive-strength = <12>;
 963                 };
 964
 965                 pcfg_output_high: pcfg-output-high {
 966                         output-high;
 967                 };
 968
 969                 pcfg_output_low: pcfg-output-low {
 970                         output-low;
 971                 };
 972
 973                 pcfg_input_high: pcfg-input-high {
 974                         bias-pull-up;
 975                         input-enable;
 976                 };
 977
 978                 pcfg_input: pcfg-input {
 979                         input-enable;
 980                 };
 981
 982                 i2c0 {
 983                         i2c0_xfer: i2c0-xfer {
 984                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
 985                                                 <2 RK_PD1 1 &pcfg_pull_none>;
 986                         };
 987                 };
 988
 989                 i2c1 {
 990                         i2c1_xfer: i2c1-xfer {
 991                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
 992                                                 <2 RK_PA5 2 &pcfg_pull_none>;
 993                         };
 994                 };
 995
 996                 i2c2 {
 997                         i2c2_xfer: i2c2-xfer {
 998                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
 999                                                 <2 RK_PB6 1 &pcfg_pull_none>;
1000                         };
1001                 };
1002
1003                 i2c3 {
1004                         i2c3_xfer: i2c3-xfer {
1005                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1006                                                 <0 RK_PA6 2 &pcfg_pull_none>;
1007                         };
1008                         i2c3_gpio: i2c3-gpio {
1009                                 rockchip,pins =
1010                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1011                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1012                         };
1013                 };
1014
1015                 hdmi_i2c {
1016                         hdmii2c_xfer: hdmii2c-xfer {
1017                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1018                                                 <0 RK_PA6 1 &pcfg_pull_none>;
1019                         };
1020                 };
1021
1022                 pdm-0 {
1023                         pdmm0_clk: pdmm0-clk {
1024                                 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1025                         };
1026
1027                         pdmm0_fsync: pdmm0-fsync {
1028                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1029                         };
1030
1031                         pdmm0_sdi0: pdmm0-sdi0 {
1032                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1033                         };
1034
1035                         pdmm0_sdi1: pdmm0-sdi1 {
1036                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1037                         };
1038
1039                         pdmm0_sdi2: pdmm0-sdi2 {
1040                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1041                         };
1042
1043                         pdmm0_sdi3: pdmm0-sdi3 {
1044                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1045                         };
1046
1047                         pdmm0_clk_sleep: pdmm0-clk-sleep {
1048                                 rockchip,pins =
1049                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1050                         };
1051
1052                         pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1053                                 rockchip,pins =
1054                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1055                         };
1056
1057                         pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1058                                 rockchip,pins =
1059                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1060                         };
1061
1062                         pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1063                                 rockchip,pins =
1064                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1065                         };
1066
1067                         pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1068                                 rockchip,pins =
1069                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1070                         };
1071
1072                         pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1073                                 rockchip,pins =
1074                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1075                         };
1076                 };
1077
1078                 tsadc {
1079                         otp_gpio: otp-gpio {
1080                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1081                         };
1082
1083                         otp_out: otp-out {
1084                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1085                         };
1086                 };
1087
1088                 uart0 {
1089                         uart0_xfer: uart0-xfer {
1090                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1091                                                 <1 RK_PB0 1 &pcfg_pull_none>;
1092                         };
1093
1094                         uart0_cts: uart0-cts {
1095                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1096                         };
1097
1098                         uart0_rts: uart0-rts {
1099                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1100                         };
1101
1102                         uart0_rts_gpio: uart0-rts-gpio {
1103                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1104                         };
1105                 };
1106
1107                 uart1 {
1108                         uart1_xfer: uart1-xfer {
1109                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1110                                                 <3 RK_PA6 4 &pcfg_pull_none>;
1111                         };
1112
1113                         uart1_cts: uart1-cts {
1114                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1115                         };
1116
1117                         uart1_rts: uart1-rts {
1118                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1119                         };
1120
1121                         uart1_rts_gpio: uart1-rts-gpio {
1122                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1123                         };
1124                 };
1125
1126                 uart2-0 {
1127                         uart2m0_xfer: uart2m0-xfer {
1128                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1129                                                 <1 RK_PA1 2 &pcfg_pull_none>;
1130                         };
1131                 };
1132
1133                 uart2-1 {
1134                         uart2m1_xfer: uart2m1-xfer {
1135                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1136                                                 <2 RK_PA1 1 &pcfg_pull_none>;
1137                         };
1138                 };
1139
1140                 spi0-0 {
1141                         spi0m0_clk: spi0m0-clk {
1142                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1143                         };
1144
1145                         spi0m0_cs0: spi0m0-cs0 {
1146                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1147                         };
1148
1149                         spi0m0_tx: spi0m0-tx {
1150                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1151                         };
1152
1153                         spi0m0_rx: spi0m0-rx {
1154                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1155                         };
1156
1157                         spi0m0_cs1: spi0m0-cs1 {
1158                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1159                         };
1160                 };
1161
1162                 spi0-1 {
1163                         spi0m1_clk: spi0m1-clk {
1164                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1165                         };
1166
1167                         spi0m1_cs0: spi0m1-cs0 {
1168                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1169                         };
1170
1171                         spi0m1_tx: spi0m1-tx {
1172                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1173                         };
1174
1175                         spi0m1_rx: spi0m1-rx {
1176                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1177                         };
1178
1179                         spi0m1_cs1: spi0m1-cs1 {
1180                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1181                         };
1182                 };
1183
1184                 spi0-2 {
1185                         spi0m2_clk: spi0m2-clk {
1186                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1187                         };
1188
1189                         spi0m2_cs0: spi0m2-cs0 {
1190                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1191                         };
1192
1193                         spi0m2_tx: spi0m2-tx {
1194                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1195                         };
1196
1197                         spi0m2_rx: spi0m2-rx {
1198                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1199                         };
1200                 };
1201
1202                 i2s1 {
1203                         i2s1_mclk: i2s1-mclk {
1204                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1205                         };
1206
1207                         i2s1_sclk: i2s1-sclk {
1208                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1209                         };
1210
1211                         i2s1_lrckrx: i2s1-lrckrx {
1212                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1213                         };
1214
1215                         i2s1_lrcktx: i2s1-lrcktx {
1216                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1217                         };
1218
1219                         i2s1_sdi: i2s1-sdi {
1220                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1221                         };
1222
1223                         i2s1_sdo: i2s1-sdo {
1224                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1225                         };
1226
1227                         i2s1_sdio1: i2s1-sdio1 {
1228                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1229                         };
1230
1231                         i2s1_sdio2: i2s1-sdio2 {
1232                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1233                         };
1234
1235                         i2s1_sdio3: i2s1-sdio3 {
1236                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1237                         };
1238
1239                         i2s1_sleep: i2s1-sleep {
1240                                 rockchip,pins =
1241                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1242                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1243                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1244                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1245                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1246                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1247                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1248                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1249                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1250                         };
1251                 };
1252
1253                 i2s2-0 {
1254                         i2s2m0_mclk: i2s2m0-mclk {
1255                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1256                         };
1257
1258                         i2s2m0_sclk: i2s2m0-sclk {
1259                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1260                         };
1261
1262                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1263                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1264                         };
1265
1266                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1267                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1268                         };
1269
1270                         i2s2m0_sdi: i2s2m0-sdi {
1271                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1272                         };
1273
1274                         i2s2m0_sdo: i2s2m0-sdo {
1275                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1276                         };
1277
1278                         i2s2m0_sleep: i2s2m0-sleep {
1279                                 rockchip,pins =
1280                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1281                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1282                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1283                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1284                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1285                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1286                         };
1287                 };
1288
1289                 i2s2-1 {
1290                         i2s2m1_mclk: i2s2m1-mclk {
1291                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1292                         };
1293
1294                         i2s2m1_sclk: i2s2m1-sclk {
1295                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1296                         };
1297
1298                         i2s2m1_lrckrx: i2sm1-lrckrx {
1299                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1300                         };
1301
1302                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1303                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1304                         };
1305
1306                         i2s2m1_sdi: i2s2m1-sdi {
1307                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1308                         };
1309
1310                         i2s2m1_sdo: i2s2m1-sdo {
1311                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1312                         };
1313
1314                         i2s2m1_sleep: i2s2m1-sleep {
1315                                 rockchip,pins =
1316                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1317                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1318                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1319                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1320                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1321                         };
1322                 };
1323
1324                 spdif-0 {
1325                         spdifm0_tx: spdifm0-tx {
1326                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1327                         };
1328                 };
1329
1330                 spdif-1 {
1331                         spdifm1_tx: spdifm1-tx {
1332                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1333                         };
1334                 };
1335
1336                 spdif-2 {
1337                         spdifm2_tx: spdifm2-tx {
1338                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1339                         };
1340                 };
1341
1342                 sdmmc0-0 {
1343                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1344                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1345                         };
1346
1347                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1348                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1349                         };
1350                 };
1351
1352                 sdmmc0-1 {
1353                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1354                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1355                         };
1356
1357                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1358                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1359                         };
1360                 };
1361
1362                 sdmmc0 {
1363                         sdmmc0_clk: sdmmc0-clk {
1364                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
1365                         };
1366
1367                         sdmmc0_cmd: sdmmc0-cmd {
1368                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
1369                         };
1370
1371                         sdmmc0_dectn: sdmmc0-dectn {
1372                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1373                         };
1374
1375                         sdmmc0_wrprt: sdmmc0-wrprt {
1376                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1377                         };
1378
1379                         sdmmc0_bus1: sdmmc0-bus1 {
1380                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
1381                         };
1382
1383                         sdmmc0_bus4: sdmmc0-bus4 {
1384                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
1385                                                 <1 RK_PA1 1 &pcfg_pull_up_4ma>,
1386                                                 <1 RK_PA2 1 &pcfg_pull_up_4ma>,
1387                                                 <1 RK_PA3 1 &pcfg_pull_up_4ma>;
1388                         };
1389
1390                         sdmmc0_gpio: sdmmc0-gpio {
1391                                 rockchip,pins =
1392                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1393                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1394                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1395                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1396                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1397                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1398                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1399                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1400                         };
1401                 };
1402
1403                 sdmmc0ext {
1404                         sdmmc0ext_clk: sdmmc0ext-clk {
1405                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1406                         };
1407
1408                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1409                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1410                         };
1411
1412                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1413                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1414                         };
1415
1416                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1417                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1418                         };
1419
1420                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1421                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1422                         };
1423
1424                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1425                                 rockchip,pins =
1426                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1427                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1428                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1429                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1430                         };
1431
1432                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1433                                 rockchip,pins =
1434                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1435                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1436                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1437                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1438                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1439                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1440                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1441                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1442                         };
1443                 };
1444
1445                 sdmmc1 {
1446                         sdmmc1_clk: sdmmc1-clk {
1447                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1448                         };
1449
1450                         sdmmc1_cmd: sdmmc1-cmd {
1451                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1452                         };
1453
1454                         sdmmc1_pwren: sdmmc1-pwren {
1455                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1456                         };
1457
1458                         sdmmc1_wrprt: sdmmc1-wrprt {
1459                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1460                         };
1461
1462                         sdmmc1_dectn: sdmmc1-dectn {
1463                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1464                         };
1465
1466                         sdmmc1_bus1: sdmmc1-bus1 {
1467                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1468                         };
1469
1470                         sdmmc1_bus4: sdmmc1-bus4 {
1471                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1472                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1473                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1474                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1475                         };
1476
1477                         sdmmc1_gpio: sdmmc1-gpio {
1478                                 rockchip,pins =
1479                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1480                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1481                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1482                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1483                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1484                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1485                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1486                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1487                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1488                         };
1489                 };
1490
1491                 emmc {
1492                         emmc_clk: emmc-clk {
1493                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1494                         };
1495
1496                         emmc_cmd: emmc-cmd {
1497                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1498                         };
1499
1500                         emmc_pwren: emmc-pwren {
1501                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1502                         };
1503
1504                         emmc_rstnout: emmc-rstnout {
1505                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1506                         };
1507
1508                         emmc_bus1: emmc-bus1 {
1509                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1510                         };
1511
1512                         emmc_bus4: emmc-bus4 {
1513                                 rockchip,pins =
1514                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1515                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1516                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1517                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1518                         };
1519
1520                         emmc_bus8: emmc-bus8 {
1521                                 rockchip,pins =
1522                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1523                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1524                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1525                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1526                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1527                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1528                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1529                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1530                         };
1531                 };
1532
1533                 pwm0 {
1534                         pwm0_pin: pwm0-pin {
1535                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1536                         };
1537                 };
1538
1539                 pwm1 {
1540                         pwm1_pin: pwm1-pin {
1541                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1542                         };
1543                 };
1544
1545                 pwm2 {
1546                         pwm2_pin: pwm2-pin {
1547                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1548                         };
1549                 };
1550
1551                 pwmir {
1552                         pwmir_pin: pwmir-pin {
1553                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1554                         };
1555                 };
1556
1557                 gmac-1 {
1558                         rgmiim1_pins: rgmiim1-pins {
1559                                 rockchip,pins =
1560                                         /* mac_txclk */
1561                                         <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1562                                         /* mac_rxclk */
1563                                         <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1564                                         /* mac_mdio */
1565                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1566                                         /* mac_txen */
1567                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1568                                         /* mac_clk */
1569                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1570                                         /* mac_rxdv */
1571                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1572                                         /* mac_mdc */
1573                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1574                                         /* mac_rxd1 */
1575                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1576                                         /* mac_rxd0 */
1577                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1578                                         /* mac_txd1 */
1579                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1580                                         /* mac_txd0 */
1581                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1582                                         /* mac_rxd3 */
1583                                         <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1584                                         /* mac_rxd2 */
1585                                         <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1586                                         /* mac_txd3 */
1587                                         <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1588                                         /* mac_txd2 */
1589                                         <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1590
1591                                         /* mac_txclk */
1592                                         <0 RK_PB0 1 &pcfg_pull_none>,
1593                                         /* mac_txen */
1594                                         <0 RK_PB4 1 &pcfg_pull_none>,
1595                                         /* mac_clk */
1596                                         <0 RK_PD0 1 &pcfg_pull_none>,
1597                                         /* mac_txd1 */
1598                                         <0 RK_PC0 1 &pcfg_pull_none>,
1599                                         /* mac_txd0 */
1600                                         <0 RK_PC1 1 &pcfg_pull_none>,
1601                                         /* mac_txd3 */
1602                                         <0 RK_PC7 1 &pcfg_pull_none>,
1603                                         /* mac_txd2 */
1604                                         <0 RK_PC6 1 &pcfg_pull_none>;
1605                         };
1606
1607                         rmiim1_pins: rmiim1-pins {
1608                                 rockchip,pins =
1609                                         /* mac_mdio */
1610                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1611                                         /* mac_txen */
1612                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1613                                         /* mac_clk */
1614                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1615                                         /* mac_rxer */
1616                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1617                                         /* mac_rxdv */
1618                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1619                                         /* mac_mdc */
1620                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1621                                         /* mac_rxd1 */
1622                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1623                                         /* mac_rxd0 */
1624                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1625                                         /* mac_txd1 */
1626                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1627                                         /* mac_txd0 */
1628                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1629
1630                                         /* mac_mdio */
1631                                         <0 RK_PB3 1 &pcfg_pull_none>,
1632                                         /* mac_txen */
1633                                         <0 RK_PB4 1 &pcfg_pull_none>,
1634                                         /* mac_clk */
1635                                         <0 RK_PD0 1 &pcfg_pull_none>,
1636                                         /* mac_mdc */
1637                                         <0 RK_PC3 1 &pcfg_pull_none>,
1638                                         /* mac_txd1 */
1639                                         <0 RK_PC0 1 &pcfg_pull_none>,
1640                                         /* mac_txd0 */
1641                                         <0 RK_PC1 1 &pcfg_pull_none>;
1642                         };
1643                 };
1644
1645                 gmac2phy {
1646                         fephyled_speed100: fephyled-speed100 {
1647                                 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1648                         };
1649
1650                         fephyled_speed10: fephyled-speed10 {
1651                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1652                         };
1653
1654                         fephyled_duplex: fephyled-duplex {
1655                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1656                         };
1657
1658                         fephyled_rxm0: fephyled-rxm0 {
1659                                 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1660                         };
1661
1662                         fephyled_txm0: fephyled-txm0 {
1663                                 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1664                         };
1665
1666                         fephyled_linkm0: fephyled-linkm0 {
1667                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1668                         };
1669
1670                         fephyled_rxm1: fephyled-rxm1 {
1671                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1672                         };
1673
1674                         fephyled_txm1: fephyled-txm1 {
1675                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1676                         };
1677
1678                         fephyled_linkm1: fephyled-linkm1 {
1679                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1680                         };
1681                 };
1682
1683                 tsadc_pin {
1684                         tsadc_int: tsadc-int {
1685                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1686                         };
1687                         tsadc_gpio: tsadc-gpio {
1688                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1689                         };
1690                 };
1691
1692                 hdmi_pin {
1693                         hdmi_cec: hdmi-cec {
1694                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1695                         };
1696
1697                         hdmi_hpd: hdmi-hpd {
1698                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1699                         };
1700                 };
1701
1702                 cif-0 {
1703                         dvp_d2d9_m0:dvp-d2d9-m0 {
1704                                 rockchip,pins =
1705                                         /* cif_d0 */
1706                                         <3 RK_PA4 2 &pcfg_pull_none>,
1707                                         /* cif_d1 */
1708                                         <3 RK_PA5 2 &pcfg_pull_none>,
1709                                         /* cif_d2 */
1710                                         <3 RK_PA6 2 &pcfg_pull_none>,
1711                                         /* cif_d3 */
1712                                         <3 RK_PA7 2 &pcfg_pull_none>,
1713                                         /* cif_d4 */
1714                                         <3 RK_PB0 2 &pcfg_pull_none>,
1715                                         /* cif_d5m0 */
1716                                         <3 RK_PB1 2 &pcfg_pull_none>,
1717                                         /* cif_d6m0 */
1718                                         <3 RK_PB2 2 &pcfg_pull_none>,
1719                                         /* cif_d7m0 */
1720                                         <3 RK_PB3 2 &pcfg_pull_none>,
1721                                         /* cif_href */
1722                                         <3 RK_PA1 2 &pcfg_pull_none>,
1723                                         /* cif_vsync */
1724                                         <3 RK_PA0 2 &pcfg_pull_none>,
1725                                         /* cif_clkoutm0 */
1726                                         <3 RK_PA3 2 &pcfg_pull_none>,
1727                                         /* cif_clkin */
1728                                         <3 RK_PA2 2 &pcfg_pull_none>;
1729                         };
1730                 };
1731
1732                 cif-1 {
1733                         dvp_d2d9_m1:dvp-d2d9-m1 {
1734                                 rockchip,pins =
1735                                         /* cif_d0 */
1736                                         <3 RK_PA4 2 &pcfg_pull_none>,
1737                                         /* cif_d1 */
1738                                         <3 RK_PA5 2 &pcfg_pull_none>,
1739                                         /* cif_d2 */
1740                                         <3 RK_PA6 2 &pcfg_pull_none>,
1741                                         /* cif_d3 */
1742                                         <3 RK_PA7 2 &pcfg_pull_none>,
1743                                         /* cif_d4 */
1744                                         <3 RK_PB0 2 &pcfg_pull_none>,
1745                                         /* cif_d5m1 */
1746                                         <2 RK_PC0 4 &pcfg_pull_none>,
1747                                         /* cif_d6m1 */
1748                                         <2 RK_PC1 4 &pcfg_pull_none>,
1749                                         /* cif_d7m1 */
1750                                         <2 RK_PC2 4 &pcfg_pull_none>,
1751                                         /* cif_href */
1752                                         <3 RK_PA1 2 &pcfg_pull_none>,
1753                                         /* cif_vsync */
1754                                         <3 RK_PA0 2 &pcfg_pull_none>,
1755                                         /* cif_clkoutm1 */
1756                                         <2 RK_PB7 4 &pcfg_pull_none>,
1757                                         /* cif_clkin */
1758                                         <3 RK_PA2 2 &pcfg_pull_none>;
1759                         };
1760                 };
1761         };
1762 };