drivers/gpu/drm/i915/i915_sysfs.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *
  26  */
  27
  28 #include <linux/device.h>
  29 #include <linux/module.h>
  30 #include <linux/stat.h>
  31 #include <linux/sysfs.h>
  32
  33 #include "gt/intel_rc6.h"
  34 #include "gt/intel_rps.h"
  35
  36 #include "i915_drv.h"
  37 #include "i915_sysfs.h"
  38 #include "intel_pm.h"
  39 #include "intel_sideband.h"
  40
  41 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
  42 {
  43         struct drm_minor *minor = dev_get_drvdata(kdev);
  44         return to_i915(minor->dev);
  45 }
  46
  47 #ifdef CONFIG_PM
  48 static u32 calc_residency(struct drm_i915_private *dev_priv,
  49                           i915_reg_t reg)
  50 {
  51         intel_wakeref_t wakeref;
  52         u64 res = 0;
  53
  54         with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
  55                 res = intel_rc6_residency_us(&dev_priv->gt.rc6, reg);
  56
  57         return DIV_ROUND_CLOSEST_ULL(res, 1000);
  58 }
  59
  60 static ssize_t
  61 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
  62 {
  63         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  64         unsigned int mask;
  65
  66         mask = 0;
  67         if (HAS_RC6(dev_priv))
  68                 mask |= BIT(0);
  69         if (HAS_RC6p(dev_priv))
  70                 mask |= BIT(1);
  71         if (HAS_RC6pp(dev_priv))
  72                 mask |= BIT(2);
  73
  74         return snprintf(buf, PAGE_SIZE, "%x\n", mask);
  75 }
  76
  77 static ssize_t
  78 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  79 {
  80         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  81         u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
  82         return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
  83 }
  84
  85 static ssize_t
  86 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  87 {
  88         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  89         u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
  90         return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
  91 }
  92
  93 static ssize_t
  94 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  95 {
  96         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  97         u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
  98         return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
  99 }
 100
 101 static ssize_t
 102 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
 103 {
 104         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 105         u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
 106         return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
 107 }
 108
 109 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
 110 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
 111 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
 112 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
 113 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
 114
 115 static struct attribute *rc6_attrs[] = {
 116         &dev_attr_rc6_enable.attr,
 117         &dev_attr_rc6_residency_ms.attr,
 118         NULL
 119 };
 120
 121 static const struct attribute_group rc6_attr_group = {
 122         .name = power_group_name,
 123         .attrs =  rc6_attrs
 124 };
 125
 126 static struct attribute *rc6p_attrs[] = {
 127         &dev_attr_rc6p_residency_ms.attr,
 128         &dev_attr_rc6pp_residency_ms.attr,
 129         NULL
 130 };
 131
 132 static const struct attribute_group rc6p_attr_group = {
 133         .name = power_group_name,
 134         .attrs =  rc6p_attrs
 135 };
 136
 137 static struct attribute *media_rc6_attrs[] = {
 138         &dev_attr_media_rc6_residency_ms.attr,
 139         NULL
 140 };
 141
 142 static const struct attribute_group media_rc6_attr_group = {
 143         .name = power_group_name,
 144         .attrs =  media_rc6_attrs
 145 };
 146 #endif
 147
 148 static int l3_access_valid(struct drm_i915_private *i915, loff_t offset)
 149 {
 150         if (!HAS_L3_DPF(i915))
 151                 return -EPERM;
 152
 153         if (!IS_ALIGNED(offset, sizeof(u32)))
 154                 return -EINVAL;
 155
 156         if (offset >= GEN7_L3LOG_SIZE)
 157                 return -ENXIO;
 158
 159         return 0;
 160 }
 161
 162 static ssize_t
 163 i915_l3_read(struct file *filp, struct kobject *kobj,
 164              struct bin_attribute *attr, char *buf,
 165              loff_t offset, size_t count)
 166 {
 167         struct device *kdev = kobj_to_dev(kobj);
 168         struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
 169         int slice = (int)(uintptr_t)attr->private;
 170         int ret;
 171
 172         ret = l3_access_valid(i915, offset);
 173         if (ret)
 174                 return ret;
 175
 176         count = round_down(count, sizeof(u32));
 177         count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
 178         memset(buf, 0, count);
 179
 180         spin_lock(&i915->gem.contexts.lock);
 181         if (i915->l3_parity.remap_info[slice])
 182                 memcpy(buf,
 183                        i915->l3_parity.remap_info[slice] + offset / sizeof(u32),
 184                        count);
 185         spin_unlock(&i915->gem.contexts.lock);
 186
 187         return count;
 188 }
 189
 190 static ssize_t
 191 i915_l3_write(struct file *filp, struct kobject *kobj,
 192               struct bin_attribute *attr, char *buf,
 193               loff_t offset, size_t count)
 194 {
 195         struct device *kdev = kobj_to_dev(kobj);
 196         struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
 197         int slice = (int)(uintptr_t)attr->private;
 198         u32 *remap_info, *freeme = NULL;
 199         struct i915_gem_context *ctx;
 200         int ret;
 201
 202         ret = l3_access_valid(i915, offset);
 203         if (ret)
 204                 return ret;
 205
 206         if (count < sizeof(u32))
 207                 return -EINVAL;
 208
 209         remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
 210         if (!remap_info)
 211                 return -ENOMEM;
 212
 213         spin_lock(&i915->gem.contexts.lock);
 214
 215         if (i915->l3_parity.remap_info[slice]) {
 216                 freeme = remap_info;
 217                 remap_info = i915->l3_parity.remap_info[slice];
 218         } else {
 219                 i915->l3_parity.remap_info[slice] = remap_info;
 220         }
 221
 222         count = round_down(count, sizeof(u32));
 223         memcpy(remap_info + offset / sizeof(u32), buf, count);
 224
 225         /* NB: We defer the remapping until we switch to the context */
 226         list_for_each_entry(ctx, &i915->gem.contexts.list, link)
 227                 ctx->remap_slice |= BIT(slice);
 228
 229         spin_unlock(&i915->gem.contexts.lock);
 230         kfree(freeme);
 231
 232         /*
 233          * TODO: Ideally we really want a GPU reset here to make sure errors
 234          * aren't propagated. Since I cannot find a stable way to reset the GPU
 235          * at this point it is left as a TODO.
 236         */
 237
 238         return count;
 239 }
 240
 241 static const struct bin_attribute dpf_attrs = {
 242         .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
 243         .size = GEN7_L3LOG_SIZE,
 244         .read = i915_l3_read,
 245         .write = i915_l3_write,
 246         .mmap = NULL,
 247         .private = (void *)0
 248 };
 249
 250 static const struct bin_attribute dpf_attrs_1 = {
 251         .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
 252         .size = GEN7_L3LOG_SIZE,
 253         .read = i915_l3_read,
 254         .write = i915_l3_write,
 255         .mmap = NULL,
 256         .private = (void *)1
 257 };
 258
 259 static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 260                                     struct device_attribute *attr, char *buf)
 261 {
 262         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 263         struct intel_rps *rps = &dev_priv->gt.rps;
 264         intel_wakeref_t wakeref;
 265         u32 freq;
 266
 267         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 268
 269         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 270                 vlv_punit_get(dev_priv);
 271                 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 272                 vlv_punit_put(dev_priv);
 273
 274                 freq = (freq >> 8) & 0xff;
 275         } else {
 276                 freq = intel_get_cagf(rps, I915_READ(GEN6_RPSTAT1));
 277         }
 278
 279         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 280
 281         return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(rps, freq));
 282 }
 283
 284 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 285                                     struct device_attribute *attr, char *buf)
 286 {
 287         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 288         struct intel_rps *rps = &dev_priv->gt.rps;
 289
 290         return snprintf(buf, PAGE_SIZE, "%d\n",
 291                         intel_gpu_freq(rps, rps->cur_freq));
 292 }
 293
 294 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 295 {
 296         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 297         struct intel_rps *rps = &dev_priv->gt.rps;
 298
 299         return snprintf(buf, PAGE_SIZE, "%d\n",
 300                         intel_gpu_freq(rps, rps->boost_freq));
 301 }
 302
 303 static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
 304                                        struct device_attribute *attr,
 305                                        const char *buf, size_t count)
 306 {
 307         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 308         struct intel_rps *rps = &dev_priv->gt.rps;
 309         bool boost = false;
 310         ssize_t ret;
 311         u32 val;
 312
 313         ret = kstrtou32(buf, 0, &val);
 314         if (ret)
 315                 return ret;
 316
 317         /* Validate against (static) hardware limits */
 318         val = intel_freq_opcode(rps, val);
 319         if (val < rps->min_freq || val > rps->max_freq)
 320                 return -EINVAL;
 321
 322         mutex_lock(&rps->lock);
 323         if (val != rps->boost_freq) {
 324                 rps->boost_freq = val;
 325                 boost = atomic_read(&rps->num_waiters);
 326         }
 327         mutex_unlock(&rps->lock);
 328         if (boost)
 329                 schedule_work(&rps->work);
 330
 331         return count;
 332 }
 333
 334 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
 335                                      struct device_attribute *attr, char *buf)
 336 {
 337         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 338         struct intel_rps *rps = &dev_priv->gt.rps;
 339
 340         return snprintf(buf, PAGE_SIZE, "%d\n",
 341                         intel_gpu_freq(rps, rps->efficient_freq));
 342 }
 343
 344 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 345 {
 346         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 347         struct intel_rps *rps = &dev_priv->gt.rps;
 348
 349         return snprintf(buf, PAGE_SIZE, "%d\n",
 350                         intel_gpu_freq(rps, rps->max_freq_softlimit));
 351 }
 352
 353 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 354                                      struct device_attribute *attr,
 355                                      const char *buf, size_t count)
 356 {
 357         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 358         struct intel_rps *rps = &dev_priv->gt.rps;
 359         ssize_t ret;
 360         u32 val;
 361
 362         ret = kstrtou32(buf, 0, &val);
 363         if (ret)
 364                 return ret;
 365
 366         mutex_lock(&rps->lock);
 367
 368         val = intel_freq_opcode(rps, val);
 369         if (val < rps->min_freq ||
 370             val > rps->max_freq ||
 371             val < rps->min_freq_softlimit) {
 372                 ret = -EINVAL;
 373                 goto unlock;
 374         }
 375
 376         if (val > rps->rp0_freq)
 377                 DRM_DEBUG("User requested overclocking to %d\n",
 378                           intel_gpu_freq(rps, val));
 379
 380         rps->max_freq_softlimit = val;
 381
 382         val = clamp_t(int, rps->cur_freq,
 383                       rps->min_freq_softlimit,
 384                       rps->max_freq_softlimit);
 385
 386         /*
 387          * We still need *_set_rps to process the new max_delay and
 388          * update the interrupt limits and PMINTRMSK even though
 389          * frequency request may be unchanged.
 390          */
 391         intel_rps_set(rps, val);
 392
 393 unlock:
 394         mutex_unlock(&rps->lock);
 395
 396         return ret ?: count;
 397 }
 398
 399 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 400 {
 401         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 402         struct intel_rps *rps = &dev_priv->gt.rps;
 403
 404         return snprintf(buf, PAGE_SIZE, "%d\n",
 405                         intel_gpu_freq(rps, rps->min_freq_softlimit));
 406 }
 407
 408 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 409                                      struct device_attribute *attr,
 410                                      const char *buf, size_t count)
 411 {
 412         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 413         struct intel_rps *rps = &dev_priv->gt.rps;
 414         ssize_t ret;
 415         u32 val;
 416
 417         ret = kstrtou32(buf, 0, &val);
 418         if (ret)
 419                 return ret;
 420
 421         mutex_lock(&rps->lock);
 422
 423         val = intel_freq_opcode(rps, val);
 424         if (val < rps->min_freq ||
 425             val > rps->max_freq ||
 426             val > rps->max_freq_softlimit) {
 427                 ret = -EINVAL;
 428                 goto unlock;
 429         }
 430
 431         rps->min_freq_softlimit = val;
 432
 433         val = clamp_t(int, rps->cur_freq,
 434                       rps->min_freq_softlimit,
 435                       rps->max_freq_softlimit);
 436
 437         /*
 438          * We still need *_set_rps to process the new min_delay and
 439          * update the interrupt limits and PMINTRMSK even though
 440          * frequency request may be unchanged.
 441          */
 442         intel_rps_set(rps, val);
 443
 444 unlock:
 445         mutex_unlock(&rps->lock);
 446
 447         return ret ?: count;
 448 }
 449
 450 static DEVICE_ATTR_RO(gt_act_freq_mhz);
 451 static DEVICE_ATTR_RO(gt_cur_freq_mhz);
 452 static DEVICE_ATTR_RW(gt_boost_freq_mhz);
 453 static DEVICE_ATTR_RW(gt_max_freq_mhz);
 454 static DEVICE_ATTR_RW(gt_min_freq_mhz);
 455
 456 static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
 457
 458 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
 459 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 460 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 461 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 462
 463 /* For now we have a static number of RP states */
 464 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 465 {
 466         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 467         struct intel_rps *rps = &dev_priv->gt.rps;
 468         u32 val;
 469
 470         if (attr == &dev_attr_gt_RP0_freq_mhz)
 471                 val = intel_gpu_freq(rps, rps->rp0_freq);
 472         else if (attr == &dev_attr_gt_RP1_freq_mhz)
 473                 val = intel_gpu_freq(rps, rps->rp1_freq);
 474         else if (attr == &dev_attr_gt_RPn_freq_mhz)
 475                 val = intel_gpu_freq(rps, rps->min_freq);
 476         else
 477                 BUG();
 478
 479         return snprintf(buf, PAGE_SIZE, "%d\n", val);
 480 }
 481
 482 static const struct attribute * const gen6_attrs[] = {
 483         &dev_attr_gt_act_freq_mhz.attr,
 484         &dev_attr_gt_cur_freq_mhz.attr,
 485         &dev_attr_gt_boost_freq_mhz.attr,
 486         &dev_attr_gt_max_freq_mhz.attr,
 487         &dev_attr_gt_min_freq_mhz.attr,
 488         &dev_attr_gt_RP0_freq_mhz.attr,
 489         &dev_attr_gt_RP1_freq_mhz.attr,
 490         &dev_attr_gt_RPn_freq_mhz.attr,
 491         NULL,
 492 };
 493
 494 static const struct attribute * const vlv_attrs[] = {
 495         &dev_attr_gt_act_freq_mhz.attr,
 496         &dev_attr_gt_cur_freq_mhz.attr,
 497         &dev_attr_gt_boost_freq_mhz.attr,
 498         &dev_attr_gt_max_freq_mhz.attr,
 499         &dev_attr_gt_min_freq_mhz.attr,
 500         &dev_attr_gt_RP0_freq_mhz.attr,
 501         &dev_attr_gt_RP1_freq_mhz.attr,
 502         &dev_attr_gt_RPn_freq_mhz.attr,
 503         &dev_attr_vlv_rpe_freq_mhz.attr,
 504         NULL,
 505 };
 506
 507 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 508
 509 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
 510                                 struct bin_attribute *attr, char *buf,
 511                                 loff_t off, size_t count)
 512 {
 513
 514         struct device *kdev = kobj_to_dev(kobj);
 515         struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
 516         struct i915_gpu_state *gpu;
 517         ssize_t ret;
 518
 519         gpu = i915_first_error_state(i915);
 520         if (IS_ERR(gpu)) {
 521                 ret = PTR_ERR(gpu);
 522         } else if (gpu) {
 523                 ret = i915_gpu_state_copy_to_buffer(gpu, buf, off, count);
 524                 i915_gpu_state_put(gpu);
 525         } else {
 526                 const char *str = "No error state collected\n";
 527                 size_t len = strlen(str);
 528
 529                 ret = min_t(size_t, count, len - off);
 530                 memcpy(buf, str + off, ret);
 531         }
 532
 533         return ret;
 534 }
 535
 536 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
 537                                  struct bin_attribute *attr, char *buf,
 538                                  loff_t off, size_t count)
 539 {
 540         struct device *kdev = kobj_to_dev(kobj);
 541         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 542
 543         DRM_DEBUG_DRIVER("Resetting error state\n");
 544         i915_reset_error_state(dev_priv);
 545
 546         return count;
 547 }
 548
 549 static const struct bin_attribute error_state_attr = {
 550         .attr.name = "error",
 551         .attr.mode = S_IRUSR | S_IWUSR,
 552         .size = 0,
 553         .read = error_state_read,
 554         .write = error_state_write,
 555 };
 556
 557 static void i915_setup_error_capture(struct device *kdev)
 558 {
 559         if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
 560                 DRM_ERROR("error_state sysfs setup failed\n");
 561 }
 562
 563 static void i915_teardown_error_capture(struct device *kdev)
 564 {
 565         sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
 566 }
 567 #else
 568 static void i915_setup_error_capture(struct device *kdev) {}
 569 static void i915_teardown_error_capture(struct device *kdev) {}
 570 #endif
 571
 572 void i915_setup_sysfs(struct drm_i915_private *dev_priv)
 573 {
 574         struct device *kdev = dev_priv->drm.primary->kdev;
 575         int ret;
 576
 577 #ifdef CONFIG_PM
 578         if (HAS_RC6(dev_priv)) {
 579                 ret = sysfs_merge_group(&kdev->kobj,
 580                                         &rc6_attr_group);
 581                 if (ret)
 582                         DRM_ERROR("RC6 residency sysfs setup failed\n");
 583         }
 584         if (HAS_RC6p(dev_priv)) {
 585                 ret = sysfs_merge_group(&kdev->kobj,
 586                                         &rc6p_attr_group);
 587                 if (ret)
 588                         DRM_ERROR("RC6p residency sysfs setup failed\n");
 589         }
 590         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 591                 ret = sysfs_merge_group(&kdev->kobj,
 592                                         &media_rc6_attr_group);
 593                 if (ret)
 594                         DRM_ERROR("Media RC6 residency sysfs setup failed\n");
 595         }
 596 #endif
 597         if (HAS_L3_DPF(dev_priv)) {
 598                 ret = device_create_bin_file(kdev, &dpf_attrs);
 599                 if (ret)
 600                         DRM_ERROR("l3 parity sysfs setup failed\n");
 601
 602                 if (NUM_L3_SLICES(dev_priv) > 1) {
 603                         ret = device_create_bin_file(kdev,
 604                                                      &dpf_attrs_1);
 605                         if (ret)
 606                                 DRM_ERROR("l3 parity slice 1 setup failed\n");
 607                 }
 608         }
 609
 610         ret = 0;
 611         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 612                 ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
 613         else if (INTEL_GEN(dev_priv) >= 6)
 614                 ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
 615         if (ret)
 616                 DRM_ERROR("RPS sysfs setup failed\n");
 617
 618         i915_setup_error_capture(kdev);
 619 }
 620
 621 void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
 622 {
 623         struct device *kdev = dev_priv->drm.primary->kdev;
 624
 625         i915_teardown_error_capture(kdev);
 626
 627         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 628                 sysfs_remove_files(&kdev->kobj, vlv_attrs);
 629         else
 630                 sysfs_remove_files(&kdev->kobj, gen6_attrs);
 631         device_remove_bin_file(kdev,  &dpf_attrs_1);
 632         device_remove_bin_file(kdev,  &dpf_attrs);
 633 #ifdef CONFIG_PM
 634         sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
 635         sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
 636 #endif
 637 }