drm/i915/gvt: Refine non privilege register address calucation

The BitField of non privilege register address is only from bit 2 to 25.

v2: use REG_GENMASK instead. (Zhenyu)

Signed-off-by: Gao, Fred <fred.gao@intel.com>
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index bd12af3491235f9fc9190a8968c96cb7caf025fb..4f8a25e760f0539d05d87900fcd28049430d99b2 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -508,7 +508,7 @@ static inline bool in_whitelist(unsigned int reg)
 static int force_nonpriv_write(struct intel_vgpu *vgpu,
        unsigned int offset, void *p_data, unsigned int bytes)
 {
-       u32 reg_nonpriv = *(u32 *)p_data;
+       u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
        int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
        u32 ring_base;
        struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
@@ -528,7 +528,7 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu,
                        bytes);
        } else
                gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
-                       vgpu->id, reg_nonpriv, offset);
+                       vgpu->id, *(u32 *)p_data, offset);
 
        return 0;
 }