- DMA API, pci_ API & extensions for non-consistent memory machines.
DMA-ISA-LPC.txt
- How to do DMA with ISA (and LPC) devices.
-DMA-mapping.txt
- - info for PCI drivers using DMA portably across all platforms.
DocBook/
- directory with DocBook templates etc. for kernel documentation.
HOWTO
- how to (attempt to) manage kernel hackers.
MSI-HOWTO.txt
- the Message Signaled Interrupts (MSI) Driver Guide HOWTO and FAQ.
-PCIEBUS-HOWTO.txt
- - a guide describing the PCI Express Port Bus driver.
RCU/
- directory with info on RCU (read-copy update).
README.DAC960
- how to use the parallel-port driver.
parport-lowlevel.txt
- description and usage of the low level parallel port functions.
-pci-error-recovery.txt
- - info on PCI error recovery.
-pci.txt
- - info on the PCI subsystem for device driver authors.
-pcieaer-howto.txt
- - the PCI Express Advanced Error Reporting Driver Guide HOWTO.
pcmcia/
- info on the Linux PCMCIA driver.
pi-futex.txt
--- /dev/null
+What: /sys/bus/pci/devices/.../vpd
+Date: February 2008
+Contact: Ben Hutchings <bhutchings@solarflare.com>
+Description:
+ A file named vpd in a device directory will be a
+ binary file containing the Vital Product Data for the
+ device. It should follow the VPD format defined in
+ PCI Specification 2.1 or 2.2, but users should consider
+ that some devices may have malformatted data. If the
+ underlying VPD has a writable section then the
+ corresponding section of this file will be writable.
--- /dev/null
+What: /sys/firmware/ibft/initiator
+Date: November 2007
+Contact: Konrad Rzeszutek <ketuzsezr@darnok.org>
+Description: The /sys/firmware/ibft/initiator directory will contain
+ files that expose the iSCSI Boot Firmware Table initiator data.
+ Usually this contains the Initiator name.
+
+What: /sys/firmware/ibft/targetX
+Date: November 2007
+Contact: Konrad Rzeszutek <ketuzsezr@darnok.org>
+Description: The /sys/firmware/ibft/targetX directory will contain
+ files that expose the iSCSI Boot Firmware Table target data.
+ Usually this contains the target's IP address, boot LUN,
+ target name, and what NIC it is associated with. It can also
+ contain the CHAP name (and password), the reverse CHAP
+ name (and password)
+
+What: /sys/firmware/ibft/ethernetX
+Date: November 2007
+Contact: Konrad Rzeszutek <ketuzsezr@darnok.org>
+Description: The /sys/firmware/ibft/ethernetX directory will contain
+ files that expose the iSCSI Boot Firmware Table NIC data.
+ This can this can the IP address, MAC, and gateway of the NIC.
!Ikernel/acct.c
</chapter>
- <chapter id="pmfuncs">
- <title>Power Management</title>
-!Ekernel/power/pm.c
- </chapter>
-
<chapter id="devdrivers">
<title>Device drivers infrastructure</title>
<sect1><title>Device Drivers Base</title>
</para>
<para>
The third type is a semaphore
- (<filename class="headerfile">include/asm/semaphore.h</filename>): it
+ (<filename class="headerfile">include/linux/semaphore.h</filename>): it
can have more than one holder at any time (the number decided at
initialization time), although it is most commonly used as a
single-holder lock (a mutex). If you can't get a semaphore, your
<para>
If you have a data structure which is only ever accessed from
user context, then you can use a simple semaphore
- (<filename>linux/asm/semaphore.h</filename>) to protect it. This
+ (<filename>linux/linux/semaphore.h</filename>) to protect it. This
is the most trivial case: you initialize the semaphore to the number
of resources available (usually 1), and call
<function>down_interruptible()</function> to grab the semaphore, and
};
-static DEFINE_MUTEX(cache_lock);
-+static spinlock_t cache_lock = SPIN_LOCK_UNLOCKED;
++static DEFINE_SPINLOCK(cache_lock);
static LIST_HEAD(cache);
static unsigned int cache_num = 0;
#define MAX_CACHE_SIZE 10
- int popularity;
};
- static spinlock_t cache_lock = SPIN_LOCK_UNLOCKED;
+ static DEFINE_SPINLOCK(cache_lock);
@@ -77,6 +84,7 @@
obj->id = id;
obj->popularity = 0;
#include <linux/slab.h>
#include <linux/string.h>
+#include <linux/rcupdate.h>
- #include <asm/semaphore.h>
+ #include <linux/semaphore.h>
#include <asm/errno.h>
struct object
useful documents, at the USB home page (see Resources). An excellent
introduction to the Linux USB subsystem can be found at the USB Working
Devices List (see Resources). It explains how the Linux USB subsystem is
- structured and introduces the reader to the concept of USB urbs, which
- are essential to USB drivers.
+ structured and introduces the reader to the concept of USB urbs
+ (USB Request Blocks), which are essential to USB drivers.
</para>
<para>
The first thing a Linux USB driver needs to do is register itself with
module_init(usb_skel_init);
</programlisting>
<para>
- When the driver is unloaded from the system, it needs to unregister
- itself with the USB subsystem. This is done with the usb_unregister
+ When the driver is unloaded from the system, it needs to deregister
+ itself with the USB subsystem. This is done with the usb_deregister
function:
</para>
<programlisting>
were passed to the USB subsystem will be called from a user program trying
to talk to the device. The first function called will be open, as the
program tries to open the device for I/O. We increment our private usage
- count and save off a pointer to our internal structure in the file
+ count and save a pointer to our internal structure in the file
structure. This is done so that future calls to file operations will
enable the driver to determine which device the user is addressing. All
of this is done with the following code:
send to the device based on the size of the write urb it has created (this
size depends on the size of the bulk out end point that the device has).
Then it copies the data from user space to kernel space, points the urb to
- the data and submits the urb to the USB subsystem. This can be shown in
- he following code:
+ the data and submits the urb to the USB subsystem. This can be seen in
+ the following code:
</para>
<programlisting>
/* we can only write as much as 1 urb will hold */
--- /dev/null
+00-INDEX
+ - this file
+PCI-DMA-mapping.txt
+ - info for PCI drivers using DMA portably across all platforms
+PCIEBUS-HOWTO.txt
+ - a guide describing the PCI Express Port Bus driver
+pci-error-recovery.txt
+ - info on PCI error recovery
+pci.txt
+ - info on the PCI subsystem for device driver authors
+pcieaer-howto.txt
+ - the PCI Express Advanced Error Reporting Driver Guide HOWTO
- Allow service drivers implemented in an independent
staged approach.
-
+
- Allow one service driver to run on multiple PCI-PCI Bridge
- Port devices.
+ Port devices.
- Manage and distribute resources of a PCI-PCI Bridge Port
device to requested service drivers.
imposes no impact on the functionality of existing service drivers.
A service driver is required to use the two APIs shown below to
-register its service with the PCI Express Port Bus driver (see
+register its service with the PCI Express Port Bus driver (see
section 5.2.1 & 5.2.2). It is important that a service driver
initializes the pcie_port_service_driver data structure, included in
header file /include/linux/pcieport_if.h, before calling these APIs.
static int __init aerdrv_service_init(void)
{
int retval = 0;
-
+
retval = pcie_port_service_register(&root_aerdrv);
if (!retval) {
/*
return retval;
}
-static void __exit aerdrv_service_exit(void)
+static void __exit aerdrv_service_exit(void)
{
pcie_port_service_unregister(&root_aerdrv);
}
request MSI based interrupts. A service driver may not know whether
any other service drivers have run on this Root Port. If either one
of them calls pci_disable_msi, it puts the other service driver
-in a wrong interrupt mode.
+in a wrong interrupt mode.
To avoid this situation all service drivers are not permitted to
switch interrupt mode on its device. The PCI Express Port Bus driver
the power state of a device before reboot.
e.g. drivers/net/e100.c.
- err_handler See Documentation/pci-error-recovery.txt
+ err_handler See Documentation/PCI/pci-error-recovery.txt
The ID table is an array of struct pci_device_id entries ending with an
well as how to enable the drivers of endpoint devices to conform with
PCI Express AER driver.
-1.2 Copyright © Intel Corporation 2006.
+1.2 Copyright © Intel Corporation 2006.
1.3 What is the PCI Express AER Driver?
copy the maintainer when you change their code.
For small patches you may want to CC the Trivial Patch Monkey
-trivial@kernel.org managed by Adrian Bunk; which collects "trivial"
+trivial@kernel.org managed by Jesper Juhl; which collects "trivial"
patches. Trivial patches must qualify for one of the following rules:
Spelling fixes in documentation
Spelling fixes which could break grep(1)
since people copy, as long as it's trivial)
Any fix by the author/maintainer of the file (ie. patch monkey
in re-transmission mode)
-URL: <http://www.kernel.org/pub/linux/kernel/people/bunk/trivial/>
+URL: <http://www.kernel.org/pub/linux/kernel/people/juhl/trivial/>
io_request_lock for serialization need to be modified accordingly.
Usually it's as easy as adding a global lock:
- static spinlock_t my_driver_lock = SPIN_LOCK_UNLOCKED;
+ static DEFINE_SPINLOCK(my_driver_lock);
and passing the address to that lock to blk_init_queue().
it may have as many structures $<device>_info$ as there are minor devices
active. $Register_cdrom()$ builds a linked list from these.
-\subsection{$Int\ unregister_cdrom(struct\ cdrom_device_info * cdi)$}
+\subsection{$Void\ unregister_cdrom(struct\ cdrom_device_info * cdi)$}
Unregistering device $cdi$ with minor number $MINOR(cdi\to dev)$ removes
the minor device from the list. If it was the last registered minor for
but from now on a more direct method of locking has to be used:
- spinlock_t driver_lock = SPIN_LOCK_UNLOCKED;
+ DEFINE_SPINLOCK(driver_lock);
struct driver_data;
irq_handler (...)
Modified by Paul Jackson <pj@sgi.com>
Modified by Christoph Lameter <clameter@sgi.com>
Modified by Paul Menage <menage@google.com>
+Modified by Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
CONTENTS:
=========
1.5 What is memory_pressure ?
1.6 What is memory spread ?
1.7 What is sched_load_balance ?
- 1.8 How do I use cpusets ?
+ 1.8 What is sched_relax_domain_level ?
+ 1.9 How do I use cpusets ?
2. Usage Examples and Syntax
2.1 Basic Usage
2.2 Adding/removing cpus
partition requested with the current, and updates its sched domains,
removing the old and adding the new, for each change.
-1.8 How do I use cpusets ?
+
+1.8 What is sched_relax_domain_level ?
+--------------------------------------
+
+In sched domain, the scheduler migrates tasks in 2 ways; periodic load
+balance on tick, and at time of some schedule events.
+
+When a task is woken up, scheduler try to move the task on idle CPU.
+For example, if a task A running on CPU X activates another task B
+on the same CPU X, and if CPU Y is X's sibling and performing idle,
+then scheduler migrate task B to CPU Y so that task B can start on
+CPU Y without waiting task A on CPU X.
+
+And if a CPU run out of tasks in its runqueue, the CPU try to pull
+extra tasks from other busy CPUs to help them before it is going to
+be idle.
+
+Of course it takes some searching cost to find movable tasks and/or
+idle CPUs, the scheduler might not search all CPUs in the domain
+everytime. In fact, in some architectures, the searching ranges on
+events are limited in the same socket or node where the CPU locates,
+while the load balance on tick searchs all.
+
+For example, assume CPU Z is relatively far from CPU X. Even if CPU Z
+is idle while CPU X and the siblings are busy, scheduler can't migrate
+woken task B from X to Z since it is out of its searching range.
+As the result, task B on CPU X need to wait task A or wait load balance
+on the next tick. For some applications in special situation, waiting
+1 tick may be too long.
+
+The 'sched_relax_domain_level' file allows you to request changing
+this searching range as you like. This file takes int value which
+indicates size of searching range in levels ideally as follows,
+otherwise initial value -1 that indicates the cpuset has no request.
+
+ -1 : no request. use system default or follow request of others.
+ 0 : no search.
+ 1 : search siblings (hyperthreads in a core).
+ 2 : search cores in a package.
+ 3 : search cpus in a node [= system wide on non-NUMA system]
+ ( 4 : search nodes in a chunk of node [on NUMA system] )
+ ( 5~ : search system wide [on NUMA system])
+
+This file is per-cpuset and affect the sched domain where the cpuset
+belongs to. Therefore if the flag 'sched_load_balance' of a cpuset
+is disabled, then 'sched_relax_domain_level' have no effect since
+there is no sched domain belonging the cpuset.
+
+If multiple cpusets are overlapping and hence they form a single sched
+domain, the largest value among those is used. Be careful, if one
+requests 0 and others are -1 then 0 is used.
+
+Note that modifying this file will have both good and bad effects,
+and whether it is acceptable or not will be depend on your situation.
+Don't modify this file if you are not sure.
+
+If your situation is:
+ - The migration costs between each cpu can be assumed considerably
+ small(for you) due to your special application's behavior or
+ special hardware support for CPU cache etc.
+ - The searching cost doesn't have impact(for you) or you can make
+ the searching cost enough small by managing cpuset to compact etc.
+ - The latency is required even it sacrifices cache hit rate etc.
+then increasing 'sched_relax_domain_level' would benefit you.
+
+
+1.9 How do I use cpusets ?
--------------------------
In order to minimize the impact of cpusets on critical kernel
.mm
53c700_d.h
53c8xx_d.h*
-BitKeeper
COPYING
CREDITS
CVS
You can obtain somewhat infrequent snapshots of klibc from
ftp://ftp.kernel.org/pub/linux/libs/klibc/
-For active users, you are better off using the klibc BitKeeper
-repositories, at http://klibc.bkbits.net/
+For active users, you are better off using the klibc git
+repository, at http://git.kernel.org/?p=libs/klibc/klibc.git
The standalone klibc distribution currently provides three components,
in addition to the klibc library:
---------------------------
-What: Solaris/SunOS syscall and binary support on Sparc
-When: 2.6.26
-Why: Largely unmaintained and almost entirely unused. File system
- layering used to divert library and dynamic linker searches to
- /usr/gnemul is extremely buggy and unfixable. Making it work
- is largely pointless as without a lot of work only the most
- trivial of Solaris binaries can work with the emulation code.
-Who: David S. Miller <davem@davemloft.net>
-
----------------------------
-
What: init_mm export
When: 2.6.26
Why: Not used in-tree. The current out-of-tree users used it to
out-of-tree driver.
Who: Thomas Gleixner <tglx@linutronix.de>
+----------------------------
+
+What: usedac i386 kernel parameter
+When: 2.6.27
+Why: replaced by allowdac and no dac combination
+Who: Glauber Costa <gcosta@redhat.com>
+
---------------------------
What: /sys/o2cb symlink
ocfs2-tools. 2 years should be sufficient time to phase in new versions
which know to look in /sys/fs/o2cb.
Who: ocfs2-devel@oss.oracle.com
+
+---------------------------
+
+What: asm/semaphore.h
+When: 2.6.26
+Why: Implementation became generic; users should now include
+ linux/semaphore.h instead.
+Who: Matthew Wilcox <willy@linux.intel.com>
Recall that an attribute should only be exporting one value, or an
array of similar values, so this shouldn't be that expensive.
- This allows userspace to do partial reads and seeks arbitrarily over
- the entire file at will.
+ This allows userspace to do partial reads and forward seeks
+ arbitrarily over the entire file at will. If userspace seeks back to
+ zero or does a pread(2) with an offset of '0' the show() method will
+ be called again, rearmed, to fill the buffer.
- On write(2), sysfs expects the entire buffer to be passed during the
first write. Sysfs then passes the entire buffer to the store()
Other notes:
+- Writing causes the show() method to be rearmed regardless of current
+ file position.
+
- The buffer will always be PAGE_SIZE bytes in length. On i386, this
is 4096.
uses the 32-bit UID system calls properly otherwise.
This affects at least:
- SunOS emulation
- Solaris emulation
iBCS on Intel
sparc32 emulation on sparc64
than 32 bit addressing. The default is to look
for translation below 32 bit and if not available
then look in the higher range.
+ strict [Default Off]
+ With this option on every unmap_single operation will
+ result in a hardware IOTLB flush operation as opposed
+ to batching them for performance.
io_delay= [X86-32,X86-64] I/O delay method
0x80
l2cr= [PPC]
+ l3cr= [PPC]
+
lapic [X86-32,APIC] Enable the local APIC even if BIOS
disabled it.
noexec [IA-64]
noexec [X86-32,X86-64]
+ On X86-32 available only on PAE configured kernels.
noexec=on: enable non-executable mappings (default)
- noexec=off: disable nn-executable mappings
+ noexec=off: disable non-executable mappings
+
+ noexec32 [X86-64]
+ This affects only 32-bit executables.
+ noexec32=on: enable non-executable mappings (default)
+ read doesn't imply executable mappings
+ noexec32=off: disable non-executable mappings
+ read implies executable mappings
nofxsr [BUGS=X86-32] Disables x86 floating point extended
register save and restore. The kernel will only save
nomsi [MSI] If the PCI_MSI kernel config parameter is
enabled, this kernel boot option can be used to
disable the use of MSI interrupts system-wide.
- nosort [X86-32] Don't sort PCI devices according to
- order given by the PCI BIOS. This sorting is
- done to get a device order compatible with
- older kernels.
biosirq [X86-32] Use PCI BIOS calls to get the interrupt
routing table. These calls are known to be buggy
on several machines and they hang the machine
USB_SERIAL_PORT_MAGIC 0x7301 usb_serial_port drivers/usb/serial/usb-serial.h
CG_MAGIC 0x00090255 ufs_cylinder_group include/linux/ufs_fs.h
A2232_MAGIC 0x000a2232 gs_port drivers/char/ser_a2232.h
-SOLARIS_SOCKET_MAGIC 0x000ADDED sol_socket_struct arch/sparc64/solaris/socksys.h
RPORT_MAGIC 0x00525001 r_port drivers/char/rocket_int.h
LSEMAGIC 0x05091998 lse drivers/fc4/fc.c
GDTIOCTL_MAGIC 0x06030f07 gdth_iowr_str drivers/scsi/gdth_ioctl.h
[*] For information on bus mastering DMA and coherency please read:
- Documentation/pci.txt
- Documentation/DMA-mapping.txt
+ Documentation/PCI/pci.txt
+ Documentation/PCI/PCI-DMA-mapping.txt
Documentation/DMA-API.txt
The policy is that the device tree should match hardware bus topology.
(Or at least the control bus, for devices which use multiple busses.)
+In particular, this means that a device registration may fail if the parent of
+the device is suspending (ie. has been chosen by the PM core as the next
+device to suspend) or has already suspended, as well as after all of the other
+devices have been suspended. Device drivers must be prepared to cope with such
+situations.
Suspending Devices
p) Freescale Synchronous Serial Interface
q) USB EHCI controllers
- VII - Specifying interrupt information for devices
+ VII - Marvell Discovery mv64[345]6x System Controller chips
+ 1) The /system-controller node
+ 2) Child nodes of /system-controller
+ a) Marvell Discovery MDIO bus
+ b) Marvell Discovery ethernet controller
+ c) Marvell Discovery PHY nodes
+ d) Marvell Discovery SDMA nodes
+ e) Marvell Discovery BRG nodes
+ f) Marvell Discovery CUNIT nodes
+ g) Marvell Discovery MPSCROUTING nodes
+ h) Marvell Discovery MPSCINTR nodes
+ i) Marvell Discovery MPSC nodes
+ j) Marvell Discovery Watch Dog Timer nodes
+ k) Marvell Discovery I2C nodes
+ l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
+ m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
+ n) Marvell Discovery GPP (General Purpose Pins) nodes
+ o) Marvell Discovery PCI host bridge node
+ p) Marvell Discovery CPU Error nodes
+ q) Marvell Discovery SRAM Controller nodes
+ r) Marvell Discovery PCI Error Handler nodes
+ s) Marvell Discovery Memory Controller nodes
+
+ VIII - Specifying interrupt information for devices
1) interrupts property
2) interrupt-parent property
3) OpenPIC Interrupt Controllers
4) ISA Interrupt Controllers
+ VIII - Specifying GPIO information for devices
+ 1) gpios property
+ 2) gpio-controller nodes
+
Appendix A - Sample SOC node for MPC8540
Recommended properties:
- - linux,network-index : This is the intended "index" of this
- network device. This is used by the bootwrapper to interpret
- MAC addresses passed by the firmware when no information other
- than indices is available to associate an address with a device.
- phy-connection-type : a string naming the controller/PHY interface type,
i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
"tbi", or "rtbi". This property is only really needed if the connection
- device_type : should be "network", "hldc", "uart", "transparent"
"bisync", "atm", or "serial".
- compatible : could be "ucc_geth" or "fsl_atm" and so on.
- - model : should be "UCC".
- - device-id : the ucc number(1-8), corresponding to UCCx in UM.
+ - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
- reg : Offset and length of the register set for the device
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
- phy-handle : The phandle for the PHY connected to this controller.
Recommended properties:
- - linux,network-index : This is the intended "index" of this
- network device. This is used by the bootwrapper to interpret
- MAC addresses passed by the firmware when no information other
- than indices is available to associate an address with a device.
- phy-connection-type : a string naming the controller/PHY interface type,
i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
- device-id = <1>;
+ cell-index = <1>;
reg = <2000 200>;
interrupts = <a0 0>;
interrupt-parent = <700>;
interrupts = <20 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
- linux,network-index = <0>;
fsl,cpm-command = <12000300>;
};
EMAC, that is the content of the current (bogus) "phy-port"
property.
- Recommended properties:
- - linux,network-index : This is the intended "index" of this
- network device. This is used by the bootwrapper to interpret
- MAC addresses passed by the firmware when no information other
- than indices is available to associate an address with a device.
-
Optional properties:
- phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
a search is performed.
Example:
EMAC0: ethernet@40000800 {
- linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-440gp", "ibm,emac";
interrupt-parent = <&UIC1>;
};
- More devices will be defined as this spec matures.
+VII - Marvell Discovery mv64[345]6x System Controller chips
+===========================================================
+
+The Marvell mv64[345]60 series of system controller chips contain
+many of the peripherals needed to implement a complete computer
+system. In this section, we define device tree nodes to describe
+the system controller chip itself and each of the peripherals
+which it contains. Compatible string values for each node are
+prefixed with the string "marvell,", for Marvell Technology Group Ltd.
+
+1) The /system-controller node
+
+ This node is used to represent the system-controller and must be
+ present when the system uses a system contller chip. The top-level
+ system-controller node contains information that is global to all
+ devices within the system controller chip. The node name begins
+ with "system-controller" followed by the unit address, which is
+ the base address of the memory-mapped register set for the system
+ controller chip.
+
+ Required properties:
+
+ - ranges : Describes the translation of system controller addresses
+ for memory mapped registers.
+ - clock-frequency: Contains the main clock frequency for the system
+ controller chip.
+ - reg : This property defines the address and size of the
+ memory-mapped registers contained within the system controller
+ chip. The address specified in the "reg" property should match
+ the unit address of the system-controller node.
+ - #address-cells : Address representation for system controller
+ devices. This field represents the number of cells needed to
+ represent the address of the memory-mapped registers of devices
+ within the system controller chip.
+ - #size-cells : Size representation for for the memory-mapped
+ registers within the system controller chip.
+ - #interrupt-cells : Defines the width of cells used to represent
+ interrupts.
+
+ Optional properties:
+
+ - model : The specific model of the system controller chip. Such
+ as, "mv64360", "mv64460", or "mv64560".
+ - compatible : A string identifying the compatibility identifiers
+ of the system controller chip.
+
+ The system-controller node contains child nodes for each system
+ controller device that the platform uses. Nodes should not be created
+ for devices which exist on the system controller chip but are not used
+
+ Example Marvell Discovery mv64360 system-controller node:
+
+ system-controller@f1000000 { /* Marvell Discovery mv64360 */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "mv64360"; /* Default */
+ compatible = "marvell,mv64360";
+ clock-frequency = <133333333>;
+ reg = <0xf1000000 0x10000>;
+ virtual-reg = <0xf1000000>;
+ ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
+ 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
+ 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
+ 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
+ 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
+
+ [ child node definitions... ]
+ }
+
+2) Child nodes of /system-controller
+
+ a) Marvell Discovery MDIO bus
+
+ The MDIO is a bus to which the PHY devices are connected. For each
+ device that exists on this bus, a child node should be created. See
+ the definition of the PHY node below for an example of how to define
+ a PHY.
+
+ Required properties:
+ - #address-cells : Should be <1>
+ - #size-cells : Should be <0>
+ - device_type : Should be "mdio"
+ - compatible : Should be "marvell,mv64360-mdio"
+
+ Example:
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "mdio";
+ compatible = "marvell,mv64360-mdio";
+
+ ethernet-phy@0 {
+ ......
+ };
+ };
+
+
+ b) Marvell Discovery ethernet controller
+
+ The Discover ethernet controller is described with two levels
+ of nodes. The first level describes an ethernet silicon block
+ and the second level describes up to 3 ethernet nodes within
+ that block. The reason for the multiple levels is that the
+ registers for the node are interleaved within a single set
+ of registers. The "ethernet-block" level describes the
+ shared register set, and the "ethernet" nodes describe ethernet
+ port-specific properties.
+
+ Ethernet block node
+
+ Required properties:
+ - #address-cells : <1>
+ - #size-cells : <0>
+ - compatible : "marvell,mv64360-eth-block"
+ - reg : Offset and length of the register set for this block
+
+ Example Discovery Ethernet block node:
+ ethernet-block@2000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,mv64360-eth-block";
+ reg = <0x2000 0x2000>;
+ ethernet@0 {
+ .......
+ };
+ };
+
+ Ethernet port node
+
+ Required properties:
+ - device_type : Should be "network".
+ - compatible : Should be "marvell,mv64360-eth".
+ - reg : Should be <0>, <1>, or <2>, according to which registers
+ within the silicon block the device uses.
+ - interrupts : <a> where a is the interrupt number for the port.
+ - interrupt-parent : the phandle for the interrupt controller
+ that services interrupts for this device.
+ - phy : the phandle for the PHY connected to this ethernet
+ controller.
+ - local-mac-address : 6 bytes, MAC address
+
+ Example Discovery Ethernet port node:
+ ethernet@0 {
+ device_type = "network";
+ compatible = "marvell,mv64360-eth";
+ reg = <0>;
+ interrupts = <32>;
+ interrupt-parent = <&PIC>;
+ phy = <&PHY0>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+
+
+ c) Marvell Discovery PHY nodes
+
+ Required properties:
+ - device_type : Should be "ethernet-phy"
+ - interrupts : <a> where a is the interrupt number for this phy.
+ - interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+ - reg : The ID number for the phy, usually a small integer
+
+ Example Discovery PHY node:
+ ethernet-phy@1 {
+ device_type = "ethernet-phy";
+ compatible = "broadcom,bcm5421";
+ interrupts = <76>; /* GPP 12 */
+ interrupt-parent = <&PIC>;
+ reg = <1>;
+ };
+
+
+ d) Marvell Discovery SDMA nodes
+
+ Represent DMA hardware associated with the MPSC (multiprotocol
+ serial controllers).
+
+ Required properties:
+ - compatible : "marvell,mv64360-sdma"
+ - reg : Offset and length of the register set for this device
+ - interrupts : <a> where a is the interrupt number for the DMA
+ device.
+ - interrupt-parent : the phandle for the interrupt controller
+ that services interrupts for this device.
+
+ Example Discovery SDMA node:
+ sdma@4000 {
+ compatible = "marvell,mv64360-sdma";
+ reg = <0x4000 0xc18>;
+ virtual-reg = <0xf1004000>;
+ interrupts = <36>;
+ interrupt-parent = <&PIC>;
+ };
+
+
+ e) Marvell Discovery BRG nodes
+
+ Represent baud rate generator hardware associated with the MPSC
+ (multiprotocol serial controllers).
+
+ Required properties:
+ - compatible : "marvell,mv64360-brg"
+ - reg : Offset and length of the register set for this device
+ - clock-src : A value from 0 to 15 which selects the clock
+ source for the baud rate generator. This value corresponds
+ to the CLKS value in the BRGx configuration register. See
+ the mv64x60 User's Manual.
+ - clock-frequence : The frequency (in Hz) of the baud rate
+ generator's input clock.
+ - current-speed : The current speed setting (presumably by
+ firmware) of the baud rate generator.
+
+ Example Discovery BRG node:
+ brg@b200 {
+ compatible = "marvell,mv64360-brg";
+ reg = <0xb200 0x8>;
+ clock-src = <8>;
+ clock-frequency = <133333333>;
+ current-speed = <9600>;
+ };
+
+
+ f) Marvell Discovery CUNIT nodes
+
+ Represent the Serial Communications Unit device hardware.
+
+ Required properties:
+ - reg : Offset and length of the register set for this device
+
+ Example Discovery CUNIT node:
+ cunit@f200 {
+ reg = <0xf200 0x200>;
+ };
+
+
+ g) Marvell Discovery MPSCROUTING nodes
+
+ Represent the Discovery's MPSC routing hardware
+
+ Required properties:
+ - reg : Offset and length of the register set for this device
+
+ Example Discovery CUNIT node:
+ mpscrouting@b500 {
+ reg = <0xb400 0xc>;
+ };
+
+
+ h) Marvell Discovery MPSCINTR nodes
+
+ Represent the Discovery's MPSC DMA interrupt hardware registers
+ (SDMA cause and mask registers).
+
+ Required properties:
+ - reg : Offset and length of the register set for this device
-VII - Specifying interrupt information for devices
+ Example Discovery MPSCINTR node:
+ mpsintr@b800 {
+ reg = <0xb800 0x100>;
+ };
+
+
+ i) Marvell Discovery MPSC nodes
+
+ Represent the Discovery's MPSC (Multiprotocol Serial Controller)
+ serial port.
+
+ Required properties:
+ - device_type : "serial"
+ - compatible : "marvell,mv64360-mpsc"
+ - reg : Offset and length of the register set for this device
+ - sdma : the phandle for the SDMA node used by this port
+ - brg : the phandle for the BRG node used by this port
+ - cunit : the phandle for the CUNIT node used by this port
+ - mpscrouting : the phandle for the MPSCROUTING node used by this port
+ - mpscintr : the phandle for the MPSCINTR node used by this port
+ - cell-index : the hardware index of this cell in the MPSC core
+ - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
+ register
+ - interrupts : <a> where a is the interrupt number for the MPSC.
+ - interrupt-parent : the phandle for the interrupt controller
+ that services interrupts for this device.
+
+ Example Discovery MPSCINTR node:
+ mpsc@8000 {
+ device_type = "serial";
+ compatible = "marvell,mv64360-mpsc";
+ reg = <0x8000 0x38>;
+ virtual-reg = <0xf1008000>;
+ sdma = <&SDMA0>;
+ brg = <&BRG0>;
+ cunit = <&CUNIT>;
+ mpscrouting = <&MPSCROUTING>;
+ mpscintr = <&MPSCINTR>;
+ cell-index = <0>;
+ max_idle = <40>;
+ interrupts = <40>;
+ interrupt-parent = <&PIC>;
+ };
+
+
+ j) Marvell Discovery Watch Dog Timer nodes
+
+ Represent the Discovery's watchdog timer hardware
+
+ Required properties:
+ - compatible : "marvell,mv64360-wdt"
+ - reg : Offset and length of the register set for this device
+
+ Example Discovery Watch Dog Timer node:
+ wdt@b410 {
+ compatible = "marvell,mv64360-wdt";
+ reg = <0xb410 0x8>;
+ };
+
+
+ k) Marvell Discovery I2C nodes
+
+ Represent the Discovery's I2C hardware
+
+ Required properties:
+ - device_type : "i2c"
+ - compatible : "marvell,mv64360-i2c"
+ - reg : Offset and length of the register set for this device
+ - interrupts : <a> where a is the interrupt number for the I2C.
+ - interrupt-parent : the phandle for the interrupt controller
+ that services interrupts for this device.
+
+ Example Discovery I2C node:
+ compatible = "marvell,mv64360-i2c";
+ reg = <0xc000 0x20>;
+ virtual-reg = <0xf100c000>;
+ interrupts = <37>;
+ interrupt-parent = <&PIC>;
+ };
+
+
+ l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
+
+ Represent the Discovery's PIC hardware
+
+ Required properties:
+ - #interrupt-cells : <1>
+ - #address-cells : <0>
+ - compatible : "marvell,mv64360-pic"
+ - reg : Offset and length of the register set for this device
+ - interrupt-controller
+
+ Example Discovery PIC node:
+ pic {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ compatible = "marvell,mv64360-pic";
+ reg = <0x0 0x88>;
+ interrupt-controller;
+ };
+
+
+ m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
+
+ Represent the Discovery's MPP hardware
+
+ Required properties:
+ - compatible : "marvell,mv64360-mpp"
+ - reg : Offset and length of the register set for this device
+
+ Example Discovery MPP node:
+ mpp@f000 {
+ compatible = "marvell,mv64360-mpp";
+ reg = <0xf000 0x10>;
+ };
+
+
+ n) Marvell Discovery GPP (General Purpose Pins) nodes
+
+ Represent the Discovery's GPP hardware
+
+ Required properties:
+ - compatible : "marvell,mv64360-gpp"
+ - reg : Offset and length of the register set for this device
+
+ Example Discovery GPP node:
+ gpp@f000 {
+ compatible = "marvell,mv64360-gpp";
+ reg = <0xf100 0x20>;
+ };
+
+
+ o) Marvell Discovery PCI host bridge node
+
+ Represents the Discovery's PCI host bridge device. The properties
+ for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
+ 1275-1994. A typical value for the compatible property is
+ "marvell,mv64360-pci".
+
+ Example Discovery PCI host bridge node
+ pci@80000000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ compatible = "marvell,mv64360-pci";
+ reg = <0xcf8 0x8>;
+ ranges = <0x01000000 0x0 0x0
+ 0x88000000 0x0 0x01000000
+ 0x02000000 0x0 0x80000000
+ 0x80000000 0x0 0x08000000>;
+ bus-range = <0 255>;
+ clock-frequency = <66000000>;
+ interrupt-parent = <&PIC>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0a */
+ 0x5000 0 0 1 &PIC 80
+ 0x5000 0 0 2 &PIC 81
+ 0x5000 0 0 3 &PIC 91
+ 0x5000 0 0 4 &PIC 93
+
+ /* IDSEL 0x0b */
+ 0x5800 0 0 1 &PIC 91
+ 0x5800 0 0 2 &PIC 93
+ 0x5800 0 0 3 &PIC 80
+ 0x5800 0 0 4 &PIC 81
+
+ /* IDSEL 0x0c */
+ 0x6000 0 0 1 &PIC 91
+ 0x6000 0 0 2 &PIC 93
+ 0x6000 0 0 3 &PIC 80
+ 0x6000 0 0 4 &PIC 81
+
+ /* IDSEL 0x0d */
+ 0x6800 0 0 1 &PIC 93
+ 0x6800 0 0 2 &PIC 80
+ 0x6800 0 0 3 &PIC 81
+ 0x6800 0 0 4 &PIC 91
+ >;
+ };
+
+
+ p) Marvell Discovery CPU Error nodes
+
+ Represent the Discovery's CPU error handler device.
+
+ Required properties:
+ - compatible : "marvell,mv64360-cpu-error"
+ - reg : Offset and length of the register set for this device
+ - interrupts : the interrupt number for this device
+ - interrupt-parent : the phandle for the interrupt controller
+ that services interrupts for this device.
+
+ Example Discovery CPU Error node:
+ cpu-error@0070 {
+ compatible = "marvell,mv64360-cpu-error";
+ reg = <0x70 0x10 0x128 0x28>;
+ interrupts = <3>;
+ interrupt-parent = <&PIC>;
+ };
+
+
+ q) Marvell Discovery SRAM Controller nodes
+
+ Represent the Discovery's SRAM controller device.
+
+ Required properties:
+ - compatible : "marvell,mv64360-sram-ctrl"
+ - reg : Offset and length of the register set for this device
+ - interrupts : the interrupt number for this device
+ - interrupt-parent : the phandle for the interrupt controller
+ that services interrupts for this device.
+
+ Example Discovery SRAM Controller node:
+ sram-ctrl@0380 {
+ compatible = "marvell,mv64360-sram-ctrl";
+ reg = <0x380 0x80>;
+ interrupts = <13>;
+ interrupt-parent = <&PIC>;
+ };
+
+
+ r) Marvell Discovery PCI Error Handler nodes
+
+ Represent the Discovery's PCI error handler device.
+
+ Required properties:
+ - compatible : "marvell,mv64360-pci-error"
+ - reg : Offset and length of the register set for this device
+ - interrupts : the interrupt number for this device
+ - interrupt-parent : the phandle for the interrupt controller
+ that services interrupts for this device.
+
+ Example Discovery PCI Error Handler node:
+ pci-error@1d40 {
+ compatible = "marvell,mv64360-pci-error";
+ reg = <0x1d40 0x40 0xc28 0x4>;
+ interrupts = <12>;
+ interrupt-parent = <&PIC>;
+ };
+
+
+ s) Marvell Discovery Memory Controller nodes
+
+ Represent the Discovery's memory controller device.
+
+ Required properties:
+ - compatible : "marvell,mv64360-mem-ctrl"
+ - reg : Offset and length of the register set for this device
+ - interrupts : the interrupt number for this device
+ - interrupt-parent : the phandle for the interrupt controller
+ that services interrupts for this device.
+
+ Example Discovery Memory Controller node:
+ mem-ctrl@1400 {
+ compatible = "marvell,mv64360-mem-ctrl";
+ reg = <0x1400 0x60>;
+ interrupts = <17>;
+ interrupt-parent = <&PIC>;
+ };
+
+
+VIII - Specifying interrupt information for devices
===================================================
The device tree represents the busses and devices of a hardware
2 = high to low edge sensitive type enabled
3 = low to high edge sensitive type enabled
+VIII - Specifying GPIO information for devices
+==============================================
+
+1) gpios property
+-----------------
+
+Nodes that makes use of GPIOs should define them using `gpios' property,
+format of which is: <&gpio-controller1-phandle gpio1-specifier
+ &gpio-controller2-phandle gpio2-specifier
+ 0 /* holes are permitted, means no GPIO 3 */
+ &gpio-controller4-phandle gpio4-specifier
+ ...>;
+
+Note that gpio-specifier length is controller dependent.
+
+gpio-specifier may encode: bank, pin position inside the bank,
+whether pin is open-drain and whether pin is logically inverted.
+
+Example of the node using GPIOs:
+
+ node {
+ gpios = <&qe_pio_e 18 0>;
+ };
+
+In this example gpio-specifier is "18 0" and encodes GPIO pin number,
+and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
+
+2) gpio-controller nodes
+------------------------
+
+Every GPIO controller node must have #gpio-cells property defined,
+this information will be used to translate gpio-specifiers.
+
+Example of two SOC GPIO banks defined as gpio-controller nodes:
+
+ qe_pio_a: gpio-controller@1400 {
+ #gpio-cells = <2>;
+ compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
+ reg = <0x1400 0x18>;
+ gpio-controller;
+ };
+
+ qe_pio_e: gpio-controller@1460 {
+ #gpio-cells = <2>;
+ compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
+ reg = <0x1460 0x18>;
+ gpio-controller;
+ };
Appendix A - Sample SOC node for MPC8540
========================================
--- /dev/null
+
+ Hypervisor-Assisted Dump
+ ------------------------
+ November 2007
+
+The goal of hypervisor-assisted dump is to enable the dump of
+a crashed system, and to do so from a fully-reset system, and
+to minimize the total elapsed time until the system is back
+in production use.
+
+As compared to kdump or other strategies, hypervisor-assisted
+dump offers several strong, practical advantages:
+
+-- Unlike kdump, the system has been reset, and loaded
+ with a fresh copy of the kernel. In particular,
+ PCI and I/O devices have been reinitialized and are
+ in a clean, consistent state.
+-- As the dump is performed, the dumped memory becomes
+ immediately available to the system for normal use.
+-- After the dump is completed, no further reboots are
+ required; the system will be fully usable, and running
+ in it's normal, production mode on it normal kernel.
+
+The above can only be accomplished by coordination with,
+and assistance from the hypervisor. The procedure is
+as follows:
+
+-- When a system crashes, the hypervisor will save
+ the low 256MB of RAM to a previously registered
+ save region. It will also save system state, system
+ registers, and hardware PTE's.
+
+-- After the low 256MB area has been saved, the
+ hypervisor will reset PCI and other hardware state.
+ It will *not* clear RAM. It will then launch the
+ bootloader, as normal.
+
+-- The freshly booted kernel will notice that there
+ is a new node (ibm,dump-kernel) in the device tree,
+ indicating that there is crash data available from
+ a previous boot. It will boot into only 256MB of RAM,
+ reserving the rest of system memory.
+
+-- Userspace tools will parse /sys/kernel/release_region
+ and read /proc/vmcore to obtain the contents of memory,
+ which holds the previous crashed kernel. The userspace
+ tools may copy this info to disk, or network, nas, san,
+ iscsi, etc. as desired.
+
+ For Example: the values in /sys/kernel/release-region
+ would look something like this (address-range pairs).
+ CPU:0x177fee000-0x10000: HPTE:0x177ffe020-0x1000: /
+ DUMP:0x177fff020-0x10000000, 0x10000000-0x16F1D370A
+
+-- As the userspace tools complete saving a portion of
+ dump, they echo an offset and size to
+ /sys/kernel/release_region to release the reserved
+ memory back to general use.
+
+ An example of this is:
+ "echo 0x40000000 0x10000000 > /sys/kernel/release_region"
+ which will release 256MB at the 1GB boundary.
+
+Please note that the hypervisor-assisted dump feature
+is only available on Power6-based systems with recent
+firmware versions.
+
+Implementation details:
+----------------------
+
+During boot, a check is made to see if firmware supports
+this feature on this particular machine. If it does, then
+we check to see if a active dump is waiting for us. If yes
+then everything but 256 MB of RAM is reserved during early
+boot. This area is released once we collect a dump from user
+land scripts that are run. If there is dump data, then
+the /sys/kernel/release_region file is created, and
+the reserved memory is held.
+
+If there is no waiting dump data, then only the highest
+256MB of the ram is reserved as a scratch area. This area
+is *not* released: this region will be kept permanently
+reserved, so that it can act as a receptacle for a copy
+of the low 256MB in the case a crash does occur. See,
+however, "open issues" below, as to whether
+such a reserved region is really needed.
+
+Currently the dump will be copied from /proc/vmcore to a
+a new file upon user intervention. The starting address
+to be read and the range for each data point in provided
+in /sys/kernel/release_region.
+
+The tools to examine the dump will be same as the ones
+used for kdump.
+
+General notes:
+--------------
+Security: please note that there are potential security issues
+with any sort of dump mechanism. In particular, plaintext
+(unencrypted) data, and possibly passwords, may be present in
+the dump data. Userspace tools must take adequate precautions to
+preserve security.
+
+Open issues/ToDo:
+------------
+ o The various code paths that tell the hypervisor that a crash
+ occurred, vs. it simply being a normal reboot, should be
+ reviewed, and possibly clarified/fixed.
+
+ o Instead of using /sys/kernel, should there be a /sys/dump
+ instead? There is a dump_subsys being created by the s390 code,
+ perhaps the pseries code should use a similar layout as well.
+
+ o Is reserving a 256MB region really required? The goal of
+ reserving a 256MB scratch area is to make sure that no
+ important crash data is clobbered when the hypervisor
+ save low mem to the scratch area. But, if one could assure
+ that nothing important is located in some 256MB area, then
+ it would not need to be reserved. Something that can be
+ improved in subsequent versions.
+
+ o Still working the kdump team to integrate this with kdump,
+ some work remains but this would not affect the current
+ patches.
+
+ o Still need to write a shell script, to copy the dump away.
+ Currently I am parsing it manually.
--- /dev/null
+/*
+ * Tests for prctl(PR_GET_TSC, ...) / prctl(PR_SET_TSC, ...)
+ *
+ * Tests if the control register is updated correctly
+ * at context switches
+ *
+ * Warning: this test will cause a very high load for a few seconds
+ *
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <signal.h>
+#include <inttypes.h>
+#include <wait.h>
+
+
+#include <sys/prctl.h>
+#include <linux/prctl.h>
+
+/* Get/set the process' ability to use the timestamp counter instruction */
+#ifndef PR_GET_TSC
+#define PR_GET_TSC 25
+#define PR_SET_TSC 26
+# define PR_TSC_ENABLE 1 /* allow the use of the timestamp counter */
+# define PR_TSC_SIGSEGV 2 /* throw a SIGSEGV instead of reading the TSC */
+#endif
+
+uint64_t rdtsc() {
+uint32_t lo, hi;
+/* We cannot use "=A", since this would use %rax on x86_64 */
+__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));
+return (uint64_t)hi << 32 | lo;
+}
+
+void sigsegv_expect(int sig)
+{
+ /* */
+}
+
+void segvtask(void)
+{
+ if (prctl(PR_SET_TSC, PR_TSC_SIGSEGV) < 0)
+ {
+ perror("prctl");
+ exit(0);
+ }
+ signal(SIGSEGV, sigsegv_expect);
+ alarm(10);
+ rdtsc();
+ fprintf(stderr, "FATAL ERROR, rdtsc() succeeded while disabled\n");
+ exit(0);
+}
+
+
+void sigsegv_fail(int sig)
+{
+ fprintf(stderr, "FATAL ERROR, rdtsc() failed while enabled\n");
+ exit(0);
+}
+
+void rdtsctask(void)
+{
+ if (prctl(PR_SET_TSC, PR_TSC_ENABLE) < 0)
+ {
+ perror("prctl");
+ exit(0);
+ }
+ signal(SIGSEGV, sigsegv_fail);
+ alarm(10);
+ for(;;) rdtsc();
+}
+
+
+int main(int argc, char **argv)
+{
+ int n_tasks = 100, i;
+
+ fprintf(stderr, "[No further output means we're allright]\n");
+
+ for (i=0; i<n_tasks; i++)
+ if (fork() == 0)
+ {
+ if (i & 1)
+ segvtask();
+ else
+ rdtsctask();
+ }
+
+ for (i=0; i<n_tasks; i++)
+ wait(NULL);
+
+ exit(0);
+}
+
--- /dev/null
+/*
+ * Tests for prctl(PR_GET_TSC, ...) / prctl(PR_SET_TSC, ...)
+ *
+ * Tests if the control register is updated correctly
+ * when set with prctl()
+ *
+ * Warning: this test will cause a very high load for a few seconds
+ *
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <signal.h>
+#include <inttypes.h>
+#include <wait.h>
+
+
+#include <sys/prctl.h>
+#include <linux/prctl.h>
+
+/* Get/set the process' ability to use the timestamp counter instruction */
+#ifndef PR_GET_TSC
+#define PR_GET_TSC 25
+#define PR_SET_TSC 26
+# define PR_TSC_ENABLE 1 /* allow the use of the timestamp counter */
+# define PR_TSC_SIGSEGV 2 /* throw a SIGSEGV instead of reading the TSC */
+#endif
+
+/* snippet from wikipedia :-) */
+
+uint64_t rdtsc() {
+uint32_t lo, hi;
+/* We cannot use "=A", since this would use %rax on x86_64 */
+__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));
+return (uint64_t)hi << 32 | lo;
+}
+
+int should_segv = 0;
+
+void sigsegv_cb(int sig)
+{
+ if (!should_segv)
+ {
+ fprintf(stderr, "FATAL ERROR, rdtsc() failed while enabled\n");
+ exit(0);
+ }
+ if (prctl(PR_SET_TSC, PR_TSC_ENABLE) < 0)
+ {
+ perror("prctl");
+ exit(0);
+ }
+ should_segv = 0;
+
+ rdtsc();
+}
+
+void task(void)
+{
+ signal(SIGSEGV, sigsegv_cb);
+ alarm(10);
+ for(;;)
+ {
+ rdtsc();
+ if (should_segv)
+ {
+ fprintf(stderr, "FATAL ERROR, rdtsc() succeeded while disabled\n");
+ exit(0);
+ }
+ if (prctl(PR_SET_TSC, PR_TSC_SIGSEGV) < 0)
+ {
+ perror("prctl");
+ exit(0);
+ }
+ should_segv = 1;
+ }
+}
+
+
+int main(int argc, char **argv)
+{
+ int n_tasks = 100, i;
+
+ fprintf(stderr, "[No further output means we're allright]\n");
+
+ for (i=0; i<n_tasks; i++)
+ if (fork() == 0)
+ task();
+
+ for (i=0; i<n_tasks; i++)
+ wait(NULL);
+
+ exit(0);
+}
+
--- /dev/null
+/*
+ * Tests for prctl(PR_GET_TSC, ...) / prctl(PR_SET_TSC, ...)
+ *
+ * Basic test to test behaviour of PR_GET_TSC and PR_SET_TSC
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <signal.h>
+#include <inttypes.h>
+
+
+#include <sys/prctl.h>
+#include <linux/prctl.h>
+
+/* Get/set the process' ability to use the timestamp counter instruction */
+#ifndef PR_GET_TSC
+#define PR_GET_TSC 25
+#define PR_SET_TSC 26
+# define PR_TSC_ENABLE 1 /* allow the use of the timestamp counter */
+# define PR_TSC_SIGSEGV 2 /* throw a SIGSEGV instead of reading the TSC */
+#endif
+
+const char *tsc_names[] =
+{
+ [0] = "[not set]",
+ [PR_TSC_ENABLE] = "PR_TSC_ENABLE",
+ [PR_TSC_SIGSEGV] = "PR_TSC_SIGSEGV",
+};
+
+uint64_t rdtsc() {
+uint32_t lo, hi;
+/* We cannot use "=A", since this would use %rax on x86_64 */
+__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));
+return (uint64_t)hi << 32 | lo;
+}
+
+void sigsegv_cb(int sig)
+{
+ int tsc_val = 0;
+
+ printf("[ SIG_SEGV ]\n");
+ printf("prctl(PR_GET_TSC, &tsc_val); ");
+ fflush(stdout);
+
+ if ( prctl(PR_GET_TSC, &tsc_val) == -1)
+ perror("prctl");
+
+ printf("tsc_val == %s\n", tsc_names[tsc_val]);
+ printf("prctl(PR_SET_TSC, PR_TSC_ENABLE)\n");
+ fflush(stdout);
+ if ( prctl(PR_SET_TSC, PR_TSC_ENABLE) == -1)
+ perror("prctl");
+
+ printf("rdtsc() == ");
+}
+
+int main(int argc, char **argv)
+{
+ int tsc_val = 0;
+
+ signal(SIGSEGV, sigsegv_cb);
+
+ printf("rdtsc() == %llu\n", (unsigned long long)rdtsc());
+ printf("prctl(PR_GET_TSC, &tsc_val); ");
+ fflush(stdout);
+
+ if ( prctl(PR_GET_TSC, &tsc_val) == -1)
+ perror("prctl");
+
+ printf("tsc_val == %s\n", tsc_names[tsc_val]);
+ printf("rdtsc() == %llu\n", (unsigned long long)rdtsc());
+ printf("prctl(PR_SET_TSC, PR_TSC_ENABLE)\n");
+ fflush(stdout);
+
+ if ( prctl(PR_SET_TSC, PR_TSC_ENABLE) == -1)
+ perror("prctl");
+
+ printf("rdtsc() == %llu\n", (unsigned long long)rdtsc());
+ printf("prctl(PR_SET_TSC, PR_TSC_SIGSEGV)\n");
+ fflush(stdout);
+
+ if ( prctl(PR_SET_TSC, PR_TSC_SIGSEGV) == -1)
+ perror("prctl");
+
+ printf("rdtsc() == ");
+ fflush(stdout);
+ printf("%llu\n", (unsigned long long)rdtsc());
+ fflush(stdout);
+
+ exit(EXIT_SUCCESS);
+}
+
+ Real-Time group scheduling
+ --------------------------
+CONTENTS
+========
-Real-Time group scheduling.
+1. Overview
+ 1.1 The problem
+ 1.2 The solution
+2. The interface
+ 2.1 System-wide settings
+ 2.2 Default behaviour
+ 2.3 Basis for grouping tasks
+3. Future plans
-The problem space:
-In order to schedule multiple groups of realtime tasks each group must
-be assigned a fixed portion of the CPU time available. Without a minimum
-guarantee a realtime group can obviously fall short. A fuzzy upper limit
-is of no use since it cannot be relied upon. Which leaves us with just
-the single fixed portion.
+1. Overview
+===========
-CPU time is divided by means of specifying how much time can be spent
-running in a given period. Say a frame fixed realtime renderer must
-deliver 25 frames a second, which yields a period of 0.04s. Now say
-it will also have to play some music and respond to input, leaving it
-with around 80% for the graphics. We can then give this group a runtime
-of 0.8 * 0.04s = 0.032s.
-This way the graphics group will have a 0.04s period with a 0.032s runtime
-limit.
+1.1 The problem
+---------------
-Now if the audio thread needs to refill the DMA buffer every 0.005s, but
-needs only about 3% CPU time to do so, it can do with a 0.03 * 0.005s
-= 0.00015s.
+Realtime scheduling is all about determinism, a group has to be able to rely on
+the amount of bandwidth (eg. CPU time) being constant. In order to schedule
+multiple groups of realtime tasks, each group must be assigned a fixed portion
+of the CPU time available. Without a minimum guarantee a realtime group can
+obviously fall short. A fuzzy upper limit is of no use since it cannot be
+relied upon. Which leaves us with just the single fixed portion.
+1.2 The solution
+----------------
-The Interface:
+CPU time is divided by means of specifying how much time can be spent running
+in a given period. We allocate this "run time" for each realtime group which
+the other realtime groups will not be permitted to use.
-system wide:
+Any time not allocated to a realtime group will be used to run normal priority
+tasks (SCHED_OTHER). Any allocated run time not used will also be picked up by
+SCHED_OTHER.
-/proc/sys/kernel/sched_rt_period_ms
-/proc/sys/kernel/sched_rt_runtime_us
+Let's consider an example: a frame fixed realtime renderer must deliver 25
+frames a second, which yields a period of 0.04s per frame. Now say it will also
+have to play some music and respond to input, leaving it with around 80% CPU
+time dedicated for the graphics. We can then give this group a run time of 0.8
+* 0.04s = 0.032s.
-CONFIG_FAIR_USER_SCHED
+This way the graphics group will have a 0.04s period with a 0.032s run time
+limit. Now if the audio thread needs to refill the DMA buffer every 0.005s, but
+needs only about 3% CPU time to do so, it can do with a 0.03 * 0.005s =
+0.00015s. So this group can be scheduled with a period of 0.005s and a run time
+of 0.00015s.
-/sys/kernel/uids/<uid>/cpu_rt_runtime_us
+The remaining CPU time will be used for user input and other tass. Because
+realtime tasks have explicitly allocated the CPU time they need to perform
+their tasks, buffer underruns in the graphocs or audio can be eliminated.
-or
+NOTE: the above example is not fully implemented as of yet (2.6.25). We still
+lack an EDF scheduler to make non-uniform periods usable.
-CONFIG_FAIR_CGROUP_SCHED
-/cgroup/<cgroup>/cpu.rt_runtime_us
+2. The Interface
+================
-[ time is specified in us because the interface is s32; this gives an
- operating range of ~35m to 1us ]
-The period takes values in [ 1, INT_MAX ], runtime in [ -1, INT_MAX - 1 ].
+2.1 System wide settings
+------------------------
-A runtime of -1 specifies runtime == period, ie. no limit.
+The system wide settings are configured under the /proc virtual file system:
-New groups get the period from /proc/sys/kernel/sched_rt_period_us and
-a runtime of 0.
+/proc/sys/kernel/sched_rt_period_us:
+ The scheduling period that is equivalent to 100% CPU bandwidth
-Settings are constrained to:
+/proc/sys/kernel/sched_rt_runtime_us:
+ A global limit on how much time realtime scheduling may use. Even without
+ CONFIG_RT_GROUP_SCHED enabled, this will limit time reserved to realtime
+ processes. With CONFIG_RT_GROUP_SCHED it signifies the total bandwidth
+ available to all realtime groups.
+
+ * Time is specified in us because the interface is s32. This gives an
+ operating range from 1us to about 35 minutes.
+ * sched_rt_period_us takes values from 1 to INT_MAX.
+ * sched_rt_runtime_us takes values from -1 to (INT_MAX - 1).
+ * A run time of -1 specifies runtime == period, ie. no limit.
+
+
+2.2 Default behaviour
+---------------------
+
+The default values for sched_rt_period_us (1000000 or 1s) and
+sched_rt_runtime_us (950000 or 0.95s). This gives 0.05s to be used by
+SCHED_OTHER (non-RT tasks). These defaults were chosen so that a run-away
+realtime tasks will not lock up the machine but leave a little time to recover
+it. By setting runtime to -1 you'd get the old behaviour back.
+
+By default all bandwidth is assigned to the root group and new groups get the
+period from /proc/sys/kernel/sched_rt_period_us and a run time of 0. If you
+want to assign bandwidth to another group, reduce the root group's bandwidth
+and assign some or all of the difference to another group.
+
+Realtime group scheduling means you have to assign a portion of total CPU
+bandwidth to the group before it will accept realtime tasks. Therefore you will
+not be able to run realtime tasks as any user other than root until you have
+done that, even if the user has the rights to run processes with realtime
+priority!
+
+
+2.3 Basis for grouping tasks
+----------------------------
+
+There are two compile-time settings for allocating CPU bandwidth. These are
+configured using the "Basis for grouping tasks" multiple choice menu under
+General setup > Group CPU Scheduler:
+
+a. CONFIG_USER_SCHED (aka "Basis for grouping tasks" = "user id")
+
+This lets you use the virtual files under
+"/sys/kernel/uids/<uid>/cpu_rt_runtime_us" to control he CPU time reserved for
+each user .
+
+The other option is:
+
+.o CONFIG_CGROUP_SCHED (aka "Basis for grouping tasks" = "Control groups")
+
+This uses the /cgroup virtual file system and "/cgroup/<cgroup>/cpu.rt_runtime_us"
+to control the CPU time reserved for each control group instead.
+
+For more information on working with control groups, you should read
+Documentation/cgroups.txt as well.
+
+Group settings are checked against the following limits in order to keep the configuration
+schedulable:
\Sum_{i} runtime_{i} / global_period <= global_runtime / global_period
-in order to keep the configuration schedulable.
+For now, this can be simplified to just the following (but see Future plans):
+
+ \Sum_{i} runtime_{i} <= global_runtime
+
+
+3. Future plans
+===============
+
+There is work in progress to make the scheduling period for each group
+("/sys/kernel/uids/<uid>/cpu_rt_period_us" or
+"/cgroup/<cgroup>/cpu.rt_period_us" respectively) configurable as well.
+
+The constraint on the period is that a subgroup must have a smaller or
+equal period to its parent. But realistically its not very useful _yet_
+as its prone to starvation without deadline scheduling.
+
+Consider two sibling groups A and B; both have 50% bandwidth, but A's
+period is twice the length of B's.
+
+* group A: period=100000us, runtime=10000us
+ - this runs for 0.01s once every 0.1s
+
+* group B: period= 50000us, runtime=10000us
+ - this runs for 0.01s twice every 0.1s (or once every 0.05 sec).
+
+This means that currently a while (1) loop in A will run for the full period of
+B and can starve B's tasks (assuming they are of lower priority) for a whole
+period.
+
+The next project will be SCHED_EDF (Earliest Deadline First scheduling) to bring
+full deadline scheduling to the linux kernel. Deadline scheduling the above
+groups and treating end of the period as a deadline will ensure that they both
+get their allocated time.
+
+Implementing SCHED_EDF might take a while to complete. Priority Inheritance is
+the biggest challenge as the current linux PI infrastructure is geared towards
+the limited static priority levels 0-139. With deadline scheduling you need to
+do deadline inheritance (since priority is inversely proportional to the
+deadline delta (deadline - now).
+
+This means the whole PI machinery will have to be reworked - and that is one of
+the most complex pieces of code we have.
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
+ARM/GUMSTIX MACHINE SUPPORT
+P: Steve Sakoman
+M: sakoman@gmail.com
+L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
+S: Maintained
+
ARM/HP JORNADA 7XX MACHINE SUPPORT
P: Kristoffer Ericson
M: kristoffer.ericson@gmail.com
L: ath5k-devel@lists.ath5k.org
S: Maintained
+ATI_REMOTE2 DRIVER
+P: Ville Syrjala
+M: syrjala@sci.fi
+S: Maintained
+
ATL1 ETHERNET DRIVER
P: Jay Cliburn
M: jcliburn@gmail.com
M: mfasheh@suse.com
P: Joel Becker
M: joel.becker@oracle.com
-L: ocfs2-devel@oss.oracle.com
+L: ocfs2-devel@oss.oracle.com (moderated for non-subscribers)
W: http://oss.oracle.com/projects/ocfs2/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mfasheh/ocfs2.git
S: Supported
S: Supported
PCI SUBSYSTEM
-P: Greg Kroah-Hartman
-M: gregkh@suse.de
+P: Jesse Barnes
+M: jbarnes@virtuousgeek.org
L: linux-kernel@vger.kernel.org
L: linux-pci@atrey.karlin.mff.cuni.cz
-T: quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
S: Supported
PCI HOTPLUG CORE
L: lm-sensors@lm-sensors.org
S: Maintained
+SMX UIO Interface
+P: Ben Nizette
+M: bn@niasdigital.com
+S: Maintained
+
SOFTWARE RAID (Multiple Disks) SUPPORT
P: Ingo Molnar
M: mingo@redhat.com
quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files)))
cmd_rmfiles = rm -f $(rm-files)
-# Run depmod only is we have System.map and depmod is executable
+# Run depmod only if we have System.map and depmod is executable
# and we build for the host arch
quiet_cmd_depmod = DEPMOD $(KERNELRELEASE)
cmd_depmod = \
int
pcibios_enable_device(struct pci_dev *dev, int mask)
{
- u16 cmd, oldcmd;
- int i;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- oldcmd = cmd;
-
- for (i = 0; i < PCI_NUM_RESOURCES; i++) {
- struct resource *res = &dev->resource[i];
-
- if (res->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- else if (res->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
-
- if (cmd != oldcmd) {
- printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
- pci_name(dev), cmd);
- /* Enable the appropriate bits in the PCI command register. */
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
+ return pci_enable_resources(dev, mask);
}
/*
select ARM_AMBA
select ARM_VIC
select GENERIC_GPIO
+ select HAVE_GPIO_LIB
help
This enables support for the Cirrus EP93xx series of CPUs.
help
Support for Freescale MXC/iMX-based family of processors
-config ARCH_ORION
+config ARCH_ORION5X
bool "Marvell Orion"
depends on MMU
select PCI
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
+ select PLAT_ORION
help
- Support for Marvell Orion System on Chip family.
+ Support for the following Marvell Orion 5x series SoCs:
+ Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.)
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
bool "SA1100-based"
select ISA
select ARCH_DISCONTIGMEM_ENABLE
+ select ARCH_SPARSEMEM_ENABLE
+ select ARCH_SELECT_MEMORY_MODEL
select ARCH_MTD_XIP
select GENERIC_GPIO
select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select TICK_ONESHOT
select HAVE_IDE
+ select HAVE_GPIO_LIB
help
Support for StrongARM 11x0 based boards.
config ARCH_OMAP
bool "TI OMAP"
select GENERIC_GPIO
+ select HAVE_GPIO_LIB
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
source "arch/arm/mach-omap2/Kconfig"
-source "arch/arm/mach-orion/Kconfig"
+source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig"
config PLAT_IOP
bool
+config PLAT_ORION
+ bool
+
source arch/arm/mm/Kconfig
config IWMMXT
config SMP
bool "Symmetric Multi-Processing (EXPERIMENTAL)"
- depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP
+ depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
help
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
config LOCAL_TIMERS
bool "Use local timer interrupts"
- depends on SMP && REALVIEW_EB_ARM11MP
+ depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
default y
help
Enable support for local timers on SMP platforms, rather then the
or have huge holes in the physical address space for other reasons.
See <file:Documentation/vm/numa> for more.
+config ARCH_SPARSEMEM_ENABLE
+ bool
+
+config ARCH_SELECT_MEMORY_MODEL
+ bool
+
config NODES_SHIFT
int
default "4" if ARCH_LH7A40X
source "drivers/dca/Kconfig"
+source "drivers/uio/Kconfig"
+
endmenu
source "fs/Kconfig"
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
- textofs-$(CONFIG_ARCH_NS9XXX) := 0x00108000
machine-$(CONFIG_ARCH_DAVINCI) := davinci
machine-$(CONFIG_ARCH_KS8695) := ks8695
incdir-$(CONFIG_ARCH_MXC) := mxc
machine-$(CONFIG_ARCH_MX3) := mx3
- machine-$(CONFIG_ARCH_ORION) := orion
+ machine-$(CONFIG_ARCH_ORION5X) := orion5x
machine-$(CONFIG_ARCH_MSM7X00A) := msm
ifeq ($(CONFIG_ARCH_EBSA110),y)
# If we have a common platform directory, then include it in the build.
core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/
+core-$(CONFIG_PLAT_ORION) += arch/arm/plat-orion/
core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/
core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/
core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/
quiet_cmd_uimage = UIMAGE $@
cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
- -C none -a $(ZRELADDR) -e $(ZRELADDR) \
+ -C none -a $(LOADADDR) -e $(LOADADDR) \
-n 'Linux-$(KERNELRELEASE)' -d $< $@
+ifeq ($(CONFIG_ZBOOT_ROM),y)
+$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
+else
+$(obj)/uImage: LOADADDR=$(ZRELADDR)
+endif
+
$(obj)/uImage: $(obj)/zImage FORCE
$(call if_changed,uimage)
@echo ' Image $@ is ready'
#include <linux/mutex.h>
#include <asm/rtc.h>
-#include <asm/semaphore.h>
static DECLARE_WAIT_QUEUE_HEAD(rtc_wait);
static struct fasync_struct *rtc_async_queue;
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/hardware/scoop.h>
/* PCMCIA to Scoop linkage
struct scoop_pcmcia_config *platform_scoop_config;
EXPORT_SYMBOL(platform_scoop_config);
-#define SCOOP_REG(d,adr) (*(volatile unsigned short*)(d +(adr)))
-
struct scoop_dev {
- void *base;
+ void __iomem *base;
+ struct gpio_chip gpio;
spinlock_t scoop_lock;
unsigned short suspend_clr;
unsigned short suspend_set;
{
struct scoop_dev *sdev = dev_get_drvdata(dev);
- SCOOP_REG(sdev->base,SCOOP_MCR) = 0x0100; // 00
- SCOOP_REG(sdev->base,SCOOP_CDR) = 0x0000; // 04
- SCOOP_REG(sdev->base,SCOOP_CCR) = 0x0000; // 10
- SCOOP_REG(sdev->base,SCOOP_IMR) = 0x0000; // 18
- SCOOP_REG(sdev->base,SCOOP_IRM) = 0x00FF; // 14
- SCOOP_REG(sdev->base,SCOOP_ISR) = 0x0000; // 1C
- SCOOP_REG(sdev->base,SCOOP_IRM) = 0x0000;
+ iowrite16(0x0100, sdev->base + SCOOP_MCR); // 00
+ iowrite16(0x0000, sdev->base + SCOOP_CDR); // 04
+ iowrite16(0x0000, sdev->base + SCOOP_CCR); // 10
+ iowrite16(0x0000, sdev->base + SCOOP_IMR); // 18
+ iowrite16(0x00FF, sdev->base + SCOOP_IRM); // 14
+ iowrite16(0x0000, sdev->base + SCOOP_ISR); // 1C
+ iowrite16(0x0000, sdev->base + SCOOP_IRM);
+}
+
+static void __scoop_gpio_set(struct scoop_dev *sdev,
+ unsigned offset, int value)
+{
+ unsigned short gpwr;
+
+ gpwr = ioread16(sdev->base + SCOOP_GPWR);
+ if (value)
+ gpwr |= 1 << (offset + 1);
+ else
+ gpwr &= ~(1 << (offset + 1));
+ iowrite16(gpwr, sdev->base + SCOOP_GPWR);
+}
+
+static void scoop_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+ unsigned long flags;
+
+ spin_lock_irqsave(&sdev->scoop_lock, flags);
+
+ __scoop_gpio_set(sdev, offset, value);
+
+ spin_unlock_irqrestore(&sdev->scoop_lock, flags);
+}
+
+static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+
+ /* XXX: I'm usure, but it seems so */
+ return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1));
+}
+
+static int scoop_gpio_direction_input(struct gpio_chip *chip,
+ unsigned offset)
+{
+ struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+ unsigned long flags;
+ unsigned short gpcr;
+
+ spin_lock_irqsave(&sdev->scoop_lock, flags);
+
+ gpcr = ioread16(sdev->base + SCOOP_GPCR);
+ gpcr &= ~(1 << (offset + 1));
+ iowrite16(gpcr, sdev->base + SCOOP_GPCR);
+
+ spin_unlock_irqrestore(&sdev->scoop_lock, flags);
+
+ return 0;
+}
+
+static int scoop_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+ unsigned long flags;
+ unsigned short gpcr;
+
+ spin_lock_irqsave(&sdev->scoop_lock, flags);
+
+ __scoop_gpio_set(sdev, offset, value);
+
+ gpcr = ioread16(sdev->base + SCOOP_GPCR);
+ gpcr |= 1 << (offset + 1);
+ iowrite16(gpcr, sdev->base + SCOOP_GPCR);
+
+ spin_unlock_irqrestore(&sdev->scoop_lock, flags);
+
+ return 0;
}
unsigned short set_scoop_gpio(struct device *dev, unsigned short bit)
struct scoop_dev *sdev = dev_get_drvdata(dev);
spin_lock_irqsave(&sdev->scoop_lock, flag);
- gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) | bit;
- SCOOP_REG(sdev->base, SCOOP_GPWR) = gpio_bit;
+ gpio_bit = ioread16(sdev->base + SCOOP_GPWR) | bit;
+ iowrite16(gpio_bit, sdev->base + SCOOP_GPWR);
spin_unlock_irqrestore(&sdev->scoop_lock, flag);
return gpio_bit;
struct scoop_dev *sdev = dev_get_drvdata(dev);
spin_lock_irqsave(&sdev->scoop_lock, flag);
- gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) & ~bit;
- SCOOP_REG(sdev->base,SCOOP_GPWR) = gpio_bit;
+ gpio_bit = ioread16(sdev->base + SCOOP_GPWR) & ~bit;
+ iowrite16(gpio_bit, sdev->base + SCOOP_GPWR);
spin_unlock_irqrestore(&sdev->scoop_lock, flag);
return gpio_bit;
unsigned short read_scoop_reg(struct device *dev, unsigned short reg)
{
struct scoop_dev *sdev = dev_get_drvdata(dev);
- return SCOOP_REG(sdev->base,reg);
+ return ioread16(sdev->base + reg);
}
void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data)
{
struct scoop_dev *sdev = dev_get_drvdata(dev);
- SCOOP_REG(sdev->base,reg)=data;
+ iowrite16(data, sdev->base + reg);
}
EXPORT_SYMBOL(reset_scoop);
{
unsigned short mcr;
- mcr = SCOOP_REG(sdev->base, SCOOP_MCR);
+ mcr = ioread16(sdev->base + SCOOP_MCR);
if ((mcr & 0x100) == 0)
- SCOOP_REG(sdev->base, SCOOP_MCR) = 0x0101;
+ iowrite16(0x0101, sdev->base + SCOOP_MCR);
}
#ifdef CONFIG_PM
struct scoop_dev *sdev = platform_get_drvdata(dev);
check_scoop_reg(sdev);
- sdev->scoop_gpwr = SCOOP_REG(sdev->base, SCOOP_GPWR);
- SCOOP_REG(sdev->base, SCOOP_GPWR) = (sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set;
+ sdev->scoop_gpwr = ioread16(sdev->base + SCOOP_GPWR);
+ iowrite16((sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set, sdev->base + SCOOP_GPWR);
return 0;
}
struct scoop_dev *sdev = platform_get_drvdata(dev);
check_scoop_reg(sdev);
- SCOOP_REG(sdev->base,SCOOP_GPWR) = sdev->scoop_gpwr;
+ iowrite16(sdev->scoop_gpwr, sdev->base + SCOOP_GPWR);
return 0;
}
#define scoop_resume NULL
#endif
-int __init scoop_probe(struct platform_device *pdev)
+static int __devinit scoop_probe(struct platform_device *pdev)
{
struct scoop_dev *devptr;
struct scoop_config *inf;
struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ int ret;
+ int temp;
if (!mem)
return -EINVAL;
devptr->base = ioremap(mem->start, mem->end - mem->start + 1);
if (!devptr->base) {
- kfree(devptr);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto err_ioremap;
}
platform_set_drvdata(pdev, devptr);
- printk("Sharp Scoop Device found at 0x%08x -> 0x%08x\n",(unsigned int)mem->start,(unsigned int)devptr->base);
+ printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base);
- SCOOP_REG(devptr->base, SCOOP_MCR) = 0x0140;
+ iowrite16(0x0140, devptr->base + SCOOP_MCR);
reset_scoop(&pdev->dev);
- SCOOP_REG(devptr->base, SCOOP_CPR) = 0x0000;
- SCOOP_REG(devptr->base, SCOOP_GPCR) = inf->io_dir & 0xffff;
- SCOOP_REG(devptr->base, SCOOP_GPWR) = inf->io_out & 0xffff;
+ iowrite16(0x0000, devptr->base + SCOOP_CPR);
+ iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR);
+ iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR);
devptr->suspend_clr = inf->suspend_clr;
devptr->suspend_set = inf->suspend_set;
+ devptr->gpio.base = -1;
+
+ if (inf->gpio_base != 0) {
+ devptr->gpio.label = pdev->dev.bus_id;
+ devptr->gpio.base = inf->gpio_base;
+ devptr->gpio.ngpio = 12; /* PA11 = 0, PA12 = 1, etc. up to PA22 = 11 */
+ devptr->gpio.set = scoop_gpio_set;
+ devptr->gpio.get = scoop_gpio_get;
+ devptr->gpio.direction_input = scoop_gpio_direction_input;
+ devptr->gpio.direction_output = scoop_gpio_direction_output;
+
+ ret = gpiochip_add(&devptr->gpio);
+ if (ret)
+ goto err_gpio;
+ }
+
return 0;
+
+ if (devptr->gpio.base != -1)
+ temp = gpiochip_remove(&devptr->gpio);
+err_gpio:
+ platform_set_drvdata(pdev, NULL);
+err_ioremap:
+ iounmap(devptr->base);
+ kfree(devptr);
+
+ return ret;
}
-static int scoop_remove(struct platform_device *pdev)
+static int __devexit scoop_remove(struct platform_device *pdev)
{
struct scoop_dev *sdev = platform_get_drvdata(pdev);
- if (sdev) {
- iounmap(sdev->base);
- kfree(sdev);
- platform_set_drvdata(pdev, NULL);
+ int ret;
+
+ if (!sdev)
+ return -EINVAL;
+
+ if (sdev->gpio.base != -1) {
+ ret = gpiochip_remove(&sdev->gpio);
+ if (ret) {
+ dev_err(&pdev->dev, "Can't remove gpio chip: %d\n", ret);
+ return ret;
+ }
}
+
+ platform_set_drvdata(pdev, NULL);
+ iounmap(sdev->base);
+ kfree(sdev);
+
return 0;
}
static struct platform_driver scoop_driver = {
.probe = scoop_probe,
- .remove = scoop_remove,
+ .remove = __devexit_p(scoop_remove),
.suspend = scoop_suspend,
.resume = scoop_resume,
.driver = {
},
};
-int __init scoop_init(void)
+static int __init scoop_init(void)
{
return platform_driver_register(&scoop_driver);
}
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc3
+# Sun Mar 9 06:33:33 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="gum"
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+# CONFIG_EPOLL is not set
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+CONFIG_ARCH_GUMSTIX=y
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
+CONFIG_MACH_GUMSTIX_F=y
+CONFIG_PXA25x=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+# CONFIG_IWMMXT is not set
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+# CONFIG_PCMCIA_IOCTL is not set
+
+#
+# PC-card bridges
+#
+CONFIG_PCMCIA_PXA2XX=y
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f01 rootfstype=jffs2"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+# CONFIG_BT_HIDP is not set
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_LL is not set
+# CONFIG_BT_HCIDTL1 is not set
+# CONFIG_BT_HCIBT3C is not set
+# CONFIG_BT_HCIBLUECARD is not set
+# CONFIG_BT_HCIBTUART is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_IEEE80211_SOFTMAC is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=m
+CONFIG_IDE_MAX_HWIFS=2
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=m
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+CONFIG_IDE_ARCH_OBSOLETE_INIT=y
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=m
+# CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+# CONFIG_DEBUG_GPIO is not set
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_SA1100_WATCHDOG=m
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+CONFIG_FB_PXA_PARAMETERS=y
+CONFIG_FB_MBX=m
+CONFIG_FB_VIRTUAL=m
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=m
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA ARM devices
+#
+CONFIG_SND_PXA2XX_PCM=m
+CONFIG_SND_PXA2XX_AC97=m
+
+#
+# PCMCIA devices
+#
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+
+#
+# System on Chip audio support
+#
+# CONFIG_SND_SOC is not set
+
+#
+# SoC Audio support for SuperH
+#
+
+#
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+CONFIG_USB_GADGET_PXA2XX=y
+CONFIG_USB_PXA2XX=y
+# CONFIG_USB_PXA2XX_SMALL is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
#
# I2C Algorithms
#
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_PCA_ISA is not set
#
# I2C Algorithms
#
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_PCA_ISA is not set
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.19-rc6
-# Fri Nov 17 18:42:21 2006
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan 8 22:20:50 2008
#
CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
-# Code maturity level options
+# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
CONFIG_SHMEM=y
-CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
-
-#
-# Block layer
-#
CONFIG_BLOCK=y
+# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
#
# Atmel AT91 System-on-Chip
#
# CONFIG_ARCH_AT91RM9200 is not set
CONFIG_ARCH_AT91SAM9260=y
# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
#
-# AT91SAM9260 Board Type
+# AT91SAM9260 / AT91SAM9XE Board Type
#
CONFIG_MACH_AT91SAM9260EK=y
+# CONFIG_MACH_CAM60 is not set
+# CONFIG_MACH_SAM9_L9260 is not set
#
# AT91 Board Options
#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
#
# AT91 Feature Selections
#
-# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
#
# Processor Type
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
#
# Bus support
#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
+# CONFIG_TICK_ONESHOT is not set
# CONFIG_PREEMPT is not set
# CONFIG_NO_IDLE_HZ is not set
CONFIG_HZ=100
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
#
# Floating point emulation
# Power management options
#
# CONFIG_PM is not set
-# CONFIG_APM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
#
# Networking
#
# Networking options
#
-# CONFIG_NETDEBUG is not set
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
# CONFIG_NET_SCHED is not set
#
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
#
# Device Drivers
#
# Generic Driver Options
#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_ATA is not set
# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
+# USB Network Adapters
#
-# CONFIG_NETDEVICES is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
# CONFIG_ISDN is not set
#
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
#
-# Ftape, the floppy tape device driver
+# I2C Algorithms
#
-# CONFIG_RAW_DRIVER is not set
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
#
-# TPM devices
+# I2C Hardware Bus support
#
-# CONFIG_TCG_TPM is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
#
-# I2C support
+# Miscellaneous I2C Chip support
#
-# CONFIG_I2C is not set
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
#
-# Misc devices
+# Watchdog Device Drivers
#
-# CONFIG_TIFM_CORE is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
#
-# LED devices
+# USB-based Watchdog Cards
#
-# CONFIG_NEW_LEDS is not set
+# CONFIG_USBPCWATCHDOG is not set
#
-# LED drivers
+# Sonics Silicon Backplane
#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
#
-# LED Triggers
+# Multifunction device drivers
#
+# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
#
-# Digital Video Broadcasting Devices
+# Graphics support
#
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
-# Graphics support
+# Display device support
#
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
+# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
#
# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
#
-# USB support
+# USB Input Devices
#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
#
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
CONFIG_USB_STORAGE_DEBUG=y
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_LIBUSUAL is not set
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
CONFIG_USB_MON=y
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
#
# USB Gadget Support
#
CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
CONFIG_USB_GADGET_AT91=y
CONFIG_USB_AT91=y
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_FILE_STORAGE_TEST is not set
CONFIG_USB_G_SERIAL=m
# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
#
-# MMC/SD Card support
+# RTC interfaces
#
-# CONFIG_MMC is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
#
-# Real Time Clock
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
#
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
#
# File systems
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
# CONFIG_NFS_FS is not set
# CONFIG_NFSD is not set
# CONFIG_SMB_FS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
+# CONFIG_DLM is not set
+CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
-# CONFIG_HEADERS_CHECK is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_ERRORS is not set
CONFIG_DEBUG_LL=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
+CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.19-rc6
-# Fri Nov 17 18:00:38 2006
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan 8 22:21:49 2008
#
CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
-# Code maturity level options
+# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
CONFIG_SHMEM=y
-CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
-
-#
-# Block layer
-#
CONFIG_BLOCK=y
+# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
#
# Atmel AT91 System-on-Chip
#
# CONFIG_ARCH_AT91RM9200 is not set
# CONFIG_ARCH_AT91SAM9260 is not set
CONFIG_ARCH_AT91SAM9261=y
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
#
# AT91SAM9261 Board Type
#
# AT91 Board Options
#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
#
# AT91 Feature Selections
#
-# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
#
# Processor Type
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
#
# Bus support
#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
+# CONFIG_TICK_ONESHOT is not set
# CONFIG_PREEMPT is not set
# CONFIG_NO_IDLE_HZ is not set
CONFIG_HZ=100
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
#
# Floating point emulation
# Power management options
#
# CONFIG_PM is not set
-# CONFIG_APM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
#
# Networking
#
# Networking options
#
-# CONFIG_NETDEBUG is not set
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
# CONFIG_NET_SCHED is not set
#
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
#
# Device Drivers
#
# Generic Driver Options
#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
# User Modules And Translation Layers
#
# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
#
# Mapping drivers for chip access
#
# Self-contained MTD device drivers
#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
CONFIG_MTD_NAND_AT91=y
# CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
# CONFIG_MTD_ONENAND is not set
#
-# Parallel port support
+# UBI - Unsorted block images
#
+# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_ATA is not set
# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
+# CONFIG_AX88796 is not set
# CONFIG_SMC91X is not set
CONFIG_DM9000=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
+# Wireless LAN
#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# USB Network Adapters
#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
# CONFIG_ISDN is not set
#
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
-# CONFIG_SERIO is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
#
# I2C Algorithms
#
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
# CONFIG_I2C_PCA is not set
-# CONFIG_I2C_PCA_ISA is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_SENSORS_DS1337 is not set
# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
#
# SPI support
#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
#
-# Dallas's 1-wire bus
+# SPI Master Controller Drivers
#
-# CONFIG_W1 is not set
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
#
-# Hardware Monitoring support
+# SPI Protocol Masters
#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
#
-# Misc devices
+# Watchdog Device Drivers
#
-# CONFIG_TIFM_CORE is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
#
-# LED devices
+# USB-based Watchdog Cards
#
-# CONFIG_NEW_LEDS is not set
+# CONFIG_USBPCWATCHDOG is not set
#
-# LED drivers
+# Sonics Silicon Backplane
#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
#
-# LED Triggers
+# Multifunction device drivers
#
+# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
# CONFIG_USB_DABUSB is not set
#
# Graphics support
#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D15605 is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_ATMEL=y
+# CONFIG_FB_INTSRAM is not set
+# CONFIG_FB_ATMEL_STN is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
#
# Sound
#
# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
#
-# USB support
+# USB Input Devices
#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
#
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
CONFIG_USB_STORAGE_DEBUG=y
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_LIBUSUAL is not set
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
CONFIG_USB_MON=y
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
#
# USB Gadget Support
#
CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
CONFIG_USB_GADGET_AT91=y
CONFIG_USB_AT91=y
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_FILE_STORAGE_TEST is not set
CONFIG_USB_G_SERIAL=m
# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
#
-# MMC/SD Card support
+# MMC/SD Card Drivers
#
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91=m
-# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
#
-# Real Time Clock
+# MMC/SD Host Controller Drivers
#
+CONFIG_MMC_AT91=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
#
# File systems
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
# CONFIG_NFS_FS is not set
# CONFIG_NFSD is not set
# CONFIG_SMB_FS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
+# CONFIG_DLM is not set
+CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
-# CONFIG_HEADERS_CHECK is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_ERRORS is not set
CONFIG_DEBUG_LL=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
+CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20-rc1
-# Mon Jan 8 16:06:54 2007
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan 8 22:12:20 2008
#
CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
-# Code maturity level options
+# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
CONFIG_SHMEM=y
-CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
-
-#
-# Block layer
-#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
#
# Atmel AT91 System-on-Chip
#
# CONFIG_ARCH_AT91SAM9260 is not set
# CONFIG_ARCH_AT91SAM9261 is not set
CONFIG_ARCH_AT91SAM9263=y
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
#
# AT91SAM9263 Board Type
# AT91 Feature Selections
#
# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
#
# Processor Type
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
#
# Bus support
#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
+# CONFIG_TICK_ONESHOT is not set
# CONFIG_PREEMPT is not set
# CONFIG_NO_IDLE_HZ is not set
CONFIG_HZ=100
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
#
# Floating point emulation
# Power management options
#
# CONFIG_PM is not set
-# CONFIG_APM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
#
# Networking
#
# Networking options
#
-# CONFIG_NETDEBUG is not set
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
# CONFIG_NET_SCHED is not set
#
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
#
# Device Drivers
#
# Generic Driver Options
#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
#
# Mapping drivers for chip access
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
CONFIG_MTD_NAND_AT91=y
# CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
# CONFIG_MTD_ONENAND is not set
#
-# Parallel port support
+# UBI - Unsorted block images
#
+# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_SCSI_DEBUG is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
+# Wireless LAN
#
-# CONFIG_NET_RADIO is not set
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
#
-# Wan interfaces
+# USB Network Adapters
#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
# CONFIG_ISDN is not set
#
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_TSDEV=y
-CONFIG_INPUT_TSDEV_SCREEN_X=240
-CONFIG_INPUT_TSDEV_SCREEN_Y=320
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_INPUT_MISC is not set
#
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
#
# I2C Algorithms
#
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
# CONFIG_I2C_PCA is not set
-# CONFIG_I2C_PCA_ISA is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_SENSORS_DS1337 is not set
# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
#
# SPI Protocol Masters
#
-
-#
-# Dallas's 1-wire bus
-#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
#
-# Misc devices
+# Watchdog Device Drivers
#
-# CONFIG_TIFM_CORE is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
#
-# LED devices
+# USB-based Watchdog Cards
#
-# CONFIG_NEW_LEDS is not set
+# CONFIG_USBPCWATCHDOG is not set
#
-# LED drivers
+# Sonics Silicon Backplane
#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
#
-# LED Triggers
+# Multifunction device drivers
#
+# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
#
# Graphics support
#
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D15605 is not set
# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_ATMEL=y
# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE is not set
-
-#
-# Logo configuration
-#
# CONFIG_LOGO is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
#
# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
#
-# HID Devices
+# USB Input Devices
#
-CONFIG_HID=y
+# CONFIG_USB_HID is not set
#
-# USB support
+# USB HID Boot Protocol drivers
#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_MULTITHREAD_PROBE is not set
# CONFIG_USB_OTG is not set
#
#
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_LIBUSUAL is not set
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
CONFIG_USB_MON=y
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
#
# USB Gadget Support
#
CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
CONFIG_USB_GADGET_AT91=y
CONFIG_USB_AT91=y
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_FILE_STORAGE_TEST is not set
CONFIG_USB_G_SERIAL=m
# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
#
-# MMC/SD Card support
+# MMC/SD Card Drivers
#
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91=m
-# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
#
-# Real Time Clock
+# MMC/SD Host Controller Drivers
#
+CONFIG_MMC_AT91=m
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
#
# File systems
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_CRAMFS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
CONFIG_LOCKD=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
# CONFIG_DLM is not set
-
-#
-# Profiling support
-#
+CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_ERRORS is not set
CONFIG_DEBUG_LL=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
-CONFIG_IOMAP_COPY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21
-# Mon May 7 16:30:40 2007
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan 8 22:24:14 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
-# Code maturity level options
+# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
CONFIG_SHMEM=y
-CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
-
-#
-# Block layer
-#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
#
# Atmel AT91 System-on-Chip
#
# CONFIG_ARCH_AT91SAM9261 is not set
# CONFIG_ARCH_AT91SAM9263 is not set
CONFIG_ARCH_AT91SAM9RL=y
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
#
# AT91SAM9RL Board Type
#
# AT91 Feature Selections
#
-# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
#
# Processor Type
#
# Bus support
#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
+# CONFIG_TICK_ONESHOT is not set
# CONFIG_PREEMPT is not set
# CONFIG_NO_IDLE_HZ is not set
CONFIG_HZ=100
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
# Power management options
#
# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
#
# Networking
#
# Networking options
#
-# CONFIG_NETDEBUG is not set
# CONFIG_PACKET is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
# CONFIG_NET_SCHED is not set
#
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
#
# Device Drivers
#
# Generic Driver Options
#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_CONCAT=y
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
#
# Mapping drivers for chip access
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
CONFIG_MTD_NAND_AT91=y
# CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_ONENAND is not set
#
-# Parallel port support
+# UBI - Unsorted block images
#
+# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
# CONFIG_SCSI_DEBUG is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
# CONFIG_NETDEVICES is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
# CONFIG_ISDN is not set
#
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_INPUT_MISC is not set
#
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
#
-# TPM devices
+# I2C Algorithms
#
-# CONFIG_TCG_TPM is not set
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
#
-# I2C support
+# I2C Hardware Bus support
#
-# CONFIG_I2C is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
#
# SPI support
# SPI Protocol Masters
#
# CONFIG_SPI_AT25 is not set
-
-#
-# Dallas's 1-wire bus
-#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
#
-# Hardware Monitoring support
+# Watchdog Device Drivers
#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
#
-# Misc devices
+# Sonics Silicon Backplane
#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
+# CONFIG_DAB is not set
#
# Graphics support
#
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
#
# Frame buffer hardware drivers
#
+# CONFIG_FB_S1D15605 is not set
# CONFIG_FB_S1D13XXX is not set
CONFIG_FB_ATMEL=y
# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE is not set
-
-#
-# Logo configuration
-#
# CONFIG_LOGO is not set
#
# Sound
#
-CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_SEQ_DUMMY=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SND_DEBUG=y
-CONFIG_SND_DEBUG_DETECT=y
-# CONFIG_SND_PCM_XRUN_DEBUG is not set
-
-#
-# Generic devices
-#
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_VIRMIDI is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
#
-# ALSA ARM devices
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
-# SoC audio support
+# USB Gadget Support
#
-# CONFIG_SND_SOC is not set
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
#
-# Open Sound System
+# MMC/SD Card Drivers
#
-# CONFIG_SOUND_PRIME is not set
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
#
-# HID Devices
+# MMC/SD Host Controller Drivers
#
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+CONFIG_MMC_AT91=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
#
-# USB support
+# RTC interfaces
#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# I2C RTC drivers
#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
#
-# USB Gadget Support
+# SPI RTC drivers
#
-# CONFIG_USB_GADGET is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
#
-# MMC/SD Card support
+# Platform RTC drivers
#
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91=y
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
#
-# Real Time Clock
+# on-CPU RTC drivers
#
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_DRV_AT91SAM9=y
#
# File systems
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=y
-
-#
-# Profiling support
-#
+CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_ERRORS is not set
CONFIG_DEBUG_LL=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
#
# I2C Hardware Bus support
#
-CONFIG_I2C_AT91=m
+CONFIG_I2C_GPIO=m
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_PCA_ISA is not set
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Thu Mar 6 10:07:26 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_AUDIT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+CONFIG_MACH_CAM60=y
+# CONFIG_MACH_SAM9_L9260 is not set
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0x20004000
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_CMDLINE="console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+CONFIG_BINFMT_MISC=y
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RCSIMPLE=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_RAM=m
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_PLATRAM=m
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+# CONFIG_MTD_NAND_AT91_ECC_SOFT is not set
+CONFIG_MTD_NAND_AT91_ECC_HW=y
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+# CONFIG_ICPLUS_PHY is not set
+CONFIG_FIXED_PHY=m
+# CONFIG_FIXED_MII_10_FDX is not set
+# CONFIG_FIXED_MII_100_FDX is not set
+# CONFIG_FIXED_MII_1000_FDX is not set
+CONFIG_FIXED_MII_AMNT=1
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_VSXXXAA=m
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_TEST=m
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_DRV_AT91SAM9_RTT=0
+CONFIG_RTC_DRV_AT91SAM9_GPBR=0
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+CONFIG_DNOTIFY=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_FORCED_INLINING is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ABLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+# CONFIG_CRYPTO_XTS is not set
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_ANUBIS=m
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_TEST=m
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=m
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=m
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.15
-# Mon Jan 9 21:51:31 2006
+# Linux kernel version: 2.6.24-rc7
+# Wed Jan 9 22:19:24 2008
#
CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
-CONFIG_UID16=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
-# Code maturity level options
+# General setup
#
CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
+CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
-
-#
-# Block layer
-#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
# System Type
#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_AAEC2000 is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91RM9200=y
#
-# AT91RM9200 Implementations
+# Boot options
#
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
#
# AT91RM9200 Board Type
#
+# CONFIG_MACH_ONEARM is not set
# CONFIG_ARCH_AT91RM9200DK is not set
# CONFIG_MACH_AT91RM9200EK is not set
CONFIG_MACH_CSB337=y
# CONFIG_MACH_CSB637 is not set
# CONFIG_MACH_CARMEVA is not set
-# CONFIG_MACH_KB9200 is not set
# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+# CONFIG_MACH_CHUB is not set
+# CONFIG_MACH_HOMEMATIC is not set
+# CONFIG_MACH_ECBAT91 is not set
+# CONFIG_MACH_SWEDATMS is not set
+
+#
+# AT91 Board Options
+#
#
-# AT91RM9200 Feature Selections
+# AT91 Feature Selections
#
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=128
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_ARM920T=y
-CONFIG_CPU_32v4=y
+CONFIG_CPU_32v4T=y
CONFIG_CPU_ABRT_EV4T=y
CONFIG_CPU_CACHE_V4WT=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
#
# Processor Features
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
#
# Bus support
#
-CONFIG_ISA_DMA_API=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_PCCARD=y
# CONFIG_PCMCIA_DEBUG is not set
CONFIG_PCMCIA=y
#
# Kernel Features
#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=128
+# CONFIG_AEABI is not set
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
CONFIG_LEDS_CPU=y
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
#
# Floating point emulation
# Power management options
#
# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
#
# Networking
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
# CONFIG_NET_SCHED is not set
#
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
#
# Device Drivers
#
# Generic Driver Options
#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0
-CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=0
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_PLATRAM is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_AT91_DATAFLASH is not set
-
-#
-# NAND Flash Device Drivers
-#
# CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
# CONFIG_MTD_ONENAND is not set
#
-# Parallel port support
+# UBI - Unsorted block images
#
+# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
# CONFIG_IDE is not set
#
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
#
-# SCSI Transport Attributes
+# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_SATA is not set
# CONFIG_SCSI_DEBUG is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_ATA is not set
# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
+# Wireless LAN
#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
+# USB Network Adapters
#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
# CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_AT91RM9200_WATCHDOG=y
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
-#
-# Ftape, the floppy tape device driver
-#
-
#
# PCMCIA character devices
#
# CONFIG_CARDMAN_4000 is not set
# CONFIG_CARDMAN_4040 is not set
# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
# CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
CONFIG_AT91_SPI=y
CONFIG_AT91_SPIDEV=y
-
-#
-# I2C support
-#
CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
#
# I2C Algorithms
#
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_SENSORS_DS1337 is not set
# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_RTC8564 is not set
# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_RTC_X1205_I2C is not set
+# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia Capabilities Port drivers
+# SPI support
#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
#
-# Multimedia devices
+# Watchdog Device Drivers
#
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91RM9200_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
#
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
#
-# CONFIG_DVB is not set
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
#
# Graphics support
#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
# Sound
#
# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
#
-# USB support
+# USB HID Boot Protocol drivers
#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
#
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_ITMTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
CONFIG_USB_MON=y
#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
# CONFIG_USB_SERIAL_AIRPRIME is not set
-# CONFIG_USB_SERIAL_ANYDATA is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_CP2101 is not set
# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
# CONFIG_USB_SERIAL_EMPEG is not set
CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_FUNSOFT is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_IPAQ is not set
# CONFIG_USB_SERIAL_IR is not set
# CONFIG_USB_SERIAL_KLSI is not set
# CONFIG_USB_SERIAL_KOBIL_SCT is not set
CONFIG_USB_SERIAL_MCT_U232=y
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
# CONFIG_USB_SERIAL_HP4X is not set
# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
# CONFIG_USB_SERIAL_TI is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_XIRCOM is not set
# CONFIG_USB_SERIAL_OPTION is not set
# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
CONFIG_USB_EZUSB=y
#
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_AUERSWALD is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_PHIDGET is not set
# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
#
# USB Gadget Support
#
CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
CONFIG_USB_GADGET_AT91=y
CONFIG_USB_AT91=y
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
#
-# MMC/SD Card support
+# MMC/SD Card Drivers
#
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91RM9200=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
#
-# Real Time Clock
+# MMC/SD Host Controller Drivers
#
+# CONFIG_MMC_AT91 is not set
+# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc1"
+# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
#
-# RTC drivers
+# I2C RTC drivers
#
-# CONFIG_RTC_DRV_X1205 is not set
CONFIG_RTC_DRV_DS1307=y
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_M48T86 is not set
-CONFIG_RTC_DRV_AT91RM9200=y
-# CONFIG_RTC_DRV_TEST is not set
+# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91RM9200=y
+
#
# File systems
#
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# Pseudo filesystems
#
CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
# CONFIG_NLS is not set
-
-#
-# Profiling support
-#
+# CONFIG_DLM is not set
+CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_ERRORS is not set
CONFIG_DEBUG_LL=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_HW=y
#
# Library routines
#
+CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.15
-# Mon Jan 9 21:52:00 2006
+# Linux kernel version: 2.6.25-rc8
+# Fri Apr 4 22:06:15 2008
#
CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
-CONFIG_UID16=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
-# Code maturity level options
+# General setup
#
CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
-
-#
-# Block layer
-#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
#
# System Type
#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION is not set
+# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_AAEC2000 is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
#
-# AT91RM9200 Implementations
+# Atmel AT91 System-on-Chip
#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
#
# AT91RM9200 Board Type
#
+# CONFIG_MACH_ONEARM is not set
# CONFIG_ARCH_AT91RM9200DK is not set
# CONFIG_MACH_AT91RM9200EK is not set
# CONFIG_MACH_CSB337 is not set
CONFIG_MACH_CSB637=y
# CONFIG_MACH_CARMEVA is not set
-# CONFIG_MACH_KB9200 is not set
# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
#
-# AT91RM9200 Feature Selections
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
#
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_TIMER_HZ=128
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_ARM920T=y
-CONFIG_CPU_32v4=y
+CONFIG_CPU_32v4T=y
CONFIG_CPU_ABRT_EV4T=y
CONFIG_CPU_CACHE_V4WT=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
#
# Processor Features
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
#
# Bus support
#
-CONFIG_ISA_DMA_API=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_PCCARD=y
# CONFIG_PCMCIA_DEBUG is not set
CONFIG_PCMCIA=y
#
# Kernel Features
#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=128
+# CONFIG_AEABI is not set
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
CONFIG_LEDS_CPU=y
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
#
# Floating point emulation
# Power management options
#
# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
#
# Networking
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
# CONFIG_NET_SCHED is not set
#
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
#
# Device Drivers
#
# Generic Driver Options
#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0
-CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=0
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_PLATRAM is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_AT91_DATAFLASH is not set
-
-#
-# NAND Flash Device Drivers
-#
# CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
# CONFIG_MTD_ONENAND is not set
#
-# Parallel port support
+# UBI - Unsorted block images
#
+# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_INITRD=y
+# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
#
-# SCSI Transport Attributes
+# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_SATA is not set
# CONFIG_SCSI_DEBUG is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_ATA is not set
# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
# CONFIG_SMC91X is not set
+# CONFIG_SMSC911X is not set
# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_CS89x0 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
#
-# Ethernet (1000 Mbit)
+# Wireless LAN
#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
+# USB Network Adapters
#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
# CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
#
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
# CONFIG_SERIAL_ATMEL_TTYAT is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_AT91RM9200_WATCHDOG=y
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=m
# CONFIG_NVRAM is not set
-CONFIG_RTC=y
-# CONFIG_AT91RM9200_RTC is not set
-# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
-#
-# Ftape, the floppy tape device driver
-#
-
#
# PCMCIA character devices
#
# CONFIG_SYNCLINK_CS is not set
# CONFIG_CARDMAN_4000 is not set
# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
# CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-CONFIG_AT91_SPI=y
-CONFIG_AT91_SPIDEV=y
-
-#
-# I2C support
-#
CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
#
#
# I2C Hardware Bus support
#
-CONFIG_I2C_AT91=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_TINY_USB is not set
#
# Miscellaneous I2C Chip support
#
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_RTC_X1205_I2C is not set
+# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
-# Hardware Monitoring support
+# SPI support
#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
#
-# Misc devices
+# Watchdog Device Drivers
#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91RM9200_WATCHDOG=y
#
-# Multimedia Capabilities Port drivers
+# USB-based Watchdog Cards
#
+# CONFIG_USBPCWATCHDOG is not set
#
-# Multimedia devices
+# Sonics Silicon Backplane
#
-# CONFIG_VIDEO_DEV is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
#
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
#
-# CONFIG_DVB is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
#
# Graphics support
#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
# Sound
#
# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
#
-# USB support
+# USB Input Devices
#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
#
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
#
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_ITMTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
CONFIG_USB_MON=y
#
# USB port drivers
#
-
-#
-# USB Serial Converter support
-#
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_EZUSB=y
CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
# CONFIG_USB_SERIAL_AIRPRIME is not set
-# CONFIG_USB_SERIAL_ANYDATA is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_CP2101 is not set
# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
# CONFIG_USB_SERIAL_EMPEG is not set
CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_FUNSOFT is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_IPAQ is not set
# CONFIG_USB_SERIAL_IR is not set
# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
# CONFIG_USB_SERIAL_GARMIN is not set
# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
CONFIG_USB_SERIAL_KEYSPAN=y
CONFIG_USB_SERIAL_KEYSPAN_MPR=y
# CONFIG_USB_SERIAL_KLSI is not set
# CONFIG_USB_SERIAL_KOBIL_SCT is not set
CONFIG_USB_SERIAL_MCT_U232=y
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
# CONFIG_USB_SERIAL_HP4X is not set
# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
# CONFIG_USB_SERIAL_TI is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_XIRCOM is not set
# CONFIG_USB_SERIAL_OPTION is not set
# CONFIG_USB_SERIAL_OMNINET is not set
-CONFIG_USB_EZUSB=y
+# CONFIG_USB_SERIAL_DEBUG is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_AUERSWALD is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_PHIDGET is not set
# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
#
-# USB DSL modem support
+# LED drivers
#
+CONFIG_LEDS_GPIO=y
#
-# USB Gadget Support
+# LED Triggers
#
-# CONFIG_USB_GADGET is not set
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
#
-# MMC/SD Card support
+# Userspace I/O
#
-# CONFIG_MMC is not set
+# CONFIG_UIO is not set
#
# File systems
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
# Pseudo filesystems
#
CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
# CONFIG_NLS is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_DLM is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
CONFIG_DEBUG_USER=y
# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ICEDCC is not set
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_MANAGER=y
# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
#
# Library routines
#
+CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.22-rc4
+# Sat Jun 9 01:30:18 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+
+#
+# AT91RM9200 Board Type
+#
+# CONFIG_MACH_ONEARM is not set
+# CONFIG_ARCH_AT91RM9200DK is not set
+# CONFIG_MACH_AT91RM9200EK is not set
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+# CONFIG_MACH_CARMEVA is not set
+# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+# CONFIG_MACH_CHUB is not set
+CONFIG_MACH_ECBAT91=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+
+#
+# PC-card bridges
+#
+CONFIG_AT91_CF=y
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+CONFIG_PREEMPT=y
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="rootfstype=reiserfs root=/dev/mmcblk0p1 console=ttyS0,115200n8 rootdelay=1"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=y
+# CONFIG_MAC80211_DEBUG is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_IEEE80211_SOFTMAC=y
+CONFIG_IEEE80211_SOFTMAC_DEBUG=y
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_AFS_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNPACPI is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# PCMCIA SCSI adapter support
+#
+# CONFIG_PCMCIA_AHA152X is not set
+# CONFIG_PCMCIA_FDOMAIN is not set
+# CONFIG_PCMCIA_NINJA_SCSI is not set
+# CONFIG_PCMCIA_QLOGIC is not set
+# CONFIG_PCMCIA_SYM53C500 is not set
+# CONFIG_ATA is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_AT91RM9200_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_AT91_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ATMEL is not set
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_AT91=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Misc devices
+#
+# CONFIG_BLINK is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# LED devices
+#
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# HID Devices
+#
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=y
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91RM9200=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
#
# I2C Algorithms
#
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_PCA_ISA is not set
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc6
+# Sun Dec 30 13:02:54 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_CGROUPS is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+# CONFIG_UID16 is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_ARMCORE is not set
+CONFIG_MACH_MAGICIAN=y
+CONFIG_PXA27x=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="keepinitrd"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+CONFIG_APM_EMULATION=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+# CONFIG_IRNET is not set
+CONFIG_IRCOMM=m
+CONFIG_IRDA_ULTRA=y
+
+#
+# IrDA options
+#
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRDA_FAST_RR=y
+CONFIG_IRDA_DEBUG=y
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+CONFIG_IRTTY_SIR=m
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+
+#
+# Old SIR device drivers
+#
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Old Serial dongle support
+#
+
+#
+# FIR device drivers
+#
+CONFIG_PXA_FICP=m
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=0
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x00000000
+CONFIG_MTD_PHYSMAP_LEN=0x04000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
+# CONFIG_MTD_PXA2XX is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_PXA27x is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+# CONFIG_SERIAL_PXA_CONSOLE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_PXA=m
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+CONFIG_W1=y
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_DS2482 is not set
+CONFIG_W1_MASTER_DS1WM=y
+
+#
+# 1-wire Slaves
+#
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+CONFIG_W1_SLAVE_DS2760=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=y
+# CONFIG_APM_POWER is not set
+CONFIG_BATTERY_DS2760=y
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+CONFIG_HTC_EGPIO=y
+CONFIG_HTC_PASIC3=y
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+CONFIG_FONT_MINI_4x6=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA ARM devices
+#
+# CONFIG_SND_PXA2XX_AC97 is not set
+
+#
+# System on Chip audio support
+#
+CONFIG_SND_SOC=m
+CONFIG_SND_PXA2XX_SOC=m
+
+#
+# SoC Audio support for SuperH
+#
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_HID=m
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+CONFIG_NEW_LEDS=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_DEBUG=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+CONFIG_NLS_CODEPAGE_1251=m
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_CBC is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Thu Feb 15 20:51:47 2007
-#
-CONFIG_ARM=y
-# CONFIG_GENERIC_TIME is not set
-CONFIG_MMU=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_UTS_NS is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
+CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_DEFAULT_IOSCHED="noop"
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_L7200 is not set
CONFIG_ARCH_NS9XXX=y
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_OMAP is not set
-
-#
-# NS9xxx Implementations
-#
+CONFIG_MACH_A9M9360=y
+CONFIG_MACH_A9M9750=y
+CONFIG_MACH_CC7UCAMRY=y
+CONFIG_MACH_CC9C=y
+CONFIG_MACH_CC9P9210=y
+CONFIG_MACH_CC9P9210JS=y
+CONFIG_MACH_CC9P9215=y
+CONFIG_MACH_CC9P9215JS=y
CONFIG_MACH_CC9P9360DEV=y
-CONFIG_PROCESSOR_NS9360=y
-CONFIG_BOARD_A9M9750DEV=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_ARM926T=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-# CONFIG_ARM_THUMB is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-
-#
-# Bus support
-#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
-CONFIG_HZ=100
-# CONFIG_AEABI is not set
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
+CONFIG_MACH_CC9P9360JS=y
+CONFIG_MACH_CC9P9360VAL=y
+CONFIG_MACH_CC9P9750DEV=y
+CONFIG_MACH_CC9P9750VAL=y
+CONFIG_MACH_CCW9C=y
+CONFIG_MACH_INC20OTTER=y
+CONFIG_MACH_OTTER=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-# CONFIG_VFP is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-# CONFIG_APM is not set
-
-#
-# Networking
-#
-# CONFIG_NET is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# ISDN subsystem
-#
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
+CONFIG_NET=y
+CONFIG_PACKET=m
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_SYN_COOKIES=y
+CONFIG_MTD=m
+CONFIG_MTD_CONCAT=m
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_CFI=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NS9XXX_ETH=y
# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-# CONFIG_SERIAL_8250_MANY_PORTS is not set
-# CONFIG_SERIAL_8250_SHARE_IRQ is not set
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
+CONFIG_SERIAL_NS921X=y
+CONFIG_SERIAL_NS921X_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+CONFIG_ADC_NS9215=m
+CONFIG_I2C=m
+CONFIG_I2C_GPIO=m
# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Misc devices
-#
-# CONFIG_TIFM_CORE is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# Real Time Clock
-#
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_RTC_CLASS=m
+CONFIG_RTC_DRV_NS9215=m
+CONFIG_EXT2_FS=m
CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
+CONFIG_JFFS2_FS=m
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_ICEDCC=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC32 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_IOMAP_COPY=y
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_MXC is not set
-CONFIG_ARCH_ORION=y
+CONFIG_ARCH_ORION5X=y
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
#
# I2C Algorithms
#
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=m
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
-CONFIG_I2C_AT91=m
+CONFIG_I2C_GPIO=m
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_STUB is not set
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23
+# Sun Oct 14 02:01:07 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+CONFIG_AUDIT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+# CONFIG_MACH_CAM60 is not set
+CONFIG_MACH_SAM9_L9260=y
+
+#
+# AT91 Board Options
+#
+CONFIG_MTD_AT91_DATAFLASH_CARD=y
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+# CONFIG_ATMEL_TCLIB is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+CONFIG_PREEMPT=y
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200 mem=64M initrd=0x21100000,4194304 root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_BLOCK2MTD=y
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=3
+CONFIG_MTD_UBI_GLUEBI=y
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_DS1553=y
+# CONFIG_RTC_DRV_STK17TA8 is not set
+CONFIG_RTC_DRV_DS1742=y
+CONFIG_RTC_DRV_M48T86=y
+# CONFIG_RTC_DRV_M48T59 is not set
+CONFIG_RTC_DRV_V3020=y
+
+#
+# on-CPU RTC drivers
+#
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_NFS_DIRECTIO=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc7-hammer
+# Thu Mar 27 16:39:48 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+# CONFIG_BUG is not set
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLAB is not set
+# CONFIG_SLUB is not set
+CONFIG_SLOB=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+CONFIG_ARCH_S3C2410=y
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+CONFIG_PLAT_S3C24XX=y
+# CONFIG_S3C2410_DMA is not set
+CONFIG_PLAT_S3C=y
+CONFIG_CPU_LLSERIAL_S3C2410_ONLY=y
+CONFIG_CPU_LLSERIAL_S3C2410=y
+
+#
+# Boot options
+#
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
+
+#
+# Power management
+#
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
+
+#
+# S3C2400 Machines
+#
+CONFIG_CPU_S3C2410=y
+CONFIG_S3C2410_GPIO=y
+CONFIG_S3C2410_CLOCK=y
+
+#
+# S3C2410 Machines
+#
+# CONFIG_ARCH_SMDK2410 is not set
+# CONFIG_ARCH_H1940 is not set
+# CONFIG_MACH_N30 is not set
+# CONFIG_ARCH_BAST is not set
+# CONFIG_MACH_OTOM is not set
+# CONFIG_MACH_AML_M5900 is not set
+CONFIG_MACH_TCT_HAMMER=y
+# CONFIG_MACH_VR1000 is not set
+# CONFIG_MACH_QT2410 is not set
+
+#
+# S3C2412 Machines
+#
+# CONFIG_MACH_SMDK2413 is not set
+# CONFIG_MACH_SMDK2412 is not set
+# CONFIG_MACH_VSTMS is not set
+
+#
+# S3C2440 Machines
+#
+# CONFIG_MACH_ANUBIS is not set
+# CONFIG_MACH_OSIRIS is not set
+# CONFIG_MACH_RX3715 is not set
+# CONFIG_ARCH_S3C2440 is not set
+# CONFIG_MACH_NEXCODER_2440 is not set
+
+#
+# S3C2442 Machines
+#
+
+#
+# S3C2443 Machines
+#
+# CONFIG_MACH_SMDK2443 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=200
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M root=/dev/ram0 init=/linuxrc rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+# CONFIG_INET is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x00000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=10240
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_VT_CONSOLE is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_S3C2410=y
+CONFIG_SERIAL_S3C2410_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+CONFIG_USB_GADGET_S3C2410=y
+CONFIG_USB_S3C2410=y
+# CONFIG_USB_S3C2410_DEBUG is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_SYSCTL is not set
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_S3C_PORT is not set
+CONFIG_DEBUG_S3C_UART=0
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc6
+# Fri Jan 11 09:53:59 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91RM9200 Board Type
+#
+# CONFIG_MACH_ONEARM is not set
+CONFIG_ARCH_AT91RM9200DK=y
+# CONFIG_MACH_AT91RM9200EK is not set
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+# CONFIG_MACH_CARMEVA is not set
+# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+CONFIG_MACH_YL9200=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0000000
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_AT91=y
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=3
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+CONFIG_DAVICOM_PHY=y
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_S1D135XX=y
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LTV350QV is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_CORGI is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+CONFIG_USB_GADGET_M66592=y
+CONFIG_USB_M66592=y
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=y
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91RM9200=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+CONFIG_INSTRUMENTATION=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+CONFIG_SLUB_DEBUG_ON=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_DEBUG_KOBJECT=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+CONFIG_DEBUG_LIST=y
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o
obj-$(CONFIG_ATAGS_PROC) += atags.o
obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o
+obj-$(CONFIG_ARM_THUMBEE) += thumbee.o
obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value));
DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate));
DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate));
+#ifdef CONFIG_ARM_THUMBEE
+ DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state));
+#endif
#ifdef CONFIG_IWMMXT
DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt));
#endif
DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush));
DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags));
DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags));
+ BLANK();
+#ifdef MULTI_DABORT
+ DEFINE(PROCESSOR_DABT_FUNC, offsetof(struct processor, _data_abort));
+#endif
+#ifdef MULTI_PABORT
+ DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort));
+#endif
return 0;
}
CALL(sys_kexec_load)
CALL(sys_utimensat)
CALL(sys_signalfd)
-/* 350 */ CALL(sys_ni_syscall)
+/* 350 */ CALL(sys_timerfd_create)
CALL(sys_eventfd)
CALL(sys_fallocate)
+ CALL(sys_timerfd_settime)
+ CALL(sys_timerfd_gettime)
#ifndef syscalls_counted
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
#define syscalls_counted
@ The abort handler must return the aborted address in r0, and
@ the fault status register in r1. r9 must be preserved.
@
-#ifdef MULTI_ABORT
+#ifdef MULTI_DABORT
ldr r4, .LCprocfns
mov lr, pc
- ldr pc, [r4]
+ ldr pc, [r4, #PROCESSOR_DABT_FUNC]
#else
- bl CPU_ABORT_HANDLER
+ bl CPU_DABORT_HANDLER
#endif
@
irq_handler
#ifdef CONFIG_PREEMPT
+ str r8, [tsk, #TI_PREEMPT] @ restore preempt count
ldr r0, [tsk, #TI_FLAGS] @ get flags
+ teq r8, #0 @ if preempt count != 0
+ movne r0, #0 @ force flags to 0
tst r0, #_TIF_NEED_RESCHED
blne svc_preempt
-preempt_return:
- ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
- str r8, [tsk, #TI_PREEMPT] @ restore preempt count
- teq r0, r7
- strne r0, [r0, -r0] @ bug()
#endif
ldr r0, [sp, #S_PSR] @ irqs are already disabled
msr spsr_cxsf, r0
#ifdef CONFIG_PREEMPT
svc_preempt:
- teq r8, #0 @ was preempt count = 0
- ldreq r6, .LCirq_stat
- movne pc, lr @ no
- ldr r0, [r6, #4] @ local_irq_count
- ldr r1, [r6, #8] @ local_bh_count
- adds r0, r0, r1
- movne pc, lr
- mov r7, #0 @ preempt_schedule_irq
- str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
+ mov r8, lr
1: bl preempt_schedule_irq @ irq en/disable is done inside
ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
tst r0, #_TIF_NEED_RESCHED
- beq preempt_return @ go again
+ moveq pc, r8 @ go again
b 1b
#endif
mrs r9, cpsr
tst r3, #PSR_I_BIT
biceq r9, r9, #PSR_I_BIT
- msr cpsr_c, r9
@
@ set args, then call main handler
@ r0 - address of faulting instruction
@ r1 - pointer to registers on stack
@
- mov r0, r2 @ address (pc)
+#ifdef MULTI_PABORT
+ mov r0, r2 @ pass address of aborted instruction.
+ ldr r4, .LCprocfns
+ mov lr, pc
+ ldr pc, [r4, #PROCESSOR_PABT_FUNC]
+#else
+ CPU_PABORT_HANDLER(r0, r2)
+#endif
+ msr cpsr_c, r9 @ Maybe enable interrupts
mov r1, sp @ regs
bl do_PrefetchAbort @ call abort handler
.align 5
.LCcralign:
.word cr_alignment
-#ifdef MULTI_ABORT
+#ifdef MULTI_DABORT
.LCprocfns:
.word processor
#endif
.LCfp:
.word fp_enter
-#ifdef CONFIG_PREEMPT
-.LCirq_stat:
- .word irq_stat
-#endif
/*
* User mode handlers
@ The abort handler must return the aborted address in r0, and
@ the fault status register in r1.
@
-#ifdef MULTI_ABORT
+#ifdef MULTI_DABORT
ldr r4, .LCprocfns
mov lr, pc
- ldr pc, [r4]
+ ldr pc, [r4, #PROCESSOR_DABT_FUNC]
#else
- bl CPU_ABORT_HANDLER
+ bl CPU_DABORT_HANDLER
#endif
@
__und_usr:
usr_entry
- tst r3, #PSR_T_BIT @ Thumb mode?
- bne __und_usr_unknown @ ignore FP
- sub r4, r2, #4
-
@
@ fall through to the emulation code, which returns using r9 if
@ it has emulated the instruction, or the more conventional lr
@
adr r9, ret_from_exception
adr lr, __und_usr_unknown
-1: ldrt r0, [r4]
+ tst r3, #PSR_T_BIT @ Thumb mode?
+ subeq r4, r2, #4 @ ARM instr at LR - 4
+ subne r4, r2, #2 @ Thumb instr at LR - 2
+1: ldreqt r0, [r4]
+ beq call_fpe
+ @ Thumb instruction
+#if __LINUX_ARM_ARCH__ >= 7
+2: ldrht r5, [r4], #2
+ and r0, r5, #0xf800 @ mask bits 111x x... .... ....
+ cmp r0, #0xe800 @ 32bit instruction if xx != 0
+ blo __und_usr_unknown
+3: ldrht r0, [r4]
+ add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
+ orr r0, r0, r5, lsl #16
+#else
+ b __und_usr_unknown
+#endif
+
@
@ fallthrough to call_fpe
@
* The out of line fixup for the ldrt above.
*/
.section .fixup, "ax"
-2: mov pc, r9
+4: mov pc, r9
.previous
.section __ex_table,"a"
- .long 1b, 2b
+ .long 1b, 4b
+#if __LINUX_ARM_ARCH__ >= 7
+ .long 2b, 4b
+ .long 3b, 4b
+#endif
.previous
/*
* r10 = this threads thread_info structure.
* lr = unrecognised instruction return address
*/
+ @
+ @ Fall-through from Thumb-2 __und_usr
+ @
+#ifdef CONFIG_NEON
+ adr r6, .LCneon_thumb_opcodes
+ b 2f
+#endif
call_fpe:
#ifdef CONFIG_NEON
- adr r6, .LCneon_opcodes
+ adr r6, .LCneon_arm_opcodes
2:
ldr r7, [r6], #4 @ mask value
cmp r7, #0 @ end mask?
1:
#endif
tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
+ tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
and r8, r0, #0x0f000000 @ mask out op-code bits
teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
#ifdef CONFIG_NEON
.align 6
-.LCneon_opcodes:
+.LCneon_arm_opcodes:
.word 0xfe000000 @ mask
.word 0xf2000000 @ opcode
.word 0xff100000 @ mask
.word 0xf4000000 @ opcode
+ .word 0x00000000 @ mask
+ .word 0x00000000 @ opcode
+
+.LCneon_thumb_opcodes:
+ .word 0xef000000 @ mask
+ .word 0xef000000 @ opcode
+
+ .word 0xff100000 @ mask
+ .word 0xf9000000 @ opcode
+
.word 0x00000000 @ mask
.word 0x00000000 @ opcode
#endif
__pabt_usr:
usr_entry
+#ifdef MULTI_PABORT
+ mov r0, r2 @ pass address of aborted instruction.
+ ldr r4, .LCprocfns
+ mov lr, pc
+ ldr pc, [r4, #PROCESSOR_PABT_FUNC]
+#else
+ CPU_PABORT_HANDLER(r0, r2)
+#endif
enable_irq @ Enable interrupts
- mov r0, r2 @ address (pc)
mov r1, sp @ regs
bl do_PrefetchAbort @ call abort handler
/* fall through */
b do_mmap2
#endif
+ENTRY(pabort_ifar)
+ mrc p15, 0, r0, cr6, cr0, 2
+ENTRY(pabort_noifar)
+ mov pc, lr
+
#ifdef CONFIG_OABI_COMPAT
/*
#ifdef CONFIG_DEBUG_LL
adr r0, str_p1
bl printascii
+ mov r0, r9
+ bl printhex8
+ adr r0, str_p2
+ bl printascii
b __error
-str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n"
+str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x"
+str_p2: .asciz ").\n"
.align
#endif
--- /dev/null
+/*
+ * arch/arm/kernel/thumbee.c
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/thread_notify.h>
+
+/*
+ * Access to the ThumbEE Handler Base register
+ */
+static inline unsigned long teehbr_read()
+{
+ unsigned long v;
+ asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v));
+ return v;
+}
+
+static inline void teehbr_write(unsigned long v)
+{
+ asm("mcr p14, 6, %0, c1, c0, 0\n" : : "r" (v));
+}
+
+static int thumbee_notifier(struct notifier_block *self, unsigned long cmd, void *t)
+{
+ struct thread_info *thread = t;
+
+ switch (cmd) {
+ case THREAD_NOTIFY_FLUSH:
+ thread->thumbee_state = 0;
+ break;
+ case THREAD_NOTIFY_SWITCH:
+ current_thread_info()->thumbee_state = teehbr_read();
+ teehbr_write(thread->thumbee_state);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block thumbee_notifier_block = {
+ .notifier_call = thumbee_notifier,
+};
+
+static int __init thumbee_init(void)
+{
+ unsigned long pfr0;
+ unsigned int cpu_arch = cpu_architecture();
+
+ if (cpu_arch < CPU_ARCH_ARMv7)
+ return 0;
+
+ /* processor feature register 0 */
+ asm("mrc p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0));
+ if ((pfr0 & 0x0000f000) != 0x00001000)
+ return 0;
+
+ printk(KERN_INFO "ThumbEE CPU extension supported.\n");
+ elf_hwcap |= HWCAP_THUMBEE;
+ thread_register_notifier(&thumbee_notifier_block);
+
+ return 0;
+}
+
+late_initcall(thumbee_init);
#include <linux/clk.h>
#include <linux/mutex.h>
-#include <asm/semaphore.h>
-
#include "clock.h"
static LIST_HEAD(clocks);
config ARCH_AT91SAM9260
bool "AT91SAM9260 or AT91SAM9XE"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
config ARCH_AT91SAM9261
bool "AT91SAM9261"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
config ARCH_AT91SAM9263
bool "AT91SAM9263"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
config ARCH_AT91SAM9RL
bool "AT91SAM9RL"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
config ARCH_AT91CAP9
bool "AT91CAP9"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
config ARCH_AT91X40
bool "AT91x40"
help
Select this if you are using Sperry-Sun's KAFA board.
+config MACH_ECBAT91
+ bool "emQbit ECB_AT91 SBC"
+ depends on ARCH_AT91RM9200
+ help
+ Select this if you are using emQbit's ECB_AT91 board.
+ <http://wiki.emqbit.com/free-ecb-at91>
+
endif
# ----------------------------------------------------------
Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
+config MACH_CAM60
+ bool "KwikByte KB9260 (CAM60) board"
+ depends on ARCH_AT91SAM9260
+ help
+ Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
+ <http://www.kwikbyte.com/KB9260.html>
+
+config MACH_SAM9_L9260
+ bool "Olimex SAM9-L9260 board"
+ depends on ARCH_AT91SAM9260
+ help
+ Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
+ <http://www.olimex.com/dev/sam9-L9260.html>
+
endif
# ----------------------------------------------------------
config MTD_AT91_DATAFLASH_CARD
bool "Enable DataFlash Card support"
- depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK)
+ depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK || MACH_SAM9_L9260 || MACH_ECBAT91)
help
Enable support for the DataFlash card.
obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
obj-$(CONFIG_MACH_KAFA) += board-kafa.o
obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o
+obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
# AT91SAM9260 board-specific support
obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
+obj-$(CONFIG_MACH_CAM60) += board-cam60.o
+obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o
# AT91SAM9261 board-specific support
obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
*/
#include <linux/module.h>
+#include <linux/pm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
+static void at91cap9_poweroff(void)
+{
+ at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
+
/* --------------------------------------------------------------------
* AT91CAP9 processor initialization
* -------------------------------------------------------------------- */
iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
at91_arch_reset = at91cap9_reset;
+ pm_power_off = at91cap9_poweroff;
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
/* Init clock subsystem */
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
+#include <linux/i2c-gpio.h>
#include <video/atmel_lcdc.h>
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91cap9.h>
-#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91cap9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
#define NAND_BASE AT91_CHIPSELECT_3
static struct resource nand_resources[] = {
- {
+ [0] = {
.start = NAND_BASE,
.end = NAND_BASE + SZ_256M - 1,
.flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91_BASE_SYS + AT91_ECC,
+ .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+ .flags = IORESOURCE_MEM,
}
};
void __init at91_add_device_nand(struct at91_nand_data *data) {}
#endif
+
/* --------------------------------------------------------------------
* TWI (i2c)
* -------------------------------------------------------------------- */
#endif
+/* --------------------------------------------------------------------
+ * Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+ [0] = {
+ .start = AT91CAP9_BASE_TCB0,
+ .end = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91CAP9_ID_TCB,
+ .end = AT91CAP9_ID_TCB,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device at91cap9_tcb_device = {
+ .name = "atmel_tcb",
+ .id = 0,
+ .resource = tcb_resources,
+ .num_resources = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+ /* this chip has one clock and irq for all three TC channels */
+ at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
+ platform_device_register(&at91cap9_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
/* --------------------------------------------------------------------
* RTT
* -------------------------------------------------------------------- */
+static struct resource rtt_resources[] = {
+ {
+ .start = AT91_BASE_SYS + AT91_RTT,
+ .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
static struct platform_device at91cap9_rtt_device = {
.name = "at91_rtt",
- .id = -1,
- .num_resources = 0,
+ .id = 0,
+ .resource = rtt_resources,
+ .num_resources = ARRAY_SIZE(rtt_resources),
};
static void __init at91_add_device_rtt(void)
at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
}
-static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
- if (!atmel_default_console_device)
- printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
+
+ if (!atmel_default_console_device)
+ printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
{
at91_add_device_rtt();
at91_add_device_watchdog();
+ at91_add_device_tc();
return 0;
}
#endif
+/* --------------------------------------------------------------------
+ * Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb0_resources[] = {
+ [0] = {
+ .start = AT91RM9200_BASE_TCB0,
+ .end = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91RM9200_ID_TC0,
+ .end = AT91RM9200_ID_TC0,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AT91RM9200_ID_TC1,
+ .end = AT91RM9200_ID_TC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = AT91RM9200_ID_TC2,
+ .end = AT91RM9200_ID_TC2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device at91rm9200_tcb0_device = {
+ .name = "atmel_tcb",
+ .id = 0,
+ .resource = tcb0_resources,
+ .num_resources = ARRAY_SIZE(tcb0_resources),
+};
+
+static struct resource tcb1_resources[] = {
+ [0] = {
+ .start = AT91RM9200_BASE_TCB1,
+ .end = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91RM9200_ID_TC3,
+ .end = AT91RM9200_ID_TC3,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AT91RM9200_ID_TC4,
+ .end = AT91RM9200_ID_TC4,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = AT91RM9200_ID_TC5,
+ .end = AT91RM9200_ID_TC5,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device at91rm9200_tcb1_device = {
+ .name = "atmel_tcb",
+ .id = 1,
+ .resource = tcb1_resources,
+ .num_resources = ARRAY_SIZE(tcb1_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+ /* this chip has a separate clock and irq for each TC channel */
+ at91_clock_associate("tc0_clk", &at91rm9200_tcb0_device.dev, "t0_clk");
+ at91_clock_associate("tc1_clk", &at91rm9200_tcb0_device.dev, "t1_clk");
+ at91_clock_associate("tc2_clk", &at91rm9200_tcb0_device.dev, "t2_clk");
+ platform_device_register(&at91rm9200_tcb0_device);
+
+ at91_clock_associate("tc3_clk", &at91rm9200_tcb1_device.dev, "t0_clk");
+ at91_clock_associate("tc4_clk", &at91rm9200_tcb1_device.dev, "t1_clk");
+ at91_clock_associate("tc5_clk", &at91rm9200_tcb1_device.dev, "t2_clk");
+ platform_device_register(&at91rm9200_tcb1_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
/* --------------------------------------------------------------------
* RTC
* -------------------------------------------------------------------- */
at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
}
-static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init __deprecated at91_init_serial(struct at91_uart_config *config)
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
- if (!atmel_default_console_device)
- printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
+
+ if (!atmel_default_console_device)
+ printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
{
at91_add_device_rtc();
at91_add_device_watchdog();
+ at91_add_device_tc();
return 0;
}
*/
#include <linux/module.h>
+#include <linux/pm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
+static void at91sam9260_poweroff(void)
+{
+ at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
/* --------------------------------------------------------------------
* AT91SAM9260 processor initialization
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
at91_arch_reset = at91sam9260_reset;
+ pm_power_off = at91sam9260_poweroff;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
#define NAND_BASE AT91_CHIPSELECT_3
static struct resource nand_resources[] = {
- {
+ [0] = {
.start = NAND_BASE,
.end = NAND_BASE + SZ_256M - 1,
.flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91_BASE_SYS + AT91_ECC,
+ .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+ .flags = IORESOURCE_MEM,
}
};
#endif
+/* --------------------------------------------------------------------
+ * Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb0_resources[] = {
+ [0] = {
+ .start = AT91SAM9260_BASE_TCB0,
+ .end = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91SAM9260_ID_TC0,
+ .end = AT91SAM9260_ID_TC0,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AT91SAM9260_ID_TC1,
+ .end = AT91SAM9260_ID_TC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = AT91SAM9260_ID_TC2,
+ .end = AT91SAM9260_ID_TC2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device at91sam9260_tcb0_device = {
+ .name = "atmel_tcb",
+ .id = 0,
+ .resource = tcb0_resources,
+ .num_resources = ARRAY_SIZE(tcb0_resources),
+};
+
+static struct resource tcb1_resources[] = {
+ [0] = {
+ .start = AT91SAM9260_BASE_TCB1,
+ .end = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91SAM9260_ID_TC3,
+ .end = AT91SAM9260_ID_TC3,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AT91SAM9260_ID_TC4,
+ .end = AT91SAM9260_ID_TC4,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = AT91SAM9260_ID_TC5,
+ .end = AT91SAM9260_ID_TC5,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device at91sam9260_tcb1_device = {
+ .name = "atmel_tcb",
+ .id = 1,
+ .resource = tcb1_resources,
+ .num_resources = ARRAY_SIZE(tcb1_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+ /* this chip has a separate clock and irq for each TC channel */
+ at91_clock_associate("tc0_clk", &at91sam9260_tcb0_device.dev, "t0_clk");
+ at91_clock_associate("tc1_clk", &at91sam9260_tcb0_device.dev, "t1_clk");
+ at91_clock_associate("tc2_clk", &at91sam9260_tcb0_device.dev, "t2_clk");
+ platform_device_register(&at91sam9260_tcb0_device);
+
+ at91_clock_associate("tc3_clk", &at91sam9260_tcb1_device.dev, "t0_clk");
+ at91_clock_associate("tc4_clk", &at91sam9260_tcb1_device.dev, "t1_clk");
+ at91_clock_associate("tc5_clk", &at91sam9260_tcb1_device.dev, "t2_clk");
+ platform_device_register(&at91sam9260_tcb1_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
/* --------------------------------------------------------------------
* RTT
* -------------------------------------------------------------------- */
static struct platform_device at91sam9260_rtt_device = {
.name = "at91_rtt",
- .id = -1,
+ .id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
}
-static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
- int i;
-
- /* Fill in list of supported UARTs */
- for (i = 0; i < config->nr_tty; i++) {
- switch (config->tty_map[i]) {
- case 0:
- configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI);
- at91_uarts[i] = &at91sam9260_uart0_device;
- at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
- break;
- case 1:
- configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
- at91_uarts[i] = &at91sam9260_uart1_device;
- at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
- break;
- case 2:
- configure_usart2_pins(0);
- at91_uarts[i] = &at91sam9260_uart2_device;
- at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
- break;
- case 3:
- configure_usart3_pins(0);
- at91_uarts[i] = &at91sam9260_uart3_device;
- at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
- break;
- case 4:
- configure_usart4_pins();
- at91_uarts[i] = &at91sam9260_uart4_device;
- at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
- break;
- case 5:
- configure_usart5_pins();
- at91_uarts[i] = &at91sam9260_uart5_device;
- at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
- break;
- case 6:
- configure_dbgu_pins();
- at91_uarts[i] = &at91sam9260_dbgu_device;
- at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
- break;
- default:
- continue;
- }
- at91_uarts[i]->id = i; /* update ID number to mapped ID */
- }
-
- /* Set serial console device */
- if (config->console_tty < ATMEL_MAX_UART)
- atmel_default_console_device = at91_uarts[config->console_tty];
- if (!atmel_default_console_device)
- printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
- if (!atmel_default_console_device)
- printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
+
+ if (!atmel_default_console_device)
+ printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
void __init at91_set_serial_console(unsigned portnr) {}
void __init at91_add_device_serial(void) {}
{
at91_add_device_rtt();
at91_add_device_watchdog();
+ at91_add_device_tc();
return 0;
}
*/
#include <linux/module.h>
+#include <linux/pm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
+static void at91sam9261_poweroff(void)
+{
+ at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
/* --------------------------------------------------------------------
* AT91SAM9261 processor initialization
iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
at91_arch_reset = at91sam9261_reset;
+ pm_power_off = at91sam9261_poweroff;
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
| (1 << AT91SAM9261_ID_IRQ2);
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91sam9261_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
#endif
+/* --------------------------------------------------------------------
+ * Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+ [0] = {
+ .start = AT91SAM9261_BASE_TCB0,
+ .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91SAM9261_ID_TC0,
+ .end = AT91SAM9261_ID_TC0,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AT91SAM9261_ID_TC1,
+ .end = AT91SAM9261_ID_TC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = AT91SAM9261_ID_TC2,
+ .end = AT91SAM9261_ID_TC2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device at91sam9261_tcb_device = {
+ .name = "atmel_tcb",
+ .id = 0,
+ .resource = tcb_resources,
+ .num_resources = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+ /* this chip has a separate clock and irq for each TC channel */
+ at91_clock_associate("tc0_clk", &at91sam9261_tcb_device.dev, "t0_clk");
+ at91_clock_associate("tc1_clk", &at91sam9261_tcb_device.dev, "t1_clk");
+ at91_clock_associate("tc2_clk", &at91sam9261_tcb_device.dev, "t2_clk");
+ platform_device_register(&at91sam9261_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
/* --------------------------------------------------------------------
* RTT
* -------------------------------------------------------------------- */
static struct platform_device at91sam9261_rtt_device = {
.name = "at91_rtt",
- .id = -1,
+ .id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
}
-static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
- int i;
-
- /* Fill in list of supported UARTs */
- for (i = 0; i < config->nr_tty; i++) {
- switch (config->tty_map[i]) {
- case 0:
- configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
- at91_uarts[i] = &at91sam9261_uart0_device;
- at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart");
- break;
- case 1:
- configure_usart1_pins(0);
- at91_uarts[i] = &at91sam9261_uart1_device;
- at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart");
- break;
- case 2:
- configure_usart2_pins(0);
- at91_uarts[i] = &at91sam9261_uart2_device;
- at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart");
- break;
- case 3:
- configure_dbgu_pins();
- at91_uarts[i] = &at91sam9261_dbgu_device;
- at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart");
- break;
- default:
- continue;
- }
- at91_uarts[i]->id = i; /* update ID number to mapped ID */
- }
-
- /* Set serial console device */
- if (config->console_tty < ATMEL_MAX_UART)
- atmel_default_console_device = at91_uarts[config->console_tty];
- if (!atmel_default_console_device)
- printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
- if (!atmel_default_console_device)
- printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
+
+ if (!atmel_default_console_device)
+ printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
void __init at91_set_serial_console(unsigned portnr) {}
void __init at91_add_device_serial(void) {}
{
at91_add_device_rtt();
at91_add_device_watchdog();
+ at91_add_device_tc();
return 0;
}
*/
#include <linux/module.h>
+#include <linux/pm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
+static void at91sam9263_poweroff(void)
+{
+ at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
/* --------------------------------------------------------------------
* AT91SAM9263 processor initialization
iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
at91_arch_reset = at91sam9263_reset;
+ pm_power_off = at91sam9263_poweroff;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
/* Init clock subsystem */
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91sam9263_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
#define NAND_BASE AT91_CHIPSELECT_3
static struct resource nand_resources[] = {
- {
+ [0] = {
.start = NAND_BASE,
.end = NAND_BASE + SZ_256M - 1,
.flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91_BASE_SYS + AT91_ECC0,
+ .end = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1,
+ .flags = IORESOURCE_MEM,
}
};
#endif
+/* --------------------------------------------------------------------
+ * Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+ [0] = {
+ .start = AT91SAM9263_BASE_TCB0,
+ .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91SAM9263_ID_TCB,
+ .end = AT91SAM9263_ID_TCB,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device at91sam9263_tcb_device = {
+ .name = "atmel_tcb",
+ .id = 0,
+ .resource = tcb_resources,
+ .num_resources = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+ /* this chip has one clock and irq for all three TC channels */
+ at91_clock_associate("tcb_clk", &at91sam9263_tcb_device.dev, "t0_clk");
+ platform_device_register(&at91sam9263_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
/* --------------------------------------------------------------------
* RTT
* -------------------------------------------------------------------- */
}
/*
- * Return the device node so that board init code can use it as the
- * parent for the device node reflecting how it's used on this board.
- *
* SSC controllers are accessed through library code, instead of any
* kind of all-singing/all-dancing driver. For example one could be
* used by a particular I2S audio codec's driver, while another one
at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
}
-static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
- int i;
-
- /* Fill in list of supported UARTs */
- for (i = 0; i < config->nr_tty; i++) {
- switch (config->tty_map[i]) {
- case 0:
- configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
- at91_uarts[i] = &at91sam9263_uart0_device;
- at91_clock_associate("usart0_clk", &at91sam9263_uart0_device.dev, "usart");
- break;
- case 1:
- configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
- at91_uarts[i] = &at91sam9263_uart1_device;
- at91_clock_associate("usart1_clk", &at91sam9263_uart1_device.dev, "usart");
- break;
- case 2:
- configure_usart2_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
- at91_uarts[i] = &at91sam9263_uart2_device;
- at91_clock_associate("usart2_clk", &at91sam9263_uart2_device.dev, "usart");
- break;
- case 3:
- configure_dbgu_pins();
- at91_uarts[i] = &at91sam9263_dbgu_device;
- at91_clock_associate("mck", &at91sam9263_dbgu_device.dev, "usart");
- break;
- default:
- continue;
- }
- at91_uarts[i]->id = i; /* update ID number to mapped ID */
- }
-
- /* Set serial console device */
- if (config->console_tty < ATMEL_MAX_UART)
- atmel_default_console_device = at91_uarts[config->console_tty];
- if (!atmel_default_console_device)
- printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
- if (!atmel_default_console_device)
- printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
+
+ if (!atmel_default_console_device)
+ printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
-void __init at91_init_serial(struct at91_uart_config *config) {}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
void __init at91_set_serial_console(unsigned portnr) {}
void __init at91_add_device_serial(void) {}
{
at91_add_device_rtt();
at91_add_device_watchdog();
+ at91_add_device_tc();
return 0;
}
/*
- * linux/arch/arm/mach-at91/at91sam926x_time.c
+ * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
*
* Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
* Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
+ * Converted to ClockSource/ClockEvents by David Brownell.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-
-#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
#include <asm/mach/time.h>
#include <asm/arch/at91_pit.h>
#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
+static u32 pit_cycle; /* write-once */
+static u32 pit_cnt; /* access only w/system irq blocked */
+
+
/*
- * Returns number of microseconds since last timer interrupt. Note that interrupts
- * will have been disabled by do_gettimeofday()
- * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ * Clocksource: just a monotonic counter of MCK/16 cycles.
+ * We don't care whether or not PIT irqs are enabled.
*/
-static unsigned long at91sam926x_gettimeoffset(void)
+static cycle_t read_pit_clk(void)
{
- unsigned long elapsed;
- unsigned long t = at91_sys_read(AT91_PIT_PIIR);
+ unsigned long flags;
+ u32 elapsed;
+ u32 t;
+
+ raw_local_irq_save(flags);
+ elapsed = pit_cnt;
+ t = at91_sys_read(AT91_PIT_PIIR);
+ raw_local_irq_restore(flags);
+
+ elapsed += PIT_PICNT(t) * pit_cycle;
+ elapsed += PIT_CPIV(t);
+ return elapsed;
+}
+
+static struct clocksource pit_clk = {
+ .name = "pit",
+ .rating = 175,
+ .read = read_pit_clk,
+ .shift = 20,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
- elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */
- return (unsigned long)(elapsed * jiffies_to_usecs(1)) / LATCH;
+/*
+ * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
+ */
+static void
+pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
+{
+ unsigned long flags;
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ /* update clocksource counter, then enable the IRQ */
+ raw_local_irq_save(flags);
+ pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+ at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
+ | AT91_PIT_PITIEN);
+ raw_local_irq_restore(flags);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ BUG();
+ /* FALLTHROUGH */
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ case CLOCK_EVT_MODE_UNUSED:
+ /* disable irq, leaving the clocksource active */
+ at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+ break;
+ case CLOCK_EVT_MODE_RESUME:
+ break;
+ }
}
+static struct clock_event_device pit_clkevt = {
+ .name = "pit",
+ .features = CLOCK_EVT_FEAT_PERIODIC,
+ .shift = 32,
+ .rating = 100,
+ .cpumask = CPU_MASK_CPU0,
+ .set_mode = pit_clkevt_mode,
+};
+
+
/*
* IRQ handler for the timer.
*/
-static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
+static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
{
- volatile long nr_ticks;
- if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */
- /* Get number to ticks performed before interrupt and clear PIT interrupt */
+ /* The PIT interrupt may be disabled, and is shared */
+ if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
+ && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
+ unsigned nr_ticks;
+
+ /* Get number of ticks performed before irq, and ack it */
nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
do {
- timer_tick();
+ pit_cnt += pit_cycle;
+ pit_clkevt.event_handler(&pit_clkevt);
nr_ticks--;
} while (nr_ticks);
return IRQ_HANDLED;
- } else
- return IRQ_NONE; /* not handled */
+ }
+
+ return IRQ_NONE;
}
-static struct irqaction at91sam926x_timer_irq = {
+static struct irqaction at91sam926x_pit_irq = {
.name = "at91_tick",
.flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = at91sam926x_timer_interrupt
+ .handler = at91sam926x_pit_interrupt
};
-void at91sam926x_timer_reset(void)
+static void at91sam926x_pit_reset(void)
{
- /* Disable timer */
+ /* Disable timer and irqs */
at91_sys_write(AT91_PIT_MR, 0);
- /* Clear any pending interrupts */
- (void) at91_sys_read(AT91_PIT_PIVR);
+ /* Clear any pending interrupts, wait for PIT to stop counting */
+ while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
+ cpu_relax();
- /* Set Period Interval timer and enable its interrupt */
- at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
+ /* Start PIT but don't enable IRQ */
+ at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
}
/*
- * Set up timer interrupt.
+ * Set up both clocksource and clockevent support.
*/
-void __init at91sam926x_timer_init(void)
+static void __init at91sam926x_pit_init(void)
{
- /* Initialize and enable the timer */
- at91sam926x_timer_reset();
+ unsigned long pit_rate;
+ unsigned bits;
+
+ /*
+ * Use our actual MCK to figure out how many MCK/16 ticks per
+ * 1/HZ period (instead of a compile-time constant LATCH).
+ */
+ pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
+ pit_cycle = (pit_rate + HZ/2) / HZ;
+ WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
- /* Make IRQs happen for the system timer. */
- setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
+ /* Initialize and enable the timer */
+ at91sam926x_pit_reset();
+
+ /*
+ * Register clocksource. The high order bits of PIV are unused,
+ * so this isn't a 32-bit counter unless we get clockevent irqs.
+ */
+ pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
+ bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
+ pit_clk.mask = CLOCKSOURCE_MASK(bits);
+ clocksource_register(&pit_clk);
+
+ /* Set up irq handler */
+ setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+
+ /* Set up and register clockevents */
+ pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
+ clockevents_register_device(&pit_clkevt);
}
-#ifdef CONFIG_PM
-static void at91sam926x_timer_suspend(void)
+static void at91sam926x_pit_suspend(void)
{
/* Disable timer */
at91_sys_write(AT91_PIT_MR, 0);
}
-#else
-#define at91sam926x_timer_suspend NULL
-#endif
struct sys_timer at91sam926x_timer = {
- .init = at91sam926x_timer_init,
- .offset = at91sam926x_gettimeoffset,
- .suspend = at91sam926x_timer_suspend,
- .resume = at91sam926x_timer_reset,
+ .init = at91sam926x_pit_init,
+ .suspend = at91sam926x_pit_suspend,
+ .resume = at91sam926x_pit_reset,
};
-
*/
#include <linux/module.h>
+#include <linux/pm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
+static void at91sam9rl_poweroff(void)
+{
+ at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
/* --------------------------------------------------------------------
* AT91SAM9RL processor initialization
iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
at91_arch_reset = at91sam9rl_reset;
+ pm_power_off = at91sam9rl_poweroff;
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
/* Init clock subsystem */
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/at91sam9rl_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
#define NAND_BASE AT91_CHIPSELECT_3
static struct resource nand_resources[] = {
- {
+ [0] = {
.start = NAND_BASE,
.end = NAND_BASE + SZ_256M - 1,
.flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91_BASE_SYS + AT91_ECC,
+ .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+ .flags = IORESOURCE_MEM,
}
};
#endif
+/* --------------------------------------------------------------------
+ * Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+ [0] = {
+ .start = AT91SAM9RL_BASE_TCB0,
+ .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91SAM9RL_ID_TC0,
+ .end = AT91SAM9RL_ID_TC0,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AT91SAM9RL_ID_TC1,
+ .end = AT91SAM9RL_ID_TC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = AT91SAM9RL_ID_TC2,
+ .end = AT91SAM9RL_ID_TC2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device at91sam9rl_tcb_device = {
+ .name = "atmel_tcb",
+ .id = 0,
+ .resource = tcb_resources,
+ .num_resources = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+ /* this chip has a separate clock and irq for each TC channel */
+ at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
+ at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
+ at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
+ platform_device_register(&at91sam9rl_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
/* --------------------------------------------------------------------
* RTC
* -------------------------------------------------------------------- */
static struct platform_device at91sam9rl_rtt_device = {
.name = "at91_rtt",
- .id = -1,
+ .id = 0,
.resource = rtt_resources,
.num_resources = ARRAY_SIZE(rtt_resources),
};
}
/*
- * Return the device node so that board init code can use it as the
- * parent for the device node reflecting how it's used on this board.
- *
* SSC controllers are accessed through library code, instead of any
* kind of all-singing/all-dancing driver. For example one could be
* used by a particular I2S audio codec's driver, while another one
at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
}
-static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
- int i;
-
- /* Fill in list of supported UARTs */
- for (i = 0; i < config->nr_tty; i++) {
- switch (config->tty_map[i]) {
- case 0:
- configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
- at91_uarts[i] = &at91sam9rl_uart0_device;
- at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
- break;
- case 1:
- configure_usart1_pins(0);
- at91_uarts[i] = &at91sam9rl_uart1_device;
- at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
- break;
- case 2:
- configure_usart2_pins(0);
- at91_uarts[i] = &at91sam9rl_uart2_device;
- at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
- break;
- case 3:
- configure_usart3_pins(0);
- at91_uarts[i] = &at91sam9rl_uart3_device;
- at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
- break;
- case 4:
- configure_dbgu_pins();
- at91_uarts[i] = &at91sam9rl_dbgu_device;
- at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
- break;
- default:
- continue;
- }
- at91_uarts[i]->id = i; /* update ID number to mapped ID */
- }
-
- /* Set serial console device */
- if (config->console_tty < ATMEL_MAX_UART)
- atmel_default_console_device = at91_uarts[config->console_tty];
- if (!atmel_default_console_device)
- printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
{
if (portnr < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[portnr];
- if (!atmel_default_console_device)
- printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_add_device_serial(void)
if (at91_uarts[i])
platform_device_register(at91_uarts[i]);
}
+
+ if (!atmel_default_console_device)
+ printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
void __init at91_set_serial_console(unsigned portnr) {}
void __init at91_add_device_serial(void) {}
at91_add_device_rtc();
at91_add_device_rtt();
at91_add_device_watchdog();
+ at91_add_device_tc();
return 0;
}
--- /dev/null
+/*
+ * KwikByte CAM60 (KB9260)
+ *
+ * based on board-sam9260ek.c
+ * Copyright (C) 2005 SAN People
+ * Copyright (C) 2006 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init cam60_map_io(void)
+{
+ /* Initialize processor: 10 MHz crystal */
+ at91sam9260_initialize(10000000);
+
+ /* DGBU on ttyS0. (Rx & Tx only) */
+ at91_register_uart(0, 0, 0);
+
+ /* set serial console to ttyS0 (ie, DBGU) */
+ at91_set_serial_console(0);
+}
+
+static void __init cam60_init_irq(void)
+{
+ at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host
+ */
+static struct at91_usbh_data __initdata cam60_usbh_data = {
+ .ports = 1,
+};
+
+
+/*
+ * SPI devices.
+ */
+#if defined(CONFIG_MTD_DATAFLASH)
+static struct mtd_partition __initdata cam60_spi_partitions[] = {
+ {
+ .name = "BOOT1",
+ .offset = 0,
+ .size = 4 * 1056,
+ },
+ {
+ .name = "BOOT2",
+ .offset = MTDPART_OFS_NXTBLK,
+ .size = 256 * 1056,
+ },
+ {
+ .name = "kernel",
+ .offset = MTDPART_OFS_NXTBLK,
+ .size = 2222 * 1056,
+ },
+ {
+ .name = "file system",
+ .offset = MTDPART_OFS_NXTBLK,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct flash_platform_data __initdata cam60_spi_flash_platform_data = {
+ .name = "spi_flash",
+ .parts = cam60_spi_partitions,
+ .nr_parts = ARRAY_SIZE(cam60_spi_partitions)
+};
+#endif
+
+static struct spi_board_info cam60_spi_devices[] = {
+#if defined(CONFIG_MTD_DATAFLASH)
+ { /* DataFlash chip */
+ .modalias = "mtd_dataflash",
+ .chip_select = 0,
+ .max_speed_hz = 15 * 1000 * 1000,
+ .bus_num = 0,
+ .platform_data = &cam60_spi_flash_platform_data
+ },
+#endif
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct __initdata at91_eth_data cam60_macb_data = {
+ .phy_irq_pin = AT91_PIN_PB5,
+ .is_rmii = 0,
+};
+
+
+/*
+ * NAND Flash
+ */
+static struct mtd_partition __initdata cam60_nand_partition[] = {
+ {
+ .name = "nand_fs",
+ .offset = 0,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+ *num_partitions = ARRAY_SIZE(cam60_nand_partition);
+ return cam60_nand_partition;
+}
+
+static struct at91_nand_data __initdata cam60_nand_data = {
+ .ale = 21,
+ .cle = 22,
+ // .det_pin = ... not there
+ .rdy_pin = AT91_PIN_PA9,
+ .enable_pin = AT91_PIN_PA7,
+ .partition_info = nand_partitions,
+};
+
+
+static void __init cam60_board_init(void)
+{
+ /* Serial */
+ at91_add_device_serial();
+ /* SPI */
+ at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
+ /* Ethernet */
+ at91_add_device_eth(&cam60_macb_data);
+ /* USB Host */
+ /* enable USB power supply circuit */
+ at91_set_gpio_output(AT91_PIN_PB18, 1);
+ at91_add_device_usbh(&cam60_usbh_data);
+ /* NAND */
+ at91_add_device_nand(&cam60_nand_data);
+}
+
+MACHINE_START(CAM60, "KwikByte CAM60")
+ /* Maintainer: KwikByte */
+ .phys_io = AT91_BASE_SYS,
+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+ .boot_params = AT91_SDRAM_BASE + 0x100,
+ .timer = &at91sam926x_timer,
+ .map_io = cam60_map_io,
+ .init_irq = cam60_init_irq,
+ .init_machine = cam60_board_init,
+MACHINE_END
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91cap9_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
#include "generic.h"
-/*
- * Serial port configuration.
- * 0 .. 3 = USART0 .. USART3
- * 4 = DBGU
- */
-static struct at91_uart_config __initdata csb337_uart_config = {
- .console_tty = 0, /* ttyS0 */
- .nr_tty = 2,
- .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
-};
-
static void __init csb337_map_io(void)
{
/* Initialize processor: 3.6864 MHz crystal */
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
- /* Setup the serial ports and console */
- at91_init_serial(&csb337_uart_config);
+ /* DBGU on ttyS0 */
+ at91_register_uart(0, 0, 0);
+
+ /* make console=ttyS0 the default */
+ at91_set_serial_console(0);
}
static void __init csb337_init_irq(void)
#include "generic.h"
-/*
- * Serial port configuration.
- * 0 .. 3 = USART0 .. USART3
- * 4 = DBGU
- */
-static struct at91_uart_config __initdata csb637_uart_config = {
- .console_tty = 0, /* ttyS0 */
- .nr_tty = 2,
- .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
-};
-
static void __init csb637_map_io(void)
{
/* Initialize processor: 3.6864 MHz crystal */
at91rm9200_initialize(3686400, AT91RM9200_BGA);
- /* Setup the LEDs */
- at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
+ /* DBGU on ttyS0 */
+ at91_register_uart(0, 0, 0);
- /* Setup the serial ports and console */
- at91_init_serial(&csb637_uart_config);
+ /* make console=ttyS0 the default */
+ at91_set_serial_console(0);
}
static void __init csb637_init_irq(void)
.num_resources = ARRAY_SIZE(csb_flash_resources),
};
+static struct gpio_led csb_leds[] = {
+ { /* "d1", red */
+ .name = "d1",
+ .gpio = AT91_PIN_PB2,
+ .active_low = 1,
+ .default_trigger = "heartbeat",
+ },
+};
+
static void __init csb637_board_init(void)
{
+ /* LED(s) */
+ at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
/* Serial */
at91_add_device_serial();
/* Ethernet */
--- /dev/null
+/*
+ * linux/arch/arm/mach-at91rm9200/board-ecbat91.c
+ * Copyright (C) 2007 emQbit.com.
+ *
+ * We started from board-dk.c, which is Copyright (C) 2005 SAN People.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init ecb_at91map_io(void)
+{
+ /* Initialize processor: 18.432 MHz crystal */
+ at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+
+ /* Setup the LEDs */
+ at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
+
+ /* DBGU on ttyS0. (Rx & Tx only) */
+ at91_register_uart(0, 0, 0);
+
+ /* USART0 on ttyS1. (Rx & Tx only) */
+ at91_register_uart(AT91RM9200_ID_US0, 1, 0);
+
+ /* set serial console to ttyS0 (ie, DBGU) */
+ at91_set_serial_console(0);
+}
+
+static void __init ecb_at91init_irq(void)
+{
+ at91rm9200_init_interrupts(NULL);
+}
+
+static struct at91_eth_data __initdata ecb_at91eth_data = {
+ .phy_irq_pin = AT91_PIN_PC4,
+ .is_rmii = 0,
+};
+
+static struct at91_usbh_data __initdata ecb_at91usbh_data = {
+ .ports = 1,
+};
+
+static struct at91_mmc_data __initdata ecb_at91mmc_data = {
+ .slot_b = 0,
+ .wire4 = 1,
+};
+
+
+#if defined(CONFIG_MTD_DATAFLASH)
+static struct mtd_partition __initdata my_flash0_partitions[] =
+{
+ { /* 0x8400 */
+ .name = "Darrell-loader",
+ .offset = 0,
+ .size = 12* 1056,
+ },
+ {
+ .name = "U-boot",
+ .offset = MTDPART_OFS_NXTBLK,
+ .size = 110 * 1056,
+ },
+ { /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
+ .name = "UBoot-env",
+ .offset = MTDPART_OFS_NXTBLK,
+ .size = 8 * 1056,
+ },
+ { /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
+ .name = "Kernel",
+ .offset = MTDPART_OFS_NXTBLK,
+ .size = 1534 * 1056,
+ },
+ { /* 190200 - jffs2 root filesystem */
+ .name = "Filesystem",
+ .offset = MTDPART_OFS_NXTBLK,
+ .size = MTDPART_SIZ_FULL, /* 26 sectors */
+ }
+};
+
+static struct flash_platform_data __initdata my_flash0_platform = {
+ .name = "Removable flash card",
+ .parts = my_flash0_partitions,
+ .nr_parts = ARRAY_SIZE(my_flash0_partitions)
+};
+
+#endif
+
+static struct spi_board_info __initdata ecb_at91spi_devices[] = {
+ { /* DataFlash chip */
+ .modalias = "mtd_dataflash",
+ .chip_select = 0,
+ .max_speed_hz = 10 * 1000 * 1000,
+ .bus_num = 0,
+#if defined(CONFIG_MTD_DATAFLASH)
+ .platform_data = &my_flash0_platform,
+#endif
+ },
+ { /* User accessable spi - cs1 (250KHz) */
+ .modalias = "spi-cs1",
+ .chip_select = 1,
+ .max_speed_hz = 250 * 1000,
+ },
+ { /* User accessable spi - cs2 (1MHz) */
+ .modalias = "spi-cs2",
+ .chip_select = 2,
+ .max_speed_hz = 1 * 1000 * 1000,
+ },
+ { /* User accessable spi - cs3 (10MHz) */
+ .modalias = "spi-cs3",
+ .chip_select = 3,
+ .max_speed_hz = 10 * 1000 * 1000,
+ },
+};
+
+static void __init ecb_at91board_init(void)
+{
+ /* Serial */
+ at91_add_device_serial();
+
+ /* Ethernet */
+ at91_add_device_eth(&ecb_at91eth_data);
+
+ /* USB Host */
+ at91_add_device_usbh(&ecb_at91usbh_data);
+
+ /* I2C */
+ at91_add_device_i2c(NULL, 0);
+
+ /* MMC */
+ at91_add_device_mmc(0, &ecb_at91mmc_data);
+
+ /* SPI */
+ at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
+}
+
+MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
+ /* Maintainer: emQbit.com */
+ .phys_io = AT91_BASE_SYS,
+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+ .boot_params = AT91_SDRAM_BASE + 0x100,
+ .timer = &at91rm9200_timer,
+ .map_io = ecb_at91map_io,
+ .init_irq = ecb_at91init_irq,
+ .init_machine = ecb_at91board_init,
+MACHINE_END
--- /dev/null
+/*
+ * linux/arch/arm/mach-at91/board-sam9-l9260.c
+ *
+ * Copyright (C) 2005 SAN People
+ * Copyright (C) 2006 Atmel
+ * Copyright (C) 2007 Olimex Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+ /* Initialize processor: 18.432 MHz crystal */
+ at91sam9260_initialize(18432000);
+
+ /* Setup the LEDs */
+ at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
+
+ /* DBGU on ttyS0. (Rx & Tx only) */
+ at91_register_uart(0, 0, 0);
+
+ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+ | ATMEL_UART_RI);
+
+ /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
+ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+ /* set serial console to ttyS0 (ie, DBGU) */
+ at91_set_serial_console(0);
+}
+
+static void __init ek_init_irq(void)
+{
+ at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+ .ports = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+ .vbus_pin = AT91_PIN_PC5,
+ .pullup_pin = 0, /* pull-up driven by UDC */
+};
+
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+#if !defined(CONFIG_MMC_AT91)
+ { /* DataFlash chip */
+ .modalias = "mtd_dataflash",
+ .chip_select = 1,
+ .max_speed_hz = 15 * 1000 * 1000,
+ .bus_num = 0,
+ },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+ { /* DataFlash card */
+ .modalias = "mtd_dataflash",
+ .chip_select = 0,
+ .max_speed_hz = 15 * 1000 * 1000,
+ .bus_num = 0,
+ },
+#endif
+#endif
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+ .phy_irq_pin = AT91_PIN_PA7,
+ .is_rmii = 0,
+};
+
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+ {
+ .name = "Bootloader Area",
+ .offset = 0,
+ .size = 10 * 1024 * 1024,
+ },
+ {
+ .name = "User Area",
+ .offset = 10 * 1024 * 1024,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+ *num_partitions = ARRAY_SIZE(ek_nand_partition);
+ return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+ .ale = 21,
+ .cle = 22,
+// .det_pin = ... not connected
+ .rdy_pin = AT91_PIN_PC13,
+ .enable_pin = AT91_PIN_PC14,
+ .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+ .bus_width_16 = 1,
+#else
+ .bus_width_16 = 0,
+#endif
+};
+
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+ .slot_b = 1,
+ .wire4 = 1,
+ .det_pin = AT91_PIN_PC8,
+ .wp_pin = AT91_PIN_PC4,
+// .vcc_pin = ... not connected
+};
+
+static void __init ek_board_init(void)
+{
+ /* Serial */
+ at91_add_device_serial();
+ /* USB Host */
+ at91_add_device_usbh(&ek_usbh_data);
+ /* USB Device */
+ at91_add_device_udc(&ek_udc_data);
+ /* SPI */
+ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+ /* NAND */
+ at91_add_device_nand(&ek_nand_data);
+ /* Ethernet */
+ at91_add_device_eth(&ek_macb_data);
+ /* MMC */
+ at91_add_device_mmc(0, &ek_mmc_data);
+ /* I2C */
+ at91_add_device_i2c(NULL, 0);
+}
+
+MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
+ /* Maintainer: Olimex */
+ .phys_io = AT91_BASE_SYS,
+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+ .boot_params = AT91_SDRAM_BASE + 0x100,
+ .timer = &at91sam926x_timer,
+ .map_io = ek_map_io,
+ .init_irq = ek_init_irq,
+ .init_machine = ek_board_init,
+MACHINE_END
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
+#include <linux/spi/at73c213.h>
+#include <linux/clk.h>
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
#include "generic.h"
-/*
- * Serial port configuration.
- * 0 .. 5 = USART0 .. USART5
- * 6 = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
- .console_tty = 0, /* ttyS0 */
- .nr_tty = 3,
- .tty_map = { 6, 0, 1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */
-};
-
static void __init ek_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
- /* Setup the serial ports and console */
- at91_init_serial(&ek_uart_config);
+ /* DGBU on ttyS0. (Rx & Tx only) */
+ at91_register_uart(0, 0, 0);
+
+ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+ | ATMEL_UART_RI);
+
+ /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+ /* set serial console to ttyS0 (ie, DBGU) */
+ at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
};
+/*
+ * Audio
+ */
+static struct at73c213_board_info at73c213_data = {
+ .ssc_id = 0,
+ .shortname = "AT91SAM9260-EK external DAC",
+};
+
+#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
+static void __init at73c213_set_clk(struct at73c213_board_info *info)
+{
+ struct clk *pck0;
+ struct clk *plla;
+
+ pck0 = clk_get(NULL, "pck0");
+ plla = clk_get(NULL, "plla");
+
+ /* AT73C213 MCK Clock */
+ at91_set_B_periph(AT91_PIN_PC1, 0); /* PCK0 */
+
+ clk_set_parent(pck0, plla);
+ clk_put(plla);
+
+ info->dac_clk = pck0;
+}
+#else
+static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
+#endif
+
/*
* SPI devices.
*/
.chip_select = 0,
.max_speed_hz = 10 * 1000 * 1000,
.bus_num = 1,
+ .mode = SPI_MODE_1,
+ .platform_data = &at73c213_data,
},
#endif
};
// .vcc_pin = ... not connected
};
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+ { /* "bottom" led, green, userled1 to be defined */
+ .name = "ds5",
+ .gpio = AT91_PIN_PA6,
+ .active_low = 1,
+ .default_trigger = "none",
+ },
+ { /* "power" led, yellow */
+ .name = "ds1",
+ .gpio = AT91_PIN_PA9,
+ .default_trigger = "heartbeat",
+ }
+};
+
static void __init ek_board_init(void)
{
/* Serial */
at91_add_device_mmc(0, &ek_mmc_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
+ /* SSC (to AT73C213) */
+ at73c213_set_clk(&at73c213_data);
+ at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
+ /* LEDs */
+ at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
}
MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
+#include <linux/spi/at73c213.h>
+#include <linux/clk.h>
#include <linux/dm9000.h>
#include <linux/fb.h>
#include <linux/gpio_keys.h>
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
-/*
- * Serial port configuration.
- * 0 .. 2 = USART0 .. USART2
- * 3 = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
- .console_tty = 0, /* ttyS0 */
- .nr_tty = 1,
- .tty_map = { 3, -1, -1, -1 } /* ttyS0, ..., ttyS3 */
-};
-
static void __init ek_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
- /* Setup the serial ports and console */
- at91_init_serial(&ek_uart_config);
+ /* DGBU on ttyS0. (Rx & Tx only) */
+ at91_register_uart(0, 0, 0);
+
+ /* set serial console to ttyS0 (ie, DBGU) */
+ at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
static void __init ek_add_device_ts(void) {}
#endif
+/*
+ * Audio
+ */
+static struct at73c213_board_info at73c213_data = {
+ .ssc_id = 1,
+ .shortname = "AT91SAM9261-EK external DAC",
+};
+
+#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
+static void __init at73c213_set_clk(struct at73c213_board_info *info)
+{
+ struct clk *pck2;
+ struct clk *plla;
+
+ pck2 = clk_get(NULL, "pck2");
+ plla = clk_get(NULL, "plla");
+
+ /* AT73C213 MCK Clock */
+ at91_set_B_periph(AT91_PIN_PB31, 0); /* PCK2 */
+
+ clk_set_parent(pck2, plla);
+ clk_put(plla);
+
+ info->dac_clk = pck2;
+}
+#else
+static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
+#endif
+
/*
* SPI devices
*/
.bus_num = 0,
.platform_data = &ads_info,
.irq = AT91SAM9261_ID_IRQ0,
+ .controller_data = (void *) AT91_PIN_PA28, /* CS pin */
},
#endif
#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
.chip_select = 3,
.max_speed_hz = 10 * 1000 * 1000,
.bus_num = 0,
+ .mode = SPI_MODE_1,
+ .platform_data = &at73c213_data,
+ .controller_data = (void*) AT91_PIN_PA29, /* default for CS3 is PA6, but it must be PA29 */
},
#endif
};
static void __init ek_add_device_buttons(void) {}
#endif
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+ { /* "bottom" led, green, userled1 to be defined */
+ .name = "ds7",
+ .gpio = AT91_PIN_PA14,
+ .active_low = 1,
+ .default_trigger = "none",
+ },
+ { /* "top" led, green, userled2 to be defined */
+ .name = "ds8",
+ .gpio = AT91_PIN_PA13,
+ .active_low = 1,
+ .default_trigger = "none",
+ },
+ { /* "power" led, yellow */
+ .name = "ds1",
+ .gpio = AT91_PIN_PA23,
+ .default_trigger = "heartbeat",
+ }
+};
+
static void __init ek_board_init(void)
{
/* Serial */
at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
/* Touchscreen */
ek_add_device_ts();
+ /* SSC (to AT73C213) */
+ at73c213_set_clk(&at73c213_data);
+ at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX);
#else
/* MMC */
at91_add_device_mmc(0, &ek_mmc_data);
at91_add_device_lcdc(&ek_lcdc_data);
/* Push Buttons */
ek_add_device_buttons();
+ /* LEDs */
+ at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
}
MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
-/*
- * Serial port configuration.
- * 0 .. 2 = USART0 .. USART2
- * 3 = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
- .console_tty = 0, /* ttyS0 */
- .nr_tty = 2,
- .tty_map = { 3, 0, -1, -1, } /* ttyS0, ..., ttyS3 */
-};
-
static void __init ek_map_io(void)
{
/* Initialize processor: 16.367 MHz crystal */
at91sam9263_initialize(16367660);
- /* Setup the serial ports and console */
- at91_init_serial(&ek_uart_config);
+ /* DGBU on ttyS0. (Rx & Tx only) */
+ at91_register_uart(0, 0, 0);
+
+ /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
+ at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+ /* set serial console to ttyS0 (ie, DBGU) */
+ at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
.name = "ds3",
.gpio = AT91_PIN_PB7,
.default_trigger = "heartbeat",
- },
+ }
};
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
#include "generic.h"
-/*
- * Serial port configuration.
- * 0 .. 3 = USART0 .. USART3
- * 4 = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
- .console_tty = 0, /* ttyS0 */
- .nr_tty = 2,
- .tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
-};
-
static void __init ek_map_io(void)
{
/* Initialize processor: 12.000 MHz crystal */
at91sam9rl_initialize(12000000);
- /* Setup the serial ports and console */
- at91_init_serial(&ek_uart_config);
+ /* DGBU on ttyS0. (Rx & Tx only) */
+ at91_register_uart(0, 0, 0);
+
+ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
+ at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+ /* set serial console to ttyS0 (ie, DBGU) */
+ at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
--- /dev/null
+/*
+ * linux/arch/arm/mach-at91/board-yl-9200.c
+ *
+ * Adapted from:
+ *various board files in
+ * /arch/arm/mach-at91
+ * modifications to convert to YL-9200 platform
+ * Copyright (C) 2007 S.Birtles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+/*#include <linux/can_bus/candata.h>*/
+#include <linux/spi/ads7846.h>
+#include <linux/mtd/physmap.h>
+
+/*#include <sound/gpio_sounder.h>*/
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91rm9200_mc.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+
+#include "generic.h"
+#include <asm/arch/at91_pio.h>
+
+#define YL_9200_FLASH_BASE AT91_CHIPSELECT_0
+#define YL_9200_FLASH_SIZE 0x800000
+
+/*
+ * Serial port configuration.
+ * 0 .. 3 = USART0 .. USART3
+ * 4 = DBGU
+ *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL
+ *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL
+ *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL
+ *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL
+ *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL
+ * on the YL-9200 we are sitting at the following
+ *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL
+ *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL
+ */
+
+/* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/
+
+static struct at91_uart_config __initdata yl_9200_uart_config = {
+ .console_tty = 0, /* ttyS0 */
+ .nr_tty = 3,
+ .tty_map = { 4, 1, 0, -1, -1 } /* ttyS0, ..., ttyS4 */
+};
+
+static void __init yl_9200_map_io(void)
+{
+ /* Initialize processor: 18.432 MHz crystal */
+ /*Also initialises register clocks & gpio*/
+ at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/
+
+ /* Setup the serial ports and console */
+ at91_init_serial(&yl_9200_uart_config);
+
+ /* Setup the LEDs D2=PB17,D3=PB16 */
+ at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/
+}
+
+static void __init yl_9200_init_irq(void)
+{
+ at91rm9200_init_interrupts(NULL);
+}
+
+static struct at91_eth_data __initdata yl_9200_eth_data = {
+ .phy_irq_pin = AT91_PIN_PB28,
+ .is_rmii = 1,
+};
+
+static struct at91_usbh_data __initdata yl_9200_usbh_data = {
+ .ports = 1, /* this should be 1 not 2 for the Yl9200*/
+};
+
+static struct at91_udc_data __initdata yl_9200_udc_data = {
+/*on sheet 7 Schemitic rev 1.0*/
+ .pullup_pin = AT91_PIN_PC4,
+ .vbus_pin= AT91_PIN_PC5,
+ .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/
+
+};
+/*
+static struct at91_cf_data __initdata yl_9200_cf_data = {
+TODO S.BIRTLES
+ .det_pin = AT91_PIN_xxx,
+ .rst_pin = AT91_PIN_xxx,
+ .irq_pin = ... not connected
+ .vcc_pin = ... always powered
+
+};
+*/
+static struct at91_mmc_data __initdata yl_9200_mmc_data = {
+ .det_pin = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/
+/* .wp_pin = ... not connected SHEET7*/
+ .slot_b = 0,
+ .wire4 = 1,
+
+};
+
+/* --------------------------------------------------------------------
+ * Touch screen
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+static int ads7843_pendown_state(void)
+{
+ return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
+}
+
+static void __init at91_init_device_ts(void)
+{
+/*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C
+THAT IS TO SAY THAT MISO,MOSI,SPCK AND CS are already configured
+we only need to enable the other datapins which are:
+PB10/RK1 BUSY
+*/
+/* Touchscreen BUSY signal , pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/
+at91_set_gpio_input(AT91_PIN_PB10, 1);
+}
+
+#else
+static void __init at91_init_device_ts(void) {}
+#endif
+
+static struct ads7846_platform_data ads_info = {
+ .model = 7843,
+ .x_min = 150,
+ .x_max = 3830,
+ .y_min = 190,
+ .y_max = 3830,
+ .vref_delay_usecs = 100,
+/* for a 8" touch screen*/
+ //.x_plate_ohms = 603, //= 450, S.Birtles TODO
+ //.y_plate_ohms = 332, //= 250, S.Birtles TODO
+/*for a 10.4" touch screen*/
+ //.x_plate_ohms =611,
+ //.y_plate_ohms =325,
+
+ .x_plate_ohms = 576,
+ .y_plate_ohms = 366,
+ //
+ .pressure_max = 15000, /*generally nonsense on the 7843*/
+ /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/
+ .debounce_max = 1,
+ .debounce_rep = 0,
+ .debounce_tol = (~0),
+ .get_pendown_state = ads7843_pendown_state,
+};
+
+/*static struct canbus_platform_data can_info = {
+ .model = 2510,
+};
+*/
+
+static struct spi_board_info yl_9200_spi_devices[] = {
+/*this sticks it at:
+ /sys/devices/platform/atmel_spi.0/spi0.0
+ /sys/bus/platform/devices/
+Documentation/spi IIRC*/
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+ /*(this IS correct 04-NOV-2007)*/
+ {
+ .modalias = "ads7846", /* because the driver is called ads7846*/
+ .chip_select = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */
+/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/
+ /*.controller_data =AT91_PIN_PA3 ,*/
+ .max_speed_hz = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */
+ .bus_num = 0,
+ .platform_data = &ads_info,
+ .irq = AT91_PIN_PB11,
+ },
+#endif
+/*we need to put our CAN driver data here!!*/
+/*THIS IS ALL DUMMY DATA*/
+/* {
+ .modalias = "mcp2510", //DUMMY for MCP2510 chip
+ .chip_select = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */
+ /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */
+ /* .controller_data =AT91_PIN_PA4 ,
+ .max_speed_hz = 25000 * 26,
+ .bus_num = 0,
+ .platform_data = &can_info,
+ .irq = AT91_PIN_PC0,
+ },
+ */
+ //max SPI chip needs to go here
+};
+
+static struct mtd_partition __initdata yl_9200_nand_partition[] = {
+ {
+ .name = "AT91 NAND partition 1, boot",
+ .offset = 0,
+ .size = 1 * SZ_256K
+ },
+ {
+ .name = "AT91 NAND partition 2, kernel",
+ .offset = 1 * SZ_256K,
+ .size = 2 * SZ_1M - 1 * SZ_256K
+ },
+ {
+ .name = "AT91 NAND partition 3, filesystem",
+ .offset = 2 * SZ_1M,
+ .size = 14 * SZ_1M
+ },
+ {
+ .name = "AT91 NAND partition 4, storage",
+ .offset = 16 * SZ_1M,
+ .size = 16 * SZ_1M
+ },
+ {
+ .name = "AT91 NAND partition 5, ext-fs",
+ .offset = 32 * SZ_1M,
+ .size = 32 * SZ_1M
+ },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+ *num_partitions = ARRAY_SIZE(yl_9200_nand_partition);
+ return yl_9200_nand_partition;
+}
+
+static struct at91_nand_data __initdata yl_9200_nand_data = {
+ .ale= 6,
+ .cle= 7,
+ /*.det_pin = AT91_PIN_PCxx,*/ /*we don't have a det pin because NandFlash is fixed to board*/
+ .rdy_pin = AT91_PIN_PC14, /*R/!B Sheet10*/
+ .enable_pin = AT91_PIN_PC15, /*!CE Sheet10 */
+ .partition_info = nand_partitions,
+};
+
+
+
+/*
+TODO S.Birtles
+potentially a problem with the size above
+physmap platform flash device: 00800000 at 10000000
+physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
+NOR chip too large to fit in mapping. Attempting to cope...
+ Intel/Sharp Extended Query Table at 0x0031
+Using buffer write method
+cfi_cmdset_0001: Erase suspend on write enabled
+Reducing visibility of 16384KiB chip to 8192KiB
+*/
+
+static struct mtd_partition yl_9200_flash_partitions[] = {
+ {
+ .name = "Bootloader",
+ .size = 0x00040000,
+ .offset = 0,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ },{
+ .name = "Kernel",
+ .size = 0x001C0000,
+ .offset = 0x00040000,
+ },{
+ .name = "Filesystem",
+ .size = MTDPART_SIZ_FULL,
+ .offset = 0x00200000
+ }
+
+};
+
+static struct physmap_flash_data yl_9200_flash_data = {
+ .width = 2,
+ .parts = yl_9200_flash_partitions,
+ .nr_parts = ARRAY_SIZE(yl_9200_flash_partitions),
+};
+
+static struct resource yl_9200_flash_resources[] = {
+{
+ .start = YL_9200_FLASH_BASE,
+ .end = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+static struct platform_device yl_9200_flash = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &yl_9200_flash_data,
+ },
+ .resource = yl_9200_flash_resources,
+ .num_resources = ARRAY_SIZE(yl_9200_flash_resources),
+};
+
+
+static struct gpio_led yl_9200_leds[] = {
+/*D2 &D3 are passed directly in via at91_init_leds*/
+ {
+ .name = "led4", /*D4*/
+ .gpio = AT91_PIN_PB15,
+ .active_low = 1,
+ .default_trigger = "heartbeat",
+ /*.default_trigger = "timer",*/
+ },
+ {
+ .name = "led5", /*D5*/
+ .gpio = AT91_PIN_PB8,
+ .active_low = 1,
+ .default_trigger = "heartbeat",
+ }
+};
+
+//static struct gpio_sounder yl_9200_sounder[] = {*/
+/*This is a simple speaker attached to a gpo line*/
+
+// {
+// .name = "Speaker", /*LS1*/
+// .gpio = AT91_PIN_PA22,
+// .active_low = 0,
+// .default_trigger = "heartbeat",
+ /*.default_trigger = "timer",*/
+// },
+//};
+
+
+
+static struct i2c_board_info __initdata yl_9200_i2c_devices[] = {
+ {
+ /*TODO*/
+ I2C_BOARD_INFO("CS4334", 0x00),
+ }
+};
+
+
+ /*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button yl_9200_buttons[] = {
+ {
+ .gpio = AT91_PIN_PA24,
+ .code = BTN_2,
+ .desc = "SW2",
+ .active_low = 1,
+ .wakeup = 1,
+ },
+ {
+ .gpio = AT91_PIN_PB1,
+ .code = BTN_3,
+ .desc = "SW3",
+ .active_low = 1,
+ .wakeup = 1,
+ },
+ {
+ .gpio = AT91_PIN_PB2,
+ .code = BTN_4,
+ .desc = "SW4",
+ .active_low = 1,
+ .wakeup = 1,
+ },
+ {
+ .gpio = AT91_PIN_PB6,
+ .code = BTN_5,
+ .desc = "SW5",
+ .active_low = 1,
+ .wakeup = 1,
+ },
+
+};
+
+static struct gpio_keys_platform_data yl_9200_button_data = {
+ .buttons = yl_9200_buttons,
+ .nbuttons = ARRAY_SIZE(yl_9200_buttons),
+};
+
+static struct platform_device yl_9200_button_device = {
+ .name = "gpio-keys",
+ .id = -1,
+ .num_resources = 0,
+ .dev = {
+ .platform_data = &yl_9200_button_data,
+ }
+};
+
+static void __init yl_9200_add_device_buttons(void)
+{
+ //SW2
+ at91_set_gpio_input(AT91_PIN_PA24, 0);
+ at91_set_deglitch(AT91_PIN_PA24, 1);
+
+ //SW3
+ at91_set_gpio_input(AT91_PIN_PB1, 0);
+ at91_set_deglitch(AT91_PIN_PB1, 1);
+ //SW4
+ at91_set_gpio_input(AT91_PIN_PB2, 0);
+ at91_set_deglitch(AT91_PIN_PB2, 1);
+
+ //SW5
+ at91_set_gpio_input(AT91_PIN_PB6, 0);
+ at91_set_deglitch(AT91_PIN_PB6, 1);
+
+
+ at91_set_gpio_output(AT91_PIN_PB7, 1); /* #TURN BUTTONS ON, SHEET 5 of schematics */
+ platform_device_register(&yl_9200_button_device);
+}
+#else
+static void __init yl_9200_add_device_buttons(void) {}
+#endif
+
+#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
+#include <video/s1d13xxxfb.h>
+
+/* EPSON S1D13806 FB (discontinued chip)*/
+/* EPSON S1D13506 FB */
+
+#define AT91_FB_REG_BASE 0x80000000L
+#define AT91_FB_REG_SIZE 0x200
+#define AT91_FB_VMEM_BASE 0x80200000L
+#define AT91_FB_VMEM_SIZE 0x200000L
+
+/*#define S1D_DISPLAY_WIDTH 640*/
+/*#define S1D_DISPLAY_HEIGHT 480*/
+
+
+static void __init yl_9200_init_video(void)
+{
+ at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
+ at91_sys_write(AT91_PIOC + PIO_BSR,0);
+ at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
+
+ at91_sys_write( AT91_SMC_CSR(2),
+ AT91_SMC_NWS_(0x4) |
+ AT91_SMC_WSEN |
+ AT91_SMC_TDF_(0x100) |
+ AT91_SMC_DBW
+ );
+
+
+
+}
+
+
+static struct s1d13xxxfb_regval yl_9200_s1dfb_initregs[] =
+{
+ {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
+ {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
+ {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
+ {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
+ {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
+ {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
+ {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
+ {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
+ {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
+ {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
+ {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
+ {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
+ {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
+ {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
+ {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
+ {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
+ {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
+ {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
+ {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
+ {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
+ {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
+ {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
+ {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
+ {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
+ {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
+ {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
+ {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
+ {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
+ {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
+ {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
+ {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
+ {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
+ {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
+ {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
+ {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
+ {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
+ {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
+ {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
+ {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
+ {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
+ {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
+ {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
+ {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
+ {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
+ {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
+ {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
+ {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
+ {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
+ {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
+ {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
+ {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
+ {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
+ {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
+ {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
+ {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
+ {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
+ {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
+ {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
+ {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
+ {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
+ {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
+ {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
+ {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
+ {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
+ {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
+ {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
+ {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
+ {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
+ {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
+ {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
+ {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
+ {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
+ {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
+ {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
+ {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
+ {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
+ {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
+ {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
+ {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
+ {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
+ {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
+ {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
+ {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
+ {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
+ {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
+ {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
+ {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
+ {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
+ {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
+ {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
+ {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
+ {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
+ {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
+ {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
+ {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
+ {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
+ {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
+ {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
+ {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
+ {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
+ {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
+ {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
+ {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
+ {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
+ {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
+};
+
+static u64 s1dfb_dmamask = 0xffffffffUL;
+
+static struct s1d13xxxfb_pdata yl_9200_s1dfb_pdata = {
+ .initregs = yl_9200_s1dfb_initregs,
+ .initregssize = ARRAY_SIZE(yl_9200_s1dfb_initregs),
+ .platform_init_video = yl_9200_init_video,
+};
+
+static struct resource yl_9200_s1dfb_resource[] = {
+ [0] = { /* video mem */
+ .name = "s1d13xxxfb memory",
+ /* .name = "s1d13806 memory",*/
+ .start = AT91_FB_VMEM_BASE,
+ .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = { /* video registers */
+ .name = "s1d13xxxfb registers",
+ /* .name = "s1d13806 registers",*/
+ .start = AT91_FB_REG_BASE,
+ .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device yl_9200_s1dfb_device = {
+ /*TODO S.Birtles , really we need the chip revision in here as well*/
+ .name = "s1d13806fb",
+ /* .name = "s1d13506fb",*/
+ .id = -1,
+ .dev = {
+ /*TODO theres a waring here!!*/
+ /*WARNING: vmlinux.o(.data+0x2dbc): Section mismatch: reference to .init.text: (between 'yl_9200_s1dfb_pdata' and 's1dfb_dmamask')*/
+ .dma_mask = &s1dfb_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ .platform_data = &yl_9200_s1dfb_pdata,
+ },
+ .resource = yl_9200_s1dfb_resource,
+ .num_resources = ARRAY_SIZE(yl_9200_s1dfb_resource),
+};
+
+void __init yl_9200_add_device_video(void)
+{
+ platform_device_register(&yl_9200_s1dfb_device);
+}
+#else
+ void __init yl_9200_add_device_video(void) {}
+#endif
+
+/*this is not called first , yl_9200_map_io is called first*/
+static void __init yl_9200_board_init(void)
+{
+ /* Serial */
+ at91_add_device_serial();
+ /* Ethernet */
+ at91_add_device_eth(&yl_9200_eth_data);
+ /* USB Host */
+ at91_add_device_usbh(&yl_9200_usbh_data);
+ /* USB Device */
+ at91_add_device_udc(&yl_9200_udc_data);
+ /* pullup_pin it is actually active low, but this is not needed, driver sets it up */
+ /*at91_set_multi_drive(yl_9200_udc_data.pullup_pin, 0);*/
+
+ /* Compact Flash */
+ /*at91_add_device_cf(&yl_9200_cf_data);*/
+
+ /* I2C */
+ at91_add_device_i2c(yl_9200_i2c_devices, ARRAY_SIZE(yl_9200_i2c_devices));
+ /* SPI */
+ /*TODO YL9200 we have 2 spi interfaces touch screen & CAN*/
+ /* AT91_PIN_PA5, AT91_PIN_PA6 , are used on the max 485 NOT SPI*/
+
+ /*touch screen and CAN*/
+ at91_add_device_spi(yl_9200_spi_devices, ARRAY_SIZE(yl_9200_spi_devices));
+
+ /*Basically the TS uses PB11 & PB10 , PB11 is configured by the SPI system BP10 IS NOT USED!!*/
+ /* we need this incase the board is running without a touch screen*/
+ #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+ at91_init_device_ts(); /*init the touch screen device*/
+ #endif
+ /* DataFlash card */
+ at91_add_device_mmc(0, &yl_9200_mmc_data);
+ /* NAND */
+ at91_add_device_nand(&yl_9200_nand_data);
+ /* NOR Flash */
+ platform_device_register(&yl_9200_flash);
+ /* LEDs. Note!! this does not include the led's we passed for the processor status */
+ at91_gpio_leds(yl_9200_leds, ARRAY_SIZE(yl_9200_leds));
+ /* VGA */
+ /*this is self registered by including the s1d13xxx chip in the kernel build*/
+ yl_9200_add_device_video();
+ /* Push Buttons */
+ yl_9200_add_device_buttons();
+ /*TODO fixup the Sounder */
+// yl_9200_add_device_sounder(yl_9200_sounder,ARRAY_SIZE(yl_9200_sounder));
+
+}
+
+MACHINE_START(YL9200, "uCdragon YL-9200")
+ /* Maintainer: S.Birtles*/
+ .phys_io = AT91_BASE_SYS,
+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+ .boot_params = AT91_SDRAM_BASE + 0x100,
+ .timer = &at91rm9200_timer,
+ .map_io = yl_9200_map_io,
+ .init_irq = yl_9200_init_irq,
+ .init_machine = yl_9200_board_init,
+MACHINE_END
#include <linux/delay.h>
#include <linux/clk.h>
-#include <asm/semaphore.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mach-types.h>
#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91rm9200_mc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/cpu.h>
#include "generic.h"
+#ifdef CONFIG_ARCH_AT91RM9200
+#include <asm/arch/at91rm9200_mc.h>
+
+/*
+ * The AT91RM9200 goes into self-refresh mode with this command, and will
+ * terminate self-refresh automatically on the next SDRAM access.
+ */
+#define sdram_selfrefresh_enable() at91_sys_write(AT91_SDRAMC_SRR, 1)
+#define sdram_selfrefresh_disable() do {} while (0)
+
+#elif defined(CONFIG_ARCH_AT91CAP9)
+#include <asm/arch/at91cap9_ddrsdr.h>
+
+static u32 saved_lpr;
+
+static inline void sdram_selfrefresh_enable(void)
+{
+ u32 lpr;
+
+ saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
+
+ lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
+ at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+}
+
+#define sdram_selfrefresh_disable() at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
+
+#else
+#include <asm/arch/at91sam9_sdramc.h>
+
+static u32 saved_lpr;
+
+static inline void sdram_selfrefresh_enable(void)
+{
+ u32 lpr;
+
+ saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
+
+ lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
+ at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
+}
+
+#define sdram_selfrefresh_disable() at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
+
+/*
+ * FIXME: The AT91SAM9263 has a second EBI controller which may have
+ * additional SDRAM. pm_slowclock.S will require a similar fix.
+ */
+
+#endif
+
+
+/*
+ * Show the reason for the previous system reset.
+ */
+#if defined(AT91_SHDWC)
+
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
+
+static void __init show_reset_status(void)
+{
+ static char reset[] __initdata = "reset";
+
+ static char general[] __initdata = "general";
+ static char wakeup[] __initdata = "wakeup";
+ static char watchdog[] __initdata = "watchdog";
+ static char software[] __initdata = "software";
+ static char user[] __initdata = "user";
+ static char unknown[] __initdata = "unknown";
+
+ static char signal[] __initdata = "signal";
+ static char rtc[] __initdata = "rtc";
+ static char rtt[] __initdata = "rtt";
+ static char restore[] __initdata = "power-restored";
+
+ char *reason, *r2 = reset;
+ u32 reset_type, wake_type;
+
+ reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
+ wake_type = at91_sys_read(AT91_SHDW_SR);
+
+ switch (reset_type) {
+ case AT91_RSTC_RSTTYP_GENERAL:
+ reason = general;
+ break;
+ case AT91_RSTC_RSTTYP_WAKEUP:
+ /* board-specific code enabled the wakeup sources */
+ reason = wakeup;
+
+ /* "wakeup signal" */
+ if (wake_type & AT91_SHDW_WAKEUP0)
+ r2 = signal;
+ else {
+ r2 = reason;
+ if (wake_type & AT91_SHDW_RTTWK) /* rtt wakeup */
+ reason = rtt;
+ else if (wake_type & AT91_SHDW_RTCWK) /* rtc wakeup */
+ reason = rtc;
+ else if (wake_type == 0) /* power-restored wakeup */
+ reason = restore;
+ else /* unknown wakeup */
+ reason = unknown;
+ }
+ break;
+ case AT91_RSTC_RSTTYP_WATCHDOG:
+ reason = watchdog;
+ break;
+ case AT91_RSTC_RSTTYP_SOFTWARE:
+ reason = software;
+ break;
+ case AT91_RSTC_RSTTYP_USER:
+ reason = user;
+ break;
+ default:
+ reason = unknown;
+ break;
+ }
+ pr_info("AT91: Starting after %s %s\n", reason, r2);
+}
+#else
+static void __init show_reset_status(void) {}
+#endif
+
static int at91_pm_valid_state(suspend_state_t state)
{
static void (*slow_clock)(void);
+#ifdef CONFIG_AT91_SLOW_CLOCK
+extern void at91_slow_clock(void);
+extern u32 at91_slow_clock_sz;
+#endif
+
static int at91_pm_enter(suspend_state_t state)
{
* turning off the main oscillator; reverse on wakeup.
*/
if (slow_clock) {
+#ifdef CONFIG_AT91_SLOW_CLOCK
+ /* copy slow_clock handler to SRAM, and call it */
+ memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
+#endif
slow_clock();
break;
} else {
- /* DEVELOPMENT ONLY */
- pr_info("AT91: PM - no slow clock mode yet ...\n");
+ pr_info("AT91: PM - no slow clock mode enabled ...\n");
/* FALLTHROUGH leaving master clock alone */
}
case PM_SUSPEND_STANDBY:
/*
* NOTE: the Wait-for-Interrupt instruction needs to be
- * in icache so the SDRAM stays in self-refresh mode until
- * the wakeup IRQ occurs.
+ * in icache so no SDRAM accesses are needed until the
+ * wakeup IRQ occurs and self-refresh is terminated.
*/
asm("b 1f; .align 5; 1:");
asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
- at91_sys_write(AT91_SDRAMC_SRR, 1); /* self-refresh mode */
- /* fall though to next state */
+ sdram_selfrefresh_enable();
+ asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
+ sdram_selfrefresh_disable();
+ break;
case PM_SUSPEND_ON:
asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
error:
+ sdram_selfrefresh_disable();
target_state = PM_SUSPEND_ON;
at91_irq_resume();
at91_gpio_resume();
static int __init at91_pm_init(void)
{
- printk("AT91: Power Management\n");
-
-#ifdef CONFIG_AT91_PM_SLOW_CLOCK
- /* REVISIT allocations of SRAM should be dynamically managed.
- * FIQ handlers and other components will want SRAM/TCM too...
- */
- slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K));
- memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz);
+#ifdef CONFIG_AT91_SLOW_CLOCK
+ slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
#endif
- /* Disable SDRAM low-power mode. Cannot be used with self-refresh. */
+ pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
+
+#ifdef CONFIG_ARCH_AT91RM9200
+ /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
at91_sys_write(AT91_SDRAMC_LPR, 0);
+#endif
suspend_set_ops(&at91_pm_ops);
+ show_reset_status();
return 0;
}
arch_initcall(at91_pm_init);
bool "EDB7211"
select ISA
select ARCH_DISCONTIGMEM_ENABLE
+ select ARCH_SPARSEMEM_ENABLE
+ select ARCH_SELECT_MEMORY_MODEL
help
Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
evaluation board.
#
# Makefile for the linux kernel.
#
-obj-y := core.o clock.o
+obj-y := core.o clock.o gpio.o
obj-m :=
obj-n :=
obj- :=
static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c };
-static void update_gpio_int_params(unsigned port)
+void ep93xx_gpio_update_int_params(unsigned port)
{
BUG_ON(port > 2);
EP93XX_GPIO_REG(int_en_register_offset[port]));
}
-/* Port ordering is: A B F D E C G H */
-static const u8 data_register_offset[8] = {
- 0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40,
-};
-
-static const u8 data_direction_register_offset[8] = {
- 0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44,
-};
-
-#define GPIO_IN 0
-#define GPIO_OUT 1
-
-static void ep93xx_gpio_set_direction(unsigned line, int direction)
-{
- unsigned int data_direction_register;
- unsigned long flags;
- unsigned char v;
-
- data_direction_register =
- EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
-
- local_irq_save(flags);
- if (direction == GPIO_OUT) {
- if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) {
- /* Port A/B/F */
- gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
- update_gpio_int_params(line >> 3);
- }
-
- v = __raw_readb(data_direction_register);
- v |= 1 << (line & 7);
- __raw_writeb(v, data_direction_register);
- } else if (direction == GPIO_IN) {
- v = __raw_readb(data_direction_register);
- v &= ~(1 << (line & 7));
- __raw_writeb(v, data_direction_register);
- }
- local_irq_restore(flags);
-}
-
-int gpio_direction_input(unsigned gpio)
-{
- if (gpio > EP93XX_GPIO_LINE_MAX)
- return -EINVAL;
-
- ep93xx_gpio_set_direction(gpio, GPIO_IN);
-
- return 0;
-}
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- if (gpio > EP93XX_GPIO_LINE_MAX)
- return -EINVAL;
-
- gpio_set_value(gpio, value);
- ep93xx_gpio_set_direction(gpio, GPIO_OUT);
-
- return 0;
-}
-EXPORT_SYMBOL(gpio_direction_output);
-
-int gpio_get_value(unsigned gpio)
-{
- unsigned int data_register;
-
- data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
-
- return !!(__raw_readb(data_register) & (1 << (gpio & 7)));
-}
-EXPORT_SYMBOL(gpio_get_value);
-
-void gpio_set_value(unsigned gpio, int value)
+void ep93xx_gpio_int_mask(unsigned line)
{
- unsigned int data_register;
- unsigned long flags;
- unsigned char v;
-
- data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
-
- local_irq_save(flags);
- v = __raw_readb(data_register);
- if (value)
- v |= 1 << (gpio & 7);
- else
- v &= ~(1 << (gpio & 7));
- __raw_writeb(v, data_register);
- local_irq_restore(flags);
+ gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
}
-EXPORT_SYMBOL(gpio_set_value);
-
/*************************************************************************
* EP93xx IRQ handling
if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
- update_gpio_int_params(port);
+ ep93xx_gpio_update_int_params(port);
}
__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
gpio_int_unmasked[port] &= ~port_mask;
- update_gpio_int_params(port);
+ ep93xx_gpio_update_int_params(port);
__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}
int port = line >> 3;
gpio_int_unmasked[port] &= ~(1 << (line & 7));
- update_gpio_int_params(port);
+ ep93xx_gpio_update_int_params(port);
}
static void ep93xx_gpio_irq_unmask(unsigned int irq)
int port = line >> 3;
gpio_int_unmasked[port] |= 1 << (line & 7);
- update_gpio_int_params(port);
+ ep93xx_gpio_update_int_params(port);
}
const int port = gpio >> 3;
const int port_mask = 1 << (gpio & 7);
- ep93xx_gpio_set_direction(gpio, GPIO_IN);
+ gpio_direction_output(gpio, gpio_get_value(gpio));
switch (type) {
case IRQT_RISING:
desc->status &= ~IRQ_TYPE_SENSE_MASK;
desc->status |= type & IRQ_TYPE_SENSE_MASK;
- update_gpio_int_params(port);
+ ep93xx_gpio_update_int_params(port);
return 0;
}
.resource = ep93xx_ohci_resources,
};
+extern void ep93xx_gpio_init(void);
void __init ep93xx_init_devices(void)
{
__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
__raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
+ ep93xx_gpio_init();
+
amba_device_register(&uart1_device, &iomem_resource);
amba_device_register(&uart2_device, &iomem_resource);
amba_device_register(&uart3_device, &iomem_resource);
--- /dev/null
+/*
+ * linux/arch/arm/mach-ep93xx/gpio.c
+ *
+ * Generic EP93xx GPIO handling
+ *
+ * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * Based on code originally from:
+ * linux/arch/arm/mach-ep93xx/core.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/seq_file.h>
+
+#include <asm/arch/ep93xx-regs.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+struct ep93xx_gpio_chip {
+ struct gpio_chip chip;
+
+ unsigned int data_reg;
+ unsigned int data_dir_reg;
+};
+
+#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
+
+/* From core.c */
+extern void ep93xx_gpio_int_mask(unsigned line);
+extern void ep93xx_gpio_update_int_params(unsigned port);
+
+static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+ unsigned long flags;
+ u8 v;
+
+ local_irq_save(flags);
+ v = __raw_readb(ep93xx_chip->data_dir_reg);
+ v &= ~(1 << offset);
+ __raw_writeb(v, ep93xx_chip->data_dir_reg);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int val)
+{
+ struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+ unsigned long flags;
+ int line;
+ u8 v;
+
+ local_irq_save(flags);
+
+ /* Set the value */
+ v = __raw_readb(ep93xx_chip->data_reg);
+ if (val)
+ v |= (1 << offset);
+ else
+ v &= ~(1 << offset);
+ __raw_writeb(v, ep93xx_chip->data_reg);
+
+ /* Drive as an output */
+ line = chip->base + offset;
+ if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
+ /* Ports A/B/F */
+ ep93xx_gpio_int_mask(line);
+ ep93xx_gpio_update_int_params(line >> 3);
+ }
+
+ v = __raw_readb(ep93xx_chip->data_dir_reg);
+ v |= (1 << offset);
+ __raw_writeb(v, ep93xx_chip->data_dir_reg);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+
+ return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
+}
+
+static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+ struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+ unsigned long flags;
+ u8 v;
+
+ local_irq_save(flags);
+ v = __raw_readb(ep93xx_chip->data_reg);
+ if (val)
+ v |= (1 << offset);
+ else
+ v &= ~(1 << offset);
+ __raw_writeb(v, ep93xx_chip->data_reg);
+ local_irq_restore(flags);
+}
+
+static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+ struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+ u8 data_reg, data_dir_reg;
+ int i;
+
+ data_reg = __raw_readb(ep93xx_chip->data_reg);
+ data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
+
+ for (i = 0; i < chip->ngpio; i++)
+ seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i,
+ (data_reg & (1 << i)) ? "set" : "clear",
+ (data_dir_reg & (1 << i)) ? "out" : "in");
+}
+
+#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
+ { \
+ .chip = { \
+ .label = name, \
+ .direction_input = ep93xx_gpio_direction_input, \
+ .direction_output = ep93xx_gpio_direction_output, \
+ .get = ep93xx_gpio_get, \
+ .set = ep93xx_gpio_set, \
+ .dbg_show = ep93xx_gpio_dbg_show, \
+ .base = base_gpio, \
+ .ngpio = 8, \
+ }, \
+ .data_reg = EP93XX_GPIO_REG(dr), \
+ .data_dir_reg = EP93XX_GPIO_REG(ddr), \
+ }
+
+static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
+ EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
+ EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
+ EP93XX_GPIO_BANK("C", 0x30, 0x34, 40),
+ EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
+ EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
+ EP93XX_GPIO_BANK("F", 0x08, 0x18, 16),
+ EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
+ EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
+};
+
+void __init ep93xx_gpio_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++)
+ gpiochip_add(&ep93xx_gpio_banks[i].chip);
+}
#include <linux/clk.h>
#include <linux/mutex.h>
-#include <asm/semaphore.h>
#include <asm/hardware/icst525.h>
#include "clock.h"
xtime.tv_sec = __raw_readl(rtc_base + RTC_DR);
ret = request_irq(dev->irq[0], arm_rtc_interrupt, IRQF_DISABLED,
- "rtc-pl030", dev);
+ "rtc-pl030", NULL);
if (ret)
goto map_out;
Say Y here if you want to run your kernel on the Thecus n2100
NAS appliance.
-config IOP3XX_ATU
- bool "Enable the PCI Controller"
- default y
- help
- Say Y here if you want the IOP to initialize its PCI Controller.
- Say N if the IOP is an add in card, the host system owns the PCI
- bus in this case.
-
config MACH_EM7210
bool "Enable support for the Lanner EM7210"
help
static int __init iq31244_pci_init(void)
{
- if (is_ep80219()) {
- if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
- pci_common_init(&ep80219_pci);
- } else if (machine_is_iq31244()) {
+ if (is_ep80219())
+ pci_common_init(&ep80219_pci);
+ else if (machine_is_iq31244()) {
if (is_80219()) {
printk("note: iq31244 board type has been selected\n");
printk("note: to select ep80219 operation:\n");
printk("\t2/ update boot loader to pass"
" the ep80219 id: %d\n", MACH_TYPE_EP80219);
}
-
- if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
- pci_common_init(&iq31244_pci);
+ pci_common_init(&iq31244_pci);
}
return 0;
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
- .preinit = iop3xx_pci_preinit,
+ .preinit = iop3xx_pci_preinit_cond,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80321_pci_map_irq,
};
Say Y here if you want to run your kernel on the Intel IQ80332
evaluation kit for the IOP332 chipset.
-config IOP3XX_ATU
- bool "Enable the PCI Controller"
- default y
- help
- Say Y here if you want the IOP to initialize its PCI Controller.
- Say N if the IOP is an add in card, the host system owns the PCI
- bus in this case.
-
endmenu
endif
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
- .preinit = iop3xx_pci_preinit,
+ .preinit = iop3xx_pci_preinit_cond,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80331_pci_map_irq,
};
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iop3xx_pci_setup,
- .preinit = iop3xx_pci_preinit,
+ .preinit = iop3xx_pci_preinit_cond,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80332_pci_map_irq,
};
# PCI support is optional
obj-$(CONFIG_PCI) += pci.o
+# LEDs
+obj-$(CONFIG_LEDS) += leds.o
+
# Board-specific support
obj-$(CONFIG_MACH_KS8695) += board-micrel.o
#endif
+/* --------------------------------------------------------------------
+ * LEDs
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_LEDS)
+short ks8695_leds_cpu = -1;
+short ks8695_leds_timer = -1;
+
+void __init ks8695_init_leds(u8 cpu_led, u8 timer_led)
+{
+ /* Enable GPIO to access the LEDs */
+ gpio_direction_output(cpu_led, 1);
+ gpio_direction_output(timer_led, 1);
+
+ ks8695_leds_cpu = cpu_led;
+ ks8695_leds_timer = timer_led;
+}
+#else
+void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {}
+#endif
+
/* -------------------------------------------------------------------- */
/*
--- /dev/null
+/*
+ * LED driver for KS8695-based boards.
+ *
+ * Copyright (C) Andrew Victor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <asm/mach-types.h>
+#include <asm/leds.h>
+#include <asm/arch/devices.h>
+#include <asm/arch/gpio.h>
+
+
+static inline void ks8695_led_on(unsigned int led)
+{
+ gpio_set_value(led, 0);
+}
+
+static inline void ks8695_led_off(unsigned int led)
+{
+ gpio_set_value(led, 1);
+}
+
+static inline void ks8695_led_toggle(unsigned int led)
+{
+ unsigned long is_off = gpio_get_value(led);
+ if (is_off)
+ ks8695_led_on(led);
+ else
+ ks8695_led_off(led);
+}
+
+
+/*
+ * Handle LED events.
+ */
+static void ks8695_leds_event(led_event_t evt)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ switch(evt) {
+ case led_start: /* System startup */
+ ks8695_led_on(ks8695_leds_cpu);
+ break;
+
+ case led_stop: /* System stop / suspend */
+ ks8695_led_off(ks8695_leds_cpu);
+ break;
+
+#ifdef CONFIG_LEDS_TIMER
+ case led_timer: /* Every 50 timer ticks */
+ ks8695_led_toggle(ks8695_leds_timer);
+ break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+ case led_idle_start: /* Entering idle state */
+ ks8695_led_off(ks8695_leds_cpu);
+ break;
+
+ case led_idle_end: /* Exit idle state */
+ ks8695_led_on(ks8695_leds_cpu);
+ break;
+#endif
+
+ default:
+ break;
+ }
+
+ local_irq_restore(flags);
+}
+
+
+static int __init leds_init(void)
+{
+ if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1))
+ return -ENODEV;
+
+ leds_event = ks8695_leds_event;
+
+ leds_event(led_start);
+ return 0;
+}
+
+__initcall(leds_init);
menu "NS9xxx Implementations"
+config NS9XXX_HAVE_SERIAL8250
+ bool
+
+config PROCESSOR_NS9360
+ bool
+
+config MODULE_CC9P9360
+ bool
+ select PROCESSOR_NS9360
+
+config BOARD_A9M9750DEV
+ select NS9XXX_HAVE_SERIAL8250
+ bool
+
+config BOARD_JSCC9P9360
+ bool
+
config MACH_CC9P9360DEV
bool "ConnectCore 9P 9360 on an A9M9750 Devboard"
- select PROCESSOR_NS9360
+ select MODULE_CC9P9360
select BOARD_A9M9750DEV
help
Say Y here if you are using the Digi ConnectCore 9P 9360
config MACH_CC9P9360JS
bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard"
- select PROCESSOR_NS9360
+ select MODULE_CC9P9360
select BOARD_JSCC9P9360
help
Say Y here if you are using the Digi ConnectCore 9P 9360
on an JSCC9P9360 Development Board.
-config PROCESSOR_NS9360
- bool
-
-config BOARD_A9M9750DEV
- bool
-
-config BOARD_JSCC9P9360
- bool
-
endmenu
endif
-obj-y := irq.o time.o generic.o gpio.o
+obj-y := clock.o generic.o gpio.o irq.o
obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o
obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o
+obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o
+
obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o
obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o
+
+# platform devices
+obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o
-zreladdr-y := 0x108000
+zreladdr-y := 0x8000
params_phys-y := 0x100
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
#include <linux/irq.h>
#include <asm/mach/map.h>
#include <asm/gpio.h>
#include <asm/arch-ns9xxx/board.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
#include <asm/arch-ns9xxx/regs-mem.h>
#include <asm/arch-ns9xxx/regs-bbu.h>
#include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
int i;
if (gpio_request(11, "board a9m9750dev extirq2") == 0)
- ns9xxx_gpio_configure(11, 0, 1);
+ ns9360_gpio_configure(11, 0, 1);
else
- printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_EXT2\n",
+ printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n",
__func__);
for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
set_irq_flags(i, IRQF_VALID);
}
- /* IRQ_EXT2: level sensitive + active low */
+ /* IRQ_NS9XXX_EXT2: level sensitive + active low */
eic = __raw_readl(SYS_EIC(2));
REGSET(eic, SYS_EIC, PLTY, AL);
REGSET(eic, SYS_EIC, LVEDG, LEVEL);
__raw_writel(eic, SYS_EIC(2));
- set_irq_chained_handler(IRQ_EXT2,
+ set_irq_chained_handler(IRQ_NS9XXX_EXT2,
a9m9750dev_fpga_demux_handler);
}
-static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = {
- {
- .iobase = FPGA_UARTA_BASE,
- .membase = (unsigned char*)FPGA_UARTA_BASE,
- .mapbase = FPGA_UARTA_BASE,
- .irq = IRQ_FPGA_UARTA,
- .iotype = UPIO_MEM,
- .uartclk = 18432000,
- .regshift = 0,
- .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
- }, {
- .iobase = FPGA_UARTB_BASE,
- .membase = (unsigned char*)FPGA_UARTB_BASE,
- .mapbase = FPGA_UARTB_BASE,
- .irq = IRQ_FPGA_UARTB,
- .iotype = UPIO_MEM,
- .uartclk = 18432000,
- .regshift = 0,
- .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
- }, {
- .iobase = FPGA_UARTC_BASE,
- .membase = (unsigned char*)FPGA_UARTC_BASE,
- .mapbase = FPGA_UARTC_BASE,
- .irq = IRQ_FPGA_UARTC,
- .iotype = UPIO_MEM,
- .uartclk = 18432000,
- .regshift = 0,
- .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
- }, {
- .iobase = FPGA_UARTD_BASE,
- .membase = (unsigned char*)FPGA_UARTD_BASE,
- .mapbase = FPGA_UARTD_BASE,
- .irq = IRQ_FPGA_UARTD,
- .iotype = UPIO_MEM,
- .uartclk = 18432000,
- .regshift = 0,
- .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
- }, {
- /* end marker */
- },
-};
-
-static struct platform_device board_a9m9750dev_serial_device = {
- .name = "serial8250",
- .dev = {
- .platform_data = board_a9m9750dev_serial8250_port,
- },
-};
-
-static struct platform_device *board_a9m9750dev_devices[] __initdata = {
- &board_a9m9750dev_serial_device,
-};
-
void __init board_a9m9750dev_init_machine(void)
{
u32 reg;
__raw_writel(0x2, MEM_SMOED(0));
__raw_writel(0x6, MEM_SMRD(0));
__raw_writel(0x6, MEM_SMWD(0));
-
- platform_add_devices(board_a9m9750dev_devices,
- ARRAY_SIZE(board_a9m9750dev_devices));
}
--- /dev/null
+/*
+ * arch/arm/mach-ns9xxx/clock.c
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <asm/semaphore.h>
+#include "clock.h"
+
+static LIST_HEAD(clocks);
+static DEFINE_SPINLOCK(clk_lock);
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ struct clk *p, *ret = NULL, *retgen = NULL;
+ unsigned long flags;
+ int idno;
+
+ if (dev == NULL || dev->bus != &platform_bus_type)
+ idno = -1;
+ else
+ idno = to_platform_device(dev)->id;
+
+ spin_lock_irqsave(&clk_lock, flags);
+ list_for_each_entry(p, &clocks, node) {
+ if (strcmp(id, p->name) == 0) {
+ if (p->id == idno) {
+ if (!try_module_get(p->owner))
+ continue;
+ ret = p;
+ break;
+ } else if (p->id == -1)
+ /* remember match with id == -1 in case there is
+ * no clock for idno */
+ retgen = p;
+ }
+ }
+
+ if (!ret && retgen && try_module_get(retgen->owner))
+ ret = retgen;
+
+ if (ret)
+ ++ret->refcount;
+
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return ret ? ret : ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+void clk_put(struct clk *clk)
+{
+ module_put(clk->owner);
+ --clk->refcount;
+}
+EXPORT_SYMBOL(clk_put);
+
+static int clk_enable_unlocked(struct clk *clk)
+{
+ int ret = 0;
+ if (clk->parent) {
+ ret = clk_enable_unlocked(clk->parent);
+ if (ret)
+ return ret;
+ }
+
+ if (clk->usage++ == 0 && clk->endisable)
+ ret = clk->endisable(clk, 1);
+
+ return ret;
+}
+
+int clk_enable(struct clk *clk)
+{
+ int ret;
+ unsigned long flags;
+
+ spin_lock_irqsave(&clk_lock, flags);
+
+ ret = clk_enable_unlocked(clk);
+
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+static void clk_disable_unlocked(struct clk *clk)
+{
+ if (--clk->usage == 0 && clk->endisable)
+ clk->endisable(clk, 0);
+
+ if (clk->parent)
+ clk_disable_unlocked(clk->parent);
+}
+
+void clk_disable(struct clk *clk)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clk_lock, flags);
+
+ clk_disable_unlocked(clk);
+
+ spin_unlock_irqrestore(&clk_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ if (clk->get_rate)
+ return clk->get_rate(clk);
+
+ if (clk->rate)
+ return clk->rate;
+
+ if (clk->parent)
+ return clk_get_rate(clk->parent);
+
+ return 0;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+int clk_register(struct clk *clk)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clk_lock, flags);
+
+ list_add(&clk->node, &clocks);
+
+ if (clk->parent)
+ ++clk->parent->refcount;
+
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return 0;
+}
+
+int clk_unregister(struct clk *clk)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&clk_lock, flags);
+
+ if (clk->usage || clk->refcount)
+ ret = -EBUSY;
+ else
+ list_del(&clk->node);
+
+ if (clk->parent)
+ --clk->parent->refcount;
+
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return ret;
+}
+
+#if defined CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static int clk_debugfs_show(struct seq_file *s, void *null)
+{
+ unsigned long flags;
+ struct clk *p;
+
+ spin_lock_irqsave(&clk_lock, flags);
+
+ list_for_each_entry(p, &clocks, node)
+ seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n",
+ p->name, p->id, p->usage, p->refcount,
+ p->usage ? clk_get_rate(p) : 0);
+
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return 0;
+}
+
+static int clk_debugfs_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, clk_debugfs_show, NULL);
+}
+
+static struct file_operations clk_debugfs_operations = {
+ .open = clk_debugfs_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static int __init clk_debugfs_init(void)
+{
+ struct dentry *dentry;
+
+ dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL,
+ &clk_debugfs_operations);
+ return IS_ERR(dentry) ? PTR_ERR(dentry) : 0;
+}
+subsys_initcall(clk_debugfs_init);
+
+#endif /* if defined CONFIG_DEBUG_FS */
--- /dev/null
+/*
+ * arch/arm/mach-ns9xxx/clock.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __NS9XXX_CLOCK_H
+#define __NS9XXX_CLOCK_H
+
+#include <linux/list.h>
+
+struct clk {
+ struct module *owner;
+ const char *name;
+ int id;
+
+ struct clk *parent;
+
+ unsigned long rate;
+ int (*endisable)(struct clk *, int enable);
+ unsigned long (*get_rate)(struct clk *);
+
+ struct list_head node;
+ unsigned long refcount;
+ unsigned long usage;
+};
+
+int clk_register(struct clk *clk);
+int clk_unregister(struct clk *clk);
+
+#endif /* ifndef __NS9XXX_CLOCK_H */
/*
* arch/arm/mach-ns9xxx/generic.c
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/memory.h>
-#include <asm/page.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
-#include <asm/arch-ns9xxx/regs-mem.h>
-#include <asm/arch-ns9xxx/board.h>
#include "generic.h"
-static struct map_desc standard_io_desc[] __initdata = {
- { /* BBus */
- .virtual = io_p2v(0x90000000),
- .pfn = __phys_to_pfn(0x90000000),
- .length = 0x00700000,
- .type = MT_DEVICE,
- }, { /* AHB */
- .virtual = io_p2v(0xa0100000),
- .pfn = __phys_to_pfn(0xa0100000),
- .length = 0x00900000,
- .type = MT_DEVICE,
- },
-};
-
-void __init ns9xxx_map_io(void)
-{
- iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
-}
-
void __init ns9xxx_init_machine(void)
{
}
/*
* arch/arm/mach-ns9xxx/generic.h
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
#include <linux/init.h>
void __init ns9xxx_init_irq(void);
-void __init ns9xxx_map_io(void);
void __init ns9xxx_init_machine(void);
-
-extern struct sys_timer ns9xxx_timer;
--- /dev/null
+/*
+ * arch/arm/mach-ns9xxx/gpio-ns9360.c
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/bug.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/arch-ns9xxx/regs-bbu.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+
+#include "gpio-ns9360.h"
+
+static inline int ns9360_valid_gpio(unsigned gpio)
+{
+ return gpio <= 72;
+}
+
+static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio)
+{
+ if (gpio < 56)
+ return BBU_GCONFb1(gpio / 8);
+ else
+ /*
+ * this could be optimised away on
+ * ns9750 only builds, but it isn't ...
+ */
+ return BBU_GCONFb2((gpio - 56) / 8);
+}
+
+static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio)
+{
+ if (gpio < 32)
+ return BBU_GCTRL1;
+ else if (gpio < 64)
+ return BBU_GCTRL2;
+ else
+ /* this could be optimised away on ns9750 only builds */
+ return BBU_GCTRL3;
+}
+
+static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio)
+{
+ if (gpio < 32)
+ return BBU_GSTAT1;
+ else if (gpio < 64)
+ return BBU_GSTAT2;
+ else
+ /* this could be optimised away on ns9750 only builds */
+ return BBU_GSTAT3;
+}
+
+/*
+ * each gpio can serve for 4 different purposes [0..3]. These are called
+ * "functions" and passed in the parameter func. Functions 0-2 are always some
+ * special things, function 3 is GPIO. If func == 3 dir specifies input or
+ * output, and with inv you can enable an inverter (independent of func).
+ */
+int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func)
+{
+ void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio);
+ u32 confval;
+
+ confval = __raw_readl(conf);
+ REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
+ REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
+ REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
+ __raw_writel(confval, conf);
+
+ return 0;
+}
+
+int ns9360_gpio_configure(unsigned gpio, int inv, int func)
+{
+ if (likely(ns9360_valid_gpio(gpio))) {
+ if (func == 3) {
+ printk(KERN_WARNING "use gpio_direction_input "
+ "or gpio_direction_output\n");
+ return -EINVAL;
+ } else
+ return __ns9360_gpio_configure(gpio, 0, inv, func);
+ } else
+ return -EINVAL;
+}
+EXPORT_SYMBOL(ns9360_gpio_configure);
+
+int ns9360_gpio_get_value(unsigned gpio)
+{
+ void __iomem *stat = ns9360_gpio_get_gstataddr(gpio);
+ int ret;
+
+ ret = 1 & (__raw_readl(stat) >> (gpio & 31));
+
+ return ret;
+}
+
+void ns9360_gpio_set_value(unsigned gpio, int value)
+{
+ void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio);
+ u32 ctrlval;
+
+ ctrlval = __raw_readl(ctrl);
+
+ if (value)
+ ctrlval |= 1 << (gpio & 31);
+ else
+ ctrlval &= ~(1 << (gpio & 31));
+
+ __raw_writel(ctrlval, ctrl);
+}
--- /dev/null
+/*
+ * arch/arm/mach-ns9xxx/gpio-ns9360.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func);
+int ns9360_gpio_get_value(unsigned gpio);
+void ns9360_gpio_set_value(unsigned gpio, int value);
/*
* arch/arm/mach-ns9xxx/gpio.c
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
#include <asm/arch-ns9xxx/gpio.h>
#include <asm/arch-ns9xxx/processor.h>
-#include <asm/arch-ns9xxx/regs-bbu.h>
-#include <asm/io.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
#include <asm/bug.h>
#include <asm/types.h>
#include <asm/bitops.h>
+#include "gpio-ns9360.h"
+
#if defined(CONFIG_PROCESSOR_NS9360)
#define GPIO_MAX 72
#elif defined(CONFIG_PROCESSOR_NS9750)
return gpio <= 49;
else
#endif
+ {
BUG();
-}
-
-static inline void __iomem *ns9xxx_gpio_get_gconfaddr(unsigned gpio)
-{
- if (gpio < 56)
- return BBU_GCONFb1(gpio / 8);
- else
- /*
- * this could be optimised away on
- * ns9750 only builds, but it isn't ...
- */
- return BBU_GCONFb2((gpio - 56) / 8);
-}
-
-static inline void __iomem *ns9xxx_gpio_get_gctrladdr(unsigned gpio)
-{
- if (gpio < 32)
- return BBU_GCTRL1;
- else if (gpio < 64)
- return BBU_GCTRL2;
- else
- /* this could be optimised away on ns9750 only builds */
- return BBU_GCTRL3;
-}
-
-static inline void __iomem *ns9xxx_gpio_get_gstataddr(unsigned gpio)
-{
- if (gpio < 32)
- return BBU_GSTAT1;
- else if (gpio < 64)
- return BBU_GSTAT2;
- else
- /* this could be optimised away on ns9750 only builds */
- return BBU_GSTAT3;
+ return 0;
+ }
}
int gpio_request(unsigned gpio, const char *label)
}
EXPORT_SYMBOL(gpio_free);
-/*
- * each gpio can serve for 4 different purposes [0..3]. These are called
- * "functions" and passed in the parameter func. Functions 0-2 are always some
- * special things, function 3 is GPIO. If func == 3 dir specifies input or
- * output, and with inv you can enable an inverter (independent of func).
- */
-static int __ns9xxx_gpio_configure(unsigned gpio, int dir, int inv, int func)
+int gpio_direction_input(unsigned gpio)
{
- void __iomem *conf = ns9xxx_gpio_get_gconfaddr(gpio);
- u32 confval;
- unsigned long flags;
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- confval = __raw_readl(conf);
- REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
- REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
- REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
- __raw_writel(confval, conf);
+ if (likely(ns9xxx_valid_gpio(gpio))) {
+ int ret = -EINVAL;
+ unsigned long flags;
- spin_unlock_irqrestore(&gpio_lock, flags);
+ spin_lock_irqsave(&gpio_lock, flags);
+#if defined(CONFIG_PROCESSOR_NS9360)
+ if (processor_is_ns9360())
+ ret = __ns9360_gpio_configure(gpio, 0, 0, 3);
+ else
+#endif
+ BUG();
- return 0;
-}
+ spin_unlock_irqrestore(&gpio_lock, flags);
-int ns9xxx_gpio_configure(unsigned gpio, int inv, int func)
-{
- if (likely(ns9xxx_valid_gpio(gpio))) {
- if (func == 3) {
- printk(KERN_WARNING "use gpio_direction_input "
- "or gpio_direction_output\n");
- return -EINVAL;
- } else
- return __ns9xxx_gpio_configure(gpio, 0, inv, func);
- } else
- return -EINVAL;
-}
-EXPORT_SYMBOL(ns9xxx_gpio_configure);
+ return ret;
-int gpio_direction_input(unsigned gpio)
-{
- if (likely(ns9xxx_valid_gpio(gpio))) {
- return __ns9xxx_gpio_configure(gpio, 0, 0, 3);
} else
return -EINVAL;
}
int gpio_direction_output(unsigned gpio, int value)
{
if (likely(ns9xxx_valid_gpio(gpio))) {
+ int ret = -EINVAL;
+ unsigned long flags;
+
gpio_set_value(gpio, value);
- return __ns9xxx_gpio_configure(gpio, 1, 0, 3);
+ spin_lock_irqsave(&gpio_lock, flags);
+#if defined(CONFIG_PROCESSOR_NS9360)
+ if (processor_is_ns9360())
+ ret = __ns9360_gpio_configure(gpio, 1, 0, 3);
+ else
+#endif
+ BUG();
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+
+ return ret;
} else
return -EINVAL;
}
int gpio_get_value(unsigned gpio)
{
- void __iomem *stat = ns9xxx_gpio_get_gstataddr(gpio);
- int ret;
-
- ret = 1 & (__raw_readl(stat) >> (gpio & 31));
-
- return ret;
+#if defined(CONFIG_PROCESSOR_NS9360)
+ if (processor_is_ns9360())
+ return ns9360_gpio_get_value(gpio);
+ else
+#endif
+ {
+ BUG();
+ return -EINVAL;
+ }
}
EXPORT_SYMBOL(gpio_get_value);
void gpio_set_value(unsigned gpio, int value)
{
- void __iomem *ctrl = ns9xxx_gpio_get_gctrladdr(gpio);
- u32 ctrlval;
unsigned long flags;
-
spin_lock_irqsave(&gpio_lock, flags);
-
- ctrlval = __raw_readl(ctrl);
-
- if (value)
- ctrlval |= 1 << (gpio & 31);
+#if defined(CONFIG_PROCESSOR_NS9360)
+ if (processor_is_ns9360())
+ ns9360_gpio_set_value(gpio, value);
else
- ctrlval &= ~(1 << (gpio & 31));
-
- __raw_writel(ctrlval, ctrl);
+#endif
+ BUG();
spin_unlock_irqrestore(&gpio_lock, flags);
}
* the Free Software Foundation.
*/
#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
#include <asm/io.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/regs-sys-common.h>
#include <asm/arch-ns9xxx/irqs.h>
#include <asm/arch-ns9xxx/board.h>
#include "generic.h"
+/* simple interrupt prio table: prio(x) < prio(y) <=> x < y */
+#define irq2prio(i) (i)
+#define prio2irq(p) (p)
+
static void ns9xxx_mask_irq(unsigned int irq)
{
/* XXX: better use cpp symbols */
- u32 ic = __raw_readl(SYS_IC(irq / 4));
- ic &= ~(1 << (7 + 8 * (3 - (irq & 3))));
- __raw_writel(ic, SYS_IC(irq / 4));
+ int prio = irq2prio(irq);
+ u32 ic = __raw_readl(SYS_IC(prio / 4));
+ ic &= ~(1 << (7 + 8 * (3 - (prio & 3))));
+ __raw_writel(ic, SYS_IC(prio / 4));
}
static void ns9xxx_ack_irq(unsigned int irq)
static void ns9xxx_unmask_irq(unsigned int irq)
{
/* XXX: better use cpp symbols */
- u32 ic = __raw_readl(SYS_IC(irq / 4));
- ic |= 1 << (7 + 8 * (3 - (irq & 3)));
- __raw_writel(ic, SYS_IC(irq / 4));
+ int prio = irq2prio(irq);
+ u32 ic = __raw_readl(SYS_IC(prio / 4));
+ ic |= 1 << (7 + 8 * (3 - (prio & 3)));
+ __raw_writel(ic, SYS_IC(prio / 4));
}
static struct irq_chip ns9xxx_chip = {
.unmask = ns9xxx_unmask_irq,
};
+#if 0
+#define handle_irq handle_level_irq
+#else
+void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
+{
+ unsigned int cpu = smp_processor_id();
+ struct irqaction *action;
+ irqreturn_t action_ret;
+
+ spin_lock(&desc->lock);
+
+ if (unlikely(desc->status & IRQ_INPROGRESS))
+ goto out_unlock;
+
+ desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
+ kstat_cpu(cpu).irqs[irq]++;
+
+ action = desc->action;
+ if (unlikely(!action || (desc->status & IRQ_DISABLED)))
+ goto out_unlock;
+
+ desc->status |= IRQ_INPROGRESS;
+ spin_unlock(&desc->lock);
+
+ action_ret = handle_IRQ_event(irq, action);
+
+ spin_lock(&desc->lock);
+ desc->status &= ~IRQ_INPROGRESS;
+ if (!(desc->status & IRQ_DISABLED) && desc->chip->ack)
+ desc->chip->ack(irq);
+
+out_unlock:
+ spin_unlock(&desc->lock);
+}
+#define handle_irq handle_prio_irq
+#endif
+
void __init ns9xxx_init_irq(void)
{
int i;
/* disable all IRQs */
for (i = 0; i < 8; ++i)
- __raw_writel((4 * i) << 24 | (4 * i + 1) << 16 |
- (4 * i + 2) << 8 | (4 * i + 3), SYS_IC(i));
+ __raw_writel(prio2irq(4 * i) << 24 |
+ prio2irq(4 * i + 1) << 16 |
+ prio2irq(4 * i + 2) << 8 |
+ prio2irq(4 * i + 3),
+ SYS_IC(i));
- /* simple interrupt prio table:
- * prio(x) < prio(y) <=> x < y
- */
for (i = 0; i < 32; ++i)
- __raw_writel(i, SYS_IVA(i));
+ __raw_writel(prio2irq(i), SYS_IVA(i));
- for (i = IRQ_WATCHDOG; i <= IRQ_EXT3; ++i) {
+ for (i = 0; i <= 31; ++i) {
set_irq_chip(i, &ns9xxx_chip);
- set_irq_handler(i, handle_level_irq);
+ set_irq_handler(i, handle_irq);
set_irq_flags(i, IRQF_VALID);
}
}
/*
* arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+
#include "board-a9m9750dev.h"
#include "generic.h"
static void __init mach_cc9p9360dev_map_io(void)
{
- ns9xxx_map_io();
+ ns9360_map_io();
board_a9m9750dev_map_io();
}
.map_io = mach_cc9p9360dev_map_io,
.init_irq = mach_cc9p9360dev_init_irq,
.init_machine = mach_cc9p9360dev_init_machine,
- .timer = &ns9xxx_timer,
+ .timer = &ns9360_timer,
.boot_params = 0x100,
MACHINE_END
/*
* arch/arm/mach-ns9xxx/mach-cc9p9360js.c
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+
#include "board-jscc9p9360.h"
#include "generic.h"
}
MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
- .map_io = ns9xxx_map_io,
+ .map_io = ns9360_map_io,
.init_irq = ns9xxx_init_irq,
.init_machine = mach_cc9p9360js_init_machine,
- .timer = &ns9xxx_timer,
+ .timer = &ns9360_timer,
.boot_params = 0x100,
MACHINE_END
--- /dev/null
+/*
+ * arch/arm/mach-ns9xxx/plat-serial8250.c
+ *
+ * Copyright (C) 2008 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+
+#include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
+#include <asm/arch-ns9xxx/board.h>
+
+#define DRIVER_NAME "serial8250"
+
+static int __init ns9xxx_plat_serial8250_init(void)
+{
+ struct plat_serial8250_port *pdata;
+ struct platform_device *pdev;
+ int ret = -ENOMEM;
+ int i;
+
+ if (!board_is_a9m9750dev())
+ return -ENODEV;
+
+ pdev = platform_device_alloc(DRIVER_NAME, 0);
+ if (!pdev)
+ goto err;
+
+ pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ goto err;
+
+ pdev->dev.platform_data = pdata;
+
+ pdata[0].iobase = FPGA_UARTA_BASE;
+ pdata[1].iobase = FPGA_UARTB_BASE;
+ pdata[2].iobase = FPGA_UARTC_BASE;
+ pdata[3].iobase = FPGA_UARTD_BASE;
+
+ for (i = 0; i < 4; ++i) {
+ pdata[i].membase = (void __iomem *)pdata[i].iobase;
+ pdata[i].mapbase = pdata[i].iobase;
+ pdata[i].iotype = UPIO_MEM;
+ pdata[i].uartclk = 18432000;
+ pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+ }
+
+ pdata[0].irq = IRQ_FPGA_UARTA;
+ pdata[1].irq = IRQ_FPGA_UARTB;
+ pdata[2].irq = IRQ_FPGA_UARTC;
+ pdata[3].irq = IRQ_FPGA_UARTD;
+
+ ret = platform_device_add(pdev);
+ if (ret) {
+err:
+ platform_device_put(pdev);
+
+ printk(KERN_WARNING "Could not add %s (errno=%d)\n",
+ DRIVER_NAME, ret);
+ }
+
+ return 0;
+}
+
+arch_initcall(ns9xxx_plat_serial8250_init);
--- /dev/null
+/*
+ * arch/arm/mach-ns9xxx/processor-ns9360.c
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
+
+void ns9360_reset(char mode)
+{
+ u32 reg;
+
+ reg = __raw_readl(SYS_PLL) >> 16;
+ REGSET(reg, SYS_PLL, SWC, YES);
+ __raw_writel(reg, SYS_PLL);
+}
+
+#define CRYSTAL 29491200 /* Hz */
+unsigned long ns9360_systemclock(void)
+{
+ u32 pll = __raw_readl(SYS_PLL);
+ return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
+ >> REGGETIM(pll, SYS_PLL, FS);
+}
+
+static struct map_desc ns9360_io_desc[] __initdata = {
+ { /* BBus */
+ .virtual = io_p2v(0x90000000),
+ .pfn = __phys_to_pfn(0x90000000),
+ .length = 0x00700000,
+ .type = MT_DEVICE,
+ }, { /* AHB */
+ .virtual = io_p2v(0xa0100000),
+ .pfn = __phys_to_pfn(0xa0100000),
+ .length = 0x00900000,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init ns9360_map_io(void)
+{
+ iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc));
+}
/*
- * arch/arm/mach-ns9xxx/time.c
+ * arch/arm/mach-ns9xxx/time-ns9360.c
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
#include <linux/clocksource.h>
#include <linux/clockchips.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
-#include <asm/arch-ns9xxx/clock.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
#include <asm/arch-ns9xxx/irqs.h>
#include <asm/arch/system.h>
#include "generic.h"
#define TIMER_CLOCKEVENT 1
static u32 latch;
-static cycle_t ns9xxx_clocksource_read(void)
+static cycle_t ns9360_clocksource_read(void)
{
return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE));
}
-static struct clocksource ns9xxx_clocksource = {
- .name = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE),
+static struct clocksource ns9360_clocksource = {
+ .name = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE),
.rating = 300,
- .read = ns9xxx_clocksource_read,
+ .read = ns9360_clocksource_read,
.mask = CLOCKSOURCE_MASK(32),
.shift = 20,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
-static void ns9xxx_clockevent_setmode(enum clock_event_mode mode,
+static void ns9360_clockevent_setmode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
- switch(mode) {
+ switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
__raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT));
REGSET(tc, SYS_TCx, REN, EN);
__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
}
-static int ns9xxx_clockevent_setnextevent(unsigned long evt,
+static int ns9360_clockevent_setnextevent(unsigned long evt,
struct clock_event_device *clk)
{
u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
return 0;
}
-static struct clock_event_device ns9xxx_clockevent_device = {
- .name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT),
+static struct clock_event_device ns9360_clockevent_device = {
+ .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
.shift = 20,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_mode = ns9xxx_clockevent_setmode,
- .set_next_event = ns9xxx_clockevent_setnextevent,
+ .set_mode = ns9360_clockevent_setmode,
+ .set_next_event = ns9360_clockevent_setnextevent,
};
-static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id)
+static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id)
{
- int timerno = irq - IRQ_TIMER0;
+ int timerno = irq - IRQ_NS9360_TIMER0;
u32 tc;
- struct clock_event_device *evt = &ns9xxx_clockevent_device;
+ struct clock_event_device *evt = &ns9360_clockevent_device;
/* clear irq */
tc = __raw_readl(SYS_TC(timerno));
return IRQ_HANDLED;
}
-static struct irqaction ns9xxx_clockevent_action = {
- .name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT),
+static struct irqaction ns9360_clockevent_action = {
+ .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = ns9xxx_clockevent_handler,
+ .handler = ns9360_clockevent_handler,
};
-static void __init ns9xxx_timer_init(void)
+static void __init ns9360_timer_init(void)
{
int tc;
__raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
- ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(),
- ns9xxx_clocksource.shift);
+ ns9360_clocksource.mult = clocksource_hz2mult(ns9360_cpuclock(),
+ ns9360_clocksource.shift);
- clocksource_register(&ns9xxx_clocksource);
+ clocksource_register(&ns9360_clocksource);
- latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0);
+ latch = SH_DIV(ns9360_cpuclock(), HZ, 0);
tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
REGSET(tc, SYS_TCx, TEN, DIS);
REGSET(tc, SYS_TCx, REN, EN);
__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
- ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(),
- NSEC_PER_SEC, ns9xxx_clockevent_device.shift);
- ns9xxx_clockevent_device.max_delta_ns =
- clockevent_delta2ns(-1, &ns9xxx_clockevent_device);
- ns9xxx_clockevent_device.min_delta_ns =
- clockevent_delta2ns(1, &ns9xxx_clockevent_device);
+ ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(),
+ NSEC_PER_SEC, ns9360_clockevent_device.shift);
+ ns9360_clockevent_device.max_delta_ns =
+ clockevent_delta2ns(-1, &ns9360_clockevent_device);
+ ns9360_clockevent_device.min_delta_ns =
+ clockevent_delta2ns(1, &ns9360_clockevent_device);
- ns9xxx_clockevent_device.cpumask = cpumask_of_cpu(0);
- clockevents_register_device(&ns9xxx_clockevent_device);
+ ns9360_clockevent_device.cpumask = cpumask_of_cpu(0);
+ clockevents_register_device(&ns9360_clockevent_device);
- setup_irq(IRQ_TIMER0 + TIMER_CLOCKEVENT, &ns9xxx_clockevent_action);
+ setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT,
+ &ns9360_clockevent_action);
}
-struct sys_timer ns9xxx_timer = {
- .init = ns9xxx_timer_init,
+struct sys_timer ns9360_timer = {
+ .init = ns9360_timer_init,
};
# Common support
obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o
-obj-$(CONFIG_OMAP_MPU_TIMER) += time.o
+obj-$(CONFIG_OMAP_MPU_TIMER) += time.o
+obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
# Power Management
obj-$(CONFIG_PM) += pm.o sleep.o
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/i2c.h>
+#include <linux/leds.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
&osk5912_mcbsp1_device,
};
+static struct gpio_led tps_leds[] = {
+ /* NOTE: D9 and D2 have hardware blink support.
+ * Also, D9 requires non-battery power.
+ */
+ { .gpio = OSK_TPS_GPIO_LED_D9, .name = "d9", },
+ { .gpio = OSK_TPS_GPIO_LED_D2, .name = "d2", },
+ { .gpio = OSK_TPS_GPIO_LED_D3, .name = "d3", .active_low = 1,
+ .default_trigger = "heartbeat", },
+};
+
+static struct gpio_led_platform_data tps_leds_data = {
+ .num_leds = 3,
+ .leds = tps_leds,
+};
+
+static struct platform_device osk5912_tps_leds = {
+ .name = "leds-gpio",
+ .id = 0,
+ .dev.platform_data = &tps_leds_data,
+};
+
+static int osk_tps_setup(struct i2c_client *client, void *context)
+{
+ /* Set GPIO 1 HIGH to disable VBUS power supply;
+ * OHCI driver powers it up/down as needed.
+ */
+ gpio_request(OSK_TPS_GPIO_USB_PWR_EN, "n_vbus_en");
+ gpio_direction_output(OSK_TPS_GPIO_USB_PWR_EN, 1);
+
+ /* Set GPIO 2 high so LED D3 is off by default */
+ tps65010_set_gpio_out_value(GPIO2, HIGH);
+
+ /* Set GPIO 3 low to take ethernet out of reset */
+ gpio_request(OSK_TPS_GPIO_LAN_RESET, "smc_reset");
+ gpio_direction_output(OSK_TPS_GPIO_LAN_RESET, 0);
+
+ /* GPIO4 is VDD_DSP */
+ gpio_request(OSK_TPS_GPIO_DSP_PWR_EN, "dsp_power");
+ gpio_direction_output(OSK_TPS_GPIO_DSP_PWR_EN, 1);
+ /* REVISIT if DSP support isn't configured, power it off ... */
+
+ /* Let LED1 (D9) blink; leds-gpio may override it */
+ tps65010_set_led(LED1, BLINK);
+
+ /* Set LED2 off by default */
+ tps65010_set_led(LED2, OFF);
+
+ /* Enable LOW_PWR handshake */
+ tps65010_set_low_pwr(ON);
+
+ /* Switch VLDO2 to 3.0V for AIC23 */
+ tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V
+ | TPS_LDO1_ENABLE);
+
+ /* register these three LEDs */
+ osk5912_tps_leds.dev.parent = &client->dev;
+ platform_device_register(&osk5912_tps_leds);
+
+ return 0;
+}
+
+static struct tps65010_board tps_board = {
+ .base = OSK_TPS_GPIO_BASE,
+ .outmask = 0x0f,
+ .setup = osk_tps_setup,
+};
+
static struct i2c_board_info __initdata osk_i2c_board_info[] = {
{
I2C_BOARD_INFO("tps65010", 0x48),
.type = "tps65010",
.irq = OMAP_GPIO_IRQ(OMAP_MPUIO(1)),
+ .platform_data = &tps_board,
+
},
/* TODO when driver support is ready:
* - aic23 audio chip at 0x1a
static void __init osk_init_smc91x(void)
{
- if ((omap_request_gpio(0)) < 0) {
+ if ((gpio_request(0, "smc_irq")) < 0) {
printk("Error requesting gpio 0 for smc91x irq\n");
return;
}
static void __init osk_init_cf(void)
{
omap_cfg_reg(M7_1610_GPIO62);
- if ((omap_request_gpio(62)) < 0) {
+ if ((gpio_request(62, "cf_irq")) < 0) {
printk("Error requesting gpio 62 for CF irq\n");
return;
}
static int mistral_get_pendown_state(void)
{
- return !omap_get_gpio_datain(4);
+ return !gpio_get_value(4);
}
static const struct ads7846_platform_data mistral_ts_info = {
omap_cfg_reg(W14_1610_CCP_DATAP);
/* CAM_PWDN */
- if (omap_request_gpio(11) == 0) {
+ if (gpio_request(11, "cam_pwdn") == 0) {
omap_cfg_reg(N20_1610_GPIO11);
- omap_set_gpio_direction(11, 0 /* out */);
- omap_set_gpio_dataout(11, 0 /* off */);
+ gpio_direction_output(11, 0);
} else
pr_debug("OSK+Mistral: CAM_PWDN is awol\n");
/* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */
+ gpio_request(6, "ts_busy");
+ gpio_direction_input(6);
+
omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
+ gpio_request(4, "ts_int");
+ gpio_direction_input(4);
set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING);
+
spi_register_board_info(mistral_boardinfo,
ARRAY_SIZE(mistral_boardinfo));
/* the sideways button (SW1) is for use as a "wakeup" button */
omap_cfg_reg(N15_1610_MPUIO2);
- if (omap_request_gpio(OMAP_MPUIO(2)) == 0) {
+ if (gpio_request(OMAP_MPUIO(2), "wakeup") == 0) {
int ret = 0;
- omap_set_gpio_direction(OMAP_MPUIO(2), 1);
+
+ gpio_direction_input(OMAP_MPUIO(2));
set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING);
#ifdef CONFIG_PM
/* share the IRQ in case someone wants to use the
IRQF_SHARED, "mistral_wakeup",
&osk_mistral_wake_interrupt);
if (ret != 0) {
- omap_free_gpio(OMAP_MPUIO(2));
+ gpio_free(OMAP_MPUIO(2));
printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n",
ret);
} else
* board, like the touchscreen, EEPROM, and wakeup (!) switch.
*/
omap_cfg_reg(PWL);
- if (omap_request_gpio(2) == 0) {
- omap_set_gpio_direction(2, 0 /* out */);
- omap_set_gpio_dataout(2, 1 /* on */);
- }
+ if (gpio_request(2, "lcd_pwr") == 0)
+ gpio_direction_output(2, 1);
platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices));
}
omap1_map_common_io();
}
-#ifdef CONFIG_TPS65010
-static int __init osk_tps_init(void)
-{
- if (!machine_is_omap_osk())
- return 0;
-
- /* Let LED1 (D9) blink */
- tps65010_set_led(LED1, BLINK);
-
- /* Disable LED 2 (D2) */
- tps65010_set_led(LED2, OFF);
-
- /* Set GPIO 1 HIGH to disable VBUS power supply;
- * OHCI driver powers it up/down as needed.
- */
- tps65010_set_gpio_out_value(GPIO1, HIGH);
-
- /* Set GPIO 2 low to turn on LED D3 */
- tps65010_set_gpio_out_value(GPIO2, HIGH);
-
- /* Set GPIO 3 low to take ethernet out of reset */
- tps65010_set_gpio_out_value(GPIO3, LOW);
-
- /* gpio4 for VDD_DSP */
- /* FIXME send power to DSP iff it's configured */
-
- /* Enable LOW_PWR */
- tps65010_set_low_pwr(ON);
-
- /* Switch VLDO2 to 3.0V for AIC23 */
- tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V
- | TPS_LDO1_ENABLE);
-
- return 0;
-}
-fs_initcall(osk_tps_init);
-#endif
-
MACHINE_START(OMAP_OSK, "TI-OSK")
/* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
.phys_io = 0xfff00000,
/*
* linux/arch/arm/mach-omap1/leds-osk.c
*
- * LED driver for OSK, and optionally Mistral QVGA, boards
+ * LED driver for OSK with optional Mistral QVGA board
*/
#include <linux/init.h>
-#include <linux/workqueue.h>
-#include <linux/i2c/tps65010.h>
#include <asm/hardware.h>
#include <asm/leds.h>
#define LED_STATE_CLAIMED (1 << 1)
static u8 led_state;
-#define GREEN_LED (1 << 0) /* TPS65010 LED1 */
-#define AMBER_LED (1 << 1) /* TPS65010 LED2 */
-#define RED_LED (1 << 2) /* TPS65010 GPIO2 */
#define TIMER_LED (1 << 3) /* Mistral board */
#define IDLE_LED (1 << 4) /* Mistral board */
static u8 hw_led_state;
-/* TPS65010 leds are changed using i2c -- from a task context.
- * Using one of these for the "idle" LED would be impractical...
- */
-#define TPS_LEDS (GREEN_LED | RED_LED | AMBER_LED)
-
-static u8 tps_leds_change;
-
-static void tps_work(struct work_struct *unused)
-{
- for (;;) {
- u8 leds;
-
- local_irq_disable();
- leds = tps_leds_change;
- tps_leds_change = 0;
- local_irq_enable();
-
- if (!leds)
- break;
-
- /* careful: the set_led() value is on/off/blink */
- if (leds & GREEN_LED)
- tps65010_set_led(LED1, !!(hw_led_state & GREEN_LED));
- if (leds & AMBER_LED)
- tps65010_set_led(LED2, !!(hw_led_state & AMBER_LED));
-
- /* the gpio led doesn't have that issue */
- if (leds & RED_LED)
- tps65010_set_gpio_out_value(GPIO2,
- !(hw_led_state & RED_LED));
- }
-}
-
-static DECLARE_WORK(work, tps_work);
-
#ifdef CONFIG_OMAP_OSK_MISTRAL
/* For now, all system indicators require the Mistral board, since that
case led_stop:
led_state &= ~LED_STATE_ENABLED;
hw_led_state = 0;
- /* NOTE: work may still be pending!! */
break;
case led_claim:
#endif /* CONFIG_OMAP_OSK_MISTRAL */
- /* "green" == tps LED1 (leftmost, normally power-good)
- * works only with DC adapter, not on battery power!
- */
- case led_green_on:
- if (led_state & LED_STATE_CLAIMED)
- hw_led_state |= GREEN_LED;
- break;
- case led_green_off:
- if (led_state & LED_STATE_CLAIMED)
- hw_led_state &= ~GREEN_LED;
- break;
-
- /* "amber" == tps LED2 (middle) */
- case led_amber_on:
- if (led_state & LED_STATE_CLAIMED)
- hw_led_state |= AMBER_LED;
- break;
- case led_amber_off:
- if (led_state & LED_STATE_CLAIMED)
- hw_led_state &= ~AMBER_LED;
- break;
-
- /* "red" == LED on tps gpio3 (rightmost) */
- case led_red_on:
- if (led_state & LED_STATE_CLAIMED)
- hw_led_state |= RED_LED;
- break;
- case led_red_off:
- if (led_state & LED_STATE_CLAIMED)
- hw_led_state &= ~RED_LED;
- break;
-
default:
break;
}
leds ^= hw_led_state;
- leds &= TPS_LEDS;
- if (leds && (led_state & LED_STATE_CLAIMED)) {
- tps_leds_change |= leds;
- schedule_work(&work);
- }
done:
local_irq_restore(flags);
*
* OMAP1 pin multiplexing configurations
*
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2003 - 2008 Nokia Corporation
*
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#ifdef CONFIG_OMAP_MUX
+static struct omap_mux_cfg arch_mux_cfg;
+
#ifdef CONFIG_ARCH_OMAP730
-struct pin_config __initdata_or_module omap730_pins[] = {
+static struct pin_config __initdata_or_module omap730_pins[] = {
MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0)
MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0)
MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0)
MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0)
MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0)
};
-#endif
+#define OMAP730_PINS_SZ ARRAY_SIZE(omap730_pins)
+#else
+#define omap730_pins NULL
+#define OMAP730_PINS_SZ 0
+#endif /* CONFIG_ARCH_OMAP730 */
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
-struct pin_config __initdata_or_module omap1xxx_pins[] = {
+static struct pin_config __initdata_or_module omap1xxx_pins[] = {
/*
* description mux mode mux pull pull pull pu_pd pu dbg
* reg offset mode reg bit ena reg
MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0)
MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0)
MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
-
};
+#define OMAP1XXX_PINS_SZ ARRAY_SIZE(omap1xxx_pins)
+#else
+#define omap1xxx_pins NULL
+#define OMAP1XXX_PINS_SZ 0
#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
-int __init omap1_mux_init(void)
+int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
{
-
-#ifdef CONFIG_ARCH_OMAP730
- omap_mux_register(omap730_pins, ARRAY_SIZE(omap730_pins));
+ static DEFINE_SPINLOCK(mux_spin_lock);
+ unsigned long flags;
+ unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
+ pull_orig = 0, pull = 0;
+ unsigned int mask, warn = 0;
+
+ /* Check the mux register in question */
+ if (cfg->mux_reg) {
+ unsigned tmp1, tmp2;
+
+ spin_lock_irqsave(&mux_spin_lock, flags);
+ reg_orig = omap_readl(cfg->mux_reg);
+
+ /* The mux registers always seem to be 3 bits long */
+ mask = (0x7 << cfg->mask_offset);
+ tmp1 = reg_orig & mask;
+ reg = reg_orig & ~mask;
+
+ tmp2 = (cfg->mask << cfg->mask_offset);
+ reg |= tmp2;
+
+ if (tmp1 != tmp2)
+ warn = 1;
+
+ omap_writel(reg, cfg->mux_reg);
+ spin_unlock_irqrestore(&mux_spin_lock, flags);
+ }
+
+ /* Check for pull up or pull down selection on 1610 */
+ if (!cpu_is_omap15xx()) {
+ if (cfg->pu_pd_reg && cfg->pull_val) {
+ spin_lock_irqsave(&mux_spin_lock, flags);
+ pu_pd_orig = omap_readl(cfg->pu_pd_reg);
+ mask = 1 << cfg->pull_bit;
+
+ if (cfg->pu_pd_val) {
+ if (!(pu_pd_orig & mask))
+ warn = 1;
+ /* Use pull up */
+ pu_pd = pu_pd_orig | mask;
+ } else {
+ if (pu_pd_orig & mask)
+ warn = 1;
+ /* Use pull down */
+ pu_pd = pu_pd_orig & ~mask;
+ }
+ omap_writel(pu_pd, cfg->pu_pd_reg);
+ spin_unlock_irqrestore(&mux_spin_lock, flags);
+ }
+ }
+
+ /* Check for an associated pull down register */
+ if (cfg->pull_reg) {
+ spin_lock_irqsave(&mux_spin_lock, flags);
+ pull_orig = omap_readl(cfg->pull_reg);
+ mask = 1 << cfg->pull_bit;
+
+ if (cfg->pull_val) {
+ if (pull_orig & mask)
+ warn = 1;
+ /* Low bit = pull enabled */
+ pull = pull_orig & ~mask;
+ } else {
+ if (!(pull_orig & mask))
+ warn = 1;
+ /* High bit = pull disabled */
+ pull = pull_orig | mask;
+ }
+
+ omap_writel(pull, cfg->pull_reg);
+ spin_unlock_irqrestore(&mux_spin_lock, flags);
+ }
+
+ if (warn) {
+#ifdef CONFIG_OMAP_MUX_WARNINGS
+ printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
#endif
-
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
- omap_mux_register(omap1xxx_pins, ARRAY_SIZE(omap1xxx_pins));
+ }
+
+#ifdef CONFIG_OMAP_MUX_DEBUG
+ if (cfg->debug || warn) {
+ printk("MUX: Setting register %s\n", cfg->name);
+ printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
+ cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
+
+ if (!cpu_is_omap15xx()) {
+ if (cfg->pu_pd_reg && cfg->pull_val) {
+ printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
+ cfg->pu_pd_name, cfg->pu_pd_reg,
+ pu_pd_orig, pu_pd);
+ }
+ }
+
+ if (cfg->pull_reg)
+ printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
+ cfg->pull_name, cfg->pull_reg, pull_orig, pull);
+ }
#endif
+#ifdef CONFIG_OMAP_MUX_ERRORS
+ return warn ? -ETXTBSY : 0;
+#else
return 0;
+#endif
+}
+
+int __init omap1_mux_init(void)
+{
+ if (cpu_is_omap730()) {
+ arch_mux_cfg.pins = omap730_pins;
+ arch_mux_cfg.size = OMAP730_PINS_SZ;
+ arch_mux_cfg.cfg_reg = omap1_cfg_reg;
+ }
+
+ if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+ arch_mux_cfg.pins = omap1xxx_pins;
+ arch_mux_cfg.size = OMAP1XXX_PINS_SZ;
+ arch_mux_cfg.cfg_reg = omap1_cfg_reg;
+ }
+
+ return omap_mux_register(&arch_mux_cfg);
}
#endif
#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
#define OMAP_MPU_TIMER_OFFSET 0x100
-/* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
- * converted to use kHz by Kevin Hilman */
-/* convert from cycles(64bits) => nanoseconds (64bits)
- * basic equation:
- * ns = cycles / (freq / ns_per_sec)
- * ns = cycles * (ns_per_sec / freq)
- * ns = cycles * (10^9 / (cpu_khz * 10^3))
- * ns = cycles * (10^6 / cpu_khz)
- *
- * Then we use scaling math (suggested by george at mvista.com) to get:
- * ns = cycles * (10^6 * SC / cpu_khz / SC
- * ns = cycles * cyc2ns_scale / SC
- *
- * And since SC is a constant power of two, we can convert the div
- * into a shift.
- * -johnstul at us.ibm.com "math is hard, lets go shopping!"
- */
-static unsigned long cyc2ns_scale;
-#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
-
-static inline void set_cyc2ns_scale(unsigned long cpu_khz)
-{
- cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
-}
-
-static inline unsigned long long cycles_2_ns(unsigned long long cyc)
-{
- return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
-}
-
-
typedef struct {
u32 cntl; /* CNTL_TIMER, R/W */
u32 load_tim; /* LOAD_TIM, W */
static __init void omap_init_mpu_timer(unsigned long rate)
{
- set_cyc2ns_scale(rate / 1000);
-
setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
printk(err, clocksource_mpu.name);
}
-
-/*
- * Scheduler clock - returns current time in nanosec units.
- */
-unsigned long long sched_clock(void)
-{
- unsigned long ticks = 0 - omap_mpu_timer_read(1);
- unsigned long long ticks64;
-
- ticks64 = omap_mpu_timer2_overflows;
- ticks64 <<= 32;
- ticks64 |= ticks;
-
- return cycles_2_ns(ticks64);
-}
-
/*
* ---------------------------------------------------------------------------
* Timer initialization
/*
- * linux/arch/arm/plat-omap/timer32k.c
+ * linux/arch/arm/mach-omap1/timer32k.c
*
* OMAP 32K Timer
*
#if defined(CONFIG_ARCH_OMAP16XX)
#define TIMER_32K_SYNCHRONIZED 0xfffbc410
-#elif defined(CONFIG_ARCH_OMAP24XX)
-#define TIMER_32K_SYNCHRONIZED (OMAP24XX_32KSYNCT_BASE + 0x10)
#else
#error OMAP 32KHz timer does not currently work on 15XX!
#endif
#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
(((nr_jiffies) * (clock_rate)) / HZ)
-#if defined(CONFIG_ARCH_OMAP1)
-
static inline void omap_32k_timer_write(int val, int reg)
{
omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
#define omap_32k_timer_ack_irq()
-#elif defined(CONFIG_ARCH_OMAP2)
-
-static struct omap_dm_timer *gptimer;
-
-static inline void omap_32k_timer_start(unsigned long load_val)
-{
- omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
- omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
- omap_dm_timer_start(gptimer);
-}
-
-static inline void omap_32k_timer_stop(void)
+static int omap_32k_timer_set_next_event(unsigned long delta,
+ struct clock_event_device *dev)
{
- omap_dm_timer_stop(gptimer);
-}
+ omap_32k_timer_start(delta);
-static inline void omap_32k_timer_ack_irq(void)
-{
- u32 status = omap_dm_timer_read_status(gptimer);
- omap_dm_timer_write_status(gptimer, status);
+ return 0;
}
-#endif
-
static void omap_32k_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
static struct clock_event_device clockevent_32k_timer = {
.name = "32k-timer",
- .features = CLOCK_EVT_FEAT_PERIODIC,
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
+ .set_next_event = omap_32k_timer_set_next_event,
.set_mode = omap_32k_timer_set_mode,
};
return omap_readl(TIMER_32K_SYNCHRONIZED);
}
-/*
- * Rounds down to nearest usec. Note that this will overflow for larger values.
- */
-static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
-{
- return (ticks_32k * 5*5*5*5*5*5) >> 9;
-}
-
-/*
- * Rounds down to nearest nsec.
- */
-static inline unsigned long long
-omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
-{
- return (unsigned long long) ticks_32k * 1000 * 5*5*5*5*5*5 >> 9;
-}
-
-/*
- * Returns current time from boot in nsecs. It's OK for this to wrap
- * around for now, as it's just a relative time stamp.
- */
-unsigned long long sched_clock(void)
-{
- return omap_32k_ticks_to_nsecs(omap_32k_sync_timer_read());
-}
-
static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &clockevent_32k_timer;
static __init void omap_init_32k_timer(void)
{
- if (cpu_class_is_omap1())
- setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
-
-#ifdef CONFIG_ARCH_OMAP2
- /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
- if (cpu_is_omap24xx()) {
- gptimer = omap_dm_timer_request_specific(1);
- BUG_ON(gptimer == NULL);
-
- omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
- setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
- omap_dm_timer_set_int_enable(gptimer,
- OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
- OMAP_TIMER_INT_MATCH);
- }
-#endif
+ setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
NSEC_PER_SEC,
#
# Common support
-obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
- serial.o gpmc.o
-
-obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
+obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \
+ devices.o serial.o gpmc.o timer-gp.o
# Power Management
-obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o
+obj-$(CONFIG_PM) += pm.o sleep.o
+
+# Clock framework
+obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
+obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
#include <asm/arch/board.h>
#include <asm/arch/common.h>
#include <asm/arch/gpmc.h>
-#include "prcm-regs.h"
#include <asm/io.h>
int eth_cs;
unsigned long cs_mem_base;
unsigned int rate;
- struct clk *l3ck;
+ struct clk *gpmc_fck;
eth_cs = SDP2430_SMC91X_CS;
- l3ck = clk_get(NULL, "core_l3_ck");
- if (IS_ERR(l3ck))
- rate = 100000000;
- else
- rate = clk_get_rate(l3ck);
+ gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
+ if (IS_ERR(gpmc_fck)) {
+ WARN_ON(1);
+ return;
+ }
+
+ clk_enable(gpmc_fck);
+ rate = clk_get_rate(gpmc_fck);
/* Make sure CS1 timings are correct, for 2430 always muxed */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
- return;
+ goto out;
}
sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300;
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
OMAP24XX_ETHR_GPIO_IRQ);
gpmc_cs_free(eth_cs);
- return;
+ goto out;
}
omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
+out:
+ clk_disable(gpmc_fck);
+ clk_put(gpmc_fck);
}
static void __init omap_2430sdp_init_irq(void)
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/leds.h>
+#include <linux/err.h>
+#include <linux/clk.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/arch/board.h>
#include <asm/arch/common.h>
#include <asm/arch/gpmc.h>
-#include "prcm-regs.h"
+#include <asm/arch/control.h>
/* LED & Switch macros */
#define LED0_GPIO13 13
{
unsigned long base;
+ unsigned int rate;
+ struct clk *gpmc_fck;
+ int eth_cs;
+
+ gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
+ if (IS_ERR(gpmc_fck)) {
+ WARN_ON(1);
+ return;
+ }
+
+ clk_enable(gpmc_fck);
+ rate = clk_get_rate(gpmc_fck);
+
+ eth_cs = APOLLON_ETH_CS;
+
/* Make sure CS1 timings are correct */
- GPMC_CONFIG1_1 = 0x00011203;
- GPMC_CONFIG2_1 = 0x001f1f01;
- GPMC_CONFIG3_1 = 0x00080803;
- GPMC_CONFIG4_1 = 0x1c091c09;
- GPMC_CONFIG5_1 = 0x041f1f1f;
- GPMC_CONFIG6_1 = 0x000004c4;
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
+
+ if (rate >= 160000000) {
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+ } else if (rate >= 130000000) {
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+ } else {/* rate = 100000000 */
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
+ }
if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {
printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");
- return;
+ goto out;
}
apollon_smc91x_resources[0].start = base + 0x300;
apollon_smc91x_resources[0].end = base + 0x30f;
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
APOLLON_ETHR_GPIO_IRQ);
gpmc_cs_free(APOLLON_ETH_CS);
- return;
+ goto out;
}
omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1);
+
+out:
+ clk_disable(gpmc_fck);
+ clk_put(gpmc_fck);
}
static void __init omap_apollon_init_irq(void)
static void __init omap_apollon_init(void)
{
+ u32 v;
+
apollon_led_init();
apollon_sw_init();
apollon_flash_init();
omap_cfg_reg(W19_24XX_SYS_NIRQ);
/* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
- CONTROL_DEVCONF |= (1 << 24);
+ v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+ v |= (1 << 24);
+ omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
/*
* Make sure the serial ports are muxed on at this point.
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/input.h>
+#include <linux/err.h>
+#include <linux/clk.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
+#include <asm/arch/control.h>
#include <asm/arch/gpio.h>
#include <asm/arch/gpioexpander.h>
#include <asm/arch/mux.h>
#include <asm/arch/keypad.h>
#include <asm/arch/menelaus.h>
#include <asm/arch/dma.h>
-#include "prcm-regs.h"
+#include <asm/arch/gpmc.h>
#include <asm/io.h>
+#define H4_FLASH_CS 0
+#define H4_SMC91X_CS 1
+
static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
};
static struct resource h4_flash_resource = {
- .start = H4_CS0_BASE,
- .end = H4_CS0_BASE + SZ_64M - 1,
.flags = IORESOURCE_MEM,
};
&h4_lcd_device,
};
+/* 2420 Sysboot setup (2430 is different) */
+static u32 get_sysboot_value(void)
+{
+ return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &
+ (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
+ OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
+ OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
+}
+
+/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
+ *
+ * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
+ * correctly. The macro needs to look at production_id not just hawkeye.
+ */
+static u32 is_gpmc_muxed(void)
+{
+ u32 mux;
+ mux = get_sysboot_value();
+ if ((mux & 0xF) == 0xd)
+ return 1; /* NAND config (could be either) */
+ if (mux & 0x2) /* if mux'ed */
+ return 1;
+ else
+ return 0;
+}
+
static inline void __init h4_init_debug(void)
{
+ int eth_cs;
+ unsigned long cs_mem_base;
+ unsigned int muxed, rate;
+ struct clk *gpmc_fck;
+
+ eth_cs = H4_SMC91X_CS;
+
+ gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
+ if (IS_ERR(gpmc_fck)) {
+ WARN_ON(1);
+ return;
+ }
+
+ clk_enable(gpmc_fck);
+ rate = clk_get_rate(gpmc_fck);
+ clk_disable(gpmc_fck);
+ clk_put(gpmc_fck);
+
+ if (is_gpmc_muxed())
+ muxed = 0x200;
+ else
+ muxed = 0;
+
/* Make sure CS1 timings are correct */
- GPMC_CONFIG1_1 = 0x00011200;
- GPMC_CONFIG2_1 = 0x001f1f01;
- GPMC_CONFIG3_1 = 0x00080803;
- GPMC_CONFIG4_1 = 0x1c091c09;
- GPMC_CONFIG5_1 = 0x041f1f1f;
- GPMC_CONFIG6_1 = 0x000004c4;
- GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,
+ 0x00011000 | muxed);
+
+ if (rate >= 160000000) {
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+ } else if (rate >= 130000000) {
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+ } else {/* rate = 100000000 */
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
+ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
+ }
+
+ if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
+ printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
+ goto out;
+ }
+
udelay(100);
omap_cfg_reg(M15_24XX_GPIO92);
if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0)
gpmc_cs_free(eth_cs);
+
+out:
+ clk_disable(gpmc_fck);
+ clk_put(gpmc_fck);
+}
+
+static void __init h4_init_flash(void)
+{
+ unsigned long base;
+
+ if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
+ printk("Can't request GPMC CS for flash\n");
+ return;
+ }
+ h4_flash_resource.start = base;
+ h4_flash_resource.end = base + SZ_64M - 1;
}
static void __init omap_h4_init_irq(void)
omap2_init_common_hw();
omap_init_irq();
omap_gpio_init();
+ h4_init_flash();
}
static struct omap_uart_config h4_uart_config __initdata = {
/*
* linux/arch/arm/mach-omap2/clock.c
*
- * Copyright (C) 2005 Texas Instruments Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Created for OMAP2.
- *
- * Cleaned up and modified to use omap shared clock framework by
- * Tony Lindgren <tony@atomide.com>
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2008 Nokia Corporation
*
- * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+#undef DEBUG
+
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
+#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
+#include <asm/arch/cpu.h>
#include <asm/div64.h>
-#include "prcm-regs.h"
#include "memory.h"
+#include "sdrc.h"
#include "clock.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
-#undef DEBUG
-
-//#define DOWN_VARIABLE_DPLL 1 /* Experimental */
+#define MAX_CLOCK_ENABLE_WAIT 100000
-static struct prcm_config *curr_prcm_set;
-static u32 curr_perf_level = PRCM_FULL_SPEED;
-static struct clk *vclk;
-static struct clk *sclk;
+u8 cpu_mask;
/*-------------------------------------------------------------------------
* Omap2 specific clock functions
*-------------------------------------------------------------------------*/
-/* Recalculate SYST_CLK */
-static void omap2_sys_clk_recalc(struct clk * clk)
+/**
+ * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
+ * @clk: OMAP clock struct ptr to use
+ *
+ * Given a pointer to a source-selectable struct clk, read the hardware
+ * register and determine what its parent is currently set to. Update the
+ * clk->parent field with the appropriate clk ptr.
+ */
+void omap2_init_clksel_parent(struct clk *clk)
{
- u32 div = PRCM_CLKSRC_CTRL;
- div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
- div >>= clk->rate_offset;
- clk->rate = (clk->parent->rate / div);
- propagate_rate(clk);
+ const struct clksel *clks;
+ const struct clksel_rate *clkr;
+ u32 r, found = 0;
+
+ if (!clk->clksel)
+ return;
+
+ r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+ r >>= __ffs(clk->clksel_mask);
+
+ for (clks = clk->clksel; clks->parent && !found; clks++) {
+ for (clkr = clks->rates; clkr->div && !found; clkr++) {
+ if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
+ if (clk->parent != clks->parent) {
+ pr_debug("clock: inited %s parent "
+ "to %s (was %s)\n",
+ clk->name, clks->parent->name,
+ ((clk->parent) ?
+ clk->parent->name : "NULL"));
+ clk->parent = clks->parent;
+ };
+ found = 1;
+ }
+ }
+ }
+
+ if (!found)
+ printk(KERN_ERR "clock: init parent: could not find "
+ "regval %0x for clock %s\n", r, clk->name);
+
+ return;
}
-static u32 omap2_get_dpll_rate(struct clk * tclk)
+/* Returns the DPLL rate */
+u32 omap2_get_dpll_rate(struct clk *clk)
{
long long dpll_clk;
- int dpll_mult, dpll_div, amult;
+ u32 dpll_mult, dpll_div, dpll;
+ const struct dpll_data *dd;
+
+ dd = clk->dpll_data;
+ /* REVISIT: What do we return on error? */
+ if (!dd)
+ return 0;
+
+ dpll = __raw_readl(dd->mult_div1_reg);
+ dpll_mult = dpll & dd->mult_mask;
+ dpll_mult >>= __ffs(dd->mult_mask);
+ dpll_div = dpll & dd->div1_mask;
+ dpll_div >>= __ffs(dd->div1_mask);
- dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */
- dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
- dpll_clk = (long long)tclk->parent->rate * dpll_mult;
+ dpll_clk = (long long)clk->parent->rate * dpll_mult;
do_div(dpll_clk, dpll_div + 1);
- amult = CM_CLKSEL2_PLL & 0x3;
- dpll_clk *= amult;
return dpll_clk;
}
-static void omap2_followparent_recalc(struct clk *clk)
-{
- followparent_recalc(clk);
-}
-
-static void omap2_propagate_rate(struct clk * clk)
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+void omap2_fixed_divisor_recalc(struct clk *clk)
{
- if (!(clk->flags & RATE_FIXED))
- clk->rate = clk->parent->rate;
+ WARN_ON(!clk->fixed_div);
- propagate_rate(clk);
-}
+ clk->rate = clk->parent->rate / clk->fixed_div;
-static void omap2_set_osc_ck(int enable)
-{
- if (enable)
- PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
- else
- PRCM_CLKSRC_CTRL |= 0x3 << 3;
+ if (clk->flags & RATE_PROPAGATES)
+ propagate_rate(clk);
}
-/* Enable an APLL if off */
-static void omap2_clk_fixed_enable(struct clk *clk)
+/**
+ * omap2_wait_clock_ready - wait for clock to enable
+ * @reg: physical address of clock IDLEST register
+ * @mask: value to mask against to determine if the clock is active
+ * @name: name of the clock (for printk)
+ *
+ * Returns 1 if the clock enabled in time, or 0 if it failed to enable
+ * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
+ */
+int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
{
- u32 cval, i=0;
+ int i = 0;
+ int ena = 0;
- if (clk->enable_bit == 0xff) /* Parent will do it */
- return;
+ /*
+ * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+ * 34xx reverses this, just to keep us on our toes
+ */
+ if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
+ ena = mask;
+ } else if (cpu_mask & RATE_IN_343X) {
+ ena = 0;
+ }
- cval = CM_CLKEN_PLL;
+ /* Wait for lock */
+ while (((__raw_readl(reg) & mask) != ena) &&
+ (i++ < MAX_CLOCK_ENABLE_WAIT)) {
+ udelay(1);
+ }
- if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
- return;
+ if (i < MAX_CLOCK_ENABLE_WAIT)
+ pr_debug("Clock %s stable after %d loops\n", name, i);
+ else
+ printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
+ name, MAX_CLOCK_ENABLE_WAIT);
- cval &= ~(0x3 << clk->enable_bit);
- cval |= (0x3 << clk->enable_bit);
- CM_CLKEN_PLL = cval;
- if (clk == &apll96_ck)
- cval = (1 << 8);
- else if (clk == &apll54_ck)
- cval = (1 << 6);
+ return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
+};
- while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */
- ++i;
- udelay(1);
- if (i == 100000) {
- printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
- break;
- }
- }
-}
+/*
+ * Note: We don't need special code here for INVERT_ENABLE
+ * for the time being since INVERT_ENABLE only applies to clocks enabled by
+ * CM_CLKEN_PLL
+ */
static void omap2_clk_wait_ready(struct clk *clk)
{
- unsigned long reg, other_reg, st_reg;
+ void __iomem *reg, *other_reg, *st_reg;
u32 bit;
- int i;
-
- reg = (unsigned long) clk->enable_reg;
- if (reg == (unsigned long) &CM_FCLKEN1_CORE ||
- reg == (unsigned long) &CM_FCLKEN2_CORE)
- other_reg = (reg & ~0xf0) | 0x10;
- else if (reg == (unsigned long) &CM_ICLKEN1_CORE ||
- reg == (unsigned long) &CM_ICLKEN2_CORE)
- other_reg = (reg & ~0xf0) | 0x00;
+
+ /*
+ * REVISIT: This code is pretty ugly. It would be nice to generalize
+ * it and pull it into struct clk itself somehow.
+ */
+ reg = clk->enable_reg;
+ if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
+ (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
+ other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
+ else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
+ (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
+ other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
else
return;
+ /* REVISIT: What are the appropriate exclusions for 34XX? */
/* No check for DSS or cam clocks */
- if ((reg & 0x0f) == 0) {
- if (clk->enable_bit <= 1 || clk->enable_bit == 31)
+ if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
+ if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
+ clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
+ clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
return;
}
+ /* REVISIT: What are the appropriate exclusions for 34XX? */
+ /* OMAP3: ignore DSS-mod clocks */
+ if (cpu_is_omap34xx() &&
+ (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0)))
+ return;
+
/* Check if both functional and interface clocks
* are running. */
bit = 1 << clk->enable_bit;
if (!(__raw_readl(other_reg) & bit))
return;
- st_reg = (other_reg & ~0xf0) | 0x20;
- i = 0;
- while (!(__raw_readl(st_reg) & bit)) {
- i++;
- if (i == 100000) {
- printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
- break;
- }
- }
- if (i)
- pr_debug("Clock %s stable after %d loops\n", clk->name, i);
+ st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
+
+ omap2_wait_clock_ready(st_reg, bit, clk->name);
}
/* Enables clock without considering parent dependencies or use count
* REVISIT: Maybe change this to use clk->enable like on omap1?
*/
-static int _omap2_clk_enable(struct clk * clk)
+int _omap2_clk_enable(struct clk *clk)
{
u32 regval32;
- if (clk->flags & ALWAYS_ENABLED)
+ if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
return 0;
- if (unlikely(clk == &osc_ck)) {
- omap2_set_osc_ck(1);
- return 0;
- }
+ if (clk->enable)
+ return clk->enable(clk);
if (unlikely(clk->enable_reg == 0)) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
clk->name);
- return 0;
- }
-
- if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
- omap2_clk_fixed_enable(clk);
- return 0;
+ return 0; /* REVISIT: -EINVAL */
}
regval32 = __raw_readl(clk->enable_reg);
- regval32 |= (1 << clk->enable_bit);
+ if (clk->flags & INVERT_ENABLE)
+ regval32 &= ~(1 << clk->enable_bit);
+ else
+ regval32 |= (1 << clk->enable_bit);
__raw_writel(regval32, clk->enable_reg);
wmb();
return 0;
}
-/* Stop APLL */
-static void omap2_clk_fixed_disable(struct clk *clk)
-{
- u32 cval;
-
- if(clk->enable_bit == 0xff) /* let parent off do it */
- return;
-
- cval = CM_CLKEN_PLL;
- cval &= ~(0x3 << clk->enable_bit);
- CM_CLKEN_PLL = cval;
-}
-
/* Disables clock without considering parent dependencies or use count */
-static void _omap2_clk_disable(struct clk *clk)
+void _omap2_clk_disable(struct clk *clk)
{
u32 regval32;
- if (unlikely(clk == &osc_ck)) {
- omap2_set_osc_ck(0);
+ if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
return;
- }
- if (clk->enable_reg == 0)
+ if (clk->disable) {
+ clk->disable(clk);
return;
+ }
- if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
- omap2_clk_fixed_disable(clk);
+ if (clk->enable_reg == 0) {
+ /*
+ * 'Independent' here refers to a clock which is not
+ * controlled by its parent.
+ */
+ printk(KERN_ERR "clock: clk_disable called on independent "
+ "clock %s which has no enable_reg\n", clk->name);
return;
}
regval32 = __raw_readl(clk->enable_reg);
- regval32 &= ~(1 << clk->enable_bit);
+ if (clk->flags & INVERT_ENABLE)
+ regval32 |= (1 << clk->enable_bit);
+ else
+ regval32 &= ~(1 << clk->enable_bit);
__raw_writel(regval32, clk->enable_reg);
wmb();
}
-static int omap2_clk_enable(struct clk *clk)
+void omap2_clk_disable(struct clk *clk)
+{
+ if (clk->usecount > 0 && !(--clk->usecount)) {
+ _omap2_clk_disable(clk);
+ if (likely((u32)clk->parent))
+ omap2_clk_disable(clk->parent);
+ }
+}
+
+int omap2_clk_enable(struct clk *clk)
{
int ret = 0;
return ret;
}
-static void omap2_clk_disable(struct clk *clk)
-{
- if (clk->usecount > 0 && !(--clk->usecount)) {
- _omap2_clk_disable(clk);
- if (likely((u32)clk->parent))
- omap2_clk_disable(clk->parent);
- }
-}
-
-/*
- * Uses the current prcm set to tell if a rate is valid.
- * You can go slower, but not faster within a given rate set.
- */
-static u32 omap2_dpll_round_rate(unsigned long target_rate)
-{
- u32 high, low;
-
- if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */
- high = curr_prcm_set->dpll_speed * 2;
- low = curr_prcm_set->dpll_speed;
- } else { /* DPLL clockout x 2 */
- high = curr_prcm_set->dpll_speed;
- low = curr_prcm_set->dpll_speed / 2;
- }
-
-#ifdef DOWN_VARIABLE_DPLL
- if (target_rate > high)
- return high;
- else
- return target_rate;
-#else
- if (target_rate > low)
- return high;
- else
- return low;
-#endif
-
-}
-
/*
* Used for clocks that are part of CLKSEL_xyz governed clocks.
* REVISIT: Maybe change to use clk->enable() functions like on omap1?
*/
-static void omap2_clksel_recalc(struct clk * clk)
+void omap2_clksel_recalc(struct clk *clk)
{
- u32 fixed = 0, div = 0;
+ u32 div = 0;
- if (clk == &dpll_ck) {
- clk->rate = omap2_get_dpll_rate(clk);
- fixed = 1;
- div = 0;
- }
+ pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
- if (clk == &iva1_mpu_int_ifck) {
- div = 2;
- fixed = 1;
- }
-
- if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
- clk->rate = sys_ck.rate;
+ div = omap2_clksel_get_divisor(clk);
+ if (div == 0)
return;
- }
- if (!fixed) {
- div = omap2_clksel_get_divisor(clk);
- if (div == 0)
- return;
- }
+ if (unlikely(clk->rate == clk->parent->rate / div))
+ return;
+ clk->rate = clk->parent->rate / div;
- if (div != 0) {
- if (unlikely(clk->rate == clk->parent->rate / div))
- return;
- clk->rate = clk->parent->rate / div;
- }
+ pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
if (unlikely(clk->flags & RATE_PROPAGATES))
propagate_rate(clk);
}
-/*
- * Finds best divider value in an array based on the source and target
- * rates. The divider array must be sorted with smallest divider first.
+/**
+ * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
+ * @clk: OMAP struct clk ptr to inspect
+ * @src_clk: OMAP struct clk ptr of the parent clk to search for
+ *
+ * Scan the struct clksel array associated with the clock to find
+ * the element associated with the supplied parent clock address.
+ * Returns a pointer to the struct clksel on success or NULL on error.
*/
-static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
- u32 src_rate, u32 tgt_rate)
+const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
+ struct clk *src_clk)
{
- int i, test_rate;
+ const struct clksel *clks;
- if (div_array == NULL)
- return ~1;
+ if (!clk->clksel)
+ return NULL;
- for (i=0; i < size; i++) {
- test_rate = src_rate / *div_array;
- if (test_rate <= tgt_rate)
- return *div_array;
- ++div_array;
+ for (clks = clk->clksel; clks->parent; clks++) {
+ if (clks->parent == src_clk)
+ break; /* Found the requested parent */
}
- return ~0; /* No acceptable divider */
+ if (!clks->parent) {
+ printk(KERN_ERR "clock: Could not find parent clock %s in "
+ "clksel array of clock %s\n", src_clk->name,
+ clk->name);
+ return NULL;
+ }
+
+ return clks;
}
-/*
- * Find divisor for the given clock and target rate.
+/**
+ * omap2_clksel_round_rate_div - find divisor for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ * @new_div: ptr to where we should store the divisor
*
+ * Finds 'best' divider value in an array based on the source and target
+ * rates. The divider array must be sorted with smallest divider first.
* Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
* they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
*/
-static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
- u32 *new_div)
+u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+ u32 *new_div)
{
- u32 gfx_div[] = {2, 3, 4};
- u32 sysclkout_div[] = {1, 2, 4, 8, 16};
- u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
- u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
- u32 best_div = ~0, asize = 0;
- u32 *div_array = NULL;
-
- switch (tclk->flags & SRC_RATE_SEL_MASK) {
- case CM_GFX_SEL1:
- asize = 3;
- div_array = gfx_div;
- break;
- case CM_PLL_SEL1:
- return omap2_dpll_round_rate(target_rate);
- case CM_SYSCLKOUT_SEL1:
- asize = 5;
- div_array = sysclkout_div;
- break;
- case CM_CORE_SEL1:
- if(tclk == &dss1_fck){
- if(tclk->parent == &core_ck){
- asize = 10;
- div_array = dss1_div;
- } else {
- *new_div = 0; /* fixed clk */
- return(tclk->parent->rate);
- }
- } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
- if(tclk->parent == &core_ck){
- asize = 10;
- div_array = vylnq_div;
- } else {
- *new_div = 0; /* fixed clk */
- return(tclk->parent->rate);
- }
- }
- break;
+ unsigned long test_rate;
+ const struct clksel *clks;
+ const struct clksel_rate *clkr;
+ u32 last_div = 0;
+
+ printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
+ clk->name, target_rate);
+
+ *new_div = 1;
+
+ clks = omap2_get_clksel_by_parent(clk, clk->parent);
+ if (clks == NULL)
+ return ~0;
+
+ for (clkr = clks->rates; clkr->div; clkr++) {
+ if (!(clkr->flags & cpu_mask))
+ continue;
+
+ /* Sanity check */
+ if (clkr->div <= last_div)
+ printk(KERN_ERR "clock: clksel_rate table not sorted "
+ "for clock %s", clk->name);
+
+ last_div = clkr->div;
+
+ test_rate = clk->parent->rate / clkr->div;
+
+ if (test_rate <= target_rate)
+ break; /* found it */
}
- best_div = omap2_divider_from_table(asize, div_array,
- tclk->parent->rate, target_rate);
- if (best_div == ~0){
- *new_div = 1;
- return best_div; /* signal error */
+ if (!clkr->div) {
+ printk(KERN_ERR "clock: Could not find divisor for target "
+ "rate %ld for clock %s parent %s\n", target_rate,
+ clk->name, clk->parent->name);
+ return ~0;
}
- *new_div = best_div;
- return (tclk->parent->rate / best_div);
+ *new_div = clkr->div;
+
+ printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
+ (clk->parent->rate / clkr->div));
+
+ return (clk->parent->rate / clkr->div);
}
-/* Given a clock and a rate apply a clock specific rounding function */
-static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+/**
+ * omap2_clksel_round_rate - find rounded rate for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ *
+ * Compatibility wrapper for OMAP clock framework
+ * Finds best target rate based on the source clock and possible dividers.
+ * rates. The divider array must be sorted with smallest divider first.
+ * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
+ * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
+ */
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
{
- u32 new_div = 0;
- int valid_rate;
+ u32 new_div;
- if (clk->flags & RATE_FIXED)
- return clk->rate;
+ return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
+}
- if (clk->flags & RATE_CKCTL) {
- valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
- return valid_rate;
- }
+/* Given a clock and a rate apply a clock specific rounding function */
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+{
if (clk->round_rate != 0)
return clk->round_rate(clk, rate);
+ if (clk->flags & RATE_FIXED)
+ printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
+ "on fixed-rate clock %s\n", clk->name);
+
return clk->rate;
}
-/*
- * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compensate for the shifted DLL value in unlock mode.
+/**
+ * omap2_clksel_to_divisor() - turn clksel field value into integer divider
+ * @clk: OMAP struct clk to use
+ * @field_val: register field value to find
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a register field
+ * value to search for, find the corresponding clock divisor. The register
+ * field value should be pre-masked and shifted down so the LSB is at bit 0
+ * before calling. Returns 0 on error
*/
-static u32 omap2_dll_force_needed(void)
+u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
{
- u32 dll_state = SDRC_DLLA_CTRL; /* dlla and dllb are a set */
+ const struct clksel *clks;
+ const struct clksel_rate *clkr;
- if ((dll_state & (1 << 2)) == (1 << 2))
- return 1;
- else
+ clks = omap2_get_clksel_by_parent(clk, clk->parent);
+ if (clks == NULL)
return 0;
-}
-static u32 omap2_reprogram_sdrc(u32 level, u32 force)
-{
- u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
- u32 prev = curr_perf_level, flags;
-
- if ((curr_perf_level == level) && !force)
- return prev;
-
- m_type = omap2_memory_get_type();
- slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
- fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
-
- if (level == PRCM_HALF_SPEED) {
- local_irq_save(flags);
- PRCM_VOLTSETUP = 0xffff;
- omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
- slow_dll_ctrl, m_type);
- curr_perf_level = PRCM_HALF_SPEED;
- local_irq_restore(flags);
+ for (clkr = clks->rates; clkr->div; clkr++) {
+ if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
+ break;
}
- if (level == PRCM_FULL_SPEED) {
- local_irq_save(flags);
- PRCM_VOLTSETUP = 0xffff;
- omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
- fast_dll_ctrl, m_type);
- curr_perf_level = PRCM_FULL_SPEED;
- local_irq_restore(flags);
+
+ if (!clkr->div) {
+ printk(KERN_ERR "clock: Could not find fieldval %d for "
+ "clock %s parent %s\n", field_val, clk->name,
+ clk->parent->name);
+ return 0;
}
- return prev;
+ return clkr->div;
}
-static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
+/**
+ * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
+ * @clk: OMAP struct clk to use
+ * @div: integer divisor to search for
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
+ * find the corresponding register field value. The return register value is
+ * the value before left-shifting. Returns 0xffffffff on error
+ */
+u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
{
- u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
- u32 bypass = 0;
- struct prcm_config tmpset;
- int ret = -EINVAL;
+ const struct clksel *clks;
+ const struct clksel_rate *clkr;
- local_irq_save(flags);
- cur_rate = omap2_get_dpll_rate(&dpll_ck);
- mult = CM_CLKSEL2_PLL & 0x3;
-
- if ((rate == (cur_rate / 2)) && (mult == 2)) {
- omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
- } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
- omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
- } else if (rate != cur_rate) {
- valid_rate = omap2_dpll_round_rate(rate);
- if (valid_rate != rate)
- goto dpll_exit;
-
- if ((CM_CLKSEL2_PLL & 0x3) == 1)
- low = curr_prcm_set->dpll_speed;
- else
- low = curr_prcm_set->dpll_speed / 2;
-
- tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
- tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
- div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
- tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
- tmpset.cm_clksel2_pll &= ~0x3;
- if (rate > low) {
- tmpset.cm_clksel2_pll |= 0x2;
- mult = ((rate / 2) / 1000000);
- done_rate = PRCM_FULL_SPEED;
- } else {
- tmpset.cm_clksel2_pll |= 0x1;
- mult = (rate / 1000000);
- done_rate = PRCM_HALF_SPEED;
- }
- tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12));
-
- /* Worst case */
- tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
-
- if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
- bypass = 1;
+ /* should never happen */
+ WARN_ON(div == 0);
- omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */
-
- /* Force dll lock mode */
- omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
- bypass);
+ clks = omap2_get_clksel_by_parent(clk, clk->parent);
+ if (clks == NULL)
+ return 0;
- /* Errata: ret dll entry state */
- omap2_init_memory_params(omap2_dll_force_needed());
- omap2_reprogram_sdrc(done_rate, 0);
+ for (clkr = clks->rates; clkr->div; clkr++) {
+ if ((clkr->flags & cpu_mask) && (clkr->div == div))
+ break;
}
- omap2_clksel_recalc(&dpll_ck);
- ret = 0;
-dpll_exit:
- local_irq_restore(flags);
- return(ret);
-}
+ if (!clkr->div) {
+ printk(KERN_ERR "clock: Could not find divisor %d for "
+ "clock %s parent %s\n", div, clk->name,
+ clk->parent->name);
+ return 0;
+ }
-/* Just return the MPU speed */
-static void omap2_mpu_recalc(struct clk * clk)
-{
- clk->rate = curr_prcm_set->mpu_speed;
+ return clkr->val;
}
-/*
- * Look for a rate equal or less than the target rate given a configuration set.
+/**
+ * omap2_get_clksel - find clksel register addr & field mask for a clk
+ * @clk: struct clk to use
+ * @field_mask: ptr to u32 to store the register field mask
*
- * What's not entirely clear is "which" field represents the key field.
- * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
- * just uses the ARM rates.
+ * Returns the address of the clksel register upon success or NULL on error.
*/
-static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
+void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
{
- struct prcm_config * ptr;
- long highest_rate;
-
- if (clk != &virt_prcm_set)
- return -EINVAL;
-
- highest_rate = -EINVAL;
-
- for (ptr = rate_table; ptr->mpu_speed; ptr++) {
- if (ptr->xtal_speed != sys_ck.rate)
- continue;
+ if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
+ return NULL;
- highest_rate = ptr->mpu_speed;
+ *field_mask = clk->clksel_mask;
- /* Can check only after xtal frequency check */
- if (ptr->mpu_speed <= rate)
- break;
- }
- return highest_rate;
+ return clk->clksel_reg;
}
-/*
- * omap2_convert_field_to_div() - turn field value into integer divider
+/**
+ * omap2_clksel_get_divisor - get current divider applied to parent clock.
+ * @clk: OMAP struct clk to use.
+ *
+ * Returns the integer divisor upon success or 0 on error.
*/
-static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
+u32 omap2_clksel_get_divisor(struct clk *clk)
{
- u32 i;
- u32 clkout_array[] = {1, 2, 4, 8, 16};
+ u32 field_mask, field_val;
+ void __iomem *div_addr;
- if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
- for (i = 0; i < 5; i++) {
- if (field_val == i)
- return clkout_array[i];
- }
- return ~0;
- } else
- return field_val;
+ div_addr = omap2_get_clksel(clk, &field_mask);
+ if (div_addr == 0)
+ return 0;
+
+ field_val = __raw_readl(div_addr) & field_mask;
+ field_val >>= __ffs(field_mask);
+
+ return omap2_clksel_to_divisor(clk, field_val);
}
-/*
- * Returns the CLKSEL divider register value
- * REVISIT: This should be cleaned up to work nicely with void __iomem *
- */
-static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
- struct clk *clk)
+int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
{
- int ret = ~0;
- u32 reg_val, div_off;
- u32 div_addr = 0;
- u32 mask = ~0;
-
- div_off = clk->rate_offset;
-
- switch ((*div_sel & SRC_RATE_SEL_MASK)) {
- case CM_MPU_SEL1:
- div_addr = (u32)&CM_CLKSEL_MPU;
- mask = 0x1f;
- break;
- case CM_DSP_SEL1:
- div_addr = (u32)&CM_CLKSEL_DSP;
- if (cpu_is_omap2420()) {
- if ((div_off == 0) || (div_off == 8))
- mask = 0x1f;
- else if (div_off == 5)
- mask = 0x3;
- } else if (cpu_is_omap2430()) {
- if (div_off == 0)
- mask = 0x1f;
- else if (div_off == 5)
- mask = 0x3;
- }
- break;
- case CM_GFX_SEL1:
- div_addr = (u32)&CM_CLKSEL_GFX;
- if (div_off == 0)
- mask = 0x7;
- break;
- case CM_MODEM_SEL1:
- div_addr = (u32)&CM_CLKSEL_MDM;
- if (div_off == 0)
- mask = 0xf;
- break;
- case CM_SYSCLKOUT_SEL1:
- div_addr = (u32)&PRCM_CLKOUT_CTRL;
- if ((div_off == 3) || (div_off == 11))
- mask= 0x3;
- break;
- case CM_CORE_SEL1:
- div_addr = (u32)&CM_CLKSEL1_CORE;
- switch (div_off) {
- case 0: /* l3 */
- case 8: /* dss1 */
- case 15: /* vylnc-2420 */
- case 20: /* ssi */
- mask = 0x1f; break;
- case 5: /* l4 */
- mask = 0x3; break;
- case 13: /* dss2 */
- mask = 0x1; break;
- case 25: /* usb */
- mask = 0x7; break;
- }
- }
+ u32 field_mask, field_val, reg_val, validrate, new_div = 0;
+ void __iomem *div_addr;
- *field_mask = mask;
+ validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+ if (validrate != rate)
+ return -EINVAL;
- if (unlikely(mask == ~0))
- div_addr = 0;
+ div_addr = omap2_get_clksel(clk, &field_mask);
+ if (div_addr == 0)
+ return -EINVAL;
- *div_sel = div_addr;
+ field_val = omap2_divisor_to_clksel(clk, new_div);
+ if (field_val == ~0)
+ return -EINVAL;
- if (unlikely(div_addr == 0))
- return ret;
+ reg_val = __raw_readl(div_addr);
+ reg_val &= ~field_mask;
+ reg_val |= (field_val << __ffs(field_mask));
+ __raw_writel(reg_val, div_addr);
+ wmb();
- /* Isolate field */
- reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
+ clk->rate = clk->parent->rate / new_div;
- /* Normalize back to divider value */
- reg_val >>= div_off;
+ if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
+ __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
+ wmb();
+ }
- return reg_val;
+ return 0;
}
-/*
- * Return divider to be applied to parent clock.
- * Return 0 on error.
- */
-static u32 omap2_clksel_get_divisor(struct clk *clk)
-{
- int ret = 0;
- u32 div, div_sel, div_off, field_mask, field_val;
-
- /* isolate control register */
- div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-
- div_off = clk->rate_offset;
- field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
- if (div_sel == 0)
- return ret;
-
- div_sel = (SRC_RATE_SEL_MASK & clk->flags);
- div = omap2_clksel_to_divisor(div_sel, field_val);
-
- return div;
-}
/* Set the clock rate for a clock source */
-static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
-
+int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret = -EINVAL;
- void __iomem * reg;
- u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
- u32 new_div = 0;
-
- if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
- if (clk == &dpll_ck)
- return omap2_reprogram_dpll(clk, rate);
-
- /* Isolate control register */
- div_sel = (SRC_RATE_SEL_MASK & clk->flags);
- div_off = clk->rate_offset;
-
- validrate = omap2_clksel_round_rate(clk, rate, &new_div);
- if (validrate != rate)
- return(ret);
- field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
- if (div_sel == 0)
- return ret;
-
- if (clk->flags & CM_SYSCLKOUT_SEL1) {
- switch (new_div) {
- case 16:
- field_val = 4;
- break;
- case 8:
- field_val = 3;
- break;
- case 4:
- field_val = 2;
- break;
- case 2:
- field_val = 1;
- break;
- case 1:
- field_val = 0;
- break;
- }
- } else
- field_val = new_div;
+ pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
- reg = (void __iomem *)div_sel;
-
- reg_val = __raw_readl(reg);
- reg_val &= ~(field_mask << div_off);
- reg_val |= (field_val << div_off);
- __raw_writel(reg_val, reg);
- wmb();
- clk->rate = clk->parent->rate / field_val;
+ /* CONFIG_PARTICIPANT clocks are changed only in sets via the
+ rate table mechanism, driven by mpu_speed */
+ if (clk->flags & CONFIG_PARTICIPANT)
+ return -EINVAL;
- if (clk->flags & DELAYED_APP) {
- __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
- wmb();
- }
- ret = 0;
- } else if (clk->set_rate != 0)
+ /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
+ if (clk->set_rate != 0)
ret = clk->set_rate(clk, rate);
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
return ret;
}
-/* Converts encoded control register address into a full address */
-static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
- struct clk *src_clk, u32 *field_mask)
-{
- u32 val = ~0, src_reg_addr = 0, mask = 0;
-
- /* Find target control register.*/
- switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
- case CM_CORE_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL1_CORE;
- if (reg_offset == 13) { /* DSS2_fclk */
- mask = 0x1;
- if (src_clk == &sys_ck)
- val = 0;
- if (src_clk == &func_48m_ck)
- val = 1;
- } else if (reg_offset == 8) { /* DSS1_fclk */
- mask = 0x1f;
- if (src_clk == &sys_ck)
- val = 0;
- else if (src_clk == &core_ck) /* divided clock */
- val = 0x10; /* rate needs fixing */
- } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
- mask = 0x1F;
- if(src_clk == &func_96m_ck)
- val = 0;
- else if (src_clk == &core_ck)
- val = 0x10;
- }
- break;
- case CM_CORE_SEL2:
- src_reg_addr = (u32)&CM_CLKSEL2_CORE;
- mask = 0x3;
- if (src_clk == &func_32k_ck)
- val = 0x0;
- if (src_clk == &sys_ck)
- val = 0x1;
- if (src_clk == &alt_ck)
- val = 0x2;
- break;
- case CM_WKUP_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL_WKUP;
- mask = 0x3;
- if (src_clk == &func_32k_ck)
- val = 0x0;
- if (src_clk == &sys_ck)
- val = 0x1;
- if (src_clk == &alt_ck)
- val = 0x2;
- break;
- case CM_PLL_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL1_PLL;
- mask = 0x1;
- if (reg_offset == 0x3) {
- if (src_clk == &apll96_ck)
- val = 0;
- if (src_clk == &alt_ck)
- val = 1;
- }
- else if (reg_offset == 0x5) {
- if (src_clk == &apll54_ck)
- val = 0;
- if (src_clk == &alt_ck)
- val = 1;
- }
- break;
- case CM_PLL_SEL2:
- src_reg_addr = (u32)&CM_CLKSEL2_PLL;
- mask = 0x3;
- if (src_clk == &func_32k_ck)
- val = 0x0;
- if (src_clk == &dpll_ck)
- val = 0x2;
- break;
- case CM_SYSCLKOUT_SEL1:
- src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
- mask = 0x3;
- if (src_clk == &dpll_ck)
- val = 0;
- if (src_clk == &sys_ck)
- val = 1;
- if (src_clk == &func_96m_ck)
- val = 2;
- if (src_clk == &func_54m_ck)
- val = 3;
- break;
- }
-
- if (val == ~0) /* Catch errors in offset */
- *type_to_addr = 0;
- else
- *type_to_addr = src_reg_addr;
- *field_mask = mask;
-
- return val;
-}
-
-static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
+/*
+ * Converts encoded control register address into a full address
+ * On error, *src_addr will be returned as 0.
+ */
+static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
+ struct clk *src_clk, u32 *field_mask,
+ struct clk *clk, u32 *parent_div)
{
- void __iomem * reg;
- u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
- int ret = -EINVAL;
-
- if (unlikely(clk->flags & CONFIG_PARTICIPANT))
- return ret;
-
- if (clk->flags & SRC_SEL_MASK) { /* On-chip SEL collection */
- src_sel = (SRC_RATE_SEL_MASK & clk->flags);
- src_off = clk->src_offset;
-
- if (src_sel == 0)
- goto set_parent_error;
-
- field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
- &field_mask);
-
- reg = (void __iomem *)src_sel;
-
- if (clk->usecount > 0)
- _omap2_clk_disable(clk);
-
- /* Set new source value (previous dividers if any in effect) */
- reg_val = __raw_readl(reg) & ~(field_mask << src_off);
- reg_val |= (field_val << src_off);
- __raw_writel(reg_val, reg);
- wmb();
+ const struct clksel *clks;
+ const struct clksel_rate *clkr;
- if (clk->flags & DELAYED_APP) {
- __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
- wmb();
- }
- if (clk->usecount > 0)
- _omap2_clk_enable(clk);
-
- clk->parent = new_parent;
+ *parent_div = 0;
+ *src_addr = 0;
- /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
- if ((new_parent == &core_ck) && (clk == &dss1_fck))
- clk->rate = new_parent->rate / 0x10;
- else
- clk->rate = new_parent->rate;
+ clks = omap2_get_clksel_by_parent(clk, src_clk);
+ if (clks == NULL)
+ return 0;
- if (unlikely(clk->flags & RATE_PROPAGATES))
- propagate_rate(clk);
+ for (clkr = clks->rates; clkr->div; clkr++) {
+ if (clkr->flags & (cpu_mask | DEFAULT_RATE))
+ break; /* Found the default rate for this platform */
+ }
+ if (!clkr->div) {
+ printk(KERN_ERR "clock: Could not find default rate for "
+ "clock %s parent %s\n", clk->name,
+ src_clk->parent->name);
return 0;
- } else {
- clk->parent = new_parent;
- rate = new_parent->rate;
- omap2_clk_set_rate(clk, rate);
- ret = 0;
}
- set_parent_error:
- return ret;
+ /* Should never happen. Add a clksel mask to the struct clk. */
+ WARN_ON(clk->clksel_mask == 0);
+
+ *field_mask = clk->clksel_mask;
+ *src_addr = clk->clksel_reg;
+ *parent_div = clkr->div;
+
+ return clkr->val;
}
-/* Sets basic clocks based on the specified rate */
-static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
+int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
{
- u32 flags, cur_rate, done_rate, bypass = 0;
- u8 cpu_mask = 0;
- struct prcm_config *prcm;
- unsigned long found_speed = 0;
+ void __iomem *src_addr;
+ u32 field_val, field_mask, reg_val, parent_div;
- if (clk != &virt_prcm_set)
+ if (unlikely(clk->flags & CONFIG_PARTICIPANT))
return -EINVAL;
- /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */
- if (cpu_is_omap2420())
- cpu_mask = RATE_IN_242X;
- else if (cpu_is_omap2430())
- cpu_mask = RATE_IN_243X;
-
- for (prcm = rate_table; prcm->mpu_speed; prcm++) {
- if (!(prcm->flags & cpu_mask))
- continue;
-
- if (prcm->xtal_speed != sys_ck.rate)
- continue;
-
- if (prcm->mpu_speed <= rate) {
- found_speed = prcm->mpu_speed;
- break;
- }
- }
-
- if (!found_speed) {
- printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
- rate / 1000000);
+ if (!clk->clksel)
return -EINVAL;
- }
-
- curr_prcm_set = prcm;
- cur_rate = omap2_get_dpll_rate(&dpll_ck);
-
- if (prcm->dpll_speed == cur_rate / 2) {
- omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
- } else if (prcm->dpll_speed == cur_rate * 2) {
- omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
- } else if (prcm->dpll_speed != cur_rate) {
- local_irq_save(flags);
- if (prcm->dpll_speed == prcm->xtal_speed)
- bypass = 1;
+ field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
+ &field_mask, clk, &parent_div);
+ if (src_addr == 0)
+ return -EINVAL;
- if ((prcm->cm_clksel2_pll & 0x3) == 2)
- done_rate = PRCM_FULL_SPEED;
- else
- done_rate = PRCM_HALF_SPEED;
+ if (clk->usecount > 0)
+ _omap2_clk_disable(clk);
- /* MPU divider */
- CM_CLKSEL_MPU = prcm->cm_clksel_mpu;
+ /* Set new source value (previous dividers if any in effect) */
+ reg_val = __raw_readl(src_addr) & ~field_mask;
+ reg_val |= (field_val << __ffs(field_mask));
+ __raw_writel(reg_val, src_addr);
+ wmb();
- /* dsp + iva1 div(2420), iva2.1(2430) */
- CM_CLKSEL_DSP = prcm->cm_clksel_dsp;
+ if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
+ __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
+ wmb();
+ }
- CM_CLKSEL_GFX = prcm->cm_clksel_gfx;
+ if (clk->usecount > 0)
+ _omap2_clk_enable(clk);
- /* Major subsystem dividers */
- CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
- if (cpu_is_omap2430())
- CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
+ clk->parent = new_parent;
- /* x2 to enter init_mem */
- omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
+ /* CLKSEL clocks follow their parents' rates, divided by a divisor */
+ clk->rate = new_parent->rate;
- omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
- bypass);
+ if (parent_div > 0)
+ clk->rate /= parent_div;
- omap2_init_memory_params(omap2_dll_force_needed());
- omap2_reprogram_sdrc(done_rate, 0);
+ pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
+ clk->name, clk->parent->name, clk->rate);
- local_irq_restore(flags);
- }
- omap2_clksel_recalc(&dpll_ck);
+ if (unlikely(clk->flags & RATE_PROPAGATES))
+ propagate_rate(clk);
return 0;
}
*-------------------------------------------------------------------------*/
#ifdef CONFIG_OMAP_RESET_CLOCKS
-static void __init omap2_clk_disable_unused(struct clk *clk)
+void omap2_clk_disable_unused(struct clk *clk)
{
- u32 regval32;
+ u32 regval32, v;
+
+ v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
regval32 = __raw_readl(clk->enable_reg);
- if ((regval32 & (1 << clk->enable_bit)) == 0)
+ if ((regval32 & (1 << clk->enable_bit)) == v)
return;
printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
_omap2_clk_disable(clk);
}
-#else
-#define omap2_clk_disable_unused NULL
#endif
-
-static struct clk_functions omap2_clk_functions = {
- .clk_enable = omap2_clk_enable,
- .clk_disable = omap2_clk_disable,
- .clk_round_rate = omap2_clk_round_rate,
- .clk_set_rate = omap2_clk_set_rate,
- .clk_set_parent = omap2_clk_set_parent,
- .clk_disable_unused = omap2_clk_disable_unused,
-};
-
-static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
-{
- u32 div, aplls, sclk = 13000000;
-
- aplls = CM_CLKSEL1_PLL;
- aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
- aplls >>= 23; /* Isolate field, 0,2,3 */
-
- if (aplls == 0)
- sclk = 19200000;
- else if (aplls == 2)
- sclk = 13000000;
- else if (aplls == 3)
- sclk = 12000000;
-
- div = PRCM_CLKSRC_CTRL;
- div &= ((1 << 7) | (1 << 6));
- div >>= sys->rate_offset;
-
- osc->rate = sclk * div;
- sys->rate = sclk;
-}
-
-/*
- * Set clocks for bypass mode for reboot to work.
- */
-void omap2_clk_prepare_for_reboot(void)
-{
- u32 rate;
-
- if (vclk == NULL || sclk == NULL)
- return;
-
- rate = clk_get_rate(sclk);
- clk_set_rate(vclk, rate);
-}
-
-/*
- * Switch the MPU rate if specified on cmdline.
- * We cannot do this early until cmdline is parsed.
- */
-static int __init omap2_clk_arch_init(void)
-{
- if (!mpurate)
- return -EINVAL;
-
- if (omap2_select_table_rate(&virt_prcm_set, mpurate))
- printk(KERN_ERR "Could not find matching MPU rate\n");
-
- propagate_rate(&osc_ck); /* update main root fast */
- propagate_rate(&func_32k_ck); /* update main root slow */
-
- printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
- "%ld.%01ld/%ld/%ld MHz\n",
- (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
- (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
- return 0;
-}
-arch_initcall(omap2_clk_arch_init);
-
-int __init omap2_clk_init(void)
-{
- struct prcm_config *prcm;
- struct clk ** clkp;
- u32 clkrate;
-
- clk_init(&omap2_clk_functions);
- omap2_get_crystal_rate(&osc_ck, &sys_ck);
-
- for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
- clkp++) {
-
- if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
- clk_register(*clkp);
- continue;
- }
-
- if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
- clk_register(*clkp);
- continue;
- }
- }
-
- /* Check the MPU rate set by bootloader */
- clkrate = omap2_get_dpll_rate(&dpll_ck);
- for (prcm = rate_table; prcm->mpu_speed; prcm++) {
- if (prcm->xtal_speed != sys_ck.rate)
- continue;
- if (prcm->dpll_speed <= clkrate)
- break;
- }
- curr_prcm_set = prcm;
-
- propagate_rate(&osc_ck); /* update main root fast */
- propagate_rate(&func_32k_ck); /* update main root slow */
-
- printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
- "%ld.%01ld/%ld/%ld MHz\n",
- (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
- (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
- /*
- * Only enable those clocks we will need, let the drivers
- * enable other clocks as necessary
- */
- clk_enable(&sync_32k_ick);
- clk_enable(&omapctrl_ick);
-
- /* Force the APLLs always active. The clocks are idled
- * automatically by hardware. */
- clk_enable(&apll96_ck);
- clk_enable(&apll54_ck);
-
- if (cpu_is_omap2430())
- clk_enable(&sdrc_ick);
-
- /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
- vclk = clk_get(NULL, "virt_prcm_set");
- sclk = clk_get(NULL, "sys_ck");
-
- return 0;
-}
/*
- * linux/arch/arm/mach-omap24xx/clock.h
+ * linux/arch/arm/mach-omap2/clock.h
*
- * Copyright (C) 2005 Texas Instruments Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Created for OMAP2.
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2008 Nokia Corporation
*
- * Copyright (C) 2004 Nokia corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
-static void omap2_sys_clk_recalc(struct clk * clk);
-static void omap2_clksel_recalc(struct clk * clk);
-static void omap2_followparent_recalc(struct clk * clk);
-static void omap2_propagate_rate(struct clk * clk);
-static void omap2_mpu_recalc(struct clk * clk);
-static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
-static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
-static void omap2_clk_disable(struct clk *clk);
-static void omap2_sys_clk_recalc(struct clk * clk);
-static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
-static u32 omap2_clksel_get_divisor(struct clk *clk);
-
-
-#define RATE_IN_242X (1 << 0)
-#define RATE_IN_243X (1 << 1)
-
-/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
- * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- */
-struct prcm_config {
- unsigned long xtal_speed; /* crystal rate */
- unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
- unsigned long mpu_speed; /* speed of MPU */
- unsigned long cm_clksel_mpu; /* mpu divider */
- unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
- unsigned long cm_clksel_gfx; /* gfx dividers */
- unsigned long cm_clksel1_core; /* major subsystem dividers */
- unsigned long cm_clksel1_pll; /* m,n */
- unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
- unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
- unsigned long base_sdrc_rfr; /* base refresh timing for a set */
- unsigned char flags;
-};
-
-/* Mask for clksel which support parent settign in set_rate */
-#define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
- CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
-
-/* Mask for clksel regs which support rate operations */
-#define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
- CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
- CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
- CM_SYSCLKOUT_SEL1)
-
-/*
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
- */
-
-/* Core fields for cm_clksel, not ratio governed */
-#define RX_CLKSEL_DSS1 (0x10 << 8)
-#define RX_CLKSEL_DSS2 (0x0 << 13)
-#define RX_CLKSEL_SSI (0x5 << 20)
-
-/*-------------------------------------------------------------------------
- * Voltage/DPLL ratios
- *-------------------------------------------------------------------------*/
-
-/* 2430 Ratio's, 2430-Ratio Config 1 */
-#define R1_CLKSEL_L3 (4 << 0)
-#define R1_CLKSEL_L4 (2 << 5)
-#define R1_CLKSEL_USB (4 << 25)
-#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- R1_CLKSEL_L4 | R1_CLKSEL_L3
-#define R1_CLKSEL_MPU (2 << 0)
-#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
-#define R1_CLKSEL_DSP (2 << 0)
-#define R1_CLKSEL_DSP_IF (2 << 5)
-#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
-#define R1_CLKSEL_GFX (2 << 0)
-#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
-#define R1_CLKSEL_MDM (4 << 0)
-#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
-
-/* 2430-Ratio Config 2 */
-#define R2_CLKSEL_L3 (6 << 0)
-#define R2_CLKSEL_L4 (2 << 5)
-#define R2_CLKSEL_USB (2 << 25)
-#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- R2_CLKSEL_L4 | R2_CLKSEL_L3
-#define R2_CLKSEL_MPU (2 << 0)
-#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
-#define R2_CLKSEL_DSP (2 << 0)
-#define R2_CLKSEL_DSP_IF (3 << 5)
-#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
-#define R2_CLKSEL_GFX (2 << 0)
-#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
-#define R2_CLKSEL_MDM (6 << 0)
-#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
-
-/* 2430-Ratio Bootm (BYPASS) */
-#define RB_CLKSEL_L3 (1 << 0)
-#define RB_CLKSEL_L4 (1 << 5)
-#define RB_CLKSEL_USB (1 << 25)
-#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- RB_CLKSEL_L4 | RB_CLKSEL_L3
-#define RB_CLKSEL_MPU (1 << 0)
-#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
-#define RB_CLKSEL_DSP (1 << 0)
-#define RB_CLKSEL_DSP_IF (1 << 5)
-#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
-#define RB_CLKSEL_GFX (1 << 0)
-#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
-#define RB_CLKSEL_MDM (1 << 0)
-#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
-
-/* 2420 Ratio Equivalents */
-#define RXX_CLKSEL_VLYNQ (0x12 << 15)
-#define RXX_CLKSEL_SSI (0x8 << 20)
-
-/* 2420-PRCM III 532MHz core */
-#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
-#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
-#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
-#define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
- RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
- RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
- RIII_CLKSEL_L3
-#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
-#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
-#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
-#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
-#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
-#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
-#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
-#define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
- RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
- RIII_CLKSEL_DSP
-#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
-#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
-
-/* 2420-PRCM II 600MHz core */
-#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
-#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
-#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
-#define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
- RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
- RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
- RII_CLKSEL_L4 | RII_CLKSEL_L3
-#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
-#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
-#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
-#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
-#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
-#define RII_CLKSEL_IVA (6 << 8) /* iva1 - 200MHz */
-#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
-#define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
- RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
- RII_CLKSEL_DSP
-#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
-#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
-
-/* 2420-PRCM VII (boot) */
-#define RVII_CLKSEL_L3 (1 << 0)
-#define RVII_CLKSEL_L4 (1 << 5)
-#define RVII_CLKSEL_DSS1 (1 << 8)
-#define RVII_CLKSEL_DSS2 (0 << 13)
-#define RVII_CLKSEL_VLYNQ (1 << 15)
-#define RVII_CLKSEL_SSI (1 << 20)
-#define RVII_CLKSEL_USB (1 << 25)
-
-#define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
- RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
- RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
-
-#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
-#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
+#include <asm/arch/clock.h>
-#define RVII_CLKSEL_DSP (1 << 0)
-#define RVII_CLKSEL_DSP_IF (1 << 5)
-#define RVII_SYNC_DSP (0 << 7)
-#define RVII_CLKSEL_IVA (1 << 8)
-#define RVII_SYNC_IVA (0 << 13)
-#define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
- RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
-
-#define RVII_CLKSEL_GFX (1 << 0)
-#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
-
-/*-------------------------------------------------------------------------
- * 2430 Target modes: Along with each configuration the CPU has several
- * modes which goes along with them. Modes mainly are the addition of
- * describe DPLL combinations to go along with a ratio.
- *-------------------------------------------------------------------------*/
-
-/* Hardware governed */
-#define MX_48M_SRC (0 << 3)
-#define MX_54M_SRC (0 << 5)
-#define MX_APLLS_CLIKIN_12 (3 << 23)
-#define MX_APLLS_CLIKIN_13 (2 << 23)
-#define MX_APLLS_CLIKIN_19_2 (0 << 23)
-
-/*
- * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
- * #2 (ratio1) baseport-target
- * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
- */
-#define M5A_DPLL_MULT_12 (133 << 12)
-#define M5A_DPLL_DIV_12 (5 << 8)
-#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
- M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12
-#define M5A_DPLL_MULT_13 (266 << 12)
-#define M5A_DPLL_DIV_13 (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
- M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13
-#define M5A_DPLL_MULT_19 (180 << 12)
-#define M5A_DPLL_DIV_19 (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
- M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2
-/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
-#define M5B_DPLL_MULT_12 (50 << 12)
-#define M5B_DPLL_DIV_12 (2 << 8)
-#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
- M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12
-#define M5B_DPLL_MULT_13 (200 << 12)
-#define M5B_DPLL_DIV_13 (12 << 8)
-
-#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
- M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13
-#define M5B_DPLL_MULT_19 (125 << 12)
-#define M5B_DPLL_DIV_19 (31 << 8)
-#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
- M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2
-/*
- * #4 (ratio2)
- * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
- */
-#define M3_DPLL_MULT_12 (55 << 12)
-#define M3_DPLL_DIV_12 (1 << 8)
-#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
- M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12
-#define M3_DPLL_MULT_13 (330 << 12)
-#define M3_DPLL_DIV_13 (12 << 8)
-#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
- M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13
-#define M3_DPLL_MULT_19 (275 << 12)
-#define M3_DPLL_DIV_19 (15 << 8)
-#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
- M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
- MX_APLLS_CLIKIN_19_2
-/* boot (boot) */
-#define MB_DPLL_MULT (1 << 12)
-#define MB_DPLL_DIV (0 << 8)
-#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
- MB_DPLL_MULT | MX_APLLS_CLIKIN_12
-
-#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
- MB_DPLL_MULT | MX_APLLS_CLIKIN_13
-
-#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
- MB_DPLL_MULT | MX_APLLS_CLIKIN_19
-
-/*
- * 2430 - chassis (sedna)
- * 165 (ratio1) same as above #2
- * 150 (ratio1)
- * 133 (ratio2) same as above #4
- * 110 (ratio2) same as above #3
- * 104 (ratio2)
- * boot (boot)
- */
-
-/*
- * 2420 Equivalent - mode registers
- * PRCM II , target DPLL = 2*300MHz = 600MHz
- */
-#define MII_DPLL_MULT_12 (50 << 12)
-#define MII_DPLL_DIV_12 (1 << 8)
-#define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
- MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12
-#define MII_DPLL_MULT_13 (300 << 12)
-#define MII_DPLL_DIV_13 (12 << 8)
-#define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
- MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13
-
-/* PRCM III target DPLL = 2*266 = 532MHz*/
-#define MIII_DPLL_MULT_12 (133 << 12)
-#define MIII_DPLL_DIV_12 (5 << 8)
-#define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
- MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
- MX_APLLS_CLIKIN_12
-#define MIII_DPLL_MULT_13 (266 << 12)
-#define MIII_DPLL_DIV_13 (12 << 8)
-#define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
- MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
- MX_APLLS_CLIKIN_13
-
-/* PRCM VII (boot bypass) */
-#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
-#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
-
-/* High and low operation value */
-#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
-#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
-
-/*
- * These represent optimal values for common parts, it won't work for all.
- * As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the opposite direction. If you
- * don't adjust it down as your clock period increases the refresh interval
- * will not be met. Setting all parameters for complete worst case may work,
- * but may cut memory performance by 2x. Due to errata the DLLs need to be
- * unlocked and their value needs run time calibration. A dynamic call is
- * need for that as no single right value exists acorss production samples.
- *
- * Only the FULL speed values are given. Current code is such that rate
- * changes must be made at DPLLoutx2. The actual value adjustment for low
- * frequency operation will be handled by omap_set_performance()
- *
- * By having the boot loader boot up in the fastest L4 speed available likely
- * will result in something which you can switch between.
- */
-#define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
-#define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
-#define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
-#define V24XX_SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
-
-/* MPU speed defines */
-#define S12M 12000000
-#define S13M 13000000
-#define S19M 19200000
-#define S26M 26000000
-#define S100M 100000000
-#define S133M 133000000
-#define S150M 150000000
-#define S165M 165000000
-#define S200M 200000000
-#define S266M 266000000
-#define S300M 300000000
-#define S330M 330000000
-#define S400M 400000000
-#define S532M 532000000
-#define S600M 600000000
-#define S660M 660000000
-
-/*-------------------------------------------------------------------------
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
- * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
- * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * Filling in table based on H4 boards and 2430-SDPs variants available.
- * There are quite a few more rates combinations which could be defined.
- *
- * When multiple values are defined the start up will try and choose the
- * fastest one. If a 'fast' value is defined, then automatically, the /2
- * one should be included as it can be used. Generally having more that
- * one fast set does not make sense, as static timings need to be changed
- * to change the set. The exception is the bypass setting which is
- * availble for low power bypass.
- *
- * Note: This table needs to be sorted, fastest to slowest.
- *-------------------------------------------------------------------------*/
-static struct prcm_config rate_table[] = {
- /* PRCM II - FAST */
- {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- /* PRCM III - FAST */
- {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- /* PRCM II - SLOW */
- {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
- RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
- RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
- RATE_IN_242X},
-
- /* PRCM III - SLOW */
- {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
- RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
- RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
- RATE_IN_242X},
-
- /* PRCM-VII (boot-bypass) */
- {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
- RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
- RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
- RATE_IN_242X},
-
- /* PRCM-VII (boot-bypass) */
- {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
- RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
- RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
- RATE_IN_242X},
-
- /* PRCM #3 - ratio2 (ES2) - FAST */
- {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
- R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
- R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
- V24XX_SDRC_RFR_CTRL_110MHz,
- RATE_IN_243X},
-
- /* PRCM #5a - ratio1 - FAST */
- {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
- V24XX_SDRC_RFR_CTRL_133MHz,
- RATE_IN_243X},
-
- /* PRCM #5b - ratio1 - FAST */
- {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
- V24XX_SDRC_RFR_CTRL_100MHz,
- RATE_IN_243X},
-
- /* PRCM #3 - ratio2 (ES2) - SLOW */
- {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
- R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
- R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
- V24XX_SDRC_RFR_CTRL_110MHz,
- RATE_IN_243X},
-
- /* PRCM #5a - ratio1 - SLOW */
- {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
- V24XX_SDRC_RFR_CTRL_133MHz,
- RATE_IN_243X},
-
- /* PRCM #5b - ratio1 - SLOW*/
- {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
- R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
- R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
- V24XX_SDRC_RFR_CTRL_100MHz,
- RATE_IN_243X},
-
- /* PRCM-boot/bypass */
- {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
- RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
- RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
- MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
- V24XX_SDRC_RFR_CTRL_BYPASS,
- RATE_IN_243X},
-
- /* PRCM-boot/bypass */
- {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
- RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
- RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
- MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
- V24XX_SDRC_RFR_CTRL_BYPASS,
- RATE_IN_243X},
-
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
-
-/*-------------------------------------------------------------------------
- * 24xx clock tree.
- *
- * NOTE:In many cases here we are assigning a 'default' parent. In many
- * cases the parent is selectable. The get/set parent calls will also
- * switch sources.
- *
- * Many some clocks say always_enabled, but they can be auto idled for
- * power savings. They will always be available upon clock request.
- *
- * Several sources are given initial rates which may be wrong, this will
- * be fixed up in the init func.
- *
- * Things are broadly separated below by clock domains. It is
- * noteworthy that most periferals have dependencies on multiple clock
- * domains. Many get their interface clocks from the L4 domain, but get
- * functional clocks from fixed sources or other core domain derived
- * clocks.
- *-------------------------------------------------------------------------*/
-
-/* Base external input clocks */
-static struct clk func_32k_ck = {
- .name = "func_32k_ck",
- .rate = 32000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | ALWAYS_ENABLED,
-};
-
-/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
-static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
- .name = "osc_ck",
- .rate = 26000000, /* fixed up in clock init */
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | RATE_PROPAGATES,
-};
-
-/* With out modem likely 12MHz, with modem likely 13MHz */
-static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
- .name = "sys_ck", /* ~ ref_clk also */
- .parent = &osc_ck,
- .rate = 13000000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
- .rate_offset = 6, /* sysclkdiv 1 or 2, already handled or no boot */
- .recalc = &omap2_sys_clk_recalc,
-};
-
-static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
- .name = "alt_ck",
- .rate = 54000000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
- .recalc = &omap2_propagate_rate,
-};
-
-/*
- * Analog domain root source clocks
- */
-
-/* dpll_ck, is broken out in to special cases through clksel */
-static struct clk dpll_ck = {
- .name = "dpll_ck",
- .parent = &sys_ck, /* Can be func_32k also */
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk apll96_ck = {
- .name = "apll96_ck",
- .parent = &sys_ck,
- .rate = 96000000,
- .flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
- RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0x2,
- .recalc = &omap2_propagate_rate,
-};
-
-static struct clk apll54_ck = {
- .name = "apll54_ck",
- .parent = &sys_ck,
- .rate = 54000000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0x6,
- .recalc = &omap2_propagate_rate,
-};
+int omap2_clk_enable(struct clk *clk);
+void omap2_clk_disable(struct clk *clk);
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
+int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
+int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
-/*
- * PRCM digital base sources
- */
-static struct clk func_54m_ck = {
- .name = "func_54m_ck",
- .parent = &apll54_ck, /* can also be alt_clk */
- .rate = 54000000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
- .src_offset = 5,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0xff,
- .recalc = &omap2_propagate_rate,
-};
-
-static struct clk core_ck = {
- .name = "core_ck",
- .parent = &dpll_ck, /* can also be 32k */
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- ALWAYS_ENABLED | RATE_PROPAGATES,
- .recalc = &omap2_propagate_rate,
-};
-
-static struct clk sleep_ck = { /* sys_clk or 32k */
- .name = "sleep_ck",
- .parent = &func_32k_ck,
- .rate = 32000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .recalc = &omap2_propagate_rate,
-};
-
-static struct clk func_96m_ck = {
- .name = "func_96m_ck",
- .parent = &apll96_ck,
- .rate = 96000000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0xff,
- .recalc = &omap2_propagate_rate,
-};
-
-static struct clk func_48m_ck = {
- .name = "func_48m_ck",
- .parent = &apll96_ck, /* 96M or Alt */
- .rate = 48000000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
- .src_offset = 3,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0xff,
- .recalc = &omap2_propagate_rate,
-};
-
-static struct clk func_12m_ck = {
- .name = "func_12m_ck",
- .parent = &func_48m_ck,
- .rate = 12000000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | RATE_PROPAGATES,
- .recalc = &omap2_propagate_rate,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0xff,
-};
-
-/* Secure timer, only available in secure mode */
-static struct clk wdt1_osc_ck = {
- .name = "ck_wdt1_osc",
- .parent = &osc_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk sys_clkout = {
- .name = "sys_clkout",
- .parent = &func_54m_ck,
- .rate = 54000000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
- .src_offset = 0,
- .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
- .enable_bit = 7,
- .rate_offset = 3,
- .recalc = &omap2_clksel_recalc,
-};
-
-/* In 2430, new in 2420 ES2 */
-static struct clk sys_clkout2 = {
- .name = "sys_clkout2",
- .parent = &func_54m_ck,
- .rate = 54000000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
- .src_offset = 8,
- .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
- .enable_bit = 15,
- .rate_offset = 11,
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk emul_ck = {
- .name = "emul_ck",
- .parent = &func_54m_ck,
- .flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
- .enable_bit = 0,
- .recalc = &omap2_propagate_rate,
-
-};
-
-/*
- * MPU clock domain
- * Clocks:
- * MPU_FCLK, MPU_ICLK
- * INT_M_FCLK, INT_M_I_CLK
- *
- * - Individual clocks are hardware managed.
- * - Base divider comes from: CM_CLKSEL_MPU
- *
- */
-static struct clk mpu_ck = { /* Control cpu */
- .name = "mpu_ck",
- .parent = &core_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
- ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
- CONFIG_PARTICIPANT | RATE_PROPAGATES,
- .rate_offset = 0, /* bits 0-4 */
- .recalc = &omap2_clksel_recalc,
-};
-
-/*
- * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
- * Clocks:
- * 2430: IVA2.1_FCLK, IVA2.1_ICLK
- * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
- */
-static struct clk iva2_1_fck = {
- .name = "iva2_1_fck",
- .parent = &core_ck,
- .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
- DELAYED_APP | RATE_PROPAGATES |
- CONFIG_PARTICIPANT,
- .rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
- .enable_bit = 0,
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk iva2_1_ick = {
- .name = "iva2_1_ick",
- .parent = &iva2_1_fck,
- .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
- DELAYED_APP | CONFIG_PARTICIPANT,
- .rate_offset = 5,
- .recalc = &omap2_clksel_recalc,
-};
-
-/*
- * Won't be too specific here. The core clock comes into this block
- * it is divided then tee'ed. One branch goes directly to xyz enable
- * controls. The other branch gets further divided by 2 then possibly
- * routed into a synchronizer and out of clocks abc.
- */
-static struct clk dsp_fck = {
- .name = "dsp_fck",
- .parent = &core_ck,
- .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
- DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
- .rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
- .enable_bit = 0,
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk dsp_ick = {
- .name = "dsp_ick", /* apparently ipi and isp */
- .parent = &dsp_fck,
- .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
- DELAYED_APP | CONFIG_PARTICIPANT,
- .rate_offset = 5,
- .enable_reg = (void __iomem *)&CM_ICLKEN_DSP,
- .enable_bit = 1, /* for ipi */
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk iva1_ifck = {
- .name = "iva1_ifck",
- .parent = &core_ck,
- .flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
- CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
- .rate_offset= 8,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
- .enable_bit = 10,
- .recalc = &omap2_clksel_recalc,
-};
-
-/* IVA1 mpu/int/i/f clocks are /2 of parent */
-static struct clk iva1_mpu_int_ifck = {
- .name = "iva1_mpu_int_ifck",
- .parent = &iva1_ifck,
- .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
- .enable_bit = 8,
- .recalc = &omap2_clksel_recalc,
-};
-
-/*
- * L3 clock domain
- * L3 clocks are used for both interface and functional clocks to
- * multiple entities. Some of these clocks are completely managed
- * by hardware, and some others allow software control. Hardware
- * managed ones general are based on directly CLK_REQ signals and
- * various auto idle settings. The functional spec sets many of these
- * as 'tie-high' for their enables.
- *
- * I-CLOCKS:
- * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
- * CAM, HS-USB.
- * F-CLOCK
- * SSI.
- *
- * GPMC memories and SDRC have timing and clock sensitive registers which
- * may very well need notification when the clock changes. Currently for low
- * operating points, these are taken care of in sleep.S.
- */
-static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
- .name = "core_l3_ck",
- .parent = &core_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
- DELAYED_APP | CONFIG_PARTICIPANT |
- RATE_PROPAGATES,
- .rate_offset = 0,
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk usb_l4_ick = { /* FS-USB interface clock */
- .name = "usb_l4_ick",
- .parent = &core_l3_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
- CONFIG_PARTICIPANT,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 0,
- .rate_offset = 25,
- .recalc = &omap2_clksel_recalc,
-};
-
-/*
- * SSI is in L3 management domain, its direct parent is core not l3,
- * many core power domain entities are grouped into the L3 clock
- * domain.
- * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
- *
- * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
- */
-static struct clk ssi_ssr_sst_fck = {
- .name = "ssi_fck",
- .parent = &core_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */
- .enable_bit = 1,
- .rate_offset = 20,
- .recalc = &omap2_clksel_recalc,
-};
-
-/*
- * GFX clock domain
- * Clocks:
- * GFX_FCLK, GFX_ICLK
- * GFX_CG1(2d), GFX_CG2(3d)
- *
- * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
- * The 2d and 3d clocks run at a hardware determined
- * divided value of fclk.
- *
- */
-static struct clk gfx_3d_fck = {
- .name = "gfx_3d_fck",
- .parent = &core_l3_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL | CM_GFX_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
- .enable_bit = 2,
- .rate_offset= 0,
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk gfx_2d_fck = {
- .name = "gfx_2d_fck",
- .parent = &core_l3_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL | CM_GFX_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
- .enable_bit = 1,
- .rate_offset= 0,
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk gfx_ick = {
- .name = "gfx_ick", /* From l3 */
- .parent = &core_l3_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */
- .enable_bit = 0,
- .recalc = &omap2_followparent_recalc,
-};
-
-/*
- * Modem clock domain (2430)
- * CLOCKS:
- * MDM_OSC_CLK
- * MDM_ICLK
- */
-static struct clk mdm_ick = { /* used both as a ick and fck */
- .name = "mdm_ick",
- .parent = &core_ck,
- .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
- DELAYED_APP | CONFIG_PARTICIPANT,
- .rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_ICLKEN_MDM,
- .enable_bit = 0,
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk mdm_osc_ck = {
- .name = "mdm_osc_ck",
- .rate = 26000000,
- .parent = &osc_ck,
- .flags = CLOCK_IN_OMAP243X | RATE_FIXED,
- .enable_reg = (void __iomem *)&CM_FCLKEN_MDM,
- .enable_bit = 1,
- .recalc = &omap2_followparent_recalc,
-};
-
-/*
- * L4 clock management domain
- *
- * This domain contains lots of interface clocks from the L4 interface, some
- * functional clocks. Fixed APLL functional source clocks are managed in
- * this domain.
- */
-static struct clk l4_ck = { /* used both as an ick and fck */
- .name = "l4_ck",
- .parent = &core_l3_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
- DELAYED_APP | RATE_PROPAGATES,
- .rate_offset = 5,
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk ssi_l4_ick = {
- .name = "ssi_l4_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */
- .enable_bit = 1,
- .recalc = &omap2_followparent_recalc,
-};
-
-/*
- * DSS clock domain
- * CLOCKs:
- * DSS_L4_ICLK, DSS_L3_ICLK,
- * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
- *
- * DSS is both initiator and target.
- */
-static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
- .name = "dss_ick",
- .parent = &l4_ck, /* really both l3 and l4 */
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 0,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk dss1_fck = {
- .name = "dss1_fck",
- .parent = &core_ck, /* Core or sys */
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 0,
- .rate_offset = 8,
- .src_offset = 8,
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk dss2_fck = { /* Alt clk used in power management */
- .name = "dss2_fck",
- .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
- DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 1,
- .src_offset = 13,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk dss_54m_fck = { /* Alt clk used in power management */
- .name = "dss_54m_fck", /* 54m tv clk */
- .parent = &func_54m_ck,
- .rate = 54000000,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 2,
- .recalc = &omap2_propagate_rate,
-};
-
-/*
- * CORE power domain ICLK & FCLK defines.
- * Many of the these can have more than one possible parent. Entries
- * here will likely have an L4 interface parent, and may have multiple
- * functional clock parents.
- */
-static struct clk gpt1_ick = {
- .name = "gpt1_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */
- .enable_bit = 0,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt1_fck = {
- .name = "gpt1_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_WKUP_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */
- .enable_bit = 0,
- .src_offset = 0,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt2_ick = {
- .name = "gpt2_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
- .enable_bit = 4,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt2_fck = {
- .name = "gpt2_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 4,
- .src_offset = 2,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt3_ick = {
- .name = "gpt3_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */
- .enable_bit = 5,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt3_fck = {
- .name = "gpt3_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 5,
- .src_offset = 4,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt4_ick = {
- .name = "gpt4_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */
- .enable_bit = 6,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt4_fck = {
- .name = "gpt4_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 6,
- .src_offset = 6,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt5_ick = {
- .name = "gpt5_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */
- .enable_bit = 7,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt5_fck = {
- .name = "gpt5_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 7,
- .src_offset = 8,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt6_ick = {
- .name = "gpt6_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_bit = 8,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt6_fck = {
- .name = "gpt6_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 8,
- .src_offset = 10,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt7_ick = {
- .name = "gpt7_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */
- .enable_bit = 9,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt7_fck = {
- .name = "gpt7_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 9,
- .src_offset = 12,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt8_ick = {
- .name = "gpt8_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */
- .enable_bit = 10,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt8_fck = {
- .name = "gpt8_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 10,
- .src_offset = 14,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt9_ick = {
- .name = "gpt9_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 11,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt9_fck = {
- .name = "gpt9_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 11,
- .src_offset = 16,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt10_ick = {
- .name = "gpt10_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 12,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt10_fck = {
- .name = "gpt10_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 12,
- .src_offset = 18,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt11_ick = {
- .name = "gpt11_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 13,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt11_fck = {
- .name = "gpt11_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 13,
- .src_offset = 20,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt12_ick = {
- .name = "gpt12_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */
- .enable_bit = 14,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpt12_fck = {
- .name = "gpt12_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 14,
- .src_offset = 22,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp1_ick = {
- .name = "mcbsp1_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_bit = 15,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp1_fck = {
- .name = "mcbsp1_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_bit = 15,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp2_ick = {
- .name = "mcbsp2_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_bit = 16,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp2_fck = {
- .name = "mcbsp2_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_bit = 16,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp3_ick = {
- .name = "mcbsp3_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 3,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp3_fck = {
- .name = "mcbsp3_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 3,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp4_ick = {
- .name = "mcbsp4_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 4,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp4_fck = {
- .name = "mcbsp4_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 4,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp5_ick = {
- .name = "mcbsp5_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 5,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp5_fck = {
- .name = "mcbsp5_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 5,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi1_ick = {
- .name = "mcspi_ick",
- .id = 1,
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 17,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi1_fck = {
- .name = "mcspi_fck",
- .id = 1,
- .parent = &func_48m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 17,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi2_ick = {
- .name = "mcspi_ick",
- .id = 2,
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 18,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi2_fck = {
- .name = "mcspi_fck",
- .id = 2,
- .parent = &func_48m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 18,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi3_ick = {
- .name = "mcspi_ick",
- .id = 3,
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 9,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi3_fck = {
- .name = "mcspi_fck",
- .id = 3,
- .parent = &func_48m_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 9,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk uart1_ick = {
- .name = "uart1_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 21,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk uart1_fck = {
- .name = "uart1_fck",
- .parent = &func_48m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 21,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk uart2_ick = {
- .name = "uart2_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 22,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk uart2_fck = {
- .name = "uart2_fck",
- .parent = &func_48m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 22,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk uart3_ick = {
- .name = "uart3_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 2,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk uart3_fck = {
- .name = "uart3_fck",
- .parent = &func_48m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 2,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpios_ick = {
- .name = "gpios_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 2,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk gpios_fck = {
- .name = "gpios_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
- .enable_bit = 2,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mpu_wdt_ick = {
- .name = "mpu_wdt_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 3,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mpu_wdt_fck = {
- .name = "mpu_wdt_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
- .enable_bit = 3,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk sync_32k_ick = {
- .name = "sync_32k_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 1,
- .recalc = &omap2_followparent_recalc,
-};
-static struct clk wdt1_ick = {
- .name = "wdt1_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 4,
- .recalc = &omap2_followparent_recalc,
-};
-static struct clk omapctrl_ick = {
- .name = "omapctrl_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 5,
- .recalc = &omap2_followparent_recalc,
-};
-static struct clk icr_ick = {
- .name = "icr_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 6,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk cam_ick = {
- .name = "cam_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 31,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk cam_fck = {
- .name = "cam_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 31,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mailboxes_ick = {
- .name = "mailboxes_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 30,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk wdt4_ick = {
- .name = "wdt4_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 29,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk wdt4_fck = {
- .name = "wdt4_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 29,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk wdt3_ick = {
- .name = "wdt3_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 28,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk wdt3_fck = {
- .name = "wdt3_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 28,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mspro_ick = {
- .name = "mspro_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 27,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mspro_fck = {
- .name = "mspro_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 27,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mmc_ick = {
- .name = "mmc_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 26,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mmc_fck = {
- .name = "mmc_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 26,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk fac_ick = {
- .name = "fac_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 25,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk fac_fck = {
- .name = "fac_fck",
- .parent = &func_12m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 25,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk eac_ick = {
- .name = "eac_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 24,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk eac_fck = {
- .name = "eac_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 24,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk hdq_ick = {
- .name = "hdq_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 23,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk hdq_fck = {
- .name = "hdq_fck",
- .parent = &func_12m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 23,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk i2c2_ick = {
- .name = "i2c_ick",
- .id = 2,
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 20,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk i2c2_fck = {
- .name = "i2c_fck",
- .id = 2,
- .parent = &func_12m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 20,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk i2chs2_fck = {
- .name = "i2chs2_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 20,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk i2c1_ick = {
- .name = "i2c_ick",
- .id = 1,
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 19,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk i2c1_fck = {
- .name = "i2c_fck",
- .id = 1,
- .parent = &func_12m_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 19,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk i2chs1_fck = {
- .name = "i2chs1_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 19,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk vlynq_ick = {
- .name = "vlynq_ick",
- .parent = &core_l3_ck,
- .flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 3,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk vlynq_fck = {
- .name = "vlynq_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 3,
- .src_offset = 15,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk sdrc_ick = {
- .name = "sdrc_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE,
- .enable_bit = 2,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk des_ick = {
- .name = "des_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
- .enable_bit = 0,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk sha_ick = {
- .name = "sha_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
- .enable_bit = 1,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk rng_ick = {
- .name = "rng_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
- .enable_bit = 2,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk aes_ick = {
- .name = "aes_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
- .enable_bit = 3,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk pka_ick = {
- .name = "pka_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
- .enable_bit = 4,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk usb_fck = {
- .name = "usb_fck",
- .parent = &func_48m_ck,
- .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 0,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk usbhs_ick = {
- .name = "usbhs_ick",
- .parent = &core_l3_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 6,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs1_ick = {
- .name = "mmchs1_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 7,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs1_fck = {
- .name = "mmchs1_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 7,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs2_ick = {
- .name = "mmchs2_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 8,
- .recalc = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs2_fck = {
- .name = "mmchs2_fck",
- .parent = &func_96m_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 8,
- .recalc = &omap2_followparent_recalc,
-};
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+void omap2_clk_disable_unused(struct clk *clk);
+#else
+#define omap2_clk_disable_unused NULL
+#endif
-static struct clk gpio5_ick = {
- .name = "gpio5_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 10,
- .recalc = &omap2_followparent_recalc,
-};
+void omap2_clksel_recalc(struct clk *clk);
+void omap2_init_clksel_parent(struct clk *clk);
+u32 omap2_clksel_get_divisor(struct clk *clk);
+u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+ u32 *new_div);
+u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
+u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
+void omap2_fixed_divisor_recalc(struct clk *clk);
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
+int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
+u32 omap2_get_dpll_rate(struct clk *clk);
+int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
-static struct clk gpio5_fck = {
- .name = "gpio5_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 10,
- .recalc = &omap2_followparent_recalc,
-};
+extern u8 cpu_mask;
-static struct clk mdm_intc_ick = {
- .name = "mdm_intc_ick",
- .parent = &l4_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 11,
- .recalc = &omap2_followparent_recalc,
+/* clksel_rate data common to 24xx/343x */
+static const struct clksel_rate gpt_32k_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
};
-static struct clk mmchsdb1_fck = {
- .name = "mmchsdb1_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 16,
- .recalc = &omap2_followparent_recalc,
+static const struct clksel_rate gpt_sys_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
};
-static struct clk mmchsdb2_fck = {
- .name = "mmchsdb2_fck",
- .parent = &func_32k_ck,
- .flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 17,
- .recalc = &omap2_followparent_recalc,
+static const struct clksel_rate gfx_l3_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+ { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
+ { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
+ { .div = 0 }
};
-/*
- * This clock is a composite clock which does entire set changes then
- * forces a rebalance. It keys on the MPU speed, but it really could
- * be any key speed part of a set in the rate table.
- *
- * to really change a set, you need memory table sets which get changed
- * in sram, pre-notifiers & post notifiers, changing the top set, without
- * having low level display recalc's won't work... this is why dpm notifiers
- * work, isr's off, walk a list of clocks already _off_ and not messing with
- * the bus.
- *
- * This clock should have no parent. It embodies the entire upper level
- * active set. A parent will mess up some of the init also.
- */
-static struct clk virt_prcm_set = {
- .name = "virt_prcm_set",
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
- .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
- .recalc = &omap2_mpu_recalc, /* sets are keyed on mpu rate */
- .set_rate = &omap2_select_table_rate,
- .round_rate = &omap2_round_to_table_rate,
-};
-
-static struct clk *onchip_clks[] = {
- /* external root sources */
- &func_32k_ck,
- &osc_ck,
- &sys_ck,
- &alt_ck,
- /* internal analog sources */
- &dpll_ck,
- &apll96_ck,
- &apll54_ck,
- /* internal prcm root sources */
- &func_54m_ck,
- &core_ck,
- &sleep_ck,
- &func_96m_ck,
- &func_48m_ck,
- &func_12m_ck,
- &wdt1_osc_ck,
- &sys_clkout,
- &sys_clkout2,
- &emul_ck,
- /* mpu domain clocks */
- &mpu_ck,
- /* dsp domain clocks */
- &iva2_1_fck, /* 2430 */
- &iva2_1_ick,
- &dsp_ick, /* 2420 */
- &dsp_fck,
- &iva1_ifck,
- &iva1_mpu_int_ifck,
- /* GFX domain clocks */
- &gfx_3d_fck,
- &gfx_2d_fck,
- &gfx_ick,
- /* Modem domain clocks */
- &mdm_ick,
- &mdm_osc_ck,
- /* DSS domain clocks */
- &dss_ick,
- &dss1_fck,
- &dss2_fck,
- &dss_54m_fck,
- /* L3 domain clocks */
- &core_l3_ck,
- &ssi_ssr_sst_fck,
- &usb_l4_ick,
- /* L4 domain clocks */
- &l4_ck, /* used as both core_l4 and wu_l4 */
- &ssi_l4_ick,
- /* virtual meta-group clock */
- &virt_prcm_set,
- /* general l4 interface ck, multi-parent functional clk */
- &gpt1_ick,
- &gpt1_fck,
- &gpt2_ick,
- &gpt2_fck,
- &gpt3_ick,
- &gpt3_fck,
- &gpt4_ick,
- &gpt4_fck,
- &gpt5_ick,
- &gpt5_fck,
- &gpt6_ick,
- &gpt6_fck,
- &gpt7_ick,
- &gpt7_fck,
- &gpt8_ick,
- &gpt8_fck,
- &gpt9_ick,
- &gpt9_fck,
- &gpt10_ick,
- &gpt10_fck,
- &gpt11_ick,
- &gpt11_fck,
- &gpt12_ick,
- &gpt12_fck,
- &mcbsp1_ick,
- &mcbsp1_fck,
- &mcbsp2_ick,
- &mcbsp2_fck,
- &mcbsp3_ick,
- &mcbsp3_fck,
- &mcbsp4_ick,
- &mcbsp4_fck,
- &mcbsp5_ick,
- &mcbsp5_fck,
- &mcspi1_ick,
- &mcspi1_fck,
- &mcspi2_ick,
- &mcspi2_fck,
- &mcspi3_ick,
- &mcspi3_fck,
- &uart1_ick,
- &uart1_fck,
- &uart2_ick,
- &uart2_fck,
- &uart3_ick,
- &uart3_fck,
- &gpios_ick,
- &gpios_fck,
- &mpu_wdt_ick,
- &mpu_wdt_fck,
- &sync_32k_ick,
- &wdt1_ick,
- &omapctrl_ick,
- &icr_ick,
- &cam_fck,
- &cam_ick,
- &mailboxes_ick,
- &wdt4_ick,
- &wdt4_fck,
- &wdt3_ick,
- &wdt3_fck,
- &mspro_ick,
- &mspro_fck,
- &mmc_ick,
- &mmc_fck,
- &fac_ick,
- &fac_fck,
- &eac_ick,
- &eac_fck,
- &hdq_ick,
- &hdq_fck,
- &i2c1_ick,
- &i2c1_fck,
- &i2chs1_fck,
- &i2c2_ick,
- &i2c2_fck,
- &i2chs2_fck,
- &vlynq_ick,
- &vlynq_fck,
- &sdrc_ick,
- &des_ick,
- &sha_ick,
- &rng_ick,
- &aes_ick,
- &pka_ick,
- &usb_fck,
- &usbhs_ick,
- &mmchs1_ick,
- &mmchs1_fck,
- &mmchs2_ick,
- &mmchs2_fck,
- &gpio5_ick,
- &gpio5_fck,
- &mdm_intc_ick,
- &mmchsdb1_fck,
- &mmchsdb2_fck,
-};
#endif
--- /dev/null
+/*
+ * linux/arch/arm/mach-omap2/clock.c
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2008 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+#include <asm/div64.h>
+#include <asm/bitops.h>
+
+#include "memory.h"
+#include "clock.h"
+#include "clock24xx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
+#define EN_APLL_STOPPED 0
+#define EN_APLL_LOCKED 3
+
+/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
+#define APLLS_CLKIN_19_2MHZ 0
+#define APLLS_CLKIN_13MHZ 2
+#define APLLS_CLKIN_12MHZ 3
+
+/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
+
+static struct prcm_config *curr_prcm_set;
+static struct clk *vclk;
+static struct clk *sclk;
+
+/*-------------------------------------------------------------------------
+ * Omap24xx specific clock functions
+ *-------------------------------------------------------------------------*/
+
+/* This actually returns the rate of core_ck, not dpll_ck. */
+static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
+{
+ long long dpll_clk;
+ u8 amult;
+
+ dpll_clk = omap2_get_dpll_rate(tclk);
+
+ amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+ amult &= OMAP24XX_CORE_CLK_SRC_MASK;
+ dpll_clk *= amult;
+
+ return dpll_clk;
+}
+
+static int omap2_enable_osc_ck(struct clk *clk)
+{
+ u32 pcc;
+
+ pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+
+ __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
+ OMAP24XX_PRCM_CLKSRC_CTRL);
+
+ return 0;
+}
+
+static void omap2_disable_osc_ck(struct clk *clk)
+{
+ u32 pcc;
+
+ pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+
+ __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
+ OMAP24XX_PRCM_CLKSRC_CTRL);
+}
+
+#ifdef OLD_CK
+/* Recalculate SYST_CLK */
+static void omap2_sys_clk_recalc(struct clk * clk)
+{
+ u32 div = PRCM_CLKSRC_CTRL;
+ div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
+ div >>= clk->rate_offset;
+ clk->rate = (clk->parent->rate / div);
+ propagate_rate(clk);
+}
+#endif /* OLD_CK */
+
+/* Enable an APLL if off */
+static int omap2_clk_fixed_enable(struct clk *clk)
+{
+ u32 cval, apll_mask;
+
+ apll_mask = EN_APLL_LOCKED << clk->enable_bit;
+
+ cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+
+ if ((cval & apll_mask) == apll_mask)
+ return 0; /* apll already enabled */
+
+ cval &= ~apll_mask;
+ cval |= apll_mask;
+ cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+
+ if (clk == &apll96_ck)
+ cval = OMAP24XX_ST_96M_APLL;
+ else if (clk == &apll54_ck)
+ cval = OMAP24XX_ST_54M_APLL;
+
+ omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
+ clk->name);
+
+ /*
+ * REVISIT: Should we return an error code if omap2_wait_clock_ready()
+ * fails?
+ */
+ return 0;
+}
+
+/* Stop APLL */
+static void omap2_clk_fixed_disable(struct clk *clk)
+{
+ u32 cval;
+
+ cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+ cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
+ cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+}
+
+/*
+ * Uses the current prcm set to tell if a rate is valid.
+ * You can go slower, but not faster within a given rate set.
+ */
+static u32 omap2_dpll_round_rate(unsigned long target_rate)
+{
+ u32 high, low, core_clk_src;
+
+ core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+ core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+ if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
+ high = curr_prcm_set->dpll_speed * 2;
+ low = curr_prcm_set->dpll_speed;
+ } else { /* DPLL clockout x 2 */
+ high = curr_prcm_set->dpll_speed;
+ low = curr_prcm_set->dpll_speed / 2;
+ }
+
+#ifdef DOWN_VARIABLE_DPLL
+ if (target_rate > high)
+ return high;
+ else
+ return target_rate;
+#else
+ if (target_rate > low)
+ return high;
+ else
+ return low;
+#endif
+
+}
+
+static void omap2_dpll_recalc(struct clk *clk)
+{
+ clk->rate = omap2_get_dpll_rate_24xx(clk);
+
+ propagate_rate(clk);
+}
+
+static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
+{
+ u32 cur_rate, low, mult, div, valid_rate, done_rate;
+ u32 bypass = 0;
+ struct prcm_config tmpset;
+ const struct dpll_data *dd;
+ unsigned long flags;
+ int ret = -EINVAL;
+
+ local_irq_save(flags);
+ cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+ mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+ mult &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+ if ((rate == (cur_rate / 2)) && (mult == 2)) {
+ omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+ } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
+ omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+ } else if (rate != cur_rate) {
+ valid_rate = omap2_dpll_round_rate(rate);
+ if (valid_rate != rate)
+ goto dpll_exit;
+
+ if (mult == 1)
+ low = curr_prcm_set->dpll_speed;
+ else
+ low = curr_prcm_set->dpll_speed / 2;
+
+ dd = clk->dpll_data;
+ if (!dd)
+ goto dpll_exit;
+
+ tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+ tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
+ dd->div1_mask);
+ div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
+ tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+ tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
+ if (rate > low) {
+ tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
+ mult = ((rate / 2) / 1000000);
+ done_rate = CORE_CLK_SRC_DPLL_X2;
+ } else {
+ tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
+ mult = (rate / 1000000);
+ done_rate = CORE_CLK_SRC_DPLL;
+ }
+ tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
+ tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
+
+ /* Worst case */
+ tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
+
+ if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
+ bypass = 1;
+
+ omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
+
+ /* Force dll lock mode */
+ omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
+ bypass);
+
+ /* Errata: ret dll entry state */
+ omap2_init_memory_params(omap2_dll_force_needed());
+ omap2_reprogram_sdrc(done_rate, 0);
+ }
+ omap2_dpll_recalc(&dpll_ck);
+ ret = 0;
+
+dpll_exit:
+ local_irq_restore(flags);
+ return(ret);
+}
+
+/**
+ * omap2_table_mpu_recalc - just return the MPU speed
+ * @clk: virt_prcm_set struct clk
+ *
+ * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
+ */
+static void omap2_table_mpu_recalc(struct clk *clk)
+{
+ clk->rate = curr_prcm_set->mpu_speed;
+}
+
+/*
+ * Look for a rate equal or less than the target rate given a configuration set.
+ *
+ * What's not entirely clear is "which" field represents the key field.
+ * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
+ * just uses the ARM rates.
+ */
+static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
+{
+ struct prcm_config *ptr;
+ long highest_rate;
+
+ if (clk != &virt_prcm_set)
+ return -EINVAL;
+
+ highest_rate = -EINVAL;
+
+ for (ptr = rate_table; ptr->mpu_speed; ptr++) {
+ if (!(ptr->flags & cpu_mask))
+ continue;
+ if (ptr->xtal_speed != sys_ck.rate)
+ continue;
+
+ highest_rate = ptr->mpu_speed;
+
+ /* Can check only after xtal frequency check */
+ if (ptr->mpu_speed <= rate)
+ break;
+ }
+ return highest_rate;
+}
+
+/* Sets basic clocks based on the specified rate */
+static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
+{
+ u32 cur_rate, done_rate, bypass = 0, tmp;
+ struct prcm_config *prcm;
+ unsigned long found_speed = 0;
+ unsigned long flags;
+
+ if (clk != &virt_prcm_set)
+ return -EINVAL;
+
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+ if (!(prcm->flags & cpu_mask))
+ continue;
+
+ if (prcm->xtal_speed != sys_ck.rate)
+ continue;
+
+ if (prcm->mpu_speed <= rate) {
+ found_speed = prcm->mpu_speed;
+ break;
+ }
+ }
+
+ if (!found_speed) {
+ printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
+ rate / 1000000);
+ return -EINVAL;
+ }
+
+ curr_prcm_set = prcm;
+ cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+
+ if (prcm->dpll_speed == cur_rate / 2) {
+ omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+ } else if (prcm->dpll_speed == cur_rate * 2) {
+ omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+ } else if (prcm->dpll_speed != cur_rate) {
+ local_irq_save(flags);
+
+ if (prcm->dpll_speed == prcm->xtal_speed)
+ bypass = 1;
+
+ if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
+ CORE_CLK_SRC_DPLL_X2)
+ done_rate = CORE_CLK_SRC_DPLL_X2;
+ else
+ done_rate = CORE_CLK_SRC_DPLL;
+
+ /* MPU divider */
+ cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
+
+ /* dsp + iva1 div(2420), iva2.1(2430) */
+ cm_write_mod_reg(prcm->cm_clksel_dsp,
+ OMAP24XX_DSP_MOD, CM_CLKSEL);
+
+ cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
+
+ /* Major subsystem dividers */
+ tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
+ cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
+ if (cpu_is_omap2430())
+ cm_write_mod_reg(prcm->cm_clksel_mdm,
+ OMAP2430_MDM_MOD, CM_CLKSEL);
+
+ /* x2 to enter init_mem */
+ omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+
+ omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
+ bypass);
+
+ omap2_init_memory_params(omap2_dll_force_needed());
+ omap2_reprogram_sdrc(done_rate, 0);
+
+ local_irq_restore(flags);
+ }
+ omap2_dpll_recalc(&dpll_ck);
+
+ return 0;
+}
+
+static struct clk_functions omap2_clk_functions = {
+ .clk_enable = omap2_clk_enable,
+ .clk_disable = omap2_clk_disable,
+ .clk_round_rate = omap2_clk_round_rate,
+ .clk_set_rate = omap2_clk_set_rate,
+ .clk_set_parent = omap2_clk_set_parent,
+ .clk_disable_unused = omap2_clk_disable_unused,
+};
+
+static u32 omap2_get_apll_clkin(void)
+{
+ u32 aplls, sclk = 0;
+
+ aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+ aplls &= OMAP24XX_APLLS_CLKIN_MASK;
+ aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
+
+ if (aplls == APLLS_CLKIN_19_2MHZ)
+ sclk = 19200000;
+ else if (aplls == APLLS_CLKIN_13MHZ)
+ sclk = 13000000;
+ else if (aplls == APLLS_CLKIN_12MHZ)
+ sclk = 12000000;
+
+ return sclk;
+}
+
+static u32 omap2_get_sysclkdiv(void)
+{
+ u32 div;
+
+ div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+ div &= OMAP_SYSCLKDIV_MASK;
+ div >>= OMAP_SYSCLKDIV_SHIFT;
+
+ return div;
+}
+
+static void omap2_osc_clk_recalc(struct clk *clk)
+{
+ clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
+ propagate_rate(clk);
+}
+
+static void omap2_sys_clk_recalc(struct clk *clk)
+{
+ clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
+ propagate_rate(clk);
+}
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
+{
+ u32 rate;
+
+ if (vclk == NULL || sclk == NULL)
+ return;
+
+ rate = clk_get_rate(sclk);
+ clk_set_rate(vclk, rate);
+}
+
+/*
+ * Switch the MPU rate if specified on cmdline.
+ * We cannot do this early until cmdline is parsed.
+ */
+static int __init omap2_clk_arch_init(void)
+{
+ if (!mpurate)
+ return -EINVAL;
+
+ if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+ printk(KERN_ERR "Could not find matching MPU rate\n");
+
+ recalculate_root_clocks();
+
+ printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
+ "%ld.%01ld/%ld/%ld MHz\n",
+ (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+ (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+ return 0;
+}
+arch_initcall(omap2_clk_arch_init);
+
+int __init omap2_clk_init(void)
+{
+ struct prcm_config *prcm;
+ struct clk **clkp;
+ u32 clkrate;
+
+ if (cpu_is_omap242x())
+ cpu_mask = RATE_IN_242X;
+ else if (cpu_is_omap2430())
+ cpu_mask = RATE_IN_243X;
+
+ clk_init(&omap2_clk_functions);
+
+ omap2_osc_clk_recalc(&osc_ck);
+ omap2_sys_clk_recalc(&sys_ck);
+
+ for (clkp = onchip_24xx_clks;
+ clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
+ clkp++) {
+
+ if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
+ clk_register(*clkp);
+ continue;
+ }
+
+ if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
+ clk_register(*clkp);
+ continue;
+ }
+ }
+
+ /* Check the MPU rate set by bootloader */
+ clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+ if (!(prcm->flags & cpu_mask))
+ continue;
+ if (prcm->xtal_speed != sys_ck.rate)
+ continue;
+ if (prcm->dpll_speed <= clkrate)
+ break;
+ }
+ curr_prcm_set = prcm;
+
+ recalculate_root_clocks();
+
+ printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
+ "%ld.%01ld/%ld/%ld MHz\n",
+ (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+ (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+ /*
+ * Only enable those clocks we will need, let the drivers
+ * enable other clocks as necessary
+ */
+ clk_enable_init_clocks();
+
+ /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
+ vclk = clk_get(NULL, "virt_prcm_set");
+ sclk = clk_get(NULL, "sys_ck");
+
+ return 0;
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-omap2/clock24xx.h
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2008 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
+
+#include "clock.h"
+
+#include "prm.h"
+#include "cm.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+
+static void omap2_table_mpu_recalc(struct clk *clk);
+static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
+static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
+static void omap2_sys_clk_recalc(struct clk *clk);
+static void omap2_osc_clk_recalc(struct clk *clk);
+static void omap2_sys_clk_recalc(struct clk *clk);
+static void omap2_dpll_recalc(struct clk *clk);
+static int omap2_clk_fixed_enable(struct clk *clk);
+static void omap2_clk_fixed_disable(struct clk *clk);
+static int omap2_enable_osc_ck(struct clk *clk);
+static void omap2_disable_osc_ck(struct clk *clk);
+static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
+
+/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
+ * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ */
+struct prcm_config {
+ unsigned long xtal_speed; /* crystal rate */
+ unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
+ unsigned long mpu_speed; /* speed of MPU */
+ unsigned long cm_clksel_mpu; /* mpu divider */
+ unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
+ unsigned long cm_clksel_gfx; /* gfx dividers */
+ unsigned long cm_clksel1_core; /* major subsystem dividers */
+ unsigned long cm_clksel1_pll; /* m,n */
+ unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
+ unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
+ unsigned long base_sdrc_rfr; /* base refresh timing for a set */
+ unsigned char flags;
+};
+
+/*
+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
+ * These configurations are characterized by voltage and speed for clocks.
+ * The device is only validated for certain combinations. One way to express
+ * these combinations is via the 'ratio's' which the clocks operate with
+ * respect to each other. These ratio sets are for a given voltage/DPLL
+ * setting. All configurations can be described by a DPLL setting and a ratio
+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ *
+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
+ * 2430 (iva2.1, NOdsp, mdm)
+ */
+
+/* Core fields for cm_clksel, not ratio governed */
+#define RX_CLKSEL_DSS1 (0x10 << 8)
+#define RX_CLKSEL_DSS2 (0x0 << 13)
+#define RX_CLKSEL_SSI (0x5 << 20)
+
+/*-------------------------------------------------------------------------
+ * Voltage/DPLL ratios
+ *-------------------------------------------------------------------------*/
+
+/* 2430 Ratio's, 2430-Ratio Config 1 */
+#define R1_CLKSEL_L3 (4 << 0)
+#define R1_CLKSEL_L4 (2 << 5)
+#define R1_CLKSEL_USB (4 << 25)
+#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
+ RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+ R1_CLKSEL_L4 | R1_CLKSEL_L3
+#define R1_CLKSEL_MPU (2 << 0)
+#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
+#define R1_CLKSEL_DSP (2 << 0)
+#define R1_CLKSEL_DSP_IF (2 << 5)
+#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
+#define R1_CLKSEL_GFX (2 << 0)
+#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
+#define R1_CLKSEL_MDM (4 << 0)
+#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
+
+/* 2430-Ratio Config 2 */
+#define R2_CLKSEL_L3 (6 << 0)
+#define R2_CLKSEL_L4 (2 << 5)
+#define R2_CLKSEL_USB (2 << 25)
+#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
+ RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+ R2_CLKSEL_L4 | R2_CLKSEL_L3
+#define R2_CLKSEL_MPU (2 << 0)
+#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
+#define R2_CLKSEL_DSP (2 << 0)
+#define R2_CLKSEL_DSP_IF (3 << 5)
+#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
+#define R2_CLKSEL_GFX (2 << 0)
+#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
+#define R2_CLKSEL_MDM (6 << 0)
+#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
+
+/* 2430-Ratio Bootm (BYPASS) */
+#define RB_CLKSEL_L3 (1 << 0)
+#define RB_CLKSEL_L4 (1 << 5)
+#define RB_CLKSEL_USB (1 << 25)
+#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
+ RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+ RB_CLKSEL_L4 | RB_CLKSEL_L3
+#define RB_CLKSEL_MPU (1 << 0)
+#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
+#define RB_CLKSEL_DSP (1 << 0)
+#define RB_CLKSEL_DSP_IF (1 << 5)
+#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
+#define RB_CLKSEL_GFX (1 << 0)
+#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
+#define RB_CLKSEL_MDM (1 << 0)
+#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
+
+/* 2420 Ratio Equivalents */
+#define RXX_CLKSEL_VLYNQ (0x12 << 15)
+#define RXX_CLKSEL_SSI (0x8 << 20)
+
+/* 2420-PRCM III 532MHz core */
+#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
+#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
+#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
+#define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
+ RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
+ RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
+ RIII_CLKSEL_L3
+#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
+#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
+#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
+#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
+#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
+#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
+#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
+#define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
+ RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
+ RIII_CLKSEL_DSP
+#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
+#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
+
+/* 2420-PRCM II 600MHz core */
+#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
+#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
+#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
+#define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
+ RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+ RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+ RII_CLKSEL_L4 | RII_CLKSEL_L3
+#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
+#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
+#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
+#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
+#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
+#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
+#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
+#define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
+ RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
+ RII_CLKSEL_DSP
+#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
+#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
+
+/* 2420-PRCM I 660MHz core */
+#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
+#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
+#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
+#define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
+ RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+ RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+ RI_CLKSEL_L4 | RI_CLKSEL_L3
+#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
+#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
+#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
+#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
+#define RI_SYNC_DSP (1 << 7) /* Activate sync */
+#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
+#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
+#define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
+ RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
+ RI_CLKSEL_DSP
+#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
+#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
+
+/* 2420-PRCM VII (boot) */
+#define RVII_CLKSEL_L3 (1 << 0)
+#define RVII_CLKSEL_L4 (1 << 5)
+#define RVII_CLKSEL_DSS1 (1 << 8)
+#define RVII_CLKSEL_DSS2 (0 << 13)
+#define RVII_CLKSEL_VLYNQ (1 << 15)
+#define RVII_CLKSEL_SSI (1 << 20)
+#define RVII_CLKSEL_USB (1 << 25)
+
+#define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
+ RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
+ RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
+
+#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
+#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
+
+#define RVII_CLKSEL_DSP (1 << 0)
+#define RVII_CLKSEL_DSP_IF (1 << 5)
+#define RVII_SYNC_DSP (0 << 7)
+#define RVII_CLKSEL_IVA (1 << 8)
+#define RVII_SYNC_IVA (0 << 13)
+#define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
+ RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
+
+#define RVII_CLKSEL_GFX (1 << 0)
+#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
+
+/*-------------------------------------------------------------------------
+ * 2430 Target modes: Along with each configuration the CPU has several
+ * modes which goes along with them. Modes mainly are the addition of
+ * describe DPLL combinations to go along with a ratio.
+ *-------------------------------------------------------------------------*/
+
+/* Hardware governed */
+#define MX_48M_SRC (0 << 3)
+#define MX_54M_SRC (0 << 5)
+#define MX_APLLS_CLIKIN_12 (3 << 23)
+#define MX_APLLS_CLIKIN_13 (2 << 23)
+#define MX_APLLS_CLIKIN_19_2 (0 << 23)
+
+/*
+ * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
+ * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
+ */
+#define M5A_DPLL_MULT_12 (133 << 12)
+#define M5A_DPLL_DIV_12 (5 << 8)
+#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
+ M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
+ MX_APLLS_CLIKIN_12
+#define M5A_DPLL_MULT_13 (61 << 12)
+#define M5A_DPLL_DIV_13 (2 << 8)
+#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
+ M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
+ MX_APLLS_CLIKIN_13
+#define M5A_DPLL_MULT_19 (55 << 12)
+#define M5A_DPLL_DIV_19 (3 << 8)
+#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
+ M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
+ MX_APLLS_CLIKIN_19_2
+/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
+#define M5B_DPLL_MULT_12 (50 << 12)
+#define M5B_DPLL_DIV_12 (2 << 8)
+#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
+ M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
+ MX_APLLS_CLIKIN_12
+#define M5B_DPLL_MULT_13 (200 << 12)
+#define M5B_DPLL_DIV_13 (12 << 8)
+
+#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
+ M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
+ MX_APLLS_CLIKIN_13
+#define M5B_DPLL_MULT_19 (125 << 12)
+#define M5B_DPLL_DIV_19 (31 << 8)
+#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
+ M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
+ MX_APLLS_CLIKIN_19_2
+/*
+ * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
+ */
+#define M4_DPLL_MULT_12 (133 << 12)
+#define M4_DPLL_DIV_12 (3 << 8)
+#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
+ M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
+ MX_APLLS_CLIKIN_12
+
+#define M4_DPLL_MULT_13 (399 << 12)
+#define M4_DPLL_DIV_13 (12 << 8)
+#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
+ M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
+ MX_APLLS_CLIKIN_13
+
+#define M4_DPLL_MULT_19 (145 << 12)
+#define M4_DPLL_DIV_19 (6 << 8)
+#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
+ M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
+ MX_APLLS_CLIKIN_19_2
+
+/*
+ * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
+ */
+#define M3_DPLL_MULT_12 (55 << 12)
+#define M3_DPLL_DIV_12 (1 << 8)
+#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
+ M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
+ MX_APLLS_CLIKIN_12
+#define M3_DPLL_MULT_13 (76 << 12)
+#define M3_DPLL_DIV_13 (2 << 8)
+#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
+ M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
+ MX_APLLS_CLIKIN_13
+#define M3_DPLL_MULT_19 (17 << 12)
+#define M3_DPLL_DIV_19 (0 << 8)
+#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
+ M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
+ MX_APLLS_CLIKIN_19_2
+
+/*
+ * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
+ */
+#define M2_DPLL_MULT_12 (55 << 12)
+#define M2_DPLL_DIV_12 (1 << 8)
+#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
+ M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
+ MX_APLLS_CLIKIN_12
+
+/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
+ * relock time issue */
+/* Core frequency changed from 330/165 to 329/164 MHz*/
+#define M2_DPLL_MULT_13 (76 << 12)
+#define M2_DPLL_DIV_13 (2 << 8)
+#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
+ M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
+ MX_APLLS_CLIKIN_13
+
+#define M2_DPLL_MULT_19 (17 << 12)
+#define M2_DPLL_DIV_19 (0 << 8)
+#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
+ M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
+ MX_APLLS_CLIKIN_19_2
+
+/* boot (boot) */
+#define MB_DPLL_MULT (1 << 12)
+#define MB_DPLL_DIV (0 << 8)
+#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+ MB_DPLL_MULT | MX_APLLS_CLIKIN_12
+
+#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+ MB_DPLL_MULT | MX_APLLS_CLIKIN_13
+
+#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+ MB_DPLL_MULT | MX_APLLS_CLIKIN_19
+
+/*
+ * 2430 - chassis (sedna)
+ * 165 (ratio1) same as above #2
+ * 150 (ratio1)
+ * 133 (ratio2) same as above #4
+ * 110 (ratio2) same as above #3
+ * 104 (ratio2)
+ * boot (boot)
+ */
+
+/* PRCM I target DPLL = 2*330MHz = 660MHz */
+#define MI_DPLL_MULT_12 (55 << 12)
+#define MI_DPLL_DIV_12 (1 << 8)
+#define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
+ MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
+ MX_APLLS_CLIKIN_12
+
+/*
+ * 2420 Equivalent - mode registers
+ * PRCM II , target DPLL = 2*300MHz = 600MHz
+ */
+#define MII_DPLL_MULT_12 (50 << 12)
+#define MII_DPLL_DIV_12 (1 << 8)
+#define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
+ MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
+ MX_APLLS_CLIKIN_12
+#define MII_DPLL_MULT_13 (300 << 12)
+#define MII_DPLL_DIV_13 (12 << 8)
+#define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
+ MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
+ MX_APLLS_CLIKIN_13
+
+/* PRCM III target DPLL = 2*266 = 532MHz*/
+#define MIII_DPLL_MULT_12 (133 << 12)
+#define MIII_DPLL_DIV_12 (5 << 8)
+#define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
+ MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
+ MX_APLLS_CLIKIN_12
+#define MIII_DPLL_MULT_13 (266 << 12)
+#define MIII_DPLL_DIV_13 (12 << 8)
+#define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
+ MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
+ MX_APLLS_CLIKIN_13
+
+/* PRCM VII (boot bypass) */
+#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
+#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
+
+/* High and low operation value */
+#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
+#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
+
+/* MPU speed defines */
+#define S12M 12000000
+#define S13M 13000000
+#define S19M 19200000
+#define S26M 26000000
+#define S100M 100000000
+#define S133M 133000000
+#define S150M 150000000
+#define S164M 164000000
+#define S165M 165000000
+#define S199M 199000000
+#define S200M 200000000
+#define S266M 266000000
+#define S300M 300000000
+#define S329M 329000000
+#define S330M 330000000
+#define S399M 399000000
+#define S400M 400000000
+#define S532M 532000000
+#define S600M 600000000
+#define S658M 658000000
+#define S660M 660000000
+#define S798M 798000000
+
+/*-------------------------------------------------------------------------
+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
+ * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
+ * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ *
+ * Filling in table based on H4 boards and 2430-SDPs variants available.
+ * There are quite a few more rates combinations which could be defined.
+ *
+ * When multiple values are defined the start up will try and choose the
+ * fastest one. If a 'fast' value is defined, then automatically, the /2
+ * one should be included as it can be used. Generally having more that
+ * one fast set does not make sense, as static timings need to be changed
+ * to change the set. The exception is the bypass setting which is
+ * availble for low power bypass.
+ *
+ * Note: This table needs to be sorted, fastest to slowest.
+ *-------------------------------------------------------------------------*/
+static struct prcm_config rate_table[] = {
+ /* PRCM I - FAST */
+ {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
+ RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
+ RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
+ RATE_IN_242X},
+
+ /* PRCM II - FAST */
+ {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
+ RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+ RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+ RATE_IN_242X},
+
+ {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
+ RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+ RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+ RATE_IN_242X},
+
+ /* PRCM III - FAST */
+ {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
+ RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+ RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+ RATE_IN_242X},
+
+ {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
+ RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+ RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+ RATE_IN_242X},
+
+ /* PRCM II - SLOW */
+ {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
+ RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+ RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+ RATE_IN_242X},
+
+ {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
+ RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+ RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+ RATE_IN_242X},
+
+ /* PRCM III - SLOW */
+ {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
+ RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+ RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+ RATE_IN_242X},
+
+ {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
+ RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+ RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+ RATE_IN_242X},
+
+ /* PRCM-VII (boot-bypass) */
+ {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
+ RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+ RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+ RATE_IN_242X},
+
+ /* PRCM-VII (boot-bypass) */
+ {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
+ RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+ RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+ RATE_IN_242X},
+
+ /* PRCM #4 - ratio2 (ES2.1) - FAST */
+ {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
+ R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+ R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
+ SDRC_RFR_CTRL_133MHz,
+ RATE_IN_243X},
+
+ /* PRCM #2 - ratio1 (ES2) - FAST */
+ {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
+ R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+ R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+ SDRC_RFR_CTRL_165MHz,
+ RATE_IN_243X},
+
+ /* PRCM #5a - ratio1 - FAST */
+ {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
+ R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+ R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+ SDRC_RFR_CTRL_133MHz,
+ RATE_IN_243X},
+
+ /* PRCM #5b - ratio1 - FAST */
+ {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
+ R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+ R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+ SDRC_RFR_CTRL_100MHz,
+ RATE_IN_243X},
+
+ /* PRCM #4 - ratio1 (ES2.1) - SLOW */
+ {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
+ R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+ R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
+ SDRC_RFR_CTRL_133MHz,
+ RATE_IN_243X},
+
+ /* PRCM #2 - ratio1 (ES2) - SLOW */
+ {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
+ R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+ R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+ SDRC_RFR_CTRL_165MHz,
+ RATE_IN_243X},
+
+ /* PRCM #5a - ratio1 - SLOW */
+ {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
+ R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+ R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+ SDRC_RFR_CTRL_133MHz,
+ RATE_IN_243X},
+
+ /* PRCM #5b - ratio1 - SLOW*/
+ {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
+ R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+ R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+ SDRC_RFR_CTRL_100MHz,
+ RATE_IN_243X},
+
+ /* PRCM-boot/bypass */
+ {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
+ RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+ RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+ SDRC_RFR_CTRL_BYPASS,
+ RATE_IN_243X},
+
+ /* PRCM-boot/bypass */
+ {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
+ RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+ RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+ SDRC_RFR_CTRL_BYPASS,
+ RATE_IN_243X},
+
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+};
+
+/*-------------------------------------------------------------------------
+ * 24xx clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In many
+ * cases the parent is selectable. The get/set parent calls will also
+ * switch sources.
+ *
+ * Many some clocks say always_enabled, but they can be auto idled for
+ * power savings. They will always be available upon clock request.
+ *
+ * Several sources are given initial rates which may be wrong, this will
+ * be fixed up in the init func.
+ *
+ * Things are broadly separated below by clock domains. It is
+ * noteworthy that most periferals have dependencies on multiple clock
+ * domains. Many get their interface clocks from the L4 domain, but get
+ * functional clocks from fixed sources or other core domain derived
+ * clocks.
+ *-------------------------------------------------------------------------*/
+
+/* Base external input clocks */
+static struct clk func_32k_ck = {
+ .name = "func_32k_ck",
+ .rate = 32000,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+ .recalc = &propagate_rate,
+};
+
+/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
+static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
+ .name = "osc_ck",
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_PROPAGATES,
+ .enable = &omap2_enable_osc_ck,
+ .disable = &omap2_disable_osc_ck,
+ .recalc = &omap2_osc_clk_recalc,
+};
+
+/* With out modem likely 12MHz, with modem likely 13MHz */
+static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
+ .name = "sys_ck", /* ~ ref_clk also */
+ .parent = &osc_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ ALWAYS_ENABLED | RATE_PROPAGATES,
+ .recalc = &omap2_sys_clk_recalc,
+};
+
+static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
+ .name = "alt_ck",
+ .rate = 54000000,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+ .recalc = &propagate_rate,
+};
+
+/*
+ * Analog domain root source clocks
+ */
+
+/* dpll_ck, is broken out in to special cases through clksel */
+/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
+ * deal with this
+ */
+
+static const struct dpll_data dpll_dd = {
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .mult_mask = OMAP24XX_DPLL_MULT_MASK,
+ .div1_mask = OMAP24XX_DPLL_DIV_MASK,
+};
+
+static struct clk dpll_ck = {
+ .name = "dpll_ck",
+ .parent = &sys_ck, /* Can be func_32k also */
+ .dpll_data = &dpll_dd,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap2_dpll_recalc,
+ .set_rate = &omap2_reprogram_dpll,
+};
+
+static struct clk apll96_ck = {
+ .name = "apll96_ck",
+ .parent = &sys_ck,
+ .rate = 96000000,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
+ .enable = &omap2_clk_fixed_enable,
+ .disable = &omap2_clk_fixed_disable,
+ .recalc = &propagate_rate,
+};
+
+static struct clk apll54_ck = {
+ .name = "apll54_ck",
+ .parent = &sys_ck,
+ .rate = 54000000,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
+ .enable = &omap2_clk_fixed_enable,
+ .disable = &omap2_clk_fixed_disable,
+ .recalc = &propagate_rate,
+};
+
+/*
+ * PRCM digital base sources
+ */
+
+/* func_54m_ck */
+
+static const struct clksel_rate func_54m_apll54_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel_rate func_54m_alt_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel func_54m_clksel[] = {
+ { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
+ { .parent = &alt_ck, .rates = func_54m_alt_rates, },
+ { .parent = NULL },
+};
+
+static struct clk func_54m_ck = {
+ .name = "func_54m_ck",
+ .parent = &apll54_ck, /* can also be alt_clk */
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_54M_SOURCE,
+ .clksel = func_54m_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk core_ck = {
+ .name = "core_ck",
+ .parent = &dpll_ck, /* can also be 32k */
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ ALWAYS_ENABLED | RATE_PROPAGATES,
+ .recalc = &followparent_recalc,
+};
+
+/* func_96m_ck */
+static const struct clksel_rate func_96m_apll96_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel_rate func_96m_alt_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel func_96m_clksel[] = {
+ { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
+ { .parent = &alt_ck, .rates = func_96m_alt_rates },
+ { .parent = NULL }
+};
+
+/* The parent of this clock is not selectable on 2420. */
+static struct clk func_96m_ck = {
+ .name = "func_96m_ck",
+ .parent = &apll96_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP2430_96M_SOURCE,
+ .clksel = func_96m_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+/* func_48m_ck */
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+ { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel func_48m_clksel[] = {
+ { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+ { .parent = &alt_ck, .rates = func_48m_alt_rates },
+ { .parent = NULL }
+};
+
+static struct clk func_48m_ck = {
+ .name = "func_48m_ck",
+ .parent = &apll96_ck, /* 96M or Alt */
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_48M_SOURCE,
+ .clksel = func_48m_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk func_12m_ck = {
+ .name = "func_12m_ck",
+ .parent = &func_48m_ck,
+ .fixed_div = 4,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_fixed_divisor_recalc,
+};
+
+/* Secure timer, only available in secure mode */
+static struct clk wdt1_osc_ck = {
+ .name = "ck_wdt1_osc",
+ .parent = &osc_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * The common_clkout* clksel_rate structs are common to
+ * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
+ * sys_clkout2_* are 2420-only, so the
+ * clksel_rate flags fields are inaccurate for those clocks. This is
+ * harmless since access to those clocks are gated by the struct clk
+ * flags fields, which mark them as 2420-only.
+ */
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+ { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel common_clkout_src_clksel[] = {
+ { .parent = &core_ck, .rates = common_clkout_src_core_rates },
+ { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
+ { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+ { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+ { .parent = NULL }
+};
+
+static struct clk sys_clkout_src = {
+ .name = "sys_clkout_src",
+ .parent = &func_54m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ RATE_PROPAGATES,
+ .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
+ .clksel = common_clkout_src_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static const struct clksel_rate common_clkout_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 2, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 8, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 16, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 0 },
+};
+
+static const struct clksel sys_clkout_clksel[] = {
+ { .parent = &sys_clkout_src, .rates = common_clkout_rates },
+ { .parent = NULL }
+};
+
+static struct clk sys_clkout = {
+ .name = "sys_clkout",
+ .parent = &sys_clkout_src,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ PARENT_CONTROLS_CLOCK,
+ .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
+ .clksel = sys_clkout_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2_src = {
+ .name = "sys_clkout2_src",
+ .parent = &func_54m_ck,
+ .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
+ .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
+ .clksel = common_clkout_src_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+ { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
+ { .parent = NULL }
+};
+
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2 = {
+ .name = "sys_clkout2",
+ .parent = &sys_clkout2_src,
+ .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
+ .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
+ .clksel = sys_clkout2_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk emul_ck = {
+ .name = "emul_ck",
+ .parent = &func_54m_ck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
+ .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
+ .recalc = &followparent_recalc,
+
+};
+
+/*
+ * MPU clock domain
+ * Clocks:
+ * MPU_FCLK, MPU_ICLK
+ * INT_M_FCLK, INT_M_I_CLK
+ *
+ * - Individual clocks are hardware managed.
+ * - Base divider comes from: CM_CLKSEL_MPU
+ *
+ */
+static const struct clksel_rate mpu_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_242X },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 0 },
+};
+
+static const struct clksel mpu_clksel[] = {
+ { .parent = &core_ck, .rates = mpu_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk mpu_ck = { /* Control cpu */
+ .name = "mpu_ck",
+ .parent = &core_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ ALWAYS_ENABLED | DELAYED_APP |
+ CONFIG_PARTICIPANT | RATE_PROPAGATES,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
+ .clksel = mpu_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+/*
+ * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
+ * Clocks:
+ * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
+ * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
+ *
+ * Won't be too specific here. The core clock comes into this block
+ * it is divided then tee'ed. One branch goes directly to xyz enable
+ * controls. The other branch gets further divided by 2 then possibly
+ * routed into a synchronizer and out of clocks abc.
+ */
+static const struct clksel_rate dsp_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 12, .val = 12, .flags = RATE_IN_242X },
+ { .div = 0 },
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+ { .parent = &core_ck, .rates = dsp_fck_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk dsp_fck = {
+ .name = "dsp_fck",
+ .parent = &core_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
+ CONFIG_PARTICIPANT | RATE_PROPAGATES,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
+ .clksel = dsp_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+/* DSP interface clock */
+static const struct clksel_rate dsp_irate_ick_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_243X },
+ { .div = 0 },
+};
+
+static const struct clksel dsp_irate_ick_clksel[] = {
+ { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
+ { .parent = NULL }
+};
+
+/*
+ * This clock does not exist as such in the TRM, but is added to
+ * separate source selection from XXX
+ */
+static struct clk dsp_irate_ick = {
+ .name = "dsp_irate_ick",
+ .parent = &dsp_fck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
+ CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
+ .clksel = dsp_irate_ick_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+/* 2420 only */
+static struct clk dsp_ick = {
+ .name = "dsp_ick", /* apparently ipi and isp */
+ .parent = &dsp_irate_ick,
+ .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
+};
+
+/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
+static struct clk iva2_1_ick = {
+ .name = "iva2_1_ick",
+ .parent = &dsp_irate_ick,
+ .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+};
+
+static struct clk iva1_ifck = {
+ .name = "iva1_ifck",
+ .parent = &core_ck,
+ .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
+ RATE_PROPAGATES | DELAYED_APP,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
+ .clksel = dsp_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+/* IVA1 mpu/int/i/f clocks are /2 of parent */
+static struct clk iva1_mpu_int_ifck = {
+ .name = "iva1_mpu_int_ifck",
+ .parent = &iva1_ifck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
+ .fixed_div = 2,
+ .recalc = &omap2_fixed_divisor_recalc,
+};
+
+/*
+ * L3 clock domain
+ * L3 clocks are used for both interface and functional clocks to
+ * multiple entities. Some of these clocks are completely managed
+ * by hardware, and some others allow software control. Hardware
+ * managed ones general are based on directly CLK_REQ signals and
+ * various auto idle settings. The functional spec sets many of these
+ * as 'tie-high' for their enables.
+ *
+ * I-CLOCKS:
+ * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
+ * CAM, HS-USB.
+ * F-CLOCK
+ * SSI.
+ *
+ * GPMC memories and SDRC have timing and clock sensitive registers which
+ * may very well need notification when the clock changes. Currently for low
+ * operating points, these are taken care of in sleep.S.
+ */
+static const struct clksel_rate core_l3_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_242X },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 12, .val = 12, .flags = RATE_IN_242X },
+ { .div = 16, .val = 16, .flags = RATE_IN_242X },
+ { .div = 0 }
+};
+
+static const struct clksel core_l3_clksel[] = {
+ { .parent = &core_ck, .rates = core_l3_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
+ .name = "core_l3_ck",
+ .parent = &core_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ ALWAYS_ENABLED | DELAYED_APP |
+ CONFIG_PARTICIPANT | RATE_PROPAGATES,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
+ .clksel = core_l3_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+/* usb_l4_ick */
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel usb_l4_ick_clksel[] = {
+ { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+ { .parent = NULL },
+};
+
+static struct clk usb_l4_ick = { /* FS-USB interface clock */
+ .name = "usb_l4_ick",
+ .parent = &core_l3_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ DELAYED_APP | CONFIG_PARTICIPANT,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_USB_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
+ .clksel = usb_l4_ick_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+/*
+ * SSI is in L3 management domain, its direct parent is core not l3,
+ * many core power domain entities are grouped into the L3 clock
+ * domain.
+ * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
+ *
+ * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
+ */
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_243X },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+ { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk ssi_ssr_sst_fck = {
+ .name = "ssi_fck",
+ .parent = &core_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ DELAYED_APP,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_SSI_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
+ .clksel = ssi_ssr_sst_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+/*
+ * GFX clock domain
+ * Clocks:
+ * GFX_FCLK, GFX_ICLK
+ * GFX_CG1(2d), GFX_CG2(3d)
+ *
+ * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
+ * The 2d and 3d clocks run at a hardware determined
+ * divided value of fclk.
+ *
+ */
+/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
+
+/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
+static const struct clksel gfx_fck_clksel[] = {
+ { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+ { .parent = NULL },
+};
+
+static struct clk gfx_3d_fck = {
+ .name = "gfx_3d_fck",
+ .parent = &core_l3_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_3D_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP_CLKSEL_GFX_MASK,
+ .clksel = gfx_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk gfx_2d_fck = {
+ .name = "gfx_2d_fck",
+ .parent = &core_l3_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_2D_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP_CLKSEL_GFX_MASK,
+ .clksel = gfx_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk gfx_ick = {
+ .name = "gfx_ick", /* From l3 */
+ .parent = &core_l3_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+ .enable_bit = OMAP_EN_GFX_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * Modem clock domain (2430)
+ * CLOCKS:
+ * MDM_OSC_CLK
+ * MDM_ICLK
+ * These clocks are usable in chassis mode only.
+ */
+static const struct clksel_rate mdm_ick_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_243X },
+ { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
+ { .div = 6, .val = 6, .flags = RATE_IN_243X },
+ { .div = 9, .val = 9, .flags = RATE_IN_243X },
+ { .div = 0 }
+};
+
+static const struct clksel mdm_ick_clksel[] = {
+ { .parent = &core_ck, .rates = mdm_ick_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk mdm_ick = { /* used both as a ick and fck */
+ .name = "mdm_ick",
+ .parent = &core_ck,
+ .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+ .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
+ .clksel = mdm_ick_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk mdm_osc_ck = {
+ .name = "mdm_osc_ck",
+ .parent = &osc_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
+ .enable_bit = OMAP2430_EN_OSC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * L4 clock management domain
+ *
+ * This domain contains lots of interface clocks from the L4 interface, some
+ * functional clocks. Fixed APLL functional source clocks are managed in
+ * this domain.
+ */
+static const struct clksel_rate l4_core_l3_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 0 }
+};
+
+static const struct clksel l4_clksel[] = {
+ { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
+ { .parent = NULL }
+};
+
+static struct clk l4_ck = { /* used both as an ick and fck */
+ .name = "l4_ck",
+ .parent = &core_l3_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
+ .clksel = l4_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk ssi_l4_ick = {
+ .name = "ssi_l4_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_SSI_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * DSS clock domain
+ * CLOCKs:
+ * DSS_L4_ICLK, DSS_L3_ICLK,
+ * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
+ *
+ * DSS is both initiator and target.
+ */
+/* XXX Add RATE_NOT_VALIDATED */
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
+ { .parent = &core_ck, .rates = dss1_fck_core_rates },
+ { .parent = NULL },
+};
+
+static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
+ .name = "dss_ick",
+ .parent = &l4_ck, /* really both l3 and l4 */
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dss1_fck = {
+ .name = "dss1_fck",
+ .parent = &core_ck, /* Core or sys */
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ DELAYED_APP,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
+ .clksel = dss1_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel dss2_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
+ { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+ { .parent = NULL }
+};
+
+static struct clk dss2_fck = { /* Alt clk used in power management */
+ .name = "dss2_fck",
+ .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ DELAYED_APP,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
+ .clksel = dss2_fck_clksel,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dss_54m_fck = { /* Alt clk used in power management */
+ .name = "dss_54m_fck", /* 54m tv clk */
+ .parent = &func_54m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_TV_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * CORE power domain ICLK & FCLK defines.
+ * Many of the these can have more than one possible parent. Entries
+ * here will likely have an L4 interface parent, and may have multiple
+ * functional clock parents.
+ */
+static const struct clksel_rate gpt_alt_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+ { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+ { .parent = &sys_ck, .rates = gpt_sys_rates },
+ { .parent = &alt_ck, .rates = gpt_alt_rates },
+ { .parent = NULL },
+};
+
+static struct clk gpt1_ick = {
+ .name = "gpt1_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt1_fck = {
+ .name = "gpt1_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk gpt2_ick = {
+ .name = "gpt2_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+ .name = "gpt2_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_ick = {
+ .name = "gpt3_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt3_fck = {
+ .name = "gpt3_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_ick = {
+ .name = "gpt4_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt4_fck = {
+ .name = "gpt4_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_ick = {
+ .name = "gpt5_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt5_fck = {
+ .name = "gpt5_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_ick = {
+ .name = "gpt6_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt6_fck = {
+ .name = "gpt6_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_ick = {
+ .name = "gpt7_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt7_fck = {
+ .name = "gpt7_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_ick = {
+ .name = "gpt8_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt8_fck = {
+ .name = "gpt8_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_ick = {
+ .name = "gpt9_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt9_fck = {
+ .name = "gpt9_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt10_ick = {
+ .name = "gpt10_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt10_fck = {
+ .name = "gpt10_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_ick = {
+ .name = "gpt11_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt11_fck = {
+ .name = "gpt11_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt12_ick = {
+ .name = "gpt12_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt12_fck = {
+ .name = "gpt12_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+ .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
+ .clksel = omap24xx_gpt_clksel,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+ .name = "mcbsp1_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+ .name = "mcbsp1_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+ .name = "mcbsp2_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp2_fck = {
+ .name = "mcbsp2_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+ .name = "mcbsp3_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+ .name = "mcbsp3_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+ .name = "mcbsp4_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+ .name = "mcbsp4_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+ .name = "mcbsp5_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp5_fck = {
+ .name = "mcbsp5_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+ .name = "mcspi_ick",
+ .id = 1,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+ .name = "mcspi_fck",
+ .id = 1,
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+ .name = "mcspi_ick",
+ .id = 2,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+ .name = "mcspi_fck",
+ .id = 2,
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+ .name = "mcspi_ick",
+ .id = 3,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+ .name = "mcspi_fck",
+ .id = 3,
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+ .name = "uart1_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_UART1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+ .name = "uart1_fck",
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_UART1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+ .name = "uart2_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_UART2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+ .name = "uart2_fck",
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_UART2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+ .name = "uart3_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_UART3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+ .name = "uart3_fck",
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_UART3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpios_ick = {
+ .name = "gpios_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpios_fck = {
+ .name = "gpios_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mpu_wdt_ick = {
+ .name = "mpu_wdt_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mpu_wdt_fck = {
+ .name = "mpu_wdt_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sync_32k_ick = {
+ .name = "sync_32k_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+static struct clk wdt1_ick = {
+ .name = "wdt1_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+static struct clk omapctrl_ick = {
+ .name = "omapctrl_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
+ .recalc = &followparent_recalc,
+};
+static struct clk icr_ick = {
+ .name = "icr_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2430_EN_ICR_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk cam_ick = {
+ .name = "cam_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_CAM_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk cam_fck = {
+ .name = "cam_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_CAM_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+ .name = "mailboxes_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt4_ick = {
+ .name = "wdt4_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt4_fck = {
+ .name = "wdt4_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+ .name = "wdt3_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_WDT3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+ .name = "wdt3_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_WDT3_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+ .name = "mspro_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+ .name = "mspro_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmc_ick = {
+ .name = "mmc_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_MMC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmc_fck = {
+ .name = "mmc_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_MMC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+ .name = "fac_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_FAC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk fac_fck = {
+ .name = "fac_fck",
+ .parent = &func_12m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_FAC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk eac_ick = {
+ .name = "eac_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_EAC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk eac_fck = {
+ .name = "eac_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_EAC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+ .name = "hdq_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+ .name = "hdq_fck",
+ .parent = &func_12m_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+ .name = "i2c_ick",
+ .id = 2,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_I2C2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+ .name = "i2c_fck",
+ .id = 2,
+ .parent = &func_12m_ck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_I2C2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2chs2_fck = {
+ .name = "i2chs_fck",
+ .id = 2,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+ .name = "i2c_ick",
+ .id = 1,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_I2C1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+ .name = "i2c_fck",
+ .id = 1,
+ .parent = &func_12m_ck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_I2C1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2chs1_fck = {
+ .name = "i2chs_fck",
+ .id = 1,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+ .name = "gpmc_fck",
+ .parent = &core_l3_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sdma_fck = {
+ .name = "sdma_fck",
+ .parent = &core_l3_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sdma_ick = {
+ .name = "sdma_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk vlynq_ick = {
+ .name = "vlynq_ick",
+ .parent = &core_l3_ck,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_242X },
+ { .div = 2, .val = 2, .flags = RATE_IN_242X },
+ { .div = 3, .val = 3, .flags = RATE_IN_242X },
+ { .div = 4, .val = 4, .flags = RATE_IN_242X },
+ { .div = 6, .val = 6, .flags = RATE_IN_242X },
+ { .div = 8, .val = 8, .flags = RATE_IN_242X },
+ { .div = 9, .val = 9, .flags = RATE_IN_242X },
+ { .div = 12, .val = 12, .flags = RATE_IN_242X },
+ { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
+ { .div = 18, .val = 18, .flags = RATE_IN_242X },
+ { .div = 0 }
+};
+
+static const struct clksel vlynq_fck_clksel[] = {
+ { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+ { .parent = &core_ck, .rates = vlynq_fck_core_rates },
+ { .parent = NULL }
+};
+
+static struct clk vlynq_fck = {
+ .name = "vlynq_fck",
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
+ .clksel = vlynq_fck_clksel,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate
+};
+
+static struct clk sdrc_ick = {
+ .name = "sdrc_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP2430_EN_SDRC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk des_ick = {
+ .name = "des_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_DES_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sha_ick = {
+ .name = "sha_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_SHA_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+ .name = "rng_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_RNG_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk aes_ick = {
+ .name = "aes_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_AES_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+ .name = "pka_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_PKA_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usb_fck = {
+ .name = "usb_fck",
+ .parent = &func_48m_ck,
+ .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_USB_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbhs_ick = {
+ .name = "usbhs_ick",
+ .parent = &core_l3_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_USBHS_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs1_ick = {
+ .name = "mmchs_ick",
+ .id = 1,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs1_fck = {
+ .name = "mmchs_fck",
+ .id = 1,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs2_ick = {
+ .name = "mmchs_ick",
+ .id = 2,
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+ .name = "mmchs_fck",
+ .id = 2,
+ .parent = &func_96m_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+ .name = "gpio5_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio5_fck = {
+ .name = "gpio5_fck",
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mdm_intc_ick = {
+ .name = "mdm_intc_ick",
+ .parent = &l4_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchsdb1_fck = {
+ .name = "mmchsdb_fck",
+ .id = 1,
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchsdb2_fck = {
+ .name = "mmchsdb_fck",
+ .id = 2,
+ .parent = &func_32k_ck,
+ .flags = CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * This clock is a composite clock which does entire set changes then
+ * forces a rebalance. It keys on the MPU speed, but it really could
+ * be any key speed part of a set in the rate table.
+ *
+ * to really change a set, you need memory table sets which get changed
+ * in sram, pre-notifiers & post notifiers, changing the top set, without
+ * having low level display recalc's won't work... this is why dpm notifiers
+ * work, isr's off, walk a list of clocks already _off_ and not messing with
+ * the bus.
+ *
+ * This clock should have no parent. It embodies the entire upper level
+ * active set. A parent will mess up some of the init also.
+ */
+static struct clk virt_prcm_set = {
+ .name = "virt_prcm_set",
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+ VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
+ .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
+ .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
+ .set_rate = &omap2_select_table_rate,
+ .round_rate = &omap2_round_to_table_rate,
+};
+
+static struct clk *onchip_24xx_clks[] __initdata = {
+ /* external root sources */
+ &func_32k_ck,
+ &osc_ck,
+ &sys_ck,
+ &alt_ck,
+ /* internal analog sources */
+ &dpll_ck,
+ &apll96_ck,
+ &apll54_ck,
+ /* internal prcm root sources */
+ &func_54m_ck,
+ &core_ck,
+ &func_96m_ck,
+ &func_48m_ck,
+ &func_12m_ck,
+ &wdt1_osc_ck,
+ &sys_clkout_src,
+ &sys_clkout,
+ &sys_clkout2_src,
+ &sys_clkout2,
+ &emul_ck,
+ /* mpu domain clocks */
+ &mpu_ck,
+ /* dsp domain clocks */
+ &dsp_fck,
+ &dsp_irate_ick,
+ &dsp_ick, /* 242x */
+ &iva2_1_ick, /* 243x */
+ &iva1_ifck, /* 242x */
+ &iva1_mpu_int_ifck, /* 242x */
+ /* GFX domain clocks */
+ &gfx_3d_fck,
+ &gfx_2d_fck,
+ &gfx_ick,
+ /* Modem domain clocks */
+ &mdm_ick,
+ &mdm_osc_ck,
+ /* DSS domain clocks */
+ &dss_ick,
+ &dss1_fck,
+ &dss2_fck,
+ &dss_54m_fck,
+ /* L3 domain clocks */
+ &core_l3_ck,
+ &ssi_ssr_sst_fck,
+ &usb_l4_ick,
+ /* L4 domain clocks */
+ &l4_ck, /* used as both core_l4 and wu_l4 */
+ &ssi_l4_ick,
+ /* virtual meta-group clock */
+ &virt_prcm_set,
+ /* general l4 interface ck, multi-parent functional clk */
+ &gpt1_ick,
+ &gpt1_fck,
+ &gpt2_ick,
+ &gpt2_fck,
+ &gpt3_ick,
+ &gpt3_fck,
+ &gpt4_ick,
+ &gpt4_fck,
+ &gpt5_ick,
+ &gpt5_fck,
+ &gpt6_ick,
+ &gpt6_fck,
+ &gpt7_ick,
+ &gpt7_fck,
+ &gpt8_ick,
+ &gpt8_fck,
+ &gpt9_ick,
+ &gpt9_fck,
+ &gpt10_ick,
+ &gpt10_fck,
+ &gpt11_ick,
+ &gpt11_fck,
+ &gpt12_ick,
+ &gpt12_fck,
+ &mcbsp1_ick,
+ &mcbsp1_fck,
+ &mcbsp2_ick,
+ &mcbsp2_fck,
+ &mcbsp3_ick,
+ &mcbsp3_fck,
+ &mcbsp4_ick,
+ &mcbsp4_fck,
+ &mcbsp5_ick,
+ &mcbsp5_fck,
+ &mcspi1_ick,
+ &mcspi1_fck,
+ &mcspi2_ick,
+ &mcspi2_fck,
+ &mcspi3_ick,
+ &mcspi3_fck,
+ &uart1_ick,
+ &uart1_fck,
+ &uart2_ick,
+ &uart2_fck,
+ &uart3_ick,
+ &uart3_fck,
+ &gpios_ick,
+ &gpios_fck,
+ &mpu_wdt_ick,
+ &mpu_wdt_fck,
+ &sync_32k_ick,
+ &wdt1_ick,
+ &omapctrl_ick,
+ &icr_ick,
+ &cam_fck,
+ &cam_ick,
+ &mailboxes_ick,
+ &wdt4_ick,
+ &wdt4_fck,
+ &wdt3_ick,
+ &wdt3_fck,
+ &mspro_ick,
+ &mspro_fck,
+ &mmc_ick,
+ &mmc_fck,
+ &fac_ick,
+ &fac_fck,
+ &eac_ick,
+ &eac_fck,
+ &hdq_ick,
+ &hdq_fck,
+ &i2c1_ick,
+ &i2c1_fck,
+ &i2chs1_fck,
+ &i2c2_ick,
+ &i2c2_fck,
+ &i2chs2_fck,
+ &gpmc_fck,
+ &sdma_fck,
+ &sdma_ick,
+ &vlynq_ick,
+ &vlynq_fck,
+ &sdrc_ick,
+ &des_ick,
+ &sha_ick,
+ &rng_ick,
+ &aes_ick,
+ &pka_ick,
+ &usb_fck,
+ &usbhs_ick,
+ &mmchs1_ick,
+ &mmchs1_fck,
+ &mmchs2_ick,
+ &mmchs2_fck,
+ &gpio5_ick,
+ &gpio5_fck,
+ &mdm_intc_ick,
+ &mmchsdb1_fck,
+ &mmchsdb2_fck,
+};
+
+#endif
+
--- /dev/null
+/*
+ * OMAP3-specific clock framework functions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+#include <asm/div64.h>
+#include <asm/bitops.h>
+
+#include "memory.h"
+#include "clock.h"
+#include "clock34xx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+
+/* CM_CLKEN_PLL*.EN* bit values */
+#define DPLL_LOCKED 0x7
+
+/**
+ * omap3_dpll_recalc - recalculate DPLL rate
+ * @clk: DPLL struct clk
+ *
+ * Recalculate and propagate the DPLL rate.
+ */
+static void omap3_dpll_recalc(struct clk *clk)
+{
+ clk->rate = omap2_get_dpll_rate(clk);
+
+ propagate_rate(clk);
+}
+
+/**
+ * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
+ * @clk: DPLL output struct clk
+ *
+ * Using parent clock DPLL data, look up DPLL state. If locked, set our
+ * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
+ */
+static void omap3_clkoutx2_recalc(struct clk *clk)
+{
+ const struct dpll_data *dd;
+ u32 v;
+ struct clk *pclk;
+
+ /* Walk up the parents of clk, looking for a DPLL */
+ pclk = clk->parent;
+ while (pclk && !pclk->dpll_data)
+ pclk = pclk->parent;
+
+ /* clk does not have a DPLL as a parent? */
+ WARN_ON(!pclk);
+
+ dd = pclk->dpll_data;
+
+ WARN_ON(!dd->control_reg || !dd->enable_mask);
+
+ v = __raw_readl(dd->control_reg) & dd->enable_mask;
+ v >>= __ffs(dd->enable_mask);
+ if (v != DPLL_LOCKED)
+ clk->rate = clk->parent->rate;
+ else
+ clk->rate = clk->parent->rate * 2;
+
+ if (clk->flags & RATE_PROPAGATES)
+ propagate_rate(clk);
+}
+
+/*
+ * As it is structured now, this will prevent an OMAP2/3 multiboot
+ * kernel from compiling. This will need further attention.
+ */
+#if defined(CONFIG_ARCH_OMAP3)
+
+static struct clk_functions omap2_clk_functions = {
+ .clk_enable = omap2_clk_enable,
+ .clk_disable = omap2_clk_disable,
+ .clk_round_rate = omap2_clk_round_rate,
+ .clk_set_rate = omap2_clk_set_rate,
+ .clk_set_parent = omap2_clk_set_parent,
+ .clk_disable_unused = omap2_clk_disable_unused,
+};
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
+{
+ /* REVISIT: Not ready for 343x */
+#if 0
+ u32 rate;
+
+ if (vclk == NULL || sclk == NULL)
+ return;
+
+ rate = clk_get_rate(sclk);
+ clk_set_rate(vclk, rate);
+#endif
+}
+
+/* REVISIT: Move this init stuff out into clock.c */
+
+/*
+ * Switch the MPU rate if specified on cmdline.
+ * We cannot do this early until cmdline is parsed.
+ */
+static int __init omap2_clk_arch_init(void)
+{
+ if (!mpurate)
+ return -EINVAL;
+
+ /* REVISIT: not yet ready for 343x */
+#if 0
+ if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+ printk(KERN_ERR "Could not find matching MPU rate\n");
+#endif
+
+ recalculate_root_clocks();
+
+ printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
+ "%ld.%01ld/%ld/%ld MHz\n",
+ (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+ (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
+
+ return 0;
+}
+arch_initcall(omap2_clk_arch_init);
+
+int __init omap2_clk_init(void)
+{
+ /* struct prcm_config *prcm; */
+ struct clk **clkp;
+ /* u32 clkrate; */
+ u32 cpu_clkflg;
+
+ /* REVISIT: Ultimately this will be used for multiboot */
+#if 0
+ if (cpu_is_omap242x()) {
+ cpu_mask = RATE_IN_242X;
+ cpu_clkflg = CLOCK_IN_OMAP242X;
+ clkp = onchip_24xx_clks;
+ } else if (cpu_is_omap2430()) {
+ cpu_mask = RATE_IN_243X;
+ cpu_clkflg = CLOCK_IN_OMAP243X;
+ clkp = onchip_24xx_clks;
+ }
+#endif
+ if (cpu_is_omap34xx()) {
+ cpu_mask = RATE_IN_343X;
+ cpu_clkflg = CLOCK_IN_OMAP343X;
+ clkp = onchip_34xx_clks;
+
+ /*
+ * Update this if there are further clock changes between ES2
+ * and production parts
+ */
+ if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
+ /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
+ cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
+ } else {
+ cpu_mask |= RATE_IN_3430ES2;
+ cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
+ }
+ }
+
+ clk_init(&omap2_clk_functions);
+
+ for (clkp = onchip_34xx_clks;
+ clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
+ clkp++) {
+ if ((*clkp)->flags & cpu_clkflg)
+ clk_register(*clkp);
+ }
+
+ /* REVISIT: Not yet ready for OMAP3 */
+#if 0
+ /* Check the MPU rate set by bootloader */
+ clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+ if (!(prcm->flags & cpu_mask))
+ continue;
+ if (prcm->xtal_speed != sys_ck.rate)
+ continue;
+ if (prcm->dpll_speed <= clkrate)
+ break;
+ }
+ curr_prcm_set = prcm;
+#endif
+
+ recalculate_root_clocks();
+
+ printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
+ "%ld.%01ld/%ld/%ld MHz\n",
+ (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+ (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
+
+ /*
+ * Only enable those clocks we will need, let the drivers
+ * enable other clocks as necessary
+ */
+ clk_enable_init_clocks();
+
+ /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
+ /* REVISIT: not yet ready for 343x */
+#if 0
+ vclk = clk_get(NULL, "virt_prcm_set");
+ sclk = clk_get(NULL, "sys_ck");
+#endif
+ return 0;
+}
+
+#endif
--- /dev/null
+/*
+ * OMAP3 clock framework
+ *
+ * Virtual clocks are introduced as a convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+
+#include <asm/arch/control.h>
+
+#include "clock.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+
+static void omap3_dpll_recalc(struct clk *clk);
+static void omap3_clkoutx2_recalc(struct clk *clk);
+
+/*
+ * DPLL1 supplies clock to the MPU.
+ * DPLL2 supplies clock to the IVA2.
+ * DPLL3 supplies CORE domain clocks.
+ * DPLL4 supplies peripheral clocks.
+ * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
+ */
+
+/* PRM CLOCKS */
+
+/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
+static struct clk omap_32k_fck = {
+ .name = "omap_32k_fck",
+ .rate = 32768,
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &propagate_rate,
+};
+
+static struct clk secure_32k_fck = {
+ .name = "secure_32k_fck",
+ .rate = 32768,
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &propagate_rate,
+};
+
+/* Virtual source clocks for osc_sys_ck */
+static struct clk virt_12m_ck = {
+ .name = "virt_12m_ck",
+ .rate = 12000000,
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &propagate_rate,
+};
+
+static struct clk virt_13m_ck = {
+ .name = "virt_13m_ck",
+ .rate = 13000000,
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &propagate_rate,
+};
+
+static struct clk virt_16_8m_ck = {
+ .name = "virt_16_8m_ck",
+ .rate = 16800000,
+ .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &propagate_rate,
+};
+
+static struct clk virt_19_2m_ck = {
+ .name = "virt_19_2m_ck",
+ .rate = 19200000,
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &propagate_rate,
+};
+
+static struct clk virt_26m_ck = {
+ .name = "virt_26m_ck",
+ .rate = 26000000,
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &propagate_rate,
+};
+
+static struct clk virt_38_4m_ck = {
+ .name = "virt_38_4m_ck",
+ .rate = 38400000,
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &propagate_rate,
+};
+
+static const struct clksel_rate osc_sys_12m_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_13m_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_16_8m_rates[] = {
+ { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_19_2m_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_26m_rates[] = {
+ { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_38_4m_rates[] = {
+ { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel osc_sys_clksel[] = {
+ { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
+ { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
+ { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
+ { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
+ { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
+ { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
+ { .parent = NULL },
+};
+
+/* Oscillator clock */
+/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
+static struct clk osc_sys_ck = {
+ .name = "osc_sys_ck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP3430_PRM_CLKSEL,
+ .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
+ .clksel = osc_sys_clksel,
+ /* REVISIT: deal with autoextclkmode? */
+ .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate div2_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_343X },
+ { .div = 0 }
+};
+
+static const struct clksel sys_clksel[] = {
+ { .parent = &osc_sys_ck, .rates = div2_rates },
+ { .parent = NULL }
+};
+
+/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
+/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
+static struct clk sys_ck = {
+ .name = "sys_ck",
+ .parent = &osc_sys_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
+ .clksel_mask = OMAP_SYSCLKDIV_MASK,
+ .clksel = sys_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk sys_altclk = {
+ .name = "sys_altclk",
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &propagate_rate,
+};
+
+/* Optional external clock input for some McBSPs */
+static struct clk mcbsp_clks = {
+ .name = "mcbsp_clks",
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &propagate_rate,
+};
+
+/* PRM EXTERNAL CLOCK OUTPUT */
+
+static struct clk sys_clkout1 = {
+ .name = "sys_clkout1",
+ .parent = &osc_sys_ck,
+ .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
+ .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+/* DPLLS */
+
+/* CM CLOCKS */
+
+static const struct clksel_rate dpll_bypass_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate dpll_locked_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate div16_dpll_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_343X },
+ { .div = 3, .val = 3, .flags = RATE_IN_343X },
+ { .div = 4, .val = 4, .flags = RATE_IN_343X },
+ { .div = 5, .val = 5, .flags = RATE_IN_343X },
+ { .div = 6, .val = 6, .flags = RATE_IN_343X },
+ { .div = 7, .val = 7, .flags = RATE_IN_343X },
+ { .div = 8, .val = 8, .flags = RATE_IN_343X },
+ { .div = 9, .val = 9, .flags = RATE_IN_343X },
+ { .div = 10, .val = 10, .flags = RATE_IN_343X },
+ { .div = 11, .val = 11, .flags = RATE_IN_343X },
+ { .div = 12, .val = 12, .flags = RATE_IN_343X },
+ { .div = 13, .val = 13, .flags = RATE_IN_343X },
+ { .div = 14, .val = 14, .flags = RATE_IN_343X },
+ { .div = 15, .val = 15, .flags = RATE_IN_343X },
+ { .div = 16, .val = 16, .flags = RATE_IN_343X },
+ { .div = 0 }
+};
+
+/* DPLL1 */
+/* MPU clock source */
+/* Type: DPLL */
+static const struct dpll_data dpll1_dd = {
+ .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
+ .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
+ .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+ .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
+ .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
+ .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
+ .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll1_ck = {
+ .name = "dpll1_ck",
+ .parent = &sys_ck,
+ .dpll_data = &dpll1_dd,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed.
+ */
+static struct clk dpll1_x2_ck = {
+ .name = "dpll1_x2_ck",
+ .parent = &dpll1_ck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
+static const struct clksel div16_dpll1_x2m2_clksel[] = {
+ { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
+ { .parent = NULL }
+};
+
+/*
+ * Does not exist in the TRM - needed to separate the M2 divider from
+ * bypass selection in mpu_ck
+ */
+static struct clk dpll1_x2m2_ck = {
+ .name = "dpll1_x2m2_ck",
+ .parent = &dpll1_x2_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+ .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
+ .clksel = div16_dpll1_x2m2_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* DPLL2 */
+/* IVA2 clock source */
+/* Type: DPLL */
+
+static const struct dpll_data dpll2_dd = {
+ .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
+ .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
+ .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+ .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
+ .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
+ .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
+ .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll2_ck = {
+ .name = "dpll2_ck",
+ .parent = &sys_ck,
+ .dpll_data = &dpll2_dd,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll2_m2x2_clksel[] = {
+ { .parent = &dpll2_ck, .rates = div16_dpll_rates },
+ { .parent = NULL }
+};
+
+/*
+ * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
+ * or CLKOUTX2. CLKOUT seems most plausible.
+ */
+static struct clk dpll2_m2_ck = {
+ .name = "dpll2_m2_ck",
+ .parent = &dpll2_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+ OMAP3430_CM_CLKSEL2_PLL),
+ .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
+ .clksel = div16_dpll2_m2x2_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* DPLL3 */
+/* Source clock for all interfaces and for some device fclks */
+/* Type: DPLL */
+static const struct dpll_data dpll3_dd = {
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
+ .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
+ .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
+ .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
+ .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll3_ck = {
+ .name = "dpll3_ck",
+ .parent = &sys_ck,
+ .dpll_data = &dpll3_dd,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed
+ */
+static struct clk dpll3_x2_ck = {
+ .name = "dpll3_x2_ck",
+ .parent = &dpll3_ck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate div31_dpll3_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_343X },
+ { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
+ { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
+ { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
+ { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
+ { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
+ { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
+ { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
+ { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
+ { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
+ { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
+ { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
+ { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
+ { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
+ { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
+ { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
+ { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
+ { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
+ { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
+ { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
+ { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
+ { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
+ { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
+ { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
+ { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
+ { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
+ { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
+ { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
+ { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
+ { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
+ { .div = 0 },
+};
+
+static const struct clksel div31_dpll3m2_clksel[] = {
+ { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
+ { .parent = NULL }
+};
+
+/*
+ * DPLL3 output M2
+ * REVISIT: This DPLL output divider must be changed in SRAM, so until
+ * that code is ready, this should remain a 'read-only' clksel clock.
+ */
+static struct clk dpll3_m2_ck = {
+ .name = "dpll3_m2_ck",
+ .parent = &dpll3_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
+ .clksel = div31_dpll3m2_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel core_ck_clksel[] = {
+ { .parent = &sys_ck, .rates = dpll_bypass_rates },
+ { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk core_ck = {
+ .name = "core_ck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .clksel_mask = OMAP3430_ST_CORE_CLK,
+ .clksel = core_ck_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel dpll3_m2x2_ck_clksel[] = {
+ { .parent = &sys_ck, .rates = dpll_bypass_rates },
+ { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk dpll3_m2x2_ck = {
+ .name = "dpll3_m2x2_ck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .clksel_mask = OMAP3430_ST_CORE_CLK,
+ .clksel = dpll3_m2x2_ck_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static const struct clksel div16_dpll3_clksel[] = {
+ { .parent = &dpll3_ck, .rates = div16_dpll_rates },
+ { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll3_m3x2_ck */
+static struct clk dpll3_m3_ck = {
+ .name = "dpll3_m3_ck",
+ .parent = &dpll3_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
+ .clksel = div16_dpll3_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll3_m3x2_ck = {
+ .name = "dpll3_m3x2_ck",
+ .parent = &dpll3_m3_ck,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel emu_core_alwon_ck_clksel[] = {
+ { .parent = &sys_ck, .rates = dpll_bypass_rates },
+ { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk emu_core_alwon_ck = {
+ .name = "emu_core_alwon_ck",
+ .parent = &dpll3_m3x2_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .clksel_mask = OMAP3430_ST_CORE_CLK,
+ .clksel = emu_core_alwon_ck_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* DPLL4 */
+/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
+/* Type: DPLL */
+static const struct dpll_data dpll4_dd = {
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+ .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
+ .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
+ .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+ .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+ .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll4_ck = {
+ .name = "dpll4_ck",
+ .parent = &sys_ck,
+ .dpll_data = &dpll4_dd,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed --
+ * XXX does this serve any downstream clocks?
+ */
+static struct clk dpll4_x2_ck = {
+ .name = "dpll4_x2_ck",
+ .parent = &dpll4_ck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel div16_dpll4_clksel[] = {
+ { .parent = &dpll4_ck, .rates = div16_dpll_rates },
+ { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll4_m2x2_ck */
+static struct clk dpll4_m2_ck = {
+ .name = "dpll4_m2_ck",
+ .parent = &dpll4_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+ .clksel_mask = OMAP3430_DIV_96M_MASK,
+ .clksel = div16_dpll4_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m2x2_ck = {
+ .name = "dpll4_m2x2_ck",
+ .parent = &dpll4_m2_ck,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel omap_96m_alwon_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dpll_bypass_rates },
+ { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk omap_96m_alwon_fck = {
+ .name = "omap_96m_alwon_fck",
+ .parent = &dpll4_m2x2_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .clksel_mask = OMAP3430_ST_PERIPH_CLK,
+ .clksel = omap_96m_alwon_fck_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk omap_96m_fck = {
+ .name = "omap_96m_fck",
+ .parent = &omap_96m_alwon_fck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static const struct clksel cm_96m_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dpll_bypass_rates },
+ { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk cm_96m_fck = {
+ .name = "cm_96m_fck",
+ .parent = &dpll4_m2x2_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .clksel_mask = OMAP3430_ST_PERIPH_CLK,
+ .clksel = cm_96m_fck_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m3x2_ck */
+static struct clk dpll4_m3_ck = {
+ .name = "dpll4_m3_ck",
+ .parent = &dpll4_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
+ .clksel = div16_dpll4_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m3x2_ck = {
+ .name = "dpll4_m3x2_ck",
+ .parent = &dpll4_m3_ck,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel virt_omap_54m_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dpll_bypass_rates },
+ { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk virt_omap_54m_fck = {
+ .name = "virt_omap_54m_fck",
+ .parent = &dpll4_m3x2_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .clksel_mask = OMAP3430_ST_PERIPH_CLK,
+ .clksel = virt_omap_54m_fck_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate omap_54m_alt_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel omap_54m_clksel[] = {
+ { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
+ { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
+ { .parent = NULL }
+};
+
+static struct clk omap_54m_fck = {
+ .name = "omap_54m_fck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_SOURCE_54M,
+ .clksel = omap_54m_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate omap_48m_96md2_rates[] = {
+ { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate omap_48m_alt_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel omap_48m_clksel[] = {
+ { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
+ { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
+ { .parent = NULL }
+};
+
+static struct clk omap_48m_fck = {
+ .name = "omap_48m_fck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_SOURCE_48M,
+ .clksel = omap_48m_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk omap_12m_fck = {
+ .name = "omap_12m_fck",
+ .parent = &omap_48m_fck,
+ .fixed_div = 4,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_fixed_divisor_recalc,
+};
+
+/* This virstual clock is the source for dpll4_m4x2_ck */
+static struct clk dpll4_m4_ck = {
+ .name = "dpll4_m4_ck",
+ .parent = &dpll4_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
+ .clksel = div16_dpll4_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m4x2_ck = {
+ .name = "dpll4_m4x2_ck",
+ .parent = &dpll4_m4_ck,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m5x2_ck */
+static struct clk dpll4_m5_ck = {
+ .name = "dpll4_m5_ck",
+ .parent = &dpll4_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
+ .clksel = div16_dpll4_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m5x2_ck = {
+ .name = "dpll4_m5x2_ck",
+ .parent = &dpll4_m5_ck,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m6x2_ck */
+static struct clk dpll4_m6_ck = {
+ .name = "dpll4_m6_ck",
+ .parent = &dpll4_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
+ .clksel = div16_dpll4_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m6x2_ck = {
+ .name = "dpll4_m6x2_ck",
+ .parent = &dpll4_m6_ck,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
+static struct clk emu_per_alwon_ck = {
+ .name = "emu_per_alwon_ck",
+ .parent = &dpll4_m6x2_ck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+/* DPLL5 */
+/* Supplies 120MHz clock, USIM source clock */
+/* Type: DPLL */
+/* 3430ES2 only */
+static const struct dpll_data dpll5_dd = {
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+ .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
+ .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+ .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+ .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
+ .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
+ .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll5_ck = {
+ .name = "dpll5_ck",
+ .parent = &sys_ck,
+ .dpll_data = &dpll5_dd,
+ .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
+ ALWAYS_ENABLED,
+ .recalc = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll5_clksel[] = {
+ { .parent = &dpll5_ck, .rates = div16_dpll_rates },
+ { .parent = NULL }
+};
+
+static struct clk dpll5_m2_ck = {
+ .name = "dpll5_m2_ck",
+ .parent = &dpll5_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+ .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
+ .clksel = div16_dpll5_clksel,
+ .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel omap_120m_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dpll_bypass_rates },
+ { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk omap_120m_fck = {
+ .name = "omap_120m_fck",
+ .parent = &dpll5_m2_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+ .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
+ .clksel = omap_120m_fck_clksel,
+ .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* CM EXTERNAL CLOCK OUTPUTS */
+
+static const struct clksel_rate clkout2_src_core_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_sys_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_96m_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_54m_rates[] = {
+ { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel clkout2_src_clksel[] = {
+ { .parent = &core_ck, .rates = clkout2_src_core_rates },
+ { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
+ { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates },
+ { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
+ { .parent = NULL }
+};
+
+static struct clk clkout2_src_ck = {
+ .name = "clkout2_src_ck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
+ .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
+ .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
+ .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
+ .clksel = clkout2_src_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate sys_clkout2_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 1, .flags = RATE_IN_343X },
+ { .div = 4, .val = 2, .flags = RATE_IN_343X },
+ { .div = 8, .val = 3, .flags = RATE_IN_343X },
+ { .div = 16, .val = 4, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+ { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
+ { .parent = NULL },
+};
+
+static struct clk sys_clkout2 = {
+ .name = "sys_clkout2",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
+ .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
+ .clksel = sys_clkout2_clksel,
+ .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* CM OUTPUT CLOCKS */
+
+static struct clk corex2_fck = {
+ .name = "corex2_fck",
+ .parent = &dpll3_m2x2_ck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+/* DPLL power domain clock controls */
+
+static const struct clksel div2_core_clksel[] = {
+ { .parent = &core_ck, .rates = div2_rates },
+ { .parent = NULL }
+};
+
+/*
+ * REVISIT: Are these in DPLL power domain or CM power domain? docs
+ * may be inconsistent here?
+ */
+static struct clk dpll1_fck = {
+ .name = "dpll1_fck",
+ .parent = &core_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
+ .clksel = div2_core_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/*
+ * MPU clksel:
+ * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
+ * derives from the high-frequency bypass clock originating from DPLL3,
+ * called 'dpll1_fck'
+ */
+static const struct clksel mpu_clksel[] = {
+ { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
+ { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk mpu_ck = {
+ .name = "mpu_ck",
+ .parent = &dpll1_x2m2_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+ .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
+ .clksel = mpu_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
+static const struct clksel_rate arm_fck_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 1, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel arm_fck_clksel[] = {
+ { .parent = &mpu_ck, .rates = arm_fck_rates },
+ { .parent = NULL }
+};
+
+static struct clk arm_fck = {
+ .name = "arm_fck",
+ .parent = &mpu_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+ .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
+ .clksel = arm_fck_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/*
+ * REVISIT: This clock is never specifically defined in the 3430 TRM,
+ * although it is referenced - so this is a guess
+ */
+static struct clk emu_mpu_alwon_ck = {
+ .name = "emu_mpu_alwon_ck",
+ .parent = &mpu_ck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dpll2_fck = {
+ .name = "dpll2_fck",
+ .parent = &core_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
+ .clksel = div2_core_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/*
+ * IVA2 clksel:
+ * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
+ * derives from the high-frequency bypass clock originating from DPLL3,
+ * called 'dpll2_fck'
+ */
+
+static const struct clksel iva2_clksel[] = {
+ { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
+ { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk iva2_ck = {
+ .name = "iva2_ck",
+ .parent = &dpll2_m2_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+ OMAP3430_CM_IDLEST_PLL),
+ .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
+ .clksel = iva2_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* Common interface clocks */
+
+static struct clk l3_ick = {
+ .name = "l3_ick",
+ .parent = &core_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
+ .clksel = div2_core_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel div2_l3_clksel[] = {
+ { .parent = &l3_ick, .rates = div2_rates },
+ { .parent = NULL }
+};
+
+static struct clk l4_ick = {
+ .name = "l4_ick",
+ .parent = &l3_ick,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
+ .clksel = div2_l3_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+
+};
+
+static const struct clksel div2_l4_clksel[] = {
+ { .parent = &l4_ick, .rates = div2_rates },
+ { .parent = NULL }
+};
+
+static struct clk rm_ick = {
+ .name = "rm_ick",
+ .parent = &l4_ick,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
+ .clksel = div2_l4_clksel,
+ .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* GFX power domain */
+
+/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
+
+static const struct clksel gfx_l3_clksel[] = {
+ { .parent = &l3_ick, .rates = gfx_l3_rates },
+ { .parent = NULL }
+};
+
+static struct clk gfx_l3_fck = {
+ .name = "gfx_l3_fck",
+ .parent = &l3_ick,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+ .enable_bit = OMAP_EN_GFX_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP_CLKSEL_GFX_MASK,
+ .clksel = gfx_l3_clksel,
+ .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gfx_l3_ick = {
+ .name = "gfx_l3_ick",
+ .parent = &l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+ .enable_bit = OMAP_EN_GFX_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gfx_cg1_ck = {
+ .name = "gfx_cg1_ck",
+ .parent = &gfx_l3_fck, /* REVISIT: correct? */
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gfx_cg2_ck = {
+ .name = "gfx_cg2_ck",
+ .parent = &gfx_l3_fck, /* REVISIT: correct? */
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .recalc = &followparent_recalc,
+};
+
+/* SGX power domain - 3430ES2 only */
+
+static const struct clksel_rate sgx_core_rates[] = {
+ { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 4, .val = 1, .flags = RATE_IN_343X },
+ { .div = 6, .val = 2, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel_rate sgx_96m_rates[] = {
+ { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel sgx_clksel[] = {
+ { .parent = &core_ck, .rates = sgx_core_rates },
+ { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
+ { .parent = NULL },
+};
+
+static struct clk sgx_fck = {
+ .name = "sgx_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
+ .clksel = sgx_clksel,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk sgx_ick = {
+ .name = "sgx_ick",
+ .parent = &l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+/* CORE power domain */
+
+static struct clk d2d_26m_fck = {
+ .name = "d2d_26m_fck",
+ .parent = &sys_ck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .recalc = &followparent_recalc,
+};
+
+static const struct clksel omap343x_gpt_clksel[] = {
+ { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
+ { .parent = &sys_ck, .rates = gpt_sys_rates },
+ { .parent = NULL}
+};
+
+static struct clk gpt10_fck = {
+ .name = "gpt10_fck",
+ .parent = &sys_ck,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_GPT10_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_fck = {
+ .name = "gpt11_fck",
+ .parent = &sys_ck,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_GPT11_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk cpefuse_fck = {
+ .name = "cpefuse_fck",
+ .parent = &sys_ck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+ .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk ts_fck = {
+ .name = "ts_fck",
+ .parent = &omap_32k_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+ .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbtll_fck = {
+ .name = "usbtll_fck",
+ .parent = &omap_120m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+ .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+/* CORE 96M FCLK-derived clocks */
+
+static struct clk core_96m_fck = {
+ .name = "core_96m_fck",
+ .parent = &omap_96m_fck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs3_fck = {
+ .name = "mmchs_fck",
+ .id = 3,
+ .parent = &core_96m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+ .name = "mmchs_fck",
+ .id = 2,
+ .parent = &core_96m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MMC2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+ .name = "mspro_fck",
+ .parent = &core_96m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs1_fck = {
+ .name = "mmchs_fck",
+ .id = 1,
+ .parent = &core_96m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MMC1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c3_fck = {
+ .name = "i2c_fck",
+ .id = 3,
+ .parent = &core_96m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_I2C3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+ .name = "i2c_fck",
+ .id = 2,
+ .parent = &core_96m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_I2C2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+ .name = "i2c_fck",
+ .id = 1,
+ .parent = &core_96m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_I2C1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+/*
+ * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
+ * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
+ */
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 }
+};
+
+static const struct clksel mcbsp_15_clksel[] = {
+ { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+ { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+ { .parent = NULL }
+};
+
+static struct clk mcbsp5_fck = {
+ .name = "mcbsp5_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+ .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
+ .clksel = mcbsp_15_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+ .name = "mcbsp1_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+ .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
+ .clksel = mcbsp_15_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* CORE_48M_FCK-derived clocks */
+
+static struct clk core_48m_fck = {
+ .name = "core_48m_fck",
+ .parent = &omap_48m_fck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi4_fck = {
+ .name = "mcspi_fck",
+ .id = 4,
+ .parent = &core_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+ .name = "mcspi_fck",
+ .id = 3,
+ .parent = &core_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+ .name = "mcspi_fck",
+ .id = 2,
+ .parent = &core_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+ .name = "mcspi_fck",
+ .id = 1,
+ .parent = &core_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+ .name = "uart2_fck",
+ .parent = &core_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_UART2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+ .name = "uart1_fck",
+ .parent = &core_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_UART1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk fshostusb_fck = {
+ .name = "fshostusb_fck",
+ .parent = &core_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .recalc = &followparent_recalc,
+};
+
+/* CORE_12M_FCK based clocks */
+
+static struct clk core_12m_fck = {
+ .name = "core_12m_fck",
+ .parent = &omap_12m_fck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+ .name = "hdq_fck",
+ .parent = &core_12m_fck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_HDQ_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+/* DPLL3-derived clock */
+
+static const struct clksel_rate ssi_ssr_corex2_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_343X },
+ { .div = 3, .val = 3, .flags = RATE_IN_343X },
+ { .div = 4, .val = 4, .flags = RATE_IN_343X },
+ { .div = 6, .val = 6, .flags = RATE_IN_343X },
+ { .div = 8, .val = 8, .flags = RATE_IN_343X },
+ { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_clksel[] = {
+ { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
+ { .parent = NULL }
+};
+
+static struct clk ssi_ssr_fck = {
+ .name = "ssi_ssr_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_SSI_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
+ .clksel = ssi_ssr_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_sst_fck = {
+ .name = "ssi_sst_fck",
+ .parent = &ssi_ssr_fck,
+ .fixed_div = 2,
+ .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+ .recalc = &omap2_fixed_divisor_recalc,
+};
+
+
+
+/* CORE_L3_ICK based clocks */
+
+static struct clk core_l3_ick = {
+ .name = "core_l3_ick",
+ .parent = &l3_ick,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick = {
+ .name = "hsotgusb_ick",
+ .parent = &core_l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sdrc_ick = {
+ .name = "sdrc_ick",
+ .parent = &core_l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_SDRC_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+ .name = "gpmc_fck",
+ .parent = &core_l3_ick,
+ .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
+ ENABLE_ON_INIT,
+ .recalc = &followparent_recalc,
+};
+
+/* SECURITY_L3_ICK based clocks */
+
+static struct clk security_l3_ick = {
+ .name = "security_l3_ick",
+ .parent = &l3_ick,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+ .name = "pka_ick",
+ .parent = &security_l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP3430_EN_PKA_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+/* CORE_L4_ICK based clocks */
+
+static struct clk core_l4_ick = {
+ .name = "core_l4_ick",
+ .parent = &l4_ick,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbtll_ick = {
+ .name = "usbtll_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs3_ick = {
+ .name = "mmchs_ick",
+ .id = 3,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+/* Intersystem Communication Registers - chassis mode only */
+static struct clk icr_ick = {
+ .name = "icr_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_ICR_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk aes2_ick = {
+ .name = "aes2_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_AES2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sha12_ick = {
+ .name = "sha12_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_SHA12_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk des2_ick = {
+ .name = "des2_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_DES2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs2_ick = {
+ .name = "mmchs_ick",
+ .id = 2,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MMC2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mmchs1_ick = {
+ .name = "mmchs_ick",
+ .id = 1,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MMC1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+ .name = "mspro_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+ .name = "hdq_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_HDQ_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi4_ick = {
+ .name = "mcspi_ick",
+ .id = 4,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+ .name = "mcspi_ick",
+ .id = 3,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+ .name = "mcspi_ick",
+ .id = 2,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+ .name = "mcspi_ick",
+ .id = 1,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c3_ick = {
+ .name = "i2c_ick",
+ .id = 3,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_I2C3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+ .name = "i2c_ick",
+ .id = 2,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_I2C2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+ .name = "i2c_ick",
+ .id = 1,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_I2C1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+ .name = "uart2_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_UART2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+ .name = "uart1_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_UART1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt11_ick = {
+ .name = "gpt11_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_GPT11_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt10_ick = {
+ .name = "gpt10_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_GPT10_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+ .name = "mcbsp5_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+ .name = "mcbsp1_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+ .name = "fac_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+ .name = "mailboxes_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk omapctrl_ick = {
+ .name = "omapctrl_ick",
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+ .recalc = &followparent_recalc,
+};
+
+/* SSI_L4_ICK based clocks */
+
+static struct clk ssi_l4_ick = {
+ .name = "ssi_l4_ick",
+ .parent = &l4_ick,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk ssi_ick = {
+ .name = "ssi_ick",
+ .parent = &ssi_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_SSI_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
+ * but l4_ick makes more sense to me */
+
+static const struct clksel usb_l4_clksel[] = {
+ { .parent = &l4_ick, .rates = div2_rates },
+ { .parent = NULL },
+};
+
+static struct clk usb_l4_ick = {
+ .name = "usb_l4_ick",
+ .parent = &l4_ick,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
+ .clksel = usb_l4_clksel,
+ .flags = CLOCK_IN_OMAP3430ES1,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
+
+/* SECURITY_L4_ICK2 based clocks */
+
+static struct clk security_l4_ick2 = {
+ .name = "security_l4_ick2",
+ .parent = &l4_ick,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk aes1_ick = {
+ .name = "aes1_ick",
+ .parent = &security_l4_ick2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP3430_EN_AES1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+ .name = "rng_ick",
+ .parent = &security_l4_ick2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP3430_EN_RNG_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sha11_ick = {
+ .name = "sha11_ick",
+ .parent = &security_l4_ick2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP3430_EN_SHA11_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk des1_ick = {
+ .name = "des1_ick",
+ .parent = &security_l4_ick2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP3430_EN_DES1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+/* DSS */
+static const struct clksel dss1_alwon_fck_clksel[] = {
+ { .parent = &sys_ck, .rates = dpll_bypass_rates },
+ { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk dss1_alwon_fck = {
+ .name = "dss1_alwon_fck",
+ .parent = &dpll4_m4x2_ck,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_DSS1_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .clksel_mask = OMAP3430_ST_PERIPH_CLK,
+ .clksel = dss1_alwon_fck_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk dss_tv_fck = {
+ .name = "dss_tv_fck",
+ .parent = &omap_54m_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_TV_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dss_96m_fck = {
+ .name = "dss_96m_fck",
+ .parent = &omap_96m_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_TV_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dss2_alwon_fck = {
+ .name = "dss2_alwon_fck",
+ .parent = &sys_ck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_DSS2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk dss_ick = {
+ /* Handles both L3 and L4 clocks */
+ .name = "dss_ick",
+ .parent = &l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+/* CAM */
+
+static const struct clksel cam_mclk_clksel[] = {
+ { .parent = &sys_ck, .rates = dpll_bypass_rates },
+ { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
+ { .parent = NULL }
+};
+
+static struct clk cam_mclk = {
+ .name = "cam_mclk",
+ .parent = &dpll4_m5x2_ck,
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+ .clksel_mask = OMAP3430_ST_PERIPH_CLK,
+ .clksel = cam_mclk_clksel,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_CAM_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk cam_l3_ick = {
+ .name = "cam_l3_ick",
+ .parent = &l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_CAM_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk cam_l4_ick = {
+ .name = "cam_l4_ick",
+ .parent = &l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_CAM_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+/* USBHOST - 3430ES2 only */
+
+static struct clk usbhost_120m_fck = {
+ .name = "usbhost_120m_fck",
+ .parent = &omap_120m_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbhost_48m_fck = {
+ .name = "usbhost_48m_fck",
+ .parent = &omap_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbhost_l3_ick = {
+ .name = "usbhost_l3_ick",
+ .parent = &l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbhost_l4_ick = {
+ .name = "usbhost_l4_ick",
+ .parent = &l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk usbhost_sar_fck = {
+ .name = "usbhost_sar_fck",
+ .parent = &osc_sys_ck,
+ .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
+ .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+/* WKUP */
+
+static const struct clksel_rate usim_96m_rates[] = {
+ { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 4, .val = 4, .flags = RATE_IN_343X },
+ { .div = 8, .val = 5, .flags = RATE_IN_343X },
+ { .div = 10, .val = 6, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel_rate usim_120m_rates[] = {
+ { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 8, .val = 8, .flags = RATE_IN_343X },
+ { .div = 16, .val = 9, .flags = RATE_IN_343X },
+ { .div = 20, .val = 10, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel usim_clksel[] = {
+ { .parent = &omap_96m_fck, .rates = usim_96m_rates },
+ { .parent = &omap_120m_fck, .rates = usim_120m_rates },
+ { .parent = &sys_ck, .rates = div2_rates },
+ { .parent = NULL },
+};
+
+/* 3430ES2 only */
+static struct clk usim_fck = {
+ .name = "usim_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
+ .clksel = usim_clksel,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt1_fck = {
+ .name = "gpt1_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT1_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk wkup_32k_fck = {
+ .name = "wkup_32k_fck",
+ .parent = &omap_32k_fck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio1_fck = {
+ .name = "gpio1_fck",
+ .parent = &wkup_32k_fck,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt2_fck = {
+ .name = "wdt2_fck",
+ .parent = &wkup_32k_fck,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_WDT2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wkup_l4_ick = {
+ .name = "wkup_l4_ick",
+ .parent = &sys_ck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &followparent_recalc,
+};
+
+/* 3430ES2 only */
+/* Never specifically named in the TRM, so we have to infer a likely name */
+static struct clk usim_ick = {
+ .name = "usim_ick",
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES2,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt2_ick = {
+ .name = "wdt2_ick",
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_WDT2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt1_ick = {
+ .name = "wdt1_ick",
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_WDT1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio1_ick = {
+ .name = "gpio1_ick",
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk omap_32ksync_ick = {
+ .name = "omap_32ksync_ick",
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt12_ick = {
+ .name = "gpt12_ick",
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT12_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt1_ick = {
+ .name = "gpt1_ick",
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+
+
+/* PER clock domain */
+
+static struct clk per_96m_fck = {
+ .name = "per_96m_fck",
+ .parent = &omap_96m_alwon_fck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk per_48m_fck = {
+ .name = "per_48m_fck",
+ .parent = &omap_48m_fck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+ .name = "uart3_fck",
+ .parent = &per_48m_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_UART3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+ .name = "gpt2_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT2_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_fck = {
+ .name = "gpt3_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT3_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_fck = {
+ .name = "gpt4_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT4_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_fck = {
+ .name = "gpt5_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT5_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_fck = {
+ .name = "gpt6_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT6_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_fck = {
+ .name = "gpt7_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT7_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_fck = {
+ .name = "gpt8_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT8_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_fck = {
+ .name = "gpt9_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT9_SHIFT,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+ .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
+ .clksel = omap343x_gpt_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk per_32k_alwon_fck = {
+ .name = "per_32k_alwon_fck",
+ .parent = &omap_32k_fck,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio6_fck = {
+ .name = "gpio6_fck",
+ .parent = &per_32k_alwon_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT6_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio5_fck = {
+ .name = "gpio5_fck",
+ .parent = &per_32k_alwon_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT5_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio4_fck = {
+ .name = "gpio4_fck",
+ .parent = &per_32k_alwon_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio3_fck = {
+ .name = "gpio3_fck",
+ .parent = &per_32k_alwon_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio2_fck = {
+ .name = "gpio2_fck",
+ .parent = &per_32k_alwon_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_GPT2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+ .name = "wdt3_fck",
+ .parent = &per_32k_alwon_fck,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_WDT3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk per_l4_ick = {
+ .name = "per_l4_ick",
+ .parent = &l4_ick,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ PARENT_CONTROLS_CLOCK,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio6_ick = {
+ .name = "gpio6_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+ .name = "gpio5_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio4_ick = {
+ .name = "gpio4_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio3_ick = {
+ .name = "gpio3_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpio2_ick = {
+ .name = "gpio2_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+ .name = "wdt3_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_WDT3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+ .name = "uart3_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_UART3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt9_ick = {
+ .name = "gpt9_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT9_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt8_ick = {
+ .name = "gpt8_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT8_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt7_ick = {
+ .name = "gpt7_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT7_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt6_ick = {
+ .name = "gpt6_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT6_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt5_ick = {
+ .name = "gpt5_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT5_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt4_ick = {
+ .name = "gpt4_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt3_ick = {
+ .name = "gpt3_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk gpt2_ick = {
+ .name = "gpt2_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+ .name = "mcbsp2_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+ .name = "mcbsp3_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+ .name = "mcbsp4_ick",
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+static const struct clksel mcbsp_234_clksel[] = {
+ { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
+ { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
+ { .parent = NULL }
+};
+
+static struct clk mcbsp2_fck = {
+ .name = "mcbsp2_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+ .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
+ .clksel = mcbsp_234_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+ .name = "mcbsp3_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+ .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
+ .clksel = mcbsp_234_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+ .name = "mcbsp4_fck",
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+ .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
+ .clksel = mcbsp_234_clksel,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* EMU clocks */
+
+/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
+
+static const struct clksel_rate emu_src_sys_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_core_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_per_rates[] = {
+ { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_mpu_rates[] = {
+ { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 0 },
+};
+
+static const struct clksel emu_src_clksel[] = {
+ { .parent = &sys_ck, .rates = emu_src_sys_rates },
+ { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
+ { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
+ { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
+ { .parent = NULL },
+};
+
+/*
+ * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
+ * to switch the source of some of the EMU clocks.
+ * XXX Are there CLKEN bits for these EMU clks?
+ */
+static struct clk emu_src_ck = {
+ .name = "emu_src_ck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_MUX_CTRL_MASK,
+ .clksel = emu_src_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclk_emu_rates[] = {
+ { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 3, .val = 3, .flags = RATE_IN_343X },
+ { .div = 4, .val = 4, .flags = RATE_IN_343X },
+ { .div = 6, .val = 6, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel pclk_emu_clksel[] = {
+ { .parent = &emu_src_ck, .rates = pclk_emu_rates },
+ { .parent = NULL },
+};
+
+static struct clk pclk_fck = {
+ .name = "pclk_fck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
+ .clksel = pclk_emu_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclkx2_emu_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_343X },
+ { .div = 3, .val = 3, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel pclkx2_emu_clksel[] = {
+ { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
+ { .parent = NULL },
+};
+
+static struct clk pclkx2_fck = {
+ .name = "pclkx2_fck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
+ .clksel = pclkx2_emu_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel atclk_emu_clksel[] = {
+ { .parent = &emu_src_ck, .rates = div2_rates },
+ { .parent = NULL },
+};
+
+static struct clk atclk_fck = {
+ .name = "atclk_fck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
+ .clksel = atclk_emu_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static struct clk traceclk_src_fck = {
+ .name = "traceclk_src_fck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
+ .clksel = emu_src_clksel,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .recalc = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate traceclk_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_343X },
+ { .div = 4, .val = 4, .flags = RATE_IN_343X },
+ { .div = 0 },
+};
+
+static const struct clksel traceclk_clksel[] = {
+ { .parent = &traceclk_src_fck, .rates = traceclk_rates },
+ { .parent = NULL },
+};
+
+static struct clk traceclk_fck = {
+ .name = "traceclk_fck",
+ .init = &omap2_init_clksel_parent,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+ .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
+ .clksel = traceclk_clksel,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .recalc = &omap2_clksel_recalc,
+};
+
+/* SR clocks */
+
+/* SmartReflex fclk (VDD1) */
+static struct clk sr1_fck = {
+ .name = "sr1_fck",
+ .parent = &sys_ck,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_SR1_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .recalc = &followparent_recalc,
+};
+
+/* SmartReflex fclk (VDD2) */
+static struct clk sr2_fck = {
+ .name = "sr2_fck",
+ .parent = &sys_ck,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_SR2_SHIFT,
+ .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk sr_l4_ick = {
+ .name = "sr_l4_ick",
+ .parent = &l4_ick,
+ .flags = CLOCK_IN_OMAP343X,
+ .recalc = &followparent_recalc,
+};
+
+/* SECURE_32K_FCK clocks */
+
+static struct clk gpt12_fck = {
+ .name = "gpt12_fck",
+ .parent = &secure_32k_fck,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk wdt1_fck = {
+ .name = "wdt1_fck",
+ .parent = &secure_32k_fck,
+ .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk *onchip_34xx_clks[] __initdata = {
+ &omap_32k_fck,
+ &virt_12m_ck,
+ &virt_13m_ck,
+ &virt_16_8m_ck,
+ &virt_19_2m_ck,
+ &virt_26m_ck,
+ &virt_38_4m_ck,
+ &osc_sys_ck,
+ &sys_ck,
+ &sys_altclk,
+ &mcbsp_clks,
+ &sys_clkout1,
+ &dpll1_ck,
+ &dpll1_x2_ck,
+ &dpll1_x2m2_ck,
+ &dpll2_ck,
+ &dpll2_m2_ck,
+ &dpll3_ck,
+ &core_ck,
+ &dpll3_x2_ck,
+ &dpll3_m2_ck,
+ &dpll3_m2x2_ck,
+ &dpll3_m3_ck,
+ &dpll3_m3x2_ck,
+ &emu_core_alwon_ck,
+ &dpll4_ck,
+ &dpll4_x2_ck,
+ &omap_96m_alwon_fck,
+ &omap_96m_fck,
+ &cm_96m_fck,
+ &virt_omap_54m_fck,
+ &omap_54m_fck,
+ &omap_48m_fck,
+ &omap_12m_fck,
+ &dpll4_m2_ck,
+ &dpll4_m2x2_ck,
+ &dpll4_m3_ck,
+ &dpll4_m3x2_ck,
+ &dpll4_m4_ck,
+ &dpll4_m4x2_ck,
+ &dpll4_m5_ck,
+ &dpll4_m5x2_ck,
+ &dpll4_m6_ck,
+ &dpll4_m6x2_ck,
+ &emu_per_alwon_ck,
+ &dpll5_ck,
+ &dpll5_m2_ck,
+ &omap_120m_fck,
+ &clkout2_src_ck,
+ &sys_clkout2,
+ &corex2_fck,
+ &dpll1_fck,
+ &mpu_ck,
+ &arm_fck,
+ &emu_mpu_alwon_ck,
+ &dpll2_fck,
+ &iva2_ck,
+ &l3_ick,
+ &l4_ick,
+ &rm_ick,
+ &gfx_l3_fck,
+ &gfx_l3_ick,
+ &gfx_cg1_ck,
+ &gfx_cg2_ck,
+ &sgx_fck,
+ &sgx_ick,
+ &d2d_26m_fck,
+ &gpt10_fck,
+ &gpt11_fck,
+ &cpefuse_fck,
+ &ts_fck,
+ &usbtll_fck,
+ &core_96m_fck,
+ &mmchs3_fck,
+ &mmchs2_fck,
+ &mspro_fck,
+ &mmchs1_fck,
+ &i2c3_fck,
+ &i2c2_fck,
+ &i2c1_fck,
+ &mcbsp5_fck,
+ &mcbsp1_fck,
+ &core_48m_fck,
+ &mcspi4_fck,
+ &mcspi3_fck,
+ &mcspi2_fck,
+ &mcspi1_fck,
+ &uart2_fck,
+ &uart1_fck,
+ &fshostusb_fck,
+ &core_12m_fck,
+ &hdq_fck,
+ &ssi_ssr_fck,
+ &ssi_sst_fck,
+ &core_l3_ick,
+ &hsotgusb_ick,
+ &sdrc_ick,
+ &gpmc_fck,
+ &security_l3_ick,
+ &pka_ick,
+ &core_l4_ick,
+ &usbtll_ick,
+ &mmchs3_ick,
+ &icr_ick,
+ &aes2_ick,
+ &sha12_ick,
+ &des2_ick,
+ &mmchs2_ick,
+ &mmchs1_ick,
+ &mspro_ick,
+ &hdq_ick,
+ &mcspi4_ick,
+ &mcspi3_ick,
+ &mcspi2_ick,
+ &mcspi1_ick,
+ &i2c3_ick,
+ &i2c2_ick,
+ &i2c1_ick,
+ &uart2_ick,
+ &uart1_ick,
+ &gpt11_ick,
+ &gpt10_ick,
+ &mcbsp5_ick,
+ &mcbsp1_ick,
+ &fac_ick,
+ &mailboxes_ick,
+ &omapctrl_ick,
+ &ssi_l4_ick,
+ &ssi_ick,
+ &usb_l4_ick,
+ &security_l4_ick2,
+ &aes1_ick,
+ &rng_ick,
+ &sha11_ick,
+ &des1_ick,
+ &dss1_alwon_fck,
+ &dss_tv_fck,
+ &dss_96m_fck,
+ &dss2_alwon_fck,
+ &dss_ick,
+ &cam_mclk,
+ &cam_l3_ick,
+ &cam_l4_ick,
+ &usbhost_120m_fck,
+ &usbhost_48m_fck,
+ &usbhost_l3_ick,
+ &usbhost_l4_ick,
+ &usbhost_sar_fck,
+ &usim_fck,
+ &gpt1_fck,
+ &wkup_32k_fck,
+ &gpio1_fck,
+ &wdt2_fck,
+ &wkup_l4_ick,
+ &usim_ick,
+ &wdt2_ick,
+ &wdt1_ick,
+ &gpio1_ick,
+ &omap_32ksync_ick,
+ &gpt12_ick,
+ &gpt1_ick,
+ &per_96m_fck,
+ &per_48m_fck,
+ &uart3_fck,
+ &gpt2_fck,
+ &gpt3_fck,
+ &gpt4_fck,
+ &gpt5_fck,
+ &gpt6_fck,
+ &gpt7_fck,
+ &gpt8_fck,
+ &gpt9_fck,
+ &per_32k_alwon_fck,
+ &gpio6_fck,
+ &gpio5_fck,
+ &gpio4_fck,
+ &gpio3_fck,
+ &gpio2_fck,
+ &wdt3_fck,
+ &per_l4_ick,
+ &gpio6_ick,
+ &gpio5_ick,
+ &gpio4_ick,
+ &gpio3_ick,
+ &gpio2_ick,
+ &wdt3_ick,
+ &uart3_ick,
+ &gpt9_ick,
+ &gpt8_ick,
+ &gpt7_ick,
+ &gpt6_ick,
+ &gpt5_ick,
+ &gpt4_ick,
+ &gpt3_ick,
+ &gpt2_ick,
+ &mcbsp2_ick,
+ &mcbsp3_ick,
+ &mcbsp4_ick,
+ &mcbsp2_fck,
+ &mcbsp3_fck,
+ &mcbsp4_fck,
+ &emu_src_ck,
+ &pclk_fck,
+ &pclkx2_fck,
+ &atclk_fck,
+ &traceclk_src_fck,
+ &traceclk_fck,
+ &sr1_fck,
+ &sr2_fck,
+ &sr_l4_ick,
+ &secure_32k_fck,
+ &gpt12_fck,
+ &wdt1_fck,
+};
+
+#endif
--- /dev/null
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Clock Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP24XX_EN_CAM_SHIFT 31
+#define OMAP24XX_EN_CAM (1 << 31)
+#define OMAP24XX_EN_WDT4_SHIFT 29
+#define OMAP24XX_EN_WDT4 (1 << 29)
+#define OMAP2420_EN_WDT3_SHIFT 28
+#define OMAP2420_EN_WDT3 (1 << 28)
+#define OMAP24XX_EN_MSPRO_SHIFT 27
+#define OMAP24XX_EN_MSPRO (1 << 27)
+#define OMAP24XX_EN_FAC_SHIFT 25
+#define OMAP24XX_EN_FAC (1 << 25)
+#define OMAP2420_EN_EAC_SHIFT 24
+#define OMAP2420_EN_EAC (1 << 24)
+#define OMAP24XX_EN_HDQ_SHIFT 23
+#define OMAP24XX_EN_HDQ (1 << 23)
+#define OMAP2420_EN_I2C2_SHIFT 20
+#define OMAP2420_EN_I2C2 (1 << 20)
+#define OMAP2420_EN_I2C1_SHIFT 19
+#define OMAP2420_EN_I2C1 (1 << 19)
+
+/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
+#define OMAP2430_EN_MCBSP5_SHIFT 5
+#define OMAP2430_EN_MCBSP5 (1 << 5)
+#define OMAP2430_EN_MCBSP4_SHIFT 4
+#define OMAP2430_EN_MCBSP4 (1 << 4)
+#define OMAP2430_EN_MCBSP3_SHIFT 3
+#define OMAP2430_EN_MCBSP3 (1 << 3)
+#define OMAP24XX_EN_SSI_SHIFT 1
+#define OMAP24XX_EN_SSI (1 << 1)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP24XX_EN_MPU_WDT_SHIFT 3
+#define OMAP24XX_EN_MPU_WDT (1 << 3)
+
+/* Bits specific to each register */
+
+/* CM_IDLEST_MPU */
+/* 2430 only */
+#define OMAP2430_ST_MPU (1 << 0)
+
+/* CM_CLKSEL_MPU */
+#define OMAP24XX_CLKSEL_MPU_SHIFT 0
+#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP24XX_AUTOSTATE_MPU (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits*/
+#define OMAP24XX_EN_TV_SHIFT 2
+#define OMAP24XX_EN_TV (1 << 2)
+#define OMAP24XX_EN_DSS2_SHIFT 1
+#define OMAP24XX_EN_DSS2 (1 << 1)
+#define OMAP24XX_EN_DSS1_SHIFT 0
+#define OMAP24XX_EN_DSS1 (1 << 0)
+
+/* CM_FCLKEN2_CORE specific bits */
+#define OMAP2430_EN_I2CHS2_SHIFT 20
+#define OMAP2430_EN_I2CHS2 (1 << 20)
+#define OMAP2430_EN_I2CHS1_SHIFT 19
+#define OMAP2430_EN_I2CHS1 (1 << 19)
+#define OMAP2430_EN_MMCHSDB2_SHIFT 17
+#define OMAP2430_EN_MMCHSDB2 (1 << 17)
+#define OMAP2430_EN_MMCHSDB1_SHIFT 16
+#define OMAP2430_EN_MMCHSDB1 (1 << 16)
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP24XX_EN_MAILBOXES_SHIFT 30
+#define OMAP24XX_EN_MAILBOXES (1 << 30)
+#define OMAP24XX_EN_DSS_SHIFT 0
+#define OMAP24XX_EN_DSS (1 << 0)
+
+/* CM_ICLKEN2_CORE specific bits */
+
+/* CM_ICLKEN3_CORE */
+/* 2430 only */
+#define OMAP2430_EN_SDRC_SHIFT 2
+#define OMAP2430_EN_SDRC (1 << 2)
+
+/* CM_ICLKEN4_CORE */
+#define OMAP24XX_EN_PKA_SHIFT 4
+#define OMAP24XX_EN_PKA (1 << 4)
+#define OMAP24XX_EN_AES_SHIFT 3
+#define OMAP24XX_EN_AES (1 << 3)
+#define OMAP24XX_EN_RNG_SHIFT 2
+#define OMAP24XX_EN_RNG (1 << 2)
+#define OMAP24XX_EN_SHA_SHIFT 1
+#define OMAP24XX_EN_SHA (1 << 1)
+#define OMAP24XX_EN_DES_SHIFT 0
+#define OMAP24XX_EN_DES (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP24XX_ST_MAILBOXES (1 << 30)
+#define OMAP24XX_ST_WDT4 (1 << 29)
+#define OMAP2420_ST_WDT3 (1 << 28)
+#define OMAP24XX_ST_MSPRO (1 << 27)
+#define OMAP24XX_ST_FAC (1 << 25)
+#define OMAP2420_ST_EAC (1 << 24)
+#define OMAP24XX_ST_HDQ (1 << 23)
+#define OMAP24XX_ST_I2C2 (1 << 20)
+#define OMAP24XX_ST_I2C1 (1 << 19)
+#define OMAP24XX_ST_MCBSP2 (1 << 16)
+#define OMAP24XX_ST_MCBSP1 (1 << 15)
+#define OMAP24XX_ST_DSS (1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP2430_ST_MCBSP5 (1 << 5)
+#define OMAP2430_ST_MCBSP4 (1 << 4)
+#define OMAP2430_ST_MCBSP3 (1 << 3)
+#define OMAP24XX_ST_SSI (1 << 1)
+
+/* CM_IDLEST3_CORE */
+/* 2430 only */
+#define OMAP2430_ST_SDRC (1 << 2)
+
+/* CM_IDLEST4_CORE */
+#define OMAP24XX_ST_PKA (1 << 4)
+#define OMAP24XX_ST_AES (1 << 3)
+#define OMAP24XX_ST_RNG (1 << 2)
+#define OMAP24XX_ST_SHA (1 << 1)
+#define OMAP24XX_ST_DES (1 << 0)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP24XX_AUTO_CAM (1 << 31)
+#define OMAP24XX_AUTO_MAILBOXES (1 << 30)
+#define OMAP24XX_AUTO_WDT4 (1 << 29)
+#define OMAP2420_AUTO_WDT3 (1 << 28)
+#define OMAP24XX_AUTO_MSPRO (1 << 27)
+#define OMAP2420_AUTO_MMC (1 << 26)
+#define OMAP24XX_AUTO_FAC (1 << 25)
+#define OMAP2420_AUTO_EAC (1 << 24)
+#define OMAP24XX_AUTO_HDQ (1 << 23)
+#define OMAP24XX_AUTO_UART2 (1 << 22)
+#define OMAP24XX_AUTO_UART1 (1 << 21)
+#define OMAP24XX_AUTO_I2C2 (1 << 20)
+#define OMAP24XX_AUTO_I2C1 (1 << 19)
+#define OMAP24XX_AUTO_MCSPI2 (1 << 18)
+#define OMAP24XX_AUTO_MCSPI1 (1 << 17)
+#define OMAP24XX_AUTO_MCBSP2 (1 << 16)
+#define OMAP24XX_AUTO_MCBSP1 (1 << 15)
+#define OMAP24XX_AUTO_GPT12 (1 << 14)
+#define OMAP24XX_AUTO_GPT11 (1 << 13)
+#define OMAP24XX_AUTO_GPT10 (1 << 12)
+#define OMAP24XX_AUTO_GPT9 (1 << 11)
+#define OMAP24XX_AUTO_GPT8 (1 << 10)
+#define OMAP24XX_AUTO_GPT7 (1 << 9)
+#define OMAP24XX_AUTO_GPT6 (1 << 8)
+#define OMAP24XX_AUTO_GPT5 (1 << 7)
+#define OMAP24XX_AUTO_GPT4 (1 << 6)
+#define OMAP24XX_AUTO_GPT3 (1 << 5)
+#define OMAP24XX_AUTO_GPT2 (1 << 4)
+#define OMAP2420_AUTO_VLYNQ (1 << 3)
+#define OMAP24XX_AUTO_DSS (1 << 0)
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP2430_AUTO_MDM_INTC (1 << 11)
+#define OMAP2430_AUTO_GPIO5 (1 << 10)
+#define OMAP2430_AUTO_MCSPI3 (1 << 9)
+#define OMAP2430_AUTO_MMCHS2 (1 << 8)
+#define OMAP2430_AUTO_MMCHS1 (1 << 7)
+#define OMAP2430_AUTO_USBHS (1 << 6)
+#define OMAP2430_AUTO_MCBSP5 (1 << 5)
+#define OMAP2430_AUTO_MCBSP4 (1 << 4)
+#define OMAP2430_AUTO_MCBSP3 (1 << 3)
+#define OMAP24XX_AUTO_UART3 (1 << 2)
+#define OMAP24XX_AUTO_SSI (1 << 1)
+#define OMAP24XX_AUTO_USB (1 << 0)
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP24XX_AUTO_SDRC (1 << 2)
+#define OMAP24XX_AUTO_GPMC (1 << 1)
+#define OMAP24XX_AUTO_SDMA (1 << 0)
+
+/* CM_AUTOIDLE4_CORE */
+#define OMAP24XX_AUTO_PKA (1 << 4)
+#define OMAP24XX_AUTO_AES (1 << 3)
+#define OMAP24XX_AUTO_RNG (1 << 2)
+#define OMAP24XX_AUTO_SHA (1 << 1)
+#define OMAP24XX_AUTO_DES (1 << 0)
+
+/* CM_CLKSEL1_CORE */
+#define OMAP24XX_CLKSEL_USB_SHIFT 25
+#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
+#define OMAP24XX_CLKSEL_SSI_SHIFT 20
+#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
+#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
+#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
+#define OMAP24XX_CLKSEL_DSS2_SHIFT 13
+#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
+#define OMAP24XX_CLKSEL_DSS1_SHIFT 8
+#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
+#define OMAP24XX_CLKSEL_L4_SHIFT 5
+#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
+#define OMAP24XX_CLKSEL_L3_SHIFT 0
+#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
+
+/* CM_CLKSEL2_CORE */
+#define OMAP24XX_CLKSEL_GPT12_SHIFT 22
+#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
+#define OMAP24XX_CLKSEL_GPT11_SHIFT 20
+#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
+#define OMAP24XX_CLKSEL_GPT10_SHIFT 18
+#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
+#define OMAP24XX_CLKSEL_GPT9_SHIFT 16
+#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
+#define OMAP24XX_CLKSEL_GPT8_SHIFT 14
+#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
+#define OMAP24XX_CLKSEL_GPT7_SHIFT 12
+#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
+#define OMAP24XX_CLKSEL_GPT6_SHIFT 10
+#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
+#define OMAP24XX_CLKSEL_GPT5_SHIFT 8
+#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
+#define OMAP24XX_CLKSEL_GPT4_SHIFT 6
+#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
+#define OMAP24XX_CLKSEL_GPT3_SHIFT 4
+#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
+#define OMAP24XX_CLKSEL_GPT2_SHIFT 2
+#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP24XX_AUTOSTATE_DSS (1 << 2)
+#define OMAP24XX_AUTOSTATE_L4 (1 << 1)
+#define OMAP24XX_AUTOSTATE_L3 (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP24XX_EN_3D_SHIFT 2
+#define OMAP24XX_EN_3D (1 << 2)
+#define OMAP24XX_EN_2D_SHIFT 1
+#define OMAP24XX_EN_2D (1 << 1)
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP24XX_AUTOSTATE_GFX (1 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP2430_EN_ICR_SHIFT 6
+#define OMAP2430_EN_ICR (1 << 6)
+#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
+#define OMAP24XX_EN_OMAPCTRL (1 << 5)
+#define OMAP24XX_EN_WDT1_SHIFT 4
+#define OMAP24XX_EN_WDT1 (1 << 4)
+#define OMAP24XX_EN_32KSYNC_SHIFT 1
+#define OMAP24XX_EN_32KSYNC (1 << 1)
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP2430_ST_ICR (1 << 6)
+#define OMAP24XX_ST_OMAPCTRL (1 << 5)
+#define OMAP24XX_ST_WDT1 (1 << 4)
+#define OMAP24XX_ST_MPU_WDT (1 << 3)
+#define OMAP24XX_ST_32KSYNC (1 << 1)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP24XX_AUTO_OMAPCTRL (1 << 5)
+#define OMAP24XX_AUTO_WDT1 (1 << 4)
+#define OMAP24XX_AUTO_MPU_WDT (1 << 3)
+#define OMAP24XX_AUTO_GPIOS (1 << 2)
+#define OMAP24XX_AUTO_32KSYNC (1 << 1)
+#define OMAP24XX_AUTO_GPT1 (1 << 0)
+
+/* CM_CLKSEL_WKUP */
+#define OMAP24XX_CLKSEL_GPT1_SHIFT 0
+#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP24XX_EN_54M_PLL_SHIFT 6
+#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
+#define OMAP24XX_EN_96M_PLL_SHIFT 2
+#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
+#define OMAP24XX_EN_DPLL_SHIFT 0
+#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP24XX_ST_54M_APLL (1 << 9)
+#define OMAP24XX_ST_96M_APLL (1 << 8)
+#define OMAP24XX_ST_54M_CLK (1 << 6)
+#define OMAP24XX_ST_12M_CLK (1 << 5)
+#define OMAP24XX_ST_48M_CLK (1 << 4)
+#define OMAP24XX_ST_96M_CLK (1 << 2)
+#define OMAP24XX_ST_CORE_CLK_SHIFT 0
+#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP24XX_AUTO_54M_SHIFT 6
+#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
+#define OMAP24XX_AUTO_96M_SHIFT 2
+#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
+#define OMAP24XX_AUTO_DPLL_SHIFT 0
+#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
+
+/* CM_CLKSEL1_PLL */
+#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
+#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
+#define OMAP24XX_APLLS_CLKIN_SHIFT 23
+#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
+#define OMAP24XX_DPLL_MULT_SHIFT 12
+#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
+#define OMAP24XX_DPLL_DIV_SHIFT 8
+#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
+#define OMAP24XX_54M_SOURCE_SHIFT 5
+#define OMAP24XX_54M_SOURCE (1 << 5)
+#define OMAP2430_96M_SOURCE_SHIFT 4
+#define OMAP2430_96M_SOURCE (1 << 4)
+#define OMAP24XX_48M_SOURCE_SHIFT 3
+#define OMAP24XX_48M_SOURCE (1 << 3)
+#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
+#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP24XX_CORE_CLK_SRC_SHIFT 0
+#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
+
+/* CM_FCLKEN_DSP */
+#define OMAP2420_EN_IVA_COP_SHIFT 10
+#define OMAP2420_EN_IVA_COP (1 << 10)
+#define OMAP2420_EN_IVA_MPU_SHIFT 8
+#define OMAP2420_EN_IVA_MPU (1 << 8)
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0)
+
+/* CM_ICLKEN_DSP */
+#define OMAP2420_EN_DSP_IPI_SHIFT 1
+#define OMAP2420_EN_DSP_IPI (1 << 1)
+
+/* CM_IDLEST_DSP */
+#define OMAP2420_ST_IVA (1 << 8)
+#define OMAP2420_ST_IPI (1 << 1)
+#define OMAP24XX_ST_DSP (1 << 0)
+
+/* CM_AUTOIDLE_DSP */
+#define OMAP2420_AUTO_DSP_IPI (1 << 1)
+
+/* CM_CLKSEL_DSP */
+#define OMAP2420_SYNC_IVA (1 << 13)
+#define OMAP2420_CLKSEL_IVA_SHIFT 8
+#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
+#define OMAP24XX_SYNC_DSP (1 << 7)
+#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
+#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
+#define OMAP24XX_CLKSEL_DSP_SHIFT 0
+#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
+
+/* CM_CLKSTCTRL_DSP */
+#define OMAP2420_AUTOSTATE_IVA (1 << 8)
+#define OMAP24XX_AUTOSTATE_DSP (1 << 0)
+
+/* CM_FCLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_EN_OSC_SHIFT 1
+#define OMAP2430_EN_OSC (1 << 1)
+
+/* CM_ICLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0)
+
+/* CM_IDLEST_MDM specific bits */
+/* 2430 only */
+
+/* CM_AUTOIDLE_MDM */
+/* 2430 only */
+#define OMAP2430_AUTO_OSC (1 << 1)
+#define OMAP2430_AUTO_MDM (1 << 0)
+
+/* CM_CLKSEL_MDM */
+/* 2430 only */
+#define OMAP2430_SYNC_MDM (1 << 4)
+#define OMAP2430_CLKSEL_MDM_SHIFT 0
+#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
+
+/* CM_CLKSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_AUTOSTATE_MDM (1 << 0)
+
+#endif
--- /dev/null
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Clock Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
+#define OMAP3430ES2_EN_MMC3_SHIFT 30
+#define OMAP3430_EN_MSPRO (1 << 23)
+#define OMAP3430_EN_MSPRO_SHIFT 23
+#define OMAP3430_EN_HDQ (1 << 22)
+#define OMAP3430_EN_HDQ_SHIFT 22
+#define OMAP3430ES1_EN_FSHOSTUSB (1 << 5)
+#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
+#define OMAP3430ES1_EN_D2D (1 << 3)
+#define OMAP3430ES1_EN_D2D_SHIFT 3
+#define OMAP3430_EN_SSI (1 << 0)
+#define OMAP3430_EN_SSI_SHIFT 0
+
+/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
+#define OMAP3430ES2_EN_USBTLL_SHIFT 2
+#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP3430_EN_WDT2 (1 << 5)
+#define OMAP3430_EN_WDT2_SHIFT 5
+
+/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
+#define OMAP3430_EN_CAM (1 << 0)
+#define OMAP3430_EN_CAM_SHIFT 0
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
+#define OMAP3430_EN_WDT3 (1 << 12)
+#define OMAP3430_EN_WDT3_SHIFT 12
+
+/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
+#define OMAP3430_OVERRIDE_ENABLE (1 << 19)
+
+
+/* Bits specific to each register */
+
+/* CM_FCLKEN_IVA2 */
+#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0)
+
+/* CM_CLKEN_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
+#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
+#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
+#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
+
+/* CM_IDLEST_IVA2 */
+#define OMAP3430_ST_IVA2 (1 << 0)
+
+/* CM_IDLEST_PLL_IVA2 */
+#define OMAP3430_ST_IVA2_CLK (1 << 0)
+
+/* CM_AUTOIDLE_PLL_IVA2 */
+#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
+#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_IVA2 */
+#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
+#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
+#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
+#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
+#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
+
+/* CM_CLKSTCTRL_IVA2 */
+#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
+#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
+
+/* CM_CLKSTST_IVA2 */
+#define OMAP3430_CLKACTIVITY_IVA2 (1 << 0)
+
+/* CM_REVISION specific bits */
+
+/* CM_SYSCONFIG specific bits */
+
+/* CM_CLKEN_PLL_MPU */
+#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
+#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
+#define OMAP3430_EN_MPU_DPLL_SHIFT 0
+#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
+
+/* CM_IDLEST_MPU */
+#define OMAP3430_ST_MPU (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK (1 << 0)
+#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
+
+/* CM_AUTOIDLE_PLL_MPU */
+#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
+#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_MPU */
+#define OMAP3430_MPU_CLK_SRC_SHIFT 19
+#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
+#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
+#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
+#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_MPU */
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
+#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
+
+/* CM_CLKSTST_MPU */
+#define OMAP3430_CLKACTIVITY_MPU (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits */
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP3430_EN_ICR (1 << 29)
+#define OMAP3430_EN_ICR_SHIFT 29
+#define OMAP3430_EN_AES2 (1 << 28)
+#define OMAP3430_EN_AES2_SHIFT 28
+#define OMAP3430_EN_SHA12 (1 << 27)
+#define OMAP3430_EN_SHA12_SHIFT 27
+#define OMAP3430_EN_DES2 (1 << 26)
+#define OMAP3430_EN_DES2_SHIFT 26
+#define OMAP3430ES1_EN_FAC (1 << 8)
+#define OMAP3430ES1_EN_FAC_SHIFT 8
+#define OMAP3430_EN_MAILBOXES (1 << 7)
+#define OMAP3430_EN_MAILBOXES_SHIFT 7
+#define OMAP3430_EN_OMAPCTRL (1 << 6)
+#define OMAP3430_EN_OMAPCTRL_SHIFT 6
+#define OMAP3430_EN_SDRC (1 << 1)
+#define OMAP3430_EN_SDRC_SHIFT 1
+
+/* CM_ICLKEN2_CORE */
+#define OMAP3430_EN_PKA (1 << 4)
+#define OMAP3430_EN_PKA_SHIFT 4
+#define OMAP3430_EN_AES1 (1 << 3)
+#define OMAP3430_EN_AES1_SHIFT 3
+#define OMAP3430_EN_RNG (1 << 2)
+#define OMAP3430_EN_RNG_SHIFT 2
+#define OMAP3430_EN_SHA11 (1 << 1)
+#define OMAP3430_EN_SHA11_SHIFT 1
+#define OMAP3430_EN_DES1 (1 << 0)
+#define OMAP3430_EN_DES1_SHIFT 0
+
+/* CM_FCLKEN3_CORE specific bits */
+#define OMAP3430ES2_EN_TS_SHIFT 1
+#define OMAP3430ES2_EN_TS_MASK (1 << 1)
+#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
+#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP3430_ST_ICR (1 << 29)
+#define OMAP3430_ST_AES2 (1 << 28)
+#define OMAP3430_ST_SHA12 (1 << 27)
+#define OMAP3430_ST_DES2 (1 << 26)
+#define OMAP3430_ST_MSPRO (1 << 23)
+#define OMAP3430_ST_HDQ (1 << 22)
+#define OMAP3430ES1_ST_FAC (1 << 8)
+#define OMAP3430ES1_ST_MAILBOXES (1 << 7)
+#define OMAP3430_ST_OMAPCTRL (1 << 6)
+#define OMAP3430_ST_SDMA (1 << 2)
+#define OMAP3430_ST_SDRC (1 << 1)
+#define OMAP3430_ST_SSI (1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP3430_ST_PKA (1 << 4)
+#define OMAP3430_ST_AES1 (1 << 3)
+#define OMAP3430_ST_RNG (1 << 2)
+#define OMAP3430_ST_SHA11 (1 << 1)
+#define OMAP3430_ST_DES1 (1 << 0)
+
+/* CM_IDLEST3_CORE */
+#define OMAP3430ES2_ST_USBTLL_SHIFT 2
+#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP3430_AUTO_AES2 (1 << 28)
+#define OMAP3430_AUTO_AES2_SHIFT 28
+#define OMAP3430_AUTO_SHA12 (1 << 27)
+#define OMAP3430_AUTO_SHA12_SHIFT 27
+#define OMAP3430_AUTO_DES2 (1 << 26)
+#define OMAP3430_AUTO_DES2_SHIFT 26
+#define OMAP3430_AUTO_MMC2 (1 << 25)
+#define OMAP3430_AUTO_MMC2_SHIFT 25
+#define OMAP3430_AUTO_MMC1 (1 << 24)
+#define OMAP3430_AUTO_MMC1_SHIFT 24
+#define OMAP3430_AUTO_MSPRO (1 << 23)
+#define OMAP3430_AUTO_MSPRO_SHIFT 23
+#define OMAP3430_AUTO_HDQ (1 << 22)
+#define OMAP3430_AUTO_HDQ_SHIFT 22
+#define OMAP3430_AUTO_MCSPI4 (1 << 21)
+#define OMAP3430_AUTO_MCSPI4_SHIFT 21
+#define OMAP3430_AUTO_MCSPI3 (1 << 20)
+#define OMAP3430_AUTO_MCSPI3_SHIFT 20
+#define OMAP3430_AUTO_MCSPI2 (1 << 19)
+#define OMAP3430_AUTO_MCSPI2_SHIFT 19
+#define OMAP3430_AUTO_MCSPI1 (1 << 18)
+#define OMAP3430_AUTO_MCSPI1_SHIFT 18
+#define OMAP3430_AUTO_I2C3 (1 << 17)
+#define OMAP3430_AUTO_I2C3_SHIFT 17
+#define OMAP3430_AUTO_I2C2 (1 << 16)
+#define OMAP3430_AUTO_I2C2_SHIFT 16
+#define OMAP3430_AUTO_I2C1 (1 << 15)
+#define OMAP3430_AUTO_I2C1_SHIFT 15
+#define OMAP3430_AUTO_UART2 (1 << 14)
+#define OMAP3430_AUTO_UART2_SHIFT 14
+#define OMAP3430_AUTO_UART1 (1 << 13)
+#define OMAP3430_AUTO_UART1_SHIFT 13
+#define OMAP3430_AUTO_GPT11 (1 << 12)
+#define OMAP3430_AUTO_GPT11_SHIFT 12
+#define OMAP3430_AUTO_GPT10 (1 << 11)
+#define OMAP3430_AUTO_GPT10_SHIFT 11
+#define OMAP3430_AUTO_MCBSP5 (1 << 10)
+#define OMAP3430_AUTO_MCBSP5_SHIFT 10
+#define OMAP3430_AUTO_MCBSP1 (1 << 9)
+#define OMAP3430_AUTO_MCBSP1_SHIFT 9
+#define OMAP3430ES1_AUTO_FAC (1 << 8)
+#define OMAP3430ES1_AUTO_FAC_SHIFT 8
+#define OMAP3430_AUTO_MAILBOXES (1 << 7)
+#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
+#define OMAP3430_AUTO_OMAPCTRL (1 << 6)
+#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
+#define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5)
+#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
+#define OMAP3430_AUTO_HSOTGUSB (1 << 4)
+#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
+#define OMAP3430ES1_AUTO_D2D (1 << 3)
+#define OMAP3430ES1_AUTO_D2D_SHIFT 3
+#define OMAP3430_AUTO_SSI (1 << 0)
+#define OMAP3430_AUTO_SSI_SHIFT 0
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP3430_AUTO_PKA (1 << 4)
+#define OMAP3430_AUTO_PKA_SHIFT 4
+#define OMAP3430_AUTO_AES1 (1 << 3)
+#define OMAP3430_AUTO_AES1_SHIFT 3
+#define OMAP3430_AUTO_RNG (1 << 2)
+#define OMAP3430_AUTO_RNG_SHIFT 2
+#define OMAP3430_AUTO_SHA11 (1 << 1)
+#define OMAP3430_AUTO_SHA11_SHIFT 1
+#define OMAP3430_AUTO_DES1 (1 << 0)
+#define OMAP3430_AUTO_DES1_SHIFT 0
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
+#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
+
+/* CM_CLKSEL_CORE */
+#define OMAP3430_CLKSEL_SSI_SHIFT 8
+#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
+#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
+#define OMAP3430_CLKSEL_GPT11_SHIFT 7
+#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
+#define OMAP3430_CLKSEL_GPT10_SHIFT 6
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
+#define OMAP3430_CLKSEL_L4_SHIFT 2
+#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
+#define OMAP3430_CLKSEL_L3_SHIFT 0
+#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
+#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
+#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
+#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
+#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
+#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
+
+/* CM_CLKSTST_CORE */
+#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2)
+#define OMAP3430_CLKACTIVITY_L4 (1 << 1)
+#define OMAP3430_CLKACTIVITY_L3 (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP3430ES1_EN_3D (1 << 2)
+#define OMAP3430ES1_EN_3D_SHIFT 2
+#define OMAP3430ES1_EN_2D (1 << 1)
+#define OMAP3430ES1_EN_2D_SHIFT 1
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_SLEEPDEP_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
+#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
+
+/* CM_CLKSTST_GFX */
+#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0)
+
+/* CM_FCLKEN_SGX */
+#define OMAP3430ES2_EN_SGX_SHIFT 1
+#define OMAP3430ES2_EN_SGX_MASK (1 << 1)
+
+/* CM_CLKSEL_SGX */
+#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
+#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP3430_EN_WDT1 (1 << 4)
+#define OMAP3430_EN_WDT1_SHIFT 4
+#define OMAP3430_EN_32KSYNC (1 << 2)
+#define OMAP3430_EN_32KSYNC_SHIFT 2
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP3430_ST_WDT2 (1 << 5)
+#define OMAP3430_ST_WDT1 (1 << 4)
+#define OMAP3430_ST_32KSYNC (1 << 2)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP3430_AUTO_WDT2 (1 << 5)
+#define OMAP3430_AUTO_WDT2_SHIFT 5
+#define OMAP3430_AUTO_WDT1 (1 << 4)
+#define OMAP3430_AUTO_WDT1_SHIFT 4
+#define OMAP3430_AUTO_GPIO1 (1 << 3)
+#define OMAP3430_AUTO_GPIO1_SHIFT 3
+#define OMAP3430_AUTO_32KSYNC (1 << 2)
+#define OMAP3430_AUTO_32KSYNC_SHIFT 2
+#define OMAP3430_AUTO_GPT12 (1 << 1)
+#define OMAP3430_AUTO_GPT12_SHIFT 1
+#define OMAP3430_AUTO_GPT1 (1 << 0)
+#define OMAP3430_AUTO_GPT1_SHIFT 0
+
+/* CM_CLKSEL_WKUP */
+#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
+#define OMAP3430_CLKSEL_RM_SHIFT 1
+#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
+#define OMAP3430_CLKSEL_GPT1_SHIFT 0
+#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
+#define OMAP3430_PWRDN_CAM_SHIFT 30
+#define OMAP3430_PWRDN_DSS1_SHIFT 29
+#define OMAP3430_PWRDN_TV_SHIFT 28
+#define OMAP3430_PWRDN_96M_SHIFT 27
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
+#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
+#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
+#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
+#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
+#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
+#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
+#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
+#define OMAP3430_EN_CORE_DPLL_SHIFT 0
+#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKEN2_PLL */
+#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
+#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
+#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
+#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
+#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP3430_ST_54M_CLK (1 << 5)
+#define OMAP3430_ST_12M_CLK (1 << 4)
+#define OMAP3430_ST_48M_CLK (1 << 3)
+#define OMAP3430_ST_96M_CLK (1 << 2)
+#define OMAP3430_ST_PERIPH_CLK (1 << 1)
+#define OMAP3430_ST_CORE_CLK (1 << 0)
+
+/* CM_IDLEST2_CKGEN */
+#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
+#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
+#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
+#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
+#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
+#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
+#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
+
+/* CM_CLKSEL1_PLL */
+/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
+#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
+#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
+#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
+#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
+#define OMAP3430_SOURCE_54M (1 << 5)
+#define OMAP3430_SOURCE_48M (1 << 3)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
+#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
+#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL3_PLL */
+#define OMAP3430_DIV_96M_SHIFT 0
+#define OMAP3430_DIV_96M_MASK (0x1f << 0)
+
+/* CM_CLKSEL4_PLL */
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL5_PLL */
+#define OMAP3430ES2_DIV_120M_SHIFT 0
+#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
+
+/* CM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT2_EN_SHIFT 7
+#define OMAP3430_CLKOUT2_EN (1 << 7)
+#define OMAP3430_CLKOUT2_DIV_SHIFT 3
+#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
+#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
+#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
+
+/* CM_FCLKEN_DSS */
+#define OMAP3430_EN_TV (1 << 2)
+#define OMAP3430_EN_TV_SHIFT 2
+#define OMAP3430_EN_DSS2 (1 << 1)
+#define OMAP3430_EN_DSS2_SHIFT 1
+#define OMAP3430_EN_DSS1 (1 << 0)
+#define OMAP3430_EN_DSS1_SHIFT 0
+
+/* CM_ICLKEN_DSS */
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0)
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
+
+/* CM_IDLEST_DSS */
+#define OMAP3430_ST_DSS (1 << 0)
+
+/* CM_AUTOIDLE_DSS */
+#define OMAP3430_AUTO_DSS (1 << 0)
+#define OMAP3430_AUTO_DSS_SHIFT 0
+
+/* CM_CLKSEL_DSS */
+#define OMAP3430_CLKSEL_TV_SHIFT 8
+#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
+#define OMAP3430_CLKSEL_DSS1_SHIFT 0
+#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
+
+/* CM_SLEEPDEP_DSS specific bits */
+
+/* CM_CLKSTCTRL_DSS */
+#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
+#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
+
+/* CM_CLKSTST_DSS */
+#define OMAP3430_CLKACTIVITY_DSS (1 << 0)
+
+/* CM_FCLKEN_CAM specific bits */
+
+/* CM_ICLKEN_CAM specific bits */
+
+/* CM_IDLEST_CAM */
+#define OMAP3430_ST_CAM (1 << 0)
+
+/* CM_AUTOIDLE_CAM */
+#define OMAP3430_AUTO_CAM (1 << 0)
+#define OMAP3430_AUTO_CAM_SHIFT 0
+
+/* CM_CLKSEL_CAM */
+#define OMAP3430_CLKSEL_CAM_SHIFT 0
+#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
+
+/* CM_SLEEPDEP_CAM specific bits */
+
+/* CM_CLKSTCTRL_CAM */
+#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
+#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
+
+/* CM_CLKSTST_CAM */
+#define OMAP3430_CLKACTIVITY_CAM (1 << 0)
+
+/* CM_FCLKEN_PER specific bits */
+
+/* CM_ICLKEN_PER specific bits */
+
+/* CM_IDLEST_PER */
+#define OMAP3430_ST_WDT3 (1 << 12)
+#define OMAP3430_ST_MCBSP4 (1 << 2)
+#define OMAP3430_ST_MCBSP3 (1 << 1)
+#define OMAP3430_ST_MCBSP2 (1 << 0)
+
+/* CM_AUTOIDLE_PER */
+#define OMAP3430_AUTO_GPIO6 (1 << 17)
+#define OMAP3430_AUTO_GPIO6_SHIFT 17
+#define OMAP3430_AUTO_GPIO5 (1 << 16)
+#define OMAP3430_AUTO_GPIO5_SHIFT 16
+#define OMAP3430_AUTO_GPIO4 (1 << 15)
+#define OMAP3430_AUTO_GPIO4_SHIFT 15
+#define OMAP3430_AUTO_GPIO3 (1 << 14)
+#define OMAP3430_AUTO_GPIO3_SHIFT 14
+#define OMAP3430_AUTO_GPIO2 (1 << 13)
+#define OMAP3430_AUTO_GPIO2_SHIFT 13
+#define OMAP3430_AUTO_WDT3 (1 << 12)
+#define OMAP3430_AUTO_WDT3_SHIFT 12
+#define OMAP3430_AUTO_UART3 (1 << 11)
+#define OMAP3430_AUTO_UART3_SHIFT 11
+#define OMAP3430_AUTO_GPT9 (1 << 10)
+#define OMAP3430_AUTO_GPT9_SHIFT 10
+#define OMAP3430_AUTO_GPT8 (1 << 9)
+#define OMAP3430_AUTO_GPT8_SHIFT 9
+#define OMAP3430_AUTO_GPT7 (1 << 8)
+#define OMAP3430_AUTO_GPT7_SHIFT 8
+#define OMAP3430_AUTO_GPT6 (1 << 7)
+#define OMAP3430_AUTO_GPT6_SHIFT 7
+#define OMAP3430_AUTO_GPT5 (1 << 6)
+#define OMAP3430_AUTO_GPT5_SHIFT 6
+#define OMAP3430_AUTO_GPT4 (1 << 5)
+#define OMAP3430_AUTO_GPT4_SHIFT 5
+#define OMAP3430_AUTO_GPT3 (1 << 4)
+#define OMAP3430_AUTO_GPT3_SHIFT 4
+#define OMAP3430_AUTO_GPT2 (1 << 3)
+#define OMAP3430_AUTO_GPT2_SHIFT 3
+#define OMAP3430_AUTO_MCBSP4 (1 << 2)
+#define OMAP3430_AUTO_MCBSP4_SHIFT 2
+#define OMAP3430_AUTO_MCBSP3 (1 << 1)
+#define OMAP3430_AUTO_MCBSP3_SHIFT 1
+#define OMAP3430_AUTO_MCBSP2 (1 << 0)
+#define OMAP3430_AUTO_MCBSP2_SHIFT 0
+
+/* CM_CLKSEL_PER */
+#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
+#define OMAP3430_CLKSEL_GPT9_SHIFT 7
+#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
+#define OMAP3430_CLKSEL_GPT8_SHIFT 6
+#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
+#define OMAP3430_CLKSEL_GPT7_SHIFT 5
+#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
+#define OMAP3430_CLKSEL_GPT6_SHIFT 4
+#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
+#define OMAP3430_CLKSEL_GPT5_SHIFT 3
+#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
+#define OMAP3430_CLKSEL_GPT4_SHIFT 2
+#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
+#define OMAP3430_CLKSEL_GPT3_SHIFT 1
+#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
+#define OMAP3430_CLKSEL_GPT2_SHIFT 0
+
+/* CM_SLEEPDEP_PER specific bits */
+#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2)
+
+/* CM_CLKSTCTRL_PER */
+#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
+#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
+
+/* CM_CLKSTST_PER */
+#define OMAP3430_CLKACTIVITY_PER (1 << 0)
+
+/* CM_CLKSEL1_EMU */
+#define OMAP3430_DIV_DPLL4_SHIFT 24
+#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
+#define OMAP3430_DIV_DPLL3_SHIFT 16
+#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
+#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
+#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
+#define OMAP3430_CLKSEL_PCLK_SHIFT 8
+#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
+#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
+#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
+#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
+#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
+#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
+#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
+#define OMAP3430_MUX_CTRL_SHIFT 0
+#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
+
+/* CM_CLKSTCTRL_EMU */
+#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
+#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
+
+/* CM_CLKSTST_EMU */
+#define OMAP3430_CLKACTIVITY_EMU (1 << 0)
+
+/* CM_CLKSEL2_EMU specific bits */
+#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
+#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
+#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
+#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
+
+/* CM_CLKSEL3_EMU specific bits */
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
+
+/* CM_POLCTRL */
+#define OMAP3430_CLKOUT2_POL (1 << 0)
+
+/* CM_IDLEST_NEON */
+#define OMAP3430_ST_NEON (1 << 0)
+
+/* CM_CLKSTCTRL_NEON */
+#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
+#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
+
+/* CM_FCLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
+#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
+#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
+#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
+
+/* CM_ICLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST_SHIFT 0
+#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
+
+/* CM_IDLEST_USBHOST */
+
+/* CM_AUTOIDLE_USBHOST */
+#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
+#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
+
+/* CM_SLEEPDEP_USBHOST */
+#define OMAP3430ES2_EN_MPU_SHIFT 1
+#define OMAP3430ES2_EN_MPU_MASK (1 << 1)
+#define OMAP3430ES2_EN_IVA2_SHIFT 2
+#define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
+
+/* CM_CLKSTCTRL_USBHOST */
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
+
+
+
+#endif
--- /dev/null
+#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
+#define __ARCH_ASM_MACH_OMAP2_CM_H
+
+/*
+ * OMAP2/3 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prcm-common.h"
+
+#ifndef __ASSEMBLER__
+#define OMAP_CM_REGADDR(module, reg) \
+ (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
+#else
+#define OMAP2420_CM_REGADDR(module, reg) \
+ IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+#define OMAP2430_CM_REGADDR(module, reg) \
+ IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+#define OMAP34XX_CM_REGADDR(module, reg) \
+ IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+#endif
+
+/*
+ * Architecture-specific global CM registers
+ * Use cm_{read,write}_reg() with these registers.
+ * These registers appear once per CM module.
+ */
+
+#define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c)
+
+#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific CM registers from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* Common between 24xx and 34xx */
+
+#define CM_FCLKEN 0x0000
+#define CM_FCLKEN1 CM_FCLKEN
+#define CM_CLKEN CM_FCLKEN
+#define CM_ICLKEN 0x0010
+#define CM_ICLKEN1 CM_ICLKEN
+#define CM_ICLKEN2 0x0014
+#define CM_ICLKEN3 0x0018
+#define CM_IDLEST 0x0020
+#define CM_IDLEST1 CM_IDLEST
+#define CM_IDLEST2 0x0024
+#define CM_AUTOIDLE 0x0030
+#define CM_AUTOIDLE1 CM_AUTOIDLE
+#define CM_AUTOIDLE2 0x0034
+#define CM_AUTOIDLE3 0x0038
+#define CM_CLKSEL 0x0040
+#define CM_CLKSEL1 CM_CLKSEL
+#define CM_CLKSEL2 0x0044
+#define CM_CLKSTCTRL 0x0048
+
+
+/* Architecture-specific registers */
+
+#define OMAP24XX_CM_FCLKEN2 0x0004
+#define OMAP24XX_CM_ICLKEN4 0x001c
+#define OMAP24XX_CM_AUTOIDLE4 0x003c
+
+#define OMAP2430_CM_IDLEST3 0x0028
+
+#define OMAP3430_CM_CLKEN_PLL 0x0004
+#define OMAP3430ES2_CM_CLKEN2 0x0004
+#define OMAP3430ES2_CM_FCLKEN3 0x0008
+#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
+#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
+#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
+#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
+#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
+#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
+#define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSTST 0x004c
+#define OMAP3430ES2_CM_CLKSEL4 0x004c
+#define OMAP3430ES2_CM_CLKSEL5 0x0050
+#define OMAP3430_CM_CLKSEL2_EMU 0x0050
+#define OMAP3430_CM_CLKSEL3_EMU 0x0054
+
+
+/* Clock management domain register get/set */
+
+#ifndef __ASSEMBLER__
+static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx)
+{
+ __raw_writel(val, OMAP_CM_REGADDR(module, idx));
+}
+
+static inline u32 cm_read_mod_reg(s16 module, s16 idx)
+{
+ return __raw_readl(OMAP_CM_REGADDR(module, idx));
+}
+#endif
+
+/* CM register bits shared between 24XX and 3430 */
+
+/* CM_CLKSEL_GFX */
+#define OMAP_CLKSEL_GFX_SHIFT 0
+#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
+
+/* CM_ICLKEN_GFX */
+#define OMAP_EN_GFX_SHIFT 0
+#define OMAP_EN_GFX (1 << 0)
+
+/* CM_IDLEST_GFX */
+#define OMAP_ST_GFX (1 << 0)
+
+
+#endif
--- /dev/null
+/*
+ * OMAP2/3 System Control Module register access
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/control.h>
+
+static u32 omap2_ctrl_base;
+
+#define OMAP_CTRL_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_ctrl_base \
+ + (reg))
+
+void omap_ctrl_base_set(u32 base)
+{
+ omap2_ctrl_base = base;
+}
+
+u32 omap_ctrl_base_get(void)
+{
+ return omap2_ctrl_base;
+}
+
+u8 omap_ctrl_readb(u16 offset)
+{
+ return __raw_readb(OMAP_CTRL_REGADDR(offset));
+}
+
+u16 omap_ctrl_readw(u16 offset)
+{
+ return __raw_readw(OMAP_CTRL_REGADDR(offset));
+}
+
+u32 omap_ctrl_readl(u16 offset)
+{
+ return __raw_readl(OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writeb(u8 val, u16 offset)
+{
+ pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val,
+ (u32)OMAP_CTRL_REGADDR(offset));
+
+ __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writew(u16 val, u16 offset)
+{
+ pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val,
+ (u32)OMAP_CTRL_REGADDR(offset));
+
+ __raw_writew(val, OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writel(u32 val, u16 offset)
+{
+ pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val,
+ (u32)OMAP_CTRL_REGADDR(offset));
+
+ __raw_writel(val, OMAP_CTRL_REGADDR(offset));
+}
+
static void __iomem *gpmc_cs_base =
(void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
-static struct clk *gpmc_l3_clk;
+static struct clk *gpmc_fck;
static void gpmc_write_reg(int idx, u32 val)
{
return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
}
-/* TODO: Add support for gpmc_fck to clock framework and use it */
unsigned long gpmc_get_fclk_period(void)
{
/* In picoseconds */
- return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
+ return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
}
unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
{
u32 l;
- gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
- BUG_ON(IS_ERR(gpmc_l3_clk));
+ gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
+ if (IS_ERR(gpmc_fck))
+ WARN_ON(1);
+ else
+ clk_enable(gpmc_fck);
l = gpmc_read_reg(GPMC_REVISION);
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
-#include "prcm-regs.h"
+#include "prm.h"
+
#include "memory.h"
+#include "sdrc.h"
+unsigned long omap2_sdrc_base;
+unsigned long omap2_sms_base;
static struct memory_timings mem_timings;
+static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
u32 omap2_memory_get_slow_dll_ctrl(void)
{
return mem_timings.m_type;
}
+/*
+ * Check the DLL lock state, and return tue if running in unlock mode.
+ * This is needed to compensate for the shifted DLL value in unlock mode.
+ */
+u32 omap2_dll_force_needed(void)
+{
+ /* dlla and dllb are a set */
+ u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
+
+ if ((dll_state & (1 << 2)) == (1 << 2))
+ return 1;
+ else
+ return 0;
+}
+
+/*
+ * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
+ * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
+ * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
+ */
+u32 omap2_reprogram_sdrc(u32 level, u32 force)
+{
+ u32 dll_ctrl, m_type;
+ u32 prev = curr_perf_level;
+ unsigned long flags;
+
+ if ((curr_perf_level == level) && !force)
+ return prev;
+
+ if (level == CORE_CLK_SRC_DPLL) {
+ dll_ctrl = omap2_memory_get_slow_dll_ctrl();
+ } else if (level == CORE_CLK_SRC_DPLL_X2) {
+ dll_ctrl = omap2_memory_get_fast_dll_ctrl();
+ } else {
+ return prev;
+ }
+
+ m_type = omap2_memory_get_type();
+
+ local_irq_save(flags);
+ __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
+ omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
+ curr_perf_level = level;
+ local_irq_restore(flags);
+
+ return prev;
+}
+
void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
{
unsigned long dll_cnt;
u32 fast_dll = 0;
- mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
+ mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
* In the case of 2422, its ok to use CS1 instead of CS0.
mem_timings.dll_mode = M_LOCK;
if (mem_timings.base_cs == 0) {
- fast_dll = SDRC_DLLA_CTRL;
- dll_cnt = SDRC_DLLA_STATUS & 0xff00;
+ fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
+ dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
} else {
- fast_dll = SDRC_DLLB_CTRL;
- dll_cnt = SDRC_DLLB_STATUS & 0xff00;
+ fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
+ dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
}
if (force_lock_to_unlock_mode) {
fast_dll &= ~0xff00;
{
u32 l;
- l = SMS_SYSCONFIG;
+ l = sms_read_reg(SMS_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
- SMS_SYSCONFIG = l;
+ sms_write_reg(l, SMS_SYSCONFIG);
- l = SDRC_SYSCONFIG;
+ l = sdrc_read_reg(SDRC_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
- SDRC_SYSCONFIG = l;
-
+ sdrc_write_reg(l, SDRC_SYSCONFIG);
}
extern u32 omap2_memory_get_slow_dll_ctrl(void);
extern u32 omap2_memory_get_fast_dll_ctrl(void);
extern u32 omap2_memory_get_type(void);
+u32 omap2_dll_force_needed(void);
+u32 omap2_reprogram_sdrc(u32 level, u32 force);
/*
* linux/arch/arm/mach-omap2/mux.c
*
- * OMAP1 pin multiplexing configurations
+ * OMAP2 pin multiplexing configurations
*
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2003 - 2008 Nokia Corporation
*
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <asm/io.h>
#include <linux/spinlock.h>
+#include <asm/arch/control.h>
#include <asm/arch/mux.h>
#ifdef CONFIG_OMAP_MUX
+static struct omap_mux_cfg arch_mux_cfg;
+
/* NOTE: See mux.h for the enumeration */
-struct pin_config __initdata_or_module omap24xx_pins[] = {
+#ifdef CONFIG_ARCH_OMAP24XX
+static struct pin_config __initdata_or_module omap24xx_pins[] = {
/*
* description mux mux pull pull debug
* offset mode ena type
MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1)
MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1)
+MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1)
MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
+MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1)
+MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1)
+MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1)
+MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1)
MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1)
MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1)
MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1)
MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1)
MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1)
-/* TSC IRQ */
-MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1)
-
/* UART3 */
MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1)
MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1)
MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1)
MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
+/* 2430 USB */
+MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1)
+MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1)
+MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1)
+MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1)
+MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1)
+MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1)
+MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1)
+MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1)
+MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1)
+MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1)
+MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1)
+
+/* 2430 HS-USB */
+MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1)
+MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1)
+MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1)
+MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1)
+MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1)
+MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1)
+MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1)
+MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1)
+MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1)
+MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1)
+MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1)
+MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1)
+
+/* 2430 McBSP */
+MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1)
+MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1)
+MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1)
+MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1)
+MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1)
+MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1)
+MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1)
+MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
};
-int __init omap2_mux_init(void)
+#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins)
+
+#else
+#define omap24xx_pins NULL
+#define OMAP24XX_PINS_SZ 0
+#endif /* CONFIG_ARCH_OMAP24XX */
+
+#define OMAP24XX_PULL_ENA (1 << 3)
+#define OMAP24XX_PULL_UP (1 << 4)
+
+#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
+void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
{
- omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins));
+ u16 orig;
+ u8 warn = 0, debug = 0;
+
+ orig = omap_ctrl_readb(cfg->mux_reg);
+
+#ifdef CONFIG_OMAP_MUX_DEBUG
+ debug = cfg->debug;
+#endif
+ warn = (orig != reg);
+ if (debug || warn)
+ printk(KERN_WARNING
+ "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
+ cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
+ orig, reg);
+}
+#else
+#define omap2_cfg_debug(x, y) do {} while (0)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP24XX
+int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
+{
+ static DEFINE_SPINLOCK(mux_spin_lock);
+ unsigned long flags;
+ u8 reg = 0;
+
+ spin_lock_irqsave(&mux_spin_lock, flags);
+ reg |= cfg->mask & 0x7;
+ if (cfg->pull_val)
+ reg |= OMAP24XX_PULL_ENA;
+ if (cfg->pu_pd_val)
+ reg |= OMAP24XX_PULL_UP;
+ omap2_cfg_debug(cfg, reg);
+ omap_ctrl_writeb(reg, cfg->mux_reg);
+ spin_unlock_irqrestore(&mux_spin_lock, flags);
+
return 0;
}
+#else
+#define omap24xx_cfg_reg 0
+#endif
+
+int __init omap2_mux_init(void)
+{
+ if (cpu_is_omap24xx()) {
+ arch_mux_cfg.pins = omap24xx_pins;
+ arch_mux_cfg.size = OMAP24XX_PINS_SZ;
+ arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
+ }
+
+ return omap_mux_register(&arch_mux_cfg);
+}
#endif
+++ /dev/null
-/*
- * linux/arch/arm/mach-omap2/pm-domain.c
- *
- * Power domain functions for OMAP2
- *
- * Copyright (C) 2006 Nokia Corporation
- * Tony Lindgren <tony@atomide.com>
- *
- * Some code based on earlier OMAP2 sample PM code
- * Copyright (C) 2005 Texas Instruments, Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <asm/io.h>
-
-#include "prcm-regs.h"
-
-/* Power domain offsets */
-#define PM_MPU_OFFSET 0x100
-#define PM_CORE_OFFSET 0x200
-#define PM_GFX_OFFSET 0x300
-#define PM_WKUP_OFFSET 0x400 /* Autoidle only */
-#define PM_PLL_OFFSET 0x500 /* Autoidle only */
-#define PM_DSP_OFFSET 0x800
-#define PM_MDM_OFFSET 0xc00
-
-/* Power domain wake-up dependency control register */
-#define PM_WKDEP_OFFSET 0xc8
-#define EN_MDM (1 << 5)
-#define EN_WKUP (1 << 4)
-#define EN_GFX (1 << 3)
-#define EN_DSP (1 << 2)
-#define EN_MPU (1 << 1)
-#define EN_CORE (1 << 0)
-
-/* Core power domain state transition control register */
-#define PM_PWSTCTRL_OFFSET 0xe0
-#define FORCESTATE (1 << 18) /* Only for DSP & GFX */
-#define MEM4RETSTATE (1 << 6)
-#define MEM3RETSTATE (1 << 5)
-#define MEM2RETSTATE (1 << 4)
-#define MEM1RETSTATE (1 << 3)
-#define LOGICRETSTATE (1 << 2) /* Logic is retained */
-#define POWERSTATE_OFF 0x3
-#define POWERSTATE_RETENTION 0x1
-#define POWERSTATE_ON 0x0
-
-/* Power domain state register */
-#define PM_PWSTST_OFFSET 0xe4
-
-/* Hardware supervised state transition control register */
-#define CM_CLKSTCTRL_OFFSET 0x48
-#define AUTOSTAT_MPU (1 << 0) /* MPU */
-#define AUTOSTAT_DSS (1 << 2) /* Core */
-#define AUTOSTAT_L4 (1 << 1) /* Core */
-#define AUTOSTAT_L3 (1 << 0) /* Core */
-#define AUTOSTAT_GFX (1 << 0) /* GFX */
-#define AUTOSTAT_IVA (1 << 8) /* 2420 IVA in DSP domain */
-#define AUTOSTAT_DSP (1 << 0) /* DSP */
-#define AUTOSTAT_MDM (1 << 0) /* MDM */
-
-/* Automatic control of interface clock idling */
-#define CM_AUTOIDLE1_OFFSET 0x30
-#define CM_AUTOIDLE2_OFFSET 0x34 /* Core only */
-#define CM_AUTOIDLE3_OFFSET 0x38 /* Core only */
-#define CM_AUTOIDLE4_OFFSET 0x3c /* Core only */
-#define AUTO_54M(x) (((x) & 0x3) << 6)
-#define AUTO_96M(x) (((x) & 0x3) << 2)
-#define AUTO_DPLL(x) (((x) & 0x3) << 0)
-#define AUTO_STOPPED 0x3
-#define AUTO_BYPASS_FAST 0x2 /* DPLL only */
-#define AUTO_BYPASS_LOW_POWER 0x1 /* DPLL only */
-#define AUTO_DISABLED 0x0
-
-/* Voltage control PRCM_VOLTCTRL bits */
-#define AUTO_EXTVOLT (1 << 15)
-#define FORCE_EXTVOLT (1 << 14)
-#define SETOFF_LEVEL(x) (((x) & 0x3) << 12)
-#define MEMRETCTRL (1 << 8)
-#define SETRET_LEVEL(x) (((x) & 0x3) << 6)
-#define VOLT_LEVEL(x) (((x) & 0x3) << 0)
-
-#define OMAP24XX_PRCM_VBASE IO_ADDRESS(OMAP24XX_PRCM_BASE)
-#define prcm_readl(r) __raw_readl(OMAP24XX_PRCM_VBASE + (r))
-#define prcm_writel(v, r) __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
-
-static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
-{
- return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
-}
-
-static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
-{
- prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
-}
-
-static u32 pmdomain_get_powerstate(int domain_offset)
-{
- return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
-}
-
-static void pmdomain_set_powerstate(u32 state, int domain_offset)
-{
- prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
-}
-
-static u32 pmdomain_get_clock_autocontrol(int domain_offset)
-{
- return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
-}
-
-static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
-{
- prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
-}
-
-static u32 pmdomain_get_clock_autoidle1(int domain_offset)
-{
- return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle2(int domain_offset)
-{
- return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle3(int domain_offset)
-{
- return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle4(int domain_offset)
-{
- return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
-}
-
-static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
-{
- prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
-{
- prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
-{
- prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
-{
- prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
-}
-
-/*
- * Configures power management domains to idle clocks automatically.
- */
-void pmdomain_set_autoidle(void)
-{
- u32 val;
-
- /* Set PLL auto stop for 54M, 96M & DPLL */
- pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
- AUTO_96M(AUTO_STOPPED) |
- AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
-
- /* External clock input control
- * REVISIT: Should this be in clock framework?
- */
- PRCM_CLKSRC_CTRL |= (0x3 << 3);
-
- /* Configure number of 32KHz clock cycles for sys_clk */
- PRCM_CLKSSETUP = 0x00ff;
-
- /* Configure automatic voltage transition */
- PRCM_VOLTSETUP = 0;
- val = PRCM_VOLTCTRL;
- val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
- val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
- PRCM_VOLTCTRL = val;
-
- /* Disable emulation tools functional clock */
- PRCM_CLKEMUL_CTRL = 0x0;
-
- /* Set core memory retention state */
- val = pmdomain_get_powerstate(PM_CORE_OFFSET);
- if (cpu_is_omap2420()) {
- val &= ~(0x7 << 3);
- val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
- } else {
- val &= ~(0xf << 3);
- val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
- MEM1RETSTATE);
- }
- pmdomain_set_powerstate(val, PM_CORE_OFFSET);
-
- /* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
- val = SMS_SYSCONFIG;
- val &= ~(0x3 << 3);
- val |= (0x2 << 3) | (1 << 0);
- SMS_SYSCONFIG |= val;
-
- val = SDRC_SYSCONFIG;
- val &= ~(0x3 << 3);
- val |= (0x2 << 3);
- SDRC_SYSCONFIG = val;
-
- /* Configure L3 interface for smart idle.
- * REVISIT: Enable autoidle bit0 ?
- */
- val = GPMC_SYSCONFIG;
- val &= ~(0x3 << 3);
- val |= (0x2 << 3) | (1 << 0);
- GPMC_SYSCONFIG = val;
-
- pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
- PM_MPU_OFFSET);
- pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
- if (!cpu_is_omap2420())
- pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
-
- /* Assume suspend function has saved the state for DSP and GFX */
- pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
- pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
-
-#if 0
- /* REVISIT: Internal USB needs special handling */
- force_standby_usb();
- if (cpu_is_omap2430())
- force_hsmmc();
- sdram_self_refresh_on_idle_req(1);
-#endif
-
- /* Enable clock auto control for all domains.
- * Note that CORE domain includes also DSS, L4 & L3.
- */
- pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
- pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
- pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
- PM_CORE_OFFSET);
- if (cpu_is_omap2420())
- pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
- PM_DSP_OFFSET);
- else {
- pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
- pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
- }
-
- /* Enable clock autoidle for all domains */
- pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
- if (cpu_is_omap2420()) {
- pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
- pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
- pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
- } else {
- pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
- pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
- pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
- pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
- }
- pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
- pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
-}
-
-/*
- * Initializes power domains by removing wake-up dependencies and powering
- * down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
- * must re-enable DSP and GFX when used.
- */
-void __init pmdomain_init(void)
-{
- /* Remove all domain wakeup dependencies */
- pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
- pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
- pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
- pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
- if (cpu_is_omap2430())
- pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
-
- /* Power down DSP and GFX */
- pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
- pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
-}
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
+#include <linux/clk.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/arch/sram.h>
#include <asm/arch/pm.h>
-#include "prcm-regs.h"
-
static struct clk *vclk;
static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
return 0;
}
-#define INT0_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) | \
- OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) | \
- OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3))
-
-#define INT1_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4))
-
-#define INT2_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) | \
- OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) | \
- OMAP_IRQ_BIT(INT_24XX_UART3_IRQ))
-
-#define preg(reg) printk("%s\t(0x%p):\t0x%08x\n", #reg, ®, reg);
-
-static void omap2_pm_debug(char * desc)
-{
- printk("%s:\n", desc);
-
- preg(CM_CLKSTCTRL_MPU);
- preg(CM_CLKSTCTRL_CORE);
- preg(CM_CLKSTCTRL_GFX);
- preg(CM_CLKSTCTRL_DSP);
- preg(CM_CLKSTCTRL_MDM);
-
- preg(PM_PWSTCTRL_MPU);
- preg(PM_PWSTCTRL_CORE);
- preg(PM_PWSTCTRL_GFX);
- preg(PM_PWSTCTRL_DSP);
- preg(PM_PWSTCTRL_MDM);
-
- preg(PM_PWSTST_MPU);
- preg(PM_PWSTST_CORE);
- preg(PM_PWSTST_GFX);
- preg(PM_PWSTST_DSP);
- preg(PM_PWSTST_MDM);
-
- preg(CM_AUTOIDLE1_CORE);
- preg(CM_AUTOIDLE2_CORE);
- preg(CM_AUTOIDLE3_CORE);
- preg(CM_AUTOIDLE4_CORE);
- preg(CM_AUTOIDLE_WKUP);
- preg(CM_AUTOIDLE_PLL);
- preg(CM_AUTOIDLE_DSP);
- preg(CM_AUTOIDLE_MDM);
-
- preg(CM_ICLKEN1_CORE);
- preg(CM_ICLKEN2_CORE);
- preg(CM_ICLKEN3_CORE);
- preg(CM_ICLKEN4_CORE);
- preg(CM_ICLKEN_GFX);
- preg(CM_ICLKEN_WKUP);
- preg(CM_ICLKEN_DSP);
- preg(CM_ICLKEN_MDM);
-
- preg(CM_IDLEST1_CORE);
- preg(CM_IDLEST2_CORE);
- preg(CM_IDLEST3_CORE);
- preg(CM_IDLEST4_CORE);
- preg(CM_IDLEST_GFX);
- preg(CM_IDLEST_WKUP);
- preg(CM_IDLEST_CKGEN);
- preg(CM_IDLEST_DSP);
- preg(CM_IDLEST_MDM);
-
- preg(RM_RSTST_MPU);
- preg(RM_RSTST_GFX);
- preg(RM_RSTST_WKUP);
- preg(RM_RSTST_DSP);
- preg(RM_RSTST_MDM);
-
- preg(PM_WKDEP_MPU);
- preg(PM_WKDEP_CORE);
- preg(PM_WKDEP_GFX);
- preg(PM_WKDEP_DSP);
- preg(PM_WKDEP_MDM);
-
- preg(CM_FCLKEN_WKUP);
- preg(CM_ICLKEN_WKUP);
- preg(CM_IDLEST_WKUP);
- preg(CM_AUTOIDLE_WKUP);
- preg(CM_CLKSEL_WKUP);
-
- preg(PM_WKEN_WKUP);
- preg(PM_WKST_WKUP);
-}
-
-static inline void omap2_pm_save_registers(void)
-{
- /* Save interrupt registers */
- OMAP24XX_SAVE(INTC_MIR0);
- OMAP24XX_SAVE(INTC_MIR1);
- OMAP24XX_SAVE(INTC_MIR2);
-
- /* Save power control registers */
- OMAP24XX_SAVE(CM_CLKSTCTRL_MPU);
- OMAP24XX_SAVE(CM_CLKSTCTRL_CORE);
- OMAP24XX_SAVE(CM_CLKSTCTRL_GFX);
- OMAP24XX_SAVE(CM_CLKSTCTRL_DSP);
- OMAP24XX_SAVE(CM_CLKSTCTRL_MDM);
-
- /* Save power state registers */
- OMAP24XX_SAVE(PM_PWSTCTRL_MPU);
- OMAP24XX_SAVE(PM_PWSTCTRL_CORE);
- OMAP24XX_SAVE(PM_PWSTCTRL_GFX);
- OMAP24XX_SAVE(PM_PWSTCTRL_DSP);
- OMAP24XX_SAVE(PM_PWSTCTRL_MDM);
-
- /* Save autoidle registers */
- OMAP24XX_SAVE(CM_AUTOIDLE1_CORE);
- OMAP24XX_SAVE(CM_AUTOIDLE2_CORE);
- OMAP24XX_SAVE(CM_AUTOIDLE3_CORE);
- OMAP24XX_SAVE(CM_AUTOIDLE4_CORE);
- OMAP24XX_SAVE(CM_AUTOIDLE_WKUP);
- OMAP24XX_SAVE(CM_AUTOIDLE_PLL);
- OMAP24XX_SAVE(CM_AUTOIDLE_DSP);
- OMAP24XX_SAVE(CM_AUTOIDLE_MDM);
-
- /* Save idle state registers */
- OMAP24XX_SAVE(CM_IDLEST1_CORE);
- OMAP24XX_SAVE(CM_IDLEST2_CORE);
- OMAP24XX_SAVE(CM_IDLEST3_CORE);
- OMAP24XX_SAVE(CM_IDLEST4_CORE);
- OMAP24XX_SAVE(CM_IDLEST_GFX);
- OMAP24XX_SAVE(CM_IDLEST_WKUP);
- OMAP24XX_SAVE(CM_IDLEST_CKGEN);
- OMAP24XX_SAVE(CM_IDLEST_DSP);
- OMAP24XX_SAVE(CM_IDLEST_MDM);
-
- /* Save clock registers */
- OMAP24XX_SAVE(CM_FCLKEN1_CORE);
- OMAP24XX_SAVE(CM_FCLKEN2_CORE);
- OMAP24XX_SAVE(CM_ICLKEN1_CORE);
- OMAP24XX_SAVE(CM_ICLKEN2_CORE);
- OMAP24XX_SAVE(CM_ICLKEN3_CORE);
- OMAP24XX_SAVE(CM_ICLKEN4_CORE);
-}
-
-static inline void omap2_pm_restore_registers(void)
-{
- /* Restore clock state registers */
- OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU);
- OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE);
- OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX);
- OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP);
- OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM);
-
- /* Restore power state registers */
- OMAP24XX_RESTORE(PM_PWSTCTRL_MPU);
- OMAP24XX_RESTORE(PM_PWSTCTRL_CORE);
- OMAP24XX_RESTORE(PM_PWSTCTRL_GFX);
- OMAP24XX_RESTORE(PM_PWSTCTRL_DSP);
- OMAP24XX_RESTORE(PM_PWSTCTRL_MDM);
-
- /* Restore idle state registers */
- OMAP24XX_RESTORE(CM_IDLEST1_CORE);
- OMAP24XX_RESTORE(CM_IDLEST2_CORE);
- OMAP24XX_RESTORE(CM_IDLEST3_CORE);
- OMAP24XX_RESTORE(CM_IDLEST4_CORE);
- OMAP24XX_RESTORE(CM_IDLEST_GFX);
- OMAP24XX_RESTORE(CM_IDLEST_WKUP);
- OMAP24XX_RESTORE(CM_IDLEST_CKGEN);
- OMAP24XX_RESTORE(CM_IDLEST_DSP);
- OMAP24XX_RESTORE(CM_IDLEST_MDM);
-
- /* Restore autoidle registers */
- OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE);
- OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE);
- OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE);
- OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE);
- OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP);
- OMAP24XX_RESTORE(CM_AUTOIDLE_PLL);
- OMAP24XX_RESTORE(CM_AUTOIDLE_DSP);
- OMAP24XX_RESTORE(CM_AUTOIDLE_MDM);
-
- /* Restore clock registers */
- OMAP24XX_RESTORE(CM_FCLKEN1_CORE);
- OMAP24XX_RESTORE(CM_FCLKEN2_CORE);
- OMAP24XX_RESTORE(CM_ICLKEN1_CORE);
- OMAP24XX_RESTORE(CM_ICLKEN2_CORE);
- OMAP24XX_RESTORE(CM_ICLKEN3_CORE);
- OMAP24XX_RESTORE(CM_ICLKEN4_CORE);
-
- /* REVISIT: Clear interrupts here */
-
- /* Restore interrupt registers */
- OMAP24XX_RESTORE(INTC_MIR0);
- OMAP24XX_RESTORE(INTC_MIR1);
- OMAP24XX_RESTORE(INTC_MIR2);
-}
-
static int omap2_pm_suspend(void)
{
- int processor_type = 0;
-
- /* REVISIT: 0x21 or 0x26? */
- if (cpu_is_omap2420())
- processor_type = 0x21;
-
- if (!processor_type)
- return -ENOTSUPP;
-
- local_irq_disable();
- local_fiq_disable();
-
- omap2_pm_save_registers();
-
- /* Disable interrupts except for the wake events */
- INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK;
- INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK;
- INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK;
-
- pmdomain_set_autoidle();
-
- /* Clear old wake-up events */
- PM_WKST1_CORE = 0;
- PM_WKST2_CORE = 0;
- PM_WKST_WKUP = 0;
-
- /* Enable wake-up events */
- PM_WKEN1_CORE = (1 << 22) | (1 << 21); /* UART1 & 2 */
- PM_WKEN2_CORE = (1 << 2); /* UART3 */
- PM_WKEN_WKUP = (1 << 2) | (1 << 0); /* GPIO & GPT1 */
-
- /* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled
- * in the SRAM suspend code */
- CM_FCLKEN1_CORE = 0;
- CM_FCLKEN2_CORE = 0;
- CM_ICLKEN1_CORE = 0;
- CM_ICLKEN3_CORE = 0;
- CM_ICLKEN4_CORE = 0;
-
- omap2_pm_debug("Status before suspend");
-
- /* Must wait for serial buffers to clear */
- mdelay(200);
-
- /* Jump to SRAM suspend code
- * REVISIT: When is this SDRC_DLLB_CTRL?
- */
- omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type);
-
- /* Back from sleep */
- omap2_pm_restore_registers();
-
- local_fiq_enable();
- local_irq_enable();
-
return 0;
}
int __init omap2_pm_init(void)
{
- printk("Power Management for TI OMAP.\n");
-
- vclk = clk_get(NULL, "virt_prcm_set");
- if (IS_ERR(vclk)) {
- printk(KERN_ERR "Could not get PM vclk\n");
- return -ENODEV;
- }
-
- /*
- * We copy the assembler sleep/wakeup routines to SRAM.
- * These routines need to be in SRAM as that's the only
- * memory the MPU can see when it wakes up.
- */
- omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
- omap24xx_idle_loop_suspend_sz);
-
- omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
- omap24xx_cpu_suspend_sz);
-
- suspend_set_ops(&omap_pm_ops);
- pm_idle = omap2_pm_idle;
-
- pmdomain_init();
-
return 0;
}
--- /dev/null
+#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+
+/*
+ * OMAP2/3 PRCM base and module definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* Module offsets from both CM_BASE & PRM_BASE */
+
+/*
+ * Offsets that are the same on 24xx and 34xx
+ *
+ * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
+ * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
+ */
+#define OCP_MOD 0x000
+#define MPU_MOD 0x100
+#define CORE_MOD 0x200
+#define GFX_MOD 0x300
+#define WKUP_MOD 0x400
+#define PLL_MOD 0x500
+
+
+/* Chip-specific module offsets */
+#define OMAP24XX_DSP_MOD 0x800
+
+#define OMAP2430_MDM_MOD 0xc00
+
+/* IVA2 module is < base on 3430 */
+#define OMAP3430_IVA2_MOD -0x800
+#define OMAP3430ES2_SGX_MOD GFX_MOD
+#define OMAP3430_CCR_MOD PLL_MOD
+#define OMAP3430_DSS_MOD 0x600
+#define OMAP3430_CAM_MOD 0x700
+#define OMAP3430_PER_MOD 0x800
+#define OMAP3430_EMU_MOD 0x900
+#define OMAP3430_GR_MOD 0xa00
+#define OMAP3430_NEON_MOD 0xb00
+#define OMAP3430ES2_USBHOST_MOD 0xc00
+
+
+/* 24XX register bits shared between CM & PRM registers */
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP2420_EN_MMC_SHIFT 26
+#define OMAP2420_EN_MMC (1 << 26)
+#define OMAP24XX_EN_UART2_SHIFT 22
+#define OMAP24XX_EN_UART2 (1 << 22)
+#define OMAP24XX_EN_UART1_SHIFT 21
+#define OMAP24XX_EN_UART1 (1 << 21)
+#define OMAP24XX_EN_MCSPI2_SHIFT 18
+#define OMAP24XX_EN_MCSPI2 (1 << 18)
+#define OMAP24XX_EN_MCSPI1_SHIFT 17
+#define OMAP24XX_EN_MCSPI1 (1 << 17)
+#define OMAP24XX_EN_MCBSP2_SHIFT 16
+#define OMAP24XX_EN_MCBSP2 (1 << 16)
+#define OMAP24XX_EN_MCBSP1_SHIFT 15
+#define OMAP24XX_EN_MCBSP1 (1 << 15)
+#define OMAP24XX_EN_GPT12_SHIFT 14
+#define OMAP24XX_EN_GPT12 (1 << 14)
+#define OMAP24XX_EN_GPT11_SHIFT 13
+#define OMAP24XX_EN_GPT11 (1 << 13)
+#define OMAP24XX_EN_GPT10_SHIFT 12
+#define OMAP24XX_EN_GPT10 (1 << 12)
+#define OMAP24XX_EN_GPT9_SHIFT 11
+#define OMAP24XX_EN_GPT9 (1 << 11)
+#define OMAP24XX_EN_GPT8_SHIFT 10
+#define OMAP24XX_EN_GPT8 (1 << 10)
+#define OMAP24XX_EN_GPT7_SHIFT 9
+#define OMAP24XX_EN_GPT7 (1 << 9)
+#define OMAP24XX_EN_GPT6_SHIFT 8
+#define OMAP24XX_EN_GPT6 (1 << 8)
+#define OMAP24XX_EN_GPT5_SHIFT 7
+#define OMAP24XX_EN_GPT5 (1 << 7)
+#define OMAP24XX_EN_GPT4_SHIFT 6
+#define OMAP24XX_EN_GPT4 (1 << 6)
+#define OMAP24XX_EN_GPT3_SHIFT 5
+#define OMAP24XX_EN_GPT3 (1 << 5)
+#define OMAP24XX_EN_GPT2_SHIFT 4
+#define OMAP24XX_EN_GPT2 (1 << 4)
+#define OMAP2420_EN_VLYNQ_SHIFT 3
+#define OMAP2420_EN_VLYNQ (1 << 3)
+
+/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_GPIO5_SHIFT 10
+#define OMAP2430_EN_GPIO5 (1 << 10)
+#define OMAP2430_EN_MCSPI3_SHIFT 9
+#define OMAP2430_EN_MCSPI3 (1 << 9)
+#define OMAP2430_EN_MMCHS2_SHIFT 8
+#define OMAP2430_EN_MMCHS2 (1 << 8)
+#define OMAP2430_EN_MMCHS1_SHIFT 7
+#define OMAP2430_EN_MMCHS1 (1 << 7)
+#define OMAP24XX_EN_UART3_SHIFT 2
+#define OMAP24XX_EN_UART3 (1 << 2)
+#define OMAP24XX_EN_USB_SHIFT 0
+#define OMAP24XX_EN_USB (1 << 0)
+
+/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_MDM_INTC_SHIFT 11
+#define OMAP2430_EN_MDM_INTC (1 << 11)
+#define OMAP2430_EN_USBHS_SHIFT 6
+#define OMAP2430_EN_USBHS (1 << 6)
+
+/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
+#define OMAP2420_ST_MMC (1 << 26)
+#define OMAP24XX_ST_UART2 (1 << 22)
+#define OMAP24XX_ST_UART1 (1 << 21)
+#define OMAP24XX_ST_MCSPI2 (1 << 18)
+#define OMAP24XX_ST_MCSPI1 (1 << 17)
+#define OMAP24XX_ST_GPT12 (1 << 14)
+#define OMAP24XX_ST_GPT11 (1 << 13)
+#define OMAP24XX_ST_GPT10 (1 << 12)
+#define OMAP24XX_ST_GPT9 (1 << 11)
+#define OMAP24XX_ST_GPT8 (1 << 10)
+#define OMAP24XX_ST_GPT7 (1 << 9)
+#define OMAP24XX_ST_GPT6 (1 << 8)
+#define OMAP24XX_ST_GPT5 (1 << 7)
+#define OMAP24XX_ST_GPT4 (1 << 6)
+#define OMAP24XX_ST_GPT3 (1 << 5)
+#define OMAP24XX_ST_GPT2 (1 << 4)
+#define OMAP2420_ST_VLYNQ (1 << 3)
+
+/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
+#define OMAP2430_ST_MDM_INTC (1 << 11)
+#define OMAP2430_ST_GPIO5 (1 << 10)
+#define OMAP2430_ST_MCSPI3 (1 << 9)
+#define OMAP2430_ST_MMCHS2 (1 << 8)
+#define OMAP2430_ST_MMCHS1 (1 << 7)
+#define OMAP2430_ST_USBHS (1 << 6)
+#define OMAP24XX_ST_UART3 (1 << 2)
+#define OMAP24XX_ST_USB (1 << 0)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP24XX_EN_GPIOS_SHIFT 2
+#define OMAP24XX_EN_GPIOS (1 << 2)
+#define OMAP24XX_EN_GPT1_SHIFT 0
+#define OMAP24XX_EN_GPT1 (1 << 0)
+
+/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
+#define OMAP24XX_ST_GPIOS (1 << 2)
+#define OMAP24XX_ST_GPT1 (1 << 0)
+
+/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
+#define OMAP2430_ST_MDM (1 << 0)
+
+
+/* 3430 register bits shared between CM & PRM registers */
+
+/* CM_REVISION, PRM_REVISION shared bits */
+#define OMAP3430_REV_SHIFT 0
+#define OMAP3430_REV_MASK (0xff << 0)
+
+/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
+#define OMAP3430_AUTOIDLE (1 << 0)
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_MMC2 (1 << 25)
+#define OMAP3430_EN_MMC2_SHIFT 25
+#define OMAP3430_EN_MMC1 (1 << 24)
+#define OMAP3430_EN_MMC1_SHIFT 24
+#define OMAP3430_EN_MCSPI4 (1 << 21)
+#define OMAP3430_EN_MCSPI4_SHIFT 21
+#define OMAP3430_EN_MCSPI3 (1 << 20)
+#define OMAP3430_EN_MCSPI3_SHIFT 20
+#define OMAP3430_EN_MCSPI2 (1 << 19)
+#define OMAP3430_EN_MCSPI2_SHIFT 19
+#define OMAP3430_EN_MCSPI1 (1 << 18)
+#define OMAP3430_EN_MCSPI1_SHIFT 18
+#define OMAP3430_EN_I2C3 (1 << 17)
+#define OMAP3430_EN_I2C3_SHIFT 17
+#define OMAP3430_EN_I2C2 (1 << 16)
+#define OMAP3430_EN_I2C2_SHIFT 16
+#define OMAP3430_EN_I2C1 (1 << 15)
+#define OMAP3430_EN_I2C1_SHIFT 15
+#define OMAP3430_EN_UART2 (1 << 14)
+#define OMAP3430_EN_UART2_SHIFT 14
+#define OMAP3430_EN_UART1 (1 << 13)
+#define OMAP3430_EN_UART1_SHIFT 13
+#define OMAP3430_EN_GPT11 (1 << 12)
+#define OMAP3430_EN_GPT11_SHIFT 12
+#define OMAP3430_EN_GPT10 (1 << 11)
+#define OMAP3430_EN_GPT10_SHIFT 11
+#define OMAP3430_EN_MCBSP5 (1 << 10)
+#define OMAP3430_EN_MCBSP5_SHIFT 10
+#define OMAP3430_EN_MCBSP1 (1 << 9)
+#define OMAP3430_EN_MCBSP1_SHIFT 9
+#define OMAP3430_EN_FSHOSTUSB (1 << 5)
+#define OMAP3430_EN_FSHOSTUSB_SHIFT 5
+#define OMAP3430_EN_D2D (1 << 3)
+#define OMAP3430_EN_D2D_SHIFT 3
+
+/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_HSOTGUSB (1 << 4)
+#define OMAP3430_EN_HSOTGUSB_SHIFT 4
+
+/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+#define OMAP3430_ST_MMC2 (1 << 25)
+#define OMAP3430_ST_MMC1 (1 << 24)
+#define OMAP3430_ST_MCSPI4 (1 << 21)
+#define OMAP3430_ST_MCSPI3 (1 << 20)
+#define OMAP3430_ST_MCSPI2 (1 << 19)
+#define OMAP3430_ST_MCSPI1 (1 << 18)
+#define OMAP3430_ST_I2C3 (1 << 17)
+#define OMAP3430_ST_I2C2 (1 << 16)
+#define OMAP3430_ST_I2C1 (1 << 15)
+#define OMAP3430_ST_UART2 (1 << 14)
+#define OMAP3430_ST_UART1 (1 << 13)
+#define OMAP3430_ST_GPT11 (1 << 12)
+#define OMAP3430_ST_GPT10 (1 << 11)
+#define OMAP3430_ST_MCBSP5 (1 << 10)
+#define OMAP3430_ST_MCBSP1 (1 << 9)
+#define OMAP3430_ST_FSHOSTUSB (1 << 5)
+#define OMAP3430_ST_HSOTGUSB (1 << 4)
+#define OMAP3430_ST_D2D (1 << 3)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPIO1 (1 << 3)
+#define OMAP3430_EN_GPIO1_SHIFT 3
+#define OMAP3430_EN_GPT1 (1 << 0)
+#define OMAP3430_EN_GPT1_SHIFT 0
+
+/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_SR2 (1 << 7)
+#define OMAP3430_EN_SR2_SHIFT 7
+#define OMAP3430_EN_SR1 (1 << 6)
+#define OMAP3430_EN_SR1_SHIFT 6
+
+/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPT12 (1 << 1)
+#define OMAP3430_EN_GPT12_SHIFT 1
+
+/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
+#define OMAP3430_ST_SR2 (1 << 7)
+#define OMAP3430_ST_SR1 (1 << 6)
+#define OMAP3430_ST_GPIO1 (1 << 3)
+#define OMAP3430_ST_GPT12 (1 << 1)
+#define OMAP3430_ST_GPT1 (1 << 0)
+
+/*
+ * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
+ * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
+ * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
+ */
+#define OMAP3430_EN_MPU (1 << 1)
+#define OMAP3430_EN_MPU_SHIFT 1
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+#define OMAP3430_EN_GPIO6 (1 << 17)
+#define OMAP3430_EN_GPIO6_SHIFT 17
+#define OMAP3430_EN_GPIO5 (1 << 16)
+#define OMAP3430_EN_GPIO5_SHIFT 16
+#define OMAP3430_EN_GPIO4 (1 << 15)
+#define OMAP3430_EN_GPIO4_SHIFT 15
+#define OMAP3430_EN_GPIO3 (1 << 14)
+#define OMAP3430_EN_GPIO3_SHIFT 14
+#define OMAP3430_EN_GPIO2 (1 << 13)
+#define OMAP3430_EN_GPIO2_SHIFT 13
+#define OMAP3430_EN_UART3 (1 << 11)
+#define OMAP3430_EN_UART3_SHIFT 11
+#define OMAP3430_EN_GPT9 (1 << 10)
+#define OMAP3430_EN_GPT9_SHIFT 10
+#define OMAP3430_EN_GPT8 (1 << 9)
+#define OMAP3430_EN_GPT8_SHIFT 9
+#define OMAP3430_EN_GPT7 (1 << 8)
+#define OMAP3430_EN_GPT7_SHIFT 8
+#define OMAP3430_EN_GPT6 (1 << 7)
+#define OMAP3430_EN_GPT6_SHIFT 7
+#define OMAP3430_EN_GPT5 (1 << 6)
+#define OMAP3430_EN_GPT5_SHIFT 6
+#define OMAP3430_EN_GPT4 (1 << 5)
+#define OMAP3430_EN_GPT4_SHIFT 5
+#define OMAP3430_EN_GPT3 (1 << 4)
+#define OMAP3430_EN_GPT3_SHIFT 4
+#define OMAP3430_EN_GPT2 (1 << 3)
+#define OMAP3430_EN_GPT2_SHIFT 3
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
+/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
+ * be ST_* bits instead? */
+#define OMAP3430_EN_MCBSP4 (1 << 2)
+#define OMAP3430_EN_MCBSP4_SHIFT 2
+#define OMAP3430_EN_MCBSP3 (1 << 1)
+#define OMAP3430_EN_MCBSP3_SHIFT 1
+#define OMAP3430_EN_MCBSP2 (1 << 0)
+#define OMAP3430_EN_MCBSP2_SHIFT 0
+
+/* CM_IDLEST_PER, PM_WKST_PER shared bits */
+#define OMAP3430_ST_GPIO6 (1 << 17)
+#define OMAP3430_ST_GPIO5 (1 << 16)
+#define OMAP3430_ST_GPIO4 (1 << 15)
+#define OMAP3430_ST_GPIO3 (1 << 14)
+#define OMAP3430_ST_GPIO2 (1 << 13)
+#define OMAP3430_ST_UART3 (1 << 11)
+#define OMAP3430_ST_GPT9 (1 << 10)
+#define OMAP3430_ST_GPT8 (1 << 9)
+#define OMAP3430_ST_GPT7 (1 << 8)
+#define OMAP3430_ST_GPT6 (1 << 7)
+#define OMAP3430_ST_GPT5 (1 << 6)
+#define OMAP3430_ST_GPT4 (1 << 5)
+#define OMAP3430_ST_GPT3 (1 << 4)
+#define OMAP3430_ST_GPT2 (1 << 3)
+
+/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
+#define OMAP3430_EN_CORE (1 << 0)
+
+#endif
+
+++ /dev/null
-/*
- * linux/arch/arm/mach-omap2/prcm-regs.h
- *
- * OMAP24XX Power Reset and Clock Management (PRCM) registers
- *
- * Copyright (C) 2005 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
-#define __ARCH_ARM_MACH_OMAP2_PRCM_H
-
-/* SET_PERFORMANCE_LEVEL PARAMETERS */
-#define PRCM_HALF_SPEED 1
-#define PRCM_FULL_SPEED 2
-
-#ifndef __ASSEMBLER__
-
-#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
-
-#define PRCM_REVISION PRCM_REG32(0x000)
-#define PRCM_SYSCONFIG PRCM_REG32(0x010)
-#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
-#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
-#define PRCM_VOLTCTRL PRCM_REG32(0x050)
-#define PRCM_VOLTST PRCM_REG32(0x054)
-#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
-#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
-#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
-#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
-#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
-#define PRCM_VOLTSETUP PRCM_REG32(0x090)
-#define PRCM_CLKSSETUP PRCM_REG32(0x094)
-#define PRCM_POLCTRL PRCM_REG32(0x098)
-
-/* GENERAL PURPOSE */
-#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
-#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
-#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
-#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
-#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
-#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
-#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
-#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
-#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
-#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
-#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
-#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
-#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
-#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
-#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
-#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
-#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
-#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
-#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
-#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
-
-/* MPU */
-#define CM_CLKSEL_MPU PRCM_REG32(0x140)
-#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
-#define RM_RSTST_MPU PRCM_REG32(0x158)
-#define PM_WKDEP_MPU PRCM_REG32(0x1C8)
-#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
-#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
-#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
-#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
-#define PM_PWSTST_MPU PRCM_REG32(0x1E4)
-
-/* CORE */
-#define CM_FCLKEN1_CORE PRCM_REG32(0x200)
-#define CM_FCLKEN2_CORE PRCM_REG32(0x204)
-#define CM_FCLKEN3_CORE PRCM_REG32(0x208)
-#define CM_ICLKEN1_CORE PRCM_REG32(0x210)
-#define CM_ICLKEN2_CORE PRCM_REG32(0x214)
-#define CM_ICLKEN3_CORE PRCM_REG32(0x218)
-#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
-#define CM_IDLEST1_CORE PRCM_REG32(0x220)
-#define CM_IDLEST2_CORE PRCM_REG32(0x224)
-#define CM_IDLEST3_CORE PRCM_REG32(0x228)
-#define CM_IDLEST4_CORE PRCM_REG32(0x22C)
-#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
-#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
-#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
-#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
-#define CM_CLKSEL1_CORE PRCM_REG32(0x240)
-#define CM_CLKSEL2_CORE PRCM_REG32(0x244)
-#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
-#define PM_WKEN1_CORE PRCM_REG32(0x2A0)
-#define PM_WKEN2_CORE PRCM_REG32(0x2A4)
-#define PM_WKST1_CORE PRCM_REG32(0x2B0)
-#define PM_WKST2_CORE PRCM_REG32(0x2B4)
-#define PM_WKDEP_CORE PRCM_REG32(0x2C8)
-#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
-#define PM_PWSTST_CORE PRCM_REG32(0x2E4)
-
-/* GFX */
-#define CM_FCLKEN_GFX PRCM_REG32(0x300)
-#define CM_ICLKEN_GFX PRCM_REG32(0x310)
-#define CM_IDLEST_GFX PRCM_REG32(0x320)
-#define CM_CLKSEL_GFX PRCM_REG32(0x340)
-#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
-#define RM_RSTCTRL_GFX PRCM_REG32(0x350)
-#define RM_RSTST_GFX PRCM_REG32(0x358)
-#define PM_WKDEP_GFX PRCM_REG32(0x3C8)
-#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
-#define PM_PWSTST_GFX PRCM_REG32(0x3E4)
-
-/* WAKE-UP */
-#define CM_FCLKEN_WKUP PRCM_REG32(0x400)
-#define CM_ICLKEN_WKUP PRCM_REG32(0x410)
-#define CM_IDLEST_WKUP PRCM_REG32(0x420)
-#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
-#define CM_CLKSEL_WKUP PRCM_REG32(0x440)
-#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
-#define RM_RSTTIME_WKUP PRCM_REG32(0x454)
-#define RM_RSTST_WKUP PRCM_REG32(0x458)
-#define PM_WKEN_WKUP PRCM_REG32(0x4A0)
-#define PM_WKST_WKUP PRCM_REG32(0x4B0)
-
-/* CLOCKS */
-#define CM_CLKEN_PLL PRCM_REG32(0x500)
-#define CM_IDLEST_CKGEN PRCM_REG32(0x520)
-#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
-#define CM_CLKSEL1_PLL PRCM_REG32(0x540)
-#define CM_CLKSEL2_PLL PRCM_REG32(0x544)
-
-/* DSP */
-#define CM_FCLKEN_DSP PRCM_REG32(0x800)
-#define CM_ICLKEN_DSP PRCM_REG32(0x810)
-#define CM_IDLEST_DSP PRCM_REG32(0x820)
-#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
-#define CM_CLKSEL_DSP PRCM_REG32(0x840)
-#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
-#define RM_RSTCTRL_DSP PRCM_REG32(0x850)
-#define RM_RSTST_DSP PRCM_REG32(0x858)
-#define PM_WKEN_DSP PRCM_REG32(0x8A0)
-#define PM_WKDEP_DSP PRCM_REG32(0x8C8)
-#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
-#define PM_PWSTST_DSP PRCM_REG32(0x8E4)
-#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
-#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
-
-/* IVA */
-#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
-#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
-
-/* Modem on 2430 */
-#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
-#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
-#define CM_IDLEST_MDM PRCM_REG32(0xC20)
-#define CM_AUTOIDLE_MDM PRCM_REG32(0xC30)
-#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
-#define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48)
-#define RM_RSTCTRL_MDM PRCM_REG32(0xC50)
-#define RM_RSTST_MDM PRCM_REG32(0xC58)
-#define PM_WKEN_MDM PRCM_REG32(0xCA0)
-#define PM_WKST_MDM PRCM_REG32(0xCB0)
-#define PM_WKDEP_MDM PRCM_REG32(0xCC8)
-#define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0)
-#define PM_PWSTST_MDM PRCM_REG32(0xCE4)
-
-#define OMAP24XX_L4_IO_BASE 0x48000000
-
-#define DISP_BASE (OMAP24XX_L4_IO_BASE + 0x50000)
-#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
-
-#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
-#define GPMC_REG32(offset) __REG32(OMAP24XX_GPMC_BASE + (offset))
-
-/* FIXME: Move these to timer code */
-#define GPT1_BASE (0x48028000)
-#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
-
-/* Misc sysconfig */
-#define DISPC_SYSCONFIG DISP_REG32(0x410)
-#define SPI_BASE (OMAP24XX_L4_IO_BASE + 0x98000)
-#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
-#define MCSPI2_SYSCONFIG __REG32(SPI_BASE + 0x2000 + 0x10)
-#define MCSPI3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0xb8010)
-
-#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE + 0x2C10)
-#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE + 0x282C)
-#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE + 0x602C)
-#define GPMC_SYSCONFIG GPMC_REG32(0x010)
-#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x94010)
-#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6A054)
-#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6C054)
-#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6E054)
-#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE + 0x10)
-#define OMAP24XX_SMS_BASE (L3_24XX_BASE + 0x8000)
-#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE + 0x10)
-#define SSI_SYSCONFIG __REG32(DISP_BASE + 0x8010)
-
-/* rkw - good cannidates for PM_ to start what nm was trying */
-#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE + 0x2A000)
-#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE + 0x78000)
-#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE + 0x7A000)
-#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE + 0x7C000)
-#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE + 0x7E000)
-#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE + 0x80000)
-#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE + 0x82000)
-#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE + 0x84000)
-#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE + 0x86000)
-#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE + 0x88000)
-#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE + 0x8A000)
-
-/* FIXME: Move these to timer code */
-#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
-#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
-#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
-#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10)
-#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10)
-#define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10)
-#define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10)
-#define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10)
-#define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10)
-#define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10)
-#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
-#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
-
-/* FIXME: Move these to gpio code */
-#define OMAP24XX_GPIO_BASE 0x48018000
-#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1)))
-
-#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1) + 0x10))
-#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2) + 0x10))
-#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3) + 0x10))
-#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4) + 0x10))
-
-#if defined(CONFIG_ARCH_OMAP243X)
-#define GPIO5_SYSCONFIG __REG32((OMAP24XX_GPIO5_BASE + 0x10))
-#endif
-
-/* GP TIMER 1 */
-#define GPTIMER1_TISTAT GPT1_REG32(0x014)
-#define GPTIMER1_TISR GPT1_REG32(0x018)
-#define GPTIMER1_TIER GPT1_REG32(0x01C)
-#define GPTIMER1_TWER GPT1_REG32(0x020)
-#define GPTIMER1_TCLR GPT1_REG32(0x024)
-#define GPTIMER1_TCRR GPT1_REG32(0x028)
-#define GPTIMER1_TLDR GPT1_REG32(0x02C)
-#define GPTIMER1_TTGR GPT1_REG32(0x030)
-#define GPTIMER1_TWPS GPT1_REG32(0x034)
-#define GPTIMER1_TMAR GPT1_REG32(0x038)
-#define GPTIMER1_TCAR1 GPT1_REG32(0x03C)
-#define GPTIMER1_TSICR GPT1_REG32(0x040)
-#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
-
-/* rkw -- base fix up please... */
-#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
-
-/* SDRC */
-#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064)
-#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068)
-#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C)
-#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070)
-#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084)
-
-/* GPIO 1 */
-#define GPIO1_BASE GPIOX_BASE(1)
-#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
-#define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C)
-#define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018)
-#define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C)
-#define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028)
-#define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020)
-#define GPIO1_RISINGDETECT GPIO1_REG32(0x048)
-#define GPIO1_DATAIN GPIO1_REG32(0x038)
-#define GPIO1_OE GPIO1_REG32(0x034)
-#define GPIO1_DATAOUT GPIO1_REG32(0x03C)
-
-/* GPIO2 */
-#define GPIO2_BASE GPIOX_BASE(2)
-#define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset))
-#define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C)
-#define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018)
-#define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C)
-#define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028)
-#define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020)
-#define GPIO2_RISINGDETECT GPIO2_REG32(0x048)
-#define GPIO2_DATAIN GPIO2_REG32(0x038)
-#define GPIO2_OE GPIO2_REG32(0x034)
-#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
-#define GPIO2_DEBOUNCENABLE GPIO2_REG32(0x050)
-#define GPIO2_DEBOUNCINGTIME GPIO2_REG32(0x054)
-
-/* GPIO 3 */
-#define GPIO3_BASE GPIOX_BASE(3)
-#define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset))
-#define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C)
-#define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018)
-#define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C)
-#define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028)
-#define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020)
-#define GPIO3_RISINGDETECT GPIO3_REG32(0x048)
-#define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C)
-#define GPIO3_DATAIN GPIO3_REG32(0x038)
-#define GPIO3_OE GPIO3_REG32(0x034)
-#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
-#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
-#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
-#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
-#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
-
-/* GPIO 4 */
-#define GPIO4_BASE GPIOX_BASE(4)
-#define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset))
-#define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C)
-#define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018)
-#define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C)
-#define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028)
-#define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020)
-#define GPIO4_RISINGDETECT GPIO4_REG32(0x048)
-#define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C)
-#define GPIO4_DATAIN GPIO4_REG32(0x038)
-#define GPIO4_OE GPIO4_REG32(0x034)
-#define GPIO4_DATAOUT GPIO4_REG32(0x03C)
-#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
-#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
-
-#if defined(CONFIG_ARCH_OMAP243X)
-/* GPIO 5 */
-#define GPIO5_REG32(offset) __REG32((OMAP24XX_GPIO5_BASE + (offset)))
-#define GPIO5_IRQENABLE1 GPIO5_REG32(0x01C)
-#define GPIO5_IRQSTATUS1 GPIO5_REG32(0x018)
-#define GPIO5_IRQENABLE2 GPIO5_REG32(0x02C)
-#define GPIO5_IRQSTATUS2 GPIO5_REG32(0x028)
-#define GPIO5_WAKEUPENABLE GPIO5_REG32(0x020)
-#define GPIO5_RISINGDETECT GPIO5_REG32(0x048)
-#define GPIO5_FALLINGDETECT GPIO5_REG32(0x04C)
-#define GPIO5_DATAIN GPIO5_REG32(0x038)
-#define GPIO5_OE GPIO5_REG32(0x034)
-#define GPIO5_DATAOUT GPIO5_REG32(0x03C)
-#define GPIO5_DEBOUNCENABLE GPIO5_REG32(0x050)
-#define GPIO5_DEBOUNCINGTIME GPIO5_REG32(0x054)
-#endif
-
-/* IO CONFIG */
-#define OMAP24XX_CTRL_BASE (L4_24XX_BASE)
-#define CONTROL_REG32(offset) __REG32(OMAP24XX_CTRL_BASE + (offset))
-
-#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
-#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
-#define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8)
-#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
-#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
-#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
-#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) /* 2420 */
-#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
-#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
-#define CONTROL_PADCONF_SYS_NIRQW0 CONTROL_REG32(0x0BC) /* 2430 */
-#define CONTROL_PADCONF_SSI1_FLAG_TX CONTROL_REG32(0x108) /* 2430 */
-
-/* CONTROL */
-#define CONTROL_DEVCONF CONTROL_REG32(0x274)
-#define CONTROL_DEVCONF1 CONTROL_REG32(0x2E8)
-
-/* INTERRUPT CONTROLLER */
-#define INTC_BASE ((L4_24XX_BASE) + 0xfe000)
-#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
-
-#define INTC1_U_BASE INTC_REG32(0x000)
-#define INTC_MIR0 INTC_REG32(0x084)
-#define INTC_MIR_SET0 INTC_REG32(0x08C)
-#define INTC_MIR_CLEAR0 INTC_REG32(0x088)
-#define INTC_ISR_CLEAR0 INTC_REG32(0x094)
-#define INTC_MIR1 INTC_REG32(0x0A4)
-#define INTC_MIR_SET1 INTC_REG32(0x0AC)
-#define INTC_MIR_CLEAR1 INTC_REG32(0x0A8)
-#define INTC_ISR_CLEAR1 INTC_REG32(0x0B4)
-#define INTC_MIR2 INTC_REG32(0x0C4)
-#define INTC_MIR_SET2 INTC_REG32(0x0CC)
-#define INTC_MIR_CLEAR2 INTC_REG32(0x0C8)
-#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
-#define INTC_SIR_IRQ INTC_REG32(0x040)
-#define INTC_CONTROL INTC_REG32(0x048)
-#define INTC_ILR11 INTC_REG32(0x12C) /* PRCM on MPU PIC */
-#define INTC_ILR30 INTC_REG32(0x178)
-#define INTC_ILR31 INTC_REG32(0x17C)
-#define INTC_ILR32 INTC_REG32(0x180)
-#define INTC_ILR37 INTC_REG32(0x194) /* GPIO4 on MPU PIC */
-#define INTC_SYSCONFIG INTC_REG32(0x010) /* GPT1 on MPU PIC */
-
-/* RAM FIREWALL */
-#define RAMFW_BASE (0x68005000)
-#define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset))
-
-#define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048)
-#define RAMFW_READPERM0 RAMFW_REG32(0x050)
-#define RAMFW_WRITEPERM0 RAMFW_REG32(0x058)
-
-/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
-//#define DEBUG_BOARD_LED_REGISTER 0x04000014
-
-/* GPMC CS0 */
-#define GPMC_CONFIG1_0 GPMC_REG32(0x060)
-#define GPMC_CONFIG2_0 GPMC_REG32(0x064)
-#define GPMC_CONFIG3_0 GPMC_REG32(0x068)
-#define GPMC_CONFIG4_0 GPMC_REG32(0x06C)
-#define GPMC_CONFIG5_0 GPMC_REG32(0x070)
-#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
-#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
-
-/* GPMC CS1 */
-#define GPMC_CONFIG1_1 GPMC_REG32(0x090)
-#define GPMC_CONFIG2_1 GPMC_REG32(0x094)
-#define GPMC_CONFIG3_1 GPMC_REG32(0x098)
-#define GPMC_CONFIG4_1 GPMC_REG32(0x09C)
-#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0)
-#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4)
-#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8)
-
-/* GPMC CS3 */
-#define GPMC_CONFIG1_3 GPMC_REG32(0x0F0)
-#define GPMC_CONFIG2_3 GPMC_REG32(0x0F4)
-#define GPMC_CONFIG3_3 GPMC_REG32(0x0F8)
-#define GPMC_CONFIG4_3 GPMC_REG32(0x0FC)
-#define GPMC_CONFIG5_3 GPMC_REG32(0x100)
-#define GPMC_CONFIG6_3 GPMC_REG32(0x104)
-#define GPMC_CONFIG7_3 GPMC_REG32(0x108)
-
-/* DSS */
-#define DSS_CONTROL DISP_REG32(0x040)
-#define DISPC_CONTROL DISP_REG32(0x440)
-#define DISPC_SYSSTATUS DISP_REG32(0x414)
-#define DISPC_IRQSTATUS DISP_REG32(0x418)
-#define DISPC_IRQENABLE DISP_REG32(0x41C)
-#define DISPC_CONFIG DISP_REG32(0x444)
-#define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C)
-#define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450)
-#define DISPC_TRANS_COLOR0 DISP_REG32(0x454)
-#define DISPC_TRANS_COLOR1 DISP_REG32(0x458)
-#define DISPC_LINE_NUMBER DISP_REG32(0x460)
-#define DISPC_TIMING_H DISP_REG32(0x464)
-#define DISPC_TIMING_V DISP_REG32(0x468)
-#define DISPC_POL_FREQ DISP_REG32(0x46C)
-#define DISPC_DIVISOR DISP_REG32(0x470)
-#define DISPC_SIZE_DIG DISP_REG32(0x478)
-#define DISPC_SIZE_LCD DISP_REG32(0x47C)
-#define DISPC_GFX_BA0 DISP_REG32(0x480)
-#define DISPC_GFX_BA1 DISP_REG32(0x484)
-#define DISPC_GFX_POSITION DISP_REG32(0x488)
-#define DISPC_GFX_SIZE DISP_REG32(0x48C)
-#define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0)
-#define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4)
-#define DISPC_GFX_ROW_INC DISP_REG32(0x4AC)
-#define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0)
-#define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4)
-#define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8)
-#define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4)
-#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
-#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
-
-/* HSUSB Suspend */
-#define HSUSB_CTRL __REG8(0x480AC001)
-#define USBOTG_POWER __REG32(0x480AC000)
-
-/* HS MMC */
-#define MMCHS1_SYSCONFIG __REG32(0x4809C010)
-#define MMCHS2_SYSCONFIG __REG32(0x480b4010)
-
-#endif /* __ASSEMBLER__ */
-
-#endif
-
-
-
-
-
#include <linux/init.h>
#include <linux/clk.h>
-#include "prcm-regs.h"
+#include <asm/io.h>
+
+#include "prm.h"
+#include "prm-regbits-24xx.h"
extern void omap2_clk_prepare_for_reboot(void);
u32 omap_prcm_get_reset_sources(void)
{
- return RM_RSTST_WKUP & 0x7f;
+ return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
}
EXPORT_SYMBOL(omap_prcm_get_reset_sources);
/* Resets clock rates and reboots the system. Only called from system.h */
void omap_prcm_arch_reset(char mode)
{
+ u32 wkup;
omap2_clk_prepare_for_reboot();
- RM_RSTCTRL_WKUP |= 2;
+
+ if (cpu_is_omap24xx()) {
+ wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3;
+ prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
+ }
}
--- /dev/null
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Power/Reset Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Bits shared between registers */
+
+/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_ST (1 << 2)
+#define OMAP24XX_WKUP2_ST (1 << 1)
+#define OMAP24XX_WKUP1_ST (1 << 0)
+
+/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_EN (1 << 2)
+#define OMAP24XX_WKUP2_EN (1 << 1)
+#define OMAP24XX_WKUP1_EN (1 << 0)
+
+/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
+#define OMAP24XX_EN_MPU (1 << 1)
+#define OMAP24XX_EN_CORE (1 << 0)
+
+/*
+ * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
+ * shared bits
+ */
+#define OMAP24XX_MEMONSTATE_SHIFT 10
+#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
+#define OMAP24XX_MEMRETSTATE (1 << 3)
+
+/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
+#define OMAP24XX_FORCESTATE (1 << 18)
+
+/*
+ * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
+ * PM_PWSTST_MDM shared bits
+ */
+#define OMAP24XX_CLKACTIVITY (1 << 19)
+
+/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
+#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
+#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4)
+
+/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
+#define OMAP2430_MEMSTATEST_SHIFT 10
+#define OMAP2430_MEMSTATEST_MASK (0x3 << 10)
+
+/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
+#define OMAP24XX_POWERSTATEST_SHIFT 0
+#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0)
+
+
+/* Bits specific to each register */
+
+/* PRCM_REVISION */
+#define OMAP24XX_REV_SHIFT 0
+#define OMAP24XX_REV_MASK (0xff << 0)
+
+/* PRCM_SYSCONFIG */
+#define OMAP24XX_AUTOIDLE (1 << 0)
+
+/* PRCM_IRQSTATUS_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_ST (1 << 6)
+#define OMAP24XX_TRANSITION_ST (1 << 5)
+#define OMAP24XX_EVGENOFF_ST (1 << 4)
+#define OMAP24XX_EVGENON_ST (1 << 3)
+
+/* PRCM_IRQENABLE_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_EN (1 << 6)
+#define OMAP24XX_TRANSITION_EN (1 << 5)
+#define OMAP24XX_EVGENOFF_EN (1 << 4)
+#define OMAP24XX_EVGENON_EN (1 << 3)
+
+/* PRCM_VOLTCTRL */
+#define OMAP24XX_AUTO_EXTVOLT (1 << 15)
+#define OMAP24XX_FORCE_EXTVOLT (1 << 14)
+#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
+#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
+#define OMAP24XX_MEMRETCTRL (1 << 8)
+#define OMAP24XX_SETRET_LEVEL_SHIFT 6
+#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
+#define OMAP24XX_VOLT_LEVEL_SHIFT 0
+#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0)
+
+/* PRCM_VOLTST */
+#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0
+#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0)
+
+/* PRCM_CLKSRC_CTRL specific bits */
+
+/* PRCM_CLKOUT_CTRL */
+#define OMAP2420_CLKOUT2_EN_SHIFT 15
+#define OMAP2420_CLKOUT2_EN (1 << 15)
+#define OMAP2420_CLKOUT2_DIV_SHIFT 11
+#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
+#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
+#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
+#define OMAP24XX_CLKOUT_EN_SHIFT 7
+#define OMAP24XX_CLKOUT_EN (1 << 7)
+#define OMAP24XX_CLKOUT_DIV_SHIFT 3
+#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
+#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
+#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
+
+/* PRCM_CLKEMUL_CTRL */
+#define OMAP24XX_EMULATION_EN_SHIFT 0
+#define OMAP24XX_EMULATION_EN (1 << 0)
+
+/* PRCM_CLKCFG_CTRL */
+#define OMAP24XX_VALID_CONFIG (1 << 0)
+
+/* PRCM_CLKCFG_STATUS */
+#define OMAP24XX_CONFIG_STATUS (1 << 0)
+
+/* PRCM_VOLTSETUP specific bits */
+
+/* PRCM_CLKSSETUP specific bits */
+
+/* PRCM_POLCTRL */
+#define OMAP2420_CLKOUT2_POL (1 << 10)
+#define OMAP24XX_CLKOUT_POL (1 << 9)
+#define OMAP24XX_CLKREQ_POL (1 << 8)
+#define OMAP2430_USE_POWEROK (1 << 2)
+#define OMAP2430_POWEROK_POL (1 << 1)
+#define OMAP24XX_EXTVOL_POL (1 << 0)
+
+/* RM_RSTST_MPU specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5)
+#define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2)
+
+/* PM_EVGENCTRL_MPU specific bits */
+
+/* PM_EVEGENONTIM_MPU specific bits */
+
+/* PM_EVEGENOFFTIM_MPU specific bits */
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP2430_FORCESTATE (1 << 18)
+
+/* PM_PWSTST_MPU specific bits */
+/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_WKEN2_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits*/
+
+/* PM_WKST2_CORE specific bits */
+
+/* PM_WKDEP_CORE specific bits*/
+#define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5)
+#define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3)
+#define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2)
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP24XX_MEMORYCHANGE (1 << 20)
+#define OMAP24XX_MEM3ONSTATE_SHIFT 14
+#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
+#define OMAP24XX_MEM2ONSTATE_SHIFT 12
+#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
+#define OMAP24XX_MEM1ONSTATE_SHIFT 10
+#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
+#define OMAP24XX_MEM3RETSTATE (1 << 5)
+#define OMAP24XX_MEM2RETSTATE (1 << 4)
+#define OMAP24XX_MEM1RETSTATE (1 << 3)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP24XX_MEM3STATEST_SHIFT 14
+#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14)
+#define OMAP24XX_MEM2STATEST_SHIFT 12
+#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12)
+#define OMAP24XX_MEM1STATEST_SHIFT 10
+#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
+
+/* RM_RSTCTRL_GFX */
+#define OMAP24XX_GFX_RST (1 << 0)
+
+/* RM_RSTST_GFX specific bits */
+#define OMAP24XX_GFX_SW_RST (1 << 4)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+/* 2430 often calls EN_WAKEUP "EN_WKUP" */
+
+/* RM_RSTCTRL_WKUP specific bits */
+
+/* RM_RSTTIME_WKUP specific bits */
+
+/* RM_RSTST_WKUP specific bits */
+/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP24XX_EXTWMPU_RST (1 << 6)
+#define OMAP24XX_SECU_WD_RST (1 << 5)
+#define OMAP24XX_MPU_WD_RST (1 << 4)
+#define OMAP24XX_SECU_VIOL_RST (1 << 3)
+
+/* PM_WKEN_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+
+/* RM_RSTCTRL_DSP */
+#define OMAP2420_RST_IVA (1 << 8)
+#define OMAP24XX_RST2_DSP (1 << 1)
+#define OMAP24XX_RST1_DSP (1 << 0)
+
+/* RM_RSTST_DSP specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP2420_IVA_SW_RST (1 << 8)
+#define OMAP24XX_DSP_SW_RST2 (1 << 5)
+#define OMAP24XX_DSP_SW_RST1 (1 << 4)
+
+/* PM_WKDEP_DSP specific bits */
+
+/* PM_PWSTCTRL_DSP specific bits */
+/* 2430 only: MEMONSTATE, MEMRETSTATE */
+#define OMAP2420_MEMIONSTATE_SHIFT 12
+#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
+#define OMAP2420_MEMIRETSTATE (1 << 4)
+
+/* PM_PWSTST_DSP specific bits */
+/* MEMSTATEST is 2430 only */
+#define OMAP2420_MEMISTATEST_SHIFT 12
+#define OMAP2420_MEMISTATEST_MASK (0x3 << 12)
+
+/* PRCM_IRQSTATUS_DSP specific bits */
+
+/* PRCM_IRQENABLE_DSP specific bits */
+
+/* RM_RSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_PWRON1_MDM (1 << 1)
+#define OMAP2430_RST1_MDM (1 << 0)
+
+/* RM_RSTST_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_MDM_SECU_VIOL (1 << 6)
+#define OMAP2430_MDM_SW_PWRON1 (1 << 5)
+#define OMAP2430_MDM_SW_RST1 (1 << 4)
+
+/* PM_WKEN_MDM */
+/* 2430 only */
+#define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0)
+
+/* PM_WKST_MDM specific bits */
+/* 2430 only */
+
+/* PM_WKDEP_MDM specific bits */
+/* 2430 only */
+
+/* PM_PWSTCTRL_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_KILLDOMAINWKUP (1 << 19)
+
+/* PM_PWSTST_MDM specific bits */
+/* 2430 only */
+
+/* PRCM_IRQSTATUS_IVA */
+/* 2420 only */
+
+/* PRCM_IRQENABLE_IVA */
+/* 2420 only */
+
+#endif
--- /dev/null
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Power/Reset Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Shared register bits */
+
+/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
+#define OMAP3430_ON_SHIFT 24
+#define OMAP3430_ON_MASK (0xff << 24)
+#define OMAP3430_ONLP_SHIFT 16
+#define OMAP3430_ONLP_MASK (0xff << 16)
+#define OMAP3430_RET_SHIFT 8
+#define OMAP3430_RET_MASK (0xff << 8)
+#define OMAP3430_OFF_SHIFT 0
+#define OMAP3430_OFF_MASK (0xff << 0)
+
+/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
+#define OMAP3430_ERROROFFSET_SHIFT 24
+#define OMAP3430_ERROROFFSET_MASK (0xff << 24)
+#define OMAP3430_ERRORGAIN_SHIFT 16
+#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
+#define OMAP3430_INITVOLTAGE_SHIFT 8
+#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
+#define OMAP3430_TIMEOUTEN (1 << 3)
+#define OMAP3430_INITVDD (1 << 2)
+#define OMAP3430_FORCEUPDATE (1 << 1)
+#define OMAP3430_VPENABLE (1 << 0)
+
+/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
+#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
+#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
+#define OMAP3430_VSTEPMIN_SHIFT 0
+#define OMAP3430_VSTEPMIN_MASK (0xff << 0)
+
+/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
+#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
+#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
+#define OMAP3430_VSTEPMAX_SHIFT 0
+#define OMAP3430_VSTEPMAX_MASK (0xff << 0)
+
+/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
+#define OMAP3430_VDDMAX_SHIFT 24
+#define OMAP3430_VDDMAX_MASK (0xff << 24)
+#define OMAP3430_VDDMIN_SHIFT 16
+#define OMAP3430_VDDMIN_MASK (0xff << 16)
+#define OMAP3430_TIMEOUT_SHIFT 0
+#define OMAP3430_TIMEOUT_MASK (0xffff << 0)
+
+/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
+#define OMAP3430_VPVOLTAGE_SHIFT 0
+#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
+
+/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
+#define OMAP3430_VPINIDLE (1 << 0)
+
+/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
+#define OMAP3430_EN_PER (1 << 7)
+
+/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
+#define OMAP3430_MEMORYCHANGE (1 << 3)
+
+/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
+#define OMAP3430_LOGICSTATEST (1 << 2)
+
+/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
+#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
+
+/*
+ * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
+ * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
+ * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
+ */
+#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
+#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
+
+/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
+#define OMAP3430_WKUP_ST (1 << 0)
+
+/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
+#define OMAP3430_WKUP_EN (1 << 0)
+
+/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
+#define OMAP3430_GRPSEL_MMC2 (1 << 25)
+#define OMAP3430_GRPSEL_MMC1 (1 << 24)
+#define OMAP3430_GRPSEL_MCSPI4 (1 << 21)
+#define OMAP3430_GRPSEL_MCSPI3 (1 << 20)
+#define OMAP3430_GRPSEL_MCSPI2 (1 << 19)
+#define OMAP3430_GRPSEL_MCSPI1 (1 << 18)
+#define OMAP3430_GRPSEL_I2C3 (1 << 17)
+#define OMAP3430_GRPSEL_I2C2 (1 << 16)
+#define OMAP3430_GRPSEL_I2C1 (1 << 15)
+#define OMAP3430_GRPSEL_UART2 (1 << 14)
+#define OMAP3430_GRPSEL_UART1 (1 << 13)
+#define OMAP3430_GRPSEL_GPT11 (1 << 12)
+#define OMAP3430_GRPSEL_GPT10 (1 << 11)
+#define OMAP3430_GRPSEL_MCBSP5 (1 << 10)
+#define OMAP3430_GRPSEL_MCBSP1 (1 << 9)
+#define OMAP3430_GRPSEL_HSOTGUSB (1 << 4)
+#define OMAP3430_GRPSEL_D2D (1 << 3)
+
+/*
+ * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
+ * PM_PWSTCTRL_PER shared bits
+ */
+#define OMAP3430_MEMONSTATE_SHIFT 16
+#define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
+#define OMAP3430_MEMRETSTATE (1 << 8)
+
+/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
+#define OMAP3430_GRPSEL_GPIO6 (1 << 17)
+#define OMAP3430_GRPSEL_GPIO5 (1 << 16)
+#define OMAP3430_GRPSEL_GPIO4 (1 << 15)
+#define OMAP3430_GRPSEL_GPIO3 (1 << 14)
+#define OMAP3430_GRPSEL_GPIO2 (1 << 13)
+#define OMAP3430_GRPSEL_UART3 (1 << 11)
+#define OMAP3430_GRPSEL_GPT9 (1 << 10)
+#define OMAP3430_GRPSEL_GPT8 (1 << 9)
+#define OMAP3430_GRPSEL_GPT7 (1 << 8)
+#define OMAP3430_GRPSEL_GPT6 (1 << 7)
+#define OMAP3430_GRPSEL_GPT5 (1 << 6)
+#define OMAP3430_GRPSEL_GPT4 (1 << 5)
+#define OMAP3430_GRPSEL_GPT3 (1 << 4)
+#define OMAP3430_GRPSEL_GPT2 (1 << 3)
+#define OMAP3430_GRPSEL_MCBSP4 (1 << 2)
+#define OMAP3430_GRPSEL_MCBSP3 (1 << 1)
+#define OMAP3430_GRPSEL_MCBSP2 (1 << 0)
+
+/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
+#define OMAP3430_GRPSEL_IO (1 << 8)
+#define OMAP3430_GRPSEL_SR2 (1 << 7)
+#define OMAP3430_GRPSEL_SR1 (1 << 6)
+#define OMAP3430_GRPSEL_GPIO1 (1 << 3)
+#define OMAP3430_GRPSEL_GPT12 (1 << 1)
+#define OMAP3430_GRPSEL_GPT1 (1 << 0)
+
+/* Bits specific to each register */
+
+/* RM_RSTCTRL_IVA2 */
+#define OMAP3430_RST3_IVA2 (1 << 2)
+#define OMAP3430_RST2_IVA2 (1 << 1)
+#define OMAP3430_RST1_IVA2 (1 << 0)
+
+/* RM_RSTST_IVA2 specific bits */
+#define OMAP3430_EMULATION_VSEQ_RST (1 << 13)
+#define OMAP3430_EMULATION_VHWA_RST (1 << 12)
+#define OMAP3430_EMULATION_IVA2_RST (1 << 11)
+#define OMAP3430_IVA2_SW_RST3 (1 << 10)
+#define OMAP3430_IVA2_SW_RST2 (1 << 9)
+#define OMAP3430_IVA2_SW_RST1 (1 << 8)
+
+/* PM_WKDEP_IVA2 specific bits */
+
+/* PM_PWSTCTRL_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
+#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
+#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
+#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
+#define OMAP3430_L2FLATMEMRETSTATE (1 << 11)
+#define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10)
+#define OMAP3430_L1FLATMEMRETSTATE (1 << 9)
+#define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8)
+
+/* PM_PWSTST_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
+#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
+#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
+#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
+
+/* PM_PREPWSTST_IVA2 specific bits */
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
+
+/* PRM_IRQSTATUS_IVA2 specific bits */
+#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2)
+#define OMAP3430_FORCEWKUP_ST (1 << 1)
+
+/* PRM_IRQENABLE_IVA2 specific bits */
+#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2)
+#define OMAP3430_FORCEWKUP_EN (1 << 1)
+
+/* PRM_REVISION specific bits */
+
+/* PRM_SYSCONFIG specific bits */
+
+/* PRM_IRQSTATUS_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_ST (1 << 24)
+#define OMAP3430_VC_RAERR_ST (1 << 23)
+#define OMAP3430_VC_SAERR_ST (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_ST (1 << 21)
+#define OMAP3430_VP2_EQVALUE_ST (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_ST (1 << 19)
+#define OMAP3430_VP2_MAXVDD_ST (1 << 18)
+#define OMAP3430_VP2_MINVDD_ST (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_ST (1 << 15)
+#define OMAP3430_VP1_EQVALUE_ST (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_ST (1 << 13)
+#define OMAP3430_VP1_MAXVDD_ST (1 << 12)
+#define OMAP3430_VP1_MINVDD_ST (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10)
+#define OMAP3430_IO_ST (1 << 9)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
+#define OMAP3430_MPU_DPLL_ST (1 << 7)
+#define OMAP3430_MPU_DPLL_ST_SHIFT 7
+#define OMAP3430_PERIPH_DPLL_ST (1 << 6)
+#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
+#define OMAP3430_CORE_DPLL_ST (1 << 5)
+#define OMAP3430_CORE_DPLL_ST_SHIFT 5
+#define OMAP3430_TRANSITION_ST (1 << 4)
+#define OMAP3430_EVGENOFF_ST (1 << 3)
+#define OMAP3430_EVGENON_ST (1 << 2)
+#define OMAP3430_FS_USB_WKUP_ST (1 << 1)
+
+/* PRM_IRQENABLE_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_EN (1 << 24)
+#define OMAP3430_VC_RAERR_EN (1 << 23)
+#define OMAP3430_VC_SAERR_EN (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_EN (1 << 21)
+#define OMAP3430_VP2_EQVALUE_EN (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_EN (1 << 19)
+#define OMAP3430_VP2_MAXVDD_EN (1 << 18)
+#define OMAP3430_VP2_MINVDD_EN (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_EN (1 << 15)
+#define OMAP3430_VP1_EQVALUE_EN (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_EN (1 << 13)
+#define OMAP3430_VP1_MAXVDD_EN (1 << 12)
+#define OMAP3430_VP1_MINVDD_EN (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10)
+#define OMAP3430_IO_EN (1 << 9)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
+#define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7)
+#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
+#define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6)
+#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
+#define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5)
+#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
+#define OMAP3430_TRANSITION_EN (1 << 4)
+#define OMAP3430_EVGENOFF_EN (1 << 3)
+#define OMAP3430_EVGENON_EN (1 << 2)
+#define OMAP3430_FS_USB_WKUP_EN (1 << 1)
+
+/* RM_RSTST_MPU specific bits */
+#define OMAP3430_EMULATION_MPU_RST (1 << 11)
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5)
+#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP3430_OFFLOADMODE_SHIFT 3
+#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
+#define OMAP3430_ONLOADMODE_SHIFT 1
+#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
+#define OMAP3430_ENABLE (1 << 0)
+
+/* PM_EVGENONTIM_MPU */
+#define OMAP3430_ONTIMEVAL_SHIFT 0
+#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+#define OMAP3430_OFFTIMEVAL_SHIFT 0
+#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP3430_L2CACHEONSTATE_SHIFT 16
+#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
+#define OMAP3430_L2CACHERETSTATE (1 << 8)
+#define OMAP3430_LOGICL1CACHERETSTATE (1 << 2)
+
+/* PM_PWSTST_MPU specific bits */
+#define OMAP3430_L2CACHESTATEST_SHIFT 6
+#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
+#define OMAP3430_LOGICL1CACHESTATEST (1 << 2)
+
+/* PM_PREPWSTST_MPU specific bits */
+#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
+#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
+#define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2)
+
+/* RM_RSTCTRL_CORE */
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1)
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0)
+
+/* RM_RSTST_CORE specific bits */
+#define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8)
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_MPUGRPSEL1_CORE specific bits */
+#define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5)
+
+/* PM_IVA2GRPSEL1_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits */
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP3430_MEM2ONSTATE_SHIFT 18
+#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
+#define OMAP3430_MEM1ONSTATE_SHIFT 16
+#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
+#define OMAP3430_MEM2RETSTATE (1 << 9)
+#define OMAP3430_MEM1RETSTATE (1 << 8)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP3430_MEM2STATEST_SHIFT 6
+#define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
+#define OMAP3430_MEM1STATEST_SHIFT 4
+#define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
+
+/* PM_PREPWSTST_CORE specific bits */
+#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
+#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
+#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
+#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
+
+/* RM_RSTST_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+#define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_PWSTST_GFX specific bits */
+
+/* PM_PREPWSTST_GFX specific bits */
+
+/* PM_WKEN_WKUP specific bits */
+#define OMAP3430_EN_IO (1 << 8)
+
+/* PM_MPUGRPSEL_WKUP specific bits */
+
+/* PM_IVA2GRPSEL_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+#define OMAP3430_ST_IO (1 << 8)
+
+/* PRM_CLKSEL */
+#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
+#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
+
+/* PRM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT_EN (1 << 7)
+#define OMAP3430_CLKOUT_EN_SHIFT 7
+
+/* RM_RSTST_DSS specific bits */
+
+/* PM_WKEN_DSS */
+#define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0)
+
+/* PM_WKDEP_DSS specific bits */
+#define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_DSS specific bits */
+
+/* PM_PWSTST_DSS specific bits */
+
+/* PM_PREPWSTST_DSS specific bits */
+
+/* RM_RSTST_CAM specific bits */
+
+/* PM_WKDEP_CAM specific bits */
+#define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_CAM specific bits */
+
+/* PM_PWSTST_CAM specific bits */
+
+/* PM_PREPWSTST_CAM specific bits */
+
+/* PM_PWSTCTRL_USBHOST specific bits */
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4)
+
+/* RM_RSTST_PER specific bits */
+
+/* PM_WKEN_PER specific bits */
+
+/* PM_MPUGRPSEL_PER specific bits */
+
+/* PM_IVA2GRPSEL_PER specific bits */
+
+/* PM_WKST_PER specific bits */
+
+/* PM_WKDEP_PER specific bits */
+#define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2)
+
+/* PM_PWSTCTRL_PER specific bits */
+
+/* PM_PWSTST_PER specific bits */
+
+/* PM_PREPWSTST_PER specific bits */
+
+/* RM_RSTST_EMU specific bits */
+
+/* PM_PWSTST_EMU specific bits */
+
+/* PRM_VC_SMPS_SA */
+#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
+#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
+#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
+#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
+
+/* PRM_VC_SMPS_VOL_RA */
+#define OMAP3430_VOLRA1_SHIFT 16
+#define OMAP3430_VOLRA1_MASK (0xff << 16)
+#define OMAP3430_VOLRA0_SHIFT 0
+#define OMAP3430_VOLRA0_MASK (0xff << 0)
+
+/* PRM_VC_SMPS_CMD_RA */
+#define OMAP3430_CMDRA1_SHIFT 16
+#define OMAP3430_CMDRA1_MASK (0xff << 16)
+#define OMAP3430_CMDRA0_SHIFT 0
+#define OMAP3430_CMDRA0_MASK (0xff << 0)
+
+/* PRM_VC_CMD_VAL_0 specific bits */
+
+/* PRM_VC_CMD_VAL_1 specific bits */
+
+/* PRM_VC_CH_CONF */
+#define OMAP3430_CMD1 (1 << 20)
+#define OMAP3430_RACEN1 (1 << 19)
+#define OMAP3430_RAC1 (1 << 18)
+#define OMAP3430_RAV1 (1 << 17)
+#define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16)
+#define OMAP3430_CMD0 (1 << 4)
+#define OMAP3430_RACEN0 (1 << 3)
+#define OMAP3430_RAC0 (1 << 2)
+#define OMAP3430_RAV0 (1 << 1)
+#define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0)
+
+/* PRM_VC_I2C_CFG */
+#define OMAP3430_HSMASTER (1 << 5)
+#define OMAP3430_SREN (1 << 4)
+#define OMAP3430_HSEN (1 << 3)
+#define OMAP3430_MCODE_SHIFT 0
+#define OMAP3430_MCODE_MASK (0x7 << 0)
+
+/* PRM_VC_BYPASS_VAL */
+#define OMAP3430_VALID (1 << 24)
+#define OMAP3430_DATA_SHIFT 16
+#define OMAP3430_DATA_MASK (0xff << 16)
+#define OMAP3430_REGADDR_SHIFT 8
+#define OMAP3430_REGADDR_MASK (0xff << 8)
+#define OMAP3430_SLAVEADDR_SHIFT 0
+#define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
+
+/* PRM_RSTCTRL */
+#define OMAP3430_RST_DPLL3 (1 << 2)
+#define OMAP3430_RST_GS (1 << 1)
+
+/* PRM_RSTTIME */
+#define OMAP3430_RSTTIME2_SHIFT 8
+#define OMAP3430_RSTTIME2_MASK (0x1f << 8)
+#define OMAP3430_RSTTIME1_SHIFT 0
+#define OMAP3430_RSTTIME1_MASK (0xff << 0)
+
+/* PRM_RSTST */
+#define OMAP3430_ICECRUSHER_RST (1 << 10)
+#define OMAP3430_ICEPICK_RST (1 << 9)
+#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8)
+#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7)
+#define OMAP3430_EXTERNAL_WARM_RST (1 << 6)
+#define OMAP3430_SECURE_WD_RST (1 << 5)
+#define OMAP3430_MPU_WD_RST (1 << 4)
+#define OMAP3430_SECURITY_VIOL_RST (1 << 3)
+#define OMAP3430_GLOBAL_SW_RST (1 << 1)
+#define OMAP3430_GLOBAL_COLD_RST (1 << 0)
+
+/* PRM_VOLTCTRL */
+#define OMAP3430_SEL_VMODE (1 << 4)
+#define OMAP3430_SEL_OFF (1 << 3)
+#define OMAP3430_AUTO_OFF (1 << 2)
+#define OMAP3430_AUTO_RET (1 << 1)
+#define OMAP3430_AUTO_SLEEP (1 << 0)
+
+/* PRM_SRAM_PCHARGE */
+#define OMAP3430_PCHARGE_TIME_SHIFT 0
+#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
+
+/* PRM_CLKSRC_CTRL */
+#define OMAP3430_SYSCLKDIV_SHIFT 6
+#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
+#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
+#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
+#define OMAP3430_SYSCLKSEL_SHIFT 0
+#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
+
+/* PRM_VOLTSETUP1 */
+#define OMAP3430_SETUP_TIME2_SHIFT 16
+#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
+#define OMAP3430_SETUP_TIME1_SHIFT 0
+#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
+
+/* PRM_VOLTOFFSET */
+#define OMAP3430_OFFSET_TIME_SHIFT 0
+#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
+
+/* PRM_CLKSETUP */
+#define OMAP3430_SETUP_TIME_SHIFT 0
+#define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
+
+/* PRM_POLCTRL */
+#define OMAP3430_OFFMODE_POL (1 << 3)
+#define OMAP3430_CLKOUT_POL (1 << 2)
+#define OMAP3430_CLKREQ_POL (1 << 1)
+#define OMAP3430_EXTVOL_POL (1 << 0)
+
+/* PRM_VOLTSETUP2 */
+#define OMAP3430_OFFMODESETUPTIME_SHIFT 0
+#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
+
+/* PRM_VP1_CONFIG specific bits */
+
+/* PRM_VP1_VSTEPMIN specific bits */
+
+/* PRM_VP1_VSTEPMAX specific bits */
+
+/* PRM_VP1_VLIMITTO specific bits */
+
+/* PRM_VP1_VOLTAGE specific bits */
+
+/* PRM_VP1_STATUS specific bits */
+
+/* PRM_VP2_CONFIG specific bits */
+
+/* PRM_VP2_VSTEPMIN specific bits */
+
+/* PRM_VP2_VSTEPMAX specific bits */
+
+/* PRM_VP2_VLIMITTO specific bits */
+
+/* PRM_VP2_VOLTAGE specific bits */
+
+/* PRM_VP2_STATUS specific bits */
+
+/* RM_RSTST_NEON specific bits */
+
+/* PM_WKDEP_NEON specific bits */
+
+/* PM_PWSTCTRL_NEON specific bits */
+
+/* PM_PWSTST_NEON specific bits */
+
+/* PM_PREPWSTST_NEON specific bits */
+
+#endif
--- /dev/null
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_H
+
+/*
+ * OMAP2/3 Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prcm-common.h"
+
+#ifndef __ASSEMBLER__
+#define OMAP_PRM_REGADDR(module, reg) \
+ (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
+#else
+#define OMAP2420_PRM_REGADDR(module, reg) \
+ IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+#define OMAP2430_PRM_REGADDR(module, reg) \
+ IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+#define OMAP34XX_PRM_REGADDR(module, reg) \
+ IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+#endif
+
+/*
+ * Architecture-specific global PRM registers
+ * Use prm_{read,write}_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ *
+ */
+
+#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP24XX_PRCM_VOLTCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
+
+#define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
+#define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
+
+#define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+
+
+#define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+#define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+#define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+#define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+#define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+#define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+#define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+
+#define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific PRM registers from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
+ * and IRQENABLE bits.)
+ *
+ */
+
+/* Registers appearing on both 24xx and 34xx */
+
+#define RM_RSTCTRL 0x0050
+#define RM_RSTTIME 0x0054
+#define RM_RSTST 0x0058
+
+#define PM_WKEN 0x00a0
+#define PM_WKEN1 PM_WKEN
+#define PM_WKST 0x00b0
+#define PM_WKST1 PM_WKST
+#define PM_WKDEP 0x00c8
+#define PM_EVGENCTRL 0x00d4
+#define PM_EVGENONTIM 0x00d8
+#define PM_EVGENOFFTIM 0x00dc
+#define PM_PWSTCTRL 0x00e0
+#define PM_PWSTST 0x00e4
+
+#define OMAP3430_PM_MPUGRPSEL 0x00a4
+#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
+
+#define OMAP3430_PM_IVAGRPSEL 0x00a8
+#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
+
+#define OMAP3430_PM_PREPWSTST 0x00e8
+
+#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
+#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
+
+
+/* Architecture-specific registers */
+
+#define OMAP24XX_PM_WKEN2 0x00a4
+#define OMAP24XX_PM_WKST2 0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
+
+#ifndef __ASSEMBLER__
+
+/* Power/reset management domain register get/set */
+
+static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx)
+{
+ __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
+}
+
+static inline u32 prm_read_mod_reg(s16 module, s16 idx)
+{
+ return __raw_readl(OMAP_PRM_REGADDR(module, idx));
+}
+
+#endif
+
+/*
+ * Bits common to specific registers
+ *
+ * The 3430 register and bit names are generally used,
+ * since they tend to make more sense
+ */
+
+/* PM_EVGENONTIM_MPU */
+/* Named PM_EVEGENONTIM_MPU on the 24XX */
+#define OMAP_ONTIMEVAL_SHIFT 0
+#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
+#define OMAP_OFFTIMEVAL_SHIFT 0
+#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
+
+/* PRM_CLKSETUP and PRCM_VOLTSETUP */
+/* Named PRCM_CLKSSETUP on the 24XX */
+#define OMAP_SETUP_TIME_SHIFT 0
+#define OMAP_SETUP_TIME_MASK (0xffff << 0)
+
+/* PRM_CLKSRC_CTRL */
+/* Named PRCM_CLKSRC_CTRL on the 24XX */
+#define OMAP_SYSCLKDIV_SHIFT 6
+#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
+#define OMAP_AUTOEXTCLKMODE_SHIFT 3
+#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
+#define OMAP_SYSCLKSEL_SHIFT 0
+#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP_OFFLOADMODE_SHIFT 3
+#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
+#define OMAP_ONLOADMODE_SHIFT 1
+#define OMAP_ONLOADMODE_MASK (0x3 << 1)
+#define OMAP_ENABLE (1 << 0)
+
+/* PRM_RSTTIME */
+/* Named RM_RSTTIME_WKUP on the 24xx */
+#define OMAP_RSTTIME2_SHIFT 8
+#define OMAP_RSTTIME2_MASK (0x1f << 8)
+#define OMAP_RSTTIME1_SHIFT 0
+#define OMAP_RSTTIME1_MASK (0xff << 0)
+
+
+/* PRM_RSTCTRL */
+/* Named RM_RSTCTRL_WKUP on the 24xx */
+/* 2420 calls RST_DPLL3 'RST_DPLL' */
+#define OMAP_RST_DPLL3 (1 << 2)
+#define OMAP_RST_GS (1 << 1)
+
+
+/*
+ * Bits common to module-shared registers
+ *
+ * Not all registers of a particular type support all of these bits -
+ * check TRM if you are unsure
+ */
+
+/*
+ * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ * PM_PWSTST_NEON
+ */
+#define OMAP_INTRANSITION (1 << 20)
+
+
+/*
+ * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ * PM_PWSTST_NEON
+ */
+#define OMAP_POWERSTATEST_SHIFT 0
+#define OMAP_POWERSTATEST_MASK (0x3 << 0)
+
+/*
+ * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
+ * called 'COREWKUP_RST'
+ *
+ * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
+ * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
+ */
+#define OMAP_COREDOMAINWKUP_RST (1 << 3)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_DOMAINWKUP_RST (1 << 2)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
+ * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_GLOBALWARM_RST (1 << 1)
+#define OMAP_GLOBALCOLD_RST (1 << 0)
+
+/*
+ * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
+ * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
+ *
+ * 2430: PM_WKDEP_MDM
+ *
+ * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
+ * PM_WKDEP_PER
+ */
+#define OMAP_EN_WKUP (1 << 4)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ * PM_PWSTCTRL_DSP
+ *
+ * 2430: PM_PWSTCTRL_MDM
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ * PM_PWSTCTRL_NEON
+ */
+#define OMAP_LOGICRETSTATE (1 << 2)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
+ *
+ * 2430: PM_PWSTCTRL_MDM shared bits
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
+ * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ * PM_PWSTCTRL_NEON shared bits
+ */
+#define OMAP_POWERSTATE_SHIFT 0
+#define OMAP_POWERSTATE_MASK (0x3 << 0)
+
+
+#endif
--- /dev/null
+#ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
+#define __ARCH_ARM_MACH_OMAP2_SDRC_H
+
+/*
+ * OMAP2 SDRC register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <asm/arch/sdrc.h>
+
+#ifndef __ASSEMBLER__
+extern unsigned long omap2_sdrc_base;
+extern unsigned long omap2_sms_base;
+
+#define OMAP_SDRC_REGADDR(reg) \
+ (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg))
+#define OMAP_SMS_REGADDR(reg) \
+ (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg))
+
+/* SDRC global register get/set */
+
+static inline void sdrc_write_reg(u32 val, u16 reg)
+{
+ __raw_writel(val, OMAP_SDRC_REGADDR(reg));
+}
+
+static inline u32 sdrc_read_reg(u16 reg)
+{
+ return __raw_readl(OMAP_SDRC_REGADDR(reg));
+}
+
+/* SMS global register get/set */
+
+static inline void sms_write_reg(u32 val, u16 reg)
+{
+ __raw_writel(val, OMAP_SMS_REGADDR(reg));
+}
+
+static inline u32 sms_read_reg(u16 reg)
+{
+ return __raw_readl(OMAP_SMS_REGADDR(reg));
+}
+#else
+#define OMAP242X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
+#define OMAP243X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
+#define OMAP34XX_SDRC_REGADDR(reg) IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
+#endif /* __ASSEMBLER__ */
+
+#endif
#include <asm/arch/io.h>
#include <asm/arch/pm.h>
-#define A_32KSYNC_CR_V IO_ADDRESS(OMAP_TIMER32K_BASE+0x10)
-#define A_PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50)
-#define A_PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80)
-#define A_CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500)
-#define A_CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520)
-#define A_CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540)
-#define A_CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544)
+#include "sdrc.h"
-#define A_SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60)
-#define A_SDRC_POWER_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70)
-#define A_SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4)
+/* First address of reserved address space? apparently valid for OMAP2 & 3 */
#define A_SDRC0_V (0xC0000000)
-#define A_SDRC_MANUAL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8)
.text
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
A_SDRC_POWER:
- .word A_SDRC_POWER_V
+ .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
A_SDRC0:
.word A_SDRC0_V
-A_CM_CLKSEL2_PLL_S:
- .word A_CM_CLKSEL2_PLL_V
-A_CM_CLKEN_PLL:
- .word A_CM_CLKEN_PLL_V
A_SDRC_DLLA_CTRL_S:
- .word A_SDRC_DLLA_CTRL_V
-A_SDRC_MANUAL_S:
- .word A_SDRC_MANUAL_V
+ .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
ENTRY(omap24xx_cpu_suspend_sz)
.word . - omap24xx_cpu_suspend
#include <asm/arch/io.h>
#include <asm/hardware.h>
-#include "prcm-regs.h"
+#include "sdrc.h"
+#include "prm.h"
+#include "cm.h"
-#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
-
-#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
-#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
-#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
-#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
-#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
-#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
-
-#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
+#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
.text
/* relative load constants */
cm_clksel2_pll:
- .word CM_CLKSEL2_PLL_V
+ .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
sdrc_dlla_ctrl:
- .word SDRC_DLLA_CTRL_V
+ .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
prcm_voltctrl:
- .word PRCM_VOLTCTRL_V
+ .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
prcm_mask_val:
.word 0xFFFF3FFC
timer_32ksynct_cr:
mov pc, lr @ back to caller
ddr_cm_clksel2_pll:
- .word CM_CLKSEL2_PLL_V
+ .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
ddr_sdrc_dlla_ctrl:
- .word SDRC_DLLA_CTRL_V
+ .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
ddr_sdrc_rfr_ctrl:
- .word SDRC_RFR_CTRL_V
+ .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
ddr_prcm_voltctrl:
- .word PRCM_VOLTCTRL_V
+ .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
ddr_prcm_mask_val:
.word 0xFFFF3FFC
ddr_timer_32ksynct:
ldmfd sp!, {r0-r12, pc} @ restore regs and return
set_config:
- .word PRCM_CLKCFG_CTRL_V
+ .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80)
pll_ctl:
- .word CM_CLKEN_PLL_V
+ .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1)
pll_stat:
- .word CM_IDLEST_CKGEN_V
+ .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1)
pll_div:
- .word CM_CLKSEL1_PLL_V
+ .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL)
sdrc_rfr:
- .word SDRC_RFR_CTRL_V
+ .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
dlla_ctrl:
- .word SDRC_DLLA_CTRL_V
+ .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
ENTRY(sram_set_prcm_sz)
.word . - sram_set_prcm
*
* OMAP2 GP timer support.
*
+ * Update to use new clocksource/clockevent layers
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * Original driver:
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
* Juha Yrjölä <juha.yrjola@nokia.com>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/irq.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
#include <asm/mach/time.h>
#include <asm/arch/dmtimer.h>
static struct omap_dm_timer *gptimer;
-
-static inline void omap2_gp_timer_start(unsigned long load_val)
-{
- omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
- omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
- omap_dm_timer_start(gptimer);
-}
+static struct clock_event_device clockevent_gpt;
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
- omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
- timer_tick();
+ struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
+ struct clock_event_device *evt = &clockevent_gpt;
+
+ omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
+ evt->event_handler(evt);
return IRQ_HANDLED;
}
.handler = omap2_gp_timer_interrupt,
};
-static void __init omap2_gp_timer_init(void)
+static int omap2_gp_timer_set_next_event(unsigned long cycles,
+ struct clock_event_device *evt)
{
- u32 tick_period;
+ omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles);
+ omap_dm_timer_start(gptimer);
+
+ return 0;
+}
+
+static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+ u32 period;
+
+ omap_dm_timer_stop(gptimer);
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
+ period -= 1;
+
+ omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period);
+ omap_dm_timer_start(gptimer);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ case CLOCK_EVT_MODE_RESUME:
+ break;
+ }
+}
+
+static struct clock_event_device clockevent_gpt = {
+ .name = "gp timer",
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .shift = 32,
+ .set_next_event = omap2_gp_timer_set_next_event,
+ .set_mode = omap2_gp_timer_set_mode,
+};
+
+static void __init omap2_gp_clockevent_init(void)
+{
+ u32 tick_rate;
- omap_dm_timer_init();
gptimer = omap_dm_timer_request_specific(1);
BUG_ON(gptimer == NULL);
+#if defined(CONFIG_OMAP_32K_TIMER)
+ omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
+#else
omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
- tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
- tick_period -= 1;
+#endif
+ tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
+ omap2_gp_timer_irq.dev_id = (void *)gptimer;
setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
- omap2_gp_timer_start(tick_period);
+ omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
+
+ clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
+ clockevent_gpt.shift);
+ clockevent_gpt.max_delta_ns =
+ clockevent_delta2ns(0xffffffff, &clockevent_gpt);
+ clockevent_gpt.min_delta_ns =
+ clockevent_delta2ns(1, &clockevent_gpt);
+
+ clockevent_gpt.cpumask = cpumask_of_cpu(0);
+ clockevents_register_device(&clockevent_gpt);
+}
+
+#ifdef CONFIG_OMAP_32K_TIMER
+/*
+ * When 32k-timer is enabled, don't use GPTimer for clocksource
+ * instead, just leave default clocksource which uses the 32k
+ * sync counter. See clocksource setup in see plat-omap/common.c.
+ */
+
+static inline void __init omap2_gp_clocksource_init(void) {}
+#else
+/*
+ * clocksource
+ */
+static struct omap_dm_timer *gpt_clocksource;
+static cycle_t clocksource_read_cycles(void)
+{
+ return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
+}
+
+static struct clocksource clocksource_gpt = {
+ .name = "gp timer",
+ .rating = 300,
+ .read = clocksource_read_cycles,
+ .mask = CLOCKSOURCE_MASK(32),
+ .shift = 24,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/* Setup free-running counter for clocksource */
+static void __init omap2_gp_clocksource_init(void)
+{
+ static struct omap_dm_timer *gpt;
+ u32 tick_rate, tick_period;
+ static char err1[] __initdata = KERN_ERR
+ "%s: failed to request dm-timer\n";
+ static char err2[] __initdata = KERN_ERR
+ "%s: can't register clocksource!\n";
+
+ gpt = omap_dm_timer_request();
+ if (!gpt)
+ printk(err1, clocksource_gpt.name);
+ gpt_clocksource = gpt;
+
+ omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
+ tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
+ tick_period = (tick_rate / HZ) - 1;
+
+ omap_dm_timer_set_load(gpt, 1, 0);
+ omap_dm_timer_start(gpt);
+
+ clocksource_gpt.mult =
+ clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
+ if (clocksource_register(&clocksource_gpt))
+ printk(err2, clocksource_gpt.name);
+}
+#endif
+
+static void __init omap2_gp_timer_init(void)
+{
+ omap_dm_timer_init();
+
+ omap2_gp_clockevent_init();
+ omap2_gp_clocksource_init();
}
struct sys_timer omap_timer = {
+++ /dev/null
-/*
- * arch/arm/mach-orion/addr-map.c
- *
- * Address map functions for Marvell Orion System On Chip
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/hardware.h>
-#include "common.h"
-
-/*
- * The Orion has fully programable address map. There's a separate address
- * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
- * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
- * address decode windows that allow it to access any of the Orion resources.
- *
- * CPU address decoding --
- * Linux assumes that it is the boot loader that already setup the access to
- * DDR and internal registers.
- * Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
- * Setup access to various devices located on the device bus interface (e.g.
- * flashes, RTC, etc) should be issued by machine-setup.c according to
- * specific board population (by using orion_setup_cpu_win()).
- *
- * Non-CPU Masters address decoding --
- * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
- * banks only (the typical use case).
- * Setup access for each master to DDR is issued by common.c.
- *
- * Note: although orion_setbits() and orion_clrbits() are not atomic
- * no locking is necessary here since code in this file is only called
- * at boot time when there is no concurrency issues.
- */
-
-/*
- * Generic Address Decode Windows bit settings
- */
-#define TARGET_DDR 0
-#define TARGET_PCI 3
-#define TARGET_PCIE 4
-#define TARGET_DEV_BUS 1
-#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
- ((n) == 1) ? 0xd : \
- ((n) == 2) ? 0xb : \
- ((n) == 3) ? 0x7 : 0xf)
-#define ATTR_PCIE_MEM 0x59
-#define ATTR_PCIE_IO 0x51
-#define ATTR_PCI_MEM 0x59
-#define ATTR_PCI_IO 0x51
-#define ATTR_DEV_CS0 0x1e
-#define ATTR_DEV_CS1 0x1d
-#define ATTR_DEV_CS2 0x1b
-#define ATTR_DEV_BOOT 0xf
-#define WIN_EN 1
-
-/*
- * Helpers to get DDR banks info
- */
-#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8))
-#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8))
-#define DDR_MAX_CS 4
-#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
-#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
-#define DDR_BANK_EN 1
-
-/*
- * CPU Address Decode Windows registers
- */
-#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4))
-#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4))
-#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4))
-#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4))
-#define CPU_MAX_WIN 8
-
-/*
- * Use this CPU address decode windows allocation
- */
-#define CPU_WIN_PCIE_IO 0
-#define CPU_WIN_PCI_IO 1
-#define CPU_WIN_PCIE_MEM 2
-#define CPU_WIN_PCI_MEM 3
-#define CPU_WIN_DEV_BOOT 4
-#define CPU_WIN_DEV_CS0 5
-#define CPU_WIN_DEV_CS1 6
-#define CPU_WIN_DEV_CS2 7
-
-/*
- * PCIE Address Decode Windows registers
- */
-#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
-#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8))
-#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8))
-#define PCIE_WIN_CTRL(n) (((n) < 5) ? \
- ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
- ORION_PCIE_REG(0x1880))
-#define PCIE_WIN_BASE(n) (((n) < 5) ? \
- ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
- ORION_PCIE_REG(0x1884))
-#define PCIE_WIN_REMAP(n) (((n) < 5) ? \
- ORION_PCIE_REG(0x182c + ((n) << 4)) : \
- ORION_PCIE_REG(0x188c))
-#define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0)
-#define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0)
-#define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4)
-#define PCIE_MAX_BARS 3
-#define PCIE_MAX_WINS 6
-
-/*
- * Use PCIE BAR '1' for all DDR banks
- */
-#define PCIE_DRAM_BAR 1
-
-/*
- * PCI Address Decode Windows registers
- */
-#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \
- ((n) == 1) ? ORION_PCI_REG(0xd08) : \
- ((n) == 2) ? ORION_PCI_REG(0xc0c) : \
- ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
-#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \
- ((n) == 1) ? ORION_PCI_REG(0xd48) : \
- ((n) == 2) ? ORION_PCI_REG(0xc4c) : \
- ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
-#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c)
-#define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4))
-#define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4))
-#define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4))
-#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c)
-
-/*
- * PCI configuration heleprs for BAR settings
- */
-#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
-#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
-#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
-
-/*
- * Gigabit Ethernet Address Decode Windows registers
- */
-#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8))
-#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8))
-#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4))
-#define ETH_WIN_EN ORION_ETH_REG(0x290)
-#define ETH_WIN_PROT ORION_ETH_REG(0x294)
-#define ETH_MAX_WIN 6
-#define ETH_MAX_REMAP_WIN 4
-
-/*
- * USB Address Decode Windows registers
- */
-#define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \
- : ORION_USB1_REG(0x320 + ((w) << 4)))
-#define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \
- : ORION_USB1_REG(0x324 + ((w) << 4)))
-#define USB_MAX_WIN 4
-
-/*
- * SATA Address Decode Windows registers
- */
-#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10))
-#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10))
-#define SATA_MAX_WIN 4
-
-static int __init orion_cpu_win_can_remap(u32 win)
-{
- u32 dev, rev;
-
- orion_pcie_id(&dev, &rev);
- if ((dev == MV88F5281_DEV_ID && win < 4)
- || (dev == MV88F5182_DEV_ID && win < 2)
- || (dev == MV88F5181_DEV_ID && win < 2))
- return 1;
-
- return 0;
-}
-
-void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
-{
- u32 win, attr, ctrl;
-
- switch (target) {
- case ORION_PCIE_IO:
- target = TARGET_PCIE;
- attr = ATTR_PCIE_IO;
- win = CPU_WIN_PCIE_IO;
- break;
- case ORION_PCI_IO:
- target = TARGET_PCI;
- attr = ATTR_PCI_IO;
- win = CPU_WIN_PCI_IO;
- break;
- case ORION_PCIE_MEM:
- target = TARGET_PCIE;
- attr = ATTR_PCIE_MEM;
- win = CPU_WIN_PCIE_MEM;
- break;
- case ORION_PCI_MEM:
- target = TARGET_PCI;
- attr = ATTR_PCI_MEM;
- win = CPU_WIN_PCI_MEM;
- break;
- case ORION_DEV_BOOT:
- target = TARGET_DEV_BUS;
- attr = ATTR_DEV_BOOT;
- win = CPU_WIN_DEV_BOOT;
- break;
- case ORION_DEV0:
- target = TARGET_DEV_BUS;
- attr = ATTR_DEV_CS0;
- win = CPU_WIN_DEV_CS0;
- break;
- case ORION_DEV1:
- target = TARGET_DEV_BUS;
- attr = ATTR_DEV_CS1;
- win = CPU_WIN_DEV_CS1;
- break;
- case ORION_DEV2:
- target = TARGET_DEV_BUS;
- attr = ATTR_DEV_CS2;
- win = CPU_WIN_DEV_CS2;
- break;
- case ORION_DDR:
- case ORION_REGS:
- /*
- * Must be mapped by bootloader.
- */
- default:
- target = attr = win = -1;
- BUG();
- }
-
- base &= 0xffff0000;
- ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
- (target << 4) | WIN_EN);
-
- orion_write(CPU_WIN_BASE(win), base);
- orion_write(CPU_WIN_CTRL(win), ctrl);
-
- if (orion_cpu_win_can_remap(win)) {
- if (remap >= 0) {
- orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
- orion_write(CPU_WIN_REMAP_HI(win), 0);
- } else {
- orion_write(CPU_WIN_REMAP_LO(win), base);
- orion_write(CPU_WIN_REMAP_HI(win), 0);
- }
- }
-}
-
-void __init orion_setup_cpu_wins(void)
-{
- int i;
-
- /*
- * First, disable and clear windows
- */
- for (i = 0; i < CPU_MAX_WIN; i++) {
- orion_write(CPU_WIN_BASE(i), 0);
- orion_write(CPU_WIN_CTRL(i), 0);
- if (orion_cpu_win_can_remap(i)) {
- orion_write(CPU_WIN_REMAP_LO(i), 0);
- orion_write(CPU_WIN_REMAP_HI(i), 0);
- }
- }
-
- /*
- * Setup windows for PCI+PCIe IO+MEM space.
- */
- orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
- ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
- orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
- ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
- orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
- ORION_PCIE_MEM_SIZE, -1);
- orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
- ORION_PCI_MEM_SIZE, -1);
-}
-
-/*
- * Setup PCIE BARs and Address Decode Wins:
- * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
- * WIN[0-3] -> DRAM bank[0-3]
- */
-void __init orion_setup_pcie_wins(void)
-{
- u32 base, size, i;
-
- /*
- * First, disable and clear BARs and windows
- */
- for (i = 1; i < PCIE_MAX_BARS; i++) {
- orion_write(PCIE_BAR_CTRL(i), 0);
- orion_write(PCIE_BAR_LO(i), 0);
- orion_write(PCIE_BAR_HI(i), 0);
- }
-
- for (i = 0; i < PCIE_MAX_WINS; i++) {
- orion_write(PCIE_WIN_CTRL(i), 0);
- orion_write(PCIE_WIN_BASE(i), 0);
- orion_write(PCIE_WIN_REMAP(i), 0);
- }
-
- /*
- * Setup windows for DDR banks. Count total DDR size on the fly.
- */
- base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
- size = 0;
- for (i = 0; i < DDR_MAX_CS; i++) {
- u32 bank_base, bank_size;
- bank_size = orion_read(DDR_SIZE_CS(i));
- bank_base = orion_read(DDR_BASE_CS(i));
- if (bank_size & DDR_BANK_EN) {
- bank_size = DDR_REG_TO_SIZE(bank_size);
- bank_base = DDR_REG_TO_BASE(bank_base);
- orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
- orion_write(PCIE_WIN_REMAP(i), 0);
- orion_write(PCIE_WIN_CTRL(i),
- ((bank_size-1) & 0xffff0000) |
- (ATTR_DDR_CS(i) << 8) |
- (TARGET_DDR << 4) |
- (PCIE_DRAM_BAR << 1) | WIN_EN);
- size += bank_size;
- }
- }
-
- /*
- * Setup BAR[1] to all DRAM banks
- */
- orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
- orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
- orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
- ((size - 1) & 0xffff0000) | WIN_EN);
-}
-
-void __init orion_setup_pci_wins(void)
-{
- u32 base, size, i;
-
- /*
- * First, disable windows
- */
- orion_write(PCI_BAR_ENABLE, 0xffffffff);
-
- /*
- * Setup windows for DDR banks.
- */
- for (i = 0; i < DDR_MAX_CS; i++) {
- base = orion_read(DDR_BASE_CS(i));
- size = orion_read(DDR_SIZE_CS(i));
- if (size & DDR_BANK_EN) {
- u32 bus, dev, func, reg, val;
- size = DDR_REG_TO_SIZE(size);
- base = DDR_REG_TO_BASE(base);
- bus = orion_pci_local_bus_nr();
- dev = orion_pci_local_dev_nr();
- func = PCI_CONF_FUNC_BAR_CS(i);
- reg = PCI_CONF_REG_BAR_LO_CS(i);
- orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
- orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
- (base & 0xfffff000) | (val & 0xfff));
- reg = PCI_CONF_REG_BAR_HI_CS(i);
- orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
- orion_write(PCI_BAR_SIZE_DDR_CS(i),
- (size - 1) & 0xfffff000);
- orion_write(PCI_BAR_REMAP_DDR_CS(i),
- base & 0xfffff000);
- orion_clrbits(PCI_BAR_ENABLE, (1 << i));
- }
- }
-
- /*
- * Disable automatic update of address remaping when writing to BARs
- */
- orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
-}
-
-void __init orion_setup_usb_wins(void)
-{
- int i;
- u32 usb_if, dev, rev;
- u32 max_usb_if = 1;
-
- orion_pcie_id(&dev, &rev);
- if (dev == MV88F5182_DEV_ID)
- max_usb_if = 2;
-
- for (usb_if = 0; usb_if < max_usb_if; usb_if++) {
- /*
- * First, disable and clear windows
- */
- for (i = 0; i < USB_MAX_WIN; i++) {
- orion_write(USB_WIN_BASE(usb_if, i), 0);
- orion_write(USB_WIN_CTRL(usb_if, i), 0);
- }
-
- /*
- * Setup windows for DDR banks.
- */
- for (i = 0; i < DDR_MAX_CS; i++) {
- u32 base, size;
- size = orion_read(DDR_SIZE_CS(i));
- base = orion_read(DDR_BASE_CS(i));
- if (size & DDR_BANK_EN) {
- base = DDR_REG_TO_BASE(base);
- size = DDR_REG_TO_SIZE(size);
- orion_write(USB_WIN_CTRL(usb_if, i),
- ((size-1) & 0xffff0000) |
- (ATTR_DDR_CS(i) << 8) |
- (TARGET_DDR << 4) | WIN_EN);
- orion_write(USB_WIN_BASE(usb_if, i),
- base & 0xffff0000);
- }
- }
- }
-}
-
-void __init orion_setup_eth_wins(void)
-{
- int i;
-
- /*
- * First, disable and clear windows
- */
- for (i = 0; i < ETH_MAX_WIN; i++) {
- orion_write(ETH_WIN_BASE(i), 0);
- orion_write(ETH_WIN_SIZE(i), 0);
- orion_setbits(ETH_WIN_EN, 1 << i);
- orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
- if (i < ETH_MAX_REMAP_WIN)
- orion_write(ETH_WIN_REMAP(i), 0);
- }
-
- /*
- * Setup windows for DDR banks.
- */
- for (i = 0; i < DDR_MAX_CS; i++) {
- u32 base, size;
- size = orion_read(DDR_SIZE_CS(i));
- base = orion_read(DDR_BASE_CS(i));
- if (size & DDR_BANK_EN) {
- base = DDR_REG_TO_BASE(base);
- size = DDR_REG_TO_SIZE(size);
- orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
- orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
- (ATTR_DDR_CS(i) << 8) |
- TARGET_DDR);
- orion_clrbits(ETH_WIN_EN, 1 << i);
- orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
- }
- }
-}
-
-void __init orion_setup_sata_wins(void)
-{
- int i;
-
- /*
- * First, disable and clear windows
- */
- for (i = 0; i < SATA_MAX_WIN; i++) {
- orion_write(SATA_WIN_BASE(i), 0);
- orion_write(SATA_WIN_CTRL(i), 0);
- }
-
- /*
- * Setup windows for DDR banks.
- */
- for (i = 0; i < DDR_MAX_CS; i++) {
- u32 base, size;
- size = orion_read(DDR_SIZE_CS(i));
- base = orion_read(DDR_BASE_CS(i));
- if (size & DDR_BANK_EN) {
- base = DDR_REG_TO_BASE(base);
- size = DDR_REG_TO_SIZE(size);
- orion_write(SATA_WIN_CTRL(i),
- ((size-1) & 0xffff0000) |
- (ATTR_DDR_CS(i) << 8) |
- (TARGET_DDR << 4) | WIN_EN);
- orion_write(SATA_WIN_BASE(i),
- base & 0xffff0000);
- }
- }
-}
+++ /dev/null
-#ifndef __ARCH_ORION_COMMON_H__
-#define __ARCH_ORION_COMMON_H__
-
-/*
- * Basic Orion init functions used early by machine-setup.
- */
-
-void __init orion_map_io(void);
-void __init orion_init_irq(void);
-void __init orion_init(void);
-
-/*
- * Enumerations and functions for Orion windows mapping. Used by Orion core
- * functions to map its interfaces and by the machine-setup to map its on-
- * board devices. Details in /mach-orion/addr-map.c
- */
-
-enum orion_target {
- ORION_DEV_BOOT = 0,
- ORION_DEV0,
- ORION_DEV1,
- ORION_DEV2,
- ORION_PCIE_MEM,
- ORION_PCIE_IO,
- ORION_PCI_MEM,
- ORION_PCI_IO,
- ORION_DDR,
- ORION_REGS,
- ORION_MAX_TARGETS
-};
-
-void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap);
-void orion_setup_cpu_wins(void);
-void orion_setup_eth_wins(void);
-void orion_setup_usb_wins(void);
-void orion_setup_pci_wins(void);
-void orion_setup_pcie_wins(void);
-void orion_setup_sata_wins(void);
-
-/*
- * Shared code used internally by other Orion core functions.
- * (/mach-orion/pci.c)
- */
-
-struct pci_sys_data;
-struct pci_bus;
-
-void orion_pcie_id(u32 *dev, u32 *rev);
-u32 orion_pcie_local_bus_nr(void);
-u32 orion_pci_local_bus_nr(void);
-u32 orion_pci_local_dev_nr(void);
-int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
-struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
-int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val);
-int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val);
-
-/*
- * Valid GPIO pins according to MPP setup, used by machine-setup.
- * (/mach-orion/gpio.c).
- */
-
-void __init orion_gpio_set_valid_pins(u32 pins);
-void gpio_display(void); /* debug */
-
-/*
- * Orion system timer (clocksource + clockevnt, /mach-orion/time.c)
- */
-extern struct sys_timer orion_timer;
-
-/*
- * Pull in Orion Ethernet platform_data, used by machine-setup
- */
-
-struct mv643xx_eth_platform_data;
-
-void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
-
-/*
- * Orion Sata platform_data, used by machine-setup
- */
-
-struct mv_sata_platform_data;
-
-void __init orion_sata_init(struct mv_sata_platform_data *sata_data);
-
-struct machine_desc;
-struct meminfo;
-struct tag;
-extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *,
- char **, struct meminfo *);
-
-#endif /* __ARCH_ORION_COMMON_H__ */
+++ /dev/null
-/*
- * arch/arm/mach-orion/pci.c
- *
- * PCI and PCIE functions for Marvell Orion System On Chip
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <asm/mach/pci.h>
-#include "common.h"
-
-/*****************************************************************************
- * Orion has one PCIE controller and one PCI controller.
- *
- * Note1: The local PCIE bus number is '0'. The local PCI bus number
- * follows the scanned PCIE bridged busses, if any.
- *
- * Note2: It is possible for PCI/PCIE agents to access many subsystem's
- * space, by configuring BARs and Address Decode Windows, e.g. flashes on
- * device bus, Orion registers, etc. However this code only enable the
- * access to DDR banks.
- ****************************************************************************/
-
-
-/*****************************************************************************
- * PCIE controller
- ****************************************************************************/
-#define PCIE_CTRL ORION_PCIE_REG(0x1a00)
-#define PCIE_STAT ORION_PCIE_REG(0x1a04)
-#define PCIE_DEV_ID ORION_PCIE_REG(0x0000)
-#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004)
-#define PCIE_DEV_REV ORION_PCIE_REG(0x0008)
-#define PCIE_MASK ORION_PCIE_REG(0x1910)
-#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8)
-#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc)
-
-/*
- * PCIE_STAT bits
- */
-#define PCIE_STAT_LINK_DOWN 1
-#define PCIE_STAT_BUS_OFFS 8
-#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS)
-#define PCIE_STAT_DEV_OFFS 20
-#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS)
-
-/*
- * PCIE_CONF_ADDR bits
- */
-#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc))
-#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
-#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
-#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
-#define PCIE_CONF_ADDR_EN (1 << 31)
-
-/*
- * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
- * and then reading the PCIE_CONF_DATA register. Need to make sure these
- * transactions are atomic.
- */
-static DEFINE_SPINLOCK(orion_pcie_lock);
-
-void orion_pcie_id(u32 *dev, u32 *rev)
-{
- *dev = orion_read(PCIE_DEV_ID) >> 16;
- *rev = orion_read(PCIE_DEV_REV) & 0xff;
-}
-
-u32 orion_pcie_local_bus_nr(void)
-{
- u32 stat = orion_read(PCIE_STAT);
- return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS);
-}
-
-static u32 orion_pcie_local_dev_nr(void)
-{
- u32 stat = orion_read(PCIE_STAT);
- return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS);
-}
-
-static u32 orion_pcie_no_link(void)
-{
- u32 stat = orion_read(PCIE_STAT);
- return(stat & PCIE_STAT_LINK_DOWN);
-}
-
-static void orion_pcie_set_bus_nr(int nr)
-{
- orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK);
- orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
-}
-
-static void orion_pcie_master_slave_enable(void)
-{
- orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
- PCI_COMMAND_IO |
- PCI_COMMAND_MEMORY);
-}
-
-static void orion_pcie_enable_interrupts(void)
-{
- /*
- * Enable interrupts lines
- * INTA[24] INTB[25] INTC[26] INTD[27]
- */
- orion_setbits(PCIE_MASK, 0xf<<24);
-}
-
-static int orion_pcie_valid_config(u32 bus, u32 dev)
-{
- /*
- * Don't go out when trying to access --
- * 1. our own device
- * 2. where there's no device connected (no link)
- * 3. nonexisting devices on local bus
- */
-
- if ((orion_pcie_local_bus_nr() == bus) &&
- (orion_pcie_local_dev_nr() == dev))
- return 0;
-
- if (orion_pcie_no_link())
- return 0;
-
- if (bus == orion_pcie_local_bus_nr())
- if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) ||
- ((orion_pcie_local_dev_nr() != 0) && (dev != 0)))
- return 0;
-
- return 1;
-}
-
-static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
- int size, u32 *val)
-{
- unsigned long flags;
- unsigned int dev, rev, pcie_addr;
-
- if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- spin_lock_irqsave(&orion_pcie_lock, flags);
-
- orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
- PCIE_CONF_DEV(PCI_SLOT(devfn)) |
- PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
- PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
-
- orion_pcie_id(&dev, &rev);
- if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
- /* extended register space */
- pcie_addr = ORION_PCIE_WA_VIRT_BASE;
- pcie_addr |= PCIE_CONF_BUS(bus->number) |
- PCIE_CONF_DEV(PCI_SLOT(devfn)) |
- PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
- PCIE_CONF_REG(where);
- *val = orion_read(pcie_addr);
- } else
- *val = orion_read(PCIE_CONF_DATA);
-
- if (size == 1)
- *val = (*val >> (8*(where & 0x3))) & 0xff;
- else if (size == 2)
- *val = (*val >> (8*(where & 0x3))) & 0xffff;
-
- spin_unlock_irqrestore(&orion_pcie_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where,
- int size, u32 val)
-{
- unsigned long flags;
- int ret;
-
- if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- spin_lock_irqsave(&orion_pcie_lock, flags);
-
- ret = PCIBIOS_SUCCESSFUL;
-
- orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
- PCIE_CONF_DEV(PCI_SLOT(devfn)) |
- PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
- PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
-
- if (size == 4) {
- __raw_writel(val, PCIE_CONF_DATA);
- } else if (size == 2) {
- __raw_writew(val, PCIE_CONF_DATA + (where & 0x3));
- } else if (size == 1) {
- __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3));
- } else {
- ret = PCIBIOS_BAD_REGISTER_NUMBER;
- }
-
- spin_unlock_irqrestore(&orion_pcie_lock, flags);
-
- return ret;
-}
-
-struct pci_ops orion_pcie_ops = {
- .read = orion_pcie_rd_conf,
- .write = orion_pcie_wr_conf,
-};
-
-
-static int orion_pcie_setup(struct pci_sys_data *sys)
-{
- struct resource *res;
-
- /*
- * Master + Slave enable
- */
- orion_pcie_master_slave_enable();
-
- /*
- * Enable interrupts lines A-D
- */
- orion_pcie_enable_interrupts();
-
- /*
- * Request resource
- */
- res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
- if (!res)
- panic("orion_pci_setup unable to alloc resources");
-
- /*
- * IORESOURCE_IO
- */
- res[0].name = "PCI-EX I/O Space";
- res[0].flags = IORESOURCE_IO;
- res[0].start = ORION_PCIE_IO_BUS_BASE;
- res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
- if (request_resource(&ioport_resource, &res[0]))
- panic("Request PCIE IO resource failed\n");
- sys->resource[0] = &res[0];
-
- /*
- * IORESOURCE_MEM
- */
- res[1].name = "PCI-EX Memory Space";
- res[1].flags = IORESOURCE_MEM;
- res[1].start = ORION_PCIE_MEM_PHYS_BASE;
- res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
- if (request_resource(&iomem_resource, &res[1]))
- panic("Request PCIE Memory resource failed\n");
- sys->resource[1] = &res[1];
-
- sys->resource[2] = NULL;
- sys->io_offset = 0;
-
- return 1;
-}
-
-/*****************************************************************************
- * PCI controller
- ****************************************************************************/
-#define PCI_MODE ORION_PCI_REG(0xd00)
-#define PCI_CMD ORION_PCI_REG(0xc00)
-#define PCI_P2P_CONF ORION_PCI_REG(0x1d14)
-#define PCI_CONF_ADDR ORION_PCI_REG(0xc78)
-#define PCI_CONF_DATA ORION_PCI_REG(0xc7c)
-
-/*
- * PCI_MODE bits
- */
-#define PCI_MODE_64BIT (1 << 2)
-#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
-
-/*
- * PCI_CMD bits
- */
-#define PCI_CMD_HOST_REORDER (1 << 29)
-
-/*
- * PCI_P2P_CONF bits
- */
-#define PCI_P2P_BUS_OFFS 16
-#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
-#define PCI_P2P_DEV_OFFS 24
-#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
-
-/*
- * PCI_CONF_ADDR bits
- */
-#define PCI_CONF_REG(reg) ((reg) & 0xfc)
-#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
-#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
-#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
-#define PCI_CONF_ADDR_EN (1 << 31)
-
-/*
- * Internal configuration space
- */
-#define PCI_CONF_FUNC_STAT_CMD 0
-#define PCI_CONF_REG_STAT_CMD 4
-#define PCIX_STAT 0x64
-#define PCIX_STAT_BUS_OFFS 8
-#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
-
-/*
- * PCI config cycles are done by programming the PCI_CONF_ADDR register
- * and then reading the PCI_CONF_DATA register. Need to make sure these
- * transactions are atomic.
- */
-static DEFINE_SPINLOCK(orion_pci_lock);
-
-u32 orion_pci_local_bus_nr(void)
-{
- u32 conf = orion_read(PCI_P2P_CONF);
- return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
-}
-
-u32 orion_pci_local_dev_nr(void)
-{
- u32 conf = orion_read(PCI_P2P_CONF);
- return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
-}
-
-int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
- u32 where, u32 size, u32 *val)
-{
- unsigned long flags;
- spin_lock_irqsave(&orion_pci_lock, flags);
-
- orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
- PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
- PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
-
- *val = orion_read(PCI_CONF_DATA);
-
- if (size == 1)
- *val = (*val >> (8*(where & 0x3))) & 0xff;
- else if (size == 2)
- *val = (*val >> (8*(where & 0x3))) & 0xffff;
-
- spin_unlock_irqrestore(&orion_pci_lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
- u32 where, u32 size, u32 val)
-{
- unsigned long flags;
- int ret = PCIBIOS_SUCCESSFUL;
-
- spin_lock_irqsave(&orion_pci_lock, flags);
-
- orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
- PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
- PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
-
- if (size == 4) {
- __raw_writel(val, PCI_CONF_DATA);
- } else if (size == 2) {
- __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
- } else if (size == 1) {
- __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
- } else {
- ret = PCIBIOS_BAD_REGISTER_NUMBER;
- }
-
- spin_unlock_irqrestore(&orion_pci_lock, flags);
-
- return ret;
-}
-
-static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
- int where, int size, u32 *val)
-{
- /*
- * Don't go out for local device
- */
- if ((orion_pci_local_bus_nr() == bus->number) &&
- (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where, size, val);
-}
-
-static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
- int where, int size, u32 val)
-{
- /*
- * Don't go out for local device
- */
- if ((orion_pci_local_bus_nr() == bus->number) &&
- (orion_pci_local_dev_nr() == PCI_SLOT(devfn)))
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where, size, val);
-}
-
-struct pci_ops orion_pci_ops = {
- .read = orion_pci_rd_conf,
- .write = orion_pci_wr_conf,
-};
-
-static void orion_pci_set_bus_nr(int nr)
-{
- u32 p2p = orion_read(PCI_P2P_CONF);
-
- if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
- /*
- * PCI-X mode
- */
- u32 pcix_status, bus, dev;
- bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
- dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
- orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
- pcix_status &= ~PCIX_STAT_BUS_MASK;
- pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
- orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
- } else {
- /*
- * PCI Conventional mode
- */
- p2p &= ~PCI_P2P_BUS_MASK;
- p2p |= (nr << PCI_P2P_BUS_OFFS);
- orion_write(PCI_P2P_CONF, p2p);
- }
-}
-
-static void orion_pci_master_slave_enable(void)
-{
- u32 bus_nr, dev_nr, func, reg, val;
-
- bus_nr = orion_pci_local_bus_nr();
- dev_nr = orion_pci_local_dev_nr();
- func = PCI_CONF_FUNC_STAT_CMD;
- reg = PCI_CONF_REG_STAT_CMD;
- orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val);
- val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7);
-}
-
-static int orion_pci_setup(struct pci_sys_data *sys)
-{
- struct resource *res;
-
- /*
- * Master + Slave enable
- */
- orion_pci_master_slave_enable();
-
- /*
- * Force ordering
- */
- orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
-
- /*
- * Request resources
- */
- res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
- if (!res)
- panic("orion_pci_setup unable to alloc resources");
-
- /*
- * IORESOURCE_IO
- */
- res[0].name = "PCI I/O Space";
- res[0].flags = IORESOURCE_IO;
- res[0].start = ORION_PCI_IO_BUS_BASE;
- res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
- if (request_resource(&ioport_resource, &res[0]))
- panic("Request PCI IO resource failed\n");
- sys->resource[0] = &res[0];
-
- /*
- * IORESOURCE_MEM
- */
- res[1].name = "PCI Memory Space";
- res[1].flags = IORESOURCE_MEM;
- res[1].start = ORION_PCI_MEM_PHYS_BASE;
- res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
- if (request_resource(&iomem_resource, &res[1]))
- panic("Request PCI Memory resource failed\n");
- sys->resource[1] = &res[1];
-
- sys->resource[2] = NULL;
- sys->io_offset = 0;
-
- return 1;
-}
-
-
-/*****************************************************************************
- * General PCIE + PCI
- ****************************************************************************/
-int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
-{
- int ret = 0;
-
- if (nr == 0) {
- /*
- * PCIE setup
- */
- orion_pcie_set_bus_nr(0);
- ret = orion_pcie_setup(sys);
- } else if (nr == 1) {
- /*
- * PCI setup
- */
- ret = orion_pci_setup(sys);
- }
-
- return ret;
-}
-
-struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
-{
- struct pci_ops *ops;
- struct pci_bus *bus;
-
-
- if (nr == 0) {
- u32 pci_bus;
- /*
- * PCIE scan
- */
- ops = &orion_pcie_ops;
- bus = pci_scan_bus(sys->busnr, ops, sys);
- /*
- * Set local PCI bus number to follow PCIE bridges (if any)
- */
- pci_bus = bus->number + bus->subordinate - bus->secondary + 1;
- orion_pci_set_bus_nr(pci_bus);
- } else if (nr == 1) {
- /*
- * PCI scan
- */
- ops = &orion_pci_ops;
- bus = pci_scan_bus(sys->busnr, ops, sys);
- } else {
- BUG();
- bus = NULL;
- }
-
- return bus;
-}
+++ /dev/null
-/*
- * arch/arm/mach-orion/time.c
- *
- * Core time functions for Marvell Orion System On Chip
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/mach/time.h>
-#include <asm/arch/orion.h>
-#include "common.h"
-
-/*
- * Timer0: clock_event_device, Tick.
- * Timer1: clocksource, Free running.
- * WatchDog: Not used.
- *
- * Timers are counting down.
- */
-#define CLOCKEVENT 0
-#define CLOCKSOURCE 1
-
-/*
- * Timers bits
- */
-#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1))
-#define TIMER_EN(x) (1 << ((x) * 2))
-#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1))
-#define BRIDGE_INT_TIMER_WD (1 << 3)
-#define TIMER_WD_EN (1 << 4)
-#define TIMER_WD_RELOAD_EN (1 << 5)
-
-static cycle_t orion_clksrc_read(void)
-{
- return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE)));
-}
-
-static struct clocksource orion_clksrc = {
- .name = "orion_clocksource",
- .shift = 20,
- .rating = 300,
- .read = orion_clksrc_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static int
-orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
-{
- unsigned long flags;
-
- if (delta == 0)
- return -ETIME;
-
- local_irq_save(flags);
-
- /*
- * Clear and enable timer interrupt bit
- */
- orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
- orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
-
- /*
- * Setup new timer value
- */
- orion_write(TIMER_VAL(CLOCKEVENT), delta);
-
- /*
- * Disable auto reload and kickoff the timer
- */
- orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT));
- orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT));
-
- local_irq_restore(flags);
-
- return 0;
-}
-
-static void
-orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
-{
- unsigned long flags;
-
- local_irq_save(flags);
-
- if (mode == CLOCK_EVT_MODE_PERIODIC) {
- /*
- * Setup latch cycles in timer and enable reload interrupt.
- */
- orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH);
- orion_write(TIMER_VAL(CLOCKEVENT), LATCH);
- orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
- orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
- TIMER_EN(CLOCKEVENT));
- } else {
- /*
- * Disable timer and interrupt
- */
- orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
- orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
- orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
- TIMER_EN(CLOCKEVENT));
- }
-
- local_irq_restore(flags);
-}
-
-static struct clock_event_device orion_clkevt = {
- .name = "orion_tick",
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .shift = 32,
- .rating = 300,
- .cpumask = CPU_MASK_CPU0,
- .set_next_event = orion_clkevt_next_event,
- .set_mode = orion_clkevt_mode,
-};
-
-static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
-{
- /*
- * Clear cause bit and do event
- */
- orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
- orion_clkevt.event_handler(&orion_clkevt);
- return IRQ_HANDLED;
-}
-
-static struct irqaction orion_timer_irq = {
- .name = "orion_tick",
- .flags = IRQF_DISABLED | IRQF_TIMER,
- .handler = orion_timer_interrupt
-};
-
-static void orion_timer_init(void)
-{
- /*
- * Setup clocksource free running timer (no interrupt on reload)
- */
- orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff);
- orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff);
- orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE));
- orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) |
- TIMER_EN(CLOCKSOURCE));
-
- /*
- * Register clocksource
- */
- orion_clksrc.mult =
- clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift);
-
- clocksource_register(&orion_clksrc);
-
- /*
- * Connect and enable tick handler
- */
- setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq);
-
- /*
- * Register clockevent
- */
- orion_clkevt.mult =
- div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift);
- orion_clkevt.max_delta_ns =
- clockevent_delta2ns(0xfffffffe, &orion_clkevt);
- orion_clkevt.min_delta_ns =
- clockevent_delta2ns(1, &orion_clkevt);
-
- clockevents_register_device(&orion_clkevt);
-}
-
-struct sys_timer orion_timer = {
- .init = orion_timer_init,
-};
-if ARCH_ORION
+if ARCH_ORION5X
menu "Orion Implementations"
Say 'Y' here if you want your kernel to support the
QNAP TS-109/TS-209 platform.
+config MACH_LINKSTATION_PRO
+ bool "Buffalo Linkstation Pro/Live"
+ select I2C_BOARDINFO
+ help
+ Say 'Y' here if you want your kernel to support the
+ Buffalo Linkstation Pro/Live platform. Both v1 and
+ v2 devices are supported.
+
endmenu
endif
-obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o
+obj-y += common.o addr-map.o pci.o gpio.o irq.o
obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
+obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
obj-$(CONFIG_MACH_DNS323) += dns323-setup.o
obj-$(CONFIG_MACH_TS209) += ts209-setup.o
--- /dev/null
+/*
+ * arch/arm/mach-orion5x/addr-map.c
+ *
+ * Address map functions for Marvell Orion 5x SoCs
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include "common.h"
+
+/*
+ * The Orion has fully programable address map. There's a separate address
+ * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
+ * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
+ * address decode windows that allow it to access any of the Orion resources.
+ *
+ * CPU address decoding --
+ * Linux assumes that it is the boot loader that already setup the access to
+ * DDR and internal registers.
+ * Setup access to PCI and PCI-E IO/MEM space is issued by this file.
+ * Setup access to various devices located on the device bus interface (e.g.
+ * flashes, RTC, etc) should be issued by machine-setup.c according to
+ * specific board population (by using orion5x_setup_*_win()).
+ *
+ * Non-CPU Masters address decoding --
+ * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
+ * banks only (the typical use case).
+ * Setup access for each master to DDR is issued by common.c.
+ *
+ * Note: although orion_setbits() and orion_clrbits() are not atomic
+ * no locking is necessary here since code in this file is only called
+ * at boot time when there is no concurrency issues.
+ */
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR 0
+#define TARGET_DEV_BUS 1
+#define TARGET_PCI 3
+#define TARGET_PCIE 4
+#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
+ ((n) == 1) ? 0xd : \
+ ((n) == 2) ? 0xb : \
+ ((n) == 3) ? 0x7 : 0xf)
+#define ATTR_PCIE_MEM 0x59
+#define ATTR_PCIE_IO 0x51
+#define ATTR_PCIE_WA 0x79
+#define ATTR_PCI_MEM 0x59
+#define ATTR_PCI_IO 0x51
+#define ATTR_DEV_CS0 0x1e
+#define ATTR_DEV_CS1 0x1d
+#define ATTR_DEV_CS2 0x1b
+#define ATTR_DEV_BOOT 0xf
+#define WIN_EN 1
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8))
+#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8))
+#define DDR_MAX_CS 4
+#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
+#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
+#define DDR_BANK_EN 1
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
+#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
+#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
+#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
+
+/*
+ * Gigabit Ethernet Address Decode Windows registers
+ */
+#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8))
+#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8))
+#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4))
+#define ETH_WIN_EN ORION5X_ETH_REG(0x290)
+#define ETH_WIN_PROT ORION5X_ETH_REG(0x294)
+#define ETH_MAX_WIN 6
+#define ETH_MAX_REMAP_WIN 4
+
+
+struct mbus_dram_target_info orion5x_mbus_dram_info;
+
+static int __init orion5x_cpu_win_can_remap(int win)
+{
+ u32 dev, rev;
+
+ orion5x_pcie_id(&dev, &rev);
+ if ((dev == MV88F5281_DEV_ID && win < 4)
+ || (dev == MV88F5182_DEV_ID && win < 2)
+ || (dev == MV88F5181_DEV_ID && win < 2))
+ return 1;
+
+ return 0;
+}
+
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+ u8 target, u8 attr, int remap)
+{
+ orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
+ orion5x_write(CPU_WIN_CTRL(win),
+ ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
+
+ if (orion5x_cpu_win_can_remap(win)) {
+ if (remap < 0)
+ remap = base;
+
+ orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
+ orion5x_write(CPU_WIN_REMAP_HI(win), 0);
+ }
+}
+
+void __init orion5x_setup_cpu_mbus_bridge(void)
+{
+ int i;
+ int cs;
+
+ /*
+ * First, disable and clear windows.
+ */
+ for (i = 0; i < 8; i++) {
+ orion5x_write(CPU_WIN_BASE(i), 0);
+ orion5x_write(CPU_WIN_CTRL(i), 0);
+ if (orion5x_cpu_win_can_remap(i)) {
+ orion5x_write(CPU_WIN_REMAP_LO(i), 0);
+ orion5x_write(CPU_WIN_REMAP_HI(i), 0);
+ }
+ }
+
+ /*
+ * Setup windows for PCI+PCIe IO+MEM space.
+ */
+ setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
+ TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
+ setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
+ TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
+ setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
+ TARGET_PCIE, ATTR_PCIE_MEM, -1);
+ setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
+ TARGET_PCI, ATTR_PCI_MEM, -1);
+
+ /*
+ * Setup MBUS dram target info.
+ */
+ orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+ for (i = 0, cs = 0; i < 4; i++) {
+ u32 base = readl(DDR_BASE_CS(i));
+ u32 size = readl(DDR_SIZE_CS(i));
+
+ /*
+ * Chip select enabled?
+ */
+ if (size & 1) {
+ struct mbus_dram_window *w;
+
+ w = &orion5x_mbus_dram_info.cs[cs++];
+ w->cs_index = i;
+ w->mbus_attr = 0xf & ~(1 << i);
+ w->base = base & 0xff000000;
+ w->size = (size | 0x00ffffff) + 1;
+ }
+ }
+ orion5x_mbus_dram_info.num_cs = cs;
+}
+
+void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
+{
+ setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+}
+
+void __init orion5x_setup_dev0_win(u32 base, u32 size)
+{
+ setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
+}
+
+void __init orion5x_setup_dev1_win(u32 base, u32 size)
+{
+ setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
+}
+
+void __init orion5x_setup_dev2_win(u32 base, u32 size)
+{
+ setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
+}
+
+void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
+{
+ setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
+}
+
+void __init orion5x_setup_eth_wins(void)
+{
+ int i;
+
+ /*
+ * First, disable and clear windows
+ */
+ for (i = 0; i < ETH_MAX_WIN; i++) {
+ orion5x_write(ETH_WIN_BASE(i), 0);
+ orion5x_write(ETH_WIN_SIZE(i), 0);
+ orion5x_setbits(ETH_WIN_EN, 1 << i);
+ orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
+ if (i < ETH_MAX_REMAP_WIN)
+ orion5x_write(ETH_WIN_REMAP(i), 0);
+ }
+
+ /*
+ * Setup windows for DDR banks.
+ */
+ for (i = 0; i < DDR_MAX_CS; i++) {
+ u32 base, size;
+ size = orion5x_read(DDR_SIZE_CS(i));
+ base = orion5x_read(DDR_BASE_CS(i));
+ if (size & DDR_BANK_EN) {
+ base = DDR_REG_TO_BASE(base);
+ size = DDR_REG_TO_SIZE(size);
+ orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
+ orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
+ (ATTR_DDR_CS(i) << 8) |
+ TARGET_DDR);
+ orion5x_clrbits(ETH_WIN_EN, 1 << i);
+ orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
+ }
+ }
+}
/*
- * arch/arm/mach-orion/common.c
+ * arch/arm/mach-orion5x/common.c
*
- * Core functions for Marvell Orion System On Chip
+ * Core functions for Marvell Orion 5x SoCs
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
+#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
+#include <linux/ata_platform.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <asm/mach/time.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/ehci-orion.h>
+#include <asm/plat-orion/orion_nand.h>
+#include <asm/plat-orion/time.h>
#include "common.h"
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
-static struct map_desc orion_io_desc[] __initdata = {
+static struct map_desc orion5x_io_desc[] __initdata = {
{
- .virtual = ORION_REGS_VIRT_BASE,
- .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE),
- .length = ORION_REGS_SIZE,
+ .virtual = ORION5X_REGS_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
+ .length = ORION5X_REGS_SIZE,
.type = MT_DEVICE
},
{
- .virtual = ORION_PCIE_IO_VIRT_BASE,
- .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE),
- .length = ORION_PCIE_IO_SIZE,
+ .virtual = ORION5X_PCIE_IO_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
+ .length = ORION5X_PCIE_IO_SIZE,
.type = MT_DEVICE
},
{
- .virtual = ORION_PCI_IO_VIRT_BASE,
- .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE),
- .length = ORION_PCI_IO_SIZE,
+ .virtual = ORION5X_PCI_IO_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
+ .length = ORION5X_PCI_IO_SIZE,
.type = MT_DEVICE
},
{
- .virtual = ORION_PCIE_WA_VIRT_BASE,
- .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE),
- .length = ORION_PCIE_WA_SIZE,
+ .virtual = ORION5X_PCIE_WA_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
+ .length = ORION5X_PCIE_WA_SIZE,
.type = MT_DEVICE
},
};
-void __init orion_map_io(void)
+void __init orion5x_map_io(void)
{
- iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
+ iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
}
/*****************************************************************************
* UART
****************************************************************************/
-static struct resource orion_uart_resources[] = {
+static struct resource orion5x_uart_resources[] = {
{
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
- .start = IRQ_ORION_UART0,
- .end = IRQ_ORION_UART0,
+ .start = IRQ_ORION5X_UART0,
+ .end = IRQ_ORION5X_UART0,
.flags = IORESOURCE_IRQ,
},
{
.flags = IORESOURCE_MEM,
},
{
- .start = IRQ_ORION_UART1,
- .end = IRQ_ORION_UART1,
+ .start = IRQ_ORION5X_UART1,
+ .end = IRQ_ORION5X_UART1,
.flags = IORESOURCE_IRQ,
},
};
-static struct plat_serial8250_port orion_uart_data[] = {
+static struct plat_serial8250_port orion5x_uart_data[] = {
{
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
- .irq = IRQ_ORION_UART0,
+ .irq = IRQ_ORION5X_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
- .uartclk = ORION_TCLK,
+ .uartclk = ORION5X_TCLK,
},
{
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
- .irq = IRQ_ORION_UART1,
+ .irq = IRQ_ORION5X_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
- .uartclk = ORION_TCLK,
+ .uartclk = ORION5X_TCLK,
},
{ },
};
-static struct platform_device orion_uart = {
+static struct platform_device orion5x_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
- .platform_data = orion_uart_data,
+ .platform_data = orion5x_uart_data,
},
- .resource = orion_uart_resources,
- .num_resources = ARRAY_SIZE(orion_uart_resources),
+ .resource = orion5x_uart_resources,
+ .num_resources = ARRAY_SIZE(orion5x_uart_resources),
};
/*******************************************************************************
* USB Controller - 2 interfaces
******************************************************************************/
-static struct resource orion_ehci0_resources[] = {
+static struct resource orion5x_ehci0_resources[] = {
{
- .start = ORION_USB0_PHYS_BASE,
- .end = ORION_USB0_PHYS_BASE + SZ_4K,
+ .start = ORION5X_USB0_PHYS_BASE,
+ .end = ORION5X_USB0_PHYS_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
- .start = IRQ_ORION_USB0_CTRL,
- .end = IRQ_ORION_USB0_CTRL,
+ .start = IRQ_ORION5X_USB0_CTRL,
+ .end = IRQ_ORION5X_USB0_CTRL,
.flags = IORESOURCE_IRQ,
},
};
-static struct resource orion_ehci1_resources[] = {
+static struct resource orion5x_ehci1_resources[] = {
{
- .start = ORION_USB1_PHYS_BASE,
- .end = ORION_USB1_PHYS_BASE + SZ_4K,
+ .start = ORION5X_USB1_PHYS_BASE,
+ .end = ORION5X_USB1_PHYS_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
- .start = IRQ_ORION_USB1_CTRL,
- .end = IRQ_ORION_USB1_CTRL,
+ .start = IRQ_ORION5X_USB1_CTRL,
+ .end = IRQ_ORION5X_USB1_CTRL,
.flags = IORESOURCE_IRQ,
},
};
+static struct orion_ehci_data orion5x_ehci_data = {
+ .dram = &orion5x_mbus_dram_info,
+};
+
static u64 ehci_dmamask = 0xffffffffUL;
-static struct platform_device orion_ehci0 = {
+static struct platform_device orion5x_ehci0 = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
+ .platform_data = &orion5x_ehci_data,
},
- .resource = orion_ehci0_resources,
- .num_resources = ARRAY_SIZE(orion_ehci0_resources),
+ .resource = orion5x_ehci0_resources,
+ .num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
};
-static struct platform_device orion_ehci1 = {
+static struct platform_device orion5x_ehci1 = {
.name = "orion-ehci",
.id = 1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
+ .platform_data = &orion5x_ehci_data,
},
- .resource = orion_ehci1_resources,
- .num_resources = ARRAY_SIZE(orion_ehci1_resources),
+ .resource = orion5x_ehci1_resources,
+ .num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
};
/*****************************************************************************
* (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
****************************************************************************/
-static struct resource orion_eth_shared_resources[] = {
+static struct resource orion5x_eth_shared_resources[] = {
{
- .start = ORION_ETH_PHYS_BASE + 0x2000,
- .end = ORION_ETH_PHYS_BASE + 0x3fff,
+ .start = ORION5X_ETH_PHYS_BASE + 0x2000,
+ .end = ORION5X_ETH_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
-static struct platform_device orion_eth_shared = {
+static struct platform_device orion5x_eth_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.num_resources = 1,
- .resource = orion_eth_shared_resources,
+ .resource = orion5x_eth_shared_resources,
};
-static struct resource orion_eth_resources[] = {
+static struct resource orion5x_eth_resources[] = {
{
.name = "eth irq",
- .start = IRQ_ORION_ETH_SUM,
- .end = IRQ_ORION_ETH_SUM,
+ .start = IRQ_ORION5X_ETH_SUM,
+ .end = IRQ_ORION5X_ETH_SUM,
.flags = IORESOURCE_IRQ,
}
};
-static struct platform_device orion_eth = {
+static struct platform_device orion5x_eth = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
- .resource = orion_eth_resources,
+ .resource = orion5x_eth_resources,
};
-void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data)
+void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
- orion_eth.dev.platform_data = eth_data;
- platform_device_register(&orion_eth_shared);
- platform_device_register(&orion_eth);
+ orion5x_eth.dev.platform_data = eth_data;
+ platform_device_register(&orion5x_eth_shared);
+ platform_device_register(&orion5x_eth);
}
/*****************************************************************************
* (The Orion and Discovery (MV643xx) families share the same I2C controller)
****************************************************************************/
-static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
+static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
.freq_m = 8, /* assumes 166 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
-static struct resource orion_i2c_resources[] = {
+static struct resource orion5x_i2c_resources[] = {
{
.name = "i2c base",
.start = I2C_PHYS_BASE,
},
{
.name = "i2c irq",
- .start = IRQ_ORION_I2C,
- .end = IRQ_ORION_I2C,
+ .start = IRQ_ORION5X_I2C,
+ .end = IRQ_ORION5X_I2C,
.flags = IORESOURCE_IRQ,
},
};
-static struct platform_device orion_i2c = {
+static struct platform_device orion5x_i2c = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
- .num_resources = ARRAY_SIZE(orion_i2c_resources),
- .resource = orion_i2c_resources,
+ .num_resources = ARRAY_SIZE(orion5x_i2c_resources),
+ .resource = orion5x_i2c_resources,
.dev = {
- .platform_data = &orion_i2c_pdata,
+ .platform_data = &orion5x_i2c_pdata,
},
};
/*****************************************************************************
* Sata port
****************************************************************************/
-static struct resource orion_sata_resources[] = {
+static struct resource orion5x_sata_resources[] = {
{
.name = "sata base",
- .start = ORION_SATA_PHYS_BASE,
- .end = ORION_SATA_PHYS_BASE + 0x5000 - 1,
+ .start = ORION5X_SATA_PHYS_BASE,
+ .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "sata irq",
- .start = IRQ_ORION_SATA,
- .end = IRQ_ORION_SATA,
+ .start = IRQ_ORION5X_SATA,
+ .end = IRQ_ORION5X_SATA,
.flags = IORESOURCE_IRQ,
},
};
-static struct platform_device orion_sata = {
+static struct platform_device orion5x_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
- .num_resources = ARRAY_SIZE(orion_sata_resources),
- .resource = orion_sata_resources,
+ .num_resources = ARRAY_SIZE(orion5x_sata_resources),
+ .resource = orion5x_sata_resources,
};
-void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
+void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
{
- orion_sata.dev.platform_data = sata_data;
- platform_device_register(&orion_sata);
+ sata_data->dram = &orion5x_mbus_dram_info;
+ orion5x_sata.dev.platform_data = sata_data;
+ platform_device_register(&orion5x_sata);
}
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+
+static void orion5x_timer_init(void)
+{
+ orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
+}
+
+struct sys_timer orion5x_timer = {
+ .init = orion5x_timer_init,
+};
+
/*****************************************************************************
* General
****************************************************************************/
/*
* Identify device ID and rev from PCIE configuration header space '0'.
*/
-static void orion_id(u32 *dev, u32 *rev, char **dev_name)
+static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
{
- orion_pcie_id(dev, rev);
+ orion5x_pcie_id(dev, rev);
if (*dev == MV88F5281_DEV_ID) {
if (*rev == MV88F5281_REV_D2) {
}
}
-void __init orion_init(void)
+void __init orion5x_init(void)
{
char *dev_name;
u32 dev, rev;
- orion_id(&dev, &rev, &dev_name);
- printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK);
+ orion5x_id(&dev, &rev, &dev_name);
+ printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK);
/*
* Setup Orion address map
*/
- orion_setup_cpu_wins();
- orion_setup_usb_wins();
- orion_setup_eth_wins();
- orion_setup_pci_wins();
- orion_setup_pcie_wins();
- if (dev == MV88F5182_DEV_ID)
- orion_setup_sata_wins();
+ orion5x_setup_cpu_mbus_bridge();
+ orion5x_setup_eth_wins();
/*
- * REgister devices
+ * Register devices.
*/
- platform_device_register(&orion_uart);
- platform_device_register(&orion_ehci0);
+ platform_device_register(&orion5x_uart);
+ platform_device_register(&orion5x_ehci0);
if (dev == MV88F5182_DEV_ID)
- platform_device_register(&orion_ehci1);
- platform_device_register(&orion_i2c);
+ platform_device_register(&orion5x_ehci1);
+ platform_device_register(&orion5x_i2c);
}
/*
--- /dev/null
+#ifndef __ARCH_ORION5X_COMMON_H
+#define __ARCH_ORION5X_COMMON_H
+
+/*
+ * Basic Orion init functions used early by machine-setup.
+ */
+
+void orion5x_map_io(void);
+void orion5x_init_irq(void);
+void orion5x_init(void);
+extern struct sys_timer orion5x_timer;
+
+/*
+ * Enumerations and functions for Orion windows mapping. Used by Orion core
+ * functions to map its interfaces and by the machine-setup to map its on-
+ * board devices. Details in /mach-orion/addr-map.c
+ */
+extern struct mbus_dram_target_info orion5x_mbus_dram_info;
+void orion5x_setup_cpu_mbus_bridge(void);
+void orion5x_setup_dev_boot_win(u32 base, u32 size);
+void orion5x_setup_dev0_win(u32 base, u32 size);
+void orion5x_setup_dev1_win(u32 base, u32 size);
+void orion5x_setup_dev2_win(u32 base, u32 size);
+void orion5x_setup_pcie_wa_win(u32 base, u32 size);
+void orion5x_setup_eth_wins(void);
+
+/*
+ * Shared code used internally by other Orion core functions.
+ * (/mach-orion/pci.c)
+ */
+
+struct pci_sys_data;
+struct pci_bus;
+
+void orion5x_pcie_id(u32 *dev, u32 *rev);
+int orion5x_pcie_local_bus_nr(void);
+int orion5x_pci_local_bus_nr(void);
+int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
+struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
+
+/*
+ * Valid GPIO pins according to MPP setup, used by machine-setup.
+ * (/mach-orion/gpio.c).
+ */
+
+void orion5x_gpio_set_valid_pins(u32 pins);
+void gpio_display(void); /* debug */
+
+/*
+ * Pull in Orion Ethernet platform_data, used by machine-setup
+ */
+
+struct mv643xx_eth_platform_data;
+
+void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
+
+/*
+ * Orion Sata platform_data, used by machine-setup
+ */
+
+struct mv_sata_platform_data;
+
+void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
+
+struct machine_desc;
+struct meminfo;
+struct tag;
+extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *,
+ char **, struct meminfo *);
+
+
+#endif
/*
- * arch/arm/mach-orion/db88f5281-setup.c
+ * arch/arm/mach-orion5x/db88f5281-setup.c
*
* Marvell Orion-2 Development Board Setup
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/orion_nand.h>
#include "common.h"
/*****************************************************************************
/*
* PCIE IRQ is connected internally (not GPIO)
*/
- if (dev->bus->number == orion_pcie_local_bus_nr())
- return IRQ_ORION_PCIE0_INT;
+ if (dev->bus->number == orion5x_pcie_local_bus_nr())
+ return IRQ_ORION5X_PCIE0_INT;
/*
* PCI IRQs are connected via GPIOs
.nr_controllers = 2,
.preinit = db88f5281_pci_preinit,
.swizzle = pci_std_swizzle,
- .setup = orion_pci_sys_setup,
- .scan = orion_pci_sys_scan_bus,
+ .setup = orion5x_pci_sys_setup,
+ .scan = orion5x_pci_sys_scan_bus,
.map_irq = db88f5281_pci_map_irq,
};
/*
* Basic Orion setup. Need to be called early.
*/
- orion_init();
+ orion5x_init();
/*
* Setup the CPU address decode windows for our on-board devices
*/
- orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE,
- DB88F5281_NOR_BOOT_SIZE, -1);
- orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE,
- DB88F5281_7SEG_SIZE, -1);
- orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE,
- DB88F5281_NOR_SIZE, -1);
- orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE,
- DB88F5281_NAND_SIZE, -1);
+ orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
+ DB88F5281_NOR_BOOT_SIZE);
+ orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
+ orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
+ orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
/*
* Setup Multiplexing Pins:
* MPP18: UART1_CTS MPP19: UART1_RTS
* MPP-DEV: DEV_D[16:31]
*/
- orion_write(MPP_0_7_CTRL, 0x00222203);
- orion_write(MPP_8_15_CTRL, 0x44000000);
- orion_write(MPP_16_19_CTRL, 0);
- orion_write(MPP_DEV_CTRL, 0);
+ orion5x_write(MPP_0_7_CTRL, 0x00222203);
+ orion5x_write(MPP_8_15_CTRL, 0x44000000);
+ orion5x_write(MPP_16_19_CTRL, 0);
+ orion5x_write(MPP_DEV_CTRL, 0);
- orion_gpio_set_valid_pins(0x00003fc3);
+ orion5x_gpio_set_valid_pins(0x00003fc3);
platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
- orion_eth_init(&db88f5281_eth_data);
+ orion5x_eth_init(&db88f5281_eth_data);
}
MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
/* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
- .phys_io = ORION_REGS_PHYS_BASE,
- .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc,
+ .phys_io = ORION5X_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.init_machine = db88f5281_init,
- .map_io = orion_map_io,
- .init_irq = orion_init_irq,
- .timer = &orion_timer,
+ .map_io = orion5x_map_io,
+ .init_irq = orion5x_init_irq,
+ .timer = &orion5x_timer,
MACHINE_END
/*
- * arch/arm/mach-orion/dns323-setup.c
+ * arch/arm/mach-orion5x/dns323-setup.c
*
* Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
*
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
#include "common.h"
#define DNS323_GPIO_LED_RIGHT_AMBER 1
static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
/* PCI-E */
- if (dev->bus->number == orion_pcie_local_bus_nr())
- return IRQ_ORION_PCIE0_INT;
+ if (dev->bus->number == orion5x_pcie_local_bus_nr())
+ return IRQ_ORION5X_PCIE0_INT;
pr_err("%s: requested mapping for unknown bus\n", __func__);
static struct hw_pci dns323_pci __initdata = {
.nr_controllers = 1,
.swizzle = pci_std_swizzle,
- .setup = orion_pci_sys_setup,
- .scan = orion_pci_sys_scan_bus,
+ .setup = orion5x_pci_sys_setup,
+ .scan = orion5x_pci_sys_scan_bus,
.map_irq = dns323_pci_map_irq,
};
static void __init dns323_init(void)
{
/* Setup basic Orion functions. Need to be called early. */
- orion_init();
+ orion5x_init();
/* setup flash mapping
* CS3 holds a 8 MB Spansion S29GL064M90TFIR4
*/
- orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE,
- DNS323_NOR_BOOT_SIZE, -1);
+ orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
/* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE
*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
- orion_write(ORION_REGS_VIRT_BASE | 0x20070,
- (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+ orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+ ORION5X_PCIE_WA_SIZE);
/* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
- orion_write(MPP_0_7_CTRL, 0);
- orion_write(MPP_8_15_CTRL, 0);
- orion_write(MPP_16_19_CTRL, 0);
- orion_write(MPP_DEV_CTRL, 0);
+ orion5x_write(MPP_0_7_CTRL, 0);
+ orion5x_write(MPP_8_15_CTRL, 0);
+ orion5x_write(MPP_16_19_CTRL, 0);
+ orion5x_write(MPP_DEV_CTRL, 0);
/* Define used GPIO pins
| 14 | Out | //unknown//
| 15 | Out | //unknown//
*/
- orion_gpio_set_valid_pins(0x07f6);
+ orion5x_gpio_set_valid_pins(0x07f6);
/* register dns323 specific power-off method */
if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
i2c_register_board_info(0, dns323_i2c_devices,
ARRAY_SIZE(dns323_i2c_devices));
- orion_eth_init(&dns323_eth_data);
+ orion5x_eth_init(&dns323_eth_data);
}
/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
MACHINE_START(DNS323, "D-Link DNS-323")
/* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
- .phys_io = ORION_REGS_PHYS_BASE,
- .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION5X_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = dns323_init,
- .map_io = orion_map_io,
- .init_irq = orion_init_irq,
- .timer = &orion_timer,
+ .map_io = orion5x_map_io,
+ .init_irq = orion5x_init_irq,
+ .timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
MACHINE_END
/*
- * arch/arm/mach-orion/gpio.c
+ * arch/arm/mach-orion5x/gpio.c
*
* GPIO functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <asm/gpio.h>
-#include <asm/arch/orion.h>
+#include <asm/io.h>
+#include <asm/arch/orion5x.h>
#include "common.h"
static DEFINE_SPINLOCK(gpio_lock);
static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */
-void __init orion_gpio_set_valid_pins(u32 pins)
+void __init orion5x_gpio_set_valid_pins(u32 pins)
{
gpio_valid[0] = pins;
}
if (!gpio_label[pin])
gpio_label[pin] = "?";
- orion_setbits(GPIO_IO_CONF, 1 << pin);
+ orion5x_setbits(GPIO_IO_CONF, 1 << pin);
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
gpio_label[pin] = "?";
mask = 1 << pin;
- orion_clrbits(GPIO_BLINK_EN, mask);
+ orion5x_clrbits(GPIO_BLINK_EN, mask);
if (value)
- orion_setbits(GPIO_OUT, mask);
+ orion5x_setbits(GPIO_OUT, mask);
else
- orion_clrbits(GPIO_OUT, mask);
- orion_clrbits(GPIO_IO_CONF, mask);
+ orion5x_clrbits(GPIO_OUT, mask);
+ orion5x_clrbits(GPIO_IO_CONF, mask);
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
{
int val, mask = 1 << pin;
- if (orion_read(GPIO_IO_CONF) & mask)
- val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL);
+ if (orion5x_read(GPIO_IO_CONF) & mask)
+ val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL);
else
- val = orion_read(GPIO_OUT);
+ val = orion5x_read(GPIO_OUT);
return val & mask;
}
spin_lock_irqsave(&gpio_lock, flags);
- orion_clrbits(GPIO_BLINK_EN, mask);
+ orion5x_clrbits(GPIO_BLINK_EN, mask);
if (value)
- orion_setbits(GPIO_OUT, mask);
+ orion5x_setbits(GPIO_OUT, mask);
else
- orion_clrbits(GPIO_OUT, mask);
+ orion5x_clrbits(GPIO_OUT, mask);
spin_unlock_irqrestore(&gpio_lock, flags);
}
EXPORT_SYMBOL(gpio_set_value);
-void orion_gpio_set_blink(unsigned pin, int blink)
+void orion5x_gpio_set_blink(unsigned pin, int blink)
{
unsigned long flags;
int mask = 1 << pin;
spin_lock_irqsave(&gpio_lock, flags);
- orion_clrbits(GPIO_OUT, mask);
+ orion5x_clrbits(GPIO_OUT, mask);
if (blink)
- orion_setbits(GPIO_BLINK_EN, mask);
+ orion5x_setbits(GPIO_BLINK_EN, mask);
else
- orion_clrbits(GPIO_BLINK_EN, mask);
+ orion5x_clrbits(GPIO_BLINK_EN, mask);
spin_unlock_irqrestore(&gpio_lock, flags);
}
-EXPORT_SYMBOL(orion_gpio_set_blink);
+EXPORT_SYMBOL(orion5x_gpio_set_blink);
int gpio_request(unsigned pin, const char *label)
{
printk("GPIO, free\n");
} else {
printk("GPIO, used by %s, ", gpio_label[i]);
- if (orion_read(GPIO_IO_CONF) & (1 << i)) {
+ if (orion5x_read(GPIO_IO_CONF) & (1 << i)) {
printk("input, active %s, level %s, edge %s\n",
- ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
- ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
- ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
+ ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
+ ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
+ ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
} else {
- printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1);
+ printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1);
}
}
}
printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
- MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL));
+ MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL));
printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
- MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL));
+ MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL));
printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
- MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL));
+ MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL));
printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
- MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL));
+ MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL));
printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
- GPIO_OUT, orion_read(GPIO_OUT));
+ GPIO_OUT, orion5x_read(GPIO_OUT));
printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
- GPIO_IO_CONF, orion_read(GPIO_IO_CONF));
+ GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF));
printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
- GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN));
+ GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN));
printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
- GPIO_IN_POL, orion_read(GPIO_IN_POL));
+ GPIO_IN_POL, orion5x_read(GPIO_IN_POL));
printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
- GPIO_DATA_IN, orion_read(GPIO_DATA_IN));
+ GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN));
printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
- GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK));
+ GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK));
printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
- GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE));
+ GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE));
printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
- GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK));
+ GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK));
}
/*
- * arch/arm/mach-orion/irq.c
+ * arch/arm/mach-orion5x/irq.c
*
* Core IRQ functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/gpio.h>
-#include <asm/arch/orion.h>
+#include <asm/io.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/irq.h>
#include "common.h"
/*****************************************************************************
* polarity LEVEL mask
*
****************************************************************************/
-static void orion_gpio_irq_ack(u32 irq)
+static void orion5x_gpio_irq_ack(u32 irq)
{
int pin = irq_to_gpio(irq);
if (irq_desc[irq].status & IRQ_LEVEL)
/*
* Mask bit for level interrupt
*/
- orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
+ orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
else
/*
* Clear casue bit for egde interrupt
*/
- orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
+ orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
}
-static void orion_gpio_irq_mask(u32 irq)
+static void orion5x_gpio_irq_mask(u32 irq)
{
int pin = irq_to_gpio(irq);
if (irq_desc[irq].status & IRQ_LEVEL)
- orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
+ orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
else
- orion_clrbits(GPIO_EDGE_MASK, 1 << pin);
+ orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin);
}
-static void orion_gpio_irq_unmask(u32 irq)
+static void orion5x_gpio_irq_unmask(u32 irq)
{
int pin = irq_to_gpio(irq);
if (irq_desc[irq].status & IRQ_LEVEL)
- orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
+ orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin);
else
- orion_setbits(GPIO_EDGE_MASK, 1 << pin);
+ orion5x_setbits(GPIO_EDGE_MASK, 1 << pin);
}
-static int orion_gpio_set_irq_type(u32 irq, u32 type)
+static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
{
int pin = irq_to_gpio(irq);
struct irq_desc *desc;
- if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
- printk(KERN_ERR "orion_gpio_set_irq_type failed "
+ if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
+ printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
"(irq %d, pin %d).\n", irq, pin);
return -EINVAL;
}
case IRQT_HIGH:
desc->handle_irq = handle_level_irq;
desc->status |= IRQ_LEVEL;
- orion_clrbits(GPIO_IN_POL, (1 << pin));
+ orion5x_clrbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_LOW:
desc->handle_irq = handle_level_irq;
desc->status |= IRQ_LEVEL;
- orion_setbits(GPIO_IN_POL, (1 << pin));
+ orion5x_setbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_RISING:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
- orion_clrbits(GPIO_IN_POL, (1 << pin));
+ orion5x_clrbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_FALLING:
desc->handle_irq = handle_edge_irq;
desc->status &= ~IRQ_LEVEL;
- orion_setbits(GPIO_IN_POL, (1 << pin));
+ orion5x_setbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_BOTHEDGE:
desc->handle_irq = handle_edge_irq;
/*
* set initial polarity based on current input level
*/
- if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN))
+ if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN))
& (1 << pin))
- orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
+ orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
else
- orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
+ orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
break;
default:
return 0;
}
-static struct irq_chip orion_gpio_irq_chip = {
+static struct irq_chip orion5x_gpio_irq_chip = {
.name = "Orion-IRQ-GPIO",
- .ack = orion_gpio_irq_ack,
- .mask = orion_gpio_irq_mask,
- .unmask = orion_gpio_irq_unmask,
- .set_type = orion_gpio_set_irq_type,
+ .ack = orion5x_gpio_irq_ack,
+ .mask = orion5x_gpio_irq_mask,
+ .unmask = orion5x_gpio_irq_unmask,
+ .set_type = orion5x_gpio_set_irq_type,
};
-static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
u32 cause, offs, pin;
- BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31);
- offs = (irq - IRQ_ORION_GPIO_0_7) * 8;
- cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) |
- (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK));
+ BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
+ offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
+ cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) |
+ (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK));
for (pin = offs; pin < offs + 8; pin++) {
if (cause & (1 << pin)) {
desc = irq_desc + irq;
if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
/* Swap polarity (race with GPIO line) */
- u32 polarity = orion_read(GPIO_IN_POL);
+ u32 polarity = orion5x_read(GPIO_IN_POL);
polarity ^= 1 << pin;
- orion_write(GPIO_IN_POL, polarity);
+ orion5x_write(GPIO_IN_POL, polarity);
}
desc_handle_irq(irq, desc);
}
}
}
-static void __init orion_init_gpio_irq(void)
+static void __init orion5x_init_gpio_irq(void)
{
int i;
struct irq_desc *desc;
/*
* Mask and clear GPIO IRQ interrupts
*/
- orion_write(GPIO_LEVEL_MASK, 0x0);
- orion_write(GPIO_EDGE_MASK, 0x0);
- orion_write(GPIO_EDGE_CAUSE, 0x0);
+ orion5x_write(GPIO_LEVEL_MASK, 0x0);
+ orion5x_write(GPIO_EDGE_MASK, 0x0);
+ orion5x_write(GPIO_EDGE_CAUSE, 0x0);
/*
* Register chained level handlers for GPIO IRQs by default.
* User can use set_type() if he wants to use edge types handlers.
*/
- for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) {
- set_irq_chip(i, &orion_gpio_irq_chip);
+ for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
+ set_irq_chip(i, &orion5x_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
desc = irq_desc + i;
desc->status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
- set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler);
- set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler);
- set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler);
- set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler);
+ set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler);
+ set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler);
+ set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler);
+ set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler);
}
/*****************************************************************************
* Orion Main IRQ
****************************************************************************/
-static void orion_main_irq_mask(u32 irq)
+static void __init orion5x_init_main_irq(void)
{
- orion_clrbits(MAIN_IRQ_MASK, 1 << irq);
+ orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
}
-static void orion_main_irq_unmask(u32 irq)
+void __init orion5x_init_irq(void)
{
- orion_setbits(MAIN_IRQ_MASK, 1 << irq);
-}
-
-static struct irq_chip orion_main_irq_chip = {
- .name = "Orion-IRQ-Main",
- .ack = orion_main_irq_mask,
- .mask = orion_main_irq_mask,
- .unmask = orion_main_irq_unmask,
-};
-
-static void __init orion_init_main_irq(void)
-{
- int i;
-
- /*
- * Mask and clear Main IRQ interrupts
- */
- orion_write(MAIN_IRQ_MASK, 0x0);
- orion_write(MAIN_IRQ_CAUSE, 0x0);
-
- /*
- * Register level handler for Main IRQs
- */
- for (i = 0; i < IRQ_ORION_GPIO_START; i++) {
- set_irq_chip(i, &orion_main_irq_chip);
- set_irq_handler(i, handle_level_irq);
- set_irq_flags(i, IRQF_VALID);
- }
-}
-
-void __init orion_init_irq(void)
-{
- orion_init_main_irq();
- orion_init_gpio_irq();
+ orion5x_init_main_irq();
+ orion5x_init_gpio_irq();
}
/*
- * arch/arm/mach-orion/kurobox_pro-setup.c
+ * arch/arm/mach-orion5x/kurobox_pro-setup.c
*
* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/orion_nand.h>
#include "common.h"
/*****************************************************************************
/*
* PCI isn't used on the Kuro
*/
- if (dev->bus->number == orion_pcie_local_bus_nr())
- return IRQ_ORION_PCIE0_INT;
+ if (dev->bus->number == orion5x_pcie_local_bus_nr())
+ return IRQ_ORION5X_PCIE0_INT;
else
printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
static struct hw_pci kurobox_pro_pci __initdata = {
.nr_controllers = 1,
.swizzle = pci_std_swizzle,
- .setup = orion_pci_sys_setup,
- .scan = orion_pci_sys_scan_bus,
+ .setup = orion5x_pci_sys_setup,
+ .scan = orion5x_pci_sys_scan_bus,
.map_irq = kurobox_pro_pci_map_irq,
};
* General Setup
****************************************************************************/
-static struct platform_device *kurobox_pro_devices[] __initdata = {
- &kurobox_pro_nor_flash,
- &kurobox_pro_nand_flash,
-};
-
static void __init kurobox_pro_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
- orion_init();
+ orion5x_init();
/*
* Setup the CPU address decode windows for our devices
*/
- orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE,
- KUROBOX_PRO_NOR_BOOT_SIZE, -1);
- orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE,
- KUROBOX_PRO_NAND_SIZE, -1);
+ orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
+ KUROBOX_PRO_NOR_BOOT_SIZE);
+ orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE);
+
/*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
- orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
- (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+ orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+ ORION5X_PCIE_WA_SIZE);
/*
* Setup Multiplexing Pins --
* MPP[15] SATA 1 active indication
* MPP[16-19] Not used
*/
- orion_write(MPP_0_7_CTRL, 0x44220003);
- orion_write(MPP_8_15_CTRL, 0x55550000);
- orion_write(MPP_16_19_CTRL, 0x0);
+ orion5x_write(MPP_0_7_CTRL, 0x44220003);
+ orion5x_write(MPP_8_15_CTRL, 0x55550000);
+ orion5x_write(MPP_16_19_CTRL, 0x0);
- orion_gpio_set_valid_pins(0x0000000c);
+ orion5x_gpio_set_valid_pins(0x0000000c);
- platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices));
+ platform_device_register(&kurobox_pro_nor_flash);
+ if (machine_is_kurobox_pro())
+ platform_device_register(&kurobox_pro_nand_flash);
i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
- orion_eth_init(&kurobox_pro_eth_data);
- orion_sata_init(&kurobox_pro_sata_data);
+ orion5x_eth_init(&kurobox_pro_eth_data);
+ orion5x_sata_init(&kurobox_pro_sata_data);
}
+#ifdef CONFIG_MACH_KUROBOX_PRO
MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
- .phys_io = ORION_REGS_PHYS_BASE,
- .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION5X_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+ .boot_params = 0x00000100,
+ .init_machine = kurobox_pro_init,
+ .map_io = orion5x_map_io,
+ .init_irq = orion5x_init_irq,
+ .timer = &orion5x_timer,
+ .fixup = tag_fixup_mem32,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_LINKSTATION_PRO
+MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
+ /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
+ .phys_io = ORION5X_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
- .map_io = orion_map_io,
- .init_irq = orion_init_irq,
- .timer = &orion_timer,
+ .map_io = orion5x_map_io,
+ .init_irq = orion5x_init_irq,
+ .timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
MACHINE_END
+#endif
--- /dev/null
+/*
+ * arch/arm/mach-orion5x/pci.c
+ *
+ * PCI and PCIe functions for Marvell Orion System On Chip
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+#include "common.h"
+
+/*****************************************************************************
+ * Orion has one PCIe controller and one PCI controller.
+ *
+ * Note1: The local PCIe bus number is '0'. The local PCI bus number
+ * follows the scanned PCIe bridged busses, if any.
+ *
+ * Note2: It is possible for PCI/PCIe agents to access many subsystem's
+ * space, by configuring BARs and Address Decode Windows, e.g. flashes on
+ * device bus, Orion registers, etc. However this code only enable the
+ * access to DDR banks.
+ ****************************************************************************/
+
+
+/*****************************************************************************
+ * PCIe controller
+ ****************************************************************************/
+#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
+
+void __init orion5x_pcie_id(u32 *dev, u32 *rev)
+{
+ *dev = orion_pcie_dev_id(PCIE_BASE);
+ *rev = orion_pcie_rev(PCIE_BASE);
+}
+
+int __init orion5x_pcie_local_bus_nr(void)
+{
+ return orion_pcie_get_local_bus_nr(PCIE_BASE);
+}
+
+static int pcie_valid_config(int bus, int dev)
+{
+ /*
+ * Don't go out when trying to access --
+ * 1. nonexisting device on local bus
+ * 2. where there's no device connected (no link)
+ */
+ if (bus == 0 && dev == 0)
+ return 1;
+
+ if (!orion_pcie_link_up(PCIE_BASE))
+ return 0;
+
+ if (bus == 0 && dev != 1)
+ return 0;
+
+ return 1;
+}
+
+
+/*
+ * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
+ * and then reading the PCIE_CONF_DATA register. Need to make sure these
+ * transactions are atomic.
+ */
+static DEFINE_SPINLOCK(orion5x_pcie_lock);
+
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+ int size, u32 *val)
+{
+ unsigned long flags;
+ int ret;
+
+ if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+ *val = 0xffffffff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ spin_lock_irqsave(&orion5x_pcie_lock, flags);
+ ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
+ spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
+
+ return ret;
+}
+
+static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
+ int where, int size, u32 *val)
+{
+ int ret;
+
+ if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+ *val = 0xffffffff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ /*
+ * We only support access to the non-extended configuration
+ * space when using the WA access method (or we would have to
+ * sacrifice 256M of CPU virtual address space.)
+ */
+ if (where >= 0x100) {
+ *val = 0xffffffff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
+ bus, devfn, where, size, val);
+
+ return ret;
+}
+
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+ int where, int size, u32 val)
+{
+ unsigned long flags;
+ int ret;
+
+ if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ spin_lock_irqsave(&orion5x_pcie_lock, flags);
+ ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
+ spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
+
+ return ret;
+}
+
+static struct pci_ops pcie_ops = {
+ .read = pcie_rd_conf,
+ .write = pcie_wr_conf,
+};
+
+
+static int __init pcie_setup(struct pci_sys_data *sys)
+{
+ struct resource *res;
+ int dev;
+
+ /*
+ * Generic PCIe unit setup.
+ */
+ orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
+
+ /*
+ * Check whether to apply Orion-1/Orion-NAS PCIe config
+ * read transaction workaround.
+ */
+ dev = orion_pcie_dev_id(PCIE_BASE);
+ if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
+ printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
+ "read transaction workaround\n");
+ pcie_ops.read = pcie_rd_conf_wa;
+ }
+
+ /*
+ * Request resources.
+ */
+ res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+ if (!res)
+ panic("pcie_setup unable to alloc resources");
+
+ /*
+ * IORESOURCE_IO
+ */
+ res[0].name = "PCIe I/O Space";
+ res[0].flags = IORESOURCE_IO;
+ res[0].start = ORION5X_PCIE_IO_BUS_BASE;
+ res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
+ if (request_resource(&ioport_resource, &res[0]))
+ panic("Request PCIe IO resource failed\n");
+ sys->resource[0] = &res[0];
+
+ /*
+ * IORESOURCE_MEM
+ */
+ res[1].name = "PCIe Memory Space";
+ res[1].flags = IORESOURCE_MEM;
+ res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
+ res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
+ if (request_resource(&iomem_resource, &res[1]))
+ panic("Request PCIe Memory resource failed\n");
+ sys->resource[1] = &res[1];
+
+ sys->resource[2] = NULL;
+ sys->io_offset = 0;
+
+ return 1;
+}
+
+/*****************************************************************************
+ * PCI controller
+ ****************************************************************************/
+#define PCI_MODE ORION5X_PCI_REG(0xd00)
+#define PCI_CMD ORION5X_PCI_REG(0xc00)
+#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
+#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
+#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
+
+/*
+ * PCI_MODE bits
+ */
+#define PCI_MODE_64BIT (1 << 2)
+#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
+
+/*
+ * PCI_CMD bits
+ */
+#define PCI_CMD_HOST_REORDER (1 << 29)
+
+/*
+ * PCI_P2P_CONF bits
+ */
+#define PCI_P2P_BUS_OFFS 16
+#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
+#define PCI_P2P_DEV_OFFS 24
+#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
+
+/*
+ * PCI_CONF_ADDR bits
+ */
+#define PCI_CONF_REG(reg) ((reg) & 0xfc)
+#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
+#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
+#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
+#define PCI_CONF_ADDR_EN (1 << 31)
+
+/*
+ * Internal configuration space
+ */
+#define PCI_CONF_FUNC_STAT_CMD 0
+#define PCI_CONF_REG_STAT_CMD 4
+#define PCIX_STAT 0x64
+#define PCIX_STAT_BUS_OFFS 8
+#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
+
+/*
+ * PCI Address Decode Windows registers
+ */
+#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
+ ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
+ ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
+ ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
+#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \
+ ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
+ ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
+ ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
+#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
+#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
+
+/*
+ * PCI configuration helpers for BAR settings
+ */
+#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
+#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
+#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
+
+/*
+ * PCI config cycles are done by programming the PCI_CONF_ADDR register
+ * and then reading the PCI_CONF_DATA register. Need to make sure these
+ * transactions are atomic.
+ */
+static DEFINE_SPINLOCK(orion5x_pci_lock);
+
+int orion5x_pci_local_bus_nr(void)
+{
+ u32 conf = orion5x_read(PCI_P2P_CONF);
+ return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
+}
+
+static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
+ u32 where, u32 size, u32 *val)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&orion5x_pci_lock, flags);
+
+ orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
+ PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
+ PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
+
+ *val = orion5x_read(PCI_CONF_DATA);
+
+ if (size == 1)
+ *val = (*val >> (8*(where & 0x3))) & 0xff;
+ else if (size == 2)
+ *val = (*val >> (8*(where & 0x3))) & 0xffff;
+
+ spin_unlock_irqrestore(&orion5x_pci_lock, flags);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
+ u32 where, u32 size, u32 val)
+{
+ unsigned long flags;
+ int ret = PCIBIOS_SUCCESSFUL;
+
+ spin_lock_irqsave(&orion5x_pci_lock, flags);
+
+ orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
+ PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
+ PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
+
+ if (size == 4) {
+ __raw_writel(val, PCI_CONF_DATA);
+ } else if (size == 2) {
+ __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
+ } else if (size == 1) {
+ __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
+ } else {
+ ret = PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+
+ spin_unlock_irqrestore(&orion5x_pci_lock, flags);
+
+ return ret;
+}
+
+static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
+ int where, int size, u32 *val)
+{
+ /*
+ * Don't go out for local device
+ */
+ if (bus->number == orion5x_pci_local_bus_nr() &&
+ PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
+ *val = 0xffffffff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
+ PCI_FUNC(devfn), where, size, val);
+}
+
+static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
+ int where, int size, u32 val)
+{
+ if (bus->number == orion5x_pci_local_bus_nr() &&
+ PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
+ PCI_FUNC(devfn), where, size, val);
+}
+
+static struct pci_ops pci_ops = {
+ .read = orion5x_pci_rd_conf,
+ .write = orion5x_pci_wr_conf,
+};
+
+static void __init orion5x_pci_set_bus_nr(int nr)
+{
+ u32 p2p = orion5x_read(PCI_P2P_CONF);
+
+ if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) {
+ /*
+ * PCI-X mode
+ */
+ u32 pcix_status, bus, dev;
+ bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
+ dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
+ orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
+ pcix_status &= ~PCIX_STAT_BUS_MASK;
+ pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
+ orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
+ } else {
+ /*
+ * PCI Conventional mode
+ */
+ p2p &= ~PCI_P2P_BUS_MASK;
+ p2p |= (nr << PCI_P2P_BUS_OFFS);
+ orion5x_write(PCI_P2P_CONF, p2p);
+ }
+}
+
+static void __init orion5x_pci_master_slave_enable(void)
+{
+ int bus_nr, func, reg;
+ u32 val;
+
+ bus_nr = orion5x_pci_local_bus_nr();
+ func = PCI_CONF_FUNC_STAT_CMD;
+ reg = PCI_CONF_REG_STAT_CMD;
+ orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
+ val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
+}
+
+static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
+{
+ u32 win_enable;
+ int bus;
+ int i;
+
+ /*
+ * First, disable windows.
+ */
+ win_enable = 0xffffffff;
+ orion5x_write(PCI_BAR_ENABLE, win_enable);
+
+ /*
+ * Setup windows for DDR banks.
+ */
+ bus = orion5x_pci_local_bus_nr();
+
+ for (i = 0; i < dram->num_cs; i++) {
+ struct mbus_dram_window *cs = dram->cs + i;
+ u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
+ u32 reg;
+ u32 val;
+
+ /*
+ * Write DRAM bank base address register.
+ */
+ reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
+ orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
+ val = (cs->base & 0xfffff000) | (val & 0xfff);
+ orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
+
+ /*
+ * Write DRAM bank size register.
+ */
+ reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
+ orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
+ orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
+ (cs->size - 1) & 0xfffff000);
+ orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
+ cs->base & 0xfffff000);
+
+ /*
+ * Enable decode window for this chip select.
+ */
+ win_enable &= ~(1 << cs->cs_index);
+ }
+
+ /*
+ * Re-enable decode windows.
+ */
+ orion5x_write(PCI_BAR_ENABLE, win_enable);
+
+ /*
+ * Disable automatic update of address remaping when writing to BARs.
+ */
+ orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
+}
+
+static int __init pci_setup(struct pci_sys_data *sys)
+{
+ struct resource *res;
+
+ /*
+ * Point PCI unit MBUS decode windows to DRAM space.
+ */
+ orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
+
+ /*
+ * Master + Slave enable
+ */
+ orion5x_pci_master_slave_enable();
+
+ /*
+ * Force ordering
+ */
+ orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
+
+ /*
+ * Request resources
+ */
+ res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+ if (!res)
+ panic("pci_setup unable to alloc resources");
+
+ /*
+ * IORESOURCE_IO
+ */
+ res[0].name = "PCI I/O Space";
+ res[0].flags = IORESOURCE_IO;
+ res[0].start = ORION5X_PCI_IO_BUS_BASE;
+ res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
+ if (request_resource(&ioport_resource, &res[0]))
+ panic("Request PCI IO resource failed\n");
+ sys->resource[0] = &res[0];
+
+ /*
+ * IORESOURCE_MEM
+ */
+ res[1].name = "PCI Memory Space";
+ res[1].flags = IORESOURCE_MEM;
+ res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
+ res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
+ if (request_resource(&iomem_resource, &res[1]))
+ panic("Request PCI Memory resource failed\n");
+ sys->resource[1] = &res[1];
+
+ sys->resource[2] = NULL;
+ sys->io_offset = 0;
+
+ return 1;
+}
+
+
+/*****************************************************************************
+ * General PCIe + PCI
+ ****************************************************************************/
+static void __devinit rc_pci_fixup(struct pci_dev *dev)
+{
+ /*
+ * Prevent enumeration of root complex.
+ */
+ if (dev->bus->parent == NULL && dev->devfn == 0) {
+ int i;
+
+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+ dev->resource[i].start = 0;
+ dev->resource[i].end = 0;
+ dev->resource[i].flags = 0;
+ }
+ }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
+
+int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
+{
+ int ret = 0;
+
+ if (nr == 0) {
+ orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
+ ret = pcie_setup(sys);
+ } else if (nr == 1) {
+ orion5x_pci_set_bus_nr(sys->busnr);
+ ret = pci_setup(sys);
+ }
+
+ return ret;
+}
+
+struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
+{
+ struct pci_bus *bus;
+
+ if (nr == 0) {
+ bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+ } else if (nr == 1) {
+ bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
+ } else {
+ bus = NULL;
+ BUG();
+ }
+
+ return bus;
+}
/*
- * arch/arm/mach-orion/rd88f5182-setup.c
+ * arch/arm/mach-orion5x/rd88f5182-setup.c
*
* Marvell Orion-NAS Reference Design Setup
*
* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/leds.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
#include "common.h"
/*****************************************************************************
/*
* PCI-E isn't used on the RD2
*/
- if (dev->bus->number == orion_pcie_local_bus_nr())
- return IRQ_ORION_PCIE0_INT;
+ if (dev->bus->number == orion5x_pcie_local_bus_nr())
+ return IRQ_ORION5X_PCIE0_INT;
/*
* PCI IRQs are connected via GPIOs
.nr_controllers = 2,
.preinit = rd88f5182_pci_preinit,
.swizzle = pci_std_swizzle,
- .setup = orion_pci_sys_setup,
- .scan = orion_pci_sys_scan_bus,
+ .setup = orion5x_pci_sys_setup,
+ .scan = orion5x_pci_sys_scan_bus,
.map_irq = rd88f5182_pci_map_irq,
};
/*
* Setup basic Orion functions. Need to be called early.
*/
- orion_init();
+ orion5x_init();
/*
* Setup the CPU address decode windows for our devices
*/
- orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE,
- RD88F5182_NOR_BOOT_SIZE, -1);
- orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE,
- RD88F5182_NOR_SIZE, -1);
+ orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
+ RD88F5182_NOR_BOOT_SIZE);
+ orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
/*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
- orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
- (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+ orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+ ORION5X_PCIE_WA_SIZE);
/*
* Setup Multiplexing Pins --
* MPP[25] USB 0 over current enable
*/
- orion_write(MPP_0_7_CTRL, 0x00000003);
- orion_write(MPP_8_15_CTRL, 0x55550000);
- orion_write(MPP_16_19_CTRL, 0x5555);
+ orion5x_write(MPP_0_7_CTRL, 0x00000003);
+ orion5x_write(MPP_8_15_CTRL, 0x55550000);
+ orion5x_write(MPP_16_19_CTRL, 0x5555);
- orion_gpio_set_valid_pins(0x000000fb);
+ orion5x_gpio_set_valid_pins(0x000000fb);
platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
- orion_eth_init(&rd88f5182_eth_data);
- orion_sata_init(&rd88f5182_sata_data);
+ orion5x_eth_init(&rd88f5182_eth_data);
+ orion5x_sata_init(&rd88f5182_sata_data);
}
MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
- .phys_io = ORION_REGS_PHYS_BASE,
- .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION5X_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = rd88f5182_init,
- .map_io = orion_map_io,
- .init_irq = orion_init_irq,
- .timer = &orion_timer,
+ .map_io = orion5x_map_io,
+ .init_irq = orion5x_init_irq,
+ .timer = &orion5x_timer,
MACHINE_END
#include <asm/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
#include "common.h"
#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
/*
* PCIE IRQ is connected internally (not GPIO)
*/
- if (dev->bus->number == orion_pcie_local_bus_nr())
- return IRQ_ORION_PCIE0_INT;
+ if (dev->bus->number == orion5x_pcie_local_bus_nr())
+ return IRQ_ORION5X_PCIE0_INT;
/*
* PCI IRQs are connected via GPIOs
.nr_controllers = 2,
.preinit = qnap_ts209_pci_preinit,
.swizzle = pci_std_swizzle,
- .setup = orion_pci_sys_setup,
- .scan = orion_pci_sys_scan_bus,
+ .setup = orion5x_pci_sys_setup,
+ .scan = orion5x_pci_sys_scan_bus,
.map_irq = qnap_ts209_pci_map_irq,
};
.force_phy_addr = 1,
};
+static int __init parse_hex_nibble(char n)
+{
+ if (n >= '0' && n <= '9')
+ return n - '0';
+
+ if (n >= 'A' && n <= 'F')
+ return n - 'A' + 10;
+
+ if (n >= 'a' && n <= 'f')
+ return n - 'a' + 10;
+
+ return -1;
+}
+
+static int __init parse_hex_byte(const char *b)
+{
+ int hi;
+ int lo;
+
+ hi = parse_hex_nibble(b[0]);
+ lo = parse_hex_nibble(b[1]);
+
+ if (hi < 0 || lo < 0)
+ return -1;
+
+ return (hi << 4) | lo;
+}
+
+static int __init check_mac_addr(const char *addr_str)
+{
+ u_int8_t addr[6];
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ int byte;
+
+ /*
+ * Enforce "xx:xx:xx:xx:xx:xx\n" format.
+ */
+ if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
+ return -1;
+
+ byte = parse_hex_byte(addr_str + (i * 3));
+ if (byte < 0)
+ return -1;
+ addr[i] = byte;
+ }
+
+ printk(KERN_INFO "ts209: found ethernet mac address ");
+ for (i = 0; i < 6; i++)
+ printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
+
+ memcpy(qnap_ts209_eth_data.mac_addr, addr, 6);
+
+ return 0;
+}
+
+/*
+ * The 'NAS Config' flash partition has an ext2 filesystem which
+ * contains a file that has the ethernet MAC address in plain text
+ * (format "xx:xx:xx:xx:xx:xx\n".)
+ */
+static void __init ts209_find_mac_addr(void)
+{
+ unsigned long addr;
+
+ for (addr = 0x00700000; addr < 0x00760000; addr += 1024) {
+ char *nor_page;
+ int ret = 0;
+
+ nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024);
+ if (nor_page != NULL) {
+ ret = check_mac_addr(nor_page);
+ iounmap(nor_page);
+ }
+
+ if (ret == 0)
+ break;
+ }
+}
+
/*****************************************************************************
* RTC S35390A on I2C bus
****************************************************************************/
static void qnap_ts209_power_off(void)
{
/* 19200 baud divisor */
- const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200));
+ const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
pr_info("%s: triggering power-off...\n", __func__);
/* hijack uart1 and reset into sane state (19200,8n1) */
- orion_write(UART1_REG(LCR), 0x83);
- orion_write(UART1_REG(DLL), divisor & 0xff);
- orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
- orion_write(UART1_REG(LCR), 0x03);
- orion_write(UART1_REG(IER), 0x00);
- orion_write(UART1_REG(FCR), 0x00);
- orion_write(UART1_REG(MCR), 0x00);
+ orion5x_write(UART1_REG(LCR), 0x83);
+ orion5x_write(UART1_REG(DLL), divisor & 0xff);
+ orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
+ orion5x_write(UART1_REG(LCR), 0x03);
+ orion5x_write(UART1_REG(IER), 0x00);
+ orion5x_write(UART1_REG(FCR), 0x00);
+ orion5x_write(UART1_REG(MCR), 0x00);
/* send the power-off command 'A' to PIC */
- orion_write(UART1_REG(TX), 'A');
+ orion5x_write(UART1_REG(TX), 'A');
}
static void __init qnap_ts209_init(void)
/*
* Setup basic Orion functions. Need to be called early.
*/
- orion_init();
+ orion5x_init();
/*
* Setup flash mapping
*/
- orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE,
- QNAP_TS209_NOR_BOOT_SIZE, -1);
+ orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
+ QNAP_TS209_NOR_BOOT_SIZE);
/*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
- orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
- (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+ orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+ ORION5X_PCIE_WA_SIZE);
/*
* Setup Multiplexing Pins --
* MPP[22] USB 0 over current
* MPP[23-25] Reserved
*/
- orion_write(MPP_0_7_CTRL, 0x3);
- orion_write(MPP_8_15_CTRL, 0x55550000);
- orion_write(MPP_16_19_CTRL, 0x5500);
- orion_gpio_set_valid_pins(0x3cc0fff);
+ orion5x_write(MPP_0_7_CTRL, 0x3);
+ orion5x_write(MPP_8_15_CTRL, 0x55550000);
+ orion5x_write(MPP_16_19_CTRL, 0x5500);
+ orion5x_gpio_set_valid_pins(0x3cc0fff);
/* register ts209 specific power-off method */
pm_power_off = qnap_ts209_power_off;
pr_warning("qnap_ts209_init: failed to get RTC IRQ\n");
i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
- orion_eth_init(&qnap_ts209_eth_data);
- orion_sata_init(&qnap_ts209_sata_data);
+ ts209_find_mac_addr();
+ orion5x_eth_init(&qnap_ts209_eth_data);
+
+ orion5x_sata_init(&qnap_ts209_sata_data);
}
MACHINE_START(TS209, "QNAP TS-109/TS-209")
/* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
- .phys_io = ORION_REGS_PHYS_BASE,
- .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION5X_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = qnap_ts209_init,
- .map_io = orion_map_io,
- .init_irq = orion_init_irq,
- .timer = &orion_timer,
+ .map_io = orion5x_map_io,
+ .init_irq = orion5x_init_irq,
+ .timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
MACHINE_END
#include <linux/err.h>
#include <linux/delay.h>
-#include <asm/semaphore.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <asm/semaphore.h>
#include <asm/io.h>
#include <asm/arch/platform.h>
#include <asm/arch/gpio.h>
choice
prompt "Select target board"
+config ARCH_GUMSTIX
+ bool "Gumstix XScale boards"
+ help
+ Say Y here if you intend to run this kernel on a
+ Gumstix Full Function Minature Computer.
+
config ARCH_LUBBOCK
bool "Intel DBPXA250 Development Platform"
select PXA25x
endif
+if ARCH_GUMSTIX
+
+choice
+ prompt "Select target Gumstix board"
+
+config MACH_GUMSTIX_F
+ bool "Basix, Connex, ws-200ax, ws-400ax systems"
+ select PXA25x
+
+endchoice
+
+endif
+
+
if MACH_TRIZEPS4
choice
# Common support (must be linked before board specific support)
obj-y += clock.o devices.o generic.o irq.o dma.o \
time.o gpio.o
-obj-$(CONFIG_PXA25x) += pxa25x.o
-obj-$(CONFIG_PXA27x) += pxa27x.o
-obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o smemc.o
+obj-$(CONFIG_PXA25x) += pxa25x.o mfp-pxa2xx.o
+obj-$(CONFIG_PXA27x) += pxa27x.o mfp-pxa2xx.o
+obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp-pxa3xx.o smemc.o
obj-$(CONFIG_CPU_PXA300) += pxa300.o
obj-$(CONFIG_CPU_PXA320) += pxa320.o
# Specific board support
+obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o
obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
#include <linux/delay.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/hardware.h>
#include "devices.h"
#include <asm/mach/pci.h>
#include <asm/arch/cm-x270.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/mach-types.h>
#include <asm/hardware/it8152.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/ohci.h>
#include <asm/arch/mmc.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/colibri.h>
#include "generic.h"
#include <asm/mach/irq.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/irda.h>
#include <asm/arch/mmc.h>
#include <asm/arch/udc.h>
#include <asm/arch/sharpsl.h>
#include <asm/arch/corgi.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include "sharpsl.h"
#define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */
#include <asm/arch/ssp.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/regs-ssp.h>
#include "sharpsl.h"
#include <asm/arch/irda.h>
#include <asm/arch/i2c.h>
#include <asm/arch/ohci.h>
+#include <asm/arch/pxa27x_keypad.h>
+#include <asm/arch/camera.h>
#include "devices.h"
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+static struct resource pxa27x_resource_keypad[] = {
+ [0] = {
+ .start = 0x41500000,
+ .end = 0x4150004c,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_KEYPAD,
+ .end = IRQ_KEYPAD,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device pxa27x_device_keypad = {
+ .name = "pxa27x-keypad",
+ .id = -1,
+ .resource = pxa27x_resource_keypad,
+ .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
+};
+
+void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
+{
+ pxa_register_device(&pxa27x_device_keypad, info);
+}
+
static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa27x_resource_ohci[] = {
.resource = pxa27x_resource_ssp3,
.num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
};
+
+static struct resource pxa27x_resource_camera[] = {
+ [0] = {
+ .start = 0x50000000,
+ .end = 0x50000fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_CAMERA,
+ .end = IRQ_CAMERA,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
+
+static struct platform_device pxa27x_device_camera = {
+ .name = "pxa27x-camera",
+ .id = 0, /* This is used to put cameras on this interface */
+ .dev = {
+ .dma_mask = &pxa27x_dma_mask_camera,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
+ .resource = pxa27x_resource_camera,
+};
+
+void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
+{
+ pxa_register_device(&pxa27x_device_camera, info);
+}
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
#ifdef CONFIG_PXA3xx
extern struct platform_device pxa27x_device_i2c_power;
extern struct platform_device pxa27x_device_ohci;
+extern struct platform_device pxa27x_device_keypad;
extern struct platform_device pxa25x_device_ssp;
extern struct platform_device pxa25x_device_nssp;
#include <asm/mach/arch.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/ohci.h>
#include <asm/arch/mmc.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/ioport.h>
-#include <linux/pm.h>
-#include <linux/string.h>
-#include <linux/sysdev.h>
#include <asm/hardware.h>
-#include <asm/irq.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
get_clk_frequency_khz(1);
}
-
-#ifdef CONFIG_PM
-
-static unsigned long saved_gplr[4];
-static unsigned long saved_gpdr[4];
-static unsigned long saved_grer[4];
-static unsigned long saved_gfer[4];
-
-static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
-{
- int i, gpio;
-
- for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
- saved_gplr[i] = GPLR(gpio);
- saved_gpdr[i] = GPDR(gpio);
- saved_grer[i] = GRER(gpio);
- saved_gfer[i] = GFER(gpio);
-
- /* Clear GPIO transition detect bits */
- GEDR(gpio) = GEDR(gpio);
- }
- return 0;
-}
-
-static int pxa_gpio_resume(struct sys_device *dev)
-{
- int i, gpio;
-
- for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
- /* restore level with set/clear */
- GPSR(gpio) = saved_gplr[i];
- GPCR(gpio) = ~saved_gplr[i];
-
- GRER(gpio) = saved_grer[i];
- GFER(gpio) = saved_gfer[i];
- GPDR(gpio) = saved_gpdr[i];
- }
- return 0;
-}
-#else
-#define pxa_gpio_suspend NULL
-#define pxa_gpio_resume NULL
-#endif
-
-struct sysdev_class pxa_gpio_sysclass = {
- .name = "gpio",
- .suspend = pxa_gpio_suspend,
- .resume = pxa_gpio_resume,
-};
-
-static int __init pxa_gpio_init(void)
-{
- return sysdev_class_register(&pxa_gpio_sysclass);
-}
-
-core_initcall(pxa_gpio_init);
* published by the Free Software Foundation.
*/
+typedef int (*set_wake_t)(unsigned int, unsigned int);
+
struct sys_timer;
extern struct sys_timer pxa_timer;
-extern void __init pxa_init_irq_low(void);
-extern void __init pxa_init_irq_high(void);
-extern void __init pxa_init_irq_gpio(int gpio_nr);
-extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int));
-extern void __init pxa_init_gpio(int gpio_nr);
+extern void __init pxa_init_irq(int irq_nr, set_wake_t fn);
+extern void __init pxa_init_gpio(int gpio_nr, set_wake_t fn);
extern void __init pxa25x_init_irq(void);
extern void __init pxa27x_init_irq(void);
extern void __init pxa3xx_init_irq(void);
mi->bank[__nr].size = (__size), \
mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
+#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
+
#ifdef CONFIG_PXA25x
extern unsigned pxa25x_get_clk_frequency_khz(int);
extern unsigned pxa25x_get_memclk_frequency_10khz(void);
extern struct sysdev_class pxa_irq_sysclass;
extern struct sysdev_class pxa_gpio_sysclass;
+extern struct sysdev_class pxa3xx_mfp_sysclass;
#include <linux/init.h>
#include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/sysdev.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include "generic.h"
__raw_writel(mask, pxa->regbase + GPCR_OFFSET);
}
+#define GPIO_CHIP(_n) \
+ [_n] = { \
+ .regbase = GPIO##_n##_BASE, \
+ .chip = { \
+ .label = "gpio-" #_n, \
+ .direction_input = pxa_gpio_direction_input, \
+ .direction_output = pxa_gpio_direction_output, \
+ .get = pxa_gpio_get, \
+ .set = pxa_gpio_set, \
+ .base = (_n) * 32, \
+ .ngpio = 32, \
+ }, \
+ }
+
static struct pxa_gpio_chip pxa_gpio_chip[] = {
- [0] = {
- .regbase = GPIO0_BASE,
- .chip = {
- .label = "gpio-0",
- .direction_input = pxa_gpio_direction_input,
- .direction_output = pxa_gpio_direction_output,
- .get = pxa_gpio_get,
- .set = pxa_gpio_set,
- .base = 0,
- .ngpio = 32,
- },
- },
- [1] = {
- .regbase = GPIO1_BASE,
- .chip = {
- .label = "gpio-1",
- .direction_input = pxa_gpio_direction_input,
- .direction_output = pxa_gpio_direction_output,
- .get = pxa_gpio_get,
- .set = pxa_gpio_set,
- .base = 32,
- .ngpio = 32,
- },
- },
- [2] = {
- .regbase = GPIO2_BASE,
- .chip = {
- .label = "gpio-2",
- .direction_input = pxa_gpio_direction_input,
- .direction_output = pxa_gpio_direction_output,
- .get = pxa_gpio_get,
- .set = pxa_gpio_set,
- .base = 64,
- .ngpio = 32, /* 21 for PXA25x */
- },
- },
+ GPIO_CHIP(0),
+ GPIO_CHIP(1),
+ GPIO_CHIP(2),
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
- [3] = {
- .regbase = GPIO3_BASE,
- .chip = {
- .label = "gpio-3",
- .direction_input = pxa_gpio_direction_input,
- .direction_output = pxa_gpio_direction_output,
- .get = pxa_gpio_get,
- .set = pxa_gpio_set,
- .base = 96,
- .ngpio = 32,
- },
- },
+ GPIO_CHIP(3),
#endif
};
-void __init pxa_init_gpio(int gpio_nr)
+/*
+ * PXA GPIO edge detection for IRQs:
+ * IRQs are generated on Falling-Edge, Rising-Edge, or both.
+ * Use this instead of directly setting GRER/GFER.
+ */
+
+static unsigned long GPIO_IRQ_rising_edge[4];
+static unsigned long GPIO_IRQ_falling_edge[4];
+static unsigned long GPIO_IRQ_mask[4];
+
+/*
+ * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
+ * function of a GPIO, and GPDRx cannot be altered once configured. It
+ * is attributed as "occupied" here (I know this terminology isn't
+ * accurate, you are welcome to propose a better one :-)
+ */
+static int __gpio_is_occupied(unsigned gpio)
+{
+ if (cpu_is_pxa25x() || cpu_is_pxa27x())
+ return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2));
+ else
+ return 0;
+}
+
+static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
+{
+ int gpio, idx;
+
+ gpio = IRQ_TO_GPIO(irq);
+ idx = gpio >> 5;
+
+ if (type == IRQ_TYPE_PROBE) {
+ /* Don't mess with enabled GPIOs using preconfigured edges or
+ * GPIOs set to alternate function or to output during probe
+ */
+ if ((GPIO_IRQ_rising_edge[idx] |
+ GPIO_IRQ_falling_edge[idx] |
+ GPDR(gpio)) & GPIO_bit(gpio))
+ return 0;
+
+ if (__gpio_is_occupied(gpio))
+ return 0;
+
+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+ }
+
+ GPDR(gpio) &= ~GPIO_bit(gpio);
+
+ if (type & IRQ_TYPE_EDGE_RISING)
+ __set_bit(gpio, GPIO_IRQ_rising_edge);
+ else
+ __clear_bit(gpio, GPIO_IRQ_rising_edge);
+
+ if (type & IRQ_TYPE_EDGE_FALLING)
+ __set_bit(gpio, GPIO_IRQ_falling_edge);
+ else
+ __clear_bit(gpio, GPIO_IRQ_falling_edge);
+
+ GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
+ GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
+
+ pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
+ ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
+ ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
+ return 0;
+}
+
+/*
+ * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
+ */
+
+static void pxa_ack_low_gpio(unsigned int irq)
+{
+ GEDR0 = (1 << (irq - IRQ_GPIO0));
+}
+
+static void pxa_mask_low_gpio(unsigned int irq)
+{
+ ICMR &= ~(1 << (irq - PXA_IRQ(0)));
+}
+
+static void pxa_unmask_low_gpio(unsigned int irq)
+{
+ ICMR |= 1 << (irq - PXA_IRQ(0));
+}
+
+static struct irq_chip pxa_low_gpio_chip = {
+ .name = "GPIO-l",
+ .ack = pxa_ack_low_gpio,
+ .mask = pxa_mask_low_gpio,
+ .unmask = pxa_unmask_low_gpio,
+ .set_type = pxa_gpio_irq_type,
+};
+
+/*
+ * Demux handler for GPIO>=2 edge detect interrupts
+ */
+
+#define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
+
+static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
+{
+ int loop, bit, n;
+ unsigned long gedr[4];
+
+ do {
+ gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
+ gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
+ gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
+ gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
+
+ GEDR0 = gedr[0]; GEDR1 = gedr[1];
+ GEDR2 = gedr[2]; GEDR3 = gedr[3];
+
+ loop = 0;
+ bit = find_first_bit(gedr, GEDR_BITS);
+ while (bit < GEDR_BITS) {
+ loop = 1;
+
+ n = PXA_GPIO_IRQ_BASE + bit;
+ desc_handle_irq(n, irq_desc + n);
+
+ bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
+ }
+ } while (loop);
+}
+
+static void pxa_ack_muxed_gpio(unsigned int irq)
+{
+ int gpio = irq - IRQ_GPIO(2) + 2;
+ GEDR(gpio) = GPIO_bit(gpio);
+}
+
+static void pxa_mask_muxed_gpio(unsigned int irq)
+{
+ int gpio = irq - IRQ_GPIO(2) + 2;
+ __clear_bit(gpio, GPIO_IRQ_mask);
+ GRER(gpio) &= ~GPIO_bit(gpio);
+ GFER(gpio) &= ~GPIO_bit(gpio);
+}
+
+static void pxa_unmask_muxed_gpio(unsigned int irq)
+{
+ int gpio = irq - IRQ_GPIO(2) + 2;
+ int idx = gpio >> 5;
+ __set_bit(gpio, GPIO_IRQ_mask);
+ GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
+ GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
+}
+
+static struct irq_chip pxa_muxed_gpio_chip = {
+ .name = "GPIO",
+ .ack = pxa_ack_muxed_gpio,
+ .mask = pxa_mask_muxed_gpio,
+ .unmask = pxa_unmask_muxed_gpio,
+ .set_type = pxa_gpio_irq_type,
+};
+
+void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
{
- int i;
+ int irq, i, gpio;
+
+ pxa_last_gpio = gpio_nr - 1;
+
+ /* clear all GPIO edge detects */
+ for (i = 0; i < gpio_nr; i += 32) {
+ GFER(i) = 0;
+ GRER(i) = 0;
+ GEDR(i) = GEDR(i);
+ }
+
+ /* GPIO 0 and 1 must have their mask bit always set */
+ GPIO_IRQ_mask[0] = 3;
+
+ for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
+ set_irq_chip(irq, &pxa_low_gpio_chip);
+ set_irq_handler(irq, handle_edge_irq);
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+ }
+
+ for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
+ set_irq_chip(irq, &pxa_muxed_gpio_chip);
+ set_irq_handler(irq, handle_edge_irq);
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+ }
+
+ /* Install handler for GPIO>=2 edge detect interrupts */
+ set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
+
+ pxa_low_gpio_chip.set_wake = fn;
+ pxa_muxed_gpio_chip.set_wake = fn;
/* add a GPIO chip for each register bank.
* the last PXA25x register only contains 21 GPIOs
*/
- for (i = 0; i < gpio_nr; i += 32) {
- if (i+32 > gpio_nr)
- pxa_gpio_chip[i/32].chip.ngpio = gpio_nr - i;
- gpiochip_add(&pxa_gpio_chip[i/32].chip);
+ for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
+ if (gpio + 32 > gpio_nr)
+ pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
+ gpiochip_add(&pxa_gpio_chip[i].chip);
}
}
+
+#ifdef CONFIG_PM
+
+static unsigned long saved_gplr[4];
+static unsigned long saved_gpdr[4];
+static unsigned long saved_grer[4];
+static unsigned long saved_gfer[4];
+
+static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
+{
+ int i, gpio;
+
+ for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
+ saved_gplr[i] = GPLR(gpio);
+ saved_gpdr[i] = GPDR(gpio);
+ saved_grer[i] = GRER(gpio);
+ saved_gfer[i] = GFER(gpio);
+
+ /* Clear GPIO transition detect bits */
+ GEDR(gpio) = GEDR(gpio);
+ }
+ return 0;
+}
+
+static int pxa_gpio_resume(struct sys_device *dev)
+{
+ int i, gpio;
+
+ for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
+ /* restore level with set/clear */
+ GPSR(gpio) = saved_gplr[i];
+ GPCR(gpio) = ~saved_gplr[i];
+
+ GRER(gpio) = saved_grer[i];
+ GFER(gpio) = saved_gfer[i];
+ GPDR(gpio) = saved_gpdr[i];
+ }
+ return 0;
+}
+#else
+#define pxa_gpio_suspend NULL
+#define pxa_gpio_resume NULL
+#endif
+
+struct sysdev_class pxa_gpio_sysclass = {
+ .name = "gpio",
+ .suspend = pxa_gpio_suspend,
+ .resume = pxa_gpio_resume,
+};
+
+static int __init pxa_gpio_init(void)
+{
+ return sysdev_class_register(&pxa_gpio_sysclass);
+}
+
+core_initcall(pxa_gpio_init);
--- /dev/null
+/*
+ * linux/arch/arm/mach-pxa/gumstix.c
+ *
+ * Support for the Gumstix motherboards.
+ *
+ * Original Author: Craig Hughes
+ * Created: Feb 14, 2008
+ * Copyright: Craig Hughes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Implemented based on lubbock.c by Nicolas Pitre and code from Craig
+ * Hughes
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/flash.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/udc.h>
+#include <asm/arch/gumstix.h>
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
+
+#include "generic.h"
+
+static struct resource flash_resource = {
+ .start = 0x00000000,
+ .end = SZ_64M - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct mtd_partition gumstix_partitions[] = {
+ {
+ .name = "Bootloader",
+ .size = 0x00040000,
+ .offset = 0,
+ .mask_flags = MTD_WRITEABLE /* force read-only */
+ } , {
+ .name = "rootfs",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND
+ }
+};
+
+static struct flash_platform_data gumstix_flash_data = {
+ .map_name = "cfi_probe",
+ .parts = gumstix_partitions,
+ .nr_parts = ARRAY_SIZE(gumstix_partitions),
+ .width = 2,
+};
+
+static struct platform_device gumstix_flash_device = {
+ .name = "pxa2xx-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &gumstix_flash_data,
+ },
+ .resource = &flash_resource,
+ .num_resources = 1,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &gumstix_flash_device,
+};
+
+#ifdef CONFIG_MMC_PXA
+static struct pxamci_platform_data gumstix_mci_platform_data;
+
+static int gumstix_mci_init(struct device *dev, irq_handler_t detect_int,
+ void *data)
+{
+ pxa_gpio_mode(GPIO6_MMCCLK_MD);
+ pxa_gpio_mode(GPIO53_MMCCLK_MD);
+ pxa_gpio_mode(GPIO8_MMCCS0_MD);
+
+ return 0;
+}
+
+static struct pxamci_platform_data gumstix_mci_platform_data = {
+ .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
+ .init = gumstix_mci_init,
+};
+
+static void __init gumstix_mmc_init(void)
+{
+ pxa_set_mci_info(&gumstix_mci_platform_data);
+}
+#else
+static void __init gumstix_mmc_init(void)
+{
+ printk(KERN_INFO "Gumstix mmc disabled\n");
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET_PXA2XX
+static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = {
+ .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn,
+ .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx,
+};
+
+static void __init gumstix_udc_init(void)
+{
+ pxa_set_udc_info(&gumstix_udc_info);
+}
+#else
+static void gumstix_udc_init(void)
+{
+ printk(KERN_INFO "Gumstix udc is disabled\n");
+}
+#endif
+
+static void __init gumstix_init(void)
+{
+ gumstix_udc_init();
+ gumstix_mmc_init();
+ (void) platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+MACHINE_START(GUMSTIX, "Gumstix")
+ .phys_io = 0x40000000,
+ .boot_params = 0xa0000100, /* match u-boot bi_boot_params */
+ .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
+ .map_io = pxa_map_io,
+ .init_irq = pxa25x_init_irq,
+ .timer = &pxa_timer,
+ .init_machine = gumstix_init,
+MACHINE_END
#include <asm/mach/map.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/idp.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/bitfield.h>
/*
* linux/arch/arm/mach-pxa/irq.c
*
- * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
+ * Generic PXA IRQ handling
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include "generic.h"
+#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
+#define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
+#define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
/*
* This is for peripheral IRQs internal to the PXA chip.
*/
-static void pxa_mask_low_irq(unsigned int irq)
+static int pxa_internal_irq_nr;
+
+static void pxa_mask_irq(unsigned int irq)
{
- ICMR &= ~(1 << irq);
+ _ICMR(irq) &= ~(1 << IRQ_BIT(irq));
}
-static void pxa_unmask_low_irq(unsigned int irq)
+static void pxa_unmask_irq(unsigned int irq)
{
- ICMR |= (1 << irq);
+ _ICMR(irq) |= 1 << IRQ_BIT(irq);
}
-static struct irq_chip pxa_internal_chip_low = {
+static struct irq_chip pxa_internal_irq_chip = {
.name = "SC",
- .ack = pxa_mask_low_irq,
- .mask = pxa_mask_low_irq,
- .unmask = pxa_unmask_low_irq,
+ .ack = pxa_mask_irq,
+ .mask = pxa_mask_irq,
+ .unmask = pxa_unmask_irq,
};
-void __init pxa_init_irq_low(void)
+void __init pxa_init_irq(int irq_nr, set_wake_t fn)
{
int irq;
- /* disable all IRQs */
- ICMR = 0;
+ pxa_internal_irq_nr = irq_nr;
- /* all IRQs are IRQ, not FIQ */
- ICLR = 0;
+ for (irq = 0; irq < irq_nr; irq += 32) {
+ _ICMR(irq) = 0; /* disable all IRQs */
+ _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
+ }
/* only unmasked interrupts kick us out of idle */
ICCR = 1;
- for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) {
- set_irq_chip(irq, &pxa_internal_chip_low);
- set_irq_handler(irq, handle_level_irq);
- set_irq_flags(irq, IRQF_VALID);
- }
-}
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-
-/*
- * This is for the second set of internal IRQs as found on the PXA27x.
- */
-
-static void pxa_mask_high_irq(unsigned int irq)
-{
- ICMR2 &= ~(1 << (irq - 32));
-}
-
-static void pxa_unmask_high_irq(unsigned int irq)
-{
- ICMR2 |= (1 << (irq - 32));
-}
-
-static struct irq_chip pxa_internal_chip_high = {
- .name = "SC-hi",
- .ack = pxa_mask_high_irq,
- .mask = pxa_mask_high_irq,
- .unmask = pxa_unmask_high_irq,
-};
-
-void __init pxa_init_irq_high(void)
-{
- int irq;
-
- ICMR2 = 0;
- ICLR2 = 0;
-
- for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) {
- set_irq_chip(irq, &pxa_internal_chip_high);
+ for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
+ set_irq_chip(irq, &pxa_internal_irq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
-}
-#endif
-
-/*
- * PXA GPIO edge detection for IRQs:
- * IRQs are generated on Falling-Edge, Rising-Edge, or both.
- * Use this instead of directly setting GRER/GFER.
- */
-
-static long GPIO_IRQ_rising_edge[4];
-static long GPIO_IRQ_falling_edge[4];
-static long GPIO_IRQ_mask[4];
-
-static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
-{
- int gpio, idx;
-
- gpio = IRQ_TO_GPIO(irq);
- idx = gpio >> 5;
-
- if (type == IRQT_PROBE) {
- /* Don't mess with enabled GPIOs using preconfigured edges or
- GPIOs set to alternate function or to output during probe */
- if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
- GPIO_bit(gpio))
- return 0;
- if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
- return 0;
- type = __IRQT_RISEDGE | __IRQT_FALEDGE;
- }
-
- /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
-
- pxa_gpio_mode(gpio | GPIO_IN);
-
- if (type & __IRQT_RISEDGE) {
- /* printk("rising "); */
- __set_bit (gpio, GPIO_IRQ_rising_edge);
- } else {
- __clear_bit (gpio, GPIO_IRQ_rising_edge);
- }
-
- if (type & __IRQT_FALEDGE) {
- /* printk("falling "); */
- __set_bit (gpio, GPIO_IRQ_falling_edge);
- } else {
- __clear_bit (gpio, GPIO_IRQ_falling_edge);
- }
-
- /* printk("edges\n"); */
-
- GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
- GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
- return 0;
-}
-
-/*
- * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
- */
-
-static void pxa_ack_low_gpio(unsigned int irq)
-{
- GEDR0 = (1 << (irq - IRQ_GPIO0));
-}
-
-static struct irq_chip pxa_low_gpio_chip = {
- .name = "GPIO-l",
- .ack = pxa_ack_low_gpio,
- .mask = pxa_mask_low_irq,
- .unmask = pxa_unmask_low_irq,
- .set_type = pxa_gpio_irq_type,
-};
-
-/*
- * Demux handler for GPIO>=2 edge detect interrupts
- */
-
-static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
-{
- unsigned int mask;
- int loop;
-
- do {
- loop = 0;
-
- mask = GEDR0 & GPIO_IRQ_mask[0] & ~3;
- if (mask) {
- GEDR0 = mask;
- irq = IRQ_GPIO(2);
- desc = irq_desc + irq;
- mask >>= 2;
- do {
- if (mask & 1)
- desc_handle_irq(irq, desc);
- irq++;
- desc++;
- mask >>= 1;
- } while (mask);
- loop = 1;
- }
-
- mask = GEDR1 & GPIO_IRQ_mask[1];
- if (mask) {
- GEDR1 = mask;
- irq = IRQ_GPIO(32);
- desc = irq_desc + irq;
- do {
- if (mask & 1)
- desc_handle_irq(irq, desc);
- irq++;
- desc++;
- mask >>= 1;
- } while (mask);
- loop = 1;
- }
-
- mask = GEDR2 & GPIO_IRQ_mask[2];
- if (mask) {
- GEDR2 = mask;
- irq = IRQ_GPIO(64);
- desc = irq_desc + irq;
- do {
- if (mask & 1)
- desc_handle_irq(irq, desc);
- irq++;
- desc++;
- mask >>= 1;
- } while (mask);
- loop = 1;
- }
-
- mask = GEDR3 & GPIO_IRQ_mask[3];
- if (mask) {
- GEDR3 = mask;
- irq = IRQ_GPIO(96);
- desc = irq_desc + irq;
- do {
- if (mask & 1)
- desc_handle_irq(irq, desc);
- irq++;
- desc++;
- mask >>= 1;
- } while (mask);
- loop = 1;
- }
- } while (loop);
-}
-
-static void pxa_ack_muxed_gpio(unsigned int irq)
-{
- int gpio = irq - IRQ_GPIO(2) + 2;
- GEDR(gpio) = GPIO_bit(gpio);
-}
-
-static void pxa_mask_muxed_gpio(unsigned int irq)
-{
- int gpio = irq - IRQ_GPIO(2) + 2;
- __clear_bit(gpio, GPIO_IRQ_mask);
- GRER(gpio) &= ~GPIO_bit(gpio);
- GFER(gpio) &= ~GPIO_bit(gpio);
-}
-
-static void pxa_unmask_muxed_gpio(unsigned int irq)
-{
- int gpio = irq - IRQ_GPIO(2) + 2;
- int idx = gpio >> 5;
- __set_bit(gpio, GPIO_IRQ_mask);
- GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
- GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
-}
-
-static struct irq_chip pxa_muxed_gpio_chip = {
- .name = "GPIO",
- .ack = pxa_ack_muxed_gpio,
- .mask = pxa_mask_muxed_gpio,
- .unmask = pxa_unmask_muxed_gpio,
- .set_type = pxa_gpio_irq_type,
-};
-
-void __init pxa_init_irq_gpio(int gpio_nr)
-{
- int irq, i;
-
- pxa_last_gpio = gpio_nr - 1;
-
- /* clear all GPIO edge detects */
- for (i = 0; i < gpio_nr; i += 32) {
- GFER(i) = 0;
- GRER(i) = 0;
- GEDR(i) = GEDR(i);
- }
-
- /* GPIO 0 and 1 must have their mask bit always set */
- GPIO_IRQ_mask[0] = 3;
-
- for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
- set_irq_chip(irq, &pxa_low_gpio_chip);
- set_irq_handler(irq, handle_edge_irq);
- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
- }
- for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
- set_irq_chip(irq, &pxa_muxed_gpio_chip);
- set_irq_handler(irq, handle_edge_irq);
- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
- }
-
- /* Install handler for GPIO>=2 edge detect interrupts */
- set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
- set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
-
- pxa_init_gpio(gpio_nr);
-}
-
-void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
-{
- pxa_internal_chip_low.set_wake = set_wake;
-#ifdef CONFIG_PXA27x
- pxa_internal_chip_high.set_wake = set_wake;
-#endif
- pxa_low_gpio_chip.set_wake = set_wake;
- pxa_muxed_gpio_chip.set_wake = set_wake;
+ pxa_internal_irq_chip.set_wake = fn;
}
#ifdef CONFIG_PM
static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
{
- switch (dev->id) {
- case 0:
- saved_icmr[0] = ICMR;
- ICMR = 0;
- break;
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
- case 1:
- saved_icmr[1] = ICMR2;
- ICMR2 = 0;
- break;
-#endif
- default:
- return -EINVAL;
+ int i, irq = PXA_IRQ(0);
+
+ for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
+ saved_icmr[i] = _ICMR(irq);
+ _ICMR(irq) = 0;
}
return 0;
static int pxa_irq_resume(struct sys_device *dev)
{
- switch (dev->id) {
- case 0:
- ICMR = saved_icmr[0];
- ICLR = 0;
- ICCR = 1;
- break;
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
- case 1:
- ICMR2 = saved_icmr[1];
- ICLR2 = 0;
- break;
-#endif
- default:
- return -EINVAL;
+ int i, irq = PXA_IRQ(0);
+
+ for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
+ _ICMR(irq) = saved_icmr[i];
+ _ICLR(irq) = 0;
}
+ ICCR = 1;
return 0;
}
#else
#include <asm/leds.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/trizeps4.h>
#include "leds.h"
#include <asm/arch/gpio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/ssp.h>
+#include <asm/arch/pxa27x_keypad.h>
#include <asm/arch/littleton.h>
#include "generic.h"
-#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
-
/* Littleton MFP configurations */
static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
/* LCD */
/* Debug Ethernet */
GPIO90_GPIO,
+
+ /* Keypad */
+ GPIO107_KP_DKIN_0,
+ GPIO108_KP_DKIN_1,
+ GPIO115_KP_MKIN_0,
+ GPIO116_KP_MKIN_1,
+ GPIO117_KP_MKIN_2,
+ GPIO118_KP_MKIN_3,
+ GPIO119_KP_MKIN_4,
+ GPIO120_KP_MKIN_5,
+ GPIO121_KP_MKOUT_0,
+ GPIO122_KP_MKOUT_1,
+ GPIO123_KP_MKOUT_2,
+ GPIO124_KP_MKOUT_3,
+ GPIO125_KP_MKOUT_4,
};
static struct resource smc91x_resources[] = {
static inline void littleton_init_lcd(void) {};
#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
+static unsigned int littleton_matrix_key_map[] = {
+ /* KEY(row, col, key_code) */
+ KEY(1, 3, KEY_0), KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3),
+ KEY(0, 1, KEY_4), KEY(1, 1, KEY_5), KEY(2, 1, KEY_6), KEY(0, 2, KEY_7),
+ KEY(1, 2, KEY_8), KEY(2, 2, KEY_9),
+
+ KEY(0, 3, KEY_KPASTERISK), /* * */
+ KEY(2, 3, KEY_KPDOT), /* # */
+
+ KEY(5, 4, KEY_ENTER),
+
+ KEY(5, 0, KEY_UP),
+ KEY(5, 1, KEY_DOWN),
+ KEY(5, 2, KEY_LEFT),
+ KEY(5, 3, KEY_RIGHT),
+ KEY(3, 2, KEY_HOME),
+ KEY(4, 1, KEY_END),
+ KEY(3, 3, KEY_BACK),
+
+ KEY(4, 0, KEY_SEND),
+ KEY(4, 2, KEY_VOLUMEUP),
+ KEY(4, 3, KEY_VOLUMEDOWN),
+
+ KEY(3, 0, KEY_F22), /* soft1 */
+ KEY(3, 1, KEY_F23), /* soft2 */
+};
+
+static struct pxa27x_keypad_platform_data littleton_keypad_info = {
+ .matrix_key_rows = 6,
+ .matrix_key_cols = 5,
+ .matrix_key_map = littleton_matrix_key_map,
+ .matrix_key_map_size = ARRAY_SIZE(littleton_matrix_key_map),
+
+ .enable_rotary0 = 1,
+ .rotary0_up_key = KEY_UP,
+ .rotary0_down_key = KEY_DOWN,
+
+ .debounce_interval = 30,
+};
+static void __init littleton_init_keypad(void)
+{
+ pxa_set_keypad_info(&littleton_keypad_info);
+}
+#else
+static inline void littleton_init_keypad(void) {}
+#endif
+
static void __init littleton_init(void)
{
/* initialize MFP configurations */
platform_device_register(&smc91x_device);
littleton_init_lcd();
+ littleton_init_keypad();
}
MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/lpd270.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa25x.h>
#include <asm/arch/lubbock.h>
#include <asm/arch/udc.h>
#include <asm/arch/irda.h>
#include "generic.h"
#include "devices.h"
+static unsigned long lubbock_pin_config[] __initdata = {
+ GPIO15_nCS_1, /* CS1 - Flash */
+ GPIO79_nCS_3, /* CS3 - SMC ethernet */
+
+ /* SSP data pins */
+ GPIO23_SSP1_SCLK,
+ GPIO25_SSP1_TXD,
+ GPIO26_SSP1_RXD,
+
+ /* BTUART */
+ GPIO42_BTUART_RXD,
+ GPIO43_BTUART_TXD,
+ GPIO44_BTUART_CTS,
+ GPIO45_BTUART_RTS,
+
+ /* PC Card */
+ GPIO48_nPOE,
+ GPIO49_nPWE,
+ GPIO50_nPIOR,
+ GPIO51_nPIOW,
+ GPIO52_nPCE_1,
+ GPIO53_nPCE_2,
+ GPIO54_nPSKTSEL,
+ GPIO55_nPREG,
+ GPIO56_nPWAIT,
+ GPIO57_nIOIS16,
+
+ /* MMC */
+ GPIO6_MMC_CLK,
+ GPIO8_MMC_CS0,
+
+ /* wakeup */
+ GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
+};
#define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
.resource = sa1111_resources,
};
-static struct resource smc91x_resources[] = {
- [0] = {
- .name = "smc91x-regs",
- .start = 0x0c000c00,
- .end = 0x0c0fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = LUBBOCK_ETH_IRQ,
- .end = LUBBOCK_ETH_IRQ,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
- [2] = {
- .name = "smc91x-attrib",
- .start = 0x0e000000,
- .end = 0x0e0fffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
/* ADS7846 is connected through SSP ... and if your board has J5 populated,
* you can select it to replace the ucb1400 by switching the touchscreen cable
* (to J5) and poking board registers (as done below). Else it's only useful
},
};
+static struct resource smc91x_resources[] = {
+ [0] = {
+ .name = "smc91x-regs",
+ .start = 0x0c000c00,
+ .end = 0x0c0fffff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = LUBBOCK_ETH_IRQ,
+ .end = LUBBOCK_ETH_IRQ,
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+ },
+ [2] = {
+ .name = "smc91x-attrib",
+ .start = 0x0e000000,
+ .end = 0x0e0fffff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = -1,
irq_handler_t detect_int,
void *data)
{
- /* setup GPIO for PXA25x MMC controller */
- pxa_gpio_mode(GPIO6_MMCCLK_MD);
- pxa_gpio_mode(GPIO8_MMCCS0_MD);
-
/* detect card insert/eject */
mmc_detect_int = detect_int;
init_timer(&mmc_timer);
{
int flashboot = (LUB_CONF_SWITCHES & 1);
+ pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config));
+
pxa_set_udc_info(&udc_info);
set_pxa_fb_info(&sharp_lm8v31);
pxa_set_mci_info(&lubbock_mci_platform_data);
pxa_map_io();
iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
- /* SSP data pins */
- pxa_gpio_mode(GPIO23_SCLK_MD);
- pxa_gpio_mode(GPIO25_STXD_MD);
- pxa_gpio_mode(GPIO26_SRXD_MD);
-
- /* This enables the BTUART */
- pxa_gpio_mode(GPIO42_BTRXD_MD);
- pxa_gpio_mode(GPIO43_BTTXD_MD);
- pxa_gpio_mode(GPIO44_BTCTS_MD);
- pxa_gpio_mode(GPIO45_BTRTS_MD);
-
- GPSR(GPIO48_nPOE) =
- GPIO_bit(GPIO48_nPOE) |
- GPIO_bit(GPIO49_nPWE) |
- GPIO_bit(GPIO50_nPIOR) |
- GPIO_bit(GPIO51_nPIOW) |
- GPIO_bit(GPIO52_nPCE_1) |
- GPIO_bit(GPIO53_nPCE_2);
-
- pxa_gpio_mode(GPIO48_nPOE_MD);
- pxa_gpio_mode(GPIO49_nPWE_MD);
- pxa_gpio_mode(GPIO50_nPIOR_MD);
- pxa_gpio_mode(GPIO51_nPIOW_MD);
- pxa_gpio_mode(GPIO52_nPCE_1_MD);
- pxa_gpio_mode(GPIO53_nPCE_2_MD);
- pxa_gpio_mode(GPIO54_pSKTSEL_MD);
- pxa_gpio_mode(GPIO55_nPREG_MD);
- pxa_gpio_mode(GPIO56_nPWAIT_MD);
- pxa_gpio_mode(GPIO57_nIOIS16_MD);
-
- /* This is for the SMC chip select */
- pxa_gpio_mode(GPIO79_nCS_3_MD);
-
- /* setup sleep mode values */
- PWER = 0x00000002;
- PFER = 0x00000000;
- PRER = 0x00000002;
- PGSR0 = 0x00008000;
- PGSR1 = 0x003F0202;
- PGSR2 = 0x0001C000;
PCFR |= PCFR_OPDE;
}
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/delay.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
+#include <linux/mfd/htc-egpio.h>
+#include <linux/mfd/htc-pasic3.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/physmap.h>
+#include <linux/pda_power.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/arch/magician.h>
+#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxafb.h>
+#include <asm/arch/i2c.h>
+#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/ohci.h>
#include "generic.h"
+static unsigned long magician_pin_config[] = {
+
+ /* SDRAM and Static Memory I/O Signals */
+ GPIO20_nSDCS_2,
+ GPIO21_nSDCS_3,
+ GPIO15_nCS_1,
+ GPIO78_nCS_2, /* PASIC3 */
+ GPIO79_nCS_3, /* EGPIO CPLD */
+ GPIO80_nCS_4,
+ GPIO33_nCS_5,
+
+ /* I2C */
+ GPIO117_I2C_SCL,
+ GPIO118_I2C_SDA,
+
+ /* PWM 0 */
+ GPIO16_PWM0_OUT,
+
+ /* I2S */
+ GPIO28_I2S_BITCLK_OUT,
+ GPIO29_I2S_SDATA_IN,
+ GPIO31_I2S_SYNC,
+ GPIO113_I2S_SYSCLK,
+
+ /* SSP 2 */
+ GPIO19_SSP2_SCLK,
+ GPIO14_SSP2_SFRM,
+ GPIO89_SSP2_TXD,
+ GPIO88_SSP2_RXD,
+
+ /* MMC */
+ GPIO32_MMC_CLK,
+ GPIO92_MMC_DAT_0,
+ GPIO109_MMC_DAT_1,
+ GPIO110_MMC_DAT_2,
+ GPIO111_MMC_DAT_3,
+ GPIO112_MMC_CMD,
+
+ /* LCD */
+ GPIO58_LCD_LDD_0,
+ GPIO59_LCD_LDD_1,
+ GPIO60_LCD_LDD_2,
+ GPIO61_LCD_LDD_3,
+ GPIO62_LCD_LDD_4,
+ GPIO63_LCD_LDD_5,
+ GPIO64_LCD_LDD_6,
+ GPIO65_LCD_LDD_7,
+ GPIO66_LCD_LDD_8,
+ GPIO67_LCD_LDD_9,
+ GPIO68_LCD_LDD_10,
+ GPIO69_LCD_LDD_11,
+ GPIO70_LCD_LDD_12,
+ GPIO71_LCD_LDD_13,
+ GPIO72_LCD_LDD_14,
+ GPIO73_LCD_LDD_15,
+ GPIO74_LCD_FCLK,
+ GPIO75_LCD_LCLK,
+ GPIO76_LCD_PCLK,
+ GPIO77_LCD_BIAS,
+
+ /* QCI */
+ GPIO12_CIF_DD_7,
+ GPIO17_CIF_DD_6,
+ GPIO50_CIF_DD_3,
+ GPIO51_CIF_DD_2,
+ GPIO52_CIF_DD_4,
+ GPIO53_CIF_MCLK,
+ GPIO54_CIF_PCLK,
+ GPIO55_CIF_DD_1,
+ GPIO81_CIF_DD_0,
+ GPIO82_CIF_DD_5,
+ GPIO84_CIF_FV,
+ GPIO85_CIF_LV,
+};
+
/*
* IRDA
*/
.id = -1,
};
+
+/*
+ * EGPIO (Xilinx CPLD)
+ *
+ * 7 32-bit aligned 8-bit registers: 3x output, 1x irq, 3x input
+ */
+
+static struct resource egpio_resources[] = {
+ [0] = {
+ .start = PXA_CS3_PHYS,
+ .end = PXA_CS3_PHYS + 0x20,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+ .end = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct htc_egpio_chip egpio_chips[] = {
+ [0] = {
+ .reg_start = 0,
+ .gpio_base = MAGICIAN_EGPIO(0, 0),
+ .num_gpios = 24,
+ .direction = HTC_EGPIO_OUTPUT,
+ .initial_values = 0x40, /* EGPIO_MAGICIAN_GSM_RESET */
+ },
+ [1] = {
+ .reg_start = 4,
+ .gpio_base = MAGICIAN_EGPIO(4, 0),
+ .num_gpios = 24,
+ .direction = HTC_EGPIO_INPUT,
+ },
+};
+
+static struct htc_egpio_platform_data egpio_info = {
+ .reg_width = 8,
+ .bus_width = 32,
+ .irq_base = IRQ_BOARD_START,
+ .num_irqs = 4,
+ .ack_register = 3,
+ .chip = egpio_chips,
+ .num_chips = ARRAY_SIZE(egpio_chips),
+};
+
+static struct platform_device egpio = {
+ .name = "htc-egpio",
+ .id = -1,
+ .resource = egpio_resources,
+ .num_resources = ARRAY_SIZE(egpio_resources),
+ .dev = {
+ .platform_data = &egpio_info,
+ },
+};
+
/*
- * LCD - Toppoly TD028STEB1
+ * LCD - Toppoly TD028STEB1 or Samsung LTP280QV
*/
static struct pxafb_mode_info toppoly_modes[] = {
},
};
+static struct pxafb_mode_info samsung_modes[] = {
+ {
+ .pixclock = 96153,
+ .bpp = 16,
+ .xres = 240,
+ .yres = 320,
+ .hsync_len = 8,
+ .vsync_len = 4,
+ .left_margin = 9,
+ .upper_margin = 4,
+ .right_margin = 9,
+ .lower_margin = 4,
+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ },
+};
+
+static void toppoly_lcd_power(int on, struct fb_var_screeninfo *si)
+{
+ pr_debug("Toppoly LCD power\n");
+
+ if (on) {
+ pr_debug("on\n");
+ gpio_set_value(EGPIO_MAGICIAN_TOPPOLY_POWER, 1);
+ gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 1);
+ udelay(2000);
+ gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 1);
+ udelay(2000);
+ /* FIXME: enable LCDC here */
+ udelay(2000);
+ gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 1);
+ udelay(2000);
+ gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 1);
+ } else {
+ pr_debug("off\n");
+ msleep(15);
+ gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 0);
+ udelay(500);
+ gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 0);
+ udelay(1000);
+ gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 0);
+ gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 0);
+ }
+}
+
+static void samsung_lcd_power(int on, struct fb_var_screeninfo *si)
+{
+ pr_debug("Samsung LCD power\n");
+
+ if (on) {
+ pr_debug("on\n");
+ if (system_rev < 3)
+ gpio_set_value(GPIO75_MAGICIAN_SAMSUNG_POWER, 1);
+ else
+ gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 1);
+ mdelay(10);
+ gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 1);
+ mdelay(10);
+ gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 1);
+ mdelay(30);
+ gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 1);
+ mdelay(10);
+ } else {
+ pr_debug("off\n");
+ mdelay(10);
+ gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 0);
+ mdelay(30);
+ gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 0);
+ mdelay(10);
+ gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 0);
+ mdelay(10);
+ if (system_rev < 3)
+ gpio_set_value(GPIO75_MAGICIAN_SAMSUNG_POWER, 0);
+ else
+ gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 0);
+ }
+}
+
static struct pxafb_mach_info toppoly_info = {
- .modes = toppoly_modes,
- .num_modes = 1,
- .fixed_modes = 1,
- .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
- .lccr3 = LCCR3_PixRsEdg,
+ .modes = toppoly_modes,
+ .num_modes = 1,
+ .fixed_modes = 1,
+ .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+ .lccr3 = LCCR3_PixRsEdg,
+ .pxafb_lcd_power = toppoly_lcd_power,
+};
+
+static struct pxafb_mach_info samsung_info = {
+ .modes = samsung_modes,
+ .num_modes = 1,
+ .fixed_modes = 1,
+ .lccr0 = LCCR0_LDDALT | LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+ .lccr3 = LCCR3_PixFlEdg,
+ .pxafb_lcd_power = samsung_lcd_power,
};
/*
if (intensity) {
PWM_CTRL0 = 1;
PWM_PERVAL0 = 0xc8;
- PWM_PWDUTY0 = intensity;
+ if (intensity > 0xc7) {
+ PWM_PWDUTY0 = intensity - 0x48;
+ gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
+ } else {
+ PWM_PWDUTY0 = intensity;
+ gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
+ }
+ gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 1);
pxa_set_cken(CKEN_PWM0, 1);
} else {
+ /* PWM_PWDUTY0 = intensity; */
+ gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 0);
pxa_set_cken(CKEN_PWM0, 0);
}
}
static struct generic_bl_info backlight_info = {
.default_intensity = 0x64,
.limit_mask = 0x0b,
- .max_intensity = 0xc7,
+ .max_intensity = 0xc7+0x48,
.set_bl_intensity = magician_set_bl_intensity,
};
static struct platform_device backlight = {
- .name = "corgi-bl",
+ .name = "generic-bl",
.dev = {
.platform_data = &backlight_info,
},
.id = -1,
};
+/*
+ * LEDs
+ */
+
+struct gpio_led gpio_leds[] = {
+ {
+ .name = "magician::vibra",
+ .default_trigger = "none",
+ .gpio = GPIO22_MAGICIAN_VIBRA_EN,
+ },
+ {
+ .name = "magician::phone_bl",
+ .default_trigger = "none",
+ .gpio = GPIO103_MAGICIAN_LED_KP,
+ },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+ .leds = gpio_leds,
+ .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &gpio_led_info,
+ },
+};
+
+static struct pasic3_led pasic3_leds[] = {
+ {
+ .led = {
+ .name = "magician:red",
+ .default_trigger = "ds2760-battery.0-charging",
+ },
+ .hw_num = 0,
+ .bit2 = PASIC3_BIT2_LED0,
+ .mask = PASIC3_MASK_LED0,
+ },
+ {
+ .led = {
+ .name = "magician:green",
+ .default_trigger = "ds2760-battery.0-charging-or-full",
+ },
+ .hw_num = 1,
+ .bit2 = PASIC3_BIT2_LED1,
+ .mask = PASIC3_MASK_LED1,
+ },
+ {
+ .led = {
+ .name = "magician:blue",
+ .default_trigger = "bluetooth",
+ },
+ .hw_num = 2,
+ .bit2 = PASIC3_BIT2_LED2,
+ .mask = PASIC3_MASK_LED2,
+ },
+};
+
+static struct platform_device pasic3;
+
+static struct pasic3_leds_machinfo __devinit pasic3_leds_info = {
+ .num_leds = ARRAY_SIZE(pasic3_leds),
+ .power_gpio = EGPIO_MAGICIAN_LED_POWER,
+ .leds = pasic3_leds,
+};
+
+/*
+ * PASIC3 with DS1WM
+ */
+
+static struct resource pasic3_resources[] = {
+ [0] = {
+ .start = PXA_CS2_PHYS,
+ .end = PXA_CS2_PHYS + 0x1b,
+ .flags = IORESOURCE_MEM,
+ },
+ /* No IRQ handler in the PASIC3, DS1WM needs an external IRQ */
+ [1] = {
+ .start = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ),
+ .end = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ),
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+ }
+};
+
+static struct pasic3_platform_data pasic3_platform_data = {
+ .bus_shift = 2,
+ .led_pdata = &pasic3_leds_info,
+ .clock_rate = 4000000,
+};
+
+static struct platform_device pasic3 = {
+ .name = "pasic3",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(pasic3_resources),
+ .resource = pasic3_resources,
+ .dev = {
+ .platform_data = &pasic3_platform_data,
+ },
+};
+
+/*
+ * External power
+ */
+
+static int magician_is_ac_online(void)
+{
+ return gpio_get_value(EGPIO_MAGICIAN_CABLE_STATE_AC);
+}
+
+static int magician_is_usb_online(void)
+{
+ return gpio_get_value(EGPIO_MAGICIAN_CABLE_STATE_USB);
+}
+
+static void magician_set_charge(int flags)
+{
+ gpio_set_value(GPIO30_MAGICIAN_nCHARGE_EN, !flags);
+ gpio_set_value(EGPIO_MAGICIAN_CHARGE_EN, flags);
+}
+
+static char *magician_supplicants[] = {
+ "ds2760-battery.0", "backup-battery"
+};
+
+static struct pda_power_pdata power_supply_info = {
+ .is_ac_online = magician_is_ac_online,
+ .is_usb_online = magician_is_usb_online,
+ .set_charge = magician_set_charge,
+ .supplied_to = magician_supplicants,
+ .num_supplicants = ARRAY_SIZE(magician_supplicants),
+};
+
+static struct resource power_supply_resources[] = {
+ [0] = {
+ .name = "ac",
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_MAGICIAN_AC,
+ .end = IRQ_MAGICIAN_AC,
+ },
+ [1] = {
+ .name = "usb",
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_MAGICIAN_AC,
+ .end = IRQ_MAGICIAN_AC,
+ },
+};
+
+static struct platform_device power_supply = {
+ .name = "pda-power",
+ .id = -1,
+ .dev = {
+ .platform_data = &power_supply_info,
+ },
+ .resource = power_supply_resources,
+ .num_resources = ARRAY_SIZE(power_supply_resources),
+};
+
+
+/*
+ * MMC/SD
+ */
+
+static int magician_mci_init(struct device *dev,
+ irq_handler_t detect_irq, void *data)
+{
+ return request_irq(IRQ_MAGICIAN_SD, detect_irq,
+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
+ "MMC card detect", data);
+}
+
+static void magician_mci_setpower(struct device *dev, unsigned int vdd)
+{
+ struct pxamci_platform_data *pdata = dev->platform_data;
+
+ gpio_set_value(EGPIO_MAGICIAN_SD_POWER, (1 << vdd) & pdata->ocr_mask);
+}
+
+static int magician_mci_get_ro(struct device *dev)
+{
+ return (!gpio_get_value(EGPIO_MAGICIAN_nSD_READONLY));
+}
+
+static void magician_mci_exit(struct device *dev, void *data)
+{
+ free_irq(IRQ_MAGICIAN_SD, data);
+}
+
+static struct pxamci_platform_data magician_mci_info = {
+ .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
+ .init = magician_mci_init,
+ .get_ro = magician_mci_get_ro,
+ .setpower = magician_mci_setpower,
+ .exit = magician_mci_exit,
+};
+
/*
* USB OHCI
* StrataFlash
*/
+static void magician_set_vpp(struct map_info *map, int vpp)
+{
+ gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp);
+}
+
#define PXA_CS_SIZE 0x04000000
static struct resource strataflash_resource = {
static struct physmap_flash_data strataflash_data = {
.width = 4,
+ .set_vpp = magician_set_vpp,
};
static struct platform_device strataflash = {
.name = "physmap-flash",
.id = -1,
- .num_resources = 1,
.resource = &strataflash_resource,
+ .num_resources = 1,
.dev = {
.platform_data = &strataflash_data,
},
static struct platform_device *devices[] __initdata = {
&gpio_keys,
+ &egpio,
&backlight,
+ &pasic3,
+ &power_supply,
&strataflash,
+ &leds_gpio,
};
static void __init magician_init(void)
{
+ void __iomem *cpld;
+ int lcd_select;
+
+ pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config));
+
platform_add_devices(devices, ARRAY_SIZE(devices));
+ pxa_set_i2c_info(NULL);
+ pxa_set_mci_info(&magician_mci_info);
pxa_set_ohci_info(&magician_ohci_info);
pxa_set_ficp_info(&magician_ficp_info);
- set_pxa_fb_info(&toppoly_info);
+
+ /* Check LCD type we have */
+ cpld = ioremap_nocache(PXA_CS3_PHYS, 0x1000);
+ if (cpld) {
+ u8 board_id = __raw_readb(cpld+0x14);
+ system_rev = board_id & 0x7;
+ lcd_select = board_id & 0x8;
+ iounmap(cpld);
+ pr_info("LCD type: %s\n", lcd_select ? "Samsung" : "Toppoly");
+ if (lcd_select && (system_rev < 3))
+ pxa_gpio_mode(GPIO75_MAGICIAN_SAMSUNG_POWER_MD);
+ pxa_gpio_mode(GPIO104_MAGICIAN_LCD_POWER_1_MD);
+ pxa_gpio_mode(GPIO105_MAGICIAN_LCD_POWER_2_MD);
+ pxa_gpio_mode(GPIO106_MAGICIAN_LCD_POWER_3_MD);
+ set_pxa_fb_info(lcd_select ? &samsung_info : &toppoly_info);
+ } else
+ pr_err("LCD detection: CPLD mapping failed\n");
}
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/backlight.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/mainstone.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>
+#include <asm/arch/i2c.h>
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/ohci.h>
+#include <asm/arch/pxa27x_keypad.h>
#include "generic.h"
#include "devices.h"
+static unsigned long mainstone_pin_config[] = {
+ /* Chip Select */
+ GPIO15_nCS_1,
+
+ /* LCD - 16bpp Active TFT */
+ GPIO58_LCD_LDD_0,
+ GPIO59_LCD_LDD_1,
+ GPIO60_LCD_LDD_2,
+ GPIO61_LCD_LDD_3,
+ GPIO62_LCD_LDD_4,
+ GPIO63_LCD_LDD_5,
+ GPIO64_LCD_LDD_6,
+ GPIO65_LCD_LDD_7,
+ GPIO66_LCD_LDD_8,
+ GPIO67_LCD_LDD_9,
+ GPIO68_LCD_LDD_10,
+ GPIO69_LCD_LDD_11,
+ GPIO70_LCD_LDD_12,
+ GPIO71_LCD_LDD_13,
+ GPIO72_LCD_LDD_14,
+ GPIO73_LCD_LDD_15,
+ GPIO74_LCD_FCLK,
+ GPIO75_LCD_LCLK,
+ GPIO76_LCD_PCLK,
+ GPIO77_LCD_BIAS,
+ GPIO16_PWM0_OUT, /* Backlight */
+
+ /* MMC */
+ GPIO32_MMC_CLK,
+ GPIO112_MMC_CMD,
+ GPIO92_MMC_DAT_0,
+ GPIO109_MMC_DAT_1,
+ GPIO110_MMC_DAT_2,
+ GPIO111_MMC_DAT_3,
+
+ /* USB Host Port 1 */
+ GPIO88_USBH1_PWR,
+ GPIO89_USBH1_PEN,
+
+ /* PC Card */
+ GPIO48_nPOE,
+ GPIO49_nPWE,
+ GPIO50_nPIOR,
+ GPIO51_nPIOW,
+ GPIO85_nPCE_1,
+ GPIO54_nPCE_2,
+ GPIO79_PSKTSEL,
+ GPIO55_nPREG,
+ GPIO56_nPWAIT,
+ GPIO57_nIOIS16,
+
+ /* AC97 */
+ GPIO45_AC97_SYSCLK,
+
+ /* Keypad */
+ GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+ GPIO94_KP_DKIN_1 | WAKEUP_ON_LEVEL_HIGH,
+ GPIO95_KP_DKIN_2 | WAKEUP_ON_LEVEL_HIGH,
+ GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
+ GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
+ GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
+ GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
+ GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
+ GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
+ GPIO103_KP_MKOUT_0,
+ GPIO104_KP_MKOUT_1,
+ GPIO105_KP_MKOUT_2,
+ GPIO106_KP_MKOUT_3,
+ GPIO107_KP_MKOUT_4,
+ GPIO108_KP_MKOUT_5,
+ GPIO96_KP_MKOUT_6,
+
+ /* GPIO */
+ GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
+};
static unsigned long mainstone_irq_enabled;
bl->props.fb_blank != FB_BLANK_UNBLANK)
brightness = 0;
- if (brightness != 0) {
- pxa_gpio_mode(GPIO16_PWM0_MD);
+ if (brightness != 0)
pxa_set_cken(CKEN_PWM0, 1);
- }
+
PWM_CTRL0 = 0;
PWM_PWDUTY0 = brightness;
PWM_PERVAL0 = bl->props.max_brightness;
+
if (brightness == 0)
pxa_set_cken(CKEN_PWM0, 0);
return 0; /* pointless return value */
{
int err;
- /*
- * setup GPIO for PXA27x MMC controller
- */
- pxa_gpio_mode(GPIO32_MMCCLK_MD);
- pxa_gpio_mode(GPIO112_MMCCMD_MD);
- pxa_gpio_mode(GPIO92_MMCDAT0_MD);
- pxa_gpio_mode(GPIO109_MMCDAT1_MD);
- pxa_gpio_mode(GPIO110_MMCDAT2_MD);
- pxa_gpio_mode(GPIO111_MMCDAT3_MD);
-
/* make sure SD/Memory Stick multiplexer's signals
* are routed to MMC controller
*/
.transceiver_mode = mainstone_irda_transceiver_mode,
};
+static struct gpio_keys_button gpio_keys_button[] = {
+ [0] = {
+ .desc = "wakeup",
+ .code = KEY_SUSPEND,
+ .type = EV_KEY,
+ .gpio = 1,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data mainstone_gpio_keys = {
+ .buttons = gpio_keys_button,
+ .nbuttons = 1,
+};
+
+static struct platform_device mst_gpio_keys_device = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &mainstone_gpio_keys,
+ },
+};
+
static struct platform_device *platform_devices[] __initdata = {
&smc91x_device,
&mst_audio_device,
&mst_flash_device[0],
&mst_flash_device[1],
+ &mst_gpio_keys_device,
};
static int mainstone_ohci_init(struct device *dev)
{
- /* setup Port1 GPIO pin. */
- pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
- pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
-
/* Set the Power Control Polarity Low and Power Sense
Polarity Low to active low. */
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
.init = mainstone_ohci_init,
};
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
+static unsigned int mainstone_matrix_keys[] = {
+ KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C),
+ KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F),
+ KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I),
+ KEY(3, 1, KEY_J), KEY(4, 1, KEY_K), KEY(5, 1, KEY_L),
+ KEY(0, 2, KEY_M), KEY(1, 2, KEY_N), KEY(2, 2, KEY_O),
+ KEY(3, 2, KEY_P), KEY(4, 2, KEY_Q), KEY(5, 2, KEY_R),
+ KEY(0, 3, KEY_S), KEY(1, 3, KEY_T), KEY(2, 3, KEY_U),
+ KEY(3, 3, KEY_V), KEY(4, 3, KEY_W), KEY(5, 3, KEY_X),
+ KEY(2, 4, KEY_Y), KEY(3, 4, KEY_Z),
+
+ KEY(0, 4, KEY_DOT), /* . */
+ KEY(1, 4, KEY_CLOSE), /* @ */
+ KEY(4, 4, KEY_SLASH),
+ KEY(5, 4, KEY_BACKSLASH),
+ KEY(0, 5, KEY_HOME),
+ KEY(1, 5, KEY_LEFTSHIFT),
+ KEY(2, 5, KEY_SPACE),
+ KEY(3, 5, KEY_SPACE),
+ KEY(4, 5, KEY_ENTER),
+ KEY(5, 5, KEY_BACKSPACE),
+
+ KEY(0, 6, KEY_UP),
+ KEY(1, 6, KEY_DOWN),
+ KEY(2, 6, KEY_LEFT),
+ KEY(3, 6, KEY_RIGHT),
+ KEY(4, 6, KEY_SELECT),
+};
+
+struct pxa27x_keypad_platform_data mainstone_keypad_info = {
+ .matrix_key_rows = 6,
+ .matrix_key_cols = 7,
+ .matrix_key_map = mainstone_matrix_keys,
+ .matrix_key_map_size = ARRAY_SIZE(mainstone_matrix_keys),
+
+ .enable_rotary0 = 1,
+ .rotary0_up_key = KEY_UP,
+ .rotary0_down_key = KEY_DOWN,
+
+ .debounce_interval = 30,
+};
+
+static void __init mainstone_init_keypad(void)
+{
+ pxa_set_keypad_info(&mainstone_keypad_info);
+}
+#else
+static inline void mainstone_init_keypad(void) {}
+#endif
+
static void __init mainstone_init(void)
{
int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
+ pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config));
+
mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
mst_flash_data[1].width = 4;
*/
ARB_CNTRL = ARB_CORE_PARK | 0x234;
- /*
- * On Mainstone, we route AC97_SYSCLK via GPIO45 to
- * the audio daughter card
- */
- pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
-
- GPSR(GPIO48_nPOE) =
- GPIO_bit(GPIO48_nPOE) |
- GPIO_bit(GPIO49_nPWE) |
- GPIO_bit(GPIO50_nPIOR) |
- GPIO_bit(GPIO51_nPIOW) |
- GPIO_bit(GPIO85_nPCE_1) |
- GPIO_bit(GPIO54_nPCE_2);
-
- pxa_gpio_mode(GPIO48_nPOE_MD);
- pxa_gpio_mode(GPIO49_nPWE_MD);
- pxa_gpio_mode(GPIO50_nPIOR_MD);
- pxa_gpio_mode(GPIO51_nPIOW_MD);
- pxa_gpio_mode(GPIO85_nPCE_1_MD);
- pxa_gpio_mode(GPIO54_nPCE_2_MD);
- pxa_gpio_mode(GPIO79_pSKTSEL_MD);
- pxa_gpio_mode(GPIO55_nPREG_MD);
- pxa_gpio_mode(GPIO56_nPWAIT_MD);
- pxa_gpio_mode(GPIO57_nIOIS16_MD);
-
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
/* reading Mainstone's "Virtual Configuration Register"
pxa_set_mci_info(&mainstone_mci_platform_data);
pxa_set_ficp_info(&mainstone_ficp_platform_data);
pxa_set_ohci_info(&mainstone_ohci_platform_data);
+ pxa_set_i2c_info(NULL);
+
+ mainstone_init_keypad();
}
pxa_map_io();
iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
- /* initialize sleep mode regs (wake-up sources, etc) */
- PGSR0 = 0x00008800;
- PGSR1 = 0x00000002;
- PGSR2 = 0x0001FC00;
- PGSR3 = 0x00001F81;
- PWER = 0xC0000002;
- PRER = 0x00000002;
- PFER = 0x00000002;
/* for use I SRAM as framebuffer. */
PSLR |= 0xF04;
PCFR = 0x66;
- /* For Keypad wakeup. */
- KPC &=~KPC_ASACT;
- KPC |=KPC_AS;
- PKWR = 0x000FD000;
- /* Need read PKWR back after set it. */
- PKWR;
}
MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
--- /dev/null
+/*
+ * linux/arch/arm/mach-pxa/mfp-pxa2xx.c
+ *
+ * PXA2xx pin mux configuration support
+ *
+ * The GPIOs on PXA2xx can be configured as one of many alternate
+ * functions, this is by concept samilar to the MFP configuration
+ * on PXA3xx, what's more important, the low power pin state and
+ * wakeup detection are also supported by the same framework.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/mfp-pxa2xx.h>
+
+#include "generic.h"
+
+#define PGSR(x) __REG2(0x40F00020, ((x) & 0x60) >> 3)
+
+#define PWER_WE35 (1 << 24)
+
+struct gpio_desc {
+ unsigned valid : 1;
+ unsigned can_wakeup : 1;
+ unsigned keypad_gpio : 1;
+ unsigned int mask; /* bit mask in PWER or PKWR */
+ unsigned long config;
+};
+
+static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
+
+static int __mfp_config_gpio(unsigned gpio, unsigned long c)
+{
+ unsigned long gafr, mask = GPIO_bit(gpio);
+ int fn;
+
+ fn = MFP_AF(c);
+ if (fn > 3)
+ return -EINVAL;
+
+ /* alternate function and direction */
+ gafr = GAFR(gpio) & ~(0x3 << ((gpio & 0xf) * 2));
+ GAFR(gpio) = gafr | (fn << ((gpio & 0xf) * 2));
+
+ if (c & MFP_DIR_OUT)
+ GPDR(gpio) |= mask;
+ else
+ GPDR(gpio) &= ~mask;
+
+ /* low power state */
+ switch (c & MFP_LPM_STATE_MASK) {
+ case MFP_LPM_DRIVE_HIGH:
+ PGSR(gpio) |= mask;
+ break;
+ case MFP_LPM_DRIVE_LOW:
+ PGSR(gpio) &= ~mask;
+ break;
+ case MFP_LPM_INPUT:
+ break;
+ default:
+ pr_warning("%s: invalid low power state for GPIO%d\n",
+ __func__, gpio);
+ return -EINVAL;
+ }
+
+ /* give early warning if MFP_LPM_CAN_WAKEUP is set on the
+ * configurations of those pins not able to wakeup
+ */
+ if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) {
+ pr_warning("%s: GPIO%d unable to wakeup\n",
+ __func__, gpio);
+ return -EINVAL;
+ }
+
+ if ((c & MFP_LPM_CAN_WAKEUP) && (c & MFP_DIR_OUT)) {
+ pr_warning("%s: output GPIO%d unable to wakeup\n",
+ __func__, gpio);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
+{
+ unsigned long flags;
+ unsigned long *c;
+ int i, gpio;
+
+ for (i = 0, c = mfp_cfgs; i < num; i++, c++) {
+
+ gpio = mfp_to_gpio(MFP_PIN(*c));
+
+ if (!gpio_desc[gpio].valid) {
+ pr_warning("%s: GPIO%d is invalid pin\n",
+ __func__, gpio);
+ continue;
+ }
+
+ local_irq_save(flags);
+
+ gpio_desc[gpio].config = *c;
+ __mfp_config_gpio(gpio, *c);
+
+ local_irq_restore(flags);
+ }
+}
+
+int gpio_set_wake(unsigned int gpio, unsigned int on)
+{
+ struct gpio_desc *d;
+ unsigned long c;
+
+ if (gpio > mfp_to_gpio(MFP_PIN_GPIO127))
+ return -EINVAL;
+
+ d = &gpio_desc[gpio];
+ c = d->config;
+
+ if (!d->valid)
+ return -EINVAL;
+
+ if (d->keypad_gpio)
+ return -EINVAL;
+
+ if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) {
+ if (on) {
+ PWER |= d->mask;
+
+ if (c & MFP_LPM_EDGE_RISE)
+ PRER |= d->mask;
+ else
+ PRER &= ~d->mask;
+
+ if (c & MFP_LPM_EDGE_FALL)
+ PFER |= d->mask;
+ else
+ PFER &= ~d->mask;
+ } else {
+ PWER &= ~d->mask;
+ PRER &= ~d->mask;
+ PFER &= ~d->mask;
+ }
+ }
+ return 0;
+}
+
+#ifdef CONFIG_PXA25x
+static int __init pxa25x_mfp_init(void)
+{
+ int i;
+
+ if (cpu_is_pxa25x()) {
+ for (i = 0; i <= 84; i++)
+ gpio_desc[i].valid = 1;
+
+ for (i = 0; i <= 15; i++) {
+ gpio_desc[i].can_wakeup = 1;
+ gpio_desc[i].mask = GPIO_bit(i);
+ }
+ }
+
+ return 0;
+}
+postcore_initcall(pxa25x_mfp_init);
+#endif /* CONFIG_PXA25x */
+
+#ifdef CONFIG_PXA27x
+static int pxa27x_pkwr_gpio[] = {
+ 13, 16, 17, 34, 36, 37, 38, 39, 90, 91, 93, 94,
+ 95, 96, 97, 98, 99, 100, 101, 102
+};
+
+int keypad_set_wake(unsigned int on)
+{
+ unsigned int i, gpio, mask = 0;
+
+ if (!on) {
+ PKWR = 0;
+ return 0;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
+
+ gpio = pxa27x_pkwr_gpio[i];
+
+ if (gpio_desc[gpio].config & MFP_LPM_CAN_WAKEUP)
+ mask |= gpio_desc[gpio].mask;
+ }
+
+ PKWR = mask;
+ return 0;
+}
+
+static int __init pxa27x_mfp_init(void)
+{
+ int i, gpio;
+
+ if (cpu_is_pxa27x()) {
+ for (i = 0; i <= 120; i++) {
+ /* skip GPIO2, 5, 6, 7, 8, they are not
+ * valid pins allow configuration
+ */
+ if (i == 2 || i == 5 || i == 6 ||
+ i == 7 || i == 8)
+ continue;
+
+ gpio_desc[i].valid = 1;
+ }
+
+ /* Keypad GPIOs */
+ for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
+ gpio = pxa27x_pkwr_gpio[i];
+ gpio_desc[gpio].can_wakeup = 1;
+ gpio_desc[gpio].keypad_gpio = 1;
+ gpio_desc[gpio].mask = 1 << i;
+ }
+
+ /* Overwrite GPIO13 as a PWER wakeup source */
+ for (i = 0; i <= 15; i++) {
+ /* skip GPIO2, 5, 6, 7, 8 */
+ if (GPIO_bit(i) & 0x1e4)
+ continue;
+
+ gpio_desc[i].can_wakeup = 1;
+ gpio_desc[i].mask = GPIO_bit(i);
+ }
+
+ gpio_desc[35].can_wakeup = 1;
+ gpio_desc[35].mask = PWER_WE35;
+ }
+
+ return 0;
+}
+postcore_initcall(pxa27x_mfp_init);
+#endif /* CONFIG_PXA27x */
static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX];
/* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */
-const static unsigned long mfpr_lpm[] = {
+static const unsigned long mfpr_lpm[] = {
MFPR_LPM_INPUT,
MFPR_LPM_DRIVE_LOW,
MFPR_LPM_DRIVE_HIGH,
};
/* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
-const static unsigned long mfpr_pull[] = {
+static const unsigned long mfpr_pull[] = {
MFPR_PULL_NONE,
MFPR_PULL_LOW,
MFPR_PULL_HIGH,
};
/* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */
-const static unsigned long mfpr_edge[] = {
+static const unsigned long mfpr_edge[] = {
MFPR_EDGE_NONE,
MFPR_EDGE_RISE,
MFPR_EDGE_FALL,
return 0;
}
+#else
+#define pxa3xx_mfp_suspend NULL
+#define pxa3xx_mfp_resume NULL
+#endif
-static struct sysdev_class mfp_sysclass = {
+struct sysdev_class pxa3xx_mfp_sysclass = {
.name = "mfp",
.suspend = pxa3xx_mfp_suspend,
.resume = pxa3xx_mfp_resume,
};
-static struct sys_device mfp_device = {
- .id = 0,
- .cls = &mfp_sysclass,
-};
-
static int __init mfp_init_devicefs(void)
{
- sysdev_class_register(&mfp_sysclass);
- return sysdev_register(&mfp_device);
+ if (cpu_is_pxa3xx())
+ return sysdev_class_register(&pxa3xx_mfp_sysclass);
+
+ return 0;
}
-device_initcall(mfp_init_devicefs);
-#endif
+postcore_initcall(mfp_init_devicefs);
#include <asm/mach/arch.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx_spi.h>
#include <asm/arch/pcm027.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/ide.h>
+#include <linux/i2c.h>
+
+#include <media/soc_camera.h>
+
+#include <asm/gpio.h>
+#include <asm/arch/i2c.h>
+#include <asm/arch/camera.h>
#include <asm/mach/map.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pcm990_baseboard.h>
.exit = NULL,
};
+/*
+ * PXA27x Camera specific stuff
+ */
+#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
+static int pcm990_pxacamera_init(struct device *dev)
+{
+ pxa_gpio_mode(GPIO98_CIF_DD_0_MD);
+ pxa_gpio_mode(GPIO105_CIF_DD_1_MD);
+ pxa_gpio_mode(GPIO104_CIF_DD_2_MD);
+ pxa_gpio_mode(GPIO103_CIF_DD_3_MD);
+ pxa_gpio_mode(GPIO95_CIF_DD_4_MD);
+ pxa_gpio_mode(GPIO94_CIF_DD_5_MD);
+ pxa_gpio_mode(GPIO93_CIF_DD_6_MD);
+ pxa_gpio_mode(GPIO108_CIF_DD_7_MD);
+ pxa_gpio_mode(GPIO107_CIF_DD_8_MD);
+ pxa_gpio_mode(GPIO106_CIF_DD_9_MD);
+ pxa_gpio_mode(GPIO42_CIF_MCLK_MD);
+ pxa_gpio_mode(GPIO45_CIF_PCLK_MD);
+ pxa_gpio_mode(GPIO43_CIF_FV_MD);
+ pxa_gpio_mode(GPIO44_CIF_LV_MD);
+
+ return 0;
+}
+
+/*
+ * CICR4: PCLK_EN: Pixel clock is supplied by the sensor
+ * MCLK_EN: Master clock is generated by PXA
+ * PCP: Data sampled on the falling edge of pixel clock
+ */
+struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
+ .init = pcm990_pxacamera_init,
+ .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_DATAWIDTH_10 |
+ PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN/* | PXA_CAMERA_PCP*/,
+ .mclk_10khz = 1000,
+};
+
+#include <linux/i2c/pca953x.h>
+
+static struct pca953x_platform_data pca9536_data = {
+ .gpio_base = NR_BUILTIN_GPIO + 1,
+};
+
+static struct soc_camera_link iclink[] = {
+ {
+ .bus_id = 0, /* Must match with the camera ID above */
+ .gpio = NR_BUILTIN_GPIO + 1,
+ }, {
+ .bus_id = 0, /* Must match with the camera ID above */
+ }
+};
+
+/* Board I2C devices. */
+static struct i2c_board_info __initdata pcm990_i2c_devices[] = {
+ {
+ /* Must initialize before the camera(s) */
+ I2C_BOARD_INFO("pca953x", 0x41),
+ .type = "pca9536",
+ .platform_data = &pca9536_data,
+ }, {
+ I2C_BOARD_INFO("mt9v022", 0x48),
+ .type = "mt9v022",
+ .platform_data = &iclink[0], /* With extender */
+ }, {
+ I2C_BOARD_INFO("mt9m001", 0x5d),
+ .type = "mt9m001",
+ .platform_data = &iclink[0], /* With extender */
+ },
+};
+#endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */
+
/*
* AC97 support
* Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ
/* USB host */
pxa_set_ohci_info(&pcm990_ohci_platform_data);
+ pxa_set_i2c_info(NULL);
+
+#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
+ pxa_set_camera_info(&pcm990_pxacamera_platform_data);
+
+ i2c_register_board_info(0, pcm990_i2c_devices,
+ ARRAY_SIZE(pcm990_i2c_devices));
+#endif
+
printk(KERN_INFO"PCM-990 Evaluation baseboard initialized\n");
}
#include <asm/mach/irq.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/udc.h>
#include <asm/arch/irda.h>
#include <asm/hardware.h>
#include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/mfp-pxa25x.h>
#include <asm/arch/pm.h>
#include <asm/arch/dma.h>
INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
+ INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
+
/*
INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
static int pxa25x_set_wake(unsigned int irq, unsigned int on)
{
int gpio = IRQ_TO_GPIO(irq);
- uint32_t gpio_bit, mask = 0;
-
- if (gpio >= 0 && gpio <= 15) {
- gpio_bit = GPIO_bit(gpio);
- mask = gpio_bit;
- if (on) {
- if (GRER(gpio) | gpio_bit)
- PRER |= gpio_bit;
- else
- PRER &= ~gpio_bit;
-
- if (GFER(gpio) | gpio_bit)
- PFER |= gpio_bit;
- else
- PFER &= ~gpio_bit;
- }
- goto set_pwer;
- }
+ uint32_t mask = 0;
+
+ if (gpio >= 0 && gpio < 85)
+ return gpio_set_wake(gpio, on);
if (irq == IRQ_RTCAlrm) {
mask = PWER_RTC;
void __init pxa25x_init_irq(void)
{
- pxa_init_irq_low();
- pxa_init_irq_gpio(85);
- pxa_init_irq_set_wake(pxa25x_set_wake);
+ pxa_init_irq(32, pxa25x_set_wake);
+ pxa_init_gpio(85, pxa25x_set_wake);
}
static struct platform_device *pxa25x_devices[] __initdata = {
return ret;
}
-subsys_initcall(pxa25x_init);
+postcore_initcall(pxa25x_init);
#include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pm.h>
#include <asm/arch/dma.h>
INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
- INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
+ INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),
INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
+ INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
+ INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),
+
/*
INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
/* PXA27x: Various gpios can issue wakeup events. This logic only
* handles the simple cases, not the WEMUX2 and WEMUX3 options
*/
-#define PXA27x_GPIO_NOWAKE_MASK \
- ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
-#define WAKEMASK(gpio) \
- (((gpio) <= 15) \
- ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
- : ((gpio == 35) ? (1 << 24) : 0))
-
static int pxa27x_set_wake(unsigned int irq, unsigned int on)
{
int gpio = IRQ_TO_GPIO(irq);
uint32_t mask;
- if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
- if (WAKEMASK(gpio) == 0)
- return -EINVAL;
-
- mask = WAKEMASK(gpio);
-
- if (on) {
- if (GRER(gpio) | GPIO_bit(gpio))
- PRER |= mask;
- else
- PRER &= ~mask;
+ if (gpio >= 0 && gpio < 128)
+ return gpio_set_wake(gpio, on);
- if (GFER(gpio) | GPIO_bit(gpio))
- PFER |= mask;
- else
- PFER &= ~mask;
- }
- goto set_pwer;
- }
+ if (irq == IRQ_KEYPAD)
+ return keypad_set_wake(on);
switch (irq) {
case IRQ_RTCAlrm:
return -EINVAL;
}
-set_pwer:
if (on)
PWER |= mask;
else
void __init pxa27x_init_irq(void)
{
- pxa_init_irq_low();
- pxa_init_irq_high();
- pxa_init_irq_gpio(128);
- pxa_init_irq_set_wake(pxa27x_set_wake);
+ pxa_init_irq(34, pxa27x_set_wake);
+ pxa_init_gpio(128, pxa27x_set_wake);
}
/*
static struct sys_device pxa27x_sysdev[] = {
{
- .id = 0,
- .cls = &pxa_irq_sysclass,
- }, {
- .id = 1,
.cls = &pxa_irq_sysclass,
}, {
.cls = &pxa_gpio_sysclass,
return ret;
}
-subsys_initcall(pxa27x_init);
+postcore_initcall(pxa27x_init);
return (clk / 10000);
}
+/*
+ * Return the current AC97 clock frequency.
+ */
+static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
+{
+ unsigned long rate = 312000000;
+ unsigned long ac97_div;
+
+ ac97_div = AC97_DIV;
+
+ /* This may loose precision for some rates but won't for the
+ * standard 24.576MHz.
+ */
+ rate /= (ac97_div >> 12) & 0x7fff;
+ rate *= (ac97_div & 0xfff);
+
+ return rate;
+}
+
/*
* Return the current HSIO bus clock frequency
*/
.getrate = clk_pxa3xx_hsio_getrate,
};
+static const struct clkops clk_pxa3xx_ac97_ops = {
+ .enable = clk_pxa3xx_cken_enable,
+ .disable = clk_pxa3xx_cken_disable,
+ .getrate = clk_pxa3xx_ac97_getrate,
+};
+
+static void clk_pout_enable(struct clk *clk)
+{
+ OSCC |= OSCC_PEN;
+}
+
+static void clk_pout_disable(struct clk *clk)
+{
+ OSCC &= ~OSCC_PEN;
+}
+
+static const struct clkops clk_pout_ops = {
+ .enable = clk_pout_enable,
+ .disable = clk_pout_disable,
+};
+
#define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
{ \
.name = _name, \
}
static struct clk pxa3xx_clks[] = {
- PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
- PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+ {
+ .name = "CLK_POUT",
+ .ops = &clk_pout_ops,
+ .rate = 13000000,
+ .delay = 70,
+ },
+
+ PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
+ PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+ PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL),
PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
+ PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),
PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
/*
* Don't sleep if no wakeup sources are defined
*/
- if (wakeup_src == 0)
+ if (wakeup_src == 0) {
+ printk(KERN_ERR "Not suspending: no wakeup sources\n");
return;
+ }
switch (state) {
case PM_SUSPEND_STANDBY:
return 0;
}
-
-static void pxa3xx_init_irq_pm(void)
-{
- pxa_init_irq_set_wake(pxa3xx_set_wake);
-}
-
#else
static inline void pxa3xx_init_pm(void) {}
-static inline void pxa3xx_init_irq_pm(void) {}
+#define pxa3xx_set_wake NULL
#endif
void __init pxa3xx_init_irq(void)
value |= (1 << 6);
__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
- pxa_init_irq_low();
- pxa_init_irq_high();
- pxa_init_irq_gpio(128);
- pxa3xx_init_irq_pm();
+ pxa_init_irq(56, pxa3xx_set_wake);
+ pxa_init_gpio(128, NULL);
}
/*
static struct sys_device pxa3xx_sysdev[] = {
{
- .id = 0,
.cls = &pxa_irq_sysclass,
}, {
- .id = 1,
- .cls = &pxa_irq_sysclass,
+ .cls = &pxa3xx_mfp_sysclass,
}, {
.cls = &pxa_gpio_sysclass,
},
return ret;
}
-subsys_initcall(pxa3xx_init);
+postcore_initcall(pxa3xx_init);
#include <asm/mach-types.h>
#include <asm/arch/pm.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/sharpsl.h>
#include "sharpsl.h"
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/irda.h>
#include <asm/arch/mmc.h>
#include <asm/arch/ohci.h>
#include <asm/arch/sharpsl.h>
#include <asm/arch/spitz.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include "sharpsl.h"
#define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */
#include <linux/delay.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
+#include <linux/gpio.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/system.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa25x.h>
#include <asm/arch/irda.h>
+#include <asm/arch/i2c.h>
#include <asm/arch/mmc.h>
#include <asm/arch/udc.h>
#include "generic.h"
#include "devices.h"
+static unsigned long tosa_pin_config[] = {
+ GPIO78_nCS_2, /* Scoop */
+ GPIO80_nCS_4, /* tg6393xb */
+ GPIO33_nCS_5, /* Scoop */
+
+ // GPIO76 CARD_VCC_ON1
+
+ GPIO19_GPIO, /* Reset out */
+ GPIO1_RST | WAKEUP_ON_EDGE_FALL,
+
+ GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* WAKE_UP */
+ GPIO2_GPIO | WAKEUP_ON_EDGE_BOTH, /* AC_IN */
+ GPIO3_GPIO | WAKEUP_ON_EDGE_FALL, /* RECORD */
+ GPIO4_GPIO | WAKEUP_ON_EDGE_FALL, /* SYNC */
+ GPIO20_GPIO, /* EAR_IN */
+ GPIO22_GPIO, /* On */
+
+ GPIO5_GPIO, /* USB_IN */
+ GPIO32_GPIO, /* Pen IRQ */
+
+ GPIO7_GPIO, /* Jacket Detect */
+ GPIO14_GPIO, /* BAT0_CRG */
+ GPIO12_GPIO, /* BAT1_CRG */
+ GPIO17_GPIO, /* BAT0_LOW */
+ GPIO84_GPIO, /* BAT1_LOW */
+ GPIO38_GPIO, /* BAT_LOCK */
+
+ GPIO11_3_6MHz,
+ GPIO15_GPIO, /* TC6393XB IRQ */
+ GPIO18_RDY,
+ GPIO27_GPIO, /* LCD Sync */
+
+ /* MMC */
+ GPIO6_MMC_CLK,
+ GPIO8_MMC_CS0,
+ GPIO9_GPIO, /* Detect */
+ // GPIO10 nSD_INT
+
+ /* CF */
+ GPIO13_GPIO, /* CD_IRQ */
+ GPIO21_GPIO, /* Main Slot IRQ */
+ GPIO36_GPIO, /* Jacket Slot IRQ */
+ GPIO48_nPOE,
+ GPIO49_nPWE,
+ GPIO50_nPIOR,
+ GPIO51_nPIOW,
+ GPIO52_nPCE_1,
+ GPIO53_nPCE_2,
+ GPIO54_nPSKTSEL,
+ GPIO55_nPREG,
+ GPIO56_nPWAIT,
+ GPIO57_nIOIS16,
+
+ /* AC97 */
+ GPIO31_AC97_SYNC,
+ GPIO30_AC97_SDATA_OUT,
+ GPIO28_AC97_BITCLK,
+ GPIO29_AC97_SDATA_IN_0,
+ // GPIO79 nAUD_IRQ
+
+ /* FFUART */
+ GPIO34_FFUART_RXD,
+ GPIO35_FFUART_CTS,
+ GPIO37_FFUART_DSR,
+ GPIO39_FFUART_TXD,
+ GPIO40_FFUART_DTR,
+ GPIO41_FFUART_RTS,
+
+ /* BTUART */
+ GPIO42_BTUART_RXD,
+ GPIO43_BTUART_TXD,
+ GPIO44_BTUART_CTS,
+ GPIO45_BTUART_RTS,
+
+ /* IrDA */
+ GPIO46_STUART_RXD,
+ GPIO47_STUART_TXD,
+
+ /* Keybd */
+ GPIO58_GPIO,
+ GPIO59_GPIO,
+ GPIO60_GPIO,
+ GPIO61_GPIO,
+ GPIO62_GPIO,
+ GPIO63_GPIO,
+ GPIO64_GPIO,
+ GPIO65_GPIO,
+ GPIO66_GPIO,
+ GPIO67_GPIO,
+ GPIO68_GPIO,
+ GPIO69_GPIO,
+ GPIO70_GPIO,
+ GPIO71_GPIO,
+ GPIO72_GPIO,
+ GPIO73_GPIO,
+ GPIO74_GPIO,
+ GPIO75_GPIO,
+
+ /* SPI */
+ GPIO81_SSP2_CLK_OUT,
+ GPIO82_SSP2_FRM_OUT,
+ GPIO83_SSP2_TXD,
+};
+
/*
* SCOOP Device
*/
static struct scoop_config tosa_scoop_setup = {
.io_dir = TOSA_SCOOP_IO_DIR,
- .io_out = TOSA_SCOOP_IO_OUT,
-
+ .gpio_base = TOSA_SCOOP_GPIO_BASE,
};
-struct platform_device tosascoop_device = {
+static struct platform_device tosascoop_device = {
.name = "sharp-scoop",
.id = 0,
.dev = {
static struct scoop_config tosa_scoop_jc_setup = {
.io_dir = TOSA_SCOOP_JC_IO_DIR,
- .io_out = TOSA_SCOOP_JC_IO_OUT,
+ .gpio_base = TOSA_SCOOP_JC_GPIO_BASE,
};
-struct platform_device tosascoop_jc_device = {
+static struct platform_device tosascoop_jc_device = {
.name = "sharp-scoop",
.id = 1,
.dev = {
},
};
-static void tosa_pcmcia_init(void)
-{
- /* Setup default state of GPIO outputs
- before we enable them as outputs. */
- GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
- GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
- GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO52_nPCE_1) |
- GPIO_bit(GPIO53_nPCE_2);
-
- pxa_gpio_mode(GPIO48_nPOE_MD);
- pxa_gpio_mode(GPIO49_nPWE_MD);
- pxa_gpio_mode(GPIO50_nPIOR_MD);
- pxa_gpio_mode(GPIO51_nPIOW_MD);
- pxa_gpio_mode(GPIO55_nPREG_MD);
- pxa_gpio_mode(GPIO56_nPWAIT_MD);
- pxa_gpio_mode(GPIO57_nIOIS16_MD);
- pxa_gpio_mode(GPIO52_nPCE_1_MD);
- pxa_gpio_mode(GPIO53_nPCE_2_MD);
- pxa_gpio_mode(GPIO54_pSKTSEL_MD);
-}
-
static struct scoop_pcmcia_config tosa_pcmcia_config = {
.devs = &tosa_pcmcia_scoop[0],
.num_devs = 2,
- .pcmcia_init = tosa_pcmcia_init,
};
/*
* USB Device Controller
*/
-static void tosa_udc_command(int cmd)
-{
- switch(cmd) {
- case PXA2XX_UDC_CMD_CONNECT:
- set_scoop_gpio(&tosascoop_jc_device.dev,TOSA_SCOOP_JC_USB_PULLUP);
- break;
- case PXA2XX_UDC_CMD_DISCONNECT:
- reset_scoop_gpio(&tosascoop_jc_device.dev,TOSA_SCOOP_JC_USB_PULLUP);
- break;
- }
-}
-
static struct pxa2xx_udc_mach_info udc_info __initdata = {
- .udc_command = tosa_udc_command,
+ .gpio_pullup = TOSA_GPIO_USB_PULLUP,
.gpio_vbus = TOSA_GPIO_USB_IN,
.gpio_vbus_inverted = 1,
};
{
int err;
- /* setup GPIO for PXA25x MMC controller */
- pxa_gpio_mode(GPIO6_MMCCLK_MD);
- pxa_gpio_mode(GPIO8_MMCCS0_MD);
- pxa_gpio_mode(TOSA_GPIO_nSD_DETECT | GPIO_IN);
-
tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250);
err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC/SD card detect", data);
- if (err)
+ if (err) {
printk(KERN_ERR "tosa_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
+ goto err_irq;
+ }
+ err = gpio_request(TOSA_GPIO_SD_WP, "sd_wp");
+ if (err) {
+ printk(KERN_ERR "tosa_mci_init: can't request SD_WP gpio\n");
+ goto err_gpio_wp;
+ }
+ err = gpio_direction_input(TOSA_GPIO_SD_WP);
+ if (err)
+ goto err_gpio_wp_dir;
+
+ err = gpio_request(TOSA_GPIO_PWR_ON, "sd_pwr");
+ if (err) {
+ printk(KERN_ERR "tosa_mci_init: can't request SD_PWR gpio\n");
+ goto err_gpio_pwr;
+ }
+ err = gpio_direction_output(TOSA_GPIO_PWR_ON, 0);
+ if (err)
+ goto err_gpio_pwr_dir;
+
+ return 0;
+
+err_gpio_pwr_dir:
+ gpio_free(TOSA_GPIO_PWR_ON);
+err_gpio_pwr:
+err_gpio_wp_dir:
+ gpio_free(TOSA_GPIO_SD_WP);
+err_gpio_wp:
+ free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data);
+err_irq:
return err;
}
struct pxamci_platform_data* p_d = dev->platform_data;
if (( 1 << vdd) & p_d->ocr_mask) {
- set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_PWR_ON);
+ gpio_set_value(TOSA_GPIO_PWR_ON, 1);
} else {
- reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_PWR_ON);
+ gpio_set_value(TOSA_GPIO_PWR_ON, 0);
}
}
static int tosa_mci_get_ro(struct device *dev)
{
- return (read_scoop_reg(&tosascoop_device.dev, SCOOP_GPWR)&TOSA_SCOOP_SD_WP);
+ return gpio_get_value(TOSA_GPIO_SD_WP);
}
static void tosa_mci_exit(struct device *dev, void *data)
{
+ gpio_free(TOSA_GPIO_PWR_ON);
+ gpio_free(TOSA_GPIO_SD_WP);
free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data);
}
/*
* Irda
*/
-static void tosa_irda_transceiver_mode(struct device *dev, int mode)
+static int tosa_irda_startup(struct device *dev)
{
- if (mode & IR_OFF) {
- reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN);
- pxa_gpio_mode(GPIO47_STTXD|GPIO_DFLT_LOW);
- pxa_gpio_mode(GPIO47_STTXD|GPIO_OUT);
- } else {
- pxa_gpio_mode(GPIO47_STTXD_MD);
- set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN);
+ int ret;
+
+ ret = gpio_request(TOSA_GPIO_IR_POWERDWN, "IrDA powerdown");
+ if (ret)
+ return ret;
+
+ ret = gpio_direction_output(TOSA_GPIO_IR_POWERDWN, 0);
+ if (ret)
+ gpio_free(TOSA_GPIO_IR_POWERDWN);
+
+ return ret;
}
+
+static void tosa_irda_shutdown(struct device *dev)
+{
+ gpio_free(TOSA_GPIO_IR_POWERDWN);
+}
+
+static void tosa_irda_transceiver_mode(struct device *dev, int mode)
+{
+ gpio_set_value(TOSA_GPIO_IR_POWERDWN, !(mode & IR_OFF));
}
static struct pxaficp_platform_data tosa_ficp_platform_data = {
.transceiver_cap = IR_SIRMODE | IR_OFF,
.transceiver_mode = tosa_irda_transceiver_mode,
+ .startup = tosa_irda_startup,
+ .shutdown = tosa_irda_shutdown,
};
/*
};
static struct gpio_keys_button tosa_gpio_keys[] = {
+ /*
+ * Two following keys are directly tied to "ON" button of tosa. Why?
+ * The first one can be used as a wakeup source, the second can't;
+ * also the first one is OR of ac_powered and on_button.
+ */
+ {
+ .type = EV_PWR,
+ .code = KEY_RESERVED,
+ .gpio = TOSA_GPIO_POWERON,
+ .desc = "Poweron",
+ .wakeup = 1,
+ .active_low = 1,
+ },
{
.type = EV_PWR,
.code = KEY_SUSPEND,
.gpio = TOSA_GPIO_ON_KEY,
.desc = "On key",
- .wakeup = 1,
+ /*
+ * can't be used as wakeup
+ * .wakeup = 1,
+ */
.active_low = 1,
},
{
/*
* Tosa LEDs
*/
+static struct gpio_led tosa_gpio_leds[] = {
+ {
+ .name = "tosa:amber:charge",
+ .default_trigger = "main-battery-charging",
+ .gpio = TOSA_GPIO_CHRG_ERR_LED,
+ },
+ {
+ .name = "tosa:green:mail",
+ .default_trigger = "nand-disk",
+ .gpio = TOSA_GPIO_NOTE_LED,
+ },
+ {
+ .name = "tosa:dual:wlan",
+ .default_trigger = "none",
+ .gpio = TOSA_GPIO_WLAN_LED,
+ },
+ {
+ .name = "tosa:blue:bluetooth",
+ .default_trigger = "none",
+ .gpio = TOSA_GPIO_BT_LED,
+ },
+};
+
+static struct gpio_led_platform_data tosa_gpio_leds_platform_data = {
+ .leds = tosa_gpio_leds,
+ .num_leds = ARRAY_SIZE(tosa_gpio_leds),
+};
+
static struct platform_device tosaled_device = {
- .name = "tosa-led",
- .id = -1,
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &tosa_gpio_leds_platform_data,
+ },
};
static struct platform_device *devices[] __initdata = {
static void __init tosa_init(void)
{
+ pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config));
+ gpio_set_wake(MFP_PIN_GPIO1, 1);
+ /* We can't pass to gpio-keys since it will drop the Reset altfunc */
+
pm_power_off = tosa_poweroff;
arm_pm_restart = tosa_restart;
- pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_IN);
- pxa_gpio_mode(TOSA_GPIO_TC6393_INT | GPIO_IN);
- pxa_gpio_mode(TOSA_GPIO_USB_IN | GPIO_IN);
-
- /* setup sleep mode values */
- PWER = 0x00000002;
- PFER = 0x00000000;
- PRER = 0x00000002;
- PGSR0 = 0x00000000;
- PGSR1 = 0x00FF0002;
- PGSR2 = 0x00014000;
PCFR |= PCFR_OPDE;
/* enable batt_fault */
pxa_set_mci_info(&tosa_mci_platform_data);
pxa_set_udc_info(&udc_info);
pxa_set_ficp_info(&tosa_ficp_platform_data);
+ pxa_set_i2c_info(NULL);
platform_scoop_config = &tosa_pcmcia_config;
platform_add_devices(devices, ARRAY_SIZE(devices));
#include <asm/mach/flash.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/trizeps4.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/zylonite.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/pxa27x_keypad.h>
#include "generic.h"
int gpio_backlight;
int gpio_eth_irq;
+int wm9713_irq;
+
int lcd_id;
int lcd_orientation;
static inline void zylonite_init_mmc(void) {}
#endif
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
+static unsigned int zylonite_matrix_key_map[] = {
+ /* KEY(row, col, key_code) */
+ KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_C), KEY(0, 5, KEY_D),
+ KEY(1, 0, KEY_E), KEY(1, 1, KEY_F), KEY(1, 2, KEY_G), KEY(1, 5, KEY_H),
+ KEY(2, 0, KEY_I), KEY(2, 1, KEY_J), KEY(2, 2, KEY_K), KEY(2, 5, KEY_L),
+ KEY(3, 0, KEY_M), KEY(3, 1, KEY_N), KEY(3, 2, KEY_O), KEY(3, 5, KEY_P),
+ KEY(5, 0, KEY_Q), KEY(5, 1, KEY_R), KEY(5, 2, KEY_S), KEY(5, 5, KEY_T),
+ KEY(6, 0, KEY_U), KEY(6, 1, KEY_V), KEY(6, 2, KEY_W), KEY(6, 5, KEY_X),
+ KEY(7, 1, KEY_Y), KEY(7, 2, KEY_Z),
+
+ KEY(4, 4, KEY_0), KEY(1, 3, KEY_1), KEY(4, 1, KEY_2), KEY(1, 4, KEY_3),
+ KEY(2, 3, KEY_4), KEY(4, 2, KEY_5), KEY(2, 4, KEY_6), KEY(3, 3, KEY_7),
+ KEY(4, 3, KEY_8), KEY(3, 4, KEY_9),
+
+ KEY(4, 5, KEY_SPACE),
+ KEY(5, 3, KEY_KPASTERISK), /* * */
+ KEY(5, 4, KEY_KPDOT), /* #" */
+
+ KEY(0, 7, KEY_UP),
+ KEY(1, 7, KEY_DOWN),
+ KEY(2, 7, KEY_LEFT),
+ KEY(3, 7, KEY_RIGHT),
+ KEY(2, 6, KEY_HOME),
+ KEY(3, 6, KEY_END),
+ KEY(6, 4, KEY_DELETE),
+ KEY(6, 6, KEY_BACK),
+ KEY(6, 3, KEY_CAPSLOCK), /* KEY_LEFTSHIFT), */
+
+ KEY(4, 6, KEY_ENTER), /* scroll push */
+ KEY(5, 7, KEY_ENTER), /* keypad action */
+
+ KEY(0, 4, KEY_EMAIL),
+ KEY(5, 6, KEY_SEND),
+ KEY(4, 0, KEY_CALENDAR),
+ KEY(7, 6, KEY_RECORD),
+ KEY(6, 7, KEY_VOLUMEUP),
+ KEY(7, 7, KEY_VOLUMEDOWN),
+
+ KEY(0, 6, KEY_F22), /* soft1 */
+ KEY(1, 6, KEY_F23), /* soft2 */
+ KEY(0, 3, KEY_AUX), /* contact */
+};
+
+static struct pxa27x_keypad_platform_data zylonite_keypad_info = {
+ .matrix_key_rows = 8,
+ .matrix_key_cols = 8,
+ .matrix_key_map = zylonite_matrix_key_map,
+ .matrix_key_map_size = ARRAY_SIZE(zylonite_matrix_key_map),
+
+ .enable_rotary0 = 1,
+ .rotary0_up_key = KEY_UP,
+ .rotary0_down_key = KEY_DOWN,
+
+ .debounce_interval = 30,
+};
+
+static void __init zylonite_init_keypad(void)
+{
+ pxa_set_keypad_info(&zylonite_keypad_info);
+}
+#else
+static inline void zylonite_init_keypad(void) {}
+#endif
+
static void __init zylonite_init(void)
{
/* board-processor specific initialization */
zylonite_init_lcd();
zylonite_init_mmc();
+ zylonite_init_keypad();
}
MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
#include <asm/arch/mfp-pxa300.h>
#include <asm/arch/zylonite.h>
-#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
+#include "generic.h"
/* PXA300/PXA310 common configurations */
static mfp_cfg_t common_mfp_cfg[] __initdata = {
GPIO27_AC97_SDATA_OUT,
GPIO28_AC97_SYNC,
+ /* WM9713 IRQ */
+ GPIO26_GPIO,
+
/* Keypad */
GPIO107_KP_DKIN_0 | MFP_LPM_EDGE_BOTH,
GPIO108_KP_DKIN_1 | MFP_LPM_EDGE_BOTH,
/* MMC card detect & write protect for controller 0 */
zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0);
zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2);
+
+ /* WM9713 IRQ */
+ wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO26);
}
if (cpu_is_pxa300()) {
#include <asm/arch/mfp-pxa320.h>
#include <asm/arch/zylonite.h>
-#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
+#include "generic.h"
static mfp_cfg_t mfp_cfg[] __initdata = {
/* LCD */
GPIO39_AC97_BITCLK,
GPIO40_AC97_nACRESET,
+ /* WM9713 IRQ */
+ GPIO15_GPIO,
+
/* I2C */
GPIO32_I2C_SCL,
GPIO33_I2C_SDA,
/* MMC card detect & write protect for controller 0 */
zylonite_mmc_slot[0].gpio_cd = mfp_to_gpio(MFP_PIN_GPIO1);
zylonite_mmc_slot[0].gpio_wp = mfp_to_gpio(MFP_PIN_GPIO5);
+
+ /* WM9713 IRQ */
+ wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO15);
}
}
config REALVIEW_EB_ARM11MP
bool "Support ARM11MPCore tile"
depends on MACH_REALVIEW_EB
- select CACHE_L2X0
help
Enable support for the ARM11MPCore tile on the Realview platform.
kernel built with this option enabled is not compatible with
other revisions of the ARM11MPCore tile.
+config MACH_REALVIEW_PB11MP
+ bool "Support RealView/PB11MPCore platform"
+ select ARM_GIC
+ help
+ Include support for the ARM(R) RealView MPCore Platform Baseboard.
+ PB11MPCore is a platform with an on-board ARM11MPCore and has
+ support for PCI-E and Compact Flash.
+
+config MACH_REALVIEW_PB1176
+ bool "Support RealView/PB1176 platform"
+ select ARM_GIC
+ help
+ Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
+
endmenu
obj-y := core.o clock.o
obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
+obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o
+obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
#include <linux/clk.h>
#include <linux/mutex.h>
-#include <asm/semaphore.h>
#include <asm/hardware/icst307.h>
#include "clock.h"
.set_vpp = realview_flash_set_vpp,
};
-static struct resource realview_flash_resource = {
- .start = REALVIEW_FLASH_BASE,
- .end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
- .flags = IORESOURCE_MEM,
-};
-
struct platform_device realview_flash_device = {
.name = "armflash",
.id = 0,
.dev = {
.platform_data = &realview_flash_data,
},
- .num_resources = 1,
- .resource = &realview_flash_resource,
};
+int realview_flash_register(struct resource *res, u32 num)
+{
+ realview_flash_device.resource = res;
+ realview_flash_device.num_resources = num;
+ return platform_device_register(&realview_flash_device);
+}
+
static struct resource realview_i2c_resource = {
.start = REALVIEW_I2C_BASE,
.end = REALVIEW_I2C_BASE + SZ_4K - 1,
/*
* Where is the timer (VA)?
*/
-#define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE)
-#define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
-#define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE)
-#define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
+void __iomem *timer0_va_base;
+void __iomem *timer1_va_base;
+void __iomem *timer2_va_base;
+void __iomem *timer3_va_base;
/*
* How long is the timer interval?
switch(mode) {
case CLOCK_EVT_MODE_PERIODIC:
- writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
+ writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
ctrl = TIMER_CTRL_PERIODIC;
ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
ctrl = 0;
}
- writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
+ writel(ctrl, timer0_va_base + TIMER_CTRL);
}
static int timer_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
- unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
+ unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
- writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
- writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
+ writel(evt, timer0_va_base + TIMER_LOAD);
+ writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
return 0;
}
struct clock_event_device *evt = &timer0_clockevent;
/* clear the interrupt */
- writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
+ writel(1, timer0_va_base + TIMER_INTCLR);
evt->event_handler(evt);
static cycle_t realview_get_cycles(void)
{
- return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
+ return ~readl(timer3_va_base + TIMER_VALUE);
}
static struct clocksource clocksource_realview = {
static void __init realview_clocksource_init(void)
{
/* setup timer 0 as free-running clocksource */
- writel(0, TIMER3_VA_BASE + TIMER_CTRL);
- writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
- writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
+ writel(0, timer3_va_base + TIMER_CTRL);
+ writel(0xffffffff, timer3_va_base + TIMER_LOAD);
+ writel(0xffffffff, timer3_va_base + TIMER_VALUE);
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
- TIMER3_VA_BASE + TIMER_CTRL);
+ timer3_va_base + TIMER_CTRL);
clocksource_realview.mult =
clocksource_khz2mult(1000, clocksource_realview.shift);
/*
* Initialise to a known state (all timers off)
*/
- writel(0, TIMER0_VA_BASE + TIMER_CTRL);
- writel(0, TIMER1_VA_BASE + TIMER_CTRL);
- writel(0, TIMER2_VA_BASE + TIMER_CTRL);
- writel(0, TIMER3_VA_BASE + TIMER_CTRL);
+ writel(0, timer0_va_base + TIMER_CTRL);
+ writel(0, timer1_va_base + TIMER_CTRL);
+ writel(0, timer2_va_base + TIMER_CTRL);
+ writel(0, timer3_va_base + TIMER_CTRL);
/*
* Make irqs happen for the system timer
extern void __iomem *twd_base_addr;
extern unsigned int twd_size;
#endif
+extern void __iomem *timer0_va_base;
+extern void __iomem *timer1_va_base;
+extern void __iomem *timer2_va_base;
+extern void __iomem *timer3_va_base;
extern void realview_leds_event(led_event_t ledevt);
extern void realview_timer_init(unsigned int timer_irq);
+extern int realview_flash_register(struct resource *res, u32 num);
#endif
#include <linux/smp.h>
#include <asm/cacheflush.h>
-#include <asm/hardware/arm_scu.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/mach-types.h>
+#include <asm/arch/board-eb.h>
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/scu.h>
+
extern void realview_secondary_startup(void);
/*
static unsigned int __init get_core_count(void)
{
unsigned int ncores;
+ void __iomem *scu_base = 0;
+
+ if (machine_is_realview_eb() && core_tile_eb11mp())
+ scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
+ else if (machine_is_realview_pb11mp())
+ scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
- if (machine_is_realview_eb() && core_tile_eb11mp()) {
- ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG);
+ if (scu_base) {
+ ncores = __raw_readl(scu_base + SCU_CONFIG);
ncores = (ncores & 0x03) + 1;
} else
ncores = 1;
return ncores;
}
+/*
+ * Setup the SCU
+ */
+static void scu_enable(void)
+{
+ u32 scu_ctrl;
+ void __iomem *scu_base;
+
+ if (machine_is_realview_eb() && core_tile_eb11mp())
+ scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
+ else if (machine_is_realview_pb11mp())
+ scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
+ else
+ BUG();
+
+ scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
+ scu_ctrl |= 1;
+ __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
+}
+
static DEFINE_SPINLOCK(boot_lock);
void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
- gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
+ if (machine_is_realview_eb() && core_tile_eb11mp())
+ gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
+ else if (machine_is_realview_pb11mp())
+ gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
/*
* let the primary processor know we're out of the
* dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
* realview_timer_init
*/
- if (machine_is_realview_eb() && core_tile_eb11mp())
+ if ((machine_is_realview_eb() && core_tile_eb11mp()) ||
+ machine_is_realview_pb11mp())
local_timer_setup(cpu);
#endif
cpu_set(i, cpu_present_map);
/*
- * Do we need any more CPUs? If so, then let them know where
- * to start. Note that, on modern versions of MILO, the "poke"
- * doesn't actually do anything until each individual core is
- * sent a soft interrupt to get it out of WFI
+ * Initialise the SCU if there are more than one CPU and let
+ * them know where to start. Note that, on modern versions of
+ * MILO, the "poke" doesn't actually do anything until each
+ * individual core is sent a soft interrupt to get it out of
+ * WFI
*/
- if (max_cpus > 1)
+ if (max_cpus > 1) {
+ scu_enable();
poke_milo();
+ }
}
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual = IO_ADDRESS(REALVIEW_GIC_CPU_BASE),
- .pfn = __phys_to_pfn(REALVIEW_GIC_CPU_BASE),
+ .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual = IO_ADDRESS(REALVIEW_GIC_DIST_BASE),
- .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE),
+ .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual = IO_ADDRESS(REALVIEW_TIMER0_1_BASE),
- .pfn = __phys_to_pfn(REALVIEW_TIMER0_1_BASE),
+ .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual = IO_ADDRESS(REALVIEW_TIMER2_3_BASE),
- .pfn = __phys_to_pfn(REALVIEW_TIMER2_3_BASE),
+ .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
},
#ifdef CONFIG_DEBUG_LL
{
- .virtual = IO_ADDRESS(REALVIEW_UART0_BASE),
- .pfn = __phys_to_pfn(REALVIEW_UART0_BASE),
+ .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}
/*
* These devices are connected directly to the multi-layer AHB switch
*/
-#define SMC_IRQ { NO_IRQ, NO_IRQ }
-#define SMC_DMA { 0, 0 }
+#define EB_SMC_IRQ { NO_IRQ, NO_IRQ }
+#define EB_SMC_DMA { 0, 0 }
#define MPMC_IRQ { NO_IRQ, NO_IRQ }
#define MPMC_DMA { 0, 0 }
-#define CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ }
-#define CLCD_DMA { 0, 0 }
+#define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ }
+#define EB_CLCD_DMA { 0, 0 }
#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ }
#define DMAC_DMA { 0, 0 }
*/
#define SCTL_IRQ { NO_IRQ, NO_IRQ }
#define SCTL_DMA { 0, 0 }
-#define WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
-#define WATCHDOG_DMA { 0, 0 }
-#define GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ }
-#define GPIO0_DMA { 0, 0 }
+#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
+#define EB_WATCHDOG_DMA { 0, 0 }
+#define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ }
+#define EB_GPIO0_DMA { 0, 0 }
#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ }
#define GPIO1_DMA { 0, 0 }
-#define RTC_IRQ { IRQ_EB_RTC, NO_IRQ }
-#define RTC_DMA { 0, 0 }
+#define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ }
+#define EB_RTC_DMA { 0, 0 }
/*
* These devices are connected via the DMA APB bridge
*/
#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ }
#define SCI_DMA { 7, 6 }
-#define UART0_IRQ { IRQ_EB_UART0, NO_IRQ }
-#define UART0_DMA { 15, 14 }
-#define UART1_IRQ { IRQ_EB_UART1, NO_IRQ }
-#define UART1_DMA { 13, 12 }
-#define UART2_IRQ { IRQ_EB_UART2, NO_IRQ }
-#define UART2_DMA { 11, 10 }
-#define UART3_IRQ { IRQ_EB_UART3, NO_IRQ }
-#define UART3_DMA { 0x86, 0x87 }
-#define SSP_IRQ { IRQ_EB_SSP, NO_IRQ }
-#define SSP_DMA { 9, 8 }
+#define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ }
+#define EB_UART0_DMA { 15, 14 }
+#define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ }
+#define EB_UART1_DMA { 13, 12 }
+#define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ }
+#define EB_UART2_DMA { 11, 10 }
+#define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ }
+#define EB_UART3_DMA { 0x86, 0x87 }
+#define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ }
+#define EB_SSP_DMA { 9, 8 }
/* FPGA Primecells */
AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
-AMBA_DEVICE(uart3, "fpga:09", UART3, NULL);
+AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL);
/* DevChip Primecells */
-AMBA_DEVICE(smc, "dev:00", SMC, NULL);
-AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
+AMBA_DEVICE(smc, "dev:00", EB_SMC, NULL);
+AMBA_DEVICE(clcd, "dev:20", EB_CLCD, &clcd_plat_data);
AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
-AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
+AMBA_DEVICE(wdog, "dev:e1", EB_WATCHDOG, NULL);
+AMBA_DEVICE(gpio0, "dev:e4", EB_GPIO0, NULL);
AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
-AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
+AMBA_DEVICE(rtc, "dev:e8", EB_RTC, NULL);
AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
-AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
-AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
-AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
-AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
+AMBA_DEVICE(uart0, "dev:f1", EB_UART0, NULL);
+AMBA_DEVICE(uart1, "dev:f2", EB_UART1, NULL);
+AMBA_DEVICE(uart2, "dev:f3", EB_UART2, NULL);
+AMBA_DEVICE(ssp0, "dev:f4", EB_SSP, NULL);
static struct amba_device *amba_devs[] __initdata = {
&dmac_device,
/*
* RealView EB platform devices
*/
+static struct resource realview_eb_flash_resource = {
+ .start = REALVIEW_EB_FLASH_BASE,
+ .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+};
-static struct resource realview_eb_smc91x_resources[] = {
+static struct resource realview_eb_eth_resources[] = {
[0] = {
- .start = REALVIEW_ETH_BASE,
- .end = REALVIEW_ETH_BASE + SZ_64K - 1,
+ .start = REALVIEW_EB_ETH_BASE,
+ .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
},
};
-static struct platform_device realview_eb_smc91x_device = {
- .name = "smc91x",
+static struct platform_device realview_eb_eth_device = {
.id = 0,
- .num_resources = ARRAY_SIZE(realview_eb_smc91x_resources),
- .resource = realview_eb_smc91x_resources,
+ .num_resources = ARRAY_SIZE(realview_eb_eth_resources),
+ .resource = realview_eb_eth_resources,
};
+/*
+ * Detect and register the correct Ethernet device. RealView/EB rev D
+ * platforms use the newer SMSC LAN9118 Ethernet chip
+ */
+static int eth_device_register(void)
+{
+ void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
+ u32 idrev;
+
+ if (!eth_addr)
+ return -ENOMEM;
+
+ idrev = readl(eth_addr + 0x50);
+ if ((idrev & 0xFFFF0000) == 0x01180000)
+ /* SMSC LAN9118 chip present */
+ realview_eb_eth_device.name = "smc911x";
+ else
+ /* SMSC 91C111 chip present */
+ realview_eb_eth_device.name = "smc91x";
+
+ iounmap(eth_addr);
+ return platform_device_register(&realview_eb_eth_device);
+}
+
static void __init gic_init_irq(void)
{
if (core_tile_eb11mp()) {
#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
/* board GIC, secondary */
- gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64);
- gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE));
+ gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
+ gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
#endif
} else {
/* board GIC, primary */
- gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE);
- gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
+ gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
+ gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
gic_cpu_init(0, gic_cpu_base_addr);
}
}
kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
/* platform devices */
- realview_eb_smc91x_resources[1].start = IRQ_EB11MP_ETH;
- realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH;
+ realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH;
+ realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH;
}
static void __init realview_eb_timer_init(void)
{
unsigned int timer_irq;
+ timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
+ timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
+ timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
+ timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
+
if (core_tile_eb11mp()) {
#ifdef CONFIG_LOCAL_TIMERS
twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE);
if (core_tile_eb11mp()) {
realview_eb11mp_fixup();
+#ifdef CONFIG_CACHE_L2X0
/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
* Bits: .... ...0 0111 1001 0000 .... .... .... */
l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
+#endif
}
clk_register(&realview_clcd_clk);
- platform_device_register(&realview_flash_device);
- platform_device_register(&realview_eb_smc91x_device);
+ realview_flash_register(&realview_eb_flash_resource, 1);
platform_device_register(&realview_i2c_device);
+ eth_device_register();
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
- .phys_io = REALVIEW_UART0_BASE,
- .io_pg_offst = (IO_ADDRESS(REALVIEW_UART0_BASE) >> 18) & 0xfffc,
+ .phys_io = REALVIEW_EB_UART0_BASE,
+ .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.map_io = realview_eb_map_io,
.init_irq = gic_init_irq,
--- /dev/null
+/*
+ * linux/arch/arm/mach-realview/realview_pb1176.c
+ *
+ * Copyright (C) 2008 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/icst307.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+#include <asm/mach/mmc.h>
+#include <asm/mach/time.h>
+
+#include <asm/arch/board-pb1176.h>
+#include <asm/arch/irqs.h>
+
+#include "core.h"
+#include "clock.h"
+
+static struct map_desc realview_pb1176_io_desc[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_DIST_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER0_1_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB1176_TIMER2_3_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_PB1176_L220_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB1176_L220_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+ },
+#ifdef CONFIG_DEBUG_LL
+ {
+ .virtual = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB1176_UART0_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+#endif
+};
+
+static void __init realview_pb1176_map_io(void)
+{
+ iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc));
+}
+
+/*
+ * RealView PB1176 AMBA devices
+ */
+#define GPIO2_IRQ { IRQ_PB1176_GPIO2, NO_IRQ }
+#define GPIO2_DMA { 0, 0 }
+#define GPIO3_IRQ { IRQ_PB1176_GPIO3, NO_IRQ }
+#define GPIO3_DMA { 0, 0 }
+#define AACI_IRQ { IRQ_PB1176_AACI, NO_IRQ }
+#define AACI_DMA { 0x80, 0x81 }
+#define MMCI0_IRQ { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
+#define MMCI0_DMA { 0x84, 0 }
+#define KMI0_IRQ { IRQ_PB1176_KMI0, NO_IRQ }
+#define KMI0_DMA { 0, 0 }
+#define KMI1_IRQ { IRQ_PB1176_KMI1, NO_IRQ }
+#define KMI1_DMA { 0, 0 }
+#define PB1176_SMC_IRQ { NO_IRQ, NO_IRQ }
+#define PB1176_SMC_DMA { 0, 0 }
+#define MPMC_IRQ { NO_IRQ, NO_IRQ }
+#define MPMC_DMA { 0, 0 }
+#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
+#define PB1176_CLCD_DMA { 0, 0 }
+#define DMAC_IRQ { IRQ_PB1176_DMAC, NO_IRQ }
+#define DMAC_DMA { 0, 0 }
+#define SCTL_IRQ { NO_IRQ, NO_IRQ }
+#define SCTL_DMA { 0, 0 }
+#define PB1176_WATCHDOG_IRQ { IRQ_DC1176_WATCHDOG, NO_IRQ }
+#define PB1176_WATCHDOG_DMA { 0, 0 }
+#define PB1176_GPIO0_IRQ { IRQ_PB1176_GPIO0, NO_IRQ }
+#define PB1176_GPIO0_DMA { 0, 0 }
+#define GPIO1_IRQ { IRQ_PB1176_GPIO1, NO_IRQ }
+#define GPIO1_DMA { 0, 0 }
+#define PB1176_RTC_IRQ { IRQ_DC1176_RTC, NO_IRQ }
+#define PB1176_RTC_DMA { 0, 0 }
+#define SCI_IRQ { IRQ_PB1176_SCI, NO_IRQ }
+#define SCI_DMA { 7, 6 }
+#define PB1176_UART0_IRQ { IRQ_DC1176_UART0, NO_IRQ }
+#define PB1176_UART0_DMA { 15, 14 }
+#define PB1176_UART1_IRQ { IRQ_DC1176_UART1, NO_IRQ }
+#define PB1176_UART1_DMA { 13, 12 }
+#define PB1176_UART2_IRQ { IRQ_DC1176_UART2, NO_IRQ }
+#define PB1176_UART2_DMA { 11, 10 }
+#define PB1176_UART3_IRQ { IRQ_DC1176_UART3, NO_IRQ }
+#define PB1176_UART3_DMA { 0x86, 0x87 }
+#define PB1176_SSP_IRQ { IRQ_PB1176_SSP, NO_IRQ }
+#define PB1176_SSP_DMA { 9, 8 }
+
+/* FPGA Primecells */
+AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
+AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
+AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
+AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
+AMBA_DEVICE(uart3, "fpga:09", PB1176_UART3, NULL);
+
+/* DevChip Primecells */
+AMBA_DEVICE(smc, "dev:00", PB1176_SMC, NULL);
+AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
+AMBA_DEVICE(wdog, "dev:e1", PB1176_WATCHDOG, NULL);
+AMBA_DEVICE(gpio0, "dev:e4", PB1176_GPIO0, NULL);
+AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
+AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
+AMBA_DEVICE(rtc, "dev:e8", PB1176_RTC, NULL);
+AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
+AMBA_DEVICE(uart0, "dev:f1", PB1176_UART0, NULL);
+AMBA_DEVICE(uart1, "dev:f2", PB1176_UART1, NULL);
+AMBA_DEVICE(uart2, "dev:f3", PB1176_UART2, NULL);
+AMBA_DEVICE(ssp0, "dev:f4", PB1176_SSP, NULL);
+
+/* Primecells on the NEC ISSP chip */
+AMBA_DEVICE(clcd, "issp:20", PB1176_CLCD, &clcd_plat_data);
+//AMBA_DEVICE(dmac, "issp:30", PB1176_DMAC, NULL);
+
+static struct amba_device *amba_devs[] __initdata = {
+// &dmac_device,
+ &uart0_device,
+ &uart1_device,
+ &uart2_device,
+ &uart3_device,
+ &smc_device,
+ &clcd_device,
+ &sctl_device,
+ &wdog_device,
+ &gpio0_device,
+ &gpio1_device,
+ &gpio2_device,
+ &rtc_device,
+ &sci0_device,
+ &ssp0_device,
+ &aaci_device,
+ &mmc0_device,
+ &kmi0_device,
+ &kmi1_device,
+};
+
+/*
+ * RealView PB1176 platform devices
+ */
+static struct resource realview_pb1176_flash_resource = {
+ .start = REALVIEW_PB1176_FLASH_BASE,
+ .end = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct resource realview_pb1176_smsc911x_resources[] = {
+ [0] = {
+ .start = REALVIEW_PB1176_ETH_BASE,
+ .end = REALVIEW_PB1176_ETH_BASE + SZ_64K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_PB1176_ETH,
+ .end = IRQ_PB1176_ETH,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device realview_pb1176_smsc911x_device = {
+ .name = "smc911x",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(realview_pb1176_smsc911x_resources),
+ .resource = realview_pb1176_smsc911x_resources,
+};
+
+static void __init gic_init_irq(void)
+{
+ /* ARM1176 DevChip GIC, primary */
+ gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
+ gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START);
+ gic_cpu_init(0, gic_cpu_base_addr);
+
+ /* board GIC, secondary */
+ gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START);
+ gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
+ gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
+}
+
+static void __init realview_pb1176_timer_init(void)
+{
+ timer0_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE);
+ timer1_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE) + 0x20;
+ timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
+ timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
+
+ realview_timer_init(IRQ_DC1176_TIMER0);
+}
+
+static struct sys_timer realview_pb1176_timer = {
+ .init = realview_pb1176_timer_init,
+};
+
+static void __init realview_pb1176_init(void)
+{
+ int i;
+
+#ifdef CONFIG_CACHE_L2X0
+ /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
+ l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
+#endif
+
+ clk_register(&realview_clcd_clk);
+
+ realview_flash_register(&realview_pb1176_flash_resource, 1);
+ platform_device_register(&realview_pb1176_smsc911x_device);
+
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+ struct amba_device *d = amba_devs[i];
+ amba_device_register(d, &iomem_resource);
+ }
+
+#ifdef CONFIG_LEDS
+ leds_event = realview_leds_event;
+#endif
+}
+
+MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
+ /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+ .phys_io = REALVIEW_PB1176_UART0_BASE,
+ .io_pg_offst = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc,
+ .boot_params = 0x00000100,
+ .map_io = realview_pb1176_map_io,
+ .init_irq = gic_init_irq,
+ .timer = &realview_pb1176_timer,
+ .init_machine = realview_pb1176_init,
+MACHINE_END
--- /dev/null
+/*
+ * linux/arch/arm/mach-realview/realview_pb11mp.c
+ *
+ * Copyright (C) 2008 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/icst307.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+#include <asm/mach/mmc.h>
+#include <asm/mach/time.h>
+
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/irqs.h>
+
+#include "core.h"
+#include "clock.h"
+
+static struct map_desc realview_pb11mp_io_desc[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+ },
+#ifdef CONFIG_DEBUG_LL
+ {
+ .virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+#endif
+};
+
+static void __init realview_pb11mp_map_io(void)
+{
+ iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
+}
+
+/*
+ * RealView PB11MPCore AMBA devices
+ */
+
+#define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ }
+#define GPIO2_DMA { 0, 0 }
+#define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ }
+#define GPIO3_DMA { 0, 0 }
+#define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ }
+#define AACI_DMA { 0x80, 0x81 }
+#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
+#define MMCI0_DMA { 0x84, 0 }
+#define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ }
+#define KMI0_DMA { 0, 0 }
+#define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ }
+#define KMI1_DMA { 0, 0 }
+#define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ }
+#define PB11MP_SMC_DMA { 0, 0 }
+#define MPMC_IRQ { NO_IRQ, NO_IRQ }
+#define MPMC_DMA { 0, 0 }
+#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ }
+#define PB11MP_CLCD_DMA { 0, 0 }
+#define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ }
+#define DMAC_DMA { 0, 0 }
+#define SCTL_IRQ { NO_IRQ, NO_IRQ }
+#define SCTL_DMA { 0, 0 }
+#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ }
+#define PB11MP_WATCHDOG_DMA { 0, 0 }
+#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ }
+#define PB11MP_GPIO0_DMA { 0, 0 }
+#define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ }
+#define GPIO1_DMA { 0, 0 }
+#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ }
+#define PB11MP_RTC_DMA { 0, 0 }
+#define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ }
+#define SCI_DMA { 7, 6 }
+#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ }
+#define PB11MP_UART0_DMA { 15, 14 }
+#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ }
+#define PB11MP_UART1_DMA { 13, 12 }
+#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ }
+#define PB11MP_UART2_DMA { 11, 10 }
+#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ }
+#define PB11MP_UART3_DMA { 0x86, 0x87 }
+#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ }
+#define PB11MP_SSP_DMA { 9, 8 }
+
+/* FPGA Primecells */
+AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
+AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
+AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
+AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
+AMBA_DEVICE(uart3, "fpga:09", PB11MP_UART3, NULL);
+
+/* DevChip Primecells */
+AMBA_DEVICE(smc, "dev:00", PB11MP_SMC, NULL);
+AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
+AMBA_DEVICE(wdog, "dev:e1", PB11MP_WATCHDOG, NULL);
+AMBA_DEVICE(gpio0, "dev:e4", PB11MP_GPIO0, NULL);
+AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
+AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
+AMBA_DEVICE(rtc, "dev:e8", PB11MP_RTC, NULL);
+AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
+AMBA_DEVICE(uart0, "dev:f1", PB11MP_UART0, NULL);
+AMBA_DEVICE(uart1, "dev:f2", PB11MP_UART1, NULL);
+AMBA_DEVICE(uart2, "dev:f3", PB11MP_UART2, NULL);
+AMBA_DEVICE(ssp0, "dev:f4", PB11MP_SSP, NULL);
+
+/* Primecells on the NEC ISSP chip */
+AMBA_DEVICE(clcd, "issp:20", PB11MP_CLCD, &clcd_plat_data);
+AMBA_DEVICE(dmac, "issp:30", DMAC, NULL);
+
+static struct amba_device *amba_devs[] __initdata = {
+ &dmac_device,
+ &uart0_device,
+ &uart1_device,
+ &uart2_device,
+ &uart3_device,
+ &smc_device,
+ &clcd_device,
+ &sctl_device,
+ &wdog_device,
+ &gpio0_device,
+ &gpio1_device,
+ &gpio2_device,
+ &rtc_device,
+ &sci0_device,
+ &ssp0_device,
+ &aaci_device,
+ &mmc0_device,
+ &kmi0_device,
+ &kmi1_device,
+};
+
+/*
+ * RealView PB11MPCore platform devices
+ */
+static struct resource realview_pb11mp_flash_resource[] = {
+ [0] = {
+ .start = REALVIEW_PB11MP_FLASH0_BASE,
+ .end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = REALVIEW_PB11MP_FLASH1_BASE,
+ .end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource realview_pb11mp_smsc911x_resources[] = {
+ [0] = {
+ .start = REALVIEW_PB11MP_ETH_BASE,
+ .end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_TC11MP_ETH,
+ .end = IRQ_TC11MP_ETH,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device realview_pb11mp_smsc911x_device = {
+ .name = "smc911x",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(realview_pb11mp_smsc911x_resources),
+ .resource = realview_pb11mp_smsc911x_resources,
+};
+
+struct resource realview_pb11mp_cf_resources[] = {
+ [0] = {
+ .start = REALVIEW_PB11MP_CF_BASE,
+ .end = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = REALVIEW_PB11MP_CF_MEM_BASE,
+ .end = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = -1, /* FIXME: Find correct irq */
+ .end = -1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device realview_pb11mp_cf_device = {
+ .name = "compactflash",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(realview_pb11mp_cf_resources),
+ .resource = realview_pb11mp_cf_resources,
+};
+
+static void __init gic_init_irq(void)
+{
+ unsigned int pldctrl;
+
+ /* new irq mode with no DCC */
+ writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
+ pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
+ pldctrl |= 2 << 22;
+ writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
+ writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
+
+ /* ARM11MPCore test chip GIC, primary */
+ gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
+ gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29);
+ gic_cpu_init(0, gic_cpu_base_addr);
+
+ /* board GIC, secondary */
+ gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START);
+ gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
+ gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
+}
+
+static void __init realview_pb11mp_timer_init(void)
+{
+ timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
+ timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
+ timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
+ timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
+
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE);
+ twd_size = REALVIEW_TC11MP_TWD_SIZE;
+#endif
+ realview_timer_init(IRQ_TC11MP_TIMER0_1);
+}
+
+static struct sys_timer realview_pb11mp_timer = {
+ .init = realview_pb11mp_timer_init,
+};
+
+static void __init realview_pb11mp_init(void)
+{
+ int i;
+
+#ifdef CONFIG_CACHE_L2X0
+ /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
+ * Bits: .... ...0 0111 1001 0000 .... .... .... */
+ l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
+#endif
+
+ clk_register(&realview_clcd_clk);
+
+ realview_flash_register(realview_pb11mp_flash_resource,
+ ARRAY_SIZE(realview_pb11mp_flash_resource));
+ platform_device_register(&realview_pb11mp_smsc911x_device);
+ platform_device_register(&realview_i2c_device);
+ platform_device_register(&realview_pb11mp_cf_device);
+
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+ struct amba_device *d = amba_devs[i];
+ amba_device_register(d, &iomem_resource);
+ }
+
+#ifdef CONFIG_LEDS
+ leds_event = realview_leds_event;
+#endif
+}
+
+MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
+ /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+ .phys_io = REALVIEW_PB11MP_UART0_BASE,
+ .io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
+ .boot_params = 0x00000100,
+ .map_io = realview_pb11mp_map_io,
+ .init_irq = gic_init_irq,
+ .timer = &realview_pb11mp_timer,
+ .init_machine = realview_pb11mp_init,
+MACHINE_END
Say Y here to enable the PC104 IRQ routing on the
Simtec BAST (EB2410ITX)
+config MACH_TCT_HAMMER
+ bool "TCT Hammer Board"
+ select CPU_S3C2410
+ help
+ Say Y here if you are using the TinCanTools Hammer Board
+ <http://www.tincantools.com>
+
config MACH_VR1000
bool "Thorcom VR1000"
select PM_SIMTEC if PM
obj-$(CONFIG_MACH_OTOM) += mach-otom.o
obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o
obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o
+obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o
obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o
obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
+#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>
/* NAND Flash on BAST board */
+#ifdef CONFIG_PM
+static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
+{
+ /* ensure that an nRESET is not generated on resume. */
+ s3c2410_gpio_setpin(S3C2410_GPA21, 1);
+ s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
+
+ return 0;
+}
+
+static int bast_pm_resume(struct sys_device *sd)
+{
+ s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
+ return 0;
+}
+
+#else
+#define bast_pm_suspend NULL
+#define bast_pm_resume NULL
+#endif
+
+static struct sysdev_class bast_pm_sysclass = {
+ .name = "mach-bast",
+ .suspend = bast_pm_suspend,
+ .resume = bast_pm_resume,
+};
+
+static struct sys_device bast_pm_sysdev = {
+ .cls = &bast_pm_sysclass,
+};
static int smartmedia_map[] = { 0 };
static int chip0_map[] = { 1 };
{
/* initialise the clocks */
- s3c24xx_dclk0.parent = NULL;
+ s3c24xx_dclk0.parent = &clk_upll;
s3c24xx_dclk0.rate = 12*1000*1000;
- s3c24xx_dclk1.parent = NULL;
+ s3c24xx_dclk1.parent = &clk_upll;
s3c24xx_dclk1.rate = 24*1000*1000;
s3c24xx_clkout0.parent = &s3c24xx_dclk0;
static void __init bast_init(void)
{
+ sysdev_class_register(&bast_pm_sysclass);
+ sysdev_register(&bast_pm_sysdev);
+
s3c24xx_fb_set_platdata(&bast_fb_info);
platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
}
--- /dev/null
+/* linux/arch/arm/mach-s3c2410/mach-tct_hammer.c
+ *
+ * Copyright (c) 2007 TinCanTools
+ * David Anders <danders@amltd.com>
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * @History:
+ * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ ***********************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/flash.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <asm/plat-s3c/regs-serial.h>
+#include <asm/plat-s3c24xx/devs.h>
+#include <asm/plat-s3c24xx/cpu.h>
+
+#ifdef CONFIG_MTD_PARTITIONS
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/physmap.h>
+
+static struct resource tct_hammer_nor_resource = {
+ .start = 0x00000000,
+ .end = 0x01000000 - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct mtd_partition tct_hammer_mtd_partitions[] = {
+ {
+ .name = "System",
+ .size = 0x240000,
+ .offset = 0,
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ }, {
+ .name = "JFFS2",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND,
+ }
+};
+
+static struct physmap_flash_data tct_hammer_flash_data = {
+ .width = 2,
+ .parts = tct_hammer_mtd_partitions,
+ .nr_parts = ARRAY_SIZE(tct_hammer_mtd_partitions),
+};
+
+static struct platform_device tct_hammer_device_nor = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &tct_hammer_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &tct_hammer_nor_resource,
+};
+
+#endif
+
+static struct map_desc tct_hammer_iodesc[] __initdata = {
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ }
+};
+
+
+static struct platform_device *tct_hammer_devices[] __initdata = {
+ &s3c_device_adc,
+ &s3c_device_wdt,
+ &s3c_device_i2c,
+ &s3c_device_usb,
+ &s3c_device_rtc,
+ &s3c_device_usbgadget,
+ &s3c_device_sdi,
+#ifdef CONFIG_MTD_PARTITIONS
+ &tct_hammer_device_nor,
+#endif
+};
+
+static void __init tct_hammer_map_io(void)
+{
+ s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
+ s3c24xx_init_clocks(0);
+ s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
+}
+
+static void __init tct_hammer_init(void)
+{
+ platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
+}
+
+MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
+ .phys_io = S3C2410_PA_UART,
+ .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+ .boot_params = S3C2410_SDRAM_PA + 0x100,
+ .map_io = tct_hammer_map_io,
+ .init_irq = s3c24xx_init_irq,
+ .init_machine = tct_hammer_init,
+ .timer = &s3c24xx_timer,
+MACHINE_END
{
/* initialise clock sources */
- s3c24xx_dclk0.parent = NULL;
+ s3c24xx_dclk0.parent = &clk_upll;
s3c24xx_dclk0.rate = 12*1000*1000;
s3c24xx_dclk1.parent = NULL;
/* work out clock scalings */
hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
- hclk /= ((tmp & S3C2421_CLKDIVN_ARMDIVN) ? 2 : 1);
+ hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
/* print brieft summary of clocks, etc */
{
/* initialise the clocks */
- s3c24xx_dclk0.parent = NULL;
+ s3c24xx_dclk0.parent = &clk_upll;
s3c24xx_dclk0.rate = 12*1000*1000;
- s3c24xx_dclk1.parent = NULL;
+ s3c24xx_dclk1.parent = &clk_upll;
s3c24xx_dclk1.rate = 24*1000*1000;
s3c24xx_clkout0.parent = &s3c24xx_dclk0;
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
+#include <linux/clk.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
/* initialise the clocks */
- s3c24xx_dclk0.parent = NULL;
+ s3c24xx_dclk0.parent = &clk_upll;
s3c24xx_dclk0.rate = 12*1000*1000;
- s3c24xx_dclk1.parent = NULL;
+ s3c24xx_dclk1.parent = &clk_upll;
s3c24xx_dclk1.rate = 24*1000*1000;
s3c24xx_clkout0.parent = &s3c24xx_dclk0;
#
# Common support
-obj-y := clock.o generic.o irq.o dma.o time.o #nmi-oopser.o
+obj-y := clock.o generic.o gpio.o irq.o dma.o time.o #nmi-oopser.o
obj-m :=
obj-n :=
obj- :=
return v;
}
-int gpio_direction_input(unsigned gpio)
-{
- unsigned long flags;
-
- if (gpio > GPIO_MAX)
- return -EINVAL;
-
- local_irq_save(flags);
- GPDR &= ~GPIO_GPIO(gpio);
- local_irq_restore(flags);
- return 0;
-}
-
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- unsigned long flags;
-
- if (gpio > GPIO_MAX)
- return -EINVAL;
-
- local_irq_save(flags);
- gpio_set_value(gpio, value);
- GPDR |= GPIO_GPIO(gpio);
- local_irq_restore(flags);
- return 0;
-}
-
-EXPORT_SYMBOL(gpio_direction_output);
-
/*
* Default power-off for SA1100
*/
extern struct sys_timer sa1100_timer;
extern void __init sa1100_map_io(void);
extern void __init sa1100_init_irq(void);
+extern void __init sa1100_init_gpio(void);
#define SET_BANK(__nr,__start,__size) \
mi->bank[__nr].start = (__start), \
--- /dev/null
+/*
+ * linux/arch/arm/mach-sa1100/gpio.c
+ *
+ * Generic SA-1100 GPIO handling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <asm/gpio.h>
+#include <asm/hardware.h>
+#include "generic.h"
+
+static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ return GPLR & GPIO_GPIO(offset);
+}
+
+static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ if (value)
+ GPSR = GPIO_GPIO(offset);
+ else
+ GPCR = GPIO_GPIO(offset);
+}
+
+static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ GPDR &= ~GPIO_GPIO(offset);
+ local_irq_restore(flags);
+ return 0;
+}
+
+static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ sa1100_gpio_set(chip, offset, value);
+ GPDR |= GPIO_GPIO(offset);
+ local_irq_restore(flags);
+ return 0;
+}
+
+static struct gpio_chip sa1100_gpio_chip = {
+ .label = "gpio",
+ .direction_input = sa1100_direction_input,
+ .direction_output = sa1100_direction_output,
+ .set = sa1100_gpio_set,
+ .get = sa1100_gpio_get,
+ .base = 0,
+ .ngpio = GPIO_MAX + 1,
+};
+
+void __init sa1100_init_gpio(void)
+{
+ gpiochip_add(&sa1100_gpio_chip);
+}
*/
set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
+
+ sa1100_init_gpio();
}
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/timex.h>
-#include <linux/signal.h>
-#include <linux/clocksource.h>
+#include <linux/clockchips.h>
#include <asm/mach/time.h>
#include <asm/hardware.h>
-#define RTC_DEF_DIVIDER (32768 - 1)
-#define RTC_DEF_TRIM 0
+#define MIN_OSCR_DELTA 2
-static int sa1100_set_rtc(void)
+static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
{
- unsigned long current_time = xtime.tv_sec;
+ struct clock_event_device *c = dev_id;
- if (RTSR & RTSR_ALE) {
- /* make sure not to forward the clock over an alarm */
- unsigned long alarm = RTAR;
- if (current_time >= alarm && alarm >= RCNR)
- return -ERESTARTSYS;
- }
- RCNR = current_time;
- return 0;
-}
+ /* Disarm the compare/match, signal the event. */
+ OIER &= ~OIER_E0;
+ OSSR = OSSR_M0;
+ c->event_handler(c);
-#ifdef CONFIG_NO_IDLE_HZ
-static unsigned long initial_match;
-static int match_posponed;
-#endif
+ return IRQ_HANDLED;
+}
-static irqreturn_t
-sa1100_timer_interrupt(int irq, void *dev_id)
+static int
+sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
{
- unsigned int next_match;
+ unsigned long flags, next, oscr;
-#ifdef CONFIG_NO_IDLE_HZ
- if (match_posponed) {
- match_posponed = 0;
- OSMR0 = initial_match;
- }
-#endif
+ raw_local_irq_save(flags);
+ OIER |= OIER_E0;
+ next = OSCR + delta;
+ OSMR0 = next;
+ oscr = OSCR;
+ raw_local_irq_restore(flags);
- /*
- * Loop until we get ahead of the free running timer.
- * This ensures an exact clock tick count and time accuracy.
- * Since IRQs are disabled at this point, coherence between
- * lost_ticks(updated in do_timer()) and the match reg value is
- * ensured, hence we can use do_gettimeofday() from interrupt
- * handlers.
- */
- do {
- timer_tick();
- OSSR = OSSR_M0; /* Clear match on timer 0 */
- next_match = (OSMR0 += LATCH);
- } while ((signed long)(next_match - OSCR) <= 0);
+ return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
+}
- return IRQ_HANDLED;
+static void
+sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
+{
+ unsigned long flags;
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_ONESHOT:
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ raw_local_irq_save(flags);
+ OIER &= ~OIER_E0;
+ OSSR = OSSR_M0;
+ raw_local_irq_restore(flags);
+ break;
+
+ case CLOCK_EVT_MODE_RESUME:
+ case CLOCK_EVT_MODE_PERIODIC:
+ break;
+ }
}
-static struct irqaction sa1100_timer_irq = {
- .name = "SA11xx Timer Tick",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = sa1100_timer_interrupt,
+static struct clock_event_device ckevt_sa1100_osmr0 = {
+ .name = "osmr0",
+ .features = CLOCK_EVT_FEAT_ONESHOT,
+ .shift = 32,
+ .rating = 200,
+ .cpumask = CPU_MASK_CPU0,
+ .set_next_event = sa1100_osmr0_set_next_event,
+ .set_mode = sa1100_osmr0_set_mode,
};
static cycle_t sa1100_read_oscr(void)
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
+static struct irqaction sa1100_timer_irq = {
+ .name = "ost0",
+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .handler = sa1100_ost0_interrupt,
+ .dev_id = &ckevt_sa1100_osmr0,
+};
+
static void __init sa1100_timer_init(void)
{
- unsigned long flags;
-
- set_rtc = sa1100_set_rtc;
-
OIER = 0; /* disable any timer interrupts */
OSSR = 0xf; /* clear status on all timers */
- setup_irq(IRQ_OST0, &sa1100_timer_irq);
- local_irq_save(flags);
- OIER = OIER_E0; /* enable match on timer 0 to cause interrupts */
- OSMR0 = OSCR + LATCH; /* set initial match */
- local_irq_restore(flags);
+
+ ckevt_sa1100_osmr0.mult =
+ div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift);
+ ckevt_sa1100_osmr0.max_delta_ns =
+ clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
+ ckevt_sa1100_osmr0.min_delta_ns =
+ clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
cksrc_sa1100_oscr.mult =
clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift);
- clocksource_register(&cksrc_sa1100_oscr);
-}
-
-#ifdef CONFIG_NO_IDLE_HZ
-static int sa1100_dyn_tick_enable_disable(void)
-{
- /* nothing to do */
- return 0;
-}
-
-static void sa1100_dyn_tick_reprogram(unsigned long ticks)
-{
- if (ticks > 1) {
- initial_match = OSMR0;
- OSMR0 = initial_match + ticks * LATCH;
- match_posponed = 1;
- }
-}
+ setup_irq(IRQ_OST0, &sa1100_timer_irq);
-static irqreturn_t
-sa1100_dyn_tick_handler(int irq, void *dev_id)
-{
- if (match_posponed) {
- match_posponed = 0;
- OSMR0 = initial_match;
- if ((signed long)(initial_match - OSCR) <= 0)
- return sa1100_timer_interrupt(irq, dev_id);
- }
- return IRQ_NONE;
+ clocksource_register(&cksrc_sa1100_oscr);
+ clockevents_register_device(&ckevt_sa1100_osmr0);
}
-static struct dyn_tick_timer sa1100_dyn_tick = {
- .enable = sa1100_dyn_tick_enable_disable,
- .disable = sa1100_dyn_tick_enable_disable,
- .reprogram = sa1100_dyn_tick_reprogram,
- .handler = sa1100_dyn_tick_handler,
-};
-#endif
-
#ifdef CONFIG_PM
unsigned long osmr[4], oier;
.init = sa1100_timer_init,
.suspend = sa1100_timer_suspend,
.resume = sa1100_timer_resume,
-#ifdef CONFIG_NO_IDLE_HZ
- .dyn_tick = &sa1100_dyn_tick,
-#endif
};
#include <linux/clk.h>
#include <linux/mutex.h>
-#include <asm/semaphore.h>
#include <asm/hardware/icst307.h>
#include "clock.h"
select CPU_CP15_MMU
select CPU_COPY_V3 if MMU
select CPU_TLB_V3 if MMU
+ select CPU_PABRT_NOIFAR
help
The ARM610 is the successor to the ARM3 processor
and was produced by VLSI Technology Inc.
select CPU_CP15_MMU
select CPU_COPY_V3 if MMU
select CPU_TLB_V3 if MMU
+ select CPU_PABRT_NOIFAR
help
A 32-bit RISC microprocessor based on the ARM7 processor core
designed by Advanced RISC Machines Ltd. The ARM710 is the
default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
select CPU_32v4T
select CPU_ABRT_LV4T
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
select CPU_32v4T
select CPU_ABRT_EV4T
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y if ARCH_LH7A40X || ARCH_KS8695
select CPU_32v4T
select CPU_ABRT_EV4T
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y if ARCH_OMAP15XX
select CPU_32v4T
select CPU_ABRT_EV4T
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
select CPU_32v5
select CPU_ABRT_EV5TJ
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_COPY_V4WB if MMU
depends on ARCH_INTEGRATOR
select CPU_32v5
select CPU_ABRT_EV4T
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_CP15_MMU
depends on ARCH_INTEGRATOR
select CPU_32v5
select CPU_ABRT_EV4T
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WT
select CPU_CACHE_VIVT
select CPU_CP15_MMU
depends on ARCH_INTEGRATOR
select CPU_32v5
select CPU_ABRT_EV4T
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_COPY_V4WB if MMU # can probably do better
depends on ARCH_INTEGRATOR
select CPU_32v5
select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_COPY_V4WB if MMU # can probably do better
select CPU_32v3 if ARCH_RPC
select CPU_32v4 if !ARCH_RPC
select CPU_ABRT_EV4
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WB
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y
select CPU_32v4
select CPU_ABRT_EV4
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_V4WB
select CPU_CACHE_VIVT
select CPU_CP15_MMU
default y
select CPU_32v5
select CPU_ABRT_EV5T
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_TLB_V4WBI if MMU
# Feroceon
config CPU_FEROCEON
bool
- depends on ARCH_ORION
+ depends on ARCH_ORION5X
default y
select CPU_32v5
select CPU_ABRT_EV5T
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_VIVT
select CPU_CP15_MMU
select CPU_COPY_V4WB if MMU
# ARMv6
config CPU_V6
bool "Support ARM V6 processor"
- depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A
+ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
default y if ARCH_MX3
default y if ARCH_MSM7X00A
select CPU_32v6
select CPU_ABRT_EV6
+ select CPU_PABRT_NOIFAR
select CPU_CACHE_V6
select CPU_CACHE_VIPT
select CPU_CP15_MMU
# ARMv7
config CPU_V7
bool "Support ARM V7 processor"
- depends on ARCH_INTEGRATOR
+ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
select CPU_32v6K
select CPU_32v7
select CPU_ABRT_EV7
+ select CPU_PABRT_IFAR
select CPU_CACHE_V7
select CPU_CACHE_VIPT
select CPU_CP15_MMU
config CPU_ABRT_EV7
bool
+config CPU_PABRT_IFAR
+ bool
+
+config CPU_PABRT_NOIFAR
+ bool
+
# The cache model
config CPU_CACHE_V3
bool
If you don't know what this all is, saying Y is a safe choice.
+config ARM_THUMBEE
+ bool "Enable ThumbEE CPU extension"
+ depends on CPU_V7
+ help
+ Say Y here if you have a CPU with the ThumbEE extension and code to
+ make use of it. Say N for code that can run on CPUs without ThumbEE.
+
config CPU_BIG_ENDIAN
bool "Build big-endian kernel"
depends on ARCH_SUPPORTS_BIG_ENDIAN
default n
config CACHE_L2X0
- bool
+ bool "Enable the L2x0 outer cache controller"
+ depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
+ default y
select OUTER_CACHE
+ help
+ This option enables the L2x0 PrimeCell.
printk("Mem-info:\n");
show_free_areas();
- printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
-
for_each_online_node(node) {
pg_data_t *n = NODE_DATA(node);
struct page *map = n->node_mem_map - n->node_start_pfn;
.word cpu_arm1020_dcache_clean_area
.word cpu_arm1020_switch_mm
.word cpu_arm1020_set_pte_ext
+ .word pabort_noifar
.size arm1020_processor_functions, . - arm1020_processor_functions
.section ".rodata"
.word cpu_arm1020e_dcache_clean_area
.word cpu_arm1020e_switch_mm
.word cpu_arm1020e_set_pte_ext
+ .word pabort_noifar
.size arm1020e_processor_functions, . - arm1020e_processor_functions
.section ".rodata"
.word cpu_arm1022_dcache_clean_area
.word cpu_arm1022_switch_mm
.word cpu_arm1022_set_pte_ext
+ .word pabort_noifar
.size arm1022_processor_functions, . - arm1022_processor_functions
.section ".rodata"
.word cpu_arm1026_dcache_clean_area
.word cpu_arm1026_switch_mm
.word cpu_arm1026_set_pte_ext
+ .word pabort_noifar
.size arm1026_processor_functions, . - arm1026_processor_functions
.section .rodata
.word cpu_arm6_dcache_clean_area
.word cpu_arm6_switch_mm
.word cpu_arm6_set_pte_ext
+ .word pabort_noifar
.size arm6_processor_functions, . - arm6_processor_functions
/*
.word cpu_arm7_dcache_clean_area
.word cpu_arm7_switch_mm
.word cpu_arm7_set_pte_ext
+ .word pabort_noifar
.size arm7_processor_functions, . - arm7_processor_functions
.section ".rodata"
.word cpu_arm720_dcache_clean_area
.word cpu_arm720_switch_mm
.word cpu_arm720_set_pte_ext
+ .word pabort_noifar
.size arm720_processor_functions, . - arm720_processor_functions
.section ".rodata"
.word cpu_arm920_dcache_clean_area
.word cpu_arm920_switch_mm
.word cpu_arm920_set_pte_ext
+ .word pabort_noifar
.size arm920_processor_functions, . - arm920_processor_functions
.section ".rodata"
.word cpu_arm922_dcache_clean_area
.word cpu_arm922_switch_mm
.word cpu_arm922_set_pte_ext
+ .word pabort_noifar
.size arm922_processor_functions, . - arm922_processor_functions
.section ".rodata"
.word cpu_arm925_dcache_clean_area
.word cpu_arm925_switch_mm
.word cpu_arm925_set_pte_ext
+ .word pabort_noifar
.size arm925_processor_functions, . - arm925_processor_functions
.section ".rodata"
.word cpu_arm926_dcache_clean_area
.word cpu_arm926_switch_mm
.word cpu_arm926_set_pte_ext
+ .word pabort_noifar
.size arm926_processor_functions, . - arm926_processor_functions
.section ".rodata"
.word cpu_feroceon_dcache_clean_area
.word cpu_feroceon_switch_mm
.word cpu_feroceon_set_pte_ext
+ .word pabort_noifar
.size feroceon_processor_functions, . - feroceon_processor_functions
.section ".rodata"
.word cpu_sa110_dcache_clean_area
.word cpu_sa110_switch_mm
.word cpu_sa110_set_pte_ext
+ .word pabort_noifar
.size sa110_processor_functions, . - sa110_processor_functions
.section ".rodata"
.word cpu_sa1100_dcache_clean_area
.word cpu_sa1100_switch_mm
.word cpu_sa1100_set_pte_ext
+ .word pabort_noifar
.size sa1100_processor_functions, . - sa1100_processor_functions
.section ".rodata"
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
-#ifdef CONFIG_SMP
-#include <asm/hardware/arm_scu.h>
-#endif
-
#include "proc-macros.S"
#define D_CACHE_LINE_SIZE 32
*/
__v6_setup:
#ifdef CONFIG_SMP
- /* Set up the SCU on core 0 only */
- mrc p15, 0, r0, c0, c0, 5 @ CPU core number
- ands r0, r0, #15
- ldreq r0, =SCU_BASE
- ldreq r5, [r0, #SCU_CTRL]
- orreq r5, r5, #1
- streq r5, [r0, #SCU_CTRL]
-
-#ifndef CONFIG_CPU_DCACHE_DISABLE
mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
orr r0, r0, #0x20
mcr p15, 0, r0, c1, c0, 1
-#endif
#endif
mov r0, #0
.word cpu_v6_dcache_clean_area
.word cpu_v6_switch_mm
.word cpu_v6_set_pte_ext
+ .word pabort_noifar
.size v6_processor_functions, . - v6_processor_functions
.type cpu_arch_name, #object
.word cpu_v7_dcache_clean_area
.word cpu_v7_switch_mm
.word cpu_v7_set_pte_ext
+ .word pabort_ifar
.size v7_processor_functions, . - v7_processor_functions
.type cpu_arch_name, #object
.word cpu_xscale_dcache_clean_area
.word cpu_xscale_switch_mm
.word cpu_xscale_set_pte_ext
+ .word pabort_noifar
.size xscale_processor_functions, . - xscale_processor_functions
.section ".rodata"
#include <asm/hardware.h>
#include <asm/mach/pci.h>
#include <asm/hardware/iop3xx.h>
+#include <asm/mach-types.h>
// #define DEBUG
res[1].flags = IORESOURCE_MEM;
request_resource(&iomem_resource, &res[1]);
- sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
- sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA;
+ /*
+ * Use whatever translation is already setup.
+ */
+ sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
+ sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
sys->resource[0] = &res[0];
sys->resource[1] = &res[1];
*IOP3XX_IATVR2 = PHYS_OFFSET;
/* Outbound window 0 */
- *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA;
+ *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA;
*IOP3XX_OUMWTVR0 = 0;
/* Outbound window 1 */
- *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE;
+ *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE;
*IOP3XX_OUMWTVR1 = 0;
/* BAR 3 ( Disabled ) */
/* Setup the I/O Bar
*/
- *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;;
+ *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA;
/* Enable inbound and outbound cycles
*/
/* Flag to determine whether the ATU is initialized and the PCI bus scanned */
int init_atu;
-void __init iop3xx_pci_preinit(void)
+int iop3xx_get_init_atu(void) {
+ /* check if default has been overridden */
+ if (init_atu != IOP3XX_INIT_ATU_DEFAULT)
+ return init_atu;
+ else
+ return IOP3XX_INIT_ATU_DISABLE;
+}
+
+static void __init iop3xx_atu_debug(void)
{
- if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
- iop3xx_atu_disable();
- iop3xx_atu_setup();
- }
+ DBG("PCI: Intel IOP3xx PCI init.\n");
+ DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n",
+ *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0);
+ DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n",
+ *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1);
+ DBG("PCI: Outbound IO window: PCI 0x%08x\n",
+ *IOP3XX_OIOWTVR);
+
+ DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+ *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
+ DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n",
+ *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1);
+ DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+ *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
+ DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+ *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
+
+ DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+ 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
- DBG("PCI: Intel 803xx PCI init code.\n");
DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
- DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
- *IOP3XX_OMWTVR0,
- *IOP3XX_OIOWTVR);
DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
- DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
- *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
- DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
- DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
- *IOP3XX_IABAR1, *IOP3XX_IALR1);
- DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
- *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
- DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
- *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
- DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
- *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
}
+/* for platforms that might be host-bus-adapters */
+void __init iop3xx_pci_preinit_cond(void)
+{
+ if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
+ iop3xx_atu_disable();
+ iop3xx_atu_setup();
+ iop3xx_atu_debug();
+ }
+}
+
+void __init iop3xx_pci_preinit(void)
+{
+ iop3xx_atu_disable();
+ iop3xx_atu_setup();
+ iop3xx_atu_debug();
+}
+
/* allow init_atu to be user overridden */
static int __init iop3xx_init_atu_setup(char *str)
{
choice
prompt "MXC/iMX System Type"
- default 0
+ default ARCH_MX3
config ARCH_MX3
bool "MX3-based"
# Common support
obj-y := irq.o
-
-obj-m :=
-obj-n :=
-obj- :=
#include <asm/mach/irq.h>
#include <asm/arch/common.h>
-/*!
- * Disable interrupt number "irq" in the AVIC
- *
- * @param irq interrupt source number
- */
+/* Disable interrupt number "irq" in the AVIC */
static void mxc_mask_irq(unsigned int irq)
{
__raw_writel(irq, AVIC_INTDISNUM);
}
-/*!
- * Enable interrupt number "irq" in the AVIC
- *
- * @param irq interrupt source number
- */
+/* Enable interrupt number "irq" in the AVIC */
static void mxc_unmask_irq(unsigned int irq)
{
__raw_writel(irq, AVIC_INTENNUM);
.unmask = mxc_unmask_irq,
};
-/*!
+/*
* This function initializes the AVIC hardware and disables all the
* interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source.
obj-n :=
obj- :=
-obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
-
# OCPI interconnect support for 1710, 1610 and 5912
obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
#include <linux/platform_device.h>
#include <asm/io.h>
-#include <asm/semaphore.h>
#include <asm/arch/clock.h>
}
}
+/**
+ * recalculate_root_clocks - recalculate and propagate all root clocks
+ *
+ * Recalculates all root clocks (clocks with no parent), which if the
+ * clock's .recalc is set correctly, should also propagate their rates.
+ * Called at init.
+ */
+void recalculate_root_clocks(void)
+{
+ struct clk *clkp;
+
+ list_for_each_entry(clkp, &clocks, node) {
+ if (unlikely(!clkp->parent) && likely((u32)clkp->recalc))
+ clkp->recalc(clkp);
+ }
+}
+
int clk_register(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
}
EXPORT_SYMBOL(clk_allow_idle);
+void clk_enable_init_clocks(void)
+{
+ struct clk *clkp;
+
+ list_for_each_entry(clkp, &clocks, node) {
+ if (clkp->flags & ENABLE_ON_INIT)
+ clk_enable(clkp);
+ }
+}
+EXPORT_SYMBOL(clk_enable_init_clocks);
+
+#ifdef CONFIG_CPU_FREQ
+void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clockfw_lock, flags);
+ if (arch_clock->clk_init_cpufreq_table)
+ arch_clock->clk_init_cpufreq_table(table);
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+EXPORT_SYMBOL(clk_init_cpufreq_table);
+#endif
+
/*-------------------------------------------------------------------------*/
#ifdef CONFIG_OMAP_RESET_CLOCKS
return 0;
}
+
#include <asm/setup.h>
#include <asm/arch/board.h>
+#include <asm/arch/control.h>
#include <asm/arch/mux.h>
#include <asm/arch/fpga.h>
#include <asm/arch/clock.h>
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+# include "../mach-omap2/sdrc.h"
+#endif
+
#define NO_LENGTH_CHECK 0xffffffff
unsigned char omap_bootloader_tag[512];
#if defined(CONFIG_ARCH_OMAP16XX)
#define TIMER_32K_SYNCHRONIZED 0xfffbc410
-#elif defined(CONFIG_ARCH_OMAP24XX)
-#define TIMER_32K_SYNCHRONIZED (OMAP24XX_32KSYNCT_BASE + 0x10)
+#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10)
#endif
#ifdef TIMER_32K_SYNCHRONIZED
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
+/*
+ * Rounds down to nearest nsec.
+ */
+unsigned long long omap_32k_ticks_to_nsecs(unsigned long ticks_32k)
+{
+ return cyc2ns(&clocksource_32k, ticks_32k);
+}
+
+/*
+ * Returns current time from boot in nsecs. It's OK for this to wrap
+ * around for now, as it's just a relative time stamp.
+ */
+unsigned long long sched_clock(void)
+{
+ return omap_32k_ticks_to_nsecs(omap_32k_read());
+}
+
static int __init omap_init_clocksource_32k(void)
{
static char err[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
- if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
+ if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
+ struct clk *sync_32k_ick;
+
+ sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
+ if (sync_32k_ick)
+ clk_enable(sync_32k_ick);
+
clocksource_32k.mult = clocksource_hz2mult(32768,
clocksource_32k.shift);
arch_initcall(omap_init_clocksource_32k);
#endif /* TIMER_32K_SYNCHRONIZED */
+
+/* Global address base setup code */
+
+#if defined(CONFIG_ARCH_OMAP2420)
+void __init omap2_set_globals_242x(void)
+{
+ omap2_sdrc_base = OMAP2420_SDRC_BASE;
+ omap2_sms_base = OMAP2420_SMS_BASE;
+ omap_ctrl_base_set(OMAP2420_CTRL_BASE);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2430)
+void __init omap2_set_globals_243x(void)
+{
+ omap2_sdrc_base = OMAP243X_SDRC_BASE;
+ omap2_sms_base = OMAP243X_SMS_BASE;
+ omap_ctrl_base_set(OMAP243X_CTRL_BASE);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3430)
+void __init omap2_set_globals_343x(void)
+{
+ omap2_sdrc_base = OMAP343X_SDRC_BASE;
+ omap2_sms_base = OMAP343X_SMS_BASE;
+ omap_ctrl_base_set(OMAP343X_CTRL_BASE);
+}
+#endif
+
u16 irq;
u16 virtual_irq_start;
int method;
- u32 reserved_map;
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
u32 suspend_wakeup;
u32 saved_wakeup;
u32 saved_fallingdetect;
u32 saved_risingdetect;
#endif
+ u32 level_mask;
spinlock_t lock;
+ struct gpio_chip chip;
};
#define METHOD_MPUIO 0
bank->enabled_non_wakeup_gpios &= ~gpio_bit;
}
- /*
- * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
- * level triggering requested.
- */
+ bank->level_mask =
+ __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+ __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
}
#endif
irq_desc[irq].status |= type;
}
spin_unlock_irqrestore(&bank->lock, flags);
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+ __set_irq_handler_unlocked(irq, handle_level_irq);
+ else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
+ __set_irq_handler_unlocked(irq, handle_edge_irq);
+
return retval;
}
{
struct gpio_bank *bank;
unsigned long flags;
+ int status;
if (check_gpio(gpio) < 0)
return -EINVAL;
+ status = gpio_request(gpio, NULL);
+ if (status < 0)
+ return status;
+
bank = get_gpio_bank(gpio);
spin_lock_irqsave(&bank->lock, flags);
- if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
- printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
- dump_stack();
- spin_unlock_irqrestore(&bank->lock, flags);
- return -1;
- }
- bank->reserved_map |= (1 << get_gpio_index(gpio));
/* Set trigger to none. You need to enable the desired trigger with
* request_irq() or set_irq_type().
return;
bank = get_gpio_bank(gpio);
spin_lock_irqsave(&bank->lock, flags);
- if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
+ if (unlikely(!gpiochip_is_requested(&bank->chip,
+ get_gpio_index(gpio)))) {
+ spin_unlock_irqrestore(&bank->lock, flags);
printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
dump_stack();
- spin_unlock_irqrestore(&bank->lock, flags);
return;
}
#ifdef CONFIG_ARCH_OMAP16XX
__raw_writel(1 << get_gpio_index(gpio), reg);
}
#endif
- bank->reserved_map &= ~(1 << get_gpio_index(gpio));
_reset_gpio(bank, gpio);
spin_unlock_irqrestore(&bank->lock, flags);
+ gpio_free(gpio);
}
/*
isr &= 0x0000ffff;
if (cpu_class_is_omap2()) {
- level_mask =
- __raw_readl(bank->base +
- OMAP24XX_GPIO_LEVELDETECT0) |
- __raw_readl(bank->base +
- OMAP24XX_GPIO_LEVELDETECT1);
- level_mask &= enabled;
+ level_mask = bank->level_mask & enabled;
}
/* clear edge sensitive interrupts before handler(s) are
gpio_irq = bank->virtual_irq_start;
for (; isr != 0; isr >>= 1, gpio_irq++) {
struct irq_desc *d;
- int irq_mask;
+
if (!(isr & 1))
continue;
d = irq_desc + gpio_irq;
- /* Don't run the handler if it's already running
- * or was disabled lazely.
- */
- if (unlikely((d->depth ||
- (d->status & IRQ_INPROGRESS)))) {
- irq_mask = 1 <<
- (gpio_irq - bank->virtual_irq_start);
- /* The unmasking will be done by
- * enable_irq in case it is disabled or
- * after returning from the handler if
- * it's already running.
- */
- _enable_gpio_irqbank(bank, irq_mask, 0);
- if (!d->depth) {
- /* Level triggered interrupts
- * won't ever be reentered
- */
- BUG_ON(level_mask & irq_mask);
- d->status |= IRQ_PENDING;
- }
- continue;
- }
desc_handle_irq(gpio_irq, d);
-
- if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
- irq_mask = 1 <<
- (gpio_irq - bank->virtual_irq_start);
- d->status &= ~IRQ_PENDING;
- _enable_gpio_irqbank(bank, irq_mask, 1);
- retrigger |= irq_mask;
- }
}
-
- if (cpu_class_is_omap2()) {
- /* clear level sensitive interrupts after handler(s) */
- _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
- _clear_gpio_irqbank(bank, isr_saved & level_mask);
- _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
- }
-
}
/* if bank has any level sensitive GPIO pin interrupt
configured, we must unmask the bank interrupt only after
{
unsigned int gpio = irq - IH_GPIO_BASE;
struct gpio_bank *bank = get_irq_chip_data(irq);
+ unsigned int irq_mask = 1 << get_gpio_index(gpio);
+
+ /* For level-triggered GPIOs, the clearing must be done after
+ * the HW source is cleared, thus after the handler has run */
+ if (bank->level_mask & irq_mask) {
+ _set_gpio_irqenable(bank, gpio, 0);
+ _clear_gpio_irqstatus(bank, gpio);
+ }
_set_gpio_irqenable(bank, gpio, 1);
}
/*---------------------------------------------------------------------*/
+/* REVISIT these are stupid implementations! replace by ones that
+ * don't switch on METHOD_* and which mostly avoid spinlocks
+ */
+
+static int gpio_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct gpio_bank *bank;
+ unsigned long flags;
+
+ bank = container_of(chip, struct gpio_bank, chip);
+ spin_lock_irqsave(&bank->lock, flags);
+ _set_gpio_direction(bank, offset, 1);
+ spin_unlock_irqrestore(&bank->lock, flags);
+ return 0;
+}
+
+static int gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ return omap_get_gpio_datain(chip->base + offset);
+}
+
+static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct gpio_bank *bank;
+ unsigned long flags;
+
+ bank = container_of(chip, struct gpio_bank, chip);
+ spin_lock_irqsave(&bank->lock, flags);
+ _set_gpio_dataout(bank, offset, value);
+ _set_gpio_direction(bank, offset, 0);
+ spin_unlock_irqrestore(&bank->lock, flags);
+ return 0;
+}
+
+static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct gpio_bank *bank;
+ unsigned long flags;
+
+ bank = container_of(chip, struct gpio_bank, chip);
+ spin_lock_irqsave(&bank->lock, flags);
+ _set_gpio_dataout(bank, offset, value);
+ spin_unlock_irqrestore(&bank->lock, flags);
+}
+
+/*---------------------------------------------------------------------*/
+
static int initialized;
#if !defined(CONFIG_ARCH_OMAP3)
static struct clk * gpio_ick;
static int __init _omap_gpio_init(void)
{
int i;
+ int gpio = 0;
struct gpio_bank *bank;
#if defined(CONFIG_ARCH_OMAP3)
char clk_name[11];
int j, gpio_count = 16;
bank = &gpio_bank[i];
- bank->reserved_map = 0;
bank->base = IO_ADDRESS(bank->base);
spin_lock_init(&bank->lock);
if (bank_is_mpuio(bank))
gpio_count = 32;
}
#endif
+
+ /* REVISIT eventually switch from OMAP-specific gpio structs
+ * over to the generic ones
+ */
+ bank->chip.direction_input = gpio_input;
+ bank->chip.get = gpio_get;
+ bank->chip.direction_output = gpio_output;
+ bank->chip.set = gpio_set;
+ if (bank_is_mpuio(bank)) {
+ bank->chip.label = "mpuio";
+ bank->chip.base = OMAP_MPUIO(0);
+ } else {
+ bank->chip.label = "gpio";
+ bank->chip.base = gpio;
+ gpio += gpio_count;
+ }
+ bank->chip.ngpio = gpio_count;
+
+ gpiochip_add(&bank->chip);
+
for (j = bank->virtual_irq_start;
j < bank->virtual_irq_start + gpio_count; j++) {
lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
unsigned irq, value, is_in, irqstat;
+ const char *label;
- if (!(bank->reserved_map & mask))
+ label = gpiochip_is_requested(&bank->chip, j);
+ if (!label)
continue;
irq = bank->virtual_irq_start + j;
is_in = gpio_is_input(bank, mask);
if (bank_is_mpuio(bank))
- seq_printf(s, "MPUIO %2d: ", j);
+ seq_printf(s, "MPUIO %2d ", j);
else
- seq_printf(s, "GPIO %3d: ", gpio);
- seq_printf(s, "%s %s",
+ seq_printf(s, "GPIO %3d ", gpio);
+ seq_printf(s, "(%10s): %s %s",
+ label,
is_in ? "in " : "out",
value ? "hi" : "lo");
+/* FIXME for at least omap2, show pullup/pulldown state */
+
irqstat = irq_desc[irq].status;
if (is_in && ((bank->suspend_wakeup & mask)
|| irqstat & IRQ_TYPE_SENSE_MASK)) {
trigger = "high";
break;
case IRQ_TYPE_NONE:
- trigger = "(unspecified)";
+ trigger = "(?)";
break;
}
- seq_printf(s, ", irq-%d %s%s",
+ seq_printf(s, ", irq-%d %-8s%s",
irq, trigger,
(bank->suspend_wakeup & mask)
? " wakeup" : "");
*
* Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
*
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2003 - 2008 Nokia Corporation
*
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#ifdef CONFIG_OMAP_MUX
-#define OMAP24XX_L4_BASE 0x48000000
-#define OMAP24XX_PULL_ENA (1 << 3)
-#define OMAP24XX_PULL_UP (1 << 4)
+static struct omap_mux_cfg *mux_cfg;
-static struct pin_config * pin_table;
-static unsigned long pin_table_sz;
-
-extern struct pin_config * omap730_pins;
-extern struct pin_config * omap1xxx_pins;
-extern struct pin_config * omap24xx_pins;
-
-int __init omap_mux_register(struct pin_config * pins, unsigned long size)
+int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
{
- pin_table = pins;
- pin_table_sz = size;
+ if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
+ || !arch_mux_cfg->cfg_reg) {
+ printk(KERN_ERR "Invalid pin table\n");
+ return -EINVAL;
+ }
+
+ mux_cfg = arch_mux_cfg;
return 0;
}
*/
int __init_or_module omap_cfg_reg(const unsigned long index)
{
- static DEFINE_SPINLOCK(mux_spin_lock);
-
- unsigned long flags;
- struct pin_config *cfg;
- unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
- pull_orig = 0, pull = 0;
- unsigned int mask, warn = 0;
+ struct pin_config *reg;
- if (!pin_table)
- BUG();
+ if (mux_cfg == NULL) {
+ printk(KERN_ERR "Pin mux table not initialized\n");
+ return -ENODEV;
+ }
- if (index >= pin_table_sz) {
+ if (index >= mux_cfg->size) {
printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
- index, pin_table_sz);
+ index, mux_cfg->size);
dump_stack();
return -ENODEV;
}
- cfg = (struct pin_config *)&pin_table[index];
- if (cpu_is_omap24xx()) {
- u8 reg = 0;
-
- reg |= cfg->mask & 0x7;
- if (cfg->pull_val)
- reg |= OMAP24XX_PULL_ENA;
- if(cfg->pu_pd_val)
- reg |= OMAP24XX_PULL_UP;
-#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
- {
- u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
- u8 debug = 0;
-
-#ifdef CONFIG_OMAP_MUX_DEBUG
- debug = cfg->debug;
-#endif
- warn = (orig != reg);
- if (debug || warn)
- printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
- cfg->name,
- OMAP24XX_L4_BASE + cfg->mux_reg,
- orig, reg);
- }
-#endif
- omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
+ reg = (struct pin_config *)&mux_cfg->pins[index];
- return 0;
- }
-
- /* Check the mux register in question */
- if (cfg->mux_reg) {
- unsigned tmp1, tmp2;
-
- spin_lock_irqsave(&mux_spin_lock, flags);
- reg_orig = omap_readl(cfg->mux_reg);
-
- /* The mux registers always seem to be 3 bits long */
- mask = (0x7 << cfg->mask_offset);
- tmp1 = reg_orig & mask;
- reg = reg_orig & ~mask;
-
- tmp2 = (cfg->mask << cfg->mask_offset);
- reg |= tmp2;
-
- if (tmp1 != tmp2)
- warn = 1;
-
- omap_writel(reg, cfg->mux_reg);
- spin_unlock_irqrestore(&mux_spin_lock, flags);
- }
-
- /* Check for pull up or pull down selection on 1610 */
- if (!cpu_is_omap15xx()) {
- if (cfg->pu_pd_reg && cfg->pull_val) {
- spin_lock_irqsave(&mux_spin_lock, flags);
- pu_pd_orig = omap_readl(cfg->pu_pd_reg);
- mask = 1 << cfg->pull_bit;
-
- if (cfg->pu_pd_val) {
- if (!(pu_pd_orig & mask))
- warn = 1;
- /* Use pull up */
- pu_pd = pu_pd_orig | mask;
- } else {
- if (pu_pd_orig & mask)
- warn = 1;
- /* Use pull down */
- pu_pd = pu_pd_orig & ~mask;
- }
- omap_writel(pu_pd, cfg->pu_pd_reg);
- spin_unlock_irqrestore(&mux_spin_lock, flags);
- }
- }
-
- /* Check for an associated pull down register */
- if (cfg->pull_reg) {
- spin_lock_irqsave(&mux_spin_lock, flags);
- pull_orig = omap_readl(cfg->pull_reg);
- mask = 1 << cfg->pull_bit;
-
- if (cfg->pull_val) {
- if (pull_orig & mask)
- warn = 1;
- /* Low bit = pull enabled */
- pull = pull_orig & ~mask;
- } else {
- if (!(pull_orig & mask))
- warn = 1;
- /* High bit = pull disabled */
- pull = pull_orig | mask;
- }
-
- omap_writel(pull, cfg->pull_reg);
- spin_unlock_irqrestore(&mux_spin_lock, flags);
- }
-
- if (warn) {
-#ifdef CONFIG_OMAP_MUX_WARNINGS
- printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
-#endif
- }
-
-#ifdef CONFIG_OMAP_MUX_DEBUG
- if (cfg->debug || warn) {
- printk("MUX: Setting register %s\n", cfg->name);
- printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
- cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
-
- if (!cpu_is_omap15xx()) {
- if (cfg->pu_pd_reg && cfg->pull_val) {
- printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
- cfg->pu_pd_name, cfg->pu_pd_reg,
- pu_pd_orig, pu_pd);
- }
- }
-
- if (cfg->pull_reg)
- printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
- cfg->pull_name, cfg->pull_reg, pull_orig, pull);
- }
-#endif
+ if (!mux_cfg->cfg_reg)
+ return -ENODEV;
-#ifdef CONFIG_OMAP_MUX_ERRORS
- return warn ? -ETXTBSY : 0;
-#else
- return 0;
-#endif
+ return mux_cfg->cfg_reg(reg);
}
EXPORT_SYMBOL(omap_cfg_reg);
#else
#include <asm/system.h>
#include <asm/hardware.h>
+#include <asm/arch/control.h>
#include <asm/arch/mux.h>
#include <asm/arch/usb.h>
#include <asm/arch/board.h>
/*-------------------------------------------------------------------------*/
-#ifdef CONFIG_ARCH_OMAP_OTG
+#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_USB_MUSB_OTG)
static struct otg_transceiver *xceiv;
#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
+static void omap2_usb_devconf_clear(u8 port, u32 mask)
+{
+ u32 r;
+
+ r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+ r &= ~USBTXWRMODEI(port, mask);
+ omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb_devconf_set(u8 port, u32 mask)
+{
+ u32 r;
+
+ r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+ r |= USBTXWRMODEI(port, mask);
+ omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb2_disable_5pinbitll(void)
+{
+ u32 r;
+
+ r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+ r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
+ omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb2_enable_5pinunitll(void)
+{
+ u32 r;
+
+ r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+ r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
+ omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
{
u32 syscon1 = 0;
if (cpu_is_omap24xx())
- CONTROL_DEVCONF_REG &= ~USBT0WRMODEI(USB_BIDIR_TLL);
+ omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
if (nwires == 0) {
if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
case 3:
syscon1 = 2;
if (cpu_is_omap24xx())
- CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR);
+ omap2_usb_devconf_set(0, USB_BIDIR);
break;
case 4:
syscon1 = 1;
if (cpu_is_omap24xx())
- CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR);
+ omap2_usb_devconf_set(0, USB_BIDIR);
break;
case 6:
syscon1 = 3;
if (cpu_is_omap24xx()) {
omap_cfg_reg(J19_24XX_USB0_VP);
omap_cfg_reg(K20_24XX_USB0_VM);
- CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_UNIDIR);
+ omap2_usb_devconf_set(0, USB_UNIDIR);
} else {
omap_cfg_reg(AA9_USB0_VP);
omap_cfg_reg(R9_USB0_VM);
if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
if (cpu_is_omap24xx())
- CONTROL_DEVCONF_REG &= ~USBT1WRMODEI(USB_BIDIR_TLL);
+ omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
if (nwires == 0)
return 0;
* this TLL link is not using DP/DM
*/
syscon1 = 1;
- CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR_TLL);
+ omap2_usb_devconf_set(1, USB_BIDIR_TLL);
break;
case 3:
syscon1 = 2;
if (cpu_is_omap24xx())
- CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR);
+ omap2_usb_devconf_set(1, USB_BIDIR);
break;
case 4:
syscon1 = 1;
if (cpu_is_omap24xx())
- CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR);
+ omap2_usb_devconf_set(1, USB_BIDIR);
break;
case 6:
if (cpu_is_omap24xx())
u32 syscon1 = 0;
if (cpu_is_omap24xx()) {
- CONTROL_DEVCONF_REG &= ~(USBT2WRMODEI(USB_BIDIR_TLL)
- | USBT2TLL5PI);
+ omap2_usb2_disable_5pinbitll();
alt_pingroup = 0;
}
* this TLL link is not using DP/DM
*/
syscon1 = 1;
- CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR_TLL);
+ omap2_usb_devconf_set(2, USB_BIDIR_TLL);
break;
case 3:
syscon1 = 2;
if (cpu_is_omap24xx())
- CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR);
+ omap2_usb_devconf_set(2, USB_BIDIR);
break;
case 4:
syscon1 = 1;
if (cpu_is_omap24xx())
- CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR);
+ omap2_usb_devconf_set(2, USB_BIDIR);
break;
case 5:
if (!cpu_is_omap24xx())
* set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
*/
syscon1 = 3;
- CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_UNIDIR_TLL)
- | USBT2TLL5PI;
+ omap2_usb2_enable_5pinunitll();
break;
case 6:
if (cpu_is_omap24xx())
--- /dev/null
+#
+# Makefile for the linux kernel.
+#
+
+obj-y := irq.o pcie.o time.o
+obj-m :=
+obj-n :=
+obj- :=
--- /dev/null
+/*
+ * arch/arm/plat-orion/irq.c
+ *
+ * Marvell Orion SoC IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/plat-orion/irq.h>
+
+static void orion_irq_mask(u32 irq)
+{
+ void __iomem *maskaddr = get_irq_chip_data(irq);
+ u32 mask;
+
+ mask = readl(maskaddr);
+ mask &= ~(1 << (irq & 31));
+ writel(mask, maskaddr);
+}
+
+static void orion_irq_unmask(u32 irq)
+{
+ void __iomem *maskaddr = get_irq_chip_data(irq);
+ u32 mask;
+
+ mask = readl(maskaddr);
+ mask |= 1 << (irq & 31);
+ writel(mask, maskaddr);
+}
+
+static struct irq_chip orion_irq_chip = {
+ .name = "orion_irq",
+ .ack = orion_irq_mask,
+ .mask = orion_irq_mask,
+ .unmask = orion_irq_unmask,
+};
+
+void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
+{
+ unsigned int i;
+
+ /*
+ * Mask all interrupts initially.
+ */
+ writel(0, maskaddr);
+
+ /*
+ * Register IRQ sources.
+ */
+ for (i = 0; i < 32; i++) {
+ unsigned int irq = irq_start + i;
+
+ set_irq_chip(irq, &orion_irq_chip);
+ set_irq_chip_data(irq, maskaddr);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+}
--- /dev/null
+/*
+ * arch/arm/plat-orion/pcie.c
+ *
+ * Marvell Orion SoC PCIe handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+
+/*
+ * PCIe unit register offsets.
+ */
+#define PCIE_DEV_ID_OFF 0x0000
+#define PCIE_CMD_OFF 0x0004
+#define PCIE_DEV_REV_OFF 0x0008
+#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
+#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
+#define PCIE_HEADER_LOG_4_OFF 0x0128
+#define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
+#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
+#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
+#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
+#define PCIE_WIN5_CTRL_OFF 0x1880
+#define PCIE_WIN5_BASE_OFF 0x1884
+#define PCIE_WIN5_REMAP_OFF 0x188c
+#define PCIE_CONF_ADDR_OFF 0x18f8
+#define PCIE_CONF_ADDR_EN 0x80000000
+#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
+#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
+#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
+#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
+#define PCIE_CONF_DATA_OFF 0x18fc
+#define PCIE_MASK_OFF 0x1910
+#define PCIE_CTRL_OFF 0x1a00
+#define PCIE_STAT_OFF 0x1a04
+#define PCIE_STAT_DEV_OFFS 20
+#define PCIE_STAT_DEV_MASK 0x1f
+#define PCIE_STAT_BUS_OFFS 8
+#define PCIE_STAT_BUS_MASK 0xff
+#define PCIE_STAT_LINK_DOWN 1
+
+
+u32 __init orion_pcie_dev_id(void __iomem *base)
+{
+ return readl(base + PCIE_DEV_ID_OFF) >> 16;
+}
+
+u32 __init orion_pcie_rev(void __iomem *base)
+{
+ return readl(base + PCIE_DEV_REV_OFF) & 0xff;
+}
+
+int orion_pcie_link_up(void __iomem *base)
+{
+ return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
+}
+
+int orion_pcie_get_local_bus_nr(void __iomem *base)
+{
+ u32 stat = readl(base + PCIE_STAT_OFF);
+
+ return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK;
+}
+
+void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
+{
+ u32 stat;
+
+ stat = readl(base + PCIE_STAT_OFF);
+ stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS);
+ stat |= nr << PCIE_STAT_BUS_OFFS;
+ writel(stat, base + PCIE_STAT_OFF);
+}
+
+/*
+ * Setup PCIE BARs and Address Decode Wins:
+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * WIN[0-3] -> DRAM bank[0-3]
+ */
+static void __init orion_pcie_setup_wins(void __iomem *base,
+ struct mbus_dram_target_info *dram)
+{
+ u32 size;
+ int i;
+
+ /*
+ * First, disable and clear BARs and windows.
+ */
+ for (i = 1; i <= 2; i++) {
+ writel(0, base + PCIE_BAR_CTRL_OFF(i));
+ writel(0, base + PCIE_BAR_LO_OFF(i));
+ writel(0, base + PCIE_BAR_HI_OFF(i));
+ }
+
+ for (i = 0; i < 5; i++) {
+ writel(0, base + PCIE_WIN04_CTRL_OFF(i));
+ writel(0, base + PCIE_WIN04_BASE_OFF(i));
+ writel(0, base + PCIE_WIN04_REMAP_OFF(i));
+ }
+
+ writel(0, base + PCIE_WIN5_CTRL_OFF);
+ writel(0, base + PCIE_WIN5_BASE_OFF);
+ writel(0, base + PCIE_WIN5_REMAP_OFF);
+
+ /*
+ * Setup windows for DDR banks. Count total DDR size on the fly.
+ */
+ size = 0;
+ for (i = 0; i < dram->num_cs; i++) {
+ struct mbus_dram_window *cs = dram->cs + i;
+
+ writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
+ writel(0, base + PCIE_WIN04_REMAP_OFF(i));
+ writel(((cs->size - 1) & 0xffff0000) |
+ (cs->mbus_attr << 8) |
+ (dram->mbus_dram_target_id << 4) | 1,
+ base + PCIE_WIN04_CTRL_OFF(i));
+
+ size += cs->size;
+ }
+
+ /*
+ * Setup BAR[1] to all DRAM banks.
+ */
+ writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
+ writel(0, base + PCIE_BAR_HI_OFF(1));
+ writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
+}
+
+void __init orion_pcie_setup(void __iomem *base,
+ struct mbus_dram_target_info *dram)
+{
+ u16 cmd;
+ u32 mask;
+
+ /*
+ * Point PCIe unit MBUS decode windows to DRAM space.
+ */
+ orion_pcie_setup_wins(base, dram);
+
+ /*
+ * Master + slave enable.
+ */
+ cmd = readw(base + PCIE_CMD_OFF);
+ cmd |= PCI_COMMAND_IO;
+ cmd |= PCI_COMMAND_MEMORY;
+ cmd |= PCI_COMMAND_MASTER;
+ writew(cmd, base + PCIE_CMD_OFF);
+
+ /*
+ * Enable interrupt lines A-D.
+ */
+ mask = readl(base + PCIE_MASK_OFF);
+ mask |= 0x0f000000;
+ writel(mask, base + PCIE_MASK_OFF);
+}
+
+int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val)
+{
+ writel(PCIE_CONF_BUS(bus->number) |
+ PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+ PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+ PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+ base + PCIE_CONF_ADDR_OFF);
+
+ *val = readl(base + PCIE_CONF_DATA_OFF);
+
+ if (size == 1)
+ *val = (*val >> (8 * (where & 3))) & 0xff;
+ else if (size == 2)
+ *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val)
+{
+ writel(PCIE_CONF_BUS(bus->number) |
+ PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+ PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+ PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+ base + PCIE_CONF_ADDR_OFF);
+
+ *val = readl(base + PCIE_CONF_DATA_OFF);
+
+ if (bus->number != orion_pcie_get_local_bus_nr(base) ||
+ PCI_FUNC(devfn) != 0)
+ *val = readl(base + PCIE_HEADER_LOG_4_OFF);
+
+ if (size == 1)
+ *val = (*val >> (8 * (where & 3))) & 0xff;
+ else if (size == 2)
+ *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val)
+{
+ *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
+ PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+ PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+ PCIE_CONF_REG(where)));
+
+ if (size == 1)
+ *val = (*val >> (8 * (where & 3))) & 0xff;
+ else if (size == 2)
+ *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 val)
+{
+ int ret = PCIBIOS_SUCCESSFUL;
+
+ writel(PCIE_CONF_BUS(bus->number) |
+ PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+ PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+ PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+ base + PCIE_CONF_ADDR_OFF);
+
+ if (size == 4) {
+ writel(val, base + PCIE_CONF_DATA_OFF);
+ } else if (size == 2) {
+ writew(val, base + PCIE_CONF_DATA_OFF + (where & 3));
+ } else if (size == 1) {
+ writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3));
+ } else {
+ ret = PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+
+ return ret;
+}
--- /dev/null
+/*
+ * arch/arm/plat-orion/time.c
+ *
+ * Marvell Orion SoC timer handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Timer 0 is used as free-running clocksource, while timer 1 is
+ * used as clock_event_device.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/mach/time.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
+
+
+/*
+ * Timer block registers.
+ */
+#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000)
+#define TIMER0_EN 0x0001
+#define TIMER0_RELOAD_EN 0x0002
+#define TIMER1_EN 0x0004
+#define TIMER1_RELOAD_EN 0x0008
+#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010)
+#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014)
+#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018)
+#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c)
+
+
+/*
+ * Clocksource handling.
+ */
+static cycle_t orion_clksrc_read(void)
+{
+ return 0xffffffff - readl(TIMER0_VAL);
+}
+
+static struct clocksource orion_clksrc = {
+ .name = "orion_clocksource",
+ .shift = 20,
+ .rating = 300,
+ .read = orion_clksrc_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+
+
+/*
+ * Clockevent handling.
+ */
+static int
+orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
+{
+ unsigned long flags;
+ u32 u;
+
+ if (delta == 0)
+ return -ETIME;
+
+ local_irq_save(flags);
+
+ /*
+ * Clear and enable clockevent timer interrupt.
+ */
+ writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+
+ u = readl(BRIDGE_MASK);
+ u |= BRIDGE_INT_TIMER1;
+ writel(u, BRIDGE_MASK);
+
+ /*
+ * Setup new clockevent timer value.
+ */
+ writel(delta, TIMER1_VAL);
+
+ /*
+ * Enable the timer.
+ */
+ u = readl(TIMER_CTRL);
+ u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
+ writel(u, TIMER_CTRL);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static void
+orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
+{
+ unsigned long flags;
+ u32 u;
+
+ local_irq_save(flags);
+ if (mode == CLOCK_EVT_MODE_PERIODIC) {
+ /*
+ * Setup timer to fire at 1/HZ intervals.
+ */
+ writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
+ writel(ticks_per_jiffy - 1, TIMER1_VAL);
+
+ /*
+ * Enable timer interrupt.
+ */
+ u = readl(BRIDGE_MASK);
+ writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
+
+ /*
+ * Enable timer.
+ */
+ u = readl(TIMER_CTRL);
+ writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
+ } else {
+ /*
+ * Disable timer.
+ */
+ u = readl(TIMER_CTRL);
+ writel(u & ~TIMER1_EN, TIMER_CTRL);
+
+ /*
+ * Disable timer interrupt.
+ */
+ u = readl(BRIDGE_MASK);
+ writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
+
+ /*
+ * ACK pending timer interrupt.
+ */
+ writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+
+ }
+ local_irq_restore(flags);
+}
+
+static struct clock_event_device orion_clkevt = {
+ .name = "orion_tick",
+ .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+ .shift = 32,
+ .rating = 300,
+ .cpumask = CPU_MASK_CPU0,
+ .set_next_event = orion_clkevt_next_event,
+ .set_mode = orion_clkevt_mode,
+};
+
+static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
+{
+ /*
+ * ACK timer interrupt and call event handler.
+ */
+ writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+ orion_clkevt.event_handler(&orion_clkevt);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction orion_timer_irq = {
+ .name = "orion_tick",
+ .flags = IRQF_DISABLED | IRQF_TIMER,
+ .handler = orion_timer_interrupt
+};
+
+void __init orion_time_init(unsigned int irq, unsigned int tclk)
+{
+ u32 u;
+
+ ticks_per_jiffy = (tclk + HZ/2) / HZ;
+
+
+ /*
+ * Setup free-running clocksource timer (interrupts
+ * disabled.)
+ */
+ writel(0xffffffff, TIMER0_VAL);
+ writel(0xffffffff, TIMER0_RELOAD);
+ u = readl(BRIDGE_MASK);
+ writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
+ u = readl(TIMER_CTRL);
+ writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
+ orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
+ clocksource_register(&orion_clksrc);
+
+
+ /*
+ * Setup clockevent timer (interrupt-driven.)
+ */
+ setup_irq(irq, &orion_timer_irq);
+ orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
+ orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
+ orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
+ clockevents_register_device(&orion_clkevt);
+}
return 0;
}
+static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
+{
+ unsigned long div;
+
+ if ((rate == 0) || !clk->parent)
+ return 0;
+
+ div = clk_get_rate(clk->parent) / rate;
+ if (div < 2)
+ div = 2;
+ else if (div > 16)
+ div = 16;
+
+ return div;
+}
+
+static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
+ unsigned long rate)
+{
+ unsigned long div = s3c24xx_calc_div(clk, rate);
+
+ if (div == 0)
+ return 0;
+
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
+
+ if (div == 0)
+ return -EINVAL;
+
+ if (clk == &s3c24xx_dclk0) {
+ mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
+ S3C2410_DCLKCON_DCLK0_CMP_MASK;
+ data = S3C2410_DCLKCON_DCLK0_DIV(div) |
+ S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
+ } else if (clk == &s3c24xx_dclk1) {
+ mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
+ S3C2410_DCLKCON_DCLK1_CMP_MASK;
+ data = S3C2410_DCLKCON_DCLK1_DIV(div) |
+ S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
+ } else
+ return -EINVAL;
+
+ clk->rate = clk_get_rate(clk->parent) / div;
+ __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
+ S3C24XX_DCLKCON);
+ return clk->rate;
+}
static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
{
.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
.enable = s3c24xx_dclk_enable,
.set_parent = s3c24xx_dclk_setparent,
+ .set_rate = s3c24xx_set_dclk_rate,
+ .round_rate = s3c24xx_round_dclk_rate,
};
struct clk s3c24xx_dclk1 = {
.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
.enable = s3c24xx_dclk_enable,
.set_parent = s3c24xx_dclk_setparent,
+ .set_rate = s3c24xx_set_dclk_rate,
+ .round_rate = s3c24xx_round_dclk_rate,
};
struct clk s3c24xx_clkout0 = {
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
+#include <linux/delay.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/delay.h>
+#include <asm/cacheflush.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <asm/arch/system-reset.h>
+
#include <asm/arch/regs-gpio.h>
#include <asm/plat-s3c/regs-serial.h>
#endif
}
+/* Hook for arm_pm_restart to ensure we execute the reset code
+ * with the caches enabled. It seems at least the S3C2440 has a problem
+ * resetting if there is bus activity interrupted by the reset.
+ */
+static void s3c24xx_pm_restart(char mode)
+{
+ if (mode != 's') {
+ unsigned long flags;
+
+ local_irq_save(flags);
+ __cpuc_flush_kern_all();
+ __cpuc_flush_user_all();
+
+ arch_reset(mode);
+ local_irq_restore(flags);
+ }
+
+ /* fallback, or unhandled */
+ arm_machine_restart(mode);
+}
+
void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
{
unsigned long idcode = 0x0;
panic("Unsupported S3C24XX CPU");
}
+ arm_pm_restart = s3c24xx_pm_restart;
+
(cpu->map_io)(mach_desc, size);
}
#
# http://www.arm.linux.org.uk/developer/machines/?action=new
#
-# Last update: Sat Jan 26 14:45:34 2008
+# Last update: Sat Apr 19 11:23:38 2008
#
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
#
se4000 ARCH_SE4000 SE4000 364
quadriceps ARCH_QUADRICEPS QUADRICEPS 365
bronco ARCH_BRONCO BRONCO 366
-esl_wireless_tab ARCH_ESL_WIRELESS_TABLETESL_WIRELESS_TABLET 367
+esl_wireless_tab ARCH_ESL_WIRELESS_TAB ESL_WIRELESS_TAB 367
esl_sofcomp ARCH_ESL_SOFCOMP ESL_SOFCOMP 368
s5c7375 ARCH_S5C7375 S5C7375 369
spearhead ARCH_SPEARHEAD SPEARHEAD 370
pantera ARCH_PANTERA PANTERA 371
prayoglite ARCH_PRAYOGLITE PRAYOGLITE 372
-gumstix ARCH_GUMSTIK GUMSTIK 373
+gumstix ARCH_GUMSTIX GUMSTIX 373
rcube ARCH_RCUBE RCUBE 374
rea_olv ARCH_REA_OLV REA_OLV 375
pxa_iphone ARCH_PXA_IPHONE PXA_IPHONE 376
htctitan MACH_HTCTITAN HTCTITAN 1463
qranium MACH_QRANIUM QRANIUM 1464
adx_wsc2 MACH_ADX_WSC2 ADX_WSC2 1465
-adx_medinet MACH_ADX_MEDINET ADX_MEDINET 1466
+adx_medcom MACH_ADX_MEDINET ADX_MEDINET 1466
bboard MACH_BBOARD BBOARD 1467
cambria MACH_CAMBRIA CAMBRIA 1468
mt7xxx MACH_MT7XXX MT7XXX 1469
mt7108 MACH_MT7108 MT7108 1613
smtr2440 MACH_SMTR2440 SMTR2440 1614
manao MACH_MANAO MANAO 1615
+cm_x300 MACH_CM_X300 CM_X300 1616
+gulfstream_kp MACH_GULFSTREAM_KP GULFSTREAM_KP 1617
+lanreadyfn522 MACH_LANREADYFN522 LANREADYFN522 1618
+arma37 MACH_ARMA37 ARMA37 1619
+mendel MACH_MENDEL MENDEL 1620
+pelco_iliad MACH_PELCO_ILIAD PELCO_ILIAD 1621
+unit2p MACH_UNIT2P UNIT2P 1622
+inc20otter MACH_INC20OTTER INC20OTTER 1623
+at91sam9g20ek MACH_AT91SAM9G20EK AT91SAM9G20EK 1624
+sc_ge2 MACH_STORCENTER STORCENTER 1625
+smdk6410 MACH_SMDK6410 SMDK6410 1626
+u300 MACH_U300 U300 1627
+u500 MACH_U500 U500 1628
+ds9260 MACH_DS9260 DS9260 1629
+riverrock MACH_RIVERROCK RIVERROCK 1630
+scibath MACH_SCIBATH SCIBATH 1631
+at91sam7se MACH_AT91SAM7SE512EK AT91SAM7SE512EK 1632
+wrt350n_v2 MACH_WRT350N_V2 WRT350N_V2 1633
+multimedia MACH_MULTIMEDIA MULTIMEDIA 1634
+marvin MACH_MARVIN MARVIN 1635
+x500 MACH_X500 X500 1636
+awlug4lcu MACH_AWLUG4LCU AWLUG4LCU 1637
+palermoc MACH_PALERMOC PALERMOC 1638
+omap_ldp MACH_OMAP_LDP OMAP_LDP 1639
+ip500 MACH_IP500 IP500 1640
+mx35ads MACH_MACH_MX35ADS MACH_MX35ADS 1641
+ase2 MACH_ASE2 ASE2 1642
+mx35evb MACH_MX35EVB MX35EVB 1643
+aml_m8050 MACH_AML_M8050 AML_M8050 1644
+mx35_3ds MACH_MX35_3DS MX35_3DS 1645
+mars MACH_MARS MARS 1646
+ntosd_644xa MACH_NTOSD_644XA NTOSD_644XA 1647
+badger MACH_BADGER BADGER 1648
+trizeps4wl MACH_TRIZEPS4WL TRIZEPS4WL 1649
+trizeps5 MACH_TRIZEPS5 TRIZEPS5 1650
+marlin MACH_MARLIN MARLIN 1651
+ts7800 MACH_TS7800 TS7800 1652
+hpipaq214 MACH_HPIPAQ214 HPIPAQ214 1653
+at572d940dcm MACH_AT572D940DCM AT572D940DCM 1654
+ne1board MACH_NE1BOARD NE1BOARD 1655
+zante MACH_ZANTE ZANTE 1656
+sffsdr MACH_SFFSDR SFFSDR 1657
+tw2662 MACH_TW2662 TW2662 1658
+vf10xx MACH_VF10XX VF10XX 1659
+zoran43xx MACH_ZORAN43XX ZORAN43XX 1660
+sonix926 MACH_SONIX926 SONIX926 1661
+celestialsemi MACH_CELESTIALSEMI CELESTIALSEMI 1662
+cc9m2443 MACH_CC9M2443 CC9M2443 1663
+tw5334 MACH_TW5334 TW5334 1664
+omap_htcartemis MACH_HTCARTEMIS HTCARTEMIS 1665
+nal_hlite MACH_NAL_HLITE NAL_HLITE 1666
+htcvogue MACH_HTCVOGUE HTCVOGUE 1667
+smartweb MACH_SMARTWEB SMARTWEB 1668
+mv86xx MACH_MV86XX MV86XX 1669
+mv87xx MACH_MV87XX MV87XX 1670
+songyoungho MACH_SONGYOUNGHO SONGYOUNGHO 1671
+younghotema MACH_YOUNGHOTEMA YOUNGHOTEMA 1672
+pcm037 MACH_PCM037 PCM037 1673
+mmvp MACH_MMVP MMVP 1674
+mmap MACH_MMAP MMAP 1675
+ptid2410 MACH_PTID2410 PTID2410 1676
+james_926 MACH_JAMES_926 JAMES_926 1677
+fm6000 MACH_FM6000 FM6000 1678
+db88f6281_bp MACH_DB88F6281_BP DB88F6281_BP 1680
+rd88f6192_nas MACH_RD88F6192_NAS RD88F6192_NAS 1681
+rd88f6281 MACH_RD88F6281 RD88F6281 1682
+db78x00_bp MACH_DB78X00_BP DB78X00_BP 1683
+smdk2416 MACH_SMDK2416 SMDK2416 1685
+oce_spider_si MACH_OCE_SPIDER_SI OCE_SPIDER_SI 1686
+oce_spider_sk MACH_OCE_SPIDER_SK OCE_SPIDER_SK 1687
+rovern6 MACH_ROVERN6 ROVERN6 1688
+pelco_evolution MACH_PELCO_EVOLUTION PELCO_EVOLUTION 1689
+wbd111 MACH_WBD111 WBD111 1690
+elaracpe MACH_ELARACPE ELARACPE 1691
+mabv3 MACH_MABV3 MABV3 1692
+mv2120 MACH_MV2120 MV2120 1693
+csb737 MACH_CSB737 CSB737 1695
+mx51_3ds MACH_MX51_3DS MX51_3DS 1696
+g900 MACH_G900 G900 1697
+apf27 MACH_APF27 APF27 1698
+ggus2000 MACH_GGUS2000 GGUS2000 1699
+omap_2430_mimic MACH_OMAP_2430_MIMIC OMAP_2430_MIMIC 1700
+imx27lite MACH_IMX27LITE IMX27LITE 1701
+almex MACH_ALMEX ALMEX 1702
+control MACH_CONTROL CONTROL 1703
+mba2410 MACH_MBA2410 MBA2410 1704
+volcano MACH_VOLCANO VOLCANO 1705
+zenith MACH_ZENITH ZENITH 1706
+muchip MACH_MUCHIP MUCHIP 1707
+magellan MACH_MAGELLAN MAGELLAN 1708
+usb_a9260 MACH_USB_A9260 USB_A9260 1709
+usb_a9263 MACH_USB_A9263 USB_A9263 1710
+qil_a9260 MACH_QIL_A9260 QIL_A9260 1711
+cme9210 MACH_CME9210 CME9210 1712
+hczh4 MACH_HCZH4 HCZH4 1713
+spearbasic MACH_SPEARBASIC SPEARBASIC 1714
+dep2440 MACH_DEP2440 DEP2440 1715
+hdl_gxr MACH_HDL_GXR HDL_GXR 1716
+hdl_gt MACH_HDL_GT HDL_GT 1717
+hdl_4g MACH_HDL_4G HDL_4G 1718
+s3c6000 MACH_S3C6000 S3C6000 1719
+mmsp2_mdk MACH_MMSP2_MDK MMSP2_MDK 1720
+mpx220 MACH_MPX220 MPX220 1721
+kzm_arm11_01 MACH_KZM_ARM11_01 KZM_ARM11_01 1722
+htc_polaris MACH_HTC_POLARIS HTC_POLARIS 1723
+htc_kaiser MACH_HTC_KAISER HTC_KAISER 1724
+lg_ks20 MACH_LG_KS20 LG_KS20 1725
+hhgps MACH_HHGPS HHGPS 1726
+nokia_n810_wimax MACH_NOKIA_N810_WIMAX NOKIA_N810_WIMAX 1727
config GENERIC_TIME
def_bool y
+config GENERIC_CLOCKEVENTS
+ def_bool y
+
config RWSEM_XCHGADD_ALGORITHM
def_bool n
menu "System Type and features"
+source "kernel/time/Kconfig"
+
config SUBARCH_AVR32B
bool
config MMU
.section .irq.text,"ax",@progbits
-.global cpu_idle_sleep
-cpu_idle_sleep:
- mask_interrupts
- get_thread_info r8
- ld.w r9, r8[TI_flags]
- bld r9, TIF_NEED_RESCHED
- brcs cpu_idle_enable_int_and_exit
- sbr r9, TIF_CPU_GOING_TO_SLEEP
- st.w r8[TI_flags], r9
- unmask_interrupts
- sleep 0
-cpu_idle_skip_sleep:
- mask_interrupts
- ld.w r9, r8[TI_flags]
- cbr r9, TIF_CPU_GOING_TO_SLEEP
- st.w r8[TI_flags], r9
-cpu_idle_enable_int_and_exit:
- unmask_interrupts
- retal r12
-
.global irq_level0
.global irq_level1
.global irq_level2
#include <asm/sysreg.h>
#include <asm/ocd.h>
+#include <asm/arch/pm.h>
+
void (*pm_power_off)(void) = NULL;
EXPORT_SYMBOL(pm_power_off);
-extern void cpu_idle_sleep(void);
-
/*
* This file handles the architecture-dependent parts of process handling..
*/
void machine_power_off(void)
{
+ if (pm_power_off)
+ pm_power_off();
}
void machine_restart(char *cmd)
/*
* Copyright (C) 2004-2007 Atmel Corporation
*
- * Based on MIPS implementation arch/mips/kernel/time.c
- * Copyright 2001 MontaVista Software Inc.
- *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-
#include <linux/clk.h>
-#include <linux/clocksource.h>
+#include <linux/clockchips.h>
#include <linux/time.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/sections.h>
-/* how many counter cycles in a jiffy? */
-static u32 cycles_per_jiffy;
+#include <asm/arch/pm.h>
-/* the count value for the next timer interrupt */
-static u32 expirelo;
-cycle_t __weak read_cycle_count(void)
+static cycle_t read_cycle_count(void)
{
return (cycle_t)sysreg_read(COUNT);
}
-struct clocksource __weak clocksource_avr32 = {
- .name = "avr32",
- .rating = 350,
+/*
+ * The architectural cycle count registers are a fine clocksource unless
+ * the system idle loop use sleep states like "idle": the CPU cycles
+ * measured by COUNT (and COMPARE) don't happen during sleep states.
+ * Their duration also changes if cpufreq changes the CPU clock rate.
+ * So we rate the clocksource using COUNT as very low quality.
+ */
+static struct clocksource counter = {
+ .name = "avr32_counter",
+ .rating = 50,
.read = read_cycle_count,
.mask = CLOCKSOURCE_MASK(32),
.shift = 16,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
-irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
-
-struct irqaction timer_irqaction = {
- .handler = timer_interrupt,
- .flags = IRQF_DISABLED,
- .name = "timer",
-};
-
-/*
- * By default we provide the null RTC ops
- */
-static unsigned long null_rtc_get_time(void)
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
- return mktime(2007, 1, 1, 0, 0, 0);
-}
-
-static int null_rtc_set_time(unsigned long sec)
-{
- return 0;
-}
+ struct clock_event_device *evdev = dev_id;
-static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
-static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
-
-static void avr32_timer_ack(void)
-{
- u32 count;
-
- /* Ack this timer interrupt and set the next one */
- expirelo += cycles_per_jiffy;
- /* setting COMPARE to 0 stops the COUNT-COMPARE */
- if (expirelo == 0) {
- sysreg_write(COMPARE, expirelo + 1);
- } else {
- sysreg_write(COMPARE, expirelo);
- }
+ /*
+ * Disable the interrupt until the clockevent subsystem
+ * reprograms it.
+ */
+ sysreg_write(COMPARE, 0);
- /* Check to see if we have missed any timer interrupts */
- count = sysreg_read(COUNT);
- if ((count - expirelo) < 0x7fffffff) {
- expirelo = count + cycles_per_jiffy;
- sysreg_write(COMPARE, expirelo);
- }
+ evdev->event_handler(evdev);
+ return IRQ_HANDLED;
}
-int __weak avr32_hpt_init(void)
-{
- int ret;
- unsigned long mult, shift, count_hz;
-
- count_hz = clk_get_rate(boot_cpu_data.clk);
- shift = clocksource_avr32.shift;
- mult = clocksource_hz2mult(count_hz, shift);
- clocksource_avr32.mult = mult;
-
- {
- u64 tmp;
-
- tmp = TICK_NSEC;
- tmp <<= shift;
- tmp += mult / 2;
- do_div(tmp, mult);
-
- cycles_per_jiffy = tmp;
- }
+static struct irqaction timer_irqaction = {
+ .handler = timer_interrupt,
+ .flags = IRQF_TIMER | IRQF_DISABLED,
+ .name = "avr32_comparator",
+};
- ret = setup_irq(0, &timer_irqaction);
- if (ret) {
- pr_debug("timer: could not request IRQ 0: %d\n", ret);
- return -ENODEV;
- }
+static int comparator_next_event(unsigned long delta,
+ struct clock_event_device *evdev)
+{
+ unsigned long flags;
- printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
- "%lu.%03lu MHz\n",
- ((count_hz + 500) / 1000) / 1000,
- ((count_hz + 500) / 1000) % 1000);
+ raw_local_irq_save(flags);
- return 0;
-}
+ /* The time to read COUNT then update COMPARE must be less
+ * than the min_delta_ns value for this clockevent source.
+ */
+ sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
-/*
- * Taken from MIPS c0_hpt_timer_init().
- *
- * The reason COUNT is written twice is probably to make sure we don't get any
- * timer interrupts while we are messing with the counter.
- */
-int __weak avr32_hpt_start(void)
-{
- u32 count = sysreg_read(COUNT);
- expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
- sysreg_write(COUNT, expirelo - cycles_per_jiffy);
- sysreg_write(COMPARE, expirelo);
- sysreg_write(COUNT, count);
+ raw_local_irq_restore(flags);
return 0;
}
-/*
- * local_timer_interrupt() does profiling and process accounting on a
- * per-CPU basis.
- *
- * In UP mode, it is invoked from the (global) timer_interrupt.
- */
-void local_timer_interrupt(int irq, void *dev_id)
+static void comparator_mode(enum clock_event_mode mode,
+ struct clock_event_device *evdev)
{
- if (current->pid)
- profile_tick(CPU_PROFILING);
- update_process_times(user_mode(get_irq_regs()));
+ switch (mode) {
+ case CLOCK_EVT_MODE_ONESHOT:
+ pr_debug("%s: start\n", evdev->name);
+ /* FALLTHROUGH */
+ case CLOCK_EVT_MODE_RESUME:
+ cpu_disable_idle_sleep();
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ sysreg_write(COMPARE, 0);
+ pr_debug("%s: stop\n", evdev->name);
+ cpu_enable_idle_sleep();
+ break;
+ default:
+ BUG();
+ }
}
-irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
-{
- /* ack timer interrupt and try to set next interrupt */
- avr32_timer_ack();
-
- /*
- * Call the generic timer interrupt handler
- */
- write_seqlock(&xtime_lock);
- do_timer(1);
- write_sequnlock(&xtime_lock);
-
- /*
- * In UP mode, we call local_timer_interrupt() to do profiling
- * and process accounting.
- *
- * SMP is not supported yet.
- */
- local_timer_interrupt(irq, dev_id);
-
- return IRQ_HANDLED;
-}
+static struct clock_event_device comparator = {
+ .name = "avr32_comparator",
+ .features = CLOCK_EVT_FEAT_ONESHOT,
+ .shift = 16,
+ .rating = 50,
+ .cpumask = CPU_MASK_CPU0,
+ .set_next_event = comparator_next_event,
+ .set_mode = comparator_mode,
+};
void __init time_init(void)
{
+ unsigned long counter_hz;
int ret;
- /*
- * Make sure we don't get any COMPARE interrupts before we can
- * handle them.
- */
- sysreg_write(COMPARE, 0);
-
- xtime.tv_sec = rtc_get_time();
+ xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
xtime.tv_nsec = 0;
set_normalized_timespec(&wall_to_monotonic,
-xtime.tv_sec, -xtime.tv_nsec);
- ret = avr32_hpt_init();
- if (ret) {
- pr_debug("timer: failed setup: %d\n", ret);
- return;
- }
+ /* figure rate for counter */
+ counter_hz = clk_get_rate(boot_cpu_data.clk);
+ counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
- ret = clocksource_register(&clocksource_avr32);
+ ret = clocksource_register(&counter);
if (ret)
pr_debug("timer: could not register clocksource: %d\n", ret);
- ret = avr32_hpt_start();
- if (ret) {
- pr_debug("timer: failed starting: %d\n", ret);
- return;
- }
-}
+ /* setup COMPARE clockevent */
+ comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
+ comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
+ comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
-static struct sysdev_class timer_class = {
- .name = "timer",
-};
+ sysreg_write(COMPARE, 0);
+ timer_irqaction.dev_id = &comparator;
-static struct sys_device timer_device = {
- .id = 0,
- .cls = &timer_class,
-};
+ ret = setup_irq(0, &timer_irqaction);
+ if (ret)
+ pr_debug("timer: could not request IRQ 0: %d\n", ret);
+ else {
+ clockevents_register_device(&comparator);
-static int __init init_timer_sysfs(void)
-{
- int err = sysdev_class_register(&timer_class);
- if (!err)
- err = sysdev_register(&timer_device);
- return err;
+ pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
+ ((counter_hz + 500) / 1000) / 1000,
+ ((counter_hz + 500) / 1000) % 1000);
+ }
}
-
-device_initcall(init_timer_sysfs);
obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
-obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o
-obj-$(CONFIG_CPU_AT32AP700X) += time-tc.o
+obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/spi/spi.h>
+#include <linux/usb/atmel_usba_udc.h>
#include <asm/io.h>
#include <asm/irq.h>
[2] = 12000000,
};
+static struct clk osc0;
+static struct clk osc1;
+
static unsigned long osc_get_rate(struct clk *clk)
{
return at32ap7000_osc_rates[clk->index];
{
unsigned long div, mul, rate;
- if (!(control & PM_BIT(PLLEN)))
- return 0;
-
div = PM_BFEXT(PLLDIV, control) + 1;
mul = PM_BFEXT(PLLMUL, control) + 1;
return rate;
}
+static long pll_set_rate(struct clk *clk, unsigned long rate,
+ u32 *pll_ctrl)
+{
+ unsigned long mul;
+ unsigned long mul_best_fit = 0;
+ unsigned long div;
+ unsigned long div_min;
+ unsigned long div_max;
+ unsigned long div_best_fit = 0;
+ unsigned long base;
+ unsigned long pll_in;
+ unsigned long actual = 0;
+ unsigned long rate_error;
+ unsigned long rate_error_prev = ~0UL;
+ u32 ctrl;
+
+ /* Rate must be between 80 MHz and 200 Mhz. */
+ if (rate < 80000000UL || rate > 200000000UL)
+ return -EINVAL;
+
+ ctrl = PM_BF(PLLOPT, 4);
+ base = clk->parent->get_rate(clk->parent);
+
+ /* PLL input frequency must be between 6 MHz and 32 MHz. */
+ div_min = DIV_ROUND_UP(base, 32000000UL);
+ div_max = base / 6000000UL;
+
+ if (div_max < div_min)
+ return -EINVAL;
+
+ for (div = div_min; div <= div_max; div++) {
+ pll_in = (base + div / 2) / div;
+ mul = (rate + pll_in / 2) / pll_in;
+
+ if (mul == 0)
+ continue;
+
+ actual = pll_in * mul;
+ rate_error = abs(actual - rate);
+
+ if (rate_error < rate_error_prev) {
+ mul_best_fit = mul;
+ div_best_fit = div;
+ rate_error_prev = rate_error;
+ }
+
+ if (rate_error == 0)
+ break;
+ }
+
+ if (div_best_fit == 0)
+ return -EINVAL;
+
+ ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
+ ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
+ ctrl |= PM_BF(PLLCOUNT, 16);
+
+ if (clk->parent == &osc1)
+ ctrl |= PM_BIT(PLLOSC);
+
+ *pll_ctrl = ctrl;
+
+ return actual;
+}
+
static unsigned long pll0_get_rate(struct clk *clk)
{
u32 control;
return pll_get_rate(clk, control);
}
+static void pll1_mode(struct clk *clk, int enabled)
+{
+ unsigned long timeout;
+ u32 status;
+ u32 ctrl;
+
+ ctrl = pm_readl(PLL1);
+
+ if (enabled) {
+ if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
+ pr_debug("clk %s: failed to enable, rate not set\n",
+ clk->name);
+ return;
+ }
+
+ ctrl |= PM_BIT(PLLEN);
+ pm_writel(PLL1, ctrl);
+
+ /* Wait for PLL lock. */
+ for (timeout = 10000; timeout; timeout--) {
+ status = pm_readl(ISR);
+ if (status & PM_BIT(LOCK1))
+ break;
+ udelay(10);
+ }
+
+ if (!(status & PM_BIT(LOCK1)))
+ printk(KERN_ERR "clk %s: timeout waiting for lock\n",
+ clk->name);
+ } else {
+ ctrl &= ~PM_BIT(PLLEN);
+ pm_writel(PLL1, ctrl);
+ }
+}
+
static unsigned long pll1_get_rate(struct clk *clk)
{
u32 control;
return pll_get_rate(clk, control);
}
+static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
+{
+ u32 ctrl = 0;
+ unsigned long actual_rate;
+
+ actual_rate = pll_set_rate(clk, rate, &ctrl);
+
+ if (apply) {
+ if (actual_rate != rate)
+ return -EINVAL;
+ if (clk->users > 0)
+ return -EBUSY;
+ pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
+ clk->name, rate, actual_rate);
+ pm_writel(PLL1, ctrl);
+ }
+
+ return actual_rate;
+}
+
+static int pll1_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 ctrl;
+
+ if (clk->users > 0)
+ return -EBUSY;
+
+ ctrl = pm_readl(PLL1);
+ WARN_ON(ctrl & PM_BIT(PLLEN));
+
+ if (parent == &osc0)
+ ctrl &= ~PM_BIT(PLLOSC);
+ else if (parent == &osc1)
+ ctrl |= PM_BIT(PLLOSC);
+ else
+ return -EINVAL;
+
+ pm_writel(PLL1, ctrl);
+ clk->parent = parent;
+
+ return 0;
+}
+
/*
* The AT32AP7000 has five primary clock sources: One 32kHz
* oscillator, two crystal oscillators and two PLLs.
};
static struct clk pll1 = {
.name = "pll1",
+ .mode = pll1_mode,
.get_rate = pll1_get_rate,
+ .set_rate = pll1_set_rate,
+ .set_parent = pll1_set_parent,
.parent = &osc0,
};
}
/* --------------------------------------------------------------------
- * System Timer/Counter (TC)
+ * Timer/Counter (TC)
* -------------------------------------------------------------------- */
-static struct resource at32_systc0_resource[] = {
+
+static struct resource at32_tcb0_resource[] = {
PBMEM(0xfff00c00),
IRQ(22),
};
-struct platform_device at32_systc0_device = {
- .name = "systc",
+static struct platform_device at32_tcb0_device = {
+ .name = "atmel_tcb",
.id = 0,
- .resource = at32_systc0_resource,
- .num_resources = ARRAY_SIZE(at32_systc0_resource),
+ .resource = at32_tcb0_resource,
+ .num_resources = ARRAY_SIZE(at32_tcb0_resource),
};
-DEV_CLK(pclk, at32_systc0, pbb, 3);
+DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
+
+static struct resource at32_tcb1_resource[] = {
+ PBMEM(0xfff01000),
+ IRQ(23),
+};
+static struct platform_device at32_tcb1_device = {
+ .name = "atmel_tcb",
+ .id = 1,
+ .resource = at32_tcb1_resource,
+ .num_resources = ARRAY_SIZE(at32_tcb1_resource),
+};
+DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
/* --------------------------------------------------------------------
* PIO
platform_device_register(&pdc_device);
platform_device_register(&dmaca0_device);
- platform_device_register(&at32_systc0_device);
+ platform_device_register(&at32_tcb0_device);
+ platform_device_register(&at32_tcb1_device);
platform_device_register(&pio0_device);
platform_device_register(&pio1_device);
.index = 2,
};
-struct platform_device *__init at32_add_device_twi(unsigned int id)
+struct platform_device *__init at32_add_device_twi(unsigned int id,
+ struct i2c_board_info *b,
+ unsigned int n)
{
struct platform_device *pdev;
atmel_twi0_pclk.dev = &pdev->dev;
+ if (b)
+ i2c_register_board_info(id, b, n);
+
platform_device_add(pdev);
return pdev;
.index = 6,
};
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
+ [idx] = { \
+ .name = nam, \
+ .index = idx, \
+ .fifo_size = maxpkt, \
+ .nr_banks = maxbk, \
+ .can_dma = dma, \
+ .can_isoc = isoc, \
+ }
+
+static struct usba_ep_data at32_usba_ep[] __initdata = {
+ EP("ep0", 0, 64, 1, 0, 0),
+ EP("ep1", 1, 512, 2, 1, 1),
+ EP("ep2", 2, 512, 2, 1, 1),
+ EP("ep3-int", 3, 64, 3, 1, 0),
+ EP("ep4-int", 4, 64, 3, 1, 0),
+ EP("ep5", 5, 1024, 3, 1, 1),
+ EP("ep6", 6, 1024, 3, 1, 1),
+};
+
+#undef EP
+
struct platform_device *__init
at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
{
+ /*
+ * pdata doesn't have room for any endpoints, so we need to
+ * append room for the ones we need right after it.
+ */
+ struct {
+ struct usba_platform_data pdata;
+ struct usba_ep_data ep[7];
+ } usba_data;
struct platform_device *pdev;
if (id != 0)
ARRAY_SIZE(usba0_resource)))
goto out_free_pdev;
- if (data) {
- if (platform_device_add_data(pdev, data, sizeof(*data)))
- goto out_free_pdev;
+ if (data)
+ usba_data.pdata.vbus_pin = data->vbus_pin;
+ else
+ usba_data.pdata.vbus_pin = -EINVAL;
+
+ data = &usba_data.pdata;
+ data->num_ep = ARRAY_SIZE(at32_usba_ep);
+ memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
- if (data->vbus_pin != GPIO_PIN_NONE)
- at32_select_gpio(data->vbus_pin, 0);
- }
+ if (platform_device_add_data(pdev, data, sizeof(usba_data)))
+ goto out_free_pdev;
+
+ if (data->vbus_pin >= 0)
+ at32_select_gpio(data->vbus_pin, 0);
usba0_pclk.dev = &pdev->dev;
usba0_hclk.dev = &pdev->dev;
&pio2_mck,
&pio3_mck,
&pio4_mck,
- &at32_systc0_pclk,
+ &at32_tcb0_t0_clk,
+ &at32_tcb1_t0_clk,
&atmel_usart0_usart,
&atmel_usart1_usart,
&atmel_usart2_usart,
#include <linux/irq.h>
#include <linux/platform_device.h>
-#include <asm/intc.h>
#include <asm/io.h>
#include "intc.h"
--- /dev/null
+/*
+ * Low-level Power Management code.
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/arch/pm.h>
+
+ .section .bss, "wa", @nobits
+ .global disable_idle_sleep
+ .type disable_idle_sleep, @object
+disable_idle_sleep:
+ .int 4
+ .size disable_idle_sleep, . - disable_idle_sleep
+
+ /* Keep this close to the irq handlers */
+ .section .irq.text, "ax", @progbits
+
+ /*
+ * void cpu_enter_idle(void)
+ *
+ * Put the CPU into "idle" mode, in which it will consume
+ * significantly less power.
+ *
+ * If an interrupt comes along in the window between
+ * unmask_interrupts and the sleep instruction below, the
+ * interrupt code will adjust the return address so that we
+ * never execute the sleep instruction. This is required
+ * because the AP7000 doesn't unmask interrupts when entering
+ * sleep modes; later CPUs may not need this workaround.
+ */
+ .global cpu_enter_idle
+ .type cpu_enter_idle, @function
+cpu_enter_idle:
+ mask_interrupts
+ get_thread_info r8
+ ld.w r9, r8[TI_flags]
+ bld r9, TIF_NEED_RESCHED
+ brcs .Lret_from_sleep
+ sbr r9, TIF_CPU_GOING_TO_SLEEP
+ st.w r8[TI_flags], r9
+ unmask_interrupts
+ sleep CPU_SLEEP_IDLE
+ .size cpu_idle_sleep, . - cpu_idle_sleep
+
+ /*
+ * Common return path for PM functions that don't run from
+ * SRAM.
+ */
+ .global cpu_idle_skip_sleep
+ .type cpu_idle_skip_sleep, @function
+cpu_idle_skip_sleep:
+ mask_interrupts
+ ld.w r9, r8[TI_flags]
+ cbr r9, TIF_CPU_GOING_TO_SLEEP
+ st.w r8[TI_flags], r9
+.Lret_from_sleep:
+ unmask_interrupts
+ retal r12
+ .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
+++ /dev/null
-/*
- * Copyright (C) 2004-2007 Atmel Corporation
- *
- * Based on MIPS implementation arch/mips/kernel/time.c
- * Copyright 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/clocksource.h>
-#include <linux/time.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/kernel_stat.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/profile.h>
-#include <linux/sysdev.h>
-#include <linux/err.h>
-
-#include <asm/div64.h>
-#include <asm/sysreg.h>
-#include <asm/io.h>
-#include <asm/sections.h>
-
-#include <asm/arch/time.h>
-
-/* how many counter cycles in a jiffy? */
-static u32 cycles_per_jiffy;
-
-/* the count value for the next timer interrupt */
-static u32 expirelo;
-
-/* the I/O registers of the TC module */
-static void __iomem *ioregs;
-
-cycle_t read_cycle_count(void)
-{
- return (cycle_t)timer_read(ioregs, 0, CV);
-}
-
-struct clocksource clocksource_avr32 = {
- .name = "avr32",
- .rating = 342,
- .read = read_cycle_count,
- .mask = CLOCKSOURCE_MASK(16),
- .shift = 16,
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static void avr32_timer_ack(void)
-{
- u16 count = expirelo;
-
- /* Ack this timer interrupt and set the next one, use a u16
- * variable so it will wrap around correctly */
- count += cycles_per_jiffy;
- expirelo = count;
- timer_write(ioregs, 0, RC, expirelo);
-
- /* Check to see if we have missed any timer interrupts */
- count = timer_read(ioregs, 0, CV);
- if ((count - expirelo) < 0x7fff) {
- expirelo = count + cycles_per_jiffy;
- timer_write(ioregs, 0, RC, expirelo);
- }
-}
-
-u32 avr32_hpt_read(void)
-{
- return timer_read(ioregs, 0, CV);
-}
-
-static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk)
-{
- unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2;
- unsigned int divs[] = { 4, 8, 16, 32 };
- int divs_size = ARRAY_SIZE(divs);
- int i = 0;
- unsigned long count_hz;
- unsigned long shift;
- unsigned long mult;
- int clock_div = -1;
- u64 tmp;
-
- shift = clocksource_avr32.shift;
-
- do {
- count_hz = clk_get_rate(pclk) / divs[i];
- mult = clocksource_hz2mult(count_hz, shift);
- clocksource_avr32.mult = mult;
-
- tmp = TICK_NSEC;
- tmp <<= shift;
- tmp += mult / 2;
- do_div(tmp, mult);
-
- cycles_per_jiffy = tmp;
- } while (cycles_per_jiffy > cycles_max && ++i < divs_size);
-
- clock_div = i + 1;
-
- if (clock_div > divs_size) {
- pr_debug("timer: could not calculate clock divider\n");
- return -EFAULT;
- }
-
- /* Set the clock divider */
- timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div));
-
- return 0;
-}
-
-int avr32_hpt_init(unsigned int count)
-{
- struct resource *regs;
- struct clk *pclk;
- int irq = -1;
- int ret = 0;
-
- ret = -ENXIO;
-
- irq = platform_get_irq(&at32_systc0_device, 0);
- if (irq < 0) {
- pr_debug("timer: could not get irq\n");
- goto out_error;
- }
-
- pclk = clk_get(&at32_systc0_device.dev, "pclk");
- if (IS_ERR(pclk)) {
- pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk));
- goto out_error;
- }
- clk_enable(pclk);
-
- regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0);
- if (!regs) {
- pr_debug("timer: could not get resource\n");
- goto out_error_clk;
- }
-
- ioregs = ioremap(regs->start, regs->end - regs->start + 1);
- if (!ioregs) {
- pr_debug("timer: could not get ioregs\n");
- goto out_error_clk;
- }
-
- ret = avr32_timer_calc_div_and_set_jiffies(pclk);
- if (ret)
- goto out_error_io;
-
- ret = setup_irq(irq, &timer_irqaction);
- if (ret) {
- pr_debug("timer: could not request irq %d: %d\n",
- irq, ret);
- goto out_error_io;
- }
-
- expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1)
- * cycles_per_jiffy;
-
- /* Enable clock and interrupts on RC compare */
- timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN));
- timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS));
- /* Set cycles to first interrupt */
- timer_write(ioregs, 0, RC, expirelo);
-
- printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n",
- ioregs, irq);
-
- return 0;
-
-out_error_io:
- iounmap(ioregs);
-out_error_clk:
- clk_put(pclk);
-out_error:
- return ret;
-}
-
-int avr32_hpt_start(void)
-{
- timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG));
- return 0;
-}
-
-irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
- unsigned int sr = timer_read(ioregs, 0, SR);
-
- if (sr & TIMER_BIT(SR_CPCS)) {
- /* ack timer interrupt and try to set next interrupt */
- avr32_timer_ack();
-
- /*
- * Call the generic timer interrupt handler
- */
- write_seqlock(&xtime_lock);
- do_timer(1);
- write_sequnlock(&xtime_lock);
-
- /*
- * In UP mode, we call local_timer_interrupt() to do profiling
- * and process accounting.
- *
- * SMP is not supported yet.
- */
- local_timer_interrupt(irq, dev_id);
-
- return IRQ_HANDLED;
- }
-
- return IRQ_NONE;
-}
*/
unsigned long mmu_context_cache = NO_CONTEXT;
-#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
-#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
-
void show_mem(void)
{
int total = 0, reserved = 0, cached = 0;
#include <linux/sched.h>
#include <linux/types.h>
-#include <asm/intc.h>
#include <asm/sysreg.h>
#include <asm/system.h>
/* This is an NTP setting */
#define TICK_SIZE (tick_nsec / 1000)
-static void time_sched_init(irqreturn_t(*timer_routine)
- (int, void *));
+static void time_sched_init(irq_handler_t timer_routine);
static unsigned long gettimeoffset(void);
static struct irqaction bfin_timer_irq = {
#define TIME_SCALE 1
static void
-time_sched_init(irqreturn_t(*timer_routine) (int, void *))
+time_sched_init(irq_handler_t timer_routine)
{
u32 tcount;
#define PCI_PROBE_BIOS 0x0001
#define PCI_PROBE_CONF1 0x0002
#define PCI_PROBE_CONF2 0x0004
-#define PCI_NO_SORT 0x0100
-#define PCI_BIOS_SORT 0x0200
#define PCI_NO_CHECKS 0x0400
#define PCI_ASSIGN_ROMS 0x1000
#define PCI_BIOS_IRQ_SCAN 0x2000
return NULL;
}
-/*
- * Several buggy motherboards address only 16 devices and mirror
- * them to next 16 IDs. We try to detect this `feature' on all
- * primary buses (those containing host bridges as they are
- * expected to be unique) and remove the ghost devices.
- */
-
-static void __init pcibios_fixup_ghosts(struct pci_bus *b)
-{
- struct list_head *ln, *mn;
- struct pci_dev *d, *e;
- int mirror = PCI_DEVFN(16,0);
- int seen_host_bridge = 0;
- int i;
-
- for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
- d = pci_dev_b(ln);
- if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
- seen_host_bridge++;
- for (mn=ln->next; mn != &b->devices; mn=mn->next) {
- e = pci_dev_b(mn);
- if (e->devfn != d->devfn + mirror ||
- e->vendor != d->vendor ||
- e->device != d->device ||
- e->class != d->class)
- continue;
- for(i=0; i<PCI_NUM_RESOURCES; i++)
- if (e->resource[i].start != d->resource[i].start ||
- e->resource[i].end != d->resource[i].end ||
- e->resource[i].flags != d->resource[i].flags)
- continue;
- break;
- }
- if (mn == &b->devices)
- return;
- }
- if (!seen_host_bridge)
- return;
- printk("PCI: Ignoring ghost devices on bus %02x\n", b->number);
-
- ln = &b->devices;
- while (ln->next != &b->devices) {
- d = pci_dev_b(ln->next);
- if (d->devfn >= mirror) {
- list_del(&d->global_list);
- list_del(&d->bus_list);
- kfree(d);
- } else
- ln = ln->next;
- }
-}
-
/*
* Discover remaining PCI buses in case there are peer host bridges.
* We use the number of last PCI bus provided by the PCI BIOS.
#if 0
printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
#endif
- pcibios_fixup_ghosts(bus);
pci_read_bridge_bases(bus);
if (bus->number == 0) {
{
return virt_to_page(ptr);
}
-
-
-EXPORT_SYMBOL(kmap_atomic_to_page);
depends on !IA64_HP_SIM
default y
-config IA64_SGI_SN_XP
- tristate "Support communication between SGI SSIs"
- depends on IA64_GENERIC || IA64_SGI_SN2
- select IA64_UNCACHED_ALLOCATOR
- help
- An SGI machine can be divided into multiple Single System
- Images which act independently of each other and have
- hardware based memory protection from the others. Enabling
- this feature will allow for direct communication between SSIs
- based on a network adapter and DMA messaging.
-
config FORCE_MAX_ZONEORDER
int "MAX_ORDER (11 - 17)" if !HUGETLB_PAGE
range 11 17 if !HUGETLB_PAGE
unw_init_running(kdump_cpu_freeze, NULL);
break;
case DIE_MCA_MONARCH_LEAVE:
- /* die_register->signr indicate if MCA is recoverable */
- if (kdump_on_fatal_mca && !args->signr) {
+ /* *(nd->data) indicate if MCA is recoverable */
+ if (kdump_on_fatal_mca && !(*(nd->data))) {
atomic_set(&kdump_in_progress, 1);
*(nd->monarch_cpu) = -1;
machine_kdump_on_init();
br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
.ret3:
(pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
+(pUStk) rsm psr.i // disable interrupts
br.cond.sptk .work_pending_syscall_end
strace_error:
# define IA64_MCA_DEBUG(fmt...)
#endif
+#define NOTIFY_INIT(event, regs, arg, spin) \
+do { \
+ if ((notify_die((event), "INIT", (regs), (arg), 0, 0) \
+ == NOTIFY_STOP) && ((spin) == 1)) \
+ ia64_mca_spin(__func__); \
+} while (0)
+
+#define NOTIFY_MCA(event, regs, arg, spin) \
+do { \
+ if ((notify_die((event), "MCA", (regs), (arg), 0, 0) \
+ == NOTIFY_STOP) && ((spin) == 1)) \
+ ia64_mca_spin(__func__); \
+} while (0)
+
/* Used by mca_asm.S */
DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
/* Mask all interrupts */
local_irq_save(flags);
- if (notify_die(DIE_MCA_RENDZVOUS_ENTER, "MCA", get_irq_regs(),
- (long)&nd, 0, 0) == NOTIFY_STOP)
- ia64_mca_spin(__func__);
+
+ NOTIFY_MCA(DIE_MCA_RENDZVOUS_ENTER, get_irq_regs(), (long)&nd, 1);
ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
/* Register with the SAL monarch that the slave has
*/
ia64_sal_mc_rendez();
- if (notify_die(DIE_MCA_RENDZVOUS_PROCESS, "MCA", get_irq_regs(),
- (long)&nd, 0, 0) == NOTIFY_STOP)
- ia64_mca_spin(__func__);
+ NOTIFY_MCA(DIE_MCA_RENDZVOUS_PROCESS, get_irq_regs(), (long)&nd, 1);
/* Wait for the monarch cpu to exit. */
while (monarch_cpu != -1)
cpu_relax(); /* spin until monarch leaves */
- if (notify_die(DIE_MCA_RENDZVOUS_LEAVE, "MCA", get_irq_regs(),
- (long)&nd, 0, 0) == NOTIFY_STOP)
- ia64_mca_spin(__func__);
+ NOTIFY_MCA(DIE_MCA_RENDZVOUS_LEAVE, get_irq_regs(), (long)&nd, 1);
ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
/* Enable all interrupts */
int recover, cpu = smp_processor_id();
struct task_struct *previous_current;
struct ia64_mca_notify_die nd =
- { .sos = sos, .monarch_cpu = &monarch_cpu };
+ { .sos = sos, .monarch_cpu = &monarch_cpu, .data = &recover };
static atomic_t mca_count;
static cpumask_t mca_cpu;
previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
- if (notify_die(DIE_MCA_MONARCH_ENTER, "MCA", regs, (long)&nd, 0, 0)
- == NOTIFY_STOP)
- ia64_mca_spin(__func__);
+ NOTIFY_MCA(DIE_MCA_MONARCH_ENTER, regs, (long)&nd, 1);
ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA;
if (sos->monarch) {
* does not work.
*/
ia64_mca_wakeup_all();
- if (notify_die(DIE_MCA_MONARCH_PROCESS, "MCA", regs, (long)&nd, 0, 0)
- == NOTIFY_STOP)
- ia64_mca_spin(__func__);
} else {
while (cpu_isset(cpu, mca_cpu))
cpu_relax(); /* spin until monarch wakes us */
- }
+ }
+
+ NOTIFY_MCA(DIE_MCA_MONARCH_PROCESS, regs, (long)&nd, 1);
/* Get the MCA error record and log it */
ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
mca_insert_tr(0x2); /*Reload dynamic itrs*/
}
- if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, (long)&nd, 0, recover)
- == NOTIFY_STOP)
- ia64_mca_spin(__func__);
+ NOTIFY_MCA(DIE_MCA_MONARCH_LEAVE, regs, (long)&nd, 1);
if (atomic_dec_return(&mca_count) > 0) {
int i;
struct ia64_mca_notify_die nd =
{ .sos = sos, .monarch_cpu = &monarch_cpu };
- (void) notify_die(DIE_INIT_ENTER, "INIT", regs, (long)&nd, 0, 0);
+ NOTIFY_INIT(DIE_INIT_ENTER, regs, (long)&nd, 0);
mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
sos->proc_state_param, cpu, sos->monarch);
ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
while (monarch_cpu == -1)
cpu_relax(); /* spin until monarch enters */
- if (notify_die(DIE_INIT_SLAVE_ENTER, "INIT", regs, (long)&nd, 0, 0)
- == NOTIFY_STOP)
- ia64_mca_spin(__func__);
- if (notify_die(DIE_INIT_SLAVE_PROCESS, "INIT", regs, (long)&nd, 0, 0)
- == NOTIFY_STOP)
- ia64_mca_spin(__func__);
+
+ NOTIFY_INIT(DIE_INIT_SLAVE_ENTER, regs, (long)&nd, 1);
+ NOTIFY_INIT(DIE_INIT_SLAVE_PROCESS, regs, (long)&nd, 1);
+
while (monarch_cpu != -1)
cpu_relax(); /* spin until monarch leaves */
- if (notify_die(DIE_INIT_SLAVE_LEAVE, "INIT", regs, (long)&nd, 0, 0)
- == NOTIFY_STOP)
- ia64_mca_spin(__func__);
+
+ NOTIFY_INIT(DIE_INIT_SLAVE_LEAVE, regs, (long)&nd, 1);
+
mprintk("Slave on cpu %d returning to normal service.\n", cpu);
set_curr_task(cpu, previous_current);
ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
}
monarch_cpu = cpu;
- if (notify_die(DIE_INIT_MONARCH_ENTER, "INIT", regs, (long)&nd, 0, 0)
- == NOTIFY_STOP)
- ia64_mca_spin(__func__);
+ NOTIFY_INIT(DIE_INIT_MONARCH_ENTER, regs, (long)&nd, 1);
/*
* Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
* to default_monarch_init_process() above and just print all the
* tasks.
*/
- if (notify_die(DIE_INIT_MONARCH_PROCESS, "INIT", regs, (long)&nd, 0, 0)
- == NOTIFY_STOP)
- ia64_mca_spin(__func__);
- if (notify_die(DIE_INIT_MONARCH_LEAVE, "INIT", regs, (long)&nd, 0, 0)
- == NOTIFY_STOP)
- ia64_mca_spin(__func__);
+ NOTIFY_INIT(DIE_INIT_MONARCH_PROCESS, regs, (long)&nd, 1);
+ NOTIFY_INIT(DIE_INIT_MONARCH_LEAVE, regs, (long)&nd, 1);
+
mprintk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu);
atomic_dec(&monarchs);
set_curr_task(cpu, previous_current);
printk(KERN_INFO "Increasing MCA rendezvous timeout from "
"%ld to %ld milliseconds\n", timeout, isrv.v0);
timeout = isrv.v0;
- (void) notify_die(DIE_MCA_NEW_TIMEOUT, "MCA", NULL, timeout, 0, 0);
+ NOTIFY_MCA(DIE_MCA_NEW_TIMEOUT, NULL, timeout, 0);
continue;
}
printk(KERN_ERR "Failed to register rendezvous interrupt "
}
static int
-pfm_do_interrupt_handler(int irq, void *arg, struct pt_regs *regs)
+pfm_do_interrupt_handler(void *arg, struct pt_regs *regs)
{
struct task_struct *task;
pfm_context_t *ctx;
start_cycles = ia64_get_itc();
- ret = pfm_do_interrupt_handler(irq, arg, regs);
+ ret = pfm_do_interrupt_handler(arg, regs);
total_cycles = ia64_get_itc();
#include <linux/smp.h>
#include <linux/timer.h>
#include <linux/vmalloc.h>
+#include <linux/semaphore.h>
-#include <asm/semaphore.h>
#include <asm/sal.h>
#include <asm/uaccess.h>
/* ??? FIXME -- record old value for shutdown. */
}
-static inline int
-pcibios_enable_resources (struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
- unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
-
- if (!dev)
- return -EINVAL;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
- /* Only set up the desired resources. */
- if (!(mask & (1 << idx)))
- continue;
-
- r = &dev->resource[idx];
- if (!(r->flags & type_mask))
- continue;
- if ((idx == PCI_ROM_RESOURCE) &&
- (!(r->flags & IORESOURCE_ROM_ENABLE)))
- continue;
- if (!r->start && r->end) {
- printk(KERN_ERR
- "PCI: Device %s not available because of resource collisions\n",
- pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
int
pcibios_enable_device (struct pci_dev *dev, int mask)
{
int ret;
- ret = pcibios_enable_resources(dev, mask);
+ ret = pci_enable_resources(dev, mask);
if (ret < 0)
return ret;
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
-# Copyright (C) 1999,2001-2006 Silicon Graphics, Inc. All Rights Reserved.
+# Copyright (C) 1999,2001-2006,2008 Silicon Graphics, Inc. All Rights Reserved.
#
EXTRA_CFLAGS += -Iarch/ia64/sn/include
sn2/
obj-$(CONFIG_IA64_GENERIC) += machvec.o
obj-$(CONFIG_SGI_TIOCX) += tiocx.o
-obj-$(CONFIG_IA64_SGI_SN_XP) += xp.o
-xp-y := xp_main.o xp_nofault.o
-obj-$(CONFIG_IA64_SGI_SN_XP) += xpc.o
-xpc-y := xpc_main.o xpc_channel.o xpc_partition.o
-obj-$(CONFIG_IA64_SGI_SN_XP) += xpnet.o
obj-$(CONFIG_PCI_MSI) += msi_sn.o
{
if (request_irq(SGI_II_ERROR, hub_eint_handler, IRQF_SHARED,
- "SN_hub_error", (void *)hubdev_info)) {
- printk("hub_error_init: Failed to request_irq for 0x%p\n",
+ "SN_hub_error", hubdev_info)) {
+ printk(KERN_ERR "hub_error_init: Failed to request_irq for 0x%p\n",
hubdev_info);
return;
}
#include <asm/processor.h>
#include <asm/topology.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <asm/sal.h>
#include <asm/sn/io.h>
*
* Simply call tioce_do_dma_map() to create a map with the barrier bit set
* in the address.
- */ static u64
+ */
+static u64
tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags)
{
return tioce_do_dma_map(pdev, paddr, byte_count, 1, dma_flags);
*
* Handle a CE error interrupt. Simply a wrapper around a SAL call which
* defers processing to the SGI prom.
- */ static irqreturn_t
+ */
+static irqreturn_t
tioce_error_intr_handler(int irq, void *arg)
{
struct tioce_common *soft = arg;
#include <asm/atarihw.h>
#include <asm/atari_stram.h>
#include <asm/io.h>
-#include <asm/semaphore.h>
#undef DEBUG
#include <asm/errno.h>
#include <asm/system.h>
-#include <asm/semaphore.h>
#include <asm/rtc.h>
#include <asm/intersil.h>
#include <linux/init.h>
#include <asm/page.h>
-#include <asm/semaphore.h>
#include <asm/sn/addrs.h>
#include <asm/sn/sn0/hub.h>
#include <asm/sn/klconfig.h>
#define PCI_PROBE_BIOS 1
#define PCI_PROBE_CONF1 2
#define PCI_PROBE_CONF2 4
-#define PCI_NO_SORT 0x100
-#define PCI_BIOS_SORT 0x200
#define PCI_NO_CHECKS 0x400
#define PCI_ASSIGN_ROMS 0x1000
#define PCI_BIOS_IRQ_SCAN 0x2000
*/
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
- u16 cmd;
- int idx;
+ int err;
+ u16 cmd, old_cmd;
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
-
- for (idx = 0; idx < DEVICE_COUNT_RESOURCE; idx++) {
- struct resource *r = &dev->resource[idx];
+ err = pci_enable_resources(dev, mask);
+ if (err < 0)
+ return err;
- /* only setup requested resources */
- if (!(mask & (1<<idx)))
- continue;
-
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ old_cmd = cmd;
cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
cmd |= PCI_COMMAND_FAST_BACK;
#endif
- DBGC("PCIBIOS: Enabling device %s cmd 0x%04x\n", pci_name(dev), cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
+
+ if (cmd != old_cmd) {
+ dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
+ old_cmd, cmd);
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+ }
return 0;
}
#include <asm/types.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <asm/mmu_context.h>
#include "sys32.h"
bool
default y
+config STACKTRACE_SUPPORT
+ bool
+ default y
+
+config TRACE_IRQFLAGS_SUPPORT
+ bool
+ depends on PPC64
+ default y
+
+config LOCKDEP_SUPPORT
+ bool
+ default y
+
config RWSEM_GENERIC_SPINLOCK
bool
bool
default y
+config GENERIC_GPIO
+ bool
+ help
+ Generic GPIO API support
+
config ARCH_NO_VIRT_TO_BUS
def_bool PPC64
select HAVE_OPROFILE
select HAVE_KPROBES
select HAVE_KRETPROBES
+ select HAVE_LMB
config EARLY_PRINTK
bool
source kernel/Kconfig.preempt
source "fs/Kconfig.binfmt"
-# We optimistically allocate largepages from the VM, so make the limit
-# large enough (16MB). This badly named config option is actually
-# max order + 1
-config FORCE_MAX_ZONEORDER
- int
- depends on PPC64
- default "9" if PPC_64K_PAGES
- default "13"
-
config HUGETLB_PAGE_SIZE_VARIABLE
bool
depends on HUGETLB_PAGE
Don't change this unless you know what you are doing.
+config PHYP_DUMP
+ bool "Hypervisor-assisted dump (EXPERIMENTAL)"
+ depends on PPC_PSERIES && EXPERIMENTAL
+ help
+ Hypervisor-assisted dump is meant to be a kdump replacement
+ offering robustness and speed not possible without system
+ hypervisor assistence.
+
+ If unsure, say "N"
+
config PPCBUG_NVRAM
bool "Enable reading PPCBUG NVRAM during boot" if PPLUS || LOPEC
default y if PPC_PREP
while on hardware with such support, it will be used to map
normal application pages.
+config FORCE_MAX_ZONEORDER
+ int "Maximum zone order"
+ default "9" if PPC_64K_PAGES
+ default "13" if PPC64 && !PPC_64K_PAGES
+ default "11"
+ help
+ The kernel memory allocator divides physically contiguous memory
+ blocks into "zones", where each zone is a power of two number of
+ pages. This option selects the largest power of two that the kernel
+ keeps in the memory allocator. If you need to allocate very large
+ blocks of physically contiguous memory, then you may need to
+ increase this value.
+
+ This config option is actually maximum order plus one. For example,
+ a value of 11 means that the largest free memory block is 2^10 pages.
+
+ The page size is not necessarily 4KB. For example, on 64-bit
+ systems, 64KB pages can be enabled via CONFIG_PPC_64K_PAGES. Keep
+ this in mind when choosing a value for this option.
+
config PPC_SUBPAGE_PROT
bool "Support setting protections for 4k subpages"
depends on PPC_64K_PAGES
bool
select PPC_INDIRECT_PCI
+config 4xx_SOC
+ bool
+
+config FSL_LBC
+ bool
+ help
+ Freescale Localbus support
+
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
config MCA
bool
hex "Size of consistent memory pool" if CONSISTENT_SIZE_BOOL
default "0x00200000" if NOT_COHERENT_CACHE
-config BOOT_LOAD_BOOL
- bool "Set the boot link/load address"
- depends on ADVANCED_OPTIONS && !PPC_MULTIPLATFORM
- help
- This option allows you to set the initial load address of the zImage
- or zImage.initrd file. This can be useful if you are on a board
- which has a small amount of memory.
-
- Say N here unless you know what you are doing.
-
-config BOOT_LOAD
- hex "Link/load address for booting" if BOOT_LOAD_BOOL
- default "0x00400000" if 40x || 8xx || 8260
- default "0x01000000" if 44x
- default "0x00800000"
-
config PIN_TLB
bool "Pinned Kernel TLBs (860 ONLY)"
depends on ADVANCED_OPTIONS && 8xx
hex "CPM UART early debug transmit descriptor address"
depends on PPC_EARLY_DEBUG_CPM
default "0xfa202008" if PPC_EP88XC
- default "0xf0000008" if CPM2
+ default "0xf0001ff8" if CPM2
default "0xff002008" if CPM1
help
This specifies the address of the transmit descriptor
LDFLAGS_vmlinux := -Bstatic
-CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
-AFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=none -mcall-aixdesc
-CFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH) -ffixed-r2 -mmultiple
-KBUILD_CPPFLAGS += $(CPPFLAGS-y)
-KBUILD_AFLAGS += $(AFLAGS-y)
-KBUILD_CFLAGS += -msoft-float -pipe $(CFLAGS-y)
+CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 -mmultiple
+KBUILD_CPPFLAGS += -Iarch/$(ARCH)
+KBUILD_AFLAGS += -Iarch/$(ARCH)
+KBUILD_CFLAGS += -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y)
CPP = $(CC) -E $(KBUILD_CFLAGS)
CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__
$(BOOT_TARGETS): vmlinux
$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
-bootwrapper_install:
+bootwrapper_install %.dtb:
$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
define archhelp
$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
+$(obj)/virtex405-head.o: BOOTCFLAGS += -mcpu=405
zlib := inffast.c inflate.c inftrees.c
cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
fixed-head.S ep88xc.c ep405.c \
cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
- cuboot-warp.c cuboot-85xx-cpm2.c
+ cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
+ virtex405-head.S
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
image-$(CONFIG_PPC_HOLLY) += zImage.holly
-image-$(CONFIG_PPC_PRPMC2800) += zImage.prpmc2800
+image-$(CONFIG_PPC_PRPMC2800) += dtbImage.prpmc2800
image-$(CONFIG_PPC_ISERIES) += zImage.iseries
image-$(CONFIG_DEFAULT_UIMAGE) += uImage
image-$(CONFIG_TAISHAN) += cuImage.taishan
image-$(CONFIG_KATMAI) += cuImage.katmai
image-$(CONFIG_WARP) += cuImage.warp
+image-$(CONFIG_YOSEMITE) += cuImage.yosemite
# Board ports in arch/powerpc/platform/8xx/Kconfig
image-$(CONFIG_PPC_MPC86XADS) += cuImage.mpc866ads
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_SBC8548) += cuImage.sbc8548
image-$(CONFIG_SBC8560) += cuImage.sbc8560
+image-$(CONFIG_KSI8560) += cuImage.ksi8560
# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
image-$(CONFIG_STORCENTER) += cuImage.storcenter
$(call if_changed,wrap,$*)
# dtbImage% - a dtbImage is a zImage with an embedded device tree blob
-$(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(dtstree)/%.dts
- $(call if_changed,wrap,$*,$(dtstree)/$*.dts,,$(obj)/ramdisk.image.gz)
+$(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(obj)/%.dtb
+ $(call if_changed,wrap,$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
-$(obj)/dtbImage.%: vmlinux $(wrapperbits) $(dtstree)/%.dts
- $(call if_changed,wrap,$*,$(dtstree)/$*.dts)
+$(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb
+ $(call if_changed,wrap,$*,,$(obj)/$*.dtb)
# This cannot be in the root of $(src) as the zImage rule always adds a $(obj)
# prefix
$(obj)/uImage: vmlinux $(wrapperbits)
$(call if_changed,wrap,uboot)
-$(obj)/cuImage.%: vmlinux $(dtstree)/%.dts $(wrapperbits)
- $(call if_changed,wrap,cuboot-$*,$(dtstree)/$*.dts)
+$(obj)/cuImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+ $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb)
-$(obj)/treeImage.initrd.%: vmlinux $(dtstree)/%.dts $(wrapperbits)
- $(call if_changed,wrap,treeboot-$*,$(dtstree)/$*.dts,,$(obj)/ramdisk.image.gz)
+$(obj)/simpleImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+ $(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
-$(obj)/treeImage.%: vmlinux $(dtstree)/%.dts $(wrapperbits)
- $(call if_changed,wrap,treeboot-$*,$(dtstree)/$*.dts)
+$(obj)/simpleImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+ $(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb)
+
+$(obj)/treeImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+ $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
+
+$(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+ $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb)
+
+# Rule to build device tree blobs
+$(obj)/%.dtb: $(dtstree)/%.dts $(obj)/dtc
+ $(obj)/dtc -O dtb -o $(obj)/$*.dtb -b 0 $(DTS_FLAGS) $(dtstree)/$*.dts
# If there isn't a platform selected then just strip the vmlinux.
ifeq (,$(image-y))
# anything not in $(targets)
clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.* treeImage.* \
- otheros.bld
+ otheros.bld *.dtb
# clean up files cached by wrapper
clean-kernel := vmlinux.strip vmlinux.bin
ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
ibm4xx_sdram_fixup_memsize();
ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
- dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
+ dt_fixup_mac_address_by_alias("ethernet0", bamboo_mac0);
+ dt_fixup_mac_address_by_alias("ethernet1", bamboo_mac1);
}
void bamboo_init(void *mac0, void *mac1)
#include "types.h"
#include "io.h"
#include "ops.h"
+#include "page.h"
struct cpm_scc {
u32 gsmrl;
u16 tbase;
u8 rfcr;
u8 tfcr;
+ u16 mrblr;
+ u32 rstate;
+ u8 res1[4];
+ u16 rbptr;
+ u8 res2[6];
+ u32 tstate;
+ u8 res3[4];
+ u16 tbptr;
+ u8 res4[6];
+ u16 maxidl;
+ u16 idlc;
+ u16 brkln;
+ u16 brkec;
+ u16 brkcr;
+ u16 rmask;
+ u8 res5[4];
};
struct cpm_bd {
static struct cpm_param *param;
static struct cpm_smc *smc;
static struct cpm_scc *scc;
-struct cpm_bd *tbdf, *rbdf;
+static struct cpm_bd *tbdf, *rbdf;
static u32 cpm_cmd;
-static u8 *muram_start;
-static u32 muram_offset;
+static void *cbd_addr;
+static u32 cbd_offset;
static void (*do_cmd)(int op);
static void (*enable_port)(void);
out_8(¶m->rfcr, 0x10);
out_8(¶m->tfcr, 0x10);
-
- rbdf = (struct cpm_bd *)muram_start;
- rbdf->addr = (u8 *)(rbdf + 2);
+ out_be16(¶m->mrblr, 1);
+ out_be16(¶m->maxidl, 0);
+ out_be16(¶m->brkec, 0);
+ out_be16(¶m->brkln, 0);
+ out_be16(¶m->brkcr, 0);
+
+ rbdf = cbd_addr;
+ rbdf->addr = (u8 *)rbdf - 1;
rbdf->sc = 0xa000;
rbdf->len = 1;
tbdf = rbdf + 1;
- tbdf->addr = (u8 *)(rbdf + 2) + 1;
+ tbdf->addr = (u8 *)rbdf - 2;
tbdf->sc = 0x2000;
tbdf->len = 1;
sync();
- out_be16(¶m->rbase, muram_offset);
- out_be16(¶m->tbase, muram_offset + sizeof(struct cpm_bd));
+ out_be16(¶m->rbase, cbd_offset);
+ out_be16(¶m->tbase, cbd_offset + sizeof(struct cpm_bd));
do_cmd(CPM_CMD_INIT_RX_TX);
int cpm_console_init(void *devp, struct serial_console_data *scdp)
{
- void *reg_virt[2];
- int is_smc = 0, is_cpm2 = 0, n;
- unsigned long reg_phys;
+ void *vreg[2];
+ u32 reg[2];
+ int is_smc = 0, is_cpm2 = 0;
void *parent, *muram;
+ void *muram_addr;
+ unsigned long muram_offset, muram_size;
if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
is_smc = 1;
else
do_cmd = cpm1_cmd;
- n = getprop(devp, "fsl,cpm-command", &cpm_cmd, 4);
- if (n < 4)
+ if (getprop(devp, "fsl,cpm-command", &cpm_cmd, 4) < 4)
return -1;
- n = getprop(devp, "virtual-reg", reg_virt, sizeof(reg_virt));
- if (n < (int)sizeof(reg_virt)) {
- for (n = 0; n < 2; n++) {
- if (!dt_xlate_reg(devp, n, ®_phys, NULL))
- return -1;
-
- reg_virt[n] = (void *)reg_phys;
- }
- }
+ if (dt_get_virtual_reg(devp, vreg, 2) < 2)
+ return -1;
if (is_smc)
- smc = reg_virt[0];
+ smc = vreg[0];
else
- scc = reg_virt[0];
+ scc = vreg[0];
- param = reg_virt[1];
+ param = vreg[1];
parent = get_parent(devp);
if (!parent)
return -1;
- n = getprop(parent, "virtual-reg", reg_virt, sizeof(reg_virt));
- if (n < (int)sizeof(reg_virt)) {
- if (!dt_xlate_reg(parent, 0, ®_phys, NULL))
- return -1;
-
- reg_virt[0] = (void *)reg_phys;
- }
-
- cpcr = reg_virt[0];
+ if (dt_get_virtual_reg(parent, &cpcr, 1) < 1)
+ return -1;
muram = finddevice("/soc/cpm/muram/data");
if (!muram)
return -1;
/* For bootwrapper-compatible device trees, we assume that the first
- * entry has at least 18 bytes, and that #address-cells/#data-cells
+ * entry has at least 128 bytes, and that #address-cells/#data-cells
* is one for both parent and child.
*/
- n = getprop(muram, "virtual-reg", reg_virt, sizeof(reg_virt));
- if (n < (int)sizeof(reg_virt)) {
- if (!dt_xlate_reg(muram, 0, ®_phys, NULL))
- return -1;
+ if (dt_get_virtual_reg(muram, &muram_addr, 1) < 1)
+ return -1;
- reg_virt[0] = (void *)reg_phys;
- }
+ if (getprop(muram, "reg", reg, 8) < 8)
+ return -1;
- muram_start = reg_virt[0];
+ muram_offset = reg[0];
+ muram_size = reg[1];
- n = getprop(muram, "reg", &muram_offset, 4);
- if (n < 4)
- return -1;
+ /* Store the buffer descriptors at the end of the first muram chunk.
+ * For SMC ports on CPM2-based platforms, relocate the parameter RAM
+ * just before the buffer descriptors.
+ */
+
+ cbd_offset = muram_offset + muram_size - 2 * sizeof(struct cpm_bd);
+
+ if (is_cpm2 && is_smc) {
+ u16 *smc_base = (u16 *)param;
+ u16 pram_offset;
+
+ pram_offset = cbd_offset - 64;
+ pram_offset = _ALIGN_DOWN(pram_offset, 64);
+
+ disable_port();
+ out_be16(smc_base, pram_offset);
+ param = muram_addr - muram_offset + pram_offset;
+ }
+
+ cbd_addr = muram_addr - muram_offset + cbd_offset;
scdp->open = cpm_serial_open;
scdp->putc = cpm_serial_putc;
u8 *soc_regs;
int i, len;
void *node, *parent_node;
- u32 naddr, nsize, mem_log2;
+ u32 naddr, nsize, mem_pow2, mem_mask;
node = finddevice("/pci");
if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
soc_regs = (u8 *)fsl_get_immr();
if (!soc_regs)
- goto err;
+ goto unhandled;
dt_get_reg_format(node, &naddr, &nsize);
if (naddr != 3 || nsize != 2)
dt_get_reg_format(parent_node, &naddr, &nsize);
if (naddr != 1 || nsize != 1)
- goto err;
+ goto unhandled;
len = getprop(node, "ranges", pci_ranges_buf,
sizeof(pci_ranges_buf));
}
if (!mem || !mmio || !io)
- goto err;
+ goto unhandled;
+ if (mem->size[1] != mmio->size[1])
+ goto unhandled;
+ if (mem->size[1] & (mem->size[1] - 1))
+ goto unhandled;
+ if (io->size[1] & (io->size[1] - 1))
+ goto unhandled;
if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
mem_base = mem;
else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
mem_base = mmio;
else
- goto err;
+ goto unhandled;
out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
out_le32(&pci_regs[0][58], 0);
out_le32(&pci_regs[0][60], 0);
- mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
- out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1));
+ mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
+ mem_mask = ~(mem_pow2 - 1) >> 12;
+ out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask);
/* If PCI is disabled, drive RST high to enable. */
if (!(in_le32(&pci_regs[0][32]) & 1)) {
return;
err:
- printf("Bad PCI node\r\n");
+ printf("Bad PCI node -- using existing firmware setup.\r\n");
+ return;
+
+unhandled:
+ printf("Unsupported PCI node -- using existing firmware setup.\r\n");
}
static void pq2_platform_fixups(void)
ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
ibm4xx_denali_fixup_memsize();
- dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
+ dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+ dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
ibm4xx_denali_fixup_memsize();
- dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
+ dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+ dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
ibm4xx_sdram_fixup_memsize();
- dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
+ dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+ dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
}
ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
ibm4xx_sdram_fixup_memsize();
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
- dt_fixup_mac_addresses(&bd.bi_enetaddr);
+ dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
}
--- /dev/null
+/*
+ * Old U-boot compatibility for Yosemite
+ *
+ * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * Copyright 2008 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "4xx.h"
+#include "44x.h"
+#include "cuboot.h"
+
+#define TARGET_4xx
+#define TARGET_44x
+#include "ppcboot.h"
+
+static bd_t bd;
+
+static void yosemite_fixups(void)
+{
+ unsigned long sysclk = 66666666;
+
+ ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
+ ibm4xx_sdram_fixup_memsize();
+ ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
+ dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+ dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ CUBOOT_INIT();
+ platform_ops.fixups = yosemite_fixups;
+ platform_ops.exit = ibm44x_dbcr_reset;
+ fdt_init(_dtb_start);
+ serial_console_init();
+}
return 0;
}
+
+int dt_get_virtual_reg(void *node, void **addr, int nres)
+{
+ unsigned long xaddr;
+ int n;
+
+ n = getprop(node, "virtual-reg", addr, nres * 4);
+ if (n > 0)
+ return n / 4;
+
+ for (n = 0; n < nres; n++) {
+ if (!dt_xlate_reg(node, n, &xaddr, NULL))
+ break;
+
+ addr[n] = (void *)xaddr;
+ }
+
+ return n;
+}
+
};
EMAC0: ethernet@ef600e00 {
- linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
interrupt-parent = <&UIC1>;
};
EMAC1: ethernet@ef600f00 {
- linux,network-index = <1>;
device_type = "network";
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
interrupt-parent = <&UIC1>;
--- /dev/null
+/*
+ * Device Tree Source for AMCC Canyonlands (460EX)
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,canyonlands";
+ compatible = "amcc,canyonlands";
+ dcr-parent = <&/cpus/cpu@0>;
+
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,460EX";
+ reg = <0>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <8000>;
+ d-cache-size = <8000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0>; /* Filled in by U-Boot */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-460ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-460ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1e 4 1f 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-460ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0e0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <a 4 b 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = "ibm,uic-460ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <3>;
+ dcr-reg = <0f0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <10 4 11 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-460ex";
+ dcr-reg = <00e 002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-460ex";
+ dcr-reg = <00c 002>;
+ };
+
+ plb {
+ compatible = "ibm,plb-460ex", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ SDRAM0: sdram {
+ compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
+ dcr-reg = <010 2>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
+ dcr-reg = <180 62>;
+ num-tx-chans = <2>;
+ num-rx-chans = <10>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-parent = <&UIC2>;
+ interrupts = < /*TXEOB*/ 6 4
+ /*RXEOB*/ 7 4
+ /*SERR*/ 3 4
+ /*TXDE*/ 4 4
+ /*RXDE*/ 5 4>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-460ex", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <b0000000 4 b0000000 50000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-460ex", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ interrupts = <6 4>;
+ interrupt-parent = <&UIC1>;
+ };
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <1 4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600400 8>;
+ virtual-reg = <ef600400>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ UART2: serial@ef600500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600500 8>;
+ virtual-reg = <ef600500>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <1d 4>;
+ };
+
+ UART3: serial@ef600600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600600 8>;
+ virtual-reg = <ef600600>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <1e 4>;
+ };
+
+ IIC0: i2c@ef600700 {
+ compatible = "ibm,iic-460ex", "ibm,iic";
+ reg = <ef600700 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ IIC1: i2c@ef600800 {
+ compatible = "ibm,iic-460ex", "ibm,iic";
+ reg = <ef600800 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <3 4>;
+ };
+
+ ZMII0: emac-zmii@ef600d00 {
+ compatible = "ibm,zmii-460ex", "ibm,zmii";
+ reg = <ef600d00 c>;
+ };
+
+ RGMII0: emac-rgmii@ef601500 {
+ compatible = "ibm,rgmii-460ex", "ibm,rgmii";
+ reg = <ef601500 8>;
+ has-mdio;
+ };
+
+ TAH0: emac-tah@ef601350 {
+ compatible = "ibm,tah-460ex", "ibm,tah";
+ reg = <ef601350 30>;
+ };
+
+ TAH1: emac-tah@ef601450 {
+ compatible = "ibm,tah-460ex", "ibm,tah";
+ reg = <ef601450 30>;
+ };
+
+ EMAC0: ethernet@ef600e00 {
+ device_type = "network";
+ compatible = "ibm,emac-460ex", "ibm,emac4";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC2 10 4
+ /*Wake*/ 1 &UIC2 14 4>;
+ reg = <ef600e00 70>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <2328>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <0>;
+ tah-device = <&TAH0>;
+ tah-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ };
+
+ EMAC1: ethernet@ef600f00 {
+ device_type = "network";
+ compatible = "ibm,emac-460ex", "ibm,emac4";
+ interrupt-parent = <&EMAC1>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC2 11 4
+ /*Wake*/ 1 &UIC2 15 4>;
+ reg = <ef600f00 70>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <1>;
+ mal-rx-channel = <8>;
+ cell-index = <1>;
+ max-frame-size = <2328>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <1>;
+ tah-device = <&TAH1>;
+ tah-channel = <1>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ mdio-device = <&EMAC0>;
+ };
+ };
+
+ PCIX0: pci@c0ec00000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
+ primary;
+ large-inbound-windows;
+ enable-msi-hole;
+ reg = <c 0ec00000 8 /* Config space access */
+ 0 0 0 /* no IACK cycles */
+ c 0ed00000 4 /* Special cycles */
+ c 0ec80000 100 /* Internal registers */
+ c 0ec80100 fc>; /* Internal messaging registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
+ 01000000 0 00000000 0000000c 08000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* This drives busses 0 to 0x3f */
+ bus-range = <0 3f>;
+
+ /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
+ interrupt-map-mask = <0000 0 0 0>;
+ interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
+ };
+
+ PCIE0: pciex@d00000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+ primary;
+ port = <0>; /* port number */
+ reg = <d 00000000 20000000 /* Config space access */
+ c 08010000 00001000>; /* Registers */
+ dcr-reg = <100 020>;
+ sdr-base = <300>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
+ 01000000 0 00000000 0000000f 80000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* This drives busses 40 to 0x7f */
+ bus-range = <40 7f>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
+ 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
+ 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
+ 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
+ };
+
+ PCIE1: pciex@d20000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+ primary;
+ port = <1>; /* port number */
+ reg = <d 20000000 20000000 /* Config space access */
+ c 08011000 00001000>; /* Registers */
+ dcr-reg = <120 020>;
+ sdr-base = <340>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
+ 01000000 0 00000000 0000000f 80010000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* This drives busses 80 to 0xbf */
+ bus-range = <80 bf>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
+ 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
+ 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
+ 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
+ };
+ };
+};
};
EMAC0: ethernet@40000800 {
- linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-440gp", "ibm,emac";
interrupt-parent = <&UIC1>;
zmii-channel = <0>;
};
EMAC1: ethernet@40000900 {
- linux,network-index = <1>;
device_type = "network";
compatible = "ibm,emac-440gp", "ibm,emac";
interrupt-parent = <&UIC1>;
data@0 {
compatible = "fsl,cpm-muram-data";
- reg = <0 0x1100 0x1140
- 0xec0 0x9800 0x800>;
+ reg = <0 0x2000 0x9800 0x800>;
};
};
device_type = "serial";
compatible = "fsl,mpc8248-smc-uart",
"fsl,cpm2-smc-uart";
- reg = <0x11a80 0x20 0x1100 0x40>;
+ reg = <0x11a80 0x20 0x87fc 2>;
interrupts = <4 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <7>;
* EP88xC Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007,2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
/ {
model = "EP88xC";
PowerPC,885@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <d#16>;
- i-cache-line-size = <d#16>;
- d-cache-size = <d#8192>;
- i-cache-size = <d#8192>;
+ reg = <0x0>;
+ d-cache-line-size = <16>;
+ i-cache-line-size = <16>;
+ d-cache-size = <8192>;
+ i-cache-size = <8192>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- interrupts = <f 2>; // decrementer interrupt
+ interrupts = <15 2>; // decrementer interrupt
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
- reg = <0 0>;
+ reg = <0x0 0x0>;
};
localbus@fa200100 {
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
- reg = <fa200100 40>;
+ reg = <0xfa200100 0x40>;
ranges = <
- 0 0 fc000000 04000000
- 3 0 fa000000 01000000
+ 0x0 0x0 0xfc000000 0x4000000
+ 0x3 0x0 0xfa000000 0x1000000
>;
flash@0,2000000 {
compatible = "cfi-flash";
- reg = <0 2000000 2000000>;
+ reg = <0x0 0x2000000 0x2000000>;
bank-width = <4>;
device-width = <2>;
};
board-control@3,400000 {
- reg = <3 400000 10>;
+ reg = <0x3 0x400000 0x10>;
compatible = "fsl,ep88xc-bcsr";
};
};
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <0 fa200000 00004000>;
+ ranges = <0x0 0xfa200000 0x4000>;
bus-frequency = <0>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
- reg = <fa200000 4000>;
+ reg = <0xfa200000 0x4000>;
mdio@e00 {
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
- reg = <e00 188>;
+ reg = <0xe00 0x188>;
#address-cells = <1>;
#size-cells = <0>;
PHY0: ethernet-phy@0 {
- reg = <0>;
+ reg = <0x0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
- reg = <1>;
+ reg = <0x1>;
device_type = "ethernet-phy";
};
};
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
- reg = <e00 188>;
+ reg = <0xe00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
interrupt-parent = <&PIC>;
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
- reg = <1e00 188>;
+ reg = <0x1e00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <7 1>;
interrupt-parent = <&PIC>;
PIC: interrupt-controller@0 {
interrupt-controller;
#interrupt-cells = <2>;
- reg = <0 24>;
+ reg = <0x0 0x24>;
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
};
#size-cells = <2>;
compatible = "fsl,pq-pcmcia";
device_type = "pcmcia";
- reg = <80 80>;
+ reg = <0x80 0x80>;
interrupt-parent = <&PIC>;
- interrupts = <d 1>;
+ interrupts = <13 1>;
};
cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
- command-proc = <9c0>;
+ command-proc = <0x9c0>;
interrupts = <0>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
- reg = <9c0 40>;
+ reg = <0x9c0 0x40>;
ranges;
muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 2000 2000>;
+ ranges = <0x0 0x2000 0x2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
- reg = <0 1c00>;
+ reg = <0x0 0x1c00>;
};
};
compatible = "fsl,mpc885-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
- reg = <9f0 10>;
+ reg = <0x9f0 0x10>;
};
CPM_PIC: interrupt-controller@930 {
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&PIC>;
- reg = <930 20>;
+ reg = <0x930 0x20>;
compatible = "fsl,mpc885-cpm-pic",
"fsl,cpm1-pic";
};
device_type = "serial";
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
- reg = <a80 10 3e80 40>;
+ reg = <0xa80 0x10 0x3e80 0x40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
- fsl,cpm-command = <0090>;
+ fsl,cpm-command = <0x90>;
linux,planetcore-label = "SMC1";
};
device_type = "serial";
compatible = "fsl,mpc885-scc-uart",
"fsl,cpm1-scc-uart";
- reg = <a20 20 3d00 80>;
- interrupts = <1d>;
+ reg = <0xa20 0x20 0x3d00 0x80>;
+ interrupts = <29>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
- fsl,cpm-command = <0040>;
+ fsl,cpm-command = <0x40>;
linux,planetcore-label = "SCC2";
};
#size-cells = <0>;
compatible = "fsl,mpc885-usb",
"fsl,cpm1-usb";
- reg = <a00 18 1c00 80>;
+ reg = <0xa00 0x18 0x1c00 0x80>;
interrupt-parent = <&CPM_PIC>;
- interrupts = <1e>;
+ interrupts = <30>;
fsl,cpm-command = <0000>;
};
};
--- /dev/null
+/*
+ * Device Tree Source for AMCC Glacier (460GT)
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,glacier";
+ compatible = "amcc,glacier", "amcc,canyonlands";
+ dcr-parent = <&/cpus/cpu@0>;
+
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ ethernet2 = &EMAC2;
+ ethernet3 = &EMAC3;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,460GT";
+ reg = <0>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <8000>;
+ d-cache-size = <8000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0>; /* Filled in by U-Boot */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1e 4 1f 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0e0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <a 4 b 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <3>;
+ dcr-reg = <0f0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <10 4 11 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-460gt";
+ dcr-reg = <00e 002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-460gt";
+ dcr-reg = <00c 002>;
+ };
+
+ plb {
+ compatible = "ibm,plb-460gt", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ SDRAM0: sdram {
+ compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
+ dcr-reg = <010 2>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
+ dcr-reg = <180 62>;
+ num-tx-chans = <4>;
+ num-rx-chans = <20>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-parent = <&UIC2>;
+ interrupts = < /*TXEOB*/ 6 4
+ /*RXEOB*/ 7 4
+ /*SERR*/ 3 4
+ /*TXDE*/ 4 4
+ /*RXDE*/ 5 4>;
+ desc-base-addr-high = <8>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-460gt", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <b0000000 4 b0000000 50000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-460gt", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ interrupts = <6 4>;
+ interrupt-parent = <&UIC1>;
+ };
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <1 4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600400 8>;
+ virtual-reg = <ef600400>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ UART2: serial@ef600500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600500 8>;
+ virtual-reg = <ef600500>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <1d 4>;
+ };
+
+ UART3: serial@ef600600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600600 8>;
+ virtual-reg = <ef600600>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <1e 4>;
+ };
+
+ IIC0: i2c@ef600700 {
+ compatible = "ibm,iic-460gt", "ibm,iic";
+ reg = <ef600700 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ IIC1: i2c@ef600800 {
+ compatible = "ibm,iic-460gt", "ibm,iic";
+ reg = <ef600800 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <3 4>;
+ };
+
+ ZMII0: emac-zmii@ef600d00 {
+ compatible = "ibm,zmii-460gt", "ibm,zmii";
+ reg = <ef600d00 c>;
+ };
+
+ RGMII0: emac-rgmii@ef601500 {
+ compatible = "ibm,rgmii-460gt", "ibm,rgmii";
+ reg = <ef601500 8>;
+ has-mdio;
+ };
+
+ RGMII1: emac-rgmii@ef601600 {
+ compatible = "ibm,rgmii-460gt", "ibm,rgmii";
+ reg = <ef601600 8>;
+ has-mdio;
+ };
+
+ TAH0: emac-tah@ef601350 {
+ compatible = "ibm,tah-460gt", "ibm,tah";
+ reg = <ef601350 30>;
+ };
+
+ TAH1: emac-tah@ef601450 {
+ compatible = "ibm,tah-460gt", "ibm,tah";
+ reg = <ef601450 30>;
+ };
+
+ EMAC0: ethernet@ef600e00 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC2 10 4
+ /*Wake*/ 1 &UIC2 14 4>;
+ reg = <ef600e00 70>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <2328>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <0>;
+ tah-device = <&TAH0>;
+ tah-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ };
+
+ EMAC1: ethernet@ef600f00 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4";
+ interrupt-parent = <&EMAC1>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC2 11 4
+ /*Wake*/ 1 &UIC2 15 4>;
+ reg = <ef600f00 70>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <1>;
+ mal-rx-channel = <8>;
+ cell-index = <1>;
+ max-frame-size = <2328>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <1>;
+ tah-device = <&TAH1>;
+ tah-channel = <1>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ mdio-device = <&EMAC0>;
+ };
+
+ EMAC2: ethernet@ef601100 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4";
+ interrupt-parent = <&EMAC2>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC2 12 4
+ /*Wake*/ 1 &UIC2 16 4>;
+ reg = <ef601100 70>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <2>;
+ mal-rx-channel = <10>;
+ cell-index = <2>;
+ max-frame-size = <2328>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000000>;
+ rgmii-device = <&RGMII1>;
+ rgmii-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ mdio-device = <&EMAC0>;
+ };
+
+ EMAC3: ethernet@ef601200 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4";
+ interrupt-parent = <&EMAC3>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC2 13 4
+ /*Wake*/ 1 &UIC2 17 4>;
+ reg = <ef601200 70>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <3>;
+ mal-rx-channel = <18>;
+ cell-index = <3>;
+ max-frame-size = <2328>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000000>;
+ rgmii-device = <&RGMII1>;
+ rgmii-channel = <1>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ mdio-device = <&EMAC0>;
+ };
+ };
+
+ PCIX0: pci@c0ec00000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
+ primary;
+ large-inbound-windows;
+ enable-msi-hole;
+ reg = <c 0ec00000 8 /* Config space access */
+ 0 0 0 /* no IACK cycles */
+ c 0ed00000 4 /* Special cycles */
+ c 0ec80000 100 /* Internal registers */
+ c 0ec80100 fc>; /* Internal messaging registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
+ 01000000 0 00000000 0000000c 08000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* This drives busses 0 to 0x3f */
+ bus-range = <0 3f>;
+
+ /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
+ interrupt-map-mask = <0000 0 0 0>;
+ interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
+ };
+
+ PCIE0: pciex@d00000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+ primary;
+ port = <0>; /* port number */
+ reg = <d 00000000 20000000 /* Config space access */
+ c 08010000 00001000>; /* Registers */
+ dcr-reg = <100 020>;
+ sdr-base = <300>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
+ 01000000 0 00000000 0000000f 80000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* This drives busses 40 to 0x7f */
+ bus-range = <40 7f>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
+ 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
+ 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
+ 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
+ };
+
+ PCIE1: pciex@d20000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+ primary;
+ port = <1>; /* port number */
+ reg = <d 20000000 20000000 /* Config space access */
+ c 08011000 00001000>; /* Registers */
+ dcr-reg = <120 020>;
+ sdr-base = <340>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
+ 01000000 0 00000000 0000000f 80010000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* This drives busses 80 to 0xbf */
+ bus-range = <80 bf>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
+ 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
+ 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
+ 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
+ };
+ };
+};
#address-cells = <1>;
#size-cells = <1>;
model = "amcc,haleakala";
- compatible = "amcc,kilauea";
+ compatible = "amcc,haleakala", "amcc,kilauea";
dcr-parent = <&/cpus/cpu@0>;
aliases {
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "gmii";
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
mal-tx-channel = <1>;
mal-rx-channel = <1>;
cell-index = <1>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
--- /dev/null
+/*
+ * Device Tree Source for Emerson KSI8560
+ *
+ * Author: Alexandr Smirnov <asmirnov@ru.mvista.com>
+ *
+ * Based on mpc8560ads.dts
+ *
+ * 2008 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ model = "KSI8560";
+ compatible = "emerson,KSI8560";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8560@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>; /* L1, 32K */
+ i-cache-size = <0x8000>; /* L1, 32K */
+ timebase-frequency = <0>; /* From U-boot */
+ bus-frequency = <0>; /* From U-boot */
+ clock-frequency = <0>; /* From U-boot */
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; /* Fixed by bootwrapper */
+ };
+
+ soc@fdf00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0x00000000 0xfdf00000 0x00100000>;
+ bus-frequency = <0>; /* Fixed by bootwrapper */
+
+ memory-controller@2000 {
+ compatible = "fsl,8540-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <0x12 0x2>;
+ };
+
+ l2-cache-controller@20000 {
+ compatible = "fsl,8540-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <0x20>; /* 32 bytes */
+ cache-size = <0x40000>; /* L2, 256K */
+ interrupt-parent = <&MPIC>;
+ interrupts = <0x10 0x2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <0x2b 0x2>;
+ interrupt-parent = <&MPIC>;
+ dfsrr;
+ };
+
+ mdio@24520 { /* For TSECs */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+
+ PHY1: ethernet-phy@1 {
+ interrupt-parent = <&MPIC>;
+ reg = <0x1>;
+ device_type = "ethernet-phy";
+ };
+
+ PHY2: ethernet-phy@2 {
+ interrupt-parent = <&MPIC>;
+ reg = <0x2>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet0: ethernet@24000 {
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ /* Mac address filled in by bootwrapper */
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
+ interrupt-parent = <&MPIC>;
+ phy-handle = <&PHY1>;
+ };
+
+ enet1: ethernet@25000 {
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ /* Mac address filled in by bootwrapper */
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
+ interrupt-parent = <&MPIC>;
+ phy-handle = <&PHY2>;
+ };
+
+ MPIC: pic@40000 {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0x40000 0x40000>;
+ device_type = "open-pic";
+ };
+
+ cpm@919c0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
+ reg = <0x919c0 0x30>;
+ ranges;
+
+ muram@80000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x10000>;
+
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0x0 0x4000 0x9000 0x2000>;
+ };
+ };
+
+ brg@919f0 {
+ compatible = "fsl,mpc8560-brg",
+ "fsl,cpm2-brg",
+ "fsl,cpm-brg";
+ reg = <0x919f0 0x10 0x915f0 0x10>;
+ clock-frequency = <165000000>; /* 166MHz */
+ };
+
+ CPMPIC: pic@90c00 {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <0x2e 0x2>;
+ interrupt-parent = <&MPIC>;
+ reg = <0x90c00 0x80>;
+ compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
+ };
+
+ serial@91a00 {
+ device_type = "serial";
+ compatible = "fsl,mpc8560-scc-uart",
+ "fsl,cpm2-scc-uart";
+ reg = <0x91a00 0x20 0x88000 0x100>;
+ fsl,cpm-brg = <1>;
+ fsl,cpm-command = <0x800000>;
+ current-speed = <0x1c200>;
+ interrupts = <0x28 0x8>;
+ interrupt-parent = <&CPMPIC>;
+ };
+
+ serial@91a20 {
+ device_type = "serial";
+ compatible = "fsl,mpc8560-scc-uart",
+ "fsl,cpm2-scc-uart";
+ reg = <0x91a20 0x20 0x88100 0x100>;
+ fsl,cpm-brg = <2>;
+ fsl,cpm-command = <0x4a00000>;
+ current-speed = <0x1c200>;
+ interrupts = <0x29 0x8>;
+ interrupt-parent = <&CPMPIC>;
+ };
+
+ mdio@90d00 { /* For FCCs */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,cpm2-mdio-bitbang";
+ reg = <0x90d00 0x14>;
+ fsl,mdio-pin = <24>;
+ fsl,mdc-pin = <25>;
+
+ PHY0: ethernet-phy@0 {
+ interrupt-parent = <&MPIC>;
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet2: ethernet@91300 {
+ device_type = "network";
+ compatible = "fsl,mpc8560-fcc-enet",
+ "fsl,cpm2-fcc-enet";
+ reg = <0x91300 0x20 0x88400 0x100 0x91390 0x1>;
+ /* Mac address filled in by bootwrapper */
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ fsl,cpm-command = <0x12000300>;
+ interrupts = <0x20 0x8>;
+ interrupt-parent = <&CPMPIC>;
+ phy-handle = <&PHY0>;
+ };
+ };
+ };
+
+ localbus@fdf05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8560-localbus";
+ reg = <0xfdf05000 0x68>;
+
+ ranges = <0x0 0x0 0xe0000000 0x00800000
+ 0x4 0x0 0xe8080000 0x00080000>;
+
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec-flash";
+ reg = <0x0 0x0 0x800000>;
+ bank-width = <0x2>;
+
+ partition@0 {
+ label = "Primary Kernel";
+ reg = <0x0 0x180000>;
+ };
+ partition@180000 {
+ label = "Primary Filesystem";
+ reg = <0x180000 0x580000>;
+ };
+ partition@700000 {
+ label = "Monitor";
+ reg = <0x300000 0x100000>;
+ read-only;
+ };
+ };
+
+ cpld@4,0 {
+ compatible = "emerson,KSI8560-cpld";
+ reg = <0x4 0x0 0x80000>;
+ };
+ };
+
+
+ chosen {
+ linux,stdout-path = "/soc/cpm/serial@91a00";
+ };
+};
* Based on sandpoint.dts
*
* 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright 2008 Freescale Semiconductor, Inc.
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
*/
+/dts-v1/;
+
/ {
model = "KuroboxHD";
compatible = "linkstation";
PowerPC,603e { /* Really 8241 */
device_type = "cpu";
- reg = <0>;
- clock-frequency = <bebc200>; /* Fixed by bootloader */
- timebase-frequency = <1743000>; /* Fixed by bootloader */
+ reg = <0x0>;
+ clock-frequency = <200000000>; /* Fixed by bootloader */
+ timebase-frequency = <24391680>; /* Fixed by bootloader */
bus-frequency = <0>; /* Fixed by bootloader */
/* Following required by dtc but not used */
- i-cache-size = <4000>;
- d-cache-size = <4000>;
+ i-cache-size = <0x4000>;
+ d-cache-size = <0x4000>;
};
};
memory {
device_type = "memory";
- reg = <00000000 04000000>;
+ reg = <0x0 0x4000000>;
};
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
- reg = <80000000 00100000>;
- ranges = <80000000 80000000 70000000 /* pci mem space */
- fc000000 fc000000 00100000 /* EUMB */
- fe000000 fe000000 00c00000 /* pci i/o space */
- fec00000 fec00000 00300000 /* pci cfg regs */
- fef00000 fef00000 00100000>; /* pci iack */
+ reg = <0x80000000 0x100000>;
+ ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
+ 0xfc000000 0xfc000000 0x100000 /* EUMB */
+ 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
+ 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
+ 0xfef00000 0xfef00000 0x100000>; /* pci iack */
i2c@80003000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <80003000 1000>;
+ reg = <0x80003000 0x1000>;
interrupts = <5 2>;
interrupt-parent = <&mpic>;
rtc@32 {
device_type = "rtc";
compatible = "ricoh,rs5c372a";
- reg = <32>;
+ reg = <0x32>;
};
};
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <80004500 8>;
- clock-frequency = <5d08d88>;
- current-speed = <2580>;
+ reg = <0x80004500 0x8>;
+ clock-frequency = <97553800>;
+ current-speed = <9600>;
interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <80004600 8>;
- clock-frequency = <5d08d88>;
- current-speed = <e100>;
- interrupts = <a 0>;
+ reg = <0x80004600 0x8>;
+ clock-frequency = <97553800>;
+ current-speed = <57600>;
+ interrupts = <10 0>;
interrupt-parent = <&mpic>;
};
device_type = "open-pic";
compatible = "chrp,open-pic";
interrupt-controller;
- reg = <80040000 40000>;
+ reg = <0x80040000 0x40000>;
};
pci0: pci@fec00000 {
#interrupt-cells = <1>;
device_type = "pci";
compatible = "mpc10x-pci";
- reg = <fec00000 400000>;
- ranges = <01000000 0 0 fe000000 0 00c00000
- 02000000 0 80000000 80000000 0 70000000>;
- bus-range = <0 ff>;
- clock-frequency = <7f28155>;
+ reg = <0xfec00000 0x400000>;
+ ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
+ 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
+ bus-range = <0 255>;
+ clock-frequency = <133333333>;
interrupt-parent = <&mpic>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 11 - IRQ0 ETH */
- 5800 0 0 1 &mpic 0 1
- 5800 0 0 2 &mpic 1 1
- 5800 0 0 3 &mpic 2 1
- 5800 0 0 4 &mpic 3 1
+ 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 12 - IRQ1 IDE0 */
- 6000 0 0 1 &mpic 1 1
- 6000 0 0 2 &mpic 2 1
- 6000 0 0 3 &mpic 3 1
- 6000 0 0 4 &mpic 0 1
+ 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 14 - IRQ3 USB2.0 */
- 7000 0 0 1 &mpic 3 1
- 7000 0 0 2 &mpic 3 1
- 7000 0 0 3 &mpic 3 1
- 7000 0 0 4 &mpic 3 1
+ 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
};
};
* Based on sandpoint.dts
*
* 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright 2008 Freescale Semiconductor, Inc.
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
*/
+/dts-v1/;
+
/ {
model = "KuroboxHG";
compatible = "linkstation";
PowerPC,603e { /* Really 8241 */
device_type = "cpu";
- reg = <0>;
- clock-frequency = <fdad680>; /* Fixed by bootloader */
- timebase-frequency = <1F04000>; /* Fixed by bootloader */
+ reg = <0x0>;
+ clock-frequency = <266000000>; /* Fixed by bootloader */
+ timebase-frequency = <32522240>; /* Fixed by bootloader */
bus-frequency = <0>; /* Fixed by bootloader */
/* Following required by dtc but not used */
- i-cache-size = <4000>;
- d-cache-size = <4000>;
+ i-cache-size = <0x4000>;
+ d-cache-size = <0x4000>;
};
};
memory {
device_type = "memory";
- reg = <00000000 08000000>;
+ reg = <0x0 0x8000000>;
};
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
- reg = <80000000 00100000>;
- ranges = <80000000 80000000 70000000 /* pci mem space */
- fc000000 fc000000 00100000 /* EUMB */
- fe000000 fe000000 00c00000 /* pci i/o space */
- fec00000 fec00000 00300000 /* pci cfg regs */
- fef00000 fef00000 00100000>; /* pci iack */
+ reg = <0x80000000 0x100000>;
+ ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
+ 0xfc000000 0xfc000000 0x100000 /* EUMB */
+ 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
+ 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
+ 0xfef00000 0xfef00000 0x100000>; /* pci iack */
i2c@80003000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <80003000 1000>;
+ reg = <0x80003000 0x1000>;
interrupts = <5 2>;
interrupt-parent = <&mpic>;
rtc@32 {
device_type = "rtc";
compatible = "ricoh,rs5c372a";
- reg = <32>;
+ reg = <0x32>;
};
};
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <80004500 8>;
- clock-frequency = <7c044a8>;
- current-speed = <2580>;
+ reg = <0x80004500 0x8>;
+ clock-frequency = <130041000>;
+ current-speed = <9600>;
interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <80004600 8>;
- clock-frequency = <7c044a8>;
- current-speed = <e100>;
- interrupts = <a 0>;
+ reg = <0x80004600 0x8>;
+ clock-frequency = <130041000>;
+ current-speed = <57600>;
+ interrupts = <10 0>;
interrupt-parent = <&mpic>;
};
device_type = "open-pic";
compatible = "chrp,open-pic";
interrupt-controller;
- reg = <80040000 40000>;
+ reg = <0x80040000 0x40000>;
};
pci0: pci@fec00000 {
#interrupt-cells = <1>;
device_type = "pci";
compatible = "mpc10x-pci";
- reg = <fec00000 400000>;
- ranges = <01000000 0 0 fe000000 0 00c00000
- 02000000 0 80000000 80000000 0 70000000>;
- bus-range = <0 ff>;
- clock-frequency = <7f28155>;
+ reg = <0xfec00000 0x400000>;
+ ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
+ 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
+ bus-range = <0 255>;
+ clock-frequency = <133333333>;
interrupt-parent = <&mpic>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 11 - IRQ0 ETH */
- 5800 0 0 1 &mpic 0 1
- 5800 0 0 2 &mpic 1 1
- 5800 0 0 3 &mpic 2 1
- 5800 0 0 4 &mpic 3 1
+ 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 12 - IRQ1 IDE0 */
- 6000 0 0 1 &mpic 1 1
- 6000 0 0 2 &mpic 2 1
- 6000 0 0 3 &mpic 3 1
- 6000 0 0 4 &mpic 0 1
+ 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 14 - IRQ3 USB2.0 */
- 7000 0 0 1 &mpic 3 1
- 7000 0 0 2 &mpic 3 1
- 7000 0 0 3 &mpic 3 1
- 7000 0 0 4 &mpic 3 1
+ 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
};
};
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
mal-tx-channel = <1>;
mal-rx-channel = <1>;
cell-index = <1>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
/*
* MPC7448HPC2 (Taiga) board Device Tree Source
*
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
* 2006 Roy Zang <Roy Zang at freescale.com>.
*
* This program is free software; you can redistribute it and/or modify it
* option) any later version.
*/
+/dts-v1/;
/ {
model = "mpc7448hpc2";
PowerPC,7448@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K bytes
- i-cache-size = <8000>; // L1, 32K bytes
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K bytes
+ i-cache-size = <0x8000>; // L1, 32K bytes
timebase-frequency = <0>; // 33 MHz, from uboot
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
memory {
device_type = "memory";
- reg = <00000000 20000000 // DDR2 512M at 0
+ reg = <0x0 0x20000000 // DDR2 512M at 0
>;
};
#address-cells = <1>;
#size-cells = <1>;
device_type = "tsi-bridge";
- ranges = <00000000 c0000000 00010000>;
- reg = <c0000000 00010000>;
+ ranges = <0x0 0xc0000000 0x10000>;
+ reg = <0xc0000000 0x10000>;
bus-frequency = <0>;
i2c@7000 {
interrupt-parent = <&mpic>;
- interrupts = <E 0>;
- reg = <7000 400>;
+ interrupts = <14 0>;
+ reg = <0x7000 0x400>;
device_type = "i2c";
compatible = "tsi108-i2c";
};
MDIO: mdio@6000 {
device_type = "mdio";
compatible = "tsi108-mdio";
- reg = <6000 50>;
+ reg = <0x6000 0x50>;
#address-cells = <1>;
#size-cells = <0>;
phy8: ethernet-phy@8 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
- reg = <8>;
+ reg = <0x8>;
};
phy9: ethernet-phy@9 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
- reg = <9>;
+ reg = <0x9>;
};
};
#size-cells = <0>;
device_type = "network";
compatible = "tsi108-ethernet";
- reg = <6000 200>;
+ reg = <0x6000 0x200>;
address = [ 00 06 D2 00 00 01 ];
- interrupts = <10 2>;
+ interrupts = <16 2>;
interrupt-parent = <&mpic>;
mdio-handle = <&MDIO>;
phy-handle = <&phy8>;
#size-cells = <0>;
device_type = "network";
compatible = "tsi108-ethernet";
- reg = <6400 200>;
+ reg = <0x6400 0x200>;
address = [ 00 06 D2 00 00 02 ];
- interrupts = <11 2>;
+ interrupts = <17 2>;
interrupt-parent = <&mpic>;
mdio-handle = <&MDIO>;
phy-handle = <&phy9>;
serial@7808 {
device_type = "serial";
compatible = "ns16550";
- reg = <7808 200>;
- clock-frequency = <3f6b5a00>;
- interrupts = <c 0>;
+ reg = <0x7808 0x200>;
+ clock-frequency = <1064000000>;
+ interrupts = <12 0>;
interrupt-parent = <&mpic>;
};
serial@7c08 {
device_type = "serial";
compatible = "ns16550";
- reg = <7c08 200>;
- clock-frequency = <3f6b5a00>;
- interrupts = <d 0>;
+ reg = <0x7c08 0x200>;
+ clock-frequency = <1064000000>;
+ interrupts = <13 0>;
interrupt-parent = <&mpic>;
};
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <7400 400>;
+ reg = <0x7400 0x400>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <1000 1000>;
+ reg = <0x1000 0x1000>;
bus-range = <0 0>;
- ranges = <02000000 0 e0000000 e0000000 0 1A000000
- 01000000 0 00000000 fa000000 0 00010000>;
- clock-frequency = <7f28154>;
+ ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000
+ 0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
+ clock-frequency = <133333332>;
interrupt-parent = <&mpic>;
- interrupts = <17 2>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupts = <23 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 */
- 0800 0 0 1 &RT0 24 0
- 0800 0 0 2 &RT0 25 0
- 0800 0 0 3 &RT0 26 0
- 0800 0 0 4 &RT0 27 0
+ 0x800 0x0 0x0 0x1 &RT0 0x24 0x0
+ 0x800 0x0 0x0 0x2 &RT0 0x25 0x0
+ 0x800 0x0 0x0 0x3 &RT0 0x26 0x0
+ 0x800 0x0 0x0 0x4 &RT0 0x27 0x0
/* IDSEL 0x12 */
- 1000 0 0 1 &RT0 25 0
- 1000 0 0 2 &RT0 26 0
- 1000 0 0 3 &RT0 27 0
- 1000 0 0 4 &RT0 24 0
+ 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
+ 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
+ 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
+ 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
/* IDSEL 0x13 */
- 1800 0 0 1 &RT0 26 0
- 1800 0 0 2 &RT0 27 0
- 1800 0 0 3 &RT0 24 0
- 1800 0 0 4 &RT0 25 0
+ 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
+ 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
+ 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
+ 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
/* IDSEL 0x14 */
- 2000 0 0 1 &RT0 27 0
- 2000 0 0 2 &RT0 24 0
- 2000 0 0 3 &RT0 25 0
- 2000 0 0 4 &RT0 26 0
+ 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
+ 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
+ 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
+ 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
>;
RT0: router@1180 {
#address-cells = <0>;
#interrupt-cells = <2>;
big-endian;
- interrupts = <17 2>;
+ interrupts = <23 2>;
interrupt-parent = <&mpic>;
};
};
/*
* MPC8272 ADS Device Tree Source
*
- * Copyright 2005 Freescale Semiconductor Inc.
+ * Copyright 2005,2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
+
/ {
model = "MPC8272ADS";
compatible = "fsl,mpc8272ads";
PowerPC,8272@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <d#32>;
- i-cache-line-size = <d#32>;
- d-cache-size = <d#16384>;
- i-cache-size = <d#16384>;
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <16384>;
+ i-cache-size = <16384>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
memory {
device_type = "memory";
- reg = <0 0>;
+ reg = <0x0 0x0>;
};
localbus@f0010100 {
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
- reg = <f0010100 40>;
+ reg = <0xf0010100 0x40>;
- ranges = <0 0 fe000000 02000000
- 1 0 f4500000 00008000
- 3 0 f8200000 00008000>;
+ ranges = <0x0 0x0 0xfe000000 0x2000000
+ 0x1 0x0 0xf4500000 0x8000
+ 0x3 0x0 0xf8200000 0x8000>;
flash@0,0 {
compatible = "jedec-flash";
- reg = <0 0 2000000>;
+ reg = <0x0 0x0 0x2000000>;
bank-width = <4>;
device-width = <1>;
};
board-control@1,0 {
- reg = <1 0 20>;
+ reg = <0x1 0x0 0x20>;
compatible = "fsl,mpc8272ads-bcsr";
};
"fsl,pq2ads-pci-pic";
#interrupt-cells = <1>;
interrupt-controller;
- reg = <3 0 8>;
+ reg = <0x3 0x0 0x8>;
interrupt-parent = <&PIC>;
- interrupts = <14 8>;
+ interrupts = <20 8>;
};
};
pci@f0010800 {
device_type = "pci";
- reg = <f0010800 10c f00101ac 8 f00101c4 8>;
+ reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- clock-frequency = <d#66666666>;
- interrupt-map-mask = <f800 0 0 7>;
+ clock-frequency = <66666666>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x16 */
- b000 0 0 1 &PCI_PIC 0
- b000 0 0 2 &PCI_PIC 1
- b000 0 0 3 &PCI_PIC 2
- b000 0 0 4 &PCI_PIC 3
+ 0xb000 0x0 0x0 0x1 &PCI_PIC 0
+ 0xb000 0x0 0x0 0x2 &PCI_PIC 1
+ 0xb000 0x0 0x0 0x3 &PCI_PIC 2
+ 0xb000 0x0 0x0 0x4 &PCI_PIC 3
/* IDSEL 0x17 */
- b800 0 0 1 &PCI_PIC 4
- b800 0 0 2 &PCI_PIC 5
- b800 0 0 3 &PCI_PIC 6
- b800 0 0 4 &PCI_PIC 7
+ 0xb800 0x0 0x0 0x1 &PCI_PIC 4
+ 0xb800 0x0 0x0 0x2 &PCI_PIC 5
+ 0xb800 0x0 0x0 0x3 &PCI_PIC 6
+ 0xb800 0x0 0x0 0x4 &PCI_PIC 7
/* IDSEL 0x18 */
- c000 0 0 1 &PCI_PIC 8
- c000 0 0 2 &PCI_PIC 9
- c000 0 0 3 &PCI_PIC a
- c000 0 0 4 &PCI_PIC b>;
+ 0xc000 0x0 0x0 0x1 &PCI_PIC 8
+ 0xc000 0x0 0x0 0x2 &PCI_PIC 9
+ 0xc000 0x0 0x0 0x3 &PCI_PIC 10
+ 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
interrupt-parent = <&PIC>;
- interrupts = <12 8>;
- ranges = <42000000 0 80000000 80000000 0 20000000
- 02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 f6000000 0 02000000>;
+ interrupts = <18 8>;
+ ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
};
soc@f0000000 {
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8272", "fsl,pq2-soc";
- ranges = <00000000 f0000000 00053000>;
+ ranges = <0x0 0xf0000000 0x53000>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
- reg = <f0000000 00053000>;
+ reg = <0xf0000000 0x53000>;
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
- reg = <119c0 30>;
+ reg = <0x119c0 0x30>;
ranges;
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0 10000>;
+ ranges = <0x0 0x0 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
- reg = <0 2000 9800 800>;
+ reg = <0x0 0x2000 0x9800 0x800>;
};
};
compatible = "fsl,mpc8272-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
- reg = <119f0 10 115f0 10>;
+ reg = <0x119f0 0x10 0x115f0 0x10>;
};
serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
- reg = <11a00 20 8000 100>;
- interrupts = <28 8>;
+ reg = <0x11a00 0x20 0x8000 0x100>;
+ interrupts = <40 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
- fsl,cpm-command = <00800000>;
+ fsl,cpm-command = <0x800000>;
};
serial@11a60 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
- reg = <11a60 20 8300 100>;
- interrupts = <2b 8>;
+ reg = <0x11a60 0x20 0x8300 0x100>;
+ interrupts = <43 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <4>;
- fsl,cpm-command = <0ce00000>;
+ fsl,cpm-command = <0xce00000>;
};
mdio@10d40 {
compatible = "fsl,mpc8272ads-mdio-bitbang",
"fsl,mpc8272-mdio-bitbang",
"fsl,cpm2-mdio-bitbang";
- reg = <10d40 14>;
+ reg = <0x10d40 0x14>;
#address-cells = <1>;
#size-cells = <0>;
- fsl,mdio-pin = <12>;
- fsl,mdc-pin = <13>;
+ fsl,mdio-pin = <18>;
+ fsl,mdc-pin = <19>;
PHY0: ethernet-phy@0 {
interrupt-parent = <&PIC>;
- interrupts = <17 8>;
- reg = <0>;
+ interrupts = <23 8>;
+ reg = <0x0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
interrupt-parent = <&PIC>;
- interrupts = <17 8>;
- reg = <3>;
+ interrupts = <23 8>;
+ reg = <0x3>;
device_type = "ethernet-phy";
};
};
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
- reg = <11300 20 8400 100 11390 1>;
+ reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <20 8>;
+ interrupts = <32 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
- fsl,cpm-command = <12000300>;
+ fsl,cpm-command = <0x12000300>;
};
ethernet@11320 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
- reg = <11320 20 8500 100 113b0 1>;
+ reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <21 8>;
+ interrupts = <33 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
- fsl,cpm-command = <16200300>;
+ fsl,cpm-command = <0x16200300>;
};
};
PIC: interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
- reg = <10c00 80>;
+ reg = <0x10c00 0x80>;
compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
};
"fsl,talitos-sec2",
"fsl,talitos",
"talitos";
- reg = <30000 10000>;
- interrupts = <b 8>;
+ reg = <0x30000 0x10000>;
+ interrupts = <11 8>;
interrupt-parent = <&PIC>;
num-channels = <4>;
- channel-fifo-len = <18>;
- exec-units-mask = <0000007e>;
+ channel-fifo-len = <24>;
+ exec-units-mask = <0x7e>;
/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
- descriptor-types-mask = <01010ebf>;
+ descriptor-types-mask = <0x1010ebf>;
};
};
enet0: ucc@2200 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
cell-index = <3>;
- device-id = <3>;
reg = <0x2200 0x200>;
interrupts = <34>;
interrupt-parent = <&qeic>;
enet1: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
cell-index = <4>;
- device-id = <4>;
reg = <0x3200 0x200>;
interrupts = <35>;
interrupt-parent = <&qeic>;
ucc@2400 {
device_type = "serial";
compatible = "ucc_uart";
- model = "UCC";
- device-id = <5>; /* The UCC number, 1-7*/
+ cell-index = <5>; /* The UCC number, 1-7*/
port-number = <0>; /* Which ttyQEx device */
soft-uart; /* We need Soft-UART */
reg = <0x2400 0x200>;
enet0: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
cell-index = <2>;
- device-id = <2>;
reg = <0x3000 0x200>;
interrupts = <33>;
interrupt-parent = <&qeic>;
enet1: ucc@2200 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
cell-index = <3>;
- device-id = <3>;
reg = <0x2200 0x200>;
interrupts = <34>;
interrupt-parent = <&qeic>;
enet0: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
cell-index = <1>;
- device-id = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
enet1: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
cell-index = <2>;
- device-id = <2>;
reg = <0x3000 0x200>;
interrupts = <33>;
interrupt-parent = <&qeic>;
/*
* MPC8540 ADS Device Tree Source
*
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
/ {
model = "MPC8540ADS";
PowerPC,8540@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
memory {
device_type = "memory";
- reg = <00000000 08000000>; // 128M at 0x0
+ reg = <0x0 0x8000000>; // 128M at 0x0
};
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <0 e0000000 00100000>;
- reg = <e0000000 00100000>; // CCSRBAR 1M
+ ranges = <0x0 0xe0000000 0x100000>;
+ reg = <0xe0000000 0x100000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
- reg = <2000 1000>;
+ reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <40000>; // L2, 256K
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
- interrupts = <10 2>;
+ interrupts = <16 2>;
};
i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <3000 100>;
- interrupts = <2b 2>;
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
- reg = <24520 20>;
+ reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <0>;
+ reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <1>;
+ reg = <0x1>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <7 1>;
- reg = <3>;
+ reg = <0x3>;
device_type = "ethernet-phy";
};
};
device_type = "network";
model = "TSEC";
compatible = "gianfar";
- reg = <24000 1000>;
+ reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1d 2 1e 2 22 2>;
+ interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
device_type = "network";
model = "TSEC";
compatible = "gianfar";
- reg = <25000 1000>;
+ reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <23 2 24 2 28 2>;
+ interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
device_type = "network";
model = "FEC";
compatible = "gianfar";
- reg = <26000 1000>;
+ reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <29 2>;
+ interrupts = <41 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
};
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <4500 100>; // reg base, size
+ reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <4600 100>; // reg base, size
+ reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
pci0: pci@e0008000 {
cell-index = <0>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x02 */
- 1000 0 0 1 &mpic 1 1
- 1000 0 0 2 &mpic 2 1
- 1000 0 0 3 &mpic 3 1
- 1000 0 0 4 &mpic 4 1
+ 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x03 */
- 1800 0 0 1 &mpic 4 1
- 1800 0 0 2 &mpic 1 1
- 1800 0 0 3 &mpic 2 1
- 1800 0 0 4 &mpic 3 1
+ 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x04 */
- 2000 0 0 1 &mpic 3 1
- 2000 0 0 2 &mpic 4 1
- 2000 0 0 3 &mpic 1 1
- 2000 0 0 4 &mpic 2 1
+ 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x05 */
- 2800 0 0 1 &mpic 2 1
- 2800 0 0 2 &mpic 3 1
- 2800 0 0 3 &mpic 4 1
- 2800 0 0 4 &mpic 1 1
+ 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x0c */
- 6000 0 0 1 &mpic 1 1
- 6000 0 0 2 &mpic 2 1
- 6000 0 0 3 &mpic 3 1
- 6000 0 0 4 &mpic 4 1
+ 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x0d */
- 6800 0 0 1 &mpic 4 1
- 6800 0 0 2 &mpic 1 1
- 6800 0 0 3 &mpic 2 1
- 6800 0 0 4 &mpic 3 1
+ 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x0e */
- 7000 0 0 1 &mpic 3 1
- 7000 0 0 2 &mpic 4 1
- 7000 0 0 3 &mpic 1 1
- 7000 0 0 4 &mpic 2 1
+ 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x0f */
- 7800 0 0 1 &mpic 2 1
- 7800 0 0 2 &mpic 3 1
- 7800 0 0 3 &mpic 4 1
- 7800 0 0 4 &mpic 1 1
+ 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 */
- 9000 0 0 1 &mpic 1 1
- 9000 0 0 2 &mpic 2 1
- 9000 0 0 3 &mpic 3 1
- 9000 0 0 4 &mpic 4 1
+ 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x13 */
- 9800 0 0 1 &mpic 4 1
- 9800 0 0 2 &mpic 1 1
- 9800 0 0 3 &mpic 2 1
- 9800 0 0 4 &mpic 3 1
+ 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x14 */
- a000 0 0 1 &mpic 3 1
- a000 0 0 2 &mpic 4 1
- a000 0 0 3 &mpic 1 1
- a000 0 0 4 &mpic 2 1
+ 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x15 */
- a800 0 0 1 &mpic 2 1
- a800 0 0 2 &mpic 3 1
- a800 0 0 3 &mpic 4 1
- a800 0 0 4 &mpic 1 1>;
+ 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <18 2>;
+ interrupts = <24 2>;
bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0008000 1000>;
+ reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
};
/*
* MPC8541 CDS Device Tree Source
*
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
/ {
model = "MPC8541CDS";
PowerPC,8541@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
memory {
device_type = "memory";
- reg = <00000000 08000000>; // 128M at 0x0
+ reg = <0x0 0x8000000>; // 128M at 0x0
};
soc8541@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <0 e0000000 00100000>;
- reg = <e0000000 00001000>; // CCSRBAR 1M
+ ranges = <0x0 0xe0000000 0x100000>;
+ reg = <0xe0000000 0x1000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8541-memory-controller";
- reg = <2000 1000>;
+ reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8541-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <40000>; // L2, 256K
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
- interrupts = <10 2>;
+ interrupts = <16 2>;
};
i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <3000 100>;
- interrupts = <2b 2>;
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
- reg = <24520 20>;
+ reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <0>;
+ reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <1>;
+ reg = <0x1>;
device_type = "ethernet-phy";
};
};
device_type = "network";
model = "TSEC";
compatible = "gianfar";
- reg = <24000 1000>;
+ reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1d 2 1e 2 22 2>;
+ interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
device_type = "network";
model = "TSEC";
compatible = "gianfar";
- reg = <25000 1000>;
+ reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <23 2 24 2 28 2>;
+ interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <4500 100>; // reg base, size
+ reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <4600 100>; // reg base, size
+ reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
- reg = <919c0 30>;
+ reg = <0x919c0 0x30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 80000 10000>;
+ ranges = <0x0 0x80000 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
- reg = <0 2000 9000 1000>;
+ reg = <0x0 0x2000 0x9000 0x1000>;
};
};
compatible = "fsl,mpc8541-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
- reg = <919f0 10 915f0 10>;
+ reg = <0x919f0 0x10 0x915f0 0x10>;
};
cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- interrupts = <2e 2>;
+ interrupts = <46 2>;
interrupt-parent = <&mpic>;
- reg = <90c00 80>;
+ reg = <0x90c00 0x80>;
compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
};
};
pci0: pci@e0008000 {
cell-index = <0>;
- interrupt-map-mask = <1f800 0 0 7>;
+ interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x10 */
- 08000 0 0 1 &mpic 0 1
- 08000 0 0 2 &mpic 1 1
- 08000 0 0 3 &mpic 2 1
- 08000 0 0 4 &mpic 3 1
+ 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x11 */
- 08800 0 0 1 &mpic 0 1
- 08800 0 0 2 &mpic 1 1
- 08800 0 0 3 &mpic 2 1
- 08800 0 0 4 &mpic 3 1
+ 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 &mpic 0 1
- 09000 0 0 2 &mpic 1 1
- 09000 0 0 3 &mpic 2 1
- 09000 0 0 4 &mpic 3 1
+ 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 &mpic 1 1
- 09800 0 0 2 &mpic 2 1
- 09800 0 0 3 &mpic 3 1
- 09800 0 0 4 &mpic 0 1
+ 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 &mpic 2 1
- 0a000 0 0 2 &mpic 3 1
- 0a000 0 0 3 &mpic 0 1
- 0a000 0 0 4 &mpic 1 1
+ 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+ 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 &mpic 3 1
- 0a800 0 0 2 &mpic 0 1
- 0a800 0 0 3 &mpic 1 1
- 0a800 0 0 4 &mpic 2 1
+ 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 &mpic 0 1
- 19000 0 0 2 &mpic 1 1
- 19000 0 0 3 &mpic 2 1
- 19000 0 0 4 &mpic 3 1>;
+ 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <18 2>;
+ interrupts = <24 2>;
bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0008000 1000>;
+ reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
i8259@19000 {
interrupt-controller;
device_type = "interrupt-controller";
- reg = <19000 0 0 0 1>;
+ reg = <0x19000 0x0 0x0 0x0 0x1>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
pci1: pci@e0009000 {
cell-index = <1>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
- a800 0 0 1 &mpic b 1
- a800 0 0 2 &mpic b 1
- a800 0 0 3 &mpic b 1
- a800 0 0 4 &mpic b 1>;
+ 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <19 2>;
+ interrupts = <25 2>;
bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
- clock-frequency = <3f940aa>;
+ ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0009000 1000>;
+ reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
/*
* MPC8544 DS Device Tree Source
*
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
/ {
model = "MPC8544DS";
compatible = "MPC8544DS", "MPC85xxDS";
};
cpus {
- #cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8544@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
memory {
device_type = "memory";
- reg = <00000000 00000000>; // Filled by U-Boot
+ reg = <0x0 0x0>; // Filled by U-Boot
};
soc8544@e0000000 {
#size-cells = <1>;
device_type = "soc";
- ranges = <00000000 e0000000 00100000>;
- reg = <e0000000 00001000>; // CCSRBAR 1M
+ ranges = <0x0 0xe0000000 0x100000>;
+ reg = <0xe0000000 0x1000>; // CCSRBAR 1M
bus-frequency = <0>; // Filled out by uboot.
memory-controller@2000 {
compatible = "fsl,8544-memory-controller";
- reg = <2000 1000>;
+ reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8544-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <40000>; // L2, 256K
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
- interrupts = <10 2>;
+ interrupts = <16 2>;
};
i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <3000 100>;
- interrupts = <2b 2>;
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
- reg = <3100 100>;
- interrupts = <2b 2>;
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
- reg = <24520 20>;
+ reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
- interrupts = <a 1>;
- reg = <0>;
+ interrupts = <10 1>;
+ reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
- interrupts = <a 1>;
- reg = <1>;
+ interrupts = <10 1>;
+ reg = <0x1>;
device_type = "ethernet-phy";
};
};
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8544-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8544-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8544-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8544-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
enet0: ethernet@24000 {
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
- reg = <24000 1000>;
+ reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1d 2 1e 2 22 2>;
+ interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
device_type = "network";
model = "TSEC";
compatible = "gianfar";
- reg = <26000 1000>;
+ reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1f 2 20 2 21 2>;
+ interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <4500 100>;
+ reg = <0x4500 0x100>;
clock-frequency = <0>;
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <4600 100>;
+ reg = <0x4600 0x100>;
clock-frequency = <0>;
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8548-guts";
- reg = <e0000 1000>;
+ reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
cell-index = <0>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 J17 Slot 1 */
- 8800 0 0 1 &mpic 2 1
- 8800 0 0 2 &mpic 3 1
- 8800 0 0 3 &mpic 4 1
- 8800 0 0 4 &mpic 1 1
+ 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 J16 Slot 2 */
- 9000 0 0 1 &mpic 3 1
- 9000 0 0 2 &mpic 4 1
- 9000 0 0 3 &mpic 2 1
- 9000 0 0 4 &mpic 1 1>;
+ 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 c0000000 c0000000 0 20000000
- 01000000 0 00000000 e1000000 0 00010000>;
- clock-frequency = <3f940aa>;
+ interrupts = <24 2>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0008000 1000>;
+ reg = <0xe0008000 0x1000>;
};
pci1: pcie@e0009000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0009000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e1010000 0 00010000>;
- clock-frequency = <1fca055>;
+ reg = <0xe0009000 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
+ clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupts = <26 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
- 0000 0 0 1 &mpic 4 1
- 0000 0 0 2 &mpic 5 1
- 0000 0 0 3 &mpic 6 1
- 0000 0 0 4 &mpic 7 1
+ 0000 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x5 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x6 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- ranges = <02000000 0 80000000
- 02000000 0 80000000
- 0 20000000
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00010000>;
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
};
};
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e000a000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 e1020000 0 00010000>;
- clock-frequency = <1fca055>;
+ reg = <0xe000a000 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+ 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
+ clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupts = <25 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
- 0000 0 0 1 &mpic 0 1
- 0000 0 0 2 &mpic 1 1
- 0000 0 0 3 &mpic 2 1
- 0000 0 0 4 &mpic 3 1
+ 0000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- ranges = <02000000 0 a0000000
- 02000000 0 a0000000
- 0 10000000
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x10000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00010000>;
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
};
};
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e000b000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 b0000000 b0000000 0 00100000
- 01000000 0 00000000 b0100000 0 00100000>;
- clock-frequency = <1fca055>;
+ reg = <0xe000b000 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
+ 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
+ clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
- interrupts = <1b 2>;
- interrupt-map-mask = <ff00 0 0 1>;
+ interrupts = <27 2>;
+ interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
interrupt-map = <
// IDSEL 0x1c USB
- e000 0 0 1 &i8259 c 2
- e100 0 0 2 &i8259 9 2
- e200 0 0 3 &i8259 a 2
- e300 0 0 4 &i8259 b 2
+ 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+ 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+ 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+ 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
// IDSEL 0x1d Audio
- e800 0 0 1 &i8259 6 2
+ 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
// IDSEL 0x1e Legacy
- f000 0 0 1 &i8259 7 2
- f100 0 0 1 &i8259 7 2
+ 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+ 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
// IDSEL 0x1f IDE/SATA
- f800 0 0 1 &i8259 e 2
- f900 0 0 1 &i8259 5 2
+ 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+ 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
>;
pcie@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- ranges = <02000000 0 b0000000
- 02000000 0 b0000000
- 0 00100000
+ ranges = <0x2000000 0x0 0xb0000000
+ 0x2000000 0x0 0xb0000000
+ 0x0 0x100000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00100000>;
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
uli1575@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
- ranges = <02000000 0 b0000000
- 02000000 0 b0000000
- 0 00100000
+ ranges = <0x2000000 0x0 0xb0000000
+ 0x2000000 0x0 0xb0000000
+ 0x0 0x100000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00100000>;
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
- reg = <f000 0 0 0 0>;
- ranges = <1 0
- 01000000 0 0
- 00001000>;
+ reg = <0xf000 0x0 0x0 0x0 0x0>;
+ ranges = <0x1 0x0
+ 0x1000000 0x0 0x0
+ 0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
- reg = <1 20 2
- 1 a0 2
- 1 4d0 2>;
+ reg = <0x1 0x20 0x2
+ 0x1 0xa0 0x2
+ 0x1 0x4d0 0x2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
- reg = <1 60 1 1 64 1>;
- interrupts = <1 3 c 3>;
+ reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+ interrupts = <1 3 12 3>;
interrupt-parent = <&i8259>;
keyboard@0 {
- reg = <0>;
+ reg = <0x0>;
compatible = "pnpPNP,303";
};
mouse@1 {
- reg = <1>;
+ reg = <0x1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible = "pnpPNP,b00";
- reg = <1 70 2>;
+ reg = <0x1 0x70 0x2>;
};
gpio@400 {
- reg = <1 400 80>;
+ reg = <0x1 0x400 0x80>;
};
};
};
/*
* MPC8548 CDS Device Tree Source
*
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
/ {
model = "MPC8548CDS";
PowerPC,8548@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
memory {
device_type = "memory";
- reg = <00000000 08000000>; // 128M at 0x0
+ reg = <0x0 0x8000000>; // 128M at 0x0
};
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <00000000 e0000000 00100000>;
- reg = <e0000000 00001000>; // CCSRBAR
+ ranges = <0x0 0xe0000000 0x100000>;
+ reg = <0xe0000000 0x1000>; // CCSRBAR
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8548-memory-controller";
- reg = <2000 1000>;
+ reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <80000>; // L2, 512K
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
- interrupts = <10 2>;
+ interrupts = <16 2>;
};
i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <3000 100>;
- interrupts = <2b 2>;
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
- reg = <3100 100>;
- interrupts = <2b 2>;
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
- reg = <24520 20>;
+ reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <0>;
+ reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <1>;
+ reg = <0x1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <2>;
+ reg = <0x2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <3>;
+ reg = <0x3>;
device_type = "ethernet-phy";
};
};
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <24000 1000>;
+ reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1d 2 1e 2 22 2>;
+ interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <25000 1000>;
+ reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <23 2 24 2 28 2>;
+ interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <26000 1000>;
+ reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1f 2 20 2 21 2>;
+ interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
};
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <27000 1000>;
+ reg = <0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <25 2 26 2 27 2>;
+ interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
};
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <4500 100>; // reg base, size
+ reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <4600 100>; // reg base, size
+ reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities reg
compatible = "fsl,mpc8548-guts";
- reg = <e0000 1000>;
+ reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
pci0: pci@e0008000 {
cell-index = <0>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */
- 02000 0 0 1 &mpic 0 1
- 02000 0 0 2 &mpic 1 1
- 02000 0 0 3 &mpic 2 1
- 02000 0 0 4 &mpic 3 1
+ 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x5 (PCIX Slot 3) */
- 02800 0 0 1 &mpic 1 1
- 02800 0 0 2 &mpic 2 1
- 02800 0 0 3 &mpic 3 1
- 02800 0 0 4 &mpic 0 1
+ 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x6 (PCIX Slot 4) */
- 03000 0 0 1 &mpic 2 1
- 03000 0 0 2 &mpic 3 1
- 03000 0 0 3 &mpic 0 1
- 03000 0 0 4 &mpic 1 1
+ 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
+ 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x8 (PCIX Slot 5) */
- 04000 0 0 1 &mpic 0 1
- 04000 0 0 2 &mpic 1 1
- 04000 0 0 3 &mpic 2 1
- 04000 0 0 4 &mpic 3 1
+ 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0xC (Tsi310 bridge) */
- 06000 0 0 1 &mpic 0 1
- 06000 0 0 2 &mpic 1 1
- 06000 0 0 3 &mpic 2 1
- 06000 0 0 4 &mpic 3 1
+ 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x14 (Slot 2) */
- 0a000 0 0 1 &mpic 0 1
- 0a000 0 0 2 &mpic 1 1
- 0a000 0 0 3 &mpic 2 1
- 0a000 0 0 4 &mpic 3 1
+ 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x15 (Slot 3) */
- 0a800 0 0 1 &mpic 1 1
- 0a800 0 0 2 &mpic 2 1
- 0a800 0 0 3 &mpic 3 1
- 0a800 0 0 4 &mpic 0 1
+ 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x16 (Slot 4) */
- 0b000 0 0 1 &mpic 2 1
- 0b000 0 0 2 &mpic 3 1
- 0b000 0 0 3 &mpic 0 1
- 0b000 0 0 4 &mpic 1 1
+ 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
+ 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x18 (Slot 5) */
- 0c000 0 0 1 &mpic 0 1
- 0c000 0 0 2 &mpic 1 1
- 0c000 0 0 3 &mpic 2 1
- 0c000 0 0 4 &mpic 3 1
+ 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
- 0E000 0 0 1 &mpic 0 1
- 0E000 0 0 2 &mpic 1 1
- 0E000 0 0 3 &mpic 2 1
- 0E000 0 0 4 &mpic 3 1>;
+ 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <18 2>;
+ interrupts = <24 2>;
bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00800000>;
- clock-frequency = <3f940aa>;
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+ 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0008000 1000>;
+ reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
pci_bridge@1c {
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x00 (PrPMC Site) */
- 0000 0 0 1 &mpic 0 1
- 0000 0 0 2 &mpic 1 1
- 0000 0 0 3 &mpic 2 1
- 0000 0 0 4 &mpic 3 1
+ 0000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x04 (VIA chip) */
- 2000 0 0 1 &mpic 0 1
- 2000 0 0 2 &mpic 1 1
- 2000 0 0 3 &mpic 2 1
- 2000 0 0 4 &mpic 3 1
+ 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x05 (8139) */
- 2800 0 0 1 &mpic 1 1
+ 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
/* IDSEL 0x06 (Slot 6) */
- 3000 0 0 1 &mpic 2 1
- 3000 0 0 2 &mpic 3 1
- 3000 0 0 3 &mpic 0 1
- 3000 0 0 4 &mpic 1 1
+ 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
+ 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDESL 0x07 (Slot 7) */
- 3800 0 0 1 &mpic 3 1
- 3800 0 0 2 &mpic 0 1
- 3800 0 0 3 &mpic 1 1
- 3800 0 0 4 &mpic 2 1>;
+ 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
+ 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
- reg = <e000 0 0 0 0>;
+ reg = <0xe000 0x0 0x0 0x0 0x0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- ranges = <02000000 0 80000000
- 02000000 0 80000000
- 0 20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00080000>;
- clock-frequency = <1fca055>;
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x80000>;
+ clock-frequency = <33333333>;
isa@4 {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
- reg = <2000 0 0 0 0>;
- ranges = <1 0 01000000 0 0 00001000>;
+ reg = <0x2000 0x0 0x0 0x0 0x0>;
+ ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
interrupt-controller;
device_type = "interrupt-controller";
- reg = <1 20 2
- 1 a0 2
- 1 4d0 2>;
+ reg = <0x1 0x20 0x2
+ 0x1 0xa0 0x2
+ 0x1 0x4d0 0x2>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
rtc@70 {
compatible = "pnpPNP,b00";
- reg = <1 70 2>;
+ reg = <0x1 0x70 0x2>;
};
};
};
pci1: pci@e0009000 {
cell-index = <1>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
- a800 0 0 1 &mpic b 1
- a800 0 0 2 &mpic 1 1
- a800 0 0 3 &mpic 2 1
- a800 0 0 4 &mpic 3 1>;
+ 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <19 2>;
+ interrupts = <25 2>;
bus-range = <0 0>;
- ranges = <02000000 0 90000000 90000000 0 10000000
- 01000000 0 00000000 e2800000 0 00800000>;
- clock-frequency = <3f940aa>;
+ ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
+ 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0009000 1000>;
+ reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
pci2: pcie@e000a000 {
cell-index = <2>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
- 00000 0 0 1 &mpic 0 1
- 00000 0 0 2 &mpic 1 1
- 00000 0 0 3 &mpic 2 1
- 00000 0 0 4 &mpic 3 1>;
+ 00000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 00000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 00000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 08000000>;
- clock-frequency = <1fca055>;
+ interrupts = <26 2>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
+ clock-frequency = <33333333>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e000a000 1000>;
+ reg = <0xe000a000 0x1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- ranges = <02000000 0 a0000000
- 02000000 0 a0000000
- 0 20000000
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 08000000>;
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x8000000>;
};
};
};
/*
* MPC8555 CDS Device Tree Source
*
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
/ {
model = "MPC8555CDS";
PowerPC,8555@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
memory {
device_type = "memory";
- reg = <00000000 08000000>; // 128M at 0x0
+ reg = <0x0 0x8000000>; // 128M at 0x0
};
soc8555@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <0 e0000000 00100000>;
- reg = <e0000000 00001000>; // CCSRBAR 1M
+ ranges = <0x0 0xe0000000 0x100000>;
+ reg = <0xe0000000 0x1000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8555-memory-controller";
- reg = <2000 1000>;
+ reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8555-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <40000>; // L2, 256K
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
- interrupts = <10 2>;
+ interrupts = <16 2>;
};
i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <3000 100>;
- interrupts = <2b 2>;
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
- reg = <24520 20>;
+ reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <0>;
+ reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <1>;
+ reg = <0x1>;
device_type = "ethernet-phy";
};
};
device_type = "network";
model = "TSEC";
compatible = "gianfar";
- reg = <24000 1000>;
+ reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1d 2 1e 2 22 2>;
+ interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
device_type = "network";
model = "TSEC";
compatible = "gianfar";
- reg = <25000 1000>;
+ reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <23 2 24 2 28 2>;
+ interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <4500 100>; // reg base, size
+ reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <4600 100>; // reg base, size
+ reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
- reg = <919c0 30>;
+ reg = <0x919c0 0x30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 80000 10000>;
+ ranges = <0x0 0x80000 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
- reg = <0 2000 9000 1000>;
+ reg = <0x0 0x2000 0x9000 0x1000>;
};
};
compatible = "fsl,mpc8555-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
- reg = <919f0 10 915f0 10>;
+ reg = <0x919f0 0x10 0x915f0 0x10>;
};
cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- interrupts = <2e 2>;
+ interrupts = <46 2>;
interrupt-parent = <&mpic>;
- reg = <90c00 80>;
+ reg = <0x90c00 0x80>;
compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
};
};
pci0: pci@e0008000 {
cell-index = <0>;
- interrupt-map-mask = <1f800 0 0 7>;
+ interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x10 */
- 08000 0 0 1 &mpic 0 1
- 08000 0 0 2 &mpic 1 1
- 08000 0 0 3 &mpic 2 1
- 08000 0 0 4 &mpic 3 1
+ 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x11 */
- 08800 0 0 1 &mpic 0 1
- 08800 0 0 2 &mpic 1 1
- 08800 0 0 3 &mpic 2 1
- 08800 0 0 4 &mpic 3 1
+ 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 &mpic 0 1
- 09000 0 0 2 &mpic 1 1
- 09000 0 0 3 &mpic 2 1
- 09000 0 0 4 &mpic 3 1
+ 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 &mpic 1 1
- 09800 0 0 2 &mpic 2 1
- 09800 0 0 3 &mpic 3 1
- 09800 0 0 4 &mpic 0 1
+ 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 &mpic 2 1
- 0a000 0 0 2 &mpic 3 1
- 0a000 0 0 3 &mpic 0 1
- 0a000 0 0 4 &mpic 1 1
+ 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+ 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 &mpic 3 1
- 0a800 0 0 2 &mpic 0 1
- 0a800 0 0 3 &mpic 1 1
- 0a800 0 0 4 &mpic 2 1
+ 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 &mpic 0 1
- 19000 0 0 2 &mpic 1 1
- 19000 0 0 3 &mpic 2 1
- 19000 0 0 4 &mpic 3 1>;
+ 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <18 2>;
+ interrupts = <24 2>;
bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0008000 1000>;
+ reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
i8259@19000 {
interrupt-controller;
device_type = "interrupt-controller";
- reg = <19000 0 0 0 1>;
+ reg = <0x19000 0x0 0x0 0x0 0x1>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
pci1: pci@e0009000 {
cell-index = <1>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
- a800 0 0 1 &mpic b 1
- a800 0 0 2 &mpic b 1
- a800 0 0 3 &mpic b 1
- a800 0 0 4 &mpic b 1>;
+ 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <19 2>;
+ interrupts = <25 2>;
bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
- clock-frequency = <3f940aa>;
+ ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0009000 1000>;
+ reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
/*
* MPC8560 ADS Device Tree Source
*
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
/ {
model = "MPC8560ADS";
PowerPC,8560@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
- timebase-frequency = <04ead9a0>;
- bus-frequency = <13ab6680>;
- clock-frequency = <312c8040>;
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <82500000>;
+ bus-frequency = <330000000>;
+ clock-frequency = <825000000>;
};
};
memory {
device_type = "memory";
- reg = <00000000 10000000>;
+ reg = <0x0 0x10000000>;
};
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <0 e0000000 00100000>;
- reg = <e0000000 00000200>;
- bus-frequency = <13ab6680>;
+ ranges = <0x0 0xe0000000 0x100000>;
+ reg = <0xe0000000 0x200>;
+ bus-frequency = <330000000>;
memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
- reg = <2000 1000>;
+ reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <40000>; // L2, 256K
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>;
- interrupts = <10 2>;
+ interrupts = <16 2>;
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
- reg = <24520 20>;
+ reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <0>;
+ reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
- reg = <1>;
+ reg = <0x1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <7 1>;
- reg = <2>;
+ reg = <0x2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <7 1>;
- reg = <3>;
+ reg = <0x3>;
device_type = "ethernet-phy";
};
};
device_type = "network";
model = "TSEC";
compatible = "gianfar";
- reg = <24000 1000>;
+ reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1d 2 1e 2 22 2>;
+ interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
device_type = "network";
model = "TSEC";
compatible = "gianfar";
- reg = <25000 1000>;
+ reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <23 2 24 2 28 2>;
+ interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
device_type = "open-pic";
};
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
- reg = <919c0 30>;
+ reg = <0x919c0 0x30>;
ranges;
muram@80000 {
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 80000 10000>;
+ ranges = <0x0 0x80000 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
- reg = <0 4000 9000 2000>;
+ reg = <0x0 0x4000 0x9000 0x2000>;
};
};
compatible = "fsl,mpc8560-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
- reg = <919f0 10 915f0 10>;
- clock-frequency = <d#165000000>;
+ reg = <0x919f0 0x10 0x915f0 0x10>;
+ clock-frequency = <165000000>;
};
cpmpic: pic@90c00 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- interrupts = <2e 2>;
+ interrupts = <46 2>;
interrupt-parent = <&mpic>;
- reg = <90c00 80>;
+ reg = <0x90c00 0x80>;
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
};
device_type = "serial";
compatible = "fsl,mpc8560-scc-uart",
"fsl,cpm2-scc-uart";
- reg = <91a00 20 88000 100>;
+ reg = <0x91a00 0x20 0x88000 0x100>;
fsl,cpm-brg = <1>;
- fsl,cpm-command = <00800000>;
- current-speed = <1c200>;
- interrupts = <28 8>;
+ fsl,cpm-command = <0x800000>;
+ current-speed = <115200>;
+ interrupts = <40 8>;
interrupt-parent = <&cpmpic>;
};
device_type = "serial";
compatible = "fsl,mpc8560-scc-uart",
"fsl,cpm2-scc-uart";
- reg = <91a20 20 88100 100>;
+ reg = <0x91a20 0x20 0x88100 0x100>;
fsl,cpm-brg = <2>;
- fsl,cpm-command = <04a00000>;
- current-speed = <1c200>;
- interrupts = <29 8>;
+ fsl,cpm-command = <0x4a00000>;
+ current-speed = <115200>;
+ interrupts = <41 8>;
interrupt-parent = <&cpmpic>;
};
device_type = "network";
compatible = "fsl,mpc8560-fcc-enet",
"fsl,cpm2-fcc-enet";
- reg = <91320 20 88500 100 913b0 1>;
+ reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ];
- fsl,cpm-command = <16200300>;
- interrupts = <21 8>;
+ fsl,cpm-command = <0x16200300>;
+ interrupts = <33 8>;
interrupt-parent = <&cpmpic>;
phy-handle = <&phy2>;
};
device_type = "network";
compatible = "fsl,mpc8560-fcc-enet",
"fsl,cpm2-fcc-enet";
- reg = <91340 20 88600 100 913d0 1>;
+ reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ];
- fsl,cpm-command = <1a400300>;
- interrupts = <22 8>;
+ fsl,cpm-command = <0x1a400300>;
+ interrupts = <34 8>;
interrupt-parent = <&cpmpic>;
phy-handle = <&phy3>;
};
#address-cells = <3>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
- reg = <e0008000 1000>;
- clock-frequency = <3f940aa>;
- interrupt-map-mask = <f800 0 0 7>;
+ reg = <0xe0008000 0x1000>;
+ clock-frequency = <66666666>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x2 */
- 1000 0 0 1 &mpic 1 1
- 1000 0 0 2 &mpic 2 1
- 1000 0 0 3 &mpic 3 1
- 1000 0 0 4 &mpic 4 1
+ 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x3 */
- 1800 0 0 1 &mpic 4 1
- 1800 0 0 2 &mpic 1 1
- 1800 0 0 3 &mpic 2 1
- 1800 0 0 4 &mpic 3 1
+ 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x4 */
- 2000 0 0 1 &mpic 3 1
- 2000 0 0 2 &mpic 4 1
- 2000 0 0 3 &mpic 1 1
- 2000 0 0 4 &mpic 2 1
+ 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x5 */
- 2800 0 0 1 &mpic 2 1
- 2800 0 0 2 &mpic 3 1
- 2800 0 0 3 &mpic 4 1
- 2800 0 0 4 &mpic 1 1
+ 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 12 */
- 6000 0 0 1 &mpic 1 1
- 6000 0 0 2 &mpic 2 1
- 6000 0 0 3 &mpic 3 1
- 6000 0 0 4 &mpic 4 1
+ 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 13 */
- 6800 0 0 1 &mpic 4 1
- 6800 0 0 2 &mpic 1 1
- 6800 0 0 3 &mpic 2 1
- 6800 0 0 4 &mpic 3 1
+ 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 14*/
- 7000 0 0 1 &mpic 3 1
- 7000 0 0 2 &mpic 4 1
- 7000 0 0 3 &mpic 1 1
- 7000 0 0 4 &mpic 2 1
+ 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 15 */
- 7800 0 0 1 &mpic 2 1
- 7800 0 0 2 &mpic 3 1
- 7800 0 0 3 &mpic 4 1
- 7800 0 0 4 &mpic 1 1
+ 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 18 */
- 9000 0 0 1 &mpic 1 1
- 9000 0 0 2 &mpic 2 1
- 9000 0 0 3 &mpic 3 1
- 9000 0 0 4 &mpic 4 1
+ 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 19 */
- 9800 0 0 1 &mpic 4 1
- 9800 0 0 2 &mpic 1 1
- 9800 0 0 3 &mpic 2 1
- 9800 0 0 4 &mpic 3 1
+ 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 20 */
- a000 0 0 1 &mpic 3 1
- a000 0 0 2 &mpic 4 1
- a000 0 0 3 &mpic 1 1
- a000 0 0 4 &mpic 2 1
+ 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 21 */
- a800 0 0 1 &mpic 2 1
- a800 0 0 2 &mpic 3 1
- a800 0 0 3 &mpic 4 1
- a800 0 0 4 &mpic 1 1>;
+ 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <18 2>;
+ interrupts = <24 2>;
bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 01000000>;
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
};
};
/*
* MPC8568E MDS Device Tree Source
*
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
-
-/*
-/memreserve/ 00000000 1000000;
-*/
+/dts-v1/;
/ {
model = "MPC8568EMDS";
PowerPC,8568@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
memory {
device_type = "memory";
- reg = <00000000 10000000>;
+ reg = <0x0 0x10000000>;
};
bcsr@f8000000 {
device_type = "board-control";
- reg = <f8000000 8000>;
+ reg = <0xf8000000 0x8000>;
};
soc8568@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <0 e0000000 00100000>;
- reg = <e0000000 00001000>;
+ ranges = <0x0 0xe0000000 0x100000>;
+ reg = <0xe0000000 0x1000>;
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8568-memory-controller";
- reg = <2000 1000>;
+ reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8568-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <80000>; // L2, 512K
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
- interrupts = <10 2>;
+ interrupts = <16 2>;
};
i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <3000 100>;
- interrupts = <2b 2>;
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
- reg = <68>;
+ reg = <0x68>;
};
};
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
- reg = <3100 100>;
- interrupts = <2b 2>;
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
- reg = <24520 20>;
+ reg = <0x24520 0x20>;
phy0: ethernet-phy@7 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
- reg = <7>;
+ reg = <0x7>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
- reg = <1>;
+ reg = <0x1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
- reg = <2>;
+ reg = <0x2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
- reg = <3>;
+ reg = <0x3>;
device_type = "ethernet-phy";
};
};
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <24000 1000>;
+ reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1d 2 1e 2 22 2>;
+ interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
};
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <25000 1000>;
+ reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <23 2 24 2 28 2>;
+ interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
};
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <4500 100>;
+ reg = <0x4500 0x100>;
clock-frequency = <0>;
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8548-guts";
- reg = <e0000 1000>;
+ reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <4600 100>;
+ reg = <0x4600 0x100>;
clock-frequency = <0>;
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
- reg = <30000 f000>;
- interrupts = <2d 2>;
+ reg = <0x30000 0xf000>;
+ interrupts = <45 2>;
interrupt-parent = <&mpic>;
num-channels = <4>;
- channel-fifo-len = <18>;
- exec-units-mask = <000000fe>;
- descriptor-types-mask = <012b0ebf>;
+ channel-fifo-len = <24>;
+ exec-units-mask = <0xfe>;
+ descriptor-types-mask = <0x12b0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
par_io@e0100 {
- reg = <e0100 100>;
+ reg = <0xe0100 0x100>;
device_type = "par_io";
num-ports = <7>;
pio1: ucc_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
- 4 0a 1 0 2 0 /* TxD0 */
- 4 09 1 0 2 0 /* TxD1 */
- 4 08 1 0 2 0 /* TxD2 */
- 4 07 1 0 2 0 /* TxD3 */
- 4 17 1 0 2 0 /* TxD4 */
- 4 16 1 0 2 0 /* TxD5 */
- 4 15 1 0 2 0 /* TxD6 */
- 4 14 1 0 2 0 /* TxD7 */
- 4 0f 2 0 2 0 /* RxD0 */
- 4 0e 2 0 2 0 /* RxD1 */
- 4 0d 2 0 2 0 /* RxD2 */
- 4 0c 2 0 2 0 /* RxD3 */
- 4 1d 2 0 2 0 /* RxD4 */
- 4 1c 2 0 2 0 /* RxD5 */
- 4 1b 2 0 2 0 /* RxD6 */
- 4 1a 2 0 2 0 /* RxD7 */
- 4 0b 1 0 2 0 /* TX_EN */
- 4 18 1 0 2 0 /* TX_ER */
- 4 10 2 0 2 0 /* RX_DV */
- 4 1e 2 0 2 0 /* RX_ER */
- 4 11 2 0 2 0 /* RX_CLK */
- 4 13 1 0 2 0 /* GTX_CLK */
- 1 1f 2 0 3 0>; /* GTX125 */
+ 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
+ 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
+ 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
+ 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
+ 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
+ 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
+ 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
+ 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
+ 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
+ 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
+ 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
+ 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
+ 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
+ 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
+ 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
+ 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
+ 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
+ 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
+ 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
+ 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
+ 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
+ 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
+ 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
};
pio2: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
- 5 0a 1 0 2 0 /* TxD0 */
- 5 09 1 0 2 0 /* TxD1 */
- 5 08 1 0 2 0 /* TxD2 */
- 5 07 1 0 2 0 /* TxD3 */
- 5 17 1 0 2 0 /* TxD4 */
- 5 16 1 0 2 0 /* TxD5 */
- 5 15 1 0 2 0 /* TxD6 */
- 5 14 1 0 2 0 /* TxD7 */
- 5 0f 2 0 2 0 /* RxD0 */
- 5 0e 2 0 2 0 /* RxD1 */
- 5 0d 2 0 2 0 /* RxD2 */
- 5 0c 2 0 2 0 /* RxD3 */
- 5 1d 2 0 2 0 /* RxD4 */
- 5 1c 2 0 2 0 /* RxD5 */
- 5 1b 2 0 2 0 /* RxD6 */
- 5 1a 2 0 2 0 /* RxD7 */
- 5 0b 1 0 2 0 /* TX_EN */
- 5 18 1 0 2 0 /* TX_ER */
- 5 10 2 0 2 0 /* RX_DV */
- 5 1e 2 0 2 0 /* RX_ER */
- 5 11 2 0 2 0 /* RX_CLK */
- 5 13 1 0 2 0 /* GTX_CLK */
- 1 1f 2 0 3 0 /* GTX125 */
- 4 06 3 0 2 0 /* MDIO */
- 4 05 1 0 2 0>; /* MDC */
+ 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
+ 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
+ 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
+ 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
+ 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
+ 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
+ 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
+ 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
+ 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
+ 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
+ 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
+ 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
+ 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
+ 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
+ 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
+ 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
+ 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
+ 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
+ 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
+ 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
+ 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
+ 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
+ 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
+ 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
+ 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
};
};
};
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
- ranges = <0 e0080000 00040000>;
- reg = <e0080000 480>;
+ ranges = <0x0 0xe0080000 0x40000>;
+ reg = <0xe0080000 0x480>;
brg-frequency = <0>;
- bus-frequency = <179A7B00>;
+ bus-frequency = <396000000>;
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
- ranges = <0 00010000 0000c000>;
+ ranges = <0x0 0x10000 0x10000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
- reg = <0 c000>;
+ reg = <0x0 0x10000>;
};
};
spi@4c0 {
cell-index = <0>;
compatible = "fsl,spi";
- reg = <4c0 40>;
+ reg = <0x4c0 0x40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "cpu";
spi@500 {
cell-index = <1>;
compatible = "fsl,spi";
- reg = <500 40>;
+ reg = <0x500 0x40>;
interrupts = <1>;
interrupt-parent = <&qeic>;
mode = "cpu";
enet2: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
cell-index = <1>;
- device-id = <1>;
- reg = <2000 200>;
- interrupts = <20>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
enet3: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
- model = "UCC";
cell-index = <2>;
- device-id = <2>;
- reg = <3000 200>;
- interrupts = <21>;
+ reg = <0x3000 0x200>;
+ interrupts = <33>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
mdio@2120 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <2120 18>;
+ reg = <0x2120 0x18>;
compatible = "fsl,ucc-mdio";
/* These are the same PHYs as on
qe_phy0: ethernet-phy@07 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
- reg = <7>;
+ reg = <0x7>;
device_type = "ethernet-phy";
};
qe_phy1: ethernet-phy@01 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
- reg = <1>;
+ reg = <0x1>;
device_type = "ethernet-phy";
};
qe_phy2: ethernet-phy@02 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
- reg = <2>;
+ reg = <0x2>;
device_type = "ethernet-phy";
};
qe_phy3: ethernet-phy@03 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
- reg = <3>;
+ reg = <0x3>;
device_type = "ethernet-phy";
};
};
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
- reg = <80 80>;
+ reg = <0x80 0x80>;
big-endian;
- interrupts = <2e 2 2e 2>; //high:30 low:30
+ interrupts = <46 2 46 2>; //high:30 low:30
interrupt-parent = <&mpic>;
};
pci0: pci@e0008000 {
cell-index = <0>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x12 AD18 */
- 9000 0 0 1 &mpic 5 1
- 9000 0 0 2 &mpic 6 1
- 9000 0 0 3 &mpic 7 1
- 9000 0 0 4 &mpic 4 1
+ 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x13 AD19 */
- 9800 0 0 1 &mpic 6 1
- 9800 0 0 2 &mpic 7 1
- 9800 0 0 3 &mpic 4 1
- 9800 0 0 4 &mpic 5 1>;
+ 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
+ 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
+ 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00800000>;
- clock-frequency = <3f940aa>;
+ interrupts = <24 2>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0008000 1000>;
+ reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
/* PCI Express */
pci1: pcie@e000a000 {
cell-index = <2>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
- 00000 0 0 1 &mpic 0 1
- 00000 0 0 2 &mpic 1 1
- 00000 0 0 3 &mpic 2 1
- 00000 0 0 4 &mpic 3 1>;
+ 00000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 00000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 00000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 e2800000 0 00800000>;
- clock-frequency = <1fca055>;
+ interrupts = <26 2>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+ 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
+ clock-frequency = <33333333>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e000a000 1000>;
+ reg = <0xe000a000 0x1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- ranges = <02000000 0 a0000000
- 02000000 0 a0000000
- 0 10000000
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x10000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00800000>;
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x800000>;
};
};
};
/*
* MPC8572 DS Device Tree Source
*
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
/ {
model = "fsl,MPC8572DS";
compatible = "fsl,MPC8572DS";
PowerPC,8572@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
PowerPC,8572@1 {
device_type = "cpu";
- reg = <1>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
+ reg = <0x1>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
memory {
device_type = "memory";
- reg = <00000000 00000000>; // Filled by U-Boot
+ reg = <0x0 0x0>; // Filled by U-Boot
};
soc8572@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <00000000 ffe00000 00100000>;
- reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
+ ranges = <0x0 0xffe00000 0x100000>;
+ reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
bus-frequency = <0>; // Filled out by uboot.
memory-controller@2000 {
compatible = "fsl,mpc8572-memory-controller";
- reg = <2000 1000>;
+ reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <18 2>;
};
memory-controller@6000 {
compatible = "fsl,mpc8572-memory-controller";
- reg = <6000 1000>;
+ reg = <0x6000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <18 2>;
};
l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <80000>; // L2, 512K
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
- interrupts = <10 2>;
+ interrupts = <16 2>;
};
i2c@3000 {
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <3000 100>;
- interrupts = <2b 2>;
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
- reg = <3100 100>;
- interrupts = <2b 2>;
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
- reg = <24520 20>;
+ reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
- interrupts = <a 1>;
- reg = <0>;
+ interrupts = <10 1>;
+ reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
- interrupts = <a 1>;
- reg = <1>;
+ interrupts = <10 1>;
+ reg = <0x1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
- interrupts = <a 1>;
- reg = <2>;
+ interrupts = <10 1>;
+ reg = <0x2>;
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
- interrupts = <a 1>;
- reg = <3>;
+ interrupts = <10 1>;
+ reg = <0x3>;
};
};
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <24000 1000>;
+ reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1d 2 1e 2 22 2>;
+ interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <25000 1000>;
+ reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <23 2 24 2 28 2>;
+ interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <26000 1000>;
+ reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1f 2 20 2 21 2>;
+ interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <27000 1000>;
+ reg = <0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <25 2 26 2 27 2>;
+ interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy3>;
phy-connection-type = "rgmii-id";
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <4500 100>;
+ reg = <0x4500 0x100>;
clock-frequency = <0>;
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <4600 100>;
+ reg = <0x4600 0x100>;
clock-frequency = <0>;
- interrupts = <2a 2>;
+ interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8572-guts";
- reg = <e0000 1000>;
+ reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <ffe08000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 ffc00000 0 00010000>;
- clock-frequency = <1fca055>;
+ reg = <0xffe08000 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
+ clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- interrupt-map-mask = <ff00 0 0 7>;
+ interrupts = <24 2>;
+ interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */
- 8800 0 0 1 &mpic 2 1
- 8800 0 0 2 &mpic 3 1
- 8800 0 0 3 &mpic 4 1
- 8800 0 0 4 &mpic 1 1
+ 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 1 - PCI slot 1 */
- 8900 0 0 1 &mpic 2 1
- 8900 0 0 2 &mpic 3 1
- 8900 0 0 3 &mpic 4 1
- 8900 0 0 4 &mpic 1 1
+ 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 2 - PCI slot 1 */
- 8a00 0 0 1 &mpic 2 1
- 8a00 0 0 2 &mpic 3 1
- 8a00 0 0 3 &mpic 4 1
- 8a00 0 0 4 &mpic 1 1
+ 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 3 - PCI slot 1 */
- 8b00 0 0 1 &mpic 2 1
- 8b00 0 0 2 &mpic 3 1
- 8b00 0 0 3 &mpic 4 1
- 8b00 0 0 4 &mpic 1 1
+ 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 4 - PCI slot 1 */
- 8c00 0 0 1 &mpic 2 1
- 8c00 0 0 2 &mpic 3 1
- 8c00 0 0 3 &mpic 4 1
- 8c00 0 0 4 &mpic 1 1
+ 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 5 - PCI slot 1 */
- 8d00 0 0 1 &mpic 2 1
- 8d00 0 0 2 &mpic 3 1
- 8d00 0 0 3 &mpic 4 1
- 8d00 0 0 4 &mpic 1 1
+ 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 6 - PCI slot 1 */
- 8e00 0 0 1 &mpic 2 1
- 8e00 0 0 2 &mpic 3 1
- 8e00 0 0 3 &mpic 4 1
- 8e00 0 0 4 &mpic 1 1
+ 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 7 - PCI slot 1 */
- 8f00 0 0 1 &mpic 2 1
- 8f00 0 0 2 &mpic 3 1
- 8f00 0 0 3 &mpic 4 1
- 8f00 0 0 4 &mpic 1 1
+ 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 func 0 - PCI slot 2 */
- 9000 0 0 1 &mpic 3 1
- 9000 0 0 2 &mpic 4 1
- 9000 0 0 3 &mpic 1 1
- 9000 0 0 4 &mpic 2 1
+ 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 1 - PCI slot 2 */
- 9100 0 0 1 &mpic 3 1
- 9100 0 0 2 &mpic 4 1
- 9100 0 0 3 &mpic 1 1
- 9100 0 0 4 &mpic 2 1
+ 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 2 - PCI slot 2 */
- 9200 0 0 1 &mpic 3 1
- 9200 0 0 2 &mpic 4 1
- 9200 0 0 3 &mpic 1 1
- 9200 0 0 4 &mpic 2 1
+ 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 3 - PCI slot 2 */
- 9300 0 0 1 &mpic 3 1
- 9300 0 0 2 &mpic 4 1
- 9300 0 0 3 &mpic 1 1
- 9300 0 0 4 &mpic 2 1
+ 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 4 - PCI slot 2 */
- 9400 0 0 1 &mpic 3 1
- 9400 0 0 2 &mpic 4 1
- 9400 0 0 3 &mpic 1 1
- 9400 0 0 4 &mpic 2 1
+ 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 5 - PCI slot 2 */
- 9500 0 0 1 &mpic 3 1
- 9500 0 0 2 &mpic 4 1
- 9500 0 0 3 &mpic 1 1
- 9500 0 0 4 &mpic 2 1
+ 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 6 - PCI slot 2 */
- 9600 0 0 1 &mpic 3 1
- 9600 0 0 2 &mpic 4 1
- 9600 0 0 3 &mpic 1 1
- 9600 0 0 4 &mpic 2 1
+ 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 7 - PCI slot 2 */
- 9700 0 0 1 &mpic 3 1
- 9700 0 0 2 &mpic 4 1
- 9700 0 0 3 &mpic 1 1
- 9700 0 0 4 &mpic 2 1
+ 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
// IDSEL 0x1c USB
- e000 0 0 1 &i8259 c 2
- e100 0 0 2 &i8259 9 2
- e200 0 0 3 &i8259 a 2
- e300 0 0 4 &i8259 b 2
+ 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+ 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+ 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+ 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
// IDSEL 0x1d Audio
- e800 0 0 1 &i8259 6 2
+ 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
// IDSEL 0x1e Legacy
- f000 0 0 1 &i8259 7 2
- f100 0 0 1 &i8259 7 2
+ 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+ 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
// IDSEL 0x1f IDE/SATA
- f800 0 0 1 &i8259 e 2
- f900 0 0 1 &i8259 5 2
+ 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+ 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
>;
pcie@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- ranges = <02000000 0 80000000
- 02000000 0 80000000
- 0 20000000
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00100000>;
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
uli1575@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
- ranges = <02000000 0 80000000
- 02000000 0 80000000
- 0 20000000
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00100000>;
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
- reg = <f000 0 0 0 0>;
- ranges = <1 0 01000000 0 0
- 00001000>;
+ reg = <0xf000 0x0 0x0 0x0 0x0>;
+ ranges = <0x1 0x0 0x1000000 0x0 0x0
+ 0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
- reg = <1 20 2
- 1 a0 2
- 1 4d0 2>;
+ reg = <0x1 0x20 0x2
+ 0x1 0xa0 0x2
+ 0x1 0x4d0 0x2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
- reg = <1 60 1 1 64 1>;
- interrupts = <1 3 c 3>;
+ reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+ interrupts = <1 3 12 3>;
interrupt-parent =
<&i8259>;
keyboard@0 {
- reg = <0>;
+ reg = <0x0>;
compatible = "pnpPNP,303";
};
mouse@1 {
- reg = <1>;
+ reg = <0x1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible = "pnpPNP,b00";
- reg = <1 70 2>;
+ reg = <0x1 0x70 0x2>;
};
gpio@400 {
- reg = <1 400 80>;
+ reg = <0x1 0x400 0x80>;
};
};
};
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <ffe09000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 ffc10000 0 00010000>;
- clock-frequency = <1fca055>;
+ reg = <0xffe09000 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
+ clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupts = <26 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
- 0000 0 0 1 &mpic 4 1
- 0000 0 0 2 &mpic 5 1
- 0000 0 0 3 &mpic 6 1
- 0000 0 0 4 &mpic 7 1
+ 0000 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x5 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x6 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- ranges = <02000000 0 a0000000
- 02000000 0 a0000000
- 0 20000000
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00100000>;
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
};
};
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <ffe0a000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 c0000000 c0000000 0 20000000
- 01000000 0 00000000 ffc20000 0 00010000>;
- clock-frequency = <1fca055>;
+ reg = <0xffe0a000 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
+ clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
- interrupts = <1b 2>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupts = <27 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
- 0000 0 0 1 &mpic 0 1
- 0000 0 0 2 &mpic 1 1
- 0000 0 0 3 &mpic 2 1
- 0000 0 0 4 &mpic 3 1
+ 0000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- ranges = <02000000 0 c0000000
- 02000000 0 c0000000
- 0 20000000
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00100000>;
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
};
};
};
/ {
model = "MPC8641HPCN";
- compatible = "mpc86xx";
+ compatible = "fsl,mpc8641hpcn";
#address-cells = <1>;
#size-cells = <1>;
* MPC866 ADS Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
/ {
model = "MPC866ADS";
PowerPC,866@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <10>; // 16 bytes
- i-cache-line-size = <10>; // 16 bytes
- d-cache-size = <2000>; // L1, 8K
- i-cache-size = <4000>; // L1, 16K
+ reg = <0x0>;
+ d-cache-line-size = <16>; // 16 bytes
+ i-cache-line-size = <16>; // 16 bytes
+ d-cache-size = <0x2000>; // L1, 8K
+ i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- interrupts = <f 2>; // decrementer interrupt
+ interrupts = <15 2>; // decrementer interrupt
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
- reg = <00000000 800000>;
+ reg = <0x0 0x800000>;
};
localbus@ff000100 {
compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
- reg = <ff000100 40>;
+ reg = <0xff000100 0x40>;
ranges = <
- 1 0 ff080000 00008000
- 5 0 ff0a0000 00008000
+ 0x1 0x0 0xff080000 0x8000
+ 0x5 0x0 0xff0a0000 0x8000
>;
board-control@1,0 {
- reg = <1 0 20 5 300 4>;
+ reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
compatible = "fsl,mpc866ads-bcsr";
};
};
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <0 ff000000 00100000>;
- reg = <ff000000 00000200>;
+ ranges = <0x0 0xff000000 0x100000>;
+ reg = <0xff000000 0x200>;
bus-frequency = <0>;
mdio@e00 {
compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
- reg = <e00 188>;
+ reg = <0xe00 0x188>;
#address-cells = <1>;
#size-cells = <0>;
PHY: ethernet-phy@f {
- reg = <f>;
+ reg = <0xf>;
device_type = "ethernet-phy";
};
};
device_type = "network";
compatible = "fsl,mpc866-fec-enet",
"fsl,pq1-fec-enet";
- reg = <e00 188>;
+ reg = <0xe00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
interrupt-parent = <&PIC>;
PIC: pic@0 {
interrupt-controller;
#interrupt-cells = <2>;
- reg = <0 24>;
+ reg = <0x0 0x24>;
compatible = "fsl,mpc866-pic", "fsl,pq1-pic";
};
#size-cells = <1>;
compatible = "fsl,mpc866-cpm", "fsl,cpm1";
ranges;
- reg = <9c0 40>;
+ reg = <0x9c0 0x40>;
brg-frequency = <0>;
interrupts = <0 2>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 2000 2000>;
+ ranges = <0x0 0x2000 0x2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
- reg = <0 1c00>;
+ reg = <0x0 0x1c00>;
};
};
compatible = "fsl,mpc866-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
- reg = <9f0 10>;
+ reg = <0x9f0 0x10>;
clock-frequency = <0>;
};
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&PIC>;
- reg = <930 20>;
+ reg = <0x930 0x20>;
compatible = "fsl,mpc866-cpm-pic",
"fsl,cpm1-pic";
};
device_type = "serial";
compatible = "fsl,mpc866-smc-uart",
"fsl,cpm1-smc-uart";
- reg = <a80 10 3e80 40>;
+ reg = <0xa80 0x10 0x3e80 0x40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
- fsl,cpm-command = <0090>;
+ fsl,cpm-command = <0x90>;
};
serial@a90 {
device_type = "serial";
compatible = "fsl,mpc866-smc-uart",
"fsl,cpm1-smc-uart";
- reg = <a90 10 3f80 40>;
+ reg = <0xa90 0x10 0x3f80 0x40>;
interrupts = <3>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
- fsl,cpm-command = <00d0>;
+ fsl,cpm-command = <0xd0>;
};
ethernet@a00 {
device_type = "network";
compatible = "fsl,mpc866-scc-enet",
"fsl,cpm1-scc-enet";
- reg = <a00 18 3c00 100>;
+ reg = <0xa00 0x18 0x3c00 0x100>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1e>;
+ interrupts = <30>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-command = <0000>;
linux,network-index = <1>;
* MPC885 ADS Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007,2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
/ {
model = "MPC885ADS";
PowerPC,885@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <d#16>;
- i-cache-line-size = <d#16>;
- d-cache-size = <d#8192>;
- i-cache-size = <d#8192>;
+ reg = <0x0>;
+ d-cache-line-size = <16>;
+ i-cache-line-size = <16>;
+ d-cache-size = <8192>;
+ i-cache-size = <8192>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- interrupts = <f 2>; // decrementer interrupt
+ interrupts = <15 2>; // decrementer interrupt
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
- reg = <0 0>;
+ reg = <0x0 0x0>;
};
localbus@ff000100 {
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
- reg = <ff000100 40>;
+ reg = <0xff000100 0x40>;
ranges = <
- 0 0 fe000000 00800000
- 1 0 ff080000 00008000
- 5 0 ff0a0000 00008000
+ 0x0 0x0 0xfe000000 0x800000
+ 0x1 0x0 0xff080000 0x8000
+ 0x5 0x0 0xff0a0000 0x8000
>;
flash@0,0 {
compatible = "jedec-flash";
- reg = <0 0 800000>;
+ reg = <0x0 0x0 0x800000>;
bank-width = <4>;
device-width = <1>;
};
board-control@1,0 {
- reg = <1 0 20 5 300 4>;
+ reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
compatible = "fsl,mpc885ads-bcsr";
};
};
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <0 ff000000 00004000>;
+ ranges = <0x0 0xff000000 0x4000>;
bus-frequency = <0>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
- reg = <ff000000 4000>;
+ reg = <0xff000000 0x4000>;
mdio@e00 {
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
- reg = <e00 188>;
+ reg = <0xe00 0x188>;
#address-cells = <1>;
#size-cells = <0>;
PHY0: ethernet-phy@0 {
- reg = <0>;
+ reg = <0x0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
- reg = <1>;
+ reg = <0x1>;
device_type = "ethernet-phy";
};
PHY2: ethernet-phy@2 {
- reg = <2>;
+ reg = <0x2>;
device_type = "ethernet-phy";
};
};
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
- reg = <e00 188>;
+ reg = <0xe00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
interrupt-parent = <&PIC>;
device_type = "network";
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
- reg = <1e00 188>;
+ reg = <0x1e00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <7 1>;
interrupt-parent = <&PIC>;
PIC: interrupt-controller@0 {
interrupt-controller;
#interrupt-cells = <2>;
- reg = <0 24>;
+ reg = <0x0 0x24>;
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
};
#size-cells = <2>;
compatible = "fsl,pq-pcmcia";
device_type = "pcmcia";
- reg = <80 80>;
+ reg = <0x80 0x80>;
interrupt-parent = <&PIC>;
- interrupts = <d 1>;
+ interrupts = <13 1>;
};
cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
- command-proc = <9c0>;
+ command-proc = <0x9c0>;
interrupts = <0>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
- reg = <9c0 40>;
+ reg = <0x9c0 0x40>;
ranges;
muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 2000 2000>;
+ ranges = <0x0 0x2000 0x2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
- reg = <0 1c00>;
+ reg = <0x0 0x1c00>;
};
};
"fsl,cpm1-brg",
"fsl,cpm-brg";
clock-frequency = <0>;
- reg = <9f0 10>;
+ reg = <0x9f0 0x10>;
};
CPM_PIC: interrupt-controller@930 {
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&PIC>;
- reg = <930 20>;
+ reg = <0x930 0x20>;
compatible = "fsl,mpc885-cpm-pic",
"fsl,cpm1-pic";
};
device_type = "serial";
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
- reg = <a80 10 3e80 40>;
+ reg = <0xa80 0x10 0x3e80 0x40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
- fsl,cpm-command = <0090>;
+ fsl,cpm-command = <0x90>;
};
serial@a90 {
device_type = "serial";
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
- reg = <a90 10 3f80 40>;
+ reg = <0xa90 0x10 0x3f80 0x40>;
interrupts = <3>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
- fsl,cpm-command = <00d0>;
+ fsl,cpm-command = <0xd0>;
};
ethernet@a40 {
device_type = "network";
compatible = "fsl,mpc885-scc-enet",
"fsl,cpm1-scc-enet";
- reg = <a40 18 3e00 100>;
+ reg = <0xa40 0x18 0x3e00 0x100>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1c>;
+ interrupts = <28>;
interrupt-parent = <&CPM_PIC>;
phy-handle = <&PHY2>;
- fsl,cpm-command = <0080>;
+ fsl,cpm-command = <0x80>;
linux,network-index = <2>;
};
};
/*
* Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
*
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007,2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* option) any later version.
*/
+/dts-v1/;
+
/ {
model = "pq2fads";
compatible = "fsl,pq2fads";
cpu@0 {
device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <d#32>;
- i-cache-line-size = <d#32>;
- d-cache-size = <d#16384>;
- i-cache-size = <d#16384>;
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <16384>;
+ i-cache-size = <16384>;
timebase-frequency = <0>;
clock-frequency = <0>;
};
memory {
device_type = "memory";
- reg = <0 0>;
+ reg = <0x0 0x0>;
};
localbus@f0010100 {
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
- reg = <f0010100 60>;
+ reg = <0xf0010100 0x60>;
- ranges = <0 0 fe000000 00800000
- 1 0 f4500000 00008000
- 8 0 f8200000 00008000>;
+ ranges = <0x0 0x0 0xfe000000 0x800000
+ 0x1 0x0 0xf4500000 0x8000
+ 0x8 0x0 0xf8200000 0x8000>;
flash@0,0 {
compatible = "jedec-flash";
- reg = <0 0 800000>;
+ reg = <0x0 0x0 0x800000>;
bank-width = <4>;
device-width = <1>;
};
bcsr@1,0 {
- reg = <1 0 20>;
+ reg = <0x1 0x0 0x20>;
compatible = "fsl,pq2fads-bcsr";
};
PCI_PIC: pic@8,0 {
#interrupt-cells = <1>;
interrupt-controller;
- reg = <8 0 8>;
+ reg = <0x8 0x0 0x8>;
compatible = "fsl,pq2ads-pci-pic";
interrupt-parent = <&PIC>;
- interrupts = <18 8>;
+ interrupts = <24 8>;
};
};
pci@f0010800 {
device_type = "pci";
- reg = <f0010800 10c f00101ac 8 f00101c4 8>;
+ reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- clock-frequency = <d#66000000>;
- interrupt-map-mask = <f800 0 0 7>;
+ clock-frequency = <66000000>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x16 */
- b000 0 0 1 &PCI_PIC 0
- b000 0 0 2 &PCI_PIC 1
- b000 0 0 3 &PCI_PIC 2
- b000 0 0 4 &PCI_PIC 3
+ 0xb000 0x0 0x0 0x1 &PCI_PIC 0
+ 0xb000 0x0 0x0 0x2 &PCI_PIC 1
+ 0xb000 0x0 0x0 0x3 &PCI_PIC 2
+ 0xb000 0x0 0x0 0x4 &PCI_PIC 3
/* IDSEL 0x17 */
- b800 0 0 1 &PCI_PIC 4
- b800 0 0 2 &PCI_PIC 5
- b800 0 0 3 &PCI_PIC 6
- b800 0 0 4 &PCI_PIC 7
+ 0xb800 0x0 0x0 0x1 &PCI_PIC 4
+ 0xb800 0x0 0x0 0x2 &PCI_PIC 5
+ 0xb800 0x0 0x0 0x3 &PCI_PIC 6
+ 0xb800 0x0 0x0 0x4 &PCI_PIC 7
/* IDSEL 0x18 */
- c000 0 0 1 &PCI_PIC 8
- c000 0 0 2 &PCI_PIC 9
- c000 0 0 3 &PCI_PIC a
- c000 0 0 4 &PCI_PIC b>;
+ 0xc000 0x0 0x0 0x1 &PCI_PIC 8
+ 0xc000 0x0 0x0 0x2 &PCI_PIC 9
+ 0xc000 0x0 0x0 0x3 &PCI_PIC 10
+ 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
interrupt-parent = <&PIC>;
- interrupts = <12 8>;
- ranges = <42000000 0 80000000 80000000 0 20000000
- 02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 f6000000 0 02000000>;
+ interrupts = <18 8>;
+ ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
};
soc@f0000000 {
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8280", "fsl,pq2-soc";
- ranges = <00000000 f0000000 00053000>;
+ ranges = <0x0 0xf0000000 0x53000>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
- reg = <f0000000 00053000>;
+ reg = <0xf0000000 0x53000>;
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
- reg = <119c0 30>;
+ reg = <0x119c0 0x30>;
ranges;
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0 10000>;
+ ranges = <0x0 0x0 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
- reg = <0 2000 9800 800>;
+ reg = <0x0 0x2000 0x9800 0x800>;
};
};
compatible = "fsl,mpc8280-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
- reg = <119f0 10 115f0 10>;
+ reg = <0x119f0 0x10 0x115f0 0x10>;
};
serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8280-scc-uart",
"fsl,cpm2-scc-uart";
- reg = <11a00 20 8000 100>;
- interrupts = <28 8>;
+ reg = <0x11a00 0x20 0x8000 0x100>;
+ interrupts = <40 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
- fsl,cpm-command = <00800000>;
+ fsl,cpm-command = <0x800000>;
};
serial@11a20 {
device_type = "serial";
compatible = "fsl,mpc8280-scc-uart",
"fsl,cpm2-scc-uart";
- reg = <11a20 20 8100 100>;
- interrupts = <29 8>;
+ reg = <0x11a20 0x20 0x8100 0x100>;
+ interrupts = <41 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <2>;
- fsl,cpm-command = <04a00000>;
+ fsl,cpm-command = <0x4a00000>;
};
ethernet@11320 {
device_type = "network";
compatible = "fsl,mpc8280-fcc-enet",
"fsl,cpm2-fcc-enet";
- reg = <11320 20 8500 100 113b0 1>;
- interrupts = <21 8>;
+ reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
+ interrupts = <33 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
- fsl,cpm-command = <16200300>;
+ fsl,cpm-command = <0x16200300>;
};
ethernet@11340 {
device_type = "network";
compatible = "fsl,mpc8280-fcc-enet",
"fsl,cpm2-fcc-enet";
- reg = <11340 20 8600 100 113d0 1>;
- interrupts = <22 8>;
+ reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>;
+ interrupts = <34 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
- fsl,cpm-command = <1a400300>;
+ fsl,cpm-command = <0x1a400300>;
local-mac-address = [00 e0 0c 00 79 01];
};
"fsl,cpm2-mdio-bitbang";
#address-cells = <1>;
#size-cells = <0>;
- reg = <10d40 14>;
+ reg = <0x10d40 0x14>;
fsl,mdio-pin = <9>;
- fsl,mdc-pin = <a>;
+ fsl,mdc-pin = <10>;
PHY0: ethernet-phy@0 {
interrupt-parent = <&PIC>;
- interrupts = <19 2>;
- reg = <0>;
+ interrupts = <25 2>;
+ reg = <0x0>;
device_type = "ethernet-phy";
};
PHY1: ethernet-phy@1 {
interrupt-parent = <&PIC>;
- interrupts = <19 2>;
- reg = <3>;
+ interrupts = <25 2>;
+ reg = <0x3>;
device_type = "ethernet-phy";
};
};
#size-cells = <0>;
compatible = "fsl,mpc8280-usb",
"fsl,cpm2-usb";
- reg = <11b60 18 8b00 100>;
+ reg = <0x11b60 0x18 0x8b00 0x100>;
interrupt-parent = <&PIC>;
- interrupts = <b 8>;
- fsl,cpm-command = <2e600000>;
+ interrupts = <11 8>;
+ fsl,cpm-command = <0x2e600000>;
};
};
PIC: interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
- reg = <10c00 80>;
+ reg = <0x10c00 0x80>;
compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
};
* if it can determine the exact PrPMC type.
*/
+/dts-v1/;
+
/ {
#address-cells = <1>;
#size-cells = <1>;
PowerPC,7447 {
device_type = "cpu";
reg = <0>;
- clock-frequency = <2bb0b140>; /* Default (733 MHz) */
- bus-frequency = <7f28155>; /* 133.333333 MHz */
- timebase-frequency = <1fca055>; /* 33.333333 MHz */
- i-cache-line-size = <20>;
- d-cache-line-size = <20>;
- i-cache-size = <8000>;
- d-cache-size = <8000>;
+ clock-frequency = <733333333>; /* Default */
+ bus-frequency = <133333333>;
+ timebase-frequency = <33333333>;
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
};
};
memory {
device_type = "memory";
- reg = <00000000 20000000>; /* Default (512MB) */
+ reg = <0x0 0x20000000>; /* Default (512MB) */
};
- mv64x60@f1000000 { /* Marvell Discovery */
+ system-controller@f1000000 { /* Marvell Discovery mv64360 */
#address-cells = <1>;
#size-cells = <1>;
model = "mv64360"; /* Default */
- compatible = "marvell,mv64x60";
- clock-frequency = <7f28155>; /* 133.333333 MHz */
- reg = <f1000000 00010000>;
- virtual-reg = <f1000000>;
- ranges = <88000000 88000000 01000000 /* PCI 0 I/O Space */
- 80000000 80000000 08000000 /* PCI 0 MEM Space */
- a0000000 a0000000 04000000 /* User FLASH */
- 00000000 f1000000 00010000 /* Bridge's regs */
- f2000000 f2000000 00040000>; /* Integrated SRAM */
+ compatible = "marvell,mv64360";
+ clock-frequency = <133333333>;
+ reg = <0xf1000000 0x10000>;
+ virtual-reg = <0xf1000000>;
+ ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
+ 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
+ 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
+ 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
+ 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
flash@a0000000 {
device_type = "rom";
compatible = "direct-mapped";
- reg = <a0000000 4000000>; /* Default (64MB) */
+ reg = <0xa0000000 0x4000000>; /* Default (64MB) */
probe-type = "CFI";
bank-width = <4>;
- partitions = <00000000 00100000 /* RO */
- 00100000 00040001 /* RW */
- 00140000 00400000 /* RO */
- 00540000 039c0000 /* RO */
- 03f00000 00100000>; /* RO */
+ partitions = <0x00000000 0x00100000 /* RO */
+ 0x00100000 0x00040001 /* RW */
+ 0x00140000 0x00400000 /* RO */
+ 0x00540000 0x039c0000 /* RO */
+ 0x03f00000 0x00100000>; /* RO */
partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B";
};
#address-cells = <1>;
#size-cells = <0>;
device_type = "mdio";
- compatible = "marvell,mv64x60-mdio";
- ethernet-phy@1 {
+ compatible = "marvell,mv64360-mdio";
+ PHY0: ethernet-phy@1 {
device_type = "ethernet-phy";
compatible = "broadcom,bcm5421";
- interrupts = <4c>; /* GPP 12 */
- interrupt-parent = <&/mv64x60/pic>;
+ interrupts = <76>; /* GPP 12 */
+ interrupt-parent = <&PIC>;
reg = <1>;
};
- ethernet-phy@3 {
+ PHY1: ethernet-phy@3 {
device_type = "ethernet-phy";
compatible = "broadcom,bcm5421";
- interrupts = <4c>; /* GPP 12 */
- interrupt-parent = <&/mv64x60/pic>;
+ interrupts = <76>; /* GPP 12 */
+ interrupt-parent = <&PIC>;
reg = <3>;
};
};
- ethernet@2000 {
- reg = <2000 2000>;
- eth0 {
+ ethernet-group@2000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,mv64360-eth-group";
+ reg = <0x2000 0x2000>;
+ ethernet@0 {
device_type = "network";
- compatible = "marvell,mv64x60-eth";
- block-index = <0>;
- interrupts = <20>;
- interrupt-parent = <&/mv64x60/pic>;
- phy = <&/mv64x60/mdio/ethernet-phy@1>;
+ compatible = "marvell,mv64360-eth";
+ reg = <0>;
+ interrupts = <32>;
+ interrupt-parent = <&PIC>;
+ phy = <&PHY0>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
- eth1 {
+ ethernet@1 {
device_type = "network";
- compatible = "marvell,mv64x60-eth";
- block-index = <1>;
- interrupts = <21>;
- interrupt-parent = <&/mv64x60/pic>;
- phy = <&/mv64x60/mdio/ethernet-phy@3>;
+ compatible = "marvell,mv64360-eth";
+ reg = <1>;
+ interrupts = <33>;
+ interrupt-parent = <&PIC>;
+ phy = <&PHY1>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
- sdma@4000 {
- device_type = "dma";
- compatible = "marvell,mv64x60-sdma";
- reg = <4000 c18>;
- virtual-reg = <f1004000>;
- interrupt-base = <0>;
- interrupts = <24>;
- interrupt-parent = <&/mv64x60/pic>;
+ SDMA0: sdma@4000 {
+ compatible = "marvell,mv64360-sdma";
+ reg = <0x4000 0xc18>;
+ virtual-reg = <0xf1004000>;
+ interrupts = <36>;
+ interrupt-parent = <&PIC>;
};
- sdma@6000 {
- device_type = "dma";
- compatible = "marvell,mv64x60-sdma";
- reg = <6000 c18>;
- virtual-reg = <f1006000>;
- interrupt-base = <0>;
- interrupts = <26>;
- interrupt-parent = <&/mv64x60/pic>;
+ SDMA1: sdma@6000 {
+ compatible = "marvell,mv64360-sdma";
+ reg = <0x6000 0xc18>;
+ virtual-reg = <0xf1006000>;
+ interrupts = <38>;
+ interrupt-parent = <&PIC>;
};
- brg@b200 {
- compatible = "marvell,mv64x60-brg";
- reg = <b200 8>;
+ BRG0: brg@b200 {
+ compatible = "marvell,mv64360-brg";
+ reg = <0xb200 0x8>;
clock-src = <8>;
- clock-frequency = <7ed6b40>;
- current-speed = <2580>;
- bcr = <0>;
+ clock-frequency = <133333333>;
+ current-speed = <9600>;
};
- brg@b208 {
- compatible = "marvell,mv64x60-brg";
- reg = <b208 8>;
+ BRG1: brg@b208 {
+ compatible = "marvell,mv64360-brg";
+ reg = <0xb208 0x8>;
clock-src = <8>;
- clock-frequency = <7ed6b40>;
- current-speed = <2580>;
- bcr = <0>;
+ clock-frequency = <133333333>;
+ current-speed = <9600>;
};
- cunit@f200 {
- reg = <f200 200>;
+ CUNIT: cunit@f200 {
+ reg = <0xf200 0x200>;
};
- mpscrouting@b400 {
- reg = <b400 c>;
+ MPSCROUTING: mpscrouting@b400 {
+ reg = <0xb400 0xc>;
};
- mpscintr@b800 {
- reg = <b800 100>;
- virtual-reg = <f100b800>;
+ MPSCINTR: mpscintr@b800 {
+ reg = <0xb800 0x100>;
+ virtual-reg = <0xf100b800>;
};
- mpsc@8000 {
+ MPSC0: mpsc@8000 {
device_type = "serial";
- compatible = "marvell,mpsc";
- reg = <8000 38>;
- virtual-reg = <f1008000>;
- sdma = <&/mv64x60/sdma@4000>;
- brg = <&/mv64x60/brg@b200>;
- cunit = <&/mv64x60/cunit@f200>;
- mpscrouting = <&/mv64x60/mpscrouting@b400>;
- mpscintr = <&/mv64x60/mpscintr@b800>;
- block-index = <0>;
- max_idle = <28>;
- chr_1 = <0>;
- chr_2 = <0>;
- chr_10 = <3>;
- mpcr = <0>;
- interrupts = <28>;
- interrupt-parent = <&/mv64x60/pic>;
+ compatible = "marvell,mv64360-mpsc";
+ reg = <0x8000 0x38>;
+ virtual-reg = <0xf1008000>;
+ sdma = <&SDMA0>;
+ brg = <&BRG0>;
+ cunit = <&CUNIT>;
+ mpscrouting = <&MPSCROUTING>;
+ mpscintr = <&MPSCINTR>;
+ cell-index = <0>;
+ interrupts = <40>;
+ interrupt-parent = <&PIC>;
};
- mpsc@9000 {
+ MPSC1: mpsc@9000 {
device_type = "serial";
- compatible = "marvell,mpsc";
- reg = <9000 38>;
- virtual-reg = <f1009000>;
- sdma = <&/mv64x60/sdma@6000>;
- brg = <&/mv64x60/brg@b208>;
- cunit = <&/mv64x60/cunit@f200>;
- mpscrouting = <&/mv64x60/mpscrouting@b400>;
- mpscintr = <&/mv64x60/mpscintr@b800>;
- block-index = <1>;
- max_idle = <28>;
- chr_1 = <0>;
- chr_2 = <0>;
- chr_10 = <3>;
- mpcr = <0>;
- interrupts = <2a>;
- interrupt-parent = <&/mv64x60/pic>;
+ compatible = "marvell,mv64360-mpsc";
+ reg = <0x9000 0x38>;
+ virtual-reg = <0xf1009000>;
+ sdma = <&SDMA1>;
+ brg = <&BRG1>;
+ cunit = <&CUNIT>;
+ mpscrouting = <&MPSCROUTING>;
+ mpscintr = <&MPSCINTR>;
+ cell-index = <1>;
+ interrupts = <42>;
+ interrupt-parent = <&PIC>;
};
wdt@b410 { /* watchdog timer */
- compatible = "marvell,mv64x60-wdt";
- reg = <b410 8>;
- timeout = <a>; /* wdt timeout in seconds */
+ compatible = "marvell,mv64360-wdt";
+ reg = <0xb410 0x8>;
};
i2c@c000 {
device_type = "i2c";
- compatible = "marvell,mv64x60-i2c";
- reg = <c000 20>;
- virtual-reg = <f100c000>;
- freq_m = <8>;
- freq_n = <3>;
- timeout = <3e8>; /* 1000 = 1 second */
- retries = <1>;
- interrupts = <25>;
- interrupt-parent = <&/mv64x60/pic>;
+ compatible = "marvell,mv64360-i2c";
+ reg = <0xc000 0x20>;
+ virtual-reg = <0xf100c000>;
+ interrupts = <37>;
+ interrupt-parent = <&PIC>;
};
- pic {
+ PIC: pic {
#interrupt-cells = <1>;
#address-cells = <0>;
- compatible = "marvell,mv64x60-pic";
- reg = <0000 88>;
+ compatible = "marvell,mv64360-pic";
+ reg = <0x0 0x88>;
interrupt-controller;
};
mpp@f000 {
- compatible = "marvell,mv64x60-mpp";
- reg = <f000 10>;
+ compatible = "marvell,mv64360-mpp";
+ reg = <0xf000 0x10>;
};
gpp@f100 {
- compatible = "marvell,mv64x60-gpp";
- reg = <f100 20>;
+ compatible = "marvell,mv64360-gpp";
+ reg = <0xf100 0x20>;
};
pci@80000000 {
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
- compatible = "marvell,mv64x60-pci";
- reg = <0cf8 8>;
- ranges = <01000000 0 0 88000000 0 01000000
- 02000000 0 80000000 80000000 0 08000000>;
- bus-range = <0 ff>;
- clock-frequency = <3EF1480>;
- interrupt-pci-iack = <0c34>;
- interrupt-parent = <&/mv64x60/pic>;
- interrupt-map-mask = <f800 0 0 7>;
+ compatible = "marvell,mv64360-pci";
+ reg = <0xcf8 0x8>;
+ ranges = <0x01000000 0x0 0x0
+ 0x88000000 0x0 0x01000000
+ 0x02000000 0x0 0x80000000
+ 0x80000000 0x0 0x08000000>;
+ bus-range = <0 255>;
+ clock-frequency = <66000000>;
+ interrupt-pci-iack = <0xc34>;
+ interrupt-parent = <&PIC>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0a */
- 5000 0 0 1 &/mv64x60/pic 50
- 5000 0 0 2 &/mv64x60/pic 51
- 5000 0 0 3 &/mv64x60/pic 5b
- 5000 0 0 4 &/mv64x60/pic 5d
+ 0x5000 0 0 1 &PIC 80
+ 0x5000 0 0 2 &PIC 81
+ 0x5000 0 0 3 &PIC 91
+ 0x5000 0 0 4 &PIC 93
/* IDSEL 0x0b */
- 5800 0 0 1 &/mv64x60/pic 5b
- 5800 0 0 2 &/mv64x60/pic 5d
- 5800 0 0 3 &/mv64x60/pic 50
- 5800 0 0 4 &/mv64x60/pic 51
+ 0x5800 0 0 1 &PIC 91
+ 0x5800 0 0 2 &PIC 93
+ 0x5800 0 0 3 &PIC 80
+ 0x5800 0 0 4 &PIC 81
/* IDSEL 0x0c */
- 6000 0 0 1 &/mv64x60/pic 5b
- 6000 0 0 2 &/mv64x60/pic 5d
- 6000 0 0 3 &/mv64x60/pic 50
- 6000 0 0 4 &/mv64x60/pic 51
+ 0x6000 0 0 1 &PIC 91
+ 0x6000 0 0 2 &PIC 93
+ 0x6000 0 0 3 &PIC 80
+ 0x6000 0 0 4 &PIC 81
/* IDSEL 0x0d */
- 6800 0 0 1 &/mv64x60/pic 5d
- 6800 0 0 2 &/mv64x60/pic 50
- 6800 0 0 3 &/mv64x60/pic 51
- 6800 0 0 4 &/mv64x60/pic 5b
+ 0x6800 0 0 1 &PIC 93
+ 0x6800 0 0 2 &PIC 80
+ 0x6800 0 0 3 &PIC 81
+ 0x6800 0 0 4 &PIC 91
>;
};
cpu-error@0070 {
- compatible = "marvell,mv64x60-cpu-error";
- reg = <0070 10 0128 28>;
- interrupts = <03>;
- interrupt-parent = <&/mv64x60/pic>;
+ compatible = "marvell,mv64360-cpu-error";
+ reg = <0x70 0x10 0x128 0x28>;
+ interrupts = <3>;
+ interrupt-parent = <&PIC>;
};
sram-ctrl@0380 {
- compatible = "marvell,mv64x60-sram-ctrl";
- reg = <0380 80>;
- interrupts = <0d>;
- interrupt-parent = <&/mv64x60/pic>;
+ compatible = "marvell,mv64360-sram-ctrl";
+ reg = <0x380 0x80>;
+ interrupts = <13>;
+ interrupt-parent = <&PIC>;
};
pci-error@1d40 {
- compatible = "marvell,mv64x60-pci-error";
- reg = <1d40 40 0c28 4>;
- interrupts = <0c>;
- interrupt-parent = <&/mv64x60/pic>;
+ compatible = "marvell,mv64360-pci-error";
+ reg = <0x1d40 0x40 0xc28 0x4>;
+ interrupts = <12>;
+ interrupt-parent = <&PIC>;
};
mem-ctrl@1400 {
- compatible = "marvell,mv64x60-mem-ctrl";
- reg = <1400 60>;
- interrupts = <11>;
- interrupt-parent = <&/mv64x60/pic>;
+ compatible = "marvell,mv64360-mem-ctrl";
+ reg = <0x1400 0x60>;
+ interrupts = <17>;
+ interrupt-parent = <&PIC>;
};
};
chosen {
bootargs = "ip=on";
- linux,stdout-path = "/mv64x60@f1000000/mpsc@8000";
+ linux,stdout-path = &MPSC0;
};
};
};
EMAC0: ethernet@ef600e00 {
- linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
interrupt-parent = <&EMAC0>;
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
};
EMAC1: ethernet@ef600f00 {
- linux,network-index = <1>;
device_type = "network";
compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
interrupt-parent = <&EMAC1>;
mal-tx-channel = <1>;
mal-rx-channel = <1>;
cell-index = <1>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
--- /dev/null
+/*
+ * SBC8641D Device Tree Source
+ *
+ * Copyright 2008 Wind River Systems Inc.
+ *
+ * Paul Gortmaker (see MAINTAINERS for contact information)
+ *
+ * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "SBC8641D";
+ compatible = "wind,sbc8641";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8641@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <32768>; // L1
+ i-cache-size = <32768>; // L1
+ timebase-frequency = <0>; // From uboot
+ bus-frequency = <0>; // From uboot
+ clock-frequency = <0>; // From uboot
+ };
+ PowerPC,8641@1 {
+ device_type = "cpu";
+ reg = <1>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
+ timebase-frequency = <0>; // From uboot
+ bus-frequency = <0>; // From uboot
+ clock-frequency = <0>; // From uboot
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>; // 512M at 0x0
+ };
+
+ localbus@f8005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8641-localbus", "simple-bus";
+ reg = <0xf8005000 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
+ 1 0 0xf0000000 0x00010000 // 64KB EEPROM
+ 2 0 0xf1000000 0x00100000 // EPLD (1MB)
+ 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
+ 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
+ 6 0 0xf4000000 0x00100000 // LCD display (1MB)
+ 7 0 0xe8000000 0x04000000>; // 64MB OneNAND
+
+ flash@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x01000000>;
+ bank-width = <2>;
+ device-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "dtb";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+ partition@300000 {
+ label = "kernel";
+ reg = <0x00100000 0x00400000>;
+ read-only;
+ };
+ partition@400000 {
+ label = "fs";
+ reg = <0x00500000 0x00a00000>;
+ };
+ partition@700000 {
+ label = "firmware";
+ reg = <0x00f00000 0x00100000>;
+ read-only;
+ };
+ };
+
+ epld@2,0 {
+ compatible = "wrs,epld-localbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <2 0 0x100000>;
+ ranges = <0 0 5 0 1 // User switches
+ 1 0 5 1 1 // Board ID/Rev
+ 3 0 5 3 1>; // LEDs
+ };
+ };
+
+ soc@f8000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+ ranges = <0x00000000 0xf8000000 0x00100000>;
+ reg = <0xf8000000 0x00001000>; // CCSRBAR
+ bus-frequency = <0>;
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+
+ phy0: ethernet-phy@1f {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <0x1f>;
+ device_type = "ethernet-phy";
+ };
+ phy1: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+ phy2: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet0: ethernet@24000 {
+ cell-index = <0>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet1: ethernet@25000 {
+ cell-index = <1>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet2: ethernet@26000 {
+ cell-index = <2>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy2>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet3: ethernet@27000 {
+ cell-index = <3>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x27000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <37 2 38 2 39 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy3>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <28 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+
+ global-utilities@e0000 {
+ compatible = "fsl,mpc8641-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie@f8008000 {
+ cell-index = <0>;
+ compatible = "fsl,mpc8641-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf8008000 0x1000>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <24 2>;
+ interrupt-map-mask = <0xff00 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0x0000 0 0 1 &mpic 0 1
+ 0x0000 0 0 2 &mpic 1 1
+ 0x0000 0 0 3 &mpic 2 1
+ 0x0000 0 0 4 &mpic 3 1
+ >;
+
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x80000000
+ 0x02000000 0x0 0x80000000
+ 0x0 0x20000000
+
+ 0x01000000 0x0 0x00000000
+ 0x01000000 0x0 0x00000000
+ 0x0 0x00100000>;
+ };
+
+ };
+
+ pci1: pcie@f8009000 {
+ cell-index = <1>;
+ compatible = "fsl,mpc8641-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf8009000 0x1000>;
+ bus-range = <0 0xff>;
+ ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0x0000 0 0 1 &mpic 4 1
+ 0x0000 0 0 2 &mpic 5 1
+ 0x0000 0 0 3 &mpic 6 1
+ 0x0000 0 0 4 &mpic 7 1
+ >;
+
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0xa0000000
+ 0x02000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x01000000 0x0 0x00000000
+ 0x01000000 0x0 0x00000000
+ 0x0 0x00100000>;
+ };
+ };
+};
};
EMAC0: ethernet@ef600e00 {
- linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-440epx", "ibm,emac4";
interrupt-parent = <&EMAC0>;
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
};
EMAC1: ethernet@ef600f00 {
- linux,network-index = <1>;
device_type = "network";
compatible = "ibm,emac-440epx", "ibm,emac4";
interrupt-parent = <&EMAC1>;
mal-tx-channel = <1>;
mal-rx-channel = <1>;
cell-index = <1>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
// FIXME: anything else?
};
+ L2C0: l2c {
+ compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
+ dcr-reg = <20 8 /* Internal SRAM DCR's */
+ 30 8>; /* L2 cache DCR's */
+ cache-line-size = <20>; /* 32 bytes */
+ cache-size = <40000>; /* L2, 256K */
+ interrupt-parent = <&UIC2>;
+ interrupts = <17 1>;
+ };
+
plb {
compatible = "ibm,plb-440gx", "ibm,plb4";
#address-cells = <2>;
reg = <40000790 8>;
};
+ TAH0: emac-tah@40000b50 {
+ compatible = "ibm,tah-440gx", "ibm,tah";
+ reg = <40000b50 30>;
+ };
+
+ TAH1: emac-tah@40000d50 {
+ compatible = "ibm,tah-440gx", "ibm,tah";
+ reg = <40000d50 30>;
+ };
EMAC0: ethernet@40000800 {
unused = <1>;
- linux,network-index = <2>;
device_type = "network";
compatible = "ibm,emac-440gx", "ibm,emac4";
interrupt-parent = <&UIC1>;
};
EMAC1: ethernet@40000900 {
unused = <1>;
- linux,network-index = <3>;
device_type = "network";
compatible = "ibm,emac-440gx", "ibm,emac4";
interrupt-parent = <&UIC1>;
};
EMAC2: ethernet@40000c00 {
- linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-440gx", "ibm,emac4";
interrupt-parent = <&UIC2>;
mal-tx-channel = <2>;
mal-rx-channel = <2>;
cell-index = <2>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
rgmii-channel = <0>;
zmii-device = <&ZMII0>;
zmii-channel = <2>;
+ tah-device = <&TAH0>;
+ tah-channel = <0>;
};
EMAC3: ethernet@40000e00 {
- linux,network-index = <1>;
device_type = "network";
compatible = "ibm,emac-440gx", "ibm,emac4";
interrupt-parent = <&UIC2>;
mal-tx-channel = <3>;
mal-rx-channel = <3>;
cell-index = <3>;
- max-frame-size = <5dc>;
+ max-frame-size = <2328>;
rx-fifo-size = <1000>;
tx-fifo-size = <800>;
phy-mode = "rgmii";
rgmii-channel = <1>;
zmii-device = <&ZMII0>;
zmii-channel = <3>;
+ tah-device = <&TAH1>;
+ tah-channel = <0>;
};
};
EMAC: ethernet@ef600800 {
- linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-405gp", "ibm,emac";
interrupt-parent = <&UIC0>;
};
EMAC0: ethernet@ef600e00 {
- linux,network-index = <0>;
device_type = "network";
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
interrupt-parent = <&UIC1>;
--- /dev/null
+/*
+ * Device Tree Source for AMCC Yosemite
+ *
+ * Copyright 2008 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,yosemite";
+ compatible = "amcc,yosemite","amcc,bamboo";
+ dcr-parent = <&/cpus/cpu@0>;
+
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ serial2 = &UART2;
+ serial3 = &UART3;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,440EP";
+ reg = <0>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ timebase-frequency = <0>; /* Filled in by zImage */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <8000>;
+ d-cache-size = <8000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0>; /* Filled in by zImage */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-440ep","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-440ep","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1e 4 1f 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-440ep";
+ dcr-reg = <00e 002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-440ep";
+ dcr-reg = <00c 002>;
+ };
+
+ plb {
+ compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ SDRAM0: sdram {
+ compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
+ dcr-reg = <010 2>;
+ };
+
+ DMA0: dma {
+ compatible = "ibm,dma-440ep", "ibm,dma-440gp";
+ dcr-reg = <100 027>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
+ dcr-reg = <180 62>;
+ num-tx-chans = <4>;
+ num-rx-chans = <2>;
+ interrupt-parent = <&MAL0>;
+ interrupts = <0 1 2 3 4>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
+ /*RXEOB*/ 1 &UIC0 b 4
+ /*SERR*/ 2 &UIC1 0 4
+ /*TXDE*/ 3 &UIC1 1 4
+ /*RXDE*/ 4 &UIC1 2 4>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Bamboo is oddball in the 44x world and doesn't use the ERPN
+ * bits.
+ */
+ ranges = <00000000 0 00000000 80000000
+ 80000000 0 80000000 80000000>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <7 4>;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ interrupts = <5 1>;
+ interrupt-parent = <&UIC1>;
+ };
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <1c200>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600400 8>;
+ virtual-reg = <ef600400>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ UART2: serial@ef600500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600500 8>;
+ virtual-reg = <ef600500>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <3 4>;
+ status = "disabled";
+ };
+
+ UART3: serial@ef600600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600600 8>;
+ virtual-reg = <ef600600>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <4 4>;
+ status = "disabled";
+ };
+
+ IIC0: i2c@ef600700 {
+ compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
+ reg = <ef600700 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ IIC1: i2c@ef600800 {
+ compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
+ reg = <ef600800 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <7 4>;
+ };
+
+ spi@ef600900 {
+ compatible = "amcc,spi-440ep";
+ reg = <ef600900 6>;
+ interrupts = <8 4>;
+ interrupt-parent = <&UIC0>;
+ };
+
+ ZMII0: emac-zmii@ef600d00 {
+ compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
+ reg = <ef600d00 c>;
+ };
+
+ EMAC0: ethernet@ef600e00 {
+ device_type = "network";
+ compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
+ interrupt-parent = <&UIC1>;
+ interrupts = <1c 4 1d 4>;
+ reg = <ef600e00 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0 1>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000000>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <0>;
+ };
+
+ EMAC1: ethernet@ef600f00 {
+ device_type = "network";
+ compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
+ interrupt-parent = <&UIC1>;
+ interrupts = <1e 4 1f 4>;
+ reg = <ef600f00 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <2 3>;
+ mal-rx-channel = <1>;
+ cell-index = <1>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000000>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <1>;
+ };
+
+ usb@ef601000 {
+ compatible = "ohci-be";
+ reg = <ef601000 80>;
+ interrupts = <8 4 9 4>;
+ interrupt-parent = < &UIC1 >;
+ };
+ };
+
+ PCI0: pci@ec000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
+ primary;
+ reg = <0 eec00000 8 /* Config space access */
+ 0 eed00000 4 /* IACK */
+ 0 eed00000 4 /* Special cycle */
+ 0 ef400000 40>; /* Internal registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed. Chip supports a second
+ * IO range but we don't use it for now
+ */
+ ranges = <02000000 0 a0000000 0 a0000000 0 20000000
+ 01000000 0 00000000 0 e8000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* Bamboo has all 4 IRQ pins tied together per slot */
+ interrupt-map-mask = <f800 0 0 0>;
+ interrupt-map = <
+ /* IDSEL 1 */
+ 0800 0 0 0 &UIC0 1c 8
+
+ /* IDSEL 2 */
+ 1000 0 0 0 &UIC0 1b 8
+
+ /* IDSEL 3 */
+ 1800 0 0 0 &UIC0 1a 8
+
+ /* IDSEL 4 */
+ 2000 0 0 0 &UIC0 19 8
+ >;
+ };
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@ef600300";
+ };
+};
ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
ibm4xx_sdram_fixup_memsize();
- dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
+ dt_fixup_mac_address_by_alias("ethernet0", ebony_mac0);
+ dt_fixup_mac_address_by_alias("ethernet1", ebony_mac1);
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
ebony_flashsel_fixup();
}
#define check_err(err) \
({ \
if (BAD_ERROR(err) || ((err < 0) && DEBUG)) \
- printf("%s():%d %s\n\r", __FUNCTION__, __LINE__, \
+ printf("%s():%d %s\n\r", __func__, __LINE__, \
fdt_strerror(err)); \
if (BAD_ERROR(err)) \
exit(); \
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp)
{
- int n;
-
/* Get the base address of the psc registers */
- n = getprop(devp, "virtual-reg", &psc, sizeof(psc));
- if (n != sizeof(psc)) {
- if (!dt_xlate_reg(devp, 0, (void *)&psc, NULL))
- return -1;
- }
+ if (dt_get_virtual_reg(devp, &psc, 1) < 1)
+ return -1;
scdp->open = psc_open;
scdp->putc = psc_putc;
if (mpscintr_base == NULL)
goto err_out;
- n = getprop(devp, "block-index", &v, sizeof(v));
+ n = getprop(devp, "cell-index", &v, sizeof(v));
if (n != sizeof(v))
goto err_out;
reg_set = (int)v;
u32 v[2];
void *devp;
- devp = finddevice("/mv64x60");
+ devp = find_node_by_compatible(NULL, "marvell,mv64360");
if (devp == NULL)
goto err_out;
if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v))
u32 v;
void *devp;
- devp = finddevice("/mv64x60");
+ devp = find_node_by_compatible(NULL, "marvell,mv64360");
if (devp == NULL)
goto err_out;
if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
u32 v;
void *devp;
- devp = finddevice("/mv64x60/i2c");
+ devp = find_node_by_compatible(NULL, "marvell,mv64360-i2c");
if (devp == NULL)
goto err_out;
if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
int ns16550_console_init(void *devp, struct serial_console_data *scdp)
{
int n;
- unsigned long reg_phys;
- n = getprop(devp, "virtual-reg", ®_base, sizeof(reg_base));
- if (n != sizeof(reg_base)) {
- if (!dt_xlate_reg(devp, 0, ®_phys, NULL))
- return -1;
-
- reg_base = (void *)reg_phys;
- }
+ if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1)
+ return -1;
n = getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift));
if (n != sizeof(reg_shift))
int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr);
int dt_is_compatible(void *node, const char *compat);
void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize);
+int dt_get_virtual_reg(void *node, void **addr, int nres);
static inline void *finddevice(const char *name)
{
acc_bits);
/* Get the cpu -> pci i/o & mem mappings from the device tree */
- devp = finddevice("/mv64x60/pci@80000000");
+ devp = find_node_by_compatible(NULL, "marvell,mv64360-pci");
if (devp == NULL)
- fatal("Error: Missing /mv64x60/pci@80000000"
+ fatal("Error: Missing marvell,mv64360-pci"
" device tree node\n\r");
rc = getprop(devp, "ranges", v, sizeof(v));
if (rc != sizeof(v))
- fatal("Error: Can't find /mv64x60/pci@80000000/ranges"
+ fatal("Error: Can't find marvell,mv64360-pci ranges"
" property\n\r");
/* Get the cpu -> pci i/o & mem mappings from the device tree */
- devp = finddevice("/mv64x60");
+ devp = find_node_by_compatible(NULL, "marvell,mv64360");
if (devp == NULL)
- fatal("Error: Missing /mv64x60 device tree node\n\r");
+ fatal("Error: Missing marvell,mv64360 device tree node\n\r");
enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
enables |= 0x0007fe00; /* Disable all cpu->pci windows */
setprop(devp, "model", model, l);
/* Set /cpus/PowerPC,7447/clock-frequency */
- devp = finddevice("/cpus/PowerPC,7447");
+ devp = find_node_by_prop_value_str(NULL, "device_type", "cpu");
if (devp == NULL)
- fatal("Error: Missing proper /cpus device tree node\n\r");
+ fatal("Error: Missing proper cpu device tree node\n\r");
v[0] = bip->core_speed;
setprop(devp, "clock-frequency", &v[0], sizeof(v[0]));
v[1] = bip->mem_size;
setprop(devp, "reg", v, sizeof(v));
- /* Update /mv64x60/model, if this is a mv64362 */
+ /* Update model, if this is a mv64362 */
if (bip->bridge_type == BRIDGE_TYPE_MV64362) {
- devp = finddevice("/mv64x60");
+ devp = find_node_by_compatible(NULL, "marvell,mv64360");
if (devp == NULL)
- fatal("Error: Missing /mv64x60 device tree node\n\r");
+ fatal("Error: Missing marvell,mv64360"
+ " device tree node\n\r");
setprop(devp, "model", "mv64362", strlen("mv64362") + 1);
}
/* Set User FLASH size */
- devp = finddevice("/mv64x60/flash@a0000000");
+ devp = find_node_by_compatible(NULL, "direct-mapped");
if (devp == NULL)
fatal("Error: Missing User FLASH device tree node\n\r");
rc = getprop(devp, "reg", v, sizeof(v));
/*
* __system_reset_overlay - The PS3 first stage entry.
*
- * The bootwraper build script copies the 0x100 bytes at symbol
- * __system_reset_overlay to offset 0x100 of the rom image.
+ * The bootwraper build script copies the 512 bytes at symbol
+ * __system_reset_overlay to offset 0x100 of the rom image. This symbol
+ * must occupy 512 or less bytes.
*
* The PS3 has a single processor with two threads.
*/
mfspr r3, 0x88
cntlzw. r3, r3
- li r4, 0
- li r5, 0
beq 1f
/* Secondary goes to __secondary_hold in kernel. */
mtctr r4
bctr
- /* Primary delays then goes to _zimage_start in wrapper. */
1:
+ /* Save the value at addr zero for a null pointer write check later. */
+
+ li r4, 0
+ lwz r3, 0(r4)
+
+ /* Primary delays then goes to _zimage_start in wrapper. */
+
or 31, 31, 31 /* db16cyc */
or 31, 31, 31 /* db16cyc */
mtctr r4
bctr
+ . = __system_reset_overlay + 512
+
/*
* __system_reset_kernel - Place holder for the kernel reset vector.
*
- * The bootwrapper build script copies 0x100 bytes from offset 0x100
+ * The bootwrapper build script copies 512 bytes from offset 0x100
* of the rom image to the symbol __system_reset_kernel. At runtime
- * the bootwrapper program copies the 0x100 bytes at __system_reset_kernel
- * to ram address 0x100. This symbol must occupy 0x100 bytes.
+ * the bootwrapper program copies the 512 bytes at __system_reset_kernel
+ * to ram address 0x100. This symbol must occupy 512 bytes.
*/
.globl __system_reset_kernel
__system_reset_kernel:
- . = __system_reset_kernel + 0x100
+ . = __system_reset_kernel + 512
#include "page.h"
#include "ops.h"
-extern s64 lv1_panic(u64 in_1);
-extern s64 lv1_get_logical_partition_id(u64 *out_1);
-extern s64 lv1_get_logical_ppe_id(u64 *out_1);
-extern s64 lv1_get_repository_node_value(u64 in_1, u64 in_2, u64 in_3,
+extern int lv1_panic(u64 in_1);
+extern int lv1_get_logical_partition_id(u64 *out_1);
+extern int lv1_get_logical_ppe_id(u64 *out_1);
+extern int lv1_get_repository_node_value(u64 in_1, u64 in_2, u64 in_3,
u64 in_4, u64 in_5, u64 *out_1, u64 *out_2);
#ifdef DEBUG
* edit the command line passed to vmlinux (by setting /chosen/bootargs).
* The buffer is put in it's own section so that tools may locate it easier.
*/
+
static char cmdline[COMMAND_LINE_SIZE]
__attribute__((__section__("__builtin_cmdline")));
static int ps3_repository_read_rm_size(u64 *rm_size)
{
- s64 result;
+ int result;
u64 lpar_id;
u64 ppe_id;
u64 v2;
{
extern char __system_reset_kernel[];
- memcpy((void *)0x100, __system_reset_kernel, 0x100);
- flush_cache((void *)0x100, 0x100);
+ memcpy((void *)0x100, __system_reset_kernel, 512);
+ flush_cache((void *)0x100, 512);
}
-void platform_init(void)
+void platform_init(unsigned long null_check)
{
const u32 heapsize = 0x1000000 - (u32)_end; /* 16MiB */
void *chosen;
unsigned long ft_addr;
u64 rm_size;
+ unsigned long val;
console_ops.write = ps3_console_write;
platform_ops.exit = ps3_exit;
printf(" flat tree at 0x%lx\n\r", ft_addr);
+ val = *(unsigned long *)0;
+
+ if (val != null_check)
+ printf("null check failed: %lx != %lx\n\r", val, null_check);
+
((kernel_entry_t)0)(ft_addr, 0, NULL);
ps3_exit();
if (dt_is_compatible(devp, "ns16550"))
rc = ns16550_console_init(devp, &serial_cd);
- else if (dt_is_compatible(devp, "marvell,mpsc"))
+ else if (dt_is_compatible(devp, "marvell,mv64360-mpsc"))
rc = mpsc_console_init(devp, &serial_cd);
else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") ||
dt_is_compatible(devp, "fsl,cpm1-smc-uart") ||
--- /dev/null
+/*
+ * The simple platform -- for booting when firmware doesn't supply a device
+ * tree or any platform configuration information.
+ * All data is extracted from an embedded device tree
+ * blob.
+ *
+ * Authors: Scott Wood <scottwood@freescale.com>
+ * Grant Likely <grant.likely@secretlab.ca>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2008 Secret Lab Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "types.h"
+#include "io.h"
+#include "stdio.h"
+#include "libfdt/libfdt.h"
+
+BSS_STACK(4*1024);
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ const u32 *na, *ns, *reg, *timebase;
+ u64 memsize64;
+ int node, size, i;
+
+ /* Make sure FDT blob is sane */
+ if (fdt_check_header(_dtb_start) != 0)
+ fatal("Invalid device tree blob\n");
+
+ /* Find the #address-cells and #size-cells properties */
+ node = fdt_path_offset(_dtb_start, "/");
+ if (node < 0)
+ fatal("Cannot find root node\n");
+ na = fdt_getprop(_dtb_start, node, "#address-cells", &size);
+ if (!na || (size != 4))
+ fatal("Cannot find #address-cells property");
+ ns = fdt_getprop(_dtb_start, node, "#size-cells", &size);
+ if (!ns || (size != 4))
+ fatal("Cannot find #size-cells property");
+
+ /* Find the memory range */
+ node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+ "memory", sizeof("memory"));
+ if (node < 0)
+ fatal("Cannot find memory node\n");
+ reg = fdt_getprop(_dtb_start, node, "reg", &size);
+ if (size < (*na+*ns) * sizeof(u32))
+ fatal("cannot get memory range\n");
+
+ /* Only interested in memory based at 0 */
+ for (i = 0; i < *na; i++)
+ if (*reg++ != 0)
+ fatal("Memory range is not based at address 0\n");
+
+ /* get the memsize and trucate it to under 4G on 32 bit machines */
+ memsize64 = 0;
+ for (i = 0; i < *ns; i++)
+ memsize64 = (memsize64 << 32) | *reg++;
+ if (sizeof(void *) == 4 && memsize64 >= 0x100000000ULL)
+ memsize64 = 0xffffffff;
+
+ /* finally, setup the timebase */
+ node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+ "cpu", sizeof("cpu"));
+ if (!node)
+ fatal("Cannot find cpu node\n");
+ timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
+ if (timebase && (size == 4))
+ timebase_period_ns = 1000000000 / *timebase;
+
+ /* Now we have the memory size; initialize the heap */
+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
+
+ /* prepare the device tree and find the console */
+ fdt_init(_dtb_start);
+ serial_console_init();
+}
ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
ibm4xx_fixup_ebc_ranges("/plb/ebc");
walnut_flashsel_fixup();
- dt_fixup_mac_addresses((u8 *) WALNUT_OPENBIOS_MAC_OFF);
+ dt_fixup_mac_address_by_alias("ethernet0", (u8 *) WALNUT_OPENBIOS_MAC_OFF);
}
void platform_init(void)
--- /dev/null
+#include "ppc_asm.h"
+
+ .text
+ .global _zimage_start
+_zimage_start:
+
+ /* PPC errata 213: needed by Virtex-4 FX */
+ mfccr0 0
+ oris 0,0,0x50000000@h
+ mtccr0 0
+
+ /*
+ * Invalidate the data cache if the data cache is turned off.
+ * - The 405 core does not invalidate the data cache on power-up
+ * or reset but does turn off the data cache. We cannot assume
+ * that the cache contents are valid.
+ * - If the data cache is turned on this must have been done by
+ * a bootloader and we assume that the cache contents are
+ * valid.
+ */
+ mfdccr r9
+ cmplwi r9,0
+ bne 2f
+ lis r9,0
+ li r8,256
+ mtctr r8
+1: dccci r0,r9
+ addi r9,r9,0x20
+ bdnz 1b
+2: b _zimage_start_lib
*-mpc83*)
platformo=$object/cuboot-83xx.o
;;
- *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555)
+ *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555|*-ksi8560*)
platformo=$object/cuboot-85xx-cpm2.o
;;
*-mpc85*|*-tqm8540|*-sbc85*)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
+simpleboot-virtex405-*)
+ platformo="$object/virtex405-head.o $object/simpleboot.o"
+ binary=y
+ ;;
esac
vmz="$tmpdir/`basename \"$kernel\"`.$ext"
uboot_version="-n Linux-$version"
fi
+# physical offset of kernel image
+membase=`${CROSS}objdump -p "$kernel" | grep -m 1 LOAD | awk '{print $7}'`
+
case "$platform" in
uboot)
rm -f "$ofile"
- mkimage -A ppc -O linux -T kernel -C gzip -a 00000000 -e 00000000 \
+ mkimage -A ppc -O linux -T kernel -C gzip -a $membase -e $membase \
$uboot_version -d "$vmz" "$ofile"
if [ -z "$cacheit" ]; then
rm -f "$vmz"
exit 0
;;
ps3)
- # The ps3's loader supports loading gzipped binary images from flash
- # rom to addr zero. The loader enters the image at addr 0x100. A
- # bootwrapper overlay is use to arrange for the kernel to be loaded
- # to addr zero and to have a suitable bootwrapper entry at 0x100.
- # To construct the rom image, 0x100 bytes from offset 0x100 in the
- # kernel is copied to the bootwrapper symbol __system_reset_kernel.
- # The 0x100 bytes at the bootwrapper symbol __system_reset_overlay is
- # then copied to offset 0x100. At runtime the bootwrapper program
- # copies the 0x100 bytes at __system_reset_kernel to addr 0x100.
+ # The ps3's loader supports loading a gzipped binary image from flash
+ # rom to ram addr zero. The loader then enters the system reset
+ # vector at addr 0x100. A bootwrapper overlay is used to arrange for
+ # a binary image of the kernel to be at addr zero, and yet have a
+ # suitable bootwrapper entry at 0x100. To construct the final rom
+ # image 512 bytes from offset 0x100 is copied to the bootwrapper
+ # place holder at symbol __system_reset_kernel. The 512 bytes of the
+ # bootwrapper entry code at symbol __system_reset_overlay is then
+ # copied to offset 0x100. At runtime the bootwrapper program copies
+ # the data at __system_reset_kernel back to addr 0x100.
system_reset_overlay=0x`${CROSS}nm "$ofile" \
| grep ' __system_reset_overlay$' \
| cut -d' ' -f1`
system_reset_kernel=`printf "%d" $system_reset_kernel`
overlay_dest="256"
- overlay_size="256"
+ overlay_size="512"
${CROSS}objcopy -O binary "$ofile" "$ofile.bin"
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc1
+# Thu Feb 21 14:29:28 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+CONFIG_44x=y
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+CONFIG_4xx=y
+CONFIG_BOOKE=y
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+# CONFIG_DEFAULT_UIMAGE is not set
+CONFIG_PPC_DCR_NATIVE=y
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_PPC_DCR=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+# CONFIG_LOGBUFFER is not set
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_PPC4xx_PCI_EXPRESS=y
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_BAMBOO is not set
+# CONFIG_EBONY is not set
+# CONFIG_SEQUOIA is not set
+# CONFIG_TAISHAN is not set
+# CONFIG_KATMAI is not set
+# CONFIG_RAINIER is not set
+# CONFIG_WARP is not set
+CONFIG_CANYONLANDS=y
+CONFIG_460EX=y
+# CONFIG_IPIC is not set
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_RCU_TRACE=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+CONFIG_SECCOMP=y
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x01000000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+# CONFIG_MTD is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=35000
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_XILINX_SYSACE is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_NEW_EMAC=y
+CONFIG_IBM_NEW_EMAC_RXB=256
+CONFIG_IBM_NEW_EMAC_TXB=256
+CONFIG_IBM_NEW_EMAC_POLL_WEIGHT=32
+CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD=256
+CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0
+# CONFIG_IBM_NEW_EMAC_DEBUG is not set
+CONFIG_IBM_NEW_EMAC_ZMII=y
+CONFIG_IBM_NEW_EMAC_RGMII=y
+CONFIG_IBM_NEW_EMAC_TAH=y
+CONFIG_IBM_NEW_EMAC_EMAC4=y
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_DEBUGGER=y
+# CONFIG_KGDB is not set
+# CONFIG_XMON is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_PPC_CLOCK is not set
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:14 2008
+# Fri Apr 11 11:10:09 2008
#
# CONFIG_PPC64 is not set
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
# CONFIG_IOMMU_HELPER is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_HAS_WALK_MEMORY=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_OF_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
#
# User Modules And Translation Layers
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_NAND_FSL_ELBC is not set
+CONFIG_MTD_NAND_FSL_ELBC=y
# CONFIG_MTD_ONENAND is not set
#
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Mon Feb 11 16:25:19 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+CONFIG_PPC_85xx=y
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_E500=y
+CONFIG_BOOKE=y
+CONFIG_FSL_BOOKE=y
+CONFIG_FSL_EMB_PERFMON=y
+# CONFIG_PHYS_64BIT is not set
+CONFIG_SPE=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_MPC85xx=y
+# CONFIG_MPC8540_ADS is not set
+# CONFIG_MPC8560_ADS is not set
+# CONFIG_MPC85xx_CDS is not set
+# CONFIG_MPC85xx_MDS is not set
+# CONFIG_MPC85xx_DS is not set
+CONFIG_KSI8560=y
+# CONFIG_STX_GP3 is not set
+# CONFIG_TQM8540 is not set
+# CONFIG_TQM8541 is not set
+# CONFIG_TQM8555 is not set
+# CONFIG_TQM8560 is not set
+# CONFIG_SBC8548 is not set
+# CONFIG_SBC8560 is not set
+# CONFIG_IPIC is not set
+CONFIG_MPIC=y
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPM2=y
+CONFIG_PPC_CPM_NEW_BINDING=y
+# CONFIG_FSL_ULI1575 is not set
+CONFIG_CPM=y
+
+#
+# Kernel options
+#
+CONFIG_HIGHMEM=y
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_RCU_TRACE=y
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
+CONFIG_MATH_EMULATION=y
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_PROC_DEVICETREE is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_FSL_SOC=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_IDE=y
+CONFIG_IDE_MAX_HWIFS=4
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+# CONFIG_BLK_DEV_IDEDISK is not set
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+CONFIG_IDE_ARCH_OBSOLETE_INIT=y
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_FS_ENET=y
+# CONFIG_FS_ENET_HAS_SCC is not set
+CONFIG_FS_ENET_HAS_FCC=y
+CONFIG_FS_ENET_MDIO_FCC=y
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_GIANFAR=y
+CONFIG_GFAR_NAPI=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_CPM=y
+CONFIG_SERIAL_CPM_CONSOLE=y
+CONFIG_SERIAL_CPM_SCC1=y
+# CONFIG_SERIAL_CPM_SCC2 is not set
+# CONFIG_SERIAL_CPM_SCC3 is not set
+# CONFIG_SERIAL_CPM_SCC4 is not set
+# CONFIG_SERIAL_CPM_SMC1 is not set
+# CONFIG_SERIAL_CPM_SMC2 is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUGGER is not set
+# CONFIG_KGDB_CONSOLE is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_PPC_CLOCK is not set
+CONFIG_PPC_LIB_RHEAP=y
# CONFIG_MPC85xx_CDS is not set
# CONFIG_MPC85xx_MDS is not set
CONFIG_MPC85xx_DS=y
+# CONFIG_KSI8560 is not set
# CONFIG_STX_GP3 is not set
# CONFIG_TQM8540 is not set
# CONFIG_TQM8541 is not set
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_MISC=m
+CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_MATH_EMULATION=y
# CONFIG_IOMMU_HELPER is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
#
# on-CPU RTC drivers
#
-# CONFIG_DMADEVICES is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_FSL_DMA=y
+# CONFIG_FSL_DMA_SELFTEST is not set
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
#
# Userspace I/O
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 10:33:36 2008
+# Thu Mar 27 13:55:37 2008
#
# CONFIG_PPC64 is not set
CONFIG_LOG_BUF_SHIFT=15
# CONFIG_CGROUPS is not set
# CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y
# CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCCARD is not set
# CONFIG_HOTPLUG_PCI is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 10:36:41 2008
+# Thu Mar 27 13:55:43 2008
#
CONFIG_PPC64=y
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CGROUPS is not set
# CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y
CONFIG_PCI_MSI=y
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCCARD is not set
# CONFIG_HOTPLUG_PCI is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 10:43:46 2008
+# Thu Mar 27 13:55:45 2008
#
CONFIG_PPC64=y
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CGROUPS is not set
# CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y
# CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCCARD is not set
# CONFIG_HOTPLUG_PCI is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
CONFIG_BLK_DEV_IDECD=y
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
CONFIG_IDE_TASK_IOCTL=y
CONFIG_IDE_PROC_FS=y
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+CONFIG_SCSI_IPR=y
+CONFIG_SCSI_IPR_TRACE=y
+CONFIG_SCSI_IPR_DUMP=y
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+CONFIG_ATA=y
+CONFIG_ATA_NONSTANDARD=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIL24 is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
# CONFIG_MD is not set
# CONFIG_FUSION is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
#
# may also be needed; see USB_STORAGE Help for more information
#
+# CONFIG_USB_STORAGE is not set
# CONFIG_USB_LIBUSUAL is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
CONFIG_USB_MON=y
#
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:25 2008
+# Linux kernel version: 2.6.25-rc9
+# Tue Apr 15 18:07:36 2008
#
# CONFIG_PPC64 is not set
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_MATH_EMULATION=y
# CONFIG_IOMMU_HELPER is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
# CONFIG_FW_LOADER is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_FSL_ELBC=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=32768
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
#
# Miscellaneous I2C Chip support
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_83xx_WDT=y
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
#
# Sonics Silicon Backplane
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
#
# Graphics support
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 11:05:14 2008
+# Thu Mar 27 13:56:21 2008
#
# CONFIG_PPC64 is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
# CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y
# CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
# CONFIG_PCI_DEBUG is not set
CONFIG_PCCARD=m
# CONFIG_PCMCIA_DEBUG is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc9
+# Tue Apr 15 08:46:44 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+CONFIG_40x=y
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_4xx=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+# CONFIG_DEFAULT_UIMAGE is not set
+CONFIG_PPC_DCR_NATIVE=y
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_PPC_DCR=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+CONFIG_PPC4xx_PCI_EXPRESS=y
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_EP405=y
+CONFIG_KILAUEA=y
+CONFIG_MAKALU=y
+CONFIG_WALNUT=y
+CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y
+CONFIG_405GP=y
+CONFIG_405EX=y
+CONFIG_XILINX_VIRTEX=y
+CONFIG_XILINX_VIRTEX_II_PRO=y
+CONFIG_XILINX_VIRTEX_4_FX=y
+CONFIG_IBM405_ERR77=y
+CONFIG_IBM405_ERR51=y
+# CONFIG_IPIC is not set
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_FSL_ULI1575 is not set
+CONFIG_OF_RTC=y
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_4xx_SOC=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+# CONFIG_PCI_LEGACY is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x00400000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=35000
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_XILINX_SYSACE is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_NEW_EMAC=y
+CONFIG_IBM_NEW_EMAC_RXB=128
+CONFIG_IBM_NEW_EMAC_TXB=64
+CONFIG_IBM_NEW_EMAC_POLL_WEIGHT=32
+CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD=256
+CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0
+# CONFIG_IBM_NEW_EMAC_DEBUG is not set
+CONFIG_IBM_NEW_EMAC_ZMII=y
+CONFIG_IBM_NEW_EMAC_RGMII=y
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+CONFIG_IBM_NEW_EMAC_EMAC4=y
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+CONFIG_XILINX_HWICAP=m
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUGGER is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_PPC_CLOCK is not set
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc2
-# Fri Feb 15 21:57:35 2008
+# Linux kernel version: 2.6.25-rc6
+# Sat Apr 5 09:35:48 2008
#
# CONFIG_PPC64 is not set
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_CLASSIC_RCU=y
-# CONFIG_PREEMPT_RCU is not set
CONFIG_PPC4xx_PCI_EXPRESS=y
#
CONFIG_KATMAI=y
CONFIG_RAINIER=y
CONFIG_WARP=y
+CONFIG_CANYONLANDS=y
+CONFIG_YOSEMITE=y
CONFIG_440EP=y
CONFIG_440EPX=y
CONFIG_440GRX=y
CONFIG_440GP=y
CONFIG_440GX=y
CONFIG_440SPe=y
+CONFIG_460EX=y
CONFIG_IBM440EP_ERR42=y
# CONFIG_IPIC is not set
# CONFIG_MPIC is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
-# CONFIG_RCU_TRACE is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_MATH_EMULATION=y
#
CONFIG_ZONE_DMA=y
CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_4xx_SOC=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_SYSCALL=y
# CONFIG_INFINIBAND is not set
# CONFIG_EDAC is not set
# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
#
# Userspace I/O
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 11:06:28 2008
+# Thu Mar 27 13:56:24 2008
#
CONFIG_PPC64=y
# CONFIG_CGROUP_NS is not set
CONFIG_CPUSETS=y
# CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_RESOURCE_COUNTERS is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_KEXEC=y
# CONFIG_CRASH_DUMP is not set
+# CONFIG_PHYP_DUMP is not set
CONFIG_IRQ_ALL_CPUS=y
# CONFIG_NUMA is not set
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y
CONFIG_PCI_MSI=y
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
# CONFIG_PCI_DEBUG is not set
CONFIG_PCCARD=y
# CONFIG_PCMCIA_DEBUG is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc6
-# Thu Mar 20 11:08:01 2008
+# Thu Mar 27 13:56:28 2008
#
CONFIG_PPC64=y
CONFIG_CGROUP_NS=y
CONFIG_CPUSETS=y
# CONFIG_GROUP_SCHED is not set
-# CONFIG_USER_SCHED is not set
-# CONFIG_CGROUP_SCHED is not set
CONFIG_CGROUP_CPUACCT=y
# CONFIG_RESOURCE_COUNTERS is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_KEXEC=y
# CONFIG_CRASH_DUMP is not set
+# CONFIG_PHYP_DUMP is not set
CONFIG_IRQ_ALL_CPUS=y
CONFIG_NUMA=y
CONFIG_NODES_SHIFT=4
# CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y
CONFIG_PCI_MSI=y
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCCARD is not set
CONFIG_HOTPLUG_PCI=m
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc6
+# Thu Apr 10 18:03:25 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_6xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+CONFIG_ALTIVEC=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_LOCKBREAK=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+CONFIG_GENERIC_TBSYNC=y
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# Platform support
+#
+# CONFIG_PPC_MULTIPLATFORM is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PPC_83xx is not set
+CONFIG_PPC_86xx=y
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_MPC8641_HPCN is not set
+CONFIG_SBC8641D=y
+# CONFIG_MPC8610_HPCD is not set
+CONFIG_MPC8641=y
+# CONFIG_IPIC is not set
+CONFIG_MPIC=y
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=m
+CONFIG_FORCE_MAX_ZONEORDER=11
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_IRQ_ALL_CPUS=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_PROC_DEVICETREE is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_FSL_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+CONFIG_NETFILTER_XTABLES=m
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+# CONFIG_IP_NF_MATCH_AH is not set
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+# CONFIG_IP_NF_TARGET_TTL is not set
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+# CONFIG_IP6_NF_MATCH_AH is not set
+# CONFIG_IP6_NF_MATCH_MH is not set
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_LOG=m
+# CONFIG_IP6_NF_TARGET_REJECT is not set
+CONFIG_IP6_NF_MANGLE=m
+# CONFIG_IP6_NF_TARGET_HL is not set
+CONFIG_IP6_NF_RAW=m
+
+#
+# Bridge: Netfilter Configuration
+#
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+CONFIG_TIPC=m
+# CONFIG_TIPC_ADVANCED is not set
+# CONFIG_TIPC_DEBUG is not set
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+# CONFIG_ATM_CLIP_NO_ICMP is not set
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=m
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+# CONFIG_NET_SCH_RR is not set
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_OF_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_NOSWAP is not set
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_LE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_LINEAR=y
+CONFIG_MD_RAID0=y
+CONFIG_MD_RAID1=y
+CONFIG_MD_RAID10=y
+# CONFIG_MD_RAID456 is not set
+CONFIG_MD_MULTIPATH=y
+CONFIG_MD_FAULTY=y
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=y
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_MIRROR=y
+CONFIG_DM_ZERO=y
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_GIANFAR=y
+# CONFIG_GFAR_NAPI is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+CONFIG_ATM_DRIVERS=y
+# CONFIG_ATM_DUMMY is not set
+# CONFIG_ATM_TCP is not set
+# CONFIG_ATM_LANAI is not set
+# CONFIG_ATM_ENI is not set
+# CONFIG_ATM_FIRESTREAM is not set
+# CONFIG_ATM_ZATM is not set
+# CONFIG_ATM_NICSTAR is not set
+# CONFIG_ATM_IDT77252 is not set
+# CONFIG_ATM_AMBASSADOR is not set
+# CONFIG_ATM_HORIZON is not set
+# CONFIG_ATM_IA is not set
+# CONFIG_ATM_FORE200E_MAYBE is not set
+# CONFIG_ATM_HE is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPP_MPPE is not set
+CONFIG_PPPOE=m
+CONFIG_PPPOATM=m
+# CONFIG_PPPOL2TP is not set
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+CONFIG_SOFT_WATCHDOG=m
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+# CONFIG_REISERFS_FS_SECURITY is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+CONFIG_OCFS2_FS=m
+CONFIG_OCFS2_DEBUG_MASKLOG=y
+# CONFIG_OCFS2_DEBUG_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=m
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=m
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_NFS_DIRECTIO=y
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMB_NLS_REMOTE="cp437"
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_DEBUGGER=y
+# CONFIG_XMON is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+# CONFIG_SECURITY_NETWORK_XFRM is not set
+CONFIG_SECURITY_CAPABILITIES=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_WP512=m
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_ANUBIS=m
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_CAMELLIA is not set
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_PPC_CLOCK is not set
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_KPROBES) += kprobes.o
obj-$(CONFIG_PPC_UDBG_16550) += legacy_serial.o udbg_16550.o
+obj-$(CONFIG_STACKTRACE) += stacktrace.o
pci64-$(CONFIG_PPC64) += pci_dn.o isa-bridge.o
obj-$(CONFIG_PCI) += pci_$(CONFIG_WORD_SIZE).o $(pci64-y) \
#ifdef CONFIG_PPC64
#include <linux/time.h>
#include <linux/hardirq.h>
-#else
-#include <linux/ptrace.h>
#endif
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/hvcall.h>
#endif
+#ifdef CONFIG_PPC_ISERIES
+#include <asm/iseries/alpaca.h>
+#endif
#define DEFINE(sym, val) \
asm volatile("\n->" #sym " %0 " #val : : "i" (val))
DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context));
#else
DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
- DEFINE(PTRACE, offsetof(struct task_struct, ptrace));
#endif /* CONFIG_PPC64 */
DEFINE(KSP, offsetof(struct thread_struct, ksp));
DEFINE(PGDIR, offsetof(struct thread_struct, pgdir));
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0));
- DEFINE(PT_PTRACED, PT_PTRACED);
#endif
#ifdef CONFIG_SPE
DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0]));
DEFINE(PAGE_OFFSET_VSID, KERNEL_VSID(PAGE_OFFSET));
DEFINE(VMALLOC_START_ESID, GET_ESID(VMALLOC_START));
DEFINE(VMALLOC_START_VSID, KERNEL_VSID(VMALLOC_START));
+
+ /* alpaca */
+ DEFINE(ALPACA_SIZE, sizeof(struct alpaca));
#endif
DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
#include <linux/string.h>
#include <linux/init.h>
#include <linux/module.h>
+#include <linux/lmb.h>
#include <asm/sections.h>
#include <asm/prom.h>
#include <asm/mmu.h>
#include <asm/pgtable.h>
#include <asm/io.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
#include <asm/processor.h>
#include <asm/udbg.h>
* Valentine Barshak <vbarshak@ru.mvista.com>
* MontaVista Software, Inc (c) 2007
*
- * Based on cpu_setup_6xx code by
+ * Based on cpu_setup_6xx code by
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
*
* This program is free software; you can redistribute it and/or
bl __fixup_440A_mcheck
mtlr r4
blr
+_GLOBAL(__setup_cpu_460ex)
+_GLOBAL(__setup_cpu_460gt)
+ b __init_fpu_44x
_GLOBAL(__setup_cpu_440gx)
_GLOBAL(__setup_cpu_440spe)
b __fixup_440A_mcheck
extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
+extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
+extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
.machine_check = machine_check_440A,
.platform = "ppc440",
},
+ { /* 460EX */
+ .pvr_mask = 0xffff0002,
+ .pvr_value = 0x13020002,
+ .cpu_name = "460EX",
+ .cpu_features = CPU_FTRS_44X,
+ .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ .cpu_setup = __setup_cpu_460ex,
+ .machine_check = machine_check_440A,
+ .platform = "ppc440",
+ },
+ { /* 460GT */
+ .pvr_mask = 0xffff0002,
+ .pvr_value = 0x13020000,
+ .cpu_name = "460GT",
+ .cpu_features = CPU_FTRS_44X,
+ .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ .cpu_setup = __setup_cpu_460gt,
+ .machine_check = machine_check_440A,
+ .platform = "ppc440",
+ },
#endif /* CONFIG_44x */
#ifdef CONFIG_FSL_BOOKE
#ifdef CONFIG_E200
*t = *s;
*PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
#if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
- /* ppc64 and booke expect identify_cpu to also call
+ /* ppc64 and booke expect identify_cpu to also call
* setup_cpu for that processor. I will consolidate
* that at a later time, for now, just use #ifdef.
* we also don't need to PTRRELOC the function pointer
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/types.h>
+#include <linux/lmb.h>
#include <asm/processor.h>
#include <asm/machdep.h>
#include <asm/kexec.h>
#include <asm/kdump.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
#include <asm/firmware.h>
#include <asm/smp.h>
#include <asm/system.h>
#include <linux/crash_dump.h>
#include <linux/bootmem.h>
+#include <linux/lmb.h>
#include <asm/kdump.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
#include <asm/firmware.h>
#include <asm/uaccess.h>
stw r11,PT_REGS(r12)
#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
/* Check to see if the dbcr0 register is set up to debug. Use the
- single-step bit to do this. */
+ internal debug mode bit to do this. */
lwz r12,THREAD_DBCR0(r12)
- andis. r12,r12,DBCR0_IC@h
+ andis. r12,r12,DBCR0_IDM@h
beq+ 3f
/* From user and task is ptraced - load up global dbcr0 */
li r12,-1 /* clear all pending debug events */
lis r11,global_dbcr0@ha
tophys(r11,r11)
addi r11,r11,global_dbcr0@l
+#ifdef CONFIG_SMP
+ rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
+ lwz r9,TI_CPU(r9)
+ slwi r9,r9,3
+ add r11,r11,r9
+#endif
lwz r12,0(r11)
mtspr SPRN_DBCR0,r12
lwz r12,4(r11)
stw r11,_CCR(r1)
syscall_exit_cont:
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
- /* If the process has its own DBCR0 value, load it up. The single
- step bit tells us that dbcr0 should be loaded. */
+ /* If the process has its own DBCR0 value, load it up. The internal
+ debug mode bit tells us that dbcr0 should be loaded. */
lwz r0,THREAD+THREAD_DBCR0(r2)
- andis. r10,r0,DBCR0_IC@h
+ andis. r10,r0,DBCR0_IDM@h
bnel- load_dbcr0
#endif
#ifdef CONFIG_44x
restore_user:
#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
- /* Check whether this process has its own DBCR0 value. The single
- step bit tells us that dbcr0 should be loaded. */
+ /* Check whether this process has its own DBCR0 value. The internal
+ debug mode bit tells us that dbcr0 should be loaded. */
lwz r0,THREAD+THREAD_DBCR0(r2)
- andis. r10,r0,DBCR0_IC@h
+ andis. r10,r0,DBCR0_IDM@h
bnel- load_dbcr0
#endif
mfspr r10,SPRN_DBCR0
lis r11,global_dbcr0@ha
addi r11,r11,global_dbcr0@l
+#ifdef CONFIG_SMP
+ rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
+ lwz r9,TI_CPU(r9)
+ slwi r9,r9,3
+ add r11,r11,r9
+#endif
stw r10,0(r11)
mtspr SPRN_DBCR0,r0
lwz r10,4(r11)
.section .bss
.align 4
global_dbcr0:
- .space 8
+ .space 8*NR_CPUS
.previous
#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
#include <asm/cputable.h>
#include <asm/firmware.h>
#include <asm/bug.h>
+#include <asm/ptrace.h>
+#include <asm/irqflags.h>
/*
* System calls.
/* This value is used to mark exception frames on the stack. */
exception_marker:
- .tc ID_72656773_68657265[TC],0x7265677368657265
+ .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
.section ".text"
.align 7
addi r9,r1,STACK_FRAME_OVERHEAD
ld r11,exception_marker@toc(r2)
std r11,-16(r9) /* "regshere" marker */
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl .trace_hardirqs_on
+ REST_GPR(0,r1)
+ REST_4GPRS(3,r1)
+ REST_2GPRS(7,r1)
+ addi r9,r1,STACK_FRAME_OVERHEAD
+ ld r12,_MSR(r1)
+#endif /* CONFIG_TRACE_IRQFLAGS */
li r10,1
stb r10,PACASOFTIRQEN(r13)
stb r10,PACAHARDIRQEN(r13)
b hardware_interrupt_entry
2:
END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif
+#endif /* CONFIG_PPC_ISERIES */
mfmsr r11
ori r11,r11,MSR_EE
mtmsrd r11,1
li r3,0
stb r3,PACASOFTIRQEN(r13) /* ensure we are soft-disabled */
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl .trace_hardirqs_off
+ mfmsr r10
+#endif
ori r10,r10,MSR_EE
mtmsrd r10 /* hard-enable again */
addi r3,r1,STACK_FRAME_OVERHEAD
4:
END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
#endif
- stb r5,PACASOFTIRQEN(r13)
+ TRACE_AND_RESTORE_IRQ(r5);
/* extract EE bit and use it to restore paca->hard_enabled */
ld r3,_MSR(r1)
bne restore
/* here we are preempting the current task */
1:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl .trace_hardirqs_on
+ /* Note: we just clobbered r10 which used to contain the previous
+ * MSR before the hard-disabling done by the caller of do_work.
+ * We don't have that value anymore, but it doesn't matter as
+ * we will hard-enable unconditionally, we can just reload the
+ * current MSR into r10
+ */
+ mfmsr r10
+#endif /* CONFIG_TRACE_IRQFLAGS */
li r0,1
stb r0,PACASOFTIRQEN(r13)
stb r0,PACAHARDIRQEN(r13)
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
+#include <asm/ptrace.h>
/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
#define LOAD_BAT(n, reg, RA, RB) \
li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
MTMSRD(r10); /* (except for mach check in rtas) */ \
stw r0,GPR0(r11); \
- lis r10,0x7265; /* put exception frame marker */ \
- addi r10,r10,0x6773; \
+ lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
+ addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
stw r10,8(r11); \
SAVE_4GPRS(3, r11); \
SAVE_2GPRS(7, r11)
/* we haven't used ctr or xer or lr */
b fast_exception_return
-/*
- * AltiVec unavailable trap from kernel - print a message, but let
- * the task use AltiVec in the kernel until it returns to user mode.
- */
-KernelAltiVec:
- lwz r3,_MSR(r1)
- oris r3,r3,MSR_VEC@h
- stw r3,_MSR(r1) /* enable use of AltiVec after return */
- lis r3,87f@h
- ori r3,r3,87f@l
- mr r4,r2 /* current */
- lwz r5,_NIP(r1)
- bl printk
- b ret_from_except
-87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
- .align 4,0
-
/*
* giveup_altivec(tsk)
* Disable AltiVec for the task given as the argument,
SET_IVOR(12, WatchdogTimer);
SET_IVOR(13, DataTLBError);
SET_IVOR(14, InstructionTLBError);
- SET_IVOR(15, Debug);
+ SET_IVOR(15, DebugCrit);
/* Establish the interrupt vector base */
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
b InstructionStorage
/* Debug Interrupt */
- DEBUG_EXCEPTION
+ DEBUG_CRIT_EXCEPTION
/*
* Local functions
#include <asm/firmware.h>
#include <asm/page_64.h>
#include <asm/exception.h>
-
-#define DO_SOFT_DISABLE
+#include <asm/irqflags.h>
/*
* We layout physical memory as follows:
*/
fast_exc_return_irq: /* restores irq state too */
ld r3,SOFTE(r1)
+ TRACE_AND_RESTORE_IRQ(r3);
ld r12,_MSR(r1)
- stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */
rldicl r4,r12,49,63 /* get MSR_EE to LSB */
stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
b 1f
mtlr r10
andi. r10,r12,MSR_RI /* check for unrecoverable exception */
- beq- unrecov_slb
+ beq- 2f
.machine push
.machine "power4"
rfid
b . /* prevent speculative execution */
+2:
+#ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
+ b unrecov_slb
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
+#endif /* CONFIG_PPC_ISERIES */
+ mfspr r11,SPRN_SRR0
+ clrrdi r10,r13,32
+ LOAD_HANDLER(r10,unrecov_slb)
+ mtspr SPRN_SRR0,r10
+ mfmsr r10
+ ori r10,r10,MSR_IR|MSR_DR|MSR_RI
+ mtspr SPRN_SRR1,r10
+ rfid
+ b .
+
unrecov_slb:
EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
DISABLE_INTS
* Hash table stuff
*/
.align 7
-_GLOBAL(do_hash_page)
+_STATIC(do_hash_page)
std r3,_DAR(r1)
std r4,_DSISR(r1)
bne- do_ste_alloc /* If so handle it */
END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+ /*
+ * On iSeries, we soft-disable interrupts here, then
+ * hard-enable interrupts so that the hash_page code can spin on
+ * the hash_table_lock without problems on a shared processor.
+ */
+ DISABLE_INTS
+
+ /*
+ * Currently, trace_hardirqs_off() will be called by DISABLE_INTS
+ * and will clobber volatile registers when irq tracing is enabled
+ * so we need to reload them. It may be possible to be smarter here
+ * and move the irq tracing elsewhere but let's keep it simple for
+ * now
+ */
+#ifdef CONFIG_TRACE_IRQFLAGS
+ ld r3,_DAR(r1)
+ ld r4,_DSISR(r1)
+ ld r5,_TRAP(r1)
+ ld r12,_MSR(r1)
+ clrrdi r5,r5,4
+#endif /* CONFIG_TRACE_IRQFLAGS */
/*
* We need to set the _PAGE_USER bit if MSR_PR is set or if we are
* accessing a userspace segment (even from the kernel). We assume
ori r4,r4,1 /* add _PAGE_PRESENT */
rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
- /*
- * On iSeries, we soft-disable interrupts here, then
- * hard-enable interrupts so that the hash_page code can spin on
- * the hash_table_lock without problems on a shared processor.
- */
- DISABLE_INTS
-
/*
* r3 contains the faulting address
* r4 contains the required access permissions
bl .hash_page /* build HPTE if possible */
cmpdi r3,0 /* see if hash_page succeeded */
-#ifdef DO_SOFT_DISABLE
BEGIN_FW_FTR_SECTION
/*
* If we had interrupts soft-enabled at the point where the
*/
beq 13f
END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif
+
BEGIN_FW_FTR_SECTION
/*
* Here we have interrupts hard-disabled, so it is sufficient
/*
* hash_page couldn't handle it, set soft interrupt enable back
- * to what it was before the trap. Note that .local_irq_restore
+ * to what it was before the trap. Note that .raw_local_irq_restore
* handles any interrupts pending at this point.
*/
ld r3,SOFTE(r1)
- bl .local_irq_restore
+ TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f)
+ bl .raw_local_irq_restore
b 11f
/* Here we have a page fault that hash_page can't handle. */
addi r2,r2,0x4000
add r2,r2,r26
+ /* Set initial ptr to current */
+ LOAD_REG_IMMEDIATE(r4, init_task)
+ std r4,PACACURRENT(r13)
+
/* Do very early kernel initializations, including initial hash table,
* stab and slb setup before we turn on relocation. */
li r0,0
stdu r0,-STACK_FRAME_OVERHEAD(r1)
- /* ptr to current */
- LOAD_REG_IMMEDIATE(r4, init_task)
- std r4,PACACURRENT(r13)
-
/* Load the TOC */
ld r2,PACATOC(r13)
std r1,PACAKSAVE(r13)
* is necessary since the MMU is always on, for Book-E parts, and the stacks
* are offset from KERNELBASE.
*
+ * There is some space optimization to be had here if desired. However
+ * to allow for a common kernel with support for debug exceptions either
+ * going to critical or their own debug level we aren't currently
+ * providing configurations that micro-optimize space usage.
*/
-#define BOOKE_EXCEPTION_STACK_SIZE (8192)
+#ifdef CONFIG_44x
+#define NUM_EXCEPTION_LVLS 2
+#else
+#define NUM_EXCEPTION_LVLS 3
+#endif
+#define BOOKE_EXCEPTION_STACK_SIZE (4096 * NUM_EXCEPTION_LVLS)
/* CRIT_SPRG only used in critical exception handling */
#define CRIT_SPRG SPRN_SPRG2
#define CRIT_STACK_TOP (exception_stack_top)
/* only on e200 for now */
-#define DEBUG_STACK_TOP (exception_stack_top - 4096)
+#define DEBUG_STACK_TOP (exception_stack_top - 8192)
#define DEBUG_SPRG SPRN_SPRG6W
#ifdef CONFIG_SMP
* save (and later restore) the MSR via SPRN_CSRR1, which will still have
* the MSR_DE bit set.
*/
-#ifdef CONFIG_E200
-#define DEBUG_EXCEPTION \
- START_EXCEPTION(Debug); \
+#define DEBUG_DEBUG_EXCEPTION \
+ START_EXCEPTION(DebugDebug); \
DEBUG_EXCEPTION_PROLOG; \
\
/* \
cmplw r12,r10; \
blt+ 2f; /* addr below exception vectors */ \
\
- lis r10,Debug@h; \
- ori r10,r10,Debug@l; \
+ lis r10,DebugDebug@h; \
+ ori r10,r10,DebugDebug@l; \
cmplw r12,r10; \
bgt+ 2f; /* addr above exception vectors */ \
\
2: mfspr r4,SPRN_DBSR; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
-#else
-#define DEBUG_EXCEPTION \
- START_EXCEPTION(Debug); \
+
+#define DEBUG_CRIT_EXCEPTION \
+ START_EXCEPTION(DebugCrit); \
CRITICAL_EXCEPTION_PROLOG; \
\
/* \
cmplw r12,r10; \
blt+ 2f; /* addr below exception vectors */ \
\
- lis r10,Debug@h; \
- ori r10,r10,Debug@l; \
+ lis r10,DebugCrit@h; \
+ ori r10,r10,DebugCrit@l; \
cmplw r12,r10; \
bgt+ 2f; /* addr above exception vectors */ \
\
2: mfspr r4,SPRN_DBSR; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
-#endif
#define INSTRUCTION_STORAGE_EXCEPTION \
START_EXCEPTION(InstructionStorage) \
mr r29,r5
mr r28,r6
mr r27,r7
+ li r25,0 /* phys kernel start (low) */
li r24,0 /* CPU number */
+ li r23,0 /* phys kernel start (high) */
/* We try to not make any assumptions about how the boot loader
* setup or used the TLBs. We invalidate all mappings from the
mtspr SPRN_MAS0,r7
tlbre
- /* Just modify the entry ID, EPN and RPN for the temp mapping */
+ /* grab and fixup the RPN */
+ mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
+ rlwinm r6,r6,25,27,30
+ li r8,-1
+ addi r6,r6,10
+ slw r6,r8,r6 /* convert to mask */
+
+ bl 1f /* Find our address */
+1: mflr r7
+
+ mfspr r8,SPRN_MAS3
+#ifdef CONFIG_PHYS_64BIT
+ mfspr r23,SPRN_MAS7
+#endif
+ and r8,r6,r8
+ subfic r9,r6,-4096
+ and r9,r9,r7
+
+ or r25,r8,r9
+ ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
+
+ /* Just modify the entry ID and EPN for the temp mapping */
lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
mtspr SPRN_MAS0,r7
ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
mtspr SPRN_MAS1,r6
mfspr r6,SPRN_MAS2
- lis r7,PHYSICAL_START@h
+ li r7,0 /* temp EPN = 0 */
rlwimi r7,r6,0,20,31
mtspr SPRN_MAS2,r7
- mfspr r6,SPRN_MAS3
- rlwimi r7,r6,0,20,31
- mtspr SPRN_MAS3,r7
+ mtspr SPRN_MAS3,r8
tlbwe
xori r6,r4,1
ori r6,r6,PAGE_OFFSET@l
rlwimi r6,r7,0,20,31
mtspr SPRN_MAS2,r6
- li r7,(MAS3_SX|MAS3_SW|MAS3_SR)
- mtspr SPRN_MAS3,r7
+ mtspr SPRN_MAS3,r8
tlbwe
/* 7. Jump to KERNELBASE mapping */
SET_IVOR(12, WatchdogTimer);
SET_IVOR(13, DataTLBError);
SET_IVOR(14, InstructionTLBError);
- SET_IVOR(15, Debug);
+ SET_IVOR(15, DebugDebug);
+#if defined(CONFIG_E500)
+ SET_IVOR(15, DebugCrit);
+#endif
SET_IVOR(32, SPEUnavailable);
SET_IVOR(33, SPEFloatingPointData);
SET_IVOR(34, SPEFloatingPointRound);
/* Debug Interrupt */
- DEBUG_EXCEPTION
+ DEBUG_DEBUG_EXCEPTION
+#if defined(CONFIG_E500)
+ DEBUG_CRIT_EXCEPTION
+#endif
/*
* Local functions
ret = ibmebus_create_device(child);
if (ret) {
printk(KERN_ERR "%s: failed to create device (%i)",
- __FUNCTION__, ret);
+ __func__, ret);
of_node_put(child);
break;
}
if (bus_find_device(&ibmebus_bus_type, NULL, path,
ibmebus_match_path)) {
printk(KERN_WARNING "%s: %s has already been probed\n",
- __FUNCTION__, path);
+ __func__, path);
rc = -EEXIST;
goto out;
}
of_node_put(dn);
} else {
printk(KERN_WARNING "%s: no such device node: %s\n",
- __FUNCTION__, path);
+ __func__, path);
rc = -ENODEV;
}
return count;
} else {
printk(KERN_WARNING "%s: %s not on the bus\n",
- __FUNCTION__, path);
+ __func__, path);
kfree(path);
return -ENODEV;
err = of_bus_type_init(&ibmebus_bus_type, "ibmebus");
if (err) {
printk(KERN_ERR "%s: failed to register IBM eBus.\n",
- __FUNCTION__);
+ __func__);
return err;
}
err = device_register(&ibmebus_bus_device);
if (err) {
printk(KERN_WARNING "%s: device_register returned %i\n",
- __FUNCTION__, err);
+ __func__, err);
bus_unregister(&ibmebus_bus_type);
return err;
unsigned int order;
if (!tbl || !tbl->it_map) {
- printk(KERN_ERR "%s: expected TCE map for %s\n", __FUNCTION__,
+ printk(KERN_ERR "%s: expected TCE map for %s\n", __func__,
node_name);
return;
}
for (i = 0; i < (tbl->it_size/64); i++) {
if (tbl->it_map[i] != 0) {
printk(KERN_WARNING "%s: Unexpected TCEs for %s\n",
- __FUNCTION__, node_name);
+ __func__, node_name);
break;
}
}
: : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled)));
}
-void local_irq_restore(unsigned long en)
+void raw_local_irq_restore(unsigned long en)
{
/*
* get_paca()->soft_enabled = en;
__hard_irq_enable();
}
+EXPORT_SYMBOL(raw_local_irq_restore);
#endif /* CONFIG_PPC64 */
int show_interrupts(struct seq_file *p, void *v)
handler = &__do_IRQ;
irqtp->task = curtp->task;
irqtp->flags = 0;
+
+ /* Copy the softirq bits in preempt_count so that the
+ * softirq checks work in the hardirq context.
+ */
+ irqtp->preempt_count =
+ (irqtp->preempt_count & ~SOFTIRQ_MASK) |
+ (curtp->preempt_count & SOFTIRQ_MASK);
+
call_handle_irq(irq, desc, irqtp, handler);
irqtp->task = NULL;
+
+
+ /* Set any flag that may have been set on the
+ * alternate stack
+ */
if (irqtp->flags)
set_bits(irqtp->flags, &curtp->flags);
} else
memset((void *)softirq_ctx[i], 0, THREAD_SIZE);
tp = softirq_ctx[i];
tp->cpu = i;
- tp->preempt_count = SOFTIRQ_OFFSET;
+ tp->preempt_count = 0;
memset((void *)hardirq_ctx[i], 0, THREAD_SIZE);
tp = hardirq_ctx[i];
* (size depending on dev->n_addr_cells)
* cell 5: the size of the range
*/
- if ((range->isa_addr.a_hi && ISA_SPACE_MASK) != ISA_SPACE_IO) {
+ if ((range->isa_addr.a_hi & ISA_SPACE_MASK) != ISA_SPACE_IO) {
range++;
rlen -= sizeof(struct isa_range);
if (rlen < sizeof(struct isa_range))
goto inval_range;
}
- if ((range->isa_addr.a_hi && ISA_SPACE_MASK) != ISA_SPACE_IO)
+ if ((range->isa_addr.a_hi & ISA_SPACE_MASK) != ISA_SPACE_IO)
goto inval_range;
isa_addr = range->isa_addr.a_lo;
*/
if ((pci_addr != 0) || (isa_addr != 0)) {
printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
- __FUNCTION__);
+ __func__);
return;
}
unsigned char *local_buffer = kmalloc(SPLPAR_MAXLENGTH, GFP_KERNEL);
if (!local_buffer) {
printk(KERN_ERR "%s %s kmalloc failure at line %d \n",
- __FILE__, __FUNCTION__, __LINE__);
+ __FILE__, __func__, __LINE__);
return;
}
if (call_status != 0) {
printk(KERN_INFO
"%s %s Error calling get-system-parameter (0x%x)\n",
- __FILE__, __FUNCTION__, call_status);
+ __FILE__, __func__, call_status);
} else {
int splpar_strlen;
int idx, w_idx;
char *workbuffer = kzalloc(SPLPAR_MAXLENGTH, GFP_KERNEL);
if (!workbuffer) {
printk(KERN_ERR "%s %s kmalloc failure at line %d \n",
- __FILE__, __FUNCTION__, __LINE__);
+ __FILE__, __func__, __LINE__);
kfree(local_buffer);
return;
}
current_weight = (resource >> 5 * 8) & 0xFF;
pr_debug("%s: current_entitled = %lu, current_weight = %u\n",
- __FUNCTION__, current_entitled, current_weight);
+ __func__, current_entitled, current_weight);
pr_debug("%s: new_entitled = %lu, new_weight = %u\n",
- __FUNCTION__, *new_entitled_ptr, *new_weight_ptr);
+ __func__, *new_entitled_ptr, *new_weight_ptr);
retval = plpar_hcall_norets(H_SET_PPP, *new_entitled_ptr,
*new_weight_ptr);
retval = -EINVAL;
} else {
printk(KERN_WARNING "%s: received unknown hv return code %ld",
- __FUNCTION__, retval);
+ __func__, retval);
retval = -EIO;
}
#include <linux/kexec.h>
#include <linux/reboot.h>
#include <linux/threads.h>
+#include <linux/lmb.h>
#include <asm/machdep.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
void machine_crash_shutdown(struct pt_regs *regs)
{
#include <asm/ptrace.h>
#include <asm/page.h>
#include <asm/lppaca.h>
-#include <asm/iseries/it_lp_reg_save.h>
#include <asm/paca.h>
#include <asm/mmu.h>
extern unsigned long __toc_start;
/*
- * iSeries structure which the hypervisor knows about - this structure
+ * The structure which the hypervisor knows about - this structure
* should not cross a page boundary. The vpa_init/register_vpa call
* is now known to fail if the lppaca structure crosses a page
- * boundary. The lppaca is also used on POWER5 pSeries boxes. The
- * lppaca is 640 bytes long, and cannot readily change since the
- * hypervisor knows its layout, so a 1kB alignment will suffice to
- * ensure that it doesn't cross a page boundary.
+ * boundary. The lppaca is also used on legacy iSeries and POWER5
+ * pSeries boxes. The lppaca is 640 bytes long, and cannot readily
+ * change since the hypervisor knows its layout, so a 1kB alignment
+ * will suffice to ensure that it doesn't cross a page boundary.
*/
struct lppaca lppaca[] = {
[0 ... (NR_CPUS-1)] = {
* processors. The processor VPD array needs one entry per physical
* processor (not thread).
*/
-#define PACA_INIT_COMMON(number) \
+#define PACA_INIT(number) \
+{ \
.lppaca_ptr = &lppaca[number], \
.lock_token = 0x8000, \
.paca_index = (number), /* Paca Index */ \
.kernel_toc = (unsigned long)(&__toc_start) + 0x8000UL, \
.hw_cpu_id = 0xffff, \
- .slb_shadow_ptr = &slb_shadow[number],
-
-#ifdef CONFIG_PPC_ISERIES
-#define PACA_INIT_ISERIES(number) \
- .reg_save_ptr = &iseries_reg_save[number],
-
-#define PACA_INIT(number) \
-{ \
- PACA_INIT_COMMON(number) \
- PACA_INIT_ISERIES(number) \
+ .slb_shadow_ptr = &slb_shadow[number], \
+ .__current = &init_task, \
}
-#else
-#define PACA_INIT(number) \
-{ \
- PACA_INIT_COMMON(number) \
-}
-
-#endif
-
struct paca_struct paca[] = {
PACA_INIT(0),
#if NR_CPUS > 1
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
if (ppc_md.pcibios_enable_device_hook)
if (ppc_md.pcibios_enable_device_hook(dev))
return -EINVAL;
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1 << idx)))
- continue;
- r = &dev->resource[idx];
- if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
- continue;
- if ((idx == PCI_ROM_RESOURCE) &&
- (!(r->flags & IORESOURCE_ROM_ENABLE)))
- continue;
- if (r->parent == NULL) {
- printk(KERN_ERR "PCI: Device %s not available because"
- " of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
+ return pci_enable_resources(dev, mask);
}
-
struct mcontext32 uc_mcontext;
};
+extern int copy_siginfo_to_user32(struct compat_siginfo __user *d, siginfo_t *s);
+
#endif /* _PPC64_PPC32_H */
#include <asm/signal.h>
#include <asm/dcr.h>
-#ifdef CONFIG_PPC64
-EXPORT_SYMBOL(local_irq_restore);
-#endif
-
#ifdef CONFIG_PPC32
extern void transfer_to_handler(void);
extern void do_IRQ(struct pt_regs *regs);
extern void single_step_exception(struct pt_regs *regs);
extern int sys_sigreturn(struct pt_regs *regs);
-EXPORT_SYMBOL(empty_zero_page);
EXPORT_SYMBOL(clear_pages);
EXPORT_SYMBOL(copy_page);
EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
EXPORT_SYMBOL(strcat);
EXPORT_SYMBOL(strlen);
EXPORT_SYMBOL(strcmp);
+EXPORT_SYMBOL(strncmp);
EXPORT_SYMBOL(csum_partial);
EXPORT_SYMBOL(csum_partial_copy_generic);
EXPORT_SYMBOL(__mtdcr);
EXPORT_SYMBOL(__mfdcr);
#endif
+EXPORT_SYMBOL(empty_zero_page);
flush_spe_to_thread(current);
error = do_execve(filename, (char __user * __user *) a1,
(char __user * __user *) a2, regs);
- if (error == 0) {
- task_lock(current);
- current->ptrace &= ~PT_DTRACE;
- task_unlock(current);
- }
putname(filename);
out:
return error;
return valid_irq_stack(sp, p, nbytes);
}
-#ifdef CONFIG_PPC64
-#define MIN_STACK_FRAME 112 /* same as STACK_FRAME_OVERHEAD, in fact */
-#define FRAME_LR_SAVE 2
-#define INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD + 288)
-#define REGS_MARKER 0x7265677368657265ul
-#define FRAME_MARKER 12
-#else
-#define MIN_STACK_FRAME 16
-#define FRAME_LR_SAVE 1
-#define INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
-#define REGS_MARKER 0x72656773ul
-#define FRAME_MARKER 2
-#endif
-
EXPORT_SYMBOL(validate_sp);
unsigned long get_wchan(struct task_struct *p)
return 0;
sp = p->thread.ksp;
- if (!validate_sp(sp, p, MIN_STACK_FRAME))
+ if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
return 0;
do {
sp = *(unsigned long *)sp;
- if (!validate_sp(sp, p, MIN_STACK_FRAME))
+ if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
return 0;
if (count > 0) {
- ip = ((unsigned long *)sp)[FRAME_LR_SAVE];
+ ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
if (!in_sched_functions(ip))
return ip;
}
lr = 0;
printk("Call Trace:\n");
do {
- if (!validate_sp(sp, tsk, MIN_STACK_FRAME))
+ if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
return;
stack = (unsigned long *) sp;
newsp = stack[0];
- ip = stack[FRAME_LR_SAVE];
+ ip = stack[STACK_FRAME_LR_SAVE];
if (!firstframe || ip != lr) {
printk("["REG"] ["REG"] ", sp, ip);
print_symbol("%s", ip);
* See if this is an exception frame.
* We look for the "regshere" marker in the current frame.
*/
- if (validate_sp(sp, tsk, INT_FRAME_SIZE)
- && stack[FRAME_MARKER] == REGS_MARKER) {
+ if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
+ && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
struct pt_regs *regs = (struct pt_regs *)
(sp + STACK_FRAME_OVERHEAD);
printk("--- Exception: %lx", regs->trap);
#include <linux/kexec.h>
#include <linux/debugfs.h>
#include <linux/irq.h>
+#include <linux/lmb.h>
#include <asm/prom.h>
#include <asm/rtas.h>
-#include <asm/lmb.h>
#include <asm/page.h>
#include <asm/processor.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/pSeries_reconfig.h>
#include <asm/pci-bridge.h>
+#include <asm/phyp_dump.h>
#include <asm/kexec.h>
#ifdef DEBUG
* The device tree may be allocated beyond our memory limit, or inside the
* crash kernel region for kdump. If so, move it out of the way.
*/
-static void move_device_tree(void)
+static void __init move_device_tree(void)
{
unsigned long start, size;
void *p;
#endif
}
+#ifdef CONFIG_PHYP_DUMP
+/**
+ * phyp_dump_calculate_reserve_size() - reserve variable boot area 5% or arg
+ *
+ * Function to find the largest size we need to reserve
+ * during early boot process.
+ *
+ * It either looks for boot param and returns that OR
+ * returns larger of 256 or 5% rounded down to multiples of 256MB.
+ *
+ */
+static inline unsigned long phyp_dump_calculate_reserve_size(void)
+{
+ unsigned long tmp;
+
+ if (phyp_dump_info->reserve_bootvar)
+ return phyp_dump_info->reserve_bootvar;
+
+ /* divide by 20 to get 5% of value */
+ tmp = lmb_end_of_DRAM();
+ do_div(tmp, 20);
+
+ /* round it down in multiples of 256 */
+ tmp = tmp & ~0x0FFFFFFFUL;
+
+ return (tmp > PHYP_DUMP_RMR_END ? tmp : PHYP_DUMP_RMR_END);
+}
+
+/**
+ * phyp_dump_reserve_mem() - reserve all not-yet-dumped mmemory
+ *
+ * This routine may reserve memory regions in the kernel only
+ * if the system is supported and a dump was taken in last
+ * boot instance or if the hardware is supported and the
+ * scratch area needs to be setup. In other instances it returns
+ * without reserving anything. The memory in case of dump being
+ * active is freed when the dump is collected (by userland tools).
+ */
+static void __init phyp_dump_reserve_mem(void)
+{
+ unsigned long base, size;
+ unsigned long variable_reserve_size;
+
+ if (!phyp_dump_info->phyp_dump_configured) {
+ printk(KERN_ERR "Phyp-dump not supported on this hardware\n");
+ return;
+ }
+
+ if (!phyp_dump_info->phyp_dump_at_boot) {
+ printk(KERN_INFO "Phyp-dump disabled at boot time\n");
+ return;
+ }
+
+ variable_reserve_size = phyp_dump_calculate_reserve_size();
+
+ if (phyp_dump_info->phyp_dump_is_active) {
+ /* Reserve *everything* above RMR.Area freed by userland tools*/
+ base = variable_reserve_size;
+ size = lmb_end_of_DRAM() - base;
+
+ /* XXX crashed_ram_end is wrong, since it may be beyond
+ * the memory_limit, it will need to be adjusted. */
+ lmb_reserve(base, size);
+
+ phyp_dump_info->init_reserve_start = base;
+ phyp_dump_info->init_reserve_size = size;
+ } else {
+ size = phyp_dump_info->cpu_state_size +
+ phyp_dump_info->hpte_region_size +
+ variable_reserve_size;
+ base = lmb_end_of_DRAM() - size;
+ lmb_reserve(base, size);
+ phyp_dump_info->init_reserve_start = base;
+ phyp_dump_info->init_reserve_size = size;
+ }
+}
+#else
+static inline void __init phyp_dump_reserve_mem(void) {}
+#endif /* CONFIG_PHYP_DUMP && CONFIG_PPC_RTAS */
+
+
void __init early_init_devtree(void *params)
{
DBG(" -> early_init_devtree(%p)\n", params);
of_scan_flat_dt(early_init_dt_scan_rtas, NULL);
#endif
+#ifdef CONFIG_PHYP_DUMP
+ /* scan tree to see if dump occured during last boot */
+ of_scan_flat_dt(early_init_dt_scan_phyp_dump, NULL);
+#endif
+
/* Retrieve various informations from the /chosen node of the
* device-tree, including the platform type, initrd location and
* size, TCE reserve, and more ...
reserve_kdump_trampoline();
reserve_crashkernel();
early_reserve_mem();
+ phyp_dump_reserve_mem();
lmb_enforce_memory_limit(memory_limit);
lmb_analyze();
*/
void of_attach_node(struct device_node *np)
{
- write_lock(&devtree_lock);
+ unsigned long flags;
+
+ write_lock_irqsave(&devtree_lock, flags);
np->sibling = np->parent->child;
np->allnext = allnodes;
np->parent->child = np;
allnodes = np;
- write_unlock(&devtree_lock);
+ write_unlock_irqrestore(&devtree_lock, flags);
}
/*
void of_detach_node(struct device_node *np)
{
struct device_node *parent;
+ unsigned long flags;
- write_lock(&devtree_lock);
+ write_lock_irqsave(&devtree_lock, flags);
parent = np->parent;
if (!parent)
of_node_set_flag(np, OF_DETACHED);
out_unlock:
- write_unlock(&devtree_lock);
+ write_unlock_irqrestore(&devtree_lock, flags);
}
#ifdef CONFIG_PPC_PSERIES
int prom_add_property(struct device_node* np, struct property* prop)
{
struct property **next;
+ unsigned long flags;
prop->next = NULL;
- write_lock(&devtree_lock);
+ write_lock_irqsave(&devtree_lock, flags);
next = &np->properties;
while (*next) {
if (strcmp(prop->name, (*next)->name) == 0) {
/* duplicate ! don't insert it */
- write_unlock(&devtree_lock);
+ write_unlock_irqrestore(&devtree_lock, flags);
return -1;
}
next = &(*next)->next;
}
*next = prop;
- write_unlock(&devtree_lock);
+ write_unlock_irqrestore(&devtree_lock, flags);
#ifdef CONFIG_PROC_DEVICETREE
/* try to add to proc as well if it was initialized */
int prom_remove_property(struct device_node *np, struct property *prop)
{
struct property **next;
+ unsigned long flags;
int found = 0;
- write_lock(&devtree_lock);
+ write_lock_irqsave(&devtree_lock, flags);
next = &np->properties;
while (*next) {
if (*next == prop) {
}
next = &(*next)->next;
}
- write_unlock(&devtree_lock);
+ write_unlock_irqrestore(&devtree_lock, flags);
if (!found)
return -ENODEV;
struct property *oldprop)
{
struct property **next;
+ unsigned long flags;
int found = 0;
- write_lock(&devtree_lock);
+ write_lock_irqsave(&devtree_lock, flags);
next = &np->properties;
while (*next) {
if (*next == oldprop) {
}
next = &(*next)->next;
}
- write_unlock(&devtree_lock);
+ write_unlock_irqrestore(&devtree_lock, flags);
if (!found)
return -ENODEV;
if (rv != PROM_ERROR && (strcmp(prop, "chrp") == 0))
prom_setprop(node, "/", "device_type", "efika", sizeof("efika"));
+ /* CODEGEN,description is exposed in /proc/cpuinfo so
+ fix that too */
+ rv = prom_getprop(node, "CODEGEN,description", prop, sizeof(prop));
+ if (rv != PROM_ERROR && (strstr(prop, "CHRP")))
+ prom_setprop(node, "/", "CODEGEN,description",
+ "Efika 5200B PowerPC System",
+ sizeof("Efika 5200B PowerPC System"));
+
/* Fixup bestcomm interrupts property */
node = call_prom("finddevice", 1, 1, ADDR("/builtin/bestcomm"));
if (PHANDLE_VALID(node)) {
#include <linux/security.h>
#include <linux/signal.h>
#include <linux/compat.h>
+#include <linux/elf.h>
#include <asm/uaccess.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
+#include "ppc32.h"
+
/*
* does not yet catch signals sent when the child dies.
* in exit.c or in signal.c.
return -EPERM;
}
+static int compat_ptrace_getsiginfo(struct task_struct *child, compat_siginfo_t __user *data)
+{
+ siginfo_t lastinfo;
+ int error = -ESRCH;
+
+ read_lock(&tasklist_lock);
+ if (likely(child->sighand != NULL)) {
+ error = -EINVAL;
+ spin_lock_irq(&child->sighand->siglock);
+ if (likely(child->last_siginfo != NULL)) {
+ lastinfo = *child->last_siginfo;
+ error = 0;
+ }
+ spin_unlock_irq(&child->sighand->siglock);
+ }
+ read_unlock(&tasklist_lock);
+ if (!error)
+ return copy_siginfo_to_user32(data, &lastinfo);
+ return error;
+}
+
long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
compat_ulong_t caddr, compat_ulong_t cdata)
{
0, PT_REGS_COUNT * sizeof(compat_long_t),
compat_ptr(data));
+ case PTRACE_GETSIGINFO:
+ return compat_ptrace_getsiginfo(child, compat_ptr(data));
+
case PTRACE_GETFPREGS:
case PTRACE_SETFPREGS:
case PTRACE_GETVRREGS:
#include <linux/smp.h>
#include <linux/completion.h>
#include <linux/cpumask.h>
+#include <linux/lmb.h>
#include <asm/prom.h>
#include <asm/rtas.h>
#include <asm/hvcall.h>
-#include <asm/semaphore.h>
#include <asm/machdep.h>
#include <asm/firmware.h>
#include <asm/page.h>
#include <asm/system.h>
#include <asm/delay.h>
#include <asm/uaccess.h>
-#include <asm/lmb.h>
#include <asm/udbg.h>
#include <asm/syscalls.h>
#include <asm/smp.h>
break;
default:
printk(KERN_ERR "%s: unexpected RTAS error %d\n",
- __FUNCTION__, rtas_rc);
+ __func__, rtas_rc);
rc = -ERANGE;
break;
}
rtas_block_ctor);
if (!flash_block_cache) {
printk(KERN_ERR "%s: failed to create block cache\n",
- __FUNCTION__);
+ __func__);
rc = -ENOMEM;
goto cleanup;
}
return 0;
}
-static int of_device_available(struct device_node * dn)
-{
- const char *status;
-
- status = of_get_property(dn, "status", NULL);
-
- if (!status)
- return 1;
-
- if (!strcmp(status, "okay"))
- return 1;
-
- return 0;
-}
-
int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
{
int returnval = -1;
for (dn = busdn->child; dn; dn = dn->sibling) {
struct pci_dn *pdn = PCI_DN(dn);
if (pdn && pdn->devfn == devfn
- && of_device_available(dn))
+ && of_device_is_available(dn))
return rtas_read_config(pdn, where, size, val);
}
for (dn = busdn->child; dn; dn = dn->sibling) {
struct pci_dn *pdn = PCI_DN(dn);
if (pdn && pdn->devfn == devfn
- && of_device_available(dn))
+ && of_device_is_available(dn))
return rtas_write_config(pdn, where, size, val);
}
return PCIBIOS_DEVICE_NOT_FOUND;
res = b->resource[0];
if (!res->flags) {
- printk(KERN_ERR "%s: no IO resource for PHB %s\n", __FUNCTION__,
+ printk(KERN_ERR "%s: no IO resource for PHB %s\n", __func__,
b->name);
return 1;
}
rc = pcibios_unmap_io_space(b);
if (rc) {
printk(KERN_ERR "%s: failed to unmap IO on bus %s\n",
- __FUNCTION__, b->name);
+ __func__, b->name);
return 1;
}
if (release_resource(res)) {
printk(KERN_ERR "%s: failed to release IO on bus %s\n",
- __FUNCTION__, b->name);
+ __func__, b->name);
return 1;
}
res = b->resource[i];
if (!res->flags && i == 0) {
printk(KERN_ERR "%s: no MEM resource for PHB %s\n",
- __FUNCTION__, b->name);
+ __func__, b->name);
return 1;
}
if (res->flags && release_resource(res)) {
printk(KERN_ERR
"%s: failed to release IO %d on bus %s\n",
- __FUNCTION__, i, b->name);
+ __func__, i, b->name);
return 1;
}
}
#include <linux/serial_8250.h>
#include <linux/debugfs.h>
#include <linux/percpu.h>
+#include <linux/lmb.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/page.h>
#include <asm/mmu.h>
-#include <asm/lmb.h>
#include <asm/xmon.h>
#include <asm/cputhreads.h>
unsigned short min;
if (cpu_id == NR_CPUS) {
+ struct device_node *root;
+ const char *model = NULL;
#if defined(CONFIG_SMP) && defined(CONFIG_PPC32)
unsigned long bogosum = 0;
int i;
seq_printf(m, "timebase\t: %lu\n", ppc_tb_freq);
if (ppc_md.name)
seq_printf(m, "platform\t: %s\n", ppc_md.name);
+ root = of_find_node_by_path("/");
+ if (root)
+ model = of_get_property(root, "model", NULL);
+ if (model)
+ seq_printf(m, "model\t\t: %s\n", model);
+ of_node_put(root);
+
if (ppc_md.show_cpuinfo != NULL)
ppc_md.show_cpuinfo(m);
}
__setup("l2cr=", ppc_setup_l2cr);
+/* Checks "l3cr=xxxx" command-line option */
+int __init ppc_setup_l3cr(char *str)
+{
+ if (cpu_has_feature(CPU_FTR_L3CR)) {
+ unsigned long val = simple_strtoul(str, NULL, 0);
+ printk(KERN_INFO "l3cr set to %lx\n", val);
+ _set_L3CR(val); /* and enable it */
+ }
+ return 1;
+}
+__setup("l3cr=", ppc_setup_l3cr);
+
#ifdef CONFIG_GENERIC_NVRAM
/* Generic nvram hooks used by drivers/char/gen_nvram.c */
if (ppc_md.panic)
setup_panic();
- init_mm.start_code = PAGE_OFFSET;
+ init_mm.start_code = (unsigned long)_stext;
init_mm.end_code = (unsigned long) _etext;
init_mm.end_data = (unsigned long) _edata;
init_mm.brk = klimit;
#include <linux/serial_8250.h>
#include <linux/bootmem.h>
#include <linux/pci.h>
+#include <linux/lockdep.h>
+#include <linux/lmb.h>
#include <asm/io.h>
#include <asm/kdump.h>
#include <asm/prom.h>
#include <asm/cache.h>
#include <asm/page.h>
#include <asm/mmu.h>
-#include <asm/lmb.h>
#include <asm/firmware.h>
#include <asm/xmon.h>
#include <asm/udbg.h>
/* Enable early debugging if any specified (see udbg.h) */
udbg_early_init();
+ /* Initialize lockdep early or else spinlocks will blow */
+ lockdep_init();
+
DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
/*
if (ppc_md.panic)
setup_panic();
- init_mm.start_code = PAGE_OFFSET;
+ init_mm.start_code = (unsigned long)_stext;
init_mm.end_code = (unsigned long) _etext;
init_mm.end_data = (unsigned long) _edata;
init_mm.brk = klimit;
#define copy_siginfo_to_user copy_siginfo_to_user32
+int copy_siginfo_from_user32(siginfo_t *to, struct compat_siginfo __user *from)
+{
+ memset(to, 0, sizeof *to);
+
+ if (copy_from_user(to, from, 3*sizeof(int)) ||
+ copy_from_user(to->_sifields._pad,
+ from->_sifields._pad, SI_PAD_SIZE32))
+ return -EFAULT;
+
+ return 0;
+}
+
/*
* Note: it is necessary to treat pid and sig as unsigned ints, with the
* corresponding cast to a signed int to insure that the proper conversion
int ret;
mm_segment_t old_fs = get_fs();
- if (copy_from_user (&info, uinfo, 3*sizeof(int)) ||
- copy_from_user (info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE32))
- return -EFAULT;
+ ret = copy_siginfo_from_user32(&info, uinfo);
+ if (unlikely(ret))
+ return ret;
+
set_fs (KERNEL_DS);
/* The __user pointer cast is valid becasuse of the set_fs() */
ret = sys_rt_sigqueueinfo((int)pid, (int)sig, (siginfo_t __user *) &info);
--- /dev/null
+/*
+ * Stack trace utility
+ *
+ * Copyright 2008 Christoph Hellwig, IBM Corp.
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/sched.h>
+#include <linux/stacktrace.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+
+/*
+ * Save stack-backtrace addresses into a stack_trace buffer.
+ */
+void save_stack_trace(struct stack_trace *trace)
+{
+ unsigned long sp;
+
+ asm("mr %0,1" : "=r" (sp));
+
+ for (;;) {
+ unsigned long *stack = (unsigned long *) sp;
+ unsigned long newsp, ip;
+
+ if (!validate_sp(sp, current, STACK_FRAME_OVERHEAD))
+ return;
+
+ newsp = stack[0];
+ ip = stack[STACK_FRAME_LR_SAVE];
+
+ if (!trace->skip)
+ trace->entries[trace->nr_entries++] = ip;
+ else
+ trace->skip--;
+
+ if (trace->nr_entries >= trace->max_entries)
+ return;
+
+ sp = newsp;
+ }
+}
#include <asm/types.h>
#include <asm/uaccess.h>
#include <asm/unistd.h>
-#include <asm/semaphore.h>
#include <asm/time.h>
#include <asm/mmu_context.h>
#include <asm/ppc-pci.h>
error = compat_do_execve(filename, compat_ptr(a1), compat_ptr(a2), regs);
- if (error == 0) {
- task_lock(current);
- current->ptrace &= ~PT_DTRACE;
- task_unlock(current);
- }
putname(filename);
out:
#include <linux/personality.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <asm/syscalls.h>
#include <asm/time.h>
#include <asm/unistd.h>
#include <linux/elf.h>
#include <linux/security.h>
#include <linux/bootmem.h>
+#include <linux/lmb.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/mmu_context.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/cputable.h>
#include <asm/sections.h>
*/
int vio_register_driver(struct vio_driver *viodrv)
{
- printk(KERN_DEBUG "%s: driver %s registering\n", __FUNCTION__,
+ printk(KERN_DEBUG "%s: driver %s registering\n", __func__,
viodrv->driver.name);
/* fill in 'struct driver' fields */
/* we need the 'device_type' property, in order to match with drivers */
if (of_node->type == NULL) {
printk(KERN_WARNING "%s: node %s missing 'device_type'\n",
- __FUNCTION__,
+ __func__,
of_node->name ? of_node->name : "<unknown>");
return NULL;
}
unit_address = of_get_property(of_node, "reg", NULL);
if (unit_address == NULL) {
printk(KERN_WARNING "%s: node %s missing 'reg'\n",
- __FUNCTION__,
+ __func__,
of_node->name ? of_node->name : "<unknown>");
return NULL;
}
/* register with generic device framework */
if (device_register(&viodev->dev)) {
printk(KERN_ERR "%s: failed to register device %s\n",
- __FUNCTION__, viodev->dev.bus_id);
+ __func__, viodev->dev.bus_id);
/* XXX free TCE table */
kfree(viodev);
return NULL;
err = device_register(&vio_bus_device.dev);
if (err) {
printk(KERN_WARNING "%s: device_register returned %i\n",
- __FUNCTION__, err);
+ __func__, err);
return err;
}
#ifdef CONFIG_PPC64
-#include <asm/page.h>
#define PROVIDE32(x) PROVIDE(__unused__##x)
#else
-#define PAGE_SIZE 4096
-#define KERNELBASE CONFIG_KERNEL_START
#define PROVIDE32(x) PROVIDE(x)
#endif
+#include <asm/page.h>
#include <asm-generic/vmlinux.lds.h>
#include <asm/cache.h>
*/
/* Text and gots */
- .text : {
+ .text : AT(ADDR(.text) - LOAD_OFFSET) {
ALIGN_FUNCTION();
*(.text.head)
_text = .;
RODATA
/* Exception & bug tables */
- __ex_table : {
+ __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
__start___ex_table = .;
*(__ex_table)
__stop___ex_table = .;
. = ALIGN(PAGE_SIZE);
__init_begin = .;
- .init.text : {
+ .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
_sinittext = .;
INIT_TEXT
_einittext = .;
/* .exit.text is discarded at runtime, not link time,
* to deal with references from __bug_table
*/
- .exit.text : {
+ .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) {
EXIT_TEXT
}
- .init.data : {
+ .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) {
INIT_DATA
__vtop_table_begin = .;
*(.vtop_fixup);
}
. = ALIGN(16);
- .init.setup : {
+ .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
__setup_start = .;
*(.init.setup)
__setup_end = .;
}
- .initcall.init : {
+ .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) {
__initcall_start = .;
INITCALLS
__initcall_end = .;
}
- .con_initcall.init : {
+ .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) {
__con_initcall_start = .;
*(.con_initcall.init)
__con_initcall_end = .;
SECURITY_INIT
. = ALIGN(8);
- __ftr_fixup : {
+ __ftr_fixup : AT(ADDR(__ftr_fixup) - LOAD_OFFSET) {
__start___ftr_fixup = .;
*(__ftr_fixup)
__stop___ftr_fixup = .;
}
#ifdef CONFIG_PPC64
. = ALIGN(8);
- __fw_ftr_fixup : {
+ __fw_ftr_fixup : AT(ADDR(__fw_ftr_fixup) - LOAD_OFFSET) {
__start___fw_ftr_fixup = .;
*(__fw_ftr_fixup)
__stop___fw_ftr_fixup = .;
#endif
#ifdef CONFIG_BLK_DEV_INITRD
. = ALIGN(PAGE_SIZE);
- .init.ramfs : {
+ .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
__initramfs_start = .;
*(.init.ramfs)
__initramfs_end = .;
}
#endif
. = ALIGN(PAGE_SIZE);
- .data.percpu : {
+ .data.percpu : AT(ADDR(.data.percpu) - LOAD_OFFSET) {
__per_cpu_start = .;
*(.data.percpu)
*(.data.percpu.shared_aligned)
}
. = ALIGN(8);
- .machine.desc : {
+ .machine.desc : AT(ADDR(.machine.desc) - LOAD_OFFSET) {
__machine_desc_start = . ;
*(.machine.desc)
__machine_desc_end = . ;
_sdata = .;
#ifdef CONFIG_PPC32
- .data :
- {
+ .data : AT(ADDR(.data) - LOAD_OFFSET) {
DATA_DATA
*(.sdata)
*(.got.plt) *(.got)
}
#else
- .data : {
+ .data : AT(ADDR(.data) - LOAD_OFFSET) {
DATA_DATA
*(.data.rel*)
*(.toc1)
*(.branch_lt)
}
- .opd : {
+ .opd : AT(ADDR(.opd) - LOAD_OFFSET) {
*(.opd)
}
- .got : {
+ .got : AT(ADDR(.got) - LOAD_OFFSET) {
__toc_start = .;
*(.got)
*(.toc)
#else
. = ALIGN(16384);
#endif
- .data.init_task : {
+ .data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET) {
*(.data.init_task)
}
. = ALIGN(PAGE_SIZE);
- .data.page_aligned : {
+ .data.page_aligned : AT(ADDR(.data.page_aligned) - LOAD_OFFSET) {
*(.data.page_aligned)
}
- .data.cacheline_aligned : {
+ .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) {
*(.data.cacheline_aligned)
}
. = ALIGN(L1_CACHE_BYTES);
- .data.read_mostly : {
+ .data.read_mostly : AT(ADDR(.data.read_mostly) - LOAD_OFFSET) {
*(.data.read_mostly)
}
. = ALIGN(PAGE_SIZE);
- __data_nosave : {
+ .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) {
__nosave_begin = .;
*(.data.nosave)
. = ALIGN(PAGE_SIZE);
* And finally the bss
*/
- .bss : {
+ .bss : AT(ADDR(.bss) - LOAD_OFFSET) {
__bss_start = .;
*(.sbss) *(.scommon)
*(.dynbss)
new_blocks = max_blocks - info->max_blocks;
- block = kmalloc(sizeof(rh_block_t) * max_blocks, GFP_KERNEL);
+ block = kmalloc(sizeof(rh_block_t) * max_blocks, GFP_ATOMIC);
if (block == NULL)
return -ENOMEM;
if ((alignment & (alignment - 1)) != 0)
return ERR_PTR(-EINVAL);
- info = kmalloc(sizeof(*info), GFP_KERNEL);
+ info = kmalloc(sizeof(*info), GFP_ATOMIC);
if (info == NULL)
return ERR_PTR(-ENOMEM);
beq 1b
blr
+_GLOBAL(strncmp)
+ PPC_LCMPI r5,0
+ beqlr
+ mtctr r5
+ addi r5,r3,-1
+ addi r4,r4,-1
+1: lbzu r3,1(r5)
+ cmpwi 1,r3,0
+ lbzu r0,1(r4)
+ subf. r3,r0,r3
+ beqlr 1
+ bdnzt eq,1b
+ blr
+
_GLOBAL(strlen)
addi r4,r3,-1
1: lbzu r0,1(r4)
frD[1] = frB[1];
#ifdef DEBUG
- printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+ printk("%s: D %p, B %p: ", __func__, frD, frB);
dump_double(frD);
printk("\n");
#endif
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+ printk("%s: %p %p %p\n", __func__, frD, frA, frB);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+ printk("%s: %p %p %p\n", __func__, frD, frA, frB);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p (%08x) %d %p %p\n", __FUNCTION__, ccr, *ccr, crfD, frA, frB);
+ printk("%s: %p (%08x) %d %p %p\n", __func__, ccr, *ccr, crfD, frA, frB);
#endif
__FP_UNPACK_D(A, frA);
long cmp;
#ifdef DEBUG
- printk("%s: %p (%08x) %d %p %p\n", __FUNCTION__, ccr, *ccr, crfD, frA, frB);
+ printk("%s: %p (%08x) %d %p %p\n", __func__, ccr, *ccr, crfD, frA, frB);
#endif
__FP_UNPACK_D(A, frA);
frD[1] = r;
#ifdef DEBUG
- printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+ printk("%s: D %p, B %p: ", __func__, frD, frB);
dump_double(frD);
printk("\n");
#endif
__FPU_FPSCR = fpscr;
#ifdef DEBUG
- printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+ printk("%s: D %p, B %p: ", __func__, frD, frB);
dump_double(frD);
printk("\n");
#endif
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+ printk("%s: %p %p %p\n", __func__, frD, frA, frB);
#endif
__FP_UNPACK_D(A, frA);
if (A_c == FP_CLS_ZERO && B_c == FP_CLS_ZERO) {
ret |= EFLAG_VXZDZ;
#ifdef DEBUG
- printk("%s: FPSCR_VXZDZ raised\n", __FUNCTION__);
+ printk("%s: FPSCR_VXZDZ raised\n", __func__);
#endif
}
if (A_c == FP_CLS_INF && B_c == FP_CLS_INF) {
ret |= EFLAG_VXIDI;
#ifdef DEBUG
- printk("%s: FPSCR_VXIDI raised\n", __FUNCTION__);
+ printk("%s: FPSCR_VXIDI raised\n", __func__);
#endif
}
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+ printk("%s: %p %p %p\n", __func__, frD, frA, frB);
#endif
__FP_UNPACK_D(A, frA);
if (A_c == FP_CLS_ZERO && B_c == FP_CLS_ZERO) {
ret |= EFLAG_VXZDZ;
#ifdef DEBUG
- printk("%s: FPSCR_VXZDZ raised\n", __FUNCTION__);
+ printk("%s: FPSCR_VXZDZ raised\n", __func__);
#endif
}
if (A_c == FP_CLS_INF && B_c == FP_CLS_INF) {
ret |= EFLAG_VXIDI;
#ifdef DEBUG
- printk("%s: FPSCR_VXIDI raised\n", __FUNCTION__);
+ printk("%s: FPSCR_VXIDI raised\n", __func__);
#endif
}
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+ printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+ printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
#endif
__FP_UNPACK_D(A, frA);
frD[1] = frB[1];
#ifdef DEBUG
- printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+ printk("%s: D %p, B %p: ", __func__, frD, frB);
dump_double(frD);
printk("\n");
#endif
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+ printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+ printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+ printk("%s: %p %p %p\n", __func__, frD, frA, frB);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+ printk("%s: %p %p %p\n", __func__, frD, frA, frB);
#endif
__FP_UNPACK_D(A, frA);
frD[1] = frB[1];
#ifdef DEBUG
- printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+ printk("%s: D %p, B %p: ", __func__, frD, frB);
dump_double(frD);
printk("\n");
#endif
frD[1] = frB[1];
#ifdef DEBUG
- printk("%s: D %p, B %p: ", __FUNCTION__, frD, frB);
+ printk("%s: D %p, B %p: ", __func__, frD, frB);
dump_double(frD);
printk("\n");
#endif
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+ printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+ printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+ printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+ printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
#endif
__FP_UNPACK_D(A, frA);
fres(void *frD, void *frB)
{
#ifdef DEBUG
- printk("%s: %p %p\n", __FUNCTION__, frD, frB);
+ printk("%s: %p %p\n", __func__, frD, frB);
#endif
return -ENOSYS;
}
FP_DECL_D(B);
#ifdef DEBUG
- printk("%s: D %p, B %p\n", __FUNCTION__, frD, frB);
+ printk("%s: D %p, B %p\n", __func__, frD, frB);
#endif
__FP_UNPACK_D(B, frB);
frsqrte(void *frD, void *frB)
{
#ifdef DEBUG
- printk("%s: %p %p\n", __FUNCTION__, frD, frB);
+ printk("%s: %p %p\n", __func__, frD, frB);
#endif
return 0;
}
FP_DECL_D(A);
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frA, frB, frC);
+ printk("%s: %p %p %p %p\n", __func__, frD, frA, frB, frC);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frB);
+ printk("%s: %p %p %p %p\n", __func__, frD, frB);
#endif
__FP_UNPACK_D(B, frB);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p %p\n", __FUNCTION__, frD, frB);
+ printk("%s: %p %p %p %p\n", __func__, frD, frB);
#endif
__FP_UNPACK_D(B, frB);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+ printk("%s: %p %p %p\n", __func__, frD, frA, frB);
#endif
__FP_UNPACK_D(A, frA);
int ret = 0;
#ifdef DEBUG
- printk("%s: %p %p %p\n", __FUNCTION__, frD, frA, frB);
+ printk("%s: %p %p %p\n", __func__, frD, frA, frB);
#endif
__FP_UNPACK_D(A, frA);
if (copy_from_user(frD, ea, sizeof(double)))
return -EFAULT;
#ifdef DEBUG
- printk("%s: D %p, ea %p: ", __FUNCTION__, frD, ea);
+ printk("%s: D %p, ea %p: ", __func__, frD, ea);
dump_double(frD);
printk("\n");
#endif
float f;
#ifdef DEBUG
- printk("%s: D %p, ea %p\n", __FUNCTION__, frD, ea);
+ printk("%s: D %p, ea %p\n", __func__, frD, ea);
#endif
if (copy_from_user(&f, ea, sizeof(float)))
u32 value, clear;
#ifdef DEBUG
- printk("%s: %p (%08x) %d %d\n", __FUNCTION__, ccr, *ccr, crfD, crfS);
+ printk("%s: %p (%08x) %d %d\n", __func__, ccr, *ccr, crfD, crfS);
#endif
clear = 15 << ((7 - crfS) << 2);
*ccr |= (value << ((7 - crfD) << 2));
#ifdef DEBUG
- printk("CR: %08x\n", __FUNCTION__, *ccr);
+ printk("CR: %08x\n", __func__, *ccr);
#endif
return 0;
frD[1] = __FPU_FPSCR;
#ifdef DEBUG
- printk("%s: frD %p: %08x.%08x\n", __FUNCTION__, frD, frD[0], frD[1]);
+ printk("%s: frD %p: %08x.%08x\n", __func__, frD, frD[0], frD[1]);
#endif
return 0;
__FPU_FPSCR &= ~(1 << (31 - crbD));
#ifdef DEBUG
- printk("%s: %d %08lx\n", __FUNCTION__, crbD, __FPU_FPSCR);
+ printk("%s: %d %08lx\n", __func__, crbD, __FPU_FPSCR);
#endif
return 0;
__FPU_FPSCR |= (1 << (31 - crbD));
#ifdef DEBUG
- printk("%s: %d %08lx\n", __FUNCTION__, crbD, __FPU_FPSCR);
+ printk("%s: %d %08lx\n", __func__, crbD, __FPU_FPSCR);
#endif
return 0;
__FPU_FPSCR |= (frB[1] & mask);
#ifdef DEBUG
- printk("%s: %02x %p: %08lx\n", __FUNCTION__, FM, frB, __FPU_FPSCR);
+ printk("%s: %02x %p: %08lx\n", __func__, FM, frB, __FPU_FPSCR);
#endif
return 0;
__FPU_FPSCR |= (IMM & 0xf) << ((7 - crfD) << 2);
#ifdef DEBUG
- printk("%s: %d %x: %08lx\n", __FUNCTION__, crfD, IMM, __FPU_FPSCR);
+ printk("%s: %d %x: %08lx\n", __func__, crfD, IMM, __FPU_FPSCR);
#endif
return 0;
{
#if 0
#ifdef DEBUG
- printk("%s: S %p, ea %p: ", __FUNCTION__, frS, ea);
+ printk("%s: S %p, ea %p: ", __func__, frS, ea);
dump_double(frS);
printk("\n");
#endif
stfiwx(u32 *frS, void *ea)
{
#ifdef DEBUG
- printk("%s: %p %p\n", __FUNCTION__, frS, ea);
+ printk("%s: %p %p\n", __func__, frS, ea);
#endif
if (copy_to_user(ea, &frS[1], sizeof(frS[1])))
int err;
#ifdef DEBUG
- printk("%s: S %p, ea %p\n", __FUNCTION__, frS, ea);
+ printk("%s: S %p, ea %p\n", __func__, frS, ea);
#endif
__FP_UNPACK_D(A, frS);
phys_addr_t p;
v = KERNELBASE;
- p = PPC_MEMSTART;
+ p = 0;
s = total_lowmem;
if (__map_without_ltlbs)
/* Pin in enough TLBs to cover any lowmem not covered by the
* initial 256M mapping established in head_44x.S */
- for (addr = PPC_PIN_SIZE; addr < total_lowmem;
+ for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
addr += PPC_PIN_SIZE)
ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
EXTRA_CFLAGS += -mno-minimal-toc
endif
-obj-y := fault.o mem.o lmb.o \
+obj-y := fault.o mem.o \
init_$(CONFIG_WORD_SIZE).o \
pgtable_$(CONFIG_WORD_SIZE).o \
mmu_context_$(CONFIG_WORD_SIZE).o
#include <asm/mmu.h>
#include <asm/uaccess.h>
#include <asm/smp.h>
-#include <asm/bootx.h>
#include <asm/machdep.h>
#include <asm/setup.h>
+#include "mmu_decl.h"
+
extern void loadcam_entry(unsigned int index);
unsigned int tlbcam_index;
unsigned int num_tlbcam_entries;
static unsigned long __cam0, __cam1, __cam2;
-extern unsigned long total_lowmem;
-extern unsigned long __max_low_memory;
-extern unsigned long __initial_memory_limit;
-#define MAX_LOW_MEM CONFIG_LOWMEM_SIZE
#define NUM_TLBCAMS (16)
void __init cam_mapin_ram(unsigned long cam0, unsigned long cam1,
unsigned long cam2)
{
- settlbcam(0, PAGE_OFFSET, PPC_MEMSTART, cam0, _PAGE_KERNEL, 0);
+ settlbcam(0, PAGE_OFFSET, memstart_addr, cam0, _PAGE_KERNEL, 0);
tlbcam_index++;
if (cam1) {
tlbcam_index++;
- settlbcam(1, PAGE_OFFSET+cam0, PPC_MEMSTART+cam0, cam1, _PAGE_KERNEL, 0);
+ settlbcam(1, PAGE_OFFSET+cam0, memstart_addr+cam0, cam1, _PAGE_KERNEL, 0);
}
if (cam2) {
tlbcam_index++;
- settlbcam(2, PAGE_OFFSET+cam0+cam1, PPC_MEMSTART+cam0+cam1, cam2, _PAGE_KERNEL, 0);
+ settlbcam(2, PAGE_OFFSET+cam0+cam1, memstart_addr+cam0+cam1, cam2, _PAGE_KERNEL, 0);
}
}
void __init
adjust_total_lowmem(void)
{
- unsigned long max_low_mem = MAX_LOW_MEM;
- unsigned long cam_max = 0x10000000;
- unsigned long ram;
+ phys_addr_t max_lowmem_size = __max_low_memory;
+ phys_addr_t cam_max_size = 0x10000000;
+ phys_addr_t ram;
- /* adjust CAM size to max_low_mem */
- if (max_low_mem < cam_max)
- cam_max = max_low_mem;
+ /* adjust CAM size to max_lowmem_size */
+ if (max_lowmem_size < cam_max_size)
+ cam_max_size = max_lowmem_size;
- /* adjust lowmem size to max_low_mem */
- if (max_low_mem < total_lowmem)
- ram = max_low_mem;
- else
- ram = total_lowmem;
+ /* adjust lowmem size to max_lowmem_size */
+ ram = min(max_lowmem_size, total_lowmem);
/* Calculate CAM values */
__cam0 = 1UL << 2 * (__ilog2(ram) / 2);
- if (__cam0 > cam_max)
- __cam0 = cam_max;
+ if (__cam0 > cam_max_size)
+ __cam0 = cam_max_size;
ram -= __cam0;
if (ram) {
__cam1 = 1UL << 2 * (__ilog2(ram) / 2);
- if (__cam1 > cam_max)
- __cam1 = cam_max;
+ if (__cam1 > cam_max_size)
+ __cam1 = cam_max_size;
ram -= __cam1;
}
if (ram) {
__cam2 = 1UL << 2 * (__ilog2(ram) / 2);
- if (__cam2 > cam_max)
- __cam2 = cam_max;
+ if (__cam2 > cam_max_size)
+ __cam2 = cam_max_size;
ram -= __cam2;
}
" CAM2=%ldMb residual: %ldMb\n",
__cam0 >> 20, __cam1 >> 20, __cam2 >> 20,
(total_lowmem - __cam0 - __cam1 - __cam2) >> 20);
- __max_low_memory = max_low_mem = __cam0 + __cam1 + __cam2;
- __initial_memory_limit = __max_low_memory;
+ __max_low_memory = __cam0 + __cam1 + __cam2;
+ __initial_memory_limit_addr = memstart_addr + __max_low_memory;
}
#include <linux/cache.h>
#include <linux/init.h>
#include <linux/signal.h>
+#include <linux/lmb.h>
#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
#include <asm/abs_addr.h>
#include <asm/tlbflush.h>
#include <asm/io.h>
return ret < 0 ? ret : 0;
}
+#ifdef CONFIG_MEMORY_HOTPLUG
+static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
+ int psize, int ssize)
+{
+ unsigned long vaddr;
+ unsigned int step, shift;
+
+ shift = mmu_psize_defs[psize].shift;
+ step = 1 << shift;
+
+ if (!ppc_md.hpte_removebolted) {
+ printk(KERN_WARNING "Platform doesn't implement "
+ "hpte_removebolted\n");
+ return -EINVAL;
+ }
+
+ for (vaddr = vstart; vaddr < vend; vaddr += step)
+ ppc_md.hpte_removebolted(vaddr, psize, ssize);
+
+ return 0;
+}
+#endif /* CONFIG_MEMORY_HOTPLUG */
+
static int __init htab_dt_scan_seg_sizes(unsigned long node,
const char *uname, int depth,
void *data)
_PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
mmu_linear_psize, mmu_kernel_ssize));
}
+
+int remove_section_mapping(unsigned long start, unsigned long end)
+{
+ return htab_remove_mapping(start, end, mmu_linear_psize,
+ mmu_kernel_ssize);
+}
#endif /* CONFIG_MEMORY_HOTPLUG */
static inline void make_bl(unsigned int *insn_addr, void *func)
#include <linux/highmem.h>
#include <linux/initrd.h>
#include <linux/pagemap.h>
+#include <linux/lmb.h>
#include <asm/pgalloc.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/btext.h>
#include <asm/tlb.h>
-#include <asm/lmb.h>
#include <asm/sections.h>
#include "mmu_decl.h"
unsigned long total_memory;
unsigned long total_lowmem;
-unsigned long ppc_memstart;
-unsigned long ppc_memoffset = PAGE_OFFSET;
+phys_addr_t memstart_addr;
+phys_addr_t lowmem_end_addr;
int boot_mapsize;
#ifdef CONFIG_PPC_PMAC
unsigned long __max_low_memory = MAX_LOW_MEM;
/*
- * limit of what is accessible with initial MMU setup -
+ * address of the limit of what is accessible with initial MMU setup -
* 256MB usually, but only 16MB on 601.
*/
-unsigned long __initial_memory_limit = 0x10000000;
+phys_addr_t __initial_memory_limit_addr = (phys_addr_t)0x10000000;
/*
* Check for command-line options that affect what MMU_init will do.
/* 601 can only access 16MB at the moment */
if (PVR_VER(mfspr(SPRN_PVR)) == 1)
- __initial_memory_limit = 0x01000000;
+ __initial_memory_limit_addr = 0x01000000;
/* 8xx can only access 8MB at the moment */
if (PVR_VER(mfspr(SPRN_PVR)) == 0x50)
- __initial_memory_limit = 0x00800000;
+ __initial_memory_limit_addr = 0x00800000;
/* parse args from command line */
MMU_setup();
printk(KERN_WARNING "Only using first contiguous memory region");
}
- total_memory = lmb_end_of_DRAM();
- total_lowmem = total_memory;
+ total_lowmem = total_memory = lmb_end_of_DRAM() - memstart_addr;
+ lowmem_end_addr = memstart_addr + total_lowmem;
#ifdef CONFIG_FSL_BOOKE
/* Freescale Book-E parts expect lowmem to be mapped by fixed TLB
if (total_lowmem > __max_low_memory) {
total_lowmem = __max_low_memory;
+ lowmem_end_addr = memstart_addr + total_lowmem;
#ifndef CONFIG_HIGHMEM
total_memory = total_lowmem;
- lmb_enforce_memory_limit(total_lowmem);
+ lmb_enforce_memory_limit(lowmem_end_addr);
lmb_analyze();
#endif /* CONFIG_HIGHMEM */
}
/* Map in I/O resources */
if (ppc_md.progress)
ppc_md.progress("MMU:setio", 0x302);
- if (ppc_md.setup_io_mappings)
- ppc_md.setup_io_mappings();
/* Initialize the context management stuff */
mmu_context_init();
p = alloc_bootmem_pages(PAGE_SIZE);
} else {
p = __va(lmb_alloc_base(PAGE_SIZE, PAGE_SIZE,
- __initial_memory_limit));
+ __initial_memory_limit_addr));
}
return p;
}
kcore_mem = kmalloc(sizeof(struct kcore_list), GFP_ATOMIC);
if (!kcore_mem)
- panic("%s: kmalloc failed\n", __FUNCTION__);
+ panic("%s: kmalloc failed\n", __func__);
/* must stay under 32 bits */
if ( 0xfffffffful - (unsigned long)__va(base) < size) {
#include <linux/nodemask.h>
#include <linux/module.h>
#include <linux/poison.h>
+#include <linux/lmb.h>
#include <asm/pgalloc.h>
#include <asm/page.h>
#include <asm/prom.h>
-#include <asm/lmb.h>
#include <asm/rtas.h>
#include <asm/io.h>
#include <asm/mmu_context.h>
#warning TASK_SIZE is smaller than it needs to be.
#endif
-/* max amount of RAM to use */
-unsigned long __max_memory;
+phys_addr_t memstart_addr;
void free_initmem(void)
{
/* GFP_ATOMIC to avoid might_sleep warnings during boot */
kcore_mem = kmalloc(sizeof(struct kcore_list), GFP_ATOMIC);
if (!kcore_mem)
- panic("%s: kmalloc failed\n", __FUNCTION__);
+ panic("%s: kmalloc failed\n", __func__);
kclist_add(kcore_mem, __va(base), size);
}
+++ /dev/null
-/*
- * Procedures for maintaining information about logical memory blocks.
- *
- * Peter Bergner, IBM Corp. June 2001.
- * Copyright (C) 2001 Peter Bergner.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/bitops.h>
-#include <asm/types.h>
-#include <asm/page.h>
-#include <asm/prom.h>
-#include <asm/lmb.h>
-#ifdef CONFIG_PPC32
-#include "mmu_decl.h" /* for __max_low_memory */
-#endif
-
-#undef DEBUG
-
-#ifdef DEBUG
-#include <asm/udbg.h>
-#define DBG(fmt...) udbg_printf(fmt)
-#else
-#define DBG(fmt...)
-#endif
-
-#define LMB_ALLOC_ANYWHERE 0
-
-struct lmb lmb;
-
-void lmb_dump_all(void)
-{
-#ifdef DEBUG
- unsigned long i;
-
- DBG("lmb_dump_all:\n");
- DBG(" memory.cnt = 0x%lx\n", lmb.memory.cnt);
- DBG(" memory.size = 0x%lx\n", lmb.memory.size);
- for (i=0; i < lmb.memory.cnt ;i++) {
- DBG(" memory.region[0x%x].base = 0x%lx\n",
- i, lmb.memory.region[i].base);
- DBG(" .size = 0x%lx\n",
- lmb.memory.region[i].size);
- }
-
- DBG("\n reserved.cnt = 0x%lx\n", lmb.reserved.cnt);
- DBG(" reserved.size = 0x%lx\n", lmb.reserved.size);
- for (i=0; i < lmb.reserved.cnt ;i++) {
- DBG(" reserved.region[0x%x].base = 0x%lx\n",
- i, lmb.reserved.region[i].base);
- DBG(" .size = 0x%lx\n",
- lmb.reserved.region[i].size);
- }
-#endif /* DEBUG */
-}
-
-static unsigned long __init lmb_addrs_overlap(unsigned long base1,
- unsigned long size1, unsigned long base2, unsigned long size2)
-{
- return ((base1 < (base2+size2)) && (base2 < (base1+size1)));
-}
-
-static long __init lmb_addrs_adjacent(unsigned long base1, unsigned long size1,
- unsigned long base2, unsigned long size2)
-{
- if (base2 == base1 + size1)
- return 1;
- else if (base1 == base2 + size2)
- return -1;
-
- return 0;
-}
-
-static long __init lmb_regions_adjacent(struct lmb_region *rgn,
- unsigned long r1, unsigned long r2)
-{
- unsigned long base1 = rgn->region[r1].base;
- unsigned long size1 = rgn->region[r1].size;
- unsigned long base2 = rgn->region[r2].base;
- unsigned long size2 = rgn->region[r2].size;
-
- return lmb_addrs_adjacent(base1, size1, base2, size2);
-}
-
-static void __init lmb_remove_region(struct lmb_region *rgn, unsigned long r)
-{
- unsigned long i;
-
- for (i = r; i < rgn->cnt - 1; i++) {
- rgn->region[i].base = rgn->region[i + 1].base;
- rgn->region[i].size = rgn->region[i + 1].size;
- }
- rgn->cnt--;
-}
-
-/* Assumption: base addr of region 1 < base addr of region 2 */
-static void __init lmb_coalesce_regions(struct lmb_region *rgn,
- unsigned long r1, unsigned long r2)
-{
- rgn->region[r1].size += rgn->region[r2].size;
- lmb_remove_region(rgn, r2);
-}
-
-/* This routine called with relocation disabled. */
-void __init lmb_init(void)
-{
- /* Create a dummy zero size LMB which will get coalesced away later.
- * This simplifies the lmb_add() code below...
- */
- lmb.memory.region[0].base = 0;
- lmb.memory.region[0].size = 0;
- lmb.memory.cnt = 1;
-
- /* Ditto. */
- lmb.reserved.region[0].base = 0;
- lmb.reserved.region[0].size = 0;
- lmb.reserved.cnt = 1;
-}
-
-/* This routine may be called with relocation disabled. */
-void __init lmb_analyze(void)
-{
- int i;
-
- lmb.memory.size = 0;
-
- for (i = 0; i < lmb.memory.cnt; i++)
- lmb.memory.size += lmb.memory.region[i].size;
-}
-
-/* This routine called with relocation disabled. */
-static long __init lmb_add_region(struct lmb_region *rgn, unsigned long base,
- unsigned long size)
-{
- unsigned long coalesced = 0;
- long adjacent, i;
-
- /* First try and coalesce this LMB with another. */
- for (i=0; i < rgn->cnt; i++) {
- unsigned long rgnbase = rgn->region[i].base;
- unsigned long rgnsize = rgn->region[i].size;
-
- if ((rgnbase == base) && (rgnsize == size))
- /* Already have this region, so we're done */
- return 0;
-
- adjacent = lmb_addrs_adjacent(base,size,rgnbase,rgnsize);
- if ( adjacent > 0 ) {
- rgn->region[i].base -= size;
- rgn->region[i].size += size;
- coalesced++;
- break;
- }
- else if ( adjacent < 0 ) {
- rgn->region[i].size += size;
- coalesced++;
- break;
- }
- }
-
- if ((i < rgn->cnt-1) && lmb_regions_adjacent(rgn, i, i+1) ) {
- lmb_coalesce_regions(rgn, i, i+1);
- coalesced++;
- }
-
- if (coalesced)
- return coalesced;
- if (rgn->cnt >= MAX_LMB_REGIONS)
- return -1;
-
- /* Couldn't coalesce the LMB, so add it to the sorted table. */
- for (i = rgn->cnt-1; i >= 0; i--) {
- if (base < rgn->region[i].base) {
- rgn->region[i+1].base = rgn->region[i].base;
- rgn->region[i+1].size = rgn->region[i].size;
- } else {
- rgn->region[i+1].base = base;
- rgn->region[i+1].size = size;
- break;
- }
- }
- rgn->cnt++;
-
- return 0;
-}
-
-/* This routine may be called with relocation disabled. */
-long __init lmb_add(unsigned long base, unsigned long size)
-{
- struct lmb_region *_rgn = &(lmb.memory);
-
- /* On pSeries LPAR systems, the first LMB is our RMO region. */
- if (base == 0)
- lmb.rmo_size = size;
-
- return lmb_add_region(_rgn, base, size);
-
-}
-
-long __init lmb_reserve(unsigned long base, unsigned long size)
-{
- struct lmb_region *_rgn = &(lmb.reserved);
-
- BUG_ON(0 == size);
-
- return lmb_add_region(_rgn, base, size);
-}
-
-long __init lmb_overlaps_region(struct lmb_region *rgn, unsigned long base,
- unsigned long size)
-{
- unsigned long i;
-
- for (i=0; i < rgn->cnt; i++) {
- unsigned long rgnbase = rgn->region[i].base;
- unsigned long rgnsize = rgn->region[i].size;
- if ( lmb_addrs_overlap(base,size,rgnbase,rgnsize) ) {
- break;
- }
- }
-
- return (i < rgn->cnt) ? i : -1;
-}
-
-unsigned long __init lmb_alloc(unsigned long size, unsigned long align)
-{
- return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE);
-}
-
-unsigned long __init lmb_alloc_base(unsigned long size, unsigned long align,
- unsigned long max_addr)
-{
- unsigned long alloc;
-
- alloc = __lmb_alloc_base(size, align, max_addr);
-
- if (alloc == 0)
- panic("ERROR: Failed to allocate 0x%lx bytes below 0x%lx.\n",
- size, max_addr);
-
- return alloc;
-}
-
-unsigned long __init __lmb_alloc_base(unsigned long size, unsigned long align,
- unsigned long max_addr)
-{
- long i, j;
- unsigned long base = 0;
-
- BUG_ON(0 == size);
-
-#ifdef CONFIG_PPC32
- /* On 32-bit, make sure we allocate lowmem */
- if (max_addr == LMB_ALLOC_ANYWHERE)
- max_addr = __max_low_memory;
-#endif
- for (i = lmb.memory.cnt-1; i >= 0; i--) {
- unsigned long lmbbase = lmb.memory.region[i].base;
- unsigned long lmbsize = lmb.memory.region[i].size;
-
- if (max_addr == LMB_ALLOC_ANYWHERE)
- base = _ALIGN_DOWN(lmbbase + lmbsize - size, align);
- else if (lmbbase < max_addr) {
- base = min(lmbbase + lmbsize, max_addr);
- base = _ALIGN_DOWN(base - size, align);
- } else
- continue;
-
- while ((lmbbase <= base) &&
- ((j = lmb_overlaps_region(&lmb.reserved, base, size)) >= 0) )
- base = _ALIGN_DOWN(lmb.reserved.region[j].base - size,
- align);
-
- if ((base != 0) && (lmbbase <= base))
- break;
- }
-
- if (i < 0)
- return 0;
-
- lmb_add_region(&lmb.reserved, base, size);
-
- return base;
-}
-
-/* You must call lmb_analyze() before this. */
-unsigned long __init lmb_phys_mem_size(void)
-{
- return lmb.memory.size;
-}
-
-unsigned long __init lmb_end_of_DRAM(void)
-{
- int idx = lmb.memory.cnt - 1;
-
- return (lmb.memory.region[idx].base + lmb.memory.region[idx].size);
-}
-
-/* You must call lmb_analyze() after this. */
-void __init lmb_enforce_memory_limit(unsigned long memory_limit)
-{
- unsigned long i, limit;
- struct lmb_property *p;
-
- if (! memory_limit)
- return;
-
- /* Truncate the lmb regions to satisfy the memory limit. */
- limit = memory_limit;
- for (i = 0; i < lmb.memory.cnt; i++) {
- if (limit > lmb.memory.region[i].size) {
- limit -= lmb.memory.region[i].size;
- continue;
- }
-
- lmb.memory.region[i].size = limit;
- lmb.memory.cnt = i + 1;
- break;
- }
-
- if (lmb.memory.region[0].size < lmb.rmo_size)
- lmb.rmo_size = lmb.memory.region[0].size;
-
- /* And truncate any reserves above the limit also. */
- for (i = 0; i < lmb.reserved.cnt; i++) {
- p = &lmb.reserved.region[i];
-
- if (p->base > memory_limit)
- p->size = 0;
- else if ((p->base + p->size) > memory_limit)
- p->size = memory_limit - p->base;
-
- if (p->size == 0) {
- lmb_remove_region(&lmb.reserved, i);
- i--;
- }
- }
-}
-
-int __init lmb_is_reserved(unsigned long addr)
-{
- int i;
-
- for (i = 0; i < lmb.reserved.cnt; i++) {
- unsigned long upper = lmb.reserved.region[i].base +
- lmb.reserved.region[i].size - 1;
- if ((addr >= lmb.reserved.region[i].base) && (addr <= upper))
- return 1;
- }
- return 0;
-}
#include <linux/initrd.h>
#include <linux/pagemap.h>
#include <linux/suspend.h>
+#include <linux/lmb.h>
#include <asm/pgalloc.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/btext.h>
#include <asm/tlb.h>
-#include <asm/lmb.h>
#include <asm/sections.h>
#include <asm/vdso.h>
}
#endif
-int __devinit arch_add_memory(int nid, u64 start, u64 size)
+int arch_add_memory(int nid, u64 start, u64 size)
{
struct pglist_data *pgdata;
struct zone *zone;
printk("Mem-info:\n");
show_free_areas();
- printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
for_each_online_pgdat(pgdat) {
unsigned long flags;
pgdat_resize_lock(pgdat, &flags);
unsigned long total_pages;
int boot_mapsize;
- max_pfn = total_pages = lmb_end_of_DRAM() >> PAGE_SHIFT;
+ max_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
+ total_pages = (lmb_end_of_DRAM() - memstart_addr) >> PAGE_SHIFT;
#ifdef CONFIG_HIGHMEM
total_pages = total_lowmem >> PAGE_SHIFT;
+ max_low_pfn = lowmem_end_addr >> PAGE_SHIFT;
#endif
/*
* present.
*/
#ifdef CONFIG_HIGHMEM
- free_bootmem_with_active_regions(0, total_lowmem >> PAGE_SHIFT);
+ free_bootmem_with_active_regions(0, lowmem_end_addr >> PAGE_SHIFT);
/* reserve the sections we're already using */
for (i = 0; i < lmb.reserved.cnt; i++) {
unsigned long addr = lmb.reserved.region[i].base +
lmb_size_bytes(&lmb.reserved, i) - 1;
- if (addr < total_lowmem)
+ if (addr < lowmem_end_addr)
reserve_bootmem(lmb.reserved.region[i].base,
lmb_size_bytes(&lmb.reserved, i),
BOOTMEM_DEFAULT);
- else if (lmb.reserved.region[i].base < total_lowmem) {
- unsigned long adjusted_size = total_lowmem -
+ else if (lmb.reserved.region[i].base < lowmem_end_addr) {
+ unsigned long adjusted_size = lowmem_end_addr -
lmb.reserved.region[i].base;
reserve_bootmem(lmb.reserved.region[i].base,
adjusted_size, BOOTMEM_DEFAULT);
(top_of_ram - total_ram) >> 20);
memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
#ifdef CONFIG_HIGHMEM
- max_zone_pfns[ZONE_DMA] = total_lowmem >> PAGE_SHIFT;
+ max_zone_pfns[ZONE_DMA] = lowmem_end_addr >> PAGE_SHIFT;
max_zone_pfns[ZONE_HIGHMEM] = top_of_ram >> PAGE_SHIFT;
#else
max_zone_pfns[ZONE_DMA] = top_of_ram >> PAGE_SHIFT;
{
unsigned long pfn, highmem_mapnr;
- highmem_mapnr = total_lowmem >> PAGE_SHIFT;
+ highmem_mapnr = lowmem_end_addr >> PAGE_SHIFT;
for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) {
struct page *page = pfn_to_page(pfn);
if (lmb_is_reserved(pfn << PAGE_SHIFT))
extern unsigned long ioremap_bot;
extern unsigned long __max_low_memory;
-extern unsigned long __initial_memory_limit;
+extern phys_addr_t __initial_memory_limit_addr;
extern unsigned long total_memory;
extern unsigned long total_lowmem;
+extern phys_addr_t memstart_addr;
+extern phys_addr_t lowmem_end_addr;
/* ...and now those things that may be slightly different between processor
* architectures. -- Dan
#include <linux/nodemask.h>
#include <linux/cpu.h>
#include <linux/notifier.h>
+#include <linux/lmb.h>
#include <asm/sparsemem.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
#include <asm/system.h>
#include <asm/smp.h>
*/
void __init mapin_ram(void)
{
- unsigned long v, p, s, f;
+ unsigned long v, s, f;
+ phys_addr_t p;
int ktext;
s = mmu_mapin_ram();
v = KERNELBASE + s;
- p = PPC_MEMSTART + s;
+ p = memstart_addr + s;
for (; s < total_lowmem; s += PAGE_SIZE) {
ktext = ((char *) v >= _stext && (char *) v < etext);
f = ktext ?_PAGE_RAM_TEXT : _PAGE_RAM;
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/highmem.h>
+#include <linux/lmb.h>
#include <asm/prom.h>
#include <asm/mmu.h>
#include <asm/machdep.h>
-#include <asm/lmb.h>
#include "mmu_decl.h"
#else
unsigned long tot, bl, done;
unsigned long max_size = (256<<20);
- unsigned long align;
if (__map_without_bats) {
printk(KERN_DEBUG "RAM mapped without BATs\n");
/* Make sure we don't map a block larger than the
smallest alignment of the physical address. */
- /* alignment of PPC_MEMSTART */
- align = ~(PPC_MEMSTART-1) & PPC_MEMSTART;
- /* set BAT block size to MIN(max_size, align) */
- if (align && align < max_size)
- max_size = align;
-
tot = total_lowmem;
for (bl = 128<<10; bl < max_size; bl <<= 1) {
if (bl * 2 > tot)
break;
}
- setbat(2, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM);
+ setbat(2, KERNELBASE, 0, bl, _PAGE_RAM);
done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1;
if ((done < tot) && !bat_addrs[3].limit) {
/* use BAT3 to cover a bit more */
for (bl = 128<<10; bl < max_size; bl <<= 1)
if (bl * 2 > tot)
break;
- setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM);
+ setbat(3, KERNELBASE+done, done, bl, _PAGE_RAM);
done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1;
}
*/
if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
Hash = __va(lmb_alloc_base(Hash_size, Hash_size,
- __initial_memory_limit));
+ __initial_memory_limit_addr));
cacheable_memzero(Hash, Hash_size);
_SDR1 = __pa(Hash) | SDR1_LOW_BITS;
* 2 of the License, or (at your option) any later version.
*/
+#include <linux/lmb.h>
+
#include <asm/pgtable.h>
#include <asm/mmu.h>
#include <asm/mmu_context.h>
#include <asm/paca.h>
#include <asm/cputable.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
#include <asm/abs_addr.h>
#include <asm/firmware.h>
#include <asm/iseries/hv_call.h>
if (spu_num >= num_spu_nodes) {
printk(KERN_ERR "SPU_PROF: "
"%s, line %d: Invalid index %d into spu info cache\n",
- __FUNCTION__, __LINE__, spu_num);
+ __func__, __LINE__, spu_num);
ret_info = NULL;
goto out;
}
if (!info) {
printk(KERN_ERR "SPU_PROF: "
"%s, line %d: create vma_map failed\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
retval = -ENOMEM;
goto err_alloc;
}
if (!new_map) {
printk(KERN_ERR "SPU_PROF: "
"%s, line %d: create vma_map failed\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
retval = -ENOMEM;
goto err_alloc;
}
printk(KERN_ERR "SPU_PROF: "
"%s, line %d: "
"Invalid index %d into spu info cache\n",
- __FUNCTION__, __LINE__, spu_index);
+ __func__, __LINE__, spu_index);
goto out;
}
end = spu_index + 1;
printk(KERN_ERR "SPU_PROF: "
"%s, line %d: Cannot find dcookie for SPU binary\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
goto out;
}
if (ret) {
printk(KERN_ERR "SPU_PROF: "
"%s, line %d: spu_switch_event_unregister returned %d\n",
- __FUNCTION__, __LINE__, ret);
+ __func__, __LINE__, ret);
goto out;
}
kzalloc(sizeof(struct vma_to_fileoffset_map), GFP_KERNEL);
if (!new) {
printk(KERN_ERR "SPU_PROF: %s, line %d: malloc failed\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
vma_map_free(map);
return NULL;
}
if (memcmp(ehdr.e_ident, expected, EI_PAD) != 0) {
printk(KERN_ERR "SPU_PROF: "
"%s, line %d: Unexpected e_ident parsing SPU ELF\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
goto fail;
}
if (ehdr.e_machine != EM_SPU) {
printk(KERN_ERR "SPU_PROF: "
"%s, line %d: Unexpected e_machine parsing SPU ELF\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
goto fail;
}
if (ehdr.e_type != ET_EXEC) {
printk(KERN_ERR "SPU_PROF: "
"%s, line %d: Unexpected e_type parsing SPU ELF\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
goto fail;
}
phdr_start = spu_elf_start + ehdr.e_phoff;
if (overlay_tbl_offset < 0) {
printk(KERN_ERR "SPU_PROF: "
"%s, line %d: Error finding SPU overlay table\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
goto fail;
}
ovly_table = spu_elf_start + overlay_tbl_offset;
* failure to stop OProfile.
*/
printk(KERN_WARNING "%s: rtas returned: %d\n",
- __FUNCTION__, ret);
+ __func__, ret);
}
static int pm_rtas_activate_signals(u32 node, u32 count)
if (unlikely(ret)) {
printk(KERN_WARNING "%s: rtas returned: %d\n",
- __FUNCTION__, ret);
+ __func__, ret);
return -EIO;
}
}
if (unlikely(spu_rtas_token == RTAS_UNKNOWN_SERVICE)) {
printk(KERN_ERR
"%s: rtas token ibm,cbe-spu-perftools unknown\n",
- __FUNCTION__);
+ __func__);
return -EIO;
}
}
if (unlikely(pm_rtas_token == RTAS_UNKNOWN_SERVICE)) {
printk(KERN_ERR
"%s: rtas token ibm,cbe-perftools unknown\n",
- __FUNCTION__);
+ __func__);
return -EIO;
}
if (unlikely(ret)) {
printk(KERN_WARNING "%s: rtas returned: %d\n",
- __FUNCTION__, ret);
+ __func__, ret);
return -EIO;
}
if (unlikely(ret != 0)) {
printk(KERN_ERR
"%s: rtas call ibm,cbe-spu-perftools failed, return = %d\n",
- __FUNCTION__, ret);
+ __func__, ret);
rtas_error = -EIO;
goto out;
}
if (unlikely(rtn_value != 0)) {
printk(KERN_ERR
"%s: rtas call ibm,cbe-spu-perftools failed, return = %d\n",
- __FUNCTION__, rtn_value);
+ __func__, rtn_value);
}
/* Deactivate the signals */
#include <asm/time.h>
#include <asm/uic.h>
#include <asm/pci-bridge.h>
+#include <asm/ppc4xx.h>
static struct device_node *bcsr_node;
static void __iomem *bcsr_regs;
.progress = udbg_progress,
.init_IRQ = uic_init_tree,
.get_irq = uic_get_irq,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
/*
* Kilauea board specific routines
*
- * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ * Copyright 2007-2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
*
* Based on the Walnut code by
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
#include <asm/time.h>
#include <asm/uic.h>
#include <asm/pci-bridge.h>
+#include <asm/ppc4xx.h>
static __initdata struct of_device_id kilauea_of_bus[] = {
{ .compatible = "ibm,plb4", },
.progress = udbg_progress,
.init_IRQ = uic_init_tree,
.get_irq = uic_get_irq,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
#include <asm/time.h>
#include <asm/uic.h>
#include <asm/pci-bridge.h>
+#include <asm/ppc4xx.h>
static __initdata struct of_device_id makalu_of_bus[] = {
{ .compatible = "ibm,plb4", },
.progress = udbg_progress,
.init_IRQ = uic_init_tree,
.get_irq = uic_get_irq,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
#include <asm/prom.h>
#include <asm/time.h>
#include <asm/xilinx_intc.h>
+#include <asm/ppc4xx.h>
static struct of_device_id xilinx_of_bus_ids[] __initdata = {
{ .compatible = "xlnx,plb-v46-1.00.a", },
.probe = virtex_probe,
.init_IRQ = xilinx_intc_init_tree,
.get_irq = xilinx_intc_get_irq,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
#include <asm/time.h>
#include <asm/uic.h>
#include <asm/pci-bridge.h>
+#include <asm/ppc4xx.h>
static __initdata struct of_device_id walnut_of_bus[] = {
{ .compatible = "ibm,plb3", },
.progress = udbg_progress,
.init_IRQ = uic_init_tree,
.get_irq = uic_get_irq,
- .calibrate_decr = generic_calibrate_decr,
+ .restart = ppc4xx_reset_system,
+ .calibrate_decr = generic_calibrate_decr,
};
extern u8 as1_readb(volatile u8 __iomem *addr);
extern void as1_writeb(u8 data, volatile u8 __iomem *addr);
-extern void ppc44x_reset_system(char *cmd);
#endif /* __POWERPC_PLATFORMS_44X_44X_H */
See http://www.pikatechnologies.com/ and follow the "PIKA for Computer
Telephony Developers" link for more information.
+config CANYONLANDS
+ bool "Canyonlands"
+ depends on 44x
+ default n
+ select 460EX
+ select PCI
+ select PPC4xx_PCI_EXPRESS
+ help
+ This option enables support for the AMCC PPC460EX evaluation board.
+
+config YOSEMITE
+ bool "Yosemite"
+ depends on 44x
+ default n
+ select 440EP
+ select PCI
+ help
+ This option enables support for the AMCC PPC440EP evaluation board.
+
#config LUAN
# bool "Luan"
# depends on 44x
bool
select IBM_NEW_EMAC_EMAC4
+config 460EX
+ bool
+ select PPC_FPU
+ select IBM_NEW_EMAC_EMAC4
+ select IBM_NEW_EMAC_RGMII
+ select IBM_NEW_EMAC_ZMII
+ select IBM_NEW_EMAC_TAH
+
# 44x errata/workaround config symbols, selected by the CPU models above
config IBM440EP_ERR42
bool
-obj-$(CONFIG_44x) := misc_44x.o
+obj-$(CONFIG_44x) := misc_44x.o idle.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_TAISHAN) += taishan.o
obj-$(CONFIG_BAMBOO) += bamboo.o
+obj-$(CONFIG_YOSEMITE) += bamboo.o
obj-$(CONFIG_SEQUOIA) += sequoia.o
obj-$(CONFIG_KATMAI) += katmai.o
obj-$(CONFIG_RAINIER) += rainier.o
obj-$(CONFIG_WARP) += warp.o
obj-$(CONFIG_WARP) += warp-nand.o
+obj-$(CONFIG_CANYONLANDS) += canyonlands.o
#include <asm/time.h>
#include <asm/uic.h>
#include <asm/pci-bridge.h>
-
-#include "44x.h"
+#include <asm/ppc4xx.h>
static __initdata struct of_device_id bamboo_of_bus[] = {
{ .compatible = "ibm,plb4", },
}
define_machine(bamboo) {
- .name = "Bamboo",
- .probe = bamboo_probe,
- .progress = udbg_progress,
- .init_IRQ = uic_init_tree,
- .get_irq = uic_get_irq,
- .restart = ppc44x_reset_system,
+ .name = "Bamboo",
+ .probe = bamboo_probe,
+ .progress = udbg_progress,
+ .init_IRQ = uic_init_tree,
+ .get_irq = uic_get_irq,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
--- /dev/null
+/*
+ * Canyonlands board specific routines
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * Based on the Katmai code by
+ * Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ * Copyright 2007 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ * Copyright 2007 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/time.h>
+#include <asm/uic.h>
+#include <asm/pci-bridge.h>
+#include <asm/ppc4xx.h>
+
+static __initdata struct of_device_id canyonlands_of_bus[] = {
+ { .compatible = "ibm,plb4", },
+ { .compatible = "ibm,opb", },
+ { .compatible = "ibm,ebc", },
+ {},
+};
+
+static int __init canyonlands_device_probe(void)
+{
+ of_platform_bus_probe(NULL, canyonlands_of_bus, NULL);
+
+ return 0;
+}
+machine_device_initcall(canyonlands, canyonlands_device_probe);
+
+static int __init canyonlands_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (!of_flat_dt_is_compatible(root, "amcc,canyonlands"))
+ return 0;
+
+ ppc_pci_flags = PPC_PCI_REASSIGN_ALL_RSRC;
+
+ return 1;
+}
+
+define_machine(canyonlands) {
+ .name = "Canyonlands",
+ .probe = canyonlands_probe,
+ .progress = udbg_progress,
+ .init_IRQ = uic_init_tree,
+ .get_irq = uic_get_irq,
+ .restart = ppc4xx_reset_system,
+ .calibrate_decr = generic_calibrate_decr,
+};
#include <asm/time.h>
#include <asm/uic.h>
#include <asm/pci-bridge.h>
-
-#include "44x.h"
+#include <asm/ppc4xx.h>
static __initdata struct of_device_id ebony_of_bus[] = {
{ .compatible = "ibm,plb4", },
.progress = udbg_progress,
.init_IRQ = uic_init_tree,
.get_irq = uic_get_irq,
- .restart = ppc44x_reset_system,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
--- /dev/null
+/*
+ * Copyright 2008 IBM Corp.
+ *
+ * Based on arch/powerpc/platforms/pasemi/idle.c:
+ * Copyright (C) 2006-2007 PA Semi, Inc
+ *
+ * Added by: Jerone Young <jyoung5@us.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <linux/of.h>
+#include <linux/kernel.h>
+#include <asm/machdep.h>
+
+static int mode_spin;
+
+static void ppc44x_idle(void)
+{
+ unsigned long msr_save;
+
+ msr_save = mfmsr();
+ /* set wait state MSR */
+ mtmsr(msr_save|MSR_WE|MSR_EE|MSR_CE|MSR_DE);
+ isync();
+ /* return to initial state */
+ mtmsr(msr_save);
+ isync();
+}
+
+int __init ppc44x_idle_init(void)
+{
+ if (!mode_spin) {
+ /* If we are not setting spin mode
+ then we set to wait mode */
+ ppc_md.power_save = &ppc44x_idle;
+ }
+
+ return 0;
+}
+
+arch_initcall(ppc44x_idle_init);
+
+static int __init idle_param(char *p)
+{
+
+ if (!strcmp("spin", p)) {
+ mode_spin = 1;
+ ppc_md.power_save = NULL;
+ }
+
+ return 0;
+}
+
+early_param("idle", idle_param);
#include <asm/time.h>
#include <asm/uic.h>
#include <asm/pci-bridge.h>
-
-#include "44x.h"
+#include <asm/ppc4xx.h>
static __initdata struct of_device_id katmai_of_bus[] = {
{ .compatible = "ibm,plb4", },
.progress = udbg_progress,
.init_IRQ = uic_init_tree,
.get_irq = uic_get_irq,
- .restart = ppc44x_reset_system,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
sync
isync
blr
-
-/*
- * void ppc44x_reset_system(char *cmd)
- *
- * At present, this routine just applies a system reset.
- */
-_GLOBAL(ppc44x_reset_system)
- mfspr r13,SPRN_DBCR0
- oris r13,r13,DBCR0_RST_SYSTEM@h
- mtspr SPRN_DBCR0,r13
- b . /* Just in case the reset doesn't work */
#include <asm/time.h>
#include <asm/uic.h>
#include <asm/pci-bridge.h>
-#include "44x.h"
+#include <asm/ppc4xx.h>
static __initdata struct of_device_id rainier_of_bus[] = {
{ .compatible = "ibm,plb4", },
.progress = udbg_progress,
.init_IRQ = uic_init_tree,
.get_irq = uic_get_irq,
- .restart = ppc44x_reset_system,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
#include <asm/uic.h>
#include <asm/pci-bridge.h>
-#include "44x.h"
+#include <asm/ppc4xx.h>
static __initdata struct of_device_id sequoia_of_bus[] = {
{ .compatible = "ibm,plb4", },
.progress = udbg_progress,
.init_IRQ = uic_init_tree,
.get_irq = uic_get_irq,
- .restart = ppc44x_reset_system,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
#include <asm/time.h>
#include <asm/uic.h>
#include <asm/pci-bridge.h>
-
-#include "44x.h"
+#include <asm/ppc4xx.h>
static __initdata struct of_device_id taishan_of_bus[] = {
{ .compatible = "ibm,plb4", },
.progress = udbg_progress,
.init_IRQ = uic_init_tree,
.get_irq = uic_get_irq,
- .restart = ppc44x_reset_system,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/ndfc.h>
+#include <asm/machdep.h>
#ifdef CONFIG_MTD_NAND_NDFC
return 0;
}
-device_initcall(warp_setup_nand_flash);
+machine_device_initcall(warp, warp_setup_nand_flash);
#endif
#include <asm/udbg.h>
#include <asm/time.h>
#include <asm/uic.h>
-
-#include "44x.h"
-
+#include <asm/ppc4xx.h>
static __initdata struct of_device_id warp_of_bus[] = {
{ .compatible = "ibm,plb4", },
.progress = udbg_progress,
.init_IRQ = uic_init_tree,
.get_irq = uic_get_irq,
- .restart = ppc44x_reset_system,
+ .restart = ppc4xx_reset_system,
.calibrate_decr = generic_calibrate_decr,
};
of_node_put(np);
if (!cdm) {
printk(KERN_ERR "%s() failed; expect abnormal behaviour\n",
- __FUNCTION__);
+ __func__);
return;
}
of_node_put(np);
if (!gpio) {
printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
- __FUNCTION__);
+ __func__);
return;
}
select 8260
select FSL_SOC
select PQ2_ADS_PCI_PIC if PCI
- select PPC_CPM_NEW_BINDING
help
This option enables support for the MPC8272 ADS board
select 8260
select FSL_SOC
select PQ2_ADS_PCI_PIC if PCI
- select PPC_CPM_NEW_BINDING
help
This option enables support for the PQ2FADS board
select 8272
select 8260
select FSL_SOC
- select PPC_CPM_NEW_BINDING
select MDIO_BITBANG
help
This enables support for the Embedded Planet EP8248E board.
static struct of_device_id mpc837x_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
+ { .compatible = "simple-bus", },
{},
};
#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
#define MPC8315_SCCR_USB_MASK 0x00c00000
#define MPC8315_SCCR_USB_DRCM_11 0x00c00000
+#define MPC8315_SCCR_USB_DRCM_01 0x00400000
#define MPC837X_SCCR_USB_DRCM_11 0x00c00000
/* system i/o configuration register low */
/* USB Control Register */
#define FSL_USB2_CONTROL_OFFS 0x500
#define CONTROL_UTMI_PHY_EN 0x00000200
+#define CONTROL_REFSEL_24MHZ 0x00000040
#define CONTROL_REFSEL_48MHZ 0x00000080
#define CONTROL_PHY_CLK_SEL_ULPI 0x00000400
#define CONTROL_OTG_PORT 0x00000020
if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
MPC8315_SCCR_USB_MASK,
- MPC8315_SCCR_USB_DRCM_11);
+ MPC8315_SCCR_USB_DRCM_01);
else
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
MPC83XX_SCCR_USB_MASK,
/* Using on-chip PHY */
if (prop && (!strcmp(prop, "utmi_wide") ||
!strcmp(prop, "utmi"))) {
- /* Set UTMI_PHY_EN, REFSEL to 48MHZ */
+ u32 refsel;
+
+ if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
+ refsel = CONTROL_REFSEL_24MHZ;
+ else
+ refsel = CONTROL_REFSEL_48MHZ;
+ /* Set UTMI_PHY_EN and REFSEL */
out_be32(usb_regs + FSL_USB2_CONTROL_OFFS,
- CONTROL_UTMI_PHY_EN | CONTROL_REFSEL_48MHZ);
+ CONTROL_UTMI_PHY_EN | refsel);
/* Using external UPLI PHY */
} else if (prop && !strcmp(prop, "ulpi")) {
/* Set PHY_CLK_SEL to ULPI */
config MPC8560_ADS
bool "Freescale MPC8560 ADS"
select DEFAULT_UIMAGE
- select PPC_CPM_NEW_BINDING
select CPM2
help
This option enables support for the MPC 8560 ADS board
help
This option enables support for the MPC85xx DS (MPC8544 DS) board
+config KSI8560
+ bool "Emerson KSI8560"
+ select DEFAULT_UIMAGE
+ help
+ This option enables support for the Emerson KSI8560 board
+
config STX_GP3
bool "Silicon Turnkey Express GP3"
help
board.
select CPM2
select DEFAULT_UIMAGE
- select PPC_CPM_NEW_BINDING
config TQM8540
bool "TQ Components TQM8540"
help
This option enables support for the TQ Components TQM8540 board.
select DEFAULT_UIMAGE
- select PPC_CPM_NEW_BINDING
select TQM85xx
config TQM8541
help
This option enables support for the TQ Components TQM8541 board.
select DEFAULT_UIMAGE
- select PPC_CPM_NEW_BINDING
select TQM85xx
select CPM2
help
This option enables support for the TQ Components TQM8555 board.
select DEFAULT_UIMAGE
- select PPC_CPM_NEW_BINDING
select TQM85xx
select CPM2
help
This option enables support for the TQ Components TQM8560 board.
select DEFAULT_UIMAGE
- select PPC_CPM_NEW_BINDING
select TQM85xx
select CPM2
config SBC8560
bool "Wind River SBC8560"
select DEFAULT_UIMAGE
- select PPC_CPM_NEW_BINDING if CPM2
help
This option enables support for the Wind River SBC8560 board
obj-$(CONFIG_TQM85xx) += tqm85xx.o
obj-$(CONFIG_SBC8560) += sbc8560.o
obj-$(CONFIG_SBC8548) += sbc8548.o
+obj-$(CONFIG_KSI8560) += ksi8560.o
--- /dev/null
+/*
+ * Board setup routines for the Emerson KSI8560
+ *
+ * Author: Alexandr Smirnov <asmirnov@ru.mvista.com>
+ *
+ * Based on mpc85xx_ads.c maintained by Kumar Gala
+ *
+ * 2008 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpic.h>
+#include <mm/mmu_decl.h>
+#include <asm/udbg.h>
+#include <asm/prom.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include <asm/cpm2.h>
+#include <sysdev/cpm2_pic.h>
+
+
+#define KSI8560_CPLD_HVR 0x04 /* Hardware Version Register */
+#define KSI8560_CPLD_PVR 0x08 /* PLD Version Register */
+#define KSI8560_CPLD_RCR1 0x30 /* Reset Command Register 1 */
+
+#define KSI8560_CPLD_RCR1_CPUHR 0x80 /* CPU Hard Reset */
+
+static void __iomem *cpld_base = NULL;
+
+static void machine_restart(char *cmd)
+{
+ if (cpld_base)
+ out_8(cpld_base + KSI8560_CPLD_RCR1, KSI8560_CPLD_RCR1_CPUHR);
+ else
+ printk(KERN_ERR "Can't find CPLD base, hang forever\n");
+
+ for (;;);
+}
+
+static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
+{
+ int cascade_irq;
+
+ while ((cascade_irq = cpm2_get_irq()) >= 0)
+ generic_handle_irq(cascade_irq);
+
+ desc->chip->eoi(irq);
+}
+
+static void __init ksi8560_pic_init(void)
+{
+ struct mpic *mpic;
+ struct resource r;
+ struct device_node *np;
+#ifdef CONFIG_CPM2
+ int irq;
+#endif
+
+ np = of_find_node_by_type(NULL, "open-pic");
+
+ if (np == NULL) {
+ printk(KERN_ERR "Could not find open-pic node\n");
+ return;
+ }
+
+ if (of_address_to_resource(np, 0, &r)) {
+ printk(KERN_ERR "Could not map mpic register space\n");
+ of_node_put(np);
+ return;
+ }
+
+ mpic = mpic_alloc(np, r.start,
+ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+ 0, 256, " OpenPIC ");
+ BUG_ON(mpic == NULL);
+ of_node_put(np);
+
+ mpic_init(mpic);
+
+#ifdef CONFIG_CPM2
+ /* Setup CPM2 PIC */
+ np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
+ if (np == NULL) {
+ printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
+ return;
+ }
+ irq = irq_of_parse_and_map(np, 0);
+
+ cpm2_pic_init(np);
+ of_node_put(np);
+ set_irq_chained_handler(irq, cpm2_cascade);
+
+ setup_irq(0, NULL);
+#endif
+}
+
+#ifdef CONFIG_CPM2
+/*
+ * Setup I/O ports
+ */
+struct cpm_pin {
+ int port, pin, flags;
+};
+
+static struct cpm_pin __initdata ksi8560_pins[] = {
+ /* SCC1 */
+ {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* SCC2 */
+ {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* FCC1 */
+ {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+ {2, 23, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK9 */
+ {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK10 */
+
+};
+
+static void __init init_ioports(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ksi8560_pins); i++) {
+ struct cpm_pin *pin = &ksi8560_pins[i];
+ cpm2_set_pin(pin->port, pin->pin, pin->flags);
+ }
+
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
+}
+#endif
+
+/*
+ * Setup the architecture
+ */
+static void __init ksi8560_setup_arch(void)
+{
+ struct device_node *cpld;
+
+ cpld = of_find_compatible_node(NULL, NULL, "emerson,KSI8560-cpld");
+ if (cpld)
+ cpld_base = of_iomap(cpld, 0);
+ else
+ printk(KERN_ERR "Can't find CPLD in device tree\n");
+
+ if (ppc_md.progress)
+ ppc_md.progress("ksi8560_setup_arch()", 0);
+
+#ifdef CONFIG_CPM2
+ cpm2_reset();
+ init_ioports();
+#endif
+}
+
+static void ksi8560_show_cpuinfo(struct seq_file *m)
+{
+ uint pvid, svid, phid1;
+ uint memsize = total_memory;
+
+ pvid = mfspr(SPRN_PVR);
+ svid = mfspr(SPRN_SVR);
+
+ seq_printf(m, "Vendor\t\t: Emerson Network Power\n");
+ seq_printf(m, "Board\t\t: KSI8560\n");
+
+ if (cpld_base) {
+ seq_printf(m, "Hardware rev\t: %d\n",
+ in_8(cpld_base + KSI8560_CPLD_HVR));
+ seq_printf(m, "CPLD rev\t: %d\n",
+ in_8(cpld_base + KSI8560_CPLD_PVR));
+ } else
+ seq_printf(m, "Unknown Hardware and CPLD revs\n");
+
+ seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
+ seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+
+ /* Display cpu Pll setting */
+ phid1 = mfspr(SPRN_HID1);
+ seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
+
+ /* Display the amount of memory */
+ seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+ { .type = "soc", },
+ { .name = "cpm", },
+ { .name = "localbus", },
+ {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+ of_platform_bus_probe(NULL, of_bus_ids, NULL);
+
+ return 0;
+}
+machine_device_initcall(ksi8560, declare_of_platform_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init ksi8560_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "emerson,KSI8560");
+}
+
+define_machine(ksi8560) {
+ .name = "KSI8560",
+ .probe = ksi8560_probe,
+ .setup_arch = ksi8560_setup_arch,
+ .init_IRQ = ksi8560_pic_init,
+ .show_cpuinfo = ksi8560_show_cpuinfo,
+ .get_irq = mpic_get_irq,
+ .restart = machine_restart,
+ .calibrate_decr = generic_calibrate_decr,
+};
int i;
for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
- struct cpm_pin *pin = &mpc8560_ads_pins[i];
+ const struct cpm_pin *pin = &mpc8560_ads_pins[i];
cpm2_set_pin(pin->port, pin->pin, pin->flags);
}
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
+#include <linux/of_platform.h>
#include <asm/system.h>
#include <asm/time.h>
#undef DEBUG
#ifdef DEBUG
-#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
+#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
#else
#define DBG(fmt, args...)
#endif
}
}
+static struct of_device_id mpc85xxds_ids[] = {
+ { .type = "soc", },
+ { .compatible = "soc", },
+ {},
+};
+
+static int __init mpc85xxds_publish_devices(void)
+{
+ return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
+}
+machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
+
/*
* Called very early, device-tree isn't unflattened
*/
help
This option enables support for the MPC8641 HPCN board.
+config SBC8641D
+ bool "Wind River SBC8641D"
+ select DEFAULT_UIMAGE
+ help
+ This option enables support for the WRS SBC8641D board.
+
config MPC8610_HPCD
bool "Freescale MPC8610 HPCD"
select DEFAULT_UIMAGE
select FSL_PCI if PCI
select PPC_UDBG_16550
select MPIC
- default y if MPC8641_HPCN
+ default y if MPC8641_HPCN || SBC8641D
config MPC8610
bool
obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
+obj-$(CONFIG_SBC8641D) += sbc8641d.o
obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
}
machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
-void __init
+static void __init
mpc86xx_hpcd_init_irq(void)
{
struct mpic *mpic1;
return 0;
}
-long __init
+static long __init
mpc86xx_time_init(void)
{
unsigned int temp;
}
#endif /* CONFIG_PCI */
-void __init
+static void __init
mpc86xx_hpcn_init_irq(void)
{
struct mpic *mpic1;
}
-void
+static void
mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
{
struct device_node *root;
{
unsigned long root = of_get_flat_dt_root();
- if (of_flat_dt_is_compatible(root, "mpc86xx"))
+ if (of_flat_dt_is_compatible(root, "fsl,mpc8641hpcn"))
return 1; /* Looks good */
+ /* Be nice and don't give silent boot death. Delete this in 2.6.27 */
+ if (of_flat_dt_is_compatible(root, "mpc86xx")) {
+ pr_warning("WARNING: your dts/dtb is old. You must update before the next kernel release\n");
+ return 1;
+ }
+
return 0;
}
-long __init
+static long __init
mpc86xx_time_init(void)
{
unsigned int temp;
--- /dev/null
+/*
+ * SBC8641D board specific routines
+ *
+ * Copyright 2008 Wind River Systems Inc.
+ *
+ * By Paul Gortmaker (see MAINTAINERS for contact information)
+ *
+ * Based largely on the 8641 HPCN support by Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc86xx.h>
+#include <asm/prom.h>
+#include <mm/mmu_decl.h>
+#include <asm/udbg.h>
+
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_pci.h>
+#include <sysdev/fsl_soc.h>
+
+#include "mpc86xx.h"
+
+static void __init
+sbc8641_init_irq(void)
+{
+ struct mpic *mpic1;
+ struct device_node *np;
+ struct resource res;
+
+ /* Determine PIC address. */
+ np = of_find_node_by_type(NULL, "open-pic");
+ if (np == NULL)
+ return;
+ of_address_to_resource(np, 0, &res);
+
+ /* Alloc mpic structure and per isu has 16 INT entries. */
+ mpic1 = mpic_alloc(np, res.start,
+ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+ 0, 256, " MPIC ");
+ of_node_put(np);
+ BUG_ON(mpic1 == NULL);
+
+ mpic_init(mpic1);
+}
+
+static void __init
+sbc8641_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+ struct device_node *np;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("sbc8641_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+ for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie")
+ fsl_add_bridge(np, 0);
+#endif
+
+ printk("SBC8641 board from Wind River\n");
+
+#ifdef CONFIG_SMP
+ mpc86xx_smp_init();
+#endif
+}
+
+
+static void
+sbc8641_show_cpuinfo(struct seq_file *m)
+{
+ struct device_node *root;
+ uint memsize = total_memory;
+ const char *model = "";
+ uint svid = mfspr(SPRN_SVR);
+
+ seq_printf(m, "Vendor\t\t: Wind River Systems\n");
+
+ root = of_find_node_by_path("/");
+ if (root)
+ model = of_get_property(root, "model", NULL);
+ seq_printf(m, "Machine\t\t: %s\n", model);
+ of_node_put(root);
+
+ seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+ seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
+
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init sbc8641_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "wind,sbc8641"))
+ return 1; /* Looks good */
+
+ return 0;
+}
+
+static long __init
+mpc86xx_time_init(void)
+{
+ unsigned int temp;
+
+ /* Set the time base to zero */
+ mtspr(SPRN_TBWL, 0);
+ mtspr(SPRN_TBWU, 0);
+
+ temp = mfspr(SPRN_HID0);
+ temp |= HID0_TBEN;
+ mtspr(SPRN_HID0, temp);
+ asm volatile("isync");
+
+ return 0;
+}
+
+static __initdata struct of_device_id of_bus_ids[] = {
+ { .compatible = "simple-bus", },
+ {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+ of_platform_bus_probe(NULL, of_bus_ids, NULL);
+
+ return 0;
+}
+machine_device_initcall(sbc8641, declare_of_platform_devices);
+
+define_machine(sbc8641) {
+ .name = "SBC8641D",
+ .probe = sbc8641_probe,
+ .setup_arch = sbc8641_setup_arch,
+ .init_IRQ = sbc8641_init_irq,
+ .show_cpuinfo = sbc8641_show_cpuinfo,
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .time_init = mpc86xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+};
config MPC86XADS
bool "MPC86XADS"
select CPM1
- select PPC_CPM_NEW_BINDING
help
MPC86x Application Development System by Freescale Semiconductor.
The MPC86xADS is meant to serve as a platform for s/w and h/w
config MPC885ADS
bool "MPC885ADS"
select CPM1
- select PPC_CPM_NEW_BINDING
help
Freescale Semiconductor MPC885 Application Development System (ADS).
Also known as DUET.
config PPC_EP88XC
bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
select CPM1
- select PPC_CPM_NEW_BINDING
help
This enables support for the Embedded Planet EP88xC board.
config PPC_ADDER875
bool "Analogue & Micro Adder 875"
select CPM1
- select PPC_CPM_NEW_BINDING
select REDBOOT
help
This enables support for the Analogue & Micro Adder 875
/* Processor frequency is MHz.
*/
- ppc_tb_freq = 50000000;
- if (!get_freq("bus-frequency", &ppc_tb_freq)) {
- printk(KERN_ERR "WARNING: Estimating decrementer frequency "
- "(not found)\n");
- }
- ppc_tb_freq /= 16;
ppc_proc_freq = 50000000;
if (!get_freq("clock-frequency", &ppc_proc_freq))
printk(KERN_ERR "WARNING: Estimating processor frequency "
"(not found)\n");
+ ppc_tb_freq = ppc_proc_freq / 16;
printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
/* Perform some more timer/timebase initialization. This used
config PPC_CPM_NEW_BINDING
bool
depends on CPM1 || CPM2
- help
- Select this if your board has been converted to use the new
- device tree bindings for CPM, and no longer needs the
- ioport callbacks or the platform device glue code.
-
- The fs_enet and cpm_uart drivers will be built as
- of_platform devices.
+ default y
config AXON_RAM
tristate "Axon DDR2 memory device driver"
bool "AMCC 40x"
select PPC_DCR_NATIVE
select PPC_UDBG_16550
+ select 4xx_SOC
config 44x
bool "AMCC 44x"
select PPC_DCR_NATIVE
select PPC_UDBG_16550
+ select 4xx_SOC
config E200
bool "Freescale e200"
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/of_platform.h>
+#include <linux/lmb.h>
#include <asm/prom.h>
#include <asm/iommu.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/udbg.h>
-#include <asm/lmb.h>
#include <asm/firmware.h>
#include <asm/cell-regs.h>
segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT;
pr_debug("%s: iommu[%d]: segments: %lu\n",
- __FUNCTION__, iommu->nid, segments);
+ __func__, iommu->nid, segments);
/* set up the segment table */
stab_size = segments * sizeof(unsigned long);
(1 << 12) / sizeof(unsigned long));
ptab_size = segments * pages_per_segment * sizeof(unsigned long);
- pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __FUNCTION__,
+ pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __func__,
iommu->nid, ptab_size, get_order(ptab_size));
page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size));
BUG_ON(!page);
n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12;
pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n",
- __FUNCTION__, iommu->nid, iommu->stab, ptab,
+ __func__, iommu->nid, iommu->stab, ptab,
n_pte_pages);
/* initialise the STEs */
if (cell_iommu_find_ioc(iommu->nid, &xlate_base))
panic("%s: missing IOC register mappings for node %d\n",
- __FUNCTION__, iommu->nid);
+ __func__, iommu->nid);
iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size);
iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset;
break;
default:
printk(KERN_WARNING "%s: unknown configuration\n",
- __FUNCTION__);
+ __func__);
break;
}
mtspr(SPRN_TSC_CELL, thread_switch_control);
(unsigned int)(addr >> 32),
(unsigned int)(addr & 0xffffffff))) {
printk(KERN_ERR "%s: error enabling PTCAL on node %d!\n",
- __FUNCTION__, nid);
+ __func__, nid);
goto out_free_pages;
}
if (!size)
return -ENODEV;
- pr_debug("%s: enabling PTCAL, size = 0x%x\n", __FUNCTION__, *size);
+ pr_debug("%s: enabling PTCAL, size = 0x%x\n", __func__, *size);
order = get_order(*size);
of_node_put(np);
const u32 *nid = of_get_property(np, "node-id", NULL);
if (!nid) {
printk(KERN_ERR "%s: node %s is missing node-id?\n",
- __FUNCTION__, np->full_name);
+ __func__, np->full_name);
continue;
}
cbe_ptcal_enable_on_node(*nid, order);
struct ptcal_area *area, *tmp;
int ret = 0;
- pr_debug("%s: disabling PTCAL\n", __FUNCTION__);
+ pr_debug("%s: disabling PTCAL\n", __func__);
list_for_each_entry_safe(area, tmp, &ptcal_list, list) {
/* disable ptcal on this node */
if (rtas_call(ptcal_stop_tok, 1, 1, NULL, area->nid)) {
printk(KERN_ERR "%s: error disabling PTCAL "
- "on node %d!\n", __FUNCTION__,
+ "on node %d!\n", __func__,
area->nid);
ret = -EIO;
continue;
struct spu_slb slb;
int psize;
- pr_debug("%s\n", __FUNCTION__);
+ pr_debug("%s\n", __func__);
slb.esid = (ea & ESID_MASK) | SLB_ESID_V;
extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
{
- pr_debug("%s, %lx, %lx\n", __FUNCTION__, dsisr, ea);
+ pr_debug("%s, %lx, %lx\n", __func__, dsisr, ea);
/* Handle kernel space hash faults immediately.
User hash faults need to be deferred to process context. */
__spu_trap_data_seg(spu, dar);
spin_unlock(&spu->register_lock);
- pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat,
+ pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat,
dar, dsisr);
if (stat & CLASS1_STORAGE_FAULT_INTR)
if (ret < 0) {
printk(KERN_WARNING "%s: Error initializing spus\n",
- __FUNCTION__);
+ __func__);
goto out_unregister_sysdev_class;
}
long (*syscall)(u64 a1, u64 a2, u64 a3, u64 a4, u64 a5, u64 a6);
if (s->nr_ret >= ARRAY_SIZE(spu_syscall_table)) {
- pr_debug("%s: invalid syscall #%ld", __FUNCTION__, s->nr_ret);
+ pr_debug("%s: invalid syscall #%ld", __func__, s->nr_ret);
return -ENOSYS;
}
tmp = of_get_property(np->parent->parent, "node-id", NULL);
if (!tmp) {
- printk(KERN_WARNING "%s: can't find node-id\n", __FUNCTION__);
+ printk(KERN_WARNING "%s: can't find node-id\n", __func__);
nid = spu->node;
} else
nid = tmp[0];
ret = fn(node);
if (ret) {
printk(KERN_WARNING "%s: Error initializing %s\n",
- __FUNCTION__, node->name);
+ __func__, node->name);
break;
}
n++;
if (!legacy_map) {
legacy_map = 1;
printk(KERN_WARNING "%s: Legacy device tree found, "
- "trying to map old style\n", __FUNCTION__);
+ "trying to map old style\n", __func__);
}
ret = spu_map_device_old(spu);
if (ret) {
if (!legacy_irq) {
legacy_irq = 1;
printk(KERN_WARNING "%s: Legacy device tree found, "
- "trying old style irq\n", __FUNCTION__);
+ "trying old style irq\n", __func__);
}
ret = spu_map_interrupts_old(spu, spe);
if (ret) {
if (ctx->flags & SPU_CREATE_NOSCHED)
continue;
- /* start searching the next fd next time we're called */
- (*fd)++;
break;
}
break;
size += rc;
+
+ /* start searching the next fd next time */
+ fd++;
}
return size;
}
spu_release_saved(ctx);
+
+ /* start searching the next fd next time */
+ fd++;
}
return 0;
#include <linux/marker.h>
#include <asm/io.h>
-#include <asm/semaphore.h>
#include <asm/spu.h>
#include <asm/spu_info.h>
#include <asm/uaccess.h>
return ctx->ops->signal1_type_get(ctx);
}
DEFINE_SPUFS_ATTRIBUTE(spufs_signal1_type, spufs_signal1_type_get,
- spufs_signal1_type_set, "%llu", SPU_ATTR_ACQUIRE);
+ spufs_signal1_type_set, "%llu\n", SPU_ATTR_ACQUIRE);
static int spufs_signal2_type_set(void *data, u64 val)
return ctx->ops->signal2_type_get(ctx);
}
DEFINE_SPUFS_ATTRIBUTE(spufs_signal2_type, spufs_signal2_type_get,
- spufs_signal2_type_set, "%llu", SPU_ATTR_ACQUIRE);
+ spufs_signal2_type_set, "%llu\n", SPU_ATTR_ACQUIRE);
#if SPUFS_MMAP_4K
static unsigned long spufs_mss_mmap_nopfn(struct vm_area_struct *vma,
wake_up_all(&ctx->mfc_wq);
- pr_debug("%s %s\n", __FUNCTION__, spu->name);
+ pr_debug("%s %s\n", __func__, spu->name);
if (ctx->mfc_fasync) {
u32 free_elements, tagstatus;
unsigned int mask;
if (tagstatus & ctx->tagwait)
mask |= POLLIN | POLLRDNORM;
- pr_debug("%s: free %d tagstatus %d tagwait %d\n", __FUNCTION__,
+ pr_debug("%s: free %d tagstatus %d tagwait %d\n", __func__,
free_elements, tagstatus, ctx->tagwait);
return mask;
#include <linux/parser.h>
#include <asm/prom.h>
-#include <asm/semaphore.h>
#include <asm/spu.h>
#include <asm/spu_priv1.h>
#include <asm/uaccess.h>
!= MFC_CNTL_PURGE_DMA_COMPLETE) {
if (time_after(jiffies, timeout)) {
printk(KERN_ERR "%s: timeout flushing MFC DMA queue\n",
- __FUNCTION__);
+ __func__);
ret = -EIO;
goto out;
}
status_loading) {
if (time_after(jiffies, timeout)) {
printk(KERN_ERR "%s: timeout waiting for loader\n",
- __FUNCTION__);
+ __func__);
ret = -EIO;
goto out_drop_priv;
}
if (!(status & SPU_STATUS_RUNNING)) {
/* If isolated LOAD has failed: run SPU, we will get a stop-and
* signal later. */
- pr_debug("%s: isolated LOAD failed\n", __FUNCTION__);
+ pr_debug("%s: isolated LOAD failed\n", __func__);
ctx->ops->runcntl_write(ctx, SPU_RUNCNTL_RUNNABLE);
ret = -EACCES;
goto out_drop_priv;
if (!(status & SPU_STATUS_ISOLATED_STATE)) {
/* This isn't allowed by the CBEA, but check anyway */
- pr_debug("%s: SPU fell out of isolated mode?\n", __FUNCTION__);
+ pr_debug("%s: SPU fell out of isolated mode?\n", __func__);
ctx->ops->runcntl_write(ctx, SPU_RUNCNTL_STOP);
ret = -EINVAL;
goto out_drop_priv;
break;
default:
printk(KERN_WARNING "%s: unexpected return code %ld\n",
- __FUNCTION__, *spu_ret);
+ __func__, *spu_ret);
ret = 0;
}
return ret;
return -EINTR;
}
+ /* need to re-get the ls, as it may have changed when we released the
+ * spu */
+ ls = (void __iomem *)ctx->ops->get_ls(ctx);
+
/* write result, jump over indirect pointer */
memcpy_toio(ls + ls_pointer, &spu_ret, sizeof(spu_ret));
ctx->ops->npc_write(ctx, npc);
save_mfc_csr_ato(prev, spu); /* Step 24. */
save_mfc_tclass_id(prev, spu); /* Step 25. */
set_mfc_tclass_id(prev, spu); /* Step 26. */
+ save_mfc_cmd(prev, spu); /* Step 26a - moved from 44. */
purge_mfc_queue(prev, spu); /* Step 27. */
wait_purge_complete(prev, spu); /* Step 28. */
setup_mfc_sr1(prev, spu); /* Step 30. */
save_ppuint_mb(prev, spu); /* Step 41. */
save_ch_part1(prev, spu); /* Step 42. */
save_spu_mb(prev, spu); /* Step 43. */
- save_mfc_cmd(prev, spu); /* Step 44. */
reset_ch(prev, spu); /* Step 45. */
}
}
u64 beat_halt_code = 0x1000000000000000UL;
+EXPORT_SYMBOL(beat_halt_code);
void beat_halt(void)
{
len = count;
if (len > BEAT_NVRW_CNT)
len = BEAT_NVRW_CNT;
- if (beat_eeprom_read(i, len, p)) {
+ if (beat_eeprom_read(i, len, p))
return -EIO;
- }
p += len;
i += len;
len = count;
if (len > BEAT_NVRW_CNT)
len = BEAT_NVRW_CNT;
- if (beat_eeprom_write(i, len, p)) {
+ if (beat_eeprom_write(i, len, p))
return -EIO;
- }
p += len;
i += len;
u64 db[2];
s64 ret;
- ret = beat_get_characters_from_console(vterm, len, (u8*)db);
+ ret = beat_get_characters_from_console(vterm, len, (u8 *)db);
if (ret == 0) {
*t1 = db[0];
*t2 = db[1];
}
return ret;
}
+EXPORT_SYMBOL(beat_get_term_char);
int64_t beat_put_term_char(u64 vterm, u64 len, u64 t1, u64 t2)
{
db[0] = t1;
db[1] = t2;
- return beat_put_characters_to_console(vterm, len, (u8*)db);
+ return beat_put_characters_to_console(vterm, len, (u8 *)db);
}
+EXPORT_SYMBOL(beat_put_term_char);
void beat_power_save(void)
{
}
device_initcall(beat_event_init);
-
-EXPORT_SYMBOL(beat_get_term_char);
-EXPORT_SYMBOL(beat_put_term_char);
-EXPORT_SYMBOL(beat_halt_code);
#ifndef _CELLEB_BEAT_H
#define _CELLEB_BEAT_H
-int64_t beat_get_term_char(uint64_t,uint64_t*,uint64_t*,uint64_t*);
-int64_t beat_put_term_char(uint64_t,uint64_t,uint64_t,uint64_t);
+int64_t beat_get_term_char(uint64_t, uint64_t *, uint64_t *, uint64_t *);
+int64_t beat_put_term_char(uint64_t, uint64_t, uint64_t, uint64_t);
int64_t beat_repository_encode(int, const char *, uint64_t[4]);
void beat_restart(char *);
void beat_power_off(void);
u64 b[2];
memcpy(b, buffer, len);
- return beat_hcall_norets(HV_put_characters_to_console, termno, len, b[0], b[1]);
+ return beat_hcall_norets(HV_put_characters_to_console, termno, len,
+ b[0], b[1]);
}
static inline s64 beat_get_spe_privileged_state_1_registers(
#include "beat_wrapper.h"
#ifdef DEBUG_LOW
-#define DBG_LOW(fmt...) do { udbg_printf(fmt); } while(0)
+#define DBG_LOW(fmt...) do { udbg_printf(fmt); } while (0)
#else
-#define DBG_LOW(fmt...) do { } while(0)
+#define DBG_LOW(fmt...) do { } while (0)
#endif
static DEFINE_SPINLOCK(beat_htab_lock);
hpte_r &= ~_PAGE_COHERENT;
spin_lock(&beat_htab_lock);
- if ((lpar_rc = beat_read_mask(hpte_group)) == 0) {
+ lpar_rc = beat_read_mask(hpte_group);
+ if (lpar_rc == 0) {
if (!(vflags & HPTE_V_BOLTED))
DBG_LOW(" full\n");
spin_unlock(&beat_htab_lock);
static uint64_t beatic_irq_mask_enable[(MAX_IRQS+255)/64];
static uint64_t beatic_irq_mask_ack[(MAX_IRQS+255)/64];
-static struct irq_host *beatic_host = NULL;
+static struct irq_host *beatic_host;
/*
* In this implementation, "virq" == "IRQ plug number",
off = (irq_plug / 256) * 4;
masks[0] = beatic_irq_mask_enable[off + 0]
- & beatic_irq_mask_ack[off + 0];
+ & beatic_irq_mask_ack[off + 0];
masks[1] = beatic_irq_mask_enable[off + 1]
- & beatic_irq_mask_ack[off + 1];
+ & beatic_irq_mask_ack[off + 1];
masks[2] = beatic_irq_mask_enable[off + 2]
- & beatic_irq_mask_ack[off + 2];
+ & beatic_irq_mask_ack[off + 2];
masks[3] = beatic_irq_mask_enable[off + 3]
- & beatic_irq_mask_ack[off + 3];
+ & beatic_irq_mask_ack[off + 3];
if (beat_set_interrupt_mask(irq_plug&~255UL,
masks[0], masks[1], masks[2], masks[3]) != 0)
panic("Failed to set mask IRQ!");
s64 err;
unsigned long flags;
- if ((err = beat_downcount_of_interrupt(irq_plug)) != 0) {
+ err = beat_downcount_of_interrupt(irq_plug);
+ if (err != 0) {
if ((err & 0xFFFFFFFF) != 0xFFFFFFF5) /* -11: wrong state */
panic("Failed to downcount IRQ! Error = %16lx", err);
struct irq_desc *desc = get_irq_desc(virq);
int64_t err;
- if ((err = beat_construct_and_connect_irq_plug(virq, hw)) < 0)
+ err = beat_construct_and_connect_irq_plug(virq, hw);
+ if (err < 0)
return -EIO;
desc->status |= IRQ_LEVEL;
beat_detect_pending_interrupts(i, pending);
__asm__ ("cntlzd %0,%1":"=r"(ub):
"r"(pending[0] & beatic_irq_mask_enable[i/64+0]
- & beatic_irq_mask_ack[i/64+0]));
+ & beatic_irq_mask_ack[i/64+0]));
if (ub != 64)
return i + ub + 0;
__asm__ ("cntlzd %0,%1":"=r"(ub):
"r"(pending[1] & beatic_irq_mask_enable[i/64+1]
- & beatic_irq_mask_ack[i/64+1]));
+ & beatic_irq_mask_ack[i/64+1]));
if (ub != 64)
return i + ub + 64;
__asm__ ("cntlzd %0,%1":"=r"(ub):
"r"(pending[2] & beatic_irq_mask_enable[i/64+2]
- & beatic_irq_mask_ack[i/64+2]));
+ & beatic_irq_mask_ack[i/64+2]));
if (ub != 64)
return i + ub + 128;
__asm__ ("cntlzd %0,%1":"=r"(ub):
"r"(pending[3] & beatic_irq_mask_enable[i/64+3]
- & beatic_irq_mask_ack[i/64+3]));
+ & beatic_irq_mask_ack[i/64+3]));
if (ub != 64)
return i + ub + 192;
}
/* Allocate an irq host */
beatic_host = irq_alloc_host(NULL, IRQ_HOST_MAP_NOMAP, 0,
- &beatic_pic_host_ops,
+ &beatic_pic_host_ops,
0);
BUG_ON(beatic_host == NULL);
irq_set_default_host(beatic_host);
if (bus != hose->bus)
addr = celleb_epci_get_epci_cfg(hose) +
(((bus->number & 0xff) << 16)
- | ((devfn & 0xff) << 8)
- | (where & 0xff)
- | 0x01000000);
+ | ((devfn & 0xff) << 8)
+ | (where & 0xff)
+ | 0x01000000);
else
addr = celleb_epci_get_epci_cfg(hose) +
(((devfn & 0xff) << 8) | (where & 0xff));
}
static int celleb_epci_read_config(struct pci_bus *bus,
- unsigned int devfn, int where, int size, u32 * val)
+ unsigned int devfn, int where, int size, u32 *val)
{
PCI_IO_ADDR epci_base;
PCI_IO_ADDR addr;
/* sio irq0=0xb00010022 irq0=0xb00010023 irq2=0xb00010024
mmio=0xfff000-0x1000,0xff2000-0x1000 */
-static int txx9_serial_bitmap __initdata = 0;
+static int txx9_serial_bitmap __initdata;
static struct {
uint32_t offset;
int i;
for (;;) {
- switch(get_option(&ptr, &i)) {
+ switch (get_option(&ptr, &i)) {
default:
return 0;
case 2:
return enable;
}
-const struct spu_priv1_ops spu_priv1_beat_ops =
-{
+const struct spu_priv1_ops spu_priv1_beat_ops = {
.int_mask_and = int_mask_and,
.int_mask_or = int_mask_or,
.int_mask_set = int_mask_set,
if (inbuflen == 0) {
/* get some more chars. */
inbuflen = 0;
- rc = beat_get_term_char(celleb_vtermno, &inbuflen, inbuf+0, inbuf+1);
+ rc = beat_get_term_char(celleb_vtermno, &inbuflen,
+ inbuf+0, inbuf+1);
if (rc != 0)
inbuflen = 0; /* otherwise inbuflen is garbage */
}
if (ch == -1) {
/* This shouldn't be needed...but... */
volatile unsigned long delay;
- for (delay=0; delay < 2000000; delay++)
+ for (delay = 0; delay < 2000000; delay++)
;
} else {
return ch;
}
if (mpic_paddr == 0) {
- printk("%s: No tsi108 PIC found !\n", __FUNCTION__);
+ printk("%s: No tsi108 PIC found !\n", __func__);
return;
}
- DBG("%s: tsi108 pic phys_addr = 0x%x\n", __FUNCTION__,
+ DBG("%s: tsi108 pic phys_addr = 0x%x\n", __func__,
(u32) mpic_paddr);
mpic = mpic_alloc(tsi_pic, mpic_paddr,
#ifdef CONFIG_PCI
tsi_pci = of_find_node_by_type(NULL, "pci");
if (tsi_pci == NULL) {
- printk("%s: No tsi108 pci node found !\n", __FUNCTION__);
+ printk("%s: No tsi108 pci node found !\n", __func__);
return;
}
cascade_node = of_find_node_by_type(NULL, "pic-router");
if (cascade_node == NULL) {
- printk("%s: No tsi108 pci cascade node found !\n", __FUNCTION__);
+ printk("%s: No tsi108 pci cascade node found !\n", __func__);
return;
}
cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
- DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __FUNCTION__,
+ DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__,
(u32) cascade_pci_irq);
tsi108_pci_int_init(cascade_node);
set_irq_data(cascade_pci_irq, mpic);
* ioremap mpp and gpp registers in case they are later
* needed by prpmc2800_reset_board().
*/
- np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-mpp");
+ np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-mpp");
reg = of_get_property(np, "reg", NULL);
paddr = of_translate_address(np, reg);
of_node_put(np);
mv64x60_mpp_reg_base = ioremap(paddr, reg[1]);
- np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-gpp");
+ np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
reg = of_get_property(np, "reg", NULL);
paddr = of_translate_address(np, reg);
of_node_put(np);
.globl system_reset_iSeries
system_reset_iSeries:
- mfspr r13,SPRN_SPRG3 /* Get paca address */
+ mfspr r13,SPRN_SPRG3 /* Get alpaca address */
+ LOAD_REG_IMMEDIATE(r23, alpaca)
+ li r0,ALPACA_SIZE
+ sub r23,r13,r23
+ divdu r23,r23,r0 /* r23 has cpu number */
+ LOAD_REG_IMMEDIATE(r13, paca)
+ mulli r0,r23,PACA_SIZE
+ add r13,r13,r0
+ mtspr SPRN_SPRG3,r13 /* Save it away for the future */
mfmsr r24
ori r24,r24,MSR_RI
mtmsrd r24 /* RI on */
- lhz r24,PACAPACAINDEX(r13) /* Get processor # */
+ mr r24,r23
cmpwi 0,r24,0 /* Are we processor 0? */
bne 1f
b .__start_initialization_iSeries /* Start up the first processor */
u64 xRsvd13; // Reserved x38-x3F
};
-extern struct ItIplParmsReal xItIplParmsReal;
-
#endif /* _ISERIES_IPL_PARMS_H */
#include <asm/ptrace.h>
#include <asm/abs_addr.h>
#include <asm/lppaca.h>
-#include <asm/iseries/it_lp_reg_save.h>
#include <asm/paca.h>
#include <asm/iseries/lpar_map.h>
#include <asm/iseries/it_lp_queue.h>
+#include <asm/iseries/alpaca.h>
#include "naca.h"
#include "vpd_areas.h"
/* The HvReleaseData is the root of the information shared between
* the hypervisor and Linux.
*/
-struct HvReleaseData hvReleaseData = {
+const struct HvReleaseData hvReleaseData = {
.xDesc = 0xc8a5d9c4, /* "HvRD" ebcdic */
.xSize = sizeof(struct HvReleaseData),
.xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas),
.xRamDiskSize = 0,
};
+struct ItLpRegSave {
+ u32 xDesc; // Eye catcher "LpRS" ebcdic 000-003
+ u16 xSize; // Size of this class 004-005
+ u8 xInUse; // Area is live 006-007
+ u8 xRsvd1[9]; // Reserved 007-00F
+
+ u8 xFixedRegSave[352]; // Fixed Register Save Area 010-16F
+ u32 xCTRL; // Control Register 170-173
+ u32 xDEC; // Decrementer 174-177
+ u32 xFPSCR; // FP Status and Control Reg 178-17B
+ u32 xPVR; // Processor Version Number 17C-17F
+
+ u64 xMMCR0; // Monitor Mode Control Reg 0 180-187
+ u32 xPMC1; // Perf Monitor Counter 1 188-18B
+ u32 xPMC2; // Perf Monitor Counter 2 18C-18F
+ u32 xPMC3; // Perf Monitor Counter 3 190-193
+ u32 xPMC4; // Perf Monitor Counter 4 194-197
+ u32 xPIR; // Processor ID Reg 198-19B
+
+ u32 xMMCR1; // Monitor Mode Control Reg 1 19C-19F
+ u32 xMMCRA; // Monitor Mode Control Reg A 1A0-1A3
+ u32 xPMC5; // Perf Monitor Counter 5 1A4-1A7
+ u32 xPMC6; // Perf Monitor Counter 6 1A8-1AB
+ u32 xPMC7; // Perf Monitor Counter 7 1AC-1AF
+ u32 xPMC8; // Perf Monitor Counter 8 1B0-1B3
+ u32 xTSC; // Thread Switch Control 1B4-1B7
+ u32 xTST; // Thread Switch Timeout 1B8-1BB
+ u32 xRsvd; // Reserved 1BC-1BF
+
+ u64 xACCR; // Address Compare Control Reg 1C0-1C7
+ u64 xIMR; // Instruction Match Register 1C8-1CF
+ u64 xSDR1; // Storage Description Reg 1 1D0-1D7
+ u64 xSPRG0; // Special Purpose Reg General0 1D8-1DF
+ u64 xSPRG1; // Special Purpose Reg General1 1E0-1E7
+ u64 xSPRG2; // Special Purpose Reg General2 1E8-1EF
+ u64 xSPRG3; // Special Purpose Reg General3 1F0-1F7
+ u64 xTB; // Time Base Register 1F8-1FF
+
+ u64 xFPR[32]; // Floating Point Registers 200-2FF
+
+ u64 xMSR; // Machine State Register 300-307
+ u64 xNIA; // Next Instruction Address 308-30F
+
+ u64 xDABR; // Data Address Breakpoint Reg 310-317
+ u64 xIABR; // Inst Address Breakpoint Reg 318-31F
+
+ u64 xHID0; // HW Implementation Dependent0 320-327
+
+ u64 xHID4; // HW Implementation Dependent4 328-32F
+ u64 xSCOMd; // SCON Data Reg (SPRG4) 330-337
+ u64 xSCOMc; // SCON Command Reg (SPRG5) 338-33F
+ u64 xSDAR; // Sample Data Address Register 340-347
+ u64 xSIAR; // Sample Inst Address Register 348-34F
+
+ u8 xRsvd3[176]; // Reserved 350-3FF
+};
+
extern void system_reset_iSeries(void);
extern void machine_check_iSeries(void);
extern void data_access_iSeries(void);
};
/* May be filled in by the hypervisor so cannot end up in the BSS */
-struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
+static struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
/* May be filled in by the hypervisor so cannot end up in the BSS */
struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data")));
/* Space for Recovery Log Buffer */
/* May be filled in by the hypervisor so cannot end up in the BSS */
-u64 xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
+static u64 xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
-struct SpCommArea xSpCommArea = {
+static const struct SpCommArea xSpCommArea = {
.xDesc = 0xE2D7C3C2,
.xFormat = 1,
};
+static const struct ItLpRegSave iseries_reg_save[] = {
+ [0 ... (NR_CPUS-1)] = {
+ .xDesc = 0xd397d9e2, /* "LpRS" */
+ .xSize = sizeof(struct ItLpRegSave),
+ },
+};
+
+#define ALPACA_INIT(number) \
+{ \
+ .lppaca_ptr = &lppaca[number], \
+ .reg_save_ptr = &iseries_reg_save[number], \
+}
+
+const struct alpaca alpaca[] = {
+ ALPACA_INIT( 0),
+#if NR_CPUS > 1
+ ALPACA_INIT( 1), ALPACA_INIT( 2), ALPACA_INIT( 3),
+#if NR_CPUS > 4
+ ALPACA_INIT( 4), ALPACA_INIT( 5), ALPACA_INIT( 6), ALPACA_INIT( 7),
+#if NR_CPUS > 8
+ ALPACA_INIT( 8), ALPACA_INIT( 9), ALPACA_INIT(10), ALPACA_INIT(11),
+ ALPACA_INIT(12), ALPACA_INIT(13), ALPACA_INIT(14), ALPACA_INIT(15),
+ ALPACA_INIT(16), ALPACA_INIT(17), ALPACA_INIT(18), ALPACA_INIT(19),
+ ALPACA_INIT(20), ALPACA_INIT(21), ALPACA_INIT(22), ALPACA_INIT(23),
+ ALPACA_INIT(24), ALPACA_INIT(25), ALPACA_INIT(26), ALPACA_INIT(27),
+ ALPACA_INIT(28), ALPACA_INIT(29), ALPACA_INIT(30), ALPACA_INIT(31),
+#if NR_CPUS > 32
+ ALPACA_INIT(32), ALPACA_INIT(33), ALPACA_INIT(34), ALPACA_INIT(35),
+ ALPACA_INIT(36), ALPACA_INIT(37), ALPACA_INIT(38), ALPACA_INIT(39),
+ ALPACA_INIT(40), ALPACA_INIT(41), ALPACA_INIT(42), ALPACA_INIT(43),
+ ALPACA_INIT(44), ALPACA_INIT(45), ALPACA_INIT(46), ALPACA_INIT(47),
+ ALPACA_INIT(48), ALPACA_INIT(49), ALPACA_INIT(50), ALPACA_INIT(51),
+ ALPACA_INIT(52), ALPACA_INIT(53), ALPACA_INIT(54), ALPACA_INIT(55),
+ ALPACA_INIT(56), ALPACA_INIT(57), ALPACA_INIT(58), ALPACA_INIT(59),
+ ALPACA_INIT(60), ALPACA_INIT(61), ALPACA_INIT(62), ALPACA_INIT(63),
+#endif
+#endif
+#endif
+#endif
+};
+
/* The LparMap data is now located at offset 0x6000 in head.S
* It was put there so that the HvReleaseData could address it
* with a 32-bit offset as required by the iSeries hypervisor
* the Naca via the HvReleaseData area. The HvReleaseData has the
* offset into the Naca of the pointer to the ItVpdAreas.
*/
-struct ItVpdAreas itVpdAreas = {
+const struct ItVpdAreas itVpdAreas = {
.xSlicDesc = 0xc9a3e5c1, /* "ItVA" */
.xSlicSize = sizeof(struct ItVpdAreas),
.xSlicVpdEntries = ItVpdMaxEntries, /* # VPD array entries */
.xSlicVpdLens = { /* VPD lengths */
0,0,0, /* 0 - 2 */
sizeof(xItExtVpdPanel), /* 3 Extended VPD */
- sizeof(struct paca_struct), /* 4 length of Paca */
+ sizeof(struct alpaca), /* 4 length of (fake) Paca */
0, /* 5 */
sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */
26992, /* 7 length of MS VPD */
.xSlicVpdAdrs = { /* VPD addresses */
0,0,0, /* 0 - 2 */
&xItExtVpdPanel, /* 3 Extended VPD */
- &paca[0], /* 4 first Paca */
+ &alpaca[0], /* 4 first (fake) Paca */
0, /* 5 */
&xItIplParmsReal, /* 6 IPL parms */
&xMsVpd, /* 7 MS Vpd */
0,0
}
};
-
-struct ItLpRegSave iseries_reg_save[] = {
- [0 ... (NR_CPUS-1)] = {
- .xDesc = 0xd397d9e2, /* "LpRS" */
- .xSize = sizeof(struct ItLpRegSave),
- },
-};
struct naca_struct {
/* Kernel only data - undefined for user space */
- void *xItVpdAreas; /* VPD Data 0x00 */
+ const void *xItVpdAreas; /* VPD Data 0x00 */
void *xRamDisk; /* iSeries ramdisk 0x08 */
u64 xRamDiskSize; /* In pages 0x10 */
};
#undef DEBUG
+#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/string.h>
static unsigned long last_jiffies;
static int num_printed;
- if ((jiffies - last_jiffies) > 60 * HZ) {
+ if (time_after(jiffies, last_jiffies + 60 * HZ)) {
last_jiffies = jiffies;
num_printed = 0;
}
char xRsvd3[20]; /* Reserved x2C-x3F */
};
-extern struct HvReleaseData hvReleaseData;
+extern const struct HvReleaseData hvReleaseData;
#endif /* _ISERIES_RELEASE_DATA_H */
u8 xRsvd2[80]; // Reserved 030-07F
};
-extern struct SpCommArea xSpCommArea;
-
#endif /* _ISERIES_SPCOMM_AREA_H */
u32 xPlicDmaLens[ItDmaMaxEntries];// Array of DMA lengths 080-0A7
u32 xPlicDmaToks[ItDmaMaxEntries];// Array of DMA tokens 0A8-0CF
u32 xSlicVpdLens[ItVpdMaxEntries];// Array of VPD lengths 0D0-12F
- void *xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers 130-1EF
+ const void *xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers 130-1EF
};
-extern struct ItVpdAreas itVpdAreas;
+extern const struct ItVpdAreas itVpdAreas;
#endif /* _ISERIES_VPD_AREAS_H */
}
return irq;
}
-
-/* XXX: To remove once all firmwares are ok */
-static void fixup_maple_ide(struct pci_dev* dev)
-{
- if (!machine_is(maple))
- return;
-
-#if 0 /* Enable this to enable IDE port 0 */
- {
- u8 v;
-
- pci_read_config_byte(dev, 0x40, &v);
- v |= 2;
- pci_write_config_byte(dev, 0x40, v);
- }
-#endif
-#if 0 /* fix bus master base */
- pci_write_config_dword(dev, 0x20, 0xcc01);
- printk("old ide resource: %lx -> %lx \n",
- dev->resource[4].start, dev->resource[4].end);
- dev->resource[4].start = 0xcc00;
- dev->resource[4].end = 0xcc10;
-#endif
-#if 0 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */
- {
- struct pci_dev *apicdev;
- u32 v;
-
- apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0));
- if (apicdev == NULL)
- printk("IDE Fixup IRQ: Can't find IO-APIC !\n");
- else {
- pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14);
- pci_read_config_dword(apicdev, 0xf4, &v);
- v &= ~0x00000022;
- pci_write_config_dword(apicdev, 0xf4, v);
- pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15);
- pci_read_config_dword(apicdev, 0xf4, &v);
- v &= ~0x00000022;
- pci_write_config_dword(apicdev, 0xf4, v);
- pci_dev_put(apicdev);
- }
- }
-#endif
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE,
- fixup_maple_ide);
#include <linux/smp.h>
#include <linux/bitops.h>
#include <linux/of_device.h>
+#include <linux/lmb.h>
#include <asm/processor.h>
#include <asm/sections.h>
#include <asm/dma.h>
#include <asm/cputable.h>
#include <asm/time.h>
-#include <asm/lmb.h>
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/udbg.h>
return 1;
}
-define_machine(maple_md) {
+define_machine(maple) {
.name = "Maple",
.probe = maple_probe,
.setup_arch = maple_setup_arch,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#define MAX_TXCH 64
#define MAX_RXCH 64
+#define MAX_FLAGS 64
+#define MAX_FUN 8
static struct pasdma_status *dma_status;
static DECLARE_BITMAP(txch_free, MAX_TXCH);
static DECLARE_BITMAP(rxch_free, MAX_RXCH);
+static DECLARE_BITMAP(flags_free, MAX_FLAGS);
+static DECLARE_BITMAP(fun_free, MAX_FUN);
/* pasemi_read_iob_reg - read IOB register
* @reg: Register to read (offset into PCI CFG space)
}
EXPORT_SYMBOL(pasemi_dma_free_buf);
+/* pasemi_dma_alloc_flag - Allocate a flag (event) for channel syncronization
+ *
+ * Allocates a flag for use with channel syncronization (event descriptors).
+ * Returns allocated flag (0-63), < 0 on error.
+ */
+int pasemi_dma_alloc_flag(void)
+{
+ int bit;
+
+retry:
+ bit = find_next_bit(flags_free, MAX_FLAGS, 0);
+ if (bit >= MAX_FLAGS)
+ return -ENOSPC;
+ if (!test_and_clear_bit(bit, flags_free))
+ goto retry;
+
+ return bit;
+}
+EXPORT_SYMBOL(pasemi_dma_alloc_flag);
+
+
+/* pasemi_dma_free_flag - Deallocates a flag (event)
+ * @flag: Flag number to deallocate
+ *
+ * Frees up a flag so it can be reused for other purposes.
+ */
+void pasemi_dma_free_flag(int flag)
+{
+ BUG_ON(test_bit(flag, flags_free));
+ BUG_ON(flag >= MAX_FLAGS);
+ set_bit(flag, flags_free);
+}
+EXPORT_SYMBOL(pasemi_dma_free_flag);
+
+
+/* pasemi_dma_set_flag - Sets a flag (event) to 1
+ * @flag: Flag number to set active
+ *
+ * Sets the flag provided to 1.
+ */
+void pasemi_dma_set_flag(int flag)
+{
+ BUG_ON(flag >= MAX_FLAGS);
+ if (flag < 32)
+ pasemi_write_dma_reg(PAS_DMA_TXF_SFLG0, 1 << flag);
+ else
+ pasemi_write_dma_reg(PAS_DMA_TXF_SFLG1, 1 << flag);
+}
+EXPORT_SYMBOL(pasemi_dma_set_flag);
+
+/* pasemi_dma_clear_flag - Sets a flag (event) to 0
+ * @flag: Flag number to set inactive
+ *
+ * Sets the flag provided to 0.
+ */
+void pasemi_dma_clear_flag(int flag)
+{
+ BUG_ON(flag >= MAX_FLAGS);
+ if (flag < 32)
+ pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 1 << flag);
+ else
+ pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 1 << flag);
+}
+EXPORT_SYMBOL(pasemi_dma_clear_flag);
+
+/* pasemi_dma_alloc_fun - Allocate a function engine
+ *
+ * Allocates a function engine to use for crypto/checksum offload
+ * Returns allocated engine (0-8), < 0 on error.
+ */
+int pasemi_dma_alloc_fun(void)
+{
+ int bit;
+
+retry:
+ bit = find_next_bit(fun_free, MAX_FLAGS, 0);
+ if (bit >= MAX_FLAGS)
+ return -ENOSPC;
+ if (!test_and_clear_bit(bit, fun_free))
+ goto retry;
+
+ return bit;
+}
+EXPORT_SYMBOL(pasemi_dma_alloc_fun);
+
+
+/* pasemi_dma_free_fun - Deallocates a function engine
+ * @flag: Engine number to deallocate
+ *
+ * Frees up a function engine so it can be used for other purposes.
+ */
+void pasemi_dma_free_fun(int fun)
+{
+ BUG_ON(test_bit(fun, fun_free));
+ BUG_ON(fun >= MAX_FLAGS);
+ set_bit(fun, fun_free);
+}
+EXPORT_SYMBOL(pasemi_dma_free_fun);
+
+
static void *map_onedev(struct pci_dev *p, int index)
{
struct device_node *dn;
struct resource res;
struct device_node *dn;
int i, intf, err = 0;
+ unsigned long timeout;
u32 tmp;
if (!machine_is(pasemi))
for (i = 0; i < MAX_RXCH; i++)
__set_bit(i, rxch_free);
+ timeout = jiffies + HZ;
+ pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, 0);
+ while (pasemi_read_dma_reg(PAS_DMA_COM_RXSTA) & 1) {
+ if (time_after(jiffies, timeout)) {
+ pr_warning("Warning: Could not disable RX section\n");
+ break;
+ }
+ }
+
+ timeout = jiffies + HZ;
+ pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, 0);
+ while (pasemi_read_dma_reg(PAS_DMA_COM_TXSTA) & 1) {
+ if (time_after(jiffies, timeout)) {
+ pr_warning("Warning: Could not disable TX section\n");
+ break;
+ }
+ }
+
+ /* setup resource allocations for the different DMA sections */
+ tmp = pasemi_read_dma_reg(PAS_DMA_COM_CFG);
+ pasemi_write_dma_reg(PAS_DMA_COM_CFG, tmp | 0x18000000);
+
+ /* enable tx section */
+ pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
+
+ /* enable rx section */
+ pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
+
+ for (i = 0; i < MAX_FLAGS; i++)
+ __set_bit(i, flags_free);
+
+ for (i = 0; i < MAX_FUN; i++)
+ __set_bit(i, fun_free);
+
+ /* clear all status flags */
+ pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 0xffffffff);
+ pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 0xffffffff);
+
printk(KERN_INFO "PA Semi PWRficient DMA library initialized "
"(%d tx, %d rx channels)\n", num_txch, num_rxch);
/*
- * Copyright (C) 2005-2007, PA Semi, Inc
+ * Copyright (C) 2005-2008, PA Semi, Inc
*
* Maintained by: Olof Johansson <olof@lixom.net>
*
#include <asm/abs_addr.h>
#include <asm/firmware.h>
-
#define IOBMAP_PAGE_SHIFT 12
#define IOBMAP_PAGE_SIZE (1 << IOBMAP_PAGE_SHIFT)
#define IOBMAP_PAGE_MASK (IOBMAP_PAGE_SIZE - 1)
#define IOB_BASE 0xe0000000
#define IOB_SIZE 0x3000
/* Configuration registers */
-#define IOBCAP_REG 0x10
-#define IOBCOM_REG 0x40
+#define IOBCAP_REG 0x40
+#define IOBCOM_REG 0x100
/* Enable IOB address translation */
#define IOBCOM_ATEN 0x00000100
/* Address decode configuration register */
-#define IOB_AD_REG 0x53
+#define IOB_AD_REG 0x14c
/* IOBCOM_AD_REG fields */
#define IOB_AD_VGPRT 0x00000e00
#define IOB_AD_VGAEN 0x00000100
#define IOB_AD_TRNG_2G 0x00000001
#define IOB_AD_TRNG_128G 0x00000003
-#define IOB_TABLEBASE_REG 0x55
+#define IOB_TABLEBASE_REG 0x154
/* Base of the 64 4-byte L1 registers */
-#define IOB_XLT_L1_REGBASE 0xac0
+#define IOB_XLT_L1_REGBASE 0x2b00
/* Register to invalidate TLB entries */
-#define IOB_AT_INVAL_TLB_REG 0xb40
+#define IOB_AT_INVAL_TLB_REG 0x2d00
/* The top two bits of the level 1 entry contains valid and type flags */
#define IOBMAP_L1E_V 0x40000000
#define IOBMAP_L2E_V 0x80000000
#define IOBMAP_L2E_V_CACHED 0xc0000000
-static u32 __iomem *iob;
+static void __iomem *iob;
static u32 iob_l1_emptyval;
static u32 iob_l2_emptyval;
static u32 *iob_l2_base;
for (i = 0; i < 64; i++) {
/* Each L1 covers 32MB, i.e. 8K entries = 32K of ram */
regword = IOBMAP_L1E_V | (__pa(iob_l2_base + i*0x2000) >> 12);
- out_le32(iob+IOB_XLT_L1_REGBASE+i, regword);
+ out_le32(iob+IOB_XLT_L1_REGBASE+i*4, regword);
}
/* set 2GB translation window, based at 0 */
#include <linux/module.h>
#include <linux/mutex.h>
-#include <asm/semaphore.h>
#include <asm/prom.h>
#include <asm/pmac_pfunc.h>
#include <linux/suspend.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
+#include <linux/lmb.h>
#include <asm/reg.h>
#include <asm/sections.h>
#include <asm/iommu.h>
#include <asm/smu.h>
#include <asm/pmc.h>
-#include <asm/lmb.h>
#include <asm/udbg.h>
#include "pmac.h"
}
/**
- * ps3_register_repository_device - Register a device from the repositiory info.
- *
+ * ps3_setup_dynamic_device - Setup a dynamic device from the repository
*/
-static int ps3_register_repository_device(
- const struct ps3_repository_device *repo)
+static int ps3_setup_dynamic_device(const struct ps3_repository_device *repo)
{
int result;
switch (repo->dev_type) {
- case PS3_DEV_TYPE_SB_GELIC:
- result = ps3_setup_gelic_device(repo);
- if (result) {
- pr_debug("%s:%d ps3_setup_gelic_device failed\n",
- __func__, __LINE__);
- }
- break;
- case PS3_DEV_TYPE_SB_USB:
-
- /* Each USB device has both an EHCI and an OHCI HC */
-
- result = ps3_setup_ehci_device(repo);
-
- if (result) {
- pr_debug("%s:%d ps3_setup_ehci_device failed\n",
- __func__, __LINE__);
- }
-
- result = ps3_setup_ohci_device(repo);
-
- if (result) {
- pr_debug("%s:%d ps3_setup_ohci_device failed\n",
- __func__, __LINE__);
- }
- break;
case PS3_DEV_TYPE_STOR_DISK:
result = ps3_setup_storage_dev(repo, PS3_MATCH_ID_STOR_DISK);
return result;
}
+/**
+ * ps3_setup_static_device - Setup a static device from the repository
+ */
+
+static int __init ps3_setup_static_device(const struct ps3_repository_device *repo)
+{
+ int result;
+
+ switch (repo->dev_type) {
+ case PS3_DEV_TYPE_SB_GELIC:
+ result = ps3_setup_gelic_device(repo);
+ if (result) {
+ pr_debug("%s:%d ps3_setup_gelic_device failed\n",
+ __func__, __LINE__);
+ }
+ break;
+ case PS3_DEV_TYPE_SB_USB:
+
+ /* Each USB device has both an EHCI and an OHCI HC */
+
+ result = ps3_setup_ehci_device(repo);
+
+ if (result) {
+ pr_debug("%s:%d ps3_setup_ehci_device failed\n",
+ __func__, __LINE__);
+ }
+
+ result = ps3_setup_ohci_device(repo);
+
+ if (result) {
+ pr_debug("%s:%d ps3_setup_ohci_device failed\n",
+ __func__, __LINE__);
+ }
+ break;
+
+ default:
+ return ps3_setup_dynamic_device(repo);
+ }
+
+ return result;
+}
+
static void ps3_find_and_add_device(u64 bus_id, u64 dev_id)
{
struct ps3_repository_device repo;
pr_debug("%s:%u: device %lu:%lu found after %u retries\n",
__func__, __LINE__, bus_id, dev_id, retries);
- ps3_register_repository_device(&repo);
+ ps3_setup_dynamic_device(&repo);
return;
}
ps3_register_graphics_devices();
- ps3_repository_find_devices(PS3_BUS_TYPE_SB,
- ps3_register_repository_device);
+ ps3_repository_find_devices(PS3_BUS_TYPE_SB, ps3_setup_static_device);
ps3_register_sound_devices();
*/
#include <linux/kernel.h>
+#include <linux/lmb.h>
#include <asm/machdep.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/lv1call.h>
#include <asm/ps3fb.h>
asm volatile("cntlzd %0,%1" : "=r" (plug) : "r" (x));
plug &= 0x3f;
- if (unlikely(plug) == NO_IRQ) {
+ if (unlikely(plug == NO_IRQ)) {
pr_debug("%s:%d: no plug found: thread_id %lu\n", __func__,
__LINE__, pd->thread_id);
dump_bmp(&per_cpu(ps3_private, 0));
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/memory_hotplug.h>
+#include <linux/lmb.h>
#include <asm/firmware.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/lv1call.h>
#include <linux/fs.h>
#include <linux/syscalls.h>
#include <linux/ctype.h>
+#include <linux/lmb.h>
-#include <asm/lmb.h>
+#include <asm/prom.h>
#include "platform.h"
ps3_sys_manager_power_off(); /* never returns */
}
+static void ps3_halt(void)
+{
+ DBG("%s:%d\n", __func__, __LINE__);
+
+ smp_send_stop();
+ ps3_sys_manager_halt(); /* never returns */
+}
+
static void ps3_panic(char *str)
{
DBG("%s:%d %s\n", __func__, __LINE__, str);
printk(" Please press POWER button.\n");
printk("\n");
- while(1);
+ while(1)
+ lv1_pause(1);
}
#if defined(CONFIG_FB_PS3) || defined(CONFIG_FB_PS3_MODULE) || \
p->address = __alloc_bootmem(p->size, p->align, __pa(MAX_DMA_ADDRESS));
if (!p->address) {
- printk(KERN_ERR "%s: Cannot allocate %s\n", __FUNCTION__,
+ printk(KERN_ERR "%s: Cannot allocate %s\n", __func__,
p->name);
return;
}
.progress = ps3_progress,
.restart = ps3_restart,
.power_off = ps3_power_off,
+ .halt = ps3_halt,
#if defined(CONFIG_KEXEC)
.kexec_cpu_down = ps3_kexec_cpu_down,
.machine_kexec = default_machine_kexec,
#include <asm/spu.h>
#include <asm/spu_priv1.h>
#include <asm/lv1call.h>
+#include <asm/ps3.h>
#include "../cell/spufs/spufs.h"
#include "platform.h"
pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow);
}
+inline u64 ps3_get_spe_id(void *arg)
+{
+ return spu_pdata(arg)->spe_id;
+}
+EXPORT_SYMBOL_GPL(ps3_get_spe_id);
+
static unsigned long get_vas_id(void)
{
unsigned long id;
obj-$(CONFIG_HVC_CONSOLE) += hvconsole.o
obj-$(CONFIG_HVCS) += hvcserver.o
obj-$(CONFIG_HCALL_STATS) += hvCall_inst.o
+obj-$(CONFIG_PHYP_DUMP) += phyp_dump.o
unsigned int rets[3];
struct eeh_early_enable_info *info = data;
int ret;
- const char *status = of_get_property(dn, "status", NULL);
const u32 *class_code = of_get_property(dn, "class-code", NULL);
const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL);
const u32 *device_id = of_get_property(dn, "device-id", NULL);
pdn->eeh_freeze_count = 0;
pdn->eeh_false_positives = 0;
- if (status && strncmp(status, "ok", 2) != 0)
- return NULL; /* ignore devices with bad status */
+ if (!of_device_is_available(dn))
+ return NULL;
/* Ignore bad nodes. */
if (!class_code || !vendor_id || !device_id)
#include <asm/smp.h>
#include "plpar_wrappers.h"
+#include "pseries.h"
#ifdef DEBUG_LOW
#define DBG_LOW(fmt...) do { udbg_printf(fmt); } while(0)
struct device_node *stdout_node;
const u32 *termno;
const char *name;
- int add_console;
/* find the boot console from /chosen/stdout */
if (!of_chosen)
printk(KERN_WARNING "stdout node missing 'name' property!\n");
goto out;
}
- /* The user has requested a console so this is already set up. */
- add_console = !strstr(cmd_line, "console=");
/* Check if it's a virtual terminal */
if (strncmp(name, "vty", 3) != 0)
udbg_putc = udbg_putcLP;
udbg_getc = udbg_getcLP;
udbg_getc_poll = udbg_getc_pollLP;
- if (add_console)
- add_preferred_console("hvc", termno[0] & 0xff, NULL);
+ add_preferred_console("hvc", termno[0] & 0xff, NULL);
} else if (of_device_is_compatible(stdout_node, "hvterm-protocol")) {
vtermno = termno[0];
udbg_putc = udbg_hvsi_putc;
udbg_getc = udbg_hvsi_getc;
udbg_getc_poll = udbg_hvsi_getc_poll;
- if (add_console)
- add_preferred_console("hvsi", termno[0] & 0xff, NULL);
+ add_preferred_console("hvsi", termno[0] & 0xff, NULL);
}
out:
of_node_put(stdout_node);
BUG_ON(lpar_rc != H_SUCCESS);
}
+static void pSeries_lpar_hpte_removebolted(unsigned long ea,
+ int psize, int ssize)
+{
+ unsigned long slot, vsid, va;
+
+ vsid = get_kernel_vsid(ea, ssize);
+ va = hpt_va(ea, vsid, ssize);
+
+ slot = pSeries_lpar_hpte_find(va, psize, ssize);
+ BUG_ON(slot == -1);
+
+ pSeries_lpar_hpte_invalidate(slot, va, psize, ssize, 0);
+}
+
/* Flag bits for H_BULK_REMOVE */
#define HBR_REQUEST 0x4000000000000000UL
#define HBR_RESPONSE 0x8000000000000000UL
ppc_md.hpte_updateboltedpp = pSeries_lpar_hpte_updateboltedpp;
ppc_md.hpte_insert = pSeries_lpar_hpte_insert;
ppc_md.hpte_remove = pSeries_lpar_hpte_remove;
+ ppc_md.hpte_removebolted = pSeries_lpar_hpte_removebolted;
ppc_md.flush_hash_range = pSeries_lpar_flush_hash_range;
ppc_md.hpte_clear_all = pSeries_lpar_hptab_clear;
}
struct pci_dev *dev;
list_for_each_entry(dev, &bus->devices, bus_list) {
- /*
- * Skip already-present devices (which are on the
- * global device list.)
- */
- if (list_empty(&dev->global_list)) {
+ /* Skip already-added devices */
+ if (!dev->is_added) {
int i;
/* Fill device archdata and setup iommu table */
/* Add to children of PCI bridge dev->bus */
child_bus = pci_add_new_bus(dev->bus, dev, sec_busno);
if (!child_bus) {
- printk (KERN_ERR "%s: could not add second bus\n", __FUNCTION__);
+ printk (KERN_ERR "%s: could not add second bus\n", __func__);
return -EIO;
}
sprintf(child_bus->name, "PCI Bus #%02x", child_bus->number);
--- /dev/null
+/*
+ * Hypervisor-assisted dump
+ *
+ * Linas Vepstas, Manish Ahuja 2008
+ * Copyright 2008 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kobject.h>
+#include <linux/mm.h>
+#include <linux/of.h>
+#include <linux/pfn.h>
+#include <linux/swap.h>
+#include <linux/sysfs.h>
+
+#include <asm/page.h>
+#include <asm/phyp_dump.h>
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/rtas.h>
+
+/* Variables, used to communicate data between early boot and late boot */
+static struct phyp_dump phyp_dump_vars;
+struct phyp_dump *phyp_dump_info = &phyp_dump_vars;
+
+static int ibm_configure_kernel_dump;
+/* ------------------------------------------------- */
+/* RTAS interfaces to declare the dump regions */
+
+struct dump_section {
+ u32 dump_flags;
+ u16 source_type;
+ u16 error_flags;
+ u64 source_address;
+ u64 source_length;
+ u64 length_copied;
+ u64 destination_address;
+};
+
+struct phyp_dump_header {
+ u32 version;
+ u16 num_of_sections;
+ u16 status;
+
+ u32 first_offset_section;
+ u32 dump_disk_section;
+ u64 block_num_dd;
+ u64 num_of_blocks_dd;
+ u32 offset_dd;
+ u32 maxtime_to_auto;
+ /* No dump disk path string used */
+
+ struct dump_section cpu_data;
+ struct dump_section hpte_data;
+ struct dump_section kernel_data;
+};
+
+/* The dump header *must be* in low memory, so .bss it */
+static struct phyp_dump_header phdr;
+
+#define NUM_DUMP_SECTIONS 3
+#define DUMP_HEADER_VERSION 0x1
+#define DUMP_REQUEST_FLAG 0x1
+#define DUMP_SOURCE_CPU 0x0001
+#define DUMP_SOURCE_HPTE 0x0002
+#define DUMP_SOURCE_RMO 0x0011
+#define DUMP_ERROR_FLAG 0x2000
+#define DUMP_TRIGGERED 0x4000
+#define DUMP_PERFORMED 0x8000
+
+
+/**
+ * init_dump_header() - initialize the header declaring a dump
+ * Returns: length of dump save area.
+ *
+ * When the hypervisor saves crashed state, it needs to put
+ * it somewhere. The dump header tells the hypervisor where
+ * the data can be saved.
+ */
+static unsigned long init_dump_header(struct phyp_dump_header *ph)
+{
+ unsigned long addr_offset = 0;
+
+ /* Set up the dump header */
+ ph->version = DUMP_HEADER_VERSION;
+ ph->num_of_sections = NUM_DUMP_SECTIONS;
+ ph->status = 0;
+
+ ph->first_offset_section =
+ (u32)offsetof(struct phyp_dump_header, cpu_data);
+ ph->dump_disk_section = 0;
+ ph->block_num_dd = 0;
+ ph->num_of_blocks_dd = 0;
+ ph->offset_dd = 0;
+
+ ph->maxtime_to_auto = 0; /* disabled */
+
+ /* The first two sections are mandatory */
+ ph->cpu_data.dump_flags = DUMP_REQUEST_FLAG;
+ ph->cpu_data.source_type = DUMP_SOURCE_CPU;
+ ph->cpu_data.source_address = 0;
+ ph->cpu_data.source_length = phyp_dump_info->cpu_state_size;
+ ph->cpu_data.destination_address = addr_offset;
+ addr_offset += phyp_dump_info->cpu_state_size;
+
+ ph->hpte_data.dump_flags = DUMP_REQUEST_FLAG;
+ ph->hpte_data.source_type = DUMP_SOURCE_HPTE;
+ ph->hpte_data.source_address = 0;
+ ph->hpte_data.source_length = phyp_dump_info->hpte_region_size;
+ ph->hpte_data.destination_address = addr_offset;
+ addr_offset += phyp_dump_info->hpte_region_size;
+
+ /* This section describes the low kernel region */
+ ph->kernel_data.dump_flags = DUMP_REQUEST_FLAG;
+ ph->kernel_data.source_type = DUMP_SOURCE_RMO;
+ ph->kernel_data.source_address = PHYP_DUMP_RMR_START;
+ ph->kernel_data.source_length = PHYP_DUMP_RMR_END;
+ ph->kernel_data.destination_address = addr_offset;
+ addr_offset += ph->kernel_data.source_length;
+
+ return addr_offset;
+}
+
+static void print_dump_header(const struct phyp_dump_header *ph)
+{
+#ifdef DEBUG
+ printk(KERN_INFO "dump header:\n");
+ /* setup some ph->sections required */
+ printk(KERN_INFO "version = %d\n", ph->version);
+ printk(KERN_INFO "Sections = %d\n", ph->num_of_sections);
+ printk(KERN_INFO "Status = 0x%x\n", ph->status);
+
+ /* No ph->disk, so all should be set to 0 */
+ printk(KERN_INFO "Offset to first section 0x%x\n",
+ ph->first_offset_section);
+ printk(KERN_INFO "dump disk sections should be zero\n");
+ printk(KERN_INFO "dump disk section = %d\n", ph->dump_disk_section);
+ printk(KERN_INFO "block num = %ld\n", ph->block_num_dd);
+ printk(KERN_INFO "number of blocks = %ld\n", ph->num_of_blocks_dd);
+ printk(KERN_INFO "dump disk offset = %d\n", ph->offset_dd);
+ printk(KERN_INFO "Max auto time= %d\n", ph->maxtime_to_auto);
+
+ /*set cpu state and hpte states as well scratch pad area */
+ printk(KERN_INFO " CPU AREA \n");
+ printk(KERN_INFO "cpu dump_flags =%d\n", ph->cpu_data.dump_flags);
+ printk(KERN_INFO "cpu source_type =%d\n", ph->cpu_data.source_type);
+ printk(KERN_INFO "cpu error_flags =%d\n", ph->cpu_data.error_flags);
+ printk(KERN_INFO "cpu source_address =%lx\n",
+ ph->cpu_data.source_address);
+ printk(KERN_INFO "cpu source_length =%lx\n",
+ ph->cpu_data.source_length);
+ printk(KERN_INFO "cpu length_copied =%lx\n",
+ ph->cpu_data.length_copied);
+
+ printk(KERN_INFO " HPTE AREA \n");
+ printk(KERN_INFO "HPTE dump_flags =%d\n", ph->hpte_data.dump_flags);
+ printk(KERN_INFO "HPTE source_type =%d\n", ph->hpte_data.source_type);
+ printk(KERN_INFO "HPTE error_flags =%d\n", ph->hpte_data.error_flags);
+ printk(KERN_INFO "HPTE source_address =%lx\n",
+ ph->hpte_data.source_address);
+ printk(KERN_INFO "HPTE source_length =%lx\n",
+ ph->hpte_data.source_length);
+ printk(KERN_INFO "HPTE length_copied =%lx\n",
+ ph->hpte_data.length_copied);
+
+ printk(KERN_INFO " SRSD AREA \n");
+ printk(KERN_INFO "SRSD dump_flags =%d\n", ph->kernel_data.dump_flags);
+ printk(KERN_INFO "SRSD source_type =%d\n", ph->kernel_data.source_type);
+ printk(KERN_INFO "SRSD error_flags =%d\n", ph->kernel_data.error_flags);
+ printk(KERN_INFO "SRSD source_address =%lx\n",
+ ph->kernel_data.source_address);
+ printk(KERN_INFO "SRSD source_length =%lx\n",
+ ph->kernel_data.source_length);
+ printk(KERN_INFO "SRSD length_copied =%lx\n",
+ ph->kernel_data.length_copied);
+#endif
+}
+
+static ssize_t show_phyp_dump_active(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+
+ /* create filesystem entry so kdump is phyp-dump aware */
+ return sprintf(buf, "%lx\n", phyp_dump_info->phyp_dump_at_boot);
+}
+
+static struct kobj_attribute pdl = __ATTR(phyp_dump_active, 0600,
+ show_phyp_dump_active,
+ NULL);
+
+static void register_dump_area(struct phyp_dump_header *ph, unsigned long addr)
+{
+ int rc;
+
+ /* Add addr value if not initialized before */
+ if (ph->cpu_data.destination_address == 0) {
+ ph->cpu_data.destination_address += addr;
+ ph->hpte_data.destination_address += addr;
+ ph->kernel_data.destination_address += addr;
+ }
+
+ /* ToDo Invalidate kdump and free memory range. */
+
+ do {
+ rc = rtas_call(ibm_configure_kernel_dump, 3, 1, NULL,
+ 1, ph, sizeof(struct phyp_dump_header));
+ } while (rtas_busy_delay(rc));
+
+ if (rc) {
+ printk(KERN_ERR "phyp-dump: unexpected error (%d) on "
+ "register\n", rc);
+ print_dump_header(ph);
+ return;
+ }
+
+ rc = sysfs_create_file(kernel_kobj, &pdl.attr);
+ if (rc)
+ printk(KERN_ERR "phyp-dump: unable to create sysfs"
+ " file (%d)\n", rc);
+}
+
+static
+void invalidate_last_dump(struct phyp_dump_header *ph, unsigned long addr)
+{
+ int rc;
+
+ /* Add addr value if not initialized before */
+ if (ph->cpu_data.destination_address == 0) {
+ ph->cpu_data.destination_address += addr;
+ ph->hpte_data.destination_address += addr;
+ ph->kernel_data.destination_address += addr;
+ }
+
+ do {
+ rc = rtas_call(ibm_configure_kernel_dump, 3, 1, NULL,
+ 2, ph, sizeof(struct phyp_dump_header));
+ } while (rtas_busy_delay(rc));
+
+ if (rc) {
+ printk(KERN_ERR "phyp-dump: unexpected error (%d) "
+ "on invalidate\n", rc);
+ print_dump_header(ph);
+ }
+}
+
+/* ------------------------------------------------- */
+/**
+ * release_memory_range -- release memory previously lmb_reserved
+ * @start_pfn: starting physical frame number
+ * @nr_pages: number of pages to free.
+ *
+ * This routine will release memory that had been previously
+ * lmb_reserved in early boot. The released memory becomes
+ * available for genreal use.
+ */
+static void release_memory_range(unsigned long start_pfn,
+ unsigned long nr_pages)
+{
+ struct page *rpage;
+ unsigned long end_pfn;
+ long i;
+
+ end_pfn = start_pfn + nr_pages;
+
+ for (i = start_pfn; i <= end_pfn; i++) {
+ rpage = pfn_to_page(i);
+ if (PageReserved(rpage)) {
+ ClearPageReserved(rpage);
+ init_page_count(rpage);
+ __free_page(rpage);
+ totalram_pages++;
+ }
+ }
+}
+
+/**
+ * track_freed_range -- Counts the range being freed.
+ * Once the counter goes to zero, it re-registers dump for
+ * future use.
+ */
+static void
+track_freed_range(unsigned long addr, unsigned long length)
+{
+ static unsigned long scratch_area_size, reserved_area_size;
+
+ if (addr < phyp_dump_info->init_reserve_start)
+ return;
+
+ if ((addr >= phyp_dump_info->init_reserve_start) &&
+ (addr <= phyp_dump_info->init_reserve_start +
+ phyp_dump_info->init_reserve_size))
+ reserved_area_size += length;
+
+ if ((addr >= phyp_dump_info->reserved_scratch_addr) &&
+ (addr <= phyp_dump_info->reserved_scratch_addr +
+ phyp_dump_info->reserved_scratch_size))
+ scratch_area_size += length;
+
+ if ((reserved_area_size == phyp_dump_info->init_reserve_size) &&
+ (scratch_area_size == phyp_dump_info->reserved_scratch_size)) {
+
+ invalidate_last_dump(&phdr,
+ phyp_dump_info->reserved_scratch_addr);
+ register_dump_area(&phdr,
+ phyp_dump_info->reserved_scratch_addr);
+ }
+}
+
+/* ------------------------------------------------- */
+/**
+ * sysfs_release_region -- sysfs interface to release memory range.
+ *
+ * Usage:
+ * "echo <start addr> <length> > /sys/kernel/release_region"
+ *
+ * Example:
+ * "echo 0x40000000 0x10000000 > /sys/kernel/release_region"
+ *
+ * will release 256MB starting at 1GB.
+ */
+static ssize_t store_release_region(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ unsigned long start_addr, length, end_addr;
+ unsigned long start_pfn, nr_pages;
+ ssize_t ret;
+
+ ret = sscanf(buf, "%lx %lx", &start_addr, &length);
+ if (ret != 2)
+ return -EINVAL;
+
+ track_freed_range(start_addr, length);
+
+ /* Range-check - don't free any reserved memory that
+ * wasn't reserved for phyp-dump */
+ if (start_addr < phyp_dump_info->init_reserve_start)
+ start_addr = phyp_dump_info->init_reserve_start;
+
+ end_addr = phyp_dump_info->init_reserve_start +
+ phyp_dump_info->init_reserve_size;
+ if (start_addr+length > end_addr)
+ length = end_addr - start_addr;
+
+ /* Release the region of memory assed in by user */
+ start_pfn = PFN_DOWN(start_addr);
+ nr_pages = PFN_DOWN(length);
+ release_memory_range(start_pfn, nr_pages);
+
+ return count;
+}
+
+static ssize_t show_release_region(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ u64 second_addr_range;
+
+ /* total reserved size - start of scratch area */
+ second_addr_range = phyp_dump_info->init_reserve_size -
+ phyp_dump_info->reserved_scratch_size;
+ return sprintf(buf, "CPU:0x%lx-0x%lx: HPTE:0x%lx-0x%lx:"
+ " DUMP:0x%lx-0x%lx, 0x%lx-0x%lx:\n",
+ phdr.cpu_data.destination_address,
+ phdr.cpu_data.length_copied,
+ phdr.hpte_data.destination_address,
+ phdr.hpte_data.length_copied,
+ phdr.kernel_data.destination_address,
+ phdr.kernel_data.length_copied,
+ phyp_dump_info->init_reserve_start,
+ second_addr_range);
+}
+
+static struct kobj_attribute rr = __ATTR(release_region, 0600,
+ show_release_region,
+ store_release_region);
+
+static int __init phyp_dump_setup(void)
+{
+ struct device_node *rtas;
+ const struct phyp_dump_header *dump_header = NULL;
+ unsigned long dump_area_start;
+ unsigned long dump_area_length;
+ int header_len = 0;
+ int rc;
+
+ /* If no memory was reserved in early boot, there is nothing to do */
+ if (phyp_dump_info->init_reserve_size == 0)
+ return 0;
+
+ /* Return if phyp dump not supported */
+ if (!phyp_dump_info->phyp_dump_configured)
+ return -ENOSYS;
+
+ /* Is there dump data waiting for us? If there isn't,
+ * then register a new dump area, and release all of
+ * the rest of the reserved ram.
+ *
+ * The /rtas/ibm,kernel-dump rtas node is present only
+ * if there is dump data waiting for us.
+ */
+ rtas = of_find_node_by_path("/rtas");
+ if (rtas) {
+ dump_header = of_get_property(rtas, "ibm,kernel-dump",
+ &header_len);
+ of_node_put(rtas);
+ }
+
+ print_dump_header(dump_header);
+ dump_area_length = init_dump_header(&phdr);
+ /* align down */
+ dump_area_start = phyp_dump_info->init_reserve_start & PAGE_MASK;
+
+ if (dump_header == NULL) {
+ register_dump_area(&phdr, dump_area_start);
+ return 0;
+ }
+
+ /* re-register the dump area, if old dump was invalid */
+ if ((dump_header) && (dump_header->status & DUMP_ERROR_FLAG)) {
+ invalidate_last_dump(&phdr, dump_area_start);
+ register_dump_area(&phdr, dump_area_start);
+ return 0;
+ }
+
+ if (dump_header) {
+ phyp_dump_info->reserved_scratch_addr =
+ dump_header->cpu_data.destination_address;
+ phyp_dump_info->reserved_scratch_size =
+ dump_header->cpu_data.source_length +
+ dump_header->hpte_data.source_length +
+ dump_header->kernel_data.source_length;
+ }
+
+ /* Should we create a dump_subsys, analogous to s390/ipl.c ? */
+ rc = sysfs_create_file(kernel_kobj, &rr.attr);
+ if (rc)
+ printk(KERN_ERR "phyp-dump: unable to create sysfs file (%d)\n",
+ rc);
+
+ /* ToDo: re-register the dump area, for next time. */
+ return 0;
+}
+machine_subsys_initcall(pseries, phyp_dump_setup);
+
+int __init early_init_dt_scan_phyp_dump(unsigned long node,
+ const char *uname, int depth, void *data)
+{
+ const unsigned int *sizes;
+
+ phyp_dump_info->phyp_dump_configured = 0;
+ phyp_dump_info->phyp_dump_is_active = 0;
+
+ if (depth != 1 || strcmp(uname, "rtas") != 0)
+ return 0;
+
+ if (of_get_flat_dt_prop(node, "ibm,configure-kernel-dump", NULL))
+ phyp_dump_info->phyp_dump_configured++;
+
+ if (of_get_flat_dt_prop(node, "ibm,dump-kernel", NULL))
+ phyp_dump_info->phyp_dump_is_active++;
+
+ sizes = of_get_flat_dt_prop(node, "ibm,configure-kernel-dump-sizes",
+ NULL);
+ if (!sizes)
+ return 0;
+
+ if (sizes[0] == 1)
+ phyp_dump_info->cpu_state_size = *((unsigned long *)&sizes[1]);
+
+ if (sizes[3] == 2)
+ phyp_dump_info->hpte_region_size =
+ *((unsigned long *)&sizes[4]);
+ return 1;
+}
+
+/* Look for phyp_dump= cmdline option */
+static int __init early_phyp_dump_enabled(char *p)
+{
+ phyp_dump_info->phyp_dump_at_boot = 1;
+
+ if (!p)
+ return 0;
+
+ if (strncmp(p, "1", 1) == 0)
+ phyp_dump_info->phyp_dump_at_boot = 1;
+ else if (strncmp(p, "0", 1) == 0)
+ phyp_dump_info->phyp_dump_at_boot = 0;
+
+ return 0;
+}
+early_param("phyp_dump", early_phyp_dump_enabled);
+
+/* Look for phyp_dump_reserve_size= cmdline option */
+static int __init early_phyp_dump_reserve_size(char *p)
+{
+ if (p)
+ phyp_dump_info->reserve_bootvar = memparse(p, &p);
+
+ return 0;
+}
+early_param("phyp_dump_reserve_size", early_phyp_dump_reserve_size);
/* Poweron flag used for enabling auto ups restart */
extern unsigned long rtas_poweron_auto;
+extern void find_udbg_vterm(void);
+
#endif /* _PSERIES_PSERIES_H */
tmp = strchr(buf, ' ');
if (!tmp) {
printk(KERN_ERR "property parse failed in %s at line %d\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
return NULL;
}
*tmp = '\0';
if (++tmp >= end) {
printk(KERN_ERR "property parse failed in %s at line %d\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
return NULL;
}
*length = simple_strtoul(tmp, &tmp, 10);
if (*length == -1) {
printk(KERN_ERR "property parse failed in %s at line %d\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
return NULL;
}
if (*tmp != ' ' || ++tmp >= end) {
printk(KERN_ERR "property parse failed in %s at line %d\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
return NULL;
}
tmp += *length;
if (tmp > end) {
printk(KERN_ERR "property parse failed in %s at line %d\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
return NULL;
}
else if (tmp < end && *tmp != ' ' && *tmp != '\0') {
printk(KERN_ERR "property parse failed in %s at line %d\n",
- __FUNCTION__, __LINE__);
+ __func__, __LINE__);
return NULL;
}
tmp++;
static int __init scanlog_init(void)
{
struct proc_dir_entry *ent;
+ void *data;
+ int err = -ENOMEM;
ibm_scan_log_dump = rtas_token("ibm,scan-log-dump");
- if (ibm_scan_log_dump == RTAS_UNKNOWN_SERVICE) {
- printk(KERN_ERR "scan-log-dump not implemented on this system\n");
- return -EIO;
- }
+ if (ibm_scan_log_dump == RTAS_UNKNOWN_SERVICE)
+ return -ENODEV;
- ent = create_proc_entry("ppc64/rtas/scan-log-dump", S_IRUSR, NULL);
- if (ent) {
- ent->proc_fops = &scanlog_fops;
- /* Ideally we could allocate a buffer < 4G */
- ent->data = kmalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
- if (!ent->data) {
- printk(KERN_ERR "Failed to allocate a buffer\n");
- remove_proc_entry("scan-log-dump", ent->parent);
- return -ENOMEM;
- }
- ((unsigned int *)ent->data)[0] = 0;
- } else {
- printk(KERN_ERR "Failed to create ppc64/scan-log-dump proc entry\n");
- return -EIO;
- }
+ /* Ideally we could allocate a buffer < 4G */
+ data = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
+ if (!data)
+ goto err;
+
+ ent = proc_create("ppc64/rtas/scan-log-dump", S_IRUSR, NULL,
+ &scanlog_fops);
+ if (!ent)
+ goto err;
+
+ ent->data = data;
proc_ppc64_scan_log_dump = ent;
return 0;
+err:
+ kfree(data);
+ return err;
}
static void __exit scanlog_cleanup(void)
#define DBG(fmt...)
#endif
-/* move those away to a .h */
-extern void find_udbg_vterm(void);
-
int fwnmi_active; /* TRUE if an FWNMI handler is present */
static void pseries_shared_idle_sleep(void);
desc->chip->eoi(irq);
}
-static void __init pseries_mpic_init_IRQ(void)
+static void __init pseries_setup_i8259_cascade(void)
{
- struct device_node *np, *old, *cascade = NULL;
- const unsigned int *addrp;
+ struct device_node *np, *old, *found = NULL;
+ unsigned int cascade;
+ const u32 *addrp;
unsigned long intack = 0;
+ int naddr;
+
+ for_each_node_by_type(np, "interrupt-controller") {
+ if (of_device_is_compatible(np, "chrp,iic")) {
+ found = np;
+ break;
+ }
+ }
+
+ if (found == NULL) {
+ printk(KERN_DEBUG "pic: no ISA interrupt controller\n");
+ return;
+ }
+
+ cascade = irq_of_parse_and_map(found, 0);
+ if (cascade == NO_IRQ) {
+ printk(KERN_ERR "pic: failed to map cascade interrupt");
+ return;
+ }
+ pr_debug("pic: cascade mapped to irq %d\n", cascade);
+
+ for (old = of_node_get(found); old != NULL ; old = np) {
+ np = of_get_parent(old);
+ of_node_put(old);
+ if (np == NULL)
+ break;
+ if (strcmp(np->name, "pci") != 0)
+ continue;
+ addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL);
+ if (addrp == NULL)
+ continue;
+ naddr = of_n_addr_cells(np);
+ intack = addrp[naddr-1];
+ if (naddr > 1)
+ intack |= ((unsigned long)addrp[naddr-2]) << 32;
+ }
+ if (intack)
+ printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack);
+ i8259_init(found, intack);
+ of_node_put(found);
+ set_irq_chained_handler(cascade, pseries_8259_cascade);
+}
+
+static void __init pseries_mpic_init_IRQ(void)
+{
+ struct device_node *np;
const unsigned int *opprop;
unsigned long openpic_addr = 0;
- unsigned int cascade_irq;
int naddr, n, i, opplen;
struct mpic *mpic;
mpic_init(mpic);
/* Look for cascade */
- for_each_node_by_type(np, "interrupt-controller")
- if (of_device_is_compatible(np, "chrp,iic")) {
- cascade = np;
- break;
- }
- if (cascade == NULL)
- return;
-
- cascade_irq = irq_of_parse_and_map(cascade, 0);
- if (cascade_irq == NO_IRQ) {
- printk(KERN_ERR "mpic: failed to map cascade interrupt");
- return;
- }
+ pseries_setup_i8259_cascade();
+}
- /* Check ACK type */
- for (old = of_node_get(cascade); old != NULL ; old = np) {
- np = of_get_parent(old);
- of_node_put(old);
- if (np == NULL)
- break;
- if (strcmp(np->name, "pci") != 0)
- continue;
- addrp = of_get_property(np, "8259-interrupt-acknowledge",
- NULL);
- if (addrp == NULL)
- continue;
- naddr = of_n_addr_cells(np);
- intack = addrp[naddr-1];
- if (naddr > 1)
- intack |= ((unsigned long)addrp[naddr-2]) << 32;
- }
- if (intack)
- printk(KERN_DEBUG "mpic: PCI 8259 intack at 0x%016lx\n",
- intack);
- i8259_init(cascade, intack);
- of_node_put(cascade);
- set_irq_chained_handler(cascade_irq, pseries_8259_cascade);
+static void __init pseries_xics_init_IRQ(void)
+{
+ xics_init_IRQ();
+ pseries_setup_i8259_cascade();
}
static void pseries_lpar_enable_pmcs(void)
smp_init_pseries_mpic();
return;
} else if (strstr(typep, "ppc-xicp")) {
- ppc_md.init_IRQ = xics_init_IRQ;
+ ppc_md.init_IRQ = pseries_xics_init_IRQ;
setup_kexec_cpu_down_xics();
smp_init_pseries_xics();
return;
{
unsigned int cpu = smp_processor_id();
unsigned long start_snooze;
+ unsigned long in_purr, out_purr;
/*
* Indicate to the HV that we are idle. Now would be
*/
get_lppaca()->idle = 1;
get_lppaca()->donate_dedicated_cpu = 1;
+ in_purr = mfspr(SPRN_PURR);
/*
* We come in with interrupts disabled, and need_resched()
out:
HMT_medium();
+ out_purr = mfspr(SPRN_PURR);
+ get_lppaca()->wait_state_cycles += out_purr - in_purr;
get_lppaca()->donate_dedicated_cpu = 0;
get_lppaca()->idle = 0;
}
.set_affinity = xics_set_affinity
};
+/* Points to the irq_chip we're actually using */
+static struct irq_chip *xics_irq_chip;
static int xics_host_match(struct irq_host *h, struct device_node *node)
{
return !of_device_is_compatible(node, "chrp,iic");
}
-static int xics_host_map_direct(struct irq_host *h, unsigned int virq,
- irq_hw_number_t hw)
+static int xics_host_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t hw)
{
- pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
+ pr_debug("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
get_irq_desc(virq)->status |= IRQ_LEVEL;
- set_irq_chip_and_handler(virq, &xics_pic_direct, handle_fasteoi_irq);
- return 0;
-}
-
-static int xics_host_map_lpar(struct irq_host *h, unsigned int virq,
- irq_hw_number_t hw)
-{
- pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
-
- get_irq_desc(virq)->status |= IRQ_LEVEL;
- set_irq_chip_and_handler(virq, &xics_pic_lpar, handle_fasteoi_irq);
+ set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
return 0;
}
return 0;
}
-static struct irq_host_ops xics_host_direct_ops = {
+static struct irq_host_ops xics_host_ops = {
.match = xics_host_match,
- .map = xics_host_map_direct,
- .xlate = xics_host_xlate,
-};
-
-static struct irq_host_ops xics_host_lpar_ops = {
- .match = xics_host_match,
- .map = xics_host_map_lpar,
+ .map = xics_host_map,
.xlate = xics_host_xlate,
};
static void __init xics_init_host(void)
{
- struct irq_host_ops *ops;
-
if (firmware_has_feature(FW_FEATURE_LPAR))
- ops = &xics_host_lpar_ops;
+ xics_irq_chip = &xics_pic_lpar;
else
- ops = &xics_host_direct_ops;
- xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, ops,
+ xics_irq_chip = &xics_pic_direct;
+
+ xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
XICS_IRQ_SPURIOUS);
BUG_ON(xics_host == NULL);
irq_set_default_host(xics_host);
}
}
-
-static void __init xics_setup_8259_cascade(void)
-{
- struct device_node *np, *old, *found = NULL;
- int cascade, naddr;
- const u32 *addrp;
- unsigned long intack = 0;
-
- for_each_node_by_type(np, "interrupt-controller")
- if (of_device_is_compatible(np, "chrp,iic")) {
- found = np;
- break;
- }
- if (found == NULL) {
- printk(KERN_DEBUG "xics: no ISA interrupt controller\n");
- return;
- }
- cascade = irq_of_parse_and_map(found, 0);
- if (cascade == NO_IRQ) {
- printk(KERN_ERR "xics: failed to map cascade interrupt");
- return;
- }
- pr_debug("xics: cascade mapped to irq %d\n", cascade);
-
- for (old = of_node_get(found); old != NULL ; old = np) {
- np = of_get_parent(old);
- of_node_put(old);
- if (np == NULL)
- break;
- if (strcmp(np->name, "pci") != 0)
- continue;
- addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL);
- if (addrp == NULL)
- continue;
- naddr = of_n_addr_cells(np);
- intack = addrp[naddr-1];
- if (naddr > 1)
- intack |= ((unsigned long)addrp[naddr-2]) << 32;
- }
- if (intack)
- printk(KERN_DEBUG "xics: PCI 8259 intack at 0x%016lx\n", intack);
- i8259_init(found, intack);
- of_node_put(found);
- set_irq_chained_handler(cascade, pseries_8259_cascade);
-}
-
void __init xics_init_IRQ(void)
{
struct device_node *np;
xics_setup_cpu();
- xics_setup_8259_cascade();
-
ppc64_boot_msg(0x21, "XICS Done");
}
extern struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
-struct irq_desc;
-extern void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc);
-
#endif /* _POWERPC_KERNEL_XICS_H */
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCI) += fsl_pci.o
+obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_RAPIDIO) += fsl_rio.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_IPIC) += ipic.o
obj-$(CONFIG_4xx) += uic.o
+obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o
obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
obj-$(CONFIG_OF_RTC) += of_rtc.o
ifeq ($(CONFIG_PCI),y)
#define CPM_MAP_SIZE (0x4000)
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-static void m8xx_cpm_dpinit(void);
-#endif
cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */
immap_t __iomem *mpc8xx_immr;
static cpic8xx_t __iomem *cpic_reg;
out_be32(&siu_conf->sc_sdcr, 1);
immr_unmap(siu_conf);
-#ifdef CONFIG_PPC_CPM_NEW_BINDING
cpm_muram_init();
-#else
- /* Reclaim the DP memory for our use. */
- m8xx_cpm_dpinit();
-#endif
}
static DEFINE_SPINLOCK(cmd_lock);
if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
goto out;
- printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__);
+ printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
ret = -EIO;
out:
spin_unlock_irqrestore(&cmd_lock, flags);
CPM_BRG_EN | CPM_BRG_DIV16);
}
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-/*
- * dpalloc / dpfree bits.
- */
-static spinlock_t cpm_dpmem_lock;
-/*
- * 16 blocks should be enough to satisfy all requests
- * until the memory subsystem goes up...
- */
-static rh_block_t cpm_boot_dpmem_rh_block[16];
-static rh_info_t cpm_dpmem_info;
-
-#define CPM_DPMEM_ALIGNMENT 8
-static u8 __iomem *dpram_vbase;
-static phys_addr_t dpram_pbase;
-
-static void m8xx_cpm_dpinit(void)
-{
- spin_lock_init(&cpm_dpmem_lock);
-
- dpram_vbase = cpmp->cp_dpmem;
- dpram_pbase = get_immrbase() + offsetof(immap_t, im_cpm.cp_dpmem);
-
- /* Initialize the info header */
- rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
- sizeof(cpm_boot_dpmem_rh_block) /
- sizeof(cpm_boot_dpmem_rh_block[0]),
- cpm_boot_dpmem_rh_block);
-
- /*
- * Attach the usable dpmem area.
- * XXX: This is actually crap. CPM_DATAONLY_BASE and
- * CPM_DATAONLY_SIZE are a subset of the available dparm. It varies
- * with the processor and the microcode patches applied / activated.
- * But the following should be at least safe.
- */
- rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
-}
-
-/*
- * Allocate the requested size worth of DP memory.
- * This function returns an offset into the DPRAM area.
- * Use cpm_dpram_addr() to get the virtual address of the area.
- */
-unsigned long cpm_dpalloc(uint size, uint align)
-{
- unsigned long start;
- unsigned long flags;
-
- spin_lock_irqsave(&cpm_dpmem_lock, flags);
- cpm_dpmem_info.alignment = align;
- start = rh_alloc(&cpm_dpmem_info, size, "commproc");
- spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
- return (uint)start;
-}
-EXPORT_SYMBOL(cpm_dpalloc);
-
-int cpm_dpfree(unsigned long offset)
-{
- int ret;
- unsigned long flags;
-
- spin_lock_irqsave(&cpm_dpmem_lock, flags);
- ret = rh_free(&cpm_dpmem_info, offset);
- spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(cpm_dpfree);
-
-unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
-{
- unsigned long start;
- unsigned long flags;
-
- spin_lock_irqsave(&cpm_dpmem_lock, flags);
- cpm_dpmem_info.alignment = align;
- start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
- spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
- return start;
-}
-EXPORT_SYMBOL(cpm_dpalloc_fixed);
-
-void cpm_dpdump(void)
-{
- rh_dump(&cpm_dpmem_info);
-}
-EXPORT_SYMBOL(cpm_dpdump);
-
-void *cpm_dpram_addr(unsigned long offset)
-{
- return (void *)(dpram_vbase + offset);
-}
-EXPORT_SYMBOL(cpm_dpram_addr);
-
-uint cpm_dpram_phys(u8 *addr)
-{
- return (dpram_pbase + (uint)(addr - dpram_vbase));
-}
-EXPORT_SYMBOL(cpm_dpram_phys);
-#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
-
struct cpm_ioport16 {
__be16 dir, par, odr_sor, dat, intr;
__be16 res[3];
#include <sysdev/fsl_soc.h>
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-static void cpm2_dpinit(void);
-#endif
-
cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
/* We allocate this here because it is used almost exclusively for
/* Reclaim the DP memory for our use.
*/
-#ifdef CONFIG_PPC_CPM_NEW_BINDING
cpm_muram_init();
-#else
- cpm2_dpinit();
-#endif
/* Tell everyone where the comm processor resides.
*/
cpmp = &cpm2_immr->im_cpm;
+
+#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
+ /* Reset the CPM.
+ */
+ cpm_command(CPM_CR_RST, 0);
+#endif
}
static DEFINE_SPINLOCK(cmd_lock);
if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
goto out;
- printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__);
+ printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
ret = -EIO;
out:
spin_unlock_irqrestore(&cmd_lock, flags);
return ret;
}
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-/*
- * dpalloc / dpfree bits.
- */
-static spinlock_t cpm_dpmem_lock;
-/* 16 blocks should be enough to satisfy all requests
- * until the memory subsystem goes up... */
-static rh_block_t cpm_boot_dpmem_rh_block[16];
-static rh_info_t cpm_dpmem_info;
-static u8 __iomem *im_dprambase;
-
-static void cpm2_dpinit(void)
-{
- spin_lock_init(&cpm_dpmem_lock);
-
- /* initialize the info header */
- rh_init(&cpm_dpmem_info, 1,
- sizeof(cpm_boot_dpmem_rh_block) /
- sizeof(cpm_boot_dpmem_rh_block[0]),
- cpm_boot_dpmem_rh_block);
-
- im_dprambase = cpm2_immr;
-
- /* Attach the usable dpmem area */
- /* XXX: This is actually crap. CPM_DATAONLY_BASE and
- * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
- * varies with the processor and the microcode patches activated.
- * But the following should be at least safe.
- */
- rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
-}
-
-/* This function returns an index into the DPRAM area.
- */
-unsigned long cpm_dpalloc(uint size, uint align)
-{
- unsigned long start;
- unsigned long flags;
-
- spin_lock_irqsave(&cpm_dpmem_lock, flags);
- cpm_dpmem_info.alignment = align;
- start = rh_alloc(&cpm_dpmem_info, size, "commproc");
- spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
- return (uint)start;
-}
-EXPORT_SYMBOL(cpm_dpalloc);
-
-int cpm_dpfree(unsigned long offset)
-{
- int ret;
- unsigned long flags;
-
- spin_lock_irqsave(&cpm_dpmem_lock, flags);
- ret = rh_free(&cpm_dpmem_info, offset);
- spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(cpm_dpfree);
-
-/* not sure if this is ever needed */
-unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
-{
- unsigned long start;
- unsigned long flags;
-
- spin_lock_irqsave(&cpm_dpmem_lock, flags);
- cpm_dpmem_info.alignment = align;
- start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
- spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
-
- return start;
-}
-EXPORT_SYMBOL(cpm_dpalloc_fixed);
-
-void cpm_dpdump(void)
-{
- rh_dump(&cpm_dpmem_info);
-}
-EXPORT_SYMBOL(cpm_dpdump);
-
-void *cpm_dpram_addr(unsigned long offset)
-{
- return (void *)(im_dprambase + offset);
-}
-EXPORT_SYMBOL(cpm_dpram_addr);
-#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
-
struct cpm2_ioports {
u32 dir, par, sor, odr, dat;
u32 res[3];
}
#endif
-#ifdef CONFIG_PPC_CPM_NEW_BINDING
static spinlock_t cpm_muram_lock;
static rh_block_t cpm_boot_muram_rh_block[16];
static rh_info_t cpm_muram_info;
return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
}
EXPORT_SYMBOL(cpm_muram_dma);
-
-#endif /* CONFIG_PPC_CPM_NEW_BINDING */
#include <linux/dma-mapping.h>
#include <linux/vmalloc.h>
#include <linux/suspend.h>
+#include <linux/lmb.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/iommu.h>
#include <asm/machdep.h>
#include <asm/abs_addr.h>
#include <asm/cacheflush.h>
-#include <asm/lmb.h>
#include <asm/ppc-pci.h>
#include "dart.h"
--- /dev/null
+/*
+ * Freescale LBC and UPM routines.
+ *
+ * Copyright (c) 2007-2008 MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <asm/fsl_lbc.h>
+
+spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
+
+struct fsl_lbc_regs __iomem *fsl_lbc_regs;
+EXPORT_SYMBOL(fsl_lbc_regs);
+
+static char __initdata *compat_lbc[] = {
+ "fsl,pq2-localbus",
+ "fsl,pq2pro-localbus",
+ "fsl,pq3-localbus",
+ "fsl,elbc",
+};
+
+static int __init fsl_lbc_init(void)
+{
+ struct device_node *lbus;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
+ lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
+ if (lbus)
+ goto found;
+ }
+ return -ENODEV;
+
+found:
+ fsl_lbc_regs = of_iomap(lbus, 0);
+ of_node_put(lbus);
+ if (!fsl_lbc_regs)
+ return -ENOMEM;
+ return 0;
+}
+arch_initcall(fsl_lbc_init);
+
+/**
+ * fsl_lbc_find - find Localbus bank
+ * @addr_base: base address of the memory bank
+ *
+ * This function walks LBC banks comparing "Base address" field of the BR
+ * registers with the supplied addr_base argument. When bases match this
+ * function returns bank number (starting with 0), otherwise it returns
+ * appropriate errno value.
+ */
+int fsl_lbc_find(phys_addr_t addr_base)
+{
+ int i;
+
+ if (!fsl_lbc_regs)
+ return -ENODEV;
+
+ for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
+ __be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
+ __be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
+
+ if (br & BR_V && (br & or & BR_BA) == addr_base)
+ return i;
+ }
+
+ return -ENOENT;
+}
+EXPORT_SYMBOL(fsl_lbc_find);
+
+/**
+ * fsl_upm_find - find pre-programmed UPM via base address
+ * @addr_base: base address of the memory bank controlled by the UPM
+ * @upm: pointer to the allocated fsl_upm structure
+ *
+ * This function fills fsl_upm structure so you can use it with the rest of
+ * UPM API. On success this function returns 0, otherwise it returns
+ * appropriate errno value.
+ */
+int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
+{
+ int bank;
+ __be32 br;
+
+ bank = fsl_lbc_find(addr_base);
+ if (bank < 0)
+ return bank;
+
+ br = in_be32(&fsl_lbc_regs->bank[bank].br);
+
+ switch (br & BR_MSEL) {
+ case BR_MS_UPMA:
+ upm->mxmr = &fsl_lbc_regs->mamr;
+ break;
+ case BR_MS_UPMB:
+ upm->mxmr = &fsl_lbc_regs->mbmr;
+ break;
+ case BR_MS_UPMC:
+ upm->mxmr = &fsl_lbc_regs->mcmr;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (br & BR_PS) {
+ case BR_PS_8:
+ upm->width = 8;
+ break;
+ case BR_PS_16:
+ upm->width = 16;
+ break;
+ case BR_PS_32:
+ upm->width = 32;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(fsl_upm_find);
EXPORT_SYMBOL(get_immrbase);
+static u32 sysfreq = -1;
+
+u32 fsl_get_sys_freq(void)
+{
+ struct device_node *soc;
+ const u32 *prop;
+ int size;
+
+ if (sysfreq != -1)
+ return sysfreq;
+
+ soc = of_find_node_by_type(NULL, "soc");
+ if (!soc)
+ return -1;
+
+ prop = of_get_property(soc, "clock-frequency", &size);
+ if (!prop || size != sizeof(*prop) || *prop == 0)
+ prop = of_get_property(soc, "bus-frequency", &size);
+
+ if (prop && size == sizeof(*prop))
+ sysfreq = *prop;
+
+ of_node_put(soc);
+ return sysfreq;
+}
+EXPORT_SYMBOL(fsl_get_sys_freq);
+
#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
static u32 brgfreq = -1;
static int __init mpc83xx_wdt_init(void)
{
struct resource r;
- struct device_node *soc, *np;
+ struct device_node *np;
struct platform_device *dev;
- const unsigned int *freq;
+ u32 freq = fsl_get_sys_freq();
int ret;
np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
goto nodev;
}
- soc = of_find_node_by_type(NULL, "soc");
-
- if (!soc) {
- ret = -ENODEV;
- goto nosoc;
- }
-
- freq = of_get_property(soc, "bus-frequency", NULL);
- if (!freq) {
- ret = -ENODEV;
- goto err;
- }
-
memset(&r, 0, sizeof(r));
ret = of_address_to_resource(np, 0, &r);
goto err;
}
- ret = platform_device_add_data(dev, freq, sizeof(int));
+ ret = platform_device_add_data(dev, &freq, sizeof(freq));
if (ret)
goto unreg;
- of_node_put(soc);
of_node_put(np);
-
return 0;
unreg:
platform_device_unregister(dev);
err:
- of_node_put(soc);
-nosoc:
of_node_put(np);
nodev:
return ret;
arch_initcall(fsl_usb_of_init);
-#ifndef CONFIG_PPC_CPM_NEW_BINDING
-#ifdef CONFIG_CPM2
-
-extern void init_scc_ioports(struct fs_uart_platform_info*);
-
-static const char fcc_regs[] = "fcc_regs";
-static const char fcc_regs_c[] = "fcc_regs_c";
-static const char fcc_pram[] = "fcc_pram";
-static char bus_id[9][BUS_ID_SIZE];
-
-static int __init fs_enet_of_init(void)
-{
- struct device_node *np;
- unsigned int i;
- struct platform_device *fs_enet_dev;
- struct resource res;
- int ret;
-
- for (np = NULL, i = 0;
- (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
- i++) {
- struct resource r[4];
- struct device_node *phy, *mdio;
- struct fs_platform_info fs_enet_data;
- const unsigned int *id, *phy_addr, *phy_irq;
- const void *mac_addr;
- const phandle *ph;
- const char *model;
-
- memset(r, 0, sizeof(r));
- memset(&fs_enet_data, 0, sizeof(fs_enet_data));
-
- ret = of_address_to_resource(np, 0, &r[0]);
- if (ret)
- goto err;
- r[0].name = fcc_regs;
-
- ret = of_address_to_resource(np, 1, &r[1]);
- if (ret)
- goto err;
- r[1].name = fcc_pram;
-
- ret = of_address_to_resource(np, 2, &r[2]);
- if (ret)
- goto err;
- r[2].name = fcc_regs_c;
- fs_enet_data.fcc_regs_c = r[2].start;
-
- of_irq_to_resource(np, 0, &r[3]);
-
- fs_enet_dev =
- platform_device_register_simple("fsl-cpm-fcc", i, &r[0], 4);
-
- if (IS_ERR(fs_enet_dev)) {
- ret = PTR_ERR(fs_enet_dev);
- goto err;
- }
-
- model = of_get_property(np, "model", NULL);
- if (model == NULL) {
- ret = -ENODEV;
- goto unreg;
- }
-
- mac_addr = of_get_mac_address(np);
- if (mac_addr)
- memcpy(fs_enet_data.macaddr, mac_addr, 6);
-
- ph = of_get_property(np, "phy-handle", NULL);
- phy = of_find_node_by_phandle(*ph);
-
- if (phy == NULL) {
- ret = -ENODEV;
- goto unreg;
- }
-
- phy_addr = of_get_property(phy, "reg", NULL);
- fs_enet_data.phy_addr = *phy_addr;
-
- phy_irq = of_get_property(phy, "interrupts", NULL);
-
- id = of_get_property(np, "device-id", NULL);
- fs_enet_data.fs_no = *id;
- strcpy(fs_enet_data.fs_type, model);
-
- mdio = of_get_parent(phy);
- ret = of_address_to_resource(mdio, 0, &res);
- if (ret) {
- of_node_put(phy);
- of_node_put(mdio);
- goto unreg;
- }
-
- fs_enet_data.clk_rx = *((u32 *)of_get_property(np,
- "rx-clock", NULL));
- fs_enet_data.clk_tx = *((u32 *)of_get_property(np,
- "tx-clock", NULL));
-
- if (strstr(model, "FCC")) {
- int fcc_index = *id - 1;
- const unsigned char *mdio_bb_prop;
-
- fs_enet_data.dpram_offset = (u32)cpm_dpram_addr(0);
- fs_enet_data.rx_ring = 32;
- fs_enet_data.tx_ring = 32;
- fs_enet_data.rx_copybreak = 240;
- fs_enet_data.use_napi = 0;
- fs_enet_data.napi_weight = 17;
- fs_enet_data.mem_offset = FCC_MEM_OFFSET(fcc_index);
- fs_enet_data.cp_page = CPM_CR_FCC_PAGE(fcc_index);
- fs_enet_data.cp_block = CPM_CR_FCC_SBLOCK(fcc_index);
-
- snprintf((char*)&bus_id[(*id)], BUS_ID_SIZE, "%x:%02x",
- (u32)res.start, fs_enet_data.phy_addr);
- fs_enet_data.bus_id = (char*)&bus_id[(*id)];
- fs_enet_data.init_ioports = init_fcc_ioports;
-
- mdio_bb_prop = of_get_property(phy, "bitbang", NULL);
- if (mdio_bb_prop) {
- struct platform_device *fs_enet_mdio_bb_dev;
- struct fs_mii_bb_platform_info fs_enet_mdio_bb_data;
-
- fs_enet_mdio_bb_dev =
- platform_device_register_simple("fsl-bb-mdio",
- i, NULL, 0);
- memset(&fs_enet_mdio_bb_data, 0,
- sizeof(struct fs_mii_bb_platform_info));
- fs_enet_mdio_bb_data.mdio_dat.bit =
- mdio_bb_prop[0];
- fs_enet_mdio_bb_data.mdio_dir.bit =
- mdio_bb_prop[1];
- fs_enet_mdio_bb_data.mdc_dat.bit =
- mdio_bb_prop[2];
- fs_enet_mdio_bb_data.mdio_port =
- mdio_bb_prop[3];
- fs_enet_mdio_bb_data.mdc_port =
- mdio_bb_prop[4];
- fs_enet_mdio_bb_data.delay =
- mdio_bb_prop[5];
-
- fs_enet_mdio_bb_data.irq[0] = phy_irq[0];
- fs_enet_mdio_bb_data.irq[1] = -1;
- fs_enet_mdio_bb_data.irq[2] = -1;
- fs_enet_mdio_bb_data.irq[3] = phy_irq[0];
- fs_enet_mdio_bb_data.irq[31] = -1;
-
- fs_enet_mdio_bb_data.mdio_dat.offset =
- (u32)&cpm2_immr->im_ioport.iop_pdatc;
- fs_enet_mdio_bb_data.mdio_dir.offset =
- (u32)&cpm2_immr->im_ioport.iop_pdirc;
- fs_enet_mdio_bb_data.mdc_dat.offset =
- (u32)&cpm2_immr->im_ioport.iop_pdatc;
-
- ret = platform_device_add_data(
- fs_enet_mdio_bb_dev,
- &fs_enet_mdio_bb_data,
- sizeof(struct fs_mii_bb_platform_info));
- if (ret)
- goto unreg;
- }
-
- of_node_put(phy);
- of_node_put(mdio);
-
- ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
- sizeof(struct
- fs_platform_info));
- if (ret)
- goto unreg;
- }
- }
- return 0;
-
-unreg:
- platform_device_unregister(fs_enet_dev);
-err:
- return ret;
-}
-
-arch_initcall(fs_enet_of_init);
-
-static const char scc_regs[] = "regs";
-static const char scc_pram[] = "pram";
-
-static int __init cpm_uart_of_init(void)
-{
- struct device_node *np;
- unsigned int i;
- struct platform_device *cpm_uart_dev;
- int ret;
-
- for (np = NULL, i = 0;
- (np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
- i++) {
- struct resource r[3];
- struct fs_uart_platform_info cpm_uart_data;
- const int *id;
- const char *model;
-
- memset(r, 0, sizeof(r));
- memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
-
- ret = of_address_to_resource(np, 0, &r[0]);
- if (ret)
- goto err;
-
- r[0].name = scc_regs;
-
- ret = of_address_to_resource(np, 1, &r[1]);
- if (ret)
- goto err;
- r[1].name = scc_pram;
-
- of_irq_to_resource(np, 0, &r[2]);
-
- cpm_uart_dev =
- platform_device_register_simple("fsl-cpm-scc:uart", i, &r[0], 3);
-
- if (IS_ERR(cpm_uart_dev)) {
- ret = PTR_ERR(cpm_uart_dev);
- goto err;
- }
-
- id = of_get_property(np, "device-id", NULL);
- cpm_uart_data.fs_no = *id;
-
- model = of_get_property(np, "model", NULL);
- strcpy(cpm_uart_data.fs_type, model);
-
- cpm_uart_data.uart_clk = ppc_proc_freq;
-
- cpm_uart_data.tx_num_fifo = 4;
- cpm_uart_data.tx_buf_size = 32;
- cpm_uart_data.rx_num_fifo = 4;
- cpm_uart_data.rx_buf_size = 32;
- cpm_uart_data.clk_rx = *((u32 *)of_get_property(np,
- "rx-clock", NULL));
- cpm_uart_data.clk_tx = *((u32 *)of_get_property(np,
- "tx-clock", NULL));
-
- ret =
- platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
- sizeof(struct
- fs_uart_platform_info));
- if (ret)
- goto unreg;
- }
-
- return 0;
-
-unreg:
- platform_device_unregister(cpm_uart_dev);
-err:
- return ret;
-}
-
-arch_initcall(cpm_uart_of_init);
-#endif /* CONFIG_CPM2 */
-
-#ifdef CONFIG_8xx
-
-extern void init_scc_ioports(struct fs_platform_info*);
-extern int platform_device_skip(const char *model, int id);
-
-static int __init fs_enet_mdio_of_init(void)
-{
- struct device_node *np;
- unsigned int i;
- struct platform_device *mdio_dev;
- struct resource res;
- int ret;
-
- for (np = NULL, i = 0;
- (np = of_find_compatible_node(np, "mdio", "fs_enet")) != NULL;
- i++) {
- struct fs_mii_fec_platform_info mdio_data;
-
- memset(&res, 0, sizeof(res));
- memset(&mdio_data, 0, sizeof(mdio_data));
-
- ret = of_address_to_resource(np, 0, &res);
- if (ret)
- goto err;
-
- mdio_dev =
- platform_device_register_simple("fsl-cpm-fec-mdio",
- res.start, &res, 1);
- if (IS_ERR(mdio_dev)) {
- ret = PTR_ERR(mdio_dev);
- goto err;
- }
-
- mdio_data.mii_speed = ((((ppc_proc_freq + 4999999) / 2500000) / 2) & 0x3F) << 1;
-
- ret =
- platform_device_add_data(mdio_dev, &mdio_data,
- sizeof(struct fs_mii_fec_platform_info));
- if (ret)
- goto unreg;
- }
- return 0;
-
-unreg:
- platform_device_unregister(mdio_dev);
-err:
- return ret;
-}
-
-arch_initcall(fs_enet_mdio_of_init);
-
-static const char *enet_regs = "regs";
-static const char *enet_pram = "pram";
-static const char *enet_irq = "interrupt";
-static char bus_id[9][BUS_ID_SIZE];
-
-static int __init fs_enet_of_init(void)
-{
- struct device_node *np;
- unsigned int i;
- struct platform_device *fs_enet_dev = NULL;
- struct resource res;
- int ret;
-
- for (np = NULL, i = 0;
- (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
- i++) {
- struct resource r[4];
- struct device_node *phy = NULL, *mdio = NULL;
- struct fs_platform_info fs_enet_data;
- const unsigned int *id;
- const unsigned int *phy_addr;
- const void *mac_addr;
- const phandle *ph;
- const char *model;
-
- memset(r, 0, sizeof(r));
- memset(&fs_enet_data, 0, sizeof(fs_enet_data));
-
- model = of_get_property(np, "model", NULL);
- if (model == NULL) {
- ret = -ENODEV;
- goto unreg;
- }
-
- id = of_get_property(np, "device-id", NULL);
- fs_enet_data.fs_no = *id;
-
- if (platform_device_skip(model, *id))
- continue;
-
- ret = of_address_to_resource(np, 0, &r[0]);
- if (ret)
- goto err;
- r[0].name = enet_regs;
-
- mac_addr = of_get_mac_address(np);
- if (mac_addr)
- memcpy(fs_enet_data.macaddr, mac_addr, 6);
-
- ph = of_get_property(np, "phy-handle", NULL);
- if (ph != NULL)
- phy = of_find_node_by_phandle(*ph);
-
- if (phy != NULL) {
- phy_addr = of_get_property(phy, "reg", NULL);
- fs_enet_data.phy_addr = *phy_addr;
- fs_enet_data.has_phy = 1;
-
- mdio = of_get_parent(phy);
- ret = of_address_to_resource(mdio, 0, &res);
- if (ret) {
- of_node_put(phy);
- of_node_put(mdio);
- goto unreg;
- }
- }
-
- model = of_get_property(np, "model", NULL);
- strcpy(fs_enet_data.fs_type, model);
-
- if (strstr(model, "FEC")) {
- r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
- r[1].flags = IORESOURCE_IRQ;
- r[1].name = enet_irq;
-
- fs_enet_dev =
- platform_device_register_simple("fsl-cpm-fec", i, &r[0], 2);
-
- if (IS_ERR(fs_enet_dev)) {
- ret = PTR_ERR(fs_enet_dev);
- goto err;
- }
-
- fs_enet_data.rx_ring = 128;
- fs_enet_data.tx_ring = 16;
- fs_enet_data.rx_copybreak = 240;
- fs_enet_data.use_napi = 1;
- fs_enet_data.napi_weight = 17;
-
- snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%x:%02x",
- (u32)res.start, fs_enet_data.phy_addr);
- fs_enet_data.bus_id = (char*)&bus_id[i];
- fs_enet_data.init_ioports = init_fec_ioports;
- }
- if (strstr(model, "SCC")) {
- ret = of_address_to_resource(np, 1, &r[1]);
- if (ret)
- goto err;
- r[1].name = enet_pram;
-
- r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
- r[2].flags = IORESOURCE_IRQ;
- r[2].name = enet_irq;
-
- fs_enet_dev =
- platform_device_register_simple("fsl-cpm-scc", i, &r[0], 3);
-
- if (IS_ERR(fs_enet_dev)) {
- ret = PTR_ERR(fs_enet_dev);
- goto err;
- }
-
- fs_enet_data.rx_ring = 64;
- fs_enet_data.tx_ring = 8;
- fs_enet_data.rx_copybreak = 240;
- fs_enet_data.use_napi = 1;
- fs_enet_data.napi_weight = 17;
-
- snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%s", "fixed@10:1");
- fs_enet_data.bus_id = (char*)&bus_id[i];
- fs_enet_data.init_ioports = init_scc_ioports;
- }
-
- of_node_put(phy);
- of_node_put(mdio);
-
- ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
- sizeof(struct
- fs_platform_info));
- if (ret)
- goto unreg;
- }
- return 0;
-
-unreg:
- platform_device_unregister(fs_enet_dev);
-err:
- return ret;
-}
-
-arch_initcall(fs_enet_of_init);
-
-static int __init fsl_pcmcia_of_init(void)
-{
- struct device_node *np;
- /*
- * Register all the devices which type is "pcmcia"
- */
- for_each_compatible_node(np, "pcmcia", "fsl,pq-pcmcia")
- of_platform_device_create(np, "m8xx-pcmcia", NULL);
- return 0;
-}
-
-arch_initcall(fsl_pcmcia_of_init);
-
-static const char *smc_regs = "regs";
-static const char *smc_pram = "pram";
-
-static int __init cpm_smc_uart_of_init(void)
-{
- struct device_node *np;
- unsigned int i;
- struct platform_device *cpm_uart_dev;
- int ret;
-
- for (np = NULL, i = 0;
- (np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
- i++) {
- struct resource r[3];
- struct fs_uart_platform_info cpm_uart_data;
- const int *id;
- const char *model;
-
- memset(r, 0, sizeof(r));
- memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
-
- ret = of_address_to_resource(np, 0, &r[0]);
- if (ret)
- goto err;
-
- r[0].name = smc_regs;
-
- ret = of_address_to_resource(np, 1, &r[1]);
- if (ret)
- goto err;
- r[1].name = smc_pram;
-
- r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
- r[2].flags = IORESOURCE_IRQ;
-
- cpm_uart_dev =
- platform_device_register_simple("fsl-cpm-smc:uart", i, &r[0], 3);
-
- if (IS_ERR(cpm_uart_dev)) {
- ret = PTR_ERR(cpm_uart_dev);
- goto err;
- }
-
- model = of_get_property(np, "model", NULL);
- strcpy(cpm_uart_data.fs_type, model);
-
- id = of_get_property(np, "device-id", NULL);
- cpm_uart_data.fs_no = *id;
- cpm_uart_data.uart_clk = ppc_proc_freq;
-
- cpm_uart_data.tx_num_fifo = 4;
- cpm_uart_data.tx_buf_size = 32;
- cpm_uart_data.rx_num_fifo = 4;
- cpm_uart_data.rx_buf_size = 32;
-
- ret =
- platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
- sizeof(struct
- fs_uart_platform_info));
- if (ret)
- goto unreg;
- }
-
- return 0;
-
-unreg:
- platform_device_unregister(cpm_uart_dev);
-err:
- return ret;
-}
-
-arch_initcall(cpm_smc_uart_of_init);
-
-#endif /* CONFIG_8xx */
-#endif /* CONFIG_PPC_CPM_NEW_BINDING */
-
static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
struct spi_board_info *board_infos,
unsigned int num_board_infos,
sysclk = get_brgfreq();
#endif
if (sysclk == -1) {
- struct device_node *np;
- const u32 *freq;
- int size;
-
- np = of_find_node_by_type(NULL, "soc");
- if (!np)
+ sysclk = fsl_get_sys_freq();
+ if (sysclk == -1)
return -ENODEV;
-
- freq = of_get_property(np, "clock-frequency", &size);
- if (!freq || size != sizeof(*freq) || *freq == 0) {
- freq = of_get_property(np, "bus-frequency", &size);
- if (!freq || size != sizeof(*freq) || *freq == 0) {
- of_node_put(np);
- return -ENODEV;
- }
- }
-
- sysclk = *freq;
- of_node_put(np);
}
ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
extern phys_addr_t get_immrbase(void);
extern u32 get_brgfreq(void);
extern u32 get_baudrate(void);
+extern u32 fsl_get_sys_freq(void);
struct spi_board_info;
switch(type) {
#ifdef CONFIG_PPC_DCR
case mpic_access_dcr:
- return dcr_write(rb->dhost, reg, value);
+ dcr_write(rb->dhost, reg, value);
+ break;
#endif
case mpic_access_mmio_be:
- return out_be32(rb->base + (reg >> 2), value);
+ out_be32(rb->base + (reg >> 2), value);
+ break;
case mpic_access_mmio_le:
default:
- return out_le32(rb->base + (reg >> 2), value);
+ out_le32(rb->base + (reg >> 2), value);
+ break;
}
}
const char *name)
{
struct mpic *mpic;
- u32 reg;
+ u32 greg_feature;
const char *vers;
int i;
int intvec_top;
/* Look for protected sources */
if (node) {
- unsigned int psize, bits, mapsize;
+ int psize;
+ unsigned int bits, mapsize;
const u32 *psrc =
of_get_property(node, "protected-sources", &psize);
if (psrc) {
* in, try to obtain one
*/
if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
- const u32 *reg;
- reg = of_get_property(node, "reg", NULL);
+ const u32 *reg = of_get_property(node, "reg", NULL);
BUG_ON(reg == NULL);
paddr = of_translate_address(node, reg);
BUG_ON(paddr == OF_BAD_ADDR);
* MPICs, num sources as well. On ISU MPICs, sources are counted
* as ISUs are added
*/
- reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
- mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
+ greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
+ mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
>> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
if (isu_size == 0)
- mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
- >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
+ mpic->num_sources =
+ ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
+ >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
/* Map the per-CPU registers */
for (i = 0; i < mpic->num_cpus; i++) {
mpic->isu_mask = (1 << mpic->isu_shift) - 1;
/* Display version */
- switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
+ switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
case 1:
vers = "1.0";
break;
void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
{
- int is_ipi;
+ unsigned int is_ipi;
struct mpic *mpic = mpic_find(irq, &is_ipi);
unsigned int src = mpic_irq_to_hw(irq);
unsigned long flags;
unsigned int mpic_irq_get_priority(unsigned int irq)
{
- int is_ipi;
+ unsigned int is_ipi;
struct mpic *mpic = mpic_find(irq, &is_ipi);
unsigned int src = mpic_irq_to_hw(irq);
unsigned long flags;
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
}
-/*
- * XXX: someone who knows mpic should check this.
- * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
- * or can we reset the mpic in the new kernel?
- */
void mpic_teardown_this_cpu(int secondary)
{
struct mpic *mpic = mpic_primary;
/* Set current processor priority to max */
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
+ /* We need to EOI the IPI since not all platforms reset the MPIC
+ * on boot and new interrupts wouldn't get delivered otherwise.
+ */
+ mpic_eoi(mpic);
spin_unlock_irqrestore(&mpic_lock, flags);
}
if (err)
return err;
- prop = of_get_property(np, "block-index", NULL);
+ prop = of_get_property(np, "cell-index", NULL);
if (!prop)
return -ENODEV;
port_number = *(int *)prop;
pdata.cache_mgmt = 1; /* All current revs need this set */
+ pdata.max_idle = 40; /* default */
prop = of_get_property(np, "max_idle", NULL);
if (prop)
pdata.max_idle = *prop;
/*
* Create mv64x60_eth platform devices
*/
-static int __init eth_register_shared_pdev(struct device_node *np)
+static struct platform_device * __init mv64x60_eth_register_shared_pdev(
+ struct device_node *np, int id)
{
struct platform_device *pdev;
struct resource r[1];
int err;
- np = of_get_parent(np);
- if (!np)
- return -ENODEV;
-
err = of_address_to_resource(np, 0, &r[0]);
- of_node_put(np);
if (err)
- return err;
+ return ERR_PTR(err);
- pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, 0,
+ pdev = platform_device_register_simple(MV643XX_ETH_SHARED_NAME, id,
r, 1);
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
-
- return 0;
+ return pdev;
}
-static int __init mv64x60_eth_device_setup(struct device_node *np, int id)
+static int __init mv64x60_eth_device_setup(struct device_node *np, int id,
+ struct platform_device *shared_pdev)
{
struct resource r[1];
struct mv643xx_eth_platform_data pdata;
const phandle *ph;
int err;
- /* only register the shared platform device the first time through */
- if (id == 0 && (err = eth_register_shared_pdev(np)))
- return err;
-
memset(r, 0, sizeof(r));
of_irq_to_resource(np, 0, &r[0]);
memset(&pdata, 0, sizeof(pdata));
- prop = of_get_property(np, "block-index", NULL);
+ prop = of_get_property(np, "reg", NULL);
if (!prop)
return -ENODEV;
pdata.port_number = *prop;
of_node_put(phy);
- pdev = platform_device_alloc(MV643XX_ETH_NAME, pdata.port_number);
+ pdev = platform_device_alloc(MV643XX_ETH_NAME, id);
if (!pdev)
return -ENOMEM;
memset(&pdata, 0, sizeof(pdata));
+ pdata.freq_m = 8; /* default */
prop = of_get_property(np, "freq_m", NULL);
if (!prop)
return -ENODEV;
pdata.freq_m = *prop;
+ pdata.freq_m = 3; /* default */
prop = of_get_property(np, "freq_n", NULL);
if (!prop)
return -ENODEV;
pdata.freq_n = *prop;
- prop = of_get_property(np, "timeout", NULL);
- if (prop)
- pdata.timeout = *prop;
- else
- pdata.timeout = 1000; /* 1 second */
+ pdata.timeout = 1000; /* default: 1 second */
pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id);
if (!pdev)
memset(&pdata, 0, sizeof(pdata));
- prop = of_get_property(np, "timeout", NULL);
- if (!prop)
- return -ENODEV;
- pdata.timeout = *prop;
+ pdata.timeout = 10; /* Default: 10 seconds */
np = of_get_parent(np);
if (!np)
static int __init mv64x60_device_setup(void)
{
- struct device_node *np = NULL;
- int id;
+ struct device_node *np, *np2;
+ struct platform_device *pdev;
+ int id, id2;
int err;
id = 0;
- for_each_compatible_node(np, "serial", "marvell,mpsc")
+ for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc")
if ((err = mv64x60_mpsc_device_setup(np, id++)))
goto error;
id = 0;
- for_each_compatible_node(np, "network", "marvell,mv64x60-eth")
- if ((err = mv64x60_eth_device_setup(np, id++)))
+ id2 = 0;
+ for_each_compatible_node(np, NULL, "marvell,mv64360-eth-group") {
+ pdev = mv64x60_eth_register_shared_pdev(np, id++);
+ if (IS_ERR(pdev)) {
+ err = PTR_ERR(pdev);
goto error;
+ }
+ for_each_child_of_node(np, np2) {
+ if (!of_device_is_compatible(np2,
+ "marvell,mv64360-eth"))
+ continue;
+ err = mv64x60_eth_device_setup(np2, id2++, pdev);
+ if (err) {
+ of_node_put(np2);
+ goto error;
+ }
+ }
+ }
id = 0;
- for_each_compatible_node(np, "i2c", "marvell,mv64x60-i2c")
+ for_each_compatible_node(np, "i2c", "marvell,mv64360-i2c")
if ((err = mv64x60_i2c_device_setup(np, id++)))
goto error;
/* support up to one watchdog timer */
- np = of_find_compatible_node(np, NULL, "marvell,mv64x60-wdt");
+ np = of_find_compatible_node(np, NULL, "marvell,mv64360-wdt");
if (np) {
if ((err = mv64x60_wdt_device_setup(np, id)))
goto error;
if (!np)
goto not_mpsc;
- if (!of_device_is_compatible(np, "marvell,mpsc"))
+ if (!of_device_is_compatible(np, "marvell,mv64360-mpsc"))
goto not_mpsc;
- prop = of_get_property(np, "block-index", NULL);
+ prop = of_get_property(np, "cell-index", NULL);
if (!prop)
goto not_mpsc;
struct platform_device *pdev;
const unsigned int *prop;
- np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60");
+ np = of_find_compatible_node(NULL, NULL, "marvell,mv64360");
if (!np)
return 0;
prop = of_get_property(np, "hs_reg_valid", NULL);
of_node_put(np);
- pdev = platform_device_register_simple("marvell,mv64x60", 0, NULL, 0);
+ pdev = platform_device_register_simple("marvell,mv64360", 0, NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
{
struct device_node *np;
- for_each_compatible_node(np, "pci", "marvell,mv64x60-pci")
+ for_each_compatible_node(np, "pci", "marvell,mv64360-pci")
mv64x60_add_bridge(np);
}
const unsigned int *reg;
unsigned long flags;
- np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-gpp");
+ np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
reg = of_get_property(np, "reg", &size);
paddr = of_translate_address(np, reg);
mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
of_node_put(np);
- np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-pic");
+ np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-pic");
reg = of_get_property(np, "reg", &size);
paddr = of_translate_address(np, reg);
mv64x60_irq_reg_base = ioremap(paddr, reg[1]);
if (!stdout)
return;
- for_each_compatible_node(np, "serial", "marvell,mpsc") {
+ for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc") {
if (np == stdout)
break;
}
*
* ibm,plb-pciex-440spe
* ibm,plb-pciex-405ex
+ * ibm,plb-pciex-460ex
*
* Anything else will be rejected for now as they are all subtly
* different unfortunately.
int time_out = 20;
/* Set PLL clock receiver to LVPECL */
- mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28);
+ dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
/* Shouldn't we do all the calibration stuff etc... here ? */
if (ppc440spe_pciex_check_reset(np))
}
/* De-assert reset of PCIe PLL, wait for lock */
- mtdcri(SDR0, PESDR0_PLLLCT1,
- mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24));
+ dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
udelay(3);
while (time_out) {
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
0x35000000);
}
- val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET);
- mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
- (val & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
+ (1 << 24) | (1 << 16), 1 << 12);
return 0;
}
.setup_utl = ppc440speB_pciex_init_utl,
};
+static int __init ppc460ex_pciex_core_init(struct device_node *np)
+{
+ /* Nothing to do, return 2 ports */
+ return 2;
+}
+
+static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
+{
+ u32 val;
+ u32 utlset1;
+
+ if (port->endpoint)
+ val = PTYPE_LEGACY_ENDPOINT << 20;
+ else
+ val = PTYPE_ROOT_PORT << 20;
+
+ if (port->index == 0) {
+ val |= LNKW_X1 << 12;
+ utlset1 = 0x20000000;
+ } else {
+ val |= LNKW_X4 << 12;
+ utlset1 = 0x20101101;
+ }
+
+ mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
+ mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
+ mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
+
+ switch (port->index) {
+ case 0:
+ mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
+ mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136);
+ mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
+
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
+ break;
+
+ case 1:
+ mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
+ mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
+ mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
+ mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
+ mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136);
+ mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136);
+ mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136);
+ mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136);
+ mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
+ mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
+ mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
+ mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
+
+ mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
+ break;
+ }
+
+ mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
+ mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
+ (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
+
+ /* Poll for PHY reset */
+ /* XXX FIXME add timeout */
+ switch (port->index) {
+ case 0:
+ while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
+ udelay(10);
+ break;
+ case 1:
+ while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
+ udelay(10);
+ break;
+ }
+
+ mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
+ (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
+ ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
+ PESDRx_RCSSET_RSTPYN);
+
+ port->has_ibpre = 1;
+
+ return 0;
+}
+
+static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
+{
+ dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
+
+ /*
+ * Set buffer allocations and then assert VRB and TXE.
+ */
+ out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
+ out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
+ out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
+ out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
+ out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
+ out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
+ out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
+ out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
+ out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
+
+ return 0;
+}
+
+static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
+{
+ .core_init = ppc460ex_pciex_core_init,
+ .port_init_hw = ppc460ex_pciex_init_port_hw,
+ .setup_utl = ppc460ex_pciex_init_utl,
+};
+
#endif /* CONFIG_44x */
#ifdef CONFIG_40x
* PCIe boards don't show this problem.
* This has to be re-tested and fixed in a later release!
*/
-#if 0 /* XXX FIXME: Not resetting the PHY will leave all resources
- * configured as done previously by U-Boot. Then Linux will currently
- * not reassign them. So the PHY reset is now done always. This will
- * lead to problems with the Atheros PCIe board again.
- */
val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
if (!(val & 0x00001000))
ppc405ex_pcie_phy_reset(port);
-#else
- ppc405ex_pcie_phy_reset(port);
-#endif
dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
else
ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
}
+ if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
+ ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
#endif /* CONFIG_44x */
#ifdef CONFIG_40x
if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
port->link = 0;
}
- mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
- mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20);
+ dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
msleep(100);
return 0;
#define PESDR1_405EX_LPB 0x044B
#define PESDR1_405EX_PHYSTA 0x044C
+/*
+ * 460EX additional DCRs
+ */
+#define PESDR0_460EX_L0BIST 0x0308
+#define PESDR0_460EX_L0BISTSTS 0x0309
+#define PESDR0_460EX_L0CDRCTL 0x030A
+#define PESDR0_460EX_L0DRV 0x030B
+#define PESDR0_460EX_L0REC 0x030C
+#define PESDR0_460EX_L0LPB 0x030D
+#define PESDR0_460EX_L0CLK 0x030E
+#define PESDR0_460EX_PHY_CTL_RST 0x030F
+#define PESDR0_460EX_RSTSTA 0x0310
+#define PESDR0_460EX_OBS 0x0311
+#define PESDR0_460EX_L0ERRC 0x0320
+
+#define PESDR1_460EX_L0BIST 0x0348
+#define PESDR1_460EX_L1BIST 0x0349
+#define PESDR1_460EX_L2BIST 0x034A
+#define PESDR1_460EX_L3BIST 0x034B
+#define PESDR1_460EX_L0BISTSTS 0x034C
+#define PESDR1_460EX_L1BISTSTS 0x034D
+#define PESDR1_460EX_L2BISTSTS 0x034E
+#define PESDR1_460EX_L3BISTSTS 0x034F
+#define PESDR1_460EX_L0CDRCTL 0x0350
+#define PESDR1_460EX_L1CDRCTL 0x0351
+#define PESDR1_460EX_L2CDRCTL 0x0352
+#define PESDR1_460EX_L3CDRCTL 0x0353
+#define PESDR1_460EX_L0DRV 0x0354
+#define PESDR1_460EX_L1DRV 0x0355
+#define PESDR1_460EX_L2DRV 0x0356
+#define PESDR1_460EX_L3DRV 0x0357
+#define PESDR1_460EX_L0REC 0x0358
+#define PESDR1_460EX_L1REC 0x0359
+#define PESDR1_460EX_L2REC 0x035A
+#define PESDR1_460EX_L3REC 0x035B
+#define PESDR1_460EX_L0LPB 0x035C
+#define PESDR1_460EX_L1LPB 0x035D
+#define PESDR1_460EX_L2LPB 0x035E
+#define PESDR1_460EX_L3LPB 0x035F
+#define PESDR1_460EX_L0CLK 0x0360
+#define PESDR1_460EX_L1CLK 0x0361
+#define PESDR1_460EX_L2CLK 0x0362
+#define PESDR1_460EX_L3CLK 0x0363
+#define PESDR1_460EX_PHY_CTL_RST 0x0364
+#define PESDR1_460EX_RSTSTA 0x0365
+#define PESDR1_460EX_OBS 0x0366
+#define PESDR1_460EX_L0ERRC 0x0368
+#define PESDR1_460EX_L1ERRC 0x0369
+#define PESDR1_460EX_L2ERRC 0x036A
+#define PESDR1_460EX_L3ERRC 0x036B
+#define PESDR0_460EX_IHS1 0x036C
+#define PESDR0_460EX_IHS2 0x036D
+
/*
* Of the above, some are common offsets from the base
*/
#define PECFG_POM2LAL 0x390
#define PECFG_POM2LAH 0x394
+/* SDR Bit Mappings */
+#define PESDRx_RCSSET_HLDPLB 0x10000000
+#define PESDRx_RCSSET_RSTGU 0x01000000
+#define PESDRx_RCSSET_RDY 0x00100000
+#define PESDRx_RCSSET_RSTDL 0x00010000
+#define PESDRx_RCSSET_RSTPYN 0x00001000
enum
{
--- /dev/null
+/*
+ * IBM/AMCC PPC4xx SoC setup code
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003 - 2006 Zultys Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/dcr.h>
+#include <asm/dcr-regs.h>
+#include <asm/reg.h>
+
+static u32 dcrbase_l2c;
+
+/*
+ * L2-cache
+ */
+
+/* Issue L2C diagnostic command */
+static inline u32 l2c_diag(u32 addr)
+{
+ mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
+ while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
+ ;
+
+ return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
+}
+
+static irqreturn_t l2c_error_handler(int irq, void *dev)
+{
+ u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);
+
+ if (sr & L2C_SR_CPE) {
+ /* Read cache trapped address */
+ u32 addr = l2c_diag(0x42000000);
+ printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
+ addr);
+ }
+ if (sr & L2C_SR_TPE) {
+ /* Read tag trapped address */
+ u32 addr = l2c_diag(0x82000000) >> 16;
+ printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
+ addr);
+ }
+
+ /* Clear parity errors */
+ if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
+ mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
+ } else {
+ printk(KERN_EMERG "L2C: LRU error\n");
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int __init ppc4xx_l2c_probe(void)
+{
+ struct device_node *np;
+ u32 r;
+ unsigned long flags;
+ int irq;
+ const u32 *dcrreg;
+ u32 dcrbase_isram;
+ int len;
+ const u32 *prop;
+ u32 l2_size;
+
+ np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
+ if (!np)
+ return 0;
+
+ /* Get l2 cache size */
+ prop = of_get_property(np, "cache-size", NULL);
+ if (prop == NULL) {
+ printk(KERN_ERR "%s: Can't get cache-size!\n", np->full_name);
+ of_node_put(np);
+ return -ENODEV;
+ }
+ l2_size = prop[0];
+
+ /* Map DCRs */
+ dcrreg = of_get_property(np, "dcr-reg", &len);
+ if (!dcrreg || (len != 4 * sizeof(u32))) {
+ printk(KERN_ERR "%s: Can't get DCR register base !",
+ np->full_name);
+ of_node_put(np);
+ return -ENODEV;
+ }
+ dcrbase_isram = dcrreg[0];
+ dcrbase_l2c = dcrreg[2];
+
+ /* Get and map irq number from device tree */
+ irq = irq_of_parse_and_map(np, 0);
+ if (irq == NO_IRQ) {
+ printk(KERN_ERR "irq_of_parse_and_map failed\n");
+ of_node_put(np);
+ return -ENODEV;
+ }
+
+ /* Install error handler */
+ if (request_irq(irq, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0) {
+ printk(KERN_ERR "Cannot install L2C error handler"
+ ", cache is not enabled\n");
+ of_node_put(np);
+ return -ENODEV;
+ }
+
+ local_irq_save(flags);
+ asm volatile ("sync" ::: "memory");
+
+ /* Disable SRAM */
+ mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
+ mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
+ mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
+ mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
+ mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
+ mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
+ mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
+ mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
+ mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
+ mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
+
+ /* Enable L2_MODE without ICU/DCU */
+ r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
+ ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
+ r |= L2C_CFG_L2M | L2C_CFG_SS_256;
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
+
+ mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
+
+ /* Hardware Clear Command */
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
+ while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
+ ;
+
+ /* Clear Cache Parity and Tag Errors */
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
+
+ /* Enable 64G snoop region starting at 0 */
+ r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
+ ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
+ r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
+ mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
+
+ r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
+ ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
+ r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
+ mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
+
+ asm volatile ("sync" ::: "memory");
+
+ /* Enable ICU/DCU ports */
+ r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
+ r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM
+ | L2C_CFG_TPEI | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
+ r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
+ | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
+
+ /* Check for 460EX/GT special handling */
+ if (of_device_is_compatible(np, "ibm,l2-cache-460ex"))
+ r |= L2C_CFG_RDBW;
+
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
+
+ asm volatile ("sync; isync" ::: "memory");
+ local_irq_restore(flags);
+
+ printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);
+
+ of_node_put(np);
+ return 0;
+}
+arch_initcall(ppc4xx_l2c_probe);
+
+/*
+ * At present, this routine just applies a system reset.
+ */
+void ppc4xx_reset_system(char *cmd)
+{
+ mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_RST_SYSTEM);
+ while (1)
+ ; /* Just in case the reset doesn't work */
+}
/* We allocate this here because it is used almost exclusively for
* the communication processor devices.
*/
-struct qe_immap *qe_immr = NULL;
+struct qe_immap __iomem *qe_immr;
EXPORT_SYMBOL(qe_immr);
static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
*/
static unsigned int brg_clk = 0;
-unsigned int get_brg_clk(void)
+unsigned int qe_get_brg_clk(void)
{
struct device_node *qe;
unsigned int size;
return brg_clk;
}
+EXPORT_SYMBOL(qe_get_brg_clk);
/* Program the BRG to the given sampling rate and multiplier
*
if ((brg < QE_BRG1) || (brg > QE_BRG16))
return -EINVAL;
- divisor = get_brg_clk() / (rate * multiplier);
+ divisor = qe_get_brg_clk() / (rate * multiplier);
if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
div16 = QE_BRGC_DIV16;
}
EXPORT_SYMBOL(qe_muram_dump);
-void *qe_muram_addr(unsigned long offset)
-{
- return (void *)&qe_immr->muram[offset];
-}
-EXPORT_SYMBOL(qe_muram_addr);
-
/* The maximum number of RISCs we support */
#define MAX_QE_RISC 2
#include <linux/ioport.h>
#include <asm/io.h>
+#include <asm/qe.h>
#include <asm/prom.h>
#include <sysdev/fsl_soc.h>
#endif
};
-static struct port_regs *par_io = NULL;
+static struct port_regs __iomem *par_io;
static int num_par_io_ports = 0;
int par_io_init(struct device_node *np)
}
ph = of_get_property(np, "pio-handle", NULL);
- if (ph == 0) {
+ if (ph == NULL) {
printk(KERN_ERR "pio-handle not available \n");
return -1;
}
{
unsigned int i;
- printk(KERN_INFO "%s: par_io=%p\n", __FUNCTION__, par_io);
+ printk(KERN_INFO "%s: par_io=%p\n", __func__, par_io);
for (i = 0; i < num_par_io_ports; i++) {
printk(KERN_INFO " cpodr[%u]=%08x\n", i,
in_be32(&par_io[i].cpodr));
/* check if the UCC port number is in range. */
if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
- printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__);
+ printk(KERN_ERR "%s: illegal UCC number\n", __func__);
return -EINVAL;
}
/* Check that 'max_rx_buf_length' is properly aligned (4). */
if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
- __FUNCTION__);
+ __func__);
return -EINVAL;
}
/* Validate Virtual Fifo register values */
if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
- printk(KERN_ERR "%s: urfs is too small\n", __FUNCTION__);
+ printk(KERN_ERR "%s: urfs is too small\n", __func__);
return -EINVAL;
}
if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: urfs is not aligned\n", __FUNCTION__);
+ printk(KERN_ERR "%s: urfs is not aligned\n", __func__);
return -EINVAL;
}
if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: urfet is not aligned.\n", __FUNCTION__);
+ printk(KERN_ERR "%s: urfet is not aligned.\n", __func__);
return -EINVAL;
}
if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: urfset is not aligned\n", __FUNCTION__);
+ printk(KERN_ERR "%s: urfset is not aligned\n", __func__);
return -EINVAL;
}
if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: utfs is not aligned\n", __FUNCTION__);
+ printk(KERN_ERR "%s: utfs is not aligned\n", __func__);
return -EINVAL;
}
if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: utfet is not aligned\n", __FUNCTION__);
+ printk(KERN_ERR "%s: utfet is not aligned\n", __func__);
return -EINVAL;
}
if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
- printk(KERN_ERR "%s: utftt is not aligned\n", __FUNCTION__);
+ printk(KERN_ERR "%s: utftt is not aligned\n", __func__);
return -EINVAL;
}
uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
if (!uccf) {
printk(KERN_ERR "%s: Cannot allocate private data\n",
- __FUNCTION__);
+ __func__);
return -ENOMEM;
}
/* Set the PHY base address */
uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
if (uccf->uf_regs == NULL) {
- printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__);
+ printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
return -ENOMEM;
}
/* Set UCC to fast type */
ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
if (ret) {
- printk(KERN_ERR "%s: cannot set UCC type\n", __FUNCTION__);
+ printk(KERN_ERR "%s: cannot set UCC type\n", __func__);
ucc_fast_free(uccf);
return ret;
}
qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
- __FUNCTION__);
+ __func__);
uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
ucc_fast_free(uccf);
return -ENOMEM;
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
- __FUNCTION__);
+ __func__);
uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
ucc_fast_free(uccf);
return -ENOMEM;
ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
COMM_DIR_RX)) {
printk(KERN_ERR "%s: illegal value for RX clock\n",
- __FUNCTION__);
+ __func__);
ucc_fast_free(uccf);
return -EINVAL;
}
ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
COMM_DIR_TX)) {
printk(KERN_ERR "%s: illegal value for TX clock\n",
- __FUNCTION__);
+ __func__);
ucc_fast_free(uccf);
return -EINVAL;
}
/* check if the UCC port number is in range. */
if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
- printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__);
+ printk(KERN_ERR "%s: illegal UCC number\n", __func__);
return -EINVAL;
}
uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
if (!uccs) {
printk(KERN_ERR "%s: Cannot allocate private data\n",
- __FUNCTION__);
+ __func__);
return -ENOMEM;
}
/* Set the PHY base address */
uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
if (uccs->us_regs == NULL) {
- printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__);
+ printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
return -ENOMEM;
}
uccs->us_pram_offset =
qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
if (IS_ERR_VALUE(uccs->us_pram_offset)) {
- printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __FUNCTION__);
+ printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
ucc_slow_free(uccs);
return -ENOMEM;
}
/* Set UCC to slow type */
ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
if (ret) {
- printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__);
+ printk(KERN_ERR "%s: cannot set UCC type", __func__);
ucc_slow_free(uccs);
return ret;
}
qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
QE_ALIGNMENT_OF_BD);
if (IS_ERR_VALUE(uccs->rx_base_offset)) {
- printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __FUNCTION__,
+ printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
us_info->rx_bd_ring_len);
uccs->rx_base_offset = 0;
ucc_slow_free(uccs);
qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
QE_ALIGNMENT_OF_BD);
if (IS_ERR_VALUE(uccs->tx_base_offset)) {
- printk(KERN_ERR "%s: cannot allocate TX BDs", __FUNCTION__);
+ printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
uccs->tx_base_offset = 0;
ucc_slow_free(uccs);
return -ENOMEM;
if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
COMM_DIR_RX)) {
printk(KERN_ERR "%s: illegal value for RX clock\n",
- __FUNCTION__);
+ __func__);
ucc_slow_free(uccs);
return -EINVAL;
}
if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
COMM_DIR_TX)) {
printk(KERN_ERR "%s: illegal value for TX clock\n",
- __FUNCTION__);
+ __func__);
ucc_slow_free(uccs);
return -EINVAL;
}
return 0;
}
fs_initcall(add_rtc);
+
+MODULE_LICENSE("GPL");
ret = of_address_to_resource(np, 0, &r[0]);
DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
- __FUNCTION__,r[0].name, r[0].start, r[0].end);
+ __func__,r[0].name, r[0].start, r[0].end);
if (ret)
goto err;
r[1].end = irq_of_parse_and_map(np, 0);
r[1].flags = IORESOURCE_IRQ;
DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
- __FUNCTION__,r[1].name, r[1].start, r[1].end);
+ __func__,r[1].name, r[1].start, r[1].end);
tsi_eth_dev =
platform_device_register_simple("tsi-ethernet", i++, &r[0],
/* PCI Config mapping */
tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
tsi108_pci_cfg_phys = cfg_phys;
- DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
+ DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__,
tsi108_pci_cfg_base);
/* Fetch host bridge registers address */
static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{ unsigned int irq;
- DBG("%s(%d, 0x%lx)\n", __FUNCTION__, virq, hw);
+ DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
if ((virq >= 1) && (virq <= 4)){
irq = virq + IRQ_PCI_INTAD_BASE - 1;
get_irq_desc(irq)->status |= IRQ_LEVEL;
#ifdef CONFIG_PPC64
#include <asm/hvcall.h>
#include <asm/paca.h>
-#include <asm/iseries/it_lp_reg_save.h>
#endif
#include "nonstdio.h"
static int xmon_depth_to_print = 64;
-#ifdef CONFIG_PPC64
-#define LRSAVE_OFFSET 0x10
-#define REG_FRAME_MARKER 0x7265677368657265ul /* "regshere" */
-#define MARKER_OFFSET 0x60
+#define LRSAVE_OFFSET (STACK_FRAME_LR_SAVE * sizeof(unsigned long))
+#define MARKER_OFFSET (STACK_FRAME_MARKER * sizeof(unsigned long))
+
+#ifdef __powerpc64__
#define REGS_OFFSET 0x70
#else
-#define LRSAVE_OFFSET 4
-#define REG_FRAME_MARKER 0x72656773
-#define MARKER_OFFSET 8
#define REGS_OFFSET 16
#endif
/* Look for "regshere" marker to see if this is
an exception frame. */
if (mread(sp + MARKER_OFFSET, &marker, sizeof(unsigned long))
- && marker == REG_FRAME_MARKER) {
+ && marker == STACK_FRAME_REGS_MARKER) {
if (mread(sp + REGS_OFFSET, ®s, sizeof(regs))
!= sizeof(regs)) {
printf("Couldn't read registers at %lx\n",
if (firmware_has_feature(FW_FEATURE_ISERIES)) {
struct paca_struct *ptrPaca;
struct lppaca *ptrLpPaca;
- struct ItLpRegSave *ptrLpRegSave;
/* Dump out relevant Paca data areas. */
printf("Paca: \n");
printf(" Saved Gpr3=%.16lx Saved Gpr4=%.16lx \n",
ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4);
printf(" Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5);
-
- printf(" Local Processor Register Save Area (LpRegSave): \n");
- ptrLpRegSave = ptrPaca->reg_save_ptr;
- printf(" Saved Sprg0=%.16lx Saved Sprg1=%.16lx \n",
- ptrLpRegSave->xSPRG0, ptrLpRegSave->xSPRG0);
- printf(" Saved Sprg2=%.16lx Saved Sprg3=%.16lx \n",
- ptrLpRegSave->xSPRG2, ptrLpRegSave->xSPRG3);
- printf(" Saved Msr =%.16lx Saved Nia =%.16lx \n",
- ptrLpRegSave->xMSR, ptrLpRegSave->xNIA);
}
#endif
({ \
u32 offset = offsetof(immap_t, member); \
void *addr = ioremap (IMAP_ADDR + offset, \
- sizeof( ((immap_t*)0)->member)); \
+ FIELD_SIZEOF(immap_t, member)); \
addr; \
})
#ifdef CONFIG_USE_MDIO
static void fec_enet_mii(struct net_device *dev);
#endif /* CONFIG_USE_MDIO */
-static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
#ifdef CONFIG_FEC_PACKETHOOK
static void fec_enet_tx(struct net_device *dev, __u32 regval);
static void fec_enet_rx(struct net_device *dev, __u32 regval);
* This is called from the MPC core interrupt.
*/
static irqreturn_t
-fec_enet_interrupt(int irq, void * dev_id)
+fec_enet_interrupt(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
volatile fec_t *fecp;
#ifdef CONFIG_USE_MDIO
fec_enet_mii(dev);
#else
-printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__,__LINE__,__FUNCTION__);
+printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__, __LINE__, __func__);
#endif /* CONFIG_USE_MDIO */
}
fecp->fec_ecntrl = ecntrl; /* restore old settings */
}
#else
-printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__,__LINE__,__FUNCTION__);
+printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__, __LINE__, __func__);
#endif /* CONFIG_USE_MDIO */
#ifndef CONFIG_RPXCLASSIC
/* we haven't used ctr or xer or lr */
b fast_exception_return
-/*
- * AltiVec unavailable trap from kernel - print a message, but let
- * the task use AltiVec in the kernel until it returns to user mode.
- */
-KernelAltiVec:
- lwz r3,_MSR(r1)
- oris r3,r3,MSR_VEC@h
- stw r3,_MSR(r1) /* enable use of AltiVec after return */
- lis r3,87f@h
- ori r3,r3,87f@l
- mr r4,r2 /* current */
- lwz r5,_NIP(r1)
- bl printk
- b ret_from_except
-87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
- .align 4,0
-
/*
* giveup_altivec(tsk)
* Disable AltiVec for the task given as the argument,
}
-int
-pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx=0; idx<6; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1<<idx)))
- continue;
-
- r = &dev->resource[idx];
- if (r->flags & IORESOURCE_UNSET) {
- printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (dev->resource[PCI_ROM_RESOURCE].start)
- cmd |= PCI_COMMAND_MEMORY;
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
static int next_controller_index;
struct pci_controller * __init
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
if (ppc_md.pcibios_enable_device_hook)
if (ppc_md.pcibios_enable_device_hook(dev, 0))
return -EINVAL;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx=0; idx<6; idx++) {
- r = &dev->resource[idx];
- if (r->flags & IORESOURCE_UNSET) {
- printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
+
+ return pci_enable_resources(dev, mask);
}
struct pci_controller*
printk("Mem-info:\n");
show_free_areas();
- printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
i = max_mapnr;
while (i-- > 0) {
total++;
{
int irq;
- pr_debug("%s\n", __FUNCTION__);
+ pr_debug("%s\n", __func__);
i8259_init(0, 0);
mv64360_init_irq();
};
const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4;
- pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __FUNCTION__,
+ pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __func__,
dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin);
return PCI_IRQ_TABLE_LOOKUP;
u32 data;
u8 data8;
- pr_debug("%s: enter\n", __FUNCTION__);
+ pr_debug("%s: enter\n", __func__);
/* Wait for debugger? */
if (ppc7d_wait_debugger) {
ppc_md.set_rtc_time = ppc7d_set_rtc_time;
ppc_md.get_rtc_time = ppc7d_get_rtc_time;
- pr_debug("%s: exit\n", __FUNCTION__);
+ pr_debug("%s: exit\n", __func__);
}
/* Called from machine_init(), early, before any of the __init functions
.end = sbc82xx_i8259_end_irq,
};
-static irqreturn_t sbc82xx_i8259_demux(int irq, void *dev_id)
+static irqreturn_t sbc82xx_i8259_demux(int dummy, void *dev_id)
{
+ int irq;
+
spin_lock(&sbc82xx_i8259_lock);
sbc82xx_i8259_map[0] = 0x0c; /* OCW3: Read IR register on RD# pulse */
int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
{
- static spinlock_t lock = SPIN_LOCK_UNLOCKED;
+ static DEFINE_SPINLOCK(lock);
struct mpc52xx_cdm __iomem *cdm;
unsigned long flags;
u16 mclken_div;
#include <asm/io.h>
#include <asm/ocp.h>
#include <asm/errno.h>
-#include <asm/semaphore.h>
//#define DBG(x) printk x
#define DBG(x)
# Cryptographic API
#
-obj-$(CONFIG_CRYPTO_SHA1_S390) += sha1_s390.o
-obj-$(CONFIG_CRYPTO_SHA256_S390) += sha256_s390.o
+obj-$(CONFIG_CRYPTO_SHA1_S390) += sha1_s390.o sha_common.o
+obj-$(CONFIG_CRYPTO_SHA256_S390) += sha256_s390.o sha_common.o
+obj-$(CONFIG_CRYPTO_SHA512_S390) += sha512_s390.o sha_common.o
obj-$(CONFIG_CRYPTO_DES_S390) += des_s390.o des_check_key.o
obj-$(CONFIG_CRYPTO_AES_S390) += aes_s390.o
obj-$(CONFIG_S390_PRNG) += prng.o
KIMD_QUERY = CRYPT_S390_KIMD | 0,
KIMD_SHA_1 = CRYPT_S390_KIMD | 1,
KIMD_SHA_256 = CRYPT_S390_KIMD | 2,
+ KIMD_SHA_512 = CRYPT_S390_KIMD | 3,
};
/*
KLMD_QUERY = CRYPT_S390_KLMD | 0,
KLMD_SHA_1 = CRYPT_S390_KLMD | 1,
KLMD_SHA_256 = CRYPT_S390_KLMD | 2,
+ KLMD_SHA_512 = CRYPT_S390_KLMD | 3,
};
/*
--- /dev/null
+/*
+ * Cryptographic API.
+ *
+ * s390 generic implementation of the SHA Secure Hash Algorithms.
+ *
+ * Copyright IBM Corp. 2007
+ * Author(s): Jan Glauber (jang@de.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+#ifndef _CRYPTO_ARCH_S390_SHA_H
+#define _CRYPTO_ARCH_S390_SHA_H
+
+#include <linux/crypto.h>
+#include <crypto/sha.h>
+
+/* must be big enough for the largest SHA variant */
+#define SHA_MAX_STATE_SIZE 16
+#define SHA_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
+
+struct s390_sha_ctx {
+ u64 count; /* message length in bytes */
+ u32 state[SHA_MAX_STATE_SIZE];
+ u8 buf[2 * SHA_MAX_BLOCK_SIZE];
+ int func; /* KIMD function to use */
+};
+
+void s390_sha_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len);
+void s390_sha_final(struct crypto_tfm *tfm, u8 *out);
+
+#endif
#include <crypto/sha.h>
#include "crypt_s390.h"
-
-struct s390_sha1_ctx {
- u64 count; /* message length */
- u32 state[5];
- u8 buf[2 * SHA1_BLOCK_SIZE];
-};
+#include "sha.h"
static void sha1_init(struct crypto_tfm *tfm)
{
- struct s390_sha1_ctx *sctx = crypto_tfm_ctx(tfm);
+ struct s390_sha_ctx *sctx = crypto_tfm_ctx(tfm);
sctx->state[0] = SHA1_H0;
sctx->state[1] = SHA1_H1;
sctx->state[3] = SHA1_H3;
sctx->state[4] = SHA1_H4;
sctx->count = 0;
-}
-
-static void sha1_update(struct crypto_tfm *tfm, const u8 *data,
- unsigned int len)
-{
- struct s390_sha1_ctx *sctx = crypto_tfm_ctx(tfm);
- unsigned int index;
- int ret;
-
- /* how much is already in the buffer? */
- index = sctx->count & 0x3f;
-
- sctx->count += len;
-
- if (index + len < SHA1_BLOCK_SIZE)
- goto store;
-
- /* process one stored block */
- if (index) {
- memcpy(sctx->buf + index, data, SHA1_BLOCK_SIZE - index);
- ret = crypt_s390_kimd(KIMD_SHA_1, sctx->state, sctx->buf,
- SHA1_BLOCK_SIZE);
- BUG_ON(ret != SHA1_BLOCK_SIZE);
- data += SHA1_BLOCK_SIZE - index;
- len -= SHA1_BLOCK_SIZE - index;
- }
-
- /* process as many blocks as possible */
- if (len >= SHA1_BLOCK_SIZE) {
- ret = crypt_s390_kimd(KIMD_SHA_1, sctx->state, data,
- len & ~(SHA1_BLOCK_SIZE - 1));
- BUG_ON(ret != (len & ~(SHA1_BLOCK_SIZE - 1)));
- data += ret;
- len -= ret;
- }
-
-store:
- /* anything left? */
- if (len)
- memcpy(sctx->buf + index , data, len);
-}
-
-/* Add padding and return the message digest. */
-static void sha1_final(struct crypto_tfm *tfm, u8 *out)
-{
- struct s390_sha1_ctx *sctx = crypto_tfm_ctx(tfm);
- u64 bits;
- unsigned int index, end;
- int ret;
-
- /* must perform manual padding */
- index = sctx->count & 0x3f;
- end = (index < 56) ? SHA1_BLOCK_SIZE : (2 * SHA1_BLOCK_SIZE);
-
- /* start pad with 1 */
- sctx->buf[index] = 0x80;
-
- /* pad with zeros */
- index++;
- memset(sctx->buf + index, 0x00, end - index - 8);
-
- /* append message length */
- bits = sctx->count * 8;
- memcpy(sctx->buf + end - 8, &bits, sizeof(bits));
-
- ret = crypt_s390_kimd(KIMD_SHA_1, sctx->state, sctx->buf, end);
- BUG_ON(ret != end);
-
- /* copy digest to out */
- memcpy(out, sctx->state, SHA1_DIGEST_SIZE);
-
- /* wipe context */
- memset(sctx, 0, sizeof *sctx);
+ sctx->func = KIMD_SHA_1;
}
static struct crypto_alg alg = {
.cra_priority = CRYPT_S390_PRIORITY,
.cra_flags = CRYPTO_ALG_TYPE_DIGEST,
.cra_blocksize = SHA1_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct s390_sha1_ctx),
+ .cra_ctxsize = sizeof(struct s390_sha_ctx),
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(alg.cra_list),
.cra_u = { .digest = {
.dia_digestsize = SHA1_DIGEST_SIZE,
.dia_init = sha1_init,
- .dia_update = sha1_update,
- .dia_final = sha1_final } }
+ .dia_update = s390_sha_update,
+ .dia_final = s390_sha_final } }
};
static int __init sha1_s390_init(void)
{
if (!crypt_s390_func_available(KIMD_SHA_1))
return -EOPNOTSUPP;
-
return crypto_register_alg(&alg);
}
module_exit(sha1_s390_fini);
MODULE_ALIAS("sha1");
-
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm");
#include <crypto/sha.h>
#include "crypt_s390.h"
-
-struct s390_sha256_ctx {
- u64 count; /* message length */
- u32 state[8];
- u8 buf[2 * SHA256_BLOCK_SIZE];
-};
+#include "sha.h"
static void sha256_init(struct crypto_tfm *tfm)
{
- struct s390_sha256_ctx *sctx = crypto_tfm_ctx(tfm);
+ struct s390_sha_ctx *sctx = crypto_tfm_ctx(tfm);
sctx->state[0] = SHA256_H0;
sctx->state[1] = SHA256_H1;
sctx->state[6] = SHA256_H6;
sctx->state[7] = SHA256_H7;
sctx->count = 0;
-}
-
-static void sha256_update(struct crypto_tfm *tfm, const u8 *data,
- unsigned int len)
-{
- struct s390_sha256_ctx *sctx = crypto_tfm_ctx(tfm);
- unsigned int index;
- int ret;
-
- /* how much is already in the buffer? */
- index = sctx->count & 0x3f;
-
- sctx->count += len;
-
- if ((index + len) < SHA256_BLOCK_SIZE)
- goto store;
-
- /* process one stored block */
- if (index) {
- memcpy(sctx->buf + index, data, SHA256_BLOCK_SIZE - index);
- ret = crypt_s390_kimd(KIMD_SHA_256, sctx->state, sctx->buf,
- SHA256_BLOCK_SIZE);
- BUG_ON(ret != SHA256_BLOCK_SIZE);
- data += SHA256_BLOCK_SIZE - index;
- len -= SHA256_BLOCK_SIZE - index;
- }
-
- /* process as many blocks as possible */
- if (len >= SHA256_BLOCK_SIZE) {
- ret = crypt_s390_kimd(KIMD_SHA_256, sctx->state, data,
- len & ~(SHA256_BLOCK_SIZE - 1));
- BUG_ON(ret != (len & ~(SHA256_BLOCK_SIZE - 1)));
- data += ret;
- len -= ret;
- }
-
-store:
- /* anything left? */
- if (len)
- memcpy(sctx->buf + index , data, len);
-}
-
-/* Add padding and return the message digest */
-static void sha256_final(struct crypto_tfm *tfm, u8 *out)
-{
- struct s390_sha256_ctx *sctx = crypto_tfm_ctx(tfm);
- u64 bits;
- unsigned int index, end;
- int ret;
-
- /* must perform manual padding */
- index = sctx->count & 0x3f;
- end = (index < 56) ? SHA256_BLOCK_SIZE : (2 * SHA256_BLOCK_SIZE);
-
- /* start pad with 1 */
- sctx->buf[index] = 0x80;
-
- /* pad with zeros */
- index++;
- memset(sctx->buf + index, 0x00, end - index - 8);
-
- /* append message length */
- bits = sctx->count * 8;
- memcpy(sctx->buf + end - 8, &bits, sizeof(bits));
-
- ret = crypt_s390_kimd(KIMD_SHA_256, sctx->state, sctx->buf, end);
- BUG_ON(ret != end);
-
- /* copy digest to out */
- memcpy(out, sctx->state, SHA256_DIGEST_SIZE);
-
- /* wipe context */
- memset(sctx, 0, sizeof *sctx);
+ sctx->func = KIMD_SHA_256;
}
static struct crypto_alg alg = {
.cra_priority = CRYPT_S390_PRIORITY,
.cra_flags = CRYPTO_ALG_TYPE_DIGEST,
.cra_blocksize = SHA256_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct s390_sha256_ctx),
+ .cra_ctxsize = sizeof(struct s390_sha_ctx),
.cra_module = THIS_MODULE,
.cra_list = LIST_HEAD_INIT(alg.cra_list),
.cra_u = { .digest = {
.dia_digestsize = SHA256_DIGEST_SIZE,
.dia_init = sha256_init,
- .dia_update = sha256_update,
- .dia_final = sha256_final } }
+ .dia_update = s390_sha_update,
+ .dia_final = s390_sha_final } }
};
static int sha256_s390_init(void)
module_exit(sha256_s390_fini);
MODULE_ALIAS("sha256");
-
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm");
--- /dev/null
+/*
+ * Cryptographic API.
+ *
+ * s390 implementation of the SHA512 and SHA38 Secure Hash Algorithm.
+ *
+ * Copyright IBM Corp. 2007
+ * Author(s): Jan Glauber (jang@de.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/crypto.h>
+
+#include "sha.h"
+#include "crypt_s390.h"
+
+static void sha512_init(struct crypto_tfm *tfm)
+{
+ struct s390_sha_ctx *ctx = crypto_tfm_ctx(tfm);
+
+ *(__u64 *)&ctx->state[0] = 0x6a09e667f3bcc908ULL;
+ *(__u64 *)&ctx->state[2] = 0xbb67ae8584caa73bULL;
+ *(__u64 *)&ctx->state[4] = 0x3c6ef372fe94f82bULL;
+ *(__u64 *)&ctx->state[6] = 0xa54ff53a5f1d36f1ULL;
+ *(__u64 *)&ctx->state[8] = 0x510e527fade682d1ULL;
+ *(__u64 *)&ctx->state[10] = 0x9b05688c2b3e6c1fULL;
+ *(__u64 *)&ctx->state[12] = 0x1f83d9abfb41bd6bULL;
+ *(__u64 *)&ctx->state[14] = 0x5be0cd19137e2179ULL;
+ ctx->count = 0;
+ ctx->func = KIMD_SHA_512;
+}
+
+static struct crypto_alg sha512_alg = {
+ .cra_name = "sha512",
+ .cra_driver_name = "sha512-s390",
+ .cra_priority = CRYPT_S390_PRIORITY,
+ .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
+ .cra_blocksize = SHA512_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct s390_sha_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_list = LIST_HEAD_INIT(sha512_alg.cra_list),
+ .cra_u = { .digest = {
+ .dia_digestsize = SHA512_DIGEST_SIZE,
+ .dia_init = sha512_init,
+ .dia_update = s390_sha_update,
+ .dia_final = s390_sha_final } }
+};
+
+MODULE_ALIAS("sha512");
+
+static void sha384_init(struct crypto_tfm *tfm)
+{
+ struct s390_sha_ctx *ctx = crypto_tfm_ctx(tfm);
+
+ *(__u64 *)&ctx->state[0] = 0xcbbb9d5dc1059ed8ULL;
+ *(__u64 *)&ctx->state[2] = 0x629a292a367cd507ULL;
+ *(__u64 *)&ctx->state[4] = 0x9159015a3070dd17ULL;
+ *(__u64 *)&ctx->state[6] = 0x152fecd8f70e5939ULL;
+ *(__u64 *)&ctx->state[8] = 0x67332667ffc00b31ULL;
+ *(__u64 *)&ctx->state[10] = 0x8eb44a8768581511ULL;
+ *(__u64 *)&ctx->state[12] = 0xdb0c2e0d64f98fa7ULL;
+ *(__u64 *)&ctx->state[14] = 0x47b5481dbefa4fa4ULL;
+ ctx->count = 0;
+ ctx->func = KIMD_SHA_512;
+}
+
+static struct crypto_alg sha384_alg = {
+ .cra_name = "sha384",
+ .cra_driver_name = "sha384-s390",
+ .cra_priority = CRYPT_S390_PRIORITY,
+ .cra_flags = CRYPTO_ALG_TYPE_DIGEST,
+ .cra_blocksize = SHA384_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct s390_sha_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_list = LIST_HEAD_INIT(sha384_alg.cra_list),
+ .cra_u = { .digest = {
+ .dia_digestsize = SHA384_DIGEST_SIZE,
+ .dia_init = sha384_init,
+ .dia_update = s390_sha_update,
+ .dia_final = s390_sha_final } }
+};
+
+MODULE_ALIAS("sha384");
+
+static int __init init(void)
+{
+ int ret;
+
+ if (!crypt_s390_func_available(KIMD_SHA_512))
+ return -EOPNOTSUPP;
+ if ((ret = crypto_register_alg(&sha512_alg)) < 0)
+ goto out;
+ if ((ret = crypto_register_alg(&sha384_alg)) < 0)
+ crypto_unregister_alg(&sha512_alg);
+out:
+ return ret;
+}
+
+static void __exit fini(void)
+{
+ crypto_unregister_alg(&sha512_alg);
+ crypto_unregister_alg(&sha384_alg);
+}
+
+module_init(init);
+module_exit(fini);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("SHA512 and SHA-384 Secure Hash Algorithm");
--- /dev/null
+/*
+ * Cryptographic API.
+ *
+ * s390 generic implementation of the SHA Secure Hash Algorithms.
+ *
+ * Copyright IBM Corp. 2007
+ * Author(s): Jan Glauber (jang@de.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+
+#include <linux/crypto.h>
+#include "sha.h"
+#include "crypt_s390.h"
+
+void s390_sha_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)
+{
+ struct s390_sha_ctx *ctx = crypto_tfm_ctx(tfm);
+ unsigned int bsize = crypto_tfm_alg_blocksize(tfm);
+ unsigned int index;
+ int ret;
+
+ /* how much is already in the buffer? */
+ index = ctx->count & (bsize - 1);
+ ctx->count += len;
+
+ if ((index + len) < bsize)
+ goto store;
+
+ /* process one stored block */
+ if (index) {
+ memcpy(ctx->buf + index, data, bsize - index);
+ ret = crypt_s390_kimd(ctx->func, ctx->state, ctx->buf, bsize);
+ BUG_ON(ret != bsize);
+ data += bsize - index;
+ len -= bsize - index;
+ }
+
+ /* process as many blocks as possible */
+ if (len >= bsize) {
+ ret = crypt_s390_kimd(ctx->func, ctx->state, data,
+ len & ~(bsize - 1));
+ BUG_ON(ret != (len & ~(bsize - 1)));
+ data += ret;
+ len -= ret;
+ }
+store:
+ if (len)
+ memcpy(ctx->buf + index , data, len);
+}
+EXPORT_SYMBOL_GPL(s390_sha_update);
+
+void s390_sha_final(struct crypto_tfm *tfm, u8 *out)
+{
+ struct s390_sha_ctx *ctx = crypto_tfm_ctx(tfm);
+ unsigned int bsize = crypto_tfm_alg_blocksize(tfm);
+ u64 bits;
+ unsigned int index, end, plen;
+ int ret;
+
+ /* SHA-512 uses 128 bit padding length */
+ plen = (bsize > SHA256_BLOCK_SIZE) ? 16 : 8;
+
+ /* must perform manual padding */
+ index = ctx->count & (bsize - 1);
+ end = (index < bsize - plen) ? bsize : (2 * bsize);
+
+ /* start pad with 1 */
+ ctx->buf[index] = 0x80;
+ index++;
+
+ /* pad with zeros */
+ memset(ctx->buf + index, 0x00, end - index - 8);
+
+ /*
+ * Append message length. Well, SHA-512 wants a 128 bit lenght value,
+ * nevertheless we use u64, should be enough for now...
+ */
+ bits = ctx->count * 8;
+ memcpy(ctx->buf + end - 8, &bits, sizeof(bits));
+
+ ret = crypt_s390_kimd(ctx->func, ctx->state, ctx->buf, end);
+ BUG_ON(ret != end);
+
+ /* copy digest to out */
+ memcpy(out, ctx->state, crypto_hash_digestsize(crypto_hash_cast(tfm)));
+ /* wipe context */
+ memset(ctx, 0, sizeof *ctx);
+}
+EXPORT_SYMBOL_GPL(s390_sha_final);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("s390 SHA cipher common functions");
#include <asm/types.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <net/scm.h>
#include <net/sock.h>
#include <linux/ctype.h>
#include <linux/sysctl.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/fs.h>
select CPU_SH2A
select CPU_HAS_FPU
+config CPU_SUBTYPE_MXG
+ bool "Support MX-G processor"
+ select CPU_SH2A
+ help
+ Select MX-G if running on an R8A03022BG part.
+
# SH-3 Processor Support
config CPU_SUBTYPE_SH7705
# SH-4A Processor Support
+config CPU_SUBTYPE_SH7723
+ bool "Support SH7723 processor"
+ select CPU_SH4A
+ select CPU_SHX2
+ select ARCH_SPARSEMEM_ENABLE
+ select SYS_SUPPORTS_NUMA
+ help
+ Select SH7723 if you have an SH-MobileR2 CPU.
+
config CPU_SUBTYPE_SH7763
bool "Support SH7763 processor"
select CPU_SH4A
Select 7619 SolutionEngine if configuring for a Hitachi SH7619
evaluation board.
+config SH_7721_SOLUTION_ENGINE
+ bool "SolutionEngine7721"
+ select SOLUTION_ENGINE
+ depends on CPU_SUBTYPE_SH7721
+ help
+ Select 7721 SolutionEngine if configuring for a Hitachi SH7721
+ evaluation board.
+
config SH_7722_SOLUTION_ENGINE
bool "SolutionEngine7722"
select SOLUTION_ENGINE
config SH_CMT
def_bool y
prompt "CMT timer support"
- depends on CPU_SH2
+ depends on CPU_SH2 && !CPU_SUBTYPE_MXG
help
This enables the use of the CMT as the system timer.
default "86" if CPU_SUBTYPE_SH7619
default "140" if CPU_SUBTYPE_SH7206
default "142" if CPU_SUBTYPE_SH7203
+ default "238" if CPU_SUBTYPE_MXG
default "16"
config SH_PCLK_FREQ
default "27000000" if CPU_SUBTYPE_SH7343
default "31250000" if CPU_SUBTYPE_SH7619
default "32000000" if CPU_SUBTYPE_SH7722
- default "33333333" if CPU_SUBTYPE_SH7770 || \
+ default "33333333" if CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7723 || \
CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
- CPU_SUBTYPE_SH7263
+ CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG
default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
default "66000000" if CPU_SUBTYPE_SH4_202
default "50000000"
config EARLY_SCIF_CONSOLE_PORT
hex
depends on EARLY_SCIF_CONSOLE
- default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763
- default "0xffe00000" if CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
- default "0xffea0000" if CPU_SUBTYPE_SH7785
- default "0xfffe8000" if CPU_SUBTYPE_SH7203
- default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
- default "0xf8420000" if CPU_SUBTYPE_SH7619
default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
+ default "0xf8420000" if CPU_SUBTYPE_SH7619
+ default "0xff804000" if CPU_SUBTYPE_MXG
default "0xffc30000" if CPU_SUBTYPE_SHX3
+ default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
+ CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
default "0xffe80000" if CPU_SH4
+ default "0xffea0000" if CPU_SUBTYPE_SH7785
+ default "0xfffe8000" if CPU_SUBTYPE_SH7203
+ default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
default "0x00000000"
config EARLY_PRINTK
machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE) += se/7751
machdir-$(CONFIG_SH_7780_SOLUTION_ENGINE) += se/7780
machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE) += se/7343
+machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE) += se/7721
machdir-$(CONFIG_SH_HP6XX) += hp6xx
machdir-$(CONFIG_SH_DREAMCAST) += dreamcast
machdir-$(CONFIG_SH_MPC1211) += mpc1211
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/i2c.h>
#include <asm/machvec.h>
#include <asm/io.h>
+#include <asm/sh_keysc.h>
+#include <asm/migor.h>
/* Address IRQ Size Bus Description
* 0x00000000 64MB 16 NOR Flash (SP29PL256N)
static struct resource smc91x_eth_resources[] = {
[0] = {
- .name = "smc91x-regs" ,
- .start = P2SEGADDR(0x10000300),
- .end = P2SEGADDR(0x1000030f),
+ .name = "SMC91C111" ,
+ .start = 0x10000300,
+ .end = 0x1000030f,
.flags = IORESOURCE_MEM,
},
[1] = {
.resource = smc91x_eth_resources,
};
+static struct sh_keysc_info sh_keysc_info = {
+ .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
+ .scan_timing = 3,
+ .delay = 5,
+ .keycodes = {
+ 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
+ 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
+ 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
+ 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
+ 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
+ },
+};
+
+static struct resource sh_keysc_resources[] = {
+ [0] = {
+ .start = 0x044b0000,
+ .end = 0x044b000f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 79,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device sh_keysc_device = {
+ .name = "sh_keysc",
+ .num_resources = ARRAY_SIZE(sh_keysc_resources),
+ .resource = sh_keysc_resources,
+ .dev = {
+ .platform_data = &sh_keysc_info,
+ },
+};
+
+static struct mtd_partition migor_nor_flash_partitions[] =
+{
+ {
+ .name = "uboot",
+ .offset = 0,
+ .size = (1 * 1024 * 1024),
+ .mask_flags = MTD_WRITEABLE, /* Read-only */
+ },
+ {
+ .name = "rootfs",
+ .offset = MTDPART_OFS_APPEND,
+ .size = (15 * 1024 * 1024),
+ },
+ {
+ .name = "other",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct physmap_flash_data migor_nor_flash_data = {
+ .width = 2,
+ .parts = migor_nor_flash_partitions,
+ .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
+};
+
+static struct resource migor_nor_flash_resources[] = {
+ [0] = {
+ .name = "NOR Flash",
+ .start = 0x00000000,
+ .end = 0x03ffffff,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+static struct platform_device migor_nor_flash_device = {
+ .name = "physmap-flash",
+ .resource = migor_nor_flash_resources,
+ .num_resources = ARRAY_SIZE(migor_nor_flash_resources),
+ .dev = {
+ .platform_data = &migor_nor_flash_data,
+ },
+};
+
+static struct mtd_partition migor_nand_flash_partitions[] = {
+ {
+ .name = "nanddata1",
+ .offset = 0x0,
+ .size = 512 * 1024 * 1024,
+ },
+ {
+ .name = "nanddata2",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 512 * 1024 * 1024,
+ },
+};
+
+static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+ if (ctrl & NAND_CLE)
+ writeb(cmd, chip->IO_ADDR_W + 0x00400000);
+ else if (ctrl & NAND_ALE)
+ writeb(cmd, chip->IO_ADDR_W + 0x00800000);
+ else
+ writeb(cmd, chip->IO_ADDR_W);
+}
+
+static int migor_nand_flash_ready(struct mtd_info *mtd)
+{
+ return ctrl_inb(PORT_PADR) & 0x02; /* PTA1 */
+}
+
+struct platform_nand_data migor_nand_flash_data = {
+ .chip = {
+ .nr_chips = 1,
+ .partitions = migor_nand_flash_partitions,
+ .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
+ .chip_delay = 20,
+ .part_probe_types = (const char *[]) { "cmdlinepart", NULL },
+ },
+ .ctrl = {
+ .dev_ready = migor_nand_flash_ready,
+ .cmd_ctrl = migor_nand_flash_cmd_ctl,
+ },
+};
+
+static struct resource migor_nand_flash_resources[] = {
+ [0] = {
+ .name = "NAND Flash",
+ .start = 0x18000000,
+ .end = 0x18ffffff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device migor_nand_flash_device = {
+ .name = "gen_nand",
+ .resource = migor_nand_flash_resources,
+ .num_resources = ARRAY_SIZE(migor_nand_flash_resources),
+ .dev = {
+ .platform_data = &migor_nand_flash_data,
+ }
+};
+
static struct platform_device *migor_devices[] __initdata = {
&smc91x_eth_device,
+ &sh_keysc_device,
+ &migor_nor_flash_device,
+ &migor_nand_flash_device,
+};
+
+static struct i2c_board_info __initdata migor_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("rtc-rs5c372", 0x32),
+ .type = "rs5c372b",
+ },
+ {
+ I2C_BOARD_INFO("migor_ts", 0x51),
+ .irq = 38, /* IRQ6 */
+ },
};
static int __init migor_devices_setup(void)
{
+ i2c_register_board_info(0, migor_i2c_devices,
+ ARRAY_SIZE(migor_i2c_devices));
+
return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
__initcall(migor_devices_setup);
static void __init migor_setup(char **cmdline_p)
{
- ctrl_outw(0x1000, 0xa4050110); /* Enable IRQ0 in PJCR */
+ /* SMC91C111 - Enable IRQ0 */
+ ctrl_outw(ctrl_inw(PORT_PJCR) & ~0x0003, PORT_PJCR);
+
+ /* KEYSC */
+ ctrl_outw(ctrl_inw(PORT_PYCR) & ~0x0fff, PORT_PYCR);
+ ctrl_outw(ctrl_inw(PORT_PZCR) & ~0x0ff0, PORT_PZCR);
+ ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA);
+ ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
+ ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
+ ctrl_outl(ctrl_inl(MSTPCR2) & ~0x00004000, MSTPCR2);
+
+ /* NAND Flash */
+ ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR);
+ ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200,
+ BSC_CS6ABCR);
+
+ /* I2C */
+ ctrl_outl(ctrl_inl(MSTPCR1) & ~0x00000200, MSTPCR1);
+
+ /* Touch Panel - Enable IRQ6 */
+ ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR);
+ ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA);
+ ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC);
}
static struct sh_machine_vector mv_migor __initmv = {
UNUSED = 0,
/* board specific interrupt sources */
- AX88796, /* Ethernet controller */
- CF, /* Compact Flash */
- PSW, /* Push Switch */
- EXT1, /* EXT1n IRQ */
- EXT4, /* EXT4n IRQ */
+ CF, /* Compact Flash */
+ TP, /* Touch panel */
+ SCIF1, /* FPGA SCIF1 */
+ SCIF0, /* FPGA SCIF0 */
+ SMBUS, /* SMBUS */
+ RTC, /* RTC Alarm */
+ AX88796, /* Ethernet controller */
+ PSW, /* Push Switch */
+
+ /* external bus connector */
+ EXT1, EXT2, EXT4, EXT5, EXT6,
};
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(CF, IRQ_CF),
- INTC_IRQ(PSW, IRQ_PSW),
+ INTC_IRQ(TP, IRQ_TP),
+ INTC_IRQ(SCIF1, IRQ_SCIF1),
+ INTC_IRQ(SCIF0, IRQ_SCIF0),
+ INTC_IRQ(SMBUS, IRQ_SMBUS),
+ INTC_IRQ(RTC, IRQ_RTC),
INTC_IRQ(AX88796, IRQ_AX88796),
- INTC_IRQ(EXT1, IRQ_EXT1),
- INTC_IRQ(EXT4, IRQ_EXT4),
+ INTC_IRQ(PSW, IRQ_PSW),
+
+ INTC_IRQ(EXT1, IRQ_EXT1), INTC_IRQ(EXT2, IRQ_EXT2),
+ INTC_IRQ(EXT4, IRQ_EXT4), INTC_IRQ(EXT5, IRQ_EXT5),
+ INTC_IRQ(EXT6, IRQ_EXT6),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xa4000000, 0, 16, /* IRLMSK */
- { 0, 0, 0, 0, CF, 0, 0, 0,
- 0, 0, 0, EXT4, 0, EXT1, PSW, AX88796 } },
+ { SCIF0, SCIF1, RTC, 0, CF, 0, TP, SMBUS,
+ 0, EXT6, EXT5, EXT4, EXT2, EXT1, PSW, AX88796 } },
};
static unsigned char irl2irq[HL_NR_IRL] __initdata = {
- 0, IRQ_CF, 0, 0,
- 0, 0, 0, 0,
- 0, IRQ_EXT4, 0, IRQ_EXT1,
+ 0, IRQ_CF, IRQ_TP, IRQ_SCIF1,
+ IRQ_SCIF0, IRQ_SMBUS, IRQ_RTC, IRQ_EXT6,
+ IRQ_EXT5, IRQ_EXT4, IRQ_EXT2, IRQ_EXT1,
0, IRQ_AX88796, IRQ_PSW,
};
* Renesas Solutions Highlander Support.
*
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
- * Copyright (C) 2005 - 2007 Paul Mundt
+ * Copyright (C) 2005 - 2008 Paul Mundt
*
* This contains support for the R7780RP-1, R7780MP, and R7785RP
* Highlander modules.
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/types.h>
+#include <linux/i2c.h>
#include <net/ax88796.h>
#include <asm/machvec.h>
#include <asm/r7780rp.h>
.resource = ax88796_resources,
};
+static struct resource smbus_resources[] = {
+ [0] = {
+ .start = PA_SMCR,
+ .end = PA_SMCR + 0x100 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SMBUS,
+ .end = IRQ_SMBUS,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device smbus_device = {
+ .name = "i2c-highlander",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(smbus_resources),
+ .resource = smbus_resources,
+};
+
+static struct i2c_board_info __initdata highlander_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("rtc-rs5c372", 0x32),
+ .type = "r2025sd",
+ },
+};
static struct platform_device *r7780rp_devices[] __initdata = {
&r8a66597_usb_host_device,
&m66592_usb_peripheral_device,
&heartbeat_device,
+ &smbus_device,
#ifndef CONFIG_SH_R7780RP
&ax88796_device,
#endif
static int __init r7780rp_devices_setup(void)
{
+ int ret = 0;
+
#ifndef CONFIG_SH_R7780RP
if (register_trapped_io(&cf_trapped_io) == 0)
- platform_device_register(&cf_ide_device);
+ ret |= platform_device_register(&cf_ide_device);
#endif
- return platform_add_devices(r7780rp_devices,
+
+ ret |= platform_add_devices(r7780rp_devices,
ARRAY_SIZE(r7780rp_devices));
+
+ ret |= i2c_register_board_info(0, highlander_i2c_devices,
+ ARRAY_SIZE(highlander_i2c_devices));
+
+ return ret;
}
device_initcall(r7780rp_devices_setup);
--- /dev/null
+obj-y := setup.o irq.o
--- /dev/null
+/*
+ * linux/arch/sh/boards/se/7721/irq.c
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <asm/se7721.h>
+
+enum {
+ UNUSED = 0,
+
+ /* board specific interrupt sources */
+ MRSHPC,
+};
+
+static struct intc_vect vectors[] __initdata = {
+ INTC_IRQ(MRSHPC, MRSHPC_IRQ0),
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+ { FPGA_ILSR6, 0, 8, 4, /* IRLMSK */
+ { 0, MRSHPC } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "SE7721", vectors,
+ NULL, NULL, prio_registers, NULL);
+
+/*
+ * Initialize IRQ setting
+ */
+void __init init_se7721_IRQ(void)
+{
+ /* PPCR */
+ ctrl_outw(ctrl_inw(0xa4050118) & ~0x00ff, 0xa4050118);
+
+ register_intc_controller(&intc_desc);
+ intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0);
+}
--- /dev/null
+/*
+ * linux/arch/sh/boards/se/7721/setup.c
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * Hitachi UL SolutionEngine 7721 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <asm/machvec.h>
+#include <asm/se7721.h>
+#include <asm/io.h>
+#include <asm/heartbeat.h>
+
+static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
+
+static struct heartbeat_data heartbeat_data = {
+ .bit_pos = heartbeat_bit_pos,
+ .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
+ .regsize = 16,
+};
+
+static struct resource heartbeat_resources[] = {
+ [0] = {
+ .start = PA_LED,
+ .end = PA_LED,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device heartbeat_device = {
+ .name = "heartbeat",
+ .id = -1,
+ .dev = {
+ .platform_data = &heartbeat_data,
+ },
+ .num_resources = ARRAY_SIZE(heartbeat_resources),
+ .resource = heartbeat_resources,
+};
+
+static struct resource cf_ide_resources[] = {
+ [0] = {
+ .start = PA_MRSHPC_IO + 0x1f0,
+ .end = PA_MRSHPC_IO + 0x1f0 + 8 ,
+ .flags = IORESOURCE_IO,
+ },
+ [1] = {
+ .start = PA_MRSHPC_IO + 0x1f0 + 0x206,
+ .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
+ .flags = IORESOURCE_IO,
+ },
+ [2] = {
+ .start = MRSHPC_IRQ0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device cf_ide_device = {
+ .name = "pata_platform",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(cf_ide_resources),
+ .resource = cf_ide_resources,
+};
+
+static struct platform_device *se7721_devices[] __initdata = {
+ &cf_ide_device,
+ &heartbeat_device
+};
+
+static int __init se7721_devices_setup(void)
+{
+ return platform_add_devices(se7721_devices,
+ ARRAY_SIZE(se7721_devices));
+}
+device_initcall(se7721_devices_setup);
+
+static void __init se7721_setup(char **cmdline_p)
+{
+ /* for USB */
+ ctrl_outw(0x0000, 0xA405010C); /* PGCR */
+ ctrl_outw(0x0000, 0xA405010E); /* PHCR */
+ ctrl_outw(0x00AA, 0xA4050118); /* PPCR */
+ ctrl_outw(0x0000, 0xA4050124); /* PSELA */
+}
+
+/*
+ * The Machine Vector
+ */
+struct sh_machine_vector mv_se7721 __initmv = {
+ .mv_name = "Solution Engine 7721",
+ .mv_setup = se7721_setup,
+ .mv_nr_irqs = 109,
+ .mv_init_irq = init_se7721_IRQ,
+};
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
+#include <linux/input.h>
#include <asm/machvec.h>
#include <asm/se7722.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
+#include <asm/sh_keysc.h>
/* Heartbeat */
static struct heartbeat_data heartbeat_data = {
.resource = cf_ide_resources,
};
+static struct sh_keysc_info sh_keysc_info = {
+ .mode = SH_KEYSC_MODE_1, /* KEYOUT0->5, KEYIN0->4 */
+ .scan_timing = 3,
+ .delay = 5,
+ .keycodes = { /* SW1 -> SW30 */
+ KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
+ KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
+ KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
+ KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T,
+ KEY_U, KEY_V, KEY_W, KEY_X, KEY_Y,
+ KEY_Z,
+ KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE, /* life */
+ },
+};
+
+static struct resource sh_keysc_resources[] = {
+ [0] = {
+ .start = 0x044b0000,
+ .end = 0x044b000f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 79,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device sh_keysc_device = {
+ .name = "sh_keysc",
+ .num_resources = ARRAY_SIZE(sh_keysc_resources),
+ .resource = sh_keysc_resources,
+ .dev = {
+ .platform_data = &sh_keysc_info,
+ },
+};
+
static struct platform_device *se7722_devices[] __initdata = {
&heartbeat_device,
&smc91x_eth_device,
&cf_ide_device,
+ &sh_keysc_device,
};
static int __init se7722_devices_setup(void)
ctrl_outw(0x0A10, PORT_PSELA); /* BS,SHHID2 */
ctrl_outw(0x0000, PORT_PYCR);
ctrl_outw(0x0000, PORT_PZCR);
+ ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
+ ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
}
/*
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc5
+# Fri Mar 21 12:05:31 2008
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+# CONFIG_BUG is not set
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=1
+CONFIG_MODULES=y
+# CONFIG_MODULE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System type
+#
+CONFIG_CPU_SH3=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+CONFIG_CPU_SUBTYPE_SH7721=y
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+# CONFIG_CPU_SUBTYPE_SH5_101 is not set
+# CONFIG_CPU_SUBTYPE_SH5_103 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_MEMORY_SIZE=0x02000000
+CONFIG_29BIT=y
+CONFIG_VSYSCALL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+
+#
+# Cache configuration
+#
+# CONFIG_SH_DIRECT_MAPPED is not set
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_SH_FPU_EMU is not set
+# CONFIG_SH_DSP is not set
+# CONFIG_SH_ADC is not set
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_DSP=y
+
+#
+# Board support
+#
+CONFIG_SOLUTION_ENGINE=y
+CONFIG_SH_7721_SOLUTION_ENGINE=y
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TMU=y
+CONFIG_SH_TIMER_IRQ=16
+CONFIG_SH_PCLK_FREQ=33333333
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# DMA support
+#
+# CONFIG_SH_DMA is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+CONFIG_HEARTBEAT=y
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+CONFIG_GUSA=y
+# CONFIG_GUSA_RB is not set
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/sda2"
+
+#
+# Bus options
+#
+CONFIG_CF_ENABLER=y
+# CONFIG_CF_AREA5 is not set
+CONFIG_CF_AREA6=y
+CONFIG_CF_BASE_ADDR=0xb8000000
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+# CONFIG_NET_SCH_RR is not set
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=y
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_IND=y
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_MV is not set
+CONFIG_PATA_PLATFORM=y
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=2
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLBFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_CODEPAGE_932=y
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_SH_STANDARD_BIOS is not set
+# CONFIG_EARLY_SCIF_CONSOLE is not set
+# CONFIG_DEBUG_BOOTMEM is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_4KSTACKS is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_SH_KGDB is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
#define PCI_PROBE_BIOS 1
#define PCI_PROBE_CONF1 2
#define PCI_PROBE_CONF2 4
-#define PCI_NO_SORT 0x100
-#define PCI_BIOS_SORT 0x200
#define PCI_NO_CHECKS 0x400
#define PCI_ASSIGN_ROMS 0x1000
#define PCI_BIOS_IRQ_SCAN 0x2000
#include <asm/se.h>
#elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
#include <asm/se7722.h>
+#elif defined(CONFIG_SH_7721_SOLUTION_ENGINE)
+#include <asm/se7721.h>
#endif
/*
* 0xB0600000 : I/O
*/
-#if defined(CONFIG_SH_SOLUTION_ENGINE) || defined(CONFIG_SH_7722_SOLUTION_ENGINE)
+#if defined(CONFIG_SH_SOLUTION_ENGINE) || \
+ defined(CONFIG_SH_7722_SOLUTION_ENGINE) || \
+ defined(CONFIG_SH_7721_SOLUTION_ENGINE)
static int __init cf_init_se(void)
{
if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0)
}
/*
- * PC-Card window open
+ * PC-Card window open
* flag == COMMON/ATTRIBUTE/IO
*/
/* common window open */
ctrl_outw(0x0b00, MRSHPC_MW0CR2);
else
/* common mode & bus width 16bit SWAP = 0*/
- ctrl_outw(0x0300, MRSHPC_MW0CR2);
+ ctrl_outw(0x0300, MRSHPC_MW0CR2);
/* attribute window open */
ctrl_outw(0x8a85, MRSHPC_MW1CR1);
int __init cf_init(void)
{
- if( mach_is_se() || mach_is_7722se() ){
+ if (mach_is_se() || mach_is_7722se() || mach_is_7721se())
return cf_init_se();
- }
-
+
return cf_init_default();
}
obj-$(CONFIG_SH_FPU) += fpu.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
boot_cpu_data.type = CPU_SH7206;
/* While SH7206 has a DSP.. */
boot_cpu_data.flags |= CPU_HAS_DSP;
+#elif defined(CONFIG_CPU_SUBTYPE_MXG)
+ boot_cpu_data.type = CPU_MXG;
+ boot_cpu_data.flags |= CPU_HAS_DSP;
#endif
boot_cpu_data.dcache.ways = 4;
--- /dev/null
+/*
+ * Renesas MX-G (R8A03022BG) Setup
+ *
+ * Copyright (C) 2008 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/serial_sci.h>
+
+enum {
+ UNUSED = 0,
+
+ /* interrupt sources */
+ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+ IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
+
+ PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
+
+ SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
+
+ SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
+ SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
+
+ MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
+ MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
+ MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
+ MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
+ MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
+ MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
+ MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
+
+ /* interrupt groups */
+ PINT, SCIF0, SCIF1,
+ MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
+};
+
+static struct intc_vect vectors[] __initdata = {
+ INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
+ INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
+ INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
+ INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
+ INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73),
+ INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75),
+ INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77),
+ INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79),
+
+ INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
+ INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
+ INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
+ INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
+
+ INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95),
+ INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97),
+ INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
+ INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
+
+ INTC_IRQ(SCIF0_RXI, 220), INTC_IRQ(SCIF0_TXI, 221),
+ INTC_IRQ(SCIF0_BRI, 222), INTC_IRQ(SCIF0_ERI, 223),
+ INTC_IRQ(SCIF1_RXI, 224), INTC_IRQ(SCIF1_TXI, 225),
+ INTC_IRQ(SCIF1_BRI, 226), INTC_IRQ(SCIF1_ERI, 227),
+
+ INTC_IRQ(MTU2_TGI0A, 228), INTC_IRQ(MTU2_TGI0B, 229),
+ INTC_IRQ(MTU2_TGI0C, 230), INTC_IRQ(MTU2_TGI0D, 231),
+ INTC_IRQ(MTU2_TCI0V, 232), INTC_IRQ(MTU2_TGI0E, 233),
+
+ INTC_IRQ(MTU2_TGI0F, 234), INTC_IRQ(MTU2_TGI1A, 235),
+ INTC_IRQ(MTU2_TGI1B, 236), INTC_IRQ(MTU2_TCI1V, 237),
+ INTC_IRQ(MTU2_TCI1U, 238), INTC_IRQ(MTU2_TGI2A, 239),
+
+ INTC_IRQ(MTU2_TGI2B, 240), INTC_IRQ(MTU2_TCI2V, 241),
+ INTC_IRQ(MTU2_TCI2U, 242), INTC_IRQ(MTU2_TGI3A, 243),
+
+ INTC_IRQ(MTU2_TGI3B, 244),
+ INTC_IRQ(MTU2_TGI3C, 245),
+
+ INTC_IRQ(MTU2_TGI3D, 246), INTC_IRQ(MTU2_TCI3V, 247),
+ INTC_IRQ(MTU2_TGI4A, 248), INTC_IRQ(MTU2_TGI4B, 249),
+ INTC_IRQ(MTU2_TGI4C, 250), INTC_IRQ(MTU2_TGI4D, 251),
+
+ INTC_IRQ(MTU2_TCI4V, 252), INTC_IRQ(MTU2_TGI5U, 253),
+ INTC_IRQ(MTU2_TGI5V, 254), INTC_IRQ(MTU2_TGI5W, 255),
+};
+
+static struct intc_group groups[] __initdata = {
+ INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
+ PINT4, PINT5, PINT6, PINT7),
+ INTC_GROUP(MTU2_GROUP1, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
+ MTU2_TCI0V, MTU2_TGI0E),
+ INTC_GROUP(MTU2_GROUP2, MTU2_TGI0F, MTU2_TGI1A, MTU2_TGI1B,
+ MTU2_TCI1V, MTU2_TCI1U, MTU2_TGI2A),
+ INTC_GROUP(MTU2_GROUP3, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
+ MTU2_TGI3A),
+ INTC_GROUP(MTU2_GROUP4, MTU2_TGI3D, MTU2_TCI3V, MTU2_TGI4A,
+ MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
+ INTC_GROUP(MTU2_GROUP5, MTU2_TCI4V, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
+ INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
+ INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+ { 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
+ { 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
+ { 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } },
+ { 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } },
+ { 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
+ { 0xfffd9800, 0, 16, 4, /* IPR06 */ { } },
+ { 0xfffd9802, 0, 16, 4, /* IPR07 */ { } },
+ { 0xfffd9804, 0, 16, 4, /* IPR08 */ { } },
+ { 0xfffd9806, 0, 16, 4, /* IPR09 */ { } },
+ { 0xfffd9808, 0, 16, 4, /* IPR10 */ { } },
+ { 0xfffd980a, 0, 16, 4, /* IPR11 */ { } },
+ { 0xfffd980c, 0, 16, 4, /* IPR12 */ { } },
+ { 0xfffd980e, 0, 16, 4, /* IPR13 */ { } },
+ { 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } },
+ { 0xfffd9812, 0, 16, 4, /* IPR15 */
+ { SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } },
+ { 0xfffd9814, 0, 16, 4, /* IPR16 */
+ { MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } },
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+ { 0xfffd9408, 0, 16, /* PINTER */
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
+ mask_registers, prio_registers, NULL);
+
+static struct plat_sci_port sci_platform_data[] = {
+ {
+ .mapbase = 0xff804000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 223, 220, 221, 222 },
+ }, {
+ .flags = 0,
+ }
+};
+
+static struct platform_device sci_device = {
+ .name = "sh-sci",
+ .id = -1,
+ .dev = {
+ .platform_data = sci_platform_data,
+ },
+};
+
+static struct platform_device *mxg_devices[] __initdata = {
+ &sci_device,
+};
+
+static int __init mxg_devices_setup(void)
+{
+ return platform_add_devices(mxg_devices,
+ ARRAY_SIZE(mxg_devices));
+}
+__initcall(mxg_devices_setup);
+
+void __init plat_irq_setup(void)
+{
+ register_intc_controller(&intc_desc);
+}
/*
* Setup some generic flags we can probe on SH-4A parts
*/
- if (((pvr >> 16) & 0xff) == 0x10) {
+ if (((pvr >> 24) & 0xff) == 0x10) {
if ((cvr & 0x10000000) == 0)
boot_cpu_data.flags |= CPU_HAS_DSP;
CPU_HAS_LLSC;
break;
case 0x3008:
- if (prr == 0xa0 || prr == 0xa1) {
- boot_cpu_data.type = CPU_SH7722;
- boot_cpu_data.icache.ways = 4;
- boot_cpu_data.dcache.ways = 4;
- boot_cpu_data.flags |= CPU_HAS_LLSC;
- }
- else if (prr == 0x70) {
+ boot_cpu_data.icache.ways = 4;
+ boot_cpu_data.dcache.ways = 4;
+ boot_cpu_data.flags |= CPU_HAS_LLSC;
+
+ switch (prr) {
+ case 0x50:
+ boot_cpu_data.type = CPU_SH7723;
+ boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE;
+ break;
+ case 0x70:
boot_cpu_data.type = CPU_SH7366;
- boot_cpu_data.icache.ways = 4;
- boot_cpu_data.dcache.ways = 4;
- boot_cpu_data.flags |= CPU_HAS_LLSC;
+ break;
+ case 0xa0:
+ case 0xa1:
+ boot_cpu_data.type = CPU_SH7722;
+ break;
}
break;
case 0x4000: /* 1st cut */
* SH-4A's have an optional PIPT L2.
*/
if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
+ /* Bug if we can't decode the L2 info */
+ BUG_ON(!(cvr & 0xf));
+
+ /* Silicon and specifications have clearly never met.. */
+ cvr ^= 0xf;
+
/*
* Size calculation is much more sensible
* than it is for the L1.
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
static struct resource usbf_resources[] = {
[0] = {
- .name = "m66592_udc",
- .start = 0xA4480000,
- .end = 0xA44800FF,
+ .name = "USBF",
+ .start = 0x04480000,
+ .end = 0x044800FF,
.flags = IORESOURCE_MEM,
},
[1] = {
- .name = "m66592_udc",
.start = 65,
.end = 65,
.flags = IORESOURCE_IRQ,
.resource = usbf_resources,
};
+static struct resource iic_resources[] = {
+ [0] = {
+ .name = "IIC",
+ .start = 0x04470000,
+ .end = 0x04470017,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 96,
+ .end = 99,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device iic_device = {
+ .name = "i2c-sh_mobile",
+ .num_resources = ARRAY_SIZE(iic_resources),
+ .resource = iic_resources,
+};
+
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xffe00000,
static struct platform_device *sh7722_devices[] __initdata = {
&usbf_device,
+ &iic_device,
&sci_device,
};
--- /dev/null
+/*
+ * SH7723 Setup
+ *
+ * Copyright (C) 2008 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/mm.h>
+#include <linux/serial_sci.h>
+#include <asm/mmzone.h>
+
+static struct plat_sci_port sci_platform_data[] = {
+ {
+ .mapbase = 0xa4e30000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCI,
+ .irqs = { 56, 56, 56, 56 },
+ },{
+ .mapbase = 0xa4e40000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCI,
+ .irqs = { 88, 88, 88, 88 },
+ },{
+ .mapbase = 0xa4e50000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCI,
+ .irqs = { 109, 109, 109, 109 },
+ }, {
+ .flags = 0,
+ }
+};
+
+static struct platform_device sci_device = {
+ .name = "sh-sci",
+ .id = -1,
+ .dev = {
+ .platform_data = sci_platform_data,
+ },
+};
+
+static struct resource rtc_resources[] = {
+ [0] = {
+ .start = 0xa465fec0,
+ .end = 0xa465fec0 + 0x58 - 1,
+ .flags = IORESOURCE_IO,
+ },
+ [1] = {
+ /* Period IRQ */
+ .start = 69,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* Carry IRQ */
+ .start = 70,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ /* Alarm IRQ */
+ .start = 68,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device rtc_device = {
+ .name = "sh-rtc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(rtc_resources),
+ .resource = rtc_resources,
+};
+
+static struct platform_device *sh7723_devices[] __initdata = {
+ &sci_device,
+ &rtc_device,
+};
+
+static int __init sh7723_devices_setup(void)
+{
+ return platform_add_devices(sh7723_devices,
+ ARRAY_SIZE(sh7723_devices));
+}
+__initcall(sh7723_devices_setup);
+
+enum {
+ UNUSED=0,
+
+ /* interrupt sources */
+ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+ HUDI,
+ DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
+ _2DG_TRI,_2DG_INI,_2DG_CEI,
+ DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
+ VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
+ SCIFA_SCIFA0,
+ VPU_VPUI,
+ TPU_TPUI,
+ ADC_ADI,
+ USB_USI0,
+ RTC_ATI,RTC_PRI,RTC_CUI,
+ DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
+ DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
+ KEYSC_KEYI,
+ SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
+ MSIOF_MSIOFI0,MSIOF_MSIOFI1,
+ SCIFA_SCIFA1,
+ FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
+ I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
+ SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
+ CMT_CMTI,
+ TSIF_TSIFI,
+ SIU_SIUI,
+ SCIFA_SCIFA2,
+ TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
+ IRDA_IRDAI,
+ ATAPI_ATAPII,
+ SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
+ VEU2H1_VEU2HI,
+ LCDC_LCDCI,
+ TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
+
+ /* interrupt groups */
+ DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
+ SDHI1, RTC, DMAC1B, SDHI0,
+};
+
+static struct intc_vect vectors[] __initdata = {
+ INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
+ INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
+ INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
+ INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
+
+ INTC_VECT(DMAC1A_DEI0,0x700),
+ INTC_VECT(DMAC1A_DEI1,0x720),
+ INTC_VECT(DMAC1A_DEI2,0x740),
+ INTC_VECT(DMAC1A_DEI3,0x760),
+
+ INTC_VECT(_2DG_TRI, 0x780),
+ INTC_VECT(_2DG_INI, 0x7A0),
+ INTC_VECT(_2DG_CEI, 0x7C0),
+
+ INTC_VECT(DMAC0A_DEI0,0x800),
+ INTC_VECT(DMAC0A_DEI1,0x820),
+ INTC_VECT(DMAC0A_DEI2,0x840),
+ INTC_VECT(DMAC0A_DEI3,0x860),
+
+ INTC_VECT(VIO_CEUI,0x880),
+ INTC_VECT(VIO_BEUI,0x8A0),
+ INTC_VECT(VIO_VEU2HI,0x8C0),
+ INTC_VECT(VIO_VOUI,0x8E0),
+
+ INTC_VECT(SCIFA_SCIFA0,0x900),
+ INTC_VECT(VPU_VPUI,0x920),
+ INTC_VECT(TPU_TPUI,0x9A0),
+ INTC_VECT(ADC_ADI,0x9E0),
+ INTC_VECT(USB_USI0,0xA20),
+
+ INTC_VECT(RTC_ATI,0xA80),
+ INTC_VECT(RTC_PRI,0xAA0),
+ INTC_VECT(RTC_CUI,0xAC0),
+
+ INTC_VECT(DMAC1B_DEI4,0xB00),
+ INTC_VECT(DMAC1B_DEI5,0xB20),
+ INTC_VECT(DMAC1B_DADERR,0xB40),
+
+ INTC_VECT(DMAC0B_DEI4,0xB80),
+ INTC_VECT(DMAC0B_DEI5,0xBA0),
+ INTC_VECT(DMAC0B_DADERR,0xBC0),
+
+ INTC_VECT(KEYSC_KEYI,0xBE0),
+ INTC_VECT(SCIF_SCIF0,0xC00),
+ INTC_VECT(SCIF_SCIF1,0xC20),
+ INTC_VECT(SCIF_SCIF2,0xC40),
+ INTC_VECT(MSIOF_MSIOFI0,0xC80),
+ INTC_VECT(MSIOF_MSIOFI1,0xCA0),
+ INTC_VECT(SCIFA_SCIFA1,0xD00),
+
+ INTC_VECT(FLCTL_FLSTEI,0xD80),
+ INTC_VECT(FLCTL_FLTENDI,0xDA0),
+ INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
+ INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
+
+ INTC_VECT(I2C_ALI,0xE00),
+ INTC_VECT(I2C_TACKI,0xE20),
+ INTC_VECT(I2C_WAITI,0xE40),
+ INTC_VECT(I2C_DTEI,0xE60),
+
+ INTC_VECT(SDHI0_SDHII0,0xE80),
+ INTC_VECT(SDHI0_SDHII1,0xEA0),
+ INTC_VECT(SDHI0_SDHII2,0xEC0),
+
+ INTC_VECT(CMT_CMTI,0xF00),
+ INTC_VECT(TSIF_TSIFI,0xF20),
+ INTC_VECT(SIU_SIUI,0xF80),
+ INTC_VECT(SCIFA_SCIFA2,0xFA0),
+
+ INTC_VECT(TMU0_TUNI0,0x400),
+ INTC_VECT(TMU0_TUNI1,0x420),
+ INTC_VECT(TMU0_TUNI2,0x440),
+
+ INTC_VECT(IRDA_IRDAI,0x480),
+ INTC_VECT(ATAPI_ATAPII,0x4A0),
+
+ INTC_VECT(SDHI1_SDHII0,0x4E0),
+ INTC_VECT(SDHI1_SDHII1,0x500),
+ INTC_VECT(SDHI1_SDHII2,0x520),
+
+ INTC_VECT(VEU2H1_VEU2HI,0x560),
+ INTC_VECT(LCDC_LCDCI,0x580),
+
+ INTC_VECT(TMU1_TUNI0,0x920),
+ INTC_VECT(TMU1_TUNI1,0x940),
+ INTC_VECT(TMU1_TUNI2,0x960),
+
+};
+
+static struct intc_group groups[] __initdata = {
+ INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
+ INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
+ INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
+ INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
+ INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
+ INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
+ INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
+ INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
+ INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
+ INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
+ INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+ { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
+ { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
+ { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
+ { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
+ { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
+ { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
+ { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
+ { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
+ { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
+ { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
+ { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
+ { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
+ { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
+ { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
+ { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
+ { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
+ FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
+ { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
+ { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
+ { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
+ { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
+ { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
+ { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
+ { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
+ { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
+ { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
+ { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
+ { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
+ { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+ { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
+ { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
+ { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
+ { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
+ { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
+ { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
+ { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
+ { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
+ { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
+ { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
+ { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
+ { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
+ { 0xa4140010, 0, 32, 4, /* INTPRI00 */
+ { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_sense_reg sense_registers[] __initdata = {
+ { 0xa414001c, 16, 2, /* ICR1 */
+ { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7723", vectors, groups,
+ mask_registers, prio_registers, sense_registers);
+
+void __init plat_irq_setup(void)
+{
+ register_intc_controller(&intc_desc);
+}
+
+void __init plat_mem_setup(void)
+{
+ /* Register the URAM space as Node 1 */
+ setup_bootmem_node(1, 0x055f0000, 0x05610000);
+}
INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
};
-static struct intc_prio priorities[] __initdata = {
- INTC_PRIO(SCIF0, 3),
- INTC_PRIO(SCIF1, 3),
- INTC_PRIO(SCIF2, 3),
-};
-
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
{ 0, 0, 0, 0, 0, 0, GPIO, 0,
{ 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
};
-static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups, priorities,
+static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
mask_registers, prio_registers, NULL);
/* Support for external interrupt pins in IRQ mode */
-
static struct intc_vect irq_vectors[] __initdata = {
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
irq_sense_registers);
/* External interrupt pins in IRL mode */
-
static struct intc_vect irl_vectors[] __initdata = {
INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
/*
* SH7770 Setup
*
- * Copyright (C) 2006 Paul Mundt
+ * Copyright (C) 2006 - 2008 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 63, 63, 63, 63 },
+ }, {
+ .mapbase = 0xff926000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 64, 64, 64, 64 },
+ }, {
+ .mapbase = 0xff927000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 65, 65, 65, 65 },
+ }, {
+ .mapbase = 0xff928000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 66, 66, 66, 66 },
+ }, {
+ .mapbase = 0xff929000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 67, 67, 67, 67 },
+ }, {
+ .mapbase = 0xff92a000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 68, 68, 68, 68 },
+ }, {
+ .mapbase = 0xff92b000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 69, 69, 69, 69 },
+ }, {
+ .mapbase = 0xff92c000,
+ .flags = UPF_BOOT_AUTOCONF,
+ .type = PORT_SCIF,
+ .irqs = { 70, 70, 70, 70 },
}, {
.flags = 0,
}
#include <linux/kexec.h>
#include <linux/module.h>
#include <linux/smp.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/page.h>
[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
+ [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
[CPU_SH7366] = "SH7366", [CPU_SH_NONE] = "Unknown"
};
.show = show_cpuinfo,
};
#endif /* CONFIG_PROC_FS */
+
+struct dentry *sh_debugfs_root;
+
+static int __init sh_debugfs_init(void)
+{
+ sh_debugfs_root = debugfs_create_dir("sh", NULL);
+ if (IS_ERR(sh_debugfs_root))
+ return PTR_ERR(sh_debugfs_root);
+
+ return 0;
+}
+arch_initcall(sh_debugfs_init);
mov #0,r0
!
1:
-#if defined(CONFIG_CPU_SH3)
- mov.l r0,@r4
-#elif defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4)
movca.l r0,@r4
mov r4,r1
+#else
+ mov.l r0,@r4
#endif
add #32,r4
mov.l r0,@-r4
mov.l @r11+,r5
mov.l @r11+,r6
mov.l @r11+,r7
-#if defined(CONFIG_CPU_SH3)
- mov.l r0,@r10
-#elif defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4)
movca.l r0,@r10
mov r10,r0
+#else
+ mov.l r0,@r10
#endif
add #32,r10
mov.l r7,@-r10
{
struct dentry *dcache_dentry, *icache_dentry;
- dcache_dentry = debugfs_create_file("dcache", S_IRUSR, NULL,
+ dcache_dentry = debugfs_create_file("dcache", S_IRUSR, sh_debugfs_root,
(unsigned int *)CACHE_TYPE_DCACHE,
&cache_debugfs_fops);
if (IS_ERR(dcache_dentry))
return PTR_ERR(dcache_dentry);
- icache_dentry = debugfs_create_file("icache", S_IRUSR, NULL,
+ icache_dentry = debugfs_create_file("icache", S_IRUSR, sh_debugfs_root,
(unsigned int *)CACHE_TYPE_ICACHE,
&cache_debugfs_fops);
if (IS_ERR(icache_dentry)) {
struct dentry *dentry;
dentry = debugfs_create_file("pmb", S_IFREG | S_IRUGO,
- NULL, NULL, &pmb_debugfs_fops);
+ sh_debugfs_root, NULL, &pmb_debugfs_fops);
if (IS_ERR(dentry))
return PTR_ERR(dentry);
7206SE SH_7206_SOLUTION_ENGINE
7343SE SH_7343_SOLUTION_ENGINE
7619SE SH_7619_SOLUTION_ENGINE
-7722SE SH_7722_SOLUTION_ENGINE
-7751SE SH_7751_SOLUTION_ENGINE
+7721SE SH_7721_SOLUTION_ENGINE
+7722SE SH_7722_SOLUTION_ENGINE
+7751SE SH_7751_SOLUTION_ENGINE
7780SE SH_7780_SOLUTION_ENGINE
7751SYSTEMH SH_7751_SYSTEMH
HP6XX SH_HP6XX
config OF
def_bool y
-config ARCH_SUPPORTS_AOUT
- def_bool y
-
config HZ
int
default 100
source "fs/Kconfig.binfmt"
-config SUNOS_EMUL
- bool "SunOS binary emulation"
- help
- This allows you to run most SunOS binaries. If you want to do this,
- say Y here and place appropriate files in /usr/gnemul/sunos. See
- <http://www.ultralinux.org/faq.html> for more information. If you
- want to run SunOS binaries on an Ultra you must also say Y to
- "Kernel support for 32-bit a.out binaries" above.
-
source "mm/Kconfig"
endmenu
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.23-rc1
-# Wed Jul 25 15:30:21 2007
+# Linux kernel version: 2.6.25
+# Sun Apr 20 01:49:51 2008
#
CONFIG_MMU=y
CONFIG_HIGHMEM=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_OF=y
+CONFIG_HZ=100
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
-# Code maturity level options
+# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
#
# General machine setup
CONFIG_PCI=y
CONFIG_PCI_SYSCALL=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_NO_DMA is not set
CONFIG_SUN_OPENPROMFS=m
# CONFIG_SPARC_LED is not set
CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_AOUT=y
CONFIG_BINFMT_MISC=m
-CONFIG_SUNOS_EMUL=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_XFRM_USER=m
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
CONFIG_NET_KEY=m
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_INET=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_INET6_XFRM_MODE_BEET=m
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
# CONFIG_NET_SCHED is not set
#
#
CONFIG_NET_PKTGEN=m
# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
CONFIG_AF_RXRPC=m
#
# Generic Driver Options
#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_SRP is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
# CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
#
# IEEE 1394 (FireWire) support
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
CONFIG_TUN=m
+# CONFIG_VETH is not set
# CONFIG_ARCNET is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
CONFIG_NETDEV_10000=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
# CONFIG_MYRI10GE is not set
# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
# CONFIG_TR is not set
#
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
-# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_EVBUG=m
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
#
# Serial drivers
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
CONFIG_HW_RANDOM=m
CONFIG_JS_RTC=m
# CONFIG_R3964 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
-# CONFIG_SENSORS_ABITUGURU3 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# Graphics support
#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
#
# Console display driver support
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
-
-#
-# USB Gadget Support
-#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_INFINIBAND is not set
-
-#
-# Real Time Clock
-#
# CONFIG_RTC_CLASS is not set
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
#
# Userspace I/O
#
CONFIG_FS_POSIX_ACL=y
CONFIG_XFS_FS=m
CONFIG_XFS_QUOTA=y
-CONFIG_XFS_SECURITY=y
CONFIG_XFS_POSIX_ACL=y
CONFIG_XFS_RT=y
-# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-CONFIG_ROMFS_FS=m
+CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
CONFIG_AUTOFS_FS=m
CONFIG_AUTOFS4_FS=m
# CONFIG_FUSE_FS is not set
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=m
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_SUN_PARTITION=y
-
-#
-# Native Language Support
-#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
# CONFIG_DLM is not set
-#
-# Instrumentation Support
-#
-# CONFIG_PROFILING is not set
-
#
# Kernel hacking
#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
-CONFIG_FORCED_INLINING=y
+# CONFIG_DEBUG_SG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
# CONFIG_DEBUG_STACK_USAGE is not set
#
CONFIG_KEYS=y
# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
CONFIG_CRYPTO_ARC4=m
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_CRC32C=m
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_HW is not set
#
IRQ_OBJS := irq.o sun4m_irq.o sun4c_irq.o sun4d_irq.o
obj-y := entry.o wof.o wuf.o etrap.o rtrap.o traps.o $(IRQ_OBJS) \
process.o signal.o ioport.o setup.o idprom.o \
- sys_sparc.o sunos_asm.o systbls.o \
- time.o windows.o cpu.o devices.o sclow.o \
- tadpole.o tick14.o ptrace.o sys_solaris.o \
+ sys_sparc.o systbls.o \
+ time.o windows.o cpu.o devices.o \
+ tadpole.o tick14.o ptrace.o \
unaligned.o una_asm.o muldiv.o \
prom.o of_device.o devres.o
obj-$(CONFIG_SUN_PM) += apc.o pmc.o
obj-$(CONFIG_MODULES) += module.o sparc_ksyms.o
obj-$(CONFIG_SPARC_LED) += led.o
-
-ifdef CONFIG_SUNOS_EMUL
-obj-y += sys_sunos.o sunos_ioctl.o
-endif
RESTORE_ALL
-#ifdef CONFIG_SUNOS_EMUL
- /* SunOS uses syscall zero as the 'indirect syscall' it looks
- * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
- * This is complete brain damage.
- */
- .globl sunos_indir
-sunos_indir:
- mov %o7, %l4
- cmp %o0, NR_SYSCALLS
- blu,a 1f
- sll %o0, 0x2, %o0
-
- sethi %hi(sunos_nosys), %l6
- b 2f
- or %l6, %lo(sunos_nosys), %l6
-
-1:
- set sunos_sys_table, %l7
- ld [%l7 + %o0], %l6
-
-2:
- mov %o1, %o0
- mov %o2, %o1
- mov %o3, %o2
- mov %o4, %o3
- mov %o5, %o4
- call %l6
- mov %l4, %o7
-#endif
-
.align 4
.globl sys_nis_syscall
sys_nis_syscall:
call sparc_execve
mov %l5, %o7
+ .globl sunos_execv
+sunos_execv:
+ st %g0, [%sp + STACKFRAME_SZ + PT_I2]
+
+ call sparc_execve
+ add %sp, STACKFRAME_SZ, %o0
+
+ b ret_sys_call
+ ld [%sp + STACKFRAME_SZ + PT_I0], %o0
+
.align 4
.globl sys_pipe
sys_pipe:
b ret_sys_call
ld [%sp + STACKFRAME_SZ + PT_I0], %o0
- /* Linux native and SunOS system calls enter here... */
+ /* Linux native system calls enter here... */
.align 4
.globl linux_sparc_syscall
linux_sparc_syscall:
st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
- /*
- * Solaris system calls and indirect system calls enter here.
- *
- * I have named the solaris indirect syscalls like that because
- * it seems like Solaris has some fast path syscalls that can
- * be handled as indirect system calls. - mig
- */
-
-linux_syscall_for_solaris:
- sethi %hi(sys_call_table), %l7
- b linux_sparc_syscall
- or %l7, %lo(sys_call_table), %l7
-
- .align 4
- .globl solaris_syscall
-solaris_syscall:
- cmp %g1,59
- be linux_syscall_for_solaris
- cmp %g1,2
- be linux_syscall_for_solaris
- cmp %g1,42
- be linux_syscall_for_solaris
- cmp %g1,119
- be,a linux_syscall_for_solaris
- mov 2, %g1
-1:
- SAVE_ALL_HEAD
- rd %wim, %l3
-
- wr %l0, PSR_ET, %psr
- nop
- nop
- mov %i0, %l5
-
- call do_solaris_syscall
- add %sp, STACKFRAME_SZ, %o0
-
- st %o0, [%sp + STACKFRAME_SZ + PT_I0]
- set PSR_C, %g2
- cmp %o0, -ERESTART_RESTARTBLOCK
- bgeu 1f
- ld [%sp + STACKFRAME_SZ + PT_PSR], %g3
-
- /* System call success, clear Carry condition code. */
- andn %g3, %g2, %g3
- clr %l6
- b 2f
- st %g3, [%sp + STACKFRAME_SZ + PT_PSR]
-
-1:
- /* System call failure, set Carry condition code.
- * Also, get abs(errno) to return to the process.
- */
- sub %g0, %o0, %o0
- mov 1, %l6
- st %o0, [%sp + STACKFRAME_SZ + PT_I0]
- or %g3, %g2, %g3
- st %g3, [%sp + STACKFRAME_SZ + PT_PSR]
-
- /* Advance the pc and npc over the trap instruction.
- * If the npc is unaligned (has a 1 in the lower byte), it means
- * the kernel does not want us to play magic (ie, skipping over
- * traps). Mainly when the Solaris code wants to set some PC and
- * nPC (setcontext).
- */
-2:
- ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 /* pc = npc */
- andcc %l1, 1, %g0
- bne 1f
- add %l1, 0x4, %l2 /* npc = npc+4 */
- st %l1, [%sp + STACKFRAME_SZ + PT_PC]
- b ret_trap_entry
- st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
-
- /* kernel knows what it is doing, fixup npc and continue */
-1:
- sub %l1, 1, %l1
- b ret_trap_entry
- st %l1, [%sp + STACKFRAME_SZ + PT_NPC]
-
-#ifndef CONFIG_SUNOS_EMUL
- .align 4
- .globl sunos_syscall
-sunos_syscall:
- SAVE_ALL_HEAD
- rd %wim, %l3
- wr %l0, PSR_ET, %psr
- nop
- nop
- mov %i0, %l5
- call do_sunos_syscall
- add %sp, STACKFRAME_SZ, %o0
-#endif
-
- /* {net, open}bsd system calls enter here... */
- .align 4
- .globl bsd_syscall
-bsd_syscall:
- /* Direct access to user regs, must faster. */
- cmp %g1, NR_SYSCALLS
- blu,a 1f
- sll %g1, 2, %l4
-
- set sys_ni_syscall, %l7
- b bsd_is_too_hard
- nop
-
-1:
- ld [%l7 + %l4], %l7
-
- .globl bsd_is_too_hard
-bsd_is_too_hard:
- rd %wim, %l3
- SAVE_ALL
-
- wr %l0, PSR_ET, %psr
- WRITE_PAUSE
-
-2:
- mov %i0, %o0
- mov %i1, %o1
- mov %i2, %o2
- mov %i0, %l5
- mov %i3, %o3
- mov %i4, %o4
- call %l7
- mov %i5, %o5
-
- st %o0, [%sp + STACKFRAME_SZ + PT_I0]
- set PSR_C, %g2
- cmp %o0, -ERESTART_RESTARTBLOCK
- bgeu 1f
- ld [%sp + STACKFRAME_SZ + PT_PSR], %g3
-
- /* System call success, clear Carry condition code. */
- andn %g3, %g2, %g3
- clr %l6
- b 2f
- st %g3, [%sp + STACKFRAME_SZ + PT_PSR]
-
-1:
- /* System call failure, set Carry condition code.
- * Also, get abs(errno) to return to the process.
- */
- sub %g0, %o0, %o0
-#if 0 /* XXX todo XXX */
- sethi %hi(bsd_xlatb_rorl), %o3
- or %o3, %lo(bsd_xlatb_rorl), %o3
- sll %o0, 2, %o0
- ld [%o3 + %o0], %o0
-#endif
- mov 1, %l6
- st %o0, [%sp + STACKFRAME_SZ + PT_I0]
- or %g3, %g2, %g3
- st %g3, [%sp + STACKFRAME_SZ + PT_PSR]
-
- /* Advance the pc and npc over the trap instruction. */
-2:
- ld [%sp + STACKFRAME_SZ + PT_NPC], %l1 /* pc = npc */
- add %l1, 0x4, %l2 /* npc = npc+4 */
- st %l1, [%sp + STACKFRAME_SZ + PT_PC]
- b ret_trap_entry
- st %l2, [%sp + STACKFRAME_SZ + PT_NPC]
-
/* Saving and restoring the FPU state is best done from lowlevel code.
*
* void fpsave(unsigned long *fpregs, unsigned long *fsr,
+++ /dev/null
-/* errtbls.c: Error number conversion tables.
- *
- * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
- *
- * Based upon preliminary work which is:
- *
- * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
- */
-
-#include <asm/solerrno.h> /* Solaris errnos */
-
-/* Here is the table which converts between Linux error number values
- * to the equivalent under Solaris. Note that since the Linux ones
- * have been set up to match exactly those of SunOS, no translation
- * table is needed for that OS.
- */
-
-int solaris_errno[] = {
- 0,
- SOL_EPERM,
- SOL_ENOENT,
- SOL_ESRCH,
- SOL_EINTR,
- SOL_EIO,
- SOL_ENXIO,
- SOL_E2BIG,
- SOL_ENOEXEC,
- SOL_EBADF,
- SOL_ECHILD,
- SOL_EAGAIN,
- SOL_ENOMEM,
- SOL_EACCES,
- SOL_EFAULT,
- SOL_NOTBLK,
- SOL_EBUSY,
- SOL_EEXIST,
- SOL_EXDEV,
- SOL_ENODEV,
- SOL_ENOTDIR,
- SOL_EISDIR,
- SOL_EINVAL,
- SOL_ENFILE,
- SOL_EMFILE,
- SOL_ENOTTY,
- SOL_ETXTBSY,
- SOL_EFBIG,
- SOL_ENOSPC,
- SOL_ESPIPE,
- SOL_EROFS,
- SOL_EMLINK,
- SOL_EPIPE,
- SOL_EDOM,
- SOL_ERANGE,
- SOL_EWOULDBLOCK,
- SOL_EINPROGRESS,
- SOL_EALREADY,
- SOL_ENOTSOCK,
- SOL_EDESTADDRREQ,
- SOL_EMSGSIZE,
- SOL_EPROTOTYPE,
- SOL_ENOPROTOOPT,
- SOL_EPROTONOSUPPORT,
- SOL_ESOCKTNOSUPPORT,
- SOL_EOPNOTSUPP,
- SOL_EPFNOSUPPORT,
- SOL_EAFNOSUPPORT,
- SOL_EADDRINUSE,
- SOL_EADDRNOTAVAIL,
- SOL_ENETDOWN,
- SOL_ENETUNREACH,
- SOL_ENETRESET,
- SOL_ECONNABORTED,
- SOL_ECONNRESET,
- SOL_ENOBUFS,
- SOL_EISCONN,
- SOL_ENOTONN,
- SOL_ESHUTDOWN,
- SOL_ETOOMANYREFS,
- SOL_ETIMEDOUT,
- SOL_ECONNREFUSED,
- SOL_ELOOP,
- SOL_ENAMETOOLONG,
- SOL_EHOSTDOWN,
- SOL_EHOSTUNREACH,
- SOL_ENOTEMPTY,
- SOL_EPROCLIM,
- SOL_EUSERS,
- SOL_EDQUOT,
- SOL_ESTALE,
- SOL_EREMOTE,
- SOL_ENOSTR,
- SOL_ETIME,
- SOL_ENOSR,
- SOL_ENOMSG,
- SOL_EBADMSG,
- SOL_IDRM,
- SOL_EDEADLK,
- SOL_ENOLCK,
- SOL_ENONET,
- SOL_ERREMOTE,
- SOL_ENOLINK,
- SOL_EADV,
- SOL_ESRMNT,
- SOL_ECOMM,
- SOL_EPROTO,
- SOL_EMULTIHOP,
- SOL_EINVAL, /* EDOTDOT XXX??? */
- SOL_REMCHG,
- SOL_NOSYS,
- SOL_STRPIPE,
- SOL_EOVERFLOW,
- SOL_EBADFD,
- SOL_ECHRNG,
- SOL_EL2NSYNC,
- SOL_EL3HLT,
- SOL_EL3RST,
- SOL_NRNG,
- SOL_EUNATCH,
- SOL_ENOCSI,
- SOL_EL2HLT,
- SOL_EBADE,
- SOL_EBADR,
- SOL_EXFULL,
- SOL_ENOANO,
- SOL_EBADRQC,
- SOL_EBADSLT,
- SOL_EDEADLOCK,
- SOL_EBFONT,
- SOL_ELIBEXEC,
- SOL_ENODATA,
- SOL_ELIBBAD,
- SOL_ENOPKG,
- SOL_ELIBACC,
- SOL_ENOTUNIQ,
- SOL_ERESTART,
- SOL_EUCLEAN,
- SOL_ENOTNAM,
- SOL_ENAVAIL,
- SOL_EISNAM,
- SOL_EREMOTEIO,
- SOL_EILSEQ,
- SOL_ELIBMAX,
- SOL_ELIBSCN,
-};
.asciz "Sparc-Linux sun4e support does not exist\n\n"
.align 4
-#ifndef CONFIG_SUNOS_EMUL
-#undef SUNOS_SYSCALL_TRAP
-#define SUNOS_SYSCALL_TRAP SUNOS_NO_SYSCALL_TRAP
-#endif
-
/* The Sparc trap table, bootloader gives us control at _start. */
.text
.globl start, _stext, _start, __stext
t_bad74:BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
t_bad79:BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
t_bad7e:BAD_TRAP(0x7e) BAD_TRAP(0x7f)
-t_sunos:SUNOS_SYSCALL_TRAP /* SunOS System Call */
+t_bad80:BAD_TRAP(0x80) /* SunOS System Call */
t_sbkpt:BREAKPOINT_TRAP /* Software Breakpoint/KGDB */
t_divz: TRAP_ENTRY(0x82, do_hw_divzero) /* Divide by zero trap */
t_flwin:TRAP_ENTRY(0x83, do_flush_windows) /* Flush Windows Trap */
t_rchk: BAD_TRAP(0x85) /* Range Check */
t_funal:BAD_TRAP(0x86) /* Fix Unaligned Access Trap */
t_iovf: BAD_TRAP(0x87) /* Integer Overflow Trap */
-t_slowl:SOLARIS_SYSCALL_TRAP /* Slowaris System Call */
-t_netbs:NETBSD_SYSCALL_TRAP /* Net-B.S. System Call */
+t_bad88:BAD_TRAP(0x88) /* Slowaris System Call */
+t_bad89:BAD_TRAP(0x89) /* Net-B.S. System Call */
t_bad8a:BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) BAD_TRAP(0x8d) BAD_TRAP(0x8e)
t_bad8f:BAD_TRAP(0x8f)
t_linux:LINUX_SYSCALL_TRAP /* Linux System Call */
t_setcc:SETCC_TRAP /* Set Condition Codes */
t_getpsr:GETPSR_TRAP /* Get PSR Register */
t_bada3:BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
-t_slowi:INDIRECT_SOLARIS_SYSCALL(156)
+t_bada7:BAD_TRAP(0xa7)
t_bada8:BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
t_badac:BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
t_badb1:BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
BAD_TRAP(0x7e) BAD_TRAP(0x7f)
- SUNOS_SYSCALL_TRAP
+ BAD_TRAP(0x80)
BREAKPOINT_TRAP
TRAP_ENTRY(0x82, do_hw_divzero)
TRAP_ENTRY(0x83, do_flush_windows) BAD_TRAP(0x84) BAD_TRAP(0x85)
- BAD_TRAP(0x86) BAD_TRAP(0x87) SOLARIS_SYSCALL_TRAP
- NETBSD_SYSCALL_TRAP BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
+ BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88)
+ BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f)
LINUX_SYSCALL_TRAP BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94)
BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99)
BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e)
BAD_TRAP(0x9f) GETCC_TRAP SETCC_TRAP GETPSR_TRAP
BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
- INDIRECT_SOLARIS_SYSCALL(156) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
+ BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
BAD_TRAP(0x7e) BAD_TRAP(0x7f)
- SUNOS_SYSCALL_TRAP
+ BAD_TRAP(0x80)
BREAKPOINT_TRAP
TRAP_ENTRY(0x82, do_hw_divzero)
TRAP_ENTRY(0x83, do_flush_windows) BAD_TRAP(0x84) BAD_TRAP(0x85)
- BAD_TRAP(0x86) BAD_TRAP(0x87) SOLARIS_SYSCALL_TRAP
- NETBSD_SYSCALL_TRAP BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
+ BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88)
+ BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f)
LINUX_SYSCALL_TRAP BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94)
BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99)
BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e)
BAD_TRAP(0x9f) GETCC_TRAP SETCC_TRAP GETPSR_TRAP
BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
- INDIRECT_SOLARIS_SYSCALL(156) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
+ BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
BAD_TRAP(0x7e) BAD_TRAP(0x7f)
- SUNOS_SYSCALL_TRAP
+ BAD_TRAP(0x80)
BREAKPOINT_TRAP
TRAP_ENTRY(0x82, do_hw_divzero)
TRAP_ENTRY(0x83, do_flush_windows) BAD_TRAP(0x84) BAD_TRAP(0x85)
- BAD_TRAP(0x86) BAD_TRAP(0x87) SOLARIS_SYSCALL_TRAP
- NETBSD_SYSCALL_TRAP BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
+ BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88)
+ BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f)
LINUX_SYSCALL_TRAP BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94)
BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99)
BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e)
BAD_TRAP(0x9f) GETCC_TRAP SETCC_TRAP GETPSR_TRAP
BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
- INDIRECT_SOLARIS_SYSCALL(156) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
+ BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
+++ /dev/null
-/* sclow.S: Low level special syscall handling.
- * Basically these are cases where we can completely
- * handle the system call without saving any state
- * because we know that the process will not sleep.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#include <asm/ptrace.h>
-#include <asm/asm-offsets.h>
-#include <asm/errno.h>
-#include <asm/winmacro.h>
-#include <asm/thread_info.h>
-#include <asm/psr.h>
-#include <asm/page.h>
-
-#define CC_AND_RETT \
- set PSR_C, %l4; \
- andn %l0, %l4, %l4; \
- wr %l4, 0x0, %psr; \
- nop; nop; nop; \
- jmp %l2; \
- rett %l2 + 4;
-
-#define SC_AND_RETT \
- set PSR_C, %l4; \
- or %l0, %l4, %l4; \
- wr %l4, 0x0, %psr; \
- nop; nop; nop; \
- jmp %l2; \
- rett %l2 + 4;
-
-#define LABEL(func) func##_low
-
- .globl LABEL(sunosnop)
-LABEL(sunosnop):
- CC_AND_RETT
-
-#if (ASIZ_task_uid == 2 && ASIZ_task_euid == 2)
- .globl LABEL(sunosgetuid)
-LABEL(sunosgetuid):
- LOAD_CURRENT(l4, l5)
- ld [%l4 + TI_TASK], %l4
- lduh [%l4 + AOFF_task_uid], %i0
- lduh [%l4 + AOFF_task_euid], %i1
- CC_AND_RETT
-#endif
-
-#if (ASIZ_task_gid == 2 && ASIZ_task_egid == 2)
- .globl LABEL(sunosgetgid)
-LABEL(sunosgetgid):
- LOAD_CURRENT(l4, l5)
- ld [%l4 + TI_TASK], %l4
- lduh [%l4 + AOFF_task_gid], %i0
- lduh [%l4 + AOFF_task_egid], %i1
- CC_AND_RETT
-#endif
-
- .globl LABEL(sunosmctl)
-LABEL(sunosmctl):
- mov 0, %i0
- CC_AND_RETT
-
- .globl LABEL(sunosgdtsize)
-LABEL(sunosgdtsize):
- mov 256, %i0
- CC_AND_RETT
-
- .globl LABEL(getpagesize)
-LABEL(getpagesize):
- set PAGE_SIZE, %i0
- CC_AND_RETT
-
- /* XXX sys_nice() XXX */
- /* XXX sys_setpriority() XXX */
- /* XXX sys_getpriority() XXX */
- /* XXX sys_setregid() XXX */
- /* XXX sys_setgid() XXX */
- /* XXX sys_setreuid() XXX */
- /* XXX sys_setuid() XXX */
- /* XXX sys_setfsuid() XXX */
- /* XXX sys_setfsgid() XXX */
- /* XXX sys_setpgid() XXX */
- /* XXX sys_getpgid() XXX */
- /* XXX sys_setsid() XXX */
- /* XXX sys_getsid() XXX */
#include <asm/uaccess.h>
#include <asm/ptrace.h>
-#include <asm/svr4.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/cacheflush.h> /* flush_sig_insns */
break;
case SIGSYS:
if (info->si_code == (__SI_FAULT|0x100)) {
- /* See sys_sunos.c */
sig_code = info->si_trapno;
break;
}
force_sigsegv(signo, current);
}
-/* Setup a Solaris stack frame */
-static inline void
-setup_svr4_frame(struct sigaction *sa, unsigned long pc, unsigned long npc,
- struct pt_regs *regs, int signr, sigset_t *oldset)
-{
- svr4_signal_frame_t __user *sfp;
- svr4_gregset_t __user *gr;
- svr4_siginfo_t __user *si;
- svr4_mcontext_t __user *mc;
- svr4_gwindows_t __user *gw;
- svr4_ucontext_t __user *uc;
- svr4_sigset_t setv;
- struct thread_info *tp = current_thread_info();
- int window = 0, err;
-
- synchronize_user_stack();
- sfp = (svr4_signal_frame_t __user *)
- get_sigframe(sa, regs, SVR4_SF_ALIGNED + sizeof(struct reg_window));
-
- if (invalid_frame_pointer(sfp, sizeof(*sfp)))
- goto sigill_and_return;
-
- /* Start with a clean frame pointer and fill it */
- err = __clear_user(sfp, sizeof(*sfp));
-
- /* Setup convenience variables */
- si = &sfp->si;
- uc = &sfp->uc;
- gw = &sfp->gw;
- mc = &uc->mcontext;
- gr = &mc->greg;
-
- /* FIXME: where am I supposed to put this?
- * sc->sigc_onstack = old_status;
- * anyways, it does not look like it is used for anything at all.
- */
- setv.sigbits[0] = oldset->sig[0];
- setv.sigbits[1] = oldset->sig[1];
- if (_NSIG_WORDS >= 4) {
- setv.sigbits[2] = oldset->sig[2];
- setv.sigbits[3] = oldset->sig[3];
- err |= __copy_to_user(&uc->sigmask, &setv, sizeof(svr4_sigset_t));
- } else
- err |= __copy_to_user(&uc->sigmask, &setv,
- 2 * sizeof(unsigned int));
-
- /* Store registers */
- err |= __put_user(regs->pc, &((*gr)[SVR4_PC]));
- err |= __put_user(regs->npc, &((*gr)[SVR4_NPC]));
- err |= __put_user(regs->psr, &((*gr)[SVR4_PSR]));
- err |= __put_user(regs->y, &((*gr)[SVR4_Y]));
-
- /* Copy g[1..7] and o[0..7] registers */
- err |= __copy_to_user(&(*gr)[SVR4_G1], ®s->u_regs[UREG_G1],
- sizeof(long) * 7);
- err |= __copy_to_user(&(*gr)[SVR4_O0], ®s->u_regs[UREG_I0],
- sizeof(long) * 8);
-
- /* Setup sigaltstack */
- err |= __put_user(current->sas_ss_sp, &uc->stack.sp);
- err |= __put_user(sas_ss_flags(regs->u_regs[UREG_FP]), &uc->stack.flags);
- err |= __put_user(current->sas_ss_size, &uc->stack.size);
-
- /* Save the currently window file: */
-
- /* 1. Link sfp->uc->gwins to our windows */
- err |= __put_user(gw, &mc->gwin);
-
- /* 2. Number of windows to restore at setcontext(): */
- err |= __put_user(tp->w_saved, &gw->count);
-
- /* 3. Save each valid window
- * Currently, it makes a copy of the windows from the kernel copy.
- * David's code for SunOS, makes the copy but keeps the pointer to
- * the kernel. My version makes the pointer point to a userland
- * copy of those. Mhm, I wonder if I shouldn't just ignore those
- * on setcontext and use those that are on the kernel, the signal
- * handler should not be modyfing those, mhm.
- *
- * These windows are just used in case synchronize_user_stack failed
- * to flush the user windows.
- */
- for (window = 0; window < tp->w_saved; window++) {
- err |= __put_user((int __user *) &(gw->win[window]), &gw->winptr[window]);
- err |= __copy_to_user(&gw->win[window],
- &tp->reg_window[window],
- sizeof(svr4_rwindow_t));
- err |= __put_user(0, gw->winptr[window]);
- }
-
- /* 4. We just pay attention to the gw->count field on setcontext */
- tp->w_saved = 0; /* So process is allowed to execute. */
-
- /* Setup the signal information. Solaris expects a bunch of
- * information to be passed to the signal handler, we don't provide
- * that much currently, should use siginfo.
- */
- err |= __put_user(signr, &si->siginfo.signo);
- err |= __put_user(SVR4_SINOINFO, &si->siginfo.code);
- if (err)
- goto sigsegv;
-
- regs->u_regs[UREG_FP] = (unsigned long) sfp;
- regs->pc = (unsigned long) sa->sa_handler;
- regs->npc = (regs->pc + 4);
-
- /* Arguments passed to signal handler */
- if (regs->u_regs[14]){
- struct reg_window __user *rw = (struct reg_window __user *)
- regs->u_regs[14];
-
- err |= __put_user(signr, &rw->ins[0]);
- err |= __put_user(si, &rw->ins[1]);
- err |= __put_user(uc, &rw->ins[2]);
- err |= __put_user(sfp, &rw->ins[6]); /* frame pointer */
- if (err)
- goto sigsegv;
-
- regs->u_regs[UREG_I0] = signr;
- regs->u_regs[UREG_I1] = (unsigned long) si;
- regs->u_regs[UREG_I2] = (unsigned long) uc;
- }
- return;
-
-sigill_and_return:
- do_exit(SIGILL);
-sigsegv:
- force_sigsegv(signr, current);
-}
-
-asmlinkage int svr4_getcontext(svr4_ucontext_t __user *uc, struct pt_regs *regs)
-{
- svr4_gregset_t __user *gr;
- svr4_mcontext_t __user *mc;
- svr4_sigset_t setv;
- int err = 0;
-
- synchronize_user_stack();
-
- if (current_thread_info()->w_saved)
- return -EFAULT;
-
- err = clear_user(uc, sizeof(*uc));
- if (err)
- return -EFAULT;
-
- /* Setup convenience variables */
- mc = &uc->mcontext;
- gr = &mc->greg;
-
- setv.sigbits[0] = current->blocked.sig[0];
- setv.sigbits[1] = current->blocked.sig[1];
- if (_NSIG_WORDS >= 4) {
- setv.sigbits[2] = current->blocked.sig[2];
- setv.sigbits[3] = current->blocked.sig[3];
- err |= __copy_to_user(&uc->sigmask, &setv, sizeof(svr4_sigset_t));
- } else
- err |= __copy_to_user(&uc->sigmask, &setv,
- 2 * sizeof(unsigned int));
-
- /* Store registers */
- err |= __put_user(regs->pc, &uc->mcontext.greg[SVR4_PC]);
- err |= __put_user(regs->npc, &uc->mcontext.greg[SVR4_NPC]);
- err |= __put_user(regs->psr, &uc->mcontext.greg[SVR4_PSR]);
- err |= __put_user(regs->y, &uc->mcontext.greg[SVR4_Y]);
-
- /* Copy g[1..7] and o[0..7] registers */
- err |= __copy_to_user(&(*gr)[SVR4_G1], ®s->u_regs[UREG_G1],
- sizeof(uint) * 7);
- err |= __copy_to_user(&(*gr)[SVR4_O0], ®s->u_regs[UREG_I0],
- sizeof(uint) * 8);
-
- /* Setup sigaltstack */
- err |= __put_user(current->sas_ss_sp, &uc->stack.sp);
- err |= __put_user(sas_ss_flags(regs->u_regs[UREG_FP]), &uc->stack.flags);
- err |= __put_user(current->sas_ss_size, &uc->stack.size);
-
- /* The register file is not saved
- * we have already stuffed all of it with sync_user_stack
- */
- return (err ? -EFAULT : 0);
-}
-
-/* Set the context for a svr4 application, this is Solaris way to sigreturn */
-asmlinkage int svr4_setcontext(svr4_ucontext_t __user *c, struct pt_regs *regs)
-{
- svr4_gregset_t __user *gr;
- unsigned long pc, npc, psr;
- mm_segment_t old_fs;
- sigset_t set;
- svr4_sigset_t setv;
- int err;
- stack_t st;
-
- /* Fixme: restore windows, or is this already taken care of in
- * svr4_setup_frame when sync_user_windows is done?
- */
- flush_user_windows();
-
- if (current_thread_info()->w_saved)
- goto sigsegv_and_return;
-
- if (((unsigned long) c) & 3)
- goto sigsegv_and_return;
-
- if (!__access_ok((unsigned long)c, sizeof(*c)))
- goto sigsegv_and_return;
-
- /* Check for valid PC and nPC */
- gr = &c->mcontext.greg;
- err = __get_user(pc, &((*gr)[SVR4_PC]));
- err |= __get_user(npc, &((*gr)[SVR4_NPC]));
-
- if ((pc | npc) & 3)
- goto sigsegv_and_return;
-
- /* Retrieve information from passed ucontext */
- /* note that nPC is ored a 1, this is used to inform entry.S */
- /* that we don't want it to mess with our PC and nPC */
-
- /* This is pretty much atomic, no amount locking would prevent
- * the races which exist anyways.
- */
- err |= __copy_from_user(&setv, &c->sigmask, sizeof(svr4_sigset_t));
-
- err |= __get_user(st.ss_sp, &c->stack.sp);
- err |= __get_user(st.ss_flags, &c->stack.flags);
- err |= __get_user(st.ss_size, &c->stack.size);
-
- if (err)
- goto sigsegv_and_return;
-
- /* It is more difficult to avoid calling this function than to
- call it and ignore errors. */
- old_fs = get_fs();
- set_fs(KERNEL_DS);
- do_sigaltstack((const stack_t __user *) &st, NULL,
- regs->u_regs[UREG_I6]);
- set_fs(old_fs);
-
- set.sig[0] = setv.sigbits[0];
- set.sig[1] = setv.sigbits[1];
- if (_NSIG_WORDS >= 4) {
- set.sig[2] = setv.sigbits[2];
- set.sig[3] = setv.sigbits[3];
- }
- sigdelsetmask(&set, ~_BLOCKABLE);
- spin_lock_irq(¤t->sighand->siglock);
- current->blocked = set;
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- regs->pc = pc;
- regs->npc = npc | 1;
- err |= __get_user(regs->y, &((*gr)[SVR4_Y]));
- err |= __get_user(psr, &((*gr)[SVR4_PSR]));
- regs->psr &= ~(PSR_ICC);
- regs->psr |= (psr & PSR_ICC);
-
- /* Restore g[1..7] and o[0..7] registers */
- err |= __copy_from_user(®s->u_regs[UREG_G1], &(*gr)[SVR4_G1],
- sizeof(long) * 7);
- err |= __copy_from_user(®s->u_regs[UREG_I0], &(*gr)[SVR4_O0],
- sizeof(long) * 8);
- return (err ? -EFAULT : 0);
-
-sigsegv_and_return:
- force_sig(SIGSEGV, current);
- return -EFAULT;
-}
-
static inline void
handle_signal(unsigned long signr, struct k_sigaction *ka,
- siginfo_t *info, sigset_t *oldset, struct pt_regs *regs,
- int svr4_signal)
+ siginfo_t *info, sigset_t *oldset, struct pt_regs *regs)
{
- if (svr4_signal)
- setup_svr4_frame(&ka->sa, regs->pc, regs->npc, regs, signr, oldset);
- else {
- if (ka->sa.sa_flags & SA_SIGINFO)
- new_setup_rt_frame(ka, regs, signr, oldset, info);
- else if (current->thread.new_signal)
- new_setup_frame(ka, regs, signr, oldset);
- else
- setup_frame(&ka->sa, regs, signr, oldset, info);
- }
+ if (ka->sa.sa_flags & SA_SIGINFO)
+ new_setup_rt_frame(ka, regs, signr, oldset, info);
+ else if (current->thread.new_signal)
+ new_setup_frame(ka, regs, signr, oldset);
+ else
+ setup_frame(&ka->sa, regs, signr, oldset, info);
+
spin_lock_irq(¤t->sighand->siglock);
sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
if (!(ka->sa.sa_flags & SA_NOMASK))
int signr;
sigset_t *oldset;
- /*
- * XXX Disable svr4 signal handling until solaris emulation works.
- * It is buggy - Anton
- */
-#define SVR4_SIGNAL_BROKEN 1
-#ifdef SVR4_SIGNAL_BROKEN
- int svr4_signal = 0;
-#else
- int svr4_signal = current->personality == PER_SVR4;
-#endif
-
cookie.restart_syscall = restart_syscall;
cookie.orig_i0 = orig_i0;
if (signr > 0) {
if (cookie.restart_syscall)
syscall_restart(cookie.orig_i0, regs, &ka.sa);
- handle_signal(signr, &ka, &info, oldset,
- regs, svr4_signal);
+ handle_signal(signr, &ka, &info, oldset, regs);
+
/* a signal was successfully delivered; the saved
* sigmask will have been stored in the signal frame,
* and will be restored by sigreturn, so we can simply
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/idprom.h>
-#include <asm/svr4.h>
#include <asm/head.h>
#include <asm/smp.h>
#include <asm/mostek.h>
#include <asm/ptrace.h>
-#include <asm/user.h>
#include <asm/uaccess.h>
#include <asm/checksum.h>
#ifdef CONFIG_SBUS
short revents;
};
-extern int svr4_getcontext (svr4_ucontext_t *, struct pt_regs *);
-extern int svr4_setcontext (svr4_ucontext_t *, struct pt_regs *);
extern void (*__copy_1page)(void *, const void *);
extern void __memmove(void *, const void *, __kernel_size_t);
extern void (*bzero_1page)(void *);
EXPORT_SYMBOL(kunmap_atomic);
#endif
-/* Solaris/SunOS binary compatibility */
-EXPORT_SYMBOL(svr4_setcontext);
-EXPORT_SYMBOL(svr4_getcontext);
-
/* prom symbols */
EXPORT_SYMBOL(idprom);
EXPORT_SYMBOL(prom_root_node);
+++ /dev/null
-/* $Id: sunos_asm.S,v 1.15 2000/01/11 17:33:21 jj Exp $
- * sunos_asm.S: SunOS system calls which must have a low-level
- * entry point to operate correctly.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- *
- * Based upon preliminary work which is:
- *
- * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
- */
-
-#include <asm/ptrace.h>
-
- .text
- .align 4
-
- /* When calling ret_sys_call, %o0 should contain the same
- * value as in [%sp + STACKFRAME_SZ + PT_I0] */
-
- /* SunOS getpid() returns pid in %o0 and ppid in %o1 */
- .globl sunos_getpid
-sunos_getpid:
- call sys_getppid
- nop
-
- call sys_getpid
- st %o0, [%sp + STACKFRAME_SZ + PT_I1]
-
- b ret_sys_call
- st %o0, [%sp + STACKFRAME_SZ + PT_I0]
-
- /* SunOS getuid() returns uid in %o0 and euid in %o1 */
- .globl sunos_getuid
-sunos_getuid:
- call sys_geteuid16
- nop
-
- call sys_getuid16
- st %o0, [%sp + STACKFRAME_SZ + PT_I1]
-
- b ret_sys_call
- st %o0, [%sp + STACKFRAME_SZ + PT_I0]
-
- /* SunOS getgid() returns gid in %o0 and egid in %o1 */
- .globl sunos_getgid
-sunos_getgid:
- call sys_getegid16
- nop
-
- call sys_getgid16
- st %o0, [%sp + STACKFRAME_SZ + PT_I1]
-
- b ret_sys_call
- st %o0, [%sp + STACKFRAME_SZ + PT_I0]
-
- /* SunOS's execv() call only specifies the argv argument, the
- * environment settings are the same as the calling processes.
- */
- .globl sunos_execv
-sunos_execv:
- st %g0, [%sp + STACKFRAME_SZ + PT_I2]
-
- call sparc_execve
- add %sp, STACKFRAME_SZ, %o0
-
- b ret_sys_call
- ld [%sp + STACKFRAME_SZ + PT_I0], %o0
+++ /dev/null
-/* $Id: sunos_ioctl.c,v 1.34 2000/09/03 14:10:56 anton Exp $
- * sunos_ioctl.c: The Linux Operating system: SunOS ioctl compatibility.
- *
- * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#include <asm/uaccess.h>
-
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/termios.h>
-#include <linux/tty.h>
-#include <linux/ioctl.h>
-#include <linux/route.h>
-#include <linux/sockios.h>
-#include <linux/if.h>
-#include <linux/netdevice.h>
-#include <linux/if_arp.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/syscalls.h>
-#include <linux/file.h>
-
-#if 0
-extern char sunkbd_type;
-extern char sunkbd_layout;
-#endif
-
-/* NR_OPEN is now larger and dynamic in recent kernels. */
-#define SUNOS_NR_OPEN 256
-
-asmlinkage int sunos_ioctl (int fd, unsigned long cmd, unsigned long arg)
-{
- int ret = -EBADF;
-
- if (fd >= SUNOS_NR_OPEN || !fcheck(fd))
- goto out;
-
- /* First handle an easy compat. case for tty ldisc. */
- if (cmd == TIOCSETD) {
- int __user *p;
- int ntty = N_TTY, tmp;
- mm_segment_t oldfs;
-
- p = (int __user *) arg;
- ret = -EFAULT;
- if (get_user(tmp, p))
- goto out;
- if (tmp == 2) {
- oldfs = get_fs();
- set_fs(KERNEL_DS);
- ret = sys_ioctl(fd, cmd, (unsigned long) &ntty);
- set_fs(oldfs);
- ret = (ret == -EINVAL ? -EOPNOTSUPP : ret);
- goto out;
- }
- }
-
- /* Binary compatibility is good American knowhow fuckin' up. */
- if (cmd == TIOCNOTTY) {
- ret = sys_setsid();
- goto out;
- }
-
- /* SunOS networking ioctls. */
- switch (cmd) {
- case _IOW('r', 10, struct rtentry):
- ret = sys_ioctl(fd, SIOCADDRT, arg);
- goto out;
- case _IOW('r', 11, struct rtentry):
- ret = sys_ioctl(fd, SIOCDELRT, arg);
- goto out;
- case _IOW('i', 12, struct ifreq):
- ret = sys_ioctl(fd, SIOCSIFADDR, arg);
- goto out;
- case _IOWR('i', 13, struct ifreq):
- ret = sys_ioctl(fd, SIOCGIFADDR, arg);
- goto out;
- case _IOW('i', 14, struct ifreq):
- ret = sys_ioctl(fd, SIOCSIFDSTADDR, arg);
- goto out;
- case _IOWR('i', 15, struct ifreq):
- ret = sys_ioctl(fd, SIOCGIFDSTADDR, arg);
- goto out;
- case _IOW('i', 16, struct ifreq):
- ret = sys_ioctl(fd, SIOCSIFFLAGS, arg);
- goto out;
- case _IOWR('i', 17, struct ifreq):
- ret = sys_ioctl(fd, SIOCGIFFLAGS, arg);
- goto out;
- case _IOW('i', 18, struct ifreq):
- ret = sys_ioctl(fd, SIOCSIFMEM, arg);
- goto out;
- case _IOWR('i', 19, struct ifreq):
- ret = sys_ioctl(fd, SIOCGIFMEM, arg);
- goto out;
- case _IOWR('i', 20, struct ifconf):
- ret = sys_ioctl(fd, SIOCGIFCONF, arg);
- goto out;
- case _IOW('i', 21, struct ifreq): /* SIOCSIFMTU */
- ret = sys_ioctl(fd, SIOCSIFMTU, arg);
- goto out;
- case _IOWR('i', 22, struct ifreq): /* SIOCGIFMTU */
- ret = sys_ioctl(fd, SIOCGIFMTU, arg);
- goto out;
-
- case _IOWR('i', 23, struct ifreq):
- ret = sys_ioctl(fd, SIOCGIFBRDADDR, arg);
- goto out;
- case _IOW('i', 24, struct ifreq):
- ret = sys_ioctl(fd, SIOCSIFBRDADDR, arg);
- goto out;
- case _IOWR('i', 25, struct ifreq):
- ret = sys_ioctl(fd, SIOCGIFNETMASK, arg);
- goto out;
- case _IOW('i', 26, struct ifreq):
- ret = sys_ioctl(fd, SIOCSIFNETMASK, arg);
- goto out;
- case _IOWR('i', 27, struct ifreq):
- ret = sys_ioctl(fd, SIOCGIFMETRIC, arg);
- goto out;
- case _IOW('i', 28, struct ifreq):
- ret = sys_ioctl(fd, SIOCSIFMETRIC, arg);
- goto out;
-
- case _IOW('i', 30, struct arpreq):
- ret = sys_ioctl(fd, SIOCSARP, arg);
- goto out;
- case _IOWR('i', 31, struct arpreq):
- ret = sys_ioctl(fd, SIOCGARP, arg);
- goto out;
- case _IOW('i', 32, struct arpreq):
- ret = sys_ioctl(fd, SIOCDARP, arg);
- goto out;
-
- case _IOW('i', 40, struct ifreq): /* SIOCUPPER */
- case _IOW('i', 41, struct ifreq): /* SIOCLOWER */
- case _IOW('i', 44, struct ifreq): /* SIOCSETSYNC */
- case _IOW('i', 45, struct ifreq): /* SIOCGETSYNC */
- case _IOW('i', 46, struct ifreq): /* SIOCSSDSTATS */
- case _IOW('i', 47, struct ifreq): /* SIOCSSESTATS */
- case _IOW('i', 48, struct ifreq): /* SIOCSPROMISC */
- ret = -EOPNOTSUPP;
- goto out;
-
- case _IOW('i', 49, struct ifreq):
- ret = sys_ioctl(fd, SIOCADDMULTI, arg);
- goto out;
- case _IOW('i', 50, struct ifreq):
- ret = sys_ioctl(fd, SIOCDELMULTI, arg);
- goto out;
-
- /* FDDI interface ioctls, unsupported. */
-
- case _IOW('i', 51, struct ifreq): /* SIOCFDRESET */
- case _IOW('i', 52, struct ifreq): /* SIOCFDSLEEP */
- case _IOW('i', 53, struct ifreq): /* SIOCSTRTFMWAR */
- case _IOW('i', 54, struct ifreq): /* SIOCLDNSTRTFW */
- case _IOW('i', 55, struct ifreq): /* SIOCGETFDSTAT */
- case _IOW('i', 56, struct ifreq): /* SIOCFDNMIINT */
- case _IOW('i', 57, struct ifreq): /* SIOCFDEXUSER */
- case _IOW('i', 58, struct ifreq): /* SIOCFDGNETMAP */
- case _IOW('i', 59, struct ifreq): /* SIOCFDGIOCTL */
- printk("FDDI ioctl, returning EOPNOTSUPP\n");
- ret = -EOPNOTSUPP;
- goto out;
-
- case _IOW('t', 125, int):
- /* More stupid tty sunos ioctls, just
- * say it worked.
- */
- ret = 0;
- goto out;
- /* Non posix grp */
- case _IOW('t', 118, int): {
- int oldval, newval, __user *ptr;
-
- cmd = TIOCSPGRP;
- ptr = (int __user *) arg;
- ret = -EFAULT;
- if (get_user(oldval, ptr))
- goto out;
- ret = sys_ioctl(fd, cmd, arg);
- __get_user(newval, ptr);
- if (newval == -1) {
- __put_user(oldval, ptr);
- ret = -EIO;
- }
- if (ret == -ENOTTY)
- ret = -EIO;
- goto out;
- }
-
- case _IOR('t', 119, int): {
- int oldval, newval, __user *ptr;
-
- cmd = TIOCGPGRP;
- ptr = (int __user *) arg;
- ret = -EFAULT;
- if (get_user(oldval, ptr))
- goto out;
- ret = sys_ioctl(fd, cmd, arg);
- __get_user(newval, ptr);
- if (newval == -1) {
- __put_user(oldval, ptr);
- ret = -EIO;
- }
- if (ret == -ENOTTY)
- ret = -EIO;
- goto out;
- }
- }
-
-#if 0
- if ((cmd & 0xff00) == ('k' << 8)) {
- printk ("[[KBIO: %8.8x\n", (unsigned int) cmd);
- }
-#endif
-
- ret = sys_ioctl(fd, cmd, arg);
- /* so stupid... */
- ret = (ret == -EINVAL ? -EOPNOTSUPP : ret);
-out:
- return ret;
-}
-
-
+++ /dev/null
-/*
- * linux/arch/sparc/kernel/sys_solaris.c
- *
- * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
- */
-
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/errno.h>
-#include <linux/personality.h>
-#include <linux/ptrace.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/module.h>
-
-asmlinkage int
-do_solaris_syscall (struct pt_regs *regs)
-{
- static int cnt = 0;
- if (++cnt < 10) printk ("No solaris handler\n");
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-#ifndef CONFIG_SUNOS_EMUL
-asmlinkage int
-do_sunos_syscall (struct pt_regs *regs)
-{
- static int cnt = 0;
- if (++cnt < 10) printk ("SunOS binary emulation not compiled in\n");
- force_sig (SIGSEGV, current);
- return 0;
-}
-#endif
+++ /dev/null
-/* $Id: sys_sunos.c,v 1.137 2002/02/08 03:57:14 davem Exp $
- * sys_sunos.c: SunOS specific syscall compatibility support.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
- *
- * Based upon preliminary work which is:
- *
- * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/resource.h>
-#include <linux/ipc.h>
-#include <linux/shm.h>
-#include <linux/msg.h>
-#include <linux/sem.h>
-#include <linux/signal.h>
-#include <linux/uio.h>
-#include <linux/utsname.h>
-#include <linux/major.h>
-#include <linux/stat.h>
-#include <linux/slab.h>
-#include <linux/pagemap.h>
-#include <linux/capability.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-#include <linux/syscalls.h>
-
-#include <net/sock.h>
-
-#include <asm/uaccess.h>
-#ifndef KERNEL_DS
-#include <linux/segment.h>
-#endif
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/pconf.h>
-#include <asm/idprom.h> /* for gethostid() */
-#include <asm/unistd.h>
-#include <asm/system.h>
-
-/* For the nfs mount emulation */
-#include <linux/socket.h>
-#include <linux/in.h>
-#include <linux/nfs.h>
-#include <linux/nfs2.h>
-#include <linux/nfs_mount.h>
-
-/* for sunos_select */
-#include <linux/time.h>
-#include <linux/personality.h>
-
-/* NR_OPEN is now larger and dynamic in recent kernels. */
-#define SUNOS_NR_OPEN 256
-
-/* We use the SunOS mmap() semantics. */
-asmlinkage unsigned long sunos_mmap(unsigned long addr, unsigned long len,
- unsigned long prot, unsigned long flags,
- unsigned long fd, unsigned long off)
-{
- struct file * file = NULL;
- unsigned long retval, ret_type;
-
- if (flags & MAP_NORESERVE) {
- static int cnt;
- if (cnt++ < 10)
- printk("%s: unimplemented SunOS MAP_NORESERVE mmap() flag\n",
- current->comm);
- flags &= ~MAP_NORESERVE;
- }
- retval = -EBADF;
- if (!(flags & MAP_ANONYMOUS)) {
- if (fd >= SUNOS_NR_OPEN)
- goto out;
- file = fget(fd);
- if (!file)
- goto out;
- }
-
- retval = -EINVAL;
- /* If this is ld.so or a shared library doing an mmap
- * of /dev/zero, transform it into an anonymous mapping.
- * SunOS is so stupid some times... hmph!
- */
- if (file) {
- if (imajor(file->f_path.dentry->d_inode) == MEM_MAJOR &&
- iminor(file->f_path.dentry->d_inode) == 5) {
- flags |= MAP_ANONYMOUS;
- fput(file);
- file = NULL;
- }
- }
- ret_type = flags & _MAP_NEW;
- flags &= ~_MAP_NEW;
-
- if (!(flags & MAP_FIXED))
- addr = 0;
- else {
- if (ARCH_SUN4C_SUN4 &&
- (len > 0x20000000 ||
- ((flags & MAP_FIXED) &&
- addr < 0xe0000000 && addr + len > 0x20000000)))
- goto out_putf;
-
- /* See asm-sparc/uaccess.h */
- if (len > TASK_SIZE - PAGE_SIZE ||
- addr + len > TASK_SIZE - PAGE_SIZE)
- goto out_putf;
- }
-
- flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
- down_write(¤t->mm->mmap_sem);
- retval = do_mmap(file, addr, len, prot, flags, off);
- up_write(¤t->mm->mmap_sem);
- if (!ret_type)
- retval = ((retval < PAGE_OFFSET) ? 0 : retval);
-
-out_putf:
- if (file)
- fput(file);
-out:
- return retval;
-}
-
-/* lmbench calls this, just say "yeah, ok" */
-asmlinkage int sunos_mctl(unsigned long addr, unsigned long len, int function, char *arg)
-{
- return 0;
-}
-
-/* SunOS is completely broken... it returns 0 on success, otherwise
- * ENOMEM. For sys_sbrk() it wants the old brk value as a return
- * on success and ENOMEM as before on failure.
- */
-asmlinkage int sunos_brk(unsigned long brk)
-{
- int freepages, retval = -ENOMEM;
- unsigned long rlim;
- unsigned long newbrk, oldbrk;
-
- down_write(¤t->mm->mmap_sem);
- if (ARCH_SUN4C_SUN4) {
- if (brk >= 0x20000000 && brk < 0xe0000000) {
- goto out;
- }
- }
-
- if (brk < current->mm->end_code)
- goto out;
-
- newbrk = PAGE_ALIGN(brk);
- oldbrk = PAGE_ALIGN(current->mm->brk);
- retval = 0;
- if (oldbrk == newbrk) {
- current->mm->brk = brk;
- goto out;
- }
-
- /*
- * Always allow shrinking brk
- */
- if (brk <= current->mm->brk) {
- current->mm->brk = brk;
- do_munmap(current->mm, newbrk, oldbrk-newbrk);
- goto out;
- }
- /*
- * Check against rlimit and stack..
- */
- retval = -ENOMEM;
- rlim = current->signal->rlim[RLIMIT_DATA].rlim_cur;
- if (rlim >= RLIM_INFINITY)
- rlim = ~0;
- if (brk - current->mm->end_code > rlim)
- goto out;
-
- /*
- * Check against existing mmap mappings.
- */
- if (find_vma_intersection(current->mm, oldbrk, newbrk+PAGE_SIZE))
- goto out;
-
- /*
- * stupid algorithm to decide if we have enough memory: while
- * simple, it hopefully works in most obvious cases.. Easy to
- * fool it, but this should catch most mistakes.
- */
- freepages = global_page_state(NR_FILE_PAGES);
- freepages >>= 1;
- freepages += nr_free_pages();
- freepages += nr_swap_pages;
- freepages -= num_physpages >> 4;
- freepages -= (newbrk-oldbrk) >> PAGE_SHIFT;
- if (freepages < 0)
- goto out;
- /*
- * Ok, we have probably got enough memory - let it rip.
- */
- current->mm->brk = brk;
- do_brk(oldbrk, newbrk-oldbrk);
- retval = 0;
-out:
- up_write(¤t->mm->mmap_sem);
- return retval;
-}
-
-asmlinkage unsigned long sunos_sbrk(int increment)
-{
- int error;
- unsigned long oldbrk;
-
- /* This should do it hopefully... */
- lock_kernel();
- oldbrk = current->mm->brk;
- error = sunos_brk(((int) current->mm->brk) + increment);
- if (!error)
- error = oldbrk;
- unlock_kernel();
- return error;
-}
-
-/* XXX Completely undocumented, and completely magic...
- * XXX I believe it is to increase the size of the stack by
- * XXX argument 'increment' and return the new end of stack
- * XXX area. Wheee...
- */
-asmlinkage unsigned long sunos_sstk(int increment)
-{
- lock_kernel();
- printk("%s: Call to sunos_sstk(increment<%d>) is unsupported\n",
- current->comm, increment);
- unlock_kernel();
- return -1;
-}
-
-/* Give hints to the kernel as to what paging strategy to use...
- * Completely bogus, don't remind me.
- */
-#define VA_NORMAL 0 /* Normal vm usage expected */
-#define VA_ABNORMAL 1 /* Abnormal/random vm usage probable */
-#define VA_SEQUENTIAL 2 /* Accesses will be of a sequential nature */
-#define VA_INVALIDATE 3 /* Page table entries should be flushed ??? */
-static char *vstrings[] = {
- "VA_NORMAL",
- "VA_ABNORMAL",
- "VA_SEQUENTIAL",
- "VA_INVALIDATE",
-};
-
-asmlinkage void sunos_vadvise(unsigned long strategy)
-{
- /* I wanna see who uses this... */
- lock_kernel();
- printk("%s: Advises us to use %s paging strategy\n",
- current->comm,
- strategy <= 3 ? vstrings[strategy] : "BOGUS");
- unlock_kernel();
-}
-
-/* This just wants the soft limit (ie. rlim_cur element) of the RLIMIT_NOFILE
- * resource limit and is for backwards compatibility with older sunos
- * revs.
- */
-asmlinkage long sunos_getdtablesize(void)
-{
- return SUNOS_NR_OPEN;
-}
-
-#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
-
-asmlinkage unsigned long sunos_sigblock(unsigned long blk_mask)
-{
- unsigned long old;
-
- spin_lock_irq(¤t->sighand->siglock);
- old = current->blocked.sig[0];
- current->blocked.sig[0] |= (blk_mask & _BLOCKABLE);
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- return old;
-}
-
-asmlinkage unsigned long sunos_sigsetmask(unsigned long newmask)
-{
- unsigned long retval;
-
- spin_lock_irq(¤t->sighand->siglock);
- retval = current->blocked.sig[0];
- current->blocked.sig[0] = (newmask & _BLOCKABLE);
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- return retval;
-}
-
-/* SunOS getdents is very similar to the newer Linux (iBCS2 compliant) */
-/* getdents system call, the format of the structure just has a different */
-/* layout (d_off+d_ino instead of d_ino+d_off) */
-struct sunos_dirent {
- long d_off;
- unsigned long d_ino;
- unsigned short d_reclen;
- unsigned short d_namlen;
- char d_name[1];
-};
-
-struct sunos_dirent_callback {
- struct sunos_dirent __user *curr;
- struct sunos_dirent __user *previous;
- int count;
- int error;
-};
-
-#define NAME_OFFSET(de) ((int) ((de)->d_name - (char __user *) (de)))
-#define ROUND_UP(x) (((x)+sizeof(long)-1) & ~(sizeof(long)-1))
-
-static int sunos_filldir(void * __buf, const char * name, int namlen,
- loff_t offset, u64 ino, unsigned int d_type)
-{
- struct sunos_dirent __user *dirent;
- struct sunos_dirent_callback * buf = __buf;
- unsigned long d_ino;
- int reclen = ROUND_UP(NAME_OFFSET(dirent) + namlen + 1);
-
- buf->error = -EINVAL; /* only used if we fail.. */
- if (reclen > buf->count)
- return -EINVAL;
- d_ino = ino;
- if (sizeof(d_ino) < sizeof(ino) && d_ino != ino)
- return -EOVERFLOW;
- dirent = buf->previous;
- if (dirent)
- put_user(offset, &dirent->d_off);
- dirent = buf->curr;
- buf->previous = dirent;
- put_user(d_ino, &dirent->d_ino);
- put_user(namlen, &dirent->d_namlen);
- put_user(reclen, &dirent->d_reclen);
- copy_to_user(dirent->d_name, name, namlen);
- put_user(0, dirent->d_name + namlen);
- dirent = (void __user *) dirent + reclen;
- buf->curr = dirent;
- buf->count -= reclen;
- return 0;
-}
-
-asmlinkage int sunos_getdents(unsigned int fd, void __user *dirent, int cnt)
-{
- struct file * file;
- struct sunos_dirent __user *lastdirent;
- struct sunos_dirent_callback buf;
- int error = -EBADF;
-
- if (fd >= SUNOS_NR_OPEN)
- goto out;
-
- file = fget(fd);
- if (!file)
- goto out;
-
- error = -EINVAL;
- if (cnt < (sizeof(struct sunos_dirent) + 255))
- goto out_putf;
-
- buf.curr = (struct sunos_dirent __user *) dirent;
- buf.previous = NULL;
- buf.count = cnt;
- buf.error = 0;
-
- error = vfs_readdir(file, sunos_filldir, &buf);
- if (error < 0)
- goto out_putf;
-
- lastdirent = buf.previous;
- error = buf.error;
- if (lastdirent) {
- put_user(file->f_pos, &lastdirent->d_off);
- error = cnt - buf.count;
- }
-
-out_putf:
- fput(file);
-out:
- return error;
-}
-
-/* Old sunos getdirentries, severely broken compatibility stuff here. */
-struct sunos_direntry {
- unsigned long d_ino;
- unsigned short d_reclen;
- unsigned short d_namlen;
- char d_name[1];
-};
-
-struct sunos_direntry_callback {
- struct sunos_direntry __user *curr;
- struct sunos_direntry __user *previous;
- int count;
- int error;
-};
-
-static int sunos_filldirentry(void * __buf, const char * name, int namlen,
- loff_t offset, u64 ino, unsigned int d_type)
-{
- struct sunos_direntry __user *dirent;
- struct sunos_direntry_callback *buf = __buf;
- unsigned long d_ino;
- int reclen = ROUND_UP(NAME_OFFSET(dirent) + namlen + 1);
-
- buf->error = -EINVAL; /* only used if we fail.. */
- if (reclen > buf->count)
- return -EINVAL;
- d_ino = ino;
- if (sizeof(d_ino) < sizeof(ino) && d_ino != ino)
- return -EOVERFLOW;
- dirent = buf->previous;
- dirent = buf->curr;
- buf->previous = dirent;
- put_user(d_ino, &dirent->d_ino);
- put_user(namlen, &dirent->d_namlen);
- put_user(reclen, &dirent->d_reclen);
- copy_to_user(dirent->d_name, name, namlen);
- put_user(0, dirent->d_name + namlen);
- dirent = (void __user *) dirent + reclen;
- buf->curr = dirent;
- buf->count -= reclen;
- return 0;
-}
-
-asmlinkage int sunos_getdirentries(unsigned int fd, void __user *dirent,
- int cnt, unsigned int __user *basep)
-{
- struct file * file;
- struct sunos_direntry __user *lastdirent;
- struct sunos_direntry_callback buf;
- int error = -EBADF;
-
- if (fd >= SUNOS_NR_OPEN)
- goto out;
-
- file = fget(fd);
- if (!file)
- goto out;
-
- error = -EINVAL;
- if (cnt < (sizeof(struct sunos_direntry) + 255))
- goto out_putf;
-
- buf.curr = (struct sunos_direntry __user *) dirent;
- buf.previous = NULL;
- buf.count = cnt;
- buf.error = 0;
-
- error = vfs_readdir(file, sunos_filldirentry, &buf);
- if (error < 0)
- goto out_putf;
-
- lastdirent = buf.previous;
- error = buf.error;
- if (lastdirent) {
- put_user(file->f_pos, basep);
- error = cnt - buf.count;
- }
-
-out_putf:
- fput(file);
-out:
- return error;
-}
-
-struct sunos_utsname {
- char sname[9];
- char nname[9];
- char nnext[56];
- char rel[9];
- char ver[9];
- char mach[9];
-};
-
-asmlinkage int sunos_uname(struct sunos_utsname __user *name)
-{
- int ret;
- down_read(&uts_sem);
- ret = copy_to_user(&name->sname[0], &utsname()->sysname[0],
- sizeof(name->sname) - 1);
- if (!ret) {
- ret |= __copy_to_user(&name->nname[0], &utsname()->nodename[0],
- sizeof(name->nname) - 1);
- ret |= __put_user('\0', &name->nname[8]);
- ret |= __copy_to_user(&name->rel[0], &utsname()->release[0],
- sizeof(name->rel) - 1);
- ret |= __copy_to_user(&name->ver[0], &utsname()->version[0],
- sizeof(name->ver) - 1);
- ret |= __copy_to_user(&name->mach[0], &utsname()->machine[0],
- sizeof(name->mach) - 1);
- }
- up_read(&uts_sem);
- return ret ? -EFAULT : 0;
-}
-
-asmlinkage int sunos_nosys(void)
-{
- struct pt_regs *regs;
- siginfo_t info;
- static int cnt;
-
- lock_kernel();
- regs = current->thread.kregs;
- info.si_signo = SIGSYS;
- info.si_errno = 0;
- info.si_code = __SI_FAULT|0x100;
- info.si_addr = (void __user *)regs->pc;
- info.si_trapno = regs->u_regs[UREG_G1];
- send_sig_info(SIGSYS, &info, current);
- if (cnt++ < 4) {
- printk("Process makes ni_syscall number %d, register dump:\n",
- (int) regs->u_regs[UREG_G1]);
- show_regs(regs);
- }
- unlock_kernel();
- return -ENOSYS;
-}
-
-/* This is not a real and complete implementation yet, just to keep
- * the easy SunOS binaries happy.
- */
-asmlinkage int sunos_fpathconf(int fd, int name)
-{
- int ret;
-
- switch(name) {
- case _PCONF_LINK:
- ret = LINK_MAX;
- break;
- case _PCONF_CANON:
- ret = MAX_CANON;
- break;
- case _PCONF_INPUT:
- ret = MAX_INPUT;
- break;
- case _PCONF_NAME:
- ret = NAME_MAX;
- break;
- case _PCONF_PATH:
- ret = PATH_MAX;
- break;
- case _PCONF_PIPE:
- ret = PIPE_BUF;
- break;
- case _PCONF_CHRESTRICT: /* XXX Investigate XXX */
- ret = 1;
- break;
- case _PCONF_NOTRUNC: /* XXX Investigate XXX */
- case _PCONF_VDISABLE:
- ret = 0;
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-asmlinkage int sunos_pathconf(char __user *path, int name)
-{
- int ret;
-
- ret = sunos_fpathconf(0, name); /* XXX cheese XXX */
- return ret;
-}
-
-/* SunOS mount system call emulation */
-
-asmlinkage int sunos_select(int width, fd_set __user *inp, fd_set __user *outp,
- fd_set __user *exp, struct timeval __user *tvp)
-{
- int ret;
-
- /* SunOS binaries expect that select won't change the tvp contents */
- ret = sys_select (width, inp, outp, exp, tvp);
- if (ret == -EINTR && tvp) {
- time_t sec, usec;
-
- __get_user(sec, &tvp->tv_sec);
- __get_user(usec, &tvp->tv_usec);
-
- if (sec == 0 && usec == 0)
- ret = 0;
- }
- return ret;
-}
-
-asmlinkage void sunos_nop(void)
-{
- return;
-}
-
-/* SunOS mount/umount. */
-#define SMNT_RDONLY 1
-#define SMNT_NOSUID 2
-#define SMNT_NEWTYPE 4
-#define SMNT_GRPID 8
-#define SMNT_REMOUNT 16
-#define SMNT_NOSUB 32
-#define SMNT_MULTI 64
-#define SMNT_SYS5 128
-
-struct sunos_fh_t {
- char fh_data [NFS_FHSIZE];
-};
-
-struct sunos_nfs_mount_args {
- struct sockaddr_in __user *addr; /* file server address */
- struct nfs_fh __user *fh; /* File handle to be mounted */
- int flags; /* flags */
- int wsize; /* write size in bytes */
- int rsize; /* read size in bytes */
- int timeo; /* initial timeout in .1 secs */
- int retrans; /* times to retry send */
- char __user *hostname; /* server's hostname */
- int acregmin; /* attr cache file min secs */
- int acregmax; /* attr cache file max secs */
- int acdirmin; /* attr cache dir min secs */
- int acdirmax; /* attr cache dir max secs */
- char __user *netname; /* server's netname */
-};
-
-
-/* Bind the socket on a local reserved port and connect it to the
- * remote server. This on Linux/i386 is done by the mount program,
- * not by the kernel.
- */
-static int
-sunos_nfs_get_server_fd (int fd, struct sockaddr_in *addr)
-{
- struct sockaddr_in local;
- struct sockaddr_in server;
- int try_port;
- struct socket *socket;
- struct inode *inode;
- struct file *file;
- int ret, result = 0;
-
- file = fget(fd);
- if (!file)
- goto out;
-
- inode = file->f_path.dentry->d_inode;
-
- socket = SOCKET_I(inode);
- local.sin_family = AF_INET;
- local.sin_addr.s_addr = htonl(INADDR_ANY);
-
- /* IPPORT_RESERVED = 1024, can't find the definition in the kernel */
- try_port = 1024;
- do {
- local.sin_port = htons (--try_port);
- ret = socket->ops->bind(socket, (struct sockaddr*)&local,
- sizeof(local));
- } while (ret && try_port > (1024 / 2));
-
- if (ret)
- goto out_putf;
-
- server.sin_family = AF_INET;
- server.sin_addr = addr->sin_addr;
- server.sin_port = NFS_PORT;
-
- /* Call sys_connect */
- ret = socket->ops->connect (socket, (struct sockaddr *) &server,
- sizeof (server), file->f_flags);
- if (ret >= 0)
- result = 1;
-
-out_putf:
- fput(file);
-out:
- return result;
-}
-
-static int get_default (int value, int def_value)
-{
- if (value)
- return value;
- else
- return def_value;
-}
-
-static int sunos_nfs_mount(char *dir_name, int linux_flags, void __user *data)
-{
- int server_fd, err;
- char *the_name, *mount_page;
- struct nfs_mount_data linux_nfs_mount;
- struct sunos_nfs_mount_args sunos_mount;
-
- /* Ok, here comes the fun part: Linux's nfs mount needs a
- * socket connection to the server, but SunOS mount does not
- * require this, so we use the information on the destination
- * address to create a socket and bind it to a reserved
- * port on this system
- */
- if (copy_from_user(&sunos_mount, data, sizeof(sunos_mount)))
- return -EFAULT;
-
- server_fd = sys_socket (AF_INET, SOCK_DGRAM, IPPROTO_UDP);
- if (server_fd < 0)
- return -ENXIO;
-
- if (copy_from_user(&linux_nfs_mount.addr,sunos_mount.addr,
- sizeof(*sunos_mount.addr)) ||
- copy_from_user(&linux_nfs_mount.root,sunos_mount.fh,
- sizeof(*sunos_mount.fh))) {
- sys_close (server_fd);
- return -EFAULT;
- }
-
- if (!sunos_nfs_get_server_fd (server_fd, &linux_nfs_mount.addr)){
- sys_close (server_fd);
- return -ENXIO;
- }
-
- /* Now, bind it to a locally reserved port */
- linux_nfs_mount.version = NFS_MOUNT_VERSION;
- linux_nfs_mount.flags = sunos_mount.flags;
- linux_nfs_mount.fd = server_fd;
-
- linux_nfs_mount.rsize = get_default (sunos_mount.rsize, 8192);
- linux_nfs_mount.wsize = get_default (sunos_mount.wsize, 8192);
- linux_nfs_mount.timeo = get_default (sunos_mount.timeo, 10);
- linux_nfs_mount.retrans = sunos_mount.retrans;
-
- linux_nfs_mount.acregmin = sunos_mount.acregmin;
- linux_nfs_mount.acregmax = sunos_mount.acregmax;
- linux_nfs_mount.acdirmin = sunos_mount.acdirmin;
- linux_nfs_mount.acdirmax = sunos_mount.acdirmax;
-
- the_name = getname(sunos_mount.hostname);
- if (IS_ERR(the_name))
- return PTR_ERR(the_name);
-
- strlcpy(linux_nfs_mount.hostname, the_name,
- sizeof(linux_nfs_mount.hostname));
- putname (the_name);
-
- mount_page = (char *) get_zeroed_page(GFP_KERNEL);
- if (!mount_page)
- return -ENOMEM;
-
- memcpy(mount_page, &linux_nfs_mount, sizeof(linux_nfs_mount));
-
- err = do_mount("", dir_name, "nfs", linux_flags, mount_page);
-
- free_page((unsigned long) mount_page);
- return err;
-}
-
-asmlinkage int
-sunos_mount(char __user *type, char __user *dir, int flags, void __user *data)
-{
- int linux_flags = 0;
- int ret = -EINVAL;
- char *dev_fname = NULL;
- char *dir_page, *type_page;
-
- if (!capable (CAP_SYS_ADMIN))
- return -EPERM;
-
- lock_kernel();
- /* We don't handle the integer fs type */
- if ((flags & SMNT_NEWTYPE) == 0)
- goto out;
-
- /* Do not allow for those flags we don't support */
- if (flags & (SMNT_GRPID|SMNT_NOSUB|SMNT_MULTI|SMNT_SYS5))
- goto out;
-
- if (flags & SMNT_REMOUNT)
- linux_flags |= MS_REMOUNT;
- if (flags & SMNT_RDONLY)
- linux_flags |= MS_RDONLY;
- if (flags & SMNT_NOSUID)
- linux_flags |= MS_NOSUID;
-
- dir_page = getname(dir);
- ret = PTR_ERR(dir_page);
- if (IS_ERR(dir_page))
- goto out;
-
- type_page = getname(type);
- ret = PTR_ERR(type_page);
- if (IS_ERR(type_page))
- goto out1;
-
- if (strcmp(type_page, "ext2") == 0) {
- dev_fname = getname(data);
- } else if (strcmp(type_page, "iso9660") == 0) {
- dev_fname = getname(data);
- } else if (strcmp(type_page, "minix") == 0) {
- dev_fname = getname(data);
- } else if (strcmp(type_page, "nfs") == 0) {
- ret = sunos_nfs_mount (dir_page, flags, data);
- goto out2;
- } else if (strcmp(type_page, "ufs") == 0) {
- printk("Warning: UFS filesystem mounts unsupported.\n");
- ret = -ENODEV;
- goto out2;
- } else if (strcmp(type_page, "proc")) {
- ret = -ENODEV;
- goto out2;
- }
- ret = PTR_ERR(dev_fname);
- if (IS_ERR(dev_fname))
- goto out2;
- ret = do_mount(dev_fname, dir_page, type_page, linux_flags, NULL);
- if (dev_fname)
- putname(dev_fname);
-out2:
- putname(type_page);
-out1:
- putname(dir_page);
-out:
- unlock_kernel();
- return ret;
-}
-
-
-asmlinkage int sunos_setpgrp(pid_t pid, pid_t pgid)
-{
- int ret;
-
- /* So stupid... */
- if ((!pid || pid == current->pid) &&
- !pgid) {
- sys_setsid();
- ret = 0;
- } else {
- ret = sys_setpgid(pid, pgid);
- }
- return ret;
-}
-
-/* So stupid... */
-asmlinkage int sunos_wait4(pid_t pid, unsigned int __user *stat_addr,
- int options, struct rusage __user*ru)
-{
- int ret;
-
- ret = sys_wait4((pid ? pid : -1), stat_addr, options, ru);
- return ret;
-}
-
-asmlinkage int sunos_killpg(int pgrp, int sig)
-{
- int ret;
-
- rcu_read_lock();
- ret = -EINVAL;
- if (pgrp > 0)
- ret = kill_pgrp(find_vpid(pgrp), sig, 0);
- rcu_read_unlock();
-
- return ret;
-}
-
-asmlinkage int sunos_audit(void)
-{
- lock_kernel();
- printk ("sys_audit\n");
- unlock_kernel();
- return -1;
-}
-
-asmlinkage unsigned long sunos_gethostid(void)
-{
- unsigned long ret;
-
- lock_kernel();
- ret = ((unsigned long)idprom->id_machtype << 24) |
- (unsigned long)idprom->id_sernum;
- unlock_kernel();
- return ret;
-}
-
-/* sysconf options, for SunOS compatibility */
-#define _SC_ARG_MAX 1
-#define _SC_CHILD_MAX 2
-#define _SC_CLK_TCK 3
-#define _SC_NGROUPS_MAX 4
-#define _SC_OPEN_MAX 5
-#define _SC_JOB_CONTROL 6
-#define _SC_SAVED_IDS 7
-#define _SC_VERSION 8
-
-asmlinkage long sunos_sysconf (int name)
-{
- long ret;
-
- switch (name){
- case _SC_ARG_MAX:
- ret = ARG_MAX;
- break;
- case _SC_CHILD_MAX:
- ret = current->signal->rlim[RLIMIT_NPROC].rlim_cur;
- break;
- case _SC_CLK_TCK:
- ret = HZ;
- break;
- case _SC_NGROUPS_MAX:
- ret = NGROUPS_MAX;
- break;
- case _SC_OPEN_MAX:
- ret = current->signal->rlim[RLIMIT_NOFILE].rlim_cur;
- break;
- case _SC_JOB_CONTROL:
- ret = 1; /* yes, we do support job control */
- break;
- case _SC_SAVED_IDS:
- ret = 1; /* yes, we do support saved uids */
- break;
- case _SC_VERSION:
- /* mhm, POSIX_VERSION is in /usr/include/unistd.h
- * should it go on /usr/include/linux?
- */
- ret = 199009L;
- break;
- default:
- ret = -1;
- break;
- };
- return ret;
-}
-
-asmlinkage int sunos_semsys(int op, unsigned long arg1, unsigned long arg2,
- unsigned long arg3, void *ptr)
-{
- union semun arg4;
- int ret;
-
- switch (op) {
- case 0:
- /* Most arguments match on a 1:1 basis but cmd doesn't */
- switch(arg3) {
- case 4:
- arg3=GETPID; break;
- case 5:
- arg3=GETVAL; break;
- case 6:
- arg3=GETALL; break;
- case 3:
- arg3=GETNCNT; break;
- case 7:
- arg3=GETZCNT; break;
- case 8:
- arg3=SETVAL; break;
- case 9:
- arg3=SETALL; break;
- }
- /* sys_semctl(): */
- /* value to modify semaphore to */
- arg4.__pad = (void __user *) ptr;
- ret = sys_semctl((int)arg1, (int)arg2, (int)arg3, arg4 );
- break;
- case 1:
- /* sys_semget(): */
- ret = sys_semget((key_t)arg1, (int)arg2, (int)arg3);
- break;
- case 2:
- /* sys_semop(): */
- ret = sys_semop((int)arg1, (struct sembuf __user *)arg2, (unsigned)arg3);
- break;
- default:
- ret = -EINVAL;
- break;
- };
- return ret;
-}
-
-asmlinkage int sunos_msgsys(int op, unsigned long arg1, unsigned long arg2,
- unsigned long arg3, unsigned long arg4)
-{
- struct sparc_stackf *sp;
- unsigned long arg5;
- int rval;
-
- switch(op) {
- case 0:
- rval = sys_msgget((key_t)arg1, (int)arg2);
- break;
- case 1:
- rval = sys_msgctl((int)arg1, (int)arg2,
- (struct msqid_ds __user *)arg3);
- break;
- case 2:
- lock_kernel();
- sp = (struct sparc_stackf *)current->thread.kregs->u_regs[UREG_FP];
- arg5 = sp->xxargs[0];
- unlock_kernel();
- rval = sys_msgrcv((int)arg1, (struct msgbuf __user *)arg2,
- (size_t)arg3, (long)arg4, (int)arg5);
- break;
- case 3:
- rval = sys_msgsnd((int)arg1, (struct msgbuf __user *)arg2,
- (size_t)arg3, (int)arg4);
- break;
- default:
- rval = -EINVAL;
- break;
- }
- return rval;
-}
-
-asmlinkage int sunos_shmsys(int op, unsigned long arg1, unsigned long arg2,
- unsigned long arg3)
-{
- unsigned long raddr;
- int rval;
-
- switch(op) {
- case 0:
- /* do_shmat(): attach a shared memory area */
- rval = do_shmat((int)arg1,(char __user *)arg2,(int)arg3,&raddr);
- if (!rval)
- rval = (int) raddr;
- break;
- case 1:
- /* sys_shmctl(): modify shared memory area attr. */
- rval = sys_shmctl((int)arg1,(int)arg2,(struct shmid_ds __user *)arg3);
- break;
- case 2:
- /* sys_shmdt(): detach a shared memory area */
- rval = sys_shmdt((char __user *)arg1);
- break;
- case 3:
- /* sys_shmget(): get a shared memory area */
- rval = sys_shmget((key_t)arg1,(int)arg2,(int)arg3);
- break;
- default:
- rval = -EINVAL;
- break;
- };
- return rval;
-}
-
-#define SUNOS_EWOULDBLOCK 35
-
-/* see the sunos man page read(2v) for an explanation
- of this garbage. We use O_NDELAY to mark
- file descriptors that have been set non-blocking
- using 4.2BSD style calls. (tridge) */
-
-static inline int check_nonblock(int ret, int fd)
-{
- if (ret == -EAGAIN) {
- struct file * file = fget(fd);
- if (file) {
- if (file->f_flags & O_NDELAY)
- ret = -SUNOS_EWOULDBLOCK;
- fput(file);
- }
- }
- return ret;
-}
-
-asmlinkage int sunos_read(unsigned int fd, char __user *buf, int count)
-{
- int ret;
-
- ret = check_nonblock(sys_read(fd,buf,count),fd);
- return ret;
-}
-
-asmlinkage int sunos_readv(unsigned long fd, const struct iovec __user *vector,
- long count)
-{
- int ret;
-
- ret = check_nonblock(sys_readv(fd,vector,count),fd);
- return ret;
-}
-
-asmlinkage int sunos_write(unsigned int fd, char __user *buf, int count)
-{
- int ret;
-
- ret = check_nonblock(sys_write(fd,buf,count),fd);
- return ret;
-}
-
-asmlinkage int sunos_writev(unsigned long fd,
- const struct iovec __user *vector, long count)
-{
- int ret;
-
- ret = check_nonblock(sys_writev(fd,vector,count),fd);
- return ret;
-}
-
-asmlinkage int sunos_recv(int fd, void __user *ubuf, int size, unsigned flags)
-{
- int ret;
-
- ret = check_nonblock(sys_recv(fd,ubuf,size,flags),fd);
- return ret;
-}
-
-asmlinkage int sunos_send(int fd, void __user *buff, int len, unsigned flags)
-{
- int ret;
-
- ret = check_nonblock(sys_send(fd,buff,len,flags),fd);
- return ret;
-}
-
-asmlinkage int sunos_accept(int fd, struct sockaddr __user *sa,
- int __user *addrlen)
-{
- int ret;
-
- while (1) {
- ret = check_nonblock(sys_accept(fd,sa,addrlen),fd);
- if (ret != -ENETUNREACH && ret != -EHOSTUNREACH)
- break;
- }
-
- return ret;
-}
-
-#define SUNOS_SV_INTERRUPT 2
-
-asmlinkage int
-sunos_sigaction(int sig, const struct old_sigaction __user *act,
- struct old_sigaction __user *oact)
-{
- struct k_sigaction new_ka, old_ka;
- int ret;
-
- if (act) {
- old_sigset_t mask;
-
- if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
- __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
- __get_user(new_ka.sa.sa_flags, &act->sa_flags))
- return -EFAULT;
- __get_user(mask, &act->sa_mask);
- new_ka.sa.sa_restorer = NULL;
- new_ka.ka_restorer = NULL;
- siginitset(&new_ka.sa.sa_mask, mask);
- new_ka.sa.sa_flags ^= SUNOS_SV_INTERRUPT;
- }
-
- ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
-
- if (!ret && oact) {
- /* In the clone() case we could copy half consistent
- * state to the user, however this could sleep and
- * deadlock us if we held the signal lock on SMP. So for
- * now I take the easy way out and do no locking.
- * But then again we don't support SunOS lwp's anyways ;-)
- */
- old_ka.sa.sa_flags ^= SUNOS_SV_INTERRUPT;
- if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
- __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
- __put_user(old_ka.sa.sa_flags, &oact->sa_flags))
- return -EFAULT;
- __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
- }
-
- return ret;
-}
-
-
-asmlinkage int sunos_setsockopt(int fd, int level, int optname,
- char __user *optval, int optlen)
-{
- int tr_opt = optname;
- int ret;
-
- if (level == SOL_IP) {
- /* Multicast socketopts (ttl, membership) */
- if (tr_opt >=2 && tr_opt <= 6)
- tr_opt += 30;
- }
- ret = sys_setsockopt(fd, level, tr_opt, optval, optlen);
- return ret;
-}
-
-asmlinkage int sunos_getsockopt(int fd, int level, int optname,
- char __user *optval, int __user *optlen)
-{
- int tr_opt = optname;
- int ret;
-
- if (level == SOL_IP) {
- /* Multicast socketopts (ttl, membership) */
- if (tr_opt >=2 && tr_opt <= 6)
- tr_opt += 30;
- }
- ret = sys_getsockopt(fd, level, tr_opt, optval, optlen);
- return ret;
-}
/*305*/ .long sys_set_mempolicy, sys_kexec_load, sys_move_pages, sys_getcpu, sys_epoll_pwait
/*310*/ .long sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate
/*315*/ .long sys_timerfd_settime, sys_timerfd_gettime
-
-#ifdef CONFIG_SUNOS_EMUL
- /* Now the SunOS syscall table. */
-
- .align 4
- .globl sunos_sys_table
-sunos_sys_table:
-/*0*/ .long sunos_indir, sys_exit, sys_fork
- .long sunos_read, sunos_write, sys_open
- .long sys_close, sunos_wait4, sys_creat
- .long sys_link, sys_unlink, sunos_execv
- .long sys_chdir, sunos_nosys, sys_mknod
- .long sys_chmod, sys_lchown16, sunos_brk
- .long sunos_nosys, sys_lseek, sunos_getpid
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_getuid, sunos_nosys, sys_ptrace
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sys_access, sunos_nosys, sunos_nosys
- .long sys_sync, sys_kill, sys_newstat
- .long sunos_nosys, sys_newlstat, sys_dup
- .long sys_pipe, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_getgid
- .long sunos_nosys, sunos_nosys
-/*50*/ .long sunos_nosys, sys_acct, sunos_nosys
- .long sunos_mctl, sunos_ioctl, sys_reboot
- .long sunos_nosys, sys_symlink, sys_readlink
- .long sys_execve, sys_umask, sys_chroot
- .long sys_newfstat, sunos_nosys, sys_getpagesize
- .long sys_msync, sys_vfork, sunos_nosys
- .long sunos_nosys, sunos_sbrk, sunos_sstk
- .long sunos_mmap, sunos_vadvise, sys_munmap
- .long sys_mprotect, sys_madvise, sys_vhangup
- .long sunos_nosys, sys_mincore, sys_getgroups16
- .long sys_setgroups16, sys_getpgrp, sunos_setpgrp
- .long sys_setitimer, sunos_nosys, sys_swapon
- .long sys_getitimer, sys_gethostname, sys_sethostname
- .long sunos_getdtablesize, sys_dup2, sunos_nop
- .long sys_fcntl, sunos_select, sunos_nop
- .long sys_fsync, sys_setpriority, sys_socket
- .long sys_connect, sunos_accept
-/*100*/ .long sys_getpriority, sunos_send, sunos_recv
- .long sunos_nosys, sys_bind, sunos_setsockopt
- .long sys_listen, sunos_nosys, sunos_sigaction
- .long sunos_sigblock, sunos_sigsetmask, sys_sigpause
- .long sys_sigstack, sys_recvmsg, sys_sendmsg
- .long sunos_nosys, sys_gettimeofday, sys_getrusage
- .long sunos_getsockopt, sunos_nosys, sunos_readv
- .long sunos_writev, sys_settimeofday, sys_fchown16
- .long sys_fchmod, sys_recvfrom, sys_setreuid16
- .long sys_setregid16, sys_rename, sys_truncate
- .long sys_ftruncate, sys_flock, sunos_nosys
- .long sys_sendto, sys_shutdown, sys_socketpair
- .long sys_mkdir, sys_rmdir, sys_utimes
- .long sys_sigreturn, sunos_nosys, sys_getpeername
- .long sunos_gethostid, sunos_nosys, sys_getrlimit
- .long sys_setrlimit, sunos_killpg, sunos_nosys
- .long sunos_nosys, sunos_nosys
-/*150*/ .long sys_getsockname, sunos_nosys, sunos_nosys
- .long sys_poll, sunos_nosys, sunos_nosys
- .long sunos_getdirentries, sys_statfs, sys_fstatfs
- .long sys_oldumount, sunos_nosys, sunos_nosys
- .long sys_getdomainname, sys_setdomainname
- .long sunos_nosys, sys_quotactl, sunos_nosys
- .long sunos_mount, sys_ustat, sunos_semsys
- .long sunos_msgsys, sunos_shmsys, sunos_audit
- .long sunos_nosys, sunos_getdents, sys_setsid
- .long sys_fchdir, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sys_sigpending, sunos_nosys
- .long sys_setpgid, sunos_pathconf, sunos_fpathconf
- .long sunos_sysconf, sunos_uname, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
-/*200*/ .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys
-/*250*/ .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys
-/*260*/ .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys
-/*270*/ .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys
-/*280*/ .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys
-/*290*/ .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys
-/*300*/ .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys
-/*310*/ .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys, sunos_nosys, sunos_nosys
- .long sunos_nosys
-
-#endif
#define TICK_SIZE (tick_nsec / 1000)
-irqreturn_t timer_interrupt(int irq, void *dev_id)
+static irqreturn_t timer_interrupt(int dummy, void *dev_id)
{
/* last time the cmos clock got updated */
static long last_rtc_update;
bool
default y
select HAVE_IDE
+ select HAVE_LMB
help
SPARC is a family of RISC microprocessors designed and marketed by
Sun Microsystems, incorporated. This port covers the newer 64-bit
bool
def_bool y
-config ARCH_SUPPORTS_AOUT
- def_bool y
-
choice
prompt "Kernel page size"
default SPARC64_PAGE_SIZE_8KB
source "init/Kconfig"
-config SYSVIPC_COMPAT
- bool
- depends on COMPAT && SYSVIPC
- default y
-
config GENERIC_HARDIRQS
bool
default y
To compile the /proc/openprom support as a module, choose M here: the
module will be called openpromfs. If unsure, choose M.
+menu "Executable file formats"
+
+source "fs/Kconfig.binfmt"
+
config SPARC32_COMPAT
bool "Kernel support for Linux/Sparc 32bit binary compatibility"
help
default y
select COMPAT_BINFMT_ELF
-config BINFMT_AOUT32
- bool "Kernel support for 32-bit (ie. SunOS) a.out binaries"
- depends on SPARC32_COMPAT && ARCH_SUPPORTS_AOUT
- help
- This allows you to run 32-bit a.out format binaries on your Ultra.
- If you want to run SunOS binaries (see SunOS binary emulation below)
- or other a.out binaries, say Y. If unsure, say N.
-
-menu "Executable file formats"
-
-source "fs/Kconfig.binfmt"
-
-config SUNOS_EMUL
- bool "SunOS binary emulation"
- depends on BINFMT_AOUT32
- help
- This allows you to run most SunOS binaries. If you want to do this,
- say Y here and place appropriate files in /usr/gnemul/sunos. See
- <http://www.ultralinux.org/faq.html> for more information. If you
- want to run SunOS binaries on an Ultra you must also say Y to
- "Kernel support for 32-bit a.out binaries" above.
-
-config SOLARIS_EMUL
- tristate "Solaris binary emulation (EXPERIMENTAL)"
- depends on SPARC32_COMPAT && NET && EXPERIMENTAL
- help
- This is experimental code which will enable you to run (many)
- Solaris binaries on your SPARC Linux machine.
-
- To compile this code as a module, choose M here: the
- module will be called solaris.
+config SYSVIPC_COMPAT
+ bool
+ depends on COMPAT && SYSVIPC
+ default y
endmenu
head-y := arch/sparc64/kernel/head.o arch/sparc64/kernel/init_task.o
core-y += arch/sparc64/kernel/ arch/sparc64/mm/
-core-$(CONFIG_SOLARIS_EMUL) += arch/sparc64/solaris/
core-y += arch/sparc64/math-emu/
libs-y += arch/sparc64/prom/ arch/sparc64/lib/
drivers-$(CONFIG_OPROFILE) += arch/sparc64/oprofile/
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25-rc3
-# Wed Mar 26 04:33:35 2008
+# Linux kernel version: 2.6.25
+# Sun Apr 20 01:33:21 2008
#
CONFIG_SPARC=y
CONFIG_SPARC64=y
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_OF=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
CONFIG_SPARC64_PAGE_SIZE_8KB=y
# CONFIG_SPARC64_PAGE_SIZE_64KB is not set
# CONFIG_SPARC64_PAGE_SIZE_512KB is not set
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
CONFIG_OPROFILE=m
CONFIG_HAVE_OPROFILE=y
CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_CLASSIC_RCU=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_SYSVIPC_COMPAT=y
CONFIG_GENERIC_HARDIRQS=y
#
# CONFIG_PCI_LEGACY is not set
# CONFIG_PCI_DEBUG is not set
CONFIG_SUN_OPENPROMFS=m
-CONFIG_SPARC32_COMPAT=y
-CONFIG_COMPAT=y
-# CONFIG_BINFMT_AOUT32 is not set
#
# Executable file formats
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_BINFMT_MISC=m
-CONFIG_SOLARIS_EMUL=y
+CONFIG_SPARC32_COMPAT=y
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
CONFIG_SCHED_SMT=y
CONFIG_SCHED_MC=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
-# CONFIG_RCU_TRACE is not set
# CONFIG_CMDLINE_BOOL is not set
#
CONFIG_INET6_XFRM_MODE_BEET=m
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
CONFIG_IP_DCCP=m
CONFIG_BLK_DEV_IDE=y
#
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_IDE_SATA is not set
CONFIG_BLK_DEV_IDEDISK=y
#
# IDE chipset support/bugfixes
#
-CONFIG_IDE_GENERIC=y
# CONFIG_BLK_DEV_PLATFORM is not set
CONFIG_BLK_DEV_IDEDMA_SFF=y
# CONFIG_BLK_DEV_VIA82CXXX is not set
# CONFIG_BLK_DEV_TC86C001 is not set
CONFIG_BLK_DEV_IDEDMA=y
-CONFIG_IDE_ARCH_OBSOLETE_INIT=y
+# CONFIG_BLK_DEV_HD_ONLY is not set
# CONFIG_BLK_DEV_HD is not set
#
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
# CONFIG_VIA_VELOCITY is not set
CONFIG_TIGON3=m
CONFIG_BNX2=m
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
#
# USB Network Adapters
CONFIG_CRYPTO_CRC32C=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_LZO is not set
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_HIFN_795X is not set
obj-$(CONFIG_PCI_MSI) += pci_msi.o
obj-$(CONFIG_SMP) += smp.o trampoline.o hvtramp.o
obj-$(CONFIG_SPARC32_COMPAT) += sys32.o sys_sparc32.o signal32.o
-obj-$(CONFIG_BINFMT_AOUT32) += binfmt_aout32.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_US3_FREQ) += us3_cpufreq.o
obj-$(CONFIG_US2E_FREQ) += us2e_cpufreq.o
obj-$(CONFIG_AUDIT) += audit.o
obj-$(CONFIG_AUDIT)$(CONFIG_SPARC32_COMPAT) += compat_audit.o
obj-y += $(obj-yy)
-
-ifdef CONFIG_SUNOS_EMUL
- obj-y += sys_sunos32.o sunos_ioctl32.o
-else
- ifdef CONFIG_SOLARIS_EMUL
- obj-y += sys_sunos32.o sunos_ioctl32.o
- endif
-endif
+++ /dev/null
-/*
- * linux/fs/binfmt_aout.c
- *
- * Copyright (C) 1991, 1992, 1996 Linus Torvalds
- *
- * Hacked a bit by DaveM to make it work with 32-bit SunOS
- * binaries on the sparc64 port.
- */
-
-#include <linux/module.h>
-
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/mman.h>
-#include <linux/a.out.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/string.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/stat.h>
-#include <linux/fcntl.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/slab.h>
-#include <linux/binfmts.h>
-#include <linux/personality.h>
-#include <linux/init.h>
-
-#include <asm/system.h>
-#include <asm/uaccess.h>
-#include <asm/pgalloc.h>
-#include <asm/mmu_context.h>
-#include <asm/a.out-core.h>
-
-static int load_aout32_binary(struct linux_binprm *, struct pt_regs * regs);
-static int load_aout32_library(struct file*);
-static int aout32_core_dump(long signr, struct pt_regs *regs, struct file *file, unsigned long limit);
-
-static struct linux_binfmt aout32_format = {
- .module = THIS_MODULE,
- .load_binary = load_aout32_binary,
- .load_shlib = load_aout32_library,
- .core_dump = aout32_core_dump,
- .min_coredump = PAGE_SIZE,
-};
-
-static void set_brk(unsigned long start, unsigned long end)
-{
- start = PAGE_ALIGN(start);
- end = PAGE_ALIGN(end);
- if (end <= start)
- return;
- down_write(¤t->mm->mmap_sem);
- do_brk(start, end - start);
- up_write(¤t->mm->mmap_sem);
-}
-
-/*
- * These are the only things you should do on a core-file: use only these
- * macros to write out all the necessary info.
- */
-
-static int dump_write(struct file *file, const void *addr, int nr)
-{
- return file->f_op->write(file, addr, nr, &file->f_pos) == nr;
-}
-
-#define DUMP_WRITE(addr, nr) \
- if (!dump_write(file, (void *)(addr), (nr))) \
- goto end_coredump;
-
-#define DUMP_SEEK(offset) \
-if (file->f_op->llseek) { \
- if (file->f_op->llseek(file,(offset),0) != (offset)) \
- goto end_coredump; \
-} else file->f_pos = (offset)
-
-/*
- * Routine writes a core dump image in the current directory.
- * Currently only a stub-function.
- *
- * Note that setuid/setgid files won't make a core-dump if the uid/gid
- * changed due to the set[u|g]id. It's enforced by the "current->mm->dumpable"
- * field, which also makes sure the core-dumps won't be recursive if the
- * dumping of the process results in another error..
- */
-
-static int aout32_core_dump(long signr, struct pt_regs *regs, struct file *file, unsigned long limit)
-{
- mm_segment_t fs;
- int has_dumped = 0;
- unsigned long dump_start, dump_size;
- struct user dump;
-# define START_DATA(u) (u.u_tsize)
-# define START_STACK(u) ((regs->u_regs[UREG_FP]) & ~(PAGE_SIZE - 1))
-
- fs = get_fs();
- set_fs(KERNEL_DS);
- has_dumped = 1;
- current->flags |= PF_DUMPCORE;
- strncpy(dump.u_comm, current->comm, sizeof(dump.u_comm));
- dump.signal = signr;
- aout_dump_thread(regs, &dump);
-
-/* If the size of the dump file exceeds the rlimit, then see what would happen
- if we wrote the stack, but not the data area. */
- if (dump.u_dsize + dump.u_ssize > limit)
- dump.u_dsize = 0;
-
-/* Make sure we have enough room to write the stack and data areas. */
- if (dump.u_ssize > limit)
- dump.u_ssize = 0;
-
-/* make sure we actually have a data and stack area to dump */
- set_fs(USER_DS);
- if (!access_ok(VERIFY_READ, (void __user *) START_DATA(dump), dump.u_dsize))
- dump.u_dsize = 0;
- if (!access_ok(VERIFY_READ, (void __user *) START_STACK(dump), dump.u_ssize))
- dump.u_ssize = 0;
-
- set_fs(KERNEL_DS);
-/* struct user */
- DUMP_WRITE(&dump,sizeof(dump));
-/* now we start writing out the user space info */
- set_fs(USER_DS);
-/* Dump the data area */
- if (dump.u_dsize != 0) {
- dump_start = START_DATA(dump);
- dump_size = dump.u_dsize;
- DUMP_WRITE(dump_start,dump_size);
- }
-/* Now prepare to dump the stack area */
- if (dump.u_ssize != 0) {
- dump_start = START_STACK(dump);
- dump_size = dump.u_ssize;
- DUMP_WRITE(dump_start,dump_size);
- }
-/* Finally dump the task struct. Not be used by gdb, but could be useful */
- set_fs(KERNEL_DS);
- DUMP_WRITE(current,sizeof(*current));
-end_coredump:
- set_fs(fs);
- return has_dumped;
-}
-
-/*
- * create_aout32_tables() parses the env- and arg-strings in new user
- * memory and creates the pointer tables from them, and puts their
- * addresses on the "stack", returning the new stack pointer value.
- */
-
-static u32 __user *create_aout32_tables(char __user *p, struct linux_binprm *bprm)
-{
- u32 __user *argv;
- u32 __user *envp;
- u32 __user *sp;
- int argc = bprm->argc;
- int envc = bprm->envc;
-
- sp = (u32 __user *)((-(unsigned long)sizeof(char *))&(unsigned long)p);
-
- /* This imposes the proper stack alignment for a new process. */
- sp = (u32 __user *) (((unsigned long) sp) & ~7);
- if ((envc+argc+3)&1)
- --sp;
-
- sp -= envc+1;
- envp = sp;
- sp -= argc+1;
- argv = sp;
- put_user(argc,--sp);
- current->mm->arg_start = (unsigned long) p;
- while (argc-->0) {
- char c;
- put_user(((u32)(unsigned long)(p)),argv++);
- do {
- get_user(c,p++);
- } while (c);
- }
- put_user(0,argv);
- current->mm->arg_end = current->mm->env_start = (unsigned long) p;
- while (envc-->0) {
- char c;
- put_user(((u32)(unsigned long)(p)),envp++);
- do {
- get_user(c,p++);
- } while (c);
- }
- put_user(0,envp);
- current->mm->env_end = (unsigned long) p;
- return sp;
-}
-
-/*
- * These are the functions used to load a.out style executables and shared
- * libraries. There is no binary dependent code anywhere else.
- */
-
-static int load_aout32_binary(struct linux_binprm * bprm, struct pt_regs * regs)
-{
- struct exec ex;
- unsigned long error;
- unsigned long fd_offset;
- unsigned long rlim;
- unsigned long orig_thr_flags;
- int retval;
-
- ex = *((struct exec *) bprm->buf); /* exec-header */
- if ((N_MAGIC(ex) != ZMAGIC && N_MAGIC(ex) != OMAGIC &&
- N_MAGIC(ex) != QMAGIC && N_MAGIC(ex) != NMAGIC) ||
- N_TRSIZE(ex) || N_DRSIZE(ex) ||
- bprm->file->f_path.dentry->d_inode->i_size < ex.a_text+ex.a_data+N_SYMSIZE(ex)+N_TXTOFF(ex)) {
- return -ENOEXEC;
- }
-
- fd_offset = N_TXTOFF(ex);
-
- /* Check initial limits. This avoids letting people circumvent
- * size limits imposed on them by creating programs with large
- * arrays in the data or bss.
- */
- rlim = current->signal->rlim[RLIMIT_DATA].rlim_cur;
- if (rlim >= RLIM_INFINITY)
- rlim = ~0;
- if (ex.a_data + ex.a_bss > rlim)
- return -ENOMEM;
-
- /* Flush all traces of the currently running executable */
- retval = flush_old_exec(bprm);
- if (retval)
- return retval;
-
- /* OK, This is the point of no return */
- set_personality(PER_SUNOS);
-
- current->mm->end_code = ex.a_text +
- (current->mm->start_code = N_TXTADDR(ex));
- current->mm->end_data = ex.a_data +
- (current->mm->start_data = N_DATADDR(ex));
- current->mm->brk = ex.a_bss +
- (current->mm->start_brk = N_BSSADDR(ex));
- current->mm->free_area_cache = current->mm->mmap_base;
- current->mm->cached_hole_size = 0;
-
- current->mm->mmap = NULL;
- compute_creds(bprm);
- current->flags &= ~PF_FORKNOEXEC;
- if (N_MAGIC(ex) == NMAGIC) {
- loff_t pos = fd_offset;
- /* Fuck me plenty... */
- down_write(¤t->mm->mmap_sem);
- error = do_brk(N_TXTADDR(ex), ex.a_text);
- up_write(¤t->mm->mmap_sem);
- bprm->file->f_op->read(bprm->file, (char __user *)N_TXTADDR(ex),
- ex.a_text, &pos);
- down_write(¤t->mm->mmap_sem);
- error = do_brk(N_DATADDR(ex), ex.a_data);
- up_write(¤t->mm->mmap_sem);
- bprm->file->f_op->read(bprm->file, (char __user *)N_DATADDR(ex),
- ex.a_data, &pos);
- goto beyond_if;
- }
-
- if (N_MAGIC(ex) == OMAGIC) {
- loff_t pos = fd_offset;
- down_write(¤t->mm->mmap_sem);
- do_brk(N_TXTADDR(ex) & PAGE_MASK,
- ex.a_text+ex.a_data + PAGE_SIZE - 1);
- up_write(¤t->mm->mmap_sem);
- bprm->file->f_op->read(bprm->file, (char __user *)N_TXTADDR(ex),
- ex.a_text+ex.a_data, &pos);
- } else {
- static unsigned long error_time;
- if ((ex.a_text & 0xfff || ex.a_data & 0xfff) &&
- (N_MAGIC(ex) != NMAGIC) && (jiffies-error_time) > 5*HZ)
- {
- printk(KERN_NOTICE "executable not page aligned\n");
- error_time = jiffies;
- }
-
- if (!bprm->file->f_op->mmap) {
- loff_t pos = fd_offset;
- down_write(¤t->mm->mmap_sem);
- do_brk(0, ex.a_text+ex.a_data);
- up_write(¤t->mm->mmap_sem);
- bprm->file->f_op->read(bprm->file,
- (char __user *)N_TXTADDR(ex),
- ex.a_text+ex.a_data, &pos);
- goto beyond_if;
- }
-
- down_write(¤t->mm->mmap_sem);
- error = do_mmap(bprm->file, N_TXTADDR(ex), ex.a_text,
- PROT_READ | PROT_EXEC,
- MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE,
- fd_offset);
- up_write(¤t->mm->mmap_sem);
-
- if (error != N_TXTADDR(ex)) {
- send_sig(SIGKILL, current, 0);
- return error;
- }
-
- down_write(¤t->mm->mmap_sem);
- error = do_mmap(bprm->file, N_DATADDR(ex), ex.a_data,
- PROT_READ | PROT_WRITE | PROT_EXEC,
- MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE,
- fd_offset + ex.a_text);
- up_write(¤t->mm->mmap_sem);
- if (error != N_DATADDR(ex)) {
- send_sig(SIGKILL, current, 0);
- return error;
- }
- }
-beyond_if:
- set_binfmt(&aout32_format);
-
- set_brk(current->mm->start_brk, current->mm->brk);
-
- /* Make sure STACK_TOP returns the right thing. */
- orig_thr_flags = current_thread_info()->flags;
- current_thread_info()->flags |= _TIF_32BIT;
-
- retval = setup_arg_pages(bprm, STACK_TOP, EXSTACK_DEFAULT);
- if (retval < 0) {
- current_thread_info()->flags = orig_thr_flags;
-
- /* Someone check-me: is this error path enough? */
- send_sig(SIGKILL, current, 0);
- return retval;
- }
-
- current->mm->start_stack =
- (unsigned long) create_aout32_tables((char __user *)bprm->p, bprm);
- tsb_context_switch(current->mm);
-
- start_thread32(regs, ex.a_entry, current->mm->start_stack);
- if (current->ptrace & PT_PTRACED)
- send_sig(SIGTRAP, current, 0);
- return 0;
-}
-
-/* N.B. Move to .h file and use code in fs/binfmt_aout.c? */
-static int load_aout32_library(struct file *file)
-{
- struct inode * inode;
- unsigned long bss, start_addr, len;
- unsigned long error;
- int retval;
- struct exec ex;
-
- inode = file->f_path.dentry->d_inode;
-
- retval = -ENOEXEC;
- error = kernel_read(file, 0, (char *) &ex, sizeof(ex));
- if (error != sizeof(ex))
- goto out;
-
- /* We come in here for the regular a.out style of shared libraries */
- if ((N_MAGIC(ex) != ZMAGIC && N_MAGIC(ex) != QMAGIC) || N_TRSIZE(ex) ||
- N_DRSIZE(ex) || ((ex.a_entry & 0xfff) && N_MAGIC(ex) == ZMAGIC) ||
- inode->i_size < ex.a_text+ex.a_data+N_SYMSIZE(ex)+N_TXTOFF(ex)) {
- goto out;
- }
-
- if (N_MAGIC(ex) == ZMAGIC && N_TXTOFF(ex) &&
- (N_TXTOFF(ex) < inode->i_sb->s_blocksize)) {
- printk("N_TXTOFF < BLOCK_SIZE. Please convert library\n");
- goto out;
- }
-
- if (N_FLAGS(ex))
- goto out;
-
- /* For QMAGIC, the starting address is 0x20 into the page. We mask
- this off to get the starting address for the page */
-
- start_addr = ex.a_entry & 0xfffff000;
-
- /* Now use mmap to map the library into memory. */
- down_write(¤t->mm->mmap_sem);
- error = do_mmap(file, start_addr, ex.a_text + ex.a_data,
- PROT_READ | PROT_WRITE | PROT_EXEC,
- MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE,
- N_TXTOFF(ex));
- up_write(¤t->mm->mmap_sem);
- retval = error;
- if (error != start_addr)
- goto out;
-
- len = PAGE_ALIGN(ex.a_text + ex.a_data);
- bss = ex.a_text + ex.a_data + ex.a_bss;
- if (bss > len) {
- down_write(¤t->mm->mmap_sem);
- error = do_brk(start_addr + len, bss - len);
- up_write(¤t->mm->mmap_sem);
- retval = error;
- if (error != start_addr + len)
- goto out;
- }
- retval = 0;
-out:
- return retval;
-}
-
-static int __init init_aout32_binfmt(void)
-{
- return register_binfmt(&aout32_format);
-}
-
-static void __exit exit_aout32_binfmt(void)
-{
- unregister_binfmt(&aout32_format);
-}
-
-module_init(init_aout32_binfmt);
-module_exit(exit_aout32_binfmt);
ba,pt %xcc, rtrap
nop
-#if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
- defined(CONFIG_SOLARIS_EMUL_MODULE)
- /* SunOS uses syscall zero as the 'indirect syscall' it looks
- * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
- * This is complete brain damage.
- */
- .globl sunos_indir
-sunos_indir:
- srl %o0, 0, %o0
- mov %o7, %l4
- cmp %o0, NR_SYSCALLS
- blu,a,pt %icc, 1f
- sll %o0, 0x2, %o0
- sethi %hi(sunos_nosys), %l6
- b,pt %xcc, 2f
- or %l6, %lo(sunos_nosys), %l6
-1: sethi %hi(sunos_sys_table), %l7
- or %l7, %lo(sunos_sys_table), %l7
- lduw [%l7 + %o0], %l6
-2: mov %o1, %o0
- mov %o2, %o1
- mov %o3, %o2
- mov %o4, %o3
- mov %o5, %o4
- call %l6
- mov %l4, %o7
-
- .globl sunos_getpid
-sunos_getpid:
- call sys_getppid
- nop
- call sys_getpid
- stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
- b,pt %xcc, ret_sys_call
- stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
-
- /* SunOS getuid() returns uid in %o0 and euid in %o1 */
- .globl sunos_getuid
-sunos_getuid:
- call sys32_geteuid16
- nop
- call sys32_getuid16
- stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
- b,pt %xcc, ret_sys_call
- stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
-
- /* SunOS getgid() returns gid in %o0 and egid in %o1 */
- .globl sunos_getgid
-sunos_getgid:
- call sys32_getegid16
- nop
- call sys32_getgid16
- stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
- b,pt %xcc, ret_sys_call
- stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
-#endif
-
/* SunOS's execv() call only specifies the argv argument, the
* environment settings are the same as the calling processes.
*/
mov %i4, %o4
- /* Linux 32-bit and SunOS system calls enter here... */
+ /* Linux 32-bit system calls enter here... */
.align 32
.globl linux_sparc_syscall32
linux_sparc_syscall32:
srl %i3, 0, %o3 ! IEU0
ba,a,pt %xcc, 3f
- /* Linux native and SunOS system calls enter here... */
+ /* Linux native system calls enter here... */
.align 32
.globl linux_sparc_syscall, ret_sys_call
linux_sparc_syscall:
#include <asm/uaccess.h>
#include <asm/ptrace.h>
-#include <asm/svr4.h>
#include <asm/pgtable.h>
#include <asm/fpumacro.h>
#include <asm/uctx.h>
#include <asm/uaccess.h>
#include <asm/ptrace.h>
-#include <asm/svr4.h>
#include <asm/pgtable.h>
#include <asm/psrcompat.h>
#include <asm/fpumacro.h>
force_sigsegv(signo, current);
}
-/* Setup a Solaris stack frame */
-static void
-setup_svr4_frame32(struct sigaction *sa, unsigned long pc, unsigned long npc,
- struct pt_regs *regs, int signr, sigset_t *oldset)
-{
- svr4_signal_frame_t __user *sfp;
- svr4_gregset_t __user *gr;
- svr4_siginfo_t __user *si;
- svr4_mcontext_t __user *mc;
- svr4_gwindows_t __user *gw;
- svr4_ucontext_t __user *uc;
- svr4_sigset_t setv;
- unsigned int psr;
- int i, err;
-
- synchronize_user_stack();
- save_and_clear_fpu();
-
- regs->u_regs[UREG_FP] &= 0x00000000ffffffffUL;
- sfp = (svr4_signal_frame_t __user *)
- get_sigframe(sa, regs,
- sizeof(struct reg_window32) + SVR4_SF_ALIGNED);
-
- if (invalid_frame_pointer(sfp, sizeof(*sfp)))
- do_exit(SIGILL);
-
- /* Start with a clean frame pointer and fill it */
- err = clear_user(sfp, sizeof(*sfp));
-
- /* Setup convenience variables */
- si = &sfp->si;
- uc = &sfp->uc;
- gw = &sfp->gw;
- mc = &uc->mcontext;
- gr = &mc->greg;
-
- /* FIXME: where am I supposed to put this?
- * sc->sigc_onstack = old_status;
- * anyways, it does not look like it is used for anything at all.
- */
- setv.sigbits[0] = oldset->sig[0];
- setv.sigbits[1] = (oldset->sig[0] >> 32);
- if (_NSIG_WORDS >= 2) {
- setv.sigbits[2] = oldset->sig[1];
- setv.sigbits[3] = (oldset->sig[1] >> 32);
- err |= __copy_to_user(&uc->sigmask, &setv, sizeof(svr4_sigset_t));
- } else
- err |= __copy_to_user(&uc->sigmask, &setv,
- 2 * sizeof(unsigned int));
-
- /* Store registers */
- if (test_thread_flag(TIF_32BIT)) {
- regs->tpc &= 0xffffffff;
- regs->tnpc &= 0xffffffff;
- }
- err |= __put_user(regs->tpc, &((*gr)[SVR4_PC]));
- err |= __put_user(regs->tnpc, &((*gr)[SVR4_NPC]));
- psr = tstate_to_psr(regs->tstate);
- if (current_thread_info()->fpsaved[0] & FPRS_FEF)
- psr |= PSR_EF;
- err |= __put_user(psr, &((*gr)[SVR4_PSR]));
- err |= __put_user(regs->y, &((*gr)[SVR4_Y]));
-
- /* Copy g[1..7] and o[0..7] registers */
- for (i = 0; i < 7; i++)
- err |= __put_user(regs->u_regs[UREG_G1+i], (&(*gr)[SVR4_G1])+i);
- for (i = 0; i < 8; i++)
- err |= __put_user(regs->u_regs[UREG_I0+i], (&(*gr)[SVR4_O0])+i);
-
- /* Setup sigaltstack */
- err |= __put_user(current->sas_ss_sp, &uc->stack.sp);
- err |= __put_user(sas_ss_flags(regs->u_regs[UREG_FP]), &uc->stack.flags);
- err |= __put_user(current->sas_ss_size, &uc->stack.size);
-
- /* Save the currently window file: */
-
- /* 1. Link sfp->uc->gwins to our windows */
- err |= __put_user(ptr_to_compat(gw), &mc->gwin);
-
- /* 2. Number of windows to restore at setcontext (): */
- err |= __put_user(get_thread_wsaved(), &gw->count);
-
- /* 3. We just pay attention to the gw->count field on setcontext */
- set_thread_wsaved(0); /* So process is allowed to execute. */
-
- /* Setup the signal information. Solaris expects a bunch of
- * information to be passed to the signal handler, we don't provide
- * that much currently, should use siginfo.
- */
- err |= __put_user(signr, &si->siginfo.signo);
- err |= __put_user(SVR4_SINOINFO, &si->siginfo.code);
- if (err)
- goto sigsegv;
-
- regs->u_regs[UREG_FP] = (unsigned long) sfp;
- regs->tpc = (unsigned long) sa->sa_handler;
- regs->tnpc = (regs->tpc + 4);
- if (test_thread_flag(TIF_32BIT)) {
- regs->tpc &= 0xffffffff;
- regs->tnpc &= 0xffffffff;
- }
-
- /* Arguments passed to signal handler */
- if (regs->u_regs[14]){
- struct reg_window32 __user *rw = (struct reg_window32 __user *)
- (regs->u_regs[14] & 0x00000000ffffffffUL);
-
- err |= __put_user(signr, &rw->ins[0]);
- err |= __put_user((u64)si, &rw->ins[1]);
- err |= __put_user((u64)uc, &rw->ins[2]);
- err |= __put_user((u64)sfp, &rw->ins[6]); /* frame pointer */
- if (err)
- goto sigsegv;
-
- regs->u_regs[UREG_I0] = signr;
- regs->u_regs[UREG_I1] = (u32)(u64) si;
- regs->u_regs[UREG_I2] = (u32)(u64) uc;
- }
- return;
-
-sigsegv:
- force_sigsegv(signr, current);
-}
-
-asmlinkage int
-svr4_getcontext(svr4_ucontext_t __user *uc, struct pt_regs *regs)
-{
- svr4_gregset_t __user *gr;
- svr4_mcontext_t __user *mc;
- svr4_sigset_t setv;
- int i, err;
- u32 psr;
-
- synchronize_user_stack();
- save_and_clear_fpu();
-
- if (get_thread_wsaved())
- do_exit(SIGSEGV);
-
- err = clear_user(uc, sizeof(*uc));
-
- /* Setup convenience variables */
- mc = &uc->mcontext;
- gr = &mc->greg;
-
- setv.sigbits[0] = current->blocked.sig[0];
- setv.sigbits[1] = (current->blocked.sig[0] >> 32);
- if (_NSIG_WORDS >= 2) {
- setv.sigbits[2] = current->blocked.sig[1];
- setv.sigbits[3] = (current->blocked.sig[1] >> 32);
- err |= __copy_to_user(&uc->sigmask, &setv, sizeof(svr4_sigset_t));
- } else
- err |= __copy_to_user(&uc->sigmask, &setv, 2 * sizeof(unsigned));
-
- /* Store registers */
- if (test_thread_flag(TIF_32BIT)) {
- regs->tpc &= 0xffffffff;
- regs->tnpc &= 0xffffffff;
- }
- err |= __put_user(regs->tpc, &uc->mcontext.greg[SVR4_PC]);
- err |= __put_user(regs->tnpc, &uc->mcontext.greg[SVR4_NPC]);
-
- psr = tstate_to_psr(regs->tstate) & ~PSR_EF;
- if (current_thread_info()->fpsaved[0] & FPRS_FEF)
- psr |= PSR_EF;
- err |= __put_user(psr, &uc->mcontext.greg[SVR4_PSR]);
-
- err |= __put_user(regs->y, &uc->mcontext.greg[SVR4_Y]);
-
- /* Copy g[1..7] and o[0..7] registers */
- for (i = 0; i < 7; i++)
- err |= __put_user(regs->u_regs[UREG_G1+i], (&(*gr)[SVR4_G1])+i);
- for (i = 0; i < 8; i++)
- err |= __put_user(regs->u_regs[UREG_I0+i], (&(*gr)[SVR4_O0])+i);
-
- /* Setup sigaltstack */
- err |= __put_user(current->sas_ss_sp, &uc->stack.sp);
- err |= __put_user(sas_ss_flags(regs->u_regs[UREG_FP]), &uc->stack.flags);
- err |= __put_user(current->sas_ss_size, &uc->stack.size);
-
- /* The register file is not saved
- * we have already stuffed all of it with sync_user_stack
- */
- return (err ? -EFAULT : 0);
-}
-
-
-/* Set the context for a svr4 application, this is Solaris way to sigreturn */
-asmlinkage int svr4_setcontext(svr4_ucontext_t __user *c, struct pt_regs *regs)
-{
- svr4_gregset_t __user *gr;
- mm_segment_t old_fs;
- u32 pc, npc, psr, u_ss_sp;
- sigset_t set;
- svr4_sigset_t setv;
- int i, err;
- stack_t st;
-
- /* Fixme: restore windows, or is this already taken care of in
- * svr4_setup_frame when sync_user_windows is done?
- */
- flush_user_windows();
-
- if (get_thread_wsaved())
- goto sigsegv;
-
- if (((unsigned long) c) & 3){
- printk("Unaligned structure passed\n");
- goto sigsegv;
- }
-
- if (!__access_ok(c, sizeof(*c))) {
- /* Miguel, add nice debugging msg _here_. ;-) */
- goto sigsegv;
- }
-
- /* Check for valid PC and nPC */
- gr = &c->mcontext.greg;
- err = __get_user(pc, &((*gr)[SVR4_PC]));
- err |= __get_user(npc, &((*gr)[SVR4_NPC]));
- if ((pc | npc) & 3)
- goto sigsegv;
-
- /* Retrieve information from passed ucontext */
- /* note that nPC is ored a 1, this is used to inform entry.S */
- /* that we don't want it to mess with our PC and nPC */
-
- err |= copy_from_user(&setv, &c->sigmask, sizeof(svr4_sigset_t));
- set.sig[0] = setv.sigbits[0] | (((long)setv.sigbits[1]) << 32);
- if (_NSIG_WORDS >= 2)
- set.sig[1] = setv.sigbits[2] | (((long)setv.sigbits[3]) << 32);
-
- err |= __get_user(u_ss_sp, &c->stack.sp);
- st.ss_sp = compat_ptr(u_ss_sp);
- err |= __get_user(st.ss_flags, &c->stack.flags);
- err |= __get_user(st.ss_size, &c->stack.size);
- if (err)
- goto sigsegv;
-
- /* It is more difficult to avoid calling this function than to
- call it and ignore errors. */
- old_fs = get_fs();
- set_fs(KERNEL_DS);
- do_sigaltstack((stack_t __user *) &st, NULL, regs->u_regs[UREG_I6]);
- set_fs(old_fs);
-
- sigdelsetmask(&set, ~_BLOCKABLE);
- spin_lock_irq(¤t->sighand->siglock);
- current->blocked = set;
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- regs->tpc = pc;
- regs->tnpc = npc | 1;
- if (test_thread_flag(TIF_32BIT)) {
- regs->tpc &= 0xffffffff;
- regs->tnpc &= 0xffffffff;
- }
- err |= __get_user(regs->y, &((*gr)[SVR4_Y]));
- err |= __get_user(psr, &((*gr)[SVR4_PSR]));
- regs->tstate &= ~(TSTATE_ICC|TSTATE_XCC);
- regs->tstate |= psr_to_tstate_icc(psr);
-
- /* Restore g[1..7] and o[0..7] registers */
- for (i = 0; i < 7; i++)
- err |= __get_user(regs->u_regs[UREG_G1+i], (&(*gr)[SVR4_G1])+i);
- for (i = 0; i < 8; i++)
- err |= __get_user(regs->u_regs[UREG_I0+i], (&(*gr)[SVR4_O0])+i);
- if (err)
- goto sigsegv;
-
- return -EINTR;
-sigsegv:
- return -EFAULT;
-}
-
static void setup_rt_frame32(struct k_sigaction *ka, struct pt_regs *regs,
unsigned long signr, sigset_t *oldset,
siginfo_t *info)
static inline void handle_signal32(unsigned long signr, struct k_sigaction *ka,
siginfo_t *info,
- sigset_t *oldset, struct pt_regs *regs,
- int svr4_signal)
+ sigset_t *oldset, struct pt_regs *regs)
{
- if (svr4_signal)
- setup_svr4_frame32(&ka->sa, regs->tpc, regs->tnpc,
- regs, signr, oldset);
- else {
- if (ka->sa.sa_flags & SA_SIGINFO)
- setup_rt_frame32(ka, regs, signr, oldset, info);
- else if (test_thread_flag(TIF_NEWSIGNALS))
- new_setup_frame32(ka, regs, signr, oldset);
- else
- setup_frame32(&ka->sa, regs, signr, oldset, info);
- }
+ if (ka->sa.sa_flags & SA_SIGINFO)
+ setup_rt_frame32(ka, regs, signr, oldset, info);
+ else if (test_thread_flag(TIF_NEWSIGNALS))
+ new_setup_frame32(ka, regs, signr, oldset);
+ else
+ setup_frame32(&ka->sa, regs, signr, oldset, info);
spin_lock_irq(¤t->sighand->siglock);
sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
if (!(ka->sa.sa_flags & SA_NOMASK))
struct signal_deliver_cookie cookie;
struct k_sigaction ka;
int signr;
- int svr4_signal = current->personality == PER_SVR4;
cookie.restart_syscall = restart_syscall;
cookie.orig_i0 = orig_i0;
if (signr > 0) {
if (cookie.restart_syscall)
syscall_restart32(orig_i0, regs, &ka.sa);
- handle_signal32(signr, &ka, &info, oldset,
- regs, svr4_signal);
+ handle_signal32(signr, &ka, &info, oldset, regs);
/* a signal was successfully delivered; the saved
* sigmask will have been stored in the signal frame,
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/idprom.h>
-#include <asm/svr4.h>
#include <asm/elf.h>
#include <asm/head.h>
#include <asm/smp.h>
#include <asm/mostek.h>
#include <asm/ptrace.h>
-#include <asm/user.h>
#include <asm/uaccess.h>
#include <asm/checksum.h>
#include <asm/fpumacro.h>
extern void linux_sparc_syscall(void);
extern void rtrap(void);
extern void show_regs(struct pt_regs *);
-extern void solaris_syscall(void);
extern void syscall_trace(struct pt_regs *, int);
-extern u32 sunos_sys_table[], sys_call_table32[];
-extern void tl0_solaris(void);
extern void sys_sigsuspend(void);
-extern int svr4_getcontext(svr4_ucontext_t *uc, struct pt_regs *regs);
-extern int svr4_setcontext(svr4_ucontext_t *uc, struct pt_regs *regs);
extern int compat_sys_ioctl(unsigned int fd, unsigned int cmd, u32 arg);
extern int (*handle_mathemu)(struct pt_regs *, struct fpustate *);
extern long sparc32_open(const char __user * filename, int flags, int mode);
extern int dump_fpu (struct pt_regs * regs, elf_fpregset_t * fpregs);
-extern unsigned int sys_call_table[];
-
extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *);
extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *,
unsigned long *);
/* I/O device mmaping on Sparc64. */
EXPORT_SYMBOL(io_remap_pfn_range);
-#if defined(CONFIG_COMPAT) && defined(CONFIG_NET)
-/* Solaris/SunOS binary compatibility */
-EXPORT_SYMBOL(verify_compat_iovec);
-#endif
-
EXPORT_SYMBOL(dump_fpu);
EXPORT_SYMBOL(put_fs_struct);
EXPORT_SYMBOL(__strlen_user);
EXPORT_SYMBOL(__strnlen_user);
-#ifdef CONFIG_SOLARIS_EMUL_MODULE
-EXPORT_SYMBOL(linux_sparc_syscall);
-EXPORT_SYMBOL(rtrap);
-EXPORT_SYMBOL(show_regs);
-EXPORT_SYMBOL(solaris_syscall);
-EXPORT_SYMBOL(syscall_trace);
-EXPORT_SYMBOL(sunos_sys_table);
-EXPORT_SYMBOL(sys_call_table32);
-EXPORT_SYMBOL(tl0_solaris);
-EXPORT_SYMBOL(sys_sigsuspend);
-EXPORT_SYMBOL(sys_getppid);
-EXPORT_SYMBOL(sys_getpid);
-EXPORT_SYMBOL(sys_geteuid);
-EXPORT_SYMBOL(sys_getuid);
-EXPORT_SYMBOL(sys_getegid);
-EXPORT_SYMBOL(sysctl_nr_open);
-EXPORT_SYMBOL(sys_getgid);
-EXPORT_SYMBOL(svr4_getcontext);
-EXPORT_SYMBOL(svr4_setcontext);
-EXPORT_SYMBOL(compat_sys_ioctl);
-EXPORT_SYMBOL(sys_ioctl);
-EXPORT_SYMBOL(sparc32_open);
-#endif
-
/* Special internal versions of library functions. */
EXPORT_SYMBOL(_clear_page);
EXPORT_SYMBOL(clear_user_page);
/* for ns8703 */
EXPORT_SYMBOL(ns87303_lock);
-/* for solaris compat module */
-EXPORT_SYMBOL_GPL(sys_call_table);
-
EXPORT_SYMBOL(tick_ops);
EXPORT_SYMBOL(xor_vis_2);
+++ /dev/null
-/* $Id: sunos_ioctl32.c,v 1.11 2000/07/30 23:12:24 davem Exp $
- * sunos_ioctl32.c: SunOS ioctl compatibility on sparc64.
- *
- * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
- * Copyright (C) 1995, 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#include <asm/uaccess.h>
-
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/termios.h>
-#include <linux/tty.h>
-#include <linux/ioctl.h>
-#include <linux/route.h>
-#include <linux/sockios.h>
-#include <linux/if.h>
-#include <linux/netdevice.h>
-#include <linux/if_arp.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/syscalls.h>
-#include <linux/compat.h>
-
-#define SUNOS_NR_OPEN 256
-
-struct rtentry32 {
- u32 rt_pad1;
- struct sockaddr rt_dst; /* target address */
- struct sockaddr rt_gateway; /* gateway addr (RTF_GATEWAY) */
- struct sockaddr rt_genmask; /* target network mask (IP) */
- unsigned short rt_flags;
- short rt_pad2;
- u32 rt_pad3;
- unsigned char rt_tos;
- unsigned char rt_class;
- short rt_pad4;
- short rt_metric; /* +1 for binary compatibility! */
- /* char * */ u32 rt_dev; /* forcing the device at add */
- u32 rt_mtu; /* per route MTU/Window */
- u32 rt_window; /* Window clamping */
- unsigned short rt_irtt; /* Initial RTT */
-
-};
-
-struct ifmap32 {
- u32 mem_start;
- u32 mem_end;
- unsigned short base_addr;
- unsigned char irq;
- unsigned char dma;
- unsigned char port;
-};
-
-struct ifreq32 {
-#define IFHWADDRLEN 6
-#define IFNAMSIZ 16
- union {
- char ifrn_name[IFNAMSIZ]; /* if name, e.g. "en0" */
- } ifr_ifrn;
- union {
- struct sockaddr ifru_addr;
- struct sockaddr ifru_dstaddr;
- struct sockaddr ifru_broadaddr;
- struct sockaddr ifru_netmask;
- struct sockaddr ifru_hwaddr;
- short ifru_flags;
- int ifru_ivalue;
- int ifru_mtu;
- struct ifmap32 ifru_map;
- char ifru_slave[IFNAMSIZ]; /* Just fits the size */
- compat_caddr_t ifru_data;
- } ifr_ifru;
-};
-
-struct ifconf32 {
- int ifc_len; /* size of buffer */
- compat_caddr_t ifcbuf;
-};
-
-extern asmlinkage int compat_sys_ioctl(unsigned int, unsigned int, u32);
-
-asmlinkage int sunos_ioctl (int fd, u32 cmd, u32 arg)
-{
- int ret = -EBADF;
-
- if(fd >= SUNOS_NR_OPEN)
- goto out;
- if(!fcheck(fd))
- goto out;
-
- if(cmd == TIOCSETD) {
- mm_segment_t old_fs = get_fs();
- int __user *p;
- int ntty = N_TTY;
- int tmp;
-
- p = (int __user *) (unsigned long) arg;
- ret = -EFAULT;
- if(get_user(tmp, p))
- goto out;
- if(tmp == 2) {
- set_fs(KERNEL_DS);
- ret = sys_ioctl(fd, cmd, (unsigned long) &ntty);
- set_fs(old_fs);
- ret = (ret == -EINVAL ? -EOPNOTSUPP : ret);
- goto out;
- }
- }
- if(cmd == TIOCNOTTY) {
- ret = sys_setsid();
- goto out;
- }
- switch(cmd) {
- case _IOW('r', 10, struct rtentry32):
- ret = compat_sys_ioctl(fd, SIOCADDRT, arg);
- goto out;
- case _IOW('r', 11, struct rtentry32):
- ret = compat_sys_ioctl(fd, SIOCDELRT, arg);
- goto out;
-
- case _IOW('i', 12, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCSIFADDR, arg);
- goto out;
- case _IOWR('i', 13, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCGIFADDR, arg);
- goto out;
- case _IOW('i', 14, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCSIFDSTADDR, arg);
- goto out;
- case _IOWR('i', 15, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCGIFDSTADDR, arg);
- goto out;
- case _IOW('i', 16, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCSIFFLAGS, arg);
- goto out;
- case _IOWR('i', 17, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCGIFFLAGS, arg);
- goto out;
- case _IOW('i', 18, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCSIFMEM, arg);
- goto out;
- case _IOWR('i', 19, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCGIFMEM, arg);
- goto out;
-
- case _IOWR('i', 20, struct ifconf32):
- ret = compat_sys_ioctl(fd, SIOCGIFCONF, arg);
- goto out;
-
- case _IOW('i', 21, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCSIFMTU, arg);
- goto out;
-
- case _IOWR('i', 22, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCGIFMTU, arg);
- goto out;
-
- case _IOWR('i', 23, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCGIFBRDADDR, arg);
- goto out;
- case _IOW('i', 24, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCSIFBRDADDR, arg);
- goto out;
- case _IOWR('i', 25, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCGIFNETMASK, arg);
- goto out;
- case _IOW('i', 26, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCSIFNETMASK, arg);
- goto out;
- case _IOWR('i', 27, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCGIFMETRIC, arg);
- goto out;
- case _IOW('i', 28, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCSIFMETRIC, arg);
- goto out;
-
- case _IOW('i', 30, struct arpreq):
- ret = compat_sys_ioctl(fd, SIOCSARP, arg);
- goto out;
- case _IOWR('i', 31, struct arpreq):
- ret = compat_sys_ioctl(fd, SIOCGARP, arg);
- goto out;
- case _IOW('i', 32, struct arpreq):
- ret = compat_sys_ioctl(fd, SIOCDARP, arg);
- goto out;
-
- case _IOW('i', 40, struct ifreq32): /* SIOCUPPER */
- case _IOW('i', 41, struct ifreq32): /* SIOCLOWER */
- case _IOW('i', 44, struct ifreq32): /* SIOCSETSYNC */
- case _IOW('i', 45, struct ifreq32): /* SIOCGETSYNC */
- case _IOW('i', 46, struct ifreq32): /* SIOCSSDSTATS */
- case _IOW('i', 47, struct ifreq32): /* SIOCSSESTATS */
- case _IOW('i', 48, struct ifreq32): /* SIOCSPROMISC */
- ret = -EOPNOTSUPP;
- goto out;
-
- case _IOW('i', 49, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCADDMULTI, arg);
- goto out;
- case _IOW('i', 50, struct ifreq32):
- ret = compat_sys_ioctl(fd, SIOCDELMULTI, arg);
- goto out;
-
- /* FDDI interface ioctls, unsupported. */
-
- case _IOW('i', 51, struct ifreq32): /* SIOCFDRESET */
- case _IOW('i', 52, struct ifreq32): /* SIOCFDSLEEP */
- case _IOW('i', 53, struct ifreq32): /* SIOCSTRTFMWAR */
- case _IOW('i', 54, struct ifreq32): /* SIOCLDNSTRTFW */
- case _IOW('i', 55, struct ifreq32): /* SIOCGETFDSTAT */
- case _IOW('i', 56, struct ifreq32): /* SIOCFDNMIINT */
- case _IOW('i', 57, struct ifreq32): /* SIOCFDEXUSER */
- case _IOW('i', 58, struct ifreq32): /* SIOCFDGNETMAP */
- case _IOW('i', 59, struct ifreq32): /* SIOCFDGIOCTL */
- printk("FDDI ioctl, returning EOPNOTSUPP\n");
- ret = -EOPNOTSUPP;
- goto out;
-
- case _IOW('t', 125, int):
- /* More stupid tty sunos ioctls, just
- * say it worked.
- */
- ret = 0;
- goto out;
-
- /* Non posix grp */
- case _IOW('t', 118, int): {
- int oldval, newval, __user *ptr;
-
- cmd = TIOCSPGRP;
- ptr = (int __user *) (unsigned long) arg;
- ret = -EFAULT;
- if(get_user(oldval, ptr))
- goto out;
- ret = compat_sys_ioctl(fd, cmd, arg);
- __get_user(newval, ptr);
- if(newval == -1) {
- __put_user(oldval, ptr);
- ret = -EIO;
- }
- if(ret == -ENOTTY)
- ret = -EIO;
- goto out;
- }
-
- case _IOR('t', 119, int): {
- int oldval, newval, __user *ptr;
-
- cmd = TIOCGPGRP;
- ptr = (int __user *) (unsigned long) arg;
- ret = -EFAULT;
- if(get_user(oldval, ptr))
- goto out;
- ret = compat_sys_ioctl(fd, cmd, arg);
- __get_user(newval, ptr);
- if(newval == -1) {
- __put_user(oldval, ptr);
- ret = -EIO;
- }
- if(ret == -ENOTTY)
- ret = -EIO;
- goto out;
- }
- };
-
- ret = compat_sys_ioctl(fd, cmd, arg);
- /* so stupid... */
- ret = (ret == -EINVAL ? -EOPNOTSUPP : ret);
-out:
- return ret;
-}
return err;
}
-asmlinkage long solaris_syscall(struct pt_regs *regs)
-{
- static int count;
-
- regs->tpc = regs->tnpc;
- regs->tnpc += 4;
- if (test_thread_flag(TIF_32BIT)) {
- regs->tpc &= 0xffffffff;
- regs->tnpc &= 0xffffffff;
- }
- if (++count <= 5) {
- printk ("For Solaris binary emulation you need solaris module loaded\n");
- show_regs (regs);
- }
- send_sig(SIGSEGV, current, 1);
-
- return -ENOSYS;
-}
-
-#ifndef CONFIG_SUNOS_EMUL
-asmlinkage long sunos_syscall(struct pt_regs *regs)
-{
- static int count;
-
- regs->tpc = regs->tnpc;
- regs->tnpc += 4;
- if (test_thread_flag(TIF_32BIT)) {
- regs->tpc &= 0xffffffff;
- regs->tnpc &= 0xffffffff;
- }
- if (++count <= 20)
- printk ("SunOS binary emulation not compiled in\n");
- force_sig(SIGSEGV, current);
-
- return -ENOSYS;
-}
-#endif
-
asmlinkage long sys_utrap_install(utrap_entry_t type,
utrap_handler_t new_p,
utrap_handler_t new_d,
#include <asm/types.h>
#include <asm/uaccess.h>
#include <asm/fpumacro.h>
-#include <asm/semaphore.h>
#include <asm/mmu_context.h>
#include <asm/compat_signal.h>
+++ /dev/null
-/* $Id: sys_sunos32.c,v 1.64 2002/02/09 19:49:31 davem Exp $
- * sys_sunos32.c: SunOS binary compatibility layer on sparc64.
- *
- * Copyright (C) 1995, 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
- *
- * Based upon preliminary work which is:
- *
- * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu)
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/capability.h>
-#include <linux/compat.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/resource.h>
-#include <linux/ipc.h>
-#include <linux/shm.h>
-#include <linux/msg.h>
-#include <linux/sem.h>
-#include <linux/signal.h>
-#include <linux/uio.h>
-#include <linux/utsname.h>
-#include <linux/major.h>
-#include <linux/stat.h>
-#include <linux/slab.h>
-#include <linux/pagemap.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-#include <linux/syscalls.h>
-
-#include <asm/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/pconf.h>
-#include <asm/idprom.h> /* for gethostid() */
-#include <asm/unistd.h>
-#include <asm/system.h>
-#include <asm/compat_signal.h>
-
-/* For the nfs mount emulation */
-#include <linux/socket.h>
-#include <linux/in.h>
-#include <linux/nfs.h>
-#include <linux/nfs2.h>
-#include <linux/nfs_mount.h>
-
-/* for sunos_select */
-#include <linux/time.h>
-#include <linux/personality.h>
-
-/* For SOCKET_I */
-#include <net/sock.h>
-#include <net/compat.h>
-
-#define SUNOS_NR_OPEN 256
-
-asmlinkage u32 sunos_mmap(u32 addr, u32 len, u32 prot, u32 flags, u32 fd, u32 off)
-{
- struct file *file = NULL;
- unsigned long retval, ret_type;
-
- if (flags & MAP_NORESERVE) {
- static int cnt;
- if (cnt++ < 10)
- printk("%s: unimplemented SunOS MAP_NORESERVE mmap() flag\n",
- current->comm);
- flags &= ~MAP_NORESERVE;
- }
- retval = -EBADF;
- if (!(flags & MAP_ANONYMOUS)) {
- struct inode * inode;
- if (fd >= SUNOS_NR_OPEN)
- goto out;
- file = fget(fd);
- if (!file)
- goto out;
- inode = file->f_path.dentry->d_inode;
- if (imajor(inode) == MEM_MAJOR && iminor(inode) == 5) {
- flags |= MAP_ANONYMOUS;
- fput(file);
- file = NULL;
- }
- }
-
- retval = -EINVAL;
- if (!(flags & MAP_FIXED))
- addr = 0;
- else if (len > 0xf0000000 || addr > 0xf0000000 - len)
- goto out_putf;
- ret_type = flags & _MAP_NEW;
- flags &= ~_MAP_NEW;
-
- flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
- down_write(¤t->mm->mmap_sem);
- retval = do_mmap(file,
- (unsigned long) addr, (unsigned long) len,
- (unsigned long) prot, (unsigned long) flags,
- (unsigned long) off);
- up_write(¤t->mm->mmap_sem);
- if (!ret_type)
- retval = ((retval < 0xf0000000) ? 0 : retval);
-out_putf:
- if (file)
- fput(file);
-out:
- return (u32) retval;
-}
-
-asmlinkage int sunos_mctl(u32 addr, u32 len, int function, u32 arg)
-{
- return 0;
-}
-
-asmlinkage int sunos_brk(u32 baddr)
-{
- int freepages, retval = -ENOMEM;
- unsigned long rlim;
- unsigned long newbrk, oldbrk, brk = (unsigned long) baddr;
-
- down_write(¤t->mm->mmap_sem);
- if (brk < current->mm->end_code)
- goto out;
- newbrk = PAGE_ALIGN(brk);
- oldbrk = PAGE_ALIGN(current->mm->brk);
- retval = 0;
- if (oldbrk == newbrk) {
- current->mm->brk = brk;
- goto out;
- }
- /* Always allow shrinking brk. */
- if (brk <= current->mm->brk) {
- current->mm->brk = brk;
- do_munmap(current->mm, newbrk, oldbrk-newbrk);
- goto out;
- }
- /* Check against rlimit and stack.. */
- retval = -ENOMEM;
- rlim = current->signal->rlim[RLIMIT_DATA].rlim_cur;
- if (rlim >= RLIM_INFINITY)
- rlim = ~0;
- if (brk - current->mm->end_code > rlim)
- goto out;
- /* Check against existing mmap mappings. */
- if (find_vma_intersection(current->mm, oldbrk, newbrk+PAGE_SIZE))
- goto out;
- /* stupid algorithm to decide if we have enough memory: while
- * simple, it hopefully works in most obvious cases.. Easy to
- * fool it, but this should catch most mistakes.
- */
- freepages = global_page_state(NR_FILE_PAGES);
- freepages >>= 1;
- freepages += nr_free_pages();
- freepages += nr_swap_pages;
- freepages -= num_physpages >> 4;
- freepages -= (newbrk-oldbrk) >> PAGE_SHIFT;
- if (freepages < 0)
- goto out;
- /* Ok, we have probably got enough memory - let it rip. */
- current->mm->brk = brk;
- do_brk(oldbrk, newbrk-oldbrk);
- retval = 0;
-out:
- up_write(¤t->mm->mmap_sem);
- return retval;
-}
-
-asmlinkage u32 sunos_sbrk(int increment)
-{
- int error, oldbrk;
-
- /* This should do it hopefully... */
- oldbrk = (int)current->mm->brk;
- error = sunos_brk(((int) current->mm->brk) + increment);
- if (!error)
- error = oldbrk;
- return error;
-}
-
-asmlinkage u32 sunos_sstk(int increment)
-{
- printk("%s: Call to sunos_sstk(increment<%d>) is unsupported\n",
- current->comm, increment);
-
- return (u32)-1;
-}
-
-/* Give hints to the kernel as to what paging strategy to use...
- * Completely bogus, don't remind me.
- */
-#define VA_NORMAL 0 /* Normal vm usage expected */
-#define VA_ABNORMAL 1 /* Abnormal/random vm usage probable */
-#define VA_SEQUENTIAL 2 /* Accesses will be of a sequential nature */
-#define VA_INVALIDATE 3 /* Page table entries should be flushed ??? */
-static char *vstrings[] = {
- "VA_NORMAL",
- "VA_ABNORMAL",
- "VA_SEQUENTIAL",
- "VA_INVALIDATE",
-};
-
-asmlinkage void sunos_vadvise(u32 strategy)
-{
- static int count;
-
- /* I wanna see who uses this... */
- if (count++ < 5)
- printk("%s: Advises us to use %s paging strategy\n",
- current->comm,
- strategy <= 3 ? vstrings[strategy] : "BOGUS");
-}
-
-/* This just wants the soft limit (ie. rlim_cur element) of the RLIMIT_NOFILE
- * resource limit and is for backwards compatibility with older sunos
- * revs.
- */
-asmlinkage int sunos_getdtablesize(void)
-{
- return SUNOS_NR_OPEN;
-}
-
-
-#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
-
-asmlinkage u32 sunos_sigblock(u32 blk_mask)
-{
- u32 old;
-
- spin_lock_irq(¤t->sighand->siglock);
- old = (u32) current->blocked.sig[0];
- current->blocked.sig[0] |= (blk_mask & _BLOCKABLE);
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- return old;
-}
-
-asmlinkage u32 sunos_sigsetmask(u32 newmask)
-{
- u32 retval;
-
- spin_lock_irq(¤t->sighand->siglock);
- retval = (u32) current->blocked.sig[0];
- current->blocked.sig[0] = (newmask & _BLOCKABLE);
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- return retval;
-}
-
-/* SunOS getdents is very similar to the newer Linux (iBCS2 compliant) */
-/* getdents system call, the format of the structure just has a different */
-/* layout (d_off+d_ino instead of d_ino+d_off) */
-struct sunos_dirent {
- s32 d_off;
- u32 d_ino;
- u16 d_reclen;
- u16 d_namlen;
- char d_name[1];
-};
-
-struct sunos_dirent_callback {
- struct sunos_dirent __user *curr;
- struct sunos_dirent __user *previous;
- int count;
- int error;
-};
-
-#define NAME_OFFSET(de) ((int) ((de)->d_name - (char __user *) (de)))
-#define ROUND_UP(x) (((x)+sizeof(s32)-1) & ~(sizeof(s32)-1))
-
-static int sunos_filldir(void * __buf, const char * name, int namlen,
- loff_t offset, ino_t ino, unsigned int d_type)
-{
- struct sunos_dirent __user *dirent;
- struct sunos_dirent_callback * buf = (struct sunos_dirent_callback *) __buf;
- int reclen = ROUND_UP(NAME_OFFSET(dirent) + namlen + 1);
- u32 d_ino;
-
- buf->error = -EINVAL; /* only used if we fail.. */
- if (reclen > buf->count)
- return -EINVAL;
- d_ino = ino;
- if (sizeof(d_ino) < sizeof(ino) && d_ino != ino)
- return -EOVERFLOW;
- dirent = buf->previous;
- if (dirent)
- put_user(offset, &dirent->d_off);
- dirent = buf->curr;
- buf->previous = dirent;
- put_user(d_ino, &dirent->d_ino);
- put_user(namlen, &dirent->d_namlen);
- put_user(reclen, &dirent->d_reclen);
- if (copy_to_user(dirent->d_name, name, namlen))
- return -EFAULT;
- put_user(0, dirent->d_name + namlen);
- dirent = (void __user *) dirent + reclen;
- buf->curr = dirent;
- buf->count -= reclen;
- return 0;
-}
-
-asmlinkage int sunos_getdents(unsigned int fd, void __user *dirent, int cnt)
-{
- struct file * file;
- struct sunos_dirent __user *lastdirent;
- struct sunos_dirent_callback buf;
- int error = -EBADF;
-
- if (fd >= SUNOS_NR_OPEN)
- goto out;
-
- file = fget(fd);
- if (!file)
- goto out;
-
- error = -EINVAL;
- if (cnt < (sizeof(struct sunos_dirent) + 255))
- goto out_putf;
-
- buf.curr = (struct sunos_dirent __user *) dirent;
- buf.previous = NULL;
- buf.count = cnt;
- buf.error = 0;
-
- error = vfs_readdir(file, sunos_filldir, &buf);
- if (error < 0)
- goto out_putf;
-
- lastdirent = buf.previous;
- error = buf.error;
- if (lastdirent) {
- put_user(file->f_pos, &lastdirent->d_off);
- error = cnt - buf.count;
- }
-
-out_putf:
- fput(file);
-out:
- return error;
-}
-
-/* Old sunos getdirentries, severely broken compatibility stuff here. */
-struct sunos_direntry {
- u32 d_ino;
- u16 d_reclen;
- u16 d_namlen;
- char d_name[1];
-};
-
-struct sunos_direntry_callback {
- struct sunos_direntry __user *curr;
- struct sunos_direntry __user *previous;
- int count;
- int error;
-};
-
-static int sunos_filldirentry(void * __buf, const char * name, int namlen,
- loff_t offset, ino_t ino, unsigned int d_type)
-{
- struct sunos_direntry __user *dirent;
- struct sunos_direntry_callback * buf =
- (struct sunos_direntry_callback *) __buf;
- int reclen = ROUND_UP(NAME_OFFSET(dirent) + namlen + 1);
- u32 d_ino;
-
- buf->error = -EINVAL; /* only used if we fail.. */
- if (reclen > buf->count)
- return -EINVAL;
- d_ino = ino;
- if (sizeof(d_ino) < sizeof(ino) && d_ino != ino)
- return -EOVERFLOW;
- dirent = buf->previous;
- dirent = buf->curr;
- buf->previous = dirent;
- put_user(d_ino, &dirent->d_ino);
- put_user(namlen, &dirent->d_namlen);
- put_user(reclen, &dirent->d_reclen);
- if (copy_to_user(dirent->d_name, name, namlen))
- return -EFAULT;
- put_user(0, dirent->d_name + namlen);
- dirent = (void __user *) dirent + reclen;
- buf->curr = dirent;
- buf->count -= reclen;
- return 0;
-}
-
-asmlinkage int sunos_getdirentries(unsigned int fd,
- void __user *dirent,
- int cnt,
- unsigned int __user *basep)
-{
- struct file * file;
- struct sunos_direntry __user *lastdirent;
- int error = -EBADF;
- struct sunos_direntry_callback buf;
-
- if (fd >= SUNOS_NR_OPEN)
- goto out;
-
- file = fget(fd);
- if (!file)
- goto out;
-
- error = -EINVAL;
- if (cnt < (sizeof(struct sunos_direntry) + 255))
- goto out_putf;
-
- buf.curr = (struct sunos_direntry __user *) dirent;
- buf.previous = NULL;
- buf.count = cnt;
- buf.error = 0;
-
- error = vfs_readdir(file, sunos_filldirentry, &buf);
- if (error < 0)
- goto out_putf;
-
- lastdirent = buf.previous;
- error = buf.error;
- if (lastdirent) {
- put_user(file->f_pos, basep);
- error = cnt - buf.count;
- }
-
-out_putf:
- fput(file);
-out:
- return error;
-}
-
-struct sunos_utsname {
- char sname[9];
- char nname[9];
- char nnext[56];
- char rel[9];
- char ver[9];
- char mach[9];
-};
-
-asmlinkage int sunos_uname(struct sunos_utsname __user *name)
-{
- int ret;
-
- down_read(&uts_sem);
- ret = copy_to_user(&name->sname[0], &utsname()->sysname[0],
- sizeof(name->sname) - 1);
- ret |= copy_to_user(&name->nname[0], &utsname()->nodename[0],
- sizeof(name->nname) - 1);
- ret |= put_user('\0', &name->nname[8]);
- ret |= copy_to_user(&name->rel[0], &utsname()->release[0],
- sizeof(name->rel) - 1);
- ret |= copy_to_user(&name->ver[0], &utsname()->version[0],
- sizeof(name->ver) - 1);
- ret |= copy_to_user(&name->mach[0], &utsname()->machine[0],
- sizeof(name->mach) - 1);
- up_read(&uts_sem);
- return (ret ? -EFAULT : 0);
-}
-
-asmlinkage int sunos_nosys(void)
-{
- struct pt_regs *regs;
- siginfo_t info;
- static int cnt;
-
- regs = current_thread_info()->kregs;
- if (test_thread_flag(TIF_32BIT)) {
- regs->tpc &= 0xffffffff;
- regs->tnpc &= 0xffffffff;
- }
- info.si_signo = SIGSYS;
- info.si_errno = 0;
- info.si_code = __SI_FAULT|0x100;
- info.si_addr = (void __user *)regs->tpc;
- info.si_trapno = regs->u_regs[UREG_G1];
- send_sig_info(SIGSYS, &info, current);
- if (cnt++ < 4) {
- printk("Process makes ni_syscall number %d, register dump:\n",
- (int) regs->u_regs[UREG_G1]);
- show_regs(regs);
- }
- return -ENOSYS;
-}
-
-/* This is not a real and complete implementation yet, just to keep
- * the easy SunOS binaries happy.
- */
-asmlinkage int sunos_fpathconf(int fd, int name)
-{
- int ret;
-
- switch(name) {
- case _PCONF_LINK:
- ret = LINK_MAX;
- break;
- case _PCONF_CANON:
- ret = MAX_CANON;
- break;
- case _PCONF_INPUT:
- ret = MAX_INPUT;
- break;
- case _PCONF_NAME:
- ret = NAME_MAX;
- break;
- case _PCONF_PATH:
- ret = PATH_MAX;
- break;
- case _PCONF_PIPE:
- ret = PIPE_BUF;
- break;
- case _PCONF_CHRESTRICT: /* XXX Investigate XXX */
- ret = 1;
- break;
- case _PCONF_NOTRUNC: /* XXX Investigate XXX */
- case _PCONF_VDISABLE:
- ret = 0;
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-asmlinkage int sunos_pathconf(u32 u_path, int name)
-{
- int ret;
-
- ret = sunos_fpathconf(0, name); /* XXX cheese XXX */
- return ret;
-}
-
-asmlinkage int sunos_select(int width, u32 inp, u32 outp, u32 exp, u32 tvp_x)
-{
- int ret;
-
- /* SunOS binaries expect that select won't change the tvp contents */
- ret = compat_sys_select(width, compat_ptr(inp), compat_ptr(outp),
- compat_ptr(exp), compat_ptr(tvp_x));
- if (ret == -EINTR && tvp_x) {
- struct compat_timeval __user *tvp = compat_ptr(tvp_x);
- time_t sec, usec;
-
- __get_user(sec, &tvp->tv_sec);
- __get_user(usec, &tvp->tv_usec);
- if (sec == 0 && usec == 0)
- ret = 0;
- }
- return ret;
-}
-
-asmlinkage void sunos_nop(void)
-{
- return;
-}
-
-#if 0 /* This code doesn't translate user pointers correctly,
- * disable for now. -DaveM
- */
-
-/* XXXXXXXXXX SunOS mount/umount. XXXXXXXXXXX */
-#define SMNT_RDONLY 1
-#define SMNT_NOSUID 2
-#define SMNT_NEWTYPE 4
-#define SMNT_GRPID 8
-#define SMNT_REMOUNT 16
-#define SMNT_NOSUB 32
-#define SMNT_MULTI 64
-#define SMNT_SYS5 128
-
-struct sunos_fh_t {
- char fh_data [NFS_FHSIZE];
-};
-
-struct sunos_nfs_mount_args {
- struct sockaddr_in *addr; /* file server address */
- struct nfs_fh *fh; /* File handle to be mounted */
- int flags; /* flags */
- int wsize; /* write size in bytes */
- int rsize; /* read size in bytes */
- int timeo; /* initial timeout in .1 secs */
- int retrans; /* times to retry send */
- char *hostname; /* server's hostname */
- int acregmin; /* attr cache file min secs */
- int acregmax; /* attr cache file max secs */
- int acdirmin; /* attr cache dir min secs */
- int acdirmax; /* attr cache dir max secs */
- char *netname; /* server's netname */
-};
-
-
-/* Bind the socket on a local reserved port and connect it to the
- * remote server. This on Linux/i386 is done by the mount program,
- * not by the kernel.
- */
-/* XXXXXXXXXXXXXXXXXXXX */
-static int
-sunos_nfs_get_server_fd (int fd, struct sockaddr_in *addr)
-{
- struct sockaddr_in local;
- struct sockaddr_in server;
- int try_port;
- int ret;
- struct socket *socket;
- struct inode *inode;
- struct file *file;
-
- file = fget(fd);
- if (!file)
- return 0;
-
- inode = file->f_path.dentry->d_inode;
-
- socket = SOCKET_I(inode);
- local.sin_family = AF_INET;
- local.sin_addr.s_addr = htonl(INADDR_ANY);
-
- /* IPPORT_RESERVED = 1024, can't find the definition in the kernel */
- try_port = 1024;
- do {
- local.sin_port = htons (--try_port);
- ret = socket->ops->bind(socket, (struct sockaddr*)&local,
- sizeof(local));
- } while (ret && try_port > (1024 / 2));
-
- if (ret) {
- fput(file);
- return 0;
- }
-
- server.sin_family = AF_INET;
- server.sin_addr = addr->sin_addr;
- server.sin_port = NFS_PORT;
-
- /* Call sys_connect */
- ret = socket->ops->connect (socket, (struct sockaddr *) &server,
- sizeof (server), file->f_flags);
- fput(file);
- if (ret < 0)
- return 0;
- return 1;
-}
-
-/* XXXXXXXXXXXXXXXXXXXX */
-static int get_default (int value, int def_value)
-{
- if (value)
- return value;
- else
- return def_value;
-}
-
-/* XXXXXXXXXXXXXXXXXXXX */
-static int sunos_nfs_mount(char *dir_name, int linux_flags, void __user *data)
-{
- int server_fd, err;
- char *the_name, *mount_page;
- struct nfs_mount_data linux_nfs_mount;
- struct sunos_nfs_mount_args sunos_mount;
-
- /* Ok, here comes the fun part: Linux's nfs mount needs a
- * socket connection to the server, but SunOS mount does not
- * require this, so we use the information on the destination
- * address to create a socket and bind it to a reserved
- * port on this system
- */
- if (copy_from_user(&sunos_mount, data, sizeof(sunos_mount)))
- return -EFAULT;
-
- server_fd = sys_socket (AF_INET, SOCK_DGRAM, IPPROTO_UDP);
- if (server_fd < 0)
- return -ENXIO;
-
- if (copy_from_user(&linux_nfs_mount.addr, sunos_mount.addr,
- sizeof(*sunos_mount.addr)) ||
- copy_from_user(&linux_nfs_mount.root, sunos_mount.fh,
- sizeof(*sunos_mount.fh))) {
- sys_close (server_fd);
- return -EFAULT;
- }
-
- if (!sunos_nfs_get_server_fd (server_fd, &linux_nfs_mount.addr)){
- sys_close (server_fd);
- return -ENXIO;
- }
-
- /* Now, bind it to a locally reserved port */
- linux_nfs_mount.version = NFS_MOUNT_VERSION;
- linux_nfs_mount.flags = sunos_mount.flags;
- linux_nfs_mount.fd = server_fd;
-
- linux_nfs_mount.rsize = get_default (sunos_mount.rsize, 8192);
- linux_nfs_mount.wsize = get_default (sunos_mount.wsize, 8192);
- linux_nfs_mount.timeo = get_default (sunos_mount.timeo, 10);
- linux_nfs_mount.retrans = sunos_mount.retrans;
-
- linux_nfs_mount.acregmin = sunos_mount.acregmin;
- linux_nfs_mount.acregmax = sunos_mount.acregmax;
- linux_nfs_mount.acdirmin = sunos_mount.acdirmin;
- linux_nfs_mount.acdirmax = sunos_mount.acdirmax;
-
- the_name = getname(sunos_mount.hostname);
- if (IS_ERR(the_name))
- return PTR_ERR(the_name);
-
- strlcpy(linux_nfs_mount.hostname, the_name,
- sizeof(linux_nfs_mount.hostname));
- putname (the_name);
-
- mount_page = (char *) get_zeroed_page(GFP_KERNEL);
- if (!mount_page)
- return -ENOMEM;
-
- memcpy(mount_page, &linux_nfs_mount, sizeof(linux_nfs_mount));
-
- err = do_mount("", dir_name, "nfs", linux_flags, mount_page);
-
- free_page((unsigned long) mount_page);
- return err;
-}
-
-/* XXXXXXXXXXXXXXXXXXXX */
-asmlinkage int
-sunos_mount(char *type, char *dir, int flags, void *data)
-{
- int linux_flags = 0;
- int ret = -EINVAL;
- char *dev_fname = 0;
- char *dir_page, *type_page;
-
- if (!capable (CAP_SYS_ADMIN))
- return -EPERM;
-
- /* We don't handle the integer fs type */
- if ((flags & SMNT_NEWTYPE) == 0)
- goto out;
-
- /* Do not allow for those flags we don't support */
- if (flags & (SMNT_GRPID|SMNT_NOSUB|SMNT_MULTI|SMNT_SYS5))
- goto out;
-
- if (flags & SMNT_REMOUNT)
- linux_flags |= MS_REMOUNT;
- if (flags & SMNT_RDONLY)
- linux_flags |= MS_RDONLY;
- if (flags & SMNT_NOSUID)
- linux_flags |= MS_NOSUID;
-
- dir_page = getname(dir);
- ret = PTR_ERR(dir_page);
- if (IS_ERR(dir_page))
- goto out;
-
- type_page = getname(type);
- ret = PTR_ERR(type_page);
- if (IS_ERR(type_page))
- goto out1;
-
- if (strcmp(type_page, "ext2") == 0) {
- dev_fname = getname(data);
- } else if (strcmp(type_page, "iso9660") == 0) {
- dev_fname = getname(data);
- } else if (strcmp(type_page, "minix") == 0) {
- dev_fname = getname(data);
- } else if (strcmp(type_page, "nfs") == 0) {
- ret = sunos_nfs_mount (dir_page, flags, data);
- goto out2;
- } else if (strcmp(type_page, "ufs") == 0) {
- printk("Warning: UFS filesystem mounts unsupported.\n");
- ret = -ENODEV;
- goto out2;
- } else if (strcmp(type_page, "proc")) {
- ret = -ENODEV;
- goto out2;
- }
- ret = PTR_ERR(dev_fname);
- if (IS_ERR(dev_fname))
- goto out2;
- lock_kernel();
- ret = do_mount(dev_fname, dir_page, type_page, linux_flags, NULL);
- unlock_kernel();
- if (dev_fname)
- putname(dev_fname);
-out2:
- putname(type_page);
-out1:
- putname(dir_page);
-out:
- return ret;
-}
-#endif
-
-asmlinkage int sunos_setpgrp(pid_t pid, pid_t pgid)
-{
- int ret;
-
- /* So stupid... */
- if ((!pid || pid == current->pid) &&
- !pgid) {
- sys_setsid();
- ret = 0;
- } else {
- ret = sys_setpgid(pid, pgid);
- }
- return ret;
-}
-
-/* So stupid... */
-extern long compat_sys_wait4(compat_pid_t, compat_uint_t __user *, int,
- struct compat_rusage __user *);
-
-asmlinkage int sunos_wait4(compat_pid_t pid, compat_uint_t __user *stat_addr, int options, struct compat_rusage __user *ru)
-{
- int ret;
-
- ret = compat_sys_wait4((pid ? pid : ((compat_pid_t)-1)),
- stat_addr, options, ru);
- return ret;
-}
-
-asmlinkage int sunos_killpg(int pgrp, int sig)
-{
- int ret;
-
- rcu_read_lock();
- ret = -EINVAL;
- if (pgrp > 0)
- ret = kill_pgrp(find_vpid(pgrp), sig, 0);
- rcu_read_unlock();
-
- return ret;
-}
-
-asmlinkage int sunos_audit(void)
-{
- printk ("sys_audit\n");
- return -1;
-}
-
-asmlinkage u32 sunos_gethostid(void)
-{
- u32 ret;
-
- ret = (((u32)idprom->id_machtype << 24) | ((u32)idprom->id_sernum));
-
- return ret;
-}
-
-/* sysconf options, for SunOS compatibility */
-#define _SC_ARG_MAX 1
-#define _SC_CHILD_MAX 2
-#define _SC_CLK_TCK 3
-#define _SC_NGROUPS_MAX 4
-#define _SC_OPEN_MAX 5
-#define _SC_JOB_CONTROL 6
-#define _SC_SAVED_IDS 7
-#define _SC_VERSION 8
-
-asmlinkage s32 sunos_sysconf (int name)
-{
- s32 ret;
-
- switch (name){
- case _SC_ARG_MAX:
- ret = ARG_MAX;
- break;
- case _SC_CHILD_MAX:
- ret = current->signal->rlim[RLIMIT_NPROC].rlim_cur;
- break;
- case _SC_CLK_TCK:
- ret = HZ;
- break;
- case _SC_NGROUPS_MAX:
- ret = NGROUPS_MAX;
- break;
- case _SC_OPEN_MAX:
- ret = current->signal->rlim[RLIMIT_NOFILE].rlim_cur;
- break;
- case _SC_JOB_CONTROL:
- ret = 1; /* yes, we do support job control */
- break;
- case _SC_SAVED_IDS:
- ret = 1; /* yes, we do support saved uids */
- break;
- case _SC_VERSION:
- /* mhm, POSIX_VERSION is in /usr/include/unistd.h
- * should it go on /usr/include/linux?
- */
- ret = 199009;
- break;
- default:
- ret = -1;
- break;
- };
- return ret;
-}
-
-asmlinkage int sunos_semsys(int op, u32 arg1, u32 arg2, u32 arg3, void __user *ptr)
-{
- union semun arg4;
- int ret;
-
- switch (op) {
- case 0:
- /* Most arguments match on a 1:1 basis but cmd doesn't */
- switch(arg3) {
- case 4:
- arg3=GETPID; break;
- case 5:
- arg3=GETVAL; break;
- case 6:
- arg3=GETALL; break;
- case 3:
- arg3=GETNCNT; break;
- case 7:
- arg3=GETZCNT; break;
- case 8:
- arg3=SETVAL; break;
- case 9:
- arg3=SETALL; break;
- }
- /* sys_semctl(): */
- /* value to modify semaphore to */
- arg4.__pad = ptr;
- ret = sys_semctl((int)arg1, (int)arg2, (int)arg3, arg4);
- break;
- case 1:
- /* sys_semget(): */
- ret = sys_semget((key_t)arg1, (int)arg2, (int)arg3);
- break;
- case 2:
- /* sys_semop(): */
- ret = sys_semop((int)arg1, (struct sembuf __user *)(unsigned long)arg2,
- (unsigned int) arg3);
- break;
- default:
- ret = -EINVAL;
- break;
- };
- return ret;
-}
-
-struct msgbuf32 {
- s32 mtype;
- char mtext[1];
-};
-
-struct ipc_perm32
-{
- key_t key;
- compat_uid_t uid;
- compat_gid_t gid;
- compat_uid_t cuid;
- compat_gid_t cgid;
- compat_mode_t mode;
- unsigned short seq;
-};
-
-struct msqid_ds32
-{
- struct ipc_perm32 msg_perm;
- u32 msg_first;
- u32 msg_last;
- compat_time_t msg_stime;
- compat_time_t msg_rtime;
- compat_time_t msg_ctime;
- u32 wwait;
- u32 rwait;
- unsigned short msg_cbytes;
- unsigned short msg_qnum;
- unsigned short msg_qbytes;
- compat_ipc_pid_t msg_lspid;
- compat_ipc_pid_t msg_lrpid;
-};
-
-static inline int sunos_msqid_get(struct msqid_ds32 __user *user,
- struct msqid_ds *kern)
-{
- if (get_user(kern->msg_perm.key, &user->msg_perm.key) ||
- __get_user(kern->msg_perm.uid, &user->msg_perm.uid) ||
- __get_user(kern->msg_perm.gid, &user->msg_perm.gid) ||
- __get_user(kern->msg_perm.cuid, &user->msg_perm.cuid) ||
- __get_user(kern->msg_perm.cgid, &user->msg_perm.cgid) ||
- __get_user(kern->msg_stime, &user->msg_stime) ||
- __get_user(kern->msg_rtime, &user->msg_rtime) ||
- __get_user(kern->msg_ctime, &user->msg_ctime) ||
- __get_user(kern->msg_ctime, &user->msg_cbytes) ||
- __get_user(kern->msg_ctime, &user->msg_qnum) ||
- __get_user(kern->msg_ctime, &user->msg_qbytes) ||
- __get_user(kern->msg_ctime, &user->msg_lspid) ||
- __get_user(kern->msg_ctime, &user->msg_lrpid))
- return -EFAULT;
- return 0;
-}
-
-static inline int sunos_msqid_put(struct msqid_ds32 __user *user,
- struct msqid_ds *kern)
-{
- if (put_user(kern->msg_perm.key, &user->msg_perm.key) ||
- __put_user(kern->msg_perm.uid, &user->msg_perm.uid) ||
- __put_user(kern->msg_perm.gid, &user->msg_perm.gid) ||
- __put_user(kern->msg_perm.cuid, &user->msg_perm.cuid) ||
- __put_user(kern->msg_perm.cgid, &user->msg_perm.cgid) ||
- __put_user(kern->msg_stime, &user->msg_stime) ||
- __put_user(kern->msg_rtime, &user->msg_rtime) ||
- __put_user(kern->msg_ctime, &user->msg_ctime) ||
- __put_user(kern->msg_ctime, &user->msg_cbytes) ||
- __put_user(kern->msg_ctime, &user->msg_qnum) ||
- __put_user(kern->msg_ctime, &user->msg_qbytes) ||
- __put_user(kern->msg_ctime, &user->msg_lspid) ||
- __put_user(kern->msg_ctime, &user->msg_lrpid))
- return -EFAULT;
- return 0;
-}
-
-static inline int sunos_msgbuf_get(struct msgbuf32 __user *user, struct msgbuf *kern, int len)
-{
- if (get_user(kern->mtype, &user->mtype) ||
- __copy_from_user(kern->mtext, &user->mtext, len))
- return -EFAULT;
- return 0;
-}
-
-static inline int sunos_msgbuf_put(struct msgbuf32 __user *user, struct msgbuf *kern, int len)
-{
- if (put_user(kern->mtype, &user->mtype) ||
- __copy_to_user(user->mtext, kern->mtext, len))
- return -EFAULT;
- return 0;
-}
-
-asmlinkage int sunos_msgsys(int op, u32 arg1, u32 arg2, u32 arg3, u32 arg4)
-{
- struct sparc_stackf32 __user *sp;
- struct msqid_ds kds;
- struct msgbuf *kmbuf;
- mm_segment_t old_fs = get_fs();
- u32 arg5;
- int rval;
-
- switch(op) {
- case 0:
- rval = sys_msgget((key_t)arg1, (int)arg2);
- break;
- case 1:
- if (!sunos_msqid_get((struct msqid_ds32 __user *)(unsigned long)arg3, &kds)) {
- set_fs(KERNEL_DS);
- rval = sys_msgctl((int)arg1, (int)arg2,
- (struct msqid_ds __user *)(unsigned long)arg3);
- set_fs(old_fs);
- if (!rval)
- rval = sunos_msqid_put((struct msqid_ds32 __user *)(unsigned long)arg3,
- &kds);
- } else
- rval = -EFAULT;
- break;
- case 2:
- rval = -EFAULT;
- kmbuf = kmalloc(sizeof(struct msgbuf) + arg3,
- GFP_KERNEL);
- if (!kmbuf)
- break;
- sp = (struct sparc_stackf32 __user *)
- (current_thread_info()->kregs->u_regs[UREG_FP] & 0xffffffffUL);
- if (get_user(arg5, &sp->xxargs[0])) {
- rval = -EFAULT;
- kfree(kmbuf);
- break;
- }
- set_fs(KERNEL_DS);
- rval = sys_msgrcv((int)arg1, (struct msgbuf __user *) kmbuf,
- (size_t)arg3,
- (long)arg4, (int)arg5);
- set_fs(old_fs);
- if (!rval)
- rval = sunos_msgbuf_put((struct msgbuf32 __user *)(unsigned long)arg2,
- kmbuf, arg3);
- kfree(kmbuf);
- break;
- case 3:
- rval = -EFAULT;
- kmbuf = kmalloc(sizeof(struct msgbuf) + arg3,
- GFP_KERNEL);
- if (!kmbuf || sunos_msgbuf_get((struct msgbuf32 __user *)(unsigned long)arg2,
- kmbuf, arg3))
- break;
- set_fs(KERNEL_DS);
- rval = sys_msgsnd((int)arg1, (struct msgbuf __user *) kmbuf,
- (size_t)arg3, (int)arg4);
- set_fs(old_fs);
- kfree(kmbuf);
- break;
- default:
- rval = -EINVAL;
- break;
- }
- return rval;
-}
-
-struct shmid_ds32 {
- struct ipc_perm32 shm_perm;
- int shm_segsz;
- compat_time_t shm_atime;
- compat_time_t shm_dtime;
- compat_time_t shm_ctime;
- compat_ipc_pid_t shm_cpid;
- compat_ipc_pid_t shm_lpid;
- unsigned short shm_nattch;
-};
-
-static inline int sunos_shmid_get(struct shmid_ds32 __user *user,
- struct shmid_ds *kern)
-{
- if (get_user(kern->shm_perm.key, &user->shm_perm.key) ||
- __get_user(kern->shm_perm.uid, &user->shm_perm.uid) ||
- __get_user(kern->shm_perm.gid, &user->shm_perm.gid) ||
- __get_user(kern->shm_perm.cuid, &user->shm_perm.cuid) ||
- __get_user(kern->shm_perm.cgid, &user->shm_perm.cgid) ||
- __get_user(kern->shm_segsz, &user->shm_segsz) ||
- __get_user(kern->shm_atime, &user->shm_atime) ||
- __get_user(kern->shm_dtime, &user->shm_dtime) ||
- __get_user(kern->shm_ctime, &user->shm_ctime) ||
- __get_user(kern->shm_cpid, &user->shm_cpid) ||
- __get_user(kern->shm_lpid, &user->shm_lpid) ||
- __get_user(kern->shm_nattch, &user->shm_nattch))
- return -EFAULT;
- return 0;
-}
-
-static inline int sunos_shmid_put(struct shmid_ds32 __user *user,
- struct shmid_ds *kern)
-{
- if (put_user(kern->shm_perm.key, &user->shm_perm.key) ||
- __put_user(kern->shm_perm.uid, &user->shm_perm.uid) ||
- __put_user(kern->shm_perm.gid, &user->shm_perm.gid) ||
- __put_user(kern->shm_perm.cuid, &user->shm_perm.cuid) ||
- __put_user(kern->shm_perm.cgid, &user->shm_perm.cgid) ||
- __put_user(kern->shm_segsz, &user->shm_segsz) ||
- __put_user(kern->shm_atime, &user->shm_atime) ||
- __put_user(kern->shm_dtime, &user->shm_dtime) ||
- __put_user(kern->shm_ctime, &user->shm_ctime) ||
- __put_user(kern->shm_cpid, &user->shm_cpid) ||
- __put_user(kern->shm_lpid, &user->shm_lpid) ||
- __put_user(kern->shm_nattch, &user->shm_nattch))
- return -EFAULT;
- return 0;
-}
-
-asmlinkage int sunos_shmsys(int op, u32 arg1, u32 arg2, u32 arg3)
-{
- struct shmid_ds ksds;
- unsigned long raddr;
- mm_segment_t old_fs = get_fs();
- int rval;
-
- switch(op) {
- case 0:
- /* do_shmat(): attach a shared memory area */
- rval = do_shmat((int)arg1,(char __user *)(unsigned long)arg2,(int)arg3,&raddr);
- if (!rval)
- rval = (int) raddr;
- break;
- case 1:
- /* sys_shmctl(): modify shared memory area attr. */
- if (!sunos_shmid_get((struct shmid_ds32 __user *)(unsigned long)arg3, &ksds)) {
- set_fs(KERNEL_DS);
- rval = sys_shmctl((int) arg1,(int) arg2,
- (struct shmid_ds __user *) &ksds);
- set_fs(old_fs);
- if (!rval)
- rval = sunos_shmid_put((struct shmid_ds32 __user *)(unsigned long)arg3,
- &ksds);
- } else
- rval = -EFAULT;
- break;
- case 2:
- /* sys_shmdt(): detach a shared memory area */
- rval = sys_shmdt((char __user *)(unsigned long)arg1);
- break;
- case 3:
- /* sys_shmget(): get a shared memory area */
- rval = sys_shmget((key_t)arg1,(int)arg2,(int)arg3);
- break;
- default:
- rval = -EINVAL;
- break;
- };
- return rval;
-}
-
-extern asmlinkage long sparc32_open(const char __user * filename, int flags, int mode);
-
-asmlinkage int sunos_open(u32 fname, int flags, int mode)
-{
- const char __user *filename = compat_ptr(fname);
-
- return sparc32_open(filename, flags, mode);
-}
-
-#define SUNOS_EWOULDBLOCK 35
-
-/* see the sunos man page read(2v) for an explanation
- of this garbage. We use O_NDELAY to mark
- file descriptors that have been set non-blocking
- using 4.2BSD style calls. (tridge) */
-
-static inline int check_nonblock(int ret, int fd)
-{
- if (ret == -EAGAIN) {
- struct file * file = fget(fd);
- if (file) {
- if (file->f_flags & O_NDELAY)
- ret = -SUNOS_EWOULDBLOCK;
- fput(file);
- }
- }
- return ret;
-}
-
-asmlinkage int sunos_read(unsigned int fd, char __user *buf, u32 count)
-{
- int ret;
-
- ret = check_nonblock(sys_read(fd, buf, count), fd);
- return ret;
-}
-
-asmlinkage int sunos_readv(u32 fd, void __user *vector, s32 count)
-{
- int ret;
-
- ret = check_nonblock(compat_sys_readv(fd, vector, count), fd);
- return ret;
-}
-
-asmlinkage int sunos_write(unsigned int fd, char __user *buf, u32 count)
-{
- int ret;
-
- ret = check_nonblock(sys_write(fd, buf, count), fd);
- return ret;
-}
-
-asmlinkage int sunos_writev(u32 fd, void __user *vector, s32 count)
-{
- int ret;
-
- ret = check_nonblock(compat_sys_writev(fd, vector, count), fd);
- return ret;
-}
-
-asmlinkage int sunos_recv(u32 __fd, void __user *ubuf, int size, unsigned flags)
-{
- int ret, fd = (int) __fd;
-
- ret = check_nonblock(sys_recv(fd, ubuf, size, flags), fd);
- return ret;
-}
-
-asmlinkage int sunos_send(u32 __fd, void __user *buff, int len, unsigned flags)
-{
- int ret, fd = (int) __fd;
-
- ret = check_nonblock(sys_send(fd, buff, len, flags), fd);
- return ret;
-}
-
-asmlinkage int sunos_accept(u32 __fd, struct sockaddr __user *sa, int __user *addrlen)
-{
- int ret, fd = (int) __fd;
-
- while (1) {
- ret = check_nonblock(sys_accept(fd, sa, addrlen), fd);
- if (ret != -ENETUNREACH && ret != -EHOSTUNREACH)
- break;
- }
- return ret;
-}
-
-#define SUNOS_SV_INTERRUPT 2
-
-asmlinkage int sunos_sigaction (int sig,
- struct old_sigaction32 __user *act,
- struct old_sigaction32 __user *oact)
-{
- struct k_sigaction new_ka, old_ka;
- int ret;
-
- if (act) {
- compat_old_sigset_t mask;
- u32 u_handler;
-
- if (get_user(u_handler, &act->sa_handler) ||
- __get_user(new_ka.sa.sa_flags, &act->sa_flags))
- return -EFAULT;
- new_ka.sa.sa_handler = compat_ptr(u_handler);
- __get_user(mask, &act->sa_mask);
- new_ka.sa.sa_restorer = NULL;
- new_ka.ka_restorer = NULL;
- siginitset(&new_ka.sa.sa_mask, mask);
- new_ka.sa.sa_flags ^= SUNOS_SV_INTERRUPT;
- }
-
- ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
-
- if (!ret && oact) {
- old_ka.sa.sa_flags ^= SUNOS_SV_INTERRUPT;
- if (put_user(ptr_to_compat(old_ka.sa.sa_handler), &oact->sa_handler) ||
- __put_user(old_ka.sa.sa_flags, &oact->sa_flags))
- return -EFAULT;
- __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
- }
-
- return ret;
-}
-
-asmlinkage int sunos_setsockopt(u32 __fd, u32 __level, u32 __optname,
- char __user *optval, u32 __optlen)
-{
- int fd = (int) __fd;
- int level = (int) __level;
- int optname = (int) __optname;
- int optlen = (int) __optlen;
- int tr_opt = optname;
- int ret;
-
- if (level == SOL_IP) {
- /* Multicast socketopts (ttl, membership) */
- if (tr_opt >=2 && tr_opt <= 6)
- tr_opt += 30;
- }
- ret = sys_setsockopt(fd, level, tr_opt,
- optval, optlen);
- return ret;
-}
-
-asmlinkage int sunos_getsockopt(u32 __fd, u32 __level, u32 __optname,
- char __user *optval, int __user *optlen)
-{
- int fd = (int) __fd;
- int level = (int) __level;
- int optname = (int) __optname;
- int tr_opt = optname;
- int ret;
-
- if (level == SOL_IP) {
- /* Multicast socketopts (ttl, membership) */
- if (tr_opt >=2 && tr_opt <= 6)
- tr_opt += 30;
- }
- ret = compat_sys_getsockopt(fd, level, tr_opt,
- optval, optlen);
- return ret;
-}
.word sys_set_mempolicy, sys_kexec_load, sys_move_pages, sys_getcpu, sys_epoll_pwait
/*310*/ .word sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate
.word sys_timerfd_settime, sys_timerfd_gettime
-
-#if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
- defined(CONFIG_SOLARIS_EMUL_MODULE)
- /* Now the 32-bit SunOS syscall table. */
-
- .align 4
- .globl sunos_sys_table
-sunos_sys_table:
-/*0*/ .word sunos_indir, sys32_exit, sys_fork
- .word sunos_read, sunos_write, sunos_open
- .word sys_close, sunos_wait4, sys_creat
- .word sys_link, sys_unlink, sunos_execv
- .word sys_chdir, sunos_nosys, sys32_mknod
- .word sys_chmod, sys32_lchown16, sunos_brk
- .word sunos_nosys, sys32_lseek, sunos_getpid
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_getuid, sunos_nosys, sys_ptrace
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sys_access, sunos_nosys, sunos_nosys
- .word sys_sync, sys_kill, compat_sys_newstat
- .word sunos_nosys, compat_sys_newlstat, sys_dup
- .word sys_pipe, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_getgid
- .word sunos_nosys, sunos_nosys
-/*50*/ .word sunos_nosys, sys_acct, sunos_nosys
- .word sunos_mctl, sunos_ioctl, sys_reboot
- .word sunos_nosys, sys_symlink, sys_readlink
- .word sys32_execve, sys_umask, sys_chroot
- .word compat_sys_newfstat, sunos_nosys, sys_getpagesize
- .word sys_msync, sys_vfork, sunos_nosys
- .word sunos_nosys, sunos_sbrk, sunos_sstk
- .word sunos_mmap, sunos_vadvise, sys_munmap
- .word sys_mprotect, sys_madvise, sys_vhangup
- .word sunos_nosys, sys_mincore, sys32_getgroups16
- .word sys32_setgroups16, sys_getpgrp, sunos_setpgrp
- .word compat_sys_setitimer, sunos_nosys, sys_swapon
- .word compat_sys_getitimer, sys_gethostname, sys_sethostname
- .word sunos_getdtablesize, sys_dup2, sunos_nop
- .word compat_sys_fcntl, sunos_select, sunos_nop
- .word sys_fsync, sys32_setpriority, sys32_socket
- .word sys32_connect, sunos_accept
-/*100*/ .word sys_getpriority, sunos_send, sunos_recv
- .word sunos_nosys, sys32_bind, sunos_setsockopt
- .word sys32_listen, sunos_nosys, sunos_sigaction
- .word sunos_sigblock, sunos_sigsetmask, sys_sigpause
- .word sys32_sigstack, sys32_recvmsg, sys32_sendmsg
- .word sunos_nosys, sys32_gettimeofday, compat_sys_getrusage
- .word sunos_getsockopt, sunos_nosys, sunos_readv
- .word sunos_writev, sys32_settimeofday, sys32_fchown16
- .word sys_fchmod, sys32_recvfrom, sys32_setreuid16
- .word sys32_setregid16, sys_rename, sys_truncate
- .word sys_ftruncate, sys_flock, sunos_nosys
- .word sys32_sendto, sys32_shutdown, sys32_socketpair
- .word sys_mkdir, sys_rmdir, sys32_utimes
- .word sys32_sigreturn, sunos_nosys, sys32_getpeername
- .word sunos_gethostid, sunos_nosys, compat_sys_getrlimit
- .word compat_sys_setrlimit, sunos_killpg, sunos_nosys
- .word sunos_nosys, sunos_nosys
-/*150*/ .word sys32_getsockname, sunos_nosys, sunos_nosys
- .word sys_poll, sunos_nosys, sunos_nosys
- .word sunos_getdirentries, compat_sys_statfs, compat_sys_fstatfs
- .word sys_oldumount, sunos_nosys, sunos_nosys
- .word sys_getdomainname, sys_setdomainname
- .word sunos_nosys, sys_quotactl, sunos_nosys
- .word sunos_nosys, sys_ustat, sunos_semsys
- .word sunos_nosys, sunos_shmsys, sunos_audit
- .word sunos_nosys, sunos_getdents, sys_setsid
- .word sys_fchdir, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, compat_sys_sigpending, sunos_nosys
- .word sys_setpgid, sunos_pathconf, sunos_fpathconf
- .word sunos_sysconf, sunos_uname, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
-/*200*/ .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys
-/*250*/ .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys
-/*260*/ .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys
-/*270*/ .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys
-/*280*/ .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys
-/*290*/ .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys
-/*300*/ .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys
-/*310*/ .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys, sunos_nosys, sunos_nosys
- .word sunos_nosys
-
-#endif
unsigned long new_addr);
extern asmlinkage unsigned long c_sys_nis_syscall(struct pt_regs *regs);
extern asmlinkage long sys_getdomainname(char __user *name, int len);
-extern asmlinkage long solaris_syscall(struct pt_regs *regs);
-extern asmlinkage long sunos_syscall(struct pt_regs *regs);
extern asmlinkage long sys_utrap_install(utrap_entry_t type,
utrap_handler_t new_p,
utrap_handler_t new_d,
tl0_f5o: FILL_5_OTHER
tl0_f6o: FILL_6_OTHER
tl0_f7o: FILL_7_OTHER
-tl0_sunos: SUNOS_SYSCALL_TRAP
+tl0_resv100: BTRAP(0x100)
tl0_bkpt: BREAKPOINT_TRAP
tl0_divz: TRAP(do_div0)
tl0_flushw: FLUSH_WINDOW_TRAP
-tl0_resv104: BTRAP(0x104) BTRAP(0x105) BTRAP(0x106) BTRAP(0x107)
- .globl tl0_solaris
-tl0_solaris: SOLARIS_SYSCALL_TRAP
-tl0_resv109: BTRAP(0x109)
-tl0_resv10a: BTRAP(0x10a) BTRAP(0x10b) BTRAP(0x10c) BTRAP(0x10d) BTRAP(0x10e)
-tl0_resv10f: BTRAP(0x10f)
+tl0_resv104: BTRAP(0x104) BTRAP(0x105) BTRAP(0x106) BTRAP(0x107) BTRAP(0x108)
+tl0_resv109: BTRAP(0x109) BTRAP(0x10a) BTRAP(0x10b) BTRAP(0x10c) BTRAP(0x10d)
+tl0_resv10e: BTRAP(0x10e) BTRAP(0x10f)
tl0_linux32: LINUX_32BIT_SYSCALL_TRAP
tl0_oldlinux64: LINUX_64BIT_SYSCALL_TRAP
tl0_resv112: TRAP_UTRAP(UT_TRAP_INSTRUCTION_18,0x112) TRAP_UTRAP(UT_TRAP_INSTRUCTION_19,0x113)
tl0_getcc: GETCC_TRAP
tl0_setcc: SETCC_TRAP
tl0_getpsr: TRAP(do_getpsr)
-tl0_resv123: BTRAP(0x123) BTRAP(0x124) BTRAP(0x125) BTRAP(0x126)
-tl0_solindir: INDIRECT_SOLARIS_SYSCALL(156)
+tl0_resv123: BTRAP(0x123) BTRAP(0x124) BTRAP(0x125) BTRAP(0x126) BTRAP(0x127)
tl0_resv128: BTRAP(0x128) BTRAP(0x129) BTRAP(0x12a) BTRAP(0x12b) BTRAP(0x12c)
tl0_resv12d: BTRAP(0x12d) BTRAP(0x12e) BTRAP(0x12f) BTRAP(0x130) BTRAP(0x131)
tl0_resv132: BTRAP(0x132) BTRAP(0x133) BTRAP(0x134) BTRAP(0x135) BTRAP(0x136)
+++ /dev/null
-#
-# Makefile for the Solaris binary emulation.
-#
-
-EXTRA_AFLAGS := -ansi
-
-solaris-objs := entry64.o fs.o misc.o signal.o systbl.o socket.o \
- ioctl.o ipc.o socksys.o timod.o
-
-obj-$(CONFIG_SOLARIS_EMUL) += solaris.o
+++ /dev/null
-/* $Id: conv.h,v 1.4 1998/08/15 20:42:51 davem Exp $
- * conv.h: Utility macros for Solaris emulation
- *
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-/* #define DEBUG_SOLARIS */
-#define DEBUG_SOLARIS_KMALLOC
-
-#ifndef __ASSEMBLY__
-
-#include <asm/unistd.h>
-
-/* Use this to get at 32-bit user passed pointers. */
-#define A(__x) \
-({ unsigned long __ret; \
- __asm__ ("srl %0, 0, %0" \
- : "=r" (__ret) \
- : "0" (__x)); \
- (void __user *)__ret; \
-})
-
-extern unsigned sys_call_table[];
-extern unsigned sys_call_table32[];
-extern unsigned sunos_sys_table[];
-
-#define SYS(name) ((long)sys_call_table[__NR_##name])
-#define SUNOS(x) ((long)sunos_sys_table[x])
-
-#ifdef DEBUG_SOLARIS
-#define SOLD(s) printk("%s,%d,%s(): %s\n",__FILE__,__LINE__,__func__,(s))
-#define SOLDD(s) printk("solaris: "); printk s
-#else
-#define SOLD(s)
-#define SOLDD(s)
-#endif
-
-#endif /* __ASSEMBLY__ */
+++ /dev/null
-/* $Id: entry64.S,v 1.7 2002/02/09 19:49:31 davem Exp $
- * entry64.S: Solaris syscall emulation entry point.
- *
- * Copyright (C) 1996,1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
- */
-
-#include <linux/errno.h>
-
-#include <asm/head.h>
-#include <asm/asi.h>
-#include <asm/smp.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/signal.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/thread_info.h>
-
-#include "conv.h"
-
-#define NR_SYSCALLS 256
-
- .text
-solaris_syscall_trace:
- add %sp, PTREGS_OFF, %o0
- call syscall_trace
- mov 0, %o1
- srl %i0, 0, %o0
- mov %i4, %o4
- srl %i1, 0, %o1
- mov %i5, %o5
- andcc %l3, 1, %g0
- be,pt %icc, 2f
- srl %i2, 0, %o2
- b,pt %xcc, 2f
- add %sp, PTREGS_OFF, %o0
-
-solaris_sucks:
-/* Solaris is a big system which needs to be able to do all the things
- * in Inf+1 different ways */
- add %i6, 0x5c, %o0
- mov %i0, %g1
- mov %i1, %i0
- mov %i2, %i1
- srl %o0, 0, %o0
- mov %i3, %i2
- movrz %g1, 256, %g1 /* Ensure we don't loop forever */
- mov %i4, %i3
- mov %i5, %i4
- ba,pt %xcc, solaris_sparc_syscall
-exen: lduwa [%o0] ASI_S, %i5
-
-exenf: ba,pt %xcc, solaris_sparc_syscall
- clr %i5
-
-/* For shared binaries, binfmt_elf32 already sets up personality
- and exec_domain. This is to handle static binaries as well */
-solaris_reg:
- call solaris_register
- nop
- ba,pt %xcc, 1f
- mov %i4, %o4
-
-linux_syscall_for_solaris:
- sethi %hi(sys_call_table32), %l6
- or %l6, %lo(sys_call_table32), %l6
- sll %l3, 2, %l4
- ba,pt %xcc, 10f
- lduw [%l6 + %l4], %l3
-
- /* Solaris system calls enter here... */
- .align 32
- .globl solaris_sparc_syscall, entry64_personality_patch
-solaris_sparc_syscall:
-entry64_personality_patch:
- ldub [%g4 + 0x0], %l0
- cmp %g1, 255
- bg,pn %icc, solaris_unimplemented
- srl %g1, 0, %g1
- sethi %hi(solaris_sys_table), %l7
- or %l7, %lo(solaris_sys_table), %l7
- brz,pn %g1, solaris_sucks
- mov %i4, %o4
- sll %g1, 2, %l4
- cmp %l0, 1
- bne,pn %icc, solaris_reg
-1: srl %i0, 0, %o0
- lduw [%l7 + %l4], %l3
- srl %i1, 0, %o1
- ldx [%g6 + TI_FLAGS], %l5
- cmp %l3, NR_SYSCALLS
- bleu,a,pn %xcc, linux_syscall_for_solaris
- nop
- andcc %l3, 1, %g0
- bne,a,pn %icc, 10f
- add %sp, PTREGS_OFF, %o0
-10: srl %i2, 0, %o2
- mov %i5, %o5
- andn %l3, 3, %l7
- andcc %l5, _TIF_SYSCALL_TRACE, %g0
- bne,pn %icc, solaris_syscall_trace
- mov %i0, %l5
-2: call %l7
- srl %i3, 0, %o3
-ret_from_solaris:
- stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
- ldx [%g6 + TI_FLAGS], %l6
- sra %o0, 0, %o0
- mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
- ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
- cmp %o0, -ERESTART_RESTARTBLOCK
- sllx %g2, 32, %g2
- bgeu,pn %xcc, 1f
- andcc %l6, _TIF_SYSCALL_TRACE, %l6
-
- /* System call success, clear Carry condition code. */
- andn %g3, %g2, %g3
- stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
- bne,pn %icc, solaris_syscall_trace2
- ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1
- andcc %l1, 1, %g0
- bne,pn %icc, 2f
- clr %l6
- add %l1, 0x4, %l2
- stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC] ! pc = npc
- call rtrap
- stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC] !npc = npc+4
-
- /* When tnpc & 1, this comes from setcontext and we don't want to advance pc */
-2: andn %l1, 3, %l1
- call rtrap
- stx %l1, [%sp + PTREGS_OFF + PT_V9_TNPC] !npc = npc&~3
-
-1:
- /* System call failure, set Carry condition code.
- * Also, get abs(errno) to return to the process.
- */
- sub %g0, %o0, %o0
- or %g3, %g2, %g3
- cmp %o0, ERANGE /* 0-ERANGE are identity mapped */
- bleu,pt %icc, 1f
- cmp %o0, EMEDIUMTYPE
- bgu,pn %icc, 1f
- sethi %hi(solaris_err_table), %l6
- sll %o0, 2, %o0
- or %l6, %lo(solaris_err_table), %l6
- ldsw [%l6 + %o0], %o0
-1: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
- mov 1, %l6
- stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
- bne,pn %icc, solaris_syscall_trace2
- ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1
- andcc %l1, 1, %g0
- bne,pn %icc, 2b
- add %l1, 0x4, %l2
- stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC] ! pc = npc
- call rtrap
- stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC] !npc = npc+4
-
-solaris_syscall_trace2:
- add %sp, PTREGS_OFF, %o0
- call syscall_trace
- mov 1, %o1
- add %l1, 0x4, %l2 /* npc = npc+4 */
- andcc %l1, 1, %g0
- bne,pn %icc, 2b
- nop
- stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
- call rtrap
- stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
-
- /* This one is tricky, so that's why we do it in assembly */
- .globl solaris_sigsuspend
-solaris_sigsuspend:
- call do_sol_sigsuspend
- nop
- brlz,pn %o0, ret_from_solaris
- nop
- call sys_sigsuspend
- stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
- b,pt %xcc, ret_from_solaris
- nop
-
- .globl solaris_getpid
-solaris_getpid:
- call sys_getppid
- nop
- call sys_getpid
- stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
- b,pt %xcc, ret_from_solaris
- nop
-
- .globl solaris_getuid
-solaris_getuid:
- call sys_geteuid
- nop
- call sys_getuid
- stx %o1, [%sp + PTREGS_OFF + PT_V9_I1]
- b,pt %xcc, ret_from_solaris
- nop
-
- .globl solaris_getgid
-solaris_getgid:
- call sys_getegid
- nop
- call sys_getgid
- stx %o1, [%sp + PTREGS_OFF + PT_V9_I1]
- b,pt %xcc, ret_from_solaris
- nop
-
- .globl solaris_unimplemented
-solaris_unimplemented:
- call do_sol_unimplemented
- add %sp, PTREGS_OFF, %o0
- ba,pt %xcc, ret_from_solaris
- nop
-
- .section __ex_table,"a"
- .align 4
- .word exen, exenf
-
+++ /dev/null
-/* $Id: fs.c,v 1.27 2002/02/08 03:57:14 davem Exp $
- * fs.c: fs related syscall emulation for Solaris
- *
- * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- *
- * 1999-08-19 Implemented solaris F_FREESP (truncate)
- * fcntl, by Jason Rappleye (rappleye@ccr.buffalo.edu)
- */
-
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/capability.h>
-#include <linux/fs.h>
-#include <linux/namei.h>
-#include <linux/mm.h>
-#include <linux/file.h>
-#include <linux/stat.h>
-#include <linux/smp_lock.h>
-#include <linux/limits.h>
-#include <linux/resource.h>
-#include <linux/quotaops.h>
-#include <linux/mount.h>
-#include <linux/vfs.h>
-
-#include <asm/uaccess.h>
-#include <asm/string.h>
-#include <asm/ptrace.h>
-
-#include "conv.h"
-
-#define R3_VERSION 1
-#define R4_VERSION 2
-
-typedef struct {
- s32 tv_sec;
- s32 tv_nsec;
-} timestruct_t;
-
-struct sol_stat {
- u32 st_dev;
- s32 st_pad1[3]; /* network id */
- u32 st_ino;
- u32 st_mode;
- u32 st_nlink;
- u32 st_uid;
- u32 st_gid;
- u32 st_rdev;
- s32 st_pad2[2];
- s32 st_size;
- s32 st_pad3; /* st_size, off_t expansion */
- timestruct_t st_atime;
- timestruct_t st_mtime;
- timestruct_t st_ctime;
- s32 st_blksize;
- s32 st_blocks;
- char st_fstype[16];
- s32 st_pad4[8]; /* expansion area */
-};
-
-struct sol_stat64 {
- u32 st_dev;
- s32 st_pad1[3]; /* network id */
- u64 st_ino;
- u32 st_mode;
- u32 st_nlink;
- u32 st_uid;
- u32 st_gid;
- u32 st_rdev;
- s32 st_pad2[2];
- s64 st_size;
- timestruct_t st_atime;
- timestruct_t st_mtime;
- timestruct_t st_ctime;
- s64 st_blksize;
- s32 st_blocks;
- char st_fstype[16];
- s32 st_pad4[4]; /* expansion area */
-};
-
-#define UFSMAGIC (((unsigned)'u'<<24)||((unsigned)'f'<<16)||((unsigned)'s'<<8))
-
-static inline int putstat(struct sol_stat __user *ubuf, struct kstat *kbuf)
-{
- u32 ino;
-
- if (kbuf->size > MAX_NON_LFS ||
- !sysv_valid_dev(kbuf->dev) ||
- !sysv_valid_dev(kbuf->rdev))
- return -EOVERFLOW;
- ino = kbuf->ino;
- if (sizeof(ino) < sizeof(kbuf->ino) && ino != kbuf->ino)
- return -EOVERFLOW;
- if (put_user (sysv_encode_dev(kbuf->dev), &ubuf->st_dev) ||
- __put_user (ino, &ubuf->st_ino) ||
- __put_user (kbuf->mode, &ubuf->st_mode) ||
- __put_user (kbuf->nlink, &ubuf->st_nlink) ||
- __put_user (kbuf->uid, &ubuf->st_uid) ||
- __put_user (kbuf->gid, &ubuf->st_gid) ||
- __put_user (sysv_encode_dev(kbuf->rdev), &ubuf->st_rdev) ||
- __put_user (kbuf->size, &ubuf->st_size) ||
- __put_user (kbuf->atime.tv_sec, &ubuf->st_atime.tv_sec) ||
- __put_user (kbuf->atime.tv_nsec, &ubuf->st_atime.tv_nsec) ||
- __put_user (kbuf->mtime.tv_sec, &ubuf->st_mtime.tv_sec) ||
- __put_user (kbuf->mtime.tv_nsec, &ubuf->st_mtime.tv_nsec) ||
- __put_user (kbuf->ctime.tv_sec, &ubuf->st_ctime.tv_sec) ||
- __put_user (kbuf->ctime.tv_nsec, &ubuf->st_ctime.tv_nsec) ||
- __put_user (kbuf->blksize, &ubuf->st_blksize) ||
- __put_user (kbuf->blocks, &ubuf->st_blocks) ||
- __put_user (UFSMAGIC, (unsigned __user *)ubuf->st_fstype))
- return -EFAULT;
- return 0;
-}
-
-static inline int putstat64(struct sol_stat64 __user *ubuf, struct kstat *kbuf)
-{
- if (!sysv_valid_dev(kbuf->dev) || !sysv_valid_dev(kbuf->rdev))
- return -EOVERFLOW;
- if (put_user (sysv_encode_dev(kbuf->dev), &ubuf->st_dev) ||
- __put_user (kbuf->ino, &ubuf->st_ino) ||
- __put_user (kbuf->mode, &ubuf->st_mode) ||
- __put_user (kbuf->nlink, &ubuf->st_nlink) ||
- __put_user (kbuf->uid, &ubuf->st_uid) ||
- __put_user (kbuf->gid, &ubuf->st_gid) ||
- __put_user (sysv_encode_dev(kbuf->rdev), &ubuf->st_rdev) ||
- __put_user (kbuf->size, &ubuf->st_size) ||
- __put_user (kbuf->atime.tv_sec, &ubuf->st_atime.tv_sec) ||
- __put_user (kbuf->atime.tv_nsec, &ubuf->st_atime.tv_nsec) ||
- __put_user (kbuf->mtime.tv_sec, &ubuf->st_mtime.tv_sec) ||
- __put_user (kbuf->mtime.tv_nsec, &ubuf->st_mtime.tv_nsec) ||
- __put_user (kbuf->ctime.tv_sec, &ubuf->st_ctime.tv_sec) ||
- __put_user (kbuf->ctime.tv_nsec, &ubuf->st_ctime.tv_nsec) ||
- __put_user (kbuf->blksize, &ubuf->st_blksize) ||
- __put_user (kbuf->blocks, &ubuf->st_blocks) ||
- __put_user (UFSMAGIC, (unsigned __user *)ubuf->st_fstype))
- return -EFAULT;
- return 0;
-}
-
-asmlinkage int solaris_stat(u32 filename, u32 statbuf)
-{
- struct kstat s;
- int ret = vfs_stat(A(filename), &s);
- if (!ret)
- return putstat(A(statbuf), &s);
- return ret;
-}
-
-asmlinkage int solaris_xstat(int vers, u32 filename, u32 statbuf)
-{
- /* Solaris doesn't bother with looking at vers, so we do neither */
- return solaris_stat(filename, statbuf);
-}
-
-asmlinkage int solaris_stat64(u32 filename, u32 statbuf)
-{
- struct kstat s;
- int ret = vfs_stat(A(filename), &s);
- if (!ret)
- return putstat64(A(statbuf), &s);
- return ret;
-}
-
-asmlinkage int solaris_lstat(u32 filename, u32 statbuf)
-{
- struct kstat s;
- int ret = vfs_lstat(A(filename), &s);
- if (!ret)
- return putstat(A(statbuf), &s);
- return ret;
-}
-
-asmlinkage int solaris_lxstat(int vers, u32 filename, u32 statbuf)
-{
- return solaris_lstat(filename, statbuf);
-}
-
-asmlinkage int solaris_lstat64(u32 filename, u32 statbuf)
-{
- struct kstat s;
- int ret = vfs_lstat(A(filename), &s);
- if (!ret)
- return putstat64(A(statbuf), &s);
- return ret;
-}
-
-asmlinkage int solaris_fstat(unsigned int fd, u32 statbuf)
-{
- struct kstat s;
- int ret = vfs_fstat(fd, &s);
- if (!ret)
- return putstat(A(statbuf), &s);
- return ret;
-}
-
-asmlinkage int solaris_fxstat(int vers, u32 fd, u32 statbuf)
-{
- return solaris_fstat(fd, statbuf);
-}
-
-asmlinkage int solaris_fstat64(unsigned int fd, u32 statbuf)
-{
- struct kstat s;
- int ret = vfs_fstat(fd, &s);
- if (!ret)
- return putstat64(A(statbuf), &s);
- return ret;
-}
-
-asmlinkage int solaris_mknod(u32 path, u32 mode, s32 dev)
-{
- int (*sys_mknod)(const char __user *,int,unsigned) =
- (int (*)(const char __user *,int,unsigned))SYS(mknod);
- int major = sysv_major(dev);
- int minor = sysv_minor(dev);
-
- /* minor is guaranteed to be OK for MKDEV, major might be not */
- if (major > 0xfff)
- return -EINVAL;
- return sys_mknod(A(path), mode, new_encode_dev(MKDEV(major,minor)));
-}
-
-asmlinkage int solaris_xmknod(int vers, u32 path, u32 mode, s32 dev)
-{
- return solaris_mknod(path, mode, dev);
-}
-
-asmlinkage int solaris_getdents64(unsigned int fd, void __user *dirent, unsigned int count)
-{
- int (*sys_getdents)(unsigned int, void __user *, unsigned int) =
- (int (*)(unsigned int, void __user *, unsigned int))SYS(getdents);
-
- return sys_getdents(fd, dirent, count);
-}
-
-/* This statfs thingie probably will go in the near future, but... */
-
-struct sol_statfs {
- short f_type;
- s32 f_bsize;
- s32 f_frsize;
- s32 f_blocks;
- s32 f_bfree;
- u32 f_files;
- u32 f_ffree;
- char f_fname[6];
- char f_fpack[6];
-};
-
-asmlinkage int solaris_statfs(u32 path, u32 buf, int len, int fstype)
-{
- int ret;
- struct statfs s;
- mm_segment_t old_fs = get_fs();
- int (*sys_statfs)(const char __user *,struct statfs __user *) =
- (int (*)(const char __user *,struct statfs __user *))SYS(statfs);
- struct sol_statfs __user *ss = A(buf);
-
- if (len != sizeof(struct sol_statfs)) return -EINVAL;
- if (!fstype) {
- /* FIXME: mixing userland and kernel pointers */
- set_fs (KERNEL_DS);
- ret = sys_statfs(A(path), &s);
- set_fs (old_fs);
- if (!ret) {
- if (put_user (s.f_type, &ss->f_type) ||
- __put_user (s.f_bsize, &ss->f_bsize) ||
- __put_user (0, &ss->f_frsize) ||
- __put_user (s.f_blocks, &ss->f_blocks) ||
- __put_user (s.f_bfree, &ss->f_bfree) ||
- __put_user (s.f_files, &ss->f_files) ||
- __put_user (s.f_ffree, &ss->f_ffree) ||
- __clear_user (&ss->f_fname, 12))
- return -EFAULT;
- }
- return ret;
- }
-/* Linux can't stat unmounted filesystems so we
- * simply lie and claim 100MB of 1GB is free. Sorry.
- */
- if (put_user (fstype, &ss->f_type) ||
- __put_user (1024, &ss->f_bsize) ||
- __put_user (0, &ss->f_frsize) ||
- __put_user (1024*1024, &ss->f_blocks) ||
- __put_user (100*1024, &ss->f_bfree) ||
- __put_user (60000, &ss->f_files) ||
- __put_user (50000, &ss->f_ffree) ||
- __clear_user (&ss->f_fname, 12))
- return -EFAULT;
- return 0;
-}
-
-asmlinkage int solaris_fstatfs(u32 fd, u32 buf, int len, int fstype)
-{
- int ret;
- struct statfs s;
- mm_segment_t old_fs = get_fs();
- int (*sys_fstatfs)(unsigned,struct statfs __user *) =
- (int (*)(unsigned,struct statfs __user *))SYS(fstatfs);
- struct sol_statfs __user *ss = A(buf);
-
- if (len != sizeof(struct sol_statfs)) return -EINVAL;
- if (!fstype) {
- set_fs (KERNEL_DS);
- ret = sys_fstatfs(fd, &s);
- set_fs (old_fs);
- if (!ret) {
- if (put_user (s.f_type, &ss->f_type) ||
- __put_user (s.f_bsize, &ss->f_bsize) ||
- __put_user (0, &ss->f_frsize) ||
- __put_user (s.f_blocks, &ss->f_blocks) ||
- __put_user (s.f_bfree, &ss->f_bfree) ||
- __put_user (s.f_files, &ss->f_files) ||
- __put_user (s.f_ffree, &ss->f_ffree) ||
- __clear_user (&ss->f_fname, 12))
- return -EFAULT;
- }
- return ret;
- }
- /* Otherwise fstatfs is the same as statfs */
- return solaris_statfs(0, buf, len, fstype);
-}
-
-struct sol_statvfs {
- u32 f_bsize;
- u32 f_frsize;
- u32 f_blocks;
- u32 f_bfree;
- u32 f_bavail;
- u32 f_files;
- u32 f_ffree;
- u32 f_favail;
- u32 f_fsid;
- char f_basetype[16];
- u32 f_flag;
- u32 f_namemax;
- char f_fstr[32];
- u32 f_filler[16];
-};
-
-struct sol_statvfs64 {
- u32 f_bsize;
- u32 f_frsize;
- u64 f_blocks;
- u64 f_bfree;
- u64 f_bavail;
- u64 f_files;
- u64 f_ffree;
- u64 f_favail;
- u32 f_fsid;
- char f_basetype[16];
- u32 f_flag;
- u32 f_namemax;
- char f_fstr[32];
- u32 f_filler[16];
-};
-
-static int report_statvfs(struct vfsmount *mnt, struct inode *inode, u32 buf)
-{
- struct kstatfs s;
- int error;
- struct sol_statvfs __user *ss = A(buf);
-
- error = vfs_statfs(mnt->mnt_root, &s);
- if (!error) {
- const char *p = mnt->mnt_sb->s_type->name;
- int i = 0;
- int j = strlen (p);
-
- if (j > 15) j = 15;
- if (IS_RDONLY(inode)) i = 1;
- if (mnt->mnt_flags & MNT_NOSUID) i |= 2;
- if (!sysv_valid_dev(inode->i_sb->s_dev))
- return -EOVERFLOW;
- if (put_user (s.f_bsize, &ss->f_bsize) ||
- __put_user (0, &ss->f_frsize) ||
- __put_user (s.f_blocks, &ss->f_blocks) ||
- __put_user (s.f_bfree, &ss->f_bfree) ||
- __put_user (s.f_bavail, &ss->f_bavail) ||
- __put_user (s.f_files, &ss->f_files) ||
- __put_user (s.f_ffree, &ss->f_ffree) ||
- __put_user (s.f_ffree, &ss->f_favail) ||
- __put_user (sysv_encode_dev(inode->i_sb->s_dev), &ss->f_fsid) ||
- __copy_to_user (ss->f_basetype,p,j) ||
- __put_user (0, (char __user *)&ss->f_basetype[j]) ||
- __put_user (s.f_namelen, &ss->f_namemax) ||
- __put_user (i, &ss->f_flag) ||
- __clear_user (&ss->f_fstr, 32))
- return -EFAULT;
- }
- return error;
-}
-
-static int report_statvfs64(struct vfsmount *mnt, struct inode *inode, u32 buf)
-{
- struct kstatfs s;
- int error;
- struct sol_statvfs64 __user *ss = A(buf);
-
- error = vfs_statfs(mnt->mnt_root, &s);
- if (!error) {
- const char *p = mnt->mnt_sb->s_type->name;
- int i = 0;
- int j = strlen (p);
-
- if (j > 15) j = 15;
- if (IS_RDONLY(inode)) i = 1;
- if (mnt->mnt_flags & MNT_NOSUID) i |= 2;
- if (!sysv_valid_dev(inode->i_sb->s_dev))
- return -EOVERFLOW;
- if (put_user (s.f_bsize, &ss->f_bsize) ||
- __put_user (0, &ss->f_frsize) ||
- __put_user (s.f_blocks, &ss->f_blocks) ||
- __put_user (s.f_bfree, &ss->f_bfree) ||
- __put_user (s.f_bavail, &ss->f_bavail) ||
- __put_user (s.f_files, &ss->f_files) ||
- __put_user (s.f_ffree, &ss->f_ffree) ||
- __put_user (s.f_ffree, &ss->f_favail) ||
- __put_user (sysv_encode_dev(inode->i_sb->s_dev), &ss->f_fsid) ||
- __copy_to_user (ss->f_basetype,p,j) ||
- __put_user (0, (char __user *)&ss->f_basetype[j]) ||
- __put_user (s.f_namelen, &ss->f_namemax) ||
- __put_user (i, &ss->f_flag) ||
- __clear_user (&ss->f_fstr, 32))
- return -EFAULT;
- }
- return error;
-}
-
-asmlinkage int solaris_statvfs(u32 path, u32 buf)
-{
- struct nameidata nd;
- int error;
-
- error = user_path_walk(A(path),&nd);
- if (!error) {
- struct inode *inode = nd.path.dentry->d_inode;
- error = report_statvfs(nd.path.mnt, inode, buf);
- path_put(&nd.path);
- }
- return error;
-}
-
-asmlinkage int solaris_fstatvfs(unsigned int fd, u32 buf)
-{
- struct file * file;
- int error;
-
- error = -EBADF;
- file = fget(fd);
- if (file) {
- error = report_statvfs(file->f_path.mnt, file->f_path.dentry->d_inode, buf);
- fput(file);
- }
-
- return error;
-}
-
-asmlinkage int solaris_statvfs64(u32 path, u32 buf)
-{
- struct nameidata nd;
- int error;
-
- lock_kernel();
- error = user_path_walk(A(path), &nd);
- if (!error) {
- struct inode *inode = nd.path.dentry->d_inode;
- error = report_statvfs64(nd.path.mnt, inode, buf);
- path_put(&nd.path);
- }
- unlock_kernel();
- return error;
-}
-
-asmlinkage int solaris_fstatvfs64(unsigned int fd, u32 buf)
-{
- struct file * file;
- int error;
-
- error = -EBADF;
- file = fget(fd);
- if (file) {
- lock_kernel();
- error = report_statvfs64(file->f_path.mnt, file->f_path.dentry->d_inode, buf);
- unlock_kernel();
- fput(file);
- }
- return error;
-}
-
-extern asmlinkage long sparc32_open(const char * filename, int flags, int mode);
-
-asmlinkage int solaris_open(u32 fname, int flags, u32 mode)
-{
- const char *filename = (const char *)(long)fname;
- int fl = flags & 0xf;
-
- /* Translate flags first. */
- if (flags & 0x2000) fl |= O_LARGEFILE;
- if (flags & 0x8050) fl |= O_SYNC;
- if (flags & 0x80) fl |= O_NONBLOCK;
- if (flags & 0x100) fl |= O_CREAT;
- if (flags & 0x200) fl |= O_TRUNC;
- if (flags & 0x400) fl |= O_EXCL;
- if (flags & 0x800) fl |= O_NOCTTY;
- flags = fl;
-
- return sparc32_open(filename, flags, mode);
-}
-
-#define SOL_F_SETLK 6
-#define SOL_F_SETLKW 7
-#define SOL_F_FREESP 11
-#define SOL_F_ISSTREAM 13
-#define SOL_F_GETLK 14
-#define SOL_F_PRIV 15
-#define SOL_F_NPRIV 16
-#define SOL_F_QUOTACTL 17
-#define SOL_F_BLOCKS 18
-#define SOL_F_BLKSIZE 19
-#define SOL_F_GETOWN 23
-#define SOL_F_SETOWN 24
-
-struct sol_flock {
- short l_type;
- short l_whence;
- u32 l_start;
- u32 l_len;
- s32 l_sysid;
- s32 l_pid;
- s32 l_pad[4];
-};
-
-asmlinkage int solaris_fcntl(unsigned fd, unsigned cmd, u32 arg)
-{
- int (*sys_fcntl)(unsigned,unsigned,unsigned long) =
- (int (*)(unsigned,unsigned,unsigned long))SYS(fcntl);
- int ret, flags;
-
- switch (cmd) {
- case F_DUPFD:
- case F_GETFD:
- case F_SETFD: return sys_fcntl(fd, cmd, (unsigned long)arg);
- case F_GETFL:
- flags = sys_fcntl(fd, cmd, 0);
- ret = flags & 0xf;
- if (flags & O_SYNC) ret |= 0x8050;
- if (flags & O_NONBLOCK) ret |= 0x80;
- return ret;
- case F_SETFL:
- flags = arg & 0xf;
- if (arg & 0x8050) flags |= O_SYNC;
- if (arg & 0x80) flags |= O_NONBLOCK;
- return sys_fcntl(fd, cmd, (long)flags);
- case SOL_F_GETLK:
- case SOL_F_SETLK:
- case SOL_F_SETLKW:
- {
- struct flock f;
- struct sol_flock __user *p = A(arg);
- mm_segment_t old_fs = get_fs();
-
- switch (cmd) {
- case SOL_F_GETLK: cmd = F_GETLK; break;
- case SOL_F_SETLK: cmd = F_SETLK; break;
- case SOL_F_SETLKW: cmd = F_SETLKW; break;
- }
-
- if (get_user (f.l_type, &p->l_type) ||
- __get_user (f.l_whence, &p->l_whence) ||
- __get_user (f.l_start, &p->l_start) ||
- __get_user (f.l_len, &p->l_len) ||
- __get_user (f.l_pid, &p->l_sysid))
- return -EFAULT;
-
- set_fs(KERNEL_DS);
- ret = sys_fcntl(fd, cmd, (unsigned long)&f);
- set_fs(old_fs);
-
- if (__put_user (f.l_type, &p->l_type) ||
- __put_user (f.l_whence, &p->l_whence) ||
- __put_user (f.l_start, &p->l_start) ||
- __put_user (f.l_len, &p->l_len) ||
- __put_user (f.l_pid, &p->l_pid) ||
- __put_user (0, &p->l_sysid))
- return -EFAULT;
-
- return ret;
- }
- case SOL_F_FREESP:
- {
- int length;
- int (*sys_newftruncate)(unsigned int, unsigned long)=
- (int (*)(unsigned int, unsigned long))SYS(ftruncate);
-
- if (get_user(length, &((struct sol_flock __user *)A(arg))->l_start))
- return -EFAULT;
-
- return sys_newftruncate(fd, length);
- }
- };
- return -EINVAL;
-}
-
-asmlinkage int solaris_ulimit(int cmd, int val)
-{
- switch (cmd) {
- case 1: /* UL_GETFSIZE - in 512B chunks */
- return current->signal->rlim[RLIMIT_FSIZE].rlim_cur >> 9;
- case 2: /* UL_SETFSIZE */
- if ((unsigned long)val > (LONG_MAX>>9)) return -ERANGE;
- val <<= 9;
- task_lock(current->group_leader);
- if (val > current->signal->rlim[RLIMIT_FSIZE].rlim_max) {
- if (!capable(CAP_SYS_RESOURCE)) {
- task_unlock(current->group_leader);
- return -EPERM;
- }
- current->signal->rlim[RLIMIT_FSIZE].rlim_max = val;
- }
- current->signal->rlim[RLIMIT_FSIZE].rlim_cur = val;
- task_unlock(current->group_leader);
- return 0;
- case 3: /* UL_GMEMLIM */
- return current->signal->rlim[RLIMIT_DATA].rlim_cur;
- case 4: /* UL_GDESLIM */
- return sysctl_nr_open;
- }
- return -EINVAL;
-}
-
-/* At least at the time I'm writing this, Linux doesn't have ACLs, so we
- just fake this */
-asmlinkage int solaris_acl(u32 filename, int cmd, int nentries, u32 aclbufp)
-{
- return -ENOSYS;
-}
-
-asmlinkage int solaris_facl(unsigned int fd, int cmd, int nentries, u32 aclbufp)
-{
- return -ENOSYS;
-}
-
-asmlinkage int solaris_pread(unsigned int fd, char __user *buf, u32 count, u32 pos)
-{
- ssize_t (*sys_pread64)(unsigned int, char __user *, size_t, loff_t) =
- (ssize_t (*)(unsigned int, char __user *, size_t, loff_t))SYS(pread64);
-
- return sys_pread64(fd, buf, count, (loff_t)pos);
-}
-
-asmlinkage int solaris_pwrite(unsigned int fd, char __user *buf, u32 count, u32 pos)
-{
- ssize_t (*sys_pwrite64)(unsigned int, char __user *, size_t, loff_t) =
- (ssize_t (*)(unsigned int, char __user *, size_t, loff_t))SYS(pwrite64);
-
- return sys_pwrite64(fd, buf, count, (loff_t)pos);
-}
-
-/* POSIX.1 names */
-#define _PC_LINK_MAX 1
-#define _PC_MAX_CANON 2
-#define _PC_MAX_INPUT 3
-#define _PC_NAME_MAX 4
-#define _PC_PATH_MAX 5
-#define _PC_PIPE_BUF 6
-#define _PC_NO_TRUNC 7
-#define _PC_VDISABLE 8
-#define _PC_CHOWN_RESTRICTED 9
-/* POSIX.4 names */
-#define _PC_ASYNC_IO 10
-#define _PC_PRIO_IO 11
-#define _PC_SYNC_IO 12
-#define _PC_LAST 12
-
-/* This is not a real and complete implementation yet, just to keep
- * the easy Solaris binaries happy.
- */
-asmlinkage int solaris_fpathconf(int fd, int name)
-{
- int ret;
-
- switch(name) {
- case _PC_LINK_MAX:
- ret = LINK_MAX;
- break;
- case _PC_MAX_CANON:
- ret = MAX_CANON;
- break;
- case _PC_MAX_INPUT:
- ret = MAX_INPUT;
- break;
- case _PC_NAME_MAX:
- ret = NAME_MAX;
- break;
- case _PC_PATH_MAX:
- ret = PATH_MAX;
- break;
- case _PC_PIPE_BUF:
- ret = PIPE_BUF;
- break;
- case _PC_CHOWN_RESTRICTED:
- ret = 1;
- break;
- case _PC_NO_TRUNC:
- case _PC_VDISABLE:
- ret = 0;
- break;
- default:
- ret = -EINVAL;
- break;
- }
- return ret;
-}
-
-asmlinkage int solaris_pathconf(u32 path, int name)
-{
- return solaris_fpathconf(0, name);
-}
-
-/* solaris_llseek returns long long - quite difficult */
-asmlinkage long solaris_llseek(struct pt_regs *regs, u32 off_hi, u32 off_lo, int whence)
-{
- int (*sys_llseek)(unsigned int, unsigned long, unsigned long, loff_t __user *, unsigned int) =
- (int (*)(unsigned int, unsigned long, unsigned long, loff_t __user *, unsigned int))SYS(_llseek);
- int ret;
- mm_segment_t old_fs = get_fs();
- loff_t retval;
-
- set_fs(KERNEL_DS);
- ret = sys_llseek((unsigned int)regs->u_regs[UREG_I0], off_hi, off_lo, &retval, whence);
- set_fs(old_fs);
- if (ret < 0) return ret;
- regs->u_regs[UREG_I1] = (u32)retval;
- return (retval >> 32);
-}
-
-/* Have to mask out all but lower 3 bits */
-asmlinkage int solaris_access(u32 filename, long mode)
-{
- int (*sys_access)(const char __user *, int) =
- (int (*)(const char __user *, int))SYS(access);
-
- return sys_access(A(filename), mode & 7);
-}
+++ /dev/null
-/* $Id: ioctl.c,v 1.17 2002/02/08 03:57:14 davem Exp $
- * ioctl.c: Solaris ioctl emulation.
- *
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- * Copyright (C) 1997,1998 Patrik Rak (prak3264@ss1000.ms.mff.cuni.cz)
- *
- * Streams & timod emulation based on code
- * Copyright (C) 1995, 1996 Mike Jagdis (jaggy@purplet.demon.co.uk)
- *
- * 1999-08-19 Implemented solaris 'm' (mag tape) and
- * 'O' (openprom) ioctls, by Jason Rappleye
- * (rappleye@ccr.buffalo.edu)
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-#include <linux/syscalls.h>
-#include <linux/ioctl.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/netdevice.h>
-#include <linux/mtio.h>
-#include <linux/time.h>
-#include <linux/rcupdate.h>
-#include <linux/compat.h>
-
-#include <net/sock.h>
-#include <net/net_namespace.h>
-
-#include <asm/uaccess.h>
-#include <asm/termios.h>
-#include <asm/openpromio.h>
-
-#include "conv.h"
-#include "socksys.h"
-
-extern asmlinkage int compat_sys_ioctl(unsigned int fd, unsigned int cmd,
- u32 arg);
-asmlinkage int solaris_ioctl(unsigned int fd, unsigned int cmd, u32 arg);
-
-extern int timod_putmsg(unsigned int fd, char __user *ctl_buf, int ctl_len,
- char __user *data_buf, int data_len, int flags);
-extern int timod_getmsg(unsigned int fd, char __user *ctl_buf, int ctl_maxlen, int __user *ctl_len,
- char __user *data_buf, int data_maxlen, int __user *data_len, int *flags);
-
-/* termio* stuff {{{ */
-
-struct solaris_termios {
- u32 c_iflag;
- u32 c_oflag;
- u32 c_cflag;
- u32 c_lflag;
- u8 c_cc[19];
-};
-
-struct solaris_termio {
- u16 c_iflag;
- u16 c_oflag;
- u16 c_cflag;
- u16 c_lflag;
- s8 c_line;
- u8 c_cc[8];
-};
-
-struct solaris_termiox {
- u16 x_hflag;
- u16 x_cflag;
- u16 x_rflag[5];
- u16 x_sflag;
-};
-
-static u32 solaris_to_linux_cflag(u32 cflag)
-{
- cflag &= 0x7fdff000;
- if (cflag & 0x200000) {
- int baud = cflag & 0xf;
- cflag &= ~0x20000f;
- switch (baud) {
- case 0: baud = B57600; break;
- case 1: baud = B76800; break;
- case 2: baud = B115200; break;
- case 3: baud = B153600; break;
- case 4: baud = B230400; break;
- case 5: baud = B307200; break;
- case 6: baud = B460800; break;
- }
- cflag |= CBAUDEX | baud;
- }
- return cflag;
-}
-
-static u32 linux_to_solaris_cflag(u32 cflag)
-{
- cflag &= ~(CMSPAR | CIBAUD);
- if (cflag & CBAUDEX) {
- int baud = cflag & CBAUD;
- cflag &= ~CBAUD;
- switch (baud) {
- case B57600: baud = 0; break;
- case B76800: baud = 1; break;
- case B115200: baud = 2; break;
- case B153600: baud = 3; break;
- case B230400: baud = 4; break;
- case B307200: baud = 5; break;
- case B460800: baud = 6; break;
- case B614400: baud = 7; break;
- case B921600: baud = 8; break;
-#if 0
- case B1843200: baud = 9; break;
-#endif
- }
- cflag |= 0x200000 | baud;
- }
- return cflag;
-}
-
-static inline int linux_to_solaris_termio(unsigned int fd, unsigned int cmd, u32 arg)
-{
- struct solaris_termio __user *p = A(arg);
- int ret;
-
- ret = sys_ioctl(fd, cmd, (unsigned long)p);
- if (!ret) {
- u32 cflag;
-
- if (__get_user (cflag, &p->c_cflag))
- return -EFAULT;
- cflag = linux_to_solaris_cflag(cflag);
- if (__put_user (cflag, &p->c_cflag))
- return -EFAULT;
- }
- return ret;
-}
-
-static int solaris_to_linux_termio(unsigned int fd, unsigned int cmd, u32 arg)
-{
- int ret;
- struct solaris_termio s;
- mm_segment_t old_fs = get_fs();
-
- if (copy_from_user (&s, (struct solaris_termio __user *)A(arg), sizeof(struct solaris_termio)))
- return -EFAULT;
- s.c_cflag = solaris_to_linux_cflag(s.c_cflag);
- set_fs(KERNEL_DS);
- ret = sys_ioctl(fd, cmd, (unsigned long)&s);
- set_fs(old_fs);
- return ret;
-}
-
-static inline int linux_to_solaris_termios(unsigned int fd, unsigned int cmd, u32 arg)
-{
- int ret;
- struct solaris_termios s;
- mm_segment_t old_fs = get_fs();
-
- set_fs(KERNEL_DS);
- ret = sys_ioctl(fd, cmd, (unsigned long)&s);
- set_fs(old_fs);
- if (!ret) {
- struct solaris_termios __user *p = A(arg);
- if (put_user (s.c_iflag, &p->c_iflag) ||
- __put_user (s.c_oflag, &p->c_oflag) ||
- __put_user (linux_to_solaris_cflag(s.c_cflag), &p->c_cflag) ||
- __put_user (s.c_lflag, &p->c_lflag) ||
- __copy_to_user (p->c_cc, s.c_cc, 16) ||
- __clear_user (p->c_cc + 16, 2))
- return -EFAULT;
- }
- return ret;
-}
-
-static int solaris_to_linux_termios(unsigned int fd, unsigned int cmd, u32 arg)
-{
- int ret;
- struct solaris_termios s;
- struct solaris_termios __user *p = A(arg);
- mm_segment_t old_fs = get_fs();
-
- set_fs(KERNEL_DS);
- ret = sys_ioctl(fd, TCGETS, (unsigned long)&s);
- set_fs(old_fs);
- if (ret) return ret;
- if (put_user (s.c_iflag, &p->c_iflag) ||
- __put_user (s.c_oflag, &p->c_oflag) ||
- __put_user (s.c_cflag, &p->c_cflag) ||
- __put_user (s.c_lflag, &p->c_lflag) ||
- __copy_from_user (s.c_cc, p->c_cc, 16))
- return -EFAULT;
- s.c_cflag = solaris_to_linux_cflag(s.c_cflag);
- set_fs(KERNEL_DS);
- ret = sys_ioctl(fd, cmd, (unsigned long)&s);
- set_fs(old_fs);
- return ret;
-}
-
-static inline int solaris_T(unsigned int fd, unsigned int cmd, u32 arg)
-{
- switch (cmd & 0xff) {
- case 1: /* TCGETA */
- return linux_to_solaris_termio(fd, TCGETA, arg);
- case 2: /* TCSETA */
- return solaris_to_linux_termio(fd, TCSETA, arg);
- case 3: /* TCSETAW */
- return solaris_to_linux_termio(fd, TCSETAW, arg);
- case 4: /* TCSETAF */
- return solaris_to_linux_termio(fd, TCSETAF, arg);
- case 5: /* TCSBRK */
- return sys_ioctl(fd, TCSBRK, arg);
- case 6: /* TCXONC */
- return sys_ioctl(fd, TCXONC, arg);
- case 7: /* TCFLSH */
- return sys_ioctl(fd, TCFLSH, arg);
- case 13: /* TCGETS */
- return linux_to_solaris_termios(fd, TCGETS, arg);
- case 14: /* TCSETS */
- return solaris_to_linux_termios(fd, TCSETS, arg);
- case 15: /* TCSETSW */
- return solaris_to_linux_termios(fd, TCSETSW, arg);
- case 16: /* TCSETSF */
- return solaris_to_linux_termios(fd, TCSETSF, arg);
- case 103: /* TIOCSWINSZ */
- return sys_ioctl(fd, TIOCSWINSZ, arg);
- case 104: /* TIOCGWINSZ */
- return sys_ioctl(fd, TIOCGWINSZ, arg);
- }
- return -ENOSYS;
-}
-
-static inline int solaris_t(unsigned int fd, unsigned int cmd, u32 arg)
-{
- switch (cmd & 0xff) {
- case 20: /* TIOCGPGRP */
- return sys_ioctl(fd, TIOCGPGRP, arg);
- case 21: /* TIOCSPGRP */
- return sys_ioctl(fd, TIOCSPGRP, arg);
- }
- return -ENOSYS;
-}
-
-/* }}} */
-
-/* A pseudo STREAMS support {{{ */
-
-struct strioctl {
- int cmd, timeout, len;
- u32 data;
-};
-
-struct solaris_si_sockparams {
- int sp_family;
- int sp_type;
- int sp_protocol;
-};
-
-struct solaris_o_si_udata {
- int tidusize;
- int addrsize;
- int optsize;
- int etsdusize;
- int servtype;
- int so_state;
- int so_options;
- int tsdusize;
-};
-
-struct solaris_si_udata {
- int tidusize;
- int addrsize;
- int optsize;
- int etsdusize;
- int servtype;
- int so_state;
- int so_options;
- int tsdusize;
- struct solaris_si_sockparams sockparams;
-};
-
-#define SOLARIS_MODULE_TIMOD 0
-#define SOLARIS_MODULE_SOCKMOD 1
-#define SOLARIS_MODULE_MAX 2
-
-static struct module_info {
- const char *name;
- /* can be expanded further if needed */
-} module_table[ SOLARIS_MODULE_MAX + 1 ] = {
- /* the ordering here must match the module numbers above! */
- { "timod" },
- { "sockmod" },
- { NULL }
-};
-
-static inline int solaris_sockmod(unsigned int fd, unsigned int cmd, u32 arg)
-{
- struct inode *ino;
- struct fdtable *fdt;
- /* I wonder which of these tests are superfluous... --patrik */
- rcu_read_lock();
- fdt = files_fdtable(current->files);
- if (! fdt->fd[fd] ||
- ! fdt->fd[fd]->f_path.dentry ||
- ! (ino = fdt->fd[fd]->f_path.dentry->d_inode) ||
- ! S_ISSOCK(ino->i_mode)) {
- rcu_read_unlock();
- return TBADF;
- }
- rcu_read_unlock();
-
- switch (cmd & 0xff) {
- case 109: /* SI_SOCKPARAMS */
- {
- struct solaris_si_sockparams si;
- if (copy_from_user (&si, A(arg), sizeof(si)))
- return (EFAULT << 8) | TSYSERR;
-
- /* Should we modify socket ino->socket_i.ops and type? */
- return 0;
- }
- case 110: /* SI_GETUDATA */
- {
- int etsdusize, servtype;
- struct solaris_si_udata __user *p = A(arg);
- switch (SOCKET_I(ino)->type) {
- case SOCK_STREAM:
- etsdusize = 1;
- servtype = 2;
- break;
- default:
- etsdusize = -2;
- servtype = 3;
- break;
- }
- if (put_user(16384, &p->tidusize) ||
- __put_user(sizeof(struct sockaddr), &p->addrsize) ||
- __put_user(-1, &p->optsize) ||
- __put_user(etsdusize, &p->etsdusize) ||
- __put_user(servtype, &p->servtype) ||
- __put_user(0, &p->so_state) ||
- __put_user(0, &p->so_options) ||
- __put_user(16384, &p->tsdusize) ||
- __put_user(SOCKET_I(ino)->ops->family, &p->sockparams.sp_family) ||
- __put_user(SOCKET_I(ino)->type, &p->sockparams.sp_type) ||
- __put_user(SOCKET_I(ino)->ops->family, &p->sockparams.sp_protocol))
- return (EFAULT << 8) | TSYSERR;
- return 0;
- }
- case 101: /* O_SI_GETUDATA */
- {
- int etsdusize, servtype;
- struct solaris_o_si_udata __user *p = A(arg);
- switch (SOCKET_I(ino)->type) {
- case SOCK_STREAM:
- etsdusize = 1;
- servtype = 2;
- break;
- default:
- etsdusize = -2;
- servtype = 3;
- break;
- }
- if (put_user(16384, &p->tidusize) ||
- __put_user(sizeof(struct sockaddr), &p->addrsize) ||
- __put_user(-1, &p->optsize) ||
- __put_user(etsdusize, &p->etsdusize) ||
- __put_user(servtype, &p->servtype) ||
- __put_user(0, &p->so_state) ||
- __put_user(0, &p->so_options) ||
- __put_user(16384, &p->tsdusize))
- return (EFAULT << 8) | TSYSERR;
- return 0;
- }
- case 102: /* SI_SHUTDOWN */
- case 103: /* SI_LISTEN */
- case 104: /* SI_SETMYNAME */
- case 105: /* SI_SETPEERNAME */
- case 106: /* SI_GETINTRANSIT */
- case 107: /* SI_TCL_LINK */
- case 108: /* SI_TCL_UNLINK */
- ;
- }
- return TNOTSUPPORT;
-}
-
-static inline int solaris_timod(unsigned int fd, unsigned int cmd, u32 arg,
- int len, int __user *len_p)
-{
- int ret;
-
- switch (cmd & 0xff) {
- case 141: /* TI_OPTMGMT */
- {
- int i;
- u32 prim;
- SOLD("TI_OPMGMT entry");
- ret = timod_putmsg(fd, A(arg), len, NULL, -1, 0);
- SOLD("timod_putmsg() returned");
- if (ret)
- return (-ret << 8) | TSYSERR;
- i = MSG_HIPRI;
- SOLD("calling timod_getmsg()");
- ret = timod_getmsg(fd, A(arg), len, len_p, NULL, -1, NULL, &i);
- SOLD("timod_getmsg() returned");
- if (ret)
- return (-ret << 8) | TSYSERR;
- SOLD("ret ok");
- if (get_user(prim, (u32 __user *)A(arg)))
- return (EFAULT << 8) | TSYSERR;
- SOLD("got prim");
- if (prim == T_ERROR_ACK) {
- u32 tmp, tmp2;
- SOLD("prim is T_ERROR_ACK");
- if (get_user(tmp, (u32 __user *)A(arg)+3) ||
- get_user(tmp2, (u32 __user *)A(arg)+2))
- return (EFAULT << 8) | TSYSERR;
- return (tmp2 << 8) | tmp;
- }
- SOLD("TI_OPMGMT return 0");
- return 0;
- }
- case 142: /* TI_BIND */
- {
- int i;
- u32 prim;
- SOLD("TI_BIND entry");
- ret = timod_putmsg(fd, A(arg), len, NULL, -1, 0);
- SOLD("timod_putmsg() returned");
- if (ret)
- return (-ret << 8) | TSYSERR;
- len = 1024; /* Solaris allows arbitrary return size */
- i = MSG_HIPRI;
- SOLD("calling timod_getmsg()");
- ret = timod_getmsg(fd, A(arg), len, len_p, NULL, -1, NULL, &i);
- SOLD("timod_getmsg() returned");
- if (ret)
- return (-ret << 8) | TSYSERR;
- SOLD("ret ok");
- if (get_user(prim, (u32 __user *)A(arg)))
- return (EFAULT << 8) | TSYSERR;
- SOLD("got prim");
- if (prim == T_ERROR_ACK) {
- u32 tmp, tmp2;
- SOLD("prim is T_ERROR_ACK");
- if (get_user(tmp, (u32 __user *)A(arg)+3) ||
- get_user(tmp2, (u32 __user *)A(arg)+2))
- return (EFAULT << 8) | TSYSERR;
- return (tmp2 << 8) | tmp;
- }
- SOLD("no ERROR_ACK requested");
- if (prim != T_OK_ACK)
- return TBADSEQ;
- SOLD("OK_ACK requested");
- i = MSG_HIPRI;
- SOLD("calling timod_getmsg()");
- ret = timod_getmsg(fd, A(arg), len, len_p, NULL, -1, NULL, &i);
- SOLD("timod_getmsg() returned");
- if (ret)
- return (-ret << 8) | TSYSERR;
- SOLD("TI_BIND return ok");
- return 0;
- }
- case 140: /* TI_GETINFO */
- case 143: /* TI_UNBIND */
- case 144: /* TI_GETMYNAME */
- case 145: /* TI_GETPEERNAME */
- case 146: /* TI_SETMYNAME */
- case 147: /* TI_SETPEERNAME */
- ;
- }
- return TNOTSUPPORT;
-}
-
-static inline int solaris_S(struct file *filp, unsigned int fd, unsigned int cmd, u32 arg)
-{
- char *p;
- int ret;
- mm_segment_t old_fs;
- struct strioctl si;
- struct inode *ino;
- struct sol_socket_struct *sock;
- struct module_info *mi;
-
- ino = filp->f_path.dentry->d_inode;
- if (!S_ISSOCK(ino->i_mode))
- return -EBADF;
- sock = filp->private_data;
- if (! sock) {
- printk("solaris_S: NULL private_data\n");
- return -EBADF;
- }
- if (sock->magic != SOLARIS_SOCKET_MAGIC) {
- printk("solaris_S: invalid magic\n");
- return -EBADF;
- }
-
-
- switch (cmd & 0xff) {
- case 1: /* I_NREAD */
- return -ENOSYS;
- case 2: /* I_PUSH */
- {
- p = getname (A(arg));
- if (IS_ERR (p))
- return PTR_ERR(p);
- ret = -EINVAL;
- for (mi = module_table; mi->name; mi++) {
- if (strcmp(mi->name, p) == 0) {
- sol_module m;
- if (sock->modcount >= MAX_NR_STREAM_MODULES) {
- ret = -ENXIO;
- break;
- }
- m = (sol_module) (mi - module_table);
- sock->module[sock->modcount++] = m;
- ret = 0;
- break;
- }
- }
- putname (p);
- return ret;
- }
- case 3: /* I_POP */
- if (sock->modcount <= 0) return -EINVAL;
- sock->modcount--;
- return 0;
- case 4: /* I_LOOK */
- {
- const char *p;
- if (sock->modcount <= 0) return -EINVAL;
- p = module_table[(unsigned)sock->module[sock->modcount]].name;
- if (copy_to_user (A(arg), p, strlen(p)))
- return -EFAULT;
- return 0;
- }
- case 5: /* I_FLUSH */
- return 0;
- case 8: /* I_STR */
- if (copy_from_user(&si, A(arg), sizeof(struct strioctl)))
- return -EFAULT;
- /* We ignore what module is actually at the top of stack. */
- switch ((si.cmd >> 8) & 0xff) {
- case 'I':
- return solaris_sockmod(fd, si.cmd, si.data);
- case 'T':
- return solaris_timod(fd, si.cmd, si.data, si.len,
- &((struct strioctl __user *)A(arg))->len);
- default:
- return solaris_ioctl(fd, si.cmd, si.data);
- }
- case 9: /* I_SETSIG */
- return sys_ioctl(fd, FIOSETOWN, current->pid);
- case 10: /* I_GETSIG */
- old_fs = get_fs();
- set_fs(KERNEL_DS);
- sys_ioctl(fd, FIOGETOWN, (unsigned long)&ret);
- set_fs(old_fs);
- if (ret == current->pid) return 0x3ff;
- else return -EINVAL;
- case 11: /* I_FIND */
- {
- int i;
- p = getname (A(arg));
- if (IS_ERR (p))
- return PTR_ERR(p);
- ret = 0;
- for (i = 0; i < sock->modcount; i++) {
- unsigned m = sock->module[i];
- if (strcmp(module_table[m].name, p) == 0) {
- ret = 1;
- break;
- }
- }
- putname (p);
- return ret;
- }
- case 19: /* I_SWROPT */
- case 32: /* I_SETCLTIME */
- return 0; /* Lie */
- }
- return -ENOSYS;
-}
-
-static inline int solaris_s(unsigned int fd, unsigned int cmd, u32 arg)
-{
- switch (cmd & 0xff) {
- case 0: /* SIOCSHIWAT */
- case 2: /* SIOCSLOWAT */
- return 0; /* We don't support them */
- case 1: /* SIOCGHIWAT */
- case 3: /* SIOCGLOWAT */
- if (put_user (0, (u32 __user *)A(arg)))
- return -EFAULT;
- return 0; /* Lie */
- case 7: /* SIOCATMARK */
- return sys_ioctl(fd, SIOCATMARK, arg);
- case 8: /* SIOCSPGRP */
- return sys_ioctl(fd, SIOCSPGRP, arg);
- case 9: /* SIOCGPGRP */
- return sys_ioctl(fd, SIOCGPGRP, arg);
- }
- return -ENOSYS;
-}
-
-static inline int solaris_r(unsigned int fd, unsigned int cmd, u32 arg)
-{
- switch (cmd & 0xff) {
- case 10: /* SIOCADDRT */
- return compat_sys_ioctl(fd, SIOCADDRT, arg);
- case 11: /* SIOCDELRT */
- return compat_sys_ioctl(fd, SIOCDELRT, arg);
- }
- return -ENOSYS;
-}
-
-static inline int solaris_i(unsigned int fd, unsigned int cmd, u32 arg)
-{
- switch (cmd & 0xff) {
- case 12: /* SIOCSIFADDR */
- return compat_sys_ioctl(fd, SIOCSIFADDR, arg);
- case 13: /* SIOCGIFADDR */
- return compat_sys_ioctl(fd, SIOCGIFADDR, arg);
- case 14: /* SIOCSIFDSTADDR */
- return compat_sys_ioctl(fd, SIOCSIFDSTADDR, arg);
- case 15: /* SIOCGIFDSTADDR */
- return compat_sys_ioctl(fd, SIOCGIFDSTADDR, arg);
- case 16: /* SIOCSIFFLAGS */
- return compat_sys_ioctl(fd, SIOCSIFFLAGS, arg);
- case 17: /* SIOCGIFFLAGS */
- return compat_sys_ioctl(fd, SIOCGIFFLAGS, arg);
- case 18: /* SIOCSIFMEM */
- return compat_sys_ioctl(fd, SIOCSIFMEM, arg);
- case 19: /* SIOCGIFMEM */
- return compat_sys_ioctl(fd, SIOCGIFMEM, arg);
- case 20: /* SIOCGIFCONF */
- return compat_sys_ioctl(fd, SIOCGIFCONF, arg);
- case 21: /* SIOCSIFMTU */
- return compat_sys_ioctl(fd, SIOCSIFMTU, arg);
- case 22: /* SIOCGIFMTU */
- return compat_sys_ioctl(fd, SIOCGIFMTU, arg);
- case 23: /* SIOCGIFBRDADDR */
- return compat_sys_ioctl(fd, SIOCGIFBRDADDR, arg);
- case 24: /* SIOCSIFBRDADDR */
- return compat_sys_ioctl(fd, SIOCSIFBRDADDR, arg);
- case 25: /* SIOCGIFNETMASK */
- return compat_sys_ioctl(fd, SIOCGIFNETMASK, arg);
- case 26: /* SIOCSIFNETMASK */
- return compat_sys_ioctl(fd, SIOCSIFNETMASK, arg);
- case 27: /* SIOCGIFMETRIC */
- return compat_sys_ioctl(fd, SIOCGIFMETRIC, arg);
- case 28: /* SIOCSIFMETRIC */
- return compat_sys_ioctl(fd, SIOCSIFMETRIC, arg);
- case 30: /* SIOCSARP */
- return compat_sys_ioctl(fd, SIOCSARP, arg);
- case 31: /* SIOCGARP */
- return compat_sys_ioctl(fd, SIOCGARP, arg);
- case 32: /* SIOCDARP */
- return compat_sys_ioctl(fd, SIOCDARP, arg);
- case 52: /* SIOCGETNAME */
- case 53: /* SIOCGETPEER */
- {
- struct sockaddr uaddr;
- int uaddr_len = sizeof(struct sockaddr), ret;
- long args[3];
- mm_segment_t old_fs = get_fs();
- int (*sys_socketcall)(int, unsigned long *) =
- (int (*)(int, unsigned long *))SYS(socketcall);
-
- args[0] = fd; args[1] = (long)&uaddr; args[2] = (long)&uaddr_len;
- set_fs(KERNEL_DS);
- ret = sys_socketcall(((cmd & 0xff) == 52) ? SYS_GETSOCKNAME : SYS_GETPEERNAME,
- args);
- set_fs(old_fs);
- if (ret >= 0) {
- if (copy_to_user(A(arg), &uaddr, uaddr_len))
- return -EFAULT;
- }
- return ret;
- }
-#if 0
- case 86: /* SIOCSOCKSYS */
- return socksys_syscall(fd, arg);
-#endif
- case 87: /* SIOCGIFNUM */
- {
- struct net_device *d;
- int i = 0;
-
- read_lock_bh(&dev_base_lock);
- for_each_netdev(&init_net, d)
- i++;
- read_unlock_bh(&dev_base_lock);
-
- if (put_user (i, (int __user *)A(arg)))
- return -EFAULT;
- return 0;
- }
- }
- return -ENOSYS;
-}
-
-static int solaris_m(unsigned int fd, unsigned int cmd, u32 arg)
-{
- int ret;
-
- switch (cmd & 0xff) {
- case 1: /* MTIOCTOP */
- ret = sys_ioctl(fd, MTIOCTOP, (unsigned long)&arg);
- break;
- case 2: /* MTIOCGET */
- ret = sys_ioctl(fd, MTIOCGET, (unsigned long)&arg);
- break;
- case 3: /* MTIOCGETDRIVETYPE */
- case 4: /* MTIOCPERSISTENT */
- case 5: /* MTIOCPERSISTENTSTATUS */
- case 6: /* MTIOCLRERR */
- case 7: /* MTIOCGUARANTEEDORDER */
- case 8: /* MTIOCRESERVE */
- case 9: /* MTIOCRELEASE */
- case 10: /* MTIOCFORCERESERVE */
- case 13: /* MTIOCSTATE */
- case 14: /* MTIOCREADIGNOREILI */
- case 15: /* MTIOCREADIGNOREEOFS */
- case 16: /* MTIOCSHORTFMK */
- default:
- ret = -ENOSYS; /* linux doesn't support these */
- break;
- };
-
- return ret;
-}
-
-static int solaris_O(unsigned int fd, unsigned int cmd, u32 arg)
-{
- int ret = -EINVAL;
-
- switch (cmd & 0xff) {
- case 1: /* OPROMGETOPT */
- ret = sys_ioctl(fd, OPROMGETOPT, arg);
- break;
- case 2: /* OPROMSETOPT */
- ret = sys_ioctl(fd, OPROMSETOPT, arg);
- break;
- case 3: /* OPROMNXTOPT */
- ret = sys_ioctl(fd, OPROMNXTOPT, arg);
- break;
- case 4: /* OPROMSETOPT2 */
- ret = sys_ioctl(fd, OPROMSETOPT2, arg);
- break;
- case 5: /* OPROMNEXT */
- ret = sys_ioctl(fd, OPROMNEXT, arg);
- break;
- case 6: /* OPROMCHILD */
- ret = sys_ioctl(fd, OPROMCHILD, arg);
- break;
- case 7: /* OPROMGETPROP */
- ret = sys_ioctl(fd, OPROMGETPROP, arg);
- break;
- case 8: /* OPROMNXTPROP */
- ret = sys_ioctl(fd, OPROMNXTPROP, arg);
- break;
- case 9: /* OPROMU2P */
- ret = sys_ioctl(fd, OPROMU2P, arg);
- break;
- case 10: /* OPROMGETCONS */
- ret = sys_ioctl(fd, OPROMGETCONS, arg);
- break;
- case 11: /* OPROMGETFBNAME */
- ret = sys_ioctl(fd, OPROMGETFBNAME, arg);
- break;
- case 12: /* OPROMGETBOOTARGS */
- ret = sys_ioctl(fd, OPROMGETBOOTARGS, arg);
- break;
- case 13: /* OPROMGETVERSION */
- case 14: /* OPROMPATH2DRV */
- case 15: /* OPROMDEV2PROMNAME */
- case 16: /* OPROMPROM2DEVNAME */
- case 17: /* OPROMGETPROPLEN */
- default:
- ret = -EINVAL;
- break;
- };
- return ret;
-}
-
-/* }}} */
-
-asmlinkage int solaris_ioctl(unsigned int fd, unsigned int cmd, u32 arg)
-{
- struct file *filp;
- int error = -EBADF;
-
- filp = fget(fd);
- if (!filp)
- goto out;
-
- lock_kernel();
- error = -EFAULT;
- switch ((cmd >> 8) & 0xff) {
- case 'S': error = solaris_S(filp, fd, cmd, arg); break;
- case 'T': error = solaris_T(fd, cmd, arg); break;
- case 'i': error = solaris_i(fd, cmd, arg); break;
- case 'r': error = solaris_r(fd, cmd, arg); break;
- case 's': error = solaris_s(fd, cmd, arg); break;
- case 't': error = solaris_t(fd, cmd, arg); break;
- case 'f': error = sys_ioctl(fd, cmd, arg); break;
- case 'm': error = solaris_m(fd, cmd, arg); break;
- case 'O': error = solaris_O(fd, cmd, arg); break;
- default:
- error = -ENOSYS;
- break;
- }
- unlock_kernel();
- fput(filp);
-out:
- if (error == -ENOSYS) {
- unsigned char c = cmd>>8;
-
- if (c < ' ' || c > 126) c = '.';
- printk("solaris_ioctl: Unknown cmd fd(%d) cmd(%08x '%c') arg(%08x)\n",
- (int)fd, (unsigned int)cmd, c, (unsigned int)arg);
- error = -EINVAL;
- }
- return error;
-}
+++ /dev/null
-/* $Id: ipc.c,v 1.5 1999/12/09 00:41:00 davem Exp $
- * ipc.c: Solaris IPC emulation
- *
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/wait.h>
-#include <linux/mm.h>
-#include <linux/shm.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/ipc.h>
-
-#include <asm/uaccess.h>
-#include <asm/string.h>
-
-#include "conv.h"
-
-struct solaris_ipc_perm {
- s32 uid;
- s32 gid;
- s32 cuid;
- s32 cgid;
- u32 mode;
- u32 seq;
- int key;
- s32 pad[4];
-};
-
-struct solaris_shmid_ds {
- struct solaris_ipc_perm shm_perm;
- int shm_segsz;
- u32 shm_amp;
- unsigned short shm_lkcnt;
- char __padxx[2];
- s32 shm_lpid;
- s32 shm_cpid;
- u32 shm_nattch;
- u32 shm_cnattch;
- s32 shm_atime;
- s32 shm_pad1;
- s32 shm_dtime;
- s32 shm_pad2;
- s32 shm_ctime;
- s32 shm_pad3;
- unsigned short shm_cv;
- char shm_pad4[2];
- u32 shm_sptas;
- s32 shm_pad5[2];
-};
-
-asmlinkage long solaris_shmsys(int cmd, u32 arg1, u32 arg2, u32 arg3)
-{
- int (*sys_ipc)(unsigned,int,int,unsigned long,void __user *,long) =
- (int (*)(unsigned,int,int,unsigned long,void __user *,long))SYS(ipc);
- mm_segment_t old_fs;
- unsigned long raddr;
- int ret;
-
- switch (cmd) {
- case 0: /* shmat */
- old_fs = get_fs();
- set_fs(KERNEL_DS);
- ret = sys_ipc(SHMAT, arg1, arg3 & ~0x4000, (unsigned long)&raddr, A(arg2), 0);
- set_fs(old_fs);
- if (ret >= 0) return (u32)raddr;
- else return ret;
- case 1: /* shmctl */
- switch (arg2) {
- case 3: /* SHM_LOCK */
- case 4: /* SHM_UNLOCK */
- return sys_ipc(SHMCTL, arg1, (arg2 == 3) ? SHM_LOCK : SHM_UNLOCK, 0, NULL, 0);
- case 10: /* IPC_RMID */
- return sys_ipc(SHMCTL, arg1, IPC_RMID, 0, NULL, 0);
- case 11: /* IPC_SET */
- {
- struct shmid_ds s;
- struct solaris_shmid_ds __user *p = A(arg3);
-
- if (get_user (s.shm_perm.uid, &p->shm_perm.uid) ||
- __get_user (s.shm_perm.gid, &p->shm_perm.gid) ||
- __get_user (s.shm_perm.mode, &p->shm_perm.mode))
- return -EFAULT;
- old_fs = get_fs();
- set_fs(KERNEL_DS);
- ret = sys_ipc(SHMCTL, arg1, IPC_SET, 0, &s, 0);
- set_fs(old_fs);
- return ret;
- }
- case 12: /* IPC_STAT */
- {
- struct shmid_ds s;
- struct solaris_shmid_ds __user *p = A(arg3);
-
- old_fs = get_fs();
- set_fs(KERNEL_DS);
- ret = sys_ipc(SHMCTL, arg1, IPC_SET, 0, &s, 0);
- set_fs(old_fs);
- if (put_user (s.shm_perm.uid, &(p->shm_perm.uid)) ||
- __put_user (s.shm_perm.gid, &(p->shm_perm.gid)) ||
- __put_user (s.shm_perm.cuid, &(p->shm_perm.cuid)) ||
- __put_user (s.shm_perm.cgid, &(p->shm_perm.cgid)) ||
- __put_user (s.shm_perm.mode, &(p->shm_perm.mode)) ||
- __put_user (s.shm_perm.seq, &(p->shm_perm.seq)) ||
- __put_user (s.shm_perm.key, &(p->shm_perm.key)) ||
- __put_user (s.shm_segsz, &(p->shm_segsz)) ||
- __put_user (s.shm_lpid, &(p->shm_lpid)) ||
- __put_user (s.shm_cpid, &(p->shm_cpid)) ||
- __put_user (s.shm_nattch, &(p->shm_nattch)) ||
- __put_user (s.shm_atime, &(p->shm_atime)) ||
- __put_user (s.shm_dtime, &(p->shm_dtime)) ||
- __put_user (s.shm_ctime, &(p->shm_ctime)))
- return -EFAULT;
- return ret;
- }
- default: return -EINVAL;
- }
- case 2: /* shmdt */
- return sys_ipc(SHMDT, 0, 0, 0, A(arg1), 0);
- case 3: /* shmget */
- return sys_ipc(SHMGET, arg1, arg2, arg3, NULL, 0);
- }
- return -EINVAL;
-}
+++ /dev/null
-/* $Id: misc.c,v 1.36 2002/02/09 19:49:31 davem Exp $
- * misc.c: Miscellaneous syscall emulation for Solaris
- *
- * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/utsname.h>
-#include <linux/limits.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/tty.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/timex.h>
-#include <linux/major.h>
-#include <linux/compat.h>
-
-#include <asm/uaccess.h>
-#include <asm/string.h>
-#include <asm/oplib.h>
-#include <asm/idprom.h>
-#include <asm/smp.h>
-#include <asm/prom.h>
-
-#include "conv.h"
-
-/* Conversion from Linux to Solaris errnos. 0-34 are identity mapped.
- Some Linux errnos (EPROCLIM, EDOTDOT, ERREMOTE, EUCLEAN, ENOTNAM,
- ENAVAIL, EISNAM, EREMOTEIO, ENOMEDIUM, EMEDIUMTYPE) have no Solaris
- equivalents. I return EINVAL in that case, which is very wrong. If
- someone suggest a better value for them, you're welcomed.
- On the other side, Solaris ECANCELED and ENOTSUP have no Linux equivalents,
- but that doesn't matter here. --jj */
-int solaris_err_table[] = {
-/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
-/* 10 */ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
-/* 20 */ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
-/* 30 */ 30, 31, 32, 33, 34, 22, 150, 149, 95, 96,
-/* 40 */ 97, 98, 99, 120, 121, 122, 123, 124, 125, 126,
-/* 50 */ 127, 128, 129, 130, 131, 132, 133, 134, 143, 144,
-/* 60 */ 145, 146, 90, 78, 147, 148, 93, 22, 94, 49,
-/* 70 */ 151, 66, 60, 62, 63, 35, 77, 36, 45, 46,
-/* 80 */ 64, 22, 67, 68, 69, 70, 71, 74, 22, 82,
-/* 90 */ 89, 92, 79, 81, 37, 38, 39, 40, 41, 42,
-/* 100 */ 43, 44, 50, 51, 52, 53, 54, 55, 56, 57,
-/* 110 */ 87, 61, 84, 65, 83, 80, 91, 22, 22, 22,
-/* 120 */ 22, 22, 88, 86, 85, 22, 22,
-};
-
-#define SOLARIS_NR_OPEN 256
-
-static u32 do_solaris_mmap(u32 addr, u32 len, u32 prot, u32 flags, u32 fd, u64 off)
-{
- struct file *file = NULL;
- unsigned long retval, ret_type;
-
- /* Do we need it here? */
- set_personality(PER_SVR4);
- if (flags & MAP_NORESERVE) {
- static int cnt;
-
- if (cnt < 5) {
- printk("%s: unimplemented Solaris MAP_NORESERVE mmap() flag\n",
- current->comm);
- cnt++;
- }
- flags &= ~MAP_NORESERVE;
- }
- retval = -EBADF;
- if(!(flags & MAP_ANONYMOUS)) {
- if(fd >= SOLARIS_NR_OPEN)
- goto out;
- file = fget(fd);
- if (!file)
- goto out;
- else {
- struct inode * inode = file->f_path.dentry->d_inode;
- if(imajor(inode) == MEM_MAJOR &&
- iminor(inode) == 5) {
- flags |= MAP_ANONYMOUS;
- fput(file);
- file = NULL;
- }
- }
- }
-
- retval = -EINVAL;
- len = PAGE_ALIGN(len);
- if(!(flags & MAP_FIXED))
- addr = 0;
- else if (len > STACK_TOP32 || addr > STACK_TOP32 - len)
- goto out_putf;
- ret_type = flags & _MAP_NEW;
- flags &= ~_MAP_NEW;
-
- down_write(¤t->mm->mmap_sem);
- flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
- retval = do_mmap(file,
- (unsigned long) addr, (unsigned long) len,
- (unsigned long) prot, (unsigned long) flags, off);
- up_write(¤t->mm->mmap_sem);
- if(!ret_type)
- retval = ((retval < STACK_TOP32) ? 0 : retval);
-
-out_putf:
- if (file)
- fput(file);
-out:
- return (u32) retval;
-}
-
-asmlinkage u32 solaris_mmap(u32 addr, u32 len, u32 prot, u32 flags, u32 fd, u32 off)
-{
- return do_solaris_mmap(addr, len, prot, flags, fd, (u64) off);
-}
-
-asmlinkage u32 solaris_mmap64(struct pt_regs *regs, u32 len, u32 prot, u32 flags, u32 fd, u32 offhi)
-{
- u32 offlo;
-
- if (regs->u_regs[UREG_G1]) {
- if (get_user (offlo, (u32 __user *)(long)((u32)regs->u_regs[UREG_I6] + 0x5c)))
- return -EFAULT;
- } else {
- if (get_user (offlo, (u32 __user *)(long)((u32)regs->u_regs[UREG_I6] + 0x60)))
- return -EFAULT;
- }
- return do_solaris_mmap((u32)regs->u_regs[UREG_I0], len, prot, flags, fd, (((u64)offhi)<<32)|offlo);
-}
-
-asmlinkage int solaris_brk(u32 brk)
-{
- int (*sunos_brk)(u32) = (int (*)(u32))SUNOS(17);
-
- return sunos_brk(brk);
-}
-
-static int __set_utsfield(char __user *to, int to_size,
- const char *from, int from_size,
- int dotchop, int countfrom)
-{
- int len = countfrom ? (to_size > from_size ?
- from_size : to_size) : to_size;
- int off;
-
- if (copy_to_user(to, from, len))
- return -EFAULT;
-
- off = len < to_size? len: len - 1;
- if (dotchop) {
- const char *p = strnchr(from, len, '.');
- if (p) off = p - from;
- }
-
- if (__put_user('\0', to + off))
- return -EFAULT;
-
- return 0;
-}
-
-#define set_utsfield(to, from, dotchop, countfrom) \
- __set_utsfield((to), sizeof(to), \
- (from), sizeof(from), \
- (dotchop), (countfrom))
-
-struct sol_uname {
- char sysname[9];
- char nodename[9];
- char release[9];
- char version[9];
- char machine[9];
-};
-
-struct sol_utsname {
- char sysname[257];
- char nodename[257];
- char release[257];
- char version[257];
- char machine[257];
-};
-
-static char *machine(void)
-{
- switch (sparc_cpu_model) {
- case sun4: return "sun4";
- case sun4c: return "sun4c";
- case sun4e: return "sun4e";
- case sun4m: return "sun4m";
- case sun4d: return "sun4d";
- case sun4u: return "sun4u";
- default: return "sparc";
- }
-}
-
-static char *platform(char *buffer, int sz)
-{
- struct device_node *dp = of_find_node_by_path("/");
- int len;
-
- *buffer = 0;
- len = strlen(dp->name);
- if (len > sz)
- len = sz;
- memcpy(buffer, dp->name, len);
- buffer[len] = 0;
- if (*buffer) {
- char *p;
-
- for (p = buffer; *p; p++)
- if (*p == '/' || *p == ' ') *p = '_';
- return buffer;
- }
-
- return "sun4u";
-}
-
-static char *serial(char *buffer, int sz)
-{
- struct device_node *dp = of_find_node_by_path("/options");
- int len;
-
- *buffer = 0;
- if (dp) {
- const char *val =
- of_get_property(dp, "system-board-serial#", &len);
-
- if (val && len > 0) {
- if (len > sz)
- len = sz;
- memcpy(buffer, val, len);
- buffer[len] = 0;
- }
- }
- if (!*buffer)
- return "4512348717234";
- else
- return buffer;
-}
-
-asmlinkage int solaris_utssys(u32 buf, u32 flags, int which, u32 buf2)
-{
- struct sol_uname __user *v = A(buf);
- int err;
-
- switch (which) {
- case 0: /* old uname */
- /* Let's cheat */
- err = set_utsfield(v->sysname, "SunOS", 1, 0);
- down_read(&uts_sem);
- err |= set_utsfield(v->nodename, utsname()->nodename,
- 1, 1);
- up_read(&uts_sem);
- err |= set_utsfield(v->release, "2.6", 0, 0);
- err |= set_utsfield(v->version, "Generic", 0, 0);
- err |= set_utsfield(v->machine, machine(), 0, 0);
- return (err ? -EFAULT : 0);
- case 2: /* ustat */
- return -ENOSYS;
- case 3: /* fusers */
- return -ENOSYS;
- default:
- return -ENOSYS;
- }
-}
-
-asmlinkage int solaris_utsname(u32 buf)
-{
- struct sol_utsname __user *v = A(buf);
- int err;
-
- /* Why should we not lie a bit? */
- down_read(&uts_sem);
- err = set_utsfield(v->sysname, "SunOS", 0, 0);
- err |= set_utsfield(v->nodename, utsname()->nodename, 1, 1);
- err |= set_utsfield(v->release, "5.6", 0, 0);
- err |= set_utsfield(v->version, "Generic", 0, 0);
- err |= set_utsfield(v->machine, machine(), 0, 0);
- up_read(&uts_sem);
-
- return (err ? -EFAULT : 0);
-}
-
-#define SI_SYSNAME 1 /* return name of operating system */
-#define SI_HOSTNAME 2 /* return name of node */
-#define SI_RELEASE 3 /* return release of operating system */
-#define SI_VERSION 4 /* return version field of utsname */
-#define SI_MACHINE 5 /* return kind of machine */
-#define SI_ARCHITECTURE 6 /* return instruction set arch */
-#define SI_HW_SERIAL 7 /* return hardware serial number */
-#define SI_HW_PROVIDER 8 /* return hardware manufacturer */
-#define SI_SRPC_DOMAIN 9 /* return secure RPC domain */
-#define SI_PLATFORM 513 /* return platform identifier */
-
-asmlinkage int solaris_sysinfo(int cmd, u32 buf, s32 count)
-{
- char *p, *q, *r;
- char buffer[256];
- int len;
-
- /* Again, we cheat :)) */
- switch (cmd) {
- case SI_SYSNAME: r = "SunOS"; break;
- case SI_HOSTNAME:
- r = buffer + 256;
- down_read(&uts_sem);
- for (p = utsname()->nodename, q = buffer;
- q < r && *p && *p != '.'; *q++ = *p++);
- up_read(&uts_sem);
- *q = 0;
- r = buffer;
- break;
- case SI_RELEASE: r = "5.6"; break;
- case SI_MACHINE: r = machine(); break;
- case SI_ARCHITECTURE: r = "sparc"; break;
- case SI_HW_PROVIDER: r = "Sun_Microsystems"; break;
- case SI_HW_SERIAL: r = serial(buffer, sizeof(buffer)); break;
- case SI_PLATFORM: r = platform(buffer, sizeof(buffer)); break;
- case SI_SRPC_DOMAIN: r = ""; break;
- case SI_VERSION: r = "Generic"; break;
- default: return -EINVAL;
- }
- len = strlen(r) + 1;
- if (count < len) {
- if (copy_to_user(A(buf), r, count - 1) ||
- __put_user(0, (char __user *)A(buf) + count - 1))
- return -EFAULT;
- } else {
- if (copy_to_user(A(buf), r, len))
- return -EFAULT;
- }
- return len;
-}
-
-#define SOLARIS_CONFIG_NGROUPS 2
-#define SOLARIS_CONFIG_CHILD_MAX 3
-#define SOLARIS_CONFIG_OPEN_FILES 4
-#define SOLARIS_CONFIG_POSIX_VER 5
-#define SOLARIS_CONFIG_PAGESIZE 6
-#define SOLARIS_CONFIG_CLK_TCK 7
-#define SOLARIS_CONFIG_XOPEN_VER 8
-#define SOLARIS_CONFIG_PROF_TCK 10
-#define SOLARIS_CONFIG_NPROC_CONF 11
-#define SOLARIS_CONFIG_NPROC_ONLN 12
-#define SOLARIS_CONFIG_AIO_LISTIO_MAX 13
-#define SOLARIS_CONFIG_AIO_MAX 14
-#define SOLARIS_CONFIG_AIO_PRIO_DELTA_MAX 15
-#define SOLARIS_CONFIG_DELAYTIMER_MAX 16
-#define SOLARIS_CONFIG_MQ_OPEN_MAX 17
-#define SOLARIS_CONFIG_MQ_PRIO_MAX 18
-#define SOLARIS_CONFIG_RTSIG_MAX 19
-#define SOLARIS_CONFIG_SEM_NSEMS_MAX 20
-#define SOLARIS_CONFIG_SEM_VALUE_MAX 21
-#define SOLARIS_CONFIG_SIGQUEUE_MAX 22
-#define SOLARIS_CONFIG_SIGRT_MIN 23
-#define SOLARIS_CONFIG_SIGRT_MAX 24
-#define SOLARIS_CONFIG_TIMER_MAX 25
-#define SOLARIS_CONFIG_PHYS_PAGES 26
-#define SOLARIS_CONFIG_AVPHYS_PAGES 27
-
-asmlinkage int solaris_sysconf(int id)
-{
- switch (id) {
- case SOLARIS_CONFIG_NGROUPS: return NGROUPS_MAX;
- case SOLARIS_CONFIG_CHILD_MAX:
- return current->signal->rlim[RLIMIT_NPROC].rlim_cur;
- case SOLARIS_CONFIG_OPEN_FILES:
- return current->signal->rlim[RLIMIT_NOFILE].rlim_cur;
- case SOLARIS_CONFIG_POSIX_VER: return 199309;
- case SOLARIS_CONFIG_PAGESIZE: return PAGE_SIZE;
- case SOLARIS_CONFIG_XOPEN_VER: return 3;
- case SOLARIS_CONFIG_CLK_TCK:
- case SOLARIS_CONFIG_PROF_TCK:
- return sparc64_get_clock_tick(smp_processor_id());
-#ifdef CONFIG_SMP
- case SOLARIS_CONFIG_NPROC_CONF: return NR_CPUS;
- case SOLARIS_CONFIG_NPROC_ONLN: return num_online_cpus();
-#else
- case SOLARIS_CONFIG_NPROC_CONF: return 1;
- case SOLARIS_CONFIG_NPROC_ONLN: return 1;
-#endif
- case SOLARIS_CONFIG_SIGRT_MIN: return 37;
- case SOLARIS_CONFIG_SIGRT_MAX: return 44;
- case SOLARIS_CONFIG_PHYS_PAGES:
- case SOLARIS_CONFIG_AVPHYS_PAGES:
- {
- struct sysinfo s;
-
- si_meminfo(&s);
- if (id == SOLARIS_CONFIG_PHYS_PAGES)
- return s.totalram >>= PAGE_SHIFT;
- else
- return s.freeram >>= PAGE_SHIFT;
- }
- /* XXX support these as well -jj */
- case SOLARIS_CONFIG_AIO_LISTIO_MAX: return -EINVAL;
- case SOLARIS_CONFIG_AIO_MAX: return -EINVAL;
- case SOLARIS_CONFIG_AIO_PRIO_DELTA_MAX: return -EINVAL;
- case SOLARIS_CONFIG_DELAYTIMER_MAX: return -EINVAL;
- case SOLARIS_CONFIG_MQ_OPEN_MAX: return -EINVAL;
- case SOLARIS_CONFIG_MQ_PRIO_MAX: return -EINVAL;
- case SOLARIS_CONFIG_RTSIG_MAX: return -EINVAL;
- case SOLARIS_CONFIG_SEM_NSEMS_MAX: return -EINVAL;
- case SOLARIS_CONFIG_SEM_VALUE_MAX: return -EINVAL;
- case SOLARIS_CONFIG_SIGQUEUE_MAX: return -EINVAL;
- case SOLARIS_CONFIG_TIMER_MAX: return -EINVAL;
- default: return -EINVAL;
- }
-}
-
-asmlinkage int solaris_procids(int cmd, s32 pid, s32 pgid)
-{
- int ret;
-
- switch (cmd) {
- case 0: /* getpgrp */
- return task_pgrp_vnr(current);
- case 1: /* setpgrp */
- {
- int (*sys_setpgid)(pid_t,pid_t) =
- (int (*)(pid_t,pid_t))SYS(setpgid);
-
- /* can anyone explain me the difference between
- Solaris setpgrp and setsid? */
- ret = sys_setpgid(0, 0);
- if (ret) return ret;
- proc_clear_tty(current);
- return task_pgrp_vnr(current);
- }
- case 2: /* getsid */
- {
- int (*sys_getsid)(pid_t) = (int (*)(pid_t))SYS(getsid);
- return sys_getsid(pid);
- }
- case 3: /* setsid */
- {
- int (*sys_setsid)(void) = (int (*)(void))SYS(setsid);
- return sys_setsid();
- }
- case 4: /* getpgid */
- {
- int (*sys_getpgid)(pid_t) = (int (*)(pid_t))SYS(getpgid);
- return sys_getpgid(pid);
- }
- case 5: /* setpgid */
- {
- int (*sys_setpgid)(pid_t,pid_t) =
- (int (*)(pid_t,pid_t))SYS(setpgid);
- return sys_setpgid(pid,pgid);
- }
- }
- return -EINVAL;
-}
-
-asmlinkage int solaris_gettimeofday(u32 tim)
-{
- int (*sys_gettimeofday)(struct timeval *, struct timezone *) =
- (int (*)(struct timeval *, struct timezone *))SYS(gettimeofday);
-
- return sys_gettimeofday((struct timeval *)(u64)tim, NULL);
-}
-
-#define RLIM_SOL_INFINITY32 0x7fffffff
-#define RLIM_SOL_SAVED_MAX32 0x7ffffffe
-#define RLIM_SOL_SAVED_CUR32 0x7ffffffd
-#define RLIM_SOL_INFINITY ((u64)-3)
-#define RLIM_SOL_SAVED_MAX ((u64)-2)
-#define RLIM_SOL_SAVED_CUR ((u64)-1)
-#define RESOURCE32(x) ((x > RLIM_INFINITY32) ? RLIM_INFINITY32 : x)
-#define RLIMIT_SOL_NOFILE 5
-#define RLIMIT_SOL_VMEM 6
-
-struct rlimit32 {
- u32 rlim_cur;
- u32 rlim_max;
-};
-
-asmlinkage int solaris_getrlimit(unsigned int resource, struct rlimit32 __user *rlim)
-{
- struct rlimit r;
- int ret;
- mm_segment_t old_fs = get_fs ();
- int (*sys_getrlimit)(unsigned int, struct rlimit *) =
- (int (*)(unsigned int, struct rlimit *))SYS(getrlimit);
-
- if (resource > RLIMIT_SOL_VMEM)
- return -EINVAL;
- switch (resource) {
- case RLIMIT_SOL_NOFILE: resource = RLIMIT_NOFILE; break;
- case RLIMIT_SOL_VMEM: resource = RLIMIT_AS; break;
- default: break;
- }
- set_fs (KERNEL_DS);
- ret = sys_getrlimit(resource, &r);
- set_fs (old_fs);
- if (!ret) {
- if (r.rlim_cur == RLIM_INFINITY)
- r.rlim_cur = RLIM_SOL_INFINITY32;
- else if ((u64)r.rlim_cur > RLIM_SOL_INFINITY32)
- r.rlim_cur = RLIM_SOL_SAVED_CUR32;
- if (r.rlim_max == RLIM_INFINITY)
- r.rlim_max = RLIM_SOL_INFINITY32;
- else if ((u64)r.rlim_max > RLIM_SOL_INFINITY32)
- r.rlim_max = RLIM_SOL_SAVED_MAX32;
- ret = put_user (r.rlim_cur, &rlim->rlim_cur);
- ret |= __put_user (r.rlim_max, &rlim->rlim_max);
- }
- return ret;
-}
-
-asmlinkage int solaris_setrlimit(unsigned int resource, struct rlimit32 __user *rlim)
-{
- struct rlimit r, rold;
- int ret;
- mm_segment_t old_fs = get_fs ();
- int (*sys_getrlimit)(unsigned int, struct rlimit __user *) =
- (int (*)(unsigned int, struct rlimit __user *))SYS(getrlimit);
- int (*sys_setrlimit)(unsigned int, struct rlimit __user *) =
- (int (*)(unsigned int, struct rlimit __user *))SYS(setrlimit);
-
- if (resource > RLIMIT_SOL_VMEM)
- return -EINVAL;
- switch (resource) {
- case RLIMIT_SOL_NOFILE: resource = RLIMIT_NOFILE; break;
- case RLIMIT_SOL_VMEM: resource = RLIMIT_AS; break;
- default: break;
- }
- if (get_user (r.rlim_cur, &rlim->rlim_cur) ||
- __get_user (r.rlim_max, &rlim->rlim_max))
- return -EFAULT;
- set_fs (KERNEL_DS);
- ret = sys_getrlimit(resource, &rold);
- if (!ret) {
- if (r.rlim_cur == RLIM_SOL_INFINITY32)
- r.rlim_cur = RLIM_INFINITY;
- else if (r.rlim_cur == RLIM_SOL_SAVED_CUR32)
- r.rlim_cur = rold.rlim_cur;
- else if (r.rlim_cur == RLIM_SOL_SAVED_MAX32)
- r.rlim_cur = rold.rlim_max;
- if (r.rlim_max == RLIM_SOL_INFINITY32)
- r.rlim_max = RLIM_INFINITY;
- else if (r.rlim_max == RLIM_SOL_SAVED_CUR32)
- r.rlim_max = rold.rlim_cur;
- else if (r.rlim_max == RLIM_SOL_SAVED_MAX32)
- r.rlim_max = rold.rlim_max;
- ret = sys_setrlimit(resource, &r);
- }
- set_fs (old_fs);
- return ret;
-}
-
-asmlinkage int solaris_getrlimit64(unsigned int resource, struct rlimit __user *rlim)
-{
- struct rlimit r;
- int ret;
- mm_segment_t old_fs = get_fs ();
- int (*sys_getrlimit)(unsigned int, struct rlimit __user *) =
- (int (*)(unsigned int, struct rlimit __user *))SYS(getrlimit);
-
- if (resource > RLIMIT_SOL_VMEM)
- return -EINVAL;
- switch (resource) {
- case RLIMIT_SOL_NOFILE: resource = RLIMIT_NOFILE; break;
- case RLIMIT_SOL_VMEM: resource = RLIMIT_AS; break;
- default: break;
- }
- set_fs (KERNEL_DS);
- ret = sys_getrlimit(resource, &r);
- set_fs (old_fs);
- if (!ret) {
- if (r.rlim_cur == RLIM_INFINITY)
- r.rlim_cur = RLIM_SOL_INFINITY;
- if (r.rlim_max == RLIM_INFINITY)
- r.rlim_max = RLIM_SOL_INFINITY;
- ret = put_user (r.rlim_cur, &rlim->rlim_cur);
- ret |= __put_user (r.rlim_max, &rlim->rlim_max);
- }
- return ret;
-}
-
-asmlinkage int solaris_setrlimit64(unsigned int resource, struct rlimit __user *rlim)
-{
- struct rlimit r, rold;
- int ret;
- mm_segment_t old_fs = get_fs ();
- int (*sys_getrlimit)(unsigned int, struct rlimit __user *) =
- (int (*)(unsigned int, struct rlimit __user *))SYS(getrlimit);
- int (*sys_setrlimit)(unsigned int, struct rlimit __user *) =
- (int (*)(unsigned int, struct rlimit __user *))SYS(setrlimit);
-
- if (resource > RLIMIT_SOL_VMEM)
- return -EINVAL;
- switch (resource) {
- case RLIMIT_SOL_NOFILE: resource = RLIMIT_NOFILE; break;
- case RLIMIT_SOL_VMEM: resource = RLIMIT_AS; break;
- default: break;
- }
- if (get_user (r.rlim_cur, &rlim->rlim_cur) ||
- __get_user (r.rlim_max, &rlim->rlim_max))
- return -EFAULT;
- set_fs (KERNEL_DS);
- ret = sys_getrlimit(resource, &rold);
- if (!ret) {
- if (r.rlim_cur == RLIM_SOL_INFINITY)
- r.rlim_cur = RLIM_INFINITY;
- else if (r.rlim_cur == RLIM_SOL_SAVED_CUR)
- r.rlim_cur = rold.rlim_cur;
- else if (r.rlim_cur == RLIM_SOL_SAVED_MAX)
- r.rlim_cur = rold.rlim_max;
- if (r.rlim_max == RLIM_SOL_INFINITY)
- r.rlim_max = RLIM_INFINITY;
- else if (r.rlim_max == RLIM_SOL_SAVED_CUR)
- r.rlim_max = rold.rlim_cur;
- else if (r.rlim_max == RLIM_SOL_SAVED_MAX)
- r.rlim_max = rold.rlim_max;
- ret = sys_setrlimit(resource, &r);
- }
- set_fs (old_fs);
- return ret;
-}
-
-struct sol_ntptimeval {
- struct compat_timeval time;
- s32 maxerror;
- s32 esterror;
-};
-
-struct sol_timex {
- u32 modes;
- s32 offset;
- s32 freq;
- s32 maxerror;
- s32 esterror;
- s32 status;
- s32 constant;
- s32 precision;
- s32 tolerance;
- s32 ppsfreq;
- s32 jitter;
- s32 shift;
- s32 stabil;
- s32 jitcnt;
- s32 calcnt;
- s32 errcnt;
- s32 stbcnt;
-};
-
-asmlinkage int solaris_ntp_gettime(struct sol_ntptimeval __user *ntp)
-{
- int (*sys_adjtimex)(struct timex __user *) =
- (int (*)(struct timex __user *))SYS(adjtimex);
- struct timex t;
- int ret;
- mm_segment_t old_fs = get_fs();
-
- set_fs(KERNEL_DS);
- t.modes = 0;
- ret = sys_adjtimex(&t);
- set_fs(old_fs);
- if (ret < 0)
- return ret;
- ret = put_user (t.time.tv_sec, &ntp->time.tv_sec);
- ret |= __put_user (t.time.tv_usec, &ntp->time.tv_usec);
- ret |= __put_user (t.maxerror, &ntp->maxerror);
- ret |= __put_user (t.esterror, &ntp->esterror);
- return ret;
-}
-
-asmlinkage int solaris_ntp_adjtime(struct sol_timex __user *txp)
-{
- int (*sys_adjtimex)(struct timex __user *) =
- (int (*)(struct timex __user *))SYS(adjtimex);
- struct timex t;
- int ret, err;
- mm_segment_t old_fs = get_fs();
-
- ret = get_user (t.modes, &txp->modes);
- ret |= __get_user (t.offset, &txp->offset);
- ret |= __get_user (t.freq, &txp->freq);
- ret |= __get_user (t.maxerror, &txp->maxerror);
- ret |= __get_user (t.esterror, &txp->esterror);
- ret |= __get_user (t.status, &txp->status);
- ret |= __get_user (t.constant, &txp->constant);
- set_fs(KERNEL_DS);
- ret = sys_adjtimex(&t);
- set_fs(old_fs);
- if (ret < 0)
- return ret;
- err = put_user (t.offset, &txp->offset);
- err |= __put_user (t.freq, &txp->freq);
- err |= __put_user (t.maxerror, &txp->maxerror);
- err |= __put_user (t.esterror, &txp->esterror);
- err |= __put_user (t.status, &txp->status);
- err |= __put_user (t.constant, &txp->constant);
- err |= __put_user (t.precision, &txp->precision);
- err |= __put_user (t.tolerance, &txp->tolerance);
- err |= __put_user (t.ppsfreq, &txp->ppsfreq);
- err |= __put_user (t.jitter, &txp->jitter);
- err |= __put_user (t.shift, &txp->shift);
- err |= __put_user (t.stabil, &txp->stabil);
- err |= __put_user (t.jitcnt, &txp->jitcnt);
- err |= __put_user (t.calcnt, &txp->calcnt);
- err |= __put_user (t.errcnt, &txp->errcnt);
- err |= __put_user (t.stbcnt, &txp->stbcnt);
- if (err)
- return -EFAULT;
- return ret;
-}
-
-asmlinkage int do_sol_unimplemented(struct pt_regs *regs)
-{
- printk ("Unimplemented Solaris syscall %d %08x %08x %08x %08x\n",
- (int)regs->u_regs[UREG_G1],
- (int)regs->u_regs[UREG_I0],
- (int)regs->u_regs[UREG_I1],
- (int)regs->u_regs[UREG_I2],
- (int)regs->u_regs[UREG_I3]);
- return -ENOSYS;
-}
-
-asmlinkage void solaris_register(void)
-{
- set_personality(PER_SVR4);
-}
-
-extern long solaris_to_linux_signals[], linux_to_solaris_signals[];
-
-struct exec_domain solaris_exec_domain = {
- .name = "Solaris",
- .handler = NULL,
- .pers_low = 1, /* PER_SVR4 personality */
- .pers_high = 1,
- .signal_map = solaris_to_linux_signals,
- .signal_invmap =linux_to_solaris_signals,
- .module = THIS_MODULE,
- .next = NULL
-};
-
-extern int init_socksys(void);
-
-MODULE_AUTHOR("Jakub Jelinek (jj@ultra.linux.cz), Patrik Rak (prak3264@ss1000.ms.mff.cuni.cz)");
-MODULE_DESCRIPTION("Solaris binary emulation module");
-MODULE_LICENSE("GPL");
-
-extern u32 tl0_solaris[8];
-#define update_ttable(x) \
- tl0_solaris[3] = (((long)(x) - (long)tl0_solaris - 3) >> 2) | 0x40000000; \
- wmb(); \
- __asm__ __volatile__ ("flush %0" : : "r" (&tl0_solaris[3]))
-
-extern u32 solaris_sparc_syscall[];
-extern u32 solaris_syscall[];
-extern void cleanup_socksys(void);
-
-extern u32 entry64_personality_patch;
-
-static int __init solaris_init(void)
-{
- int ret;
-
- SOLDD(("Solaris module at %p\n", solaris_sparc_syscall));
- register_exec_domain(&solaris_exec_domain);
- if ((ret = init_socksys())) {
- unregister_exec_domain(&solaris_exec_domain);
- return ret;
- }
- update_ttable(solaris_sparc_syscall);
- entry64_personality_patch |=
- (offsetof(struct task_struct, personality) +
- (sizeof(unsigned long) - 1));
- wmb();
- __asm__ __volatile__("flush %0"
- : : "r" (&entry64_personality_patch));
- return 0;
-}
-
-static void __exit solaris_exit(void)
-{
- update_ttable(solaris_syscall);
- cleanup_socksys();
- unregister_exec_domain(&solaris_exec_domain);
-}
-
-module_init(solaris_init);
-module_exit(solaris_exit);
+++ /dev/null
-/* $Id: signal.c,v 1.7 2000/09/05 21:44:54 davem Exp $
- * signal.c: Signal emulation for Solaris
- *
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-#include <linux/types.h>
-#include <linux/errno.h>
-
-#include <asm/uaccess.h>
-#include <asm/svr4.h>
-#include <asm/string.h>
-
-#include "conv.h"
-#include "signal.h"
-
-#define _S(nr) (1L<<((nr)-1))
-
-#define _BLOCKABLE (~(_S(SIGKILL) | _S(SIGSTOP)))
-
-long linux_to_solaris_signals[] = {
- 0,
- SOLARIS_SIGHUP, SOLARIS_SIGINT,
- SOLARIS_SIGQUIT, SOLARIS_SIGILL,
- SOLARIS_SIGTRAP, SOLARIS_SIGIOT,
- SOLARIS_SIGEMT, SOLARIS_SIGFPE,
- SOLARIS_SIGKILL, SOLARIS_SIGBUS,
- SOLARIS_SIGSEGV, SOLARIS_SIGSYS,
- SOLARIS_SIGPIPE, SOLARIS_SIGALRM,
- SOLARIS_SIGTERM, SOLARIS_SIGURG,
- SOLARIS_SIGSTOP, SOLARIS_SIGTSTP,
- SOLARIS_SIGCONT, SOLARIS_SIGCLD,
- SOLARIS_SIGTTIN, SOLARIS_SIGTTOU,
- SOLARIS_SIGPOLL, SOLARIS_SIGXCPU,
- SOLARIS_SIGXFSZ, SOLARIS_SIGVTALRM,
- SOLARIS_SIGPROF, SOLARIS_SIGWINCH,
- SOLARIS_SIGUSR1, SOLARIS_SIGUSR1,
- SOLARIS_SIGUSR2, -1,
-};
-
-long solaris_to_linux_signals[] = {
- 0,
- SIGHUP, SIGINT, SIGQUIT, SIGILL,
- SIGTRAP, SIGIOT, SIGEMT, SIGFPE,
- SIGKILL, SIGBUS, SIGSEGV, SIGSYS,
- SIGPIPE, SIGALRM, SIGTERM, SIGUSR1,
- SIGUSR2, SIGCHLD, -1, SIGWINCH,
- SIGURG, SIGPOLL, SIGSTOP, SIGTSTP,
- SIGCONT, SIGTTIN, SIGTTOU, SIGVTALRM,
- SIGPROF, SIGXCPU, SIGXFSZ, -1,
- -1, -1, -1, -1,
- -1, -1, -1, -1,
- -1, -1, -1, -1,
-};
-
-static inline long mapsig(long sig)
-{
- if ((unsigned long)sig > SOLARIS_NSIGNALS)
- return -EINVAL;
- return solaris_to_linux_signals[sig];
-}
-
-asmlinkage int solaris_kill(int pid, int sig)
-{
- int (*sys_kill)(int,int) =
- (int (*)(int,int))SYS(kill);
- int s = mapsig(sig);
-
- if (s < 0) return s;
- return sys_kill(pid, s);
-}
-
-static long sig_handler(int sig, u32 arg, int one_shot)
-{
- struct sigaction sa, old;
- int ret;
- mm_segment_t old_fs = get_fs();
- int (*sys_sigaction)(int,struct sigaction __user *,struct sigaction __user *) =
- (int (*)(int,struct sigaction __user *,struct sigaction __user *))SYS(sigaction);
-
- sigemptyset(&sa.sa_mask);
- sa.sa_restorer = NULL;
- sa.sa_handler = (__sighandler_t)A(arg);
- sa.sa_flags = 0;
- if (one_shot) sa.sa_flags = SA_ONESHOT | SA_NOMASK;
- set_fs (KERNEL_DS);
- ret = sys_sigaction(sig, (void __user *)&sa, (void __user *)&old);
- set_fs (old_fs);
- if (ret < 0) return ret;
- return (u32)(unsigned long)old.sa_handler;
-}
-
-static inline long solaris_signal(int sig, u32 arg)
-{
- return sig_handler (sig, arg, 1);
-}
-
-static long solaris_sigset(int sig, u32 arg)
-{
- if (arg != 2) /* HOLD */ {
- spin_lock_irq(¤t->sighand->siglock);
- sigdelsetmask(¤t->blocked, _S(sig));
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- return sig_handler (sig, arg, 0);
- } else {
- spin_lock_irq(¤t->sighand->siglock);
- sigaddsetmask(¤t->blocked, (_S(sig) & ~_BLOCKABLE));
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- return 0;
- }
-}
-
-static inline long solaris_sighold(int sig)
-{
- return solaris_sigset(sig, 2);
-}
-
-static inline long solaris_sigrelse(int sig)
-{
- spin_lock_irq(¤t->sighand->siglock);
- sigdelsetmask(¤t->blocked, _S(sig));
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- return 0;
-}
-
-static inline long solaris_sigignore(int sig)
-{
- return sig_handler(sig, (u32)(unsigned long)SIG_IGN, 0);
-}
-
-static inline long solaris_sigpause(int sig)
-{
- printk ("Need to support solaris sigpause\n");
- return -ENOSYS;
-}
-
-asmlinkage long solaris_sigfunc(int sig, u32 arg)
-{
- int func = sig & ~0xff;
-
- sig = mapsig(sig & 0xff);
- if (sig < 0) return sig;
- switch (func) {
- case 0: return solaris_signal(sig, arg);
- case 0x100: return solaris_sigset(sig, arg);
- case 0x200: return solaris_sighold(sig);
- case 0x400: return solaris_sigrelse(sig);
- case 0x800: return solaris_sigignore(sig);
- case 0x1000: return solaris_sigpause(sig);
- }
- return -EINVAL;
-}
-
-typedef struct {
- u32 __sigbits[4];
-} sol_sigset_t;
-
-static inline int mapin(u32 *p, sigset_t *q)
-{
- int i;
- u32 x;
- int sig;
-
- sigemptyset(q);
- x = p[0];
- for (i = 1; i <= SOLARIS_NSIGNALS; i++) {
- if (x & 1) {
- sig = solaris_to_linux_signals[i];
- if (sig == -1)
- return -EINVAL;
- sigaddsetmask(q, (1L << (sig - 1)));
- }
- x >>= 1;
- if (i == 32)
- x = p[1];
- }
- return 0;
-}
-
-static inline int mapout(sigset_t *q, u32 *p)
-{
- int i;
- int sig;
-
- p[0] = 0;
- p[1] = 0;
- for (i = 1; i <= 32; i++) {
- if (sigismember(q, sigmask(i))) {
- sig = linux_to_solaris_signals[i];
- if (sig == -1)
- return -EINVAL;
- if (sig > 32)
- p[1] |= 1L << (sig - 33);
- else
- p[0] |= 1L << (sig - 1);
- }
- }
- return 0;
-}
-
-asmlinkage int solaris_sigprocmask(int how, u32 in, u32 out)
-{
- sigset_t in_s, *ins, out_s, *outs;
- mm_segment_t old_fs = get_fs();
- int ret;
- int (*sys_sigprocmask)(int,sigset_t __user *,sigset_t __user *) =
- (int (*)(int,sigset_t __user *,sigset_t __user *))SYS(sigprocmask);
-
- ins = NULL; outs = NULL;
- if (in) {
- u32 tmp[2];
-
- if (copy_from_user (tmp, (void __user *)A(in), 2*sizeof(u32)))
- return -EFAULT;
- ins = &in_s;
- if (mapin (tmp, ins)) return -EINVAL;
- }
- if (out) outs = &out_s;
- set_fs (KERNEL_DS);
- ret = sys_sigprocmask((how == 3) ? SIG_SETMASK : how,
- (void __user *)ins, (void __user *)outs);
- set_fs (old_fs);
- if (ret) return ret;
- if (out) {
- u32 tmp[4];
-
- tmp[2] = 0; tmp[3] = 0;
- if (mapout (outs, tmp)) return -EINVAL;
- if (copy_to_user((void __user *)A(out), tmp, 4*sizeof(u32)))
- return -EFAULT;
- }
- return 0;
-}
-
-asmlinkage long do_sol_sigsuspend(u32 mask)
-{
- sigset_t s;
- u32 tmp[2];
-
- if (copy_from_user (tmp, (sol_sigset_t __user *)A(mask), 2*sizeof(u32)))
- return -EFAULT;
- if (mapin (tmp, &s)) return -EINVAL;
- return (long)s.sig[0];
-}
-
-struct sol_sigaction {
- int sa_flags;
- u32 sa_handler;
- u32 sa_mask[4];
- int sa_resv[2];
-};
-
-asmlinkage int solaris_sigaction(int sig, u32 act, u32 old)
-{
- u32 tmp, tmp2[4];
- struct sigaction s, s2;
- int ret;
- mm_segment_t old_fs = get_fs();
- struct sol_sigaction __user *p = (void __user *)A(old);
- int (*sys_sigaction)(int,struct sigaction __user *,struct sigaction __user *) =
- (int (*)(int,struct sigaction __user *,struct sigaction __user *))SYS(sigaction);
-
- sig = mapsig(sig);
- if (sig < 0) {
- /* We cheat a little bit for Solaris only signals */
- if (old && clear_user(p, sizeof(struct sol_sigaction)))
- return -EFAULT;
- return 0;
- }
- if (act) {
- if (get_user (tmp, &p->sa_flags))
- return -EFAULT;
- s.sa_flags = 0;
- if (tmp & SOLARIS_SA_ONSTACK) s.sa_flags |= SA_STACK;
- if (tmp & SOLARIS_SA_RESTART) s.sa_flags |= SA_RESTART;
- if (tmp & SOLARIS_SA_NODEFER) s.sa_flags |= SA_NOMASK;
- if (tmp & SOLARIS_SA_RESETHAND) s.sa_flags |= SA_ONESHOT;
- if (tmp & SOLARIS_SA_NOCLDSTOP) s.sa_flags |= SA_NOCLDSTOP;
- if (get_user (tmp, &p->sa_handler) ||
- copy_from_user (tmp2, &p->sa_mask, 2*sizeof(u32)))
- return -EFAULT;
- s.sa_handler = (__sighandler_t)A(tmp);
- if (mapin (tmp2, &s.sa_mask)) return -EINVAL;
- s.sa_restorer = NULL;
- }
- set_fs(KERNEL_DS);
- ret = sys_sigaction(sig, act ? (void __user *)&s : NULL,
- old ? (void __user *)&s2 : NULL);
- set_fs(old_fs);
- if (ret) return ret;
- if (old) {
- if (mapout (&s2.sa_mask, tmp2)) return -EINVAL;
- tmp = 0; tmp2[2] = 0; tmp2[3] = 0;
- if (s2.sa_flags & SA_STACK) tmp |= SOLARIS_SA_ONSTACK;
- if (s2.sa_flags & SA_RESTART) tmp |= SOLARIS_SA_RESTART;
- if (s2.sa_flags & SA_NOMASK) tmp |= SOLARIS_SA_NODEFER;
- if (s2.sa_flags & SA_ONESHOT) tmp |= SOLARIS_SA_RESETHAND;
- if (s2.sa_flags & SA_NOCLDSTOP) tmp |= SOLARIS_SA_NOCLDSTOP;
- if (put_user (tmp, &p->sa_flags) ||
- __put_user ((u32)(unsigned long)s2.sa_handler, &p->sa_handler) ||
- copy_to_user (&p->sa_mask, tmp2, 4*sizeof(u32)))
- return -EFAULT;
- }
- return 0;
-}
-
-asmlinkage int solaris_sigpending(int which, u32 set)
-{
- sigset_t s;
- u32 tmp[4];
- switch (which) {
- case 1: /* sigpending */
- spin_lock_irq(¤t->sighand->siglock);
- sigandsets(&s, ¤t->blocked, ¤t->pending.signal);
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
- break;
- case 2: /* sigfillset - I just set signals which have linux equivalents */
- sigfillset(&s);
- break;
- default: return -EINVAL;
- }
- if (mapout (&s, tmp)) return -EINVAL;
- tmp[2] = 0; tmp[3] = 0;
- if (copy_to_user ((u32 __user *)A(set), tmp, sizeof(tmp)))
- return -EFAULT;
- return 0;
-}
-
-asmlinkage int solaris_wait(u32 stat_loc)
-{
- unsigned __user *p = (unsigned __user *)A(stat_loc);
- int (*sys_wait4)(pid_t,unsigned __user *, int, struct rusage __user *) =
- (int (*)(pid_t,unsigned __user *, int, struct rusage __user *))SYS(wait4);
- int ret, status;
-
- ret = sys_wait4(-1, p, WUNTRACED, NULL);
- if (ret >= 0 && stat_loc) {
- if (get_user (status, p))
- return -EFAULT;
- if (((status - 1) & 0xffff) < 0xff)
- status = linux_to_solaris_signals[status & 0x7f] & 0x7f;
- else if ((status & 0xff) == 0x7f)
- status = (linux_to_solaris_signals[(status >> 8) & 0xff] << 8) | 0x7f;
- if (__put_user (status, p))
- return -EFAULT;
- }
- return ret;
-}
-
-asmlinkage int solaris_waitid(int idtype, s32 pid, u32 info, int options)
-{
- int (*sys_wait4)(pid_t,unsigned __user *, int, struct rusage __user *) =
- (int (*)(pid_t,unsigned __user *, int, struct rusage __user *))SYS(wait4);
- int opts, status, ret;
-
- switch (idtype) {
- case 0: /* P_PID */ break;
- case 1: /* P_PGID */ pid = -pid; break;
- case 7: /* P_ALL */ pid = -1; break;
- default: return -EINVAL;
- }
- opts = 0;
- if (options & SOLARIS_WUNTRACED) opts |= WUNTRACED;
- if (options & SOLARIS_WNOHANG) opts |= WNOHANG;
- current->state = TASK_RUNNING;
- ret = sys_wait4(pid, (unsigned int __user *)A(info), opts, NULL);
- if (ret < 0) return ret;
- if (info) {
- struct sol_siginfo __user *s = (void __user *)A(info);
-
- if (get_user (status, (unsigned int __user *)A(info)))
- return -EFAULT;
-
- if (__put_user (SOLARIS_SIGCLD, &s->si_signo) ||
- __put_user (ret, &s->_data._proc._pid))
- return -EFAULT;
-
- switch (status & 0xff) {
- case 0: ret = SOLARIS_CLD_EXITED;
- status = (status >> 8) & 0xff;
- break;
- case 0x7f:
- status = (status >> 8) & 0xff;
- switch (status) {
- case SIGSTOP:
- case SIGTSTP: ret = SOLARIS_CLD_STOPPED;
- default: ret = SOLARIS_CLD_EXITED;
- }
- status = linux_to_solaris_signals[status];
- break;
- default:
- if (status & 0x80) ret = SOLARIS_CLD_DUMPED;
- else ret = SOLARIS_CLD_KILLED;
- status = linux_to_solaris_signals[status & 0x7f];
- break;
- }
-
- if (__put_user (ret, &s->si_code) ||
- __put_user (status, &s->_data._proc._pdata._cld._status))
- return -EFAULT;
- }
- return 0;
-}
-
-extern int svr4_setcontext(svr4_ucontext_t *c, struct pt_regs *regs);
-extern int svr4_getcontext(svr4_ucontext_t *c, struct pt_regs *regs);
-
-asmlinkage int solaris_context(struct pt_regs *regs)
-{
- switch ((unsigned)regs->u_regs[UREG_I0]) {
- case 0: /* getcontext */
- return svr4_getcontext((svr4_ucontext_t *)(long)(u32)regs->u_regs[UREG_I1], regs);
- case 1: /* setcontext */
- return svr4_setcontext((svr4_ucontext_t *)(long)(u32)regs->u_regs[UREG_I1], regs);
- default:
- return -EINVAL;
-
- }
-}
-
-asmlinkage int solaris_sigaltstack(u32 ss, u32 oss)
-{
-/* XXX Implement this soon */
- return 0;
-}
+++ /dev/null
-/* $Id: signal.h,v 1.3 1998/04/12 06:20:33 davem Exp $
- * signal.h: Signal emulation for Solaris
- *
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-
-#define SOLARIS_SIGHUP 1
-#define SOLARIS_SIGINT 2
-#define SOLARIS_SIGQUIT 3
-#define SOLARIS_SIGILL 4
-#define SOLARIS_SIGTRAP 5
-#define SOLARIS_SIGIOT 6
-#define SOLARIS_SIGEMT 7
-#define SOLARIS_SIGFPE 8
-#define SOLARIS_SIGKILL 9
-#define SOLARIS_SIGBUS 10
-#define SOLARIS_SIGSEGV 11
-#define SOLARIS_SIGSYS 12
-#define SOLARIS_SIGPIPE 13
-#define SOLARIS_SIGALRM 14
-#define SOLARIS_SIGTERM 15
-#define SOLARIS_SIGUSR1 16
-#define SOLARIS_SIGUSR2 17
-#define SOLARIS_SIGCLD 18
-#define SOLARIS_SIGPWR 19
-#define SOLARIS_SIGWINCH 20
-#define SOLARIS_SIGURG 21
-#define SOLARIS_SIGPOLL 22
-#define SOLARIS_SIGSTOP 23
-#define SOLARIS_SIGTSTP 24
-#define SOLARIS_SIGCONT 25
-#define SOLARIS_SIGTTIN 26
-#define SOLARIS_SIGTTOU 27
-#define SOLARIS_SIGVTALRM 28
-#define SOLARIS_SIGPROF 29
-#define SOLARIS_SIGXCPU 30
-#define SOLARIS_SIGXFSZ 31
-#define SOLARIS_SIGWAITING 32
-#define SOLARIS_SIGLWP 33
-#define SOLARIS_SIGFREEZE 34
-#define SOLARIS_SIGTHAW 35
-#define SOLARIS_SIGCANCEL 36
-#define SOLARIS_SIGRTMIN 37
-#define SOLARIS_SIGRTMAX 44
-#define SOLARIS_NSIGNALS 44
-
-
-#define SOLARIS_SA_ONSTACK 1
-#define SOLARIS_SA_RESETHAND 2
-#define SOLARIS_SA_RESTART 4
-#define SOLARIS_SA_SIGINFO 8
-#define SOLARIS_SA_NODEFER 16
-#define SOLARIS_SA_NOCLDWAIT 0x10000
-#define SOLARIS_SA_NOCLDSTOP 0x20000
-
-struct sol_siginfo {
- int si_signo;
- int si_code;
- int si_errno;
- union {
- char pad[128-3*sizeof(int)];
- struct {
- s32 _pid;
- union {
- struct {
- s32 _uid;
- s32 _value;
- } _kill;
- struct {
- s32 _utime;
- int _status;
- s32 _stime;
- } _cld;
- } _pdata;
- } _proc;
- struct { /* SIGSEGV, SIGBUS, SIGILL and SIGFPE */
- u32 _addr;
- int _trapno;
- } _fault;
- struct { /* SIGPOLL, SIGXFSZ */
- int _fd;
- s32 _band;
- } _file;
- } _data;
-};
-
-#define SOLARIS_WUNTRACED 0x04
-#define SOLARIS_WNOHANG 0x40
-#define SOLARIS_WEXITED 0x01
-#define SOLARIS_WTRAPPED 0x02
-#define SOLARIS_WSTOPPED WUNTRACED
-#define SOLARIS_WCONTINUED 0x08
-#define SOLARIS_WNOWAIT 0x80
-
-#define SOLARIS_TRAP_BRKPT 1
-#define SOLARIS_TRAP_TRACE 2
-#define SOLARIS_CLD_EXITED 1
-#define SOLARIS_CLD_KILLED 2
-#define SOLARIS_CLD_DUMPED 3
-#define SOLARIS_CLD_TRAPPED 4
-#define SOLARIS_CLD_STOPPED 5
-#define SOLARIS_CLD_CONTINUED 6
-#define SOLARIS_POLL_IN 1
-#define SOLARIS_POLL_OUT 2
-#define SOLARIS_POLL_MSG 3
-#define SOLARIS_POLL_ERR 4
-#define SOLARIS_POLL_PRI 5
-#define SOLARIS_POLL_HUP 6
+++ /dev/null
-/* $Id: socket.c,v 1.6 2002/02/08 03:57:14 davem Exp $
- * socket.c: Socket syscall emulation for Solaris 2.6+
- *
- * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
- *
- * 1999-08-19 Fixed socketpair code
- * Jason Rappleye (rappleye@ccr.buffalo.edu)
- */
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/socket.h>
-#include <linux/file.h>
-#include <linux/net.h>
-#include <linux/compat.h>
-#include <net/compat.h>
-#include <net/sock.h>
-
-#include <asm/uaccess.h>
-#include <asm/string.h>
-#include <asm/oplib.h>
-#include <asm/idprom.h>
-
-#include "conv.h"
-
-#define SOCK_SOL_STREAM 2
-#define SOCK_SOL_DGRAM 1
-#define SOCK_SOL_RAW 4
-#define SOCK_SOL_RDM 5
-#define SOCK_SOL_SEQPACKET 6
-
-#define SOL_SO_SNDLOWAT 0x1003
-#define SOL_SO_RCVLOWAT 0x1004
-#define SOL_SO_SNDTIMEO 0x1005
-#define SOL_SO_RCVTIMEO 0x1006
-#define SOL_SO_STATE 0x2000
-
-#define SOL_SS_NDELAY 0x040
-#define SOL_SS_NONBLOCK 0x080
-#define SOL_SS_ASYNC 0x100
-
-#define SO_STATE 0x000e
-
-static int socket_check(int family, int type)
-{
- if (family != PF_UNIX && family != PF_INET)
- return -ESOCKTNOSUPPORT;
- switch (type) {
- case SOCK_SOL_STREAM: type = SOCK_STREAM; break;
- case SOCK_SOL_DGRAM: type = SOCK_DGRAM; break;
- case SOCK_SOL_RAW: type = SOCK_RAW; break;
- case SOCK_SOL_RDM: type = SOCK_RDM; break;
- case SOCK_SOL_SEQPACKET: type = SOCK_SEQPACKET; break;
- default: return -EINVAL;
- }
- return type;
-}
-
-static int solaris_to_linux_sockopt(int optname)
-{
- switch (optname) {
- case SOL_SO_SNDLOWAT: optname = SO_SNDLOWAT; break;
- case SOL_SO_RCVLOWAT: optname = SO_RCVLOWAT; break;
- case SOL_SO_SNDTIMEO: optname = SO_SNDTIMEO; break;
- case SOL_SO_RCVTIMEO: optname = SO_RCVTIMEO; break;
- case SOL_SO_STATE: optname = SO_STATE; break;
- };
-
- return optname;
-}
-
-asmlinkage int solaris_socket(int family, int type, int protocol)
-{
- int (*sys_socket)(int, int, int) =
- (int (*)(int, int, int))SYS(socket);
-
- type = socket_check (family, type);
- if (type < 0) return type;
- return sys_socket(family, type, protocol);
-}
-
-asmlinkage int solaris_socketpair(int *usockvec)
-{
- int (*sys_socketpair)(int, int, int, int *) =
- (int (*)(int, int, int, int *))SYS(socketpair);
-
- /* solaris socketpair really only takes one arg at the syscall
- * level, int * usockvec. The libs apparently take care of
- * making sure that family==AF_UNIX and type==SOCK_STREAM. The
- * pointer we really want ends up residing in the first (and
- * supposedly only) argument.
- */
-
- return sys_socketpair(AF_UNIX, SOCK_STREAM, 0, (int *)usockvec);
-}
-
-asmlinkage int solaris_bind(int fd, struct sockaddr *addr, int addrlen)
-{
- int (*sys_bind)(int, struct sockaddr *, int) =
- (int (*)(int, struct sockaddr *, int))SUNOS(104);
-
- return sys_bind(fd, addr, addrlen);
-}
-
-asmlinkage int solaris_setsockopt(int fd, int level, int optname, u32 optval, int optlen)
-{
- int (*sunos_setsockopt)(int, int, int, u32, int) =
- (int (*)(int, int, int, u32, int))SUNOS(105);
-
- optname = solaris_to_linux_sockopt(optname);
- if (optname < 0)
- return optname;
- if (optname == SO_STATE)
- return 0;
-
- return sunos_setsockopt(fd, level, optname, optval, optlen);
-}
-
-asmlinkage int solaris_getsockopt(int fd, int level, int optname, u32 optval, u32 optlen)
-{
- int (*sunos_getsockopt)(int, int, int, u32, u32) =
- (int (*)(int, int, int, u32, u32))SUNOS(118);
-
- optname = solaris_to_linux_sockopt(optname);
- if (optname < 0)
- return optname;
-
- if (optname == SO_STATE)
- optname = SOL_SO_STATE;
-
- return sunos_getsockopt(fd, level, optname, optval, optlen);
-}
-
-asmlinkage int solaris_connect(int fd, struct sockaddr __user *addr, int addrlen)
-{
- int (*sys_connect)(int, struct sockaddr __user *, int) =
- (int (*)(int, struct sockaddr __user *, int))SYS(connect);
-
- return sys_connect(fd, addr, addrlen);
-}
-
-asmlinkage int solaris_accept(int fd, struct sockaddr __user *addr, int __user *addrlen)
-{
- int (*sys_accept)(int, struct sockaddr __user *, int __user *) =
- (int (*)(int, struct sockaddr __user *, int __user *))SYS(accept);
-
- return sys_accept(fd, addr, addrlen);
-}
-
-asmlinkage int solaris_listen(int fd, int backlog)
-{
- int (*sys_listen)(int, int) =
- (int (*)(int, int))SUNOS(106);
-
- return sys_listen(fd, backlog);
-}
-
-asmlinkage int solaris_shutdown(int fd, int how)
-{
- int (*sys_shutdown)(int, int) =
- (int (*)(int, int))SYS(shutdown);
-
- return sys_shutdown(fd, how);
-}
-
-#define MSG_SOL_OOB 0x1
-#define MSG_SOL_PEEK 0x2
-#define MSG_SOL_DONTROUTE 0x4
-#define MSG_SOL_EOR 0x8
-#define MSG_SOL_CTRUNC 0x10
-#define MSG_SOL_TRUNC 0x20
-#define MSG_SOL_WAITALL 0x40
-#define MSG_SOL_DONTWAIT 0x80
-
-static int solaris_to_linux_msgflags(int flags)
-{
- int fl = flags & (MSG_OOB|MSG_PEEK|MSG_DONTROUTE);
-
- if (flags & MSG_SOL_EOR) fl |= MSG_EOR;
- if (flags & MSG_SOL_CTRUNC) fl |= MSG_CTRUNC;
- if (flags & MSG_SOL_TRUNC) fl |= MSG_TRUNC;
- if (flags & MSG_SOL_WAITALL) fl |= MSG_WAITALL;
- if (flags & MSG_SOL_DONTWAIT) fl |= MSG_DONTWAIT;
- return fl;
-}
-
-static int linux_to_solaris_msgflags(int flags)
-{
- int fl = flags & (MSG_OOB|MSG_PEEK|MSG_DONTROUTE);
-
- if (flags & MSG_EOR) fl |= MSG_SOL_EOR;
- if (flags & MSG_CTRUNC) fl |= MSG_SOL_CTRUNC;
- if (flags & MSG_TRUNC) fl |= MSG_SOL_TRUNC;
- if (flags & MSG_WAITALL) fl |= MSG_SOL_WAITALL;
- if (flags & MSG_DONTWAIT) fl |= MSG_SOL_DONTWAIT;
- return fl;
-}
-
-asmlinkage int solaris_recvfrom(int s, char __user *buf, int len, int flags, u32 from, u32 fromlen)
-{
- int (*sys_recvfrom)(int, void __user *, size_t, unsigned, struct sockaddr __user *, int __user *) =
- (int (*)(int, void __user *, size_t, unsigned, struct sockaddr __user *, int __user *))SYS(recvfrom);
-
- return sys_recvfrom(s, buf, len, solaris_to_linux_msgflags(flags), A(from), A(fromlen));
-}
-
-asmlinkage int solaris_recv(int s, char __user *buf, int len, int flags)
-{
- int (*sys_recvfrom)(int, void __user *, size_t, unsigned, struct sockaddr __user *, int __user *) =
- (int (*)(int, void __user *, size_t, unsigned, struct sockaddr __user *, int __user *))SYS(recvfrom);
-
- return sys_recvfrom(s, buf, len, solaris_to_linux_msgflags(flags), NULL, NULL);
-}
-
-asmlinkage int solaris_sendto(int s, char __user *buf, int len, int flags, u32 to, u32 tolen)
-{
- int (*sys_sendto)(int, void __user *, size_t, unsigned, struct sockaddr __user *, int __user *) =
- (int (*)(int, void __user *, size_t, unsigned, struct sockaddr __user *, int __user *))SYS(sendto);
-
- return sys_sendto(s, buf, len, solaris_to_linux_msgflags(flags), A(to), A(tolen));
-}
-
-asmlinkage int solaris_send(int s, char *buf, int len, int flags)
-{
- int (*sys_sendto)(int, void *, size_t, unsigned, struct sockaddr *, int *) =
- (int (*)(int, void *, size_t, unsigned, struct sockaddr *, int *))SYS(sendto);
-
- return sys_sendto(s, buf, len, solaris_to_linux_msgflags(flags), NULL, NULL);
-}
-
-asmlinkage int solaris_getpeername(int fd, struct sockaddr *addr, int *addrlen)
-{
- int (*sys_getpeername)(int, struct sockaddr *, int *) =
- (int (*)(int, struct sockaddr *, int *))SYS(getpeername);
-
- return sys_getpeername(fd, addr, addrlen);
-}
-
-asmlinkage int solaris_getsockname(int fd, struct sockaddr *addr, int *addrlen)
-{
- int (*sys_getsockname)(int, struct sockaddr *, int *) =
- (int (*)(int, struct sockaddr *, int *))SYS(getsockname);
-
- return sys_getsockname(fd, addr, addrlen);
-}
-
-/* XXX This really belongs in some header file... -DaveM */
-#define MAX_SOCK_ADDR 128 /* 108 for Unix domain -
- 16 for IP, 16 for IPX,
- 24 for IPv6,
- about 80 for AX.25 */
-
-struct sol_nmsghdr {
- u32 msg_name;
- int msg_namelen;
- u32 msg_iov;
- u32 msg_iovlen;
- u32 msg_control;
- u32 msg_controllen;
- u32 msg_flags;
-};
-
-struct sol_cmsghdr {
- u32 cmsg_len;
- int cmsg_level;
- int cmsg_type;
- unsigned char cmsg_data[0];
-};
-
-static inline int msghdr_from_user32_to_kern(struct msghdr *kmsg,
- struct sol_nmsghdr __user *umsg)
-{
- u32 tmp1, tmp2, tmp3;
- int err;
-
- err = get_user(tmp1, &umsg->msg_name);
- err |= __get_user(tmp2, &umsg->msg_iov);
- err |= __get_user(tmp3, &umsg->msg_control);
- if (err)
- return -EFAULT;
-
- kmsg->msg_name = A(tmp1);
- kmsg->msg_iov = A(tmp2);
- kmsg->msg_control = A(tmp3);
-
- err = get_user(kmsg->msg_namelen, &umsg->msg_namelen);
- err |= get_user(kmsg->msg_controllen, &umsg->msg_controllen);
- err |= get_user(kmsg->msg_flags, &umsg->msg_flags);
-
- kmsg->msg_flags = solaris_to_linux_msgflags(kmsg->msg_flags);
-
- return err;
-}
-
-asmlinkage int solaris_sendmsg(int fd, struct sol_nmsghdr __user *user_msg, unsigned user_flags)
-{
- struct socket *sock;
- char address[MAX_SOCK_ADDR];
- struct iovec iovstack[UIO_FASTIOV], *iov = iovstack;
- unsigned char ctl[sizeof(struct cmsghdr) + 20];
- unsigned char *ctl_buf = ctl;
- struct msghdr msg_sys;
- int err, ctl_len, iov_size, total_len;
-
- err = -EFAULT;
- if (msghdr_from_user32_to_kern(&msg_sys, user_msg))
- goto out;
-
- sock = sockfd_lookup(fd, &err);
- if (!sock)
- goto out;
-
- /* do not move before msg_sys is valid */
- err = -EMSGSIZE;
- if (msg_sys.msg_iovlen > UIO_MAXIOV)
- goto out_put;
-
- /* Check whether to allocate the iovec area*/
- err = -ENOMEM;
- iov_size = msg_sys.msg_iovlen * sizeof(struct iovec);
- if (msg_sys.msg_iovlen > UIO_FASTIOV) {
- iov = sock_kmalloc(sock->sk, iov_size, GFP_KERNEL);
- if (!iov)
- goto out_put;
- }
-
- err = verify_compat_iovec(&msg_sys, iov, address, VERIFY_READ);
- if (err < 0)
- goto out_freeiov;
- total_len = err;
-
- err = -ENOBUFS;
- if (msg_sys.msg_controllen > INT_MAX)
- goto out_freeiov;
-
- ctl_len = msg_sys.msg_controllen;
- if (ctl_len) {
- struct sol_cmsghdr __user *ucmsg = msg_sys.msg_control;
- unsigned long *kcmsg;
- compat_size_t cmlen;
-
- err = -EINVAL;
- if (ctl_len <= sizeof(compat_size_t))
- goto out_freeiov;
-
- if (ctl_len > sizeof(ctl)) {
- err = -ENOBUFS;
- ctl_buf = kmalloc(ctl_len, GFP_KERNEL);
- if (!ctl_buf)
- goto out_freeiov;
- }
- __get_user(cmlen, &ucmsg->cmsg_len);
- kcmsg = (unsigned long *) ctl_buf;
- *kcmsg++ = (unsigned long)cmlen;
- err = -EFAULT;
- if (copy_from_user(kcmsg, &ucmsg->cmsg_level,
- ctl_len - sizeof(compat_size_t)))
- goto out_freectl;
- msg_sys.msg_control = ctl_buf;
- }
- msg_sys.msg_flags = solaris_to_linux_msgflags(user_flags);
-
- if (sock->file->f_flags & O_NONBLOCK)
- msg_sys.msg_flags |= MSG_DONTWAIT;
- err = sock_sendmsg(sock, &msg_sys, total_len);
-
-out_freectl:
- if (ctl_buf != ctl)
- sock_kfree_s(sock->sk, ctl_buf, ctl_len);
-out_freeiov:
- if (iov != iovstack)
- sock_kfree_s(sock->sk, iov, iov_size);
-out_put:
- sockfd_put(sock);
-out:
- return err;
-}
-
-asmlinkage int solaris_recvmsg(int fd, struct sol_nmsghdr __user *user_msg, unsigned int user_flags)
-{
- struct socket *sock;
- struct iovec iovstack[UIO_FASTIOV];
- struct iovec *iov = iovstack;
- struct msghdr msg_sys;
- unsigned long cmsg_ptr;
- int err, iov_size, total_len, len;
-
- /* kernel mode address */
- char addr[MAX_SOCK_ADDR];
-
- /* user mode address pointers */
- struct sockaddr __user *uaddr;
- int __user *uaddr_len;
-
- if (msghdr_from_user32_to_kern(&msg_sys, user_msg))
- return -EFAULT;
-
- sock = sockfd_lookup(fd, &err);
- if (!sock)
- goto out;
-
- err = -EMSGSIZE;
- if (msg_sys.msg_iovlen > UIO_MAXIOV)
- goto out_put;
-
- /* Check whether to allocate the iovec area*/
- err = -ENOMEM;
- iov_size = msg_sys.msg_iovlen * sizeof(struct iovec);
- if (msg_sys.msg_iovlen > UIO_FASTIOV) {
- iov = sock_kmalloc(sock->sk, iov_size, GFP_KERNEL);
- if (!iov)
- goto out_put;
- }
-
- /*
- * Save the user-mode address (verify_iovec will change the
- * kernel msghdr to use the kernel address space)
- */
-
- uaddr = (void __user *) msg_sys.msg_name;
- uaddr_len = &user_msg->msg_namelen;
- err = verify_compat_iovec(&msg_sys, iov, addr, VERIFY_WRITE);
- if (err < 0)
- goto out_freeiov;
- total_len = err;
-
- cmsg_ptr = (unsigned long) msg_sys.msg_control;
- msg_sys.msg_flags = MSG_CMSG_COMPAT;
-
- if (sock->file->f_flags & O_NONBLOCK)
- user_flags |= MSG_DONTWAIT;
-
- err = sock_recvmsg(sock, &msg_sys, total_len, user_flags);
- if(err < 0)
- goto out_freeiov;
-
- len = err;
-
- if (uaddr != NULL) {
- err = move_addr_to_user(addr, msg_sys.msg_namelen, uaddr, uaddr_len);
- if (err < 0)
- goto out_freeiov;
- }
- err = __put_user(linux_to_solaris_msgflags(msg_sys.msg_flags), &user_msg->msg_flags);
- if (err)
- goto out_freeiov;
- err = __put_user((unsigned long)msg_sys.msg_control - cmsg_ptr,
- &user_msg->msg_controllen);
- if (err)
- goto out_freeiov;
- err = len;
-
-out_freeiov:
- if (iov != iovstack)
- sock_kfree_s(sock->sk, iov, iov_size);
-out_put:
- sockfd_put(sock);
-out:
- return err;
-}
+++ /dev/null
-/* $Id: socksys.c,v 1.21 2002/02/08 03:57:14 davem Exp $
- * socksys.c: /dev/inet/ stuff for Solaris emulation.
- *
- * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- * Copyright (C) 1997, 1998 Patrik Rak (prak3264@ss1000.ms.mff.cuni.cz)
- * Copyright (C) 1995, 1996 Mike Jagdis (jaggy@purplet.demon.co.uk)
- */
-
-/*
- * Dave, _please_ give me specifications on this fscking mess so that I
- * could at least get it into the state when it wouldn't screw the rest of
- * the kernel over. socksys.c and timod.c _stink_ and we are not talking
- * H2S here, it's isopropilmercaptan in concentrations way over LD50. -- AV
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-#include <linux/ioctl.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/init.h>
-#include <linux/poll.h>
-#include <linux/slab.h>
-#include <linux/syscalls.h>
-#include <linux/in.h>
-
-#include <net/sock.h>
-
-#include <asm/uaccess.h>
-#include <asm/termios.h>
-
-#include "conv.h"
-#include "socksys.h"
-
-static int af_inet_protocols[] = {
-IPPROTO_ICMP, IPPROTO_ICMP, IPPROTO_IGMP, IPPROTO_IPIP, IPPROTO_TCP,
-IPPROTO_EGP, IPPROTO_PUP, IPPROTO_UDP, IPPROTO_IDP, IPPROTO_RAW,
-0, 0, 0, 0, 0, 0,
-};
-
-#ifndef DEBUG_SOLARIS_KMALLOC
-
-#define mykmalloc kmalloc
-#define mykfree kfree
-
-#else
-
-extern void * mykmalloc(size_t s, gfp_t gfp);
-extern void mykfree(void *);
-
-#endif
-
-static unsigned int (*sock_poll)(struct file *, poll_table *);
-
-static struct file_operations socksys_file_ops = {
- /* Currently empty */
-};
-
-static int socksys_open(struct inode * inode, struct file * filp)
-{
- int family, type, protocol, fd;
- struct dentry *dentry;
- int (*sys_socket)(int,int,int) =
- (int (*)(int,int,int))SUNOS(97);
- struct sol_socket_struct * sock;
-
- family = ((iminor(inode) >> 4) & 0xf);
- switch (family) {
- case AF_UNIX:
- type = SOCK_STREAM;
- protocol = 0;
- break;
- case AF_INET:
- protocol = af_inet_protocols[iminor(inode) & 0xf];
- switch (protocol) {
- case IPPROTO_TCP: type = SOCK_STREAM; break;
- case IPPROTO_UDP: type = SOCK_DGRAM; break;
- default: type = SOCK_RAW; break;
- }
- break;
- default:
- type = SOCK_RAW;
- protocol = 0;
- break;
- }
-
- fd = sys_socket(family, type, protocol);
- if (fd < 0)
- return fd;
- /*
- * N.B. The following operations are not legal!
- *
- * No shit. WTF is it supposed to do, anyway?
- *
- * Try instead:
- * d_delete(filp->f_path.dentry), then d_instantiate with sock inode
- */
- dentry = filp->f_path.dentry;
- filp->f_path.dentry = dget(fcheck(fd)->f_path.dentry);
- filp->f_path.dentry->d_inode->i_rdev = inode->i_rdev;
- filp->f_path.dentry->d_inode->i_flock = inode->i_flock;
- SOCKET_I(filp->f_path.dentry->d_inode)->file = filp;
- filp->f_op = &socksys_file_ops;
- sock = (struct sol_socket_struct*)
- mykmalloc(sizeof(struct sol_socket_struct), GFP_KERNEL);
- if (!sock) return -ENOMEM;
- SOLDD(("sock=%016lx(%016lx)\n", sock, filp));
- sock->magic = SOLARIS_SOCKET_MAGIC;
- sock->modcount = 0;
- sock->state = TS_UNBND;
- sock->offset = 0;
- sock->pfirst = sock->plast = NULL;
- filp->private_data = sock;
- SOLDD(("filp->private_data %016lx\n", filp->private_data));
-
- sys_close(fd);
- dput(dentry);
- return 0;
-}
-
-static int socksys_release(struct inode * inode, struct file * filp)
-{
- struct sol_socket_struct * sock;
- struct T_primsg *it;
-
- /* XXX: check this */
- sock = (struct sol_socket_struct *)filp->private_data;
- SOLDD(("sock release %016lx(%016lx)\n", sock, filp));
- it = sock->pfirst;
- while (it) {
- struct T_primsg *next = it->next;
-
- SOLDD(("socksys_release %016lx->%016lx\n", it, next));
- mykfree((char*)it);
- it = next;
- }
- filp->private_data = NULL;
- SOLDD(("socksys_release %016lx\n", sock));
- mykfree((char*)sock);
- return 0;
-}
-
-static unsigned int socksys_poll(struct file * filp, poll_table * wait)
-{
- struct inode *ino;
- unsigned int mask = 0;
-
- ino=filp->f_path.dentry->d_inode;
- if (ino && S_ISSOCK(ino->i_mode)) {
- struct sol_socket_struct *sock;
- sock = (struct sol_socket_struct*)filp->private_data;
- if (sock && sock->pfirst) {
- mask |= POLLIN | POLLRDNORM;
- if (sock->pfirst->pri == MSG_HIPRI)
- mask |= POLLPRI;
- }
- }
- if (sock_poll)
- mask |= (*sock_poll)(filp, wait);
- return mask;
-}
-
-static const struct file_operations socksys_fops = {
- .open = socksys_open,
- .release = socksys_release,
-};
-
-int __init init_socksys(void)
-{
- int ret;
- struct file * file;
- int (*sys_socket)(int,int,int) =
- (int (*)(int,int,int))SUNOS(97);
- int (*sys_close)(unsigned int) =
- (int (*)(unsigned int))SYS(close);
-
- ret = register_chrdev (30, "socksys", &socksys_fops);
- if (ret < 0) {
- printk ("Couldn't register socksys character device\n");
- return ret;
- }
- ret = sys_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
- if (ret < 0) {
- printk ("Couldn't create socket\n");
- return ret;
- }
-
- file = fcheck(ret);
- /* N.B. Is this valid? Suppose the f_ops are in a module ... */
- socksys_file_ops = *file->f_op;
- sys_close(ret);
- sock_poll = socksys_file_ops.poll;
- socksys_file_ops.poll = socksys_poll;
- socksys_file_ops.release = socksys_release;
- return 0;
-}
-
-void __exit cleanup_socksys(void)
-{
- unregister_chrdev(30, "socksys");
-}
+++ /dev/null
-/* $Id: socksys.h,v 1.2 1998/03/26 08:46:07 jj Exp $
- * socksys.h: Definitions for STREAMS modules emulation code.
- *
- * Copyright (C) 1998 Patrik Rak (prak3264@ss1000.ms.mff.cuni.cz)
- */
-
-#define MSG_HIPRI 0x01
-#define MSG_ANY 0x02
-#define MSG_BAND 0x04
-
-#define MORECTL 1
-#define MOREDATA 2
-
-#define TBADADDR 1
-#define TBADOPT 2
-#define TACCES 3
-#define TBADF 4
-#define TNOADDR 5
-#define TOUTSTATE 6
-#define TBADSEQ 7
-#define TSYSERR 8
-#define TLOOK 9
-#define TBADDATA 10
-#define TBUFOVFLW 11
-#define TFLOW 12
-#define TNODATA 13
-#define TNODIS 14
-#define TNOUDERR 15
-#define TBADFLAG 16
-#define TNOREL 17
-#define TNOTSUPPORT 18
-#define TSTATECHNG 19
-
-#define T_CONN_REQ 0
-#define T_CONN_RES 1
-#define T_DISCON_REQ 2
-#define T_DATA_REQ 3
-#define T_EXDATA_REQ 4
-#define T_INFO_REQ 5
-#define T_BIND_REQ 6
-#define T_UNBIND_REQ 7
-#define T_UNITDATA_REQ 8
-#define T_OPTMGMT_REQ 9
-#define T_ORDREL_REQ 10
-
-#define T_CONN_IND 11
-#define T_CONN_CON 12
-#define T_DISCON_IND 13
-#define T_DATA_IND 14
-#define T_EXDATA_IND 15
-#define T_INFO_ACK 16
-#define T_BIND_ACK 17
-#define T_ERROR_ACK 18
-#define T_OK_ACK 19
-#define T_UNITDATA_IND 20
-#define T_UDERROR_IND 21
-#define T_OPTMGMT_ACK 22
-#define T_ORDREL_IND 23
-
-#define T_NEGOTIATE 0x0004
-#define T_FAILURE 0x0040
-
-#define TS_UNBND 0 /* unbound */
-#define TS_WACK_BREQ 1 /* waiting for T_BIND_REQ ack */
-#define TS_WACK_UREQ 2 /* waiting for T_UNBIND_REQ ack */
-#define TS_IDLE 3 /* idle */
-#define TS_WACK_OPTREQ 4 /* waiting for T_OPTMGMT_REQ ack */
-#define TS_WACK_CREQ 5 /* waiting for T_CONN_REQ ack */
-#define TS_WCON_CREQ 6 /* waiting for T_CONN_REQ confirmation */
-#define TS_WRES_CIND 7 /* waiting for T_CONN_IND */
-#define TS_WACK_CRES 8 /* waiting for T_CONN_RES ack */
-#define TS_DATA_XFER 9 /* data transfer */
-#define TS_WIND_ORDREL 10 /* releasing read but not write */
-#define TS_WREQ_ORDREL 11 /* wait to release write but not read */
-#define TS_WACK_DREQ6 12 /* waiting for T_DISCON_REQ ack */
-#define TS_WACK_DREQ7 13 /* waiting for T_DISCON_REQ ack */
-#define TS_WACK_DREQ9 14 /* waiting for T_DISCON_REQ ack */
-#define TS_WACK_DREQ10 15 /* waiting for T_DISCON_REQ ack */
-#define TS_WACK_DREQ11 16 /* waiting for T_DISCON_REQ ack */
-#define TS_NOSTATES 17
-
-struct T_conn_req {
- s32 PRIM_type;
- s32 DEST_length;
- s32 DEST_offset;
- s32 OPT_length;
- s32 OPT_offset;
-};
-
-struct T_bind_req {
- s32 PRIM_type;
- s32 ADDR_length;
- s32 ADDR_offset;
- u32 CONIND_number;
-};
-
-struct T_unitdata_req {
- s32 PRIM_type;
- s32 DEST_length;
- s32 DEST_offset;
- s32 OPT_length;
- s32 OPT_offset;
-};
-
-struct T_optmgmt_req {
- s32 PRIM_type;
- s32 OPT_length;
- s32 OPT_offset;
- s32 MGMT_flags;
-};
-
-struct T_bind_ack {
- s32 PRIM_type;
- s32 ADDR_length;
- s32 ADDR_offset;
- u32 CONIND_number;
-};
-
-struct T_error_ack {
- s32 PRIM_type;
- s32 ERROR_prim;
- s32 TLI_error;
- s32 UNIX_error;
-};
-
-struct T_ok_ack {
- s32 PRIM_type;
- s32 CORRECT_prim;
-};
-
-struct T_conn_ind {
- s32 PRIM_type;
- s32 SRC_length;
- s32 SRC_offset;
- s32 OPT_length;
- s32 OPT_offset;
- s32 SEQ_number;
-};
-
-struct T_conn_con {
- s32 PRIM_type;
- s32 RES_length;
- s32 RES_offset;
- s32 OPT_length;
- s32 OPT_offset;
-};
-
-struct T_discon_ind {
- s32 PRIM_type;
- s32 DISCON_reason;
- s32 SEQ_number;
-};
-
-struct T_unitdata_ind {
- s32 PRIM_type;
- s32 SRC_length;
- s32 SRC_offset;
- s32 OPT_length;
- s32 OPT_offset;
-};
-
-struct T_optmgmt_ack {
- s32 PRIM_type;
- s32 OPT_length;
- s32 OPT_offset;
- s32 MGMT_flags;
-};
-
-struct opthdr {
- s32 level;
- s32 name;
- s32 len;
- char value[0];
-};
-
-struct T_primsg {
- struct T_primsg *next;
- unsigned char pri;
- unsigned char band;
- int length;
- s32 type;
-};
-
-struct strbuf {
- s32 maxlen;
- s32 len;
- u32 buf;
-} ;
-
-/* Constants used by STREAMS modules emulation code */
-
-typedef char sol_module;
-
-#define MAX_NR_STREAM_MODULES 16
-
-/* Private data structure assigned to sockets. */
-
-struct sol_socket_struct {
- int magic;
- int modcount;
- sol_module module[MAX_NR_STREAM_MODULES];
- long state;
- int offset;
- struct T_primsg *pfirst, *plast;
-};
-
-#define SOLARIS_SOCKET_MAGIC 0xADDED
-
+++ /dev/null
-/* $Id: systbl.S,v 1.11 2000/03/13 21:57:35 davem Exp $
- * systbl.S: System call entry point table for Solaris compatibility.
- *
- * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
- */
-
-#include <asm/unistd.h>
-
-/* Fall back to sys_call_table32 entry */
-#define CHAIN(name) __NR_##name
-
-/* Pass pt_regs pointer as first argument */
-#define REGS(name) name+1
-
-/* Hack till all be implemented */
-#define solaris_getpmsg solaris_unimplemented
-#define solaris_hrtsys solaris_unimplemented
-#define solaris_msgsys solaris_unimplemented
-#define solaris_putpmsg solaris_unimplemented
-#define solaris_semsys solaris_unimplemented
-
- .data
- .globl solaris_sys_table
-solaris_sys_table:
- .word solaris_unimplemented /* nosys 0 */
- .word CHAIN(exit) /* exit d 1 */
- .word CHAIN(fork) /* fork 2 */
- .word CHAIN(read) /* read dpd 3 */
- .word CHAIN(write) /* write dpd 4 */
- .word solaris_open /* open soo 5 */
- .word CHAIN(close) /* close d 6 */
- .word solaris_wait /* wait xxx 7 */
- .word CHAIN(creat) /* creat so 8 */
- .word CHAIN(link) /* link ss 9 */
- .word CHAIN(unlink) /* unlink s 10 */
- .word solaris_unimplemented /* exec sxx 11 */
- .word CHAIN(chdir) /* chdir s 12 */
- .word CHAIN(time) /* time 13 */
- .word solaris_mknod /* mknod sox 14 */
- .word CHAIN(chmod) /* chmod so 15 */
- .word CHAIN(chown) /* chown sdd 16 */
- .word solaris_brk /* brk/break x 17 */
- .word solaris_stat /* stat sp 18 */
- .word CHAIN(lseek) /* seek/lseek ddd 19 */
- .word solaris_getpid /* getpid 20 */
- .word solaris_unimplemented /* mount 21 */
- .word CHAIN(umount) /* umount s 22 */
- .word CHAIN(setuid) /* setuid d 23 */
- .word solaris_getuid /* getuid 24 */
- .word CHAIN(stime) /* stime d 25 */
-#if 0
- .word solaris_ptrace /* ptrace xdxx 26 */
-#else
- .word CHAIN(ptrace) /* ptrace xdxx 26 */
-#endif
- .word CHAIN(alarm) /* alarm d 27 */
- .word solaris_fstat /* fstat dp 28 */
- .word CHAIN(pause) /* pause 29 */
- .word CHAIN(utime) /* utime xx 30 */
- .word solaris_unimplemented /* stty 31 */
- .word solaris_unimplemented /* gtty 32 */
- .word solaris_access /* access so 33 */
- .word CHAIN(nice) /* nice d 34 */
- .word solaris_statfs /* statfs spdd 35 */
- .word CHAIN(sync) /* sync 36 */
- .word solaris_kill /* kill dd 37 */
- .word solaris_fstatfs /* fstatfs dpdd 38 */
- .word solaris_procids /* pgrpsys ddd 39 */
- .word solaris_unimplemented /* xenix 40 */
- .word CHAIN(dup) /* dup d 41 */
- .word CHAIN(pipe) /* pipe 42 */
- .word CHAIN(times) /* times p 43 */
- .word 44 /*CHAIN(profil)*/ /* prof xxxx 44 */
- .word solaris_unimplemented /* lock/plock 45 */
- .word CHAIN(setgid) /* setgid d 46 */
- .word solaris_getgid /* getgid 47 */
- .word solaris_sigfunc /* sigfunc xx 48 */
- .word REGS(solaris_msgsys) /* msgsys dxddd 49 */
- .word solaris_unimplemented /* syssun/3b 50 */
- .word CHAIN(acct) /* acct/sysacct x 51 */
- .word solaris_shmsys /* shmsys ddxo 52 */
- .word REGS(solaris_semsys) /* semsys dddx 53 */
- .word solaris_ioctl /* ioctl dxx 54 */
- .word solaris_unimplemented /* uadmin xxx 55 */
- .word solaris_unimplemented /* reserved:exch 56 */
- .word solaris_utssys /* utssys x 57 */
- .word CHAIN(fsync) /* fsync d 58 */
- .word CHAIN(execve) /* execv spp 59 */
- .word CHAIN(umask) /* umask o 60 */
- .word CHAIN(chroot) /* chroot s 61 */
- .word solaris_fcntl /* fcntl dxx 62 */
- .word solaris_ulimit /* ulimit xx 63 */
- .word solaris_unimplemented /* ? 64 */
- .word solaris_unimplemented /* ? 65 */
- .word solaris_unimplemented /* ? 66 */
- .word solaris_unimplemented /* ? 67 */
- .word solaris_unimplemented /* ? 68 */
- .word solaris_unimplemented /* ? 69 */
- .word solaris_unimplemented /* advfs 70 */
- .word solaris_unimplemented /* unadvfs 71 */
- .word solaris_unimplemented /* rmount 72 */
- .word solaris_unimplemented /* rumount 73 */
- .word solaris_unimplemented /* rfstart 74 */
- .word solaris_unimplemented /* ? 75 */
- .word solaris_unimplemented /* rdebug 76 */
- .word solaris_unimplemented /* rfstop 77 */
- .word solaris_unimplemented /* rfsys 78 */
- .word CHAIN(rmdir) /* rmdir s 79 */
- .word CHAIN(mkdir) /* mkdir so 80 */
- .word CHAIN(getdents) /* getdents dxd 81 */
- .word solaris_unimplemented /* libattach 82 */
- .word solaris_unimplemented /* libdetach 83 */
- .word CHAIN(sysfs) /* sysfs dxx 84 */
- .word solaris_getmsg /* getmsg dxxx 85 */
- .word solaris_putmsg /* putmsg dxxd 86 */
- .word CHAIN(poll) /* poll xdd 87 */
- .word solaris_lstat /* lstat sp 88 */
- .word CHAIN(symlink) /* symlink ss 89 */
- .word CHAIN(readlink) /* readlink spd 90 */
- .word CHAIN(setgroups) /* setgroups dp 91 */
- .word CHAIN(getgroups) /* getgroups dp 92 */
- .word CHAIN(fchmod) /* fchmod do 93 */
- .word CHAIN(fchown) /* fchown ddd 94 */
- .word solaris_sigprocmask /* sigprocmask dxx 95 */
- .word solaris_sigsuspend /* sigsuspend x 96 */
- .word solaris_sigaltstack /* sigaltstack xx 97 */
- .word solaris_sigaction /* sigaction dxx 98 */
- .word solaris_sigpending /* sigpending dd 99 */
- .word REGS(solaris_context) /* context 100 */
- .word solaris_unimplemented /* evsys 101 */
- .word solaris_unimplemented /* evtrapret 102 */
- .word solaris_statvfs /* statvfs sp 103 */
- .word solaris_fstatvfs /* fstatvfs dp 104 */
- .word solaris_unimplemented /* unknown 105 */
- .word solaris_unimplemented /* nfssys 106 */
- .word solaris_waitid /* waitid ddxd 107 */
- .word solaris_unimplemented /* sigsendsys ddd 108 */
- .word REGS(solaris_hrtsys) /* hrtsys xxx 109 */
- .word solaris_unimplemented /* acancel dxd 110 */
- .word solaris_unimplemented /* async 111 */
- .word solaris_unimplemented /* priocntlsys 112 */
- .word solaris_pathconf /* pathconf sd 113 */
- .word CHAIN(mincore) /* mincore d 114 */
- .word solaris_mmap /* mmap xxxxdx 115 */
- .word CHAIN(mprotect) /* mprotect xdx 116 */
- .word CHAIN(munmap) /* munmap xd 117 */
- .word solaris_fpathconf /* fpathconf dd 118 */
- .word CHAIN(fork) /* fork 119 */
- .word solaris_unimplemented /* fchdir d 120 */
- .word CHAIN(readv) /* readv dxd 121 */
- .word CHAIN(writev) /* writev dxd 122 */
- .word solaris_xstat /* xstat dsx 123 */
- .word solaris_lxstat /* lxstat dsx 124 */
- .word solaris_fxstat /* fxstat ddx 125 */
- .word solaris_xmknod /* xmknod dsox 126 */
- .word solaris_unimplemented /* syslocal d 127 */
- .word solaris_setrlimit /* setrlimit dp 128 */
- .word solaris_getrlimit /* getrlimit dp 129 */
- .word CHAIN(chown) /* lchown sdd 130 */
- .word solaris_unimplemented /* memcntl 131 */
- .word solaris_getpmsg /* getpmsg dxxxx 132 */
- .word solaris_putpmsg /* putpmsg dxxdd 133 */
- .word CHAIN(rename) /* rename ss 134 */
- .word solaris_utsname /* uname x 135 */
- .word solaris_unimplemented /* setegid 136 */
- .word solaris_sysconf /* sysconfig d 137 */
- .word solaris_unimplemented /* adjtime 138 */
- .word solaris_sysinfo /* systeminfo dsd 139 */
- .word solaris_unimplemented /* ? 140 */
- .word solaris_unimplemented /* seteuid 141 */
- .word solaris_unimplemented /* ? 142 */
- .word solaris_unimplemented /* ? 143 */
- .word solaris_unimplemented /* secsys dx 144 */
- .word solaris_unimplemented /* filepriv sdxd 145 */
- .word solaris_unimplemented /* procpriv dxd 146 */
- .word solaris_unimplemented /* devstat sdx 147 */
- .word solaris_unimplemented /* aclipc ddddx 148 */
- .word solaris_unimplemented /* fdevstat ddx 149 */
- .word solaris_unimplemented /* flvlfile ddx 150 */
- .word solaris_unimplemented /* lvlfile sdx 151 */
- .word solaris_unimplemented /* ? 152 */
- .word solaris_unimplemented /* fchroot d 153 */
- .word solaris_unimplemented /* lvlproc dx 154 */
- .word solaris_unimplemented /* ? 155 */
- .word solaris_gettimeofday /* gettimeofday x 156 */
- .word CHAIN(getitimer) /* getitimer dx 157 */
- .word CHAIN(setitimer) /* setitimer dxx 158 */
- .word solaris_unimplemented /* lwp-xxx 159 */
- .word solaris_unimplemented /* lwp-xxx 160 */
- .word solaris_unimplemented /* lwp-xxx 161 */
- .word solaris_unimplemented /* lwp-xxx 162 */
- .word solaris_unimplemented /* lwp-xxx 163 */
- .word solaris_unimplemented /* lwp-xxx 164 */
- .word solaris_unimplemented /* lwp-xxx 165 */
- .word solaris_unimplemented /* lwp-xxx 166 */
- .word solaris_unimplemented /* lwp-xxx 167 */
- .word solaris_unimplemented /* lwp-xxx 168 */
- .word solaris_unimplemented /* lwp-xxx 169 */
- .word solaris_unimplemented /* lwp-xxx 170 */
- .word solaris_unimplemented /* lwp-xxx 171 */
- .word solaris_unimplemented /* lwp-xxx 172 */
- .word solaris_pread /* pread dpdd 173 */
- .word solaris_pwrite /* pwrite dpdd 174 */
- .word REGS(solaris_llseek) /* llseek dLd 175 */
- .word solaris_unimplemented /* lwpself 176 */
- .word solaris_unimplemented /* lwpinfo 177 */
- .word solaris_unimplemented /* lwpprivate 178 */
- .word solaris_unimplemented /* processorbind 179 */
- .word solaris_unimplemented /* processorexbind 180 */
- .word solaris_unimplemented /* 181 */
- .word solaris_unimplemented /* sync_mailbox 182 */
- .word solaris_unimplemented /* prepblock 183 */
- .word solaris_unimplemented /* block 184 */
- .word solaris_acl /* acl sddp 185 */
- .word solaris_unimplemented /* unblock 186 */
- .word solaris_unimplemented /* cancelblock 187 */
- .word solaris_unimplemented /* ? 188 */
- .word solaris_unimplemented /* xxxxx 189 */
- .word solaris_unimplemented /* xxxxxe 190 */
- .word solaris_unimplemented /* 191 */
- .word solaris_unimplemented /* 192 */
- .word solaris_unimplemented /* 193 */
- .word solaris_unimplemented /* 194 */
- .word solaris_unimplemented /* 195 */
- .word solaris_unimplemented /* 196 */
- .word solaris_unimplemented /* 197 */
- .word solaris_unimplemented /* 198 */
- .word CHAIN(nanosleep) /* nanosleep dd 199 */
- .word solaris_facl /* facl dddp 200 */
- .word solaris_unimplemented /* 201 */
- .word CHAIN(setreuid) /* setreuid dd 202 */
- .word CHAIN(setregid) /* setregid dd 203 */
- .word solaris_unimplemented /* 204 */
- .word solaris_unimplemented /* 205 */
- .word solaris_unimplemented /* 206 */
- .word solaris_unimplemented /* 207 */
- .word solaris_unimplemented /* 208 */
- .word solaris_unimplemented /* 209 */
- .word solaris_unimplemented /* 210 */
- .word solaris_unimplemented /* 211 */
- .word solaris_unimplemented /* 212 */
- .word solaris_getdents64 /* getdents64 dpd 213 */
- .word REGS(solaris_mmap64) /* mmap64 xxxxdX 214 */
- .word solaris_stat64 /* stat64 sP 215 */
- .word solaris_lstat64 /* lstat64 sP 216 */
- .word solaris_fstat64 /* fstat64 dP 217 */
- .word solaris_statvfs64 /* statvfs64 sP 218 */
- .word solaris_fstatvfs64 /* fstatvfs64 dP 219 */
- .word solaris_setrlimit64 /* setrlimit64 dP 220 */
- .word solaris_getrlimit64 /* getrlimit64 dP 221 */
- .word CHAIN(pread64) /* pread64 dpdD 222 */
- .word CHAIN(pwrite64) /* pwrite64 dpdD 223 */
- .word CHAIN(creat) /* creat64 so 224 */
- .word solaris_open /* open64 soo 225 */
- .word solaris_unimplemented /* 226 */
- .word solaris_unimplemented /* 227 */
- .word solaris_unimplemented /* 228 */
- .word solaris_unimplemented /* 229 */
- .word solaris_socket /* socket ddd 230 */
- .word solaris_socketpair /* socketpair dddp 231 */
- .word solaris_bind /* bind dpd 232 */
- .word solaris_listen /* listen dd 233 */
- .word solaris_accept /* accept dpp 234 */
- .word solaris_connect /* connect dpd 235 */
- .word solaris_shutdown /* shutdown dd 236 */
- .word solaris_recv /* recv dpdd 237 */
- .word solaris_recvfrom /* recvfrom dpddpp 238 */
- .word solaris_recvmsg /* recvmsg dpd 239 */
- .word solaris_send /* send dpdd 240 */
- .word solaris_sendmsg /* sendmsg dpd 241 */
- .word solaris_sendto /* sendto dpddpd 242 */
- .word solaris_getpeername /* getpeername dpp 243 */
- .word solaris_getsockname /* getsockname dpp 244 */
- .word solaris_getsockopt /* getsockopt dddpp 245 */
- .word solaris_setsockopt /* setsockopt dddpp 246 */
- .word solaris_unimplemented /* 247 */
- .word solaris_ntp_gettime /* ntp_gettime p 248 */
- .word solaris_ntp_adjtime /* ntp_adjtime p 249 */
- .word solaris_unimplemented /* 250 */
- .word solaris_unimplemented /* 251 */
- .word solaris_unimplemented /* 252 */
- .word solaris_unimplemented /* 253 */
- .word solaris_unimplemented /* 254 */
- .word solaris_unimplemented /* 255 */
+++ /dev/null
-/* $Id: timod.c,v 1.19 2002/02/08 03:57:14 davem Exp $
- * timod.c: timod emulation.
- *
- * Copyright (C) 1998 Patrik Rak (prak3264@ss1000.ms.mff.cuni.cz)
- *
- * Streams & timod emulation based on code
- * Copyright (C) 1995, 1996 Mike Jagdis (jaggy@purplet.demon.co.uk)
- *
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-#include <linux/ioctl.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/netdevice.h>
-#include <linux/poll.h>
-
-#include <net/sock.h>
-
-#include <asm/uaccess.h>
-#include <asm/termios.h>
-
-#include "conv.h"
-#include "socksys.h"
-
-asmlinkage int solaris_ioctl(unsigned int fd, unsigned int cmd, u32 arg);
-
-static DEFINE_SPINLOCK(timod_pagelock);
-static char * page = NULL ;
-
-#ifndef DEBUG_SOLARIS_KMALLOC
-
-#define mykmalloc kmalloc
-#define mykfree kfree
-
-#else
-
-void * mykmalloc(size_t s, gfp_t gfp)
-{
- static char * page;
- static size_t free;
- void * r;
- s = ((s + 63) & ~63);
- if( s > PAGE_SIZE ) {
- SOLD("too big size, calling real kmalloc");
- return kmalloc(s, gfp);
- }
- if( s > free ) {
- /* we are wasting memory, but we don't care */
- page = (char *)__get_free_page(gfp);
- free = PAGE_SIZE;
- }
- r = page;
- page += s;
- free -= s;
- return r;
-}
-
-void mykfree(void *p)
-{
-}
-
-#endif
-
-#ifndef DEBUG_SOLARIS
-
-#define BUF_SIZE PAGE_SIZE
-#define PUT_MAGIC(a,m)
-#define SCHECK_MAGIC(a,m)
-#define BUF_OFFSET 0
-#define MKCTL_TRAILER 0
-
-#else
-
-#define BUF_SIZE (PAGE_SIZE-2*sizeof(u64))
-#define BUFPAGE_MAGIC 0xBADC0DEDDEADBABEL
-#define MKCTL_MAGIC 0xDEADBABEBADC0DEDL
-#define PUT_MAGIC(a,m) do{(*(u64*)(a))=(m);}while(0)
-#define SCHECK_MAGIC(a,m) do{if((*(u64*)(a))!=(m))printk("%s,%u,%s(): magic %08x at %p corrupted!\n",\
- __FILE__,__LINE__,__func__,(m),(a));}while(0)
-#define BUF_OFFSET sizeof(u64)
-#define MKCTL_TRAILER sizeof(u64)
-
-#endif
-
-static char *getpage( void )
-{
- char *r;
- SOLD("getting page");
- spin_lock(&timod_pagelock);
- if (page) {
- r = page;
- page = NULL;
- spin_unlock(&timod_pagelock);
- SOLD("got cached");
- return r + BUF_OFFSET;
- }
- spin_unlock(&timod_pagelock);
- SOLD("getting new");
- r = (char *)__get_free_page(GFP_KERNEL);
- PUT_MAGIC(r,BUFPAGE_MAGIC);
- PUT_MAGIC(r+PAGE_SIZE-sizeof(u64),BUFPAGE_MAGIC);
- return r + BUF_OFFSET;
-}
-
-static void putpage(char *p)
-{
- SOLD("putting page");
- p = p - BUF_OFFSET;
- SCHECK_MAGIC(p,BUFPAGE_MAGIC);
- SCHECK_MAGIC(p+PAGE_SIZE-sizeof(u64),BUFPAGE_MAGIC);
- spin_lock(&timod_pagelock);
- if (page) {
- spin_unlock(&timod_pagelock);
- free_page((unsigned long)p);
- SOLD("freed it");
- } else {
- page = p;
- spin_unlock(&timod_pagelock);
- SOLD("cached it");
- }
-}
-
-static struct T_primsg *timod_mkctl(int size)
-{
- struct T_primsg *it;
-
- SOLD("creating primsg");
- it = (struct T_primsg *)mykmalloc(size+sizeof(*it)-sizeof(s32)+2*MKCTL_TRAILER, GFP_KERNEL);
- if (it) {
- SOLD("got it");
- it->pri = MSG_HIPRI;
- it->length = size;
- PUT_MAGIC((char*)((u64)(((char *)&it->type)+size+7)&~7),MKCTL_MAGIC);
- }
- return it;
-}
-
-static void timod_wake_socket(unsigned int fd)
-{
- struct socket *sock;
- struct fdtable *fdt;
-
- SOLD("wakeing socket");
- fdt = files_fdtable(current->files);
- sock = SOCKET_I(fdt->fd[fd]->f_path.dentry->d_inode);
- wake_up_interruptible(&sock->wait);
- read_lock(&sock->sk->sk_callback_lock);
- if (sock->fasync_list && !test_bit(SOCK_ASYNC_WAITDATA, &sock->flags))
- __kill_fasync(sock->fasync_list, SIGIO, POLL_IN);
- read_unlock(&sock->sk->sk_callback_lock);
- SOLD("done");
-}
-
-static void timod_queue(unsigned int fd, struct T_primsg *it)
-{
- struct sol_socket_struct *sock;
- struct fdtable *fdt;
-
- SOLD("queuing primsg");
- fdt = files_fdtable(current->files);
- sock = (struct sol_socket_struct *)fdt->fd[fd]->private_data;
- it->next = sock->pfirst;
- sock->pfirst = it;
- if (!sock->plast)
- sock->plast = it;
- timod_wake_socket(fd);
- SOLD("done");
-}
-
-static void timod_queue_end(unsigned int fd, struct T_primsg *it)
-{
- struct sol_socket_struct *sock;
- struct fdtable *fdt;
-
- SOLD("queuing primsg at end");
- fdt = files_fdtable(current->files);
- sock = (struct sol_socket_struct *)fdt->fd[fd]->private_data;
- it->next = NULL;
- if (sock->plast)
- sock->plast->next = it;
- else
- sock->pfirst = it;
- sock->plast = it;
- SOLD("done");
-}
-
-static void timod_error(unsigned int fd, int prim, int terr, int uerr)
-{
- struct T_primsg *it;
-
- SOLD("making error");
- it = timod_mkctl(sizeof(struct T_error_ack));
- if (it) {
- struct T_error_ack *err = (struct T_error_ack *)&it->type;
-
- SOLD("got it");
- err->PRIM_type = T_ERROR_ACK;
- err->ERROR_prim = prim;
- err->TLI_error = terr;
- err->UNIX_error = uerr; /* FIXME: convert this */
- timod_queue(fd, it);
- }
- SOLD("done");
-}
-
-static void timod_ok(unsigned int fd, int prim)
-{
- struct T_primsg *it;
- struct T_ok_ack *ok;
-
- SOLD("creating ok ack");
- it = timod_mkctl(sizeof(*ok));
- if (it) {
- SOLD("got it");
- ok = (struct T_ok_ack *)&it->type;
- ok->PRIM_type = T_OK_ACK;
- ok->CORRECT_prim = prim;
- timod_queue(fd, it);
- }
- SOLD("done");
-}
-
-static int timod_optmgmt(unsigned int fd, int flag, char __user *opt_buf, int opt_len, int do_ret)
-{
- int error, failed;
- int ret_space, ret_len;
- long args[5];
- char *ret_pos,*ret_buf;
- int (*sys_socketcall)(int, unsigned long *) =
- (int (*)(int, unsigned long *))SYS(socketcall);
- mm_segment_t old_fs = get_fs();
-
- SOLD("entry");
- SOLDD(("fd %u flg %u buf %p len %u doret %u",fd,flag,opt_buf,opt_len,do_ret));
- if (!do_ret && (!opt_buf || opt_len <= 0))
- return 0;
- SOLD("getting page");
- ret_pos = ret_buf = getpage();
- ret_space = BUF_SIZE;
- ret_len = 0;
-
- error = failed = 0;
- SOLD("looping");
- while(opt_len >= sizeof(struct opthdr)) {
- struct opthdr *opt;
- int orig_opt_len;
- SOLD("loop start");
- opt = (struct opthdr *)ret_pos;
- if (ret_space < sizeof(struct opthdr)) {
- failed = TSYSERR;
- break;
- }
- SOLD("getting opthdr");
- if (copy_from_user(opt, opt_buf, sizeof(struct opthdr)) ||
- opt->len > opt_len) {
- failed = TBADOPT;
- break;
- }
- SOLD("got opthdr");
- if (flag == T_NEGOTIATE) {
- char *buf;
-
- SOLD("handling T_NEGOTIATE");
- buf = ret_pos + sizeof(struct opthdr);
- if (ret_space < opt->len + sizeof(struct opthdr) ||
- copy_from_user(buf, opt_buf+sizeof(struct opthdr), opt->len)) {
- failed = TSYSERR;
- break;
- }
- SOLD("got optdata");
- args[0] = fd;
- args[1] = opt->level;
- args[2] = opt->name;
- args[3] = (long)buf;
- args[4] = opt->len;
- SOLD("calling SETSOCKOPT");
- set_fs(KERNEL_DS);
- error = sys_socketcall(SYS_SETSOCKOPT, args);
- set_fs(old_fs);
- if (error) {
- failed = TBADOPT;
- break;
- }
- SOLD("SETSOCKOPT ok");
- }
- orig_opt_len = opt->len;
- opt->len = ret_space - sizeof(struct opthdr);
- if (opt->len < 0) {
- failed = TSYSERR;
- break;
- }
- args[0] = fd;
- args[1] = opt->level;
- args[2] = opt->name;
- args[3] = (long)(ret_pos+sizeof(struct opthdr));
- args[4] = (long)&opt->len;
- SOLD("calling GETSOCKOPT");
- set_fs(KERNEL_DS);
- error = sys_socketcall(SYS_GETSOCKOPT, args);
- set_fs(old_fs);
- if (error) {
- failed = TBADOPT;
- break;
- }
- SOLD("GETSOCKOPT ok");
- ret_space -= sizeof(struct opthdr) + opt->len;
- ret_len += sizeof(struct opthdr) + opt->len;
- ret_pos += sizeof(struct opthdr) + opt->len;
- opt_len -= sizeof(struct opthdr) + orig_opt_len;
- opt_buf += sizeof(struct opthdr) + orig_opt_len;
- SOLD("loop end");
- }
- SOLD("loop done");
- if (do_ret) {
- SOLD("generating ret msg");
- if (failed)
- timod_error(fd, T_OPTMGMT_REQ, failed, -error);
- else {
- struct T_primsg *it;
- it = timod_mkctl(sizeof(struct T_optmgmt_ack) + ret_len);
- if (it) {
- struct T_optmgmt_ack *ack =
- (struct T_optmgmt_ack *)&it->type;
- SOLD("got primsg");
- ack->PRIM_type = T_OPTMGMT_ACK;
- ack->OPT_length = ret_len;
- ack->OPT_offset = sizeof(struct T_optmgmt_ack);
- ack->MGMT_flags = (failed ? T_FAILURE : flag);
- memcpy(((char*)ack)+sizeof(struct T_optmgmt_ack),
- ret_buf, ret_len);
- timod_queue(fd, it);
- }
- }
- }
- SOLDD(("put_page %p\n", ret_buf));
- putpage(ret_buf);
- SOLD("done");
- return 0;
-}
-
-int timod_putmsg(unsigned int fd, char __user *ctl_buf, int ctl_len,
- char __user *data_buf, int data_len, int flags)
-{
- int ret, error, terror;
- char *buf;
- struct file *filp;
- struct inode *ino;
- struct fdtable *fdt;
- struct sol_socket_struct *sock;
- mm_segment_t old_fs = get_fs();
- long args[6];
- int (*sys_socketcall)(int, unsigned long __user *) =
- (int (*)(int, unsigned long __user *))SYS(socketcall);
- int (*sys_sendto)(int, void __user *, size_t, unsigned, struct sockaddr __user *, int) =
- (int (*)(int, void __user *, size_t, unsigned, struct sockaddr __user *, int))SYS(sendto);
-
- fdt = files_fdtable(current->files);
- filp = fdt->fd[fd];
- ino = filp->f_path.dentry->d_inode;
- sock = (struct sol_socket_struct *)filp->private_data;
- SOLD("entry");
- if (get_user(ret, (int __user *)A(ctl_buf)))
- return -EFAULT;
- switch (ret) {
- case T_BIND_REQ:
- {
- struct T_bind_req req;
-
- SOLDD(("bind %016lx(%016lx)\n", sock, filp));
- SOLD("T_BIND_REQ");
- if (sock->state != TS_UNBND) {
- timod_error(fd, T_BIND_REQ, TOUTSTATE, 0);
- return 0;
- }
- SOLD("state ok");
- if (copy_from_user(&req, ctl_buf, sizeof(req))) {
- timod_error(fd, T_BIND_REQ, TSYSERR, EFAULT);
- return 0;
- }
- SOLD("got ctl req");
- if (req.ADDR_offset && req.ADDR_length) {
- if (req.ADDR_length > BUF_SIZE) {
- timod_error(fd, T_BIND_REQ, TSYSERR, EFAULT);
- return 0;
- }
- SOLD("req size ok");
- buf = getpage();
- if (copy_from_user(buf, ctl_buf + req.ADDR_offset, req.ADDR_length)) {
- timod_error(fd, T_BIND_REQ, TSYSERR, EFAULT);
- putpage(buf);
- return 0;
- }
- SOLD("got ctl data");
- args[0] = fd;
- args[1] = (long)buf;
- args[2] = req.ADDR_length;
- SOLD("calling BIND");
- set_fs(KERNEL_DS);
- error = sys_socketcall(SYS_BIND, args);
- set_fs(old_fs);
- putpage(buf);
- SOLD("BIND returned");
- } else
- error = 0;
- if (!error) {
- struct T_primsg *it;
- if (req.CONIND_number) {
- args[0] = fd;
- args[1] = req.CONIND_number;
- SOLD("calling LISTEN");
- set_fs(KERNEL_DS);
- error = sys_socketcall(SYS_LISTEN, args);
- set_fs(old_fs);
- SOLD("LISTEN done");
- }
- it = timod_mkctl(sizeof(struct T_bind_ack)+sizeof(struct sockaddr));
- if (it) {
- struct T_bind_ack *ack;
-
- ack = (struct T_bind_ack *)&it->type;
- ack->PRIM_type = T_BIND_ACK;
- ack->ADDR_offset = sizeof(*ack);
- ack->ADDR_length = sizeof(struct sockaddr);
- ack->CONIND_number = req.CONIND_number;
- args[0] = fd;
- args[1] = (long)(ack+sizeof(*ack));
- args[2] = (long)&ack->ADDR_length;
- set_fs(KERNEL_DS);
- sys_socketcall(SYS_GETSOCKNAME,args);
- set_fs(old_fs);
- sock->state = TS_IDLE;
- timod_ok(fd, T_BIND_REQ);
- timod_queue_end(fd, it);
- SOLD("BIND done");
- return 0;
- }
- }
- SOLD("some error");
- switch (error) {
- case -EINVAL:
- terror = TOUTSTATE;
- error = 0;
- break;
- case -EACCES:
- terror = TACCES;
- error = 0;
- break;
- case -EADDRNOTAVAIL:
- case -EADDRINUSE:
- terror = TNOADDR;
- error = 0;
- break;
- default:
- terror = TSYSERR;
- break;
- }
- timod_error(fd, T_BIND_REQ, terror, -error);
- SOLD("BIND done");
- return 0;
- }
- case T_CONN_REQ:
- {
- struct T_conn_req req;
- unsigned short oldflags;
- struct T_primsg *it;
- SOLD("T_CONN_REQ");
- if (sock->state != TS_UNBND && sock->state != TS_IDLE) {
- timod_error(fd, T_CONN_REQ, TOUTSTATE, 0);
- return 0;
- }
- SOLD("state ok");
- if (copy_from_user(&req, ctl_buf, sizeof(req))) {
- timod_error(fd, T_CONN_REQ, TSYSERR, EFAULT);
- return 0;
- }
- SOLD("got ctl req");
- if (ctl_len > BUF_SIZE) {
- timod_error(fd, T_CONN_REQ, TSYSERR, EFAULT);
- return 0;
- }
- SOLD("req size ok");
- buf = getpage();
- if (copy_from_user(buf, ctl_buf, ctl_len)) {
- timod_error(fd, T_CONN_REQ, TSYSERR, EFAULT);
- putpage(buf);
- return 0;
- }
-#ifdef DEBUG_SOLARIS
- {
- char * ptr = buf;
- int len = ctl_len;
- printk("returned data (%d bytes): ",len);
- while( len-- ) {
- if (!(len & 7))
- printk(" ");
- printk("%02x",(unsigned char)*ptr++);
- }
- printk("\n");
- }
-#endif
- SOLD("got ctl data");
- args[0] = fd;
- args[1] = (long)buf+req.DEST_offset;
- args[2] = req.DEST_length;
- oldflags = filp->f_flags;
- filp->f_flags &= ~O_NONBLOCK;
- SOLD("calling CONNECT");
- set_fs(KERNEL_DS);
- error = sys_socketcall(SYS_CONNECT, args);
- set_fs(old_fs);
- filp->f_flags = oldflags;
- SOLD("CONNECT done");
- if (!error) {
- struct T_conn_con *con;
- SOLD("no error");
- it = timod_mkctl(ctl_len);
- if (!it) {
- putpage(buf);
- return -ENOMEM;
- }
- con = (struct T_conn_con *)&it->type;
-#ifdef DEBUG_SOLARIS
- {
- char * ptr = buf;
- int len = ctl_len;
- printk("returned data (%d bytes): ",len);
- while( len-- ) {
- if (!(len & 7))
- printk(" ");
- printk("%02x",(unsigned char)*ptr++);
- }
- printk("\n");
- }
-#endif
- memcpy(con, buf, ctl_len);
- SOLD("copied ctl_buf");
- con->PRIM_type = T_CONN_CON;
- sock->state = TS_DATA_XFER;
- } else {
- struct T_discon_ind *dis;
- SOLD("some error");
- it = timod_mkctl(sizeof(*dis));
- if (!it) {
- putpage(buf);
- return -ENOMEM;
- }
- SOLD("got primsg");
- dis = (struct T_discon_ind *)&it->type;
- dis->PRIM_type = T_DISCON_IND;
- dis->DISCON_reason = -error; /* FIXME: convert this as in iABI_errors() */
- dis->SEQ_number = 0;
- }
- putpage(buf);
- timod_ok(fd, T_CONN_REQ);
- it->pri = 0;
- timod_queue_end(fd, it);
- SOLD("CONNECT done");
- return 0;
- }
- case T_OPTMGMT_REQ:
- {
- struct T_optmgmt_req req;
- SOLD("OPTMGMT_REQ");
- if (copy_from_user(&req, ctl_buf, sizeof(req)))
- return -EFAULT;
- SOLD("got req");
- return timod_optmgmt(fd, req.MGMT_flags,
- req.OPT_offset > 0 ? ctl_buf + req.OPT_offset : NULL,
- req.OPT_length, 1);
- }
- case T_UNITDATA_REQ:
- {
- struct T_unitdata_req req;
-
- int err;
- SOLD("T_UNITDATA_REQ");
- if (sock->state != TS_IDLE && sock->state != TS_DATA_XFER) {
- timod_error(fd, T_CONN_REQ, TOUTSTATE, 0);
- return 0;
- }
- SOLD("state ok");
- if (copy_from_user(&req, ctl_buf, sizeof(req))) {
- timod_error(fd, T_CONN_REQ, TSYSERR, EFAULT);
- return 0;
- }
- SOLD("got ctl req");
-#ifdef DEBUG_SOLARIS
- {
- char * ptr = ctl_buf+req.DEST_offset;
- int len = req.DEST_length;
- printk("socket address (%d bytes): ",len);
- while( len-- ) {
- char c;
- if (get_user(c,ptr))
- printk("??");
- else
- printk("%02x",(unsigned char)c);
- ptr++;
- }
- printk("\n");
- }
-#endif
- err = sys_sendto(fd, data_buf, data_len, 0, req.DEST_length > 0 ? (struct sockaddr __user *)(ctl_buf+req.DEST_offset) : NULL, req.DEST_length);
- if (err == data_len)
- return 0;
- if(err >= 0) {
- printk("timod: sendto failed to send all the data\n");
- return 0;
- }
- timod_error(fd, T_CONN_REQ, TSYSERR, -err);
- return 0;
- }
- default:
- printk(KERN_INFO "timod_putmsg: unsupported command %u.\n", ret);
- break;
- }
- return -EINVAL;
-}
-
-int timod_getmsg(unsigned int fd, char __user *ctl_buf, int ctl_maxlen, s32 __user *ctl_len,
- char __user *data_buf, int data_maxlen, s32 __user *data_len, int *flags_p)
-{
- int error;
- int oldflags;
- struct file *filp;
- struct inode *ino;
- struct fdtable *fdt;
- struct sol_socket_struct *sock;
- struct T_unitdata_ind udi;
- mm_segment_t old_fs = get_fs();
- long args[6];
- char __user *tmpbuf;
- int tmplen;
- int (*sys_socketcall)(int, unsigned long __user *) =
- (int (*)(int, unsigned long __user *))SYS(socketcall);
- int (*sys_recvfrom)(int, void __user *, size_t, unsigned, struct sockaddr __user *, int __user *);
-
- SOLD("entry");
- SOLDD(("%u %p %d %p %p %d %p %d\n", fd, ctl_buf, ctl_maxlen, ctl_len, data_buf, data_maxlen, data_len, *flags_p));
- fdt = files_fdtable(current->files);
- filp = fdt->fd[fd];
- ino = filp->f_path.dentry->d_inode;
- sock = (struct sol_socket_struct *)filp->private_data;
- SOLDD(("%p %p\n", sock->pfirst, sock->pfirst ? sock->pfirst->next : NULL));
- if ( ctl_maxlen > 0 && !sock->pfirst && SOCKET_I(ino)->type == SOCK_STREAM
- && sock->state == TS_IDLE) {
- SOLD("calling LISTEN");
- args[0] = fd;
- args[1] = -1;
- set_fs(KERNEL_DS);
- sys_socketcall(SYS_LISTEN, args);
- set_fs(old_fs);
- SOLD("LISTEN done");
- }
- if (!(filp->f_flags & O_NONBLOCK)) {
- struct poll_wqueues wait_table;
- poll_table *wait;
-
- poll_initwait(&wait_table);
- wait = &wait_table.pt;
- for(;;) {
- SOLD("loop");
- set_current_state(TASK_INTERRUPTIBLE);
- /* ! ( l<0 || ( l>=0 && ( ! pfirst || (flags == HIPRI && pri != HIPRI) ) ) ) */
- /* ( ! l<0 && ! ( l>=0 && ( ! pfirst || (flags == HIPRI && pri != HIPRI) ) ) ) */
- /* ( l>=0 && ( ! l>=0 || ! ( ! pfirst || (flags == HIPRI && pri != HIPRI) ) ) ) */
- /* ( l>=0 && ( l<0 || ( pfirst && ! (flags == HIPRI && pri != HIPRI) ) ) ) */
- /* ( l>=0 && ( l<0 || ( pfirst && (flags != HIPRI || pri == HIPRI) ) ) ) */
- /* ( l>=0 && ( pfirst && (flags != HIPRI || pri == HIPRI) ) ) */
- if (ctl_maxlen >= 0 && sock->pfirst && (*flags_p != MSG_HIPRI || sock->pfirst->pri == MSG_HIPRI))
- break;
- SOLD("cond 1 passed");
- if (
- #if 1
- *flags_p != MSG_HIPRI &&
- #endif
- ((filp->f_op->poll(filp, wait) & POLLIN) ||
- (filp->f_op->poll(filp, NULL) & POLLIN) ||
- signal_pending(current))
- ) {
- break;
- }
- if( *flags_p == MSG_HIPRI ) {
- SOLD("avoiding lockup");
- break ;
- }
- if(wait_table.error) {
- SOLD("wait-table error");
- poll_freewait(&wait_table);
- return wait_table.error;
- }
- SOLD("scheduling");
- schedule();
- }
- SOLD("loop done");
- current->state = TASK_RUNNING;
- poll_freewait(&wait_table);
- if (signal_pending(current)) {
- SOLD("signal pending");
- return -EINTR;
- }
- }
- if (ctl_maxlen >= 0 && sock->pfirst) {
- struct T_primsg *it = sock->pfirst;
- int l = min_t(int, ctl_maxlen, it->length);
- SCHECK_MAGIC((char*)((u64)(((char *)&it->type)+sock->offset+it->length+7)&~7),MKCTL_MAGIC);
- SOLD("purting ctl data");
- if(copy_to_user(ctl_buf,
- (char*)&it->type + sock->offset, l))
- return -EFAULT;
- SOLD("pur it");
- if(put_user(l, ctl_len))
- return -EFAULT;
- SOLD("set ctl_len");
- *flags_p = it->pri;
- it->length -= l;
- if (it->length) {
- SOLD("more ctl");
- sock->offset += l;
- return MORECTL;
- } else {
- SOLD("removing message");
- sock->pfirst = it->next;
- if (!sock->pfirst)
- sock->plast = NULL;
- SOLDD(("getmsg kfree %016lx->%016lx\n", it, sock->pfirst));
- mykfree(it);
- sock->offset = 0;
- SOLD("ctl done");
- return 0;
- }
- }
- *flags_p = 0;
- if (ctl_maxlen >= 0) {
- SOLD("ACCEPT perhaps?");
- if (SOCKET_I(ino)->type == SOCK_STREAM && sock->state == TS_IDLE) {
- struct T_conn_ind ind;
- char *buf = getpage();
- int len = BUF_SIZE;
-
- SOLD("trying ACCEPT");
- if (put_user(ctl_maxlen - sizeof(ind), ctl_len))
- return -EFAULT;
- args[0] = fd;
- args[1] = (long)buf;
- args[2] = (long)&len;
- oldflags = filp->f_flags;
- filp->f_flags |= O_NONBLOCK;
- SOLD("calling ACCEPT");
- set_fs(KERNEL_DS);
- error = sys_socketcall(SYS_ACCEPT, args);
- set_fs(old_fs);
- filp->f_flags = oldflags;
- if (error < 0) {
- SOLD("some error");
- putpage(buf);
- return error;
- }
- if (error) {
- SOLD("connect");
- putpage(buf);
- if (sizeof(ind) > ctl_maxlen) {
- SOLD("generating CONN_IND");
- ind.PRIM_type = T_CONN_IND;
- ind.SRC_length = len;
- ind.SRC_offset = sizeof(ind);
- ind.OPT_length = ind.OPT_offset = 0;
- ind.SEQ_number = error;
- if(copy_to_user(ctl_buf, &ind, sizeof(ind))||
- put_user(sizeof(ind)+ind.SRC_length,ctl_len))
- return -EFAULT;
- SOLD("CONN_IND created");
- }
- if (data_maxlen >= 0)
- put_user(0, data_len);
- SOLD("CONN_IND done");
- return 0;
- }
- if (len>ctl_maxlen) {
- SOLD("data don't fit");
- putpage(buf);
- return -EFAULT; /* XXX - is this ok ? */
- }
- if(copy_to_user(ctl_buf,buf,len) || put_user(len,ctl_len)){
- SOLD("can't copy data");
- putpage(buf);
- return -EFAULT;
- }
- SOLD("ACCEPT done");
- putpage(buf);
- }
- }
- SOLD("checking data req");
- if (data_maxlen <= 0) {
- if (data_maxlen == 0)
- put_user(0, data_len);
- if (ctl_maxlen >= 0)
- put_user(0, ctl_len);
- return -EAGAIN;
- }
- SOLD("wants data");
- if (ctl_maxlen > sizeof(udi) && sock->state == TS_IDLE) {
- SOLD("udi fits");
- tmpbuf = ctl_buf + sizeof(udi);
- tmplen = ctl_maxlen - sizeof(udi);
- } else {
- SOLD("udi does not fit");
- tmpbuf = NULL;
- tmplen = 0;
- }
- if (put_user(tmplen, ctl_len))
- return -EFAULT;
- SOLD("set ctl_len");
- oldflags = filp->f_flags;
- filp->f_flags |= O_NONBLOCK;
- SOLD("calling recvfrom");
- sys_recvfrom = (int (*)(int, void __user *, size_t, unsigned, struct sockaddr __user *, int __user *))SYS(recvfrom);
- error = sys_recvfrom(fd, data_buf, data_maxlen, 0, (struct sockaddr __user *)tmpbuf, ctl_len);
- filp->f_flags = oldflags;
- if (error < 0)
- return error;
- SOLD("error >= 0" ) ;
- if (error && ctl_maxlen > sizeof(udi) && sock->state == TS_IDLE) {
- SOLD("generating udi");
- udi.PRIM_type = T_UNITDATA_IND;
- if (get_user(udi.SRC_length, ctl_len))
- return -EFAULT;
- udi.SRC_offset = sizeof(udi);
- udi.OPT_length = udi.OPT_offset = 0;
- if (copy_to_user(ctl_buf, &udi, sizeof(udi)) ||
- put_user(sizeof(udi)+udi.SRC_length, ctl_len))
- return -EFAULT;
- SOLD("udi done");
- } else {
- if (put_user(0, ctl_len))
- return -EFAULT;
- }
- put_user(error, data_len);
- SOLD("done");
- return 0;
-}
-
-asmlinkage int solaris_getmsg(unsigned int fd, u32 arg1, u32 arg2, u32 arg3)
-{
- struct file *filp;
- struct inode *ino;
- struct strbuf __user *ctlptr;
- struct strbuf __user *datptr;
- struct strbuf ctl, dat;
- int __user *flgptr;
- int flags;
- int error = -EBADF;
- struct fdtable *fdt;
-
- SOLD("entry");
- lock_kernel();
- if (fd >= sysctl_nr_open)
- goto out;
-
- fdt = files_fdtable(current->files);
- filp = fdt->fd[fd];
- if(!filp) goto out;
-
- ino = filp->f_path.dentry->d_inode;
- if (!ino || !S_ISSOCK(ino->i_mode))
- goto out;
-
- ctlptr = (struct strbuf __user *)A(arg1);
- datptr = (struct strbuf __user *)A(arg2);
- flgptr = (int __user *)A(arg3);
-
- error = -EFAULT;
-
- if (ctlptr) {
- if (copy_from_user(&ctl,ctlptr,sizeof(struct strbuf)) ||
- put_user(-1,&ctlptr->len))
- goto out;
- } else
- ctl.maxlen = -1;
-
- if (datptr) {
- if (copy_from_user(&dat,datptr,sizeof(struct strbuf)) ||
- put_user(-1,&datptr->len))
- goto out;
- } else
- dat.maxlen = -1;
-
- if (get_user(flags,flgptr))
- goto out;
-
- switch (flags) {
- case 0:
- case MSG_HIPRI:
- case MSG_ANY:
- case MSG_BAND:
- break;
- default:
- error = -EINVAL;
- goto out;
- }
-
- error = timod_getmsg(fd,A(ctl.buf),ctl.maxlen,&ctlptr->len,
- A(dat.buf),dat.maxlen,&datptr->len,&flags);
-
- if (!error && put_user(flags,flgptr))
- error = -EFAULT;
-out:
- unlock_kernel();
- SOLD("done");
- return error;
-}
-
-asmlinkage int solaris_putmsg(unsigned int fd, u32 arg1, u32 arg2, u32 arg3)
-{
- struct file *filp;
- struct inode *ino;
- struct strbuf __user *ctlptr;
- struct strbuf __user *datptr;
- struct strbuf ctl, dat;
- int flags = (int) arg3;
- int error = -EBADF;
- struct fdtable *fdt;
-
- SOLD("entry");
- lock_kernel();
- if (fd >= sysctl_nr_open)
- goto out;
-
- fdt = files_fdtable(current->files);
- filp = fdt->fd[fd];
- if(!filp) goto out;
-
- ino = filp->f_path.dentry->d_inode;
- if (!ino) goto out;
-
- if (!S_ISSOCK(ino->i_mode) &&
- (imajor(ino) != 30 || iminor(ino) != 1))
- goto out;
-
- ctlptr = A(arg1);
- datptr = A(arg2);
-
- error = -EFAULT;
-
- if (ctlptr) {
- if (copy_from_user(&ctl,ctlptr,sizeof(ctl)))
- goto out;
- if (ctl.len < 0 && flags) {
- error = -EINVAL;
- goto out;
- }
- } else {
- ctl.len = 0;
- ctl.buf = 0;
- }
-
- if (datptr) {
- if (copy_from_user(&dat,datptr,sizeof(dat)))
- goto out;
- } else {
- dat.len = 0;
- dat.buf = 0;
- }
-
- error = timod_putmsg(fd,A(ctl.buf),ctl.len,
- A(dat.buf),dat.len,flags);
-out:
- unlock_kernel();
- SOLD("done");
- return error;
-}
#include <linux/file.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <asm/unistd.h>
/*
config HAVE_SETUP_PER_CPU_AREA
def_bool X86_64 || (X86_SMP && !X86_VOYAGER)
+config HAVE_CPUMASK_OF_CPU_MAP
+ def_bool X86_64_SMP
+
config ARCH_HIBERNATION_POSSIBLE
def_bool y
depends on !SMP || !X86_VOYAGER
help
Enable ACPI SRAT based node topology detection.
+# Some NUMA nodes have memory ranges that span
+# other nodes. Even though a pfn is valid and
+# between a node's start and end pfns, it may not
+# reside on that node. See memmap_init_zone()
+# for details.
+config NODES_SPAN_OTHER_NODES
+ def_bool y
+ depends on X86_64_ACPI_NUMA
+
config NUMA_EMU
bool "NUMA emulation"
depends on X86_64 && NUMA
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/a20.c
- *
* Enable A20 gate (return -1 on failure)
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/apm.c
- *
* Get APM BIOS information
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/bitops.h
- *
* Very simple bitops for the boot code.
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/boot.h
- *
* Header file for the real-mode kernel code
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/cmdline.c
- *
* Simple command-line parser for early boot.
*/
/*
* Setup the stack for the decompressor
*/
- leal stack_end(%ebx), %esp
+ leal boot_stack_end(%ebx), %esp
/*
* Do the decompression, and jump to the new kernel..
pushl %eax # input_len
leal input_data(%ebx), %eax
pushl %eax # input_data
- leal _end(%ebx), %eax
- pushl %eax # end of the image as third argument
+ leal boot_heap(%ebx), %eax
+ pushl %eax # heap area as third argument
pushl %esi # real mode pointer as second arg
call decompress_kernel
addl $20, %esp
jmp *%ebp
.bss
+/* Stack and heap for uncompression */
.balign 4
-stack:
- .fill 4096, 1, 0
-stack_end:
+boot_heap:
+ .fill BOOT_HEAP_SIZE, 1, 0
+boot_stack:
+ .fill BOOT_STACK_SIZE, 1, 0
+boot_stack_end:
#include <asm/segment.h>
#include <asm/pgtable.h>
#include <asm/page.h>
+#include <asm/boot.h>
#include <asm/msr.h>
#include <asm/asm-offsets.h>
subl $1b, %ebp
/* setup a stack and make sure cpu supports long mode. */
- movl $user_stack_end, %eax
+ movl $boot_stack_end, %eax
addl %ebp, %eax
movl %eax, %esp
/* Copy the compressed kernel to the end of our buffer
* where decompression in place becomes safe.
*/
- leaq _end(%rip), %r8
- leaq _end(%rbx), %r9
- movq $_end /* - $startup_32 */, %rcx
+ leaq _end_before_pgt(%rip), %r8
+ leaq _end_before_pgt(%rbx), %r9
+ movq $_end_before_pgt /* - $startup_32 */, %rcx
1: subq $8, %r8
subq $8, %r9
movq 0(%r8), %rax
*/
xorq %rax, %rax
leaq _edata(%rbx), %rdi
- leaq _end(%rbx), %rcx
+ leaq _end_before_pgt(%rbx), %rcx
subq %rdi, %rcx
cld
rep
stosb
/* Setup the stack */
- leaq user_stack_end(%rip), %rsp
+ leaq boot_stack_end(%rip), %rsp
/* zero EFLAGS after setting rsp */
pushq $0
*/
pushq %rsi # Save the real mode argument
movq %rsi, %rdi # real mode address
- leaq _heap(%rip), %rsi # _heap
+ leaq boot_heap(%rip), %rsi # malloc area for uncompression
leaq input_data(%rip), %rdx # input_data
movl input_len(%rip), %eax
movq %rax, %rcx # input_len
.quad 0x0080890000000000 /* TS descriptor */
.quad 0x0000000000000000 /* TS continued */
gdt_end:
- .bss
-/* Stack for uncompression */
- .balign 4
-user_stack:
- .fill 4096,4,0
-user_stack_end:
+
+.bss
+/* Stack and heap for uncompression */
+.balign 4
+boot_heap:
+ .fill BOOT_HEAP_SIZE, 1, 0
+boot_stack:
+ .fill BOOT_STACK_SIZE, 1, 0
+boot_stack_end:
static memptr free_mem_ptr;
static memptr free_mem_end_ptr;
-#ifdef CONFIG_X86_64
-#define HEAP_SIZE 0x7000
-#else
-#define HEAP_SIZE 0x4000
-#endif
-
static char *vidmem;
static int vidport;
static int lines, cols;
window = output; /* Output buffer (Normally at 1M) */
free_mem_ptr = heap; /* Heap */
- free_mem_end_ptr = heap + HEAP_SIZE;
+ free_mem_end_ptr = heap + BOOT_HEAP_SIZE;
inbuf = input_data; /* Input buffer */
insize = input_len;
inptr = 0;
*(.bss.*)
*(COMMON)
. = ALIGN(8);
- _end = . ;
+ _end_before_pgt = . ;
. = ALIGN(4096);
pgtable = . ;
. = . + 4096 * 6;
- _heap = .;
+ _ebss = .;
}
}
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/copy.S
- *
* Memory copy routines
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/cpucheck.c
- *
* Check for obligatory CPU features and abort if the features are not
* present. This code should be compilable as 16-, 32- or 64-bit
* code, so be very careful with types and inline assembly.
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/edd.c
- *
* Get EDD BIOS disk information
*/
#!/bin/sh
#
-# arch/i386/boot/install.sh
-#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/main.c
- *
* Main module for the real-mode kernel code
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/mca.c
- *
* Get the MCA system description table
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/memory.c
- *
* Memory detection code
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/pm.c
- *
* Prepare the machine for transition to protected mode.
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/pmjump.S
- *
* The actual transition into protected mode
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/printf.c
- *
* Oh, it's a waste of space, but oh-so-yummy for debugging. This
* version of printf() does not include 64-bit support. "Live with
* it."
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/string.c
- *
* Very basic string functions
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/tty.c
- *
* Very simple screen I/O
* XXX: Probably should add very simple serial I/O?
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/version.c
- *
* Kernel version string
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/video-bios.c
- *
* Standard video BIOS modes
*
* We have two options for this; silent and scanned.
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/video-vesa.c
- *
* VESA text modes
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/video-vga.c
- *
* Common all-VGA modes
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/video.c
- *
* Select video mode
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/video.h
- *
* Header file for the real-mode video probing code
*/
* ----------------------------------------------------------------------- */
/*
- * arch/i386/boot/voyager.c
- *
* Get the Voyager config information
*/
pop %ebx
mov %r0,(%ebp)
pop %ebp
- mov $1,%eax
ret
// AES (Rijndael) Decryption Subroutine
pop %ebx
mov %r0,(%ebp)
pop %ebp
- mov $1,%eax
ret
-
#include <asm/mman.h>
#include <asm/types.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <asm/atomic.h>
#include <asm/ia32.h>
#include <asm/vgtod.h>
obj-$(CONFIG_X86_32) += sys_i386_32.o i386_ksyms_32.o
obj-$(CONFIG_X86_64) += sys_x86_64.o x8664_ksyms_64.o
obj-$(CONFIG_X86_64) += syscall_64.o vsyscall_64.o setup64.o
-obj-y += pci-dma_$(BITS).o bootflag.o e820_$(BITS).o
-obj-y += quirks.o i8237.o topology.o kdebugfs.o
-obj-y += alternative.o i8253.o
-obj-$(CONFIG_X86_64) += pci-nommu_64.o bugs_64.o
+obj-y += bootflag.o e820_$(BITS).o
+obj-y += pci-dma.o quirks.o i8237.o topology.o kdebugfs.o
+obj-y += alternative.o i8253.o pci-nommu.o
+obj-$(CONFIG_X86_64) += bugs_64.o
obj-y += tsc_$(BITS).o io_delay.o rtc.o
obj-$(CONFIG_X86_TRAMPOLINE) += trampoline.o
+obj-y += process.o
obj-y += i387.o
obj-y += ptrace.o
obj-y += ds.o
/*
- * arch/i386/kernel/acpi/cstate.c
- *
* Copyright (C) 2005 Intel Corporation
* Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
* - Added _PDC for SMP C-states on Intel CPUs
/* Make sure we are running on right CPU */
saved_mask = current->cpus_allowed;
- retval = set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ retval = set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
if (retval)
return -1;
cx->address);
out:
- set_cpus_allowed(current, saved_mask);
+ set_cpus_allowed_ptr(current, &saved_mask);
return retval;
}
EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
/*
- * arch/i386/kernel/acpi/processor.c
- *
* Copyright (C) 2005 Intel Corporation
* Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
* - Added _PDC for platforms with Intel CPUs
#include <linux/module.h>
#include <linux/percpu.h>
#include <linux/bootmem.h>
-#include <asm/semaphore.h>
#include <asm/processor.h>
#include <asm/i387.h>
#include <asm/msr.h>
cpumask_t saved_mask = current->cpus_allowed;
cmd->val = 0;
- set_cpus_allowed(current, cmd->mask);
+ set_cpus_allowed_ptr(current, &cmd->mask);
do_drv_read(cmd);
- set_cpus_allowed(current, saved_mask);
+ set_cpus_allowed_ptr(current, &saved_mask);
}
static void drv_write(struct drv_cmd *cmd)
unsigned int i;
for_each_cpu_mask(i, cmd->mask) {
- set_cpus_allowed(current, cpumask_of_cpu(i));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(i));
do_drv_write(cmd);
}
- set_cpus_allowed(current, saved_mask);
+ set_cpus_allowed_ptr(current, &saved_mask);
return;
}
-static u32 get_cur_val(cpumask_t mask)
+static u32 get_cur_val(const cpumask_t *mask)
{
struct acpi_processor_performance *perf;
struct drv_cmd cmd;
- if (unlikely(cpus_empty(mask)))
+ if (unlikely(cpus_empty(*mask)))
return 0;
- switch (per_cpu(drv_data, first_cpu(mask))->cpu_feature) {
+ switch (per_cpu(drv_data, first_cpu(*mask))->cpu_feature) {
case SYSTEM_INTEL_MSR_CAPABLE:
cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
cmd.addr.msr.reg = MSR_IA32_PERF_STATUS;
break;
case SYSTEM_IO_CAPABLE:
cmd.type = SYSTEM_IO_CAPABLE;
- perf = per_cpu(drv_data, first_cpu(mask))->acpi_data;
+ perf = per_cpu(drv_data, first_cpu(*mask))->acpi_data;
cmd.addr.io.port = perf->control_register.address;
cmd.addr.io.bit_width = perf->control_register.bit_width;
break;
return 0;
}
- cmd.mask = mask;
+ cmd.mask = *mask;
drv_read(&cmd);
unsigned int retval;
saved_mask = current->cpus_allowed;
- set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
if (get_cpu() != cpu) {
/* We were not able to run on requested processor */
put_cpu();
retval = per_cpu(drv_data, cpu)->max_freq * perf_percent / 100;
put_cpu();
- set_cpus_allowed(current, saved_mask);
+ set_cpus_allowed_ptr(current, &saved_mask);
dprintk("cpu %d: performance percent %d\n", cpu, perf_percent);
return retval;
return 0;
}
- freq = extract_freq(get_cur_val(cpumask_of_cpu(cpu)), data);
+ freq = extract_freq(get_cur_val(&cpumask_of_cpu(cpu)), data);
dprintk("cur freq = %u\n", freq);
return freq;
}
-static unsigned int check_freqs(cpumask_t mask, unsigned int freq,
+static unsigned int check_freqs(const cpumask_t *mask, unsigned int freq,
struct acpi_cpufreq_data *data)
{
unsigned int cur_freq;
drv_write(&cmd);
if (acpi_pstate_strict) {
- if (!check_freqs(cmd.mask, freqs.new, data)) {
+ if (!check_freqs(&cmd.mask, freqs.new, data)) {
dprintk("acpi_cpufreq_target failed (%d)\n",
policy->cpu);
return -EAGAIN;
if (c->x86_vendor != X86_VENDOR_INTEL)
return -ENODEV;
- if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) ||
- !test_bit(X86_FEATURE_ACC, c->x86_capability))
+ if (!test_cpu_cap(c, X86_FEATURE_ACPI) ||
+ !test_cpu_cap(c, X86_FEATURE_ACC))
return -ENODEV;
ret = cpufreq_register_driver(&p4clockmod_driver);
static int check_supported_cpu(unsigned int cpu)
{
- cpumask_t oldmask = CPU_MASK_ALL;
+ cpumask_t oldmask;
u32 eax, ebx, ecx, edx;
unsigned int rc = 0;
oldmask = current->cpus_allowed;
- set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
if (smp_processor_id() != cpu) {
printk(KERN_ERR PFX "limiting to cpu %u failed\n", cpu);
rc = 1;
out:
- set_cpus_allowed(current, oldmask);
+ set_cpus_allowed_ptr(current, &oldmask);
return rc;
}
/* Driver entry point to switch to the target frequency */
static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsigned relation)
{
- cpumask_t oldmask = CPU_MASK_ALL;
+ cpumask_t oldmask;
struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu);
u32 checkfid;
u32 checkvid;
/* only run on specific CPU from here on */
oldmask = current->cpus_allowed;
- set_cpus_allowed(current, cpumask_of_cpu(pol->cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu));
if (smp_processor_id() != pol->cpu) {
printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu);
ret = 0;
err_out:
- set_cpus_allowed(current, oldmask);
+ set_cpus_allowed_ptr(current, &oldmask);
return ret;
}
static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
{
struct powernow_k8_data *data;
- cpumask_t oldmask = CPU_MASK_ALL;
+ cpumask_t oldmask;
int rc;
if (!cpu_online(pol->cpu))
/* only run on specific CPU from here on */
oldmask = current->cpus_allowed;
- set_cpus_allowed(current, cpumask_of_cpu(pol->cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu));
if (smp_processor_id() != pol->cpu) {
printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu);
fidvid_msr_init();
/* run on any CPU again */
- set_cpus_allowed(current, oldmask);
+ set_cpus_allowed_ptr(current, &oldmask);
if (cpu_family == CPU_HW_PSTATE)
pol->cpus = cpumask_of_cpu(pol->cpu);
return 0;
err_out:
- set_cpus_allowed(current, oldmask);
+ set_cpus_allowed_ptr(current, &oldmask);
powernow_k8_cpu_exit_acpi(data);
kfree(data);
if (!data)
return -EINVAL;
- set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
if (smp_processor_id() != cpu) {
- printk(KERN_ERR PFX "limiting to CPU %d failed in powernowk8_get\n", cpu);
- set_cpus_allowed(current, oldmask);
+ printk(KERN_ERR PFX
+ "limiting to CPU %d failed in powernowk8_get\n", cpu);
+ set_cpus_allowed_ptr(current, &oldmask);
return 0;
}
goto out;
if (cpu_family == CPU_HW_PSTATE)
- khz = find_khz_freq_from_pstate(data->powernow_table, data->currpstate);
+ khz = find_khz_freq_from_pstate(data->powernow_table,
+ data->currpstate);
else
khz = find_khz_freq_from_fid(data->currfid);
out:
- set_cpus_allowed(current, oldmask);
+ set_cpus_allowed_ptr(current, &oldmask);
return khz;
}
cpumask_t saved_mask;
saved_mask = current->cpus_allowed;
- set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
if (smp_processor_id() != cpu)
return 0;
clock_freq = extract_clock(l, cpu, 1);
}
- set_cpus_allowed(current, saved_mask);
+ set_cpus_allowed_ptr(current, &saved_mask);
return clock_freq;
}
else
cpu_set(j, set_mask);
- set_cpus_allowed(current, set_mask);
+ set_cpus_allowed_ptr(current, &set_mask);
preempt_disable();
if (unlikely(!cpu_isset(smp_processor_id(), set_mask))) {
dprintk("couldn't limit to CPUs in this domain\n");
if (!cpus_empty(covered_cpus)) {
for_each_cpu_mask(j, covered_cpus) {
- set_cpus_allowed(current, cpumask_of_cpu(j));
+ set_cpus_allowed_ptr(current,
+ &cpumask_of_cpu(j));
wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
}
}
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
}
}
- set_cpus_allowed(current, saved_mask);
+ set_cpus_allowed_ptr(current, &saved_mask);
return 0;
migrate_end:
preempt_enable();
- set_cpus_allowed(current, saved_mask);
+ set_cpus_allowed_ptr(current, &saved_mask);
return 0;
}
return 0;
}
-static unsigned int _speedstep_get(cpumask_t cpus)
+static unsigned int _speedstep_get(const cpumask_t *cpus)
{
unsigned int speed;
cpumask_t cpus_allowed;
cpus_allowed = current->cpus_allowed;
- set_cpus_allowed(current, cpus);
+ set_cpus_allowed_ptr(current, cpus);
speed = speedstep_get_processor_frequency(speedstep_processor);
- set_cpus_allowed(current, cpus_allowed);
+ set_cpus_allowed_ptr(current, &cpus_allowed);
dprintk("detected %u kHz as current frequency\n", speed);
return speed;
}
static unsigned int speedstep_get(unsigned int cpu)
{
- return _speedstep_get(cpumask_of_cpu(cpu));
+ return _speedstep_get(&cpumask_of_cpu(cpu));
}
/**
if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0], target_freq, relation, &newstate))
return -EINVAL;
- freqs.old = _speedstep_get(policy->cpus);
+ freqs.old = _speedstep_get(&policy->cpus);
freqs.new = speedstep_freqs[newstate].frequency;
freqs.cpu = policy->cpu;
}
/* switch to physical CPU where state is to be changed */
- set_cpus_allowed(current, policy->cpus);
+ set_cpus_allowed_ptr(current, &policy->cpus);
speedstep_set_state(newstate);
/* allow to be run on all CPUs */
- set_cpus_allowed(current, cpus_allowed);
+ set_cpus_allowed_ptr(current, &cpus_allowed);
for_each_cpu_mask(i, policy->cpus) {
freqs.cpu = i;
#endif
cpus_allowed = current->cpus_allowed;
- set_cpus_allowed(current, policy->cpus);
+ set_cpus_allowed_ptr(current, &policy->cpus);
/* detect low and high frequency and transition latency */
result = speedstep_get_freqs(speedstep_processor,
&speedstep_freqs[SPEEDSTEP_HIGH].frequency,
&policy->cpuinfo.transition_latency,
&speedstep_set_state);
- set_cpus_allowed(current, cpus_allowed);
+ set_cpus_allowed_ptr(current, &cpus_allowed);
if (result)
return result;
/* get current speed setting */
- speed = _speedstep_get(policy->cpus);
+ speed = _speedstep_get(&policy->cpus);
if (!speed)
return -EIO;
union _cpuid4_leaf_ebx ebx;
union _cpuid4_leaf_ecx ecx;
unsigned long size;
- cpumask_t shared_cpu_map;
+ cpumask_t shared_cpu_map; /* future?: only cpus/node is needed */
};
unsigned short num_cache_leaves;
}
/* pointer to _cpuid4_info array (for each cache leaf) */
-static struct _cpuid4_info *cpuid4_info[NR_CPUS];
-#define CPUID4_INFO_IDX(x,y) (&((cpuid4_info[x])[y]))
+static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info);
+#define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y]))
#ifdef CONFIG_SMP
static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
if (cpu_data(i).apicid >> index_msb ==
c->apicid >> index_msb) {
cpu_set(i, this_leaf->shared_cpu_map);
- if (i != cpu && cpuid4_info[i]) {
+ if (i != cpu && per_cpu(cpuid4_info, i)) {
sibling_leaf = CPUID4_INFO_IDX(i, index);
cpu_set(cpu, sibling_leaf->shared_cpu_map);
}
for (i = 0; i < num_cache_leaves; i++)
cache_remove_shared_cpu_map(cpu, i);
- kfree(cpuid4_info[cpu]);
- cpuid4_info[cpu] = NULL;
+ kfree(per_cpu(cpuid4_info, cpu));
+ per_cpu(cpuid4_info, cpu) = NULL;
}
static int __cpuinit detect_cache_attributes(unsigned int cpu)
if (num_cache_leaves == 0)
return -ENOENT;
- cpuid4_info[cpu] = kzalloc(
+ per_cpu(cpuid4_info, cpu) = kzalloc(
sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
- if (cpuid4_info[cpu] == NULL)
+ if (per_cpu(cpuid4_info, cpu) == NULL)
return -ENOMEM;
oldmask = current->cpus_allowed;
- retval = set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ retval = set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
if (retval)
goto out;
}
cache_shared_cpu_map_setup(cpu, j);
}
- set_cpus_allowed(current, oldmask);
+ set_cpus_allowed_ptr(current, &oldmask);
out:
if (retval) {
- kfree(cpuid4_info[cpu]);
- cpuid4_info[cpu] = NULL;
+ kfree(per_cpu(cpuid4_info, cpu));
+ per_cpu(cpuid4_info, cpu) = NULL;
}
return retval;
extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
/* pointer to kobject for cpuX/cache */
-static struct kobject * cache_kobject[NR_CPUS];
+static DEFINE_PER_CPU(struct kobject *, cache_kobject);
struct _index_kobject {
struct kobject kobj;
};
/* pointer to array of kobjects for cpuX/cache/indexY */
-static struct _index_kobject *index_kobject[NR_CPUS];
-#define INDEX_KOBJECT_PTR(x,y) (&((index_kobject[x])[y]))
+static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
+#define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(index_kobject, x))[y]))
#define show_one_plus(file_name, object, val) \
static ssize_t show_##file_name \
return sprintf (buf, "%luK\n", this_leaf->size / 1024);
}
-static ssize_t show_shared_cpu_map(struct _cpuid4_info *this_leaf, char *buf)
+static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
+ int type, char *buf)
{
- char mask_str[NR_CPUS];
- cpumask_scnprintf(mask_str, NR_CPUS, this_leaf->shared_cpu_map);
- return sprintf(buf, "%s\n", mask_str);
+ ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
+ int n = 0;
+
+ if (len > 1) {
+ cpumask_t *mask = &this_leaf->shared_cpu_map;
+
+ n = type?
+ cpulist_scnprintf(buf, len-2, *mask):
+ cpumask_scnprintf(buf, len-2, *mask);
+ buf[n++] = '\n';
+ buf[n] = '\0';
+ }
+ return n;
+}
+
+static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
+{
+ return show_shared_cpu_map_func(leaf, 0, buf);
+}
+
+static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
+{
+ return show_shared_cpu_map_func(leaf, 1, buf);
}
static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) {
define_one_ro(number_of_sets);
define_one_ro(size);
define_one_ro(shared_cpu_map);
+define_one_ro(shared_cpu_list);
static struct attribute * default_attrs[] = {
&type.attr,
&number_of_sets.attr,
&size.attr,
&shared_cpu_map.attr,
+ &shared_cpu_list.attr,
NULL
};
static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
{
- kfree(cache_kobject[cpu]);
- kfree(index_kobject[cpu]);
- cache_kobject[cpu] = NULL;
- index_kobject[cpu] = NULL;
+ kfree(per_cpu(cache_kobject, cpu));
+ kfree(per_cpu(index_kobject, cpu));
+ per_cpu(cache_kobject, cpu) = NULL;
+ per_cpu(index_kobject, cpu) = NULL;
free_cache_attributes(cpu);
}
return err;
/* Allocate all required memory */
- cache_kobject[cpu] = kzalloc(sizeof(struct kobject), GFP_KERNEL);
- if (unlikely(cache_kobject[cpu] == NULL))
+ per_cpu(cache_kobject, cpu) =
+ kzalloc(sizeof(struct kobject), GFP_KERNEL);
+ if (unlikely(per_cpu(cache_kobject, cpu) == NULL))
goto err_out;
- index_kobject[cpu] = kzalloc(
+ per_cpu(index_kobject, cpu) = kzalloc(
sizeof(struct _index_kobject ) * num_cache_leaves, GFP_KERNEL);
- if (unlikely(index_kobject[cpu] == NULL))
+ if (unlikely(per_cpu(index_kobject, cpu) == NULL))
goto err_out;
return 0;
if (unlikely(retval < 0))
return retval;
- retval = kobject_init_and_add(cache_kobject[cpu], &ktype_percpu_entry,
+ retval = kobject_init_and_add(per_cpu(cache_kobject, cpu),
+ &ktype_percpu_entry,
&sys_dev->kobj, "%s", "cache");
if (retval < 0) {
cpuid4_cache_sysfs_exit(cpu);
this_object->cpu = cpu;
this_object->index = i;
retval = kobject_init_and_add(&(this_object->kobj),
- &ktype_cache, cache_kobject[cpu],
+ &ktype_cache,
+ per_cpu(cache_kobject, cpu),
"index%1lu", i);
if (unlikely(retval)) {
for (j = 0; j < i; j++) {
kobject_put(&(INDEX_KOBJECT_PTR(cpu,j)->kobj));
}
- kobject_put(cache_kobject[cpu]);
+ kobject_put(per_cpu(cache_kobject, cpu));
cpuid4_cache_sysfs_exit(cpu);
break;
}
if (!retval)
cpu_set(cpu, cache_dev_map);
- kobject_uevent(cache_kobject[cpu], KOBJ_ADD);
+ kobject_uevent(per_cpu(cache_kobject, cpu), KOBJ_ADD);
return retval;
}
unsigned int cpu = sys_dev->id;
unsigned long i;
- if (cpuid4_info[cpu] == NULL)
+ if (per_cpu(cpuid4_info, cpu) == NULL)
return;
if (!cpu_isset(cpu, cache_dev_map))
return;
for (i = 0; i < num_cache_leaves; i++)
kobject_put(&(INDEX_KOBJECT_PTR(cpu,i)->kobj));
- kobject_put(cache_kobject[cpu]);
+ kobject_put(per_cpu(cache_kobject, cpu));
cpuid4_cache_sysfs_exit(cpu);
}
ssize_t(*store) (struct threshold_block *, const char *, size_t count);
};
-static cpumask_t affinity_set(unsigned int cpu)
+static void affinity_set(unsigned int cpu, cpumask_t *oldmask,
+ cpumask_t *newmask)
{
- cpumask_t oldmask = current->cpus_allowed;
- cpumask_t newmask = CPU_MASK_NONE;
- cpu_set(cpu, newmask);
- set_cpus_allowed(current, newmask);
- return oldmask;
+ *oldmask = current->cpus_allowed;
+ cpus_clear(*newmask);
+ cpu_set(cpu, *newmask);
+ set_cpus_allowed_ptr(current, newmask);
}
-static void affinity_restore(cpumask_t oldmask)
+static void affinity_restore(const cpumask_t *oldmask)
{
- set_cpus_allowed(current, oldmask);
+ set_cpus_allowed_ptr(current, oldmask);
}
#define SHOW_FIELDS(name) \
const char *buf, size_t count)
{
char *end;
- cpumask_t oldmask;
+ cpumask_t oldmask, newmask;
unsigned long new = simple_strtoul(buf, &end, 0);
if (end == buf)
return -EINVAL;
b->interrupt_enable = !!new;
- oldmask = affinity_set(b->cpu);
+ affinity_set(b->cpu, &oldmask, &newmask);
threshold_restart_bank(b, 0, 0);
- affinity_restore(oldmask);
+ affinity_restore(&oldmask);
return end - buf;
}
const char *buf, size_t count)
{
char *end;
- cpumask_t oldmask;
+ cpumask_t oldmask, newmask;
u16 old;
unsigned long new = simple_strtoul(buf, &end, 0);
if (end == buf)
old = b->threshold_limit;
b->threshold_limit = new;
- oldmask = affinity_set(b->cpu);
+ affinity_set(b->cpu, &oldmask, &newmask);
threshold_restart_bank(b, 0, old);
- affinity_restore(oldmask);
+ affinity_restore(&oldmask);
return end - buf;
}
static ssize_t show_error_count(struct threshold_block *b, char *buf)
{
u32 high, low;
- cpumask_t oldmask;
- oldmask = affinity_set(b->cpu);
+ cpumask_t oldmask, newmask;
+ affinity_set(b->cpu, &oldmask, &newmask);
rdmsr(b->address, low, high);
- affinity_restore(oldmask);
+ affinity_restore(&oldmask);
return sprintf(buf, "%x\n",
(high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit));
}
static ssize_t store_error_count(struct threshold_block *b,
const char *buf, size_t count)
{
- cpumask_t oldmask;
- oldmask = affinity_set(b->cpu);
+ cpumask_t oldmask, newmask;
+ affinity_set(b->cpu, &oldmask, &newmask);
threshold_restart_bank(b, 1, 0);
- affinity_restore(oldmask);
+ affinity_restore(&oldmask);
return 1;
}
{
int i, err = 0;
struct threshold_bank *b = NULL;
- cpumask_t oldmask = CPU_MASK_NONE;
+ cpumask_t oldmask, newmask;
char name[32];
sprintf(name, "threshold_bank%i", bank);
per_cpu(threshold_banks, cpu)[bank] = b;
- oldmask = affinity_set(cpu);
+ affinity_set(cpu, &oldmask, &newmask);
err = allocate_threshold_blocks(cpu, bank, 0,
MSR_IA32_MC0_MISC + bank * 4);
- affinity_restore(oldmask);
+ affinity_restore(&oldmask);
if (err)
goto out_free;
/*
- * linux/arch/i386/kernel/cpu/mcheck/therm_throt.c
*
* Thermal throttle event support code (such as syslog messaging and rate
* limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
#include <linux/smp.h>
#include <linux/timex.h>
#include <linux/string.h>
-#include <asm/semaphore.h>
#include <linux/seq_file.h>
#include <linux/cpufreq.h>
err = cpuid_device_create(cpu);
break;
case CPU_UP_CANCELED:
+ case CPU_UP_CANCELED_FROZEN:
case CPU_DEAD:
cpuid_device_destroy(cpu);
break;
- case CPU_UP_CANCELED_FROZEN:
- destroy_suspended_device(cpuid_class, MKDEV(CPUID_MAJOR, cpu));
- break;
}
return err ? NOTIFY_BAD : NOTIFY_OK;
}
/*
* Find the highest page frame number we have available
*/
-void __init find_max_pfn(void)
+void __init propagate_e820_map(void)
{
int i;
* size before original memory map is
* reset.
*/
- find_max_pfn();
+ propagate_e820_map();
saved_max_pfn = max_pfn;
#endif
e820.nr_map = 0;
}
/* Check for already reserved areas */
-static inline int
+static inline int __init
bad_addr(unsigned long *addrp, unsigned long size, unsigned long align)
{
int i;
}
/* Check for already reserved areas */
-static inline int
+static inline int __init
bad_addr_size(unsigned long *addrp, unsigned long *sizep, unsigned long align)
{
int i;
{
efi_memory_desc_t *md;
void *p;
+ u64 addr, npages;
/* Make EFI runtime service code area executable */
for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
if (md->type != EFI_RUNTIME_SERVICES_CODE)
continue;
- set_memory_x(md->virt_addr, md->num_pages);
+ addr = md->virt_addr;
+ npages = md->num_pages;
+ memrange_efi_to_native(&addr, &npages);
+ set_memory_x(addr, npages);
}
}
efi_memory_desc_t *md;
efi_status_t status;
unsigned long size;
- u64 end, systab;
+ u64 end, systab, addr, npages;
void *p, *va;
efi.systab = NULL;
size = md->num_pages << EFI_PAGE_SHIFT;
end = md->phys_addr + size;
- if ((end >> PAGE_SHIFT) <= max_pfn_mapped)
+ if (PFN_UP(end) <= max_pfn_mapped)
va = __va(md->phys_addr);
else
va = efi_ioremap(md->phys_addr, size);
continue;
}
- if (!(md->attribute & EFI_MEMORY_WB))
- set_memory_uc(md->virt_addr, md->num_pages);
+ if (!(md->attribute & EFI_MEMORY_WB)) {
+ addr = md->virt_addr;
+ npages = md->num_pages;
+ memrange_efi_to_native(&addr, &npages);
+ set_memory_uc(addr, npages);
+ }
systab = (u64) (unsigned long) efi_phys.systab;
if (md->phys_addr <= systab && systab < end) {
void __iomem * __init efi_ioremap(unsigned long phys_addr, unsigned long size)
{
- static unsigned pages_mapped;
+ static unsigned pages_mapped __initdata;
unsigned i, pages;
+ unsigned long offset;
- /* phys_addr and size must be page aligned */
- if ((phys_addr & ~PAGE_MASK) || (size & ~PAGE_MASK))
- return NULL;
+ pages = PFN_UP(phys_addr + size) - PFN_DOWN(phys_addr);
+ offset = phys_addr & ~PAGE_MASK;
+ phys_addr &= PAGE_MASK;
- pages = size >> PAGE_SHIFT;
if (pages_mapped + pages > MAX_EFI_IO_PAGES)
return NULL;
}
return (void __iomem *)__fix_to_virt(FIX_EFI_IO_MAP_FIRST_PAGE - \
- (pages_mapped - pages));
+ (pages_mapped - pages)) + offset;
}
/*
- * linux/arch/i386/entry.S
*
* Copyright (C) 1991, 1992 Linus Torvalds
*/
val = (1UL << UVH_IPI_INT_SEND_SHFT) |
(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
- (6 << UVH_IPI_INT_DELIVERY_MODE_SHFT);
+ APIC_DM_INIT;
+ uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
+ mdelay(10);
+
+ val = (1UL << UVH_IPI_INT_SEND_SHFT) |
+ (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
+ (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
+ APIC_DM_STARTUP;
uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
return 0;
}
static void uv_send_IPI_one(int cpu, int vector)
{
- unsigned long val, apicid;
+ unsigned long val, apicid, lapicid;
int nasid;
apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
+ lapicid = apicid & 0x3f; /* ZZZ macro needed */
nasid = uv_apicid_to_nasid(apicid);
val =
- (1UL << UVH_IPI_INT_SEND_SHFT) | (apicid <<
+ (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
UVH_IPI_INT_APIC_ID_SHFT) |
(vector << UVH_IPI_INT_VECTOR_SHFT);
uv_write_global_mmr64(nasid, UVH_IPI_INT, val);
- printk(KERN_DEBUG
- "UV: IPI to cpu %d, apicid 0x%lx, vec %d, nasid%d, val 0x%lx\n",
- cpu, apicid, vector, nasid, val);
}
static void uv_send_IPI_mask(cpumask_t mask, int vector)
reserve_early(__pa_symbol(&_text), __pa_symbol(&_end), "TEXT DATA BSS");
+#ifdef CONFIG_BLK_DEV_INITRD
/* Reserve INITRD */
if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
reserve_early(ramdisk_image, ramdisk_end, "RAMDISK");
}
+#endif
reserve_ebda_region();
/*
- * linux/arch/i386/kernel/head.S -- the 32-bit startup code.
*
* Copyright (C) 1991, 1992 Linus Torvalds
*
#endif
static unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu;
+unsigned int xstate_size;
+static struct i387_fxsave_struct fx_scratch __cpuinitdata;
-void mxcsr_feature_mask_init(void)
+void __cpuinit mxcsr_feature_mask_init(void)
{
unsigned long mask = 0;
clts();
if (cpu_has_fxsr) {
- memset(¤t->thread.i387.fxsave, 0,
- sizeof(struct i387_fxsave_struct));
- asm volatile("fxsave %0" : : "m" (current->thread.i387.fxsave));
- mask = current->thread.i387.fxsave.mxcsr_mask;
+ memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct));
+ asm volatile("fxsave %0" : : "m" (fx_scratch));
+ mask = fx_scratch.mxcsr_mask;
if (mask == 0)
mask = 0x0000ffbf;
}
stts();
}
+void __init init_thread_xstate(void)
+{
+ if (cpu_has_fxsr)
+ xstate_size = sizeof(struct i387_fxsave_struct);
+#ifdef CONFIG_X86_32
+ else
+ xstate_size = sizeof(struct i387_fsave_struct);
+#endif
+}
+
#ifdef CONFIG_X86_64
/*
* Called at bootup to set up the initial FPU state that is later cloned
void __cpuinit fpu_init(void)
{
unsigned long oldcr0 = read_cr0();
- extern void __bad_fxsave_alignment(void);
-
- if (offsetof(struct task_struct, thread.i387.fxsave) & 15)
- __bad_fxsave_alignment();
set_in_cr4(X86_CR4_OSFXSR);
set_in_cr4(X86_CR4_OSXMMEXCPT);
* value at reset if we support XMM instructions and then
* remeber the current task has used the FPU.
*/
-void init_fpu(struct task_struct *tsk)
+int init_fpu(struct task_struct *tsk)
{
if (tsk_used_math(tsk)) {
if (tsk == current)
unlazy_fpu(tsk);
- return;
+ return 0;
+ }
+
+ /*
+ * Memory allocation at the first usage of the FPU and other state.
+ */
+ if (!tsk->thread.xstate) {
+ tsk->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
+ GFP_KERNEL);
+ if (!tsk->thread.xstate)
+ return -ENOMEM;
}
if (cpu_has_fxsr) {
- memset(&tsk->thread.i387.fxsave, 0,
- sizeof(struct i387_fxsave_struct));
- tsk->thread.i387.fxsave.cwd = 0x37f;
+ struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
+
+ memset(fx, 0, xstate_size);
+ fx->cwd = 0x37f;
if (cpu_has_xmm)
- tsk->thread.i387.fxsave.mxcsr = MXCSR_DEFAULT;
+ fx->mxcsr = MXCSR_DEFAULT;
} else {
- memset(&tsk->thread.i387.fsave, 0,
- sizeof(struct i387_fsave_struct));
- tsk->thread.i387.fsave.cwd = 0xffff037fu;
- tsk->thread.i387.fsave.swd = 0xffff0000u;
- tsk->thread.i387.fsave.twd = 0xffffffffu;
- tsk->thread.i387.fsave.fos = 0xffff0000u;
+ struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave;
+ memset(fp, 0, xstate_size);
+ fp->cwd = 0xffff037fu;
+ fp->swd = 0xffff0000u;
+ fp->twd = 0xffffffffu;
+ fp->fos = 0xffff0000u;
}
/*
* Only the device not available exception or ptrace can call init_fpu.
*/
set_stopped_child_used_math(tsk);
+ return 0;
}
int fpregs_active(struct task_struct *target, const struct user_regset *regset)
unsigned int pos, unsigned int count,
void *kbuf, void __user *ubuf)
{
+ int ret;
+
if (!cpu_has_fxsr)
return -ENODEV;
- init_fpu(target);
+ ret = init_fpu(target);
+ if (ret)
+ return ret;
return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &target->thread.i387.fxsave, 0, -1);
+ &target->thread.xstate->fxsave, 0, -1);
}
int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
if (!cpu_has_fxsr)
return -ENODEV;
- init_fpu(target);
+ ret = init_fpu(target);
+ if (ret)
+ return ret;
+
set_stopped_child_used_math(target);
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &target->thread.i387.fxsave, 0, -1);
+ &target->thread.xstate->fxsave, 0, -1);
/*
* mxcsr reserved bits must be masked to zero for security reasons.
*/
- target->thread.i387.fxsave.mxcsr &= mxcsr_feature_mask;
+ target->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask;
return ret;
}
static void
convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
{
- struct i387_fxsave_struct *fxsave = &tsk->thread.i387.fxsave;
+ struct i387_fxsave_struct *fxsave = &tsk->thread.xstate->fxsave;
struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
int i;
const struct user_i387_ia32_struct *env)
{
- struct i387_fxsave_struct *fxsave = &tsk->thread.i387.fxsave;
+ struct i387_fxsave_struct *fxsave = &tsk->thread.xstate->fxsave;
struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
int i;
void *kbuf, void __user *ubuf)
{
struct user_i387_ia32_struct env;
+ int ret;
if (!HAVE_HWFP)
return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
- init_fpu(target);
+ ret = init_fpu(target);
+ if (ret)
+ return ret;
if (!cpu_has_fxsr) {
return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &target->thread.i387.fsave, 0, -1);
+ &target->thread.xstate->fsave, 0,
+ -1);
}
if (kbuf && pos == 0 && count == sizeof(env)) {
if (!HAVE_HWFP)
return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
- init_fpu(target);
+ ret = init_fpu(target);
+ if (ret)
+ return ret;
+
set_stopped_child_used_math(target);
if (!cpu_has_fxsr) {
return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &target->thread.i387.fsave, 0, -1);
+ &target->thread.xstate->fsave, 0, -1);
}
if (pos > 0 || count < sizeof(env))
static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf)
{
struct task_struct *tsk = current;
+ struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave;
unlazy_fpu(tsk);
- tsk->thread.i387.fsave.status = tsk->thread.i387.fsave.swd;
- if (__copy_to_user(buf, &tsk->thread.i387.fsave,
- sizeof(struct i387_fsave_struct)))
+ fp->status = fp->swd;
+ if (__copy_to_user(buf, fp, sizeof(struct i387_fsave_struct)))
return -1;
return 1;
}
static int save_i387_fxsave(struct _fpstate_ia32 __user *buf)
{
struct task_struct *tsk = current;
+ struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
struct user_i387_ia32_struct env;
int err = 0;
if (__copy_to_user(buf, &env, sizeof(env)))
return -1;
- err |= __put_user(tsk->thread.i387.fxsave.swd, &buf->status);
+ err |= __put_user(fx->swd, &buf->status);
err |= __put_user(X86_FXSR_MAGIC, &buf->magic);
if (err)
return -1;
- if (__copy_to_user(&buf->_fxsr_env[0], &tsk->thread.i387.fxsave,
+ if (__copy_to_user(&buf->_fxsr_env[0], fx,
sizeof(struct i387_fxsave_struct)))
return -1;
return 1;
struct task_struct *tsk = current;
clear_fpu(tsk);
- return __copy_from_user(&tsk->thread.i387.fsave, buf,
+ return __copy_from_user(&tsk->thread.xstate->fsave, buf,
sizeof(struct i387_fsave_struct));
}
int err;
clear_fpu(tsk);
- err = __copy_from_user(&tsk->thread.i387.fxsave, &buf->_fxsr_env[0],
+ err = __copy_from_user(&tsk->thread.xstate->fxsave, &buf->_fxsr_env[0],
sizeof(struct i387_fxsave_struct));
/* mxcsr reserved bits must be masked to zero for security reasons */
- tsk->thread.i387.fxsave.mxcsr &= mxcsr_feature_mask;
+ tsk->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask;
if (err || __copy_from_user(&env, buf, sizeof(env)))
return 1;
convert_to_fxsr(tsk, &env);
per_cpu(vector_irq, cpu)[vector] = -1;
cfg->vector = 0;
- cfg->domain = CPU_MASK_NONE;
+ cpus_clear(cfg->domain);
}
void __setup_vector_irq(int cpu)
#include <asm/apicdef.h>
#include <asm/system.h>
-#ifdef CONFIG_X86_32
-# include <mach_ipi.h>
-#else
-# include <asm/mach_apic.h>
-#endif
+#include <mach_ipi.h>
/*
* Put the error code here just in case the user cares:
if (!uci->valid)
continue;
- set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
error = get_maching_microcode(new_mc, cpu);
if (error < 0)
goto out;
vfree(new_mc);
if (cursor < 0)
error = cursor;
- set_cpus_allowed(current, old);
+ set_cpus_allowed_ptr(current, &old);
return error;
}
return 0;
old = current->cpus_allowed;
- set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
/* Check if the microcode we have in memory matches the CPU */
if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
" sig=0x%x, pf=0x%x, rev=0x%x\n",
cpu, uci->sig, uci->pf, uci->rev);
- set_cpus_allowed(current, old);
+ set_cpus_allowed_ptr(current, &old);
return err;
}
old = current->cpus_allowed;
- set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
mutex_lock(µcode_mutex);
collect_cpu_info(cpu);
if (uci->valid && system_state == SYSTEM_RUNNING && !resume)
cpu_request_microcode(cpu);
mutex_unlock(µcode_mutex);
- set_cpus_allowed(current, old);
+ set_cpus_allowed_ptr(current, &old);
}
static void microcode_fini_cpu(int cpu)
old = current->cpus_allowed;
get_online_cpus();
- set_cpus_allowed(current, cpumask_of_cpu(cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
mutex_lock(µcode_mutex);
if (uci->valid)
err = cpu_request_microcode(cpu);
mutex_unlock(µcode_mutex);
put_online_cpus();
- set_cpus_allowed(current, old);
+ set_cpus_allowed_ptr(current, &old);
}
if (err)
return err;
err = msr_device_create(cpu);
break;
case CPU_UP_CANCELED:
+ case CPU_UP_CANCELED_FROZEN:
case CPU_DEAD:
msr_device_destroy(cpu);
break;
- case CPU_UP_CANCELED_FROZEN:
- destroy_suspended_device(msr_class, MKDEV(MSR_MAJOR, cpu));
- break;
}
return err ? NOTIFY_BAD : NOTIFY_OK;
}
extern void die_nmi(struct pt_regs *, const char *msg);
-__kprobes int nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
+notrace __kprobes int
+nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
{
/*
}
EXPORT_SYMBOL(touch_nmi_watchdog);
-int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
+notrace __kprobes int
+nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
{
int sum;
int touched = 0;
static unsigned ignore_nmis;
-asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
+asmlinkage notrace __kprobes void
+do_nmi(struct pt_regs *regs, long error_code)
{
nmi_enter();
add_pda(__nmi_count,1);
return 0;
}
-static dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
+static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr,
size_t size, int direction)
{
dma_addr_t dma_handle = bad_dma_address;
+ void *vaddr = phys_to_virt(paddr);
unsigned long uaddr;
unsigned int npages;
struct iommu_table *tbl = find_iommu_table(dev);
error:
do {
- dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
- PCI_ANY_ID, dev);
+ dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
if (!dev)
break;
if (!is_cal_pci_dev(dev->device))
-/*
- * Dynamic DMA mapping support.
- */
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/string.h>
-#include <linux/pci.h>
-#include <linux/module.h>
+#include <linux/dma-mapping.h>
#include <linux/dmar.h>
-#include <asm/io.h>
+#include <linux/bootmem.h>
+#include <linux/pci.h>
+
+#include <asm/proto.h>
+#include <asm/dma.h>
#include <asm/gart.h>
#include <asm/calgary.h>
-int iommu_merge __read_mostly = 0;
-
-dma_addr_t bad_dma_address __read_mostly;
-EXPORT_SYMBOL(bad_dma_address);
+int forbid_dac __read_mostly;
+EXPORT_SYMBOL(forbid_dac);
-/* This tells the BIO block layer to assume merging. Default to off
- because we cannot guarantee merging later. */
-int iommu_bio_merge __read_mostly = 0;
-EXPORT_SYMBOL(iommu_bio_merge);
+const struct dma_mapping_ops *dma_ops;
+EXPORT_SYMBOL(dma_ops);
-static int iommu_sac_force __read_mostly = 0;
+int iommu_sac_force __read_mostly = 0;
-int no_iommu __read_mostly;
#ifdef CONFIG_IOMMU_DEBUG
int panic_on_overflow __read_mostly = 1;
int force_iommu __read_mostly = 1;
#else
int panic_on_overflow __read_mostly = 0;
-int force_iommu __read_mostly= 0;
+int force_iommu __read_mostly = 0;
#endif
+int iommu_merge __read_mostly = 0;
+
+int no_iommu __read_mostly;
/* Set this to 1 if there is a HW IOMMU in the system */
int iommu_detected __read_mostly = 0;
+/* This tells the BIO block layer to assume merging. Default to off
+ because we cannot guarantee merging later. */
+int iommu_bio_merge __read_mostly = 0;
+EXPORT_SYMBOL(iommu_bio_merge);
+
+dma_addr_t bad_dma_address __read_mostly = 0;
+EXPORT_SYMBOL(bad_dma_address);
+
/* Dummy device used for NULL arguments (normally ISA). Better would
be probably a smaller DMA mask, but this is bug-to-bug compatible
- to i386. */
+ to older i386. */
struct device fallback_dev = {
.bus_id = "fallback device",
.coherent_dma_mask = DMA_32BIT_MASK,
.dma_mask = &fallback_dev.coherent_dma_mask,
};
+int dma_set_mask(struct device *dev, u64 mask)
+{
+ if (!dev->dma_mask || !dma_supported(dev, mask))
+ return -EIO;
+
+ *dev->dma_mask = mask;
+
+ return 0;
+}
+EXPORT_SYMBOL(dma_set_mask);
+
+#ifdef CONFIG_X86_64
+static __initdata void *dma32_bootmem_ptr;
+static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
+
+static int __init parse_dma32_size_opt(char *p)
+{
+ if (!p)
+ return -EINVAL;
+ dma32_bootmem_size = memparse(p, &p);
+ return 0;
+}
+early_param("dma32_size", parse_dma32_size_opt);
+
+void __init dma32_reserve_bootmem(void)
+{
+ unsigned long size, align;
+ if (end_pfn <= MAX_DMA32_PFN)
+ return;
+
+ align = 64ULL<<20;
+ size = round_up(dma32_bootmem_size, align);
+ dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
+ __pa(MAX_DMA_ADDRESS));
+ if (dma32_bootmem_ptr)
+ dma32_bootmem_size = size;
+ else
+ dma32_bootmem_size = 0;
+}
+static void __init dma32_free_bootmem(void)
+{
+ int node;
+
+ if (end_pfn <= MAX_DMA32_PFN)
+ return;
+
+ if (!dma32_bootmem_ptr)
+ return;
+
+ for_each_online_node(node)
+ free_bootmem_node(NODE_DATA(node), __pa(dma32_bootmem_ptr),
+ dma32_bootmem_size);
+
+ dma32_bootmem_ptr = NULL;
+ dma32_bootmem_size = 0;
+}
+
+void __init pci_iommu_alloc(void)
+{
+ /* free the range so iommu could get some range less than 4G */
+ dma32_free_bootmem();
+ /*
+ * The order of these functions is important for
+ * fall-back/fail-over reasons
+ */
+#ifdef CONFIG_GART_IOMMU
+ gart_iommu_hole_init();
+#endif
+
+#ifdef CONFIG_CALGARY_IOMMU
+ detect_calgary();
+#endif
+
+ detect_intel_iommu();
+
+#ifdef CONFIG_SWIOTLB
+ pci_swiotlb_init();
+#endif
+}
+#endif
+
+/*
+ * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
+ * documentation.
+ */
+static __init int iommu_setup(char *p)
+{
+ iommu_merge = 1;
+
+ if (!p)
+ return -EINVAL;
+
+ while (*p) {
+ if (!strncmp(p, "off", 3))
+ no_iommu = 1;
+ /* gart_parse_options has more force support */
+ if (!strncmp(p, "force", 5))
+ force_iommu = 1;
+ if (!strncmp(p, "noforce", 7)) {
+ iommu_merge = 0;
+ force_iommu = 0;
+ }
+
+ if (!strncmp(p, "biomerge", 8)) {
+ iommu_bio_merge = 4096;
+ iommu_merge = 1;
+ force_iommu = 1;
+ }
+ if (!strncmp(p, "panic", 5))
+ panic_on_overflow = 1;
+ if (!strncmp(p, "nopanic", 7))
+ panic_on_overflow = 0;
+ if (!strncmp(p, "merge", 5)) {
+ iommu_merge = 1;
+ force_iommu = 1;
+ }
+ if (!strncmp(p, "nomerge", 7))
+ iommu_merge = 0;
+ if (!strncmp(p, "forcesac", 8))
+ iommu_sac_force = 1;
+ if (!strncmp(p, "allowdac", 8))
+ forbid_dac = 0;
+ if (!strncmp(p, "nodac", 5))
+ forbid_dac = -1;
+ if (!strncmp(p, "usedac", 6)) {
+ forbid_dac = -1;
+ return 1;
+ }
+#ifdef CONFIG_SWIOTLB
+ if (!strncmp(p, "soft", 4))
+ swiotlb = 1;
+#endif
+
+#ifdef CONFIG_GART_IOMMU
+ gart_parse_options(p);
+#endif
+
+#ifdef CONFIG_CALGARY_IOMMU
+ if (!strncmp(p, "calgary", 7))
+ use_calgary = 1;
+#endif /* CONFIG_CALGARY_IOMMU */
+
+ p += strcspn(p, ",");
+ if (*p == ',')
+ ++p;
+ }
+ return 0;
+}
+early_param("iommu", iommu_setup);
+
+#ifdef CONFIG_X86_32
+int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+ dma_addr_t device_addr, size_t size, int flags)
+{
+ void __iomem *mem_base = NULL;
+ int pages = size >> PAGE_SHIFT;
+ int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
+
+ if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
+ goto out;
+ if (!size)
+ goto out;
+ if (dev->dma_mem)
+ goto out;
+
+ /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
+
+ mem_base = ioremap(bus_addr, size);
+ if (!mem_base)
+ goto out;
+
+ dev->dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
+ if (!dev->dma_mem)
+ goto out;
+ dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
+ if (!dev->dma_mem->bitmap)
+ goto free1_out;
+
+ dev->dma_mem->virt_base = mem_base;
+ dev->dma_mem->device_base = device_addr;
+ dev->dma_mem->size = pages;
+ dev->dma_mem->flags = flags;
+
+ if (flags & DMA_MEMORY_MAP)
+ return DMA_MEMORY_MAP;
+
+ return DMA_MEMORY_IO;
+
+ free1_out:
+ kfree(dev->dma_mem);
+ out:
+ if (mem_base)
+ iounmap(mem_base);
+ return 0;
+}
+EXPORT_SYMBOL(dma_declare_coherent_memory);
+
+void dma_release_declared_memory(struct device *dev)
+{
+ struct dma_coherent_mem *mem = dev->dma_mem;
+
+ if (!mem)
+ return;
+ dev->dma_mem = NULL;
+ iounmap(mem->virt_base);
+ kfree(mem->bitmap);
+ kfree(mem);
+}
+EXPORT_SYMBOL(dma_release_declared_memory);
+
+void *dma_mark_declared_memory_occupied(struct device *dev,
+ dma_addr_t device_addr, size_t size)
+{
+ struct dma_coherent_mem *mem = dev->dma_mem;
+ int pos, err;
+ int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1);
+
+ pages >>= PAGE_SHIFT;
+
+ if (!mem)
+ return ERR_PTR(-EINVAL);
+
+ pos = (device_addr - mem->device_base) >> PAGE_SHIFT;
+ err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages));
+ if (err != 0)
+ return ERR_PTR(err);
+ return mem->virt_base + (pos << PAGE_SHIFT);
+}
+EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
+
+static int dma_alloc_from_coherent_mem(struct device *dev, ssize_t size,
+ dma_addr_t *dma_handle, void **ret)
+{
+ struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
+ int order = get_order(size);
+
+ if (mem) {
+ int page = bitmap_find_free_region(mem->bitmap, mem->size,
+ order);
+ if (page >= 0) {
+ *dma_handle = mem->device_base + (page << PAGE_SHIFT);
+ *ret = mem->virt_base + (page << PAGE_SHIFT);
+ memset(*ret, 0, size);
+ }
+ if (mem->flags & DMA_MEMORY_EXCLUSIVE)
+ *ret = NULL;
+ }
+ return (mem != NULL);
+}
+
+static int dma_release_coherent(struct device *dev, int order, void *vaddr)
+{
+ struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
+
+ if (mem && vaddr >= mem->virt_base && vaddr <
+ (mem->virt_base + (mem->size << PAGE_SHIFT))) {
+ int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
+
+ bitmap_release_region(mem->bitmap, page, order);
+ return 1;
+ }
+ return 0;
+}
+#else
+#define dma_alloc_from_coherent_mem(dev, size, handle, ret) (0)
+#define dma_release_coherent(dev, order, vaddr) (0)
+#endif /* CONFIG_X86_32 */
+
+int dma_supported(struct device *dev, u64 mask)
+{
+#ifdef CONFIG_PCI
+ if (mask > 0xffffffff && forbid_dac > 0) {
+ printk(KERN_INFO "PCI: Disallowing DAC for device %s\n",
+ dev->bus_id);
+ return 0;
+ }
+#endif
+
+ if (dma_ops->dma_supported)
+ return dma_ops->dma_supported(dev, mask);
+
+ /* Copied from i386. Doesn't make much sense, because it will
+ only work for pci_alloc_coherent.
+ The caller just has to use GFP_DMA in this case. */
+ if (mask < DMA_24BIT_MASK)
+ return 0;
+
+ /* Tell the device to use SAC when IOMMU force is on. This
+ allows the driver to use cheaper accesses in some cases.
+
+ Problem with this is that if we overflow the IOMMU area and
+ return DAC as fallback address the device may not handle it
+ correctly.
+
+ As a special case some controllers have a 39bit address
+ mode that is as efficient as 32bit (aic79xx). Don't force
+ SAC for these. Assume all masks <= 40 bits are of this
+ type. Normally this doesn't make any difference, but gives
+ more gentle handling of IOMMU overflow. */
+ if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
+ printk(KERN_INFO "%s: Force SAC with mask %Lx\n",
+ dev->bus_id, mask);
+ return 0;
+ }
+
+ return 1;
+}
+EXPORT_SYMBOL(dma_supported);
+
/* Allocate DMA memory on node near device */
-noinline static void *
+noinline struct page *
dma_alloc_pages(struct device *dev, gfp_t gfp, unsigned order)
{
- struct page *page;
int node;
node = dev_to_node(dev);
- page = alloc_pages_node(node, gfp, order);
- return page ? page_address(page) : NULL;
+ return alloc_pages_node(node, gfp, order);
}
/*
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
gfp_t gfp)
{
- void *memory;
+ void *memory = NULL;
+ struct page *page;
unsigned long dma_mask = 0;
- u64 bus;
+ dma_addr_t bus;
+
+ /* ignore region specifiers */
+ gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
+
+ if (dma_alloc_from_coherent_mem(dev, size, dma_handle, &memory))
+ return memory;
if (!dev)
dev = &fallback_dev;
/* Don't invoke OOM killer */
gfp |= __GFP_NORETRY;
- /* Kludge to make it bug-to-bug compatible with i386. i386
- uses the normal dma_mask for alloc_coherent. */
- dma_mask &= *dev->dma_mask;
-
+#ifdef CONFIG_X86_64
/* Why <=? Even when the mask is smaller than 4GB it is often
larger than 16MB and in this case we have a chance of
finding fitting memory in the next higher zone first. If
not retry with true GFP_DMA. -AK */
if (dma_mask <= DMA_32BIT_MASK)
gfp |= GFP_DMA32;
+#endif
again:
- memory = dma_alloc_pages(dev, gfp, get_order(size));
- if (memory == NULL)
+ page = dma_alloc_pages(dev, gfp, get_order(size));
+ if (page == NULL)
return NULL;
{
int high, mmu;
- bus = virt_to_bus(memory);
- high = (bus + size) >= dma_mask;
+ bus = page_to_phys(page);
+ memory = page_address(page);
+ high = (bus + size) >= dma_mask;
mmu = high;
if (force_iommu && !(gfp & GFP_DMA))
mmu = 1;
memset(memory, 0, size);
if (!mmu) {
- *dma_handle = virt_to_bus(memory);
+ *dma_handle = bus;
return memory;
}
}
}
if (dma_ops->map_simple) {
- *dma_handle = dma_ops->map_simple(dev, memory,
+ *dma_handle = dma_ops->map_simple(dev, virt_to_phys(memory),
size,
PCI_DMA_BIDIRECTIONAL);
if (*dma_handle != bad_dma_address)
}
if (panic_on_overflow)
- panic("dma_alloc_coherent: IOMMU overflow by %lu bytes\n",size);
+ panic("dma_alloc_coherent: IOMMU overflow by %lu bytes\n",
+ (unsigned long)size);
free_pages((unsigned long)memory, get_order(size));
return NULL;
}
void dma_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t bus)
{
+ int order = get_order(size);
WARN_ON(irqs_disabled()); /* for portability */
+ if (dma_release_coherent(dev, order, vaddr))
+ return;
if (dma_ops->unmap_single)
dma_ops->unmap_single(dev, bus, size, 0);
- free_pages((unsigned long)vaddr, get_order(size));
+ free_pages((unsigned long)vaddr, order);
}
EXPORT_SYMBOL(dma_free_coherent);
-static int forbid_dac __read_mostly;
-
-int dma_supported(struct device *dev, u64 mask)
-{
-#ifdef CONFIG_PCI
- if (mask > 0xffffffff && forbid_dac > 0) {
-
-
-
- printk(KERN_INFO "PCI: Disallowing DAC for device %s\n", dev->bus_id);
- return 0;
- }
-#endif
-
- if (dma_ops->dma_supported)
- return dma_ops->dma_supported(dev, mask);
-
- /* Copied from i386. Doesn't make much sense, because it will
- only work for pci_alloc_coherent.
- The caller just has to use GFP_DMA in this case. */
- if (mask < DMA_24BIT_MASK)
- return 0;
-
- /* Tell the device to use SAC when IOMMU force is on. This
- allows the driver to use cheaper accesses in some cases.
-
- Problem with this is that if we overflow the IOMMU area and
- return DAC as fallback address the device may not handle it
- correctly.
-
- As a special case some controllers have a 39bit address
- mode that is as efficient as 32bit (aic79xx). Don't force
- SAC for these. Assume all masks <= 40 bits are of this
- type. Normally this doesn't make any difference, but gives
- more gentle handling of IOMMU overflow. */
- if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
- printk(KERN_INFO "%s: Force SAC with mask %Lx\n", dev->bus_id,mask);
- return 0;
- }
-
- return 1;
-}
-EXPORT_SYMBOL(dma_supported);
-
-int dma_set_mask(struct device *dev, u64 mask)
-{
- if (!dev->dma_mask || !dma_supported(dev, mask))
- return -EIO;
- *dev->dma_mask = mask;
- return 0;
-}
-EXPORT_SYMBOL(dma_set_mask);
-
-/*
- * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
- * documentation.
- */
-static __init int iommu_setup(char *p)
-{
- iommu_merge = 1;
-
- if (!p)
- return -EINVAL;
-
- while (*p) {
- if (!strncmp(p, "off", 3))
- no_iommu = 1;
- /* gart_parse_options has more force support */
- if (!strncmp(p, "force", 5))
- force_iommu = 1;
- if (!strncmp(p, "noforce", 7)) {
- iommu_merge = 0;
- force_iommu = 0;
- }
-
- if (!strncmp(p, "biomerge", 8)) {
- iommu_bio_merge = 4096;
- iommu_merge = 1;
- force_iommu = 1;
- }
- if (!strncmp(p, "panic", 5))
- panic_on_overflow = 1;
- if (!strncmp(p, "nopanic", 7))
- panic_on_overflow = 0;
- if (!strncmp(p, "merge", 5)) {
- iommu_merge = 1;
- force_iommu = 1;
- }
- if (!strncmp(p, "nomerge", 7))
- iommu_merge = 0;
- if (!strncmp(p, "forcesac", 8))
- iommu_sac_force = 1;
- if (!strncmp(p, "allowdac", 8))
- forbid_dac = 0;
- if (!strncmp(p, "nodac", 5))
- forbid_dac = -1;
-
-#ifdef CONFIG_SWIOTLB
- if (!strncmp(p, "soft", 4))
- swiotlb = 1;
-#endif
-
-#ifdef CONFIG_GART_IOMMU
- gart_parse_options(p);
-#endif
-
-#ifdef CONFIG_CALGARY_IOMMU
- if (!strncmp(p, "calgary", 7))
- use_calgary = 1;
-#endif /* CONFIG_CALGARY_IOMMU */
-
- p += strcspn(p, ",");
- if (*p == ',')
- ++p;
- }
- return 0;
-}
-early_param("iommu", iommu_setup);
-
-void __init pci_iommu_alloc(void)
-{
- /*
- * The order of these functions is important for
- * fall-back/fail-over reasons
- */
-#ifdef CONFIG_GART_IOMMU
- gart_iommu_hole_init();
-#endif
-
-#ifdef CONFIG_CALGARY_IOMMU
- detect_calgary();
-#endif
-
- detect_intel_iommu();
-
-#ifdef CONFIG_SWIOTLB
- pci_swiotlb_init();
-#endif
-}
-
static int __init pci_iommu_init(void)
{
#ifdef CONFIG_CALGARY_IOMMU
{
gart_iommu_shutdown();
}
+/* Must execute after PCI subsystem */
+fs_initcall(pci_iommu_init);
#ifdef CONFIG_PCI
/* Many VIA bridges seem to corrupt data for DAC. Disable it here */
static __devinit void via_no_dac(struct pci_dev *dev)
{
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
- printk(KERN_INFO "PCI: VIA PCI bridge detected. Disabling DAC.\n");
+ printk(KERN_INFO "PCI: VIA PCI bridge detected."
+ "Disabling DAC.\n");
forbid_dac = 1;
}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
#endif
-/* Must execute after PCI subsystem */
-fs_initcall(pci_iommu_init);
+++ /dev/null
-/*
- * Dynamic DMA mapping support.
- *
- * On i386 there is no hardware dynamic DMA address translation,
- * so consistent alloc/free are merely page allocation/freeing.
- * The rest of the dynamic DMA mapping interface is implemented
- * in asm/pci.h.
- */
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/string.h>
-#include <linux/pci.h>
-#include <linux/module.h>
-#include <asm/io.h>
-
-struct dma_coherent_mem {
- void *virt_base;
- u32 device_base;
- int size;
- int flags;
- unsigned long *bitmap;
-};
-
-void *dma_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp)
-{
- void *ret;
- struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
- int order = get_order(size);
- /* ignore region specifiers */
- gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
-
- if (mem) {
- int page = bitmap_find_free_region(mem->bitmap, mem->size,
- order);
- if (page >= 0) {
- *dma_handle = mem->device_base + (page << PAGE_SHIFT);
- ret = mem->virt_base + (page << PAGE_SHIFT);
- memset(ret, 0, size);
- return ret;
- }
- if (mem->flags & DMA_MEMORY_EXCLUSIVE)
- return NULL;
- }
-
- if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
- gfp |= GFP_DMA;
-
- ret = (void *)__get_free_pages(gfp, order);
-
- if (ret != NULL) {
- memset(ret, 0, size);
- *dma_handle = virt_to_phys(ret);
- }
- return ret;
-}
-EXPORT_SYMBOL(dma_alloc_coherent);
-
-void dma_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle)
-{
- struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
- int order = get_order(size);
-
- WARN_ON(irqs_disabled()); /* for portability */
- if (mem && vaddr >= mem->virt_base && vaddr < (mem->virt_base + (mem->size << PAGE_SHIFT))) {
- int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
-
- bitmap_release_region(mem->bitmap, page, order);
- } else
- free_pages((unsigned long)vaddr, order);
-}
-EXPORT_SYMBOL(dma_free_coherent);
-
-int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
- dma_addr_t device_addr, size_t size, int flags)
-{
- void __iomem *mem_base = NULL;
- int pages = size >> PAGE_SHIFT;
- int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
-
- if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
- goto out;
- if (!size)
- goto out;
- if (dev->dma_mem)
- goto out;
-
- /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
-
- mem_base = ioremap(bus_addr, size);
- if (!mem_base)
- goto out;
-
- dev->dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
- if (!dev->dma_mem)
- goto out;
- dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
- if (!dev->dma_mem->bitmap)
- goto free1_out;
-
- dev->dma_mem->virt_base = mem_base;
- dev->dma_mem->device_base = device_addr;
- dev->dma_mem->size = pages;
- dev->dma_mem->flags = flags;
-
- if (flags & DMA_MEMORY_MAP)
- return DMA_MEMORY_MAP;
-
- return DMA_MEMORY_IO;
-
- free1_out:
- kfree(dev->dma_mem);
- out:
- if (mem_base)
- iounmap(mem_base);
- return 0;
-}
-EXPORT_SYMBOL(dma_declare_coherent_memory);
-
-void dma_release_declared_memory(struct device *dev)
-{
- struct dma_coherent_mem *mem = dev->dma_mem;
-
- if(!mem)
- return;
- dev->dma_mem = NULL;
- iounmap(mem->virt_base);
- kfree(mem->bitmap);
- kfree(mem);
-}
-EXPORT_SYMBOL(dma_release_declared_memory);
-
-void *dma_mark_declared_memory_occupied(struct device *dev,
- dma_addr_t device_addr, size_t size)
-{
- struct dma_coherent_mem *mem = dev->dma_mem;
- int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1) >> PAGE_SHIFT;
- int pos, err;
-
- if (!mem)
- return ERR_PTR(-EINVAL);
-
- pos = (device_addr - mem->device_base) >> PAGE_SHIFT;
- err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages));
- if (err != 0)
- return ERR_PTR(err);
- return mem->virt_base + (pos << PAGE_SHIFT);
-}
-EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
-
-#ifdef CONFIG_PCI
-/* Many VIA bridges seem to corrupt data for DAC. Disable it here */
-
-int forbid_dac;
-EXPORT_SYMBOL(forbid_dac);
-
-static __devinit void via_no_dac(struct pci_dev *dev)
-{
- if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
- printk(KERN_INFO "PCI: VIA PCI bridge detected. Disabling DAC.\n");
- forbid_dac = 1;
- }
-}
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
-
-static int check_iommu(char *s)
-{
- if (!strcmp(s, "usedac")) {
- forbid_dac = -1;
- return 1;
- }
- return 0;
-}
-__setup("iommu=", check_iommu);
-#endif
}
static dma_addr_t
-gart_map_simple(struct device *dev, char *buf, size_t size, int dir)
+gart_map_simple(struct device *dev, phys_addr_t paddr, size_t size, int dir)
{
- dma_addr_t map = dma_map_area(dev, virt_to_bus(buf), size, dir);
+ dma_addr_t map = dma_map_area(dev, paddr, size, dir);
flush_gart();
/* Map a single area into the IOMMU */
static dma_addr_t
-gart_map_single(struct device *dev, void *addr, size_t size, int dir)
+gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir)
{
- unsigned long phys_mem, bus;
+ unsigned long bus;
if (!dev)
dev = &fallback_dev;
- phys_mem = virt_to_phys(addr);
- if (!need_iommu(dev, phys_mem, size))
- return phys_mem;
+ if (!need_iommu(dev, paddr, size))
+ return paddr;
- bus = gart_map_simple(dev, addr, size, dir);
+ bus = gart_map_simple(dev, paddr, size, dir);
return bus;
}
static int
check_addr(char *name, struct device *hwdev, dma_addr_t bus, size_t size)
{
- if (hwdev && bus + size > *hwdev->dma_mask) {
+ if (hwdev && bus + size > *hwdev->dma_mask) {
if (*hwdev->dma_mask >= DMA_32BIT_MASK)
printk(KERN_ERR
"nommu_%s: overflow %Lx+%zu of device mask %Lx\n",
}
static dma_addr_t
-nommu_map_single(struct device *hwdev, void *ptr, size_t size,
+nommu_map_single(struct device *hwdev, phys_addr_t paddr, size_t size,
int direction)
{
- dma_addr_t bus = virt_to_bus(ptr);
+ dma_addr_t bus = paddr;
+ WARN_ON(size == 0);
if (!check_addr("map_single", hwdev, bus, size))
return bad_dma_address;
+ flush_write_buffers();
return bus;
}
-static void nommu_unmap_single(struct device *dev, dma_addr_t addr,size_t size,
- int direction)
-{
-}
/* Map a set of buffers described by scatterlist in streaming
* mode for DMA. This is the scatter-gather version of the
struct scatterlist *s;
int i;
+ WARN_ON(nents == 0 || sg[0].length == 0);
+
for_each_sg(sg, s, nents, i) {
BUG_ON(!sg_page(s));
- s->dma_address = virt_to_bus(sg_virt(s));
+ s->dma_address = sg_phys(s);
if (!check_addr("map_sg", hwdev, s->dma_address, s->length))
return 0;
s->dma_length = s->length;
}
+ flush_write_buffers();
return nents;
}
-/* Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-static void nommu_unmap_sg(struct device *dev, struct scatterlist *sg,
- int nents, int dir)
+/* Make sure we keep the same behaviour */
+static int nommu_mapping_error(dma_addr_t dma_addr)
{
+#ifdef CONFIG_X86_32
+ return 0;
+#else
+ return (dma_addr == bad_dma_address);
+#endif
}
+
const struct dma_mapping_ops nommu_dma_ops = {
.map_single = nommu_map_single,
- .unmap_single = nommu_unmap_single,
.map_sg = nommu_map_sg,
- .unmap_sg = nommu_unmap_sg,
+ .mapping_error = nommu_mapping_error,
.is_phys = 1,
};
int swiotlb __read_mostly;
+static dma_addr_t
+swiotlb_map_single_phys(struct device *hwdev, phys_addr_t paddr, size_t size,
+ int direction)
+{
+ return swiotlb_map_single(hwdev, phys_to_virt(paddr), size, direction);
+}
+
const struct dma_mapping_ops swiotlb_dma_ops = {
.mapping_error = swiotlb_dma_mapping_error,
.alloc_coherent = swiotlb_alloc_coherent,
.free_coherent = swiotlb_free_coherent,
- .map_single = swiotlb_map_single,
+ .map_single = swiotlb_map_single_phys,
.unmap_single = swiotlb_unmap_single,
.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
.sync_single_for_device = swiotlb_sync_single_for_device,
--- /dev/null
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+
+struct kmem_cache *task_xstate_cachep;
+
+int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
+{
+ *dst = *src;
+ if (src->thread.xstate) {
+ dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
+ GFP_KERNEL);
+ if (!dst->thread.xstate)
+ return -ENOMEM;
+ WARN_ON((unsigned long)dst->thread.xstate & 15);
+ memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
+ }
+ return 0;
+}
+
+void free_thread_xstate(struct task_struct *tsk)
+{
+ if (tsk->thread.xstate) {
+ kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
+ tsk->thread.xstate = NULL;
+ }
+}
+
+void free_thread_info(struct thread_info *ti)
+{
+ free_thread_xstate(ti->task);
+ free_pages((unsigned long)ti, get_order(THREAD_SIZE));
+}
+
+void arch_task_cache_init(void)
+{
+ task_xstate_cachep =
+ kmem_cache_create("task_xstate", xstate_size,
+ __alignof__(union thread_xstate),
+ SLAB_PANIC, NULL);
+}
#include <linux/personality.h>
#include <linux/tick.h>
#include <linux/percpu.h>
+#include <linux/prctl.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/i387.h>
#include <asm/desc.h>
-#include <asm/vm86.h>
#ifdef CONFIG_MATH_EMULATION
#include <asm/math_emu.h>
#endif
regs->cs = __USER_CS;
regs->ip = new_ip;
regs->sp = new_sp;
+ /*
+ * Free the old FP and other extended state
+ */
+ free_thread_xstate(current);
}
EXPORT_SYMBOL_GPL(start_thread);
-#ifdef CONFIG_SECCOMP
static void hard_disable_TSC(void)
{
write_cr4(read_cr4() | X86_CR4_TSD);
}
+
void disable_TSC(void)
{
preempt_disable();
hard_disable_TSC();
preempt_enable();
}
+
static void hard_enable_TSC(void)
{
write_cr4(read_cr4() & ~X86_CR4_TSD);
}
-#endif /* CONFIG_SECCOMP */
+
+void enable_TSC(void)
+{
+ preempt_disable();
+ if (test_and_clear_thread_flag(TIF_NOTSC))
+ /*
+ * Must flip the CPU state synchronously with
+ * TIF_NOTSC in the current running context.
+ */
+ hard_enable_TSC();
+ preempt_enable();
+}
+
+int get_tsc_mode(unsigned long adr)
+{
+ unsigned int val;
+
+ if (test_thread_flag(TIF_NOTSC))
+ val = PR_TSC_SIGSEGV;
+ else
+ val = PR_TSC_ENABLE;
+
+ return put_user(val, (unsigned int __user *)adr);
+}
+
+int set_tsc_mode(unsigned int val)
+{
+ if (val == PR_TSC_SIGSEGV)
+ disable_TSC();
+ else if (val == PR_TSC_ENABLE)
+ enable_TSC();
+ else
+ return -EINVAL;
+
+ return 0;
+}
static noinline void
__switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
set_debugreg(next->debugreg7, 7);
}
-#ifdef CONFIG_SECCOMP
if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
test_tsk_thread_flag(next_p, TIF_NOTSC)) {
/* prev and next are different */
else
hard_enable_TSC();
}
-#endif
#ifdef X86_BTS
if (test_tsk_thread_flag(prev_p, TIF_BTS_TRACE_TS))
/* we're going to use this soon, after a few expensive things */
if (next_p->fpu_counter > 5)
- prefetch(&next->i387.fxsave);
+ prefetch(next->xstate);
/*
* Reload esp0.
#include <linux/kprobes.h>
#include <linux/kdebug.h>
#include <linux/tick.h>
+#include <linux/prctl.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
regs->ss = __USER_DS;
regs->flags = 0x200;
set_fs(USER_DS);
+ /*
+ * Free the old FP and other extended state
+ */
+ free_thread_xstate(current);
}
EXPORT_SYMBOL_GPL(start_thread);
+static void hard_disable_TSC(void)
+{
+ write_cr4(read_cr4() | X86_CR4_TSD);
+}
+
+void disable_TSC(void)
+{
+ preempt_disable();
+ if (!test_and_set_thread_flag(TIF_NOTSC))
+ /*
+ * Must flip the CPU state synchronously with
+ * TIF_NOTSC in the current running context.
+ */
+ hard_disable_TSC();
+ preempt_enable();
+}
+
+static void hard_enable_TSC(void)
+{
+ write_cr4(read_cr4() & ~X86_CR4_TSD);
+}
+
+void enable_TSC(void)
+{
+ preempt_disable();
+ if (test_and_clear_thread_flag(TIF_NOTSC))
+ /*
+ * Must flip the CPU state synchronously with
+ * TIF_NOTSC in the current running context.
+ */
+ hard_enable_TSC();
+ preempt_enable();
+}
+
+int get_tsc_mode(unsigned long adr)
+{
+ unsigned int val;
+
+ if (test_thread_flag(TIF_NOTSC))
+ val = PR_TSC_SIGSEGV;
+ else
+ val = PR_TSC_ENABLE;
+
+ return put_user(val, (unsigned int __user *)adr);
+}
+
+int set_tsc_mode(unsigned int val)
+{
+ if (val == PR_TSC_SIGSEGV)
+ disable_TSC();
+ else if (val == PR_TSC_ENABLE)
+ enable_TSC();
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
/*
* This special macro can be used to load a debugging register
*/
loaddebug(next, 7);
}
+ if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
+ test_tsk_thread_flag(next_p, TIF_NOTSC)) {
+ /* prev and next are different */
+ if (test_tsk_thread_flag(next_p, TIF_NOTSC))
+ hard_disable_TSC();
+ else
+ hard_enable_TSC();
+ }
+
if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
/*
* Copy the relevant range of the IO bitmap.
/* we're going to use this soon, after a few expensive things */
if (next_p->fpu_counter>5)
- prefetch(&next->i387.fxsave);
+ prefetch(next->xstate);
/*
* Reload esp0, LDT and the page table pointer:
reboot_cpu_id = smp_processor_id();
/* Make certain I only run on the appropriate processor */
- set_cpus_allowed(current, cpumask_of_cpu(reboot_cpu_id));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(reboot_cpu_id));
/* O.K Now that I'm on the appropriate processor,
* stop all of the others.
#endif
}
+#ifdef CONFIG_HAVE_CPUMASK_OF_CPU_MAP
+cpumask_t *cpumask_of_cpu_map __read_mostly;
+EXPORT_SYMBOL(cpumask_of_cpu_map);
+
+/* requires nr_cpu_ids to be initialized */
+static void __init setup_cpumask_of_cpu(void)
+{
+ int i;
+
+ /* alloc_bootmem zeroes memory */
+ cpumask_of_cpu_map = alloc_bootmem_low(sizeof(cpumask_t) * nr_cpu_ids);
+ for (i = 0; i < nr_cpu_ids; i++)
+ cpu_set(i, cpumask_of_cpu_map[i]);
+}
+#else
+static inline void setup_cpumask_of_cpu(void) { }
+#endif
+
#ifdef CONFIG_X86_32
/*
* Great future not-so-futuristic plan: make i386 and x86_64 do it
*/
void __init setup_per_cpu_areas(void)
{
- int i;
+ int i, highest_cpu = 0;
unsigned long size;
#ifdef CONFIG_HOTPLUG_CPU
__per_cpu_offset[i] = ptr - __per_cpu_start;
#endif
memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
+
+ highest_cpu = i;
}
+ nr_cpu_ids = highest_cpu + 1;
+ printk(KERN_DEBUG "NR_CPUS: %d, nr_cpu_ids: %d\n", NR_CPUS, nr_cpu_ids);
+
/* Setup percpu data maps */
setup_per_cpu_maps();
+
+ /* Setup cpumask_of_cpu map */
+ setup_cpumask_of_cpu();
}
#endif
Control non executable heap for 32bit processes.
To control the stack too use noexec=off
-on PROT_READ does not imply PROT_EXEC for 32bit processes
-off PROT_READ implies PROT_EXEC (default)
+on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
+off PROT_READ implies PROT_EXEC
*/
static int __init nonx32_setup(char *str)
{
#include <linux/efi.h>
#include <linux/init.h>
#include <linux/edd.h>
+#include <linux/iscsi_ibft.h>
#include <linux/nodemask.h>
#include <linux/kexec.h>
#include <linux/crash_dump.h>
#endif
numa_kva_reserve();
reserve_crashkernel();
+
+ reserve_ibft_region();
}
/*
efi_init();
/* update e820 for memory not covered by WB MTRRs */
- find_max_pfn();
+ propagate_e820_map();
mtrr_bp_init();
if (mtrr_trim_uncached_memory(max_pfn))
- find_max_pfn();
+ propagate_e820_map();
max_low_pfn = setup_memory();
#include <linux/acpi.h>
#include <linux/kallsyms.h>
#include <linux/edd.h>
+#include <linux/iscsi_ibft.h>
#include <linux/mmzone.h>
#include <linux/kexec.h>
#include <linux/cpufreq.h>
early_res_to_bootmem();
+ dma32_reserve_bootmem();
+
#ifdef CONFIG_ACPI_SLEEP
/*
* Reserve low memory region for sleep support.
unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
if (ramdisk_end <= end_of_mem) {
- reserve_bootmem_generic(ramdisk_image, ramdisk_size);
+ /*
+ * don't need to reserve again, already reserved early
+ * in x86_64_start_kernel, and early_res_to_bootmem
+ * convert that to reserved in bootmem
+ */
initrd_start = ramdisk_image + PAGE_OFFSET;
initrd_end = initrd_start+ramdisk_size;
} else {
- /* Assumes everything on node 0 */
free_bootmem(ramdisk_image, ramdisk_size);
printk(KERN_ERR "initrd extends beyond end of memory "
"(0x%08lx > 0x%08lx)\ndisabling initrd\n",
}
#endif
reserve_crashkernel();
+
+ reserve_ibft_region();
+
paging_init();
map_vsyscall();
#include <asm/mtrr.h>
#include <asm/nmi.h>
#include <asm/vmi.h>
+#include <asm/genapic.h>
#include <linux/mc146818rtc.h>
#include <mach_apic.h>
unsigned long send_status, accept_status = 0;
int maxlvt, num_starts, j;
+ if (get_uv_system_type() == UV_NON_UNIQUE_APIC) {
+ send_status = uv_wakeup_secondary(phys_apicid, start_eip);
+ atomic_set(&init_deasserted, 1);
+ return send_status;
+ }
+
/*
* Be paranoid about clearing APIC errors.
*/
atomic_set(&init_deasserted, 0);
- Dprintk("Setting warm reset code and vector.\n");
+ if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
- store_NMI_vector(&nmi_high, &nmi_low);
+ Dprintk("Setting warm reset code and vector.\n");
- smpboot_setup_warm_reset_vector(start_ip);
- /*
- * Be paranoid about clearing APIC errors.
- */
- apic_write(APIC_ESR, 0);
- apic_read(APIC_ESR);
+ store_NMI_vector(&nmi_high, &nmi_low);
+
+ smpboot_setup_warm_reset_vector(start_ip);
+ /*
+ * Be paranoid about clearing APIC errors.
+ */
+ apic_write(APIC_ESR, 0);
+ apic_read(APIC_ESR);
+ }
/*
* Starting actual IPI sequence...
else
/* trampoline code not run */
printk(KERN_ERR "Not responding.\n");
- inquire_remote_apic(apicid);
+ if (get_uv_system_type() != UV_NON_UNIQUE_APIC)
+ inquire_remote_apic(apicid);
}
}
}
}
-static __kprobes void
+static notrace __kprobes void
mem_parity_error(unsigned char reason, struct pt_regs *regs)
{
printk(KERN_EMERG
clear_mem_error(reason);
}
-static __kprobes void
+static notrace __kprobes void
io_check_error(unsigned char reason, struct pt_regs *regs)
{
unsigned long i;
outb(reason, 0x61);
}
-static __kprobes void
+static notrace __kprobes void
unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
{
if (notify_die(DIE_NMIUNKNOWN, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP)
static DEFINE_SPINLOCK(nmi_print_lock);
-void __kprobes die_nmi(struct pt_regs *regs, const char *msg)
+void notrace __kprobes die_nmi(struct pt_regs *regs, const char *msg)
{
if (notify_die(DIE_NMIWATCHDOG, msg, regs, 0, 2, SIGINT) == NOTIFY_STOP)
return;
do_exit(SIGSEGV);
}
-static __kprobes void default_do_nmi(struct pt_regs *regs)
+static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
{
unsigned char reason = 0;
static int ignore_nmis;
-__kprobes void do_nmi(struct pt_regs *regs, long error_code)
+notrace __kprobes void do_nmi(struct pt_regs *regs, long error_code)
{
int cpu;
struct thread_info *thread = current_thread_info();
struct task_struct *tsk = thread->task;
+ if (!tsk_used_math(tsk)) {
+ local_irq_enable();
+ /*
+ * does a slab alloc which can sleep
+ */
+ if (init_fpu(tsk)) {
+ /*
+ * ran out of memory!
+ */
+ do_group_exit(SIGKILL);
+ return;
+ }
+ local_irq_disable();
+ }
+
clts(); /* Allow maths ops (or we recurse) */
- if (!tsk_used_math(tsk))
- init_fpu(tsk);
restore_fpu(tsk);
thread->status |= TS_USEDFPU; /* So we fnsave on switch_to() */
tsk->fpu_counter++;
#endif
set_trap_gate(19, &simd_coprocessor_error);
- /*
- * Verify that the FXSAVE/FXRSTOR data will be 16-byte aligned.
- * Generate a build-time error if the alignment is wrong.
- */
- BUILD_BUG_ON(offsetof(struct task_struct, thread.i387.fxsave) & 15);
if (cpu_has_fxsr) {
printk(KERN_INFO "Enabling fast FPU save and restore... ");
set_in_cr4(X86_CR4_OSFXSR);
set_bit(SYSCALL_VECTOR, used_vectors);
+ init_thread_xstate();
/*
* Should be a barrier for any external CPU state:
*/
oops_end(flags, regs, SIGSEGV);
}
-void __kprobes die_nmi(char *str, struct pt_regs *regs, int do_panic)
+notrace __kprobes void
+die_nmi(char *str, struct pt_regs *regs, int do_panic)
{
unsigned long flags;
die("general protection fault", regs, error_code);
}
-static __kprobes void
+static notrace __kprobes void
mem_parity_error(unsigned char reason, struct pt_regs * regs)
{
printk(KERN_EMERG "Uhhuh. NMI received for unknown reason %02x.\n",
outb(reason, 0x61);
}
-static __kprobes void
+static notrace __kprobes void
io_check_error(unsigned char reason, struct pt_regs * regs)
{
printk("NMI: IOCK error (debug interrupt?)\n");
outb(reason, 0x61);
}
-static __kprobes void
+static notrace __kprobes void
unknown_nmi_error(unsigned char reason, struct pt_regs * regs)
{
if (notify_die(DIE_NMIUNKNOWN, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP)
/* Runs on IST stack. This code must keep interrupts off all the time.
Nested NMIs are prevented by the CPU. */
-asmlinkage __kprobes void default_do_nmi(struct pt_regs *regs)
+asmlinkage notrace __kprobes void default_do_nmi(struct pt_regs *regs)
{
unsigned char reason = 0;
int cpu;
asmlinkage void math_state_restore(void)
{
struct task_struct *me = current;
- clts(); /* Allow maths ops (or we recurse) */
- if (!used_math())
- init_fpu(me);
- restore_fpu_checking(&me->thread.i387.fxsave);
+ if (!used_math()) {
+ local_irq_enable();
+ /*
+ * does a slab alloc which can sleep
+ */
+ if (init_fpu(me)) {
+ /*
+ * ran out of memory!
+ */
+ do_group_exit(SIGKILL);
+ return;
+ }
+ local_irq_disable();
+ }
+
+ clts(); /* Allow maths ops (or we recurse) */
+ restore_fpu_checking(&me->thread.xstate->fxsave);
task_thread_info(me)->status |= TS_USEDFPU;
me->fpu_counter++;
}
set_system_gate(IA32_SYSCALL_VECTOR, ia32_syscall);
#endif
+ /*
+ * initialize the per thread extended state:
+ */
+ init_thread_xstate();
/*
* Should be a barrier for any external CPU state.
*/
* if the CPU frequency is scaled, TSC-based delays will need a different
* loops_per_jiffy value to function properly.
*/
-static unsigned int ref_freq = 0;
-static unsigned long loops_per_jiffy_ref = 0;
-static unsigned long cpu_khz_ref = 0;
+static unsigned int ref_freq;
+static unsigned long loops_per_jiffy_ref;
+static unsigned long cpu_khz_ref;
static int
time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
/* clock source code */
-static unsigned long current_tsc_khz = 0;
+static unsigned long current_tsc_khz;
+static struct clocksource clocksource_tsc;
+/*
+ * We compare the TSC to the cycle_last value in the clocksource
+ * structure to avoid a nasty time-warp issue. This can be observed in
+ * a very small window right after one CPU updated cycle_last under
+ * xtime lock and the other CPU reads a TSC value which is smaller
+ * than the cycle_last reference value due to a TSC which is slighty
+ * behind. This delta is nowhere else observable, but in that case it
+ * results in a forward time jump in the range of hours due to the
+ * unsigned delta calculation of the time keeping core code, which is
+ * necessary to support wrapping clocksources like pm timer.
+ */
static cycle_t read_tsc(void)
{
cycle_t ret;
rdtscll(ret);
- return ret;
+ return ret >= clocksource_tsc.cycle_last ?
+ ret : clocksource_tsc.cycle_last;
}
static struct clocksource clocksource_tsc = {
#include <asm/hpet.h>
#include <asm/timex.h>
#include <asm/timer.h>
+#include <asm/vgtod.h>
static int notsc __initdata = 0;
__setup("notsc", notsc_setup);
+static struct clocksource clocksource_tsc;
-/* clock source code: */
+/*
+ * We compare the TSC to the cycle_last value in the clocksource
+ * structure to avoid a nasty time-warp. This can be observed in a
+ * very small window right after one CPU updated cycle_last under
+ * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
+ * is smaller than the cycle_last reference value due to a TSC which
+ * is slighty behind. This delta is nowhere else observable, but in
+ * that case it results in a forward time jump in the range of hours
+ * due to the unsigned delta calculation of the time keeping core
+ * code, which is necessary to support wrapping clocksources like pm
+ * timer.
+ */
static cycle_t read_tsc(void)
{
cycle_t ret = (cycle_t)get_cycles();
- return ret;
+
+ return ret >= clocksource_tsc.cycle_last ?
+ ret : clocksource_tsc.cycle_last;
}
static cycle_t __vsyscall_fn vread_tsc(void)
{
cycle_t ret = (cycle_t)vget_cycles();
- return ret;
+
+ return ret >= __vsyscall_gtod_data.clock.cycle_last ?
+ ret : __vsyscall_gtod_data.clock.cycle_last;
}
static struct clocksource clocksource_tsc = {
/*
- * linux/arch/i386/mach-visws/visws_apic.c
- *
* Copyright (C) 1999 Bent Hagemark, Ingo Molnar
*
* SGI Visual Workstation interrupt controller
*
* Author: J.E.J.Bottomley@HansenPartnership.com
*
- * linux/arch/i386/kernel/voyager.c
- *
* This file contains all the voyager specific routines for getting
* initialisation of the architecture to function. For additional
* features see:
*
* Author: J.E.J.Bottomley@HansenPartnership.com
*
- * linux/arch/i386/kernel/voyager_cat.c
- *
* This file contains all the logic for manipulating the CAT bus
* in a level 5 machine.
*
*
* Author: J.E.J.Bottomley@HansenPartnership.com
*
- * linux/arch/i386/kernel/voyager_smp.c
- *
* This file provides all the same external entries as smp.c but uses
* the voyager hal to provide the functionality
*/
*
* Author: J.E.J.Bottomley@HansenPartnership.com
*
- * linux/arch/i386/kernel/voyager_thread.c
- *
* This module provides the machine status monitor thread for the
* voyager architecture. This allows us to monitor the machine
* environment (temp, voltage, fan function) and the front panel and
unsigned int pos, unsigned int count,
const void *kbuf, const void __user *ubuf)
{
- struct i387_soft_struct *s387 = &target->thread.i387.soft;
+ struct i387_soft_struct *s387 = &target->thread.xstate->soft;
void *space = s387->st_space;
int ret;
int offset, other, i, tags, regnr, tag, newtop;
unsigned int pos, unsigned int count,
void *kbuf, void __user *ubuf)
{
- struct i387_soft_struct *s387 = &target->thread.i387.soft;
+ struct i387_soft_struct *s387 = &target->thread.xstate->soft;
const void *space = s387->st_space;
int ret;
int offset = (S387->ftop & 7) * 10, other = 80 - offset;
#define SEG_EXPAND_DOWN(s) (((s).b & ((1 << 11) | (1 << 10))) \
== (1 << 10))
-#define I387 (current->thread.i387)
-#define FPU_info (I387.soft.info)
+#define I387 (current->thread.xstate)
+#define FPU_info (I387->soft.info)
#define FPU_CS (*(unsigned short *) &(FPU_info->___cs))
#define FPU_SS (*(unsigned short *) &(FPU_info->___ss))
#define FPU_EIP (FPU_info->___eip)
#define FPU_ORIG_EIP (FPU_info->___orig_eip)
-#define FPU_lookahead (I387.soft.lookahead)
+#define FPU_lookahead (I387->soft.lookahead)
/* nz if ip_offset and cs_selector are not to be set for the current
instruction. */
-#define no_ip_update (*(u_char *)&(I387.soft.no_update))
-#define FPU_rm (*(u_char *)&(I387.soft.rm))
+#define no_ip_update (*(u_char *)&(I387->soft.no_update))
+#define FPU_rm (*(u_char *)&(I387->soft.rm))
/* Number of bytes of data which can be legally accessed by the current
instruction. This only needs to hold a number <= 108, so a byte will do. */
-#define access_limit (*(u_char *)&(I387.soft.alimit))
+#define access_limit (*(u_char *)&(I387->soft.alimit))
-#define partial_status (I387.soft.swd)
-#define control_word (I387.soft.cwd)
-#define fpu_tag_word (I387.soft.twd)
-#define registers (I387.soft.st_space)
-#define top (I387.soft.ftop)
+#define partial_status (I387->soft.swd)
+#define control_word (I387->soft.cwd)
+#define fpu_tag_word (I387->soft.twd)
+#define registers (I387->soft.st_space)
+#define top (I387->soft.ftop)
-#define instruction_address (*(struct address *)&I387.soft.fip)
-#define operand_address (*(struct address *)&I387.soft.foo)
+#define instruction_address (*(struct address *)&I387->soft.fip)
+#define operand_address (*(struct address *)&I387->soft.foo)
#define FPU_access_ok(x,y,z) if ( !access_ok(x,y,z) ) \
math_abort(FPU_info,SIGSEGV)
control_word |= 0xffff0040;
partial_status = status_word() | 0xffff0000;
fpu_tag_word |= 0xffff0000;
- I387.soft.fcs &= ~0xf8000000;
- I387.soft.fos |= 0xffff0000;
+ I387->soft.fcs &= ~0xf8000000;
+ I387->soft.fos |= 0xffff0000;
#endif /* PECULIAR_486 */
if (__copy_to_user(d, &control_word, 7 * 4))
FPU_abort;
printk("NUMA - single node, flat memory mode\n");
/* Run the memory configuration and find the top of memory. */
- find_max_pfn();
+ propagate_e820_map();
node_start_pfn[0] = 0;
node_end_pfn[0] = max_pfn;
memory_present(0, 0, max_pfn);
/*
* Find the highest page frame number we have available for the node
*/
-static void __init find_max_pfn_node(int nid)
+static void __init propagate_e820_map_node(int nid)
{
if (node_end_pfn[nid] > max_pfn)
node_end_pfn[nid] = max_pfn;
printk("High memory starts at vaddr %08lx\n",
(ulong) pfn_to_kaddr(highstart_pfn));
for_each_online_node(nid)
- find_max_pfn_node(nid);
+ propagate_e820_map_node(nid);
memset(NODE_DATA(0), 0, sizeof(struct pglist_data));
NODE_DATA(0)->bdata = &node0_bdata;
/*
- * linux/arch/i386/mm/init.c
*
* Copyright (C) 1995 Linus Torvalds
*
#include <asm/numa.h>
#include <asm/cacheflush.h>
-const struct dma_mapping_ops *dma_ops;
-EXPORT_SYMBOL(dma_ops);
-
static unsigned long dma_reserve __initdata;
DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
if (!phys_addr_valid(phys_addr)) {
printk(KERN_WARNING "ioremap: invalid physical address %llx\n",
- phys_addr);
+ (unsigned long long)phys_addr);
WARN_ON_ONCE(1);
return NULL;
}
new_prot_val == _PAGE_CACHE_WB)) {
pr_debug(
"ioremap error for 0x%llx-0x%llx, requested 0x%lx, got 0x%lx\n",
- phys_addr, phys_addr + size,
+ (unsigned long long)phys_addr,
+ (unsigned long long)(phys_addr + size),
prot_val, new_prot_val);
free_memtype(phys_addr, phys_addr + size);
return NULL;
if (!found)
return -1;
- memnode_shift = compute_hash_shift(nodes, 8);
+ memnode_shift = compute_hash_shift(nodes, 8, NULL);
if (memnode_shift < 0) {
printk(KERN_ERR "No NUMA node hash function found. Contact maintainer\n");
return -1;
* -1 if node overlap or lost ram (shift too big)
*/
static int __init populate_memnodemap(const struct bootnode *nodes,
- int numnodes, int shift)
+ int numnodes, int shift, int *nodeids)
{
unsigned long addr, end;
int i, res = -1;
do {
if (memnodemap[addr >> shift] != NUMA_NO_NODE)
return -1;
- memnodemap[addr >> shift] = i;
+
+ if (!nodeids)
+ memnodemap[addr >> shift] = i;
+ else
+ memnodemap[addr >> shift] = nodeids[i];
+
addr += (1UL << shift);
} while (addr < end);
res = 1;
return i;
}
-int __init compute_hash_shift(struct bootnode *nodes, int numnodes)
+int __init compute_hash_shift(struct bootnode *nodes, int numnodes,
+ int *nodeids)
{
int shift;
printk(KERN_DEBUG "NUMA: Using %d for the hash shift.\n",
shift);
- if (populate_memnodemap(nodes, numnodes, shift) != 1) {
+ if (populate_memnodemap(nodes, numnodes, shift, nodeids) != 1) {
printk(KERN_INFO "Your memory is not aligned you need to "
"rebuild your kernel with a bigger NODEMAPSIZE "
"shift=%d\n", shift);
* Sets up the system RAM area from start_pfn to end_pfn according to the
* numa=fake command-line option.
*/
+static struct bootnode nodes[MAX_NUMNODES] __initdata;
+
static int __init numa_emulation(unsigned long start_pfn, unsigned long end_pfn)
{
- struct bootnode nodes[MAX_NUMNODES];
u64 size, addr = start_pfn << PAGE_SHIFT;
u64 max_addr = end_pfn << PAGE_SHIFT;
int num_nodes = 0, num = 0, coeff_flag, coeff = -1, i;
}
}
out:
- memnode_shift = compute_hash_shift(nodes, num_nodes);
+ memnode_shift = compute_hash_shift(nodes, num_nodes, NULL);
if (memnode_shift < 0) {
memnode_shift = 0;
printk(KERN_ERR "No NUMA hash function found. NUMA emulation "
-/*
- * linux/arch/i386/mm/pgtable.c
- */
-
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/errno.h>
static int found_add_area __initdata;
int hotadd_percent __initdata = 0;
+static int num_node_memblks __initdata;
+static struct bootnode node_memblk_range[NR_NODE_MEMBLKS] __initdata;
+static int memblk_nodeid[NR_NODE_MEMBLKS] __initdata;
+
/* Too small nodes confuse the VM badly. Usually they result
from BIOS bugs. */
#define NODE_MIN_SIZE (4*1024*1024)
return acpi_map_pxm_to_node(pxm);
}
-static __init int conflicting_nodes(unsigned long start, unsigned long end)
+static __init int conflicting_memblks(unsigned long start, unsigned long end)
{
int i;
- for_each_node_mask(i, nodes_parsed) {
- struct bootnode *nd = &nodes[i];
+ for (i = 0; i < num_node_memblks; i++) {
+ struct bootnode *nd = &node_memblk_range[i];
if (nd->start == nd->end)
continue;
if (nd->end > start && nd->start < end)
- return i;
+ return memblk_nodeid[i];
if (nd->end == end && nd->start == start)
- return i;
+ return memblk_nodeid[i];
}
return -1;
}
bad_srat();
return;
}
- i = conflicting_nodes(start, end);
+ i = conflicting_memblks(start, end);
if (i == node) {
printk(KERN_WARNING
"SRAT: Warning: PXM %d (%lx-%lx) overlaps with itself (%Lx-%Lx)\n",
nd->end = end;
}
- printk(KERN_INFO "SRAT: Node %u PXM %u %Lx-%Lx\n", node, pxm,
- nd->start, nd->end);
- e820_register_active_regions(node, nd->start >> PAGE_SHIFT,
- nd->end >> PAGE_SHIFT);
+ printk(KERN_INFO "SRAT: Node %u PXM %u %lx-%lx\n", node, pxm,
+ start, end);
+ e820_register_active_regions(node, start >> PAGE_SHIFT,
+ end >> PAGE_SHIFT);
push_node_boundaries(node, nd->start >> PAGE_SHIFT,
nd->end >> PAGE_SHIFT);
if ((nd->start | nd->end) == 0)
node_clear(node, nodes_parsed);
}
+
+ node_memblk_range[num_node_memblks].start = start;
+ node_memblk_range[num_node_memblks].end = end;
+ memblk_nodeid[num_node_memblks] = node;
+ num_node_memblks++;
}
/* Sanity check to catch more bad SRATs (they are amazingly common).
return -1;
}
- memnode_shift = compute_hash_shift(nodes, MAX_NUMNODES);
+ memnode_shift = compute_hash_shift(node_memblk_range, num_node_memblks,
+ memblk_nodeid);
if (memnode_shift < 0) {
printk(KERN_ERR
"SRAT: No NUMA node hash function found. Contact maintainer\n");
#include "op_x86_model.h"
static struct op_x86_model_spec const *model;
-static struct op_msrs cpu_msrs[NR_CPUS];
-static unsigned long saved_lvtpc[NR_CPUS];
+static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
+static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
static int nmi_start(void);
static void nmi_stop(void);
switch (val) {
case DIE_NMI:
- if (model->check_ctrs(args->regs, &cpu_msrs[cpu]))
+ if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
ret = NOTIFY_STOP;
break;
default:
static void nmi_save_registers(void *dummy)
{
int cpu = smp_processor_id();
- struct op_msrs *msrs = &cpu_msrs[cpu];
+ struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
nmi_cpu_save_registers(msrs);
}
{
int i;
for_each_possible_cpu(i) {
- kfree(cpu_msrs[i].counters);
- cpu_msrs[i].counters = NULL;
- kfree(cpu_msrs[i].controls);
- cpu_msrs[i].controls = NULL;
+ kfree(per_cpu(cpu_msrs, i).counters);
+ per_cpu(cpu_msrs, i).counters = NULL;
+ kfree(per_cpu(cpu_msrs, i).controls);
+ per_cpu(cpu_msrs, i).controls = NULL;
}
}
int i;
for_each_possible_cpu(i) {
- cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
- if (!cpu_msrs[i].counters) {
+ per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
+ GFP_KERNEL);
+ if (!per_cpu(cpu_msrs, i).counters) {
success = 0;
break;
}
- cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
- if (!cpu_msrs[i].controls) {
+ per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
+ GFP_KERNEL);
+ if (!per_cpu(cpu_msrs, i).controls) {
success = 0;
break;
}
static void nmi_cpu_setup(void *dummy)
{
int cpu = smp_processor_id();
- struct op_msrs *msrs = &cpu_msrs[cpu];
+ struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
spin_lock(&oprofilefs_lock);
model->setup_ctrs(msrs);
spin_unlock(&oprofilefs_lock);
- saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
+ per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
apic_write(APIC_LVTPC, APIC_DM_NMI);
}
*/
/* Assume saved/restored counters are the same on all CPUs */
- model->fill_in_addresses(&cpu_msrs[0]);
+ model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
for_each_possible_cpu(cpu) {
if (cpu != 0) {
- memcpy(cpu_msrs[cpu].counters, cpu_msrs[0].counters,
+ memcpy(per_cpu(cpu_msrs, cpu).counters,
+ per_cpu(cpu_msrs, 0).counters,
sizeof(struct op_msr) * model->num_counters);
- memcpy(cpu_msrs[cpu].controls, cpu_msrs[0].controls,
+ memcpy(per_cpu(cpu_msrs, cpu).controls,
+ per_cpu(cpu_msrs, 0).controls,
sizeof(struct op_msr) * model->num_controls);
}
{
unsigned int v;
int cpu = smp_processor_id();
- struct op_msrs *msrs = &cpu_msrs[cpu];
+ struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
/* restoring APIC_LVTPC can trigger an apic error because the delivery
* mode and vector nr combination can be illegal. That's by design: on
*/
v = apic_read(APIC_LVTERR);
apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
- apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
+ apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
apic_write(APIC_LVTERR, v);
nmi_restore_registers(msrs);
}
static void nmi_shutdown(void)
{
+ struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
nmi_enabled = 0;
on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
unregister_die_notifier(&profile_exceptions_nb);
- model->shutdown(cpu_msrs);
+ model->shutdown(msrs);
free_msrs();
}
static void nmi_cpu_start(void *dummy)
{
- struct op_msrs const *msrs = &cpu_msrs[smp_processor_id()];
+ struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
model->start(msrs);
}
static void nmi_cpu_stop(void *dummy)
{
- struct op_msrs const *msrs = &cpu_msrs[smp_processor_id()];
+ struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
model->stop(msrs);
}
static void
get_current_resources(struct acpi_device *device, int busnum,
- struct pci_bus *bus)
+ int domain, struct pci_bus *bus)
{
struct pci_root_info info;
size_t size;
if (!info.res)
goto res_alloc_fail;
- info.name = kmalloc(12, GFP_KERNEL);
+ info.name = kmalloc(16, GFP_KERNEL);
if (!info.name)
goto name_alloc_fail;
- sprintf(info.name, "PCI Bus #%02x", busnum);
+ sprintf(info.name, "PCI Bus %04x:%02x", domain, busnum);
info.res_num = 0;
acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource,
#endif
if (bus && (pci_probe & PCI_USE__CRS))
- get_current_resources(device, busnum, bus);
+ get_current_resources(device, busnum, domain, bus);
return bus;
}
printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
for_each_pci_dev(dev)
acpi_pci_irq_enable(dev);
- } else
- printk(KERN_INFO "PCI: If a device doesn't work, try \"pci=routeirq\". If it helps, post a report\n");
+ }
#ifdef CONFIG_X86_IO_APIC
if (acpi_ioapic)
*/
DEFINE_SPINLOCK(pci_config_lock);
-/*
- * Several buggy motherboards address only 16 devices and mirror
- * them to next 16 IDs. We try to detect this `feature' on all
- * primary buses (those containing host bridges as they are
- * expected to be unique) and remove the ghost devices.
- */
-
-static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
-{
- struct list_head *ln, *mn;
- struct pci_dev *d, *e;
- int mirror = PCI_DEVFN(16,0);
- int seen_host_bridge = 0;
- int i;
-
- DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
- list_for_each(ln, &b->devices) {
- d = pci_dev_b(ln);
- if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
- seen_host_bridge++;
- for (mn=ln->next; mn != &b->devices; mn=mn->next) {
- e = pci_dev_b(mn);
- if (e->devfn != d->devfn + mirror ||
- e->vendor != d->vendor ||
- e->device != d->device ||
- e->class != d->class)
- continue;
- for(i=0; i<PCI_NUM_RESOURCES; i++)
- if (e->resource[i].start != d->resource[i].start ||
- e->resource[i].end != d->resource[i].end ||
- e->resource[i].flags != d->resource[i].flags)
- continue;
- break;
- }
- if (mn == &b->devices)
- return;
- }
- if (!seen_host_bridge)
- return;
- printk(KERN_WARNING "PCI: Ignoring ghost devices on bus %02x\n", b->number);
-
- ln = &b->devices;
- while (ln->next != &b->devices) {
- d = pci_dev_b(ln->next);
- if (d->devfn >= mirror) {
- list_del(&d->global_list);
- list_del(&d->bus_list);
- kfree(d);
- } else
- ln = ln->next;
- }
-}
-
static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
{
struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
{
struct pci_dev *dev;
- pcibios_fixup_ghosts(b);
pci_read_bridge_bases(b);
list_for_each_entry(dev, &b->devices, bus_list)
pcibios_fixup_device_resources(dev);
if (pci_bf_sort >= pci_force_bf)
pci_sort_breadthfirst();
-#ifdef CONFIG_PCI_BIOS
- if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
- pcibios_sort();
-#endif
return 0;
}
} else if (!strcmp(str, "nobios")) {
pci_probe &= ~PCI_PROBE_BIOS;
return NULL;
- } else if (!strcmp(str, "nosort")) {
- pci_probe |= PCI_NO_SORT;
- return NULL;
} else if (!strcmp(str, "biosirq")) {
pci_probe |= PCI_BIOS_IRQ_SCAN;
return NULL;
{
int err;
- if ((err = pcibios_enable_resources(dev, mask)) < 0)
+ if ((err = pci_enable_resources(dev, mask)) < 0)
return err;
if (!dev->msi_enabled)
*/
fs_initcall(pcibios_assign_resources);
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1 << idx)))
- continue;
-
- r = &dev->resource[idx];
- if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
- continue;
- if ((idx == PCI_ROM_RESOURCE) &&
- (!(r->flags & IORESOURCE_ROM_ENABLE)))
- continue;
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available "
- "because of resource %d collisions\n",
- pci_name(dev), idx);
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
/*
* If we set up a device for bus mastering, we need to check the latency
* timer as certain crappy BIOSes forget to set it properly.
return 0;
}
-static int __devinit pci_bios_find_device (unsigned short vendor, unsigned short device_id,
- unsigned short index, unsigned char *bus, unsigned char *device_fn)
-{
- unsigned short bx;
- unsigned short ret;
-
- __asm__("lcall *(%%edi); cld\n\t"
- "jc 1f\n\t"
- "xor %%ah, %%ah\n"
- "1:"
- : "=b" (bx),
- "=a" (ret)
- : "1" (PCIBIOS_FIND_PCI_DEVICE),
- "c" (device_id),
- "d" (vendor),
- "S" ((int) index),
- "D" (&pci_indirect));
- *bus = (bx >> 8) & 0xff;
- *device_fn = bx & 0xff;
- return (int) (ret & 0xff00) >> 8;
-}
-
static int pci_bios_read(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 *value)
{
return NULL;
}
-/*
- * Sort the device list according to PCI BIOS. Nasty hack, but since some
- * fool forgot to define the `correct' device order in the PCI BIOS specs
- * and we want to be (possibly bug-to-bug ;-]) compatible with older kernels
- * which used BIOS ordering, we are bound to do this...
- */
-
-void __devinit pcibios_sort(void)
-{
- LIST_HEAD(sorted_devices);
- struct list_head *ln;
- struct pci_dev *dev, *d;
- int idx, found;
- unsigned char bus, devfn;
-
- DBG("PCI: Sorting device list...\n");
- while (!list_empty(&pci_devices)) {
- ln = pci_devices.next;
- dev = pci_dev_g(ln);
- idx = found = 0;
- while (pci_bios_find_device(dev->vendor, dev->device, idx, &bus, &devfn) == PCIBIOS_SUCCESSFUL) {
- idx++;
- list_for_each(ln, &pci_devices) {
- d = pci_dev_g(ln);
- if (d->bus->number == bus && d->devfn == devfn) {
- list_move_tail(&d->global_list, &sorted_devices);
- if (d == dev)
- found = 1;
- break;
- }
- }
- if (ln == &pci_devices) {
- printk(KERN_WARNING "PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
- /*
- * We must not continue scanning as several buggy BIOSes
- * return garbage after the last device. Grr.
- */
- break;
- }
- }
- if (!found) {
- printk(KERN_WARNING "PCI: Device %s not found by BIOS\n",
- pci_name(dev));
- list_move_tail(&dev->global_list, &sorted_devices);
- }
- }
- list_splice(&sorted_devices, &pci_devices);
-}
-
/*
* BIOS Functions for IRQ Routing
*/
{
if ((pci_probe & PCI_PROBE_BIOS)
&& ((raw_pci_ops = pci_find_bios()))) {
- pci_probe |= PCI_BIOS_SORT;
pci_bios_present = 1;
}
}
#define PCI_PROBE_MASK 0x000f
#define PCI_PROBE_NOEARLY 0x0010
-#define PCI_NO_SORT 0x0100
-#define PCI_BIOS_SORT 0x0200
#define PCI_NO_CHECKS 0x0400
#define PCI_USE_PIRQ_MASK 0x0800
#define PCI_ASSIGN_ROMS 0x1000
extern unsigned int pcibios_max_latency;
void pcibios_resource_survey(void);
-int pcibios_enable_resources(struct pci_dev *, int);
/* pci-pc.c */
extern void pci_direct_init(int type);
extern void pci_pcbios_init(void);
extern void pci_mmcfg_init(int type);
-extern void pcibios_sort(void);
/* pci-mmconfig.c */
$(obj)/%.so: $(obj)/%.so.dbg FORCE
$(call if_changed,objcopy)
-CFL := $(PROFILING) -mcmodel=small -fPIC -g0 -O2 -fasynchronous-unwind-tables -m64
+CFL := $(PROFILING) -mcmodel=small -fPIC -O2 -fasynchronous-unwind-tables -m64 \
+ $(filter -g%,$(KBUILD_CFLAGS))
$(vobjs): KBUILD_CFLAGS += $(CFL)
/*
- * arch/i386/video/fbdev.c - i386 Framebuffer
*
* Copyright (C) 2007 Antonino Daplas <adaplas@gmail.com>
*
bool "Enable the block layer" if EMBEDDED
default y
help
- This permits the block layer to be removed from the kernel if it's not
- needed (on some embedded devices for example). If this option is
- disabled, then blockdev files will become unusable and some
- filesystems (such as ext3) will become unavailable.
+ Provide block layer support for the kernel.
- This option will also disable SCSI character devices and USB storage
- since they make use of various block layer definitions and
- facilities.
+ Disable this option to remove the block layer support from the
+ kernel. This may be useful for embedded devices.
+
+ If this option is disabled:
+
+ - block device files will become unusable
+ - some filesystems (such as ext3) will become unavailable.
+
+ Also, SCSI character devices and USB storage will be disabled since
+ they make use of various block layer definitions and facilities.
Say Y here unless you know you really don't want to mount disks and
suchlike.
bool "Support for Large Block Devices"
depends on !64BIT
help
- Say Y here if you want to attach large (bigger than 2TB) discs to
- your machine, or if you want to have a raid or loopback device
- bigger than 2TB. Otherwise say N.
+ Enable block devices of size 2TB and larger.
+
+ This option is required to support the full capacity of large
+ (2TB+) block devices, including RAID, disk, Network Block Device,
+ Logical Volume Manager (LVM) and loopback.
+
+ For example, RAID devices are frequently bigger than the capacity
+ of the largest individual hard drive.
+
+ This option is not required if you have individual disk drives
+ which total 2TB+ and you are not aggregating the capacity into
+ a large block device (e.g. using RAID or LVM).
+
+ If unsure, say N.
config BLK_DEV_IO_TRACE
bool "Support for tracing block io actions"
select RELAY
select DEBUG_FS
help
- Say Y here, if you want to be able to trace the block layer actions
+ Say Y here if you want to be able to trace the block layer actions
on a given queue. Tracing allows you to see any traffic happening
- on a block device queue. For more information (and the user space
- support tools needed), fetch the blktrace app from:
+ on a block device queue. For more information (and the userspace
+ support tools needed), fetch the blktrace tools from:
git://git.kernel.dk/blktrace.git
+ If unsure, say N.
+
config LSF
bool "Support for Large Single Files"
depends on !64BIT
help
- Say Y here if you want to be able to handle very large files (bigger
- than 2TB), otherwise say N.
+ Say Y here if you want to be able to handle very large files (2TB
+ and larger), otherwise say N.
If unsure, say Y.
bool "Block layer SG support v4 (EXPERIMENTAL)"
depends on EXPERIMENTAL
---help---
- Saying Y here will enable generic SG (SCSI generic) v4 support
- for any block device.
-
- Unlike SG v3 (aka block/scsi_ioctl.c drivers/scsi/sg.c), SG v4
- can handle complicated SCSI commands: tagged variable length cdbs
- with bidirectional data transfers and generic request/response
- protocols (e.g. Task Management Functions and SMP in Serial
- Attached SCSI).
+ Saying Y here will enable generic SG (SCSI generic) v4 support
+ for any block device.
+
+ Unlike SG v3 (aka block/scsi_ioctl.c drivers/scsi/sg.c), SG v4
+ can handle complicated SCSI commands: tagged variable length cdbs
+ with bidirectional data transfers and generic request/response
+ protocols (e.g. Task Management Functions and SMP in Serial
+ Attached SCSI).
+
+ If unsure, say N.
endif # BLOCK
#include <linux/module.h>
#include <linux/bio.h>
#include <linux/blkdev.h>
+#include <scsi/sg.h> /* for struct sg_iovec */
#include "blk.h"
ubuf += ret;
}
- /*
- * __blk_rq_map_user() copies the buffers if starting address
- * or length isn't aligned to dma_pad_mask. As the copied
- * buffer is always page aligned, we know that there's enough
- * room for padding. Extend the last bio and update
- * rq->data_len accordingly.
- *
- * On unmap, bio_uncopy_user() will use unmodified
- * bio_map_data pointed to by bio->bi_private.
- */
- if (len & q->dma_pad_mask) {
- unsigned int pad_len = (q->dma_pad_mask & ~len) + 1;
- struct bio *tail = rq->biotail;
-
- tail->bi_io_vec[tail->bi_vcnt - 1].bv_len += pad_len;
- tail->bi_size += pad_len;
-
- rq->extra_len += pad_len;
- }
+ if (!bio_flagged(bio, BIO_USER_MAPPED))
+ rq->cmd_flags |= REQ_COPY_USER;
rq->buffer = rq->data = NULL;
return 0;
struct sg_iovec *iov, int iov_count, unsigned int len)
{
struct bio *bio;
+ int i, read = rq_data_dir(rq) == READ;
+ int unaligned = 0;
if (!iov || iov_count <= 0)
return -EINVAL;
- /* we don't allow misaligned data like bio_map_user() does. If the
- * user is using sg, they're expected to know the alignment constraints
- * and respect them accordingly */
- bio = bio_map_user_iov(q, NULL, iov, iov_count,
- rq_data_dir(rq) == READ);
+ for (i = 0; i < iov_count; i++) {
+ unsigned long uaddr = (unsigned long)iov[i].iov_base;
+
+ if (uaddr & queue_dma_alignment(q)) {
+ unaligned = 1;
+ break;
+ }
+ }
+
+ if (unaligned || (q->dma_pad_mask & len))
+ bio = bio_copy_user_iov(q, iov, iov_count, read);
+ else
+ bio = bio_map_user_iov(q, NULL, iov, iov_count, read);
+
if (IS_ERR(bio))
return PTR_ERR(bio);
return -EINVAL;
}
+ if (!bio_flagged(bio, BIO_USER_MAPPED))
+ rq->cmd_flags |= REQ_COPY_USER;
+
bio_get(bio);
blk_rq_bio_prep(q, rq, bio);
rq->buffer = rq->data = NULL;
bvprv = bvec;
} /* segments in rq */
+
+ if (unlikely(rq->cmd_flags & REQ_COPY_USER) &&
+ (rq->data_len & q->dma_pad_mask)) {
+ unsigned int pad_len = (q->dma_pad_mask & ~rq->data_len) + 1;
+
+ sg->length += pad_len;
+ rq->extra_len += pad_len;
+ }
+
if (q->dma_drain_size && q->dma_drain_needed(rq)) {
if (rq->cmd_flags & REQ_RW)
memset(q->dma_drain_buffer, 0, q->dma_drain_size);
struct request_queue *q = disk->queue;
- if (!q || !q->request_fn)
+ if (WARN_ON(!q))
return -ENXIO;
+ if (!q->request_fn)
+ return 0;
+
ret = kobject_add(&q->kobj, kobject_get(&disk->dev.kobj),
"%s", "queue");
if (ret < 0)
{
struct request_queue *q = disk->queue;
- if (q && q->request_fn) {
+ if (WARN_ON(!q))
+ return;
+
+ if (q->request_fn) {
elv_unregister_queue(q);
kobject_uevent(&q->kobj, KOBJ_REMOVE);
mutex_lock(&bsg_mutex);
hlist_add_head(&bd->dev_list, bsg_dev_idx_hash(iminor(inode)));
- strncpy(bd->name, rq->bsg_dev.class_dev->class_id, sizeof(bd->name) - 1);
+ strncpy(bd->name, rq->bsg_dev.class_dev->bus_id, sizeof(bd->name) - 1);
dprintk("bound to <%s>, max queue %d\n",
format_dev_t(buf, inode->i_rdev), bd->max_queue);
mutex_lock(&bsg_mutex);
idr_remove(&bsg_minor_idr, bcd->minor);
sysfs_remove_link(&q->kobj, "bsg");
- class_device_unregister(bcd->class_dev);
+ device_unregister(bcd->class_dev);
put_device(bcd->dev);
bcd->class_dev = NULL;
mutex_unlock(&bsg_mutex);
struct bsg_class_device *bcd;
dev_t dev;
int ret, minor;
- struct class_device *class_dev = NULL;
+ struct device *class_dev = NULL;
const char *devname;
if (name)
bcd->queue = q;
bcd->dev = get_device(gdev);
dev = MKDEV(bsg_major, bcd->minor);
- class_dev = class_device_create(bsg_class, NULL, dev, gdev, "%s",
- devname);
+ class_dev = device_create(bsg_class, gdev, dev, "%s", devname);
if (IS_ERR(class_dev)) {
ret = PTR_ERR(class_dev);
goto put_dev;
return 0;
unregister_class_dev:
- class_device_unregister(class_dev);
+ device_unregister(class_dev);
put_dev:
put_device(gdev);
remove_idr:
# Cryptographic API Configuration
#
menuconfig CRYPTO
- bool "Cryptographic API"
+ tristate "Cryptographic API"
help
This option provides the core Cryptographic API.
if CRYPTO
+comment "Crypto core or helper"
+
config CRYPTO_ALGAPI
tristate
help
tristate
select CRYPTO_ALGAPI
-config CRYPTO_SEQIV
- tristate "Sequence Number IV Generator"
- select CRYPTO_AEAD
- select CRYPTO_BLKCIPHER
- help
- This IV generator generates an IV based on a sequence number by
- xoring it with a salt. This algorithm is mainly useful for CTR
- and similar modes.
-
config CRYPTO_HASH
tristate
select CRYPTO_ALGAPI
Create default cryptographic template instantiations such as
cbc(aes).
-config CRYPTO_HMAC
- tristate "HMAC support"
- select CRYPTO_HASH
- select CRYPTO_MANAGER
- help
- HMAC: Keyed-Hashing for Message Authentication (RFC2104).
- This is required for IPSec.
-
-config CRYPTO_XCBC
- tristate "XCBC support"
+config CRYPTO_GF128MUL
+ tristate "GF(2^128) multiplication functions (EXPERIMENTAL)"
depends on EXPERIMENTAL
- select CRYPTO_HASH
- select CRYPTO_MANAGER
help
- XCBC: Keyed-Hashing with encryption algorithm
- http://www.ietf.org/rfc/rfc3566.txt
- http://csrc.nist.gov/encryption/modes/proposedmodes/
- xcbc-mac/xcbc-mac-spec.pdf
+ Efficient table driven implementation of multiplications in the
+ field GF(2^128). This is needed by some cypher modes. This
+ option will be selected automatically if you select such a
+ cipher mode. Only select this option by hand if you expect to load
+ an external module that requires these functions.
config CRYPTO_NULL
tristate "Null algorithms"
help
These are 'Null' algorithms, used by IPsec, which do nothing.
-config CRYPTO_MD4
- tristate "MD4 digest algorithm"
- select CRYPTO_ALGAPI
- help
- MD4 message digest algorithm (RFC1320).
-
-config CRYPTO_MD5
- tristate "MD5 digest algorithm"
- select CRYPTO_ALGAPI
+config CRYPTO_CRYPTD
+ tristate "Software async crypto daemon"
+ select CRYPTO_BLKCIPHER
+ select CRYPTO_MANAGER
help
- MD5 message digest algorithm (RFC1321).
+ This is a generic software asynchronous crypto daemon that
+ converts an arbitrary synchronous software crypto algorithm
+ into an asynchronous algorithm that executes in a kernel thread.
-config CRYPTO_SHA1
- tristate "SHA1 digest algorithm"
- select CRYPTO_ALGAPI
+config CRYPTO_AUTHENC
+ tristate "Authenc support"
+ select CRYPTO_AEAD
+ select CRYPTO_BLKCIPHER
+ select CRYPTO_MANAGER
+ select CRYPTO_HASH
help
- SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
+ Authenc: Combined mode wrapper for IPsec.
+ This is required for IPSec.
-config CRYPTO_SHA256
- tristate "SHA224 and SHA256 digest algorithm"
+config CRYPTO_TEST
+ tristate "Testing module"
+ depends on m
select CRYPTO_ALGAPI
+ select CRYPTO_AEAD
+ select CRYPTO_BLKCIPHER
help
- SHA256 secure hash standard (DFIPS 180-2).
-
- This version of SHA implements a 256 bit hash with 128 bits of
- security against collision attacks.
+ Quick & dirty crypto test module.
- This code also includes SHA-224, a 224 bit hash with 112 bits
- of security against collision attacks.
+comment "Authenticated Encryption with Associated Data"
-config CRYPTO_SHA512
- tristate "SHA384 and SHA512 digest algorithms"
- select CRYPTO_ALGAPI
+config CRYPTO_CCM
+ tristate "CCM support"
+ select CRYPTO_CTR
+ select CRYPTO_AEAD
help
- SHA512 secure hash standard (DFIPS 180-2).
-
- This version of SHA implements a 512 bit hash with 256 bits of
- security against collision attacks.
-
- This code also includes SHA-384, a 384 bit hash with 192 bits
- of security against collision attacks.
+ Support for Counter with CBC MAC. Required for IPsec.
-config CRYPTO_WP512
- tristate "Whirlpool digest algorithms"
- select CRYPTO_ALGAPI
+config CRYPTO_GCM
+ tristate "GCM/GMAC support"
+ select CRYPTO_CTR
+ select CRYPTO_AEAD
+ select CRYPTO_GF128MUL
help
- Whirlpool hash algorithm 512, 384 and 256-bit hashes
-
- Whirlpool-512 is part of the NESSIE cryptographic primitives.
- Whirlpool will be part of the ISO/IEC 10118-3:2003(E) standard
-
- See also:
- <http://planeta.terra.com.br/informatica/paulobarreto/WhirlpoolPage.html>
+ Support for Galois/Counter Mode (GCM) and Galois Message
+ Authentication Code (GMAC). Required for IPSec.
-config CRYPTO_TGR192
- tristate "Tiger digest algorithms"
- select CRYPTO_ALGAPI
+config CRYPTO_SEQIV
+ tristate "Sequence Number IV Generator"
+ select CRYPTO_AEAD
+ select CRYPTO_BLKCIPHER
help
- Tiger hash algorithm 192, 160 and 128-bit hashes
-
- Tiger is a hash function optimized for 64-bit processors while
- still having decent performance on 32-bit processors.
- Tiger was developed by Ross Anderson and Eli Biham.
+ This IV generator generates an IV based on a sequence number by
+ xoring it with a salt. This algorithm is mainly useful for CTR
- See also:
- <http://www.cs.technion.ac.il/~biham/Reports/Tiger/>.
+comment "Block modes"
-config CRYPTO_GF128MUL
- tristate "GF(2^128) multiplication functions (EXPERIMENTAL)"
- depends on EXPERIMENTAL
- help
- Efficient table driven implementation of multiplications in the
- field GF(2^128). This is needed by some cypher modes. This
- option will be selected automatically if you select such a
- cipher mode. Only select this option by hand if you expect to load
- an external module that requires these functions.
-
-config CRYPTO_ECB
- tristate "ECB support"
+config CRYPTO_CBC
+ tristate "CBC support"
select CRYPTO_BLKCIPHER
select CRYPTO_MANAGER
help
- ECB: Electronic CodeBook mode
- This is the simplest block cipher algorithm. It simply encrypts
- the input block by block.
+ CBC: Cipher Block Chaining mode
+ This block cipher algorithm is required for IPSec.
-config CRYPTO_CBC
- tristate "CBC support"
+config CRYPTO_CTR
+ tristate "CTR support"
select CRYPTO_BLKCIPHER
+ select CRYPTO_SEQIV
select CRYPTO_MANAGER
help
- CBC: Cipher Block Chaining mode
+ CTR: Counter mode
This block cipher algorithm is required for IPSec.
-config CRYPTO_PCBC
- tristate "PCBC support"
+config CRYPTO_CTS
+ tristate "CTS support"
+ select CRYPTO_BLKCIPHER
+ help
+ CTS: Cipher Text Stealing
+ This is the Cipher Text Stealing mode as described by
+ Section 8 of rfc2040 and referenced by rfc3962.
+ (rfc3962 includes errata information in its Appendix A)
+ This mode is required for Kerberos gss mechanism support
+ for AES encryption.
+
+config CRYPTO_ECB
+ tristate "ECB support"
select CRYPTO_BLKCIPHER
select CRYPTO_MANAGER
help
- PCBC: Propagating Cipher Block Chaining mode
- This block cipher algorithm is required for RxRPC.
+ ECB: Electronic CodeBook mode
+ This is the simplest block cipher algorithm. It simply encrypts
+ the input block by block.
config CRYPTO_LRW
tristate "LRW support (EXPERIMENTAL)"
The first 128, 192 or 256 bits in the key are used for AES and the
rest is used to tie each cipher block to its logical position.
+config CRYPTO_PCBC
+ tristate "PCBC support"
+ select CRYPTO_BLKCIPHER
+ select CRYPTO_MANAGER
+ help
+ PCBC: Propagating Cipher Block Chaining mode
+ This block cipher algorithm is required for RxRPC.
+
config CRYPTO_XTS
tristate "XTS support (EXPERIMENTAL)"
depends on EXPERIMENTAL
key size 256, 384 or 512 bits. This implementation currently
can't handle a sectorsize which is not a multiple of 16 bytes.
-config CRYPTO_CTR
- tristate "CTR support"
- select CRYPTO_BLKCIPHER
- select CRYPTO_SEQIV
+comment "Hash modes"
+
+config CRYPTO_HMAC
+ tristate "HMAC support"
+ select CRYPTO_HASH
select CRYPTO_MANAGER
help
- CTR: Counter mode
- This block cipher algorithm is required for IPSec.
+ HMAC: Keyed-Hashing for Message Authentication (RFC2104).
+ This is required for IPSec.
-config CRYPTO_GCM
- tristate "GCM/GMAC support"
- select CRYPTO_CTR
- select CRYPTO_AEAD
- select CRYPTO_GF128MUL
+config CRYPTO_XCBC
+ tristate "XCBC support"
+ depends on EXPERIMENTAL
+ select CRYPTO_HASH
+ select CRYPTO_MANAGER
help
- Support for Galois/Counter Mode (GCM) and Galois Message
- Authentication Code (GMAC). Required for IPSec.
+ XCBC: Keyed-Hashing with encryption algorithm
+ http://www.ietf.org/rfc/rfc3566.txt
+ http://csrc.nist.gov/encryption/modes/proposedmodes/
+ xcbc-mac/xcbc-mac-spec.pdf
-config CRYPTO_CCM
- tristate "CCM support"
- select CRYPTO_CTR
- select CRYPTO_AEAD
- help
- Support for Counter with CBC MAC. Required for IPsec.
+comment "Digest"
-config CRYPTO_CRYPTD
- tristate "Software async crypto daemon"
- select CRYPTO_BLKCIPHER
- select CRYPTO_MANAGER
+config CRYPTO_CRC32C
+ tristate "CRC32c CRC algorithm"
+ select CRYPTO_ALGAPI
+ select LIBCRC32C
help
- This is a generic software asynchronous crypto daemon that
- converts an arbitrary synchronous software crypto algorithm
- into an asynchronous algorithm that executes in a kernel thread.
+ Castagnoli, et al Cyclic Redundancy-Check Algorithm. Used
+ by iSCSI for header and data digests and by others.
+ See Castagnoli93. This implementation uses lib/libcrc32c.
+ Module will be crc32c.
-config CRYPTO_DES
- tristate "DES and Triple DES EDE cipher algorithms"
+config CRYPTO_MD4
+ tristate "MD4 digest algorithm"
select CRYPTO_ALGAPI
help
- DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
+ MD4 message digest algorithm (RFC1320).
-config CRYPTO_FCRYPT
- tristate "FCrypt cipher algorithm"
+config CRYPTO_MD5
+ tristate "MD5 digest algorithm"
select CRYPTO_ALGAPI
- select CRYPTO_BLKCIPHER
help
- FCrypt algorithm used by RxRPC.
+ MD5 message digest algorithm (RFC1321).
-config CRYPTO_BLOWFISH
- tristate "Blowfish cipher algorithm"
+config CRYPTO_MICHAEL_MIC
+ tristate "Michael MIC keyed digest algorithm"
select CRYPTO_ALGAPI
help
- Blowfish cipher algorithm, by Bruce Schneier.
-
- This is a variable key length cipher which can use keys from 32
- bits to 448 bits in length. It's fast, simple and specifically
- designed for use on "large microprocessors".
-
- See also:
- <http://www.schneier.com/blowfish.html>
+ Michael MIC is used for message integrity protection in TKIP
+ (IEEE 802.11i). This algorithm is required for TKIP, but it
+ should not be used for other purposes because of the weakness
+ of the algorithm.
-config CRYPTO_TWOFISH
- tristate "Twofish cipher algorithm"
+config CRYPTO_SHA1
+ tristate "SHA1 digest algorithm"
select CRYPTO_ALGAPI
- select CRYPTO_TWOFISH_COMMON
help
- Twofish cipher algorithm.
-
- Twofish was submitted as an AES (Advanced Encryption Standard)
- candidate cipher by researchers at CounterPane Systems. It is a
- 16 round block cipher supporting key sizes of 128, 192, and 256
- bits.
-
- See also:
- <http://www.schneier.com/twofish.html>
+ SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
-config CRYPTO_TWOFISH_COMMON
- tristate
+config CRYPTO_SHA256
+ tristate "SHA224 and SHA256 digest algorithm"
+ select CRYPTO_ALGAPI
help
- Common parts of the Twofish cipher algorithm shared by the
- generic c and the assembler implementations.
+ SHA256 secure hash standard (DFIPS 180-2).
-config CRYPTO_TWOFISH_586
- tristate "Twofish cipher algorithms (i586)"
- depends on (X86 || UML_X86) && !64BIT
+ This version of SHA implements a 256 bit hash with 128 bits of
+ security against collision attacks.
+
+ This code also includes SHA-224, a 224 bit hash with 112 bits
+ of security against collision attacks.
+
+config CRYPTO_SHA512
+ tristate "SHA384 and SHA512 digest algorithms"
select CRYPTO_ALGAPI
- select CRYPTO_TWOFISH_COMMON
help
- Twofish cipher algorithm.
+ SHA512 secure hash standard (DFIPS 180-2).
- Twofish was submitted as an AES (Advanced Encryption Standard)
- candidate cipher by researchers at CounterPane Systems. It is a
- 16 round block cipher supporting key sizes of 128, 192, and 256
- bits.
+ This version of SHA implements a 512 bit hash with 256 bits of
+ security against collision attacks.
- See also:
- <http://www.schneier.com/twofish.html>
+ This code also includes SHA-384, a 384 bit hash with 192 bits
+ of security against collision attacks.
-config CRYPTO_TWOFISH_X86_64
- tristate "Twofish cipher algorithm (x86_64)"
- depends on (X86 || UML_X86) && 64BIT
+config CRYPTO_TGR192
+ tristate "Tiger digest algorithms"
select CRYPTO_ALGAPI
- select CRYPTO_TWOFISH_COMMON
help
- Twofish cipher algorithm (x86_64).
+ Tiger hash algorithm 192, 160 and 128-bit hashes
- Twofish was submitted as an AES (Advanced Encryption Standard)
- candidate cipher by researchers at CounterPane Systems. It is a
- 16 round block cipher supporting key sizes of 128, 192, and 256
- bits.
+ Tiger is a hash function optimized for 64-bit processors while
+ still having decent performance on 32-bit processors.
+ Tiger was developed by Ross Anderson and Eli Biham.
See also:
- <http://www.schneier.com/twofish.html>
+ <http://www.cs.technion.ac.il/~biham/Reports/Tiger/>.
-config CRYPTO_SERPENT
- tristate "Serpent cipher algorithm"
+config CRYPTO_WP512
+ tristate "Whirlpool digest algorithms"
select CRYPTO_ALGAPI
help
- Serpent cipher algorithm, by Anderson, Biham & Knudsen.
+ Whirlpool hash algorithm 512, 384 and 256-bit hashes
- Keys are allowed to be from 0 to 256 bits in length, in steps
- of 8 bits. Also includes the 'Tnepres' algorithm, a reversed
- variant of Serpent for compatibility with old kerneli.org code.
+ Whirlpool-512 is part of the NESSIE cryptographic primitives.
+ Whirlpool will be part of the ISO/IEC 10118-3:2003(E) standard
See also:
- <http://www.cl.cam.ac.uk/~rja14/serpent.html>
+ <http://planeta.terra.com.br/informatica/paulobarreto/WhirlpoolPage.html>
+
+comment "Ciphers"
config CRYPTO_AES
tristate "AES cipher algorithms"
select CRYPTO_ALGAPI
help
- AES cipher algorithms (FIPS-197). AES uses the Rijndael
+ AES cipher algorithms (FIPS-197). AES uses the Rijndael
algorithm.
Rijndael appears to be consistently a very good performer in
- both hardware and software across a wide range of computing
- environments regardless of its use in feedback or non-feedback
- modes. Its key setup time is excellent, and its key agility is
- good. Rijndael's very low memory requirements make it very well
- suited for restricted-space environments, in which it also
- demonstrates excellent performance. Rijndael's operations are
- among the easiest to defend against power and timing attacks.
+ both hardware and software across a wide range of computing
+ environments regardless of its use in feedback or non-feedback
+ modes. Its key setup time is excellent, and its key agility is
+ good. Rijndael's very low memory requirements make it very well
+ suited for restricted-space environments, in which it also
+ demonstrates excellent performance. Rijndael's operations are
+ among the easiest to defend against power and timing attacks.
- The AES specifies three key sizes: 128, 192 and 256 bits
+ The AES specifies three key sizes: 128, 192 and 256 bits
See <http://csrc.nist.gov/CryptoToolkit/aes/> for more information.
select CRYPTO_ALGAPI
select CRYPTO_AES
help
- AES cipher algorithms (FIPS-197). AES uses the Rijndael
+ AES cipher algorithms (FIPS-197). AES uses the Rijndael
algorithm.
Rijndael appears to be consistently a very good performer in
- both hardware and software across a wide range of computing
- environments regardless of its use in feedback or non-feedback
- modes. Its key setup time is excellent, and its key agility is
- good. Rijndael's very low memory requirements make it very well
- suited for restricted-space environments, in which it also
- demonstrates excellent performance. Rijndael's operations are
- among the easiest to defend against power and timing attacks.
+ both hardware and software across a wide range of computing
+ environments regardless of its use in feedback or non-feedback
+ modes. Its key setup time is excellent, and its key agility is
+ good. Rijndael's very low memory requirements make it very well
+ suited for restricted-space environments, in which it also
+ demonstrates excellent performance. Rijndael's operations are
+ among the easiest to defend against power and timing attacks.
- The AES specifies three key sizes: 128, 192 and 256 bits
+ The AES specifies three key sizes: 128, 192 and 256 bits
See <http://csrc.nist.gov/encryption/aes/> for more information.
select CRYPTO_ALGAPI
select CRYPTO_AES
help
- AES cipher algorithms (FIPS-197). AES uses the Rijndael
+ AES cipher algorithms (FIPS-197). AES uses the Rijndael
algorithm.
Rijndael appears to be consistently a very good performer in
- both hardware and software across a wide range of computing
- environments regardless of its use in feedback or non-feedback
- modes. Its key setup time is excellent, and its key agility is
- good. Rijndael's very low memory requirements make it very well
- suited for restricted-space environments, in which it also
- demonstrates excellent performance. Rijndael's operations are
- among the easiest to defend against power and timing attacks.
+ both hardware and software across a wide range of computing
+ environments regardless of its use in feedback or non-feedback
+ modes. Its key setup time is excellent, and its key agility is
+ good. Rijndael's very low memory requirements make it very well
+ suited for restricted-space environments, in which it also
+ demonstrates excellent performance. Rijndael's operations are
+ among the easiest to defend against power and timing attacks.
- The AES specifies three key sizes: 128, 192 and 256 bits
+ The AES specifies three key sizes: 128, 192 and 256 bits
See <http://csrc.nist.gov/encryption/aes/> for more information.
+config CRYPTO_ANUBIS
+ tristate "Anubis cipher algorithm"
+ select CRYPTO_ALGAPI
+ help
+ Anubis cipher algorithm.
+
+ Anubis is a variable key length cipher which can use keys from
+ 128 bits to 320 bits in length. It was evaluated as a entrant
+ in the NESSIE competition.
+
+ See also:
+ <https://www.cosic.esat.kuleuven.ac.be/nessie/reports/>
+ <http://planeta.terra.com.br/informatica/paulobarreto/AnubisPage.html>
+
+config CRYPTO_ARC4
+ tristate "ARC4 cipher algorithm"
+ select CRYPTO_ALGAPI
+ help
+ ARC4 cipher algorithm.
+
+ ARC4 is a stream cipher using keys ranging from 8 bits to 2048
+ bits in length. This algorithm is required for driver-based
+ WEP, but it should not be for other purposes because of the
+ weakness of the algorithm.
+
+config CRYPTO_BLOWFISH
+ tristate "Blowfish cipher algorithm"
+ select CRYPTO_ALGAPI
+ help
+ Blowfish cipher algorithm, by Bruce Schneier.
+
+ This is a variable key length cipher which can use keys from 32
+ bits to 448 bits in length. It's fast, simple and specifically
+ designed for use on "large microprocessors".
+
+ See also:
+ <http://www.schneier.com/blowfish.html>
+
+config CRYPTO_CAMELLIA
+ tristate "Camellia cipher algorithms"
+ depends on CRYPTO
+ select CRYPTO_ALGAPI
+ help
+ Camellia cipher algorithms module.
+
+ Camellia is a symmetric key block cipher developed jointly
+ at NTT and Mitsubishi Electric Corporation.
+
+ The Camellia specifies three key sizes: 128, 192 and 256 bits.
+
+ See also:
+ <https://info.isl.ntt.co.jp/crypt/eng/camellia/index_s.html>
+
config CRYPTO_CAST5
tristate "CAST5 (CAST-128) cipher algorithm"
select CRYPTO_ALGAPI
The CAST6 encryption algorithm (synonymous with CAST-256) is
described in RFC2612.
-config CRYPTO_TEA
- tristate "TEA, XTEA and XETA cipher algorithms"
+config CRYPTO_DES
+ tristate "DES and Triple DES EDE cipher algorithms"
select CRYPTO_ALGAPI
help
- TEA cipher algorithm.
-
- Tiny Encryption Algorithm is a simple cipher that uses
- many rounds for security. It is very fast and uses
- little memory.
-
- Xtendend Tiny Encryption Algorithm is a modification to
- the TEA algorithm to address a potential key weakness
- in the TEA algorithm.
-
- Xtendend Encryption Tiny Algorithm is a mis-implementation
- of the XTEA algorithm for compatibility purposes.
+ DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
-config CRYPTO_ARC4
- tristate "ARC4 cipher algorithm"
+config CRYPTO_FCRYPT
+ tristate "FCrypt cipher algorithm"
select CRYPTO_ALGAPI
+ select CRYPTO_BLKCIPHER
help
- ARC4 cipher algorithm.
-
- ARC4 is a stream cipher using keys ranging from 8 bits to 2048
- bits in length. This algorithm is required for driver-based
- WEP, but it should not be for other purposes because of the
- weakness of the algorithm.
+ FCrypt algorithm used by RxRPC.
config CRYPTO_KHAZAD
tristate "Khazad cipher algorithm"
See also:
<http://planeta.terra.com.br/informatica/paulobarreto/KhazadPage.html>
-config CRYPTO_ANUBIS
- tristate "Anubis cipher algorithm"
- select CRYPTO_ALGAPI
- help
- Anubis cipher algorithm.
-
- Anubis is a variable key length cipher which can use keys from
- 128 bits to 320 bits in length. It was evaluated as a entrant
- in the NESSIE competition.
-
- See also:
- <https://www.cosic.esat.kuleuven.ac.be/nessie/reports/>
- <http://planeta.terra.com.br/informatica/paulobarreto/AnubisPage.html>
-
-config CRYPTO_SEED
- tristate "SEED cipher algorithm"
- select CRYPTO_ALGAPI
- help
- SEED cipher algorithm (RFC4269).
-
- SEED is a 128-bit symmetric key block cipher that has been
- developed by KISA (Korea Information Security Agency) as a
- national standard encryption algorithm of the Republic of Korea.
- It is a 16 round block cipher with the key size of 128 bit.
-
- See also:
- <http://www.kisa.or.kr/kisa/seed/jsp/seed_eng.jsp>
-
config CRYPTO_SALSA20
tristate "Salsa20 stream cipher algorithm (EXPERIMENTAL)"
depends on EXPERIMENTAL
The Salsa20 stream cipher algorithm is designed by Daniel J.
Bernstein <djb@cr.yp.to>. See <http://cr.yp.to/snuffle.html>
-config CRYPTO_DEFLATE
- tristate "Deflate compression algorithm"
+config CRYPTO_SEED
+ tristate "SEED cipher algorithm"
select CRYPTO_ALGAPI
- select ZLIB_INFLATE
- select ZLIB_DEFLATE
help
- This is the Deflate algorithm (RFC1951), specified for use in
- IPSec with the IPCOMP protocol (RFC3173, RFC2394).
-
- You will most probably want this if using IPSec.
+ SEED cipher algorithm (RFC4269).
-config CRYPTO_MICHAEL_MIC
- tristate "Michael MIC keyed digest algorithm"
+ SEED is a 128-bit symmetric key block cipher that has been
+ developed by KISA (Korea Information Security Agency) as a
+ national standard encryption algorithm of the Republic of Korea.
+ It is a 16 round block cipher with the key size of 128 bit.
+
+ See also:
+ <http://www.kisa.or.kr/kisa/seed/jsp/seed_eng.jsp>
+
+config CRYPTO_SERPENT
+ tristate "Serpent cipher algorithm"
select CRYPTO_ALGAPI
help
- Michael MIC is used for message integrity protection in TKIP
- (IEEE 802.11i). This algorithm is required for TKIP, but it
- should not be used for other purposes because of the weakness
- of the algorithm.
+ Serpent cipher algorithm, by Anderson, Biham & Knudsen.
-config CRYPTO_CRC32C
- tristate "CRC32c CRC algorithm"
+ Keys are allowed to be from 0 to 256 bits in length, in steps
+ of 8 bits. Also includes the 'Tnepres' algorithm, a reversed
+ variant of Serpent for compatibility with old kerneli.org code.
+
+ See also:
+ <http://www.cl.cam.ac.uk/~rja14/serpent.html>
+
+config CRYPTO_TEA
+ tristate "TEA, XTEA and XETA cipher algorithms"
select CRYPTO_ALGAPI
- select LIBCRC32C
help
- Castagnoli, et al Cyclic Redundancy-Check Algorithm. Used
- by iSCSI for header and data digests and by others.
- See Castagnoli93. This implementation uses lib/libcrc32c.
- Module will be crc32c.
+ TEA cipher algorithm.
-config CRYPTO_CAMELLIA
- tristate "Camellia cipher algorithms"
- depends on CRYPTO
+ Tiny Encryption Algorithm is a simple cipher that uses
+ many rounds for security. It is very fast and uses
+ little memory.
+
+ Xtendend Tiny Encryption Algorithm is a modification to
+ the TEA algorithm to address a potential key weakness
+ in the TEA algorithm.
+
+ Xtendend Encryption Tiny Algorithm is a mis-implementation
+ of the XTEA algorithm for compatibility purposes.
+
+config CRYPTO_TWOFISH
+ tristate "Twofish cipher algorithm"
select CRYPTO_ALGAPI
+ select CRYPTO_TWOFISH_COMMON
help
- Camellia cipher algorithms module.
+ Twofish cipher algorithm.
- Camellia is a symmetric key block cipher developed jointly
- at NTT and Mitsubishi Electric Corporation.
+ Twofish was submitted as an AES (Advanced Encryption Standard)
+ candidate cipher by researchers at CounterPane Systems. It is a
+ 16 round block cipher supporting key sizes of 128, 192, and 256
+ bits.
- The Camellia specifies three key sizes: 128, 192 and 256 bits.
+ See also:
+ <http://www.schneier.com/twofish.html>
+
+config CRYPTO_TWOFISH_COMMON
+ tristate
+ help
+ Common parts of the Twofish cipher algorithm shared by the
+ generic c and the assembler implementations.
+
+config CRYPTO_TWOFISH_586
+ tristate "Twofish cipher algorithms (i586)"
+ depends on (X86 || UML_X86) && !64BIT
+ select CRYPTO_ALGAPI
+ select CRYPTO_TWOFISH_COMMON
+ help
+ Twofish cipher algorithm.
+
+ Twofish was submitted as an AES (Advanced Encryption Standard)
+ candidate cipher by researchers at CounterPane Systems. It is a
+ 16 round block cipher supporting key sizes of 128, 192, and 256
+ bits.
See also:
- <https://info.isl.ntt.co.jp/crypt/eng/camellia/index_s.html>
+ <http://www.schneier.com/twofish.html>
-config CRYPTO_TEST
- tristate "Testing module"
- depends on m
+config CRYPTO_TWOFISH_X86_64
+ tristate "Twofish cipher algorithm (x86_64)"
+ depends on (X86 || UML_X86) && 64BIT
select CRYPTO_ALGAPI
- select CRYPTO_AEAD
- select CRYPTO_BLKCIPHER
+ select CRYPTO_TWOFISH_COMMON
help
- Quick & dirty crypto test module.
+ Twofish cipher algorithm (x86_64).
-config CRYPTO_AUTHENC
- tristate "Authenc support"
- select CRYPTO_AEAD
- select CRYPTO_BLKCIPHER
- select CRYPTO_MANAGER
- select CRYPTO_HASH
+ Twofish was submitted as an AES (Advanced Encryption Standard)
+ candidate cipher by researchers at CounterPane Systems. It is a
+ 16 round block cipher supporting key sizes of 128, 192, and 256
+ bits.
+
+ See also:
+ <http://www.schneier.com/twofish.html>
+
+comment "Compression"
+
+config CRYPTO_DEFLATE
+ tristate "Deflate compression algorithm"
+ select CRYPTO_ALGAPI
+ select ZLIB_INFLATE
+ select ZLIB_DEFLATE
help
- Authenc: Combined mode wrapper for IPsec.
- This is required for IPSec.
+ This is the Deflate algorithm (RFC1951), specified for use in
+ IPSec with the IPCOMP protocol (RFC3173, RFC2394).
+
+ You will most probably want this if using IPSec.
config CRYPTO_LZO
tristate "LZO compression algorithm"
# Cryptographic API
#
-obj-$(CONFIG_CRYPTO) += api.o cipher.o digest.o compress.o
+obj-$(CONFIG_CRYPTO) += crypto.o
+crypto-objs := api.o cipher.o digest.o compress.o
crypto_algapi-$(CONFIG_PROC_FS) += proc.o
crypto_algapi-objs := algapi.o scatterwalk.o $(crypto_algapi-y)
obj-$(CONFIG_CRYPTO_MD5) += md5.o
obj-$(CONFIG_CRYPTO_SHA1) += sha1_generic.o
obj-$(CONFIG_CRYPTO_SHA256) += sha256_generic.o
-obj-$(CONFIG_CRYPTO_SHA512) += sha512.o
+obj-$(CONFIG_CRYPTO_SHA512) += sha512_generic.o
obj-$(CONFIG_CRYPTO_WP512) += wp512.o
obj-$(CONFIG_CRYPTO_TGR192) += tgr192.o
obj-$(CONFIG_CRYPTO_GF128MUL) += gf128mul.o
obj-$(CONFIG_CRYPTO_ECB) += ecb.o
obj-$(CONFIG_CRYPTO_CBC) += cbc.o
obj-$(CONFIG_CRYPTO_PCBC) += pcbc.o
+obj-$(CONFIG_CRYPTO_CTS) += cts.o
obj-$(CONFIG_CRYPTO_LRW) += lrw.o
obj-$(CONFIG_CRYPTO_XTS) += xts.o
obj-$(CONFIG_CRYPTO_CTR) += ctr.o
ctx->key_enc[8 * i + 15] = t; \
} while (0)
-int crypto_aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
+/**
+ * crypto_aes_expand_key - Expands the AES key as described in FIPS-197
+ * @ctx: The location where the computed key will be stored.
+ * @in_key: The supplied key.
+ * @key_len: The length of the supplied key.
+ *
+ * Returns 0 on success. The function fails only if an invalid key size (or
+ * pointer) is supplied.
+ * The expanded key size is 240 bytes (max of 14 rounds with a unique 16 bytes
+ * key schedule plus a 16 bytes key which is used before the first round).
+ * The decryption key is prepared for the "Equivalent Inverse Cipher" as
+ * described in FIPS-197. The first slot (16 bytes) of each key (enc or dec) is
+ * for the initial combination, the second slot for the first round and so on.
+ */
+int crypto_aes_expand_key(struct crypto_aes_ctx *ctx, const u8 *in_key,
unsigned int key_len)
{
- struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
const __le32 *key = (const __le32 *)in_key;
- u32 *flags = &tfm->crt_flags;
u32 i, t, u, v, w, j;
- if (key_len % 8) {
- *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+ if (key_len != AES_KEYSIZE_128 && key_len != AES_KEYSIZE_192 &&
+ key_len != AES_KEYSIZE_256)
return -EINVAL;
- }
ctx->key_length = key_len;
ctx->key_dec[key_len + 27] = ctx->key_enc[3] = le32_to_cpu(key[3]);
switch (key_len) {
- case 16:
+ case AES_KEYSIZE_128:
t = ctx->key_enc[3];
for (i = 0; i < 10; ++i)
loop4(i);
break;
- case 24:
+ case AES_KEYSIZE_192:
ctx->key_enc[4] = le32_to_cpu(key[4]);
t = ctx->key_enc[5] = le32_to_cpu(key[5]);
for (i = 0; i < 8; ++i)
loop6(i);
break;
- case 32:
+ case AES_KEYSIZE_256:
ctx->key_enc[4] = le32_to_cpu(key[4]);
ctx->key_enc[5] = le32_to_cpu(key[5]);
ctx->key_enc[6] = le32_to_cpu(key[6]);
}
return 0;
}
+EXPORT_SYMBOL_GPL(crypto_aes_expand_key);
+
+/**
+ * crypto_aes_set_key - Set the AES key.
+ * @tfm: The %crypto_tfm that is used in the context.
+ * @in_key: The input key.
+ * @key_len: The size of the key.
+ *
+ * Returns 0 on success, on failure the %CRYPTO_TFM_RES_BAD_KEY_LEN flag in tfm
+ * is set. The function uses crypto_aes_expand_key() to expand the key.
+ * &crypto_aes_ctx _must_ be the private data embedded in @tfm which is
+ * retrieved with crypto_tfm_ctx().
+ */
+int crypto_aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
+ unsigned int key_len)
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+ u32 *flags = &tfm->crt_flags;
+ int ret;
+
+ ret = crypto_aes_expand_key(ctx, in_key, key_len);
+ if (!ret)
+ return 0;
+
+ *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+ return -EINVAL;
+}
EXPORT_SYMBOL_GPL(crypto_aes_set_key);
/* encrypt a block of text */
.cia_decrypt = anubis_decrypt } }
};
-static int __init init(void)
+static int __init anubis_mod_init(void)
{
int ret = 0;
return ret;
}
-static void __exit fini(void)
+static void __exit anubis_mod_fini(void)
{
crypto_unregister_alg(&anubis_alg);
}
-module_init(init);
-module_exit(fini);
+module_init(anubis_mod_init);
+module_exit(anubis_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Anubis Cryptographic Algorithm");
return ret;
}
EXPORT_SYMBOL_GPL(crypto_has_alg);
+
+MODULE_DESCRIPTION("Cryptographic core API");
+MODULE_LICENSE("GPL");
.cia_decrypt = bf_decrypt } }
};
-static int __init init(void)
+static int __init blowfish_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit blowfish_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(blowfish_mod_init);
+module_exit(blowfish_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Blowfish Cipher Algorithm");
}
};
-static int __init init(void)
+static int __init cast5_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit cast5_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(cast5_mod_init);
+module_exit(cast5_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Cast5 Cipher Algorithm");
}
};
-static int __init init(void)
+static int __init cast6_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit cast6_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(cast6_mod_init);
+module_exit(cast6_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Cast6 Cipher Algorithm");
}
};
-static int __init init(void)
+static int __init crc32c_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit crc32c_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(crc32c_mod_init);
+module_exit(crc32c_mod_fini);
MODULE_AUTHOR("Clay Haapala <chaapala@cisco.com>");
MODULE_DESCRIPTION("CRC32c (Castagnoli) calculations wrapper for lib/crc32c");
MODULE_ALIAS("digest_null");
MODULE_ALIAS("cipher_null");
-static int __init init(void)
+static int __init crypto_null_mod_init(void)
{
int ret = 0;
goto out;
}
-static void __exit fini(void)
+static void __exit crypto_null_mod_fini(void)
{
crypto_unregister_alg(&compress_null);
crypto_unregister_alg(&digest_null);
crypto_unregister_alg(&cipher_null);
}
-module_init(init);
-module_exit(fini);
+module_init(crypto_null_mod_init);
+module_exit(crypto_null_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Null Cryptographic Algorithms");
--- /dev/null
+/*
+ * CTS: Cipher Text Stealing mode
+ *
+ * COPYRIGHT (c) 2008
+ * The Regents of the University of Michigan
+ * ALL RIGHTS RESERVED
+ *
+ * Permission is granted to use, copy, create derivative works
+ * and redistribute this software and such derivative works
+ * for any purpose, so long as the name of The University of
+ * Michigan is not used in any advertising or publicity
+ * pertaining to the use of distribution of this software
+ * without specific, written prior authorization. If the
+ * above copyright notice or any other identification of the
+ * University of Michigan is included in any copy of any
+ * portion of this software, then the disclaimer below must
+ * also be included.
+ *
+ * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION
+ * FROM THE UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY
+ * PURPOSE, AND WITHOUT WARRANTY BY THE UNIVERSITY OF
+ * MICHIGAN OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING
+ * WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE
+ * REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE
+ * FOR ANY DAMAGES, INCLUDING SPECIAL, INDIRECT, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
+ * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGES.
+ */
+
+/* Derived from various:
+ * Copyright (c) 2006 Herbert Xu <herbert@gondor.apana.org.au>
+ */
+
+/*
+ * This is the Cipher Text Stealing mode as described by
+ * Section 8 of rfc2040 and referenced by rfc3962.
+ * rfc3962 includes errata information in its Appendix A.
+ */
+
+#include <crypto/algapi.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/log2.h>
+#include <linux/module.h>
+#include <linux/scatterlist.h>
+#include <crypto/scatterwalk.h>
+#include <linux/slab.h>
+
+struct crypto_cts_ctx {
+ struct crypto_blkcipher *child;
+};
+
+static int crypto_cts_setkey(struct crypto_tfm *parent, const u8 *key,
+ unsigned int keylen)
+{
+ struct crypto_cts_ctx *ctx = crypto_tfm_ctx(parent);
+ struct crypto_blkcipher *child = ctx->child;
+ int err;
+
+ crypto_blkcipher_clear_flags(child, CRYPTO_TFM_REQ_MASK);
+ crypto_blkcipher_set_flags(child, crypto_tfm_get_flags(parent) &
+ CRYPTO_TFM_REQ_MASK);
+ err = crypto_blkcipher_setkey(child, key, keylen);
+ crypto_tfm_set_flags(parent, crypto_blkcipher_get_flags(child) &
+ CRYPTO_TFM_RES_MASK);
+ return err;
+}
+
+static int cts_cbc_encrypt(struct crypto_cts_ctx *ctx,
+ struct blkcipher_desc *desc,
+ struct scatterlist *dst,
+ struct scatterlist *src,
+ unsigned int offset,
+ unsigned int nbytes)
+{
+ int bsize = crypto_blkcipher_blocksize(desc->tfm);
+ u8 tmp[bsize], tmp2[bsize];
+ struct blkcipher_desc lcldesc;
+ struct scatterlist sgsrc[1], sgdst[1];
+ int lastn = nbytes - bsize;
+ u8 iv[bsize];
+ u8 s[bsize * 2], d[bsize * 2];
+ int err;
+
+ if (lastn < 0)
+ return -EINVAL;
+
+ memset(s, 0, sizeof(s));
+ scatterwalk_map_and_copy(s, src, offset, nbytes, 0);
+
+ memcpy(iv, desc->info, bsize);
+
+ lcldesc.tfm = ctx->child;
+ lcldesc.info = iv;
+ lcldesc.flags = desc->flags;
+
+ sg_set_buf(&sgsrc[0], s, bsize);
+ sg_set_buf(&sgdst[0], tmp, bsize);
+ err = crypto_blkcipher_encrypt_iv(&lcldesc, sgdst, sgsrc, bsize);
+
+ memcpy(d + bsize, tmp, lastn);
+
+ lcldesc.info = tmp;
+
+ sg_set_buf(&sgsrc[0], s + bsize, bsize);
+ sg_set_buf(&sgdst[0], tmp2, bsize);
+ err = crypto_blkcipher_encrypt_iv(&lcldesc, sgdst, sgsrc, bsize);
+
+ memcpy(d, tmp2, bsize);
+
+ scatterwalk_map_and_copy(d, dst, offset, nbytes, 1);
+
+ memcpy(desc->info, tmp2, bsize);
+
+ return err;
+}
+
+static int crypto_cts_encrypt(struct blkcipher_desc *desc,
+ struct scatterlist *dst, struct scatterlist *src,
+ unsigned int nbytes)
+{
+ struct crypto_cts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+ int bsize = crypto_blkcipher_blocksize(desc->tfm);
+ int tot_blocks = (nbytes + bsize - 1) / bsize;
+ int cbc_blocks = tot_blocks > 2 ? tot_blocks - 2 : 0;
+ struct blkcipher_desc lcldesc;
+ int err;
+
+ lcldesc.tfm = ctx->child;
+ lcldesc.info = desc->info;
+ lcldesc.flags = desc->flags;
+
+ if (tot_blocks == 1) {
+ err = crypto_blkcipher_encrypt_iv(&lcldesc, dst, src, bsize);
+ } else if (nbytes <= bsize * 2) {
+ err = cts_cbc_encrypt(ctx, desc, dst, src, 0, nbytes);
+ } else {
+ /* do normal function for tot_blocks - 2 */
+ err = crypto_blkcipher_encrypt_iv(&lcldesc, dst, src,
+ cbc_blocks * bsize);
+ if (err == 0) {
+ /* do cts for final two blocks */
+ err = cts_cbc_encrypt(ctx, desc, dst, src,
+ cbc_blocks * bsize,
+ nbytes - (cbc_blocks * bsize));
+ }
+ }
+
+ return err;
+}
+
+static int cts_cbc_decrypt(struct crypto_cts_ctx *ctx,
+ struct blkcipher_desc *desc,
+ struct scatterlist *dst,
+ struct scatterlist *src,
+ unsigned int offset,
+ unsigned int nbytes)
+{
+ int bsize = crypto_blkcipher_blocksize(desc->tfm);
+ u8 tmp[bsize];
+ struct blkcipher_desc lcldesc;
+ struct scatterlist sgsrc[1], sgdst[1];
+ int lastn = nbytes - bsize;
+ u8 iv[bsize];
+ u8 s[bsize * 2], d[bsize * 2];
+ int err;
+
+ if (lastn < 0)
+ return -EINVAL;
+
+ scatterwalk_map_and_copy(s, src, offset, nbytes, 0);
+
+ lcldesc.tfm = ctx->child;
+ lcldesc.info = iv;
+ lcldesc.flags = desc->flags;
+
+ /* 1. Decrypt Cn-1 (s) to create Dn (tmp)*/
+ memset(iv, 0, sizeof(iv));
+ sg_set_buf(&sgsrc[0], s, bsize);
+ sg_set_buf(&sgdst[0], tmp, bsize);
+ err = crypto_blkcipher_decrypt_iv(&lcldesc, sgdst, sgsrc, bsize);
+ if (err)
+ return err;
+ /* 2. Pad Cn with zeros at the end to create C of length BB */
+ memset(iv, 0, sizeof(iv));
+ memcpy(iv, s + bsize, lastn);
+ /* 3. Exclusive-or Dn (tmp) with C (iv) to create Xn (tmp) */
+ crypto_xor(tmp, iv, bsize);
+ /* 4. Select the first Ln bytes of Xn (tmp) to create Pn */
+ memcpy(d + bsize, tmp, lastn);
+
+ /* 5. Append the tail (BB - Ln) bytes of Xn (tmp) to Cn to create En */
+ memcpy(s + bsize + lastn, tmp + lastn, bsize - lastn);
+ /* 6. Decrypt En to create Pn-1 */
+ memset(iv, 0, sizeof(iv));
+ sg_set_buf(&sgsrc[0], s + bsize, bsize);
+ sg_set_buf(&sgdst[0], d, bsize);
+ err = crypto_blkcipher_decrypt_iv(&lcldesc, sgdst, sgsrc, bsize);
+
+ /* XOR with previous block */
+ crypto_xor(d, desc->info, bsize);
+
+ scatterwalk_map_and_copy(d, dst, offset, nbytes, 1);
+
+ memcpy(desc->info, s, bsize);
+ return err;
+}
+
+static int crypto_cts_decrypt(struct blkcipher_desc *desc,
+ struct scatterlist *dst, struct scatterlist *src,
+ unsigned int nbytes)
+{
+ struct crypto_cts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+ int bsize = crypto_blkcipher_blocksize(desc->tfm);
+ int tot_blocks = (nbytes + bsize - 1) / bsize;
+ int cbc_blocks = tot_blocks > 2 ? tot_blocks - 2 : 0;
+ struct blkcipher_desc lcldesc;
+ int err;
+
+ lcldesc.tfm = ctx->child;
+ lcldesc.info = desc->info;
+ lcldesc.flags = desc->flags;
+
+ if (tot_blocks == 1) {
+ err = crypto_blkcipher_decrypt_iv(&lcldesc, dst, src, bsize);
+ } else if (nbytes <= bsize * 2) {
+ err = cts_cbc_decrypt(ctx, desc, dst, src, 0, nbytes);
+ } else {
+ /* do normal function for tot_blocks - 2 */
+ err = crypto_blkcipher_decrypt_iv(&lcldesc, dst, src,
+ cbc_blocks * bsize);
+ if (err == 0) {
+ /* do cts for final two blocks */
+ err = cts_cbc_decrypt(ctx, desc, dst, src,
+ cbc_blocks * bsize,
+ nbytes - (cbc_blocks * bsize));
+ }
+ }
+ return err;
+}
+
+static int crypto_cts_init_tfm(struct crypto_tfm *tfm)
+{
+ struct crypto_instance *inst = (void *)tfm->__crt_alg;
+ struct crypto_spawn *spawn = crypto_instance_ctx(inst);
+ struct crypto_cts_ctx *ctx = crypto_tfm_ctx(tfm);
+ struct crypto_blkcipher *cipher;
+
+ cipher = crypto_spawn_blkcipher(spawn);
+ if (IS_ERR(cipher))
+ return PTR_ERR(cipher);
+
+ ctx->child = cipher;
+ return 0;
+}
+
+static void crypto_cts_exit_tfm(struct crypto_tfm *tfm)
+{
+ struct crypto_cts_ctx *ctx = crypto_tfm_ctx(tfm);
+ crypto_free_blkcipher(ctx->child);
+}
+
+static struct crypto_instance *crypto_cts_alloc(struct rtattr **tb)
+{
+ struct crypto_instance *inst;
+ struct crypto_alg *alg;
+ int err;
+
+ err = crypto_check_attr_type(tb, CRYPTO_ALG_TYPE_BLKCIPHER);
+ if (err)
+ return ERR_PTR(err);
+
+ alg = crypto_attr_alg(tb[1], CRYPTO_ALG_TYPE_BLKCIPHER,
+ CRYPTO_ALG_TYPE_MASK);
+ err = PTR_ERR(alg);
+ if (IS_ERR(alg))
+ return ERR_PTR(err);
+
+ inst = ERR_PTR(-EINVAL);
+ if (!is_power_of_2(alg->cra_blocksize))
+ goto out_put_alg;
+
+ inst = crypto_alloc_instance("cts", alg);
+ if (IS_ERR(inst))
+ goto out_put_alg;
+
+ inst->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER;
+ inst->alg.cra_priority = alg->cra_priority;
+ inst->alg.cra_blocksize = alg->cra_blocksize;
+ inst->alg.cra_alignmask = alg->cra_alignmask;
+ inst->alg.cra_type = &crypto_blkcipher_type;
+
+ /* We access the data as u32s when xoring. */
+ inst->alg.cra_alignmask |= __alignof__(u32) - 1;
+
+ inst->alg.cra_blkcipher.ivsize = alg->cra_blocksize;
+ inst->alg.cra_blkcipher.min_keysize = alg->cra_blkcipher.min_keysize;
+ inst->alg.cra_blkcipher.max_keysize = alg->cra_blkcipher.max_keysize;
+
+ inst->alg.cra_blkcipher.geniv = "seqiv";
+
+ inst->alg.cra_ctxsize = sizeof(struct crypto_cts_ctx);
+
+ inst->alg.cra_init = crypto_cts_init_tfm;
+ inst->alg.cra_exit = crypto_cts_exit_tfm;
+
+ inst->alg.cra_blkcipher.setkey = crypto_cts_setkey;
+ inst->alg.cra_blkcipher.encrypt = crypto_cts_encrypt;
+ inst->alg.cra_blkcipher.decrypt = crypto_cts_decrypt;
+
+out_put_alg:
+ crypto_mod_put(alg);
+ return inst;
+}
+
+static void crypto_cts_free(struct crypto_instance *inst)
+{
+ crypto_drop_spawn(crypto_instance_ctx(inst));
+ kfree(inst);
+}
+
+static struct crypto_template crypto_cts_tmpl = {
+ .name = "cts",
+ .alloc = crypto_cts_alloc,
+ .free = crypto_cts_free,
+ .module = THIS_MODULE,
+};
+
+static int __init crypto_cts_module_init(void)
+{
+ return crypto_register_template(&crypto_cts_tmpl);
+}
+
+static void __exit crypto_cts_module_exit(void)
+{
+ crypto_unregister_template(&crypto_cts_tmpl);
+}
+
+module_init(crypto_cts_module_init);
+module_exit(crypto_cts_module_exit);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("CTS-CBC CipherText Stealing for CBC");
.coa_decompress = deflate_decompress } }
};
-static int __init init(void)
+static int __init deflate_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit deflate_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(deflate_mod_init);
+module_exit(deflate_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Deflate Compression Algorithm for IPCOMP");
MODULE_ALIAS("des3_ede");
-static int __init init(void)
+static int __init des_generic_mod_init(void)
{
int ret = 0;
return ret;
}
-static void __exit fini(void)
+static void __exit des_generic_mod_fini(void)
{
crypto_unregister_alg(&des3_ede_alg);
crypto_unregister_alg(&des_alg);
}
-module_init(init);
-module_exit(fini);
+module_init(des_generic_mod_init);
+module_exit(des_generic_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("DES & Triple DES EDE Cipher Algorithms");
.cia_decrypt = fcrypt_decrypt } }
};
-static int __init init(void)
+static int __init fcrypt_mod_init(void)
{
return crypto_register_alg(&fcrypt_alg);
}
-static void __exit fini(void)
+static void __exit fcrypt_mod_fini(void)
{
crypto_unregister_alg(&fcrypt_alg);
}
-module_init(init);
-module_exit(fini);
+module_init(fcrypt_mod_init);
+module_exit(fcrypt_mod_fini);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("FCrypt Cipher Algorithm");
.cia_decrypt = khazad_decrypt } }
};
-static int __init init(void)
+static int __init khazad_mod_init(void)
{
int ret = 0;
return ret;
}
-static void __exit fini(void)
+static void __exit khazad_mod_fini(void)
{
crypto_unregister_alg(&khazad_alg);
}
-module_init(init);
-module_exit(fini);
+module_init(khazad_mod_init);
+module_exit(khazad_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Khazad Cryptographic Algorithm");
static inline void inc(be128 *iv)
{
- if (!(iv->b = cpu_to_be64(be64_to_cpu(iv->b) + 1)))
- iv->a = cpu_to_be64(be64_to_cpu(iv->a) + 1);
+ be64_add_cpu(&iv->b, 1);
+ if (!iv->b)
+ be64_add_cpu(&iv->a, 1);
}
static inline void lrw_round(struct sinfo *s, void *dst, const void *src)
.coa_decompress = lzo_decompress } }
};
-static int __init init(void)
+static int __init lzo_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit lzo_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(lzo_mod_init);
+module_exit(lzo_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("LZO Compression Algorithm");
.dia_final = md4_final } }
};
-static int __init init(void)
+static int __init md4_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit md4_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(md4_mod_init);
+module_exit(md4_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("MD4 Message Digest Algorithm");
.dia_final = md5_final } }
};
-static int __init init(void)
+static int __init md5_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit md5_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(md5_mod_init);
+module_exit(md5_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("MD5 Message Digest Algorithm");
return 0;
}
-static struct seq_operations crypto_seq_ops = {
+static const struct seq_operations crypto_seq_ops = {
.start = c_start,
.next = c_next,
.stop = c_stop,
void __init crypto_init_proc(void)
{
- struct proc_dir_entry *proc;
-
- proc = create_proc_entry("crypto", 0, NULL);
- if (proc)
- proc->proc_fops = &proc_crypto_ops;
+ proc_create("crypto", 0, NULL, &proc_crypto_ops);
}
void __exit crypto_exit_proc(void)
}
};
-static int __init init(void)
+static int __init salsa20_generic_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit salsa20_generic_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(salsa20_generic_mod_init);
+module_exit(salsa20_generic_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION ("Salsa20 stream cipher algorithm");
.cia_decrypt = tnepres_decrypt } }
};
-static int __init init(void)
+static int __init serpent_mod_init(void)
{
int ret = crypto_register_alg(&serpent_alg);
return ret;
}
-static void __exit fini(void)
+static void __exit serpent_mod_fini(void)
{
crypto_unregister_alg(&tnepres_alg);
crypto_unregister_alg(&serpent_alg);
}
-module_init(init);
-module_exit(fini);
+module_init(serpent_mod_init);
+module_exit(serpent_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Serpent and tnepres (kerneli compatible serpent reversed) Cipher Algorithm");
.dia_final = sha1_final } }
};
-static int __init init(void)
+static int __init sha1_generic_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit sha1_generic_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(sha1_generic_mod_init);
+module_exit(sha1_generic_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm");
.dia_final = sha224_final } }
};
-static int __init init(void)
+static int __init sha256_generic_mod_init(void)
{
int ret = 0;
return ret;
}
-static void __exit fini(void)
+static void __exit sha256_generic_mod_fini(void)
{
crypto_unregister_alg(&sha224);
crypto_unregister_alg(&sha256);
}
-module_init(init);
-module_exit(fini);
+module_init(sha256_generic_mod_init);
+module_exit(sha256_generic_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("SHA-224 and SHA-256 Secure Hash Algorithm");
}
/* load the state into our registers */
- a=state[0]; b=state[1]; c=state[2]; d=state[3];
- e=state[4]; f=state[5]; g=state[6]; h=state[7];
-
+ a=state[0]; b=state[1]; c=state[2]; d=state[3];
+ e=state[4]; f=state[5]; g=state[6]; h=state[7];
+
/* now iterate */
for (i=0; i<80; i+=8) {
t1 = h + e1(e) + Ch(e,f,g) + sha512_K[i ] + W[i ];
t1 = a + e1(f) + Ch(f,g,h) + sha512_K[i+7] + W[i+7];
t2 = e0(b) + Maj(b,c,d); e+=t1; a=t1+t2;
}
-
- state[0] += a; state[1] += b; state[2] += c; state[3] += d;
- state[4] += e; state[5] += f; state[6] += g; state[7] += h;
+
+ state[0] += a; state[1] += b; state[2] += c; state[3] += d;
+ state[4] += e; state[5] += f; state[6] += g; state[7] += h;
/* erase our data */
a = b = c = d = e = f = g = h = t1 = t2 = 0;
/* Compute number of bytes mod 128 */
index = (unsigned int)((sctx->count[0] >> 3) & 0x7F);
-
+
/* Update number of bits */
if ((sctx->count[0] += (len << 3)) < (len << 3)) {
if ((sctx->count[1] += 1) < 1)
sctx->count[3]++;
sctx->count[1] += (len >> 29);
}
-
+
part_len = 128 - index;
-
+
/* Transform as many times as possible. */
if (len >= part_len) {
memcpy(&sctx->buf[index], data, part_len);
}
};
-MODULE_ALIAS("sha384");
-
-static int __init init(void)
+static int __init sha512_generic_mod_init(void)
{
int ret = 0;
return ret;
}
-static void __exit fini(void)
+static void __exit sha512_generic_mod_fini(void)
{
crypto_unregister_alg(&sha384);
crypto_unregister_alg(&sha512);
}
-module_init(init);
-module_exit(fini);
+module_init(sha512_generic_mod_init);
+module_exit(sha512_generic_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("SHA-512 and SHA-384 Secure Hash Algorithms");
+
+MODULE_ALIAS("sha384");
+MODULE_ALIAS("sha512");
"des", "md5", "des3_ede", "rot13", "sha1", "sha224", "sha256",
"blowfish", "twofish", "serpent", "sha384", "sha512", "md4", "aes",
"cast6", "arc4", "michael_mic", "deflate", "crc32c", "tea", "xtea",
- "arc4", "michael_mic", "deflate", "crc32c", "tea", "xtea",
"khazad", "wp512", "wp384", "wp256", "tnepres", "xeta", "fcrypt",
- "camellia", "seed", "salsa20", "lzo", NULL
+ "camellia", "seed", "salsa20", "lzo", "cts", NULL
};
static void hexdump(unsigned char *buf, unsigned int len)
char result[64];
struct crypto_hash *tfm;
struct hash_desc desc;
- struct hash_testvec *hash_tv;
- unsigned int tsize;
int ret;
+ void *hash_buff;
printk("\ntesting %s\n", algo);
- tsize = sizeof(struct hash_testvec);
- tsize *= tcount;
-
- if (tsize > TVMEMSIZE) {
- printk("template (%u) too big for tvmem (%u)\n", tsize, TVMEMSIZE);
- return;
- }
-
- memcpy(tvmem, template, tsize);
- hash_tv = (void *)tvmem;
-
tfm = crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC);
if (IS_ERR(tfm)) {
printk("failed to load transform for %s: %ld\n", algo,
printk("test %u:\n", i + 1);
memset(result, 0, 64);
- sg_init_one(&sg[0], hash_tv[i].plaintext, hash_tv[i].psize);
+ hash_buff = kzalloc(template[i].psize, GFP_KERNEL);
+ if (!hash_buff)
+ continue;
+
+ memcpy(hash_buff, template[i].plaintext, template[i].psize);
+ sg_init_one(&sg[0], hash_buff, template[i].psize);
- if (hash_tv[i].ksize) {
- ret = crypto_hash_setkey(tfm, hash_tv[i].key,
- hash_tv[i].ksize);
+ if (template[i].ksize) {
+ ret = crypto_hash_setkey(tfm, template[i].key,
+ template[i].ksize);
if (ret) {
printk("setkey() failed ret=%d\n", ret);
+ kfree(hash_buff);
goto out;
}
}
- ret = crypto_hash_digest(&desc, sg, hash_tv[i].psize, result);
+ ret = crypto_hash_digest(&desc, sg, template[i].psize, result);
if (ret) {
printk("digest () failed ret=%d\n", ret);
+ kfree(hash_buff);
goto out;
}
hexdump(result, crypto_hash_digestsize(tfm));
printk("%s\n",
- memcmp(result, hash_tv[i].digest,
+ memcmp(result, template[i].digest,
crypto_hash_digestsize(tfm)) ?
"fail" : "pass");
+ kfree(hash_buff);
}
printk("testing %s across pages\n", algo);
j = 0;
for (i = 0; i < tcount; i++) {
- if (hash_tv[i].np) {
+ if (template[i].np) {
j++;
printk("test %u:\n", j);
memset(result, 0, 64);
temp = 0;
- sg_init_table(sg, hash_tv[i].np);
- for (k = 0; k < hash_tv[i].np; k++) {
+ sg_init_table(sg, template[i].np);
+ for (k = 0; k < template[i].np; k++) {
memcpy(&xbuf[IDX[k]],
- hash_tv[i].plaintext + temp,
- hash_tv[i].tap[k]);
- temp += hash_tv[i].tap[k];
+ template[i].plaintext + temp,
+ template[i].tap[k]);
+ temp += template[i].tap[k];
sg_set_buf(&sg[k], &xbuf[IDX[k]],
- hash_tv[i].tap[k]);
+ template[i].tap[k]);
}
- if (hash_tv[i].ksize) {
- ret = crypto_hash_setkey(tfm, hash_tv[i].key,
- hash_tv[i].ksize);
+ if (template[i].ksize) {
+ ret = crypto_hash_setkey(tfm, template[i].key,
+ template[i].ksize);
if (ret) {
printk("setkey() failed ret=%d\n", ret);
}
}
- ret = crypto_hash_digest(&desc, sg, hash_tv[i].psize,
+ ret = crypto_hash_digest(&desc, sg, template[i].psize,
result);
if (ret) {
printk("digest () failed ret=%d\n", ret);
hexdump(result, crypto_hash_digestsize(tfm));
printk("%s\n",
- memcmp(result, hash_tv[i].digest,
+ memcmp(result, template[i].digest,
crypto_hash_digestsize(tfm)) ?
"fail" : "pass");
}
unsigned int tcount)
{
unsigned int ret, i, j, k, temp;
- unsigned int tsize;
char *q;
struct crypto_aead *tfm;
char *key;
- struct aead_testvec *aead_tv;
struct aead_request *req;
struct scatterlist sg[8];
struct scatterlist asg[8];
const char *e;
struct tcrypt_result result;
unsigned int authsize;
+ void *input;
+ void *assoc;
+ char iv[MAX_IVLEN];
if (enc == ENCRYPT)
e = "encryption";
printk(KERN_INFO "\ntesting %s %s\n", algo, e);
- tsize = sizeof(struct aead_testvec);
- tsize *= tcount;
-
- if (tsize > TVMEMSIZE) {
- printk(KERN_INFO "template (%u) too big for tvmem (%u)\n",
- tsize, TVMEMSIZE);
- return;
- }
-
- memcpy(tvmem, template, tsize);
- aead_tv = (void *)tvmem;
-
init_completion(&result.completion);
tfm = crypto_alloc_aead(algo, 0, 0);
tcrypt_complete, &result);
for (i = 0, j = 0; i < tcount; i++) {
- if (!aead_tv[i].np) {
+ if (!template[i].np) {
printk(KERN_INFO "test %u (%d bit key):\n",
- ++j, aead_tv[i].klen * 8);
+ ++j, template[i].klen * 8);
+
+ /* some tepmplates have no input data but they will
+ * touch input
+ */
+ input = kzalloc(template[i].ilen + template[i].rlen, GFP_KERNEL);
+ if (!input)
+ continue;
+
+ assoc = kzalloc(template[i].alen, GFP_KERNEL);
+ if (!assoc) {
+ kfree(input);
+ continue;
+ }
+
+ memcpy(input, template[i].input, template[i].ilen);
+ memcpy(assoc, template[i].assoc, template[i].alen);
+ if (template[i].iv)
+ memcpy(iv, template[i].iv, MAX_IVLEN);
+ else
+ memset(iv, 0, MAX_IVLEN);
crypto_aead_clear_flags(tfm, ~0);
- if (aead_tv[i].wk)
+ if (template[i].wk)
crypto_aead_set_flags(
tfm, CRYPTO_TFM_REQ_WEAK_KEY);
- key = aead_tv[i].key;
+
+ if (template[i].key)
+ key = template[i].key;
+ else
+ key = kzalloc(template[i].klen, GFP_KERNEL);
ret = crypto_aead_setkey(tfm, key,
- aead_tv[i].klen);
+ template[i].klen);
if (ret) {
printk(KERN_INFO "setkey() failed flags=%x\n",
crypto_aead_get_flags(tfm));
- if (!aead_tv[i].fail)
- goto out;
+ if (!template[i].fail)
+ goto next_one;
}
- authsize = abs(aead_tv[i].rlen - aead_tv[i].ilen);
+ authsize = abs(template[i].rlen - template[i].ilen);
ret = crypto_aead_setauthsize(tfm, authsize);
if (ret) {
printk(KERN_INFO
"failed to set authsize = %u\n",
authsize);
- goto out;
+ goto next_one;
}
- sg_init_one(&sg[0], aead_tv[i].input,
- aead_tv[i].ilen + (enc ? authsize : 0));
+ sg_init_one(&sg[0], input,
+ template[i].ilen + (enc ? authsize : 0));
- sg_init_one(&asg[0], aead_tv[i].assoc,
- aead_tv[i].alen);
+ sg_init_one(&asg[0], assoc, template[i].alen);
aead_request_set_crypt(req, sg, sg,
- aead_tv[i].ilen,
- aead_tv[i].iv);
+ template[i].ilen, iv);
- aead_request_set_assoc(req, asg, aead_tv[i].alen);
+ aead_request_set_assoc(req, asg, template[i].alen);
ret = enc ?
crypto_aead_encrypt(req) :
default:
printk(KERN_INFO "%s () failed err=%d\n",
e, -ret);
- goto out;
+ goto next_one;
}
q = kmap(sg_page(&sg[0])) + sg[0].offset;
- hexdump(q, aead_tv[i].rlen);
+ hexdump(q, template[i].rlen);
printk(KERN_INFO "enc/dec: %s\n",
- memcmp(q, aead_tv[i].result,
- aead_tv[i].rlen) ? "fail" : "pass");
+ memcmp(q, template[i].result,
+ template[i].rlen) ? "fail" : "pass");
+ kunmap(sg_page(&sg[0]));
+next_one:
+ if (!template[i].key)
+ kfree(key);
+ kfree(assoc);
+ kfree(input);
}
}
memset(axbuf, 0, XBUFSIZE);
for (i = 0, j = 0; i < tcount; i++) {
- if (aead_tv[i].np) {
+ if (template[i].np) {
printk(KERN_INFO "test %u (%d bit key):\n",
- ++j, aead_tv[i].klen * 8);
+ ++j, template[i].klen * 8);
+
+ if (template[i].iv)
+ memcpy(iv, template[i].iv, MAX_IVLEN);
+ else
+ memset(iv, 0, MAX_IVLEN);
crypto_aead_clear_flags(tfm, ~0);
- if (aead_tv[i].wk)
+ if (template[i].wk)
crypto_aead_set_flags(
tfm, CRYPTO_TFM_REQ_WEAK_KEY);
- key = aead_tv[i].key;
+ key = template[i].key;
- ret = crypto_aead_setkey(tfm, key, aead_tv[i].klen);
+ ret = crypto_aead_setkey(tfm, key, template[i].klen);
if (ret) {
printk(KERN_INFO "setkey() failed flags=%x\n",
crypto_aead_get_flags(tfm));
- if (!aead_tv[i].fail)
+ if (!template[i].fail)
goto out;
}
- sg_init_table(sg, aead_tv[i].np);
- for (k = 0, temp = 0; k < aead_tv[i].np; k++) {
+ sg_init_table(sg, template[i].np);
+ for (k = 0, temp = 0; k < template[i].np; k++) {
memcpy(&xbuf[IDX[k]],
- aead_tv[i].input + temp,
- aead_tv[i].tap[k]);
- temp += aead_tv[i].tap[k];
+ template[i].input + temp,
+ template[i].tap[k]);
+ temp += template[i].tap[k];
sg_set_buf(&sg[k], &xbuf[IDX[k]],
- aead_tv[i].tap[k]);
+ template[i].tap[k]);
}
- authsize = abs(aead_tv[i].rlen - aead_tv[i].ilen);
+ authsize = abs(template[i].rlen - template[i].ilen);
ret = crypto_aead_setauthsize(tfm, authsize);
if (ret) {
printk(KERN_INFO
if (enc)
sg[k - 1].length += authsize;
- sg_init_table(asg, aead_tv[i].anp);
- for (k = 0, temp = 0; k < aead_tv[i].anp; k++) {
+ sg_init_table(asg, template[i].anp);
+ for (k = 0, temp = 0; k < template[i].anp; k++) {
memcpy(&axbuf[IDX[k]],
- aead_tv[i].assoc + temp,
- aead_tv[i].atap[k]);
- temp += aead_tv[i].atap[k];
+ template[i].assoc + temp,
+ template[i].atap[k]);
+ temp += template[i].atap[k];
sg_set_buf(&asg[k], &axbuf[IDX[k]],
- aead_tv[i].atap[k]);
+ template[i].atap[k]);
}
aead_request_set_crypt(req, sg, sg,
- aead_tv[i].ilen,
- aead_tv[i].iv);
+ template[i].ilen,
+ iv);
- aead_request_set_assoc(req, asg, aead_tv[i].alen);
+ aead_request_set_assoc(req, asg, template[i].alen);
ret = enc ?
crypto_aead_encrypt(req) :
goto out;
}
- for (k = 0, temp = 0; k < aead_tv[i].np; k++) {
+ for (k = 0, temp = 0; k < template[i].np; k++) {
printk(KERN_INFO "page %u\n", k);
q = kmap(sg_page(&sg[k])) + sg[k].offset;
- hexdump(q, aead_tv[i].tap[k]);
+ hexdump(q, template[i].tap[k]);
printk(KERN_INFO "%s\n",
- memcmp(q, aead_tv[i].result + temp,
- aead_tv[i].tap[k] -
- (k < aead_tv[i].np - 1 || enc ?
+ memcmp(q, template[i].result + temp,
+ template[i].tap[k] -
+ (k < template[i].np - 1 || enc ?
0 : authsize)) ?
"fail" : "pass");
- temp += aead_tv[i].tap[k];
+ temp += template[i].tap[k];
+ kunmap(sg_page(&sg[k]));
}
}
}
struct cipher_testvec *template, unsigned int tcount)
{
unsigned int ret, i, j, k, temp;
- unsigned int tsize;
char *q;
struct crypto_ablkcipher *tfm;
- char *key;
- struct cipher_testvec *cipher_tv;
struct ablkcipher_request *req;
struct scatterlist sg[8];
const char *e;
struct tcrypt_result result;
+ void *data;
+ char iv[MAX_IVLEN];
if (enc == ENCRYPT)
e = "encryption";
printk("\ntesting %s %s\n", algo, e);
- tsize = sizeof (struct cipher_testvec);
- if (tsize > TVMEMSIZE) {
- printk("template (%u) too big for tvmem (%u)\n", tsize,
- TVMEMSIZE);
- return;
- }
- cipher_tv = (void *)tvmem;
-
init_completion(&result.completion);
-
tfm = crypto_alloc_ablkcipher(algo, 0, 0);
if (IS_ERR(tfm)) {
j = 0;
for (i = 0; i < tcount; i++) {
- memcpy(cipher_tv, &template[i], tsize);
- if (!(cipher_tv->np)) {
+
+ data = kzalloc(template[i].ilen, GFP_KERNEL);
+ if (!data)
+ continue;
+
+ memcpy(data, template[i].input, template[i].ilen);
+ if (template[i].iv)
+ memcpy(iv, template[i].iv, MAX_IVLEN);
+ else
+ memset(iv, 0, MAX_IVLEN);
+
+ if (!(template[i].np)) {
j++;
printk("test %u (%d bit key):\n",
- j, cipher_tv->klen * 8);
+ j, template[i].klen * 8);
crypto_ablkcipher_clear_flags(tfm, ~0);
- if (cipher_tv->wk)
+ if (template[i].wk)
crypto_ablkcipher_set_flags(
tfm, CRYPTO_TFM_REQ_WEAK_KEY);
- key = cipher_tv->key;
- ret = crypto_ablkcipher_setkey(tfm, key,
- cipher_tv->klen);
+ ret = crypto_ablkcipher_setkey(tfm, template[i].key,
+ template[i].klen);
if (ret) {
printk("setkey() failed flags=%x\n",
crypto_ablkcipher_get_flags(tfm));
- if (!cipher_tv->fail)
+ if (!template[i].fail) {
+ kfree(data);
goto out;
+ }
}
- sg_init_one(&sg[0], cipher_tv->input,
- cipher_tv->ilen);
+ sg_init_one(&sg[0], data, template[i].ilen);
ablkcipher_request_set_crypt(req, sg, sg,
- cipher_tv->ilen,
- cipher_tv->iv);
-
+ template[i].ilen, iv);
ret = enc ?
crypto_ablkcipher_encrypt(req) :
crypto_ablkcipher_decrypt(req);
/* fall through */
default:
printk("%s () failed err=%d\n", e, -ret);
+ kfree(data);
goto out;
}
q = kmap(sg_page(&sg[0])) + sg[0].offset;
- hexdump(q, cipher_tv->rlen);
+ hexdump(q, template[i].rlen);
printk("%s\n",
- memcmp(q, cipher_tv->result,
- cipher_tv->rlen) ? "fail" : "pass");
+ memcmp(q, template[i].result,
+ template[i].rlen) ? "fail" : "pass");
+ kunmap(sg_page(&sg[0]));
}
+ kfree(data);
}
printk("\ntesting %s %s across pages (chunking)\n", algo, e);
j = 0;
for (i = 0; i < tcount; i++) {
- memcpy(cipher_tv, &template[i], tsize);
- if (cipher_tv->np) {
+
+ data = kzalloc(template[i].ilen, GFP_KERNEL);
+ if (!data)
+ continue;
+
+ memcpy(data, template[i].input, template[i].ilen);
+
+ if (template[i].iv)
+ memcpy(iv, template[i].iv, MAX_IVLEN);
+ else
+ memset(iv, 0, MAX_IVLEN);
+
+ if (template[i].np) {
j++;
printk("test %u (%d bit key):\n",
- j, cipher_tv->klen * 8);
+ j, template[i].klen * 8);
crypto_ablkcipher_clear_flags(tfm, ~0);
- if (cipher_tv->wk)
+ if (template[i].wk)
crypto_ablkcipher_set_flags(
tfm, CRYPTO_TFM_REQ_WEAK_KEY);
- key = cipher_tv->key;
- ret = crypto_ablkcipher_setkey(tfm, key,
- cipher_tv->klen);
+ ret = crypto_ablkcipher_setkey(tfm, template[i].key,
+ template[i].klen);
if (ret) {
printk("setkey() failed flags=%x\n",
- crypto_ablkcipher_get_flags(tfm));
+ crypto_ablkcipher_get_flags(tfm));
- if (!cipher_tv->fail)
+ if (!template[i].fail) {
+ kfree(data);
goto out;
+ }
}
temp = 0;
- sg_init_table(sg, cipher_tv->np);
- for (k = 0; k < cipher_tv->np; k++) {
+ sg_init_table(sg, template[i].np);
+ for (k = 0; k < template[i].np; k++) {
memcpy(&xbuf[IDX[k]],
- cipher_tv->input + temp,
- cipher_tv->tap[k]);
- temp += cipher_tv->tap[k];
+ template[i].input + temp,
+ template[i].tap[k]);
+ temp += template[i].tap[k];
sg_set_buf(&sg[k], &xbuf[IDX[k]],
- cipher_tv->tap[k]);
+ template[i].tap[k]);
}
ablkcipher_request_set_crypt(req, sg, sg,
- cipher_tv->ilen,
- cipher_tv->iv);
+ template[i].ilen, iv);
ret = enc ?
crypto_ablkcipher_encrypt(req) :
}
temp = 0;
- for (k = 0; k < cipher_tv->np; k++) {
+ for (k = 0; k < template[i].np; k++) {
printk("page %u\n", k);
q = kmap(sg_page(&sg[k])) + sg[k].offset;
- hexdump(q, cipher_tv->tap[k]);
+ hexdump(q, template[i].tap[k]);
printk("%s\n",
- memcmp(q, cipher_tv->result + temp,
- cipher_tv->tap[k]) ? "fail" :
+ memcmp(q, template[i].result + temp,
+ template[i].tap[k]) ? "fail" :
"pass");
- temp += cipher_tv->tap[k];
+ temp += template[i].tap[k];
+ kunmap(sg_page(&sg[k]));
}
}
}
-
out:
crypto_free_ablkcipher(tfm);
ablkcipher_request_free(req);
return ret;
}
+static u32 block_sizes[] = { 16, 64, 256, 1024, 8192, 0 };
+
static void test_cipher_speed(char *algo, int enc, unsigned int sec,
struct cipher_testvec *template,
- unsigned int tcount, struct cipher_speed *speed)
+ unsigned int tcount, u8 *keysize)
{
unsigned int ret, i, j, iv_len;
unsigned char *key, *p, iv[128];
struct crypto_blkcipher *tfm;
struct blkcipher_desc desc;
const char *e;
+ u32 *b_size;
if (enc == ENCRYPT)
e = "encryption";
desc.tfm = tfm;
desc.flags = 0;
- for (i = 0; speed[i].klen != 0; i++) {
- if ((speed[i].blen + speed[i].klen) > TVMEMSIZE) {
- printk("template (%u) too big for tvmem (%u)\n",
- speed[i].blen + speed[i].klen, TVMEMSIZE);
- goto out;
- }
+ i = 0;
+ do {
+
+ b_size = block_sizes;
+ do {
+
+ if ((*keysize + *b_size) > TVMEMSIZE) {
+ printk("template (%u) too big for tvmem (%u)\n",
+ *keysize + *b_size, TVMEMSIZE);
+ goto out;
+ }
- printk("test %u (%d bit key, %d byte blocks): ", i,
- speed[i].klen * 8, speed[i].blen);
+ printk("test %u (%d bit key, %d byte blocks): ", i,
+ *keysize * 8, *b_size);
- memset(tvmem, 0xff, speed[i].klen + speed[i].blen);
+ memset(tvmem, 0xff, *keysize + *b_size);
- /* set key, plain text and IV */
- key = (unsigned char *)tvmem;
- for (j = 0; j < tcount; j++) {
- if (template[j].klen == speed[i].klen) {
- key = template[j].key;
- break;
+ /* set key, plain text and IV */
+ key = (unsigned char *)tvmem;
+ for (j = 0; j < tcount; j++) {
+ if (template[j].klen == *keysize) {
+ key = template[j].key;
+ break;
+ }
}
- }
- p = (unsigned char *)tvmem + speed[i].klen;
+ p = (unsigned char *)tvmem + *keysize;
- ret = crypto_blkcipher_setkey(tfm, key, speed[i].klen);
- if (ret) {
- printk("setkey() failed flags=%x\n",
- crypto_blkcipher_get_flags(tfm));
- goto out;
- }
+ ret = crypto_blkcipher_setkey(tfm, key, *keysize);
+ if (ret) {
+ printk("setkey() failed flags=%x\n",
+ crypto_blkcipher_get_flags(tfm));
+ goto out;
+ }
- iv_len = crypto_blkcipher_ivsize(tfm);
- if (iv_len) {
- memset(&iv, 0xff, iv_len);
- crypto_blkcipher_set_iv(tfm, iv, iv_len);
- }
+ iv_len = crypto_blkcipher_ivsize(tfm);
+ if (iv_len) {
+ memset(&iv, 0xff, iv_len);
+ crypto_blkcipher_set_iv(tfm, iv, iv_len);
+ }
- if (sec)
- ret = test_cipher_jiffies(&desc, enc, p, speed[i].blen,
- sec);
- else
- ret = test_cipher_cycles(&desc, enc, p, speed[i].blen);
+ if (sec)
+ ret = test_cipher_jiffies(&desc, enc, p, *b_size, sec);
+ else
+ ret = test_cipher_cycles(&desc, enc, p, *b_size);
- if (ret) {
- printk("%s() failed flags=%x\n", e, desc.flags);
- break;
- }
- }
+ if (ret) {
+ printk("%s() failed flags=%x\n", e, desc.flags);
+ break;
+ }
+ b_size++;
+ i++;
+ } while (*b_size);
+ keysize++;
+ } while (*keysize);
out:
crypto_free_blkcipher(tfm);
unsigned int i;
char result[COMP_BUF_SIZE];
struct crypto_comp *tfm;
- struct comp_testvec *tv;
unsigned int tsize;
printk("\ntesting %s compression\n", algo);
- tsize = sizeof(struct comp_testvec);
- tsize *= ctcount;
- if (tsize > TVMEMSIZE) {
- printk("template (%u) too big for tvmem (%u)\n", tsize,
- TVMEMSIZE);
- return;
- }
-
- memcpy(tvmem, ctemplate, tsize);
- tv = (void *)tvmem;
-
tfm = crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC);
if (IS_ERR(tfm)) {
printk("failed to load transform for %s\n", algo);
printk("test %u:\n", i + 1);
memset(result, 0, sizeof (result));
- ilen = tv[i].inlen;
- ret = crypto_comp_compress(tfm, tv[i].input,
+ ilen = ctemplate[i].inlen;
+ ret = crypto_comp_compress(tfm, ctemplate[i].input,
ilen, result, &dlen);
if (ret) {
printk("fail: ret=%d\n", ret);
}
hexdump(result, dlen);
printk("%s (ratio %d:%d)\n",
- memcmp(result, tv[i].output, dlen) ? "fail" : "pass",
+ memcmp(result, ctemplate[i].output, dlen) ? "fail" : "pass",
ilen, dlen);
}
goto out;
}
- memcpy(tvmem, dtemplate, tsize);
- tv = (void *)tvmem;
-
for (i = 0; i < dtcount; i++) {
int ilen, ret, dlen = COMP_BUF_SIZE;
printk("test %u:\n", i + 1);
memset(result, 0, sizeof (result));
- ilen = tv[i].inlen;
- ret = crypto_comp_decompress(tfm, tv[i].input,
+ ilen = dtemplate[i].inlen;
+ ret = crypto_comp_decompress(tfm, dtemplate[i].input,
ilen, result, &dlen);
if (ret) {
printk("fail: ret=%d\n", ret);
}
hexdump(result, dlen);
printk("%s (ratio %d:%d)\n",
- memcmp(result, tv[i].output, dlen) ? "fail" : "pass",
+ memcmp(result, dtemplate[i].output, dlen) ? "fail" : "pass",
ilen, dlen);
}
out:
test_cipher("ecb(seed)", DECRYPT, seed_dec_tv_template,
SEED_DEC_TEST_VECTORS);
+ //CTS
+ test_cipher("cts(cbc(aes))", ENCRYPT, cts_mode_enc_tv_template,
+ CTS_MODE_ENC_TEST_VECTORS);
+ test_cipher("cts(cbc(aes))", DECRYPT, cts_mode_dec_tv_template,
+ CTS_MODE_DEC_TEST_VECTORS);
+
test_hash("sha384", sha384_tv_template, SHA384_TEST_VECTORS);
test_hash("sha512", sha512_tv_template, SHA512_TEST_VECTORS);
test_hash("wp512", wp512_tv_template, WP512_TEST_VECTORS);
AES_CCM_DEC_TEST_VECTORS);
break;
+ case 38:
+ test_cipher("cts(cbc(aes))", ENCRYPT, cts_mode_enc_tv_template,
+ CTS_MODE_ENC_TEST_VECTORS);
+ test_cipher("cts(cbc(aes))", DECRYPT, cts_mode_dec_tv_template,
+ CTS_MODE_DEC_TEST_VECTORS);
+ break;
+
case 100:
test_hash("hmac(md5)", hmac_md5_tv_template,
HMAC_MD5_TEST_VECTORS);
case 200:
test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0,
- aes_speed_template);
+ speed_template_16_24_32);
test_cipher_speed("ecb(aes)", DECRYPT, sec, NULL, 0,
- aes_speed_template);
+ speed_template_16_24_32);
test_cipher_speed("cbc(aes)", ENCRYPT, sec, NULL, 0,
- aes_speed_template);
+ speed_template_16_24_32);
test_cipher_speed("cbc(aes)", DECRYPT, sec, NULL, 0,
- aes_speed_template);
+ speed_template_16_24_32);
test_cipher_speed("lrw(aes)", ENCRYPT, sec, NULL, 0,
- aes_lrw_speed_template);
+ speed_template_32_40_48);
test_cipher_speed("lrw(aes)", DECRYPT, sec, NULL, 0,
- aes_lrw_speed_template);
+ speed_template_32_40_48);
test_cipher_speed("xts(aes)", ENCRYPT, sec, NULL, 0,
- aes_xts_speed_template);
+ speed_template_32_48_64);
test_cipher_speed("xts(aes)", DECRYPT, sec, NULL, 0,
- aes_xts_speed_template);
+ speed_template_32_48_64);
break;
case 201:
test_cipher_speed("ecb(des3_ede)", ENCRYPT, sec,
- des3_ede_enc_tv_template,
- DES3_EDE_ENC_TEST_VECTORS,
- des3_ede_speed_template);
+ des3_ede_enc_tv_template, DES3_EDE_ENC_TEST_VECTORS,
+ speed_template_24);
test_cipher_speed("ecb(des3_ede)", DECRYPT, sec,
- des3_ede_dec_tv_template,
- DES3_EDE_DEC_TEST_VECTORS,
- des3_ede_speed_template);
+ des3_ede_enc_tv_template, DES3_EDE_ENC_TEST_VECTORS,
+ speed_template_24);
test_cipher_speed("cbc(des3_ede)", ENCRYPT, sec,
- des3_ede_enc_tv_template,
- DES3_EDE_ENC_TEST_VECTORS,
- des3_ede_speed_template);
+ des3_ede_enc_tv_template, DES3_EDE_ENC_TEST_VECTORS,
+ speed_template_24);
test_cipher_speed("cbc(des3_ede)", DECRYPT, sec,
- des3_ede_dec_tv_template,
- DES3_EDE_DEC_TEST_VECTORS,
- des3_ede_speed_template);
+ des3_ede_enc_tv_template, DES3_EDE_ENC_TEST_VECTORS,
+ speed_template_24);
break;
case 202:
test_cipher_speed("ecb(twofish)", ENCRYPT, sec, NULL, 0,
- twofish_speed_template);
+ speed_template_16_24_32);
test_cipher_speed("ecb(twofish)", DECRYPT, sec, NULL, 0,
- twofish_speed_template);
+ speed_template_16_24_32);
test_cipher_speed("cbc(twofish)", ENCRYPT, sec, NULL, 0,
- twofish_speed_template);
+ speed_template_16_24_32);
test_cipher_speed("cbc(twofish)", DECRYPT, sec, NULL, 0,
- twofish_speed_template);
+ speed_template_16_24_32);
break;
case 203:
test_cipher_speed("ecb(blowfish)", ENCRYPT, sec, NULL, 0,
- blowfish_speed_template);
+ speed_template_8_32);
test_cipher_speed("ecb(blowfish)", DECRYPT, sec, NULL, 0,
- blowfish_speed_template);
+ speed_template_8_32);
test_cipher_speed("cbc(blowfish)", ENCRYPT, sec, NULL, 0,
- blowfish_speed_template);
+ speed_template_8_32);
test_cipher_speed("cbc(blowfish)", DECRYPT, sec, NULL, 0,
- blowfish_speed_template);
+ speed_template_8_32);
break;
case 204:
test_cipher_speed("ecb(des)", ENCRYPT, sec, NULL, 0,
- des_speed_template);
+ speed_template_8);
test_cipher_speed("ecb(des)", DECRYPT, sec, NULL, 0,
- des_speed_template);
+ speed_template_8);
test_cipher_speed("cbc(des)", ENCRYPT, sec, NULL, 0,
- des_speed_template);
+ speed_template_8);
test_cipher_speed("cbc(des)", DECRYPT, sec, NULL, 0,
- des_speed_template);
+ speed_template_8);
break;
case 205:
test_cipher_speed("ecb(camellia)", ENCRYPT, sec, NULL, 0,
- camellia_speed_template);
+ speed_template_16_24_32);
test_cipher_speed("ecb(camellia)", DECRYPT, sec, NULL, 0,
- camellia_speed_template);
+ speed_template_16_24_32);
test_cipher_speed("cbc(camellia)", ENCRYPT, sec, NULL, 0,
- camellia_speed_template);
+ speed_template_16_24_32);
test_cipher_speed("cbc(camellia)", DECRYPT, sec, NULL, 0,
- camellia_speed_template);
+ speed_template_16_24_32);
break;
case 206:
test_cipher_speed("salsa20", ENCRYPT, sec, NULL, 0,
- salsa20_speed_template);
+ speed_template_16_32);
break;
case 300:
}
}
-static int __init init(void)
+static int __init tcrypt_mod_init(void)
{
int err = -ENOMEM;
* If an init function is provided, an exit function must also be provided
* to allow module unload.
*/
-static void __exit fini(void) { }
+static void __exit tcrypt_mod_fini(void) { }
-module_init(init);
-module_exit(fini);
+module_init(tcrypt_mod_init);
+module_exit(tcrypt_mod_fini);
module_param(mode, int, 0);
module_param(sec, uint, 0);
struct hash_testvec {
/* only used with keyed hash algorithms */
- char key[132] __attribute__ ((__aligned__(4)));
- char plaintext[240];
- char digest[MAX_DIGEST_SIZE];
+ char *key;
+ char *plaintext;
+ char *digest;
unsigned char tap[MAX_TAP];
unsigned char psize;
unsigned char np;
};
struct cipher_testvec {
- char key[MAX_KEYLEN] __attribute__ ((__aligned__(4)));
- char iv[MAX_IVLEN];
- char input[4100];
- char result[4100];
+ char *key;
+ char *iv;
+ char *input;
+ char *result;
unsigned char tap[MAX_TAP];
int np;
unsigned char fail;
};
struct aead_testvec {
- char key[MAX_KEYLEN] __attribute__ ((__aligned__(4)));
- char iv[MAX_IVLEN];
- char input[512];
- char assoc[512];
- char result[512];
+ char *key;
+ char *iv;
+ char *input;
+ char *assoc;
+ char *result;
unsigned char tap[MAX_TAP];
unsigned char atap[MAX_TAP];
int np;
unsigned short rlen;
};
-struct cipher_speed {
- unsigned char klen;
- unsigned int blen;
-};
-
struct hash_speed {
unsigned int blen; /* buffer length */
unsigned int plen; /* per-update length */
};
+static char zeroed_string[48];
+
/*
* MD4 test vectors from RFC1320
*/
static struct hash_testvec md4_tv_template [] = {
{
.plaintext = "",
- .digest = { 0x31, 0xd6, 0xcf, 0xe0, 0xd1, 0x6a, 0xe9, 0x31,
- 0xb7, 0x3c, 0x59, 0xd7, 0xe0, 0xc0, 0x89, 0xc0 },
+ .digest = "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31"
+ "\xb7\x3c\x59\xd7\xe0\xc0\x89\xc0",
}, {
.plaintext = "a",
.psize = 1,
- .digest = { 0xbd, 0xe5, 0x2c, 0xb3, 0x1d, 0xe3, 0x3e, 0x46,
- 0x24, 0x5e, 0x05, 0xfb, 0xdb, 0xd6, 0xfb, 0x24 },
+ .digest = "\xbd\xe5\x2c\xb3\x1d\xe3\x3e\x46"
+ "\x24\x5e\x05\xfb\xdb\xd6\xfb\x24",
}, {
.plaintext = "abc",
.psize = 3,
- .digest = { 0xa4, 0x48, 0x01, 0x7a, 0xaf, 0x21, 0xd8, 0x52,
- 0x5f, 0xc1, 0x0a, 0xe8, 0x7a, 0xa6, 0x72, 0x9d },
+ .digest = "\xa4\x48\x01\x7a\xaf\x21\xd8\x52"
+ "\x5f\xc1\x0a\xe8\x7a\xa6\x72\x9d",
}, {
.plaintext = "message digest",
.psize = 14,
- .digest = { 0xd9, 0x13, 0x0a, 0x81, 0x64, 0x54, 0x9f, 0xe8,
- 0x18, 0x87, 0x48, 0x06, 0xe1, 0xc7, 0x01, 0x4b },
+ .digest = "\xd9\x13\x0a\x81\x64\x54\x9f\xe8"
+ "\x18\x87\x48\x06\xe1\xc7\x01\x4b",
}, {
.plaintext = "abcdefghijklmnopqrstuvwxyz",
.psize = 26,
- .digest = { 0xd7, 0x9e, 0x1c, 0x30, 0x8a, 0xa5, 0xbb, 0xcd,
- 0xee, 0xa8, 0xed, 0x63, 0xdf, 0x41, 0x2d, 0xa9 },
+ .digest = "\xd7\x9e\x1c\x30\x8a\xa5\xbb\xcd"
+ "\xee\xa8\xed\x63\xdf\x41\x2d\xa9",
.np = 2,
.tap = { 13, 13 },
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789",
.psize = 62,
- .digest = { 0x04, 0x3f, 0x85, 0x82, 0xf2, 0x41, 0xdb, 0x35,
- 0x1c, 0xe6, 0x27, 0xe1, 0x53, 0xe7, 0xf0, 0xe4 },
+ .digest = "\x04\x3f\x85\x82\xf2\x41\xdb\x35"
+ "\x1c\xe6\x27\xe1\x53\xe7\xf0\xe4",
}, {
.plaintext = "123456789012345678901234567890123456789012345678901234567890123"
- "45678901234567890",
+ "45678901234567890",
.psize = 80,
- .digest = { 0xe3, 0x3b, 0x4d, 0xdc, 0x9c, 0x38, 0xf2, 0x19,
- 0x9c, 0x3e, 0x7b, 0x16, 0x4f, 0xcc, 0x05, 0x36 },
+ .digest = "\xe3\x3b\x4d\xdc\x9c\x38\xf2\x19"
+ "\x9c\x3e\x7b\x16\x4f\xcc\x05\x36",
},
};
static struct hash_testvec md5_tv_template[] = {
{
- .digest = { 0xd4, 0x1d, 0x8c, 0xd9, 0x8f, 0x00, 0xb2, 0x04,
- 0xe9, 0x80, 0x09, 0x98, 0xec, 0xf8, 0x42, 0x7e },
+ .digest = "\xd4\x1d\x8c\xd9\x8f\x00\xb2\x04"
+ "\xe9\x80\x09\x98\xec\xf8\x42\x7e",
}, {
.plaintext = "a",
.psize = 1,
- .digest = { 0x0c, 0xc1, 0x75, 0xb9, 0xc0, 0xf1, 0xb6, 0xa8,
- 0x31, 0xc3, 0x99, 0xe2, 0x69, 0x77, 0x26, 0x61 },
+ .digest = "\x0c\xc1\x75\xb9\xc0\xf1\xb6\xa8"
+ "\x31\xc3\x99\xe2\x69\x77\x26\x61",
}, {
.plaintext = "abc",
.psize = 3,
- .digest = { 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0,
- 0xd6, 0x96, 0x3f, 0x7d, 0x28, 0xe1, 0x7f, 0x72 },
+ .digest = "\x90\x01\x50\x98\x3c\xd2\x4f\xb0"
+ "\xd6\x96\x3f\x7d\x28\xe1\x7f\x72",
}, {
.plaintext = "message digest",
.psize = 14,
- .digest = { 0xf9, 0x6b, 0x69, 0x7d, 0x7c, 0xb7, 0x93, 0x8d,
- 0x52, 0x5a, 0x2f, 0x31, 0xaa, 0xf1, 0x61, 0xd0 },
+ .digest = "\xf9\x6b\x69\x7d\x7c\xb7\x93\x8d"
+ "\x52\x5a\x2f\x31\xaa\xf1\x61\xd0",
}, {
.plaintext = "abcdefghijklmnopqrstuvwxyz",
.psize = 26,
- .digest = { 0xc3, 0xfc, 0xd3, 0xd7, 0x61, 0x92, 0xe4, 0x00,
- 0x7d, 0xfb, 0x49, 0x6c, 0xca, 0x67, 0xe1, 0x3b },
+ .digest = "\xc3\xfc\xd3\xd7\x61\x92\xe4\x00"
+ "\x7d\xfb\x49\x6c\xca\x67\xe1\x3b",
.np = 2,
.tap = {13, 13}
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789",
.psize = 62,
- .digest = { 0xd1, 0x74, 0xab, 0x98, 0xd2, 0x77, 0xd9, 0xf5,
- 0xa5, 0x61, 0x1c, 0x2c, 0x9f, 0x41, 0x9d, 0x9f },
+ .digest = "\xd1\x74\xab\x98\xd2\x77\xd9\xf5"
+ "\xa5\x61\x1c\x2c\x9f\x41\x9d\x9f",
}, {
.plaintext = "12345678901234567890123456789012345678901234567890123456789012"
- "345678901234567890",
+ "345678901234567890",
.psize = 80,
- .digest = { 0x57, 0xed, 0xf4, 0xa2, 0x2b, 0xe3, 0xc9, 0x55,
- 0xac, 0x49, 0xda, 0x2e, 0x21, 0x07, 0xb6, 0x7a },
+ .digest = "\x57\xed\xf4\xa2\x2b\xe3\xc9\x55"
+ "\xac\x49\xda\x2e\x21\x07\xb6\x7a",
}
};
{
.plaintext = "abc",
.psize = 3,
- .digest = { 0xa9, 0x99, 0x3e, 0x36, 0x47, 0x06, 0x81, 0x6a, 0xba, 0x3e,
- 0x25, 0x71, 0x78, 0x50, 0xc2, 0x6c, 0x9c, 0xd0, 0xd8, 0x9d },
+ .digest = "\xa9\x99\x3e\x36\x47\x06\x81\x6a\xba\x3e"
+ "\x25\x71\x78\x50\xc2\x6c\x9c\xd0\xd8\x9d",
}, {
.plaintext = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq",
.psize = 56,
- .digest = { 0x84, 0x98, 0x3e, 0x44, 0x1c, 0x3b, 0xd2, 0x6e, 0xba, 0xae,
- 0x4a, 0xa1, 0xf9, 0x51, 0x29, 0xe5, 0xe5, 0x46, 0x70, 0xf1 },
+ .digest = "\x84\x98\x3e\x44\x1c\x3b\xd2\x6e\xba\xae"
+ "\x4a\xa1\xf9\x51\x29\xe5\xe5\x46\x70\xf1",
.np = 2,
.tap = { 28, 28 }
}
{
.plaintext = "abc",
.psize = 3,
- .digest = { 0x23, 0x09, 0x7D, 0x22, 0x34, 0x05, 0xD8, 0x22,
- 0x86, 0x42, 0xA4, 0x77, 0xBD, 0xA2, 0x55, 0xB3,
- 0x2A, 0xAD, 0xBC, 0xE4, 0xBD, 0xA0, 0xB3, 0xF7,
- 0xE3, 0x6C, 0x9D, 0xA7},
+ .digest = "\x23\x09\x7D\x22\x34\x05\xD8\x22"
+ "\x86\x42\xA4\x77\xBD\xA2\x55\xB3"
+ "\x2A\xAD\xBC\xE4\xBD\xA0\xB3\xF7"
+ "\xE3\x6C\x9D\xA7",
}, {
.plaintext =
"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq",
.psize = 56,
- .digest = { 0x75, 0x38, 0x8B, 0x16, 0x51, 0x27, 0x76, 0xCC,
- 0x5D, 0xBA, 0x5D, 0xA1, 0xFD, 0x89, 0x01, 0x50,
- 0xB0, 0xC6, 0x45, 0x5C, 0xB4, 0xF5, 0x8B, 0x19,
- 0x52, 0x52, 0x25, 0x25 },
+ .digest = "\x75\x38\x8B\x16\x51\x27\x76\xCC"
+ "\x5D\xBA\x5D\xA1\xFD\x89\x01\x50"
+ "\xB0\xC6\x45\x5C\xB4\xF5\x8B\x19"
+ "\x52\x52\x25\x25",
.np = 2,
.tap = { 28, 28 }
}
{
.plaintext = "abc",
.psize = 3,
- .digest = { 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea,
- 0x41, 0x41, 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23,
- 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c,
- 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad },
+ .digest = "\xba\x78\x16\xbf\x8f\x01\xcf\xea"
+ "\x41\x41\x40\xde\x5d\xae\x22\x23"
+ "\xb0\x03\x61\xa3\x96\x17\x7a\x9c"
+ "\xb4\x10\xff\x61\xf2\x00\x15\xad",
}, {
.plaintext = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq",
.psize = 56,
- .digest = { 0x24, 0x8d, 0x6a, 0x61, 0xd2, 0x06, 0x38, 0xb8,
- 0xe5, 0xc0, 0x26, 0x93, 0x0c, 0x3e, 0x60, 0x39,
- 0xa3, 0x3c, 0xe4, 0x59, 0x64, 0xff, 0x21, 0x67,
- 0xf6, 0xec, 0xed, 0xd4, 0x19, 0xdb, 0x06, 0xc1 },
+ .digest = "\x24\x8d\x6a\x61\xd2\x06\x38\xb8"
+ "\xe5\xc0\x26\x93\x0c\x3e\x60\x39"
+ "\xa3\x3c\xe4\x59\x64\xff\x21\x67"
+ "\xf6\xec\xed\xd4\x19\xdb\x06\xc1",
.np = 2,
.tap = { 28, 28 }
},
{
.plaintext= "abc",
.psize = 3,
- .digest = { 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b,
- 0xb5, 0xa0, 0x3d, 0x69, 0x9a, 0xc6, 0x50, 0x07,
- 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63,
- 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed,
- 0x80, 0x86, 0x07, 0x2b, 0xa1, 0xe7, 0xcc, 0x23,
- 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7 },
+ .digest = "\xcb\x00\x75\x3f\x45\xa3\x5e\x8b"
+ "\xb5\xa0\x3d\x69\x9a\xc6\x50\x07"
+ "\x27\x2c\x32\xab\x0e\xde\xd1\x63"
+ "\x1a\x8b\x60\x5a\x43\xff\x5b\xed"
+ "\x80\x86\x07\x2b\xa1\xe7\xcc\x23"
+ "\x58\xba\xec\xa1\x34\xc8\x25\xa7",
}, {
.plaintext = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq",
.psize = 56,
- .digest = { 0x33, 0x91, 0xfd, 0xdd, 0xfc, 0x8d, 0xc7, 0x39,
- 0x37, 0x07, 0xa6, 0x5b, 0x1b, 0x47, 0x09, 0x39,
- 0x7c, 0xf8, 0xb1, 0xd1, 0x62, 0xaf, 0x05, 0xab,
- 0xfe, 0x8f, 0x45, 0x0d, 0xe5, 0xf3, 0x6b, 0xc6,
- 0xb0, 0x45, 0x5a, 0x85, 0x20, 0xbc, 0x4e, 0x6f,
- 0x5f, 0xe9, 0x5b, 0x1f, 0xe3, 0xc8, 0x45, 0x2b},
+ .digest = "\x33\x91\xfd\xdd\xfc\x8d\xc7\x39"
+ "\x37\x07\xa6\x5b\x1b\x47\x09\x39"
+ "\x7c\xf8\xb1\xd1\x62\xaf\x05\xab"
+ "\xfe\x8f\x45\x0d\xe5\xf3\x6b\xc6"
+ "\xb0\x45\x5a\x85\x20\xbc\x4e\x6f"
+ "\x5f\xe9\x5b\x1f\xe3\xc8\x45\x2b",
}, {
.plaintext = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn"
- "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu",
+ "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu",
.psize = 112,
- .digest = { 0x09, 0x33, 0x0c, 0x33, 0xf7, 0x11, 0x47, 0xe8,
- 0x3d, 0x19, 0x2f, 0xc7, 0x82, 0xcd, 0x1b, 0x47,
- 0x53, 0x11, 0x1b, 0x17, 0x3b, 0x3b, 0x05, 0xd2,
- 0x2f, 0xa0, 0x80, 0x86, 0xe3, 0xb0, 0xf7, 0x12,
- 0xfc, 0xc7, 0xc7, 0x1a, 0x55, 0x7e, 0x2d, 0xb9,
- 0x66, 0xc3, 0xe9, 0xfa, 0x91, 0x74, 0x60, 0x39 },
+ .digest = "\x09\x33\x0c\x33\xf7\x11\x47\xe8"
+ "\x3d\x19\x2f\xc7\x82\xcd\x1b\x47"
+ "\x53\x11\x1b\x17\x3b\x3b\x05\xd2"
+ "\x2f\xa0\x80\x86\xe3\xb0\xf7\x12"
+ "\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9"
+ "\x66\xc3\xe9\xfa\x91\x74\x60\x39",
}, {
.plaintext = "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcd"
- "efghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz",
+ "efghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz",
.psize = 104,
- .digest = { 0x3d, 0x20, 0x89, 0x73, 0xab, 0x35, 0x08, 0xdb,
- 0xbd, 0x7e, 0x2c, 0x28, 0x62, 0xba, 0x29, 0x0a,
- 0xd3, 0x01, 0x0e, 0x49, 0x78, 0xc1, 0x98, 0xdc,
- 0x4d, 0x8f, 0xd0, 0x14, 0xe5, 0x82, 0x82, 0x3a,
- 0x89, 0xe1, 0x6f, 0x9b, 0x2a, 0x7b, 0xbc, 0x1a,
- 0xc9, 0x38, 0xe2, 0xd1, 0x99, 0xe8, 0xbe, 0xa4 },
+ .digest = "\x3d\x20\x89\x73\xab\x35\x08\xdb"
+ "\xbd\x7e\x2c\x28\x62\xba\x29\x0a"
+ "\xd3\x01\x0e\x49\x78\xc1\x98\xdc"
+ "\x4d\x8f\xd0\x14\xe5\x82\x82\x3a"
+ "\x89\xe1\x6f\x9b\x2a\x7b\xbc\x1a"
+ "\xc9\x38\xe2\xd1\x99\xe8\xbe\xa4",
.np = 4,
.tap = { 26, 26, 26, 26 }
},
{
.plaintext = "abc",
.psize = 3,
- .digest = { 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba,
- 0xcc, 0x41, 0x73, 0x49, 0xae, 0x20, 0x41, 0x31,
- 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2,
- 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a,
- 0x21, 0x92, 0x99, 0x2a, 0x27, 0x4f, 0xc1, 0xa8,
- 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd,
- 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e,
- 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f },
+ .digest = "\xdd\xaf\x35\xa1\x93\x61\x7a\xba"
+ "\xcc\x41\x73\x49\xae\x20\x41\x31"
+ "\x12\xe6\xfa\x4e\x89\xa9\x7e\xa2"
+ "\x0a\x9e\xee\xe6\x4b\x55\xd3\x9a"
+ "\x21\x92\x99\x2a\x27\x4f\xc1\xa8"
+ "\x36\xba\x3c\x23\xa3\xfe\xeb\xbd"
+ "\x45\x4d\x44\x23\x64\x3c\xe8\x0e"
+ "\x2a\x9a\xc9\x4f\xa5\x4c\xa4\x9f",
}, {
.plaintext = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq",
.psize = 56,
- .digest = { 0x20, 0x4a, 0x8f, 0xc6, 0xdd, 0xa8, 0x2f, 0x0a,
- 0x0c, 0xed, 0x7b, 0xeb, 0x8e, 0x08, 0xa4, 0x16,
- 0x57, 0xc1, 0x6e, 0xf4, 0x68, 0xb2, 0x28, 0xa8,
- 0x27, 0x9b, 0xe3, 0x31, 0xa7, 0x03, 0xc3, 0x35,
- 0x96, 0xfd, 0x15, 0xc1, 0x3b, 0x1b, 0x07, 0xf9,
- 0xaa, 0x1d, 0x3b, 0xea, 0x57, 0x78, 0x9c, 0xa0,
- 0x31, 0xad, 0x85, 0xc7, 0xa7, 0x1d, 0xd7, 0x03,
- 0x54, 0xec, 0x63, 0x12, 0x38, 0xca, 0x34, 0x45 },
+ .digest = "\x20\x4a\x8f\xc6\xdd\xa8\x2f\x0a"
+ "\x0c\xed\x7b\xeb\x8e\x08\xa4\x16"
+ "\x57\xc1\x6e\xf4\x68\xb2\x28\xa8"
+ "\x27\x9b\xe3\x31\xa7\x03\xc3\x35"
+ "\x96\xfd\x15\xc1\x3b\x1b\x07\xf9"
+ "\xaa\x1d\x3b\xea\x57\x78\x9c\xa0"
+ "\x31\xad\x85\xc7\xa7\x1d\xd7\x03"
+ "\x54\xec\x63\x12\x38\xca\x34\x45",
}, {
.plaintext = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn"
- "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu",
+ "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu",
.psize = 112,
- .digest = { 0x8e, 0x95, 0x9b, 0x75, 0xda, 0xe3, 0x13, 0xda,
- 0x8c, 0xf4, 0xf7, 0x28, 0x14, 0xfc, 0x14, 0x3f,
- 0x8f, 0x77, 0x79, 0xc6, 0xeb, 0x9f, 0x7f, 0xa1,
- 0x72, 0x99, 0xae, 0xad, 0xb6, 0x88, 0x90, 0x18,
- 0x50, 0x1d, 0x28, 0x9e, 0x49, 0x00, 0xf7, 0xe4,
- 0x33, 0x1b, 0x99, 0xde, 0xc4, 0xb5, 0x43, 0x3a,
- 0xc7, 0xd3, 0x29, 0xee, 0xb6, 0xdd, 0x26, 0x54,
- 0x5e, 0x96, 0xe5, 0x5b, 0x87, 0x4b, 0xe9, 0x09 },
+ .digest = "\x8e\x95\x9b\x75\xda\xe3\x13\xda"
+ "\x8c\xf4\xf7\x28\x14\xfc\x14\x3f"
+ "\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1"
+ "\x72\x99\xae\xad\xb6\x88\x90\x18"
+ "\x50\x1d\x28\x9e\x49\x00\xf7\xe4"
+ "\x33\x1b\x99\xde\xc4\xb5\x43\x3a"
+ "\xc7\xd3\x29\xee\xb6\xdd\x26\x54"
+ "\x5e\x96\xe5\x5b\x87\x4b\xe9\x09",
}, {
.plaintext = "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcd"
- "efghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz",
+ "efghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz",
.psize = 104,
- .digest = { 0x93, 0x0d, 0x0c, 0xef, 0xcb, 0x30, 0xff, 0x11,
- 0x33, 0xb6, 0x89, 0x81, 0x21, 0xf1, 0xcf, 0x3d,
- 0x27, 0x57, 0x8a, 0xfc, 0xaf, 0xe8, 0x67, 0x7c,
- 0x52, 0x57, 0xcf, 0x06, 0x99, 0x11, 0xf7, 0x5d,
- 0x8f, 0x58, 0x31, 0xb5, 0x6e, 0xbf, 0xda, 0x67,
- 0xb2, 0x78, 0xe6, 0x6d, 0xff, 0x8b, 0x84, 0xfe,
- 0x2b, 0x28, 0x70, 0xf7, 0x42, 0xa5, 0x80, 0xd8,
- 0xed, 0xb4, 0x19, 0x87, 0x23, 0x28, 0x50, 0xc9 },
+ .digest = "\x93\x0d\x0c\xef\xcb\x30\xff\x11"
+ "\x33\xb6\x89\x81\x21\xf1\xcf\x3d"
+ "\x27\x57\x8a\xfc\xaf\xe8\x67\x7c"
+ "\x52\x57\xcf\x06\x99\x11\xf7\x5d"
+ "\x8f\x58\x31\xb5\x6e\xbf\xda\x67"
+ "\xb2\x78\xe6\x6d\xff\x8b\x84\xfe"
+ "\x2b\x28\x70\xf7\x42\xa5\x80\xd8"
+ "\xed\xb4\x19\x87\x23\x28\x50\xc9",
.np = 4,
.tap = { 26, 26, 26, 26 }
},
{
.plaintext = "",
.psize = 0,
- .digest = { 0x19, 0xFA, 0x61, 0xD7, 0x55, 0x22, 0xA4, 0x66,
- 0x9B, 0x44, 0xE3, 0x9C, 0x1D, 0x2E, 0x17, 0x26,
- 0xC5, 0x30, 0x23, 0x21, 0x30, 0xD4, 0x07, 0xF8,
- 0x9A, 0xFE, 0xE0, 0x96, 0x49, 0x97, 0xF7, 0xA7,
- 0x3E, 0x83, 0xBE, 0x69, 0x8B, 0x28, 0x8F, 0xEB,
- 0xCF, 0x88, 0xE3, 0xE0, 0x3C, 0x4F, 0x07, 0x57,
- 0xEA, 0x89, 0x64, 0xE5, 0x9B, 0x63, 0xD9, 0x37,
- 0x08, 0xB1, 0x38, 0xCC, 0x42, 0xA6, 0x6E, 0xB3 },
+ .digest = "\x19\xFA\x61\xD7\x55\x22\xA4\x66"
+ "\x9B\x44\xE3\x9C\x1D\x2E\x17\x26"
+ "\xC5\x30\x23\x21\x30\xD4\x07\xF8"
+ "\x9A\xFE\xE0\x96\x49\x97\xF7\xA7"
+ "\x3E\x83\xBE\x69\x8B\x28\x8F\xEB"
+ "\xCF\x88\xE3\xE0\x3C\x4F\x07\x57"
+ "\xEA\x89\x64\xE5\x9B\x63\xD9\x37"
+ "\x08\xB1\x38\xCC\x42\xA6\x6E\xB3",
}, {
.plaintext = "a",
.psize = 1,
- .digest = { 0x8A, 0xCA, 0x26, 0x02, 0x79, 0x2A, 0xEC, 0x6F,
- 0x11, 0xA6, 0x72, 0x06, 0x53, 0x1F, 0xB7, 0xD7,
- 0xF0, 0xDF, 0xF5, 0x94, 0x13, 0x14, 0x5E, 0x69,
- 0x73, 0xC4, 0x50, 0x01, 0xD0, 0x08, 0x7B, 0x42,
- 0xD1, 0x1B, 0xC6, 0x45, 0x41, 0x3A, 0xEF, 0xF6,
- 0x3A, 0x42, 0x39, 0x1A, 0x39, 0x14, 0x5A, 0x59,
- 0x1A, 0x92, 0x20, 0x0D, 0x56, 0x01, 0x95, 0xE5,
- 0x3B, 0x47, 0x85, 0x84, 0xFD, 0xAE, 0x23, 0x1A },
+ .digest = "\x8A\xCA\x26\x02\x79\x2A\xEC\x6F"
+ "\x11\xA6\x72\x06\x53\x1F\xB7\xD7"
+ "\xF0\xDF\xF5\x94\x13\x14\x5E\x69"
+ "\x73\xC4\x50\x01\xD0\x08\x7B\x42"
+ "\xD1\x1B\xC6\x45\x41\x3A\xEF\xF6"
+ "\x3A\x42\x39\x1A\x39\x14\x5A\x59"
+ "\x1A\x92\x20\x0D\x56\x01\x95\xE5"
+ "\x3B\x47\x85\x84\xFD\xAE\x23\x1A",
}, {
.plaintext = "abc",
.psize = 3,
- .digest = { 0x4E, 0x24, 0x48, 0xA4, 0xC6, 0xF4, 0x86, 0xBB,
- 0x16, 0xB6, 0x56, 0x2C, 0x73, 0xB4, 0x02, 0x0B,
- 0xF3, 0x04, 0x3E, 0x3A, 0x73, 0x1B, 0xCE, 0x72,
- 0x1A, 0xE1, 0xB3, 0x03, 0xD9, 0x7E, 0x6D, 0x4C,
- 0x71, 0x81, 0xEE, 0xBD, 0xB6, 0xC5, 0x7E, 0x27,
- 0x7D, 0x0E, 0x34, 0x95, 0x71, 0x14, 0xCB, 0xD6,
- 0xC7, 0x97, 0xFC, 0x9D, 0x95, 0xD8, 0xB5, 0x82,
- 0xD2, 0x25, 0x29, 0x20, 0x76, 0xD4, 0xEE, 0xF5 },
+ .digest = "\x4E\x24\x48\xA4\xC6\xF4\x86\xBB"
+ "\x16\xB6\x56\x2C\x73\xB4\x02\x0B"
+ "\xF3\x04\x3E\x3A\x73\x1B\xCE\x72"
+ "\x1A\xE1\xB3\x03\xD9\x7E\x6D\x4C"
+ "\x71\x81\xEE\xBD\xB6\xC5\x7E\x27"
+ "\x7D\x0E\x34\x95\x71\x14\xCB\xD6"
+ "\xC7\x97\xFC\x9D\x95\xD8\xB5\x82"
+ "\xD2\x25\x29\x20\x76\xD4\xEE\xF5",
}, {
.plaintext = "message digest",
.psize = 14,
- .digest = { 0x37, 0x8C, 0x84, 0xA4, 0x12, 0x6E, 0x2D, 0xC6,
- 0xE5, 0x6D, 0xCC, 0x74, 0x58, 0x37, 0x7A, 0xAC,
- 0x83, 0x8D, 0x00, 0x03, 0x22, 0x30, 0xF5, 0x3C,
- 0xE1, 0xF5, 0x70, 0x0C, 0x0F, 0xFB, 0x4D, 0x3B,
- 0x84, 0x21, 0x55, 0x76, 0x59, 0xEF, 0x55, 0xC1,
- 0x06, 0xB4, 0xB5, 0x2A, 0xC5, 0xA4, 0xAA, 0xA6,
- 0x92, 0xED, 0x92, 0x00, 0x52, 0x83, 0x8F, 0x33,
- 0x62, 0xE8, 0x6D, 0xBD, 0x37, 0xA8, 0x90, 0x3E },
+ .digest = "\x37\x8C\x84\xA4\x12\x6E\x2D\xC6"
+ "\xE5\x6D\xCC\x74\x58\x37\x7A\xAC"
+ "\x83\x8D\x00\x03\x22\x30\xF5\x3C"
+ "\xE1\xF5\x70\x0C\x0F\xFB\x4D\x3B"
+ "\x84\x21\x55\x76\x59\xEF\x55\xC1"
+ "\x06\xB4\xB5\x2A\xC5\xA4\xAA\xA6"
+ "\x92\xED\x92\x00\x52\x83\x8F\x33"
+ "\x62\xE8\x6D\xBD\x37\xA8\x90\x3E",
}, {
.plaintext = "abcdefghijklmnopqrstuvwxyz",
.psize = 26,
- .digest = { 0xF1, 0xD7, 0x54, 0x66, 0x26, 0x36, 0xFF, 0xE9,
- 0x2C, 0x82, 0xEB, 0xB9, 0x21, 0x2A, 0x48, 0x4A,
- 0x8D, 0x38, 0x63, 0x1E, 0xAD, 0x42, 0x38, 0xF5,
- 0x44, 0x2E, 0xE1, 0x3B, 0x80, 0x54, 0xE4, 0x1B,
- 0x08, 0xBF, 0x2A, 0x92, 0x51, 0xC3, 0x0B, 0x6A,
- 0x0B, 0x8A, 0xAE, 0x86, 0x17, 0x7A, 0xB4, 0xA6,
- 0xF6, 0x8F, 0x67, 0x3E, 0x72, 0x07, 0x86, 0x5D,
- 0x5D, 0x98, 0x19, 0xA3, 0xDB, 0xA4, 0xEB, 0x3B },
+ .digest = "\xF1\xD7\x54\x66\x26\x36\xFF\xE9"
+ "\x2C\x82\xEB\xB9\x21\x2A\x48\x4A"
+ "\x8D\x38\x63\x1E\xAD\x42\x38\xF5"
+ "\x44\x2E\xE1\x3B\x80\x54\xE4\x1B"
+ "\x08\xBF\x2A\x92\x51\xC3\x0B\x6A"
+ "\x0B\x8A\xAE\x86\x17\x7A\xB4\xA6"
+ "\xF6\x8F\x67\x3E\x72\x07\x86\x5D"
+ "\x5D\x98\x19\xA3\xDB\xA4\xEB\x3B",
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
- "abcdefghijklmnopqrstuvwxyz0123456789",
+ "abcdefghijklmnopqrstuvwxyz0123456789",
.psize = 62,
- .digest = { 0xDC, 0x37, 0xE0, 0x08, 0xCF, 0x9E, 0xE6, 0x9B,
- 0xF1, 0x1F, 0x00, 0xED, 0x9A, 0xBA, 0x26, 0x90,
- 0x1D, 0xD7, 0xC2, 0x8C, 0xDE, 0xC0, 0x66, 0xCC,
- 0x6A, 0xF4, 0x2E, 0x40, 0xF8, 0x2F, 0x3A, 0x1E,
- 0x08, 0xEB, 0xA2, 0x66, 0x29, 0x12, 0x9D, 0x8F,
- 0xB7, 0xCB, 0x57, 0x21, 0x1B, 0x92, 0x81, 0xA6,
- 0x55, 0x17, 0xCC, 0x87, 0x9D, 0x7B, 0x96, 0x21,
- 0x42, 0xC6, 0x5F, 0x5A, 0x7A, 0xF0, 0x14, 0x67 },
+ .digest = "\xDC\x37\xE0\x08\xCF\x9E\xE6\x9B"
+ "\xF1\x1F\x00\xED\x9A\xBA\x26\x90"
+ "\x1D\xD7\xC2\x8C\xDE\xC0\x66\xCC"
+ "\x6A\xF4\x2E\x40\xF8\x2F\x3A\x1E"
+ "\x08\xEB\xA2\x66\x29\x12\x9D\x8F"
+ "\xB7\xCB\x57\x21\x1B\x92\x81\xA6"
+ "\x55\x17\xCC\x87\x9D\x7B\x96\x21"
+ "\x42\xC6\x5F\x5A\x7A\xF0\x14\x67",
}, {
.plaintext = "1234567890123456789012345678901234567890"
- "1234567890123456789012345678901234567890",
+ "1234567890123456789012345678901234567890",
.psize = 80,
- .digest = { 0x46, 0x6E, 0xF1, 0x8B, 0xAB, 0xB0, 0x15, 0x4D,
- 0x25, 0xB9, 0xD3, 0x8A, 0x64, 0x14, 0xF5, 0xC0,
- 0x87, 0x84, 0x37, 0x2B, 0xCC, 0xB2, 0x04, 0xD6,
- 0x54, 0x9C, 0x4A, 0xFA, 0xDB, 0x60, 0x14, 0x29,
- 0x4D, 0x5B, 0xD8, 0xDF, 0x2A, 0x6C, 0x44, 0xE5,
- 0x38, 0xCD, 0x04, 0x7B, 0x26, 0x81, 0xA5, 0x1A,
- 0x2C, 0x60, 0x48, 0x1E, 0x88, 0xC5, 0xA2, 0x0B,
- 0x2C, 0x2A, 0x80, 0xCF, 0x3A, 0x9A, 0x08, 0x3B },
+ .digest = "\x46\x6E\xF1\x8B\xAB\xB0\x15\x4D"
+ "\x25\xB9\xD3\x8A\x64\x14\xF5\xC0"
+ "\x87\x84\x37\x2B\xCC\xB2\x04\xD6"
+ "\x54\x9C\x4A\xFA\xDB\x60\x14\x29"
+ "\x4D\x5B\xD8\xDF\x2A\x6C\x44\xE5"
+ "\x38\xCD\x04\x7B\x26\x81\xA5\x1A"
+ "\x2C\x60\x48\x1E\x88\xC5\xA2\x0B"
+ "\x2C\x2A\x80\xCF\x3A\x9A\x08\x3B",
}, {
.plaintext = "abcdbcdecdefdefgefghfghighijhijk",
.psize = 32,
- .digest = { 0x2A, 0x98, 0x7E, 0xA4, 0x0F, 0x91, 0x70, 0x61,
- 0xF5, 0xD6, 0xF0, 0xA0, 0xE4, 0x64, 0x4F, 0x48,
- 0x8A, 0x7A, 0x5A, 0x52, 0xDE, 0xEE, 0x65, 0x62,
- 0x07, 0xC5, 0x62, 0xF9, 0x88, 0xE9, 0x5C, 0x69,
- 0x16, 0xBD, 0xC8, 0x03, 0x1B, 0xC5, 0xBE, 0x1B,
- 0x7B, 0x94, 0x76, 0x39, 0xFE, 0x05, 0x0B, 0x56,
- 0x93, 0x9B, 0xAA, 0xA0, 0xAD, 0xFF, 0x9A, 0xE6,
- 0x74, 0x5B, 0x7B, 0x18, 0x1C, 0x3B, 0xE3, 0xFD },
+ .digest = "\x2A\x98\x7E\xA4\x0F\x91\x70\x61"
+ "\xF5\xD6\xF0\xA0\xE4\x64\x4F\x48"
+ "\x8A\x7A\x5A\x52\xDE\xEE\x65\x62"
+ "\x07\xC5\x62\xF9\x88\xE9\x5C\x69"
+ "\x16\xBD\xC8\x03\x1B\xC5\xBE\x1B"
+ "\x7B\x94\x76\x39\xFE\x05\x0B\x56"
+ "\x93\x9B\xAA\xA0\xAD\xFF\x9A\xE6"
+ "\x74\x5B\x7B\x18\x1C\x3B\xE3\xFD",
},
};
{
.plaintext = "",
.psize = 0,
- .digest = { 0x19, 0xFA, 0x61, 0xD7, 0x55, 0x22, 0xA4, 0x66,
- 0x9B, 0x44, 0xE3, 0x9C, 0x1D, 0x2E, 0x17, 0x26,
- 0xC5, 0x30, 0x23, 0x21, 0x30, 0xD4, 0x07, 0xF8,
- 0x9A, 0xFE, 0xE0, 0x96, 0x49, 0x97, 0xF7, 0xA7,
- 0x3E, 0x83, 0xBE, 0x69, 0x8B, 0x28, 0x8F, 0xEB,
- 0xCF, 0x88, 0xE3, 0xE0, 0x3C, 0x4F, 0x07, 0x57 },
+ .digest = "\x19\xFA\x61\xD7\x55\x22\xA4\x66"
+ "\x9B\x44\xE3\x9C\x1D\x2E\x17\x26"
+ "\xC5\x30\x23\x21\x30\xD4\x07\xF8"
+ "\x9A\xFE\xE0\x96\x49\x97\xF7\xA7"
+ "\x3E\x83\xBE\x69\x8B\x28\x8F\xEB"
+ "\xCF\x88\xE3\xE0\x3C\x4F\x07\x57",
}, {
.plaintext = "a",
.psize = 1,
- .digest = { 0x8A, 0xCA, 0x26, 0x02, 0x79, 0x2A, 0xEC, 0x6F,
- 0x11, 0xA6, 0x72, 0x06, 0x53, 0x1F, 0xB7, 0xD7,
- 0xF0, 0xDF, 0xF5, 0x94, 0x13, 0x14, 0x5E, 0x69,
- 0x73, 0xC4, 0x50, 0x01, 0xD0, 0x08, 0x7B, 0x42,
- 0xD1, 0x1B, 0xC6, 0x45, 0x41, 0x3A, 0xEF, 0xF6,
- 0x3A, 0x42, 0x39, 0x1A, 0x39, 0x14, 0x5A, 0x59 },
+ .digest = "\x8A\xCA\x26\x02\x79\x2A\xEC\x6F"
+ "\x11\xA6\x72\x06\x53\x1F\xB7\xD7"
+ "\xF0\xDF\xF5\x94\x13\x14\x5E\x69"
+ "\x73\xC4\x50\x01\xD0\x08\x7B\x42"
+ "\xD1\x1B\xC6\x45\x41\x3A\xEF\xF6"
+ "\x3A\x42\x39\x1A\x39\x14\x5A\x59",
}, {
.plaintext = "abc",
.psize = 3,
- .digest = { 0x4E, 0x24, 0x48, 0xA4, 0xC6, 0xF4, 0x86, 0xBB,
- 0x16, 0xB6, 0x56, 0x2C, 0x73, 0xB4, 0x02, 0x0B,
- 0xF3, 0x04, 0x3E, 0x3A, 0x73, 0x1B, 0xCE, 0x72,
- 0x1A, 0xE1, 0xB3, 0x03, 0xD9, 0x7E, 0x6D, 0x4C,
- 0x71, 0x81, 0xEE, 0xBD, 0xB6, 0xC5, 0x7E, 0x27,
- 0x7D, 0x0E, 0x34, 0x95, 0x71, 0x14, 0xCB, 0xD6 },
+ .digest = "\x4E\x24\x48\xA4\xC6\xF4\x86\xBB"
+ "\x16\xB6\x56\x2C\x73\xB4\x02\x0B"
+ "\xF3\x04\x3E\x3A\x73\x1B\xCE\x72"
+ "\x1A\xE1\xB3\x03\xD9\x7E\x6D\x4C"
+ "\x71\x81\xEE\xBD\xB6\xC5\x7E\x27"
+ "\x7D\x0E\x34\x95\x71\x14\xCB\xD6",
}, {
.plaintext = "message digest",
.psize = 14,
- .digest = { 0x37, 0x8C, 0x84, 0xA4, 0x12, 0x6E, 0x2D, 0xC6,
- 0xE5, 0x6D, 0xCC, 0x74, 0x58, 0x37, 0x7A, 0xAC,
- 0x83, 0x8D, 0x00, 0x03, 0x22, 0x30, 0xF5, 0x3C,
- 0xE1, 0xF5, 0x70, 0x0C, 0x0F, 0xFB, 0x4D, 0x3B,
- 0x84, 0x21, 0x55, 0x76, 0x59, 0xEF, 0x55, 0xC1,
- 0x06, 0xB4, 0xB5, 0x2A, 0xC5, 0xA4, 0xAA, 0xA6 },
+ .digest = "\x37\x8C\x84\xA4\x12\x6E\x2D\xC6"
+ "\xE5\x6D\xCC\x74\x58\x37\x7A\xAC"
+ "\x83\x8D\x00\x03\x22\x30\xF5\x3C"
+ "\xE1\xF5\x70\x0C\x0F\xFB\x4D\x3B"
+ "\x84\x21\x55\x76\x59\xEF\x55\xC1"
+ "\x06\xB4\xB5\x2A\xC5\xA4\xAA\xA6",
}, {
.plaintext = "abcdefghijklmnopqrstuvwxyz",
.psize = 26,
- .digest = { 0xF1, 0xD7, 0x54, 0x66, 0x26, 0x36, 0xFF, 0xE9,
- 0x2C, 0x82, 0xEB, 0xB9, 0x21, 0x2A, 0x48, 0x4A,
- 0x8D, 0x38, 0x63, 0x1E, 0xAD, 0x42, 0x38, 0xF5,
- 0x44, 0x2E, 0xE1, 0x3B, 0x80, 0x54, 0xE4, 0x1B,
- 0x08, 0xBF, 0x2A, 0x92, 0x51, 0xC3, 0x0B, 0x6A,
- 0x0B, 0x8A, 0xAE, 0x86, 0x17, 0x7A, 0xB4, 0xA6 },
+ .digest = "\xF1\xD7\x54\x66\x26\x36\xFF\xE9"
+ "\x2C\x82\xEB\xB9\x21\x2A\x48\x4A"
+ "\x8D\x38\x63\x1E\xAD\x42\x38\xF5"
+ "\x44\x2E\xE1\x3B\x80\x54\xE4\x1B"
+ "\x08\xBF\x2A\x92\x51\xC3\x0B\x6A"
+ "\x0B\x8A\xAE\x86\x17\x7A\xB4\xA6",
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
- "abcdefghijklmnopqrstuvwxyz0123456789",
+ "abcdefghijklmnopqrstuvwxyz0123456789",
.psize = 62,
- .digest = { 0xDC, 0x37, 0xE0, 0x08, 0xCF, 0x9E, 0xE6, 0x9B,
- 0xF1, 0x1F, 0x00, 0xED, 0x9A, 0xBA, 0x26, 0x90,
- 0x1D, 0xD7, 0xC2, 0x8C, 0xDE, 0xC0, 0x66, 0xCC,
- 0x6A, 0xF4, 0x2E, 0x40, 0xF8, 0x2F, 0x3A, 0x1E,
- 0x08, 0xEB, 0xA2, 0x66, 0x29, 0x12, 0x9D, 0x8F,
- 0xB7, 0xCB, 0x57, 0x21, 0x1B, 0x92, 0x81, 0xA6 },
+ .digest = "\xDC\x37\xE0\x08\xCF\x9E\xE6\x9B"
+ "\xF1\x1F\x00\xED\x9A\xBA\x26\x90"
+ "\x1D\xD7\xC2\x8C\xDE\xC0\x66\xCC"
+ "\x6A\xF4\x2E\x40\xF8\x2F\x3A\x1E"
+ "\x08\xEB\xA2\x66\x29\x12\x9D\x8F"
+ "\xB7\xCB\x57\x21\x1B\x92\x81\xA6",
}, {
.plaintext = "1234567890123456789012345678901234567890"
- "1234567890123456789012345678901234567890",
+ "1234567890123456789012345678901234567890",
.psize = 80,
- .digest = { 0x46, 0x6E, 0xF1, 0x8B, 0xAB, 0xB0, 0x15, 0x4D,
- 0x25, 0xB9, 0xD3, 0x8A, 0x64, 0x14, 0xF5, 0xC0,
- 0x87, 0x84, 0x37, 0x2B, 0xCC, 0xB2, 0x04, 0xD6,
- 0x54, 0x9C, 0x4A, 0xFA, 0xDB, 0x60, 0x14, 0x29,
- 0x4D, 0x5B, 0xD8, 0xDF, 0x2A, 0x6C, 0x44, 0xE5,
- 0x38, 0xCD, 0x04, 0x7B, 0x26, 0x81, 0xA5, 0x1A },
+ .digest = "\x46\x6E\xF1\x8B\xAB\xB0\x15\x4D"
+ "\x25\xB9\xD3\x8A\x64\x14\xF5\xC0"
+ "\x87\x84\x37\x2B\xCC\xB2\x04\xD6"
+ "\x54\x9C\x4A\xFA\xDB\x60\x14\x29"
+ "\x4D\x5B\xD8\xDF\x2A\x6C\x44\xE5"
+ "\x38\xCD\x04\x7B\x26\x81\xA5\x1A",
}, {
.plaintext = "abcdbcdecdefdefgefghfghighijhijk",
.psize = 32,
- .digest = { 0x2A, 0x98, 0x7E, 0xA4, 0x0F, 0x91, 0x70, 0x61,
- 0xF5, 0xD6, 0xF0, 0xA0, 0xE4, 0x64, 0x4F, 0x48,
- 0x8A, 0x7A, 0x5A, 0x52, 0xDE, 0xEE, 0x65, 0x62,
- 0x07, 0xC5, 0x62, 0xF9, 0x88, 0xE9, 0x5C, 0x69,
- 0x16, 0xBD, 0xC8, 0x03, 0x1B, 0xC5, 0xBE, 0x1B,
- 0x7B, 0x94, 0x76, 0x39, 0xFE, 0x05, 0x0B, 0x56 },
+ .digest = "\x2A\x98\x7E\xA4\x0F\x91\x70\x61"
+ "\xF5\xD6\xF0\xA0\xE4\x64\x4F\x48"
+ "\x8A\x7A\x5A\x52\xDE\xEE\x65\x62"
+ "\x07\xC5\x62\xF9\x88\xE9\x5C\x69"
+ "\x16\xBD\xC8\x03\x1B\xC5\xBE\x1B"
+ "\x7B\x94\x76\x39\xFE\x05\x0B\x56",
},
};
{
.plaintext = "",
.psize = 0,
- .digest = { 0x19, 0xFA, 0x61, 0xD7, 0x55, 0x22, 0xA4, 0x66,
- 0x9B, 0x44, 0xE3, 0x9C, 0x1D, 0x2E, 0x17, 0x26,
- 0xC5, 0x30, 0x23, 0x21, 0x30, 0xD4, 0x07, 0xF8,
- 0x9A, 0xFE, 0xE0, 0x96, 0x49, 0x97, 0xF7, 0xA7 },
+ .digest = "\x19\xFA\x61\xD7\x55\x22\xA4\x66"
+ "\x9B\x44\xE3\x9C\x1D\x2E\x17\x26"
+ "\xC5\x30\x23\x21\x30\xD4\x07\xF8"
+ "\x9A\xFE\xE0\x96\x49\x97\xF7\xA7",
}, {
.plaintext = "a",
.psize = 1,
- .digest = { 0x8A, 0xCA, 0x26, 0x02, 0x79, 0x2A, 0xEC, 0x6F,
- 0x11, 0xA6, 0x72, 0x06, 0x53, 0x1F, 0xB7, 0xD7,
- 0xF0, 0xDF, 0xF5, 0x94, 0x13, 0x14, 0x5E, 0x69,
- 0x73, 0xC4, 0x50, 0x01, 0xD0, 0x08, 0x7B, 0x42 },
+ .digest = "\x8A\xCA\x26\x02\x79\x2A\xEC\x6F"
+ "\x11\xA6\x72\x06\x53\x1F\xB7\xD7"
+ "\xF0\xDF\xF5\x94\x13\x14\x5E\x69"
+ "\x73\xC4\x50\x01\xD0\x08\x7B\x42",
}, {
.plaintext = "abc",
.psize = 3,
- .digest = { 0x4E, 0x24, 0x48, 0xA4, 0xC6, 0xF4, 0x86, 0xBB,
- 0x16, 0xB6, 0x56, 0x2C, 0x73, 0xB4, 0x02, 0x0B,
- 0xF3, 0x04, 0x3E, 0x3A, 0x73, 0x1B, 0xCE, 0x72,
- 0x1A, 0xE1, 0xB3, 0x03, 0xD9, 0x7E, 0x6D, 0x4C },
+ .digest = "\x4E\x24\x48\xA4\xC6\xF4\x86\xBB"
+ "\x16\xB6\x56\x2C\x73\xB4\x02\x0B"
+ "\xF3\x04\x3E\x3A\x73\x1B\xCE\x72"
+ "\x1A\xE1\xB3\x03\xD9\x7E\x6D\x4C",
}, {
.plaintext = "message digest",
.psize = 14,
- .digest = { 0x37, 0x8C, 0x84, 0xA4, 0x12, 0x6E, 0x2D, 0xC6,
- 0xE5, 0x6D, 0xCC, 0x74, 0x58, 0x37, 0x7A, 0xAC,
- 0x83, 0x8D, 0x00, 0x03, 0x22, 0x30, 0xF5, 0x3C,
- 0xE1, 0xF5, 0x70, 0x0C, 0x0F, 0xFB, 0x4D, 0x3B },
+ .digest = "\x37\x8C\x84\xA4\x12\x6E\x2D\xC6"
+ "\xE5\x6D\xCC\x74\x58\x37\x7A\xAC"
+ "\x83\x8D\x00\x03\x22\x30\xF5\x3C"
+ "\xE1\xF5\x70\x0C\x0F\xFB\x4D\x3B",
}, {
.plaintext = "abcdefghijklmnopqrstuvwxyz",
.psize = 26,
- .digest = { 0xF1, 0xD7, 0x54, 0x66, 0x26, 0x36, 0xFF, 0xE9,
- 0x2C, 0x82, 0xEB, 0xB9, 0x21, 0x2A, 0x48, 0x4A,
- 0x8D, 0x38, 0x63, 0x1E, 0xAD, 0x42, 0x38, 0xF5,
- 0x44, 0x2E, 0xE1, 0x3B, 0x80, 0x54, 0xE4, 0x1B },
+ .digest = "\xF1\xD7\x54\x66\x26\x36\xFF\xE9"
+ "\x2C\x82\xEB\xB9\x21\x2A\x48\x4A"
+ "\x8D\x38\x63\x1E\xAD\x42\x38\xF5"
+ "\x44\x2E\xE1\x3B\x80\x54\xE4\x1B",
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
- "abcdefghijklmnopqrstuvwxyz0123456789",
+ "abcdefghijklmnopqrstuvwxyz0123456789",
.psize = 62,
- .digest = { 0xDC, 0x37, 0xE0, 0x08, 0xCF, 0x9E, 0xE6, 0x9B,
- 0xF1, 0x1F, 0x00, 0xED, 0x9A, 0xBA, 0x26, 0x90,
- 0x1D, 0xD7, 0xC2, 0x8C, 0xDE, 0xC0, 0x66, 0xCC,
- 0x6A, 0xF4, 0x2E, 0x40, 0xF8, 0x2F, 0x3A, 0x1E },
+ .digest = "\xDC\x37\xE0\x08\xCF\x9E\xE6\x9B"
+ "\xF1\x1F\x00\xED\x9A\xBA\x26\x90"
+ "\x1D\xD7\xC2\x8C\xDE\xC0\x66\xCC"
+ "\x6A\xF4\x2E\x40\xF8\x2F\x3A\x1E",
}, {
.plaintext = "1234567890123456789012345678901234567890"
- "1234567890123456789012345678901234567890",
+ "1234567890123456789012345678901234567890",
.psize = 80,
- .digest = { 0x46, 0x6E, 0xF1, 0x8B, 0xAB, 0xB0, 0x15, 0x4D,
- 0x25, 0xB9, 0xD3, 0x8A, 0x64, 0x14, 0xF5, 0xC0,
- 0x87, 0x84, 0x37, 0x2B, 0xCC, 0xB2, 0x04, 0xD6,
- 0x54, 0x9C, 0x4A, 0xFA, 0xDB, 0x60, 0x14, 0x29 },
+ .digest = "\x46\x6E\xF1\x8B\xAB\xB0\x15\x4D"
+ "\x25\xB9\xD3\x8A\x64\x14\xF5\xC0"
+ "\x87\x84\x37\x2B\xCC\xB2\x04\xD6"
+ "\x54\x9C\x4A\xFA\xDB\x60\x14\x29",
}, {
.plaintext = "abcdbcdecdefdefgefghfghighijhijk",
.psize = 32,
- .digest = { 0x2A, 0x98, 0x7E, 0xA4, 0x0F, 0x91, 0x70, 0x61,
- 0xF5, 0xD6, 0xF0, 0xA0, 0xE4, 0x64, 0x4F, 0x48,
- 0x8A, 0x7A, 0x5A, 0x52, 0xDE, 0xEE, 0x65, 0x62,
- 0x07, 0xC5, 0x62, 0xF9, 0x88, 0xE9, 0x5C, 0x69 },
+ .digest = "\x2A\x98\x7E\xA4\x0F\x91\x70\x61"
+ "\xF5\xD6\xF0\xA0\xE4\x64\x4F\x48"
+ "\x8A\x7A\x5A\x52\xDE\xEE\x65\x62"
+ "\x07\xC5\x62\xF9\x88\xE9\x5C\x69",
},
};
{
.plaintext = "",
.psize = 0,
- .digest = { 0x24, 0xf0, 0x13, 0x0c, 0x63, 0xac, 0x93, 0x32,
- 0x16, 0x16, 0x6e, 0x76, 0xb1, 0xbb, 0x92, 0x5f,
- 0xf3, 0x73, 0xde, 0x2d, 0x49, 0x58, 0x4e, 0x7a },
+ .digest = "\x24\xf0\x13\x0c\x63\xac\x93\x32"
+ "\x16\x16\x6e\x76\xb1\xbb\x92\x5f"
+ "\xf3\x73\xde\x2d\x49\x58\x4e\x7a",
}, {
.plaintext = "abc",
.psize = 3,
- .digest = { 0xf2, 0x58, 0xc1, 0xe8, 0x84, 0x14, 0xab, 0x2a,
- 0x52, 0x7a, 0xb5, 0x41, 0xff, 0xc5, 0xb8, 0xbf,
- 0x93, 0x5f, 0x7b, 0x95, 0x1c, 0x13, 0x29, 0x51 },
+ .digest = "\xf2\x58\xc1\xe8\x84\x14\xab\x2a"
+ "\x52\x7a\xb5\x41\xff\xc5\xb8\xbf"
+ "\x93\x5f\x7b\x95\x1c\x13\x29\x51",
}, {
.plaintext = "Tiger",
.psize = 5,
- .digest = { 0x9f, 0x00, 0xf5, 0x99, 0x07, 0x23, 0x00, 0xdd,
- 0x27, 0x6a, 0xbb, 0x38, 0xc8, 0xeb, 0x6d, 0xec,
- 0x37, 0x79, 0x0c, 0x11, 0x6f, 0x9d, 0x2b, 0xdf },
+ .digest = "\x9f\x00\xf5\x99\x07\x23\x00\xdd"
+ "\x27\x6a\xbb\x38\xc8\xeb\x6d\xec"
+ "\x37\x79\x0c\x11\x6f\x9d\x2b\xdf",
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+-",
.psize = 64,
- .digest = { 0x87, 0xfb, 0x2a, 0x90, 0x83, 0x85, 0x1c, 0xf7,
- 0x47, 0x0d, 0x2c, 0xf8, 0x10, 0xe6, 0xdf, 0x9e,
- 0xb5, 0x86, 0x44, 0x50, 0x34, 0xa5, 0xa3, 0x86 },
+ .digest = "\x87\xfb\x2a\x90\x83\x85\x1c\xf7"
+ "\x47\x0d\x2c\xf8\x10\xe6\xdf\x9e"
+ "\xb5\x86\x44\x50\x34\xa5\xa3\x86",
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZ=abcdefghijklmnopqrstuvwxyz+0123456789",
.psize = 64,
- .digest = { 0x46, 0x7d, 0xb8, 0x08, 0x63, 0xeb, 0xce, 0x48,
- 0x8d, 0xf1, 0xcd, 0x12, 0x61, 0x65, 0x5d, 0xe9,
- 0x57, 0x89, 0x65, 0x65, 0x97, 0x5f, 0x91, 0x97 },
+ .digest = "\x46\x7d\xb8\x08\x63\xeb\xce\x48"
+ "\x8d\xf1\xcd\x12\x61\x65\x5d\xe9"
+ "\x57\x89\x65\x65\x97\x5f\x91\x97",
}, {
.plaintext = "Tiger - A Fast New Hash Function, "
- "by Ross Anderson and Eli Biham, "
- "proceedings of Fast Software Encryption 3, "
- "Cambridge, 1996.",
+ "by Ross Anderson and Eli Biham, "
+ "proceedings of Fast Software Encryption 3, "
+ "Cambridge, 1996.",
.psize = 125,
- .digest = { 0x3d, 0x9a, 0xeb, 0x03, 0xd1, 0xbd, 0x1a, 0x63,
- 0x57, 0xb2, 0x77, 0x4d, 0xfd, 0x6d, 0x5b, 0x24,
- 0xdd, 0x68, 0x15, 0x1d, 0x50, 0x39, 0x74, 0xfc },
+ .digest = "\x3d\x9a\xeb\x03\xd1\xbd\x1a\x63"
+ "\x57\xb2\x77\x4d\xfd\x6d\x5b\x24"
+ "\xdd\x68\x15\x1d\x50\x39\x74\xfc",
},
};
{
.plaintext = "",
.psize = 0,
- .digest = { 0x24, 0xf0, 0x13, 0x0c, 0x63, 0xac, 0x93, 0x32,
- 0x16, 0x16, 0x6e, 0x76, 0xb1, 0xbb, 0x92, 0x5f,
- 0xf3, 0x73, 0xde, 0x2d },
+ .digest = "\x24\xf0\x13\x0c\x63\xac\x93\x32"
+ "\x16\x16\x6e\x76\xb1\xbb\x92\x5f"
+ "\xf3\x73\xde\x2d",
}, {
.plaintext = "abc",
.psize = 3,
- .digest = { 0xf2, 0x58, 0xc1, 0xe8, 0x84, 0x14, 0xab, 0x2a,
- 0x52, 0x7a, 0xb5, 0x41, 0xff, 0xc5, 0xb8, 0xbf,
- 0x93, 0x5f, 0x7b, 0x95 },
+ .digest = "\xf2\x58\xc1\xe8\x84\x14\xab\x2a"
+ "\x52\x7a\xb5\x41\xff\xc5\xb8\xbf"
+ "\x93\x5f\x7b\x95",
}, {
.plaintext = "Tiger",
.psize = 5,
- .digest = { 0x9f, 0x00, 0xf5, 0x99, 0x07, 0x23, 0x00, 0xdd,
- 0x27, 0x6a, 0xbb, 0x38, 0xc8, 0xeb, 0x6d, 0xec,
- 0x37, 0x79, 0x0c, 0x11 },
+ .digest = "\x9f\x00\xf5\x99\x07\x23\x00\xdd"
+ "\x27\x6a\xbb\x38\xc8\xeb\x6d\xec"
+ "\x37\x79\x0c\x11",
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+-",
.psize = 64,
- .digest = { 0x87, 0xfb, 0x2a, 0x90, 0x83, 0x85, 0x1c, 0xf7,
- 0x47, 0x0d, 0x2c, 0xf8, 0x10, 0xe6, 0xdf, 0x9e,
- 0xb5, 0x86, 0x44, 0x50 },
+ .digest = "\x87\xfb\x2a\x90\x83\x85\x1c\xf7"
+ "\x47\x0d\x2c\xf8\x10\xe6\xdf\x9e"
+ "\xb5\x86\x44\x50",
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZ=abcdefghijklmnopqrstuvwxyz+0123456789",
.psize = 64,
- .digest = { 0x46, 0x7d, 0xb8, 0x08, 0x63, 0xeb, 0xce, 0x48,
- 0x8d, 0xf1, 0xcd, 0x12, 0x61, 0x65, 0x5d, 0xe9,
- 0x57, 0x89, 0x65, 0x65 },
+ .digest = "\x46\x7d\xb8\x08\x63\xeb\xce\x48"
+ "\x8d\xf1\xcd\x12\x61\x65\x5d\xe9"
+ "\x57\x89\x65\x65",
}, {
.plaintext = "Tiger - A Fast New Hash Function, "
- "by Ross Anderson and Eli Biham, "
- "proceedings of Fast Software Encryption 3, "
- "Cambridge, 1996.",
+ "by Ross Anderson and Eli Biham, "
+ "proceedings of Fast Software Encryption 3, "
+ "Cambridge, 1996.",
.psize = 125,
- .digest = { 0x3d, 0x9a, 0xeb, 0x03, 0xd1, 0xbd, 0x1a, 0x63,
- 0x57, 0xb2, 0x77, 0x4d, 0xfd, 0x6d, 0x5b, 0x24,
- 0xdd, 0x68, 0x15, 0x1d },
+ .digest = "\x3d\x9a\xeb\x03\xd1\xbd\x1a\x63"
+ "\x57\xb2\x77\x4d\xfd\x6d\x5b\x24"
+ "\xdd\x68\x15\x1d",
},
};
{
.plaintext = "",
.psize = 0,
- .digest = { 0x24, 0xf0, 0x13, 0x0c, 0x63, 0xac, 0x93, 0x32,
- 0x16, 0x16, 0x6e, 0x76, 0xb1, 0xbb, 0x92, 0x5f },
+ .digest = "\x24\xf0\x13\x0c\x63\xac\x93\x32"
+ "\x16\x16\x6e\x76\xb1\xbb\x92\x5f",
}, {
.plaintext = "abc",
.psize = 3,
- .digest = { 0xf2, 0x58, 0xc1, 0xe8, 0x84, 0x14, 0xab, 0x2a,
- 0x52, 0x7a, 0xb5, 0x41, 0xff, 0xc5, 0xb8, 0xbf },
+ .digest = "\xf2\x58\xc1\xe8\x84\x14\xab\x2a"
+ "\x52\x7a\xb5\x41\xff\xc5\xb8\xbf",
}, {
.plaintext = "Tiger",
.psize = 5,
- .digest = { 0x9f, 0x00, 0xf5, 0x99, 0x07, 0x23, 0x00, 0xdd,
- 0x27, 0x6a, 0xbb, 0x38, 0xc8, 0xeb, 0x6d, 0xec },
+ .digest = "\x9f\x00\xf5\x99\x07\x23\x00\xdd"
+ "\x27\x6a\xbb\x38\xc8\xeb\x6d\xec",
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+-",
.psize = 64,
- .digest = { 0x87, 0xfb, 0x2a, 0x90, 0x83, 0x85, 0x1c, 0xf7,
- 0x47, 0x0d, 0x2c, 0xf8, 0x10, 0xe6, 0xdf, 0x9e },
+ .digest = "\x87\xfb\x2a\x90\x83\x85\x1c\xf7"
+ "\x47\x0d\x2c\xf8\x10\xe6\xdf\x9e",
}, {
.plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZ=abcdefghijklmnopqrstuvwxyz+0123456789",
.psize = 64,
- .digest = { 0x46, 0x7d, 0xb8, 0x08, 0x63, 0xeb, 0xce, 0x48,
- 0x8d, 0xf1, 0xcd, 0x12, 0x61, 0x65, 0x5d, 0xe9 },
+ .digest = "\x46\x7d\xb8\x08\x63\xeb\xce\x48"
+ "\x8d\xf1\xcd\x12\x61\x65\x5d\xe9",
}, {
.plaintext = "Tiger - A Fast New Hash Function, "
- "by Ross Anderson and Eli Biham, "
- "proceedings of Fast Software Encryption 3, "
- "Cambridge, 1996.",
+ "by Ross Anderson and Eli Biham, "
+ "proceedings of Fast Software Encryption 3, "
+ "Cambridge, 1996.",
.psize = 125,
- .digest = { 0x3d, 0x9a, 0xeb, 0x03, 0xd1, 0xbd, 0x1a, 0x63,
- 0x57, 0xb2, 0x77, 0x4d, 0xfd, 0x6d, 0x5b, 0x24 },
+ .digest = "\x3d\x9a\xeb\x03\xd1\xbd\x1a\x63"
+ "\x57\xb2\x77\x4d\xfd\x6d\x5b\x24",
},
};
static struct hash_testvec hmac_md5_tv_template[] =
{
{
- .key = { [0 ... 15] = 0x0b },
+ .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b",
.ksize = 16,
.plaintext = "Hi There",
.psize = 8,
- .digest = { 0x92, 0x94, 0x72, 0x7a, 0x36, 0x38, 0xbb, 0x1c,
- 0x13, 0xf4, 0x8e, 0xf8, 0x15, 0x8b, 0xfc, 0x9d },
+ .digest = "\x92\x94\x72\x7a\x36\x38\xbb\x1c"
+ "\x13\xf4\x8e\xf8\x15\x8b\xfc\x9d",
}, {
- .key = { 'J', 'e', 'f', 'e' },
+ .key = "Jefe",
.ksize = 4,
.plaintext = "what do ya want for nothing?",
.psize = 28,
- .digest = { 0x75, 0x0c, 0x78, 0x3e, 0x6a, 0xb0, 0xb5, 0x03,
- 0xea, 0xa8, 0x6e, 0x31, 0x0a, 0x5d, 0xb7, 0x38 },
+ .digest = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03"
+ "\xea\xa8\x6e\x31\x0a\x5d\xb7\x38",
.np = 2,
.tap = {14, 14}
}, {
- .key = { [0 ... 15] = 0xaa },
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa",
.ksize = 16,
- .plaintext = { [0 ... 49] = 0xdd },
+ .plaintext = "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd"
+ "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd"
+ "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd"
+ "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd",
.psize = 50,
- .digest = { 0x56, 0xbe, 0x34, 0x52, 0x1d, 0x14, 0x4c, 0x88,
- 0xdb, 0xb8, 0xc7, 0x33, 0xf0, 0xe8, 0xb3, 0xf6 },
+ .digest = "\x56\xbe\x34\x52\x1d\x14\x4c\x88"
+ "\xdb\xb8\xc7\x33\xf0\xe8\xb3\xf6",
}, {
- .key = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
- 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
- 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, },
+ .key = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18\x19",
.ksize = 25,
- .plaintext = { [0 ... 49] = 0xcd },
+ .plaintext = "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd"
+ "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd"
+ "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd"
+ "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd",
.psize = 50,
- .digest = { 0x69, 0x7e, 0xaf, 0x0a, 0xca, 0x3a, 0x3a, 0xea,
- 0x3a, 0x75, 0x16, 0x47, 0x46, 0xff, 0xaa, 0x79 },
+ .digest = "\x69\x7e\xaf\x0a\xca\x3a\x3a\xea"
+ "\x3a\x75\x16\x47\x46\xff\xaa\x79",
}, {
- .key = { [0 ... 15] = 0x0c },
+ .key = "\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c",
.ksize = 16,
.plaintext = "Test With Truncation",
.psize = 20,
- .digest = { 0x56, 0x46, 0x1e, 0xf2, 0x34, 0x2e, 0xdc, 0x00,
- 0xf9, 0xba, 0xb9, 0x95, 0x69, 0x0e, 0xfd, 0x4c },
- }, {
- .key = { [0 ... 79] = 0xaa },
+ .digest = "\x56\x46\x1e\xf2\x34\x2e\xdc\x00"
+ "\xf9\xba\xb9\x95\x69\x0e\xfd\x4c",
+ }, {
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa",
.ksize = 80,
.plaintext = "Test Using Larger Than Block-Size Key - Hash Key First",
.psize = 54,
- .digest = { 0x6b, 0x1a, 0xb7, 0xfe, 0x4b, 0xd7, 0xbf, 0x8f,
- 0x0b, 0x62, 0xe6, 0xce, 0x61, 0xb9, 0xd0, 0xcd },
- }, {
- .key = { [0 ... 79] = 0xaa },
+ .digest = "\x6b\x1a\xb7\xfe\x4b\xd7\xbf\x8f"
+ "\x0b\x62\xe6\xce\x61\xb9\xd0\xcd",
+ }, {
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa",
.ksize = 80,
.plaintext = "Test Using Larger Than Block-Size Key and Larger Than One "
- "Block-Size Data",
+ "Block-Size Data",
.psize = 73,
- .digest = { 0x6f, 0x63, 0x0f, 0xad, 0x67, 0xcd, 0xa0, 0xee,
- 0x1f, 0xb1, 0xf5, 0x62, 0xdb, 0x3a, 0xa5, 0x3e },
+ .digest = "\x6f\x63\x0f\xad\x67\xcd\xa0\xee"
+ "\x1f\xb1\xf5\x62\xdb\x3a\xa5\x3e",
},
};
static struct hash_testvec hmac_sha1_tv_template[] = {
{
- .key = { [0 ... 19] = 0x0b },
+ .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b",
.ksize = 20,
.plaintext = "Hi There",
.psize = 8,
- .digest = { 0xb6, 0x17, 0x31, 0x86, 0x55, 0x05, 0x72, 0x64,
- 0xe2, 0x8b, 0xc0, 0xb6, 0xfb, 0x37, 0x8c, 0x8e, 0xf1,
- 0x46, 0xbe },
+ .digest = "\xb6\x17\x31\x86\x55\x05\x72\x64"
+ "\xe2\x8b\xc0\xb6\xfb\x37\x8c\x8e\xf1"
+ "\x46\xbe",
}, {
- .key = { 'J', 'e', 'f', 'e' },
+ .key = "Jefe",
.ksize = 4,
.plaintext = "what do ya want for nothing?",
.psize = 28,
- .digest = { 0xef, 0xfc, 0xdf, 0x6a, 0xe5, 0xeb, 0x2f, 0xa2, 0xd2, 0x74,
- 0x16, 0xd5, 0xf1, 0x84, 0xdf, 0x9c, 0x25, 0x9a, 0x7c, 0x79 },
+ .digest = "\xef\xfc\xdf\x6a\xe5\xeb\x2f\xa2\xd2\x74"
+ "\x16\xd5\xf1\x84\xdf\x9c\x25\x9a\x7c\x79",
.np = 2,
.tap = { 14, 14 }
}, {
- .key = { [0 ... 19] = 0xaa },
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa",
.ksize = 20,
- .plaintext = { [0 ... 49] = 0xdd },
+ .plaintext = "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd"
+ "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd"
+ "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd"
+ "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd",
.psize = 50,
- .digest = { 0x12, 0x5d, 0x73, 0x42, 0xb9, 0xac, 0x11, 0xcd, 0x91, 0xa3,
- 0x9a, 0xf4, 0x8a, 0xa1, 0x7b, 0x4f, 0x63, 0xf1, 0x75, 0xd3 },
+ .digest = "\x12\x5d\x73\x42\xb9\xac\x11\xcd\x91\xa3"
+ "\x9a\xf4\x8a\xa1\x7b\x4f\x63\xf1\x75\xd3",
}, {
- .key = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
- 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
- 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19 },
+ .key = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18\x19",
.ksize = 25,
- .plaintext = { [0 ... 49] = 0xcd },
+ .plaintext = "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd"
+ "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd"
+ "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd"
+ "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd",
.psize = 50,
- .digest = { 0x4c, 0x90, 0x07, 0xf4, 0x02, 0x62, 0x50, 0xc6, 0xbc, 0x84,
- 0x14, 0xf9, 0xbf, 0x50, 0xc8, 0x6c, 0x2d, 0x72, 0x35, 0xda },
+ .digest = "\x4c\x90\x07\xf4\x02\x62\x50\xc6\xbc\x84"
+ "\x14\xf9\xbf\x50\xc8\x6c\x2d\x72\x35\xda",
}, {
- .key = { [0 ... 19] = 0x0c },
+ .key = "\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c",
.ksize = 20,
.plaintext = "Test With Truncation",
.psize = 20,
- .digest = { 0x4c, 0x1a, 0x03, 0x42, 0x4b, 0x55, 0xe0, 0x7f, 0xe7, 0xf2,
- 0x7b, 0xe1, 0xd5, 0x8b, 0xb9, 0x32, 0x4a, 0x9a, 0x5a, 0x04 },
- }, {
- .key = { [0 ... 79] = 0xaa },
+ .digest = "\x4c\x1a\x03\x42\x4b\x55\xe0\x7f\xe7\xf2"
+ "\x7b\xe1\xd5\x8b\xb9\x32\x4a\x9a\x5a\x04",
+ }, {
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa",
.ksize = 80,
.plaintext = "Test Using Larger Than Block-Size Key - Hash Key First",
.psize = 54,
- .digest = { 0xaa, 0x4a, 0xe5, 0xe1, 0x52, 0x72, 0xd0, 0x0e, 0x95, 0x70,
- 0x56, 0x37, 0xce, 0x8a, 0x3b, 0x55, 0xed, 0x40, 0x21, 0x12 },
- }, {
- .key = { [0 ... 79] = 0xaa },
+ .digest = "\xaa\x4a\xe5\xe1\x52\x72\xd0\x0e\x95\x70"
+ "\x56\x37\xce\x8a\x3b\x55\xed\x40\x21\x12",
+ }, {
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa",
.ksize = 80,
.plaintext = "Test Using Larger Than Block-Size Key and Larger Than One "
- "Block-Size Data",
+ "Block-Size Data",
.psize = 73,
- .digest = { 0xe8, 0xe9, 0x9d, 0x0f, 0x45, 0x23, 0x7d, 0x78, 0x6d, 0x6b,
- 0xba, 0xa7, 0x96, 0x5c, 0x78, 0x08, 0xbb, 0xff, 0x1a, 0x91 },
+ .digest = "\xe8\xe9\x9d\x0f\x45\x23\x7d\x78\x6d\x6b"
+ "\xba\xa7\x96\x5c\x78\x08\xbb\xff\x1a\x91",
},
};
static struct hash_testvec hmac_sha224_tv_template[] = {
{
- .key = { 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
- 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
- 0x0b, 0x0b, 0x0b, 0x0b },
+ .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ "\x0b\x0b\x0b\x0b",
.ksize = 20,
/* ("Hi There") */
- .plaintext = { 0x48, 0x69, 0x20, 0x54, 0x68, 0x65, 0x72, 0x65 },
+ .plaintext = "\x48\x69\x20\x54\x68\x65\x72\x65",
.psize = 8,
- .digest = { 0x89, 0x6f, 0xb1, 0x12, 0x8a, 0xbb, 0xdf, 0x19,
- 0x68, 0x32, 0x10, 0x7c, 0xd4, 0x9d, 0xf3, 0x3f,
- 0x47, 0xb4, 0xb1, 0x16, 0x99, 0x12, 0xba, 0x4f,
- 0x53, 0x68, 0x4b, 0x22},
+ .digest = "\x89\x6f\xb1\x12\x8a\xbb\xdf\x19"
+ "\x68\x32\x10\x7c\xd4\x9d\xf3\x3f"
+ "\x47\xb4\xb1\x16\x99\x12\xba\x4f"
+ "\x53\x68\x4b\x22",
}, {
- .key = { 0x4a, 0x65, 0x66, 0x65 }, /* ("Jefe") */
+ .key = "Jefe",
.ksize = 4,
/* ("what do ya want for nothing?") */
- .plaintext = { 0x77, 0x68, 0x61, 0x74, 0x20, 0x64, 0x6f, 0x20,
- 0x79, 0x61, 0x20, 0x77, 0x61, 0x6e, 0x74, 0x20,
- 0x66, 0x6f, 0x72, 0x20, 0x6e, 0x6f, 0x74, 0x68,
- 0x69, 0x6e, 0x67, 0x3f },
+ .plaintext = "\x77\x68\x61\x74\x20\x64\x6f\x20"
+ "\x79\x61\x20\x77\x61\x6e\x74\x20"
+ "\x66\x6f\x72\x20\x6e\x6f\x74\x68"
+ "\x69\x6e\x67\x3f",
.psize = 28,
- .digest = { 0xa3, 0x0e, 0x01, 0x09, 0x8b, 0xc6, 0xdb, 0xbf,
- 0x45, 0x69, 0x0f, 0x3a, 0x7e, 0x9e, 0x6d, 0x0f,
- 0x8b, 0xbe, 0xa2, 0xa3, 0x9e, 0x61, 0x48, 0x00,
- 0x8f, 0xd0, 0x5e, 0x44 },
+ .digest = "\xa3\x0e\x01\x09\x8b\xc6\xdb\xbf"
+ "\x45\x69\x0f\x3a\x7e\x9e\x6d\x0f"
+ "\x8b\xbe\xa2\xa3\x9e\x61\x48\x00"
+ "\x8f\xd0\x5e\x44",
.np = 4,
.tap = { 7, 7, 7, 7 }
}, {
- .key = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa },
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa",
.ksize = 131,
/* ("Test Using Larger Than Block-Size Key - Hash Key First") */
- .plaintext = { 0x54, 0x65, 0x73, 0x74, 0x20, 0x55, 0x73, 0x69,
- 0x6e, 0x67, 0x20, 0x4c, 0x61, 0x72, 0x67, 0x65,
- 0x72, 0x20, 0x54, 0x68, 0x61, 0x6e, 0x20, 0x42,
- 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x53, 0x69, 0x7a,
- 0x65, 0x20, 0x4b, 0x65, 0x79, 0x20, 0x2d, 0x20,
- 0x48, 0x61, 0x73, 0x68, 0x20, 0x4b, 0x65, 0x79,
- 0x20, 0x46, 0x69, 0x72, 0x73, 0x74 },
+ .plaintext = "\x54\x65\x73\x74\x20\x55\x73\x69"
+ "\x6e\x67\x20\x4c\x61\x72\x67\x65"
+ "\x72\x20\x54\x68\x61\x6e\x20\x42"
+ "\x6c\x6f\x63\x6b\x2d\x53\x69\x7a"
+ "\x65\x20\x4b\x65\x79\x20\x2d\x20"
+ "\x48\x61\x73\x68\x20\x4b\x65\x79"
+ "\x20\x46\x69\x72\x73\x74",
.psize = 54,
- .digest = { 0x95, 0xe9, 0xa0, 0xdb, 0x96, 0x20, 0x95, 0xad,
- 0xae, 0xbe, 0x9b, 0x2d, 0x6f, 0x0d, 0xbc, 0xe2,
- 0xd4, 0x99, 0xf1, 0x12, 0xf2, 0xd2, 0xb7, 0x27,
- 0x3f, 0xa6, 0x87, 0x0e },
- }, {
- .key = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa },
+ .digest = "\x95\xe9\xa0\xdb\x96\x20\x95\xad"
+ "\xae\xbe\x9b\x2d\x6f\x0d\xbc\xe2"
+ "\xd4\x99\xf1\x12\xf2\xd2\xb7\x27"
+ "\x3f\xa6\x87\x0e",
+ }, {
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa",
.ksize = 131,
/* ("This is a test using a larger than block-size key and a")
(" larger than block-size data. The key needs to be")
(" hashed before being used by the HMAC algorithm.") */
- .plaintext = { 0x54, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20,
- 0x61, 0x20, 0x74, 0x65, 0x73, 0x74, 0x20, 0x75,
- 0x73, 0x69, 0x6e, 0x67, 0x20, 0x61, 0x20, 0x6c,
- 0x61, 0x72, 0x67, 0x65, 0x72, 0x20, 0x74, 0x68,
- 0x61, 0x6e, 0x20, 0x62, 0x6c, 0x6f, 0x63, 0x6b,
- 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x20, 0x6b, 0x65,
- 0x79, 0x20, 0x61, 0x6e, 0x64, 0x20, 0x61, 0x20,
- 0x6c, 0x61, 0x72, 0x67, 0x65, 0x72, 0x20, 0x74,
- 0x68, 0x61, 0x6e, 0x20, 0x62, 0x6c, 0x6f, 0x63,
- 0x6b, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x20, 0x64,
- 0x61, 0x74, 0x61, 0x2e, 0x20, 0x54, 0x68, 0x65,
- 0x20, 0x6b, 0x65, 0x79, 0x20, 0x6e, 0x65, 0x65,
- 0x64, 0x73, 0x20, 0x74, 0x6f, 0x20, 0x62, 0x65,
- 0x20, 0x68, 0x61, 0x73, 0x68, 0x65, 0x64, 0x20,
- 0x62, 0x65, 0x66, 0x6f, 0x72, 0x65, 0x20, 0x62,
- 0x65, 0x69, 0x6e, 0x67, 0x20, 0x75, 0x73, 0x65,
- 0x64, 0x20, 0x62, 0x79, 0x20, 0x74, 0x68, 0x65,
- 0x20, 0x48, 0x4d, 0x41, 0x43, 0x20, 0x61, 0x6c,
- 0x67, 0x6f, 0x72, 0x69, 0x74, 0x68, 0x6d, 0x2e },
+ .plaintext = "\x54\x68\x69\x73\x20\x69\x73\x20"
+ "\x61\x20\x74\x65\x73\x74\x20\x75"
+ "\x73\x69\x6e\x67\x20\x61\x20\x6c"
+ "\x61\x72\x67\x65\x72\x20\x74\x68"
+ "\x61\x6e\x20\x62\x6c\x6f\x63\x6b"
+ "\x2d\x73\x69\x7a\x65\x20\x6b\x65"
+ "\x79\x20\x61\x6e\x64\x20\x61\x20"
+ "\x6c\x61\x72\x67\x65\x72\x20\x74"
+ "\x68\x61\x6e\x20\x62\x6c\x6f\x63"
+ "\x6b\x2d\x73\x69\x7a\x65\x20\x64"
+ "\x61\x74\x61\x2e\x20\x54\x68\x65"
+ "\x20\x6b\x65\x79\x20\x6e\x65\x65"
+ "\x64\x73\x20\x74\x6f\x20\x62\x65"
+ "\x20\x68\x61\x73\x68\x65\x64\x20"
+ "\x62\x65\x66\x6f\x72\x65\x20\x62"
+ "\x65\x69\x6e\x67\x20\x75\x73\x65"
+ "\x64\x20\x62\x79\x20\x74\x68\x65"
+ "\x20\x48\x4d\x41\x43\x20\x61\x6c"
+ "\x67\x6f\x72\x69\x74\x68\x6d\x2e",
.psize = 152,
- .digest = { 0x3a, 0x85, 0x41, 0x66, 0xac, 0x5d, 0x9f, 0x02,
- 0x3f, 0x54, 0xd5, 0x17, 0xd0, 0xb3, 0x9d, 0xbd,
- 0x94, 0x67, 0x70, 0xdb, 0x9c, 0x2b, 0x95, 0xc9,
- 0xf6, 0xf5, 0x65, 0xd1 },
+ .digest = "\x3a\x85\x41\x66\xac\x5d\x9f\x02"
+ "\x3f\x54\xd5\x17\xd0\xb3\x9d\xbd"
+ "\x94\x67\x70\xdb\x9c\x2b\x95\xc9"
+ "\xf6\xf5\x65\xd1",
},
};
static struct hash_testvec hmac_sha256_tv_template[] = {
{
- .key = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
- 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
- 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
- 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20},
+ .key = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18"
+ "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20",
.ksize = 32,
.plaintext = "abc",
.psize = 3,
- .digest = { 0xa2, 0x1b, 0x1f, 0x5d, 0x4c, 0xf4, 0xf7, 0x3a,
- 0x4d, 0xd9, 0x39, 0x75, 0x0f, 0x7a, 0x06, 0x6a,
- 0x7f, 0x98, 0xcc, 0x13, 0x1c, 0xb1, 0x6a, 0x66,
- 0x92, 0x75, 0x90, 0x21, 0xcf, 0xab, 0x81, 0x81 },
- }, {
- .key = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
- 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
- 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
- 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20 },
+ .digest = "\xa2\x1b\x1f\x5d\x4c\xf4\xf7\x3a"
+ "\x4d\xd9\x39\x75\x0f\x7a\x06\x6a"
+ "\x7f\x98\xcc\x13\x1c\xb1\x6a\x66"
+ "\x92\x75\x90\x21\xcf\xab\x81\x81",
+ }, {
+ .key = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18"
+ "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20",
.ksize = 32,
.plaintext = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq",
.psize = 56,
- .digest = { 0x10, 0x4f, 0xdc, 0x12, 0x57, 0x32, 0x8f, 0x08,
- 0x18, 0x4b, 0xa7, 0x31, 0x31, 0xc5, 0x3c, 0xae,
- 0xe6, 0x98, 0xe3, 0x61, 0x19, 0x42, 0x11, 0x49,
- 0xea, 0x8c, 0x71, 0x24, 0x56, 0x69, 0x7d, 0x30 },
- }, {
- .key = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
- 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
- 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
- 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20 },
+ .digest = "\x10\x4f\xdc\x12\x57\x32\x8f\x08"
+ "\x18\x4b\xa7\x31\x31\xc5\x3c\xae"
+ "\xe6\x98\xe3\x61\x19\x42\x11\x49"
+ "\xea\x8c\x71\x24\x56\x69\x7d\x30",
+ }, {
+ .key = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18"
+ "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20",
.ksize = 32,
.plaintext = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
- "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq",
+ "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq",
.psize = 112,
- .digest = { 0x47, 0x03, 0x05, 0xfc, 0x7e, 0x40, 0xfe, 0x34,
- 0xd3, 0xee, 0xb3, 0xe7, 0x73, 0xd9, 0x5a, 0xab,
- 0x73, 0xac, 0xf0, 0xfd, 0x06, 0x04, 0x47, 0xa5,
- 0xeb, 0x45, 0x95, 0xbf, 0x33, 0xa9, 0xd1, 0xa3 },
- }, {
- .key = { [0 ... 31] = 0x0b },
+ .digest = "\x47\x03\x05\xfc\x7e\x40\xfe\x34"
+ "\xd3\xee\xb3\xe7\x73\xd9\x5a\xab"
+ "\x73\xac\xf0\xfd\x06\x04\x47\xa5"
+ "\xeb\x45\x95\xbf\x33\xa9\xd1\xa3",
+ }, {
+ .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ "\x0b\x0b\x0b\x0b\x0b\x0b",
.ksize = 32,
.plaintext = "Hi There",
.psize = 8,
- .digest = { 0x19, 0x8a, 0x60, 0x7e, 0xb4, 0x4b, 0xfb, 0xc6,
- 0x99, 0x03, 0xa0, 0xf1, 0xcf, 0x2b, 0xbd, 0xc5,
- 0xba, 0x0a, 0xa3, 0xf3, 0xd9, 0xae, 0x3c, 0x1c,
- 0x7a, 0x3b, 0x16, 0x96, 0xa0, 0xb6, 0x8c, 0xf7 },
+ .digest = "\x19\x8a\x60\x7e\xb4\x4b\xfb\xc6"
+ "\x99\x03\xa0\xf1\xcf\x2b\xbd\xc5"
+ "\xba\x0a\xa3\xf3\xd9\xae\x3c\x1c"
+ "\x7a\x3b\x16\x96\xa0\xb6\x8c\xf7",
}, {
.key = "Jefe",
.ksize = 4,
.plaintext = "what do ya want for nothing?",
.psize = 28,
- .digest = { 0x5b, 0xdc, 0xc1, 0x46, 0xbf, 0x60, 0x75, 0x4e,
- 0x6a, 0x04, 0x24, 0x26, 0x08, 0x95, 0x75, 0xc7,
- 0x5a, 0x00, 0x3f, 0x08, 0x9d, 0x27, 0x39, 0x83,
- 0x9d, 0xec, 0x58, 0xb9, 0x64, 0xec, 0x38, 0x43 },
+ .digest = "\x5b\xdc\xc1\x46\xbf\x60\x75\x4e"
+ "\x6a\x04\x24\x26\x08\x95\x75\xc7"
+ "\x5a\x00\x3f\x08\x9d\x27\x39\x83"
+ "\x9d\xec\x58\xb9\x64\xec\x38\x43",
.np = 2,
.tap = { 14, 14 }
}, {
- .key = { [0 ... 31] = 0xaa },
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa",
.ksize = 32,
- .plaintext = { [0 ... 49] = 0xdd },
+ .plaintext = "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd"
+ "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd"
+ "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd"
+ "\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd\xdd",
.psize = 50,
- .digest = { 0xcd, 0xcb, 0x12, 0x20, 0xd1, 0xec, 0xcc, 0xea,
- 0x91, 0xe5, 0x3a, 0xba, 0x30, 0x92, 0xf9, 0x62,
- 0xe5, 0x49, 0xfe, 0x6c, 0xe9, 0xed, 0x7f, 0xdc,
- 0x43, 0x19, 0x1f, 0xbd, 0xe4, 0x5c, 0x30, 0xb0 },
- }, {
- .key = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
- 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
- 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
- 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20,
- 0x21, 0x22, 0x23, 0x24, 0x25 },
+ .digest = "\xcd\xcb\x12\x20\xd1\xec\xcc\xea"
+ "\x91\xe5\x3a\xba\x30\x92\xf9\x62"
+ "\xe5\x49\xfe\x6c\xe9\xed\x7f\xdc"
+ "\x43\x19\x1f\xbd\xe4\x5c\x30\xb0",
+ }, {
+ .key = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18"
+ "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
+ "\x21\x22\x23\x24\x25",
.ksize = 37,
- .plaintext = { [0 ... 49] = 0xcd },
+ .plaintext = "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd"
+ "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd"
+ "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd"
+ "\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd\xcd",
.psize = 50,
- .digest = { 0xd4, 0x63, 0x3c, 0x17, 0xf6, 0xfb, 0x8d, 0x74,
- 0x4c, 0x66, 0xde, 0xe0, 0xf8, 0xf0, 0x74, 0x55,
- 0x6e, 0xc4, 0xaf, 0x55, 0xef, 0x07, 0x99, 0x85,
- 0x41, 0x46, 0x8e, 0xb4, 0x9b, 0xd2, 0xe9, 0x17 },
- }, {
- .key = { [0 ... 31] = 0x0c },
+ .digest = "\xd4\x63\x3c\x17\xf6\xfb\x8d\x74"
+ "\x4c\x66\xde\xe0\xf8\xf0\x74\x55"
+ "\x6e\xc4\xaf\x55\xef\x07\x99\x85"
+ "\x41\x46\x8e\xb4\x9b\xd2\xe9\x17",
+ }, {
+ .key = "\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c"
+ "\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c\x0c"
+ "\x0c\x0c\x0c\x0c\x0c\x0c",
.ksize = 32,
.plaintext = "Test With Truncation",
.psize = 20,
- .digest = { 0x75, 0x46, 0xaf, 0x01, 0x84, 0x1f, 0xc0, 0x9b,
- 0x1a, 0xb9, 0xc3, 0x74, 0x9a, 0x5f, 0x1c, 0x17,
- 0xd4, 0xf5, 0x89, 0x66, 0x8a, 0x58, 0x7b, 0x27,
- 0x00, 0xa9, 0xc9, 0x7c, 0x11, 0x93, 0xcf, 0x42 },
- }, {
- .key = { [0 ... 79] = 0xaa },
+ .digest = "\x75\x46\xaf\x01\x84\x1f\xc0\x9b"
+ "\x1a\xb9\xc3\x74\x9a\x5f\x1c\x17"
+ "\xd4\xf5\x89\x66\x8a\x58\x7b\x27"
+ "\x00\xa9\xc9\x7c\x11\x93\xcf\x42",
+ }, {
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa",
.ksize = 80,
.plaintext = "Test Using Larger Than Block-Size Key - Hash Key First",
.psize = 54,
- .digest = { 0x69, 0x53, 0x02, 0x5e, 0xd9, 0x6f, 0x0c, 0x09,
- 0xf8, 0x0a, 0x96, 0xf7, 0x8e, 0x65, 0x38, 0xdb,
- 0xe2, 0xe7, 0xb8, 0x20, 0xe3, 0xdd, 0x97, 0x0e,
- 0x7d, 0xdd, 0x39, 0x09, 0x1b, 0x32, 0x35, 0x2f },
- }, {
- .key = { [0 ... 79] = 0xaa },
+ .digest = "\x69\x53\x02\x5e\xd9\x6f\x0c\x09"
+ "\xf8\x0a\x96\xf7\x8e\x65\x38\xdb"
+ "\xe2\xe7\xb8\x20\xe3\xdd\x97\x0e"
+ "\x7d\xdd\x39\x09\x1b\x32\x35\x2f",
+ }, {
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa",
.ksize = 80,
.plaintext = "Test Using Larger Than Block-Size Key and Larger Than "
- "One Block-Size Data",
+ "One Block-Size Data",
.psize = 73,
- .digest = { 0x63, 0x55, 0xac, 0x22, 0xe8, 0x90, 0xd0, 0xa3,
- 0xc8, 0x48, 0x1a, 0x5c, 0xa4, 0x82, 0x5b, 0xc8,
- 0x84, 0xd3, 0xe7, 0xa1, 0xff, 0x98, 0xa2, 0xfc,
- 0x2a, 0xc7, 0xd8, 0xe0, 0x64, 0xc3, 0xb2, 0xe6 },
+ .digest = "\x63\x55\xac\x22\xe8\x90\xd0\xa3"
+ "\xc8\x48\x1a\x5c\xa4\x82\x5b\xc8"
+ "\x84\xd3\xe7\xa1\xff\x98\xa2\xfc"
+ "\x2a\xc7\xd8\xe0\x64\xc3\xb2\xe6",
},
};
static struct hash_testvec aes_xcbc128_tv_template[] = {
{
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .plaintext = { [0 ... 15] = 0 },
- .digest = { 0x75, 0xf0, 0x25, 0x1d, 0x52, 0x8a, 0xc0, 0x1c,
- 0x45, 0x73, 0xdf, 0xd5, 0x84, 0xd7, 0x9f, 0x29 },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .plaintext = zeroed_string,
+ .digest = "\x75\xf0\x25\x1d\x52\x8a\xc0\x1c"
+ "\x45\x73\xdf\xd5\x84\xd7\x9f\x29",
.psize = 0,
.ksize = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .plaintext = { 0x00, 0x01, 0x02 },
- .digest = { 0x5b, 0x37, 0x65, 0x80, 0xae, 0x2f, 0x19, 0xaf,
- 0xe7, 0x21, 0x9c, 0xee, 0xf1, 0x72, 0x75, 0x6f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .plaintext = "\x00\x01\x02",
+ .digest = "\x5b\x37\x65\x80\xae\x2f\x19\xaf"
+ "\xe7\x21\x9c\xee\xf1\x72\x75\x6f",
.psize = 3,
.ksize = 16,
} , {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .plaintext = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .digest = { 0xd2, 0xa2, 0x46, 0xfa, 0x34, 0x9b, 0x68, 0xa7,
- 0x99, 0x98, 0xa4, 0x39, 0x4f, 0xf7, 0xa2, 0x63 },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .plaintext = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .digest = "\xd2\xa2\x46\xfa\x34\x9b\x68\xa7"
+ "\x99\x98\xa4\x39\x4f\xf7\xa2\x63",
.psize = 16,
.ksize = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .plaintext = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13 },
- .digest = { 0x47, 0xf5, 0x1b, 0x45, 0x64, 0x96, 0x62, 0x15,
- 0xb8, 0x98, 0x5c, 0x63, 0x05, 0x5e, 0xd3, 0x08 },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .plaintext = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13",
+ .digest = "\x47\xf5\x1b\x45\x64\x96\x62\x15"
+ "\xb8\x98\x5c\x63\x05\x5e\xd3\x08",
.tap = { 10, 10 },
.psize = 20,
.np = 2,
.ksize = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .plaintext = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
- .digest = { 0xf5, 0x4f, 0x0e, 0xc8, 0xd2, 0xb9, 0xf3, 0xd3,
- 0x68, 0x07, 0x73, 0x4b, 0xd5, 0x28, 0x3f, 0xd4 },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .plaintext = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+ .digest = "\xf5\x4f\x0e\xc8\xd2\xb9\xf3\xd3"
+ "\x68\x07\x73\x4b\xd5\x28\x3f\xd4",
.psize = 32,
.ksize = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .plaintext = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- 0x20, 0x21 },
- .digest = { 0xbe, 0xcb, 0xb3, 0xbc, 0xcd, 0xb5, 0x18, 0xa3,
- 0x06, 0x77, 0xd5, 0x48, 0x1f, 0xb6, 0xb4, 0xd8 },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .plaintext = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
+ "\x20\x21",
+ .digest = "\xbe\xcb\xb3\xbc\xcd\xb5\x18\xa3"
+ "\x06\x77\xd5\x48\x1f\xb6\xb4\xd8",
.tap = { 17, 17 },
.psize = 34,
.np = 2,
static struct hash_testvec hmac_sha384_tv_template[] = {
{
- .key = { 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
- 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
- 0x0b, 0x0b, 0x0b, 0x0b }, // (20 bytes)
+ .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ "\x0b\x0b\x0b\x0b",
.ksize = 20,
- .plaintext = { 0x48, 0x69, 0x20, 0x54, 0x68, 0x65, 0x72, 0x65 }, // ("Hi There")
+ .plaintext = "Hi There",
.psize = 8,
- .digest = { 0xaf, 0xd0, 0x39, 0x44, 0xd8, 0x48, 0x95, 0x62,
- 0x6b, 0x08, 0x25, 0xf4, 0xab, 0x46, 0x90, 0x7f,
- 0x15, 0xf9, 0xda, 0xdb, 0xe4, 0x10, 0x1e, 0xc6,
- 0x82, 0xaa, 0x03, 0x4c, 0x7c, 0xeb, 0xc5, 0x9c,
- 0xfa, 0xea, 0x9e, 0xa9, 0x07, 0x6e, 0xde, 0x7f,
- 0x4a, 0xf1, 0x52, 0xe8, 0xb2, 0xfa, 0x9c, 0xb6 },
- }, {
- .key = { 0x4a, 0x65, 0x66, 0x65 }, // ("Jefe")
+ .digest = "\xaf\xd0\x39\x44\xd8\x48\x95\x62"
+ "\x6b\x08\x25\xf4\xab\x46\x90\x7f"
+ "\x15\xf9\xda\xdb\xe4\x10\x1e\xc6"
+ "\x82\xaa\x03\x4c\x7c\xeb\xc5\x9c"
+ "\xfa\xea\x9e\xa9\x07\x6e\xde\x7f"
+ "\x4a\xf1\x52\xe8\xb2\xfa\x9c\xb6",
+ }, {
+ .key = "Jefe",
.ksize = 4,
- .plaintext = { 0x77, 0x68, 0x61, 0x74, 0x20, 0x64, 0x6f, 0x20,
- 0x79, 0x61, 0x20, 0x77, 0x61, 0x6e, 0x74, 0x20, // ("what do ya want ")
- 0x66, 0x6f, 0x72, 0x20, 0x6e, 0x6f, 0x74, 0x68,
- 0x69, 0x6e, 0x67, 0x3f }, // ("for nothing?")
+ .plaintext = "what do ya want for nothing?",
.psize = 28,
- .digest = { 0xaf, 0x45, 0xd2, 0xe3, 0x76, 0x48, 0x40, 0x31,
- 0x61, 0x7f, 0x78, 0xd2, 0xb5, 0x8a, 0x6b, 0x1b,
- 0x9c, 0x7e, 0xf4, 0x64, 0xf5, 0xa0, 0x1b, 0x47,
- 0xe4, 0x2e, 0xc3, 0x73, 0x63, 0x22, 0x44, 0x5e,
- 0x8e, 0x22, 0x40, 0xca, 0x5e, 0x69, 0xe2, 0xc7,
- 0x8b, 0x32, 0x39, 0xec, 0xfa, 0xb2, 0x16, 0x49 },
+ .digest = "\xaf\x45\xd2\xe3\x76\x48\x40\x31"
+ "\x61\x7f\x78\xd2\xb5\x8a\x6b\x1b"
+ "\x9c\x7e\xf4\x64\xf5\xa0\x1b\x47"
+ "\xe4\x2e\xc3\x73\x63\x22\x44\x5e"
+ "\x8e\x22\x40\xca\x5e\x69\xe2\xc7"
+ "\x8b\x32\x39\xec\xfa\xb2\x16\x49",
.np = 4,
.tap = { 7, 7, 7, 7 }
}, {
- .key = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa }, // (131 bytes)
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa",
.ksize = 131,
- .plaintext = { 0x54, 0x65, 0x73, 0x74, 0x20, 0x55, 0x73, 0x69,
- 0x6e, 0x67, 0x20, 0x4c, 0x61, 0x72, 0x67, 0x65, // ("Test Using Large")
- 0x72, 0x20, 0x54, 0x68, 0x61, 0x6e, 0x20, 0x42,
- 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x53, 0x69, 0x7a, // ("r Than Block-Siz")
- 0x65, 0x20, 0x4b, 0x65, 0x79, 0x20, 0x2d, 0x20,
- 0x48, 0x61, 0x73, 0x68, 0x20, 0x4b, 0x65, 0x79, // ("e Key - Hash Key")
- 0x20, 0x46, 0x69, 0x72, 0x73, 0x74 }, // (" First")
+ .plaintext = "Test Using Larger Than Block-Siz"
+ "e Key - Hash Key First",
.psize = 54,
- .digest = { 0x4e, 0xce, 0x08, 0x44, 0x85, 0x81, 0x3e, 0x90,
- 0x88, 0xd2, 0xc6, 0x3a, 0x04, 0x1b, 0xc5, 0xb4,
- 0x4f, 0x9e, 0xf1, 0x01, 0x2a, 0x2b, 0x58, 0x8f,
- 0x3c, 0xd1, 0x1f, 0x05, 0x03, 0x3a, 0xc4, 0xc6,
- 0x0c, 0x2e, 0xf6, 0xab, 0x40, 0x30, 0xfe, 0x82,
- 0x96, 0x24, 0x8d, 0xf1, 0x63, 0xf4, 0x49, 0x52 },
- }, {
- .key = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa }, // (131 bytes)
+ .digest = "\x4e\xce\x08\x44\x85\x81\x3e\x90"
+ "\x88\xd2\xc6\x3a\x04\x1b\xc5\xb4"
+ "\x4f\x9e\xf1\x01\x2a\x2b\x58\x8f"
+ "\x3c\xd1\x1f\x05\x03\x3a\xc4\xc6"
+ "\x0c\x2e\xf6\xab\x40\x30\xfe\x82"
+ "\x96\x24\x8d\xf1\x63\xf4\x49\x52",
+ }, {
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa",
.ksize = 131,
- .plaintext = { 0x54, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20,
- 0x61, 0x20, 0x74, 0x65, 0x73, 0x74, 0x20, 0x75, // ("This is a test u")
- 0x73, 0x69, 0x6e, 0x67, 0x20, 0x61, 0x20, 0x6c,
- 0x61, 0x72, 0x67, 0x65, 0x72, 0x20, 0x74, 0x68, // ("sing a larger th")
- 0x61, 0x6e, 0x20, 0x62, 0x6c, 0x6f, 0x63, 0x6b,
- 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x20, 0x6b, 0x65, // ("an block-size ke")
- 0x79, 0x20, 0x61, 0x6e, 0x64, 0x20, 0x61, 0x20,
- 0x6c, 0x61, 0x72, 0x67, 0x65, 0x72, 0x20, 0x74, // ("y and a larger t")
- 0x68, 0x61, 0x6e, 0x20, 0x62, 0x6c, 0x6f, 0x63,
- 0x6b, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x20, 0x64, // ("han block-size d")
- 0x61, 0x74, 0x61, 0x2e, 0x20, 0x54, 0x68, 0x65,
- 0x20, 0x6b, 0x65, 0x79, 0x20, 0x6e, 0x65, 0x65, // ("ata. The key nee")
- 0x64, 0x73, 0x20, 0x74, 0x6f, 0x20, 0x62, 0x65,
- 0x20, 0x68, 0x61, 0x73, 0x68, 0x65, 0x64, 0x20, // ("ds to be hashed ")
- 0x62, 0x65, 0x66, 0x6f, 0x72, 0x65, 0x20, 0x62,
- 0x65, 0x69, 0x6e, 0x67, 0x20, 0x75, 0x73, 0x65, // ("before being use")
- 0x64, 0x20, 0x62, 0x79, 0x20, 0x74, 0x68, 0x65,
- 0x20, 0x48, 0x4d, 0x41, 0x43, 0x20, 0x61, 0x6c, // ("d by the HMAC al")
- 0x67, 0x6f, 0x72, 0x69, 0x74, 0x68, 0x6d, 0x2e }, // ("gorithm.")
+ .plaintext = "This is a test u"
+ "sing a larger th"
+ "an block-size ke"
+ "y and a larger t"
+ "han block-size d"
+ "ata. The key nee"
+ "ds to be hashed "
+ "before being use"
+ "d by the HMAC al"
+ "gorithm.",
.psize = 152,
- .digest = { 0x66, 0x17, 0x17, 0x8e, 0x94, 0x1f, 0x02, 0x0d,
- 0x35, 0x1e, 0x2f, 0x25, 0x4e, 0x8f, 0xd3, 0x2c,
- 0x60, 0x24, 0x20, 0xfe, 0xb0, 0xb8, 0xfb, 0x9a,
- 0xdc, 0xce, 0xbb, 0x82, 0x46, 0x1e, 0x99, 0xc5,
- 0xa6, 0x78, 0xcc, 0x31, 0xe7, 0x99, 0x17, 0x6d,
- 0x38, 0x60, 0xe6, 0x11, 0x0c, 0x46, 0x52, 0x3e },
+ .digest = "\x66\x17\x17\x8e\x94\x1f\x02\x0d"
+ "\x35\x1e\x2f\x25\x4e\x8f\xd3\x2c"
+ "\x60\x24\x20\xfe\xb0\xb8\xfb\x9a"
+ "\xdc\xce\xbb\x82\x46\x1e\x99\xc5"
+ "\xa6\x78\xcc\x31\xe7\x99\x17\x6d"
+ "\x38\x60\xe6\x11\x0c\x46\x52\x3e",
},
};
static struct hash_testvec hmac_sha512_tv_template[] = {
{
- .key = { 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
- 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b,
- 0x0b, 0x0b, 0x0b, 0x0b }, // (20 bytes)
+ .key = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ "\x0b\x0b\x0b\x0b",
.ksize = 20,
- .plaintext = { 0x48, 0x69, 0x20, 0x54, 0x68, 0x65, 0x72, 0x65 }, // ("Hi There")
+ .plaintext = "Hi There",
.psize = 8,
- .digest = { 0x87, 0xaa, 0x7c, 0xde, 0xa5, 0xef, 0x61, 0x9d,
- 0x4f, 0xf0, 0xb4, 0x24, 0x1a, 0x1d, 0x6c, 0xb0,
- 0x23, 0x79, 0xf4, 0xe2, 0xce, 0x4e, 0xc2, 0x78,
- 0x7a, 0xd0, 0xb3, 0x05, 0x45, 0xe1, 0x7c, 0xde,
- 0xda, 0xa8, 0x33, 0xb7, 0xd6, 0xb8, 0xa7, 0x02,
- 0x03, 0x8b, 0x27, 0x4e, 0xae, 0xa3, 0xf4, 0xe4,
- 0xbe, 0x9d, 0x91, 0x4e, 0xeb, 0x61, 0xf1, 0x70,
- 0x2e, 0x69, 0x6c, 0x20, 0x3a, 0x12, 0x68, 0x54 },
- }, {
- .key = { 0x4a, 0x65, 0x66, 0x65 }, // ("Jefe")
+ .digest = "\x87\xaa\x7c\xde\xa5\xef\x61\x9d"
+ "\x4f\xf0\xb4\x24\x1a\x1d\x6c\xb0"
+ "\x23\x79\xf4\xe2\xce\x4e\xc2\x78"
+ "\x7a\xd0\xb3\x05\x45\xe1\x7c\xde"
+ "\xda\xa8\x33\xb7\xd6\xb8\xa7\x02"
+ "\x03\x8b\x27\x4e\xae\xa3\xf4\xe4"
+ "\xbe\x9d\x91\x4e\xeb\x61\xf1\x70"
+ "\x2e\x69\x6c\x20\x3a\x12\x68\x54",
+ }, {
+ .key = "Jefe",
.ksize = 4,
- .plaintext = { 0x77, 0x68, 0x61, 0x74, 0x20, 0x64, 0x6f, 0x20,
- 0x79, 0x61, 0x20, 0x77, 0x61, 0x6e, 0x74, 0x20, // ("what do ya want ")
- 0x66, 0x6f, 0x72, 0x20, 0x6e, 0x6f, 0x74, 0x68,
- 0x69, 0x6e, 0x67, 0x3f }, // ("for nothing?")
+ .plaintext = "what do ya want for nothing?",
.psize = 28,
- .digest = { 0x16, 0x4b, 0x7a, 0x7b, 0xfc, 0xf8, 0x19, 0xe2,
- 0xe3, 0x95, 0xfb, 0xe7, 0x3b, 0x56, 0xe0, 0xa3,
- 0x87, 0xbd, 0x64, 0x22, 0x2e, 0x83, 0x1f, 0xd6,
- 0x10, 0x27, 0x0c, 0xd7, 0xea, 0x25, 0x05, 0x54,
- 0x97, 0x58, 0xbf, 0x75, 0xc0, 0x5a, 0x99, 0x4a,
- 0x6d, 0x03, 0x4f, 0x65, 0xf8, 0xf0, 0xe6, 0xfd,
- 0xca, 0xea, 0xb1, 0xa3, 0x4d, 0x4a, 0x6b, 0x4b,
- 0x63, 0x6e, 0x07, 0x0a, 0x38, 0xbc, 0xe7, 0x37 },
+ .digest = "\x16\x4b\x7a\x7b\xfc\xf8\x19\xe2"
+ "\xe3\x95\xfb\xe7\x3b\x56\xe0\xa3"
+ "\x87\xbd\x64\x22\x2e\x83\x1f\xd6"
+ "\x10\x27\x0c\xd7\xea\x25\x05\x54"
+ "\x97\x58\xbf\x75\xc0\x5a\x99\x4a"
+ "\x6d\x03\x4f\x65\xf8\xf0\xe6\xfd"
+ "\xca\xea\xb1\xa3\x4d\x4a\x6b\x4b"
+ "\x63\x6e\x07\x0a\x38\xbc\xe7\x37",
.np = 4,
.tap = { 7, 7, 7, 7 }
}, {
- .key = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa }, // (131 bytes)
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa",
.ksize = 131,
- .plaintext = { 0x54, 0x65, 0x73, 0x74, 0x20, 0x55, 0x73, 0x69,
- 0x6e, 0x67, 0x20, 0x4c, 0x61, 0x72, 0x67, 0x65, // ("Test Using Large")
- 0x72, 0x20, 0x54, 0x68, 0x61, 0x6e, 0x20, 0x42,
- 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x53, 0x69, 0x7a, // ("r Than Block-Siz")
- 0x65, 0x20, 0x4b, 0x65, 0x79, 0x20, 0x2d, 0x20,
- 0x48, 0x61, 0x73, 0x68, 0x20, 0x4b, 0x65, 0x79, // ("e Key - Hash Key")
- 0x20, 0x46, 0x69, 0x72, 0x73, 0x74 }, // (" First")
+ .plaintext = "Test Using Large"
+ "r Than Block-Siz"
+ "e Key - Hash Key"
+ " First",
.psize = 54,
- .digest = { 0x80, 0xb2, 0x42, 0x63, 0xc7, 0xc1, 0xa3, 0xeb,
- 0xb7, 0x14, 0x93, 0xc1, 0xdd, 0x7b, 0xe8, 0xb4,
- 0x9b, 0x46, 0xd1, 0xf4, 0x1b, 0x4a, 0xee, 0xc1,
- 0x12, 0x1b, 0x01, 0x37, 0x83, 0xf8, 0xf3, 0x52,
- 0x6b, 0x56, 0xd0, 0x37, 0xe0, 0x5f, 0x25, 0x98,
- 0xbd, 0x0f, 0xd2, 0x21, 0x5d, 0x6a, 0x1e, 0x52,
- 0x95, 0xe6, 0x4f, 0x73, 0xf6, 0x3f, 0x0a, 0xec,
- 0x8b, 0x91, 0x5a, 0x98, 0x5d, 0x78, 0x65, 0x98 },
- }, {
- .key = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa }, // (131 bytes)
+ .digest = "\x80\xb2\x42\x63\xc7\xc1\xa3\xeb"
+ "\xb7\x14\x93\xc1\xdd\x7b\xe8\xb4"
+ "\x9b\x46\xd1\xf4\x1b\x4a\xee\xc1"
+ "\x12\x1b\x01\x37\x83\xf8\xf3\x52"
+ "\x6b\x56\xd0\x37\xe0\x5f\x25\x98"
+ "\xbd\x0f\xd2\x21\x5d\x6a\x1e\x52"
+ "\x95\xe6\x4f\x73\xf6\x3f\x0a\xec"
+ "\x8b\x91\x5a\x98\x5d\x78\x65\x98",
+ }, {
+ .key = "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
+ "\xaa\xaa\xaa",
.ksize = 131,
- .plaintext = { 0x54, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20,
- 0x61, 0x20, 0x74, 0x65, 0x73, 0x74, 0x20, 0x75, // ("This is a test u")
- 0x73, 0x69, 0x6e, 0x67, 0x20, 0x61, 0x20, 0x6c,
- 0x61, 0x72, 0x67, 0x65, 0x72, 0x20, 0x74, 0x68, // ("sing a larger th")
- 0x61, 0x6e, 0x20, 0x62, 0x6c, 0x6f, 0x63, 0x6b,
- 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x20, 0x6b, 0x65, // ("an block-size ke")
- 0x79, 0x20, 0x61, 0x6e, 0x64, 0x20, 0x61, 0x20,
- 0x6c, 0x61, 0x72, 0x67, 0x65, 0x72, 0x20, 0x74, // ("y and a larger t")
- 0x68, 0x61, 0x6e, 0x20, 0x62, 0x6c, 0x6f, 0x63,
- 0x6b, 0x2d, 0x73, 0x69, 0x7a, 0x65, 0x20, 0x64, // ("han block-size d")
- 0x61, 0x74, 0x61, 0x2e, 0x20, 0x54, 0x68, 0x65,
- 0x20, 0x6b, 0x65, 0x79, 0x20, 0x6e, 0x65, 0x65, // ("ata. The key nee")
- 0x64, 0x73, 0x20, 0x74, 0x6f, 0x20, 0x62, 0x65,
- 0x20, 0x68, 0x61, 0x73, 0x68, 0x65, 0x64, 0x20, // ("ds to be hashed ")
- 0x62, 0x65, 0x66, 0x6f, 0x72, 0x65, 0x20, 0x62,
- 0x65, 0x69, 0x6e, 0x67, 0x20, 0x75, 0x73, 0x65, // ("before being use")
- 0x64, 0x20, 0x62, 0x79, 0x20, 0x74, 0x68, 0x65,
- 0x20, 0x48, 0x4d, 0x41, 0x43, 0x20, 0x61, 0x6c, // ("d by the HMAC al")
- 0x67, 0x6f, 0x72, 0x69, 0x74, 0x68, 0x6d, 0x2e }, // ("gorithm.")
+ .plaintext =
+ "This is a test u"
+ "sing a larger th"
+ "an block-size ke"
+ "y and a larger t"
+ "han block-size d"
+ "ata. The key nee"
+ "ds to be hashed "
+ "before being use"
+ "d by the HMAC al"
+ "gorithm.",
.psize = 152,
- .digest = { 0xe3, 0x7b, 0x6a, 0x77, 0x5d, 0xc8, 0x7d, 0xba,
- 0xa4, 0xdf, 0xa9, 0xf9, 0x6e, 0x5e, 0x3f, 0xfd,
- 0xde, 0xbd, 0x71, 0xf8, 0x86, 0x72, 0x89, 0x86,
- 0x5d, 0xf5, 0xa3, 0x2d, 0x20, 0xcd, 0xc9, 0x44,
- 0xb6, 0x02, 0x2c, 0xac, 0x3c, 0x49, 0x82, 0xb1,
- 0x0d, 0x5e, 0xeb, 0x55, 0xc3, 0xe4, 0xde, 0x15,
- 0x13, 0x46, 0x76, 0xfb, 0x6d, 0xe0, 0x44, 0x60,
- 0x65, 0xc9, 0x74, 0x40, 0xfa, 0x8c, 0x6a, 0x58 },
+ .digest = "\xe3\x7b\x6a\x77\x5d\xc8\x7d\xba"
+ "\xa4\xdf\xa9\xf9\x6e\x5e\x3f\xfd"
+ "\xde\xbd\x71\xf8\x86\x72\x89\x86"
+ "\x5d\xf5\xa3\x2d\x20\xcd\xc9\x44"
+ "\xb6\x02\x2c\xac\x3c\x49\x82\xb1"
+ "\x0d\x5e\xeb\x55\xc3\xe4\xde\x15"
+ "\x13\x46\x76\xfb\x6d\xe0\x44\x60"
+ "\x65\xc9\x74\x40\xfa\x8c\x6a\x58",
},
};
static struct cipher_testvec des_enc_tv_template[] = {
{ /* From Applied Cryptography */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7 },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xe7",
.ilen = 8,
- .result = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d },
+ .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d",
.rlen = 8,
}, { /* Same key, different plaintext block */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99 },
+ .input = "\x22\x33\x44\x55\x66\x77\x88\x99",
.ilen = 8,
- .result = { 0xf7, 0x9c, 0x89, 0x2a, 0x33, 0x8f, 0x4a, 0x8b },
+ .result = "\xf7\x9c\x89\x2a\x33\x8f\x4a\x8b",
.rlen = 8,
}, { /* Sbox test from NBS */
- .key = { 0x7c, 0xa1, 0x10, 0x45, 0x4a, 0x1a, 0x6e, 0x57 },
+ .key = "\x7c\xa1\x10\x45\x4a\x1a\x6e\x57",
.klen = 8,
- .input = { 0x01, 0xa1, 0xd6, 0xd0, 0x39, 0x77, 0x67, 0x42 },
+ .input = "\x01\xa1\xd6\xd0\x39\x77\x67\x42",
.ilen = 8,
- .result = { 0x69, 0x0f, 0x5b, 0x0d, 0x9a, 0x26, 0x93, 0x9b },
+ .result = "\x69\x0f\x5b\x0d\x9a\x26\x93\x9b",
.rlen = 8,
}, { /* Three blocks */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7,
- 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99,
- 0xca, 0xfe, 0xba, 0xbe, 0xfe, 0xed, 0xbe, 0xef },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xe7"
+ "\x22\x33\x44\x55\x66\x77\x88\x99"
+ "\xca\xfe\xba\xbe\xfe\xed\xbe\xef",
.ilen = 24,
- .result = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d,
- 0xf7, 0x9c, 0x89, 0x2a, 0x33, 0x8f, 0x4a, 0x8b,
- 0xb4, 0x99, 0x26, 0xf7, 0x1f, 0xe1, 0xd4, 0x90 },
+ .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d"
+ "\xf7\x9c\x89\x2a\x33\x8f\x4a\x8b"
+ "\xb4\x99\x26\xf7\x1f\xe1\xd4\x90",
.rlen = 24,
}, { /* Weak key */
.fail = 1,
.wk = 1,
- .key = { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 },
+ .key = "\x01\x01\x01\x01\x01\x01\x01\x01",
.klen = 8,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7 },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xe7",
.ilen = 8,
- .result = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d },
+ .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d",
.rlen = 8,
}, { /* Two blocks -- for testing encryption across pages */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7,
- 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99 },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xe7"
+ "\x22\x33\x44\x55\x66\x77\x88\x99",
.ilen = 16,
- .result = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d,
- 0xf7, 0x9c, 0x89, 0x2a, 0x33, 0x8f, 0x4a, 0x8b },
+ .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d"
+ "\xf7\x9c\x89\x2a\x33\x8f\x4a\x8b",
.rlen = 16,
.np = 2,
.tap = { 8, 8 }
}, { /* Four blocks -- for testing encryption with chunking */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7,
- 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99,
- 0xca, 0xfe, 0xba, 0xbe, 0xfe, 0xed, 0xbe, 0xef,
- 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99 },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xe7"
+ "\x22\x33\x44\x55\x66\x77\x88\x99"
+ "\xca\xfe\xba\xbe\xfe\xed\xbe\xef"
+ "\x22\x33\x44\x55\x66\x77\x88\x99",
.ilen = 32,
- .result = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d,
- 0xf7, 0x9c, 0x89, 0x2a, 0x33, 0x8f, 0x4a, 0x8b,
- 0xb4, 0x99, 0x26, 0xf7, 0x1f, 0xe1, 0xd4, 0x90,
- 0xf7, 0x9c, 0x89, 0x2a, 0x33, 0x8f, 0x4a, 0x8b },
+ .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d"
+ "\xf7\x9c\x89\x2a\x33\x8f\x4a\x8b"
+ "\xb4\x99\x26\xf7\x1f\xe1\xd4\x90"
+ "\xf7\x9c\x89\x2a\x33\x8f\x4a\x8b",
.rlen = 32,
.np = 3,
.tap = { 14, 10, 8 }
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7,
- 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99,
- 0xca, 0xfe, 0xba, 0xbe, 0xfe, 0xed, 0xbe, 0xef },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xe7"
+ "\x22\x33\x44\x55\x66\x77\x88\x99"
+ "\xca\xfe\xba\xbe\xfe\xed\xbe\xef",
.ilen = 24,
- .result = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d,
- 0xf7, 0x9c, 0x89, 0x2a, 0x33, 0x8f, 0x4a, 0x8b,
- 0xb4, 0x99, 0x26, 0xf7, 0x1f, 0xe1, 0xd4, 0x90 },
+ .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d"
+ "\xf7\x9c\x89\x2a\x33\x8f\x4a\x8b"
+ "\xb4\x99\x26\xf7\x1f\xe1\xd4\x90",
.rlen = 24,
.np = 4,
.tap = { 2, 1, 3, 18 }
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7,
- 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99 },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xe7"
+ "\x22\x33\x44\x55\x66\x77\x88\x99",
.ilen = 16,
- .result = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d,
- 0xf7, 0x9c, 0x89, 0x2a, 0x33, 0x8f, 0x4a, 0x8b },
+ .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d"
+ "\xf7\x9c\x89\x2a\x33\x8f\x4a\x8b",
.rlen = 16,
.np = 5,
.tap = { 2, 2, 2, 2, 8 }
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7 },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xe7",
.ilen = 8,
- .result = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d },
+ .result = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d",
.rlen = 8,
.np = 8,
.tap = { 1, 1, 1, 1, 1, 1, 1, 1 }
static struct cipher_testvec des_dec_tv_template[] = {
{ /* From Applied Cryptography */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d },
+ .input = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d",
.ilen = 8,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7 },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xe7",
.rlen = 8,
}, { /* Sbox test from NBS */
- .key = { 0x7c, 0xa1, 0x10, 0x45, 0x4a, 0x1a, 0x6e, 0x57 },
+ .key = "\x7c\xa1\x10\x45\x4a\x1a\x6e\x57",
.klen = 8,
- .input = { 0x69, 0x0f, 0x5b, 0x0d, 0x9a, 0x26, 0x93, 0x9b },
+ .input = "\x69\x0f\x5b\x0d\x9a\x26\x93\x9b",
.ilen = 8,
- .result = { 0x01, 0xa1, 0xd6, 0xd0, 0x39, 0x77, 0x67, 0x42 },
+ .result = "\x01\xa1\xd6\xd0\x39\x77\x67\x42",
.rlen = 8,
}, { /* Two blocks, for chunking test */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d,
- 0x69, 0x0f, 0x5b, 0x0d, 0x9a, 0x26, 0x93, 0x9b },
+ .input = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d"
+ "\x69\x0f\x5b\x0d\x9a\x26\x93\x9b",
.ilen = 16,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7,
- 0xa3, 0x99, 0x7b, 0xca, 0xaf, 0x69, 0xa0, 0xf5 },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xe7"
+ "\xa3\x99\x7b\xca\xaf\x69\xa0\xf5",
.rlen = 16,
.np = 2,
.tap = { 8, 8 }
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0xc9, 0x57, 0x44, 0x25, 0x6a, 0x5e, 0xd3, 0x1d,
- 0x69, 0x0f, 0x5b, 0x0d, 0x9a, 0x26, 0x93, 0x9b },
+ .input = "\xc9\x57\x44\x25\x6a\x5e\xd3\x1d"
+ "\x69\x0f\x5b\x0d\x9a\x26\x93\x9b",
.ilen = 16,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xe7,
- 0xa3, 0x99, 0x7b, 0xca, 0xaf, 0x69, 0xa0, 0xf5 },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xe7"
+ "\xa3\x99\x7b\xca\xaf\x69\xa0\xf5",
.rlen = 16,
.np = 3,
.tap = { 3, 12, 1 }
static struct cipher_testvec des_cbc_enc_tv_template[] = {
{ /* From OpenSSL */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef},
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .iv = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10},
- .input = { 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x20,
- 0x4e, 0x6f, 0x77, 0x20, 0x69, 0x73, 0x20, 0x74,
- 0x68, 0x65, 0x20, 0x74, 0x69, 0x6d, 0x65, 0x20 },
+ .iv = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
+ .input = "\x37\x36\x35\x34\x33\x32\x31\x20"
+ "\x4e\x6f\x77\x20\x69\x73\x20\x74"
+ "\x68\x65\x20\x74\x69\x6d\x65\x20",
.ilen = 24,
- .result = { 0xcc, 0xd1, 0x73, 0xff, 0xab, 0x20, 0x39, 0xf4,
- 0xac, 0xd8, 0xae, 0xfd, 0xdf, 0xd8, 0xa1, 0xeb,
- 0x46, 0x8e, 0x91, 0x15, 0x78, 0x88, 0xba, 0x68 },
+ .result = "\xcc\xd1\x73\xff\xab\x20\x39\xf4"
+ "\xac\xd8\xae\xfd\xdf\xd8\xa1\xeb"
+ "\x46\x8e\x91\x15\x78\x88\xba\x68",
.rlen = 24,
}, { /* FIPS Pub 81 */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .iv = { 0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef },
- .input = { 0x4e, 0x6f, 0x77, 0x20, 0x69, 0x73, 0x20, 0x74 },
+ .iv = "\x12\x34\x56\x78\x90\xab\xcd\xef",
+ .input = "\x4e\x6f\x77\x20\x69\x73\x20\x74",
.ilen = 8,
- .result = { 0xe5, 0xc7, 0xcd, 0xde, 0x87, 0x2b, 0xf2, 0x7c },
+ .result = "\xe5\xc7\xcd\xde\x87\x2b\xf2\x7c",
.rlen = 8,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .iv = { 0xe5, 0xc7, 0xcd, 0xde, 0x87, 0x2b, 0xf2, 0x7c },
- .input = { 0x68, 0x65, 0x20, 0x74, 0x69, 0x6d, 0x65, 0x20 },
+ .iv = "\xe5\xc7\xcd\xde\x87\x2b\xf2\x7c",
+ .input = "\x68\x65\x20\x74\x69\x6d\x65\x20",
.ilen = 8,
- .result = { 0x43, 0xe9, 0x34, 0x00, 0x8c, 0x38, 0x9c, 0x0f },
+ .result = "\x43\xe9\x34\x00\x8c\x38\x9c\x0f",
.rlen = 8,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .iv = { 0x43, 0xe9, 0x34, 0x00, 0x8c, 0x38, 0x9c, 0x0f },
- .input = { 0x66, 0x6f, 0x72, 0x20, 0x61, 0x6c, 0x6c, 0x20 },
+ .iv = "\x43\xe9\x34\x00\x8c\x38\x9c\x0f",
+ .input = "\x66\x6f\x72\x20\x61\x6c\x6c\x20",
.ilen = 8,
- .result = { 0x68, 0x37, 0x88, 0x49, 0x9a, 0x7c, 0x05, 0xf6 },
+ .result = "\x68\x37\x88\x49\x9a\x7c\x05\xf6",
.rlen = 8,
}, { /* Copy of openssl vector for chunk testing */
/* From OpenSSL */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef},
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .iv = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10},
- .input = { 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x20,
- 0x4e, 0x6f, 0x77, 0x20, 0x69, 0x73, 0x20, 0x74,
- 0x68, 0x65, 0x20, 0x74, 0x69, 0x6d, 0x65, 0x20 },
+ .iv = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
+ .input = "\x37\x36\x35\x34\x33\x32\x31\x20"
+ "\x4e\x6f\x77\x20\x69\x73\x20\x74"
+ "\x68\x65\x20\x74\x69\x6d\x65\x20",
.ilen = 24,
- .result = { 0xcc, 0xd1, 0x73, 0xff, 0xab, 0x20, 0x39, 0xf4,
- 0xac, 0xd8, 0xae, 0xfd, 0xdf, 0xd8, 0xa1, 0xeb,
- 0x46, 0x8e, 0x91, 0x15, 0x78, 0x88, 0xba, 0x68 },
+ .result = "\xcc\xd1\x73\xff\xab\x20\x39\xf4"
+ "\xac\xd8\xae\xfd\xdf\xd8\xa1\xeb"
+ "\x46\x8e\x91\x15\x78\x88\xba\x68",
.rlen = 24,
.np = 2,
.tap = { 13, 11 }
static struct cipher_testvec des_cbc_dec_tv_template[] = {
{ /* FIPS Pub 81 */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .iv = { 0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef },
- .input = { 0xe5, 0xc7, 0xcd, 0xde, 0x87, 0x2b, 0xf2, 0x7c },
+ .iv = "\x12\x34\x56\x78\x90\xab\xcd\xef",
+ .input = "\xe5\xc7\xcd\xde\x87\x2b\xf2\x7c",
.ilen = 8,
- .result = { 0x4e, 0x6f, 0x77, 0x20, 0x69, 0x73, 0x20, 0x74 },
+ .result = "\x4e\x6f\x77\x20\x69\x73\x20\x74",
.rlen = 8,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .iv = { 0xe5, 0xc7, 0xcd, 0xde, 0x87, 0x2b, 0xf2, 0x7c },
- .input = { 0x43, 0xe9, 0x34, 0x00, 0x8c, 0x38, 0x9c, 0x0f },
+ .iv = "\xe5\xc7\xcd\xde\x87\x2b\xf2\x7c",
+ .input = "\x43\xe9\x34\x00\x8c\x38\x9c\x0f",
.ilen = 8,
- .result = { 0x68, 0x65, 0x20, 0x74, 0x69, 0x6d, 0x65, 0x20 },
+ .result = "\x68\x65\x20\x74\x69\x6d\x65\x20",
.rlen = 8,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .iv = { 0x43, 0xe9, 0x34, 0x00, 0x8c, 0x38, 0x9c, 0x0f },
- .input = { 0x68, 0x37, 0x88, 0x49, 0x9a, 0x7c, 0x05, 0xf6 },
+ .iv = "\x43\xe9\x34\x00\x8c\x38\x9c\x0f",
+ .input = "\x68\x37\x88\x49\x9a\x7c\x05\xf6",
.ilen = 8,
- .result = { 0x66, 0x6f, 0x72, 0x20, 0x61, 0x6c, 0x6c, 0x20 },
+ .result = "\x66\x6f\x72\x20\x61\x6c\x6c\x20",
.rlen = 8,
}, { /* Copy of above, for chunk testing */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .iv = { 0x43, 0xe9, 0x34, 0x00, 0x8c, 0x38, 0x9c, 0x0f },
- .input = { 0x68, 0x37, 0x88, 0x49, 0x9a, 0x7c, 0x05, 0xf6 },
+ .iv = "\x43\xe9\x34\x00\x8c\x38\x9c\x0f",
+ .input = "\x68\x37\x88\x49\x9a\x7c\x05\xf6",
.ilen = 8,
- .result = { 0x66, 0x6f, 0x72, 0x20, 0x61, 0x6c, 0x6c, 0x20 },
+ .result = "\x66\x6f\x72\x20\x61\x6c\x6c\x20",
.rlen = 8,
.np = 2,
.tap = { 4, 4 }
*/
static struct cipher_testvec des3_ede_enc_tv_template[] = {
{ /* These are from openssl */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10},
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\x55\x55\x55\x55\x55\x55\x55\x55"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.klen = 24,
- .input = { 0x73, 0x6f, 0x6d, 0x65, 0x64, 0x61, 0x74, 0x61 },
+ .input = "\x73\x6f\x6d\x65\x64\x61\x74\x61",
.ilen = 8,
- .result = { 0x18, 0xd7, 0x48, 0xe5, 0x63, 0x62, 0x05, 0x72 },
+ .result = "\x18\xd7\x48\xe5\x63\x62\x05\x72",
.rlen = 8,
}, {
- .key = { 0x03, 0x52, 0x02, 0x07, 0x67, 0x20, 0x82, 0x17,
- 0x86, 0x02, 0x87, 0x66, 0x59, 0x08, 0x21, 0x98,
- 0x64, 0x05, 0x6a, 0xbd, 0xfe, 0xa9, 0x34, 0x57 },
+ .key = "\x03\x52\x02\x07\x67\x20\x82\x17"
+ "\x86\x02\x87\x66\x59\x08\x21\x98"
+ "\x64\x05\x6a\xbd\xfe\xa9\x34\x57",
.klen = 24,
- .input = { 0x73, 0x71, 0x75, 0x69, 0x67, 0x67, 0x6c, 0x65 },
+ .input = "\x73\x71\x75\x69\x67\x67\x6c\x65",
.ilen = 8,
- .result = { 0xc0, 0x7d, 0x2a, 0x0f, 0xa5, 0x66, 0xfa, 0x30 },
+ .result = "\xc0\x7d\x2a\x0f\xa5\x66\xfa\x30",
.rlen = 8,
}, {
- .key = { 0x10, 0x46, 0x10, 0x34, 0x89, 0x98, 0x80, 0x20,
- 0x91, 0x07, 0xd0, 0x15, 0x89, 0x19, 0x01, 0x01,
- 0x19, 0x07, 0x92, 0x10, 0x98, 0x1a, 0x01, 0x01 },
+ .key = "\x10\x46\x10\x34\x89\x98\x80\x20"
+ "\x91\x07\xd0\x15\x89\x19\x01\x01"
+ "\x19\x07\x92\x10\x98\x1a\x01\x01",
.klen = 24,
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00",
.ilen = 8,
- .result = { 0xe1, 0xef, 0x62, 0xc3, 0x32, 0xfe, 0x82, 0x5b },
+ .result = "\xe1\xef\x62\xc3\x32\xfe\x82\x5b",
.rlen = 8,
},
};
static struct cipher_testvec des3_ede_dec_tv_template[] = {
{ /* These are from openssl */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10},
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\x55\x55\x55\x55\x55\x55\x55\x55"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.klen = 24,
- .input = { 0x18, 0xd7, 0x48, 0xe5, 0x63, 0x62, 0x05, 0x72 },
+ .input = "\x18\xd7\x48\xe5\x63\x62\x05\x72",
.ilen = 8,
- .result = { 0x73, 0x6f, 0x6d, 0x65, 0x64, 0x61, 0x74, 0x61 },
+ .result = "\x73\x6f\x6d\x65\x64\x61\x74\x61",
.rlen = 8,
}, {
- .key = { 0x03, 0x52, 0x02, 0x07, 0x67, 0x20, 0x82, 0x17,
- 0x86, 0x02, 0x87, 0x66, 0x59, 0x08, 0x21, 0x98,
- 0x64, 0x05, 0x6a, 0xbd, 0xfe, 0xa9, 0x34, 0x57 },
+ .key = "\x03\x52\x02\x07\x67\x20\x82\x17"
+ "\x86\x02\x87\x66\x59\x08\x21\x98"
+ "\x64\x05\x6a\xbd\xfe\xa9\x34\x57",
.klen = 24,
- .input = { 0xc0, 0x7d, 0x2a, 0x0f, 0xa5, 0x66, 0xfa, 0x30 },
+ .input = "\xc0\x7d\x2a\x0f\xa5\x66\xfa\x30",
.ilen = 8,
- .result = { 0x73, 0x71, 0x75, 0x69, 0x67, 0x67, 0x6c, 0x65 },
+ .result = "\x73\x71\x75\x69\x67\x67\x6c\x65",
.rlen = 8,
}, {
- .key = { 0x10, 0x46, 0x10, 0x34, 0x89, 0x98, 0x80, 0x20,
- 0x91, 0x07, 0xd0, 0x15, 0x89, 0x19, 0x01, 0x01,
- 0x19, 0x07, 0x92, 0x10, 0x98, 0x1a, 0x01, 0x01 },
+ .key = "\x10\x46\x10\x34\x89\x98\x80\x20"
+ "\x91\x07\xd0\x15\x89\x19\x01\x01"
+ "\x19\x07\x92\x10\x98\x1a\x01\x01",
.klen = 24,
- .input = { 0xe1, 0xef, 0x62, 0xc3, 0x32, 0xfe, 0x82, 0x5b },
+ .input = "\xe1\xef\x62\xc3\x32\xfe\x82\x5b",
.ilen = 8,
- .result = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .result = "\x00\x00\x00\x00\x00\x00\x00\x00",
.rlen = 8,
},
};
static struct cipher_testvec bf_enc_tv_template[] = {
{ /* DES test vectors from OpenSSL */
- .key = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 8,
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00",
.ilen = 8,
- .result = { 0x4e, 0xf9, 0x97, 0x45, 0x61, 0x98, 0xdd, 0x78 },
+ .result = "\x4e\xf9\x97\x45\x61\x98\xdd\x78",
.rlen = 8,
}, {
- .key = { 0x1f, 0x1f, 0x1f, 0x1f, 0x0e, 0x0e, 0x0e, 0x0e },
+ .key = "\x1f\x1f\x1f\x1f\x0e\x0e\x0e\x0e",
.klen = 8,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.ilen = 8,
- .result = { 0xa7, 0x90, 0x79, 0x51, 0x08, 0xea, 0x3c, 0xae },
+ .result = "\xa7\x90\x79\x51\x08\xea\x3c\xae",
.rlen = 8,
}, {
- .key = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87 },
+ .key = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
.klen = 8,
- .input = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .input = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.ilen = 8,
- .result = { 0xe8, 0x7a, 0x24, 0x4e, 0x2c, 0xc8, 0x5e, 0x82 },
+ .result = "\xe8\x7a\x24\x4e\x2c\xc8\x5e\x82",
.rlen = 8,
}, { /* Vary the keylength... */
- .key = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87,
- 0x78, 0x69, 0x5a, 0x4b, 0x3c, 0x2d, 0x1e, 0x0f },
+ .key = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87"
+ "\x78\x69\x5a\x4b\x3c\x2d\x1e\x0f",
.klen = 16,
- .input = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .input = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.ilen = 8,
- .result = { 0x93, 0x14, 0x28, 0x87, 0xee, 0x3b, 0xe1, 0x5c },
+ .result = "\x93\x14\x28\x87\xee\x3b\xe1\x5c",
.rlen = 8,
}, {
- .key = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87,
- 0x78, 0x69, 0x5a, 0x4b, 0x3c, 0x2d, 0x1e, 0x0f,
- 0x00, 0x11, 0x22, 0x33, 0x44 },
+ .key = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87"
+ "\x78\x69\x5a\x4b\x3c\x2d\x1e\x0f"
+ "\x00\x11\x22\x33\x44",
.klen = 21,
- .input = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .input = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.ilen = 8,
- .result = { 0xe6, 0xf5, 0x1e, 0xd7, 0x9b, 0x9d, 0xb2, 0x1f },
+ .result = "\xe6\xf5\x1e\xd7\x9b\x9d\xb2\x1f",
.rlen = 8,
}, { /* Generated with bf488 */
- .key = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87,
- 0x78, 0x69, 0x5a, 0x4b, 0x3c, 0x2d, 0x1e, 0x0f,
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x04, 0x68, 0x91, 0x04, 0xc2, 0xfd, 0x3b, 0x2f,
- 0x58, 0x40, 0x23, 0x64, 0x1a, 0xba, 0x61, 0x76,
- 0x1f, 0x1f, 0x1f, 0x1f, 0x0e, 0x0e, 0x0e, 0x0e,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
+ .key = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87"
+ "\x78\x69\x5a\x4b\x3c\x2d\x1e\x0f"
+ "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x04\x68\x91\x04\xc2\xfd\x3b\x2f"
+ "\x58\x40\x23\x64\x1a\xba\x61\x76"
+ "\x1f\x1f\x1f\x1f\x0e\x0e\x0e\x0e"
+ "\xff\xff\xff\xff\xff\xff\xff\xff",
.klen = 56,
- .input = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .input = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.ilen = 8,
- .result = { 0xc0, 0x45, 0x04, 0x01, 0x2e, 0x4e, 0x1f, 0x53 },
+ .result = "\xc0\x45\x04\x01\x2e\x4e\x1f\x53",
.rlen = 8,
},
};
static struct cipher_testvec bf_dec_tv_template[] = {
{ /* DES test vectors from OpenSSL */
- .key = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 8,
- .input = { 0x4e, 0xf9, 0x97, 0x45, 0x61, 0x98, 0xdd, 0x78 },
+ .input = "\x4e\xf9\x97\x45\x61\x98\xdd\x78",
.ilen = 8,
- .result = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .result = "\x00\x00\x00\x00\x00\x00\x00\x00",
.rlen = 8,
}, {
- .key = { 0x1f, 0x1f, 0x1f, 0x1f, 0x0e, 0x0e, 0x0e, 0x0e },
+ .key = "\x1f\x1f\x1f\x1f\x0e\x0e\x0e\x0e",
.klen = 8,
- .input = { 0xa7, 0x90, 0x79, 0x51, 0x08, 0xea, 0x3c, 0xae },
+ .input = "\xa7\x90\x79\x51\x08\xea\x3c\xae",
.ilen = 8,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.rlen = 8,
}, {
- .key = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87 },
+ .key = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
.klen = 8,
- .input = { 0xe8, 0x7a, 0x24, 0x4e, 0x2c, 0xc8, 0x5e, 0x82 },
+ .input = "\xe8\x7a\x24\x4e\x2c\xc8\x5e\x82",
.ilen = 8,
- .result = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .result = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.rlen = 8,
}, { /* Vary the keylength... */
- .key = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87,
- 0x78, 0x69, 0x5a, 0x4b, 0x3c, 0x2d, 0x1e, 0x0f },
+ .key = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87"
+ "\x78\x69\x5a\x4b\x3c\x2d\x1e\x0f",
.klen = 16,
- .input = { 0x93, 0x14, 0x28, 0x87, 0xee, 0x3b, 0xe1, 0x5c },
+ .input = "\x93\x14\x28\x87\xee\x3b\xe1\x5c",
.ilen = 8,
- .result = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .result = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.rlen = 8,
}, {
- .key = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87,
- 0x78, 0x69, 0x5a, 0x4b, 0x3c, 0x2d, 0x1e, 0x0f,
- 0x00, 0x11, 0x22, 0x33, 0x44 },
+ .key = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87"
+ "\x78\x69\x5a\x4b\x3c\x2d\x1e\x0f"
+ "\x00\x11\x22\x33\x44",
.klen = 21,
- .input = { 0xe6, 0xf5, 0x1e, 0xd7, 0x9b, 0x9d, 0xb2, 0x1f },
+ .input = "\xe6\xf5\x1e\xd7\x9b\x9d\xb2\x1f",
.ilen = 8,
- .result = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .result = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.rlen = 8,
}, { /* Generated with bf488, using OpenSSL, Libgcrypt and Nettle */
- .key = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87,
- 0x78, 0x69, 0x5a, 0x4b, 0x3c, 0x2d, 0x1e, 0x0f,
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x04, 0x68, 0x91, 0x04, 0xc2, 0xfd, 0x3b, 0x2f,
- 0x58, 0x40, 0x23, 0x64, 0x1a, 0xba, 0x61, 0x76,
- 0x1f, 0x1f, 0x1f, 0x1f, 0x0e, 0x0e, 0x0e, 0x0e,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
+ .key = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87"
+ "\x78\x69\x5a\x4b\x3c\x2d\x1e\x0f"
+ "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x04\x68\x91\x04\xc2\xfd\x3b\x2f"
+ "\x58\x40\x23\x64\x1a\xba\x61\x76"
+ "\x1f\x1f\x1f\x1f\x0e\x0e\x0e\x0e"
+ "\xff\xff\xff\xff\xff\xff\xff\xff",
.klen = 56,
- .input = { 0xc0, 0x45, 0x04, 0x01, 0x2e, 0x4e, 0x1f, 0x53 },
+ .input = "\xc0\x45\x04\x01\x2e\x4e\x1f\x53",
.ilen = 8,
- .result = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .result = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.rlen = 8,
},
};
static struct cipher_testvec bf_cbc_enc_tv_template[] = {
{ /* From OpenSSL */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87 },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
.klen = 16,
- .iv = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
- .input = { 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x20,
- 0x4e, 0x6f, 0x77, 0x20, 0x69, 0x73, 0x20, 0x74,
- 0x68, 0x65, 0x20, 0x74, 0x69, 0x6d, 0x65, 0x20,
- 0x66, 0x6f, 0x72, 0x20, 0x00, 0x00, 0x00, 0x00 },
+ .iv = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
+ .input = "\x37\x36\x35\x34\x33\x32\x31\x20"
+ "\x4e\x6f\x77\x20\x69\x73\x20\x74"
+ "\x68\x65\x20\x74\x69\x6d\x65\x20"
+ "\x66\x6f\x72\x20\x00\x00\x00\x00",
.ilen = 32,
- .result = { 0x6b, 0x77, 0xb4, 0xd6, 0x30, 0x06, 0xde, 0xe6,
- 0x05, 0xb1, 0x56, 0xe2, 0x74, 0x03, 0x97, 0x93,
- 0x58, 0xde, 0xb9, 0xe7, 0x15, 0x46, 0x16, 0xd9,
- 0x59, 0xf1, 0x65, 0x2b, 0xd5, 0xff, 0x92, 0xcc },
+ .result = "\x6b\x77\xb4\xd6\x30\x06\xde\xe6"
+ "\x05\xb1\x56\xe2\x74\x03\x97\x93"
+ "\x58\xde\xb9\xe7\x15\x46\x16\xd9"
+ "\x59\xf1\x65\x2b\xd5\xff\x92\xcc",
.rlen = 32,
},
};
static struct cipher_testvec bf_cbc_dec_tv_template[] = {
{ /* From OpenSSL */
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87 },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
.klen = 16,
- .iv = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
- .input = { 0x6b, 0x77, 0xb4, 0xd6, 0x30, 0x06, 0xde, 0xe6,
- 0x05, 0xb1, 0x56, 0xe2, 0x74, 0x03, 0x97, 0x93,
- 0x58, 0xde, 0xb9, 0xe7, 0x15, 0x46, 0x16, 0xd9,
- 0x59, 0xf1, 0x65, 0x2b, 0xd5, 0xff, 0x92, 0xcc },
+ .iv = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
+ .input = "\x6b\x77\xb4\xd6\x30\x06\xde\xe6"
+ "\x05\xb1\x56\xe2\x74\x03\x97\x93"
+ "\x58\xde\xb9\xe7\x15\x46\x16\xd9"
+ "\x59\xf1\x65\x2b\xd5\xff\x92\xcc",
.ilen = 32,
- .result = { 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x20,
- 0x4e, 0x6f, 0x77, 0x20, 0x69, 0x73, 0x20, 0x74,
- 0x68, 0x65, 0x20, 0x74, 0x69, 0x6d, 0x65, 0x20,
- 0x66, 0x6f, 0x72, 0x20, 0x00, 0x00, 0x00, 0x00 },
+ .result = "\x37\x36\x35\x34\x33\x32\x31\x20"
+ "\x4e\x6f\x77\x20\x69\x73\x20\x74"
+ "\x68\x65\x20\x74\x69\x6d\x65\x20"
+ "\x66\x6f\x72\x20\x00\x00\x00\x00",
.rlen = 32,
},
};
static struct cipher_testvec tf_enc_tv_template[] = {
{
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .input = { [0 ... 15] = 0x00 },
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0x9f, 0x58, 0x9f, 0x5c, 0xf6, 0x12, 0x2c, 0x32,
- 0xb6, 0xbf, 0xec, 0x2f, 0x2a, 0xe8, 0xc3, 0x5a },
+ .result = "\x9f\x58\x9f\x5c\xf6\x12\x2c\x32"
+ "\xb6\xbf\xec\x2f\x2a\xe8\xc3\x5a",
.rlen = 16,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10"
+ "\x00\x11\x22\x33\x44\x55\x66\x77",
.klen = 24,
- .input = { [0 ... 15] = 0x00 },
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0xcf, 0xd1, 0xd2, 0xe5, 0xa9, 0xbe, 0x9c, 0xdf,
- 0x50, 0x1f, 0x13, 0xb8, 0x92, 0xbd, 0x22, 0x48 },
+ .result = "\xcf\xd1\xd2\xe5\xa9\xbe\x9c\xdf"
+ "\x50\x1f\x13\xb8\x92\xbd\x22\x48",
.rlen = 16,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10"
+ "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x88\x99\xaa\xbb\xcc\xdd\xee\xff",
.klen = 32,
- .input = { [0 ... 15] = 0x00 },
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0x37, 0x52, 0x7b, 0xe0, 0x05, 0x23, 0x34, 0xb8,
- 0x9f, 0x0c, 0xfc, 0xca, 0xe8, 0x7c, 0xfa, 0x20 },
+ .result = "\x37\x52\x7b\xe0\x05\x23\x34\xb8"
+ "\x9f\x0c\xfc\xca\xe8\x7c\xfa\x20",
.rlen = 16,
},
};
static struct cipher_testvec tf_dec_tv_template[] = {
{
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .input = { 0x9f, 0x58, 0x9f, 0x5c, 0xf6, 0x12, 0x2c, 0x32,
- 0xb6, 0xbf, 0xec, 0x2f, 0x2a, 0xe8, 0xc3, 0x5a },
+ .input = "\x9f\x58\x9f\x5c\xf6\x12\x2c\x32"
+ "\xb6\xbf\xec\x2f\x2a\xe8\xc3\x5a",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10"
+ "\x00\x11\x22\x33\x44\x55\x66\x77",
.klen = 24,
- .input = { 0xcf, 0xd1, 0xd2, 0xe5, 0xa9, 0xbe, 0x9c, 0xdf,
- 0x50, 0x1f, 0x13, 0xb8, 0x92, 0xbd, 0x22, 0x48 },
+ .input = "\xcf\xd1\xd2\xe5\xa9\xbe\x9c\xdf"
+ "\x50\x1f\x13\xb8\x92\xbd\x22\x48",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10"
+ "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x88\x99\xaa\xbb\xcc\xdd\xee\xff",
.klen = 32,
- .input = { 0x37, 0x52, 0x7b, 0xe0, 0x05, 0x23, 0x34, 0xb8,
- 0x9f, 0x0c, 0xfc, 0xca, 0xe8, 0x7c, 0xfa, 0x20 },
+ .input = "\x37\x52\x7b\xe0\x05\x23\x34\xb8"
+ "\x9f\x0c\xfc\xca\xe8\x7c\xfa\x20",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
},
};
static struct cipher_testvec tf_cbc_enc_tv_template[] = {
{ /* Generated with Nettle */
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .iv = { [0 ... 15] = 0x00 },
- .input = { [0 ... 15] = 0x00 },
+ .iv = zeroed_string,
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0x9f, 0x58, 0x9f, 0x5c, 0xf6, 0x12, 0x2c, 0x32,
- 0xb6, 0xbf, 0xec, 0x2f, 0x2a, 0xe8, 0xc3, 0x5a },
+ .result = "\x9f\x58\x9f\x5c\xf6\x12\x2c\x32"
+ "\xb6\xbf\xec\x2f\x2a\xe8\xc3\x5a",
.rlen = 16,
}, {
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .iv = { 0x9f, 0x58, 0x9f, 0x5c, 0xf6, 0x12, 0x2c, 0x32,
- 0xb6, 0xbf, 0xec, 0x2f, 0x2a, 0xe8, 0xc3, 0x5a },
- .input = { [0 ... 15] = 0x00 },
+ .iv = "\x9f\x58\x9f\x5c\xf6\x12\x2c\x32"
+ "\xb6\xbf\xec\x2f\x2a\xe8\xc3\x5a",
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0xd4, 0x91, 0xdb, 0x16, 0xe7, 0xb1, 0xc3, 0x9e,
- 0x86, 0xcb, 0x08, 0x6b, 0x78, 0x9f, 0x54, 0x19 },
+ .result = "\xd4\x91\xdb\x16\xe7\xb1\xc3\x9e"
+ "\x86\xcb\x08\x6b\x78\x9f\x54\x19",
.rlen = 16,
}, {
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .iv = { 0xd4, 0x91, 0xdb, 0x16, 0xe7, 0xb1, 0xc3, 0x9e,
- 0x86, 0xcb, 0x08, 0x6b, 0x78, 0x9f, 0x54, 0x19 },
- .input = { [0 ... 15] = 0x00 },
+ .iv = "\xd4\x91\xdb\x16\xe7\xb1\xc3\x9e"
+ "\x86\xcb\x08\x6b\x78\x9f\x54\x19",
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0x05, 0xef, 0x8c, 0x61, 0xa8, 0x11, 0x58, 0x26,
- 0x34, 0xba, 0x5c, 0xb7, 0x10, 0x6a, 0xa6, 0x41 },
+ .result = "\x05\xef\x8c\x61\xa8\x11\x58\x26"
+ "\x34\xba\x5c\xb7\x10\x6a\xa6\x41",
.rlen = 16,
}, {
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .iv = { [0 ... 15] = 0x00 },
- .input = { [0 ... 47] = 0x00 },
+ .iv = zeroed_string,
+ .input = zeroed_string,
.ilen = 48,
- .result = { 0x9f, 0x58, 0x9f, 0x5c, 0xf6, 0x12, 0x2c, 0x32,
- 0xb6, 0xbf, 0xec, 0x2f, 0x2a, 0xe8, 0xc3, 0x5a,
- 0xd4, 0x91, 0xdb, 0x16, 0xe7, 0xb1, 0xc3, 0x9e,
- 0x86, 0xcb, 0x08, 0x6b, 0x78, 0x9f, 0x54, 0x19,
- 0x05, 0xef, 0x8c, 0x61, 0xa8, 0x11, 0x58, 0x26,
- 0x34, 0xba, 0x5c, 0xb7, 0x10, 0x6a, 0xa6, 0x41 },
+ .result = "\x9f\x58\x9f\x5c\xf6\x12\x2c\x32"
+ "\xb6\xbf\xec\x2f\x2a\xe8\xc3\x5a"
+ "\xd4\x91\xdb\x16\xe7\xb1\xc3\x9e"
+ "\x86\xcb\x08\x6b\x78\x9f\x54\x19"
+ "\x05\xef\x8c\x61\xa8\x11\x58\x26"
+ "\x34\xba\x5c\xb7\x10\x6a\xa6\x41",
.rlen = 48,
},
};
static struct cipher_testvec tf_cbc_dec_tv_template[] = {
{ /* Reverse of the first four above */
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .iv = { [0 ... 15] = 0x00 },
- .input = { 0x9f, 0x58, 0x9f, 0x5c, 0xf6, 0x12, 0x2c, 0x32,
- 0xb6, 0xbf, 0xec, 0x2f, 0x2a, 0xe8, 0xc3, 0x5a },
+ .iv = zeroed_string,
+ .input = "\x9f\x58\x9f\x5c\xf6\x12\x2c\x32"
+ "\xb6\xbf\xec\x2f\x2a\xe8\xc3\x5a",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
}, {
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .iv = { 0x9f, 0x58, 0x9f, 0x5c, 0xf6, 0x12, 0x2c, 0x32,
- 0xb6, 0xbf, 0xec, 0x2f, 0x2a, 0xe8, 0xc3, 0x5a },
- .input = { 0xd4, 0x91, 0xdb, 0x16, 0xe7, 0xb1, 0xc3, 0x9e,
- 0x86, 0xcb, 0x08, 0x6b, 0x78, 0x9f, 0x54, 0x19 },
+ .iv = "\x9f\x58\x9f\x5c\xf6\x12\x2c\x32"
+ "\xb6\xbf\xec\x2f\x2a\xe8\xc3\x5a",
+ .input = "\xd4\x91\xdb\x16\xe7\xb1\xc3\x9e"
+ "\x86\xcb\x08\x6b\x78\x9f\x54\x19",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
}, {
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .iv = { 0xd4, 0x91, 0xdb, 0x16, 0xe7, 0xb1, 0xc3, 0x9e,
- 0x86, 0xcb, 0x08, 0x6b, 0x78, 0x9f, 0x54, 0x19 },
- .input = { 0x05, 0xef, 0x8c, 0x61, 0xa8, 0x11, 0x58, 0x26,
- 0x34, 0xba, 0x5c, 0xb7, 0x10, 0x6a, 0xa6, 0x41 },
+ .iv = "\xd4\x91\xdb\x16\xe7\xb1\xc3\x9e"
+ "\x86\xcb\x08\x6b\x78\x9f\x54\x19",
+ .input = "\x05\xef\x8c\x61\xa8\x11\x58\x26"
+ "\x34\xba\x5c\xb7\x10\x6a\xa6\x41",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
}, {
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .iv = { [0 ... 15] = 0x00 },
- .input = { 0x9f, 0x58, 0x9f, 0x5c, 0xf6, 0x12, 0x2c, 0x32,
- 0xb6, 0xbf, 0xec, 0x2f, 0x2a, 0xe8, 0xc3, 0x5a,
- 0xd4, 0x91, 0xdb, 0x16, 0xe7, 0xb1, 0xc3, 0x9e,
- 0x86, 0xcb, 0x08, 0x6b, 0x78, 0x9f, 0x54, 0x19,
- 0x05, 0xef, 0x8c, 0x61, 0xa8, 0x11, 0x58, 0x26,
- 0x34, 0xba, 0x5c, 0xb7, 0x10, 0x6a, 0xa6, 0x41 },
+ .iv = zeroed_string,
+ .input = "\x9f\x58\x9f\x5c\xf6\x12\x2c\x32"
+ "\xb6\xbf\xec\x2f\x2a\xe8\xc3\x5a"
+ "\xd4\x91\xdb\x16\xe7\xb1\xc3\x9e"
+ "\x86\xcb\x08\x6b\x78\x9f\x54\x19"
+ "\x05\xef\x8c\x61\xa8\x11\x58\x26"
+ "\x34\xba\x5c\xb7\x10\x6a\xa6\x41",
.ilen = 48,
- .result = { [0 ... 47] = 0x00 },
+ .result = zeroed_string,
.rlen = 48,
},
};
static struct cipher_testvec serpent_enc_tv_template[] = {
{
- .input = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .input = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.ilen = 16,
- .result = { 0x12, 0x07, 0xfc, 0xce, 0x9b, 0xd0, 0xd6, 0x47,
- 0x6a, 0xe9, 0x8f, 0xbe, 0xd1, 0x43, 0xa0, 0xe2 },
+ .result = "\x12\x07\xfc\xce\x9b\xd0\xd6\x47"
+ "\x6a\xe9\x8f\xbe\xd1\x43\xa0\xe2",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.klen = 16,
- .input = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .input = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.ilen = 16,
- .result = { 0x4c, 0x7d, 0x8a, 0x32, 0x80, 0x72, 0xa2, 0x2c,
- 0x82, 0x3e, 0x4a, 0x1f, 0x3a, 0xcd, 0xa1, 0x6d },
+ .result = "\x4c\x7d\x8a\x32\x80\x72\xa2\x2c"
+ "\x82\x3e\x4a\x1f\x3a\xcd\xa1\x6d",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.klen = 32,
- .input = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .input = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.ilen = 16,
- .result = { 0xde, 0x26, 0x9f, 0xf8, 0x33, 0xe4, 0x32, 0xb8,
- 0x5b, 0x2e, 0x88, 0xd2, 0x70, 0x1c, 0xe7, 0x5c },
+ .result = "\xde\x26\x9f\xf8\x33\xe4\x32\xb8"
+ "\x5b\x2e\x88\xd2\x70\x1c\xe7\x5c",
.rlen = 16,
}, {
- .key = { [15] = 0x80 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x80",
.klen = 16,
- .input = { [0 ... 15] = 0x00 },
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0xdd, 0xd2, 0x6b, 0x98, 0xa5, 0xff, 0xd8, 0x2c,
- 0x05, 0x34, 0x5a, 0x9d, 0xad, 0xbf, 0xaf, 0x49},
+ .result = "\xdd\xd2\x6b\x98\xa5\xff\xd8\x2c"
+ "\x05\x34\x5a\x9d\xad\xbf\xaf\x49",
.rlen = 16,
},
};
static struct cipher_testvec tnepres_enc_tv_template[] = {
{ /* KeySize=128, PT=0, I=1 */
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .key = { 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .key = "\x80\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 16,
.ilen = 16,
- .result = { 0x49, 0xaf, 0xbf, 0xad, 0x9d, 0x5a, 0x34, 0x05,
- 0x2c, 0xd8, 0xff, 0xa5, 0x98, 0x6b, 0xd2, 0xdd },
+ .result = "\x49\xaf\xbf\xad\x9d\x5a\x34\x05"
+ "\x2c\xd8\xff\xa5\x98\x6b\xd2\xdd",
.rlen = 16,
}, { /* KeySize=192, PT=0, I=1 */
- .key = { 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x80\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 24,
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.ilen = 16,
- .result = { 0xe7, 0x8e, 0x54, 0x02, 0xc7, 0x19, 0x55, 0x68,
- 0xac, 0x36, 0x78, 0xf7, 0xa3, 0xf6, 0x0c, 0x66 },
+ .result = "\xe7\x8e\x54\x02\xc7\x19\x55\x68"
+ "\xac\x36\x78\xf7\xa3\xf6\x0c\x66",
.rlen = 16,
}, { /* KeySize=256, PT=0, I=1 */
- .key = { 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x80\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 32,
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.ilen = 16,
- .result = { 0xab, 0xed, 0x96, 0xe7, 0x66, 0xbf, 0x28, 0xcb,
- 0xc0, 0xeb, 0xd2, 0x1a, 0x82, 0xef, 0x08, 0x19 },
+ .result = "\xab\xed\x96\xe7\x66\xbf\x28\xcb"
+ "\xc0\xeb\xd2\x1a\x82\xef\x08\x19",
.rlen = 16,
}, { /* KeySize=256, I=257 */
- .key = { 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18,
- 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
- 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 },
+ .key = "\x1f\x1e\x1d\x1c\x1b\x1a\x19\x18"
+ "\x17\x16\x15\x14\x13\x12\x11\x10"
+ "\x0f\x0e\x0d\x0c\x0b\x0a\x09\x08"
+ "\x07\x06\x05\x04\x03\x02\x01\x00",
.klen = 32,
- .input = { 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 },
+ .input = "\x0f\x0e\x0d\x0c\x0b\x0a\x09\x08"
+ "\x07\x06\x05\x04\x03\x02\x01\x00",
.ilen = 16,
- .result = { 0x5c, 0xe7, 0x1c, 0x70, 0xd2, 0x88, 0x2e, 0x5b,
- 0xb8, 0x32, 0xe4, 0x33, 0xf8, 0x9f, 0x26, 0xde },
+ .result = "\x5c\xe7\x1c\x70\xd2\x88\x2e\x5b"
+ "\xb8\x32\xe4\x33\xf8\x9f\x26\xde",
.rlen = 16,
},
};
static struct cipher_testvec serpent_dec_tv_template[] = {
{
- .input = { 0x12, 0x07, 0xfc, 0xce, 0x9b, 0xd0, 0xd6, 0x47,
- 0x6a, 0xe9, 0x8f, 0xbe, 0xd1, 0x43, 0xa0, 0xe2 },
+ .input = "\x12\x07\xfc\xce\x9b\xd0\xd6\x47"
+ "\x6a\xe9\x8f\xbe\xd1\x43\xa0\xe2",
.ilen = 16,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.klen = 16,
- .input = { 0x4c, 0x7d, 0x8a, 0x32, 0x80, 0x72, 0xa2, 0x2c,
- 0x82, 0x3e, 0x4a, 0x1f, 0x3a, 0xcd, 0xa1, 0x6d },
+ .input = "\x4c\x7d\x8a\x32\x80\x72\xa2\x2c"
+ "\x82\x3e\x4a\x1f\x3a\xcd\xa1\x6d",
.ilen = 16,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.klen = 32,
- .input = { 0xde, 0x26, 0x9f, 0xf8, 0x33, 0xe4, 0x32, 0xb8,
- 0x5b, 0x2e, 0x88, 0xd2, 0x70, 0x1c, 0xe7, 0x5c },
+ .input = "\xde\x26\x9f\xf8\x33\xe4\x32\xb8"
+ "\x5b\x2e\x88\xd2\x70\x1c\xe7\x5c",
.ilen = 16,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.rlen = 16,
}, {
- .key = { [15] = 0x80 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x80",
.klen = 16,
- .input = { 0xdd, 0xd2, 0x6b, 0x98, 0xa5, 0xff, 0xd8, 0x2c,
- 0x05, 0x34, 0x5a, 0x9d, 0xad, 0xbf, 0xaf, 0x49},
+ .input = "\xdd\xd2\x6b\x98\xa5\xff\xd8\x2c"
+ "\x05\x34\x5a\x9d\xad\xbf\xaf\x49",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
},
};
static struct cipher_testvec tnepres_dec_tv_template[] = {
{
- .input = { 0x41, 0xcc, 0x6b, 0x31, 0x59, 0x31, 0x45, 0x97,
- 0x6d, 0x6f, 0xbb, 0x38, 0x4b, 0x37, 0x21, 0x28 },
+ .input = "\x41\xcc\x6b\x31\x59\x31\x45\x97"
+ "\x6d\x6f\xbb\x38\x4b\x37\x21\x28",
.ilen = 16,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.klen = 16,
- .input = { 0xea, 0xf4, 0xd7, 0xfc, 0xd8, 0x01, 0x34, 0x47,
- 0x81, 0x45, 0x0b, 0xfa, 0x0c, 0xd6, 0xad, 0x6e },
+ .input = "\xea\xf4\xd7\xfc\xd8\x01\x34\x47"
+ "\x81\x45\x0b\xfa\x0c\xd6\xad\x6e",
.ilen = 16,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.klen = 32,
- .input = { 0x64, 0xa9, 0x1a, 0x37, 0xed, 0x9f, 0xe7, 0x49,
- 0xa8, 0x4e, 0x76, 0xd6, 0xf5, 0x0d, 0x78, 0xee },
+ .input = "\x64\xa9\x1a\x37\xed\x9f\xe7\x49"
+ "\xa8\x4e\x76\xd6\xf5\x0d\x78\xee",
.ilen = 16,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.rlen = 16,
}, { /* KeySize=128, I=121 */
- .key = { [15] = 0x80 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x80",
.klen = 16,
- .input = { 0x3d, 0xda, 0xbf, 0xc0, 0x06, 0xda, 0xab, 0x06,
- 0x46, 0x2a, 0xf4, 0xef, 0x81, 0x54, 0x4e, 0x26 },
+ .input = "\x3d\xda\xbf\xc0\x06\xda\xab\x06"
+ "\x46\x2a\xf4\xef\x81\x54\x4e\x26",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
},
};
static struct cipher_testvec cast6_enc_tv_template[] = {
{
- .key = { 0x23, 0x42, 0xbb, 0x9e, 0xfa, 0x38, 0x54, 0x2c,
- 0x0a, 0xf7, 0x56, 0x47, 0xf2, 0x9f, 0x61, 0x5d },
+ .key = "\x23\x42\xbb\x9e\xfa\x38\x54\x2c"
+ "\x0a\xf7\x56\x47\xf2\x9f\x61\x5d",
.klen = 16,
- .input = { [0 ... 15] = 0x00 },
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0xc8, 0x42, 0xa0, 0x89, 0x72, 0xb4, 0x3d, 0x20,
- 0x83, 0x6c, 0x91, 0xd1, 0xb7, 0x53, 0x0f, 0x6b },
+ .result = "\xc8\x42\xa0\x89\x72\xb4\x3d\x20"
+ "\x83\x6c\x91\xd1\xb7\x53\x0f\x6b",
.rlen = 16,
}, {
- .key = { 0x23, 0x42, 0xbb, 0x9e, 0xfa, 0x38, 0x54, 0x2c,
- 0xbe, 0xd0, 0xac, 0x83, 0x94, 0x0a, 0xc2, 0x98,
- 0xba, 0xc7, 0x7a, 0x77, 0x17, 0x94, 0x28, 0x63 },
+ .key = "\x23\x42\xbb\x9e\xfa\x38\x54\x2c"
+ "\xbe\xd0\xac\x83\x94\x0a\xc2\x98"
+ "\xba\xc7\x7a\x77\x17\x94\x28\x63",
.klen = 24,
- .input = { [0 ... 15] = 0x00 },
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0x1b, 0x38, 0x6c, 0x02, 0x10, 0xdc, 0xad, 0xcb,
- 0xdd, 0x0e, 0x41, 0xaa, 0x08, 0xa7, 0xa7, 0xe8 },
+ .result = "\x1b\x38\x6c\x02\x10\xdc\xad\xcb"
+ "\xdd\x0e\x41\xaa\x08\xa7\xa7\xe8",
.rlen = 16,
}, {
- .key = { 0x23, 0x42, 0xbb, 0x9e, 0xfa, 0x38, 0x54, 0x2c,
- 0xbe, 0xd0, 0xac, 0x83, 0x94, 0x0a, 0xc2, 0x98,
- 0x8d, 0x7c, 0x47, 0xce, 0x26, 0x49, 0x08, 0x46,
- 0x1c, 0xc1, 0xb5, 0x13, 0x7a, 0xe6, 0xb6, 0x04 },
+ .key = "\x23\x42\xbb\x9e\xfa\x38\x54\x2c"
+ "\xbe\xd0\xac\x83\x94\x0a\xc2\x98"
+ "\x8d\x7c\x47\xce\x26\x49\x08\x46"
+ "\x1c\xc1\xb5\x13\x7a\xe6\xb6\x04",
.klen = 32,
- .input = { [0 ... 15] = 0x00 },
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0x4f, 0x6a, 0x20, 0x38, 0x28, 0x68, 0x97, 0xb9,
- 0xc9, 0x87, 0x01, 0x36, 0x55, 0x33, 0x17, 0xfa },
+ .result = "\x4f\x6a\x20\x38\x28\x68\x97\xb9"
+ "\xc9\x87\x01\x36\x55\x33\x17\xfa",
.rlen = 16,
},
};
static struct cipher_testvec cast6_dec_tv_template[] = {
{
- .key = { 0x23, 0x42, 0xbb, 0x9e, 0xfa, 0x38, 0x54, 0x2c,
- 0x0a, 0xf7, 0x56, 0x47, 0xf2, 0x9f, 0x61, 0x5d },
+ .key = "\x23\x42\xbb\x9e\xfa\x38\x54\x2c"
+ "\x0a\xf7\x56\x47\xf2\x9f\x61\x5d",
.klen = 16,
- .input = { 0xc8, 0x42, 0xa0, 0x89, 0x72, 0xb4, 0x3d, 0x20,
- 0x83, 0x6c, 0x91, 0xd1, 0xb7, 0x53, 0x0f, 0x6b },
+ .input = "\xc8\x42\xa0\x89\x72\xb4\x3d\x20"
+ "\x83\x6c\x91\xd1\xb7\x53\x0f\x6b",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
}, {
- .key = { 0x23, 0x42, 0xbb, 0x9e, 0xfa, 0x38, 0x54, 0x2c,
- 0xbe, 0xd0, 0xac, 0x83, 0x94, 0x0a, 0xc2, 0x98,
- 0xba, 0xc7, 0x7a, 0x77, 0x17, 0x94, 0x28, 0x63 },
+ .key = "\x23\x42\xbb\x9e\xfa\x38\x54\x2c"
+ "\xbe\xd0\xac\x83\x94\x0a\xc2\x98"
+ "\xba\xc7\x7a\x77\x17\x94\x28\x63",
.klen = 24,
- .input = { 0x1b, 0x38, 0x6c, 0x02, 0x10, 0xdc, 0xad, 0xcb,
- 0xdd, 0x0e, 0x41, 0xaa, 0x08, 0xa7, 0xa7, 0xe8 },
+ .input = "\x1b\x38\x6c\x02\x10\xdc\xad\xcb"
+ "\xdd\x0e\x41\xaa\x08\xa7\xa7\xe8",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
}, {
- .key = { 0x23, 0x42, 0xbb, 0x9e, 0xfa, 0x38, 0x54, 0x2c,
- 0xbe, 0xd0, 0xac, 0x83, 0x94, 0x0a, 0xc2, 0x98,
- 0x8d, 0x7c, 0x47, 0xce, 0x26, 0x49, 0x08, 0x46,
- 0x1c, 0xc1, 0xb5, 0x13, 0x7a, 0xe6, 0xb6, 0x04 },
+ .key = "\x23\x42\xbb\x9e\xfa\x38\x54\x2c"
+ "\xbe\xd0\xac\x83\x94\x0a\xc2\x98"
+ "\x8d\x7c\x47\xce\x26\x49\x08\x46"
+ "\x1c\xc1\xb5\x13\x7a\xe6\xb6\x04",
.klen = 32,
- .input = { 0x4f, 0x6a, 0x20, 0x38, 0x28, 0x68, 0x97, 0xb9,
- 0xc9, 0x87, 0x01, 0x36, 0x55, 0x33, 0x17, 0xfa },
+ .input = "\x4f\x6a\x20\x38\x28\x68\x97\xb9"
+ "\xc9\x87\x01\x36\x55\x33\x17\xfa",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
},
};
static struct cipher_testvec aes_enc_tv_template[] = {
{ /* From FIPS-197 */
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.klen = 16,
- .input = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff },
+ .input = "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x88\x99\xaa\xbb\xcc\xdd\xee\xff",
.ilen = 16,
- .result = { 0x69, 0xc4, 0xe0, 0xd8, 0x6a, 0x7b, 0x04, 0x30,
- 0xd8, 0xcd, 0xb7, 0x80, 0x70, 0xb4, 0xc5, 0x5a },
+ .result = "\x69\xc4\xe0\xd8\x6a\x7b\x04\x30"
+ "\xd8\xcd\xb7\x80\x70\xb4\xc5\x5a",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17",
.klen = 24,
- .input = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff },
+ .input = "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x88\x99\xaa\xbb\xcc\xdd\xee\xff",
.ilen = 16,
- .result = { 0xdd, 0xa9, 0x7c, 0xa4, 0x86, 0x4c, 0xdf, 0xe0,
- 0x6e, 0xaf, 0x70, 0xa0, 0xec, 0x0d, 0x71, 0x91 },
+ .result = "\xdd\xa9\x7c\xa4\x86\x4c\xdf\xe0"
+ "\x6e\xaf\x70\xa0\xec\x0d\x71\x91",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.klen = 32,
- .input = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff },
+ .input = "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x88\x99\xaa\xbb\xcc\xdd\xee\xff",
.ilen = 16,
- .result = { 0x8e, 0xa2, 0xb7, 0xca, 0x51, 0x67, 0x45, 0xbf,
- 0xea, 0xfc, 0x49, 0x90, 0x4b, 0x49, 0x60, 0x89 },
+ .result = "\x8e\xa2\xb7\xca\x51\x67\x45\xbf"
+ "\xea\xfc\x49\x90\x4b\x49\x60\x89",
.rlen = 16,
},
};
static struct cipher_testvec aes_dec_tv_template[] = {
{ /* From FIPS-197 */
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.klen = 16,
- .input = { 0x69, 0xc4, 0xe0, 0xd8, 0x6a, 0x7b, 0x04, 0x30,
- 0xd8, 0xcd, 0xb7, 0x80, 0x70, 0xb4, 0xc5, 0x5a },
+ .input = "\x69\xc4\xe0\xd8\x6a\x7b\x04\x30"
+ "\xd8\xcd\xb7\x80\x70\xb4\xc5\x5a",
.ilen = 16,
- .result = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff },
+ .result = "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x88\x99\xaa\xbb\xcc\xdd\xee\xff",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17",
.klen = 24,
- .input = { 0xdd, 0xa9, 0x7c, 0xa4, 0x86, 0x4c, 0xdf, 0xe0,
- 0x6e, 0xaf, 0x70, 0xa0, 0xec, 0x0d, 0x71, 0x91 },
+ .input = "\xdd\xa9\x7c\xa4\x86\x4c\xdf\xe0"
+ "\x6e\xaf\x70\xa0\xec\x0d\x71\x91",
.ilen = 16,
- .result = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff },
+ .result = "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x88\x99\xaa\xbb\xcc\xdd\xee\xff",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.klen = 32,
- .input = { 0x8e, 0xa2, 0xb7, 0xca, 0x51, 0x67, 0x45, 0xbf,
- 0xea, 0xfc, 0x49, 0x90, 0x4b, 0x49, 0x60, 0x89 },
+ .input = "\x8e\xa2\xb7\xca\x51\x67\x45\xbf"
+ "\xea\xfc\x49\x90\x4b\x49\x60\x89",
.ilen = 16,
- .result = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff },
+ .result = "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x88\x99\xaa\xbb\xcc\xdd\xee\xff",
.rlen = 16,
},
};
static struct cipher_testvec aes_cbc_enc_tv_template[] = {
{ /* From RFC 3602 */
- .key = { 0x06, 0xa9, 0x21, 0x40, 0x36, 0xb8, 0xa1, 0x5b,
- 0x51, 0x2e, 0x03, 0xd5, 0x34, 0x12, 0x00, 0x06 },
+ .key = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b"
+ "\x51\x2e\x03\xd5\x34\x12\x00\x06",
.klen = 16,
- .iv = { 0x3d, 0xaf, 0xba, 0x42, 0x9d, 0x9e, 0xb4, 0x30,
- 0xb4, 0x22, 0xda, 0x80, 0x2c, 0x9f, 0xac, 0x41 },
- .input = { "Single block msg" },
+ .iv = "\x3d\xaf\xba\x42\x9d\x9e\xb4\x30"
+ "\xb4\x22\xda\x80\x2c\x9f\xac\x41",
+ .input = "Single block msg",
.ilen = 16,
- .result = { 0xe3, 0x53, 0x77, 0x9c, 0x10, 0x79, 0xae, 0xb8,
- 0x27, 0x08, 0x94, 0x2d, 0xbe, 0x77, 0x18, 0x1a },
+ .result = "\xe3\x53\x77\x9c\x10\x79\xae\xb8"
+ "\x27\x08\x94\x2d\xbe\x77\x18\x1a",
.rlen = 16,
}, {
- .key = { 0xc2, 0x86, 0x69, 0x6d, 0x88, 0x7c, 0x9a, 0xa0,
- 0x61, 0x1b, 0xbb, 0x3e, 0x20, 0x25, 0xa4, 0x5a },
+ .key = "\xc2\x86\x69\x6d\x88\x7c\x9a\xa0"
+ "\x61\x1b\xbb\x3e\x20\x25\xa4\x5a",
.klen = 16,
- .iv = { 0x56, 0x2e, 0x17, 0x99, 0x6d, 0x09, 0x3d, 0x28,
- 0xdd, 0xb3, 0xba, 0x69, 0x5a, 0x2e, 0x6f, 0x58 },
- .input = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .iv = "\x56\x2e\x17\x99\x6d\x09\x3d\x28"
+ "\xdd\xb3\xba\x69\x5a\x2e\x6f\x58",
+ .input = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.ilen = 32,
- .result = { 0xd2, 0x96, 0xcd, 0x94, 0xc2, 0xcc, 0xcf, 0x8a,
- 0x3a, 0x86, 0x30, 0x28, 0xb5, 0xe1, 0xdc, 0x0a,
- 0x75, 0x86, 0x60, 0x2d, 0x25, 0x3c, 0xff, 0xf9,
- 0x1b, 0x82, 0x66, 0xbe, 0xa6, 0xd6, 0x1a, 0xb1 },
+ .result = "\xd2\x96\xcd\x94\xc2\xcc\xcf\x8a"
+ "\x3a\x86\x30\x28\xb5\xe1\xdc\x0a"
+ "\x75\x86\x60\x2d\x25\x3c\xff\xf9"
+ "\x1b\x82\x66\xbe\xa6\xd6\x1a\xb1",
.rlen = 32,
}, { /* From NIST SP800-38A */
- .key = { 0x8e, 0x73, 0xb0, 0xf7, 0xda, 0x0e, 0x64, 0x52,
- 0xc8, 0x10, 0xf3, 0x2b, 0x80, 0x90, 0x79, 0xe5,
- 0x62, 0xf8, 0xea, 0xd2, 0x52, 0x2c, 0x6b, 0x7b },
+ .key = "\x8e\x73\xb0\xf7\xda\x0e\x64\x52"
+ "\xc8\x10\xf3\x2b\x80\x90\x79\xe5"
+ "\x62\xf8\xea\xd2\x52\x2c\x6b\x7b",
.klen = 24,
- .iv = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .input = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
- 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
- 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c,
- 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51,
- 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11,
- 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef,
- 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17,
- 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10 },
+ .iv = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .input = "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96"
+ "\xe9\x3d\x7e\x11\x73\x93\x17\x2a"
+ "\xae\x2d\x8a\x57\x1e\x03\xac\x9c"
+ "\x9e\xb7\x6f\xac\x45\xaf\x8e\x51"
+ "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11"
+ "\xe5\xfb\xc1\x19\x1a\x0a\x52\xef"
+ "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17"
+ "\xad\x2b\x41\x7b\xe6\x6c\x37\x10",
.ilen = 64,
- .result = { 0x4f, 0x02, 0x1d, 0xb2, 0x43, 0xbc, 0x63, 0x3d,
- 0x71, 0x78, 0x18, 0x3a, 0x9f, 0xa0, 0x71, 0xe8,
- 0xb4, 0xd9, 0xad, 0xa9, 0xad, 0x7d, 0xed, 0xf4,
- 0xe5, 0xe7, 0x38, 0x76, 0x3f, 0x69, 0x14, 0x5a,
- 0x57, 0x1b, 0x24, 0x20, 0x12, 0xfb, 0x7a, 0xe0,
- 0x7f, 0xa9, 0xba, 0xac, 0x3d, 0xf1, 0x02, 0xe0,
- 0x08, 0xb0, 0xe2, 0x79, 0x88, 0x59, 0x88, 0x81,
- 0xd9, 0x20, 0xa9, 0xe6, 0x4f, 0x56, 0x15, 0xcd },
+ .result = "\x4f\x02\x1d\xb2\x43\xbc\x63\x3d"
+ "\x71\x78\x18\x3a\x9f\xa0\x71\xe8"
+ "\xb4\xd9\xad\xa9\xad\x7d\xed\xf4"
+ "\xe5\xe7\x38\x76\x3f\x69\x14\x5a"
+ "\x57\x1b\x24\x20\x12\xfb\x7a\xe0"
+ "\x7f\xa9\xba\xac\x3d\xf1\x02\xe0"
+ "\x08\xb0\xe2\x79\x88\x59\x88\x81"
+ "\xd9\x20\xa9\xe6\x4f\x56\x15\xcd",
.rlen = 64,
}, {
- .key = { 0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe,
- 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81,
- 0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7,
- 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4 },
+ .key = "\x60\x3d\xeb\x10\x15\xca\x71\xbe"
+ "\x2b\x73\xae\xf0\x85\x7d\x77\x81"
+ "\x1f\x35\x2c\x07\x3b\x61\x08\xd7"
+ "\x2d\x98\x10\xa3\x09\x14\xdf\xf4",
.klen = 32,
- .iv = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .input = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
- 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
- 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c,
- 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51,
- 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11,
- 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef,
- 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17,
- 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10 },
+ .iv = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .input = "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96"
+ "\xe9\x3d\x7e\x11\x73\x93\x17\x2a"
+ "\xae\x2d\x8a\x57\x1e\x03\xac\x9c"
+ "\x9e\xb7\x6f\xac\x45\xaf\x8e\x51"
+ "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11"
+ "\xe5\xfb\xc1\x19\x1a\x0a\x52\xef"
+ "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17"
+ "\xad\x2b\x41\x7b\xe6\x6c\x37\x10",
.ilen = 64,
- .result = { 0xf5, 0x8c, 0x4c, 0x04, 0xd6, 0xe5, 0xf1, 0xba,
- 0x77, 0x9e, 0xab, 0xfb, 0x5f, 0x7b, 0xfb, 0xd6,
- 0x9c, 0xfc, 0x4e, 0x96, 0x7e, 0xdb, 0x80, 0x8d,
- 0x67, 0x9f, 0x77, 0x7b, 0xc6, 0x70, 0x2c, 0x7d,
- 0x39, 0xf2, 0x33, 0x69, 0xa9, 0xd9, 0xba, 0xcf,
- 0xa5, 0x30, 0xe2, 0x63, 0x04, 0x23, 0x14, 0x61,
- 0xb2, 0xeb, 0x05, 0xe2, 0xc3, 0x9b, 0xe9, 0xfc,
- 0xda, 0x6c, 0x19, 0x07, 0x8c, 0x6a, 0x9d, 0x1b },
+ .result = "\xf5\x8c\x4c\x04\xd6\xe5\xf1\xba"
+ "\x77\x9e\xab\xfb\x5f\x7b\xfb\xd6"
+ "\x9c\xfc\x4e\x96\x7e\xdb\x80\x8d"
+ "\x67\x9f\x77\x7b\xc6\x70\x2c\x7d"
+ "\x39\xf2\x33\x69\xa9\xd9\xba\xcf"
+ "\xa5\x30\xe2\x63\x04\x23\x14\x61"
+ "\xb2\xeb\x05\xe2\xc3\x9b\xe9\xfc"
+ "\xda\x6c\x19\x07\x8c\x6a\x9d\x1b",
.rlen = 64,
},
};
static struct cipher_testvec aes_cbc_dec_tv_template[] = {
{ /* From RFC 3602 */
- .key = { 0x06, 0xa9, 0x21, 0x40, 0x36, 0xb8, 0xa1, 0x5b,
- 0x51, 0x2e, 0x03, 0xd5, 0x34, 0x12, 0x00, 0x06 },
+ .key = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b"
+ "\x51\x2e\x03\xd5\x34\x12\x00\x06",
.klen = 16,
- .iv = { 0x3d, 0xaf, 0xba, 0x42, 0x9d, 0x9e, 0xb4, 0x30,
- 0xb4, 0x22, 0xda, 0x80, 0x2c, 0x9f, 0xac, 0x41 },
- .input = { 0xe3, 0x53, 0x77, 0x9c, 0x10, 0x79, 0xae, 0xb8,
- 0x27, 0x08, 0x94, 0x2d, 0xbe, 0x77, 0x18, 0x1a },
+ .iv = "\x3d\xaf\xba\x42\x9d\x9e\xb4\x30"
+ "\xb4\x22\xda\x80\x2c\x9f\xac\x41",
+ .input = "\xe3\x53\x77\x9c\x10\x79\xae\xb8"
+ "\x27\x08\x94\x2d\xbe\x77\x18\x1a",
.ilen = 16,
- .result = { "Single block msg" },
+ .result = "Single block msg",
.rlen = 16,
}, {
- .key = { 0xc2, 0x86, 0x69, 0x6d, 0x88, 0x7c, 0x9a, 0xa0,
- 0x61, 0x1b, 0xbb, 0x3e, 0x20, 0x25, 0xa4, 0x5a },
+ .key = "\xc2\x86\x69\x6d\x88\x7c\x9a\xa0"
+ "\x61\x1b\xbb\x3e\x20\x25\xa4\x5a",
.klen = 16,
- .iv = { 0x56, 0x2e, 0x17, 0x99, 0x6d, 0x09, 0x3d, 0x28,
- 0xdd, 0xb3, 0xba, 0x69, 0x5a, 0x2e, 0x6f, 0x58 },
- .input = { 0xd2, 0x96, 0xcd, 0x94, 0xc2, 0xcc, 0xcf, 0x8a,
- 0x3a, 0x86, 0x30, 0x28, 0xb5, 0xe1, 0xdc, 0x0a,
- 0x75, 0x86, 0x60, 0x2d, 0x25, 0x3c, 0xff, 0xf9,
- 0x1b, 0x82, 0x66, 0xbe, 0xa6, 0xd6, 0x1a, 0xb1 },
+ .iv = "\x56\x2e\x17\x99\x6d\x09\x3d\x28"
+ "\xdd\xb3\xba\x69\x5a\x2e\x6f\x58",
+ .input = "\xd2\x96\xcd\x94\xc2\xcc\xcf\x8a"
+ "\x3a\x86\x30\x28\xb5\xe1\xdc\x0a"
+ "\x75\x86\x60\x2d\x25\x3c\xff\xf9"
+ "\x1b\x82\x66\xbe\xa6\xd6\x1a\xb1",
.ilen = 32,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.rlen = 32,
}, { /* From NIST SP800-38A */
- .key = { 0x8e, 0x73, 0xb0, 0xf7, 0xda, 0x0e, 0x64, 0x52,
- 0xc8, 0x10, 0xf3, 0x2b, 0x80, 0x90, 0x79, 0xe5,
- 0x62, 0xf8, 0xea, 0xd2, 0x52, 0x2c, 0x6b, 0x7b },
+ .key = "\x8e\x73\xb0\xf7\xda\x0e\x64\x52"
+ "\xc8\x10\xf3\x2b\x80\x90\x79\xe5"
+ "\x62\xf8\xea\xd2\x52\x2c\x6b\x7b",
.klen = 24,
- .iv = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .input = { 0x4f, 0x02, 0x1d, 0xb2, 0x43, 0xbc, 0x63, 0x3d,
- 0x71, 0x78, 0x18, 0x3a, 0x9f, 0xa0, 0x71, 0xe8,
- 0xb4, 0xd9, 0xad, 0xa9, 0xad, 0x7d, 0xed, 0xf4,
- 0xe5, 0xe7, 0x38, 0x76, 0x3f, 0x69, 0x14, 0x5a,
- 0x57, 0x1b, 0x24, 0x20, 0x12, 0xfb, 0x7a, 0xe0,
- 0x7f, 0xa9, 0xba, 0xac, 0x3d, 0xf1, 0x02, 0xe0,
- 0x08, 0xb0, 0xe2, 0x79, 0x88, 0x59, 0x88, 0x81,
- 0xd9, 0x20, 0xa9, 0xe6, 0x4f, 0x56, 0x15, 0xcd },
+ .iv = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .input = "\x4f\x02\x1d\xb2\x43\xbc\x63\x3d"
+ "\x71\x78\x18\x3a\x9f\xa0\x71\xe8"
+ "\xb4\xd9\xad\xa9\xad\x7d\xed\xf4"
+ "\xe5\xe7\x38\x76\x3f\x69\x14\x5a"
+ "\x57\x1b\x24\x20\x12\xfb\x7a\xe0"
+ "\x7f\xa9\xba\xac\x3d\xf1\x02\xe0"
+ "\x08\xb0\xe2\x79\x88\x59\x88\x81"
+ "\xd9\x20\xa9\xe6\x4f\x56\x15\xcd",
.ilen = 64,
- .result = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
- 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
- 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c,
- 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51,
- 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11,
- 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef,
- 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17,
- 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10 },
+ .result = "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96"
+ "\xe9\x3d\x7e\x11\x73\x93\x17\x2a"
+ "\xae\x2d\x8a\x57\x1e\x03\xac\x9c"
+ "\x9e\xb7\x6f\xac\x45\xaf\x8e\x51"
+ "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11"
+ "\xe5\xfb\xc1\x19\x1a\x0a\x52\xef"
+ "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17"
+ "\xad\x2b\x41\x7b\xe6\x6c\x37\x10",
.rlen = 64,
}, {
- .key = { 0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe,
- 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81,
- 0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7,
- 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4 },
+ .key = "\x60\x3d\xeb\x10\x15\xca\x71\xbe"
+ "\x2b\x73\xae\xf0\x85\x7d\x77\x81"
+ "\x1f\x35\x2c\x07\x3b\x61\x08\xd7"
+ "\x2d\x98\x10\xa3\x09\x14\xdf\xf4",
.klen = 32,
- .iv = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
- .input = { 0xf5, 0x8c, 0x4c, 0x04, 0xd6, 0xe5, 0xf1, 0xba,
- 0x77, 0x9e, 0xab, 0xfb, 0x5f, 0x7b, 0xfb, 0xd6,
- 0x9c, 0xfc, 0x4e, 0x96, 0x7e, 0xdb, 0x80, 0x8d,
- 0x67, 0x9f, 0x77, 0x7b, 0xc6, 0x70, 0x2c, 0x7d,
- 0x39, 0xf2, 0x33, 0x69, 0xa9, 0xd9, 0xba, 0xcf,
- 0xa5, 0x30, 0xe2, 0x63, 0x04, 0x23, 0x14, 0x61,
- 0xb2, 0xeb, 0x05, 0xe2, 0xc3, 0x9b, 0xe9, 0xfc,
- 0xda, 0x6c, 0x19, 0x07, 0x8c, 0x6a, 0x9d, 0x1b },
+ .iv = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+ .input = "\xf5\x8c\x4c\x04\xd6\xe5\xf1\xba"
+ "\x77\x9e\xab\xfb\x5f\x7b\xfb\xd6"
+ "\x9c\xfc\x4e\x96\x7e\xdb\x80\x8d"
+ "\x67\x9f\x77\x7b\xc6\x70\x2c\x7d"
+ "\x39\xf2\x33\x69\xa9\xd9\xba\xcf"
+ "\xa5\x30\xe2\x63\x04\x23\x14\x61"
+ "\xb2\xeb\x05\xe2\xc3\x9b\xe9\xfc"
+ "\xda\x6c\x19\x07\x8c\x6a\x9d\x1b",
.ilen = 64,
- .result = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96,
- 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a,
- 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c,
- 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51,
- 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11,
- 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef,
- 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17,
- 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10 },
+ .result = "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96"
+ "\xe9\x3d\x7e\x11\x73\x93\x17\x2a"
+ "\xae\x2d\x8a\x57\x1e\x03\xac\x9c"
+ "\x9e\xb7\x6f\xac\x45\xaf\x8e\x51"
+ "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11"
+ "\xe5\xfb\xc1\x19\x1a\x0a\x52\xef"
+ "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17"
+ "\xad\x2b\x41\x7b\xe6\x6c\x37\x10",
.rlen = 64,
},
};
static struct cipher_testvec aes_lrw_enc_tv_template[] = {
/* from http://grouper.ieee.org/groups/1619/email/pdf00017.pdf */
{ /* LRW-32-AES 1 */
- .key = { 0x45, 0x62, 0xac, 0x25, 0xf8, 0x28, 0x17, 0x6d,
- 0x4c, 0x26, 0x84, 0x14, 0xb5, 0x68, 0x01, 0x85,
- 0x25, 0x8e, 0x2a, 0x05, 0xe7, 0x3e, 0x9d, 0x03,
- 0xee, 0x5a, 0x83, 0x0c, 0xcc, 0x09, 0x4c, 0x87 },
+ .key = "\x45\x62\xac\x25\xf8\x28\x17\x6d"
+ "\x4c\x26\x84\x14\xb5\x68\x01\x85"
+ "\x25\x8e\x2a\x05\xe7\x3e\x9d\x03"
+ "\xee\x5a\x83\x0c\xcc\x09\x4c\x87",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
- .input = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x01",
+ .input = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.ilen = 16,
- .result = { 0xf1, 0xb2, 0x73, 0xcd, 0x65, 0xa3, 0xdf, 0x5f,
- 0xe9, 0x5d, 0x48, 0x92, 0x54, 0x63, 0x4e, 0xb8 },
+ .result = "\xf1\xb2\x73\xcd\x65\xa3\xdf\x5f"
+ "\xe9\x5d\x48\x92\x54\x63\x4e\xb8",
.rlen = 16,
}, { /* LRW-32-AES 2 */
- .key = { 0x59, 0x70, 0x47, 0x14, 0xf5, 0x57, 0x47, 0x8c,
- 0xd7, 0x79, 0xe8, 0x0f, 0x54, 0x88, 0x79, 0x44,
- 0x0d, 0x48, 0xf0, 0xb7, 0xb1, 0x5a, 0x53, 0xea,
- 0x1c, 0xaa, 0x6b, 0x29, 0xc2, 0xca, 0xfb, 0xaf
- },
+ .key = "\x59\x70\x47\x14\xf5\x57\x47\x8c"
+ "\xd7\x79\xe8\x0f\x54\x88\x79\x44"
+ "\x0d\x48\xf0\xb7\xb1\x5a\x53\xea"
+ "\x1c\xaa\x6b\x29\xc2\xca\xfb\xaf",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 },
- .input = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x02",
+ .input = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.ilen = 16,
- .result = { 0x00, 0xc8, 0x2b, 0xae, 0x95, 0xbb, 0xcd, 0xe5,
- 0x27, 0x4f, 0x07, 0x69, 0xb2, 0x60, 0xe1, 0x36 },
+ .result = "\x00\xc8\x2b\xae\x95\xbb\xcd\xe5"
+ "\x27\x4f\x07\x69\xb2\x60\xe1\x36",
.rlen = 16,
}, { /* LRW-32-AES 3 */
- .key = { 0xd8, 0x2a, 0x91, 0x34, 0xb2, 0x6a, 0x56, 0x50,
- 0x30, 0xfe, 0x69, 0xe2, 0x37, 0x7f, 0x98, 0x47,
- 0xcd, 0xf9, 0x0b, 0x16, 0x0c, 0x64, 0x8f, 0xb6,
- 0xb0, 0x0d, 0x0d, 0x1b, 0xae, 0x85, 0x87, 0x1f },
+ .key = "\xd8\x2a\x91\x34\xb2\x6a\x56\x50"
+ "\x30\xfe\x69\xe2\x37\x7f\x98\x47"
+ "\xcd\xf9\x0b\x16\x0c\x64\x8f\xb6"
+ "\xb0\x0d\x0d\x1b\xae\x85\x87\x1f",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x02\x00\x00\x00\x00",
+ .input = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.ilen = 16,
- .result = { 0x76, 0x32, 0x21, 0x83, 0xed, 0x8f, 0xf1, 0x82,
- 0xf9, 0x59, 0x62, 0x03, 0x69, 0x0e, 0x5e, 0x01 },
+ .result = "\x76\x32\x21\x83\xed\x8f\xf1\x82"
+ "\xf9\x59\x62\x03\x69\x0e\x5e\x01",
.rlen = 16,
}, { /* LRW-32-AES 4 */
- .key = { 0x0f, 0x6a, 0xef, 0xf8, 0xd3, 0xd2, 0xbb, 0x15,
- 0x25, 0x83, 0xf7, 0x3c, 0x1f, 0x01, 0x28, 0x74,
- 0xca, 0xc6, 0xbc, 0x35, 0x4d, 0x4a, 0x65, 0x54,
- 0x90, 0xae, 0x61, 0xcf, 0x7b, 0xae, 0xbd, 0xcc,
- 0xad, 0xe4, 0x94, 0xc5, 0x4a, 0x29, 0xae, 0x70 },
+ .key = "\x0f\x6a\xef\xf8\xd3\xd2\xbb\x15"
+ "\x25\x83\xf7\x3c\x1f\x01\x28\x74"
+ "\xca\xc6\xbc\x35\x4d\x4a\x65\x54"
+ "\x90\xae\x61\xcf\x7b\xae\xbd\xcc"
+ "\xad\xe4\x94\xc5\x4a\x29\xae\x70",
.klen = 40,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
- .input = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x01",
+ .input = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.ilen = 16,
- .result = { 0x9c, 0x0f, 0x15, 0x2f, 0x55, 0xa2, 0xd8, 0xf0,
- 0xd6, 0x7b, 0x8f, 0x9e, 0x28, 0x22, 0xbc, 0x41 },
+ .result = "\x9c\x0f\x15\x2f\x55\xa2\xd8\xf0"
+ "\xd6\x7b\x8f\x9e\x28\x22\xbc\x41",
.rlen = 16,
}, { /* LRW-32-AES 5 */
- .key = { 0x8a, 0xd4, 0xee, 0x10, 0x2f, 0xbd, 0x81, 0xff,
- 0xf8, 0x86, 0xce, 0xac, 0x93, 0xc5, 0xad, 0xc6,
- 0xa0, 0x19, 0x07, 0xc0, 0x9d, 0xf7, 0xbb, 0xdd,
- 0x52, 0x13, 0xb2, 0xb7, 0xf0, 0xff, 0x11, 0xd8,
- 0xd6, 0x08, 0xd0, 0xcd, 0x2e, 0xb1, 0x17, 0x6f },
+ .key = "\x8a\xd4\xee\x10\x2f\xbd\x81\xff"
+ "\xf8\x86\xce\xac\x93\xc5\xad\xc6"
+ "\xa0\x19\x07\xc0\x9d\xf7\xbb\xdd"
+ "\x52\x13\xb2\xb7\xf0\xff\x11\xd8"
+ "\xd6\x08\xd0\xcd\x2e\xb1\x17\x6f",
.klen = 40,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x02\x00\x00\x00\x00",
+ .input = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.ilen = 16,
- .result = { 0xd4, 0x27, 0x6a, 0x7f, 0x14, 0x91, 0x3d, 0x65,
- 0xc8, 0x60, 0x48, 0x02, 0x87, 0xe3, 0x34, 0x06 },
+ .result = "\xd4\x27\x6a\x7f\x14\x91\x3d\x65"
+ "\xc8\x60\x48\x02\x87\xe3\x34\x06",
.rlen = 16,
}, { /* LRW-32-AES 6 */
- .key = { 0xf8, 0xd4, 0x76, 0xff, 0xd6, 0x46, 0xee, 0x6c,
- 0x23, 0x84, 0xcb, 0x1c, 0x77, 0xd6, 0x19, 0x5d,
- 0xfe, 0xf1, 0xa9, 0xf3, 0x7b, 0xbc, 0x8d, 0x21,
- 0xa7, 0x9c, 0x21, 0xf8, 0xcb, 0x90, 0x02, 0x89,
- 0xa8, 0x45, 0x34, 0x8e, 0xc8, 0xc5, 0xb5, 0xf1,
- 0x26, 0xf5, 0x0e, 0x76, 0xfe, 0xfd, 0x1b, 0x1e },
+ .key = "\xf8\xd4\x76\xff\xd6\x46\xee\x6c"
+ "\x23\x84\xcb\x1c\x77\xd6\x19\x5d"
+ "\xfe\xf1\xa9\xf3\x7b\xbc\x8d\x21"
+ "\xa7\x9c\x21\xf8\xcb\x90\x02\x89"
+ "\xa8\x45\x34\x8e\xc8\xc5\xb5\xf1"
+ "\x26\xf5\x0e\x76\xfe\xfd\x1b\x1e",
.klen = 48,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
- .input = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x01",
+ .input = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.ilen = 16,
- .result = { 0xbd, 0x06, 0xb8, 0xe1, 0xdb, 0x98, 0x89, 0x9e,
- 0xc4, 0x98, 0xe4, 0x91, 0xcf, 0x1c, 0x70, 0x2b },
+ .result = "\xbd\x06\xb8\xe1\xdb\x98\x89\x9e"
+ "\xc4\x98\xe4\x91\xcf\x1c\x70\x2b",
.rlen = 16,
}, { /* LRW-32-AES 7 */
- .key = { 0xfb, 0x76, 0x15, 0xb2, 0x3d, 0x80, 0x89, 0x1d,
- 0xd4, 0x70, 0x98, 0x0b, 0xc7, 0x95, 0x84, 0xc8,
- 0xb2, 0xfb, 0x64, 0xce, 0x60, 0x97, 0x87, 0x8d,
- 0x17, 0xfc, 0xe4, 0x5a, 0x49, 0xe8, 0x30, 0xb7,
- 0x6e, 0x78, 0x17, 0xe7, 0x2d, 0x5e, 0x12, 0xd4,
- 0x60, 0x64, 0x04, 0x7a, 0xf1, 0x2f, 0x9e, 0x0c },
+ .key = "\xfb\x76\x15\xb2\x3d\x80\x89\x1d"
+ "\xd4\x70\x98\x0b\xc7\x95\x84\xc8"
+ "\xb2\xfb\x64\xce\x60\x97\x87\x8d"
+ "\x17\xfc\xe4\x5a\x49\xe8\x30\xb7"
+ "\x6e\x78\x17\xe7\x2d\x5e\x12\xd4"
+ "\x60\x64\x04\x7a\xf1\x2f\x9e\x0c",
.klen = 48,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x02\x00\x00\x00\x00",
+ .input = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.ilen = 16,
- .result = { 0x5b, 0x90, 0x8e, 0xc1, 0xab, 0xdd, 0x67, 0x5f,
- 0x3d, 0x69, 0x8a, 0x95, 0x53, 0xc8, 0x9c, 0xe5 },
+ .result = "\x5b\x90\x8e\xc1\xab\xdd\x67\x5f"
+ "\x3d\x69\x8a\x95\x53\xc8\x9c\xe5",
.rlen = 16,
}, {
/* http://www.mail-archive.com/stds-p1619@listserv.ieee.org/msg00173.html */
- .key = { 0xf8, 0xd4, 0x76, 0xff, 0xd6, 0x46, 0xee, 0x6c,
- 0x23, 0x84, 0xcb, 0x1c, 0x77, 0xd6, 0x19, 0x5d,
- 0xfe, 0xf1, 0xa9, 0xf3, 0x7b, 0xbc, 0x8d, 0x21,
- 0xa7, 0x9c, 0x21, 0xf8, 0xcb, 0x90, 0x02, 0x89,
- 0xa8, 0x45, 0x34, 0x8e, 0xc8, 0xc5, 0xb5, 0xf1,
- 0x26, 0xf5, 0x0e, 0x76, 0xfe, 0xfd, 0x1b, 0x1e },
+ .key = "\xf8\xd4\x76\xff\xd6\x46\xee\x6c"
+ "\x23\x84\xcb\x1c\x77\xd6\x19\x5d"
+ "\xfe\xf1\xa9\xf3\x7b\xbc\x8d\x21"
+ "\xa7\x9c\x21\xf8\xcb\x90\x02\x89"
+ "\xa8\x45\x34\x8e\xc8\xc5\xb5\xf1"
+ "\x26\xf5\x0e\x76\xfe\xfd\x1b\x1e",
.klen = 48,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
- .input = { 0x05, 0x11, 0xb7, 0x18, 0xab, 0xc6, 0x2d, 0xac,
- 0x70, 0x5d, 0xf6, 0x22, 0x94, 0xcd, 0xe5, 0x6c,
- 0x17, 0x6b, 0xf6, 0x1c, 0xf0, 0xf3, 0x6e, 0xf8,
- 0x50, 0x38, 0x1f, 0x71, 0x49, 0xb6, 0x57, 0xd6,
- 0x8f, 0xcb, 0x8d, 0x6b, 0xe3, 0xa6, 0x29, 0x90,
- 0xfe, 0x2a, 0x62, 0x82, 0xae, 0x6d, 0x8b, 0xf6,
- 0xad, 0x1e, 0x9e, 0x20, 0x5f, 0x38, 0xbe, 0x04,
- 0xda, 0x10, 0x8e, 0xed, 0xa2, 0xa4, 0x87, 0xab,
- 0xda, 0x6b, 0xb4, 0x0c, 0x75, 0xba, 0xd3, 0x7c,
- 0xc9, 0xac, 0x42, 0x31, 0x95, 0x7c, 0xc9, 0x04,
- 0xeb, 0xd5, 0x6e, 0x32, 0x69, 0x8a, 0xdb, 0xa6,
- 0x15, 0xd7, 0x3f, 0x4f, 0x2f, 0x66, 0x69, 0x03,
- 0x9c, 0x1f, 0x54, 0x0f, 0xde, 0x1f, 0xf3, 0x65,
- 0x4c, 0x96, 0x12, 0xed, 0x7c, 0x92, 0x03, 0x01,
- 0x6f, 0xbc, 0x35, 0x93, 0xac, 0xf1, 0x27, 0xf1,
- 0xb4, 0x96, 0x82, 0x5a, 0x5f, 0xb0, 0xa0, 0x50,
- 0x89, 0xa4, 0x8e, 0x66, 0x44, 0x85, 0xcc, 0xfd,
- 0x33, 0x14, 0x70, 0xe3, 0x96, 0xb2, 0xc3, 0xd3,
- 0xbb, 0x54, 0x5a, 0x1a, 0xf9, 0x74, 0xa2, 0xc5,
- 0x2d, 0x64, 0x75, 0xdd, 0xb4, 0x54, 0xe6, 0x74,
- 0x8c, 0xd3, 0x9d, 0x9e, 0x86, 0xab, 0x51, 0x53,
- 0xb7, 0x93, 0x3e, 0x6f, 0xd0, 0x4e, 0x2c, 0x40,
- 0xf6, 0xa8, 0x2e, 0x3e, 0x9d, 0xf4, 0x66, 0xa5,
- 0x76, 0x12, 0x73, 0x44, 0x1a, 0x56, 0xd7, 0x72,
- 0x88, 0xcd, 0x21, 0x8c, 0x4c, 0x0f, 0xfe, 0xda,
- 0x95, 0xe0, 0x3a, 0xa6, 0xa5, 0x84, 0x46, 0xcd,
- 0xd5, 0x3e, 0x9d, 0x3a, 0xe2, 0x67, 0xe6, 0x60,
- 0x1a, 0xe2, 0x70, 0x85, 0x58, 0xc2, 0x1b, 0x09,
- 0xe1, 0xd7, 0x2c, 0xca, 0xad, 0xa8, 0x8f, 0xf9,
- 0xac, 0xb3, 0x0e, 0xdb, 0xca, 0x2e, 0xe2, 0xb8,
- 0x51, 0x71, 0xd9, 0x3c, 0x6c, 0xf1, 0x56, 0xf8,
- 0xea, 0x9c, 0xf1, 0xfb, 0x0c, 0xe6, 0xb7, 0x10,
- 0x1c, 0xf8, 0xa9, 0x7c, 0xe8, 0x53, 0x35, 0xc1,
- 0x90, 0x3e, 0x76, 0x4a, 0x74, 0xa4, 0x21, 0x2c,
- 0xf6, 0x2c, 0x4e, 0x0f, 0x94, 0x3a, 0x88, 0x2e,
- 0x41, 0x09, 0x6a, 0x33, 0x7d, 0xf6, 0xdd, 0x3f,
- 0x8d, 0x23, 0x31, 0x74, 0x84, 0xeb, 0x88, 0x6e,
- 0xcc, 0xb9, 0xbc, 0x22, 0x83, 0x19, 0x07, 0x22,
- 0xa5, 0x2d, 0xdf, 0xa5, 0xf3, 0x80, 0x85, 0x78,
- 0x84, 0x39, 0x6a, 0x6d, 0x6a, 0x99, 0x4f, 0xa5,
- 0x15, 0xfe, 0x46, 0xb0, 0xe4, 0x6c, 0xa5, 0x41,
- 0x3c, 0xce, 0x8f, 0x42, 0x60, 0x71, 0xa7, 0x75,
- 0x08, 0x40, 0x65, 0x8a, 0x82, 0xbf, 0xf5, 0x43,
- 0x71, 0x96, 0xa9, 0x4d, 0x44, 0x8a, 0x20, 0xbe,
- 0xfa, 0x4d, 0xbb, 0xc0, 0x7d, 0x31, 0x96, 0x65,
- 0xe7, 0x75, 0xe5, 0x3e, 0xfd, 0x92, 0x3b, 0xc9,
- 0x55, 0xbb, 0x16, 0x7e, 0xf7, 0xc2, 0x8c, 0xa4,
- 0x40, 0x1d, 0xe5, 0xef, 0x0e, 0xdf, 0xe4, 0x9a,
- 0x62, 0x73, 0x65, 0xfd, 0x46, 0x63, 0x25, 0x3d,
- 0x2b, 0xaf, 0xe5, 0x64, 0xfe, 0xa5, 0x5c, 0xcf,
- 0x24, 0xf3, 0xb4, 0xac, 0x64, 0xba, 0xdf, 0x4b,
- 0xc6, 0x96, 0x7d, 0x81, 0x2d, 0x8d, 0x97, 0xf7,
- 0xc5, 0x68, 0x77, 0x84, 0x32, 0x2b, 0xcc, 0x85,
- 0x74, 0x96, 0xf0, 0x12, 0x77, 0x61, 0xb9, 0xeb,
- 0x71, 0xaa, 0x82, 0xcb, 0x1c, 0xdb, 0x89, 0xc8,
- 0xc6, 0xb5, 0xe3, 0x5c, 0x7d, 0x39, 0x07, 0x24,
- 0xda, 0x39, 0x87, 0x45, 0xc0, 0x2b, 0xbb, 0x01,
- 0xac, 0xbc, 0x2a, 0x5c, 0x7f, 0xfc, 0xe8, 0xce,
- 0x6d, 0x9c, 0x6f, 0xed, 0xd3, 0xc1, 0xa1, 0xd6,
- 0xc5, 0x55, 0xa9, 0x66, 0x2f, 0xe1, 0xc8, 0x32,
- 0xa6, 0x5d, 0xa4, 0x3a, 0x98, 0x73, 0xe8, 0x45,
- 0xa4, 0xc7, 0xa8, 0xb4, 0xf6, 0x13, 0x03, 0xf6,
- 0xe9, 0x2e, 0xc4, 0x29, 0x0f, 0x84, 0xdb, 0xc4,
- 0x21, 0xc4, 0xc2, 0x75, 0x67, 0x89, 0x37, 0x0a },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x01",
+ .input = "\x05\x11\xb7\x18\xab\xc6\x2d\xac"
+ "\x70\x5d\xf6\x22\x94\xcd\xe5\x6c"
+ "\x17\x6b\xf6\x1c\xf0\xf3\x6e\xf8"
+ "\x50\x38\x1f\x71\x49\xb6\x57\xd6"
+ "\x8f\xcb\x8d\x6b\xe3\xa6\x29\x90"
+ "\xfe\x2a\x62\x82\xae\x6d\x8b\xf6"
+ "\xad\x1e\x9e\x20\x5f\x38\xbe\x04"
+ "\xda\x10\x8e\xed\xa2\xa4\x87\xab"
+ "\xda\x6b\xb4\x0c\x75\xba\xd3\x7c"
+ "\xc9\xac\x42\x31\x95\x7c\xc9\x04"
+ "\xeb\xd5\x6e\x32\x69\x8a\xdb\xa6"
+ "\x15\xd7\x3f\x4f\x2f\x66\x69\x03"
+ "\x9c\x1f\x54\x0f\xde\x1f\xf3\x65"
+ "\x4c\x96\x12\xed\x7c\x92\x03\x01"
+ "\x6f\xbc\x35\x93\xac\xf1\x27\xf1"
+ "\xb4\x96\x82\x5a\x5f\xb0\xa0\x50"
+ "\x89\xa4\x8e\x66\x44\x85\xcc\xfd"
+ "\x33\x14\x70\xe3\x96\xb2\xc3\xd3"
+ "\xbb\x54\x5a\x1a\xf9\x74\xa2\xc5"
+ "\x2d\x64\x75\xdd\xb4\x54\xe6\x74"
+ "\x8c\xd3\x9d\x9e\x86\xab\x51\x53"
+ "\xb7\x93\x3e\x6f\xd0\x4e\x2c\x40"
+ "\xf6\xa8\x2e\x3e\x9d\xf4\x66\xa5"
+ "\x76\x12\x73\x44\x1a\x56\xd7\x72"
+ "\x88\xcd\x21\x8c\x4c\x0f\xfe\xda"
+ "\x95\xe0\x3a\xa6\xa5\x84\x46\xcd"
+ "\xd5\x3e\x9d\x3a\xe2\x67\xe6\x60"
+ "\x1a\xe2\x70\x85\x58\xc2\x1b\x09"
+ "\xe1\xd7\x2c\xca\xad\xa8\x8f\xf9"
+ "\xac\xb3\x0e\xdb\xca\x2e\xe2\xb8"
+ "\x51\x71\xd9\x3c\x6c\xf1\x56\xf8"
+ "\xea\x9c\xf1\xfb\x0c\xe6\xb7\x10"
+ "\x1c\xf8\xa9\x7c\xe8\x53\x35\xc1"
+ "\x90\x3e\x76\x4a\x74\xa4\x21\x2c"
+ "\xf6\x2c\x4e\x0f\x94\x3a\x88\x2e"
+ "\x41\x09\x6a\x33\x7d\xf6\xdd\x3f"
+ "\x8d\x23\x31\x74\x84\xeb\x88\x6e"
+ "\xcc\xb9\xbc\x22\x83\x19\x07\x22"
+ "\xa5\x2d\xdf\xa5\xf3\x80\x85\x78"
+ "\x84\x39\x6a\x6d\x6a\x99\x4f\xa5"
+ "\x15\xfe\x46\xb0\xe4\x6c\xa5\x41"
+ "\x3c\xce\x8f\x42\x60\x71\xa7\x75"
+ "\x08\x40\x65\x8a\x82\xbf\xf5\x43"
+ "\x71\x96\xa9\x4d\x44\x8a\x20\xbe"
+ "\xfa\x4d\xbb\xc0\x7d\x31\x96\x65"
+ "\xe7\x75\xe5\x3e\xfd\x92\x3b\xc9"
+ "\x55\xbb\x16\x7e\xf7\xc2\x8c\xa4"
+ "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a"
+ "\x62\x73\x65\xfd\x46\x63\x25\x3d"
+ "\x2b\xaf\xe5\x64\xfe\xa5\x5c\xcf"
+ "\x24\xf3\xb4\xac\x64\xba\xdf\x4b"
+ "\xc6\x96\x7d\x81\x2d\x8d\x97\xf7"
+ "\xc5\x68\x77\x84\x32\x2b\xcc\x85"
+ "\x74\x96\xf0\x12\x77\x61\xb9\xeb"
+ "\x71\xaa\x82\xcb\x1c\xdb\x89\xc8"
+ "\xc6\xb5\xe3\x5c\x7d\x39\x07\x24"
+ "\xda\x39\x87\x45\xc0\x2b\xbb\x01"
+ "\xac\xbc\x2a\x5c\x7f\xfc\xe8\xce"
+ "\x6d\x9c\x6f\xed\xd3\xc1\xa1\xd6"
+ "\xc5\x55\xa9\x66\x2f\xe1\xc8\x32"
+ "\xa6\x5d\xa4\x3a\x98\x73\xe8\x45"
+ "\xa4\xc7\xa8\xb4\xf6\x13\x03\xf6"
+ "\xe9\x2e\xc4\x29\x0f\x84\xdb\xc4"
+ "\x21\xc4\xc2\x75\x67\x89\x37\x0a",
.ilen = 512,
- .result = { 0x1a, 0x1d, 0xa9, 0x30, 0xad, 0xf9, 0x2f, 0x9b,
- 0xb6, 0x1d, 0xae, 0xef, 0xf0, 0x2f, 0xf8, 0x5a,
- 0x39, 0x3c, 0xbf, 0x2a, 0xb2, 0x45, 0xb2, 0x23,
- 0x1b, 0x63, 0x3c, 0xcf, 0xaa, 0xbe, 0xcf, 0x4e,
- 0xfa, 0xe8, 0x29, 0xc2, 0x20, 0x68, 0x2b, 0x3c,
- 0x2e, 0x8b, 0xf7, 0x6e, 0x25, 0xbd, 0xe3, 0x3d,
- 0x66, 0x27, 0xd6, 0xaf, 0xd6, 0x64, 0x3e, 0xe3,
- 0xe8, 0x58, 0x46, 0x97, 0x39, 0x51, 0x07, 0xde,
- 0xcb, 0x37, 0xbc, 0xa9, 0xc0, 0x5f, 0x75, 0xc3,
- 0x0e, 0x84, 0x23, 0x1d, 0x16, 0xd4, 0x1c, 0x59,
- 0x9c, 0x1a, 0x02, 0x55, 0xab, 0x3a, 0x97, 0x1d,
- 0xdf, 0xdd, 0xc7, 0x06, 0x51, 0xd7, 0x70, 0xae,
- 0x23, 0xc6, 0x8c, 0xf5, 0x1e, 0xa0, 0xe5, 0x82,
- 0xb8, 0xb2, 0xbf, 0x04, 0xa0, 0x32, 0x8e, 0x68,
- 0xeb, 0xaf, 0x6e, 0x2d, 0x94, 0x22, 0x2f, 0xce,
- 0x4c, 0xb5, 0x59, 0xe2, 0xa2, 0x2f, 0xa0, 0x98,
- 0x1a, 0x97, 0xc6, 0xd4, 0xb5, 0x00, 0x59, 0xf2,
- 0x84, 0x14, 0x72, 0xb1, 0x9a, 0x6e, 0xa3, 0x7f,
- 0xea, 0x20, 0xe7, 0xcb, 0x65, 0x77, 0x3a, 0xdf,
- 0xc8, 0x97, 0x67, 0x15, 0xc2, 0x2a, 0x27, 0xcc,
- 0x18, 0x55, 0xa1, 0x24, 0x0b, 0x24, 0x24, 0xaf,
- 0x5b, 0xec, 0x68, 0xb8, 0xc8, 0xf5, 0xba, 0x63,
- 0xff, 0xed, 0x89, 0xce, 0xd5, 0x3d, 0x88, 0xf3,
- 0x25, 0xef, 0x05, 0x7c, 0x3a, 0xef, 0xeb, 0xd8,
- 0x7a, 0x32, 0x0d, 0xd1, 0x1e, 0x58, 0x59, 0x99,
- 0x90, 0x25, 0xb5, 0x26, 0xb0, 0xe3, 0x2b, 0x6c,
- 0x4c, 0xa9, 0x8b, 0x84, 0x4f, 0x5e, 0x01, 0x50,
- 0x41, 0x30, 0x58, 0xc5, 0x62, 0x74, 0x52, 0x1d,
- 0x45, 0x24, 0x6a, 0x42, 0x64, 0x4f, 0x97, 0x1c,
- 0xa8, 0x66, 0xb5, 0x6d, 0x79, 0xd4, 0x0d, 0x48,
- 0xc5, 0x5f, 0xf3, 0x90, 0x32, 0xdd, 0xdd, 0xe1,
- 0xe4, 0xa9, 0x9f, 0xfc, 0xc3, 0x52, 0x5a, 0x46,
- 0xe4, 0x81, 0x84, 0x95, 0x36, 0x59, 0x7a, 0x6b,
- 0xaa, 0xb3, 0x60, 0xad, 0xce, 0x9f, 0x9f, 0x28,
- 0xe0, 0x01, 0x75, 0x22, 0xc4, 0x4e, 0xa9, 0x62,
- 0x5c, 0x62, 0x0d, 0x00, 0xcb, 0x13, 0xe8, 0x43,
- 0x72, 0xd4, 0x2d, 0x53, 0x46, 0xb5, 0xd1, 0x16,
- 0x22, 0x18, 0xdf, 0x34, 0x33, 0xf5, 0xd6, 0x1c,
- 0xb8, 0x79, 0x78, 0x97, 0x94, 0xff, 0x72, 0x13,
- 0x4c, 0x27, 0xfc, 0xcb, 0xbf, 0x01, 0x53, 0xa6,
- 0xb4, 0x50, 0x6e, 0xde, 0xdf, 0xb5, 0x43, 0xa4,
- 0x59, 0xdf, 0x52, 0xf9, 0x7c, 0xe0, 0x11, 0x6f,
- 0x2d, 0x14, 0x8e, 0x24, 0x61, 0x2c, 0xe1, 0x17,
- 0xcc, 0xce, 0x51, 0x0c, 0x19, 0x8a, 0x82, 0x30,
- 0x94, 0xd5, 0x3d, 0x6a, 0x53, 0x06, 0x5e, 0xbd,
- 0xb7, 0xeb, 0xfa, 0xfd, 0x27, 0x51, 0xde, 0x85,
- 0x1e, 0x86, 0x53, 0x11, 0x53, 0x94, 0x00, 0xee,
- 0x2b, 0x8c, 0x08, 0x2a, 0xbf, 0xdd, 0xae, 0x11,
- 0xcb, 0x1e, 0xa2, 0x07, 0x9a, 0x80, 0xcf, 0x62,
- 0x9b, 0x09, 0xdc, 0x95, 0x3c, 0x96, 0x8e, 0xb1,
- 0x09, 0xbd, 0xe4, 0xeb, 0xdb, 0xca, 0x70, 0x7a,
- 0x9e, 0xfa, 0x31, 0x18, 0x45, 0x3c, 0x21, 0x33,
- 0xb0, 0xb3, 0x2b, 0xea, 0xf3, 0x71, 0x2d, 0xe1,
- 0x03, 0xad, 0x1b, 0x48, 0xd4, 0x67, 0x27, 0xf0,
- 0x62, 0xe4, 0x3d, 0xfb, 0x9b, 0x08, 0x76, 0xe7,
- 0xdd, 0x2b, 0x01, 0x39, 0x04, 0x5a, 0x58, 0x7a,
- 0xf7, 0x11, 0x90, 0xec, 0xbd, 0x51, 0x5c, 0x32,
- 0x6b, 0xd7, 0x35, 0x39, 0x02, 0x6b, 0xf2, 0xa6,
- 0xd0, 0x0d, 0x07, 0xe1, 0x06, 0xc4, 0x5b, 0x7d,
- 0xe4, 0x6a, 0xd7, 0xee, 0x15, 0x1f, 0x83, 0xb4,
- 0xa3, 0xa7, 0x5e, 0xc3, 0x90, 0xb7, 0xef, 0xd3,
- 0xb7, 0x4f, 0xf8, 0x92, 0x4c, 0xb7, 0x3c, 0x29,
- 0xcd, 0x7e, 0x2b, 0x5d, 0x43, 0xea, 0x42, 0xe7,
- 0x74, 0x3f, 0x7d, 0x58, 0x88, 0x75, 0xde, 0x3e },
+ .result = "\x1a\x1d\xa9\x30\xad\xf9\x2f\x9b"
+ "\xb6\x1d\xae\xef\xf0\x2f\xf8\x5a"
+ "\x39\x3c\xbf\x2a\xb2\x45\xb2\x23"
+ "\x1b\x63\x3c\xcf\xaa\xbe\xcf\x4e"
+ "\xfa\xe8\x29\xc2\x20\x68\x2b\x3c"
+ "\x2e\x8b\xf7\x6e\x25\xbd\xe3\x3d"
+ "\x66\x27\xd6\xaf\xd6\x64\x3e\xe3"
+ "\xe8\x58\x46\x97\x39\x51\x07\xde"
+ "\xcb\x37\xbc\xa9\xc0\x5f\x75\xc3"
+ "\x0e\x84\x23\x1d\x16\xd4\x1c\x59"
+ "\x9c\x1a\x02\x55\xab\x3a\x97\x1d"
+ "\xdf\xdd\xc7\x06\x51\xd7\x70\xae"
+ "\x23\xc6\x8c\xf5\x1e\xa0\xe5\x82"
+ "\xb8\xb2\xbf\x04\xa0\x32\x8e\x68"
+ "\xeb\xaf\x6e\x2d\x94\x22\x2f\xce"
+ "\x4c\xb5\x59\xe2\xa2\x2f\xa0\x98"
+ "\x1a\x97\xc6\xd4\xb5\x00\x59\xf2"
+ "\x84\x14\x72\xb1\x9a\x6e\xa3\x7f"
+ "\xea\x20\xe7\xcb\x65\x77\x3a\xdf"
+ "\xc8\x97\x67\x15\xc2\x2a\x27\xcc"
+ "\x18\x55\xa1\x24\x0b\x24\x24\xaf"
+ "\x5b\xec\x68\xb8\xc8\xf5\xba\x63"
+ "\xff\xed\x89\xce\xd5\x3d\x88\xf3"
+ "\x25\xef\x05\x7c\x3a\xef\xeb\xd8"
+ "\x7a\x32\x0d\xd1\x1e\x58\x59\x99"
+ "\x90\x25\xb5\x26\xb0\xe3\x2b\x6c"
+ "\x4c\xa9\x8b\x84\x4f\x5e\x01\x50"
+ "\x41\x30\x58\xc5\x62\x74\x52\x1d"
+ "\x45\x24\x6a\x42\x64\x4f\x97\x1c"
+ "\xa8\x66\xb5\x6d\x79\xd4\x0d\x48"
+ "\xc5\x5f\xf3\x90\x32\xdd\xdd\xe1"
+ "\xe4\xa9\x9f\xfc\xc3\x52\x5a\x46"
+ "\xe4\x81\x84\x95\x36\x59\x7a\x6b"
+ "\xaa\xb3\x60\xad\xce\x9f\x9f\x28"
+ "\xe0\x01\x75\x22\xc4\x4e\xa9\x62"
+ "\x5c\x62\x0d\x00\xcb\x13\xe8\x43"
+ "\x72\xd4\x2d\x53\x46\xb5\xd1\x16"
+ "\x22\x18\xdf\x34\x33\xf5\xd6\x1c"
+ "\xb8\x79\x78\x97\x94\xff\x72\x13"
+ "\x4c\x27\xfc\xcb\xbf\x01\x53\xa6"
+ "\xb4\x50\x6e\xde\xdf\xb5\x43\xa4"
+ "\x59\xdf\x52\xf9\x7c\xe0\x11\x6f"
+ "\x2d\x14\x8e\x24\x61\x2c\xe1\x17"
+ "\xcc\xce\x51\x0c\x19\x8a\x82\x30"
+ "\x94\xd5\x3d\x6a\x53\x06\x5e\xbd"
+ "\xb7\xeb\xfa\xfd\x27\x51\xde\x85"
+ "\x1e\x86\x53\x11\x53\x94\x00\xee"
+ "\x2b\x8c\x08\x2a\xbf\xdd\xae\x11"
+ "\xcb\x1e\xa2\x07\x9a\x80\xcf\x62"
+ "\x9b\x09\xdc\x95\x3c\x96\x8e\xb1"
+ "\x09\xbd\xe4\xeb\xdb\xca\x70\x7a"
+ "\x9e\xfa\x31\x18\x45\x3c\x21\x33"
+ "\xb0\xb3\x2b\xea\xf3\x71\x2d\xe1"
+ "\x03\xad\x1b\x48\xd4\x67\x27\xf0"
+ "\x62\xe4\x3d\xfb\x9b\x08\x76\xe7"
+ "\xdd\x2b\x01\x39\x04\x5a\x58\x7a"
+ "\xf7\x11\x90\xec\xbd\x51\x5c\x32"
+ "\x6b\xd7\x35\x39\x02\x6b\xf2\xa6"
+ "\xd0\x0d\x07\xe1\x06\xc4\x5b\x7d"
+ "\xe4\x6a\xd7\xee\x15\x1f\x83\xb4"
+ "\xa3\xa7\x5e\xc3\x90\xb7\xef\xd3"
+ "\xb7\x4f\xf8\x92\x4c\xb7\x3c\x29"
+ "\xcd\x7e\x2b\x5d\x43\xea\x42\xe7"
+ "\x74\x3f\x7d\x58\x88\x75\xde\x3e",
.rlen = 512,
}
};
/* from http://grouper.ieee.org/groups/1619/email/pdf00017.pdf */
/* same as enc vectors with input and result reversed */
{ /* LRW-32-AES 1 */
- .key = { 0x45, 0x62, 0xac, 0x25, 0xf8, 0x28, 0x17, 0x6d,
- 0x4c, 0x26, 0x84, 0x14, 0xb5, 0x68, 0x01, 0x85,
- 0x25, 0x8e, 0x2a, 0x05, 0xe7, 0x3e, 0x9d, 0x03,
- 0xee, 0x5a, 0x83, 0x0c, 0xcc, 0x09, 0x4c, 0x87 },
+ .key = "\x45\x62\xac\x25\xf8\x28\x17\x6d"
+ "\x4c\x26\x84\x14\xb5\x68\x01\x85"
+ "\x25\x8e\x2a\x05\xe7\x3e\x9d\x03"
+ "\xee\x5a\x83\x0c\xcc\x09\x4c\x87",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
- .input = { 0xf1, 0xb2, 0x73, 0xcd, 0x65, 0xa3, 0xdf, 0x5f,
- 0xe9, 0x5d, 0x48, 0x92, 0x54, 0x63, 0x4e, 0xb8 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x01",
+ .input = "\xf1\xb2\x73\xcd\x65\xa3\xdf\x5f"
+ "\xe9\x5d\x48\x92\x54\x63\x4e\xb8",
.ilen = 16,
- .result = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .result = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.rlen = 16,
}, { /* LRW-32-AES 2 */
- .key = { 0x59, 0x70, 0x47, 0x14, 0xf5, 0x57, 0x47, 0x8c,
- 0xd7, 0x79, 0xe8, 0x0f, 0x54, 0x88, 0x79, 0x44,
- 0x0d, 0x48, 0xf0, 0xb7, 0xb1, 0x5a, 0x53, 0xea,
- 0x1c, 0xaa, 0x6b, 0x29, 0xc2, 0xca, 0xfb, 0xaf
- },
+ .key = "\x59\x70\x47\x14\xf5\x57\x47\x8c"
+ "\xd7\x79\xe8\x0f\x54\x88\x79\x44"
+ "\x0d\x48\xf0\xb7\xb1\x5a\x53\xea"
+ "\x1c\xaa\x6b\x29\xc2\xca\xfb\xaf",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 },
- .input = { 0x00, 0xc8, 0x2b, 0xae, 0x95, 0xbb, 0xcd, 0xe5,
- 0x27, 0x4f, 0x07, 0x69, 0xb2, 0x60, 0xe1, 0x36 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x02",
+ .input = "\x00\xc8\x2b\xae\x95\xbb\xcd\xe5"
+ "\x27\x4f\x07\x69\xb2\x60\xe1\x36",
.ilen = 16,
- .result = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .result = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.rlen = 16,
}, { /* LRW-32-AES 3 */
- .key = { 0xd8, 0x2a, 0x91, 0x34, 0xb2, 0x6a, 0x56, 0x50,
- 0x30, 0xfe, 0x69, 0xe2, 0x37, 0x7f, 0x98, 0x47,
- 0xcd, 0xf9, 0x0b, 0x16, 0x0c, 0x64, 0x8f, 0xb6,
- 0xb0, 0x0d, 0x0d, 0x1b, 0xae, 0x85, 0x87, 0x1f },
+ .key = "\xd8\x2a\x91\x34\xb2\x6a\x56\x50"
+ "\x30\xfe\x69\xe2\x37\x7f\x98\x47"
+ "\xcd\xf9\x0b\x16\x0c\x64\x8f\xb6"
+ "\xb0\x0d\x0d\x1b\xae\x85\x87\x1f",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x76, 0x32, 0x21, 0x83, 0xed, 0x8f, 0xf1, 0x82,
- 0xf9, 0x59, 0x62, 0x03, 0x69, 0x0e, 0x5e, 0x01 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x02\x00\x00\x00\x00",
+ .input = "\x76\x32\x21\x83\xed\x8f\xf1\x82"
+ "\xf9\x59\x62\x03\x69\x0e\x5e\x01",
.ilen = 16,
- .result = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .result = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.rlen = 16,
}, { /* LRW-32-AES 4 */
- .key = { 0x0f, 0x6a, 0xef, 0xf8, 0xd3, 0xd2, 0xbb, 0x15,
- 0x25, 0x83, 0xf7, 0x3c, 0x1f, 0x01, 0x28, 0x74,
- 0xca, 0xc6, 0xbc, 0x35, 0x4d, 0x4a, 0x65, 0x54,
- 0x90, 0xae, 0x61, 0xcf, 0x7b, 0xae, 0xbd, 0xcc,
- 0xad, 0xe4, 0x94, 0xc5, 0x4a, 0x29, 0xae, 0x70 },
+ .key = "\x0f\x6a\xef\xf8\xd3\xd2\xbb\x15"
+ "\x25\x83\xf7\x3c\x1f\x01\x28\x74"
+ "\xca\xc6\xbc\x35\x4d\x4a\x65\x54"
+ "\x90\xae\x61\xcf\x7b\xae\xbd\xcc"
+ "\xad\xe4\x94\xc5\x4a\x29\xae\x70",
.klen = 40,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
- .input = { 0x9c, 0x0f, 0x15, 0x2f, 0x55, 0xa2, 0xd8, 0xf0,
- 0xd6, 0x7b, 0x8f, 0x9e, 0x28, 0x22, 0xbc, 0x41 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x01",
+ .input = "\x9c\x0f\x15\x2f\x55\xa2\xd8\xf0"
+ "\xd6\x7b\x8f\x9e\x28\x22\xbc\x41",
.ilen = 16,
- .result = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .result = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.rlen = 16,
}, { /* LRW-32-AES 5 */
- .key = { 0x8a, 0xd4, 0xee, 0x10, 0x2f, 0xbd, 0x81, 0xff,
- 0xf8, 0x86, 0xce, 0xac, 0x93, 0xc5, 0xad, 0xc6,
- 0xa0, 0x19, 0x07, 0xc0, 0x9d, 0xf7, 0xbb, 0xdd,
- 0x52, 0x13, 0xb2, 0xb7, 0xf0, 0xff, 0x11, 0xd8,
- 0xd6, 0x08, 0xd0, 0xcd, 0x2e, 0xb1, 0x17, 0x6f },
+ .key = "\x8a\xd4\xee\x10\x2f\xbd\x81\xff"
+ "\xf8\x86\xce\xac\x93\xc5\xad\xc6"
+ "\xa0\x19\x07\xc0\x9d\xf7\xbb\xdd"
+ "\x52\x13\xb2\xb7\xf0\xff\x11\xd8"
+ "\xd6\x08\xd0\xcd\x2e\xb1\x17\x6f",
.klen = 40,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0xd4, 0x27, 0x6a, 0x7f, 0x14, 0x91, 0x3d, 0x65,
- 0xc8, 0x60, 0x48, 0x02, 0x87, 0xe3, 0x34, 0x06 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x02\x00\x00\x00\x00",
+ .input = "\xd4\x27\x6a\x7f\x14\x91\x3d\x65"
+ "\xc8\x60\x48\x02\x87\xe3\x34\x06",
.ilen = 16,
- .result = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .result = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.rlen = 16,
}, { /* LRW-32-AES 6 */
- .key = { 0xf8, 0xd4, 0x76, 0xff, 0xd6, 0x46, 0xee, 0x6c,
- 0x23, 0x84, 0xcb, 0x1c, 0x77, 0xd6, 0x19, 0x5d,
- 0xfe, 0xf1, 0xa9, 0xf3, 0x7b, 0xbc, 0x8d, 0x21,
- 0xa7, 0x9c, 0x21, 0xf8, 0xcb, 0x90, 0x02, 0x89,
- 0xa8, 0x45, 0x34, 0x8e, 0xc8, 0xc5, 0xb5, 0xf1,
- 0x26, 0xf5, 0x0e, 0x76, 0xfe, 0xfd, 0x1b, 0x1e },
+ .key = "\xf8\xd4\x76\xff\xd6\x46\xee\x6c"
+ "\x23\x84\xcb\x1c\x77\xd6\x19\x5d"
+ "\xfe\xf1\xa9\xf3\x7b\xbc\x8d\x21"
+ "\xa7\x9c\x21\xf8\xcb\x90\x02\x89"
+ "\xa8\x45\x34\x8e\xc8\xc5\xb5\xf1"
+ "\x26\xf5\x0e\x76\xfe\xfd\x1b\x1e",
.klen = 48,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
- .input = { 0xbd, 0x06, 0xb8, 0xe1, 0xdb, 0x98, 0x89, 0x9e,
- 0xc4, 0x98, 0xe4, 0x91, 0xcf, 0x1c, 0x70, 0x2b },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x01",
+ .input = "\xbd\x06\xb8\xe1\xdb\x98\x89\x9e"
+ "\xc4\x98\xe4\x91\xcf\x1c\x70\x2b",
.ilen = 16,
- .result = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .result = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.rlen = 16,
}, { /* LRW-32-AES 7 */
- .key = { 0xfb, 0x76, 0x15, 0xb2, 0x3d, 0x80, 0x89, 0x1d,
- 0xd4, 0x70, 0x98, 0x0b, 0xc7, 0x95, 0x84, 0xc8,
- 0xb2, 0xfb, 0x64, 0xce, 0x60, 0x97, 0x87, 0x8d,
- 0x17, 0xfc, 0xe4, 0x5a, 0x49, 0xe8, 0x30, 0xb7,
- 0x6e, 0x78, 0x17, 0xe7, 0x2d, 0x5e, 0x12, 0xd4,
- 0x60, 0x64, 0x04, 0x7a, 0xf1, 0x2f, 0x9e, 0x0c },
+ .key = "\xfb\x76\x15\xb2\x3d\x80\x89\x1d"
+ "\xd4\x70\x98\x0b\xc7\x95\x84\xc8"
+ "\xb2\xfb\x64\xce\x60\x97\x87\x8d"
+ "\x17\xfc\xe4\x5a\x49\xe8\x30\xb7"
+ "\x6e\x78\x17\xe7\x2d\x5e\x12\xd4"
+ "\x60\x64\x04\x7a\xf1\x2f\x9e\x0c",
.klen = 48,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x5b, 0x90, 0x8e, 0xc1, 0xab, 0xdd, 0x67, 0x5f,
- 0x3d, 0x69, 0x8a, 0x95, 0x53, 0xc8, 0x9c, 0xe5 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x02\x00\x00\x00\x00",
+ .input = "\x5b\x90\x8e\xc1\xab\xdd\x67\x5f"
+ "\x3d\x69\x8a\x95\x53\xc8\x9c\xe5",
.ilen = 16,
- .result = { 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 },
+ .result = "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x41\x42\x43\x44\x45\x46",
.rlen = 16,
}, {
/* http://www.mail-archive.com/stds-p1619@listserv.ieee.org/msg00173.html */
- .key = { 0xf8, 0xd4, 0x76, 0xff, 0xd6, 0x46, 0xee, 0x6c,
- 0x23, 0x84, 0xcb, 0x1c, 0x77, 0xd6, 0x19, 0x5d,
- 0xfe, 0xf1, 0xa9, 0xf3, 0x7b, 0xbc, 0x8d, 0x21,
- 0xa7, 0x9c, 0x21, 0xf8, 0xcb, 0x90, 0x02, 0x89,
- 0xa8, 0x45, 0x34, 0x8e, 0xc8, 0xc5, 0xb5, 0xf1,
- 0x26, 0xf5, 0x0e, 0x76, 0xfe, 0xfd, 0x1b, 0x1e },
+ .key = "\xf8\xd4\x76\xff\xd6\x46\xee\x6c"
+ "\x23\x84\xcb\x1c\x77\xd6\x19\x5d"
+ "\xfe\xf1\xa9\xf3\x7b\xbc\x8d\x21"
+ "\xa7\x9c\x21\xf8\xcb\x90\x02\x89"
+ "\xa8\x45\x34\x8e\xc8\xc5\xb5\xf1"
+ "\x26\xf5\x0e\x76\xfe\xfd\x1b\x1e",
.klen = 48,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
- .input = { 0x1a, 0x1d, 0xa9, 0x30, 0xad, 0xf9, 0x2f, 0x9b,
- 0xb6, 0x1d, 0xae, 0xef, 0xf0, 0x2f, 0xf8, 0x5a,
- 0x39, 0x3c, 0xbf, 0x2a, 0xb2, 0x45, 0xb2, 0x23,
- 0x1b, 0x63, 0x3c, 0xcf, 0xaa, 0xbe, 0xcf, 0x4e,
- 0xfa, 0xe8, 0x29, 0xc2, 0x20, 0x68, 0x2b, 0x3c,
- 0x2e, 0x8b, 0xf7, 0x6e, 0x25, 0xbd, 0xe3, 0x3d,
- 0x66, 0x27, 0xd6, 0xaf, 0xd6, 0x64, 0x3e, 0xe3,
- 0xe8, 0x58, 0x46, 0x97, 0x39, 0x51, 0x07, 0xde,
- 0xcb, 0x37, 0xbc, 0xa9, 0xc0, 0x5f, 0x75, 0xc3,
- 0x0e, 0x84, 0x23, 0x1d, 0x16, 0xd4, 0x1c, 0x59,
- 0x9c, 0x1a, 0x02, 0x55, 0xab, 0x3a, 0x97, 0x1d,
- 0xdf, 0xdd, 0xc7, 0x06, 0x51, 0xd7, 0x70, 0xae,
- 0x23, 0xc6, 0x8c, 0xf5, 0x1e, 0xa0, 0xe5, 0x82,
- 0xb8, 0xb2, 0xbf, 0x04, 0xa0, 0x32, 0x8e, 0x68,
- 0xeb, 0xaf, 0x6e, 0x2d, 0x94, 0x22, 0x2f, 0xce,
- 0x4c, 0xb5, 0x59, 0xe2, 0xa2, 0x2f, 0xa0, 0x98,
- 0x1a, 0x97, 0xc6, 0xd4, 0xb5, 0x00, 0x59, 0xf2,
- 0x84, 0x14, 0x72, 0xb1, 0x9a, 0x6e, 0xa3, 0x7f,
- 0xea, 0x20, 0xe7, 0xcb, 0x65, 0x77, 0x3a, 0xdf,
- 0xc8, 0x97, 0x67, 0x15, 0xc2, 0x2a, 0x27, 0xcc,
- 0x18, 0x55, 0xa1, 0x24, 0x0b, 0x24, 0x24, 0xaf,
- 0x5b, 0xec, 0x68, 0xb8, 0xc8, 0xf5, 0xba, 0x63,
- 0xff, 0xed, 0x89, 0xce, 0xd5, 0x3d, 0x88, 0xf3,
- 0x25, 0xef, 0x05, 0x7c, 0x3a, 0xef, 0xeb, 0xd8,
- 0x7a, 0x32, 0x0d, 0xd1, 0x1e, 0x58, 0x59, 0x99,
- 0x90, 0x25, 0xb5, 0x26, 0xb0, 0xe3, 0x2b, 0x6c,
- 0x4c, 0xa9, 0x8b, 0x84, 0x4f, 0x5e, 0x01, 0x50,
- 0x41, 0x30, 0x58, 0xc5, 0x62, 0x74, 0x52, 0x1d,
- 0x45, 0x24, 0x6a, 0x42, 0x64, 0x4f, 0x97, 0x1c,
- 0xa8, 0x66, 0xb5, 0x6d, 0x79, 0xd4, 0x0d, 0x48,
- 0xc5, 0x5f, 0xf3, 0x90, 0x32, 0xdd, 0xdd, 0xe1,
- 0xe4, 0xa9, 0x9f, 0xfc, 0xc3, 0x52, 0x5a, 0x46,
- 0xe4, 0x81, 0x84, 0x95, 0x36, 0x59, 0x7a, 0x6b,
- 0xaa, 0xb3, 0x60, 0xad, 0xce, 0x9f, 0x9f, 0x28,
- 0xe0, 0x01, 0x75, 0x22, 0xc4, 0x4e, 0xa9, 0x62,
- 0x5c, 0x62, 0x0d, 0x00, 0xcb, 0x13, 0xe8, 0x43,
- 0x72, 0xd4, 0x2d, 0x53, 0x46, 0xb5, 0xd1, 0x16,
- 0x22, 0x18, 0xdf, 0x34, 0x33, 0xf5, 0xd6, 0x1c,
- 0xb8, 0x79, 0x78, 0x97, 0x94, 0xff, 0x72, 0x13,
- 0x4c, 0x27, 0xfc, 0xcb, 0xbf, 0x01, 0x53, 0xa6,
- 0xb4, 0x50, 0x6e, 0xde, 0xdf, 0xb5, 0x43, 0xa4,
- 0x59, 0xdf, 0x52, 0xf9, 0x7c, 0xe0, 0x11, 0x6f,
- 0x2d, 0x14, 0x8e, 0x24, 0x61, 0x2c, 0xe1, 0x17,
- 0xcc, 0xce, 0x51, 0x0c, 0x19, 0x8a, 0x82, 0x30,
- 0x94, 0xd5, 0x3d, 0x6a, 0x53, 0x06, 0x5e, 0xbd,
- 0xb7, 0xeb, 0xfa, 0xfd, 0x27, 0x51, 0xde, 0x85,
- 0x1e, 0x86, 0x53, 0x11, 0x53, 0x94, 0x00, 0xee,
- 0x2b, 0x8c, 0x08, 0x2a, 0xbf, 0xdd, 0xae, 0x11,
- 0xcb, 0x1e, 0xa2, 0x07, 0x9a, 0x80, 0xcf, 0x62,
- 0x9b, 0x09, 0xdc, 0x95, 0x3c, 0x96, 0x8e, 0xb1,
- 0x09, 0xbd, 0xe4, 0xeb, 0xdb, 0xca, 0x70, 0x7a,
- 0x9e, 0xfa, 0x31, 0x18, 0x45, 0x3c, 0x21, 0x33,
- 0xb0, 0xb3, 0x2b, 0xea, 0xf3, 0x71, 0x2d, 0xe1,
- 0x03, 0xad, 0x1b, 0x48, 0xd4, 0x67, 0x27, 0xf0,
- 0x62, 0xe4, 0x3d, 0xfb, 0x9b, 0x08, 0x76, 0xe7,
- 0xdd, 0x2b, 0x01, 0x39, 0x04, 0x5a, 0x58, 0x7a,
- 0xf7, 0x11, 0x90, 0xec, 0xbd, 0x51, 0x5c, 0x32,
- 0x6b, 0xd7, 0x35, 0x39, 0x02, 0x6b, 0xf2, 0xa6,
- 0xd0, 0x0d, 0x07, 0xe1, 0x06, 0xc4, 0x5b, 0x7d,
- 0xe4, 0x6a, 0xd7, 0xee, 0x15, 0x1f, 0x83, 0xb4,
- 0xa3, 0xa7, 0x5e, 0xc3, 0x90, 0xb7, 0xef, 0xd3,
- 0xb7, 0x4f, 0xf8, 0x92, 0x4c, 0xb7, 0x3c, 0x29,
- 0xcd, 0x7e, 0x2b, 0x5d, 0x43, 0xea, 0x42, 0xe7,
- 0x74, 0x3f, 0x7d, 0x58, 0x88, 0x75, 0xde, 0x3e },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x01",
+ .input = "\x1a\x1d\xa9\x30\xad\xf9\x2f\x9b"
+ "\xb6\x1d\xae\xef\xf0\x2f\xf8\x5a"
+ "\x39\x3c\xbf\x2a\xb2\x45\xb2\x23"
+ "\x1b\x63\x3c\xcf\xaa\xbe\xcf\x4e"
+ "\xfa\xe8\x29\xc2\x20\x68\x2b\x3c"
+ "\x2e\x8b\xf7\x6e\x25\xbd\xe3\x3d"
+ "\x66\x27\xd6\xaf\xd6\x64\x3e\xe3"
+ "\xe8\x58\x46\x97\x39\x51\x07\xde"
+ "\xcb\x37\xbc\xa9\xc0\x5f\x75\xc3"
+ "\x0e\x84\x23\x1d\x16\xd4\x1c\x59"
+ "\x9c\x1a\x02\x55\xab\x3a\x97\x1d"
+ "\xdf\xdd\xc7\x06\x51\xd7\x70\xae"
+ "\x23\xc6\x8c\xf5\x1e\xa0\xe5\x82"
+ "\xb8\xb2\xbf\x04\xa0\x32\x8e\x68"
+ "\xeb\xaf\x6e\x2d\x94\x22\x2f\xce"
+ "\x4c\xb5\x59\xe2\xa2\x2f\xa0\x98"
+ "\x1a\x97\xc6\xd4\xb5\x00\x59\xf2"
+ "\x84\x14\x72\xb1\x9a\x6e\xa3\x7f"
+ "\xea\x20\xe7\xcb\x65\x77\x3a\xdf"
+ "\xc8\x97\x67\x15\xc2\x2a\x27\xcc"
+ "\x18\x55\xa1\x24\x0b\x24\x24\xaf"
+ "\x5b\xec\x68\xb8\xc8\xf5\xba\x63"
+ "\xff\xed\x89\xce\xd5\x3d\x88\xf3"
+ "\x25\xef\x05\x7c\x3a\xef\xeb\xd8"
+ "\x7a\x32\x0d\xd1\x1e\x58\x59\x99"
+ "\x90\x25\xb5\x26\xb0\xe3\x2b\x6c"
+ "\x4c\xa9\x8b\x84\x4f\x5e\x01\x50"
+ "\x41\x30\x58\xc5\x62\x74\x52\x1d"
+ "\x45\x24\x6a\x42\x64\x4f\x97\x1c"
+ "\xa8\x66\xb5\x6d\x79\xd4\x0d\x48"
+ "\xc5\x5f\xf3\x90\x32\xdd\xdd\xe1"
+ "\xe4\xa9\x9f\xfc\xc3\x52\x5a\x46"
+ "\xe4\x81\x84\x95\x36\x59\x7a\x6b"
+ "\xaa\xb3\x60\xad\xce\x9f\x9f\x28"
+ "\xe0\x01\x75\x22\xc4\x4e\xa9\x62"
+ "\x5c\x62\x0d\x00\xcb\x13\xe8\x43"
+ "\x72\xd4\x2d\x53\x46\xb5\xd1\x16"
+ "\x22\x18\xdf\x34\x33\xf5\xd6\x1c"
+ "\xb8\x79\x78\x97\x94\xff\x72\x13"
+ "\x4c\x27\xfc\xcb\xbf\x01\x53\xa6"
+ "\xb4\x50\x6e\xde\xdf\xb5\x43\xa4"
+ "\x59\xdf\x52\xf9\x7c\xe0\x11\x6f"
+ "\x2d\x14\x8e\x24\x61\x2c\xe1\x17"
+ "\xcc\xce\x51\x0c\x19\x8a\x82\x30"
+ "\x94\xd5\x3d\x6a\x53\x06\x5e\xbd"
+ "\xb7\xeb\xfa\xfd\x27\x51\xde\x85"
+ "\x1e\x86\x53\x11\x53\x94\x00\xee"
+ "\x2b\x8c\x08\x2a\xbf\xdd\xae\x11"
+ "\xcb\x1e\xa2\x07\x9a\x80\xcf\x62"
+ "\x9b\x09\xdc\x95\x3c\x96\x8e\xb1"
+ "\x09\xbd\xe4\xeb\xdb\xca\x70\x7a"
+ "\x9e\xfa\x31\x18\x45\x3c\x21\x33"
+ "\xb0\xb3\x2b\xea\xf3\x71\x2d\xe1"
+ "\x03\xad\x1b\x48\xd4\x67\x27\xf0"
+ "\x62\xe4\x3d\xfb\x9b\x08\x76\xe7"
+ "\xdd\x2b\x01\x39\x04\x5a\x58\x7a"
+ "\xf7\x11\x90\xec\xbd\x51\x5c\x32"
+ "\x6b\xd7\x35\x39\x02\x6b\xf2\xa6"
+ "\xd0\x0d\x07\xe1\x06\xc4\x5b\x7d"
+ "\xe4\x6a\xd7\xee\x15\x1f\x83\xb4"
+ "\xa3\xa7\x5e\xc3\x90\xb7\xef\xd3"
+ "\xb7\x4f\xf8\x92\x4c\xb7\x3c\x29"
+ "\xcd\x7e\x2b\x5d\x43\xea\x42\xe7"
+ "\x74\x3f\x7d\x58\x88\x75\xde\x3e",
.ilen = 512,
- .result = { 0x05, 0x11, 0xb7, 0x18, 0xab, 0xc6, 0x2d, 0xac,
- 0x70, 0x5d, 0xf6, 0x22, 0x94, 0xcd, 0xe5, 0x6c,
- 0x17, 0x6b, 0xf6, 0x1c, 0xf0, 0xf3, 0x6e, 0xf8,
- 0x50, 0x38, 0x1f, 0x71, 0x49, 0xb6, 0x57, 0xd6,
- 0x8f, 0xcb, 0x8d, 0x6b, 0xe3, 0xa6, 0x29, 0x90,
- 0xfe, 0x2a, 0x62, 0x82, 0xae, 0x6d, 0x8b, 0xf6,
- 0xad, 0x1e, 0x9e, 0x20, 0x5f, 0x38, 0xbe, 0x04,
- 0xda, 0x10, 0x8e, 0xed, 0xa2, 0xa4, 0x87, 0xab,
- 0xda, 0x6b, 0xb4, 0x0c, 0x75, 0xba, 0xd3, 0x7c,
- 0xc9, 0xac, 0x42, 0x31, 0x95, 0x7c, 0xc9, 0x04,
- 0xeb, 0xd5, 0x6e, 0x32, 0x69, 0x8a, 0xdb, 0xa6,
- 0x15, 0xd7, 0x3f, 0x4f, 0x2f, 0x66, 0x69, 0x03,
- 0x9c, 0x1f, 0x54, 0x0f, 0xde, 0x1f, 0xf3, 0x65,
- 0x4c, 0x96, 0x12, 0xed, 0x7c, 0x92, 0x03, 0x01,
- 0x6f, 0xbc, 0x35, 0x93, 0xac, 0xf1, 0x27, 0xf1,
- 0xb4, 0x96, 0x82, 0x5a, 0x5f, 0xb0, 0xa0, 0x50,
- 0x89, 0xa4, 0x8e, 0x66, 0x44, 0x85, 0xcc, 0xfd,
- 0x33, 0x14, 0x70, 0xe3, 0x96, 0xb2, 0xc3, 0xd3,
- 0xbb, 0x54, 0x5a, 0x1a, 0xf9, 0x74, 0xa2, 0xc5,
- 0x2d, 0x64, 0x75, 0xdd, 0xb4, 0x54, 0xe6, 0x74,
- 0x8c, 0xd3, 0x9d, 0x9e, 0x86, 0xab, 0x51, 0x53,
- 0xb7, 0x93, 0x3e, 0x6f, 0xd0, 0x4e, 0x2c, 0x40,
- 0xf6, 0xa8, 0x2e, 0x3e, 0x9d, 0xf4, 0x66, 0xa5,
- 0x76, 0x12, 0x73, 0x44, 0x1a, 0x56, 0xd7, 0x72,
- 0x88, 0xcd, 0x21, 0x8c, 0x4c, 0x0f, 0xfe, 0xda,
- 0x95, 0xe0, 0x3a, 0xa6, 0xa5, 0x84, 0x46, 0xcd,
- 0xd5, 0x3e, 0x9d, 0x3a, 0xe2, 0x67, 0xe6, 0x60,
- 0x1a, 0xe2, 0x70, 0x85, 0x58, 0xc2, 0x1b, 0x09,
- 0xe1, 0xd7, 0x2c, 0xca, 0xad, 0xa8, 0x8f, 0xf9,
- 0xac, 0xb3, 0x0e, 0xdb, 0xca, 0x2e, 0xe2, 0xb8,
- 0x51, 0x71, 0xd9, 0x3c, 0x6c, 0xf1, 0x56, 0xf8,
- 0xea, 0x9c, 0xf1, 0xfb, 0x0c, 0xe6, 0xb7, 0x10,
- 0x1c, 0xf8, 0xa9, 0x7c, 0xe8, 0x53, 0x35, 0xc1,
- 0x90, 0x3e, 0x76, 0x4a, 0x74, 0xa4, 0x21, 0x2c,
- 0xf6, 0x2c, 0x4e, 0x0f, 0x94, 0x3a, 0x88, 0x2e,
- 0x41, 0x09, 0x6a, 0x33, 0x7d, 0xf6, 0xdd, 0x3f,
- 0x8d, 0x23, 0x31, 0x74, 0x84, 0xeb, 0x88, 0x6e,
- 0xcc, 0xb9, 0xbc, 0x22, 0x83, 0x19, 0x07, 0x22,
- 0xa5, 0x2d, 0xdf, 0xa5, 0xf3, 0x80, 0x85, 0x78,
- 0x84, 0x39, 0x6a, 0x6d, 0x6a, 0x99, 0x4f, 0xa5,
- 0x15, 0xfe, 0x46, 0xb0, 0xe4, 0x6c, 0xa5, 0x41,
- 0x3c, 0xce, 0x8f, 0x42, 0x60, 0x71, 0xa7, 0x75,
- 0x08, 0x40, 0x65, 0x8a, 0x82, 0xbf, 0xf5, 0x43,
- 0x71, 0x96, 0xa9, 0x4d, 0x44, 0x8a, 0x20, 0xbe,
- 0xfa, 0x4d, 0xbb, 0xc0, 0x7d, 0x31, 0x96, 0x65,
- 0xe7, 0x75, 0xe5, 0x3e, 0xfd, 0x92, 0x3b, 0xc9,
- 0x55, 0xbb, 0x16, 0x7e, 0xf7, 0xc2, 0x8c, 0xa4,
- 0x40, 0x1d, 0xe5, 0xef, 0x0e, 0xdf, 0xe4, 0x9a,
- 0x62, 0x73, 0x65, 0xfd, 0x46, 0x63, 0x25, 0x3d,
- 0x2b, 0xaf, 0xe5, 0x64, 0xfe, 0xa5, 0x5c, 0xcf,
- 0x24, 0xf3, 0xb4, 0xac, 0x64, 0xba, 0xdf, 0x4b,
- 0xc6, 0x96, 0x7d, 0x81, 0x2d, 0x8d, 0x97, 0xf7,
- 0xc5, 0x68, 0x77, 0x84, 0x32, 0x2b, 0xcc, 0x85,
- 0x74, 0x96, 0xf0, 0x12, 0x77, 0x61, 0xb9, 0xeb,
- 0x71, 0xaa, 0x82, 0xcb, 0x1c, 0xdb, 0x89, 0xc8,
- 0xc6, 0xb5, 0xe3, 0x5c, 0x7d, 0x39, 0x07, 0x24,
- 0xda, 0x39, 0x87, 0x45, 0xc0, 0x2b, 0xbb, 0x01,
- 0xac, 0xbc, 0x2a, 0x5c, 0x7f, 0xfc, 0xe8, 0xce,
- 0x6d, 0x9c, 0x6f, 0xed, 0xd3, 0xc1, 0xa1, 0xd6,
- 0xc5, 0x55, 0xa9, 0x66, 0x2f, 0xe1, 0xc8, 0x32,
- 0xa6, 0x5d, 0xa4, 0x3a, 0x98, 0x73, 0xe8, 0x45,
- 0xa4, 0xc7, 0xa8, 0xb4, 0xf6, 0x13, 0x03, 0xf6,
- 0xe9, 0x2e, 0xc4, 0x29, 0x0f, 0x84, 0xdb, 0xc4,
- 0x21, 0xc4, 0xc2, 0x75, 0x67, 0x89, 0x37, 0x0a },
+ .result = "\x05\x11\xb7\x18\xab\xc6\x2d\xac"
+ "\x70\x5d\xf6\x22\x94\xcd\xe5\x6c"
+ "\x17\x6b\xf6\x1c\xf0\xf3\x6e\xf8"
+ "\x50\x38\x1f\x71\x49\xb6\x57\xd6"
+ "\x8f\xcb\x8d\x6b\xe3\xa6\x29\x90"
+ "\xfe\x2a\x62\x82\xae\x6d\x8b\xf6"
+ "\xad\x1e\x9e\x20\x5f\x38\xbe\x04"
+ "\xda\x10\x8e\xed\xa2\xa4\x87\xab"
+ "\xda\x6b\xb4\x0c\x75\xba\xd3\x7c"
+ "\xc9\xac\x42\x31\x95\x7c\xc9\x04"
+ "\xeb\xd5\x6e\x32\x69\x8a\xdb\xa6"
+ "\x15\xd7\x3f\x4f\x2f\x66\x69\x03"
+ "\x9c\x1f\x54\x0f\xde\x1f\xf3\x65"
+ "\x4c\x96\x12\xed\x7c\x92\x03\x01"
+ "\x6f\xbc\x35\x93\xac\xf1\x27\xf1"
+ "\xb4\x96\x82\x5a\x5f\xb0\xa0\x50"
+ "\x89\xa4\x8e\x66\x44\x85\xcc\xfd"
+ "\x33\x14\x70\xe3\x96\xb2\xc3\xd3"
+ "\xbb\x54\x5a\x1a\xf9\x74\xa2\xc5"
+ "\x2d\x64\x75\xdd\xb4\x54\xe6\x74"
+ "\x8c\xd3\x9d\x9e\x86\xab\x51\x53"
+ "\xb7\x93\x3e\x6f\xd0\x4e\x2c\x40"
+ "\xf6\xa8\x2e\x3e\x9d\xf4\x66\xa5"
+ "\x76\x12\x73\x44\x1a\x56\xd7\x72"
+ "\x88\xcd\x21\x8c\x4c\x0f\xfe\xda"
+ "\x95\xe0\x3a\xa6\xa5\x84\x46\xcd"
+ "\xd5\x3e\x9d\x3a\xe2\x67\xe6\x60"
+ "\x1a\xe2\x70\x85\x58\xc2\x1b\x09"
+ "\xe1\xd7\x2c\xca\xad\xa8\x8f\xf9"
+ "\xac\xb3\x0e\xdb\xca\x2e\xe2\xb8"
+ "\x51\x71\xd9\x3c\x6c\xf1\x56\xf8"
+ "\xea\x9c\xf1\xfb\x0c\xe6\xb7\x10"
+ "\x1c\xf8\xa9\x7c\xe8\x53\x35\xc1"
+ "\x90\x3e\x76\x4a\x74\xa4\x21\x2c"
+ "\xf6\x2c\x4e\x0f\x94\x3a\x88\x2e"
+ "\x41\x09\x6a\x33\x7d\xf6\xdd\x3f"
+ "\x8d\x23\x31\x74\x84\xeb\x88\x6e"
+ "\xcc\xb9\xbc\x22\x83\x19\x07\x22"
+ "\xa5\x2d\xdf\xa5\xf3\x80\x85\x78"
+ "\x84\x39\x6a\x6d\x6a\x99\x4f\xa5"
+ "\x15\xfe\x46\xb0\xe4\x6c\xa5\x41"
+ "\x3c\xce\x8f\x42\x60\x71\xa7\x75"
+ "\x08\x40\x65\x8a\x82\xbf\xf5\x43"
+ "\x71\x96\xa9\x4d\x44\x8a\x20\xbe"
+ "\xfa\x4d\xbb\xc0\x7d\x31\x96\x65"
+ "\xe7\x75\xe5\x3e\xfd\x92\x3b\xc9"
+ "\x55\xbb\x16\x7e\xf7\xc2\x8c\xa4"
+ "\x40\x1d\xe5\xef\x0e\xdf\xe4\x9a"
+ "\x62\x73\x65\xfd\x46\x63\x25\x3d"
+ "\x2b\xaf\xe5\x64\xfe\xa5\x5c\xcf"
+ "\x24\xf3\xb4\xac\x64\xba\xdf\x4b"
+ "\xc6\x96\x7d\x81\x2d\x8d\x97\xf7"
+ "\xc5\x68\x77\x84\x32\x2b\xcc\x85"
+ "\x74\x96\xf0\x12\x77\x61\xb9\xeb"
+ "\x71\xaa\x82\xcb\x1c\xdb\x89\xc8"
+ "\xc6\xb5\xe3\x5c\x7d\x39\x07\x24"
+ "\xda\x39\x87\x45\xc0\x2b\xbb\x01"
+ "\xac\xbc\x2a\x5c\x7f\xfc\xe8\xce"
+ "\x6d\x9c\x6f\xed\xd3\xc1\xa1\xd6"
+ "\xc5\x55\xa9\x66\x2f\xe1\xc8\x32"
+ "\xa6\x5d\xa4\x3a\x98\x73\xe8\x45"
+ "\xa4\xc7\xa8\xb4\xf6\x13\x03\xf6"
+ "\xe9\x2e\xc4\x29\x0f\x84\xdb\xc4"
+ "\x21\xc4\xc2\x75\x67\x89\x37\x0a",
.rlen = 512,
}
};
static struct cipher_testvec aes_xts_enc_tv_template[] = {
/* http://grouper.ieee.org/groups/1619/email/pdf00086.pdf */
{ /* XTS-AES 1 */
- .key = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.ilen = 32,
- .result = { 0x91, 0x7c, 0xf6, 0x9e, 0xbd, 0x68, 0xb2, 0xec,
- 0x9b, 0x9f, 0xe9, 0xa3, 0xea, 0xdd, 0xa6, 0x92,
- 0xcd, 0x43, 0xd2, 0xf5, 0x95, 0x98, 0xed, 0x85,
- 0x8c, 0x02, 0xc2, 0x65, 0x2f, 0xbf, 0x92, 0x2e },
+ .result = "\x91\x7c\xf6\x9e\xbd\x68\xb2\xec"
+ "\x9b\x9f\xe9\xa3\xea\xdd\xa6\x92"
+ "\xcd\x43\xd2\xf5\x95\x98\xed\x85"
+ "\x8c\x02\xc2\x65\x2f\xbf\x92\x2e",
.rlen = 32,
}, { /* XTS-AES 2 */
- .key = { 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
- 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22 },
+ .key = "\x11\x11\x11\x11\x11\x11\x11\x11"
+ "\x11\x11\x11\x11\x11\x11\x11\x11"
+ "\x22\x22\x22\x22\x22\x22\x22\x22"
+ "\x22\x22\x22\x22\x22\x22\x22\x22",
.klen = 32,
- .iv = { 0x33, 0x33, 0x33, 0x33, 0x33, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44 },
+ .iv = "\x33\x33\x33\x33\x33\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44",
.ilen = 32,
- .result = { 0xc4, 0x54, 0x18, 0x5e, 0x6a, 0x16, 0x93, 0x6e,
- 0x39, 0x33, 0x40, 0x38, 0xac, 0xef, 0x83, 0x8b,
- 0xfb, 0x18, 0x6f, 0xff, 0x74, 0x80, 0xad, 0xc4,
- 0x28, 0x93, 0x82, 0xec, 0xd6, 0xd3, 0x94, 0xf0 },
+ .result = "\xc4\x54\x18\x5e\x6a\x16\x93\x6e"
+ "\x39\x33\x40\x38\xac\xef\x83\x8b"
+ "\xfb\x18\x6f\xff\x74\x80\xad\xc4"
+ "\x28\x93\x82\xec\xd6\xd3\x94\xf0",
.rlen = 32,
}, { /* XTS-AES 3 */
- .key = { 0xff, 0xfe, 0xfd, 0xfc, 0xfb, 0xfa, 0xf9, 0xf8,
- 0xf7, 0xf6, 0xf5, 0xf4, 0xf3, 0xf2, 0xf1, 0xf0,
- 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
- 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22 },
+ .key = "\xff\xfe\xfd\xfc\xfb\xfa\xf9\xf8"
+ "\xf7\xf6\xf5\xf4\xf3\xf2\xf1\xf0"
+ "\x22\x22\x22\x22\x22\x22\x22\x22"
+ "\x22\x22\x22\x22\x22\x22\x22\x22",
.klen = 32,
- .iv = { 0x33, 0x33, 0x33, 0x33, 0x33, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44 },
+ .iv = "\x33\x33\x33\x33\x33\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44",
.ilen = 32,
- .result = { 0xaf, 0x85, 0x33, 0x6b, 0x59, 0x7a, 0xfc, 0x1a,
- 0x90, 0x0b, 0x2e, 0xb2, 0x1e, 0xc9, 0x49, 0xd2,
- 0x92, 0xdf, 0x4c, 0x04, 0x7e, 0x0b, 0x21, 0x53,
- 0x21, 0x86, 0xa5, 0x97, 0x1a, 0x22, 0x7a, 0x89 },
+ .result = "\xaf\x85\x33\x6b\x59\x7a\xfc\x1a"
+ "\x90\x0b\x2e\xb2\x1e\xc9\x49\xd2"
+ "\x92\xdf\x4c\x04\x7e\x0b\x21\x53"
+ "\x21\x86\xa5\x97\x1a\x22\x7a\x89",
.rlen = 32,
}, { /* XTS-AES 4 */
- .key = { 0x27, 0x18, 0x28, 0x18, 0x28, 0x45, 0x90, 0x45,
- 0x23, 0x53, 0x60, 0x28, 0x74, 0x71, 0x35, 0x26,
- 0x31, 0x41, 0x59, 0x26, 0x53, 0x58, 0x97, 0x93,
- 0x23, 0x84, 0x62, 0x64, 0x33, 0x83, 0x27, 0x95 },
+ .key = "\x27\x18\x28\x18\x28\x45\x90\x45"
+ "\x23\x53\x60\x28\x74\x71\x35\x26"
+ "\x31\x41\x59\x26\x53\x58\x97\x93"
+ "\x23\x84\x62\x64\x33\x83\x27\x95",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
- 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
- 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
- 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
- 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
- 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
- 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
- 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
- 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
- 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
- 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
- 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
- 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
- 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
- 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
- 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
- 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
- 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
- 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
- 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
- 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
- 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
- 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
- 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
- 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
- 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
- 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
- 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
- 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
- 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
- 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
- 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
- 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
- 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
- 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
- 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
- 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
- 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
- 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
- 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
- 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
- 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
- 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
- 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
- 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
- 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
- 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
- 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
+ "\x20\x21\x22\x23\x24\x25\x26\x27"
+ "\x28\x29\x2a\x2b\x2c\x2d\x2e\x2f"
+ "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x3a\x3b\x3c\x3d\x3e\x3f"
+ "\x40\x41\x42\x43\x44\x45\x46\x47"
+ "\x48\x49\x4a\x4b\x4c\x4d\x4e\x4f"
+ "\x50\x51\x52\x53\x54\x55\x56\x57"
+ "\x58\x59\x5a\x5b\x5c\x5d\x5e\x5f"
+ "\x60\x61\x62\x63\x64\x65\x66\x67"
+ "\x68\x69\x6a\x6b\x6c\x6d\x6e\x6f"
+ "\x70\x71\x72\x73\x74\x75\x76\x77"
+ "\x78\x79\x7a\x7b\x7c\x7d\x7e\x7f"
+ "\x80\x81\x82\x83\x84\x85\x86\x87"
+ "\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f"
+ "\x90\x91\x92\x93\x94\x95\x96\x97"
+ "\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7"
+ "\xa8\xa9\xaa\xab\xac\xad\xae\xaf"
+ "\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7"
+ "\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf"
+ "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf"
+ "\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7"
+ "\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf"
+ "\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7"
+ "\xe8\xe9\xea\xeb\xec\xed\xee\xef"
+ "\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7"
+ "\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"
+ "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
+ "\x20\x21\x22\x23\x24\x25\x26\x27"
+ "\x28\x29\x2a\x2b\x2c\x2d\x2e\x2f"
+ "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x3a\x3b\x3c\x3d\x3e\x3f"
+ "\x40\x41\x42\x43\x44\x45\x46\x47"
+ "\x48\x49\x4a\x4b\x4c\x4d\x4e\x4f"
+ "\x50\x51\x52\x53\x54\x55\x56\x57"
+ "\x58\x59\x5a\x5b\x5c\x5d\x5e\x5f"
+ "\x60\x61\x62\x63\x64\x65\x66\x67"
+ "\x68\x69\x6a\x6b\x6c\x6d\x6e\x6f"
+ "\x70\x71\x72\x73\x74\x75\x76\x77"
+ "\x78\x79\x7a\x7b\x7c\x7d\x7e\x7f"
+ "\x80\x81\x82\x83\x84\x85\x86\x87"
+ "\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f"
+ "\x90\x91\x92\x93\x94\x95\x96\x97"
+ "\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7"
+ "\xa8\xa9\xaa\xab\xac\xad\xae\xaf"
+ "\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7"
+ "\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf"
+ "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf"
+ "\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7"
+ "\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf"
+ "\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7"
+ "\xe8\xe9\xea\xeb\xec\xed\xee\xef"
+ "\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7"
+ "\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff",
.ilen = 512,
- .result = { 0x27, 0xa7, 0x47, 0x9b, 0xef, 0xa1, 0xd4, 0x76,
- 0x48, 0x9f, 0x30, 0x8c, 0xd4, 0xcf, 0xa6, 0xe2,
- 0xa9, 0x6e, 0x4b, 0xbe, 0x32, 0x08, 0xff, 0x25,
- 0x28, 0x7d, 0xd3, 0x81, 0x96, 0x16, 0xe8, 0x9c,
- 0xc7, 0x8c, 0xf7, 0xf5, 0xe5, 0x43, 0x44, 0x5f,
- 0x83, 0x33, 0xd8, 0xfa, 0x7f, 0x56, 0x00, 0x00,
- 0x05, 0x27, 0x9f, 0xa5, 0xd8, 0xb5, 0xe4, 0xad,
- 0x40, 0xe7, 0x36, 0xdd, 0xb4, 0xd3, 0x54, 0x12,
- 0x32, 0x80, 0x63, 0xfd, 0x2a, 0xab, 0x53, 0xe5,
- 0xea, 0x1e, 0x0a, 0x9f, 0x33, 0x25, 0x00, 0xa5,
- 0xdf, 0x94, 0x87, 0xd0, 0x7a, 0x5c, 0x92, 0xcc,
- 0x51, 0x2c, 0x88, 0x66, 0xc7, 0xe8, 0x60, 0xce,
- 0x93, 0xfd, 0xf1, 0x66, 0xa2, 0x49, 0x12, 0xb4,
- 0x22, 0x97, 0x61, 0x46, 0xae, 0x20, 0xce, 0x84,
- 0x6b, 0xb7, 0xdc, 0x9b, 0xa9, 0x4a, 0x76, 0x7a,
- 0xae, 0xf2, 0x0c, 0x0d, 0x61, 0xad, 0x02, 0x65,
- 0x5e, 0xa9, 0x2d, 0xc4, 0xc4, 0xe4, 0x1a, 0x89,
- 0x52, 0xc6, 0x51, 0xd3, 0x31, 0x74, 0xbe, 0x51,
- 0xa1, 0x0c, 0x42, 0x11, 0x10, 0xe6, 0xd8, 0x15,
- 0x88, 0xed, 0xe8, 0x21, 0x03, 0xa2, 0x52, 0xd8,
- 0xa7, 0x50, 0xe8, 0x76, 0x8d, 0xef, 0xff, 0xed,
- 0x91, 0x22, 0x81, 0x0a, 0xae, 0xb9, 0x9f, 0x91,
- 0x72, 0xaf, 0x82, 0xb6, 0x04, 0xdc, 0x4b, 0x8e,
- 0x51, 0xbc, 0xb0, 0x82, 0x35, 0xa6, 0xf4, 0x34,
- 0x13, 0x32, 0xe4, 0xca, 0x60, 0x48, 0x2a, 0x4b,
- 0xa1, 0xa0, 0x3b, 0x3e, 0x65, 0x00, 0x8f, 0xc5,
- 0xda, 0x76, 0xb7, 0x0b, 0xf1, 0x69, 0x0d, 0xb4,
- 0xea, 0xe2, 0x9c, 0x5f, 0x1b, 0xad, 0xd0, 0x3c,
- 0x5c, 0xcf, 0x2a, 0x55, 0xd7, 0x05, 0xdd, 0xcd,
- 0x86, 0xd4, 0x49, 0x51, 0x1c, 0xeb, 0x7e, 0xc3,
- 0x0b, 0xf1, 0x2b, 0x1f, 0xa3, 0x5b, 0x91, 0x3f,
- 0x9f, 0x74, 0x7a, 0x8a, 0xfd, 0x1b, 0x13, 0x0e,
- 0x94, 0xbf, 0xf9, 0x4e, 0xff, 0xd0, 0x1a, 0x91,
- 0x73, 0x5c, 0xa1, 0x72, 0x6a, 0xcd, 0x0b, 0x19,
- 0x7c, 0x4e, 0x5b, 0x03, 0x39, 0x36, 0x97, 0xe1,
- 0x26, 0x82, 0x6f, 0xb6, 0xbb, 0xde, 0x8e, 0xcc,
- 0x1e, 0x08, 0x29, 0x85, 0x16, 0xe2, 0xc9, 0xed,
- 0x03, 0xff, 0x3c, 0x1b, 0x78, 0x60, 0xf6, 0xde,
- 0x76, 0xd4, 0xce, 0xcd, 0x94, 0xc8, 0x11, 0x98,
- 0x55, 0xef, 0x52, 0x97, 0xca, 0x67, 0xe9, 0xf3,
- 0xe7, 0xff, 0x72, 0xb1, 0xe9, 0x97, 0x85, 0xca,
- 0x0a, 0x7e, 0x77, 0x20, 0xc5, 0xb3, 0x6d, 0xc6,
- 0xd7, 0x2c, 0xac, 0x95, 0x74, 0xc8, 0xcb, 0xbc,
- 0x2f, 0x80, 0x1e, 0x23, 0xe5, 0x6f, 0xd3, 0x44,
- 0xb0, 0x7f, 0x22, 0x15, 0x4b, 0xeb, 0xa0, 0xf0,
- 0x8c, 0xe8, 0x89, 0x1e, 0x64, 0x3e, 0xd9, 0x95,
- 0xc9, 0x4d, 0x9a, 0x69, 0xc9, 0xf1, 0xb5, 0xf4,
- 0x99, 0x02, 0x7a, 0x78, 0x57, 0x2a, 0xee, 0xbd,
- 0x74, 0xd2, 0x0c, 0xc3, 0x98, 0x81, 0xc2, 0x13,
- 0xee, 0x77, 0x0b, 0x10, 0x10, 0xe4, 0xbe, 0xa7,
- 0x18, 0x84, 0x69, 0x77, 0xae, 0x11, 0x9f, 0x7a,
- 0x02, 0x3a, 0xb5, 0x8c, 0xca, 0x0a, 0xd7, 0x52,
- 0xaf, 0xe6, 0x56, 0xbb, 0x3c, 0x17, 0x25, 0x6a,
- 0x9f, 0x6e, 0x9b, 0xf1, 0x9f, 0xdd, 0x5a, 0x38,
- 0xfc, 0x82, 0xbb, 0xe8, 0x72, 0xc5, 0x53, 0x9e,
- 0xdb, 0x60, 0x9e, 0xf4, 0xf7, 0x9c, 0x20, 0x3e,
- 0xbb, 0x14, 0x0f, 0x2e, 0x58, 0x3c, 0xb2, 0xad,
- 0x15, 0xb4, 0xaa, 0x5b, 0x65, 0x50, 0x16, 0xa8,
- 0x44, 0x92, 0x77, 0xdb, 0xd4, 0x77, 0xef, 0x2c,
- 0x8d, 0x6c, 0x01, 0x7d, 0xb7, 0x38, 0xb1, 0x8d,
- 0xeb, 0x4a, 0x42, 0x7d, 0x19, 0x23, 0xce, 0x3f,
- 0xf2, 0x62, 0x73, 0x57, 0x79, 0xa4, 0x18, 0xf2,
- 0x0a, 0x28, 0x2d, 0xf9, 0x20, 0x14, 0x7b, 0xea,
- 0xbe, 0x42, 0x1e, 0xe5, 0x31, 0x9d, 0x05, 0x68 },
+ .result = "\x27\xa7\x47\x9b\xef\xa1\xd4\x76"
+ "\x48\x9f\x30\x8c\xd4\xcf\xa6\xe2"
+ "\xa9\x6e\x4b\xbe\x32\x08\xff\x25"
+ "\x28\x7d\xd3\x81\x96\x16\xe8\x9c"
+ "\xc7\x8c\xf7\xf5\xe5\x43\x44\x5f"
+ "\x83\x33\xd8\xfa\x7f\x56\x00\x00"
+ "\x05\x27\x9f\xa5\xd8\xb5\xe4\xad"
+ "\x40\xe7\x36\xdd\xb4\xd3\x54\x12"
+ "\x32\x80\x63\xfd\x2a\xab\x53\xe5"
+ "\xea\x1e\x0a\x9f\x33\x25\x00\xa5"
+ "\xdf\x94\x87\xd0\x7a\x5c\x92\xcc"
+ "\x51\x2c\x88\x66\xc7\xe8\x60\xce"
+ "\x93\xfd\xf1\x66\xa2\x49\x12\xb4"
+ "\x22\x97\x61\x46\xae\x20\xce\x84"
+ "\x6b\xb7\xdc\x9b\xa9\x4a\x76\x7a"
+ "\xae\xf2\x0c\x0d\x61\xad\x02\x65"
+ "\x5e\xa9\x2d\xc4\xc4\xe4\x1a\x89"
+ "\x52\xc6\x51\xd3\x31\x74\xbe\x51"
+ "\xa1\x0c\x42\x11\x10\xe6\xd8\x15"
+ "\x88\xed\xe8\x21\x03\xa2\x52\xd8"
+ "\xa7\x50\xe8\x76\x8d\xef\xff\xed"
+ "\x91\x22\x81\x0a\xae\xb9\x9f\x91"
+ "\x72\xaf\x82\xb6\x04\xdc\x4b\x8e"
+ "\x51\xbc\xb0\x82\x35\xa6\xf4\x34"
+ "\x13\x32\xe4\xca\x60\x48\x2a\x4b"
+ "\xa1\xa0\x3b\x3e\x65\x00\x8f\xc5"
+ "\xda\x76\xb7\x0b\xf1\x69\x0d\xb4"
+ "\xea\xe2\x9c\x5f\x1b\xad\xd0\x3c"
+ "\x5c\xcf\x2a\x55\xd7\x05\xdd\xcd"
+ "\x86\xd4\x49\x51\x1c\xeb\x7e\xc3"
+ "\x0b\xf1\x2b\x1f\xa3\x5b\x91\x3f"
+ "\x9f\x74\x7a\x8a\xfd\x1b\x13\x0e"
+ "\x94\xbf\xf9\x4e\xff\xd0\x1a\x91"
+ "\x73\x5c\xa1\x72\x6a\xcd\x0b\x19"
+ "\x7c\x4e\x5b\x03\x39\x36\x97\xe1"
+ "\x26\x82\x6f\xb6\xbb\xde\x8e\xcc"
+ "\x1e\x08\x29\x85\x16\xe2\xc9\xed"
+ "\x03\xff\x3c\x1b\x78\x60\xf6\xde"
+ "\x76\xd4\xce\xcd\x94\xc8\x11\x98"
+ "\x55\xef\x52\x97\xca\x67\xe9\xf3"
+ "\xe7\xff\x72\xb1\xe9\x97\x85\xca"
+ "\x0a\x7e\x77\x20\xc5\xb3\x6d\xc6"
+ "\xd7\x2c\xac\x95\x74\xc8\xcb\xbc"
+ "\x2f\x80\x1e\x23\xe5\x6f\xd3\x44"
+ "\xb0\x7f\x22\x15\x4b\xeb\xa0\xf0"
+ "\x8c\xe8\x89\x1e\x64\x3e\xd9\x95"
+ "\xc9\x4d\x9a\x69\xc9\xf1\xb5\xf4"
+ "\x99\x02\x7a\x78\x57\x2a\xee\xbd"
+ "\x74\xd2\x0c\xc3\x98\x81\xc2\x13"
+ "\xee\x77\x0b\x10\x10\xe4\xbe\xa7"
+ "\x18\x84\x69\x77\xae\x11\x9f\x7a"
+ "\x02\x3a\xb5\x8c\xca\x0a\xd7\x52"
+ "\xaf\xe6\x56\xbb\x3c\x17\x25\x6a"
+ "\x9f\x6e\x9b\xf1\x9f\xdd\x5a\x38"
+ "\xfc\x82\xbb\xe8\x72\xc5\x53\x9e"
+ "\xdb\x60\x9e\xf4\xf7\x9c\x20\x3e"
+ "\xbb\x14\x0f\x2e\x58\x3c\xb2\xad"
+ "\x15\xb4\xaa\x5b\x65\x50\x16\xa8"
+ "\x44\x92\x77\xdb\xd4\x77\xef\x2c"
+ "\x8d\x6c\x01\x7d\xb7\x38\xb1\x8d"
+ "\xeb\x4a\x42\x7d\x19\x23\xce\x3f"
+ "\xf2\x62\x73\x57\x79\xa4\x18\xf2"
+ "\x0a\x28\x2d\xf9\x20\x14\x7b\xea"
+ "\xbe\x42\x1e\xe5\x31\x9d\x05\x68",
.rlen = 512,
}
};
static struct cipher_testvec aes_xts_dec_tv_template[] = {
/* http://grouper.ieee.org/groups/1619/email/pdf00086.pdf */
{ /* XTS-AES 1 */
- .key = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x91, 0x7c, 0xf6, 0x9e, 0xbd, 0x68, 0xb2, 0xec,
- 0x9b, 0x9f, 0xe9, 0xa3, 0xea, 0xdd, 0xa6, 0x92,
- 0xcd, 0x43, 0xd2, 0xf5, 0x95, 0x98, 0xed, 0x85,
- 0x8c, 0x02, 0xc2, 0x65, 0x2f, 0xbf, 0x92, 0x2e },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x91\x7c\xf6\x9e\xbd\x68\xb2\xec"
+ "\x9b\x9f\xe9\xa3\xea\xdd\xa6\x92"
+ "\xcd\x43\xd2\xf5\x95\x98\xed\x85"
+ "\x8c\x02\xc2\x65\x2f\xbf\x92\x2e",
.ilen = 32,
- .result = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .result = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.rlen = 32,
}, { /* XTS-AES 2 */
- .key = { 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
- 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22 },
+ .key = "\x11\x11\x11\x11\x11\x11\x11\x11"
+ "\x11\x11\x11\x11\x11\x11\x11\x11"
+ "\x22\x22\x22\x22\x22\x22\x22\x22"
+ "\x22\x22\x22\x22\x22\x22\x22\x22",
.klen = 32,
- .iv = { 0x33, 0x33, 0x33, 0x33, 0x33, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0xc4, 0x54, 0x18, 0x5e, 0x6a, 0x16, 0x93, 0x6e,
- 0x39, 0x33, 0x40, 0x38, 0xac, 0xef, 0x83, 0x8b,
- 0xfb, 0x18, 0x6f, 0xff, 0x74, 0x80, 0xad, 0xc4,
- 0x28, 0x93, 0x82, 0xec, 0xd6, 0xd3, 0x94, 0xf0 },
+ .iv = "\x33\x33\x33\x33\x33\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\xc4\x54\x18\x5e\x6a\x16\x93\x6e"
+ "\x39\x33\x40\x38\xac\xef\x83\x8b"
+ "\xfb\x18\x6f\xff\x74\x80\xad\xc4"
+ "\x28\x93\x82\xec\xd6\xd3\x94\xf0",
.ilen = 32,
- .result = { 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44 },
+ .result = "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44",
.rlen = 32,
}, { /* XTS-AES 3 */
- .key = { 0xff, 0xfe, 0xfd, 0xfc, 0xfb, 0xfa, 0xf9, 0xf8,
- 0xf7, 0xf6, 0xf5, 0xf4, 0xf3, 0xf2, 0xf1, 0xf0,
- 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
- 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22 },
+ .key = "\xff\xfe\xfd\xfc\xfb\xfa\xf9\xf8"
+ "\xf7\xf6\xf5\xf4\xf3\xf2\xf1\xf0"
+ "\x22\x22\x22\x22\x22\x22\x22\x22"
+ "\x22\x22\x22\x22\x22\x22\x22\x22",
.klen = 32,
- .iv = { 0x33, 0x33, 0x33, 0x33, 0x33, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0xaf, 0x85, 0x33, 0x6b, 0x59, 0x7a, 0xfc, 0x1a,
- 0x90, 0x0b, 0x2e, 0xb2, 0x1e, 0xc9, 0x49, 0xd2,
- 0x92, 0xdf, 0x4c, 0x04, 0x7e, 0x0b, 0x21, 0x53,
- 0x21, 0x86, 0xa5, 0x97, 0x1a, 0x22, 0x7a, 0x89 },
+ .iv = "\x33\x33\x33\x33\x33\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\xaf\x85\x33\x6b\x59\x7a\xfc\x1a"
+ "\x90\x0b\x2e\xb2\x1e\xc9\x49\xd2"
+ "\x92\xdf\x4c\x04\x7e\x0b\x21\x53"
+ "\x21\x86\xa5\x97\x1a\x22\x7a\x89",
.ilen = 32,
- .result = { 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
- 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44 },
+ .result = "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44"
+ "\x44\x44\x44\x44\x44\x44\x44\x44",
.rlen = 32,
}, { /* XTS-AES 4 */
- .key = { 0x27, 0x18, 0x28, 0x18, 0x28, 0x45, 0x90, 0x45,
- 0x23, 0x53, 0x60, 0x28, 0x74, 0x71, 0x35, 0x26,
- 0x31, 0x41, 0x59, 0x26, 0x53, 0x58, 0x97, 0x93,
- 0x23, 0x84, 0x62, 0x64, 0x33, 0x83, 0x27, 0x95 },
+ .key = "\x27\x18\x28\x18\x28\x45\x90\x45"
+ "\x23\x53\x60\x28\x74\x71\x35\x26"
+ "\x31\x41\x59\x26\x53\x58\x97\x93"
+ "\x23\x84\x62\x64\x33\x83\x27\x95",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x27, 0xa7, 0x47, 0x9b, 0xef, 0xa1, 0xd4, 0x76,
- 0x48, 0x9f, 0x30, 0x8c, 0xd4, 0xcf, 0xa6, 0xe2,
- 0xa9, 0x6e, 0x4b, 0xbe, 0x32, 0x08, 0xff, 0x25,
- 0x28, 0x7d, 0xd3, 0x81, 0x96, 0x16, 0xe8, 0x9c,
- 0xc7, 0x8c, 0xf7, 0xf5, 0xe5, 0x43, 0x44, 0x5f,
- 0x83, 0x33, 0xd8, 0xfa, 0x7f, 0x56, 0x00, 0x00,
- 0x05, 0x27, 0x9f, 0xa5, 0xd8, 0xb5, 0xe4, 0xad,
- 0x40, 0xe7, 0x36, 0xdd, 0xb4, 0xd3, 0x54, 0x12,
- 0x32, 0x80, 0x63, 0xfd, 0x2a, 0xab, 0x53, 0xe5,
- 0xea, 0x1e, 0x0a, 0x9f, 0x33, 0x25, 0x00, 0xa5,
- 0xdf, 0x94, 0x87, 0xd0, 0x7a, 0x5c, 0x92, 0xcc,
- 0x51, 0x2c, 0x88, 0x66, 0xc7, 0xe8, 0x60, 0xce,
- 0x93, 0xfd, 0xf1, 0x66, 0xa2, 0x49, 0x12, 0xb4,
- 0x22, 0x97, 0x61, 0x46, 0xae, 0x20, 0xce, 0x84,
- 0x6b, 0xb7, 0xdc, 0x9b, 0xa9, 0x4a, 0x76, 0x7a,
- 0xae, 0xf2, 0x0c, 0x0d, 0x61, 0xad, 0x02, 0x65,
- 0x5e, 0xa9, 0x2d, 0xc4, 0xc4, 0xe4, 0x1a, 0x89,
- 0x52, 0xc6, 0x51, 0xd3, 0x31, 0x74, 0xbe, 0x51,
- 0xa1, 0x0c, 0x42, 0x11, 0x10, 0xe6, 0xd8, 0x15,
- 0x88, 0xed, 0xe8, 0x21, 0x03, 0xa2, 0x52, 0xd8,
- 0xa7, 0x50, 0xe8, 0x76, 0x8d, 0xef, 0xff, 0xed,
- 0x91, 0x22, 0x81, 0x0a, 0xae, 0xb9, 0x9f, 0x91,
- 0x72, 0xaf, 0x82, 0xb6, 0x04, 0xdc, 0x4b, 0x8e,
- 0x51, 0xbc, 0xb0, 0x82, 0x35, 0xa6, 0xf4, 0x34,
- 0x13, 0x32, 0xe4, 0xca, 0x60, 0x48, 0x2a, 0x4b,
- 0xa1, 0xa0, 0x3b, 0x3e, 0x65, 0x00, 0x8f, 0xc5,
- 0xda, 0x76, 0xb7, 0x0b, 0xf1, 0x69, 0x0d, 0xb4,
- 0xea, 0xe2, 0x9c, 0x5f, 0x1b, 0xad, 0xd0, 0x3c,
- 0x5c, 0xcf, 0x2a, 0x55, 0xd7, 0x05, 0xdd, 0xcd,
- 0x86, 0xd4, 0x49, 0x51, 0x1c, 0xeb, 0x7e, 0xc3,
- 0x0b, 0xf1, 0x2b, 0x1f, 0xa3, 0x5b, 0x91, 0x3f,
- 0x9f, 0x74, 0x7a, 0x8a, 0xfd, 0x1b, 0x13, 0x0e,
- 0x94, 0xbf, 0xf9, 0x4e, 0xff, 0xd0, 0x1a, 0x91,
- 0x73, 0x5c, 0xa1, 0x72, 0x6a, 0xcd, 0x0b, 0x19,
- 0x7c, 0x4e, 0x5b, 0x03, 0x39, 0x36, 0x97, 0xe1,
- 0x26, 0x82, 0x6f, 0xb6, 0xbb, 0xde, 0x8e, 0xcc,
- 0x1e, 0x08, 0x29, 0x85, 0x16, 0xe2, 0xc9, 0xed,
- 0x03, 0xff, 0x3c, 0x1b, 0x78, 0x60, 0xf6, 0xde,
- 0x76, 0xd4, 0xce, 0xcd, 0x94, 0xc8, 0x11, 0x98,
- 0x55, 0xef, 0x52, 0x97, 0xca, 0x67, 0xe9, 0xf3,
- 0xe7, 0xff, 0x72, 0xb1, 0xe9, 0x97, 0x85, 0xca,
- 0x0a, 0x7e, 0x77, 0x20, 0xc5, 0xb3, 0x6d, 0xc6,
- 0xd7, 0x2c, 0xac, 0x95, 0x74, 0xc8, 0xcb, 0xbc,
- 0x2f, 0x80, 0x1e, 0x23, 0xe5, 0x6f, 0xd3, 0x44,
- 0xb0, 0x7f, 0x22, 0x15, 0x4b, 0xeb, 0xa0, 0xf0,
- 0x8c, 0xe8, 0x89, 0x1e, 0x64, 0x3e, 0xd9, 0x95,
- 0xc9, 0x4d, 0x9a, 0x69, 0xc9, 0xf1, 0xb5, 0xf4,
- 0x99, 0x02, 0x7a, 0x78, 0x57, 0x2a, 0xee, 0xbd,
- 0x74, 0xd2, 0x0c, 0xc3, 0x98, 0x81, 0xc2, 0x13,
- 0xee, 0x77, 0x0b, 0x10, 0x10, 0xe4, 0xbe, 0xa7,
- 0x18, 0x84, 0x69, 0x77, 0xae, 0x11, 0x9f, 0x7a,
- 0x02, 0x3a, 0xb5, 0x8c, 0xca, 0x0a, 0xd7, 0x52,
- 0xaf, 0xe6, 0x56, 0xbb, 0x3c, 0x17, 0x25, 0x6a,
- 0x9f, 0x6e, 0x9b, 0xf1, 0x9f, 0xdd, 0x5a, 0x38,
- 0xfc, 0x82, 0xbb, 0xe8, 0x72, 0xc5, 0x53, 0x9e,
- 0xdb, 0x60, 0x9e, 0xf4, 0xf7, 0x9c, 0x20, 0x3e,
- 0xbb, 0x14, 0x0f, 0x2e, 0x58, 0x3c, 0xb2, 0xad,
- 0x15, 0xb4, 0xaa, 0x5b, 0x65, 0x50, 0x16, 0xa8,
- 0x44, 0x92, 0x77, 0xdb, 0xd4, 0x77, 0xef, 0x2c,
- 0x8d, 0x6c, 0x01, 0x7d, 0xb7, 0x38, 0xb1, 0x8d,
- 0xeb, 0x4a, 0x42, 0x7d, 0x19, 0x23, 0xce, 0x3f,
- 0xf2, 0x62, 0x73, 0x57, 0x79, 0xa4, 0x18, 0xf2,
- 0x0a, 0x28, 0x2d, 0xf9, 0x20, 0x14, 0x7b, 0xea,
- 0xbe, 0x42, 0x1e, 0xe5, 0x31, 0x9d, 0x05, 0x68 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x27\xa7\x47\x9b\xef\xa1\xd4\x76"
+ "\x48\x9f\x30\x8c\xd4\xcf\xa6\xe2"
+ "\xa9\x6e\x4b\xbe\x32\x08\xff\x25"
+ "\x28\x7d\xd3\x81\x96\x16\xe8\x9c"
+ "\xc7\x8c\xf7\xf5\xe5\x43\x44\x5f"
+ "\x83\x33\xd8\xfa\x7f\x56\x00\x00"
+ "\x05\x27\x9f\xa5\xd8\xb5\xe4\xad"
+ "\x40\xe7\x36\xdd\xb4\xd3\x54\x12"
+ "\x32\x80\x63\xfd\x2a\xab\x53\xe5"
+ "\xea\x1e\x0a\x9f\x33\x25\x00\xa5"
+ "\xdf\x94\x87\xd0\x7a\x5c\x92\xcc"
+ "\x51\x2c\x88\x66\xc7\xe8\x60\xce"
+ "\x93\xfd\xf1\x66\xa2\x49\x12\xb4"
+ "\x22\x97\x61\x46\xae\x20\xce\x84"
+ "\x6b\xb7\xdc\x9b\xa9\x4a\x76\x7a"
+ "\xae\xf2\x0c\x0d\x61\xad\x02\x65"
+ "\x5e\xa9\x2d\xc4\xc4\xe4\x1a\x89"
+ "\x52\xc6\x51\xd3\x31\x74\xbe\x51"
+ "\xa1\x0c\x42\x11\x10\xe6\xd8\x15"
+ "\x88\xed\xe8\x21\x03\xa2\x52\xd8"
+ "\xa7\x50\xe8\x76\x8d\xef\xff\xed"
+ "\x91\x22\x81\x0a\xae\xb9\x9f\x91"
+ "\x72\xaf\x82\xb6\x04\xdc\x4b\x8e"
+ "\x51\xbc\xb0\x82\x35\xa6\xf4\x34"
+ "\x13\x32\xe4\xca\x60\x48\x2a\x4b"
+ "\xa1\xa0\x3b\x3e\x65\x00\x8f\xc5"
+ "\xda\x76\xb7\x0b\xf1\x69\x0d\xb4"
+ "\xea\xe2\x9c\x5f\x1b\xad\xd0\x3c"
+ "\x5c\xcf\x2a\x55\xd7\x05\xdd\xcd"
+ "\x86\xd4\x49\x51\x1c\xeb\x7e\xc3"
+ "\x0b\xf1\x2b\x1f\xa3\x5b\x91\x3f"
+ "\x9f\x74\x7a\x8a\xfd\x1b\x13\x0e"
+ "\x94\xbf\xf9\x4e\xff\xd0\x1a\x91"
+ "\x73\x5c\xa1\x72\x6a\xcd\x0b\x19"
+ "\x7c\x4e\x5b\x03\x39\x36\x97\xe1"
+ "\x26\x82\x6f\xb6\xbb\xde\x8e\xcc"
+ "\x1e\x08\x29\x85\x16\xe2\xc9\xed"
+ "\x03\xff\x3c\x1b\x78\x60\xf6\xde"
+ "\x76\xd4\xce\xcd\x94\xc8\x11\x98"
+ "\x55\xef\x52\x97\xca\x67\xe9\xf3"
+ "\xe7\xff\x72\xb1\xe9\x97\x85\xca"
+ "\x0a\x7e\x77\x20\xc5\xb3\x6d\xc6"
+ "\xd7\x2c\xac\x95\x74\xc8\xcb\xbc"
+ "\x2f\x80\x1e\x23\xe5\x6f\xd3\x44"
+ "\xb0\x7f\x22\x15\x4b\xeb\xa0\xf0"
+ "\x8c\xe8\x89\x1e\x64\x3e\xd9\x95"
+ "\xc9\x4d\x9a\x69\xc9\xf1\xb5\xf4"
+ "\x99\x02\x7a\x78\x57\x2a\xee\xbd"
+ "\x74\xd2\x0c\xc3\x98\x81\xc2\x13"
+ "\xee\x77\x0b\x10\x10\xe4\xbe\xa7"
+ "\x18\x84\x69\x77\xae\x11\x9f\x7a"
+ "\x02\x3a\xb5\x8c\xca\x0a\xd7\x52"
+ "\xaf\xe6\x56\xbb\x3c\x17\x25\x6a"
+ "\x9f\x6e\x9b\xf1\x9f\xdd\x5a\x38"
+ "\xfc\x82\xbb\xe8\x72\xc5\x53\x9e"
+ "\xdb\x60\x9e\xf4\xf7\x9c\x20\x3e"
+ "\xbb\x14\x0f\x2e\x58\x3c\xb2\xad"
+ "\x15\xb4\xaa\x5b\x65\x50\x16\xa8"
+ "\x44\x92\x77\xdb\xd4\x77\xef\x2c"
+ "\x8d\x6c\x01\x7d\xb7\x38\xb1\x8d"
+ "\xeb\x4a\x42\x7d\x19\x23\xce\x3f"
+ "\xf2\x62\x73\x57\x79\xa4\x18\xf2"
+ "\x0a\x28\x2d\xf9\x20\x14\x7b\xea"
+ "\xbe\x42\x1e\xe5\x31\x9d\x05\x68",
.ilen = 512,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
- 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
- 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
- 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
- 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
- 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
- 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
- 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
- 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
- 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
- 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
- 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
- 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
- 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
- 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
- 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
- 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
- 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
- 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
- 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
- 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
- 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
- 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
- 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
- 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
- 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
- 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
- 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
- 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
- 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
- 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
- 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
- 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
- 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
- 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
- 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
- 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
- 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
- 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
- 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
- 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
- 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
- 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
- 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
- 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
- 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
- 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
- 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
+ "\x20\x21\x22\x23\x24\x25\x26\x27"
+ "\x28\x29\x2a\x2b\x2c\x2d\x2e\x2f"
+ "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x3a\x3b\x3c\x3d\x3e\x3f"
+ "\x40\x41\x42\x43\x44\x45\x46\x47"
+ "\x48\x49\x4a\x4b\x4c\x4d\x4e\x4f"
+ "\x50\x51\x52\x53\x54\x55\x56\x57"
+ "\x58\x59\x5a\x5b\x5c\x5d\x5e\x5f"
+ "\x60\x61\x62\x63\x64\x65\x66\x67"
+ "\x68\x69\x6a\x6b\x6c\x6d\x6e\x6f"
+ "\x70\x71\x72\x73\x74\x75\x76\x77"
+ "\x78\x79\x7a\x7b\x7c\x7d\x7e\x7f"
+ "\x80\x81\x82\x83\x84\x85\x86\x87"
+ "\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f"
+ "\x90\x91\x92\x93\x94\x95\x96\x97"
+ "\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7"
+ "\xa8\xa9\xaa\xab\xac\xad\xae\xaf"
+ "\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7"
+ "\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf"
+ "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf"
+ "\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7"
+ "\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf"
+ "\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7"
+ "\xe8\xe9\xea\xeb\xec\xed\xee\xef"
+ "\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7"
+ "\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"
+ "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
+ "\x20\x21\x22\x23\x24\x25\x26\x27"
+ "\x28\x29\x2a\x2b\x2c\x2d\x2e\x2f"
+ "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x3a\x3b\x3c\x3d\x3e\x3f"
+ "\x40\x41\x42\x43\x44\x45\x46\x47"
+ "\x48\x49\x4a\x4b\x4c\x4d\x4e\x4f"
+ "\x50\x51\x52\x53\x54\x55\x56\x57"
+ "\x58\x59\x5a\x5b\x5c\x5d\x5e\x5f"
+ "\x60\x61\x62\x63\x64\x65\x66\x67"
+ "\x68\x69\x6a\x6b\x6c\x6d\x6e\x6f"
+ "\x70\x71\x72\x73\x74\x75\x76\x77"
+ "\x78\x79\x7a\x7b\x7c\x7d\x7e\x7f"
+ "\x80\x81\x82\x83\x84\x85\x86\x87"
+ "\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f"
+ "\x90\x91\x92\x93\x94\x95\x96\x97"
+ "\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7"
+ "\xa8\xa9\xaa\xab\xac\xad\xae\xaf"
+ "\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7"
+ "\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf"
+ "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf"
+ "\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7"
+ "\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf"
+ "\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7"
+ "\xe8\xe9\xea\xeb\xec\xed\xee\xef"
+ "\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7"
+ "\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff",
.rlen = 512,
}
};
static struct cipher_testvec aes_ctr_enc_tv_template[] = {
{ /* From RFC 3686 */
- .key = { 0xae, 0x68, 0x52, 0xf8, 0x12, 0x10, 0x67, 0xcc,
- 0x4b, 0xf7, 0xa5, 0x76, 0x55, 0x77, 0xf3, 0x9e,
- 0x00, 0x00, 0x00, 0x30 },
+ .key = "\xae\x68\x52\xf8\x12\x10\x67\xcc"
+ "\x4b\xf7\xa5\x76\x55\x77\xf3\x9e"
+ "\x00\x00\x00\x30",
.klen = 20,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { "Single block msg" },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "Single block msg",
.ilen = 16,
- .result = { 0xe4, 0x09, 0x5d, 0x4f, 0xb7, 0xa7, 0xb3, 0x79,
- 0x2d, 0x61, 0x75, 0xa3, 0x26, 0x13, 0x11, 0xb8 },
+ .result = "\xe4\x09\x5d\x4f\xb7\xa7\xb3\x79"
+ "\x2d\x61\x75\xa3\x26\x13\x11\xb8",
.rlen = 16,
}, {
- .key = { 0x7e, 0x24, 0x06, 0x78, 0x17, 0xfa, 0xe0, 0xd7,
- 0x43, 0xd6, 0xce, 0x1f, 0x32, 0x53, 0x91, 0x63,
- 0x00, 0x6c, 0xb6, 0xdb },
+ .key = "\x7e\x24\x06\x78\x17\xfa\xe0\xd7"
+ "\x43\xd6\xce\x1f\x32\x53\x91\x63"
+ "\x00\x6c\xb6\xdb",
.klen = 20,
- .iv = { 0xc0, 0x54, 0x3b, 0x59, 0xda, 0x48, 0xd9, 0x0b },
- .input = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
- .ilen = 32,
- .result = { 0x51, 0x04, 0xa1, 0x06, 0x16, 0x8a, 0x72, 0xd9,
- 0x79, 0x0d, 0x41, 0xee, 0x8e, 0xda, 0xd3, 0x88,
- 0xeb, 0x2e, 0x1e, 0xfc, 0x46, 0xda, 0x57, 0xc8,
- 0xfc, 0xe6, 0x30, 0xdf, 0x91, 0x41, 0xbe, 0x28 },
+ .iv = "\xc0\x54\x3b\x59\xda\x48\xd9\x0b",
+ .input = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+ .ilen = 32,
+ .result = "\x51\x04\xa1\x06\x16\x8a\x72\xd9"
+ "\x79\x0d\x41\xee\x8e\xda\xd3\x88"
+ "\xeb\x2e\x1e\xfc\x46\xda\x57\xc8"
+ "\xfc\xe6\x30\xdf\x91\x41\xbe\x28",
.rlen = 32,
}, {
- .key = { 0x16, 0xaf, 0x5b, 0x14, 0x5f, 0xc9, 0xf5, 0x79,
- 0xc1, 0x75, 0xf9, 0x3e, 0x3b, 0xfb, 0x0e, 0xed,
- 0x86, 0x3d, 0x06, 0xcc, 0xfd, 0xb7, 0x85, 0x15,
- 0x00, 0x00, 0x00, 0x48 },
- .klen = 28,
- .iv = { 0x36, 0x73, 0x3c, 0x14, 0x7d, 0x6d, 0x93, 0xcb },
- .input = { "Single block msg" },
- .ilen = 16,
- .result = { 0x4b, 0x55, 0x38, 0x4f, 0xe2, 0x59, 0xc9, 0xc8,
- 0x4e, 0x79, 0x35, 0xa0, 0x03, 0xcb, 0xe9, 0x28 },
+ .key = "\x16\xaf\x5b\x14\x5f\xc9\xf5\x79"
+ "\xc1\x75\xf9\x3e\x3b\xfb\x0e\xed"
+ "\x86\x3d\x06\xcc\xfd\xb7\x85\x15"
+ "\x00\x00\x00\x48",
+ .klen = 28,
+ .iv = "\x36\x73\x3c\x14\x7d\x6d\x93\xcb",
+ .input = "Single block msg",
+ .ilen = 16,
+ .result = "\x4b\x55\x38\x4f\xe2\x59\xc9\xc8"
+ "\x4e\x79\x35\xa0\x03\xcb\xe9\x28",
.rlen = 16,
}, {
- .key = { 0x7c, 0x5c, 0xb2, 0x40, 0x1b, 0x3d, 0xc3, 0x3c,
- 0x19, 0xe7, 0x34, 0x08, 0x19, 0xe0, 0xf6, 0x9c,
- 0x67, 0x8c, 0x3d, 0xb8, 0xe6, 0xf6, 0xa9, 0x1a,
- 0x00, 0x96, 0xb0, 0x3b },
+ .key = "\x7c\x5c\xb2\x40\x1b\x3d\xc3\x3c"
+ "\x19\xe7\x34\x08\x19\xe0\xf6\x9c"
+ "\x67\x8c\x3d\xb8\xe6\xf6\xa9\x1a"
+ "\x00\x96\xb0\x3b",
.klen = 28,
- .iv = { 0x02, 0x0c, 0x6e, 0xad, 0xc2, 0xcb, 0x50, 0x0d },
- .input = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .iv = "\x02\x0c\x6e\xad\xc2\xcb\x50\x0d",
+ .input = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.ilen = 32,
- .result = { 0x45, 0x32, 0x43, 0xfc, 0x60, 0x9b, 0x23, 0x32,
- 0x7e, 0xdf, 0xaa, 0xfa, 0x71, 0x31, 0xcd, 0x9f,
- 0x84, 0x90, 0x70, 0x1c, 0x5a, 0xd4, 0xa7, 0x9c,
- 0xfc, 0x1f, 0xe0, 0xff, 0x42, 0xf4, 0xfb, 0x00 },
- .rlen = 32,
- }, {
- .key = { 0x77, 0x6b, 0xef, 0xf2, 0x85, 0x1d, 0xb0, 0x6f,
- 0x4c, 0x8a, 0x05, 0x42, 0xc8, 0x69, 0x6f, 0x6c,
- 0x6a, 0x81, 0xaf, 0x1e, 0xec, 0x96, 0xb4, 0xd3,
- 0x7f, 0xc1, 0xd6, 0x89, 0xe6, 0xc1, 0xc1, 0x04,
- 0x00, 0x00, 0x00, 0x60 },
+ .result = "\x45\x32\x43\xfc\x60\x9b\x23\x32"
+ "\x7e\xdf\xaa\xfa\x71\x31\xcd\x9f"
+ "\x84\x90\x70\x1c\x5a\xd4\xa7\x9c"
+ "\xfc\x1f\xe0\xff\x42\xf4\xfb\x00",
+ .rlen = 32,
+ }, {
+ .key = "\x77\x6b\xef\xf2\x85\x1d\xb0\x6f"
+ "\x4c\x8a\x05\x42\xc8\x69\x6f\x6c"
+ "\x6a\x81\xaf\x1e\xec\x96\xb4\xd3"
+ "\x7f\xc1\xd6\x89\xe6\xc1\xc1\x04"
+ "\x00\x00\x00\x60",
.klen = 36,
- .iv = { 0xdb, 0x56, 0x72, 0xc9, 0x7a, 0xa8, 0xf0, 0xb2 },
- .input = { "Single block msg" },
+ .iv = "\xdb\x56\x72\xc9\x7a\xa8\xf0\xb2",
+ .input = "Single block msg",
.ilen = 16,
- .result = { 0x14, 0x5a, 0xd0, 0x1d, 0xbf, 0x82, 0x4e, 0xc7,
- 0x56, 0x08, 0x63, 0xdc, 0x71, 0xe3, 0xe0, 0xc0 },
- .rlen = 16,
- }, {
- .key = { 0xf6, 0xd6, 0x6d, 0x6b, 0xd5, 0x2d, 0x59, 0xbb,
- 0x07, 0x96, 0x36, 0x58, 0x79, 0xef, 0xf8, 0x86,
- 0xc6, 0x6d, 0xd5, 0x1a, 0x5b, 0x6a, 0x99, 0x74,
- 0x4b, 0x50, 0x59, 0x0c, 0x87, 0xa2, 0x38, 0x84,
- 0x00, 0xfa, 0xac, 0x24 },
- .klen = 36,
- .iv = { 0xc1, 0x58, 0x5e, 0xf1, 0x5a, 0x43, 0xd8, 0x75 },
- .input = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .result = "\x14\x5a\xd0\x1d\xbf\x82\x4e\xc7"
+ "\x56\x08\x63\xdc\x71\xe3\xe0\xc0",
+ .rlen = 16,
+ }, {
+ .key = "\xf6\xd6\x6d\x6b\xd5\x2d\x59\xbb"
+ "\x07\x96\x36\x58\x79\xef\xf8\x86"
+ "\xc6\x6d\xd5\x1a\x5b\x6a\x99\x74"
+ "\x4b\x50\x59\x0c\x87\xa2\x38\x84"
+ "\x00\xfa\xac\x24",
+ .klen = 36,
+ .iv = "\xc1\x58\x5e\xf1\x5a\x43\xd8\x75",
+ .input = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.ilen = 32,
- .result = { 0xf0, 0x5e, 0x23, 0x1b, 0x38, 0x94, 0x61, 0x2c,
- 0x49, 0xee, 0x00, 0x0b, 0x80, 0x4e, 0xb2, 0xa9,
- 0xb8, 0x30, 0x6b, 0x50, 0x8f, 0x83, 0x9d, 0x6a,
- 0x55, 0x30, 0x83, 0x1d, 0x93, 0x44, 0xaf, 0x1c },
+ .result = "\xf0\x5e\x23\x1b\x38\x94\x61\x2c"
+ "\x49\xee\x00\x0b\x80\x4e\xb2\xa9"
+ "\xb8\x30\x6b\x50\x8f\x83\x9d\x6a"
+ "\x55\x30\x83\x1d\x93\x44\xaf\x1c",
.rlen = 32,
}, {
// generated using Crypto++
- .key = {
- 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- 0x00, 0x00, 0x00, 0x00,
- },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
+ "\x00\x00\x00\x00",
.klen = 32 + 4,
- .iv = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- },
- .input = {
- 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
- 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
- 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
- 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
- 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
- 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
- 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
- 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
- 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
- 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
- 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
- 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
- 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
- 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
- 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
- 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
- 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
- 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
- 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
- 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
- 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
- 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
- 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
- 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
- 0x00, 0x03, 0x06, 0x09, 0x0c, 0x0f, 0x12, 0x15,
- 0x18, 0x1b, 0x1e, 0x21, 0x24, 0x27, 0x2a, 0x2d,
- 0x30, 0x33, 0x36, 0x39, 0x3c, 0x3f, 0x42, 0x45,
- 0x48, 0x4b, 0x4e, 0x51, 0x54, 0x57, 0x5a, 0x5d,
- 0x60, 0x63, 0x66, 0x69, 0x6c, 0x6f, 0x72, 0x75,
- 0x78, 0x7b, 0x7e, 0x81, 0x84, 0x87, 0x8a, 0x8d,
- 0x90, 0x93, 0x96, 0x99, 0x9c, 0x9f, 0xa2, 0xa5,
- 0xa8, 0xab, 0xae, 0xb1, 0xb4, 0xb7, 0xba, 0xbd,
- 0xc0, 0xc3, 0xc6, 0xc9, 0xcc, 0xcf, 0xd2, 0xd5,
- 0xd8, 0xdb, 0xde, 0xe1, 0xe4, 0xe7, 0xea, 0xed,
- 0xf0, 0xf3, 0xf6, 0xf9, 0xfc, 0xff, 0x02, 0x05,
- 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, 0x1a, 0x1d,
- 0x20, 0x23, 0x26, 0x29, 0x2c, 0x2f, 0x32, 0x35,
- 0x38, 0x3b, 0x3e, 0x41, 0x44, 0x47, 0x4a, 0x4d,
- 0x50, 0x53, 0x56, 0x59, 0x5c, 0x5f, 0x62, 0x65,
- 0x68, 0x6b, 0x6e, 0x71, 0x74, 0x77, 0x7a, 0x7d,
- 0x80, 0x83, 0x86, 0x89, 0x8c, 0x8f, 0x92, 0x95,
- 0x98, 0x9b, 0x9e, 0xa1, 0xa4, 0xa7, 0xaa, 0xad,
- 0xb0, 0xb3, 0xb6, 0xb9, 0xbc, 0xbf, 0xc2, 0xc5,
- 0xc8, 0xcb, 0xce, 0xd1, 0xd4, 0xd7, 0xda, 0xdd,
- 0xe0, 0xe3, 0xe6, 0xe9, 0xec, 0xef, 0xf2, 0xf5,
- 0xf8, 0xfb, 0xfe, 0x01, 0x04, 0x07, 0x0a, 0x0d,
- 0x10, 0x13, 0x16, 0x19, 0x1c, 0x1f, 0x22, 0x25,
- 0x28, 0x2b, 0x2e, 0x31, 0x34, 0x37, 0x3a, 0x3d,
- 0x40, 0x43, 0x46, 0x49, 0x4c, 0x4f, 0x52, 0x55,
- 0x58, 0x5b, 0x5e, 0x61, 0x64, 0x67, 0x6a, 0x6d,
- 0x70, 0x73, 0x76, 0x79, 0x7c, 0x7f, 0x82, 0x85,
- 0x88, 0x8b, 0x8e, 0x91, 0x94, 0x97, 0x9a, 0x9d,
- 0xa0, 0xa3, 0xa6, 0xa9, 0xac, 0xaf, 0xb2, 0xb5,
- 0xb8, 0xbb, 0xbe, 0xc1, 0xc4, 0xc7, 0xca, 0xcd,
- 0xd0, 0xd3, 0xd6, 0xd9, 0xdc, 0xdf, 0xe2, 0xe5,
- 0xe8, 0xeb, 0xee, 0xf1, 0xf4, 0xf7, 0xfa, 0xfd,
- 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 0x1e, 0x23,
- 0x28, 0x2d, 0x32, 0x37, 0x3c, 0x41, 0x46, 0x4b,
- 0x50, 0x55, 0x5a, 0x5f, 0x64, 0x69, 0x6e, 0x73,
- 0x78, 0x7d, 0x82, 0x87, 0x8c, 0x91, 0x96, 0x9b,
- 0xa0, 0xa5, 0xaa, 0xaf, 0xb4, 0xb9, 0xbe, 0xc3,
- 0xc8, 0xcd, 0xd2, 0xd7, 0xdc, 0xe1, 0xe6, 0xeb,
- 0xf0, 0xf5, 0xfa, 0xff, 0x04, 0x09, 0x0e, 0x13,
- 0x18, 0x1d, 0x22, 0x27, 0x2c, 0x31, 0x36, 0x3b,
- 0x40, 0x45, 0x4a, 0x4f, 0x54, 0x59, 0x5e, 0x63,
- 0x68, 0x6d, 0x72, 0x77, 0x7c, 0x81, 0x86, 0x8b,
- 0x90, 0x95, 0x9a, 0x9f, 0xa4, 0xa9, 0xae, 0xb3,
- 0xb8, 0xbd, 0xc2, 0xc7, 0xcc, 0xd1, 0xd6, 0xdb,
- 0xe0, 0xe5, 0xea, 0xef, 0xf4, 0xf9, 0xfe, 0x03,
- 0x08, 0x0d, 0x12, 0x17, 0x1c, 0x21, 0x26, 0x2b,
- 0x30, 0x35, 0x3a, 0x3f, 0x44, 0x49, 0x4e, 0x53,
- 0x58, 0x5d, 0x62, 0x67, 0x6c, 0x71, 0x76, 0x7b,
- 0x80, 0x85, 0x8a, 0x8f, 0x94, 0x99, 0x9e, 0xa3,
- 0xa8, 0xad, 0xb2, 0xb7, 0xbc, 0xc1, 0xc6, 0xcb,
- 0xd0, 0xd5, 0xda, 0xdf, 0xe4, 0xe9, 0xee, 0xf3,
- 0xf8, 0xfd, 0x02, 0x07, 0x0c, 0x11, 0x16, 0x1b,
- 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3e, 0x43,
- 0x48, 0x4d, 0x52, 0x57, 0x5c, 0x61, 0x66, 0x6b,
- 0x70, 0x75, 0x7a, 0x7f, 0x84, 0x89, 0x8e, 0x93,
- 0x98, 0x9d, 0xa2, 0xa7, 0xac, 0xb1, 0xb6, 0xbb,
- 0xc0, 0xc5, 0xca, 0xcf, 0xd4, 0xd9, 0xde, 0xe3,
- 0xe8, 0xed, 0xf2, 0xf7, 0xfc, 0x01, 0x06, 0x0b,
- 0x10, 0x15, 0x1a, 0x1f, 0x24, 0x29, 0x2e, 0x33,
- 0x38, 0x3d, 0x42, 0x47, 0x4c, 0x51, 0x56, 0x5b,
- 0x60, 0x65, 0x6a, 0x6f, 0x74, 0x79, 0x7e, 0x83,
- 0x88, 0x8d, 0x92, 0x97, 0x9c, 0xa1, 0xa6, 0xab,
- 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9, 0xce, 0xd3,
- 0xd8, 0xdd, 0xe2, 0xe7, 0xec, 0xf1, 0xf6, 0xfb,
- 0x00, 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31,
- 0x38, 0x3f, 0x46, 0x4d, 0x54, 0x5b, 0x62, 0x69,
- 0x70, 0x77, 0x7e, 0x85, 0x8c, 0x93, 0x9a, 0xa1,
- 0xa8, 0xaf, 0xb6, 0xbd, 0xc4, 0xcb, 0xd2, 0xd9,
- 0xe0, 0xe7, 0xee, 0xf5, 0xfc, 0x03, 0x0a, 0x11,
- 0x18, 0x1f, 0x26, 0x2d, 0x34, 0x3b, 0x42, 0x49,
- 0x50, 0x57, 0x5e, 0x65, 0x6c, 0x73, 0x7a, 0x81,
- 0x88, 0x8f, 0x96, 0x9d, 0xa4, 0xab, 0xb2, 0xb9,
- 0xc0, 0xc7, 0xce, 0xd5, 0xdc, 0xe3, 0xea, 0xf1,
- 0xf8, 0xff, 0x06, 0x0d, 0x14, 0x1b, 0x22, 0x29,
- 0x30, 0x37, 0x3e, 0x45, 0x4c, 0x53, 0x5a, 0x61,
- 0x68, 0x6f, 0x76, 0x7d, 0x84, 0x8b, 0x92, 0x99,
- 0xa0, 0xa7, 0xae, 0xb5, 0xbc, 0xc3, 0xca, 0xd1,
- 0xd8, 0xdf, 0xe6, 0xed, 0xf4, 0xfb, 0x02, 0x09,
- 0x10, 0x17, 0x1e, 0x25, 0x2c, 0x33, 0x3a, 0x41,
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- 0x38, 0x4d, 0x62, 0x77, 0x8c, 0xa1, 0xb6, 0xcb,
- 0xe0, 0xf5, 0x0a, 0x1f, 0x34, 0x49, 0x5e, 0x73,
- 0x88, 0x9d, 0xb2, 0xc7, 0xdc, 0xf1, 0x06, 0x1b,
- 0x30, 0x45, 0x5a, 0x6f, 0x84, 0x99, 0xae, 0xc3,
- 0xd8, 0xed, 0x02, 0x17, 0x2c, 0x41, 0x56, 0x6b,
- 0x80, 0x95, 0xaa, 0xbf, 0xd4, 0xe9, 0xfe, 0x13,
- 0x28, 0x3d, 0x52, 0x67, 0x7c, 0x91, 0xa6, 0xbb,
- 0xd0, 0xe5, 0xfa, 0x0f, 0x24, 0x39, 0x4e, 0x63,
- 0x78, 0x8d, 0xa2, 0xb7, 0xcc, 0xe1, 0xf6, 0x0b,
- 0x20, 0x35, 0x4a, 0x5f, 0x74, 0x89, 0x9e, 0xb3,
- 0xc8, 0xdd, 0xf2, 0x07, 0x1c, 0x31, 0x46, 0x5b,
- 0x70, 0x85, 0x9a, 0xaf, 0xc4, 0xd9, 0xee, 0x03,
- 0x18, 0x2d, 0x42, 0x57, 0x6c, 0x81, 0x96, 0xab,
- 0xc0, 0xd5, 0xea, 0xff, 0x14, 0x29, 0x3e, 0x53,
- 0x68, 0x7d, 0x92, 0xa7, 0xbc, 0xd1, 0xe6, 0xfb,
- 0x10, 0x25, 0x3a, 0x4f, 0x64, 0x79, 0x8e, 0xa3,
- 0xb8, 0xcd, 0xe2, 0xf7, 0x0c, 0x21, 0x36, 0x4b,
- 0x60, 0x75, 0x8a, 0x9f, 0xb4, 0xc9, 0xde, 0xf3,
- 0x08, 0x1d, 0x32, 0x47, 0x5c, 0x71, 0x86, 0x9b,
- 0xb0, 0xc5, 0xda, 0xef, 0x04, 0x19, 0x2e, 0x43,
- 0x58, 0x6d, 0x82, 0x97, 0xac, 0xc1, 0xd6, 0xeb,
- 0x00, 0x17, 0x2e, 0x45, 0x5c, 0x73, 0x8a, 0xa1,
- 0xb8, 0xcf, 0xe6, 0xfd, 0x14, 0x2b, 0x42, 0x59,
- 0x70, 0x87, 0x9e, 0xb5, 0xcc, 0xe3, 0xfa, 0x11,
- 0x28, 0x3f, 0x56, 0x6d, 0x84, 0x9b, 0xb2, 0xc9,
- 0xe0, 0xf7, 0x0e, 0x25, 0x3c, 0x53, 0x6a, 0x81,
- 0x98, 0xaf, 0xc6, 0xdd, 0xf4, 0x0b, 0x22, 0x39,
- 0x50, 0x67, 0x7e, 0x95, 0xac, 0xc3, 0xda, 0xf1,
- 0x08, 0x1f, 0x36, 0x4d, 0x64, 0x7b, 0x92, 0xa9,
- 0xc0, 0xd7, 0xee, 0x05, 0x1c, 0x33, 0x4a, 0x61,
- 0x78, 0x8f, 0xa6, 0xbd, 0xd4, 0xeb, 0x02, 0x19,
- 0x30, 0x47, 0x5e, 0x75, 0x8c, 0xa3, 0xba, 0xd1,
- 0xe8, 0xff, 0x16, 0x2d, 0x44, 0x5b, 0x72, 0x89,
- 0xa0, 0xb7, 0xce, 0xe5, 0xfc, 0x13, 0x2a, 0x41,
- 0x58, 0x6f, 0x86, 0x9d, 0xb4, 0xcb, 0xe2, 0xf9,
- 0x10, 0x27, 0x3e, 0x55, 0x6c, 0x83, 0x9a, 0xb1,
- 0xc8, 0xdf, 0xf6, 0x0d, 0x24, 0x3b, 0x52, 0x69,
- 0x80, 0x97, 0xae, 0xc5, 0xdc, 0xf3, 0x0a, 0x21,
- 0x38, 0x4f, 0x66, 0x7d, 0x94, 0xab, 0xc2, 0xd9,
- 0xf0, 0x07, 0x1e, 0x35, 0x4c, 0x63, 0x7a, 0x91,
- 0xa8, 0xbf, 0xd6, 0xed, 0x04, 0x1b, 0x32, 0x49,
- 0x60, 0x77, 0x8e, 0xa5, 0xbc, 0xd3, 0xea, 0x01,
- 0x18, 0x2f, 0x46, 0x5d, 0x74, 0x8b, 0xa2, 0xb9,
- 0xd0, 0xe7, 0xfe, 0x15, 0x2c, 0x43, 0x5a, 0x71,
- 0x88, 0x9f, 0xb6, 0xcd, 0xe4, 0xfb, 0x12, 0x29,
- 0x40, 0x57, 0x6e, 0x85, 0x9c, 0xb3, 0xca, 0xe1,
- 0xf8, 0x0f, 0x26, 0x3d, 0x54, 0x6b, 0x82, 0x99,
- 0xb0, 0xc7, 0xde, 0xf5, 0x0c, 0x23, 0x3a, 0x51,
- 0x68, 0x7f, 0x96, 0xad, 0xc4, 0xdb, 0xf2, 0x09,
- 0x20, 0x37, 0x4e, 0x65, 0x7c, 0x93, 0xaa, 0xc1,
- 0xd8, 0xef, 0x06, 0x1d, 0x34, 0x4b, 0x62, 0x79,
- 0x90, 0xa7, 0xbe, 0xd5, 0xec, 0x03, 0x1a, 0x31,
- 0x48, 0x5f, 0x76, 0x8d, 0xa4, 0xbb, 0xd2, 0xe9,
- 0x00, 0x19, 0x32, 0x4b, 0x64, 0x7d, 0x96, 0xaf,
- 0xc8, 0xe1, 0xfa, 0x13, 0x2c, 0x45, 0x5e, 0x77,
- 0x90, 0xa9, 0xc2, 0xdb, 0xf4, 0x0d, 0x26, 0x3f,
- 0x58, 0x71, 0x8a, 0xa3, 0xbc, 0xd5, 0xee, 0x07,
- 0x20, 0x39, 0x52, 0x6b, 0x84, 0x9d, 0xb6, 0xcf,
- 0xe8, 0x01, 0x1a, 0x33, 0x4c, 0x65, 0x7e, 0x97,
- 0xb0, 0xc9, 0xe2, 0xfb, 0x14, 0x2d, 0x46, 0x5f,
- 0x78, 0x91, 0xaa, 0xc3, 0xdc, 0xf5, 0x0e, 0x27,
- 0x40, 0x59, 0x72, 0x8b, 0xa4, 0xbd, 0xd6, 0xef,
- 0x08, 0x21, 0x3a, 0x53, 0x6c, 0x85, 0x9e, 0xb7,
- 0xd0, 0xe9, 0x02, 0x1b, 0x34, 0x4d, 0x66, 0x7f,
- 0x98, 0xb1, 0xca, 0xe3, 0xfc, 0x15, 0x2e, 0x47,
- 0x60, 0x79, 0x92, 0xab, 0xc4, 0xdd, 0xf6, 0x0f,
- 0x28, 0x41, 0x5a, 0x73, 0x8c, 0xa5, 0xbe, 0xd7,
- 0xf0, 0x09, 0x22, 0x3b, 0x54, 0x6d, 0x86, 0x9f,
- 0xb8, 0xd1, 0xea, 0x03, 0x1c, 0x35, 0x4e, 0x67,
- 0x80, 0x99, 0xb2, 0xcb, 0xe4, 0xfd, 0x16, 0x2f,
- 0x48, 0x61, 0x7a, 0x93, 0xac, 0xc5, 0xde, 0xf7,
- 0x10, 0x29, 0x42, 0x5b, 0x74, 0x8d, 0xa6, 0xbf,
- 0xd8, 0xf1, 0x0a, 0x23, 0x3c, 0x55, 0x6e, 0x87,
- 0xa0, 0xb9, 0xd2, 0xeb, 0x04, 0x1d, 0x36, 0x4f,
- 0x68, 0x81, 0x9a, 0xb3, 0xcc, 0xe5, 0xfe, 0x17,
- 0x30, 0x49, 0x62, 0x7b, 0x94, 0xad, 0xc6, 0xdf,
- 0xf8, 0x11, 0x2a, 0x43, 0x5c, 0x75, 0x8e, 0xa7,
- 0xc0, 0xd9, 0xf2, 0x0b, 0x24, 0x3d, 0x56, 0x6f,
- 0x88, 0xa1, 0xba, 0xd3, 0xec, 0x05, 0x1e, 0x37,
- 0x50, 0x69, 0x82, 0x9b, 0xb4, 0xcd, 0xe6, 0xff,
- 0x18, 0x31, 0x4a, 0x63, 0x7c, 0x95, 0xae, 0xc7,
- 0xe0, 0xf9, 0x12, 0x2b, 0x44, 0x5d, 0x76, 0x8f,
- 0xa8, 0xc1, 0xda, 0xf3, 0x0c, 0x25, 0x3e, 0x57,
- 0x70, 0x89, 0xa2, 0xbb, 0xd4, 0xed, 0x06, 0x1f,
- 0x38, 0x51, 0x6a, 0x83, 0x9c, 0xb5, 0xce, 0xe7,
- 0x00, 0x1b, 0x36, 0x51, 0x6c, 0x87, 0xa2, 0xbd,
- 0xd8, 0xf3, 0x0e, 0x29, 0x44, 0x5f, 0x7a, 0x95,
- 0xb0, 0xcb, 0xe6, 0x01, 0x1c, 0x37, 0x52, 0x6d,
- 0x88, 0xa3, 0xbe, 0xd9, 0xf4, 0x0f, 0x2a, 0x45,
- 0x60, 0x7b, 0x96, 0xb1, 0xcc, 0xe7, 0x02, 0x1d,
- 0x38, 0x53, 0x6e, 0x89, 0xa4, 0xbf, 0xda, 0xf5,
- 0x10, 0x2b, 0x46, 0x61, 0x7c, 0x97, 0xb2, 0xcd,
- 0xe8, 0x03, 0x1e, 0x39, 0x54, 0x6f, 0x8a, 0xa5,
- 0xc0, 0xdb, 0xf6, 0x11, 0x2c, 0x47, 0x62, 0x7d,
- 0x98, 0xb3, 0xce, 0xe9, 0x04, 0x1f, 0x3a, 0x55,
- 0x70, 0x8b, 0xa6, 0xc1, 0xdc, 0xf7, 0x12, 0x2d,
- 0x48, 0x63, 0x7e, 0x99, 0xb4, 0xcf, 0xea, 0x05,
- 0x20, 0x3b, 0x56, 0x71, 0x8c, 0xa7, 0xc2, 0xdd,
- 0xf8, 0x13, 0x2e, 0x49, 0x64, 0x7f, 0x9a, 0xb5,
- 0xd0, 0xeb, 0x06, 0x21, 0x3c, 0x57, 0x72, 0x8d,
- 0xa8, 0xc3, 0xde, 0xf9, 0x14, 0x2f, 0x4a, 0x65,
- 0x80, 0x9b, 0xb6, 0xd1, 0xec, 0x07, 0x22, 0x3d,
- 0x58, 0x73, 0x8e, 0xa9, 0xc4, 0xdf, 0xfa, 0x15,
- 0x30, 0x4b, 0x66, 0x81, 0x9c, 0xb7, 0xd2, 0xed,
- 0x08, 0x23, 0x3e, 0x59, 0x74, 0x8f, 0xaa, 0xc5,
- 0xe0, 0xfb, 0x16, 0x31, 0x4c, 0x67, 0x82, 0x9d,
- 0xb8, 0xd3, 0xee, 0x09, 0x24, 0x3f, 0x5a, 0x75,
- 0x90, 0xab, 0xc6, 0xe1, 0xfc, 0x17, 0x32, 0x4d,
- 0x68, 0x83, 0x9e, 0xb9, 0xd4, 0xef, 0x0a, 0x25,
- 0x40, 0x5b, 0x76, 0x91, 0xac, 0xc7, 0xe2, 0xfd,
- 0x18, 0x33, 0x4e, 0x69, 0x84, 0x9f, 0xba, 0xd5,
- 0xf0, 0x0b, 0x26, 0x41, 0x5c, 0x77, 0x92, 0xad,
- 0xc8, 0xe3, 0xfe, 0x19, 0x34, 0x4f, 0x6a, 0x85,
- 0xa0, 0xbb, 0xd6, 0xf1, 0x0c, 0x27, 0x42, 0x5d,
- 0x78, 0x93, 0xae, 0xc9, 0xe4, 0xff, 0x1a, 0x35,
- 0x50, 0x6b, 0x86, 0xa1, 0xbc, 0xd7, 0xf2, 0x0d,
- 0x28, 0x43, 0x5e, 0x79, 0x94, 0xaf, 0xca, 0xe5,
- 0x00, 0x1d, 0x3a, 0x57, 0x74, 0x91, 0xae, 0xcb,
- 0xe8, 0x05, 0x22, 0x3f, 0x5c, 0x79, 0x96, 0xb3,
- 0xd0, 0xed, 0x0a, 0x27, 0x44, 0x61, 0x7e, 0x9b,
- 0xb8, 0xd5, 0xf2, 0x0f, 0x2c, 0x49, 0x66, 0x83,
- 0xa0, 0xbd, 0xda, 0xf7, 0x14, 0x31, 0x4e, 0x6b,
- 0x88, 0xa5, 0xc2, 0xdf, 0xfc, 0x19, 0x36, 0x53,
- 0x70, 0x8d, 0xaa, 0xc7, 0xe4, 0x01, 0x1e, 0x3b,
- 0x58, 0x75, 0x92, 0xaf, 0xcc, 0xe9, 0x06, 0x23,
- 0x40, 0x5d, 0x7a, 0x97, 0xb4, 0xd1, 0xee, 0x0b,
- 0x28, 0x45, 0x62, 0x7f, 0x9c, 0xb9, 0xd6, 0xf3,
- 0x10, 0x2d, 0x4a, 0x67, 0x84, 0xa1, 0xbe, 0xdb,
- 0xf8, 0x15, 0x32, 0x4f, 0x6c, 0x89, 0xa6, 0xc3,
- 0xe0, 0xfd, 0x1a, 0x37, 0x54, 0x71, 0x8e, 0xab,
- 0xc8, 0xe5, 0x02, 0x1f, 0x3c, 0x59, 0x76, 0x93,
- 0xb0, 0xcd, 0xea, 0x07, 0x24, 0x41, 0x5e, 0x7b,
- 0x98, 0xb5, 0xd2, 0xef, 0x0c, 0x29, 0x46, 0x63,
- 0x80, 0x9d, 0xba, 0xd7, 0xf4, 0x11, 0x2e, 0x4b,
- 0x68, 0x85, 0xa2, 0xbf, 0xdc, 0xf9, 0x16, 0x33,
- 0x50, 0x6d, 0x8a, 0xa7, 0xc4, 0xe1, 0xfe, 0x1b,
- 0x38, 0x55, 0x72, 0x8f, 0xac, 0xc9, 0xe6, 0x03,
- 0x20, 0x3d, 0x5a, 0x77, 0x94, 0xb1, 0xce, 0xeb,
- 0x08, 0x25, 0x42, 0x5f, 0x7c, 0x99, 0xb6, 0xd3,
- 0xf0, 0x0d, 0x2a, 0x47, 0x64, 0x81, 0x9e, 0xbb,
- 0xd8, 0xf5, 0x12, 0x2f, 0x4c, 0x69, 0x86, 0xa3,
- 0xc0, 0xdd, 0xfa, 0x17, 0x34, 0x51, 0x6e, 0x8b,
- 0xa8, 0xc5, 0xe2, 0xff, 0x1c, 0x39, 0x56, 0x73,
- 0x90, 0xad, 0xca, 0xe7, 0x04, 0x21, 0x3e, 0x5b,
- 0x78, 0x95, 0xb2, 0xcf, 0xec, 0x09, 0x26, 0x43,
- 0x60, 0x7d, 0x9a, 0xb7, 0xd4, 0xf1, 0x0e, 0x2b,
- 0x48, 0x65, 0x82, 0x9f, 0xbc, 0xd9, 0xf6, 0x13,
- 0x30, 0x4d, 0x6a, 0x87, 0xa4, 0xc1, 0xde, 0xfb,
- 0x18, 0x35, 0x52, 0x6f, 0x8c, 0xa9, 0xc6, 0xe3,
- 0x00, 0x1f, 0x3e, 0x5d, 0x7c, 0x9b, 0xba, 0xd9,
- 0xf8, 0x17, 0x36, 0x55, 0x74, 0x93, 0xb2, 0xd1,
- 0xf0, 0x0f, 0x2e, 0x4d, 0x6c, 0x8b, 0xaa, 0xc9,
- 0xe8, 0x07, 0x26, 0x45, 0x64, 0x83, 0xa2, 0xc1,
- 0xe0, 0xff, 0x1e, 0x3d, 0x5c, 0x7b, 0x9a, 0xb9,
- 0xd8, 0xf7, 0x16, 0x35, 0x54, 0x73, 0x92, 0xb1,
- 0xd0, 0xef, 0x0e, 0x2d, 0x4c, 0x6b, 0x8a, 0xa9,
- 0xc8, 0xe7, 0x06, 0x25, 0x44, 0x63, 0x82, 0xa1,
- 0xc0, 0xdf, 0xfe, 0x1d, 0x3c, 0x5b, 0x7a, 0x99,
- 0xb8, 0xd7, 0xf6, 0x15, 0x34, 0x53, 0x72, 0x91,
- 0xb0, 0xcf, 0xee, 0x0d, 0x2c, 0x4b, 0x6a, 0x89,
- 0xa8, 0xc7, 0xe6, 0x05, 0x24, 0x43, 0x62, 0x81,
- 0xa0, 0xbf, 0xde, 0xfd, 0x1c, 0x3b, 0x5a, 0x79,
- 0x98, 0xb7, 0xd6, 0xf5, 0x14, 0x33, 0x52, 0x71,
- 0x90, 0xaf, 0xce, 0xed, 0x0c, 0x2b, 0x4a, 0x69,
- 0x88, 0xa7, 0xc6, 0xe5, 0x04, 0x23, 0x42, 0x61,
- 0x80, 0x9f, 0xbe, 0xdd, 0xfc, 0x1b, 0x3a, 0x59,
- 0x78, 0x97, 0xb6, 0xd5, 0xf4, 0x13, 0x32, 0x51,
- 0x70, 0x8f, 0xae, 0xcd, 0xec, 0x0b, 0x2a, 0x49,
- 0x68, 0x87, 0xa6, 0xc5, 0xe4, 0x03, 0x22, 0x41,
- 0x60, 0x7f, 0x9e, 0xbd, 0xdc, 0xfb, 0x1a, 0x39,
- 0x58, 0x77, 0x96, 0xb5, 0xd4, 0xf3, 0x12, 0x31,
- 0x50, 0x6f, 0x8e, 0xad, 0xcc, 0xeb, 0x0a, 0x29,
- 0x48, 0x67, 0x86, 0xa5, 0xc4, 0xe3, 0x02, 0x21,
- 0x40, 0x5f, 0x7e, 0x9d, 0xbc, 0xdb, 0xfa, 0x19,
- 0x38, 0x57, 0x76, 0x95, 0xb4, 0xd3, 0xf2, 0x11,
- 0x30, 0x4f, 0x6e, 0x8d, 0xac, 0xcb, 0xea, 0x09,
- 0x28, 0x47, 0x66, 0x85, 0xa4, 0xc3, 0xe2, 0x01,
- 0x20, 0x3f, 0x5e, 0x7d, 0x9c, 0xbb, 0xda, 0xf9,
- 0x18, 0x37, 0x56, 0x75, 0x94, 0xb3, 0xd2, 0xf1,
- 0x10, 0x2f, 0x4e, 0x6d, 0x8c, 0xab, 0xca, 0xe9,
- 0x08, 0x27, 0x46, 0x65, 0x84, 0xa3, 0xc2, 0xe1,
- 0x00, 0x21, 0x42, 0x63,
- },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input =
+ "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
+ "\x20\x21\x22\x23\x24\x25\x26\x27"
+ "\x28\x29\x2a\x2b\x2c\x2d\x2e\x2f"
+ "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x3a\x3b\x3c\x3d\x3e\x3f"
+ "\x40\x41\x42\x43\x44\x45\x46\x47"
+ "\x48\x49\x4a\x4b\x4c\x4d\x4e\x4f"
+ "\x50\x51\x52\x53\x54\x55\x56\x57"
+ "\x58\x59\x5a\x5b\x5c\x5d\x5e\x5f"
+ "\x60\x61\x62\x63\x64\x65\x66\x67"
+ "\x68\x69\x6a\x6b\x6c\x6d\x6e\x6f"
+ "\x70\x71\x72\x73\x74\x75\x76\x77"
+ "\x78\x79\x7a\x7b\x7c\x7d\x7e\x7f"
+ "\x80\x81\x82\x83\x84\x85\x86\x87"
+ "\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f"
+ "\x90\x91\x92\x93\x94\x95\x96\x97"
+ "\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7"
+ "\xa8\xa9\xaa\xab\xac\xad\xae\xaf"
+ "\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7"
+ "\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf"
+ "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf"
+ "\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7"
+ "\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf"
+ "\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7"
+ "\xe8\xe9\xea\xeb\xec\xed\xee\xef"
+ "\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7"
+ "\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"
+ "\x00\x03\x06\x09\x0c\x0f\x12\x15"
+ "\x18\x1b\x1e\x21\x24\x27\x2a\x2d"
+ "\x30\x33\x36\x39\x3c\x3f\x42\x45"
+ "\x48\x4b\x4e\x51\x54\x57\x5a\x5d"
+ "\x60\x63\x66\x69\x6c\x6f\x72\x75"
+ "\x78\x7b\x7e\x81\x84\x87\x8a\x8d"
+ "\x90\x93\x96\x99\x9c\x9f\xa2\xa5"
+ "\xa8\xab\xae\xb1\xb4\xb7\xba\xbd"
+ "\xc0\xc3\xc6\xc9\xcc\xcf\xd2\xd5"
+ "\xd8\xdb\xde\xe1\xe4\xe7\xea\xed"
+ "\xf0\xf3\xf6\xf9\xfc\xff\x02\x05"
+ "\x08\x0b\x0e\x11\x14\x17\x1a\x1d"
+ "\x20\x23\x26\x29\x2c\x2f\x32\x35"
+ "\x38\x3b\x3e\x41\x44\x47\x4a\x4d"
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+ "\xe8\x07\x26\x45\x64\x83\xa2\xc1"
+ "\xe0\xff\x1e\x3d\x5c\x7b\x9a\xb9"
+ "\xd8\xf7\x16\x35\x54\x73\x92\xb1"
+ "\xd0\xef\x0e\x2d\x4c\x6b\x8a\xa9"
+ "\xc8\xe7\x06\x25\x44\x63\x82\xa1"
+ "\xc0\xdf\xfe\x1d\x3c\x5b\x7a\x99"
+ "\xb8\xd7\xf6\x15\x34\x53\x72\x91"
+ "\xb0\xcf\xee\x0d\x2c\x4b\x6a\x89"
+ "\xa8\xc7\xe6\x05\x24\x43\x62\x81"
+ "\xa0\xbf\xde\xfd\x1c\x3b\x5a\x79"
+ "\x98\xb7\xd6\xf5\x14\x33\x52\x71"
+ "\x90\xaf\xce\xed\x0c\x2b\x4a\x69"
+ "\x88\xa7\xc6\xe5\x04\x23\x42\x61"
+ "\x80\x9f\xbe\xdd\xfc\x1b\x3a\x59"
+ "\x78\x97\xb6\xd5\xf4\x13\x32\x51"
+ "\x70\x8f\xae\xcd\xec\x0b\x2a\x49"
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+ "\x20\x3f\x5e\x7d\x9c\xbb\xda\xf9"
+ "\x18\x37\x56\x75\x94\xb3\xd2\xf1"
+ "\x10\x2f\x4e\x6d\x8c\xab\xca\xe9"
+ "\x08\x27\x46\x65\x84\xa3\xc2\xe1"
+ "\x00\x21\x42\x63",
.ilen = 4100,
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- 0xd3, 0x02, 0xe8, 0xdc, 0x5d, 0x0d, 0x50, 0xdc,
- 0xae, 0xb7, 0x46, 0xf9, 0xa8, 0xe6, 0xd0, 0x16,
- 0xcc, 0xe6, 0x2c, 0x81, 0xc7, 0xad, 0xe9, 0xf0,
- 0x05, 0x72, 0x6d, 0x3d, 0x0a, 0x7a, 0xa9, 0x02,
- 0xac, 0x82, 0x93, 0x6e, 0xb6, 0x1c, 0x28, 0xfc,
- 0x44, 0x12, 0xfb, 0x73, 0x77, 0xd4, 0x13, 0x39,
- 0x29, 0x88, 0x8a, 0xf3, 0x5c, 0xa6, 0x36, 0xa0,
- 0x2a, 0xed, 0x7e, 0xb1, 0x1d, 0xd6, 0x4c, 0x6b,
- 0x41, 0x01, 0x18, 0x5d, 0x5d, 0x07, 0x97, 0xa6,
- 0x4b, 0xef, 0x31, 0x18, 0xea, 0xac, 0xb1, 0x84,
- 0x21, 0xed, 0xda, 0x86,
- },
+ .result =
+ "\xf0\x5c\x74\xad\x4e\xbc\x99\xe2"
+ "\xae\xff\x91\x3a\x44\xcf\x38\x32"
+ "\x1e\xad\xa7\xcd\xa1\x39\x95\xaa"
+ "\x10\xb1\xb3\x2e\x04\x31\x8f\x86"
+ "\xf2\x62\x74\x70\x0c\xa4\x46\x08"
+ "\xa8\xb7\x99\xa8\xe9\xd2\x73\x79"
+ "\x7e\x6e\xd4\x8f\x1e\xc7\x8e\x31"
+ "\x0b\xfa\x4b\xce\xfd\xf3\x57\x71"
+ "\xe9\x46\x03\xa5\x3d\x34\x00\xe2"
+ "\x18\xff\x75\x6d\x06\x2d\x00\xab"
+ "\xb9\x3e\x6c\x59\xc5\x84\x06\xb5"
+ "\x8b\xd0\x89\x9c\x4a\x79\x16\xc6"
+ "\x3d\x74\x54\xfa\x44\xcd\x23\x26"
+ "\x5c\xcf\x7e\x28\x92\x32\xbf\xdf"
+ "\xa7\x20\x3c\x74\x58\x2a\x9a\xde"
+ "\x61\x00\x1c\x4f\xff\x59\xc4\x22"
+ "\xac\x3c\xd0\xe8\x6c\xf9\x97\x1b"
+ "\x58\x9b\xad\x71\xe8\xa9\xb5\x0d"
+ "\xee\x2f\x04\x1f\x7f\xbc\x99\xee"
+ "\x84\xff\x42\x60\xdc\x3a\x18\xa5"
+ "\x81\xf9\xef\xdc\x7a\x0f\x65\x41"
+ "\x2f\xa3\xd3\xf9\xc2\xcb\xc0\x4d"
+ "\x8f\xd3\x76\x96\xad\x49\x6d\x38"
+ "\x3d\x39\x0b\x6c\x80\xb7\x54\x69"
+ "\xf0\x2c\x90\x02\x29\x0d\x1c\x12"
+ "\xad\x55\xc3\x8b\x68\xd9\xcc\xb3"
+ "\xb2\x64\x33\x90\x5e\xca\x4b\xe2"
+ "\xfb\x75\xdc\x63\xf7\x9f\x82\x74"
+ "\xf0\xc9\xaa\x7f\xe9\x2a\x9b\x33"
+ "\xbc\x88\x00\x7f\xca\xb2\x1f\x14"
+ "\xdb\xc5\x8e\x7b\x11\x3c\x3e\x08"
+ "\xf3\x83\xe8\xe0\x94\x86\x2e\x92"
+ "\x78\x6b\x01\xc9\xc7\x83\xba\x21"
+ "\x6a\x25\x15\x33\x4e\x45\x08\xec"
+ "\x35\xdb\xe0\x6e\x31\x51\x79\xa9"
+ "\x42\x44\x65\xc1\xa0\xf1\xf9\x2a"
+ "\x70\xd5\xb6\xc6\xc1\x8c\x39\xfc"
+ "\x25\xa6\x55\xd9\xdd\x2d\x4c\xec"
+ "\x49\xc6\xeb\x0e\xa8\x25\x2a\x16"
+ "\x1b\x66\x84\xda\xe2\x92\xe5\xc0"
+ "\xc8\x53\x07\xaf\x80\x84\xec\xfd"
+ "\xcd\xd1\x6e\xcd\x6f\x6a\xf5\x36"
+ "\xc5\x15\xe5\x25\x7d\x77\xd1\x1a"
+ "\x93\x36\xa9\xcf\x7c\xa4\x54\x4a"
+ "\x06\x51\x48\x4e\xf6\x59\x87\xd2"
+ "\x04\x02\xef\xd3\x44\xde\x76\x31"
+ "\xb3\x34\x17\x1b\x9d\x66\x11\x9f"
+ "\x1e\xcc\x17\xe9\xc7\x3c\x1b\xe7"
+ "\xcb\x50\x08\xfc\xdc\x2b\x24\xdb"
+ "\x65\x83\xd0\x3b\xe3\x30\xea\x94"
+ "\x6c\xe7\xe8\x35\x32\xc7\xdb\x64"
+ "\xb4\x01\xab\x36\x2c\x77\x13\xaf"
+ "\xf8\x2b\x88\x3f\x54\x39\xc4\x44"
+ "\xfe\xef\x6f\x68\x34\xbe\x0f\x05"
+ "\x16\x6d\xf6\x0a\x30\xe7\xe3\xed"
+ "\xc4\xde\x3c\x1b\x13\xd8\xdb\xfe"
+ "\x41\x62\xe5\x28\xd4\x8d\xa3\xc7"
+ "\x93\x97\xc6\x48\x45\x1d\x9f\x83"
+ "\xdf\x4b\x40\x3e\x42\x25\x87\x80"
+ "\x4c\x7d\xa8\xd4\x98\x23\x95\x75"
+ "\x41\x8c\xda\x41\x9b\xd4\xa7\x06"
+ "\xb5\xf1\x71\x09\x53\xbe\xca\xbf"
+ "\x32\x03\xed\xf0\x50\x1c\x56\x39"
+ "\x5b\xa4\x75\x18\xf7\x9b\x58\xef"
+ "\x53\xfc\x2a\x38\x23\x15\x75\xcd"
+ "\x45\xe5\x5a\x82\x55\xba\x21\xfa"
+ "\xd4\xbd\xc6\x94\x7c\xc5\x80\x12"
+ "\xf7\x4b\x32\xc4\x9a\x82\xd8\x28"
+ "\x8f\xd9\xc2\x0f\x60\x03\xbe\x5e"
+ "\x21\xd6\x5f\x58\xbf\x5c\xb1\x32"
+ "\x82\x8d\xa9\xe5\xf2\x66\x1a\xc0"
+ "\xa0\xbc\x58\x2f\x71\xf5\x2f\xed"
+ "\xd1\x26\xb9\xd8\x49\x5a\x07\x19"
+ "\x01\x7c\x59\xb0\xf8\xa4\xb7\xd3"
+ "\x7b\x1a\x8c\x38\xf4\x50\xa4\x59"
+ "\xb0\xcc\x41\x0b\x88\x7f\xe5\x31"
+ "\xb3\x42\xba\xa2\x7e\xd4\x32\x71"
+ "\x45\x87\x48\xa9\xc2\xf2\x89\xb3"
+ "\xe4\xa7\x7e\x52\x15\x61\xfa\xfe"
+ "\xc9\xdd\x81\xeb\x13\xab\xab\xc3"
+ "\x98\x59\xd8\x16\x3d\x14\x7a\x1c"
+ "\x3c\x41\x9a\x16\x16\x9b\xd2\xd2"
+ "\x69\x3a\x29\x23\xac\x86\x32\xa5"
+ "\x48\x9c\x9e\xf3\x47\x77\x81\x70"
+ "\x24\xe8\x85\xd2\xf5\xb5\xfa\xff"
+ "\x59\x6a\xd3\x50\x59\x43\x59\xde"
+ "\xd9\xf1\x55\xa5\x0c\xc3\x1a\x1a"
+ "\x18\x34\x0d\x1a\x63\x33\xed\x10"
+ "\xe0\x1d\x2a\x18\xd2\xc0\x54\xa8"
+ "\xca\xb5\x9a\xd3\xdd\xca\x45\x84"
+ "\x50\xe7\x0f\xfe\xa4\x99\x5a\xbe"
+ "\x43\x2d\x9a\xcb\x92\x3f\x5a\x1d"
+ "\x85\xd8\xc9\xdf\x68\xc9\x12\x80"
+ "\x56\x0c\xdc\x00\xdc\x3a\x7d\x9d"
+ "\xa3\xa2\xe8\x4d\xbf\xf9\x70\xa0"
+ "\xa4\x13\x4f\x6b\xaf\x0a\x89\x7f"
+ "\xda\xf0\xbf\x9b\xc8\x1d\xe5\xf8"
+ "\x2e\x8b\x07\xb5\x73\x1b\xcc\xa2"
+ "\xa6\xad\x30\xbc\x78\x3c\x5b\x10"
+ "\xfa\x5e\x62\x2d\x9e\x64\xb3\x33"
+ "\xce\xf9\x1f\x86\xe7\x8b\xa2\xb8"
+ "\xe8\x99\x57\x8c\x11\xed\x66\xd9"
+ "\x3c\x72\xb9\xc3\xe6\x4e\x17\x3a"
+ "\x6a\xcb\x42\x24\x06\xed\x3e\x4e"
+ "\xa3\xe8\x6a\x94\xda\x0d\x4e\xd5"
+ "\x14\x19\xcf\xb6\x26\xd8\x2e\xcc"
+ "\x64\x76\x38\x49\x4d\xfe\x30\x6d"
+ "\xe4\xc8\x8c\x7b\xc4\xe0\x35\xba"
+ "\x22\x6e\x76\xe1\x1a\xf2\x53\xc3"
+ "\x28\xa2\x82\x1f\x61\x69\xad\xc1"
+ "\x7b\x28\x4b\x1e\x6c\x85\x95\x9b"
+ "\x51\xb5\x17\x7f\x12\x69\x8c\x24"
+ "\xd5\xc7\x5a\x5a\x11\x54\xff\x5a"
+ "\xf7\x16\xc3\x91\xa6\xf0\xdc\x0a"
+ "\xb6\xa7\x4a\x0d\x7a\x58\xfe\xa5"
+ "\xf5\xcb\x8f\x7b\x0e\xea\x57\xe7"
+ "\xbd\x79\xd6\x1c\x88\x23\x6c\xf2"
+ "\x4d\x29\x77\x53\x35\x6a\x00\x8d"
+ "\xcd\xa3\x58\xbe\x77\x99\x18\xf8"
+ "\xe6\xe1\x8f\xe9\x37\x8f\xe3\xe2"
+ "\x5a\x8a\x93\x25\xaf\xf3\x78\x80"
+ "\xbe\xa6\x1b\xc6\xac\x8b\x1c\x91"
+ "\x58\xe1\x9f\x89\x35\x9d\x1d\x21"
+ "\x29\x9f\xf4\x99\x02\x27\x0f\xa8"
+ "\x4f\x79\x94\x2b\x33\x2c\xda\xa2"
+ "\x26\x39\x83\x94\xef\x27\xd8\x53"
+ "\x8f\x66\x0d\xe4\x41\x7d\x34\xcd"
+ "\x43\x7c\x95\x0a\x53\xef\x66\xda"
+ "\x7e\x9b\xf3\x93\xaf\xd0\x73\x71"
+ "\xba\x40\x9b\x74\xf8\xd7\xd7\x41"
+ "\x6d\xaf\x72\x9c\x8d\x21\x87\x3c"
+ "\xfd\x0a\x90\xa9\x47\x96\x9e\xd3"
+ "\x88\xee\x73\xcf\x66\x2f\x52\x56"
+ "\x6d\xa9\x80\x4c\xe2\x6f\x62\x88"
+ "\x3f\x0e\x54\x17\x48\x80\x5d\xd3"
+ "\xc3\xda\x25\x3d\xa1\xc8\xcb\x9f"
+ "\x9b\x70\xb3\xa1\xeb\x04\x52\xa1"
+ "\xf2\x22\x0f\xfc\xc8\x18\xfa\xf9"
+ "\x85\x9c\xf1\xac\xeb\x0c\x02\x46"
+ "\x75\xd2\xf5\x2c\xe3\xd2\x59\x94"
+ "\x12\xf3\x3c\xfc\xd7\x92\xfa\x36"
+ "\xba\x61\x34\x38\x7c\xda\x48\x3e"
+ "\x08\xc9\x39\x23\x5e\x02\x2c\x1a"
+ "\x18\x7e\xb4\xd9\xfd\x9e\x40\x02"
+ "\xb1\x33\x37\x32\xe7\xde\xd6\xd0"
+ "\x7c\x58\x65\x4b\xf8\x34\x27\x9c"
+ "\x44\xb4\xbd\xe9\xe9\x4c\x78\x7d"
+ "\x4b\x9f\xce\xb1\xcd\x47\xa5\x37"
+ "\xe5\x6d\xbd\xb9\x43\x94\x0a\xd4"
+ "\xd6\xf9\x04\x5f\xb5\x66\x6c\x1a"
+ "\x35\x12\xe3\x36\x28\x27\x36\x58"
+ "\x01\x2b\x79\xe4\xba\x6d\x10\x7d"
+ "\x65\xdf\x84\x95\xf4\xd5\xb6\x8f"
+ "\x2b\x9f\x96\x00\x86\x60\xf0\x21"
+ "\x76\xa8\x6a\x8c\x28\x1c\xb3\x6b"
+ "\x97\xd7\xb6\x53\x2a\xcc\xab\x40"
+ "\x9d\x62\x79\x58\x52\xe6\x65\xb7"
+ "\xab\x55\x67\x9c\x89\x7c\x03\xb0"
+ "\x73\x59\xc5\x81\xf5\x18\x17\x5c"
+ "\x89\xf3\x78\x35\x44\x62\x78\x72"
+ "\xd0\x96\xeb\x31\xe7\x87\x77\x14"
+ "\x99\x51\xf2\x59\x26\x9e\xb5\xa6"
+ "\x45\xfe\x6e\xbd\x07\x4c\x94\x5a"
+ "\xa5\x7d\xfc\xf1\x2b\x77\xe2\xfe"
+ "\x17\xd4\x84\xa0\xac\xb5\xc7\xda"
+ "\xa9\x1a\xb6\xf3\x74\x11\xb4\x9d"
+ "\xfb\x79\x2e\x04\x2d\x50\x28\x83"
+ "\xbf\xc6\x52\xd3\x34\xd6\xe8\x7a"
+ "\xb6\xea\xe7\xa8\x6c\x15\x1e\x2c"
+ "\x57\xbc\x48\x4e\x5f\x5c\xb6\x92"
+ "\xd2\x49\x77\x81\x6d\x90\x70\xae"
+ "\x98\xa1\x03\x0d\x6b\xb9\x77\x14"
+ "\xf1\x4e\x23\xd3\xf8\x68\xbd\xc2"
+ "\xfe\x04\xb7\x5c\xc5\x17\x60\x8f"
+ "\x65\x54\xa4\x7a\x42\xdc\x18\x0d"
+ "\xb5\xcf\x0f\xd3\xc7\x91\x66\x1b"
+ "\x45\x42\x27\x75\x50\xe5\xee\xb8"
+ "\x7f\x33\x2c\xba\x4a\x92\x4d\x2c"
+ "\x3c\xe3\x0d\x80\x01\xba\x0d\x29"
+ "\xd8\x3c\xe9\x13\x16\x57\xe6\xea"
+ "\x94\x52\xe7\x00\x4d\x30\xb0\x0f"
+ "\x35\xb8\xb8\xa7\xb1\xb5\x3b\x44"
+ "\xe1\x2f\xfd\x88\xed\x43\xe7\x52"
+ "\x10\x93\xb3\x8a\x30\x6b\x0a\xf7"
+ "\x23\xc6\x50\x9d\x4a\xb0\xde\xc3"
+ "\xdc\x9b\x2f\x01\x56\x36\x09\xc5"
+ "\x2f\x6b\xfe\xf1\xd8\x27\x45\x03"
+ "\x30\x5e\x5c\x5b\xb4\x62\x0e\x1a"
+ "\xa9\x21\x2b\x92\x94\x87\x62\x57"
+ "\x4c\x10\x74\x1a\xf1\x0a\xc5\x84"
+ "\x3b\x9e\x72\x02\xd7\xcc\x09\x56"
+ "\xbd\x54\xc1\xf0\xc3\xe3\xb3\xf8"
+ "\xd2\x0d\x61\xcb\xef\xce\x0d\x05"
+ "\xb0\x98\xd9\x8e\x4f\xf9\xbc\x93"
+ "\xa6\xea\xc8\xcf\x10\x53\x4b\xf1"
+ "\xec\xfc\x89\xf9\x64\xb0\x22\xbf"
+ "\x9e\x55\x46\x9f\x7c\x50\x8e\x84"
+ "\x54\x20\x98\xd7\x6c\x40\x1e\xdb"
+ "\x69\x34\x78\x61\x24\x21\x9c\x8a"
+ "\xb3\x62\x31\x8b\x6e\xf5\x2a\x35"
+ "\x86\x13\xb1\x6c\x64\x2e\x41\xa5"
+ "\x05\xf2\x42\xba\xd2\x3a\x0d\x8e"
+ "\x8a\x59\x94\x3c\xcf\x36\x27\x82"
+ "\xc2\x45\xee\x58\xcd\x88\xb4\xec"
+ "\xde\xb2\x96\x0a\xaf\x38\x6f\x88"
+ "\xd7\xd8\xe1\xdf\xb9\x96\xa9\x0a"
+ "\xb1\x95\x28\x86\x20\xe9\x17\x49"
+ "\xa2\x29\x38\xaa\xa5\xe9\x6e\xf1"
+ "\x19\x27\xc0\xd5\x2a\x22\xc3\x0b"
+ "\xdb\x7c\x73\x10\xb9\xba\x89\x76"
+ "\x54\xae\x7d\x71\xb3\x93\xf6\x32"
+ "\xe6\x47\x43\x55\xac\xa0\x0d\xc2"
+ "\x93\x27\x4a\x8e\x0e\x74\x15\xc7"
+ "\x0b\x85\xd9\x0c\xa9\x30\x7a\x3e"
+ "\xea\x8f\x85\x6d\x3a\x12\x4f\x72"
+ "\x69\x58\x7a\x80\xbb\xb5\x97\xf3"
+ "\xcf\x70\xd2\x5d\xdd\x4d\x21\x79"
+ "\x54\x4d\xe4\x05\xe8\xbd\xc2\x62"
+ "\xb1\x3b\x77\x1c\xd6\x5c\xf3\xa0"
+ "\x79\x00\xa8\x6c\x29\xd9\x18\x24"
+ "\x36\xa2\x46\xc0\x96\x65\x7f\xbd"
+ "\x2a\xed\x36\x16\x0c\xaa\x9f\xf4"
+ "\xc5\xb4\xe2\x12\xed\x69\xed\x4f"
+ "\x26\x2c\x39\x52\x89\x98\xe7\x2c"
+ "\x99\xa4\x9e\xa3\x9b\x99\x46\x7a"
+ "\x3a\xdc\xa8\x59\xa3\xdb\xc3\x3b"
+ "\x95\x0d\x3b\x09\x6e\xee\x83\x5d"
+ "\x32\x4d\xed\xab\xfa\x98\x14\x4e"
+ "\xc3\x15\x45\x53\x61\xc4\x93\xbd"
+ "\x90\xf4\x99\x95\x4c\xe6\x76\x92"
+ "\x29\x90\x46\x30\x92\x69\x7d\x13"
+ "\xf2\xa5\xcd\x69\x49\x44\xb2\x0f"
+ "\x63\x40\x36\x5f\x09\xe2\x78\xf8"
+ "\x91\xe3\xe2\xfa\x10\xf7\xc8\x24"
+ "\xa8\x89\x32\x5c\x37\x25\x1d\xb2"
+ "\xea\x17\x8a\x0a\xa9\x64\xc3\x7c"
+ "\x3c\x7c\xbd\xc6\x79\x34\xe7\xe2"
+ "\x85\x8e\xbf\xf8\xde\x92\xa0\xae"
+ "\x20\xc4\xf6\xbb\x1f\x38\x19\x0e"
+ "\xe8\x79\x9c\xa1\x23\xe9\x54\x7e"
+ "\x37\x2f\xe2\x94\x32\xaf\xa0\x23"
+ "\x49\xe4\xc0\xb3\xac\x00\x8f\x36"
+ "\x05\xc4\xa6\x96\xec\x05\x98\x4f"
+ "\x96\x67\x57\x1f\x20\x86\x1b\x2d"
+ "\x69\xe4\x29\x93\x66\x5f\xaf\x6b"
+ "\x88\x26\x2c\x67\x02\x4b\x52\xd0"
+ "\x83\x7a\x43\x1f\xc0\x71\x15\x25"
+ "\x77\x65\x08\x60\x11\x76\x4c\x8d"
+ "\xed\xa9\x27\xc6\xb1\x2a\x2c\x6a"
+ "\x4a\x97\xf5\xc6\xb7\x70\x42\xd3"
+ "\x03\xd1\x24\x95\xec\x6d\xab\x38"
+ "\x72\xce\xe2\x8b\x33\xd7\x51\x09"
+ "\xdc\x45\xe0\x09\x96\x32\xf3\xc4"
+ "\x84\xdc\x73\x73\x2d\x1b\x11\x98"
+ "\xc5\x0e\x69\x28\x94\xc7\xb5\x4d"
+ "\xc8\x8a\xd0\xaa\x13\x2e\x18\x74"
+ "\xdd\xd1\x1e\xf3\x90\xe8\xfc\x9a"
+ "\x72\x4a\x0e\xd1\xe4\xfb\x0d\x96"
+ "\xd1\x0c\x79\x85\x1b\x1c\xfe\xe1"
+ "\x62\x8f\x7a\x73\x32\xab\xc8\x18"
+ "\x69\xe3\x34\x30\xdf\x13\xa6\xe5"
+ "\xe8\x0e\x67\x7f\x81\x11\xb4\x60"
+ "\xc7\xbd\x79\x65\x50\xdc\xc4\x5b"
+ "\xde\x39\xa4\x01\x72\x63\xf3\xd1"
+ "\x64\x4e\xdf\xfc\x27\x92\x37\x0d"
+ "\x57\xcd\x11\x4f\x11\x04\x8e\x1d"
+ "\x16\xf7\xcd\x92\x9a\x99\x30\x14"
+ "\xf1\x7c\x67\x1b\x1f\x41\x0b\xe8"
+ "\x32\xe8\xb8\xc1\x4f\x54\x86\x4f"
+ "\xe5\x79\x81\x73\xcd\x43\x59\x68"
+ "\x73\x02\x3b\x78\x21\x72\x43\x00"
+ "\x49\x17\xf7\x00\xaf\x68\x24\x53"
+ "\x05\x0a\xc3\x33\xe0\x33\x3f\x69"
+ "\xd2\x84\x2f\x0b\xed\xde\x04\xf4"
+ "\x11\x94\x13\x69\x51\x09\x28\xde"
+ "\x57\x5c\xef\xdc\x9a\x49\x1c\x17"
+ "\x97\xf3\x96\xc1\x7f\x5d\x2e\x7d"
+ "\x55\xb8\xb3\x02\x09\xb3\x1f\xe7"
+ "\xc9\x8d\xa3\x36\x34\x8a\x77\x13"
+ "\x30\x63\x4c\xa5\xcd\xc3\xe0\x7e"
+ "\x05\xa1\x7b\x0c\xcb\x74\x47\x31"
+ "\x62\x03\x43\xf1\x87\xb4\xb0\x85"
+ "\x87\x8e\x4b\x25\xc7\xcf\xae\x4b"
+ "\x36\x46\x3e\x62\xbc\x6f\xeb\x5f"
+ "\x73\xac\xe6\x07\xee\xc1\xa1\xd6"
+ "\xc4\xab\xc9\xd6\x89\x45\xe1\xf1"
+ "\x04\x4e\x1a\x6f\xbb\x4f\x3a\xa3"
+ "\xa0\xcb\xa3\x0a\xd8\x71\x35\x55"
+ "\xe4\xbc\x2e\x04\x06\xe6\xff\x5b"
+ "\x1c\xc0\x11\x7c\xc5\x17\xf3\x38"
+ "\xcf\xe9\xba\x0f\x0e\xef\x02\xc2"
+ "\x8d\xc6\xbc\x4b\x67\x20\x95\xd7"
+ "\x2c\x45\x5b\x86\x44\x8c\x6f\x2e"
+ "\x7e\x9f\x1c\x77\xba\x6b\x0e\xa3"
+ "\x69\xdc\xab\x24\x57\x60\x47\xc1"
+ "\xd1\xa5\x9d\x23\xe6\xb1\x37\xfe"
+ "\x93\xd2\x4c\x46\xf9\x0c\xc6\xfb"
+ "\xd6\x9d\x99\x69\xab\x7a\x07\x0c"
+ "\x65\xe7\xc4\x08\x96\xe2\xa5\x01"
+ "\x3f\x46\x07\x05\x7e\xe8\x9a\x90"
+ "\x50\xdc\xe9\x7a\xea\xa1\x39\x6e"
+ "\x66\xe4\x6f\xa5\x5f\xb2\xd9\x5b"
+ "\xf5\xdb\x2a\x32\xf0\x11\x6f\x7c"
+ "\x26\x10\x8f\x3d\x80\xe9\x58\xf7"
+ "\xe0\xa8\x57\xf8\xdb\x0e\xce\x99"
+ "\x63\x19\x3d\xd5\xec\x1b\x77\x69"
+ "\x98\xf6\xe4\x5f\x67\x17\x4b\x09"
+ "\x85\x62\x82\x70\x18\xe2\x9a\x78"
+ "\xe2\x62\xbd\xb4\xf1\x42\xc6\xfb"
+ "\x08\xd0\xbd\xeb\x4e\x09\xf2\xc8"
+ "\x1e\xdc\x3d\x32\x21\x56\x9c\x4f"
+ "\x35\xf3\x61\x06\x72\x84\xc4\x32"
+ "\xf2\xf1\xfa\x0b\x2f\xc3\xdb\x02"
+ "\x04\xc2\xde\x57\x64\x60\x8d\xcf"
+ "\xcb\x86\x5d\x97\x3e\xb1\x9c\x01"
+ "\xd6\x28\x8f\x99\xbc\x46\xeb\x05"
+ "\xaf\x7e\xb8\x21\x2a\x56\x85\x1c"
+ "\xb3\x71\xa0\xde\xca\x96\xf1\x78"
+ "\x49\xa2\x99\x81\x80\x5c\x01\xf5"
+ "\xa0\xa2\x56\x63\xe2\x70\x07\xa5"
+ "\x95\xd6\x85\xeb\x36\x9e\xa9\x51"
+ "\x66\x56\x5f\x1d\x02\x19\xe2\xf6"
+ "\x4f\x73\x38\x09\x75\x64\x48\xe0"
+ "\xf1\x7e\x0e\xe8\x9d\xf9\xed\x94"
+ "\xfe\x16\x26\x62\x49\x74\xf4\xb0"
+ "\xd4\xa9\x6c\xb0\xfd\x53\xe9\x81"
+ "\xe0\x7a\xbf\xcf\xb5\xc4\x01\x81"
+ "\x79\x99\x77\x01\x3b\xe9\xa2\xb6"
+ "\xe6\x6a\x8a\x9e\x56\x1c\x8d\x1e"
+ "\x8f\x06\x55\x2c\x6c\xdc\x92\x87"
+ "\x64\x3b\x4b\x19\xa1\x13\x64\x1d"
+ "\x4a\xe9\xc0\x00\xb8\x95\xef\x6b"
+ "\x1a\x86\x6d\x37\x52\x02\xc2\xe0"
+ "\xc8\xbb\x42\x0c\x02\x21\x4a\xc9"
+ "\xef\xa0\x54\xe4\x5e\x16\x53\x81"
+ "\x70\x62\x10\xaf\xde\xb8\xb5\xd3"
+ "\xe8\x5e\x6c\xc3\x8a\x3e\x18\x07"
+ "\xf2\x2f\x7d\xa7\xe1\x3d\x4e\xb4"
+ "\x26\xa7\xa3\x93\x86\xb2\x04\x1e"
+ "\x53\x5d\x86\xd6\xde\x65\xca\xe3"
+ "\x4e\xc1\xcf\xef\xc8\x70\x1b\x83"
+ "\x13\xdd\x18\x8b\x0d\x76\xd2\xf6"
+ "\x37\x7a\x93\x7a\x50\x11\x9f\x96"
+ "\x86\x25\xfd\xac\xdc\xbe\x18\x93"
+ "\x19\x6b\xec\x58\x4f\xb9\x75\xa7"
+ "\xdd\x3f\x2f\xec\xc8\x5a\x84\xab"
+ "\xd5\xe4\x8a\x07\xf6\x4d\x23\xd6"
+ "\x03\xfb\x03\x6a\xea\x66\xbf\xd4"
+ "\xb1\x34\xfb\x78\xe9\x55\xdc\x7c"
+ "\x3d\x9c\xe5\x9a\xac\xc3\x7a\x80"
+ "\x24\x6d\xa0\xef\x25\x7c\xb7\xea"
+ "\xce\x4d\x5f\x18\x60\xce\x87\x22"
+ "\x66\x2f\xd5\xdd\xdd\x02\x21\x75"
+ "\x82\xa0\x1f\x58\xc6\xd3\x62\xf7"
+ "\x32\xd8\xaf\x1e\x07\x77\x51\x96"
+ "\xd5\x6b\x1e\x7e\x80\x02\xe8\x67"
+ "\xea\x17\x0b\x10\xd2\x3f\x28\x25"
+ "\x4f\x05\x77\x02\x14\x69\xf0\x2c"
+ "\xbe\x0c\xf1\x74\x30\xd1\xb9\x9b"
+ "\xfc\x8c\xbb\x04\x16\xd9\xba\xc3"
+ "\xbc\x91\x8a\xc4\x30\xa4\xb0\x12"
+ "\x4c\x21\x87\xcb\xc9\x1d\x16\x96"
+ "\x07\x6f\x23\x54\xb9\x6f\x79\xe5"
+ "\x64\xc0\x64\xda\xb1\xae\xdd\x60"
+ "\x6c\x1a\x9d\xd3\x04\x8e\x45\xb0"
+ "\x92\x61\xd0\x48\x81\xed\x5e\x1d"
+ "\xa0\xc9\xa4\x33\xc7\x13\x51\x5d"
+ "\x7f\x83\x73\xb6\x70\x18\x65\x3e"
+ "\x2f\x0e\x7a\x12\x39\x98\xab\xd8"
+ "\x7e\x6f\xa3\xd1\xba\x56\xad\xbd"
+ "\xf0\x03\x01\x1c\x85\x35\x9f\xeb"
+ "\x19\x63\xa1\xaf\xfe\x2d\x35\x50"
+ "\x39\xa0\x65\x7c\x95\x7e\x6b\xfe"
+ "\xc1\xac\x07\x7c\x98\x4f\xbe\x57"
+ "\xa7\x22\xec\xe2\x7e\x29\x09\x53"
+ "\xe8\xbf\xb4\x7e\x3f\x8f\xfc\x14"
+ "\xce\x54\xf9\x18\x58\xb5\xff\x44"
+ "\x05\x9d\xce\x1b\xb6\x82\x23\xc8"
+ "\x2e\xbc\x69\xbb\x4a\x29\x0f\x65"
+ "\x94\xf0\x63\x06\x0e\xef\x8c\xbd"
+ "\xff\xfd\xb0\x21\x6e\x57\x05\x75"
+ "\xda\xd5\xc4\xeb\x8d\x32\xf7\x50"
+ "\xd3\x6f\x22\xed\x5f\x8e\xa2\x5b"
+ "\x80\x8c\xc8\x78\x40\x24\x4b\x89"
+ "\x30\xce\x7a\x97\x0e\xc4\xaf\xef"
+ "\x9b\xb4\xcd\x66\x74\x14\x04\x2b"
+ "\xf7\xce\x0b\x1c\x6e\xc2\x78\x8c"
+ "\xca\xc5\xd0\x1c\x95\x4a\x91\x2d"
+ "\xa7\x20\xeb\x86\x52\xb7\x67\xd8"
+ "\x0c\xd6\x04\x14\xde\x51\x74\x75"
+ "\xe7\x11\xb4\x87\xa3\x3d\x2d\xad"
+ "\x4f\xef\xa0\x0f\x70\x00\x6d\x13"
+ "\x19\x1d\x41\x50\xe9\xd8\xf0\x32"
+ "\x71\xbc\xd3\x11\xf2\xac\xbe\xaf"
+ "\x75\x46\x65\x4e\x07\x34\x37\xa3"
+ "\x89\xfe\x75\xd4\x70\x4c\xc6\x3f"
+ "\x69\x24\x0e\x38\x67\x43\x8c\xde"
+ "\x06\xb5\xb8\xe7\xc4\xf0\x41\x8f"
+ "\xf0\xbd\x2f\x0b\xb9\x18\xf8\xde"
+ "\x64\xb1\xdb\xee\x00\x50\x77\xe1"
+ "\xc7\xff\xa6\xfa\xdd\x70\xf4\xe3"
+ "\x93\xe9\x77\x35\x3d\x4b\x2f\x2b"
+ "\x6d\x55\xf0\xfc\x88\x54\x4e\x89"
+ "\xc1\x8a\x23\x31\x2d\x14\x2a\xb8"
+ "\x1b\x15\xdd\x9e\x6e\x7b\xda\x05"
+ "\x91\x7d\x62\x64\x96\x72\xde\xfc"
+ "\xc1\xec\xf0\x23\x51\x6f\xdb\x5b"
+ "\x1d\x08\x57\xce\x09\xb8\xf6\xcd"
+ "\x8d\x95\xf2\x20\xbf\x0f\x20\x57"
+ "\x98\x81\x84\x4f\x15\x5c\x76\xe7"
+ "\x3e\x0a\x3a\x6c\xc4\x8a\xbe\x78"
+ "\x74\x77\xc3\x09\x4b\x5d\x48\xe4"
+ "\xc8\xcb\x0b\xea\x17\x28\xcf\xcf"
+ "\x31\x32\x44\xa4\xe5\x0e\x1a\x98"
+ "\x94\xc4\xf0\xff\xae\x3e\x44\xe8"
+ "\xa5\xb3\xb5\x37\x2f\xe8\xaf\x6f"
+ "\x28\xc1\x37\x5f\x31\xd2\xb9\x33"
+ "\xb1\xb2\x52\x94\x75\x2c\x29\x59"
+ "\x06\xc2\x25\xe8\x71\x65\x4e\xed"
+ "\xc0\x9c\xb1\xbb\x25\xdc\x6c\xe7"
+ "\x4b\xa5\x7a\x54\x7a\x60\xff\x7a"
+ "\xe0\x50\x40\x96\x35\x63\xe4\x0b"
+ "\x76\xbd\xa4\x65\x00\x1b\x57\x88"
+ "\xae\xed\x39\x88\x42\x11\x3c\xed"
+ "\x85\x67\x7d\xb9\x68\x82\xe9\x43"
+ "\x3c\x47\x53\xfa\xe8\xf8\x9f\x1f"
+ "\x9f\xef\x0f\xf7\x30\xd9\x30\x0e"
+ "\xb9\x9f\x69\x18\x2f\x7e\xf8\xf8"
+ "\xf8\x8c\x0f\xd4\x02\x4d\xea\xcd"
+ "\x0a\x9c\x6f\x71\x6d\x5a\x4c\x60"
+ "\xce\x20\x56\x32\xc6\xc5\x99\x1f"
+ "\x09\xe6\x4e\x18\x1a\x15\x13\xa8"
+ "\x7d\xb1\x6b\xc0\xb2\x6d\xf8\x26"
+ "\x66\xf8\x3d\x18\x74\x70\x66\x7a"
+ "\x34\x17\xde\xba\x47\xf1\x06\x18"
+ "\xcb\xaf\xeb\x4a\x1e\x8f\xa7\x77"
+ "\xe0\x3b\x78\x62\x66\xc9\x10\xea"
+ "\x1f\xb7\x29\x0a\x45\xa1\x1d\x1e"
+ "\x1d\xe2\x65\x61\x50\x9c\xd7\x05"
+ "\xf2\x0b\x5b\x12\x61\x02\xc8\xe5"
+ "\x63\x4f\x20\x0c\x07\x17\x33\x5e"
+ "\x03\x9a\x53\x0f\x2e\x55\xfe\x50"
+ "\x43\x7d\xd0\xb6\x7e\x5a\xda\xae"
+ "\x58\xef\x15\xa9\x83\xd9\x46\xb1"
+ "\x42\xaa\xf5\x02\x6c\xce\x92\x06"
+ "\x1b\xdb\x66\x45\x91\x79\xc2\x2d"
+ "\xe6\x53\xd3\x14\xfd\xbb\x44\x63"
+ "\xc6\xd7\x3d\x7a\x0c\x75\x78\x9d"
+ "\x5c\xa6\x39\xb3\xe5\x63\xca\x8b"
+ "\xfe\xd3\xef\x60\x83\xf6\x8e\x70"
+ "\xb6\x67\xc7\x77\xed\x23\xef\x4c"
+ "\xf0\xed\x2d\x07\x59\x6f\xc1\x01"
+ "\x34\x37\x08\xab\xd9\x1f\x09\xb1"
+ "\xce\x5b\x17\xff\x74\xf8\x9c\xd5"
+ "\x2c\x56\x39\x79\x0f\x69\x44\x75"
+ "\x58\x27\x01\xc4\xbf\xa7\xa1\x1d"
+ "\x90\x17\x77\x86\x5a\x3f\xd9\xd1"
+ "\x0e\xa0\x10\xf8\xec\x1e\xa5\x7f"
+ "\x5e\x36\xd1\xe3\x04\x2c\x70\xf7"
+ "\x8e\xc0\x98\x2f\x6c\x94\x2b\x41"
+ "\xb7\x60\x00\xb7\x2e\xb8\x02\x8d"
+ "\xb8\xb0\xd3\x86\xba\x1d\xd7\x90"
+ "\xd6\xb6\xe1\xfc\xd7\xd8\x28\x06"
+ "\x63\x9b\xce\x61\x24\x79\xc0\x70"
+ "\x52\xd0\xb6\xd4\x28\x95\x24\x87"
+ "\x03\x1f\xb7\x9a\xda\xa3\xfb\x52"
+ "\x5b\x68\xe7\x4c\x8c\x24\xe1\x42"
+ "\xf7\xd5\xfd\xad\x06\x32\x9f\xba"
+ "\xc1\xfc\xdd\xc6\xfc\xfc\xb3\x38"
+ "\x74\x56\x58\x40\x02\x37\x52\x2c"
+ "\x55\xcc\xb3\x9e\x7a\xe9\xd4\x38"
+ "\x41\x5e\x0c\x35\xe2\x11\xd1\x13"
+ "\xf8\xb7\x8d\x72\x6b\x22\x2a\xb0"
+ "\xdb\x08\xba\x35\xb9\x3f\xc8\xd3"
+ "\x24\x90\xec\x58\xd2\x09\xc7\x2d"
+ "\xed\x38\x80\x36\x72\x43\x27\x49"
+ "\x4a\x80\x8a\xa2\xe8\xd3\xda\x30"
+ "\x7d\xb6\x82\x37\x86\x92\x86\x3e"
+ "\x08\xb2\x28\x5a\x55\x44\x24\x7d"
+ "\x40\x48\x8a\xb6\x89\x58\x08\xa0"
+ "\xd6\x6d\x3a\x17\xbf\xf6\x54\xa2"
+ "\xf5\xd3\x8c\x0f\x78\x12\x57\x8b"
+ "\xd5\xc2\xfd\x58\x5b\x7f\x38\xe3"
+ "\xcc\xb7\x7c\x48\xb3\x20\xe8\x81"
+ "\x14\x32\x45\x05\xe0\xdb\x9f\x75"
+ "\x85\xb4\x6a\xfc\x95\xe3\x54\x22"
+ "\x12\xee\x30\xfe\xd8\x30\xef\x34"
+ "\x50\xab\x46\x30\x98\x2f\xb7\xc0"
+ "\x15\xa2\x83\xb6\xf2\x06\x21\xa2"
+ "\xc3\x26\x37\x14\xd1\x4d\xb5\x10"
+ "\x52\x76\x4d\x6a\xee\xb5\x2b\x15"
+ "\xb7\xf9\x51\xe8\x2a\xaf\xc7\xfa"
+ "\x77\xaf\xb0\x05\x4d\xd1\x68\x8e"
+ "\x74\x05\x9f\x9d\x93\xa5\x3e\x7f"
+ "\x4e\x5f\x9d\xcb\x09\xc7\x83\xe3"
+ "\x02\x9d\x27\x1f\xef\x85\x05\x8d"
+ "\xec\x55\x88\x0f\x0d\x7c\x4c\xe8"
+ "\xa1\x75\xa0\xd8\x06\x47\x14\xef"
+ "\xaa\x61\xcf\x26\x15\xad\xd8\xa3"
+ "\xaa\x75\xf2\x78\x4a\x5a\x61\xdf"
+ "\x8b\xc7\x04\xbc\xb2\x32\xd2\x7e"
+ "\x42\xee\xb4\x2f\x51\xff\x7b\x2e"
+ "\xd3\x02\xe8\xdc\x5d\x0d\x50\xdc"
+ "\xae\xb7\x46\xf9\xa8\xe6\xd0\x16"
+ "\xcc\xe6\x2c\x81\xc7\xad\xe9\xf0"
+ "\x05\x72\x6d\x3d\x0a\x7a\xa9\x02"
+ "\xac\x82\x93\x6e\xb6\x1c\x28\xfc"
+ "\x44\x12\xfb\x73\x77\xd4\x13\x39"
+ "\x29\x88\x8a\xf3\x5c\xa6\x36\xa0"
+ "\x2a\xed\x7e\xb1\x1d\xd6\x4c\x6b"
+ "\x41\x01\x18\x5d\x5d\x07\x97\xa6"
+ "\x4b\xef\x31\x18\xea\xac\xb1\x84"
+ "\x21\xed\xda\x86",
.rlen = 4100,
},
};
static struct cipher_testvec aes_ctr_dec_tv_template[] = {
{ /* From RFC 3686 */
- .key = { 0xae, 0x68, 0x52, 0xf8, 0x12, 0x10, 0x67, 0xcc,
- 0x4b, 0xf7, 0xa5, 0x76, 0x55, 0x77, 0xf3, 0x9e,
- 0x00, 0x00, 0x00, 0x30 },
+ .key = "\xae\x68\x52\xf8\x12\x10\x67\xcc"
+ "\x4b\xf7\xa5\x76\x55\x77\xf3\x9e"
+ "\x00\x00\x00\x30",
.klen = 20,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0xe4, 0x09, 0x5d, 0x4f, 0xb7, 0xa7, 0xb3, 0x79,
- 0x2d, 0x61, 0x75, 0xa3, 0x26, 0x13, 0x11, 0xb8 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\xe4\x09\x5d\x4f\xb7\xa7\xb3\x79"
+ "\x2d\x61\x75\xa3\x26\x13\x11\xb8",
.ilen = 16,
- .result = { "Single block msg" },
+ .result = "Single block msg",
.rlen = 16,
}, {
- .key = { 0x7e, 0x24, 0x06, 0x78, 0x17, 0xfa, 0xe0, 0xd7,
- 0x43, 0xd6, 0xce, 0x1f, 0x32, 0x53, 0x91, 0x63,
- 0x00, 0x6c, 0xb6, 0xdb },
+ .key = "\x7e\x24\x06\x78\x17\xfa\xe0\xd7"
+ "\x43\xd6\xce\x1f\x32\x53\x91\x63"
+ "\x00\x6c\xb6\xdb",
.klen = 20,
- .iv = { 0xc0, 0x54, 0x3b, 0x59, 0xda, 0x48, 0xd9, 0x0b },
- .input = { 0x51, 0x04, 0xa1, 0x06, 0x16, 0x8a, 0x72, 0xd9,
- 0x79, 0x0d, 0x41, 0xee, 0x8e, 0xda, 0xd3, 0x88,
- 0xeb, 0x2e, 0x1e, 0xfc, 0x46, 0xda, 0x57, 0xc8,
- 0xfc, 0xe6, 0x30, 0xdf, 0x91, 0x41, 0xbe, 0x28 },
- .ilen = 32,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .iv = "\xc0\x54\x3b\x59\xda\x48\xd9\x0b",
+ .input = "\x51\x04\xa1\x06\x16\x8a\x72\xd9"
+ "\x79\x0d\x41\xee\x8e\xda\xd3\x88"
+ "\xeb\x2e\x1e\xfc\x46\xda\x57\xc8"
+ "\xfc\xe6\x30\xdf\x91\x41\xbe\x28",
+ .ilen = 32,
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.rlen = 32,
}, {
- .key = { 0x16, 0xaf, 0x5b, 0x14, 0x5f, 0xc9, 0xf5, 0x79,
- 0xc1, 0x75, 0xf9, 0x3e, 0x3b, 0xfb, 0x0e, 0xed,
- 0x86, 0x3d, 0x06, 0xcc, 0xfd, 0xb7, 0x85, 0x15,
- 0x00, 0x00, 0x00, 0x48 },
- .klen = 28,
- .iv = { 0x36, 0x73, 0x3c, 0x14, 0x7d, 0x6d, 0x93, 0xcb },
- .input = { 0x4b, 0x55, 0x38, 0x4f, 0xe2, 0x59, 0xc9, 0xc8,
- 0x4e, 0x79, 0x35, 0xa0, 0x03, 0xcb, 0xe9, 0x28 },
- .ilen = 16,
- .result = { "Single block msg" },
+ .key = "\x16\xaf\x5b\x14\x5f\xc9\xf5\x79"
+ "\xc1\x75\xf9\x3e\x3b\xfb\x0e\xed"
+ "\x86\x3d\x06\xcc\xfd\xb7\x85\x15"
+ "\x00\x00\x00\x48",
+ .klen = 28,
+ .iv = "\x36\x73\x3c\x14\x7d\x6d\x93\xcb",
+ .input = "\x4b\x55\x38\x4f\xe2\x59\xc9\xc8"
+ "\x4e\x79\x35\xa0\x03\xcb\xe9\x28",
+ .ilen = 16,
+ .result = "Single block msg",
.rlen = 16,
}, {
- .key = { 0x7c, 0x5c, 0xb2, 0x40, 0x1b, 0x3d, 0xc3, 0x3c,
- 0x19, 0xe7, 0x34, 0x08, 0x19, 0xe0, 0xf6, 0x9c,
- 0x67, 0x8c, 0x3d, 0xb8, 0xe6, 0xf6, 0xa9, 0x1a,
- 0x00, 0x96, 0xb0, 0x3b },
+ .key = "\x7c\x5c\xb2\x40\x1b\x3d\xc3\x3c"
+ "\x19\xe7\x34\x08\x19\xe0\xf6\x9c"
+ "\x67\x8c\x3d\xb8\xe6\xf6\xa9\x1a"
+ "\x00\x96\xb0\x3b",
.klen = 28,
- .iv = { 0x02, 0x0c, 0x6e, 0xad, 0xc2, 0xcb, 0x50, 0x0d },
- .input = { 0x45, 0x32, 0x43, 0xfc, 0x60, 0x9b, 0x23, 0x32,
- 0x7e, 0xdf, 0xaa, 0xfa, 0x71, 0x31, 0xcd, 0x9f,
- 0x84, 0x90, 0x70, 0x1c, 0x5a, 0xd4, 0xa7, 0x9c,
- 0xfc, 0x1f, 0xe0, 0xff, 0x42, 0xf4, 0xfb, 0x00 },
+ .iv = "\x02\x0c\x6e\xad\xc2\xcb\x50\x0d",
+ .input = "\x45\x32\x43\xfc\x60\x9b\x23\x32"
+ "\x7e\xdf\xaa\xfa\x71\x31\xcd\x9f"
+ "\x84\x90\x70\x1c\x5a\xd4\xa7\x9c"
+ "\xfc\x1f\xe0\xff\x42\xf4\xfb\x00",
.ilen = 32,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
- .rlen = 32,
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
+ .rlen = 32,
}, {
- .key = { 0x77, 0x6b, 0xef, 0xf2, 0x85, 0x1d, 0xb0, 0x6f,
- 0x4c, 0x8a, 0x05, 0x42, 0xc8, 0x69, 0x6f, 0x6c,
- 0x6a, 0x81, 0xaf, 0x1e, 0xec, 0x96, 0xb4, 0xd3,
- 0x7f, 0xc1, 0xd6, 0x89, 0xe6, 0xc1, 0xc1, 0x04,
- 0x00, 0x00, 0x00, 0x60 },
+ .key = "\x77\x6b\xef\xf2\x85\x1d\xb0\x6f"
+ "\x4c\x8a\x05\x42\xc8\x69\x6f\x6c"
+ "\x6a\x81\xaf\x1e\xec\x96\xb4\xd3"
+ "\x7f\xc1\xd6\x89\xe6\xc1\xc1\x04"
+ "\x00\x00\x00\x60",
.klen = 36,
- .iv = { 0xdb, 0x56, 0x72, 0xc9, 0x7a, 0xa8, 0xf0, 0xb2 },
- .input = { 0x14, 0x5a, 0xd0, 0x1d, 0xbf, 0x82, 0x4e, 0xc7,
- 0x56, 0x08, 0x63, 0xdc, 0x71, 0xe3, 0xe0, 0xc0 },
+ .iv = "\xdb\x56\x72\xc9\x7a\xa8\xf0\xb2",
+ .input = "\x14\x5a\xd0\x1d\xbf\x82\x4e\xc7"
+ "\x56\x08\x63\xdc\x71\xe3\xe0\xc0",
.ilen = 16,
- .result = { "Single block msg" },
- .rlen = 16,
- }, {
- .key = { 0xf6, 0xd6, 0x6d, 0x6b, 0xd5, 0x2d, 0x59, 0xbb,
- 0x07, 0x96, 0x36, 0x58, 0x79, 0xef, 0xf8, 0x86,
- 0xc6, 0x6d, 0xd5, 0x1a, 0x5b, 0x6a, 0x99, 0x74,
- 0x4b, 0x50, 0x59, 0x0c, 0x87, 0xa2, 0x38, 0x84,
- 0x00, 0xfa, 0xac, 0x24 },
- .klen = 36,
- .iv = { 0xc1, 0x58, 0x5e, 0xf1, 0x5a, 0x43, 0xd8, 0x75 },
- .input = { 0xf0, 0x5e, 0x23, 0x1b, 0x38, 0x94, 0x61, 0x2c,
- 0x49, 0xee, 0x00, 0x0b, 0x80, 0x4e, 0xb2, 0xa9,
- 0xb8, 0x30, 0x6b, 0x50, 0x8f, 0x83, 0x9d, 0x6a,
- 0x55, 0x30, 0x83, 0x1d, 0x93, 0x44, 0xaf, 0x1c },
+ .result = "Single block msg",
+ .rlen = 16,
+ }, {
+ .key = "\xf6\xd6\x6d\x6b\xd5\x2d\x59\xbb"
+ "\x07\x96\x36\x58\x79\xef\xf8\x86"
+ "\xc6\x6d\xd5\x1a\x5b\x6a\x99\x74"
+ "\x4b\x50\x59\x0c\x87\xa2\x38\x84"
+ "\x00\xfa\xac\x24",
+ .klen = 36,
+ .iv = "\xc1\x58\x5e\xf1\x5a\x43\xd8\x75",
+ .input = "\xf0\x5e\x23\x1b\x38\x94\x61\x2c"
+ "\x49\xee\x00\x0b\x80\x4e\xb2\xa9"
+ "\xb8\x30\x6b\x50\x8f\x83\x9d\x6a"
+ "\x55\x30\x83\x1d\x93\x44\xaf\x1c",
.ilen = 32,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.rlen = 32,
},
};
static struct aead_testvec aes_gcm_enc_tv_template[] = {
{ /* From McGrew & Viega - http://citeseer.ist.psu.edu/656989.html */
+ .key = zeroed_string,
.klen = 16,
- .result = { 0x58, 0xe2, 0xfc, 0xce, 0xfa, 0x7e, 0x30, 0x61,
- 0x36, 0x7f, 0x1d, 0x57, 0xa4, 0xe7, 0x45, 0x5a },
+ .result = "\x58\xe2\xfc\xce\xfa\x7e\x30\x61"
+ "\x36\x7f\x1d\x57\xa4\xe7\x45\x5a",
.rlen = 16,
}, {
+ .key = zeroed_string,
.klen = 16,
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0x03, 0x88, 0xda, 0xce, 0x60, 0xb6, 0xa3, 0x92,
- 0xf3, 0x28, 0xc2, 0xb9, 0x71, 0xb2, 0xfe, 0x78,
- 0xab, 0x6e, 0x47, 0xd4, 0x2c, 0xec, 0x13, 0xbd,
- 0xf5, 0x3a, 0x67, 0xb2, 0x12, 0x57, 0xbd, 0xdf },
+ .result = "\x03\x88\xda\xce\x60\xb6\xa3\x92"
+ "\xf3\x28\xc2\xb9\x71\xb2\xfe\x78"
+ "\xab\x6e\x47\xd4\x2c\xec\x13\xbd"
+ "\xf5\x3a\x67\xb2\x12\x57\xbd\xdf",
.rlen = 32,
}, {
- .key = { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 },
+ .key = "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08",
.klen = 16,
- .iv = { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88 },
- .input = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
- 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
- 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
- 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
- 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
- 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
- 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
- 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 },
+ .iv = "\xca\xfe\xba\xbe\xfa\xce\xdb\xad"
+ "\xde\xca\xf8\x88",
+ .input = "\xd9\x31\x32\x25\xf8\x84\x06\xe5"
+ "\xa5\x59\x09\xc5\xaf\xf5\x26\x9a"
+ "\x86\xa7\xa9\x53\x15\x34\xf7\xda"
+ "\x2e\x4c\x30\x3d\x8a\x31\x8a\x72"
+ "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
+ "\x2f\xcf\x0e\x24\x49\xa6\xb5\x25"
+ "\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57"
+ "\xba\x63\x7b\x39\x1a\xaf\xd2\x55",
.ilen = 64,
- .result = { 0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24,
- 0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c,
- 0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0,
- 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e,
- 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c,
- 0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05,
- 0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97,
- 0x3d, 0x58, 0xe0, 0x91, 0x47, 0x3f, 0x59, 0x85,
- 0x4d, 0x5c, 0x2a, 0xf3, 0x27, 0xcd, 0x64, 0xa6,
- 0x2c, 0xf3, 0x5a, 0xbd, 0x2b, 0xa6, 0xfa, 0xb4 },
+ .result = "\x42\x83\x1e\xc2\x21\x77\x74\x24"
+ "\x4b\x72\x21\xb7\x84\xd0\xd4\x9c"
+ "\xe3\xaa\x21\x2f\x2c\x02\xa4\xe0"
+ "\x35\xc1\x7e\x23\x29\xac\xa1\x2e"
+ "\x21\xd5\x14\xb2\x54\x66\x93\x1c"
+ "\x7d\x8f\x6a\x5a\xac\x84\xaa\x05"
+ "\x1b\xa3\x0b\x39\x6a\x0a\xac\x97"
+ "\x3d\x58\xe0\x91\x47\x3f\x59\x85"
+ "\x4d\x5c\x2a\xf3\x27\xcd\x64\xa6"
+ "\x2c\xf3\x5a\xbd\x2b\xa6\xfa\xb4",
.rlen = 80,
}, {
- .key = { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 },
+ .key = "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08",
.klen = 16,
- .iv = { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88 },
- .input = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
- 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
- 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
- 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
- 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
- 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
- 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
- 0xba, 0x63, 0x7b, 0x39 },
+ .iv = "\xca\xfe\xba\xbe\xfa\xce\xdb\xad"
+ "\xde\xca\xf8\x88",
+ .input = "\xd9\x31\x32\x25\xf8\x84\x06\xe5"
+ "\xa5\x59\x09\xc5\xaf\xf5\x26\x9a"
+ "\x86\xa7\xa9\x53\x15\x34\xf7\xda"
+ "\x2e\x4c\x30\x3d\x8a\x31\x8a\x72"
+ "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
+ "\x2f\xcf\x0e\x24\x49\xa6\xb5\x25"
+ "\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57"
+ "\xba\x63\x7b\x39",
.ilen = 60,
- .assoc = { 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xab, 0xad, 0xda, 0xd2 },
+ .assoc = "\xfe\xed\xfa\xce\xde\xad\xbe\xef"
+ "\xfe\xed\xfa\xce\xde\xad\xbe\xef"
+ "\xab\xad\xda\xd2",
.alen = 20,
- .result = { 0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24,
- 0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c,
- 0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0,
- 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e,
- 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c,
- 0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05,
- 0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97,
- 0x3d, 0x58, 0xe0, 0x91,
- 0x5b, 0xc9, 0x4f, 0xbc, 0x32, 0x21, 0xa5, 0xdb,
- 0x94, 0xfa, 0xe9, 0x5a, 0xe7, 0x12, 0x1a, 0x47 },
+ .result = "\x42\x83\x1e\xc2\x21\x77\x74\x24"
+ "\x4b\x72\x21\xb7\x84\xd0\xd4\x9c"
+ "\xe3\xaa\x21\x2f\x2c\x02\xa4\xe0"
+ "\x35\xc1\x7e\x23\x29\xac\xa1\x2e"
+ "\x21\xd5\x14\xb2\x54\x66\x93\x1c"
+ "\x7d\x8f\x6a\x5a\xac\x84\xaa\x05"
+ "\x1b\xa3\x0b\x39\x6a\x0a\xac\x97"
+ "\x3d\x58\xe0\x91"
+ "\x5b\xc9\x4f\xbc\x32\x21\xa5\xdb"
+ "\x94\xfa\xe9\x5a\xe7\x12\x1a\x47",
.rlen = 76,
}, {
+ .key = zeroed_string,
.klen = 24,
- .result = { 0xcd, 0x33, 0xb2, 0x8a, 0xc7, 0x73, 0xf7, 0x4b,
- 0xa0, 0x0e, 0xd1, 0xf3, 0x12, 0x57, 0x24, 0x35 },
+ .result = "\xcd\x33\xb2\x8a\xc7\x73\xf7\x4b"
+ "\xa0\x0e\xd1\xf3\x12\x57\x24\x35",
.rlen = 16,
}, {
+ .key = zeroed_string,
.klen = 24,
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0x98, 0xe7, 0x24, 0x7c, 0x07, 0xf0, 0xfe, 0x41,
- 0x1c, 0x26, 0x7e, 0x43, 0x84, 0xb0, 0xf6, 0x00,
- 0x2f, 0xf5, 0x8d, 0x80, 0x03, 0x39, 0x27, 0xab,
- 0x8e, 0xf4, 0xd4, 0x58, 0x75, 0x14, 0xf0, 0xfb },
+ .result = "\x98\xe7\x24\x7c\x07\xf0\xfe\x41"
+ "\x1c\x26\x7e\x43\x84\xb0\xf6\x00"
+ "\x2f\xf5\x8d\x80\x03\x39\x27\xab"
+ "\x8e\xf4\xd4\x58\x75\x14\xf0\xfb",
.rlen = 32,
}, {
- .key = { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
- 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c },
+ .key = "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08"
+ "\xfe\xff\xe9\x92\x86\x65\x73\x1c",
.klen = 24,
- .iv = { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88 },
- .input = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
- 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
- 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
- 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
- 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
- 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
- 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
- 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 },
+ .iv = "\xca\xfe\xba\xbe\xfa\xce\xdb\xad"
+ "\xde\xca\xf8\x88",
+ .input = "\xd9\x31\x32\x25\xf8\x84\x06\xe5"
+ "\xa5\x59\x09\xc5\xaf\xf5\x26\x9a"
+ "\x86\xa7\xa9\x53\x15\x34\xf7\xda"
+ "\x2e\x4c\x30\x3d\x8a\x31\x8a\x72"
+ "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
+ "\x2f\xcf\x0e\x24\x49\xa6\xb5\x25"
+ "\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57"
+ "\xba\x63\x7b\x39\x1a\xaf\xd2\x55",
.ilen = 64,
- .result = { 0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41,
- 0xeb, 0x06, 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57,
- 0x85, 0x9e, 0x1c, 0xea, 0xa6, 0xef, 0xd9, 0x84,
- 0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, 0xe1, 0x9c,
- 0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25,
- 0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47,
- 0x18, 0xe2, 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9,
- 0xcc, 0xda, 0x27, 0x10, 0xac, 0xad, 0xe2, 0x56,
- 0x99, 0x24, 0xa7, 0xc8, 0x58, 0x73, 0x36, 0xbf,
- 0xb1, 0x18, 0x02, 0x4d, 0xb8, 0x67, 0x4a, 0x14 },
+ .result = "\x39\x80\xca\x0b\x3c\x00\xe8\x41"
+ "\xeb\x06\xfa\xc4\x87\x2a\x27\x57"
+ "\x85\x9e\x1c\xea\xa6\xef\xd9\x84"
+ "\x62\x85\x93\xb4\x0c\xa1\xe1\x9c"
+ "\x7d\x77\x3d\x00\xc1\x44\xc5\x25"
+ "\xac\x61\x9d\x18\xc8\x4a\x3f\x47"
+ "\x18\xe2\x44\x8b\x2f\xe3\x24\xd9"
+ "\xcc\xda\x27\x10\xac\xad\xe2\x56"
+ "\x99\x24\xa7\xc8\x58\x73\x36\xbf"
+ "\xb1\x18\x02\x4d\xb8\x67\x4a\x14",
.rlen = 80,
}, {
- .key = { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
- 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c },
+ .key = "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08"
+ "\xfe\xff\xe9\x92\x86\x65\x73\x1c",
.klen = 24,
- .iv = { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88 },
- .input = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
- 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
- 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
- 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
- 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
- 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
- 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
- 0xba, 0x63, 0x7b, 0x39 },
+ .iv = "\xca\xfe\xba\xbe\xfa\xce\xdb\xad"
+ "\xde\xca\xf8\x88",
+ .input = "\xd9\x31\x32\x25\xf8\x84\x06\xe5"
+ "\xa5\x59\x09\xc5\xaf\xf5\x26\x9a"
+ "\x86\xa7\xa9\x53\x15\x34\xf7\xda"
+ "\x2e\x4c\x30\x3d\x8a\x31\x8a\x72"
+ "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
+ "\x2f\xcf\x0e\x24\x49\xa6\xb5\x25"
+ "\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57"
+ "\xba\x63\x7b\x39",
.ilen = 60,
- .assoc = { 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xab, 0xad, 0xda, 0xd2 },
+ .assoc = "\xfe\xed\xfa\xce\xde\xad\xbe\xef"
+ "\xfe\xed\xfa\xce\xde\xad\xbe\xef"
+ "\xab\xad\xda\xd2",
.alen = 20,
- .result = { 0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41,
- 0xeb, 0x06, 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57,
- 0x85, 0x9e, 0x1c, 0xea, 0xa6, 0xef, 0xd9, 0x84,
- 0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, 0xe1, 0x9c,
- 0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25,
- 0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47,
- 0x18, 0xe2, 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9,
- 0xcc, 0xda, 0x27, 0x10,
- 0x25, 0x19, 0x49, 0x8e, 0x80, 0xf1, 0x47, 0x8f,
- 0x37, 0xba, 0x55, 0xbd, 0x6d, 0x27, 0x61, 0x8c },
+ .result = "\x39\x80\xca\x0b\x3c\x00\xe8\x41"
+ "\xeb\x06\xfa\xc4\x87\x2a\x27\x57"
+ "\x85\x9e\x1c\xea\xa6\xef\xd9\x84"
+ "\x62\x85\x93\xb4\x0c\xa1\xe1\x9c"
+ "\x7d\x77\x3d\x00\xc1\x44\xc5\x25"
+ "\xac\x61\x9d\x18\xc8\x4a\x3f\x47"
+ "\x18\xe2\x44\x8b\x2f\xe3\x24\xd9"
+ "\xcc\xda\x27\x10"
+ "\x25\x19\x49\x8e\x80\xf1\x47\x8f"
+ "\x37\xba\x55\xbd\x6d\x27\x61\x8c",
.rlen = 76,
.np = 2,
.tap = { 32, 28 },
.anp = 2,
.atap = { 8, 12 }
}, {
+ .key = zeroed_string,
.klen = 32,
- .result = { 0x53, 0x0f, 0x8a, 0xfb, 0xc7, 0x45, 0x36, 0xb9,
- 0xa9, 0x63, 0xb4, 0xf1, 0xc4, 0xcb, 0x73, 0x8b },
+ .result = "\x53\x0f\x8a\xfb\xc7\x45\x36\xb9"
+ "\xa9\x63\xb4\xf1\xc4\xcb\x73\x8b",
.rlen = 16,
}
};
static struct aead_testvec aes_gcm_dec_tv_template[] = {
{ /* From McGrew & Viega - http://citeseer.ist.psu.edu/656989.html */
+ .key = zeroed_string,
.klen = 32,
- .input = { 0xce, 0xa7, 0x40, 0x3d, 0x4d, 0x60, 0x6b, 0x6e,
- 0x07, 0x4e, 0xc5, 0xd3, 0xba, 0xf3, 0x9d, 0x18,
- 0xd0, 0xd1, 0xc8, 0xa7, 0x99, 0x99, 0x6b, 0xf0,
- 0x26, 0x5b, 0x98, 0xb5, 0xd4, 0x8a, 0xb9, 0x19 },
+ .input = "\xce\xa7\x40\x3d\x4d\x60\x6b\x6e"
+ "\x07\x4e\xc5\xd3\xba\xf3\x9d\x18"
+ "\xd0\xd1\xc8\xa7\x99\x99\x6b\xf0"
+ "\x26\x5b\x98\xb5\xd4\x8a\xb9\x19",
.ilen = 32,
+ .result = zeroed_string,
.rlen = 16,
}, {
- .key = { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
- 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 },
+ .key = "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08"
+ "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08",
.klen = 32,
- .iv = { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88 },
- .input = { 0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07,
- 0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d,
- 0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9,
- 0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa,
- 0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d,
- 0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38,
- 0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a,
- 0xbc, 0xc9, 0xf6, 0x62, 0x89, 0x80, 0x15, 0xad,
- 0xb0, 0x94, 0xda, 0xc5, 0xd9, 0x34, 0x71, 0xbd,
- 0xec, 0x1a, 0x50, 0x22, 0x70, 0xe3, 0xcc, 0x6c },
+ .iv = "\xca\xfe\xba\xbe\xfa\xce\xdb\xad"
+ "\xde\xca\xf8\x88",
+ .input = "\x52\x2d\xc1\xf0\x99\x56\x7d\x07"
+ "\xf4\x7f\x37\xa3\x2a\x84\x42\x7d"
+ "\x64\x3a\x8c\xdc\xbf\xe5\xc0\xc9"
+ "\x75\x98\xa2\xbd\x25\x55\xd1\xaa"
+ "\x8c\xb0\x8e\x48\x59\x0d\xbb\x3d"
+ "\xa7\xb0\x8b\x10\x56\x82\x88\x38"
+ "\xc5\xf6\x1e\x63\x93\xba\x7a\x0a"
+ "\xbc\xc9\xf6\x62\x89\x80\x15\xad"
+ "\xb0\x94\xda\xc5\xd9\x34\x71\xbd"
+ "\xec\x1a\x50\x22\x70\xe3\xcc\x6c",
.ilen = 80,
- .result = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
- 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
- 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
- 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
- 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
- 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
- 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
- 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 },
+ .result = "\xd9\x31\x32\x25\xf8\x84\x06\xe5"
+ "\xa5\x59\x09\xc5\xaf\xf5\x26\x9a"
+ "\x86\xa7\xa9\x53\x15\x34\xf7\xda"
+ "\x2e\x4c\x30\x3d\x8a\x31\x8a\x72"
+ "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
+ "\x2f\xcf\x0e\x24\x49\xa6\xb5\x25"
+ "\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57"
+ "\xba\x63\x7b\x39\x1a\xaf\xd2\x55",
.rlen = 64,
}, {
- .key = { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
- 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 },
+ .key = "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08"
+ "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08",
.klen = 32,
- .iv = { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88 },
- .input = { 0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07,
- 0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d,
- 0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9,
- 0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa,
- 0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d,
- 0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38,
- 0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a,
- 0xbc, 0xc9, 0xf6, 0x62,
- 0x76, 0xfc, 0x6e, 0xce, 0x0f, 0x4e, 0x17, 0x68,
- 0xcd, 0xdf, 0x88, 0x53, 0xbb, 0x2d, 0x55, 0x1b },
+ .iv = "\xca\xfe\xba\xbe\xfa\xce\xdb\xad"
+ "\xde\xca\xf8\x88",
+ .input = "\x52\x2d\xc1\xf0\x99\x56\x7d\x07"
+ "\xf4\x7f\x37\xa3\x2a\x84\x42\x7d"
+ "\x64\x3a\x8c\xdc\xbf\xe5\xc0\xc9"
+ "\x75\x98\xa2\xbd\x25\x55\xd1\xaa"
+ "\x8c\xb0\x8e\x48\x59\x0d\xbb\x3d"
+ "\xa7\xb0\x8b\x10\x56\x82\x88\x38"
+ "\xc5\xf6\x1e\x63\x93\xba\x7a\x0a"
+ "\xbc\xc9\xf6\x62"
+ "\x76\xfc\x6e\xce\x0f\x4e\x17\x68"
+ "\xcd\xdf\x88\x53\xbb\x2d\x55\x1b",
.ilen = 76,
- .assoc = { 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xab, 0xad, 0xda, 0xd2 },
+ .assoc = "\xfe\xed\xfa\xce\xde\xad\xbe\xef"
+ "\xfe\xed\xfa\xce\xde\xad\xbe\xef"
+ "\xab\xad\xda\xd2",
.alen = 20,
- .result = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
- 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
- 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
- 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
- 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
- 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
- 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
- 0xba, 0x63, 0x7b, 0x39 },
+ .result = "\xd9\x31\x32\x25\xf8\x84\x06\xe5"
+ "\xa5\x59\x09\xc5\xaf\xf5\x26\x9a"
+ "\x86\xa7\xa9\x53\x15\x34\xf7\xda"
+ "\x2e\x4c\x30\x3d\x8a\x31\x8a\x72"
+ "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
+ "\x2f\xcf\x0e\x24\x49\xa6\xb5\x25"
+ "\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57"
+ "\xba\x63\x7b\x39",
.rlen = 60,
.np = 2,
.tap = { 48, 28 },
.anp = 3,
.atap = { 8, 8, 4 }
}, {
- .key = { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 },
+ .key = "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08",
.klen = 16,
- .iv = { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88 },
- .input = { 0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24,
- 0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c,
- 0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0,
- 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e,
- 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c,
- 0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05,
- 0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97,
- 0x3d, 0x58, 0xe0, 0x91, 0x47, 0x3f, 0x59, 0x85,
- 0x4d, 0x5c, 0x2a, 0xf3, 0x27, 0xcd, 0x64, 0xa6,
- 0x2c, 0xf3, 0x5a, 0xbd, 0x2b, 0xa6, 0xfa, 0xb4 },
+ .iv = "\xca\xfe\xba\xbe\xfa\xce\xdb\xad"
+ "\xde\xca\xf8\x88",
+ .input = "\x42\x83\x1e\xc2\x21\x77\x74\x24"
+ "\x4b\x72\x21\xb7\x84\xd0\xd4\x9c"
+ "\xe3\xaa\x21\x2f\x2c\x02\xa4\xe0"
+ "\x35\xc1\x7e\x23\x29\xac\xa1\x2e"
+ "\x21\xd5\x14\xb2\x54\x66\x93\x1c"
+ "\x7d\x8f\x6a\x5a\xac\x84\xaa\x05"
+ "\x1b\xa3\x0b\x39\x6a\x0a\xac\x97"
+ "\x3d\x58\xe0\x91\x47\x3f\x59\x85"
+ "\x4d\x5c\x2a\xf3\x27\xcd\x64\xa6"
+ "\x2c\xf3\x5a\xbd\x2b\xa6\xfa\xb4",
.ilen = 80,
- .result = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
- 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
- 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
- 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
- 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
- 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
- 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
- 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 },
+ .result = "\xd9\x31\x32\x25\xf8\x84\x06\xe5"
+ "\xa5\x59\x09\xc5\xaf\xf5\x26\x9a"
+ "\x86\xa7\xa9\x53\x15\x34\xf7\xda"
+ "\x2e\x4c\x30\x3d\x8a\x31\x8a\x72"
+ "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
+ "\x2f\xcf\x0e\x24\x49\xa6\xb5\x25"
+ "\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57"
+ "\xba\x63\x7b\x39\x1a\xaf\xd2\x55",
.rlen = 64,
}, {
- .key = { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 },
+ .key = "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08",
.klen = 16,
- .iv = { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88 },
- .input = { 0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24,
- 0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c,
- 0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0,
- 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e,
- 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c,
- 0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05,
- 0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97,
- 0x3d, 0x58, 0xe0, 0x91,
- 0x5b, 0xc9, 0x4f, 0xbc, 0x32, 0x21, 0xa5, 0xdb,
- 0x94, 0xfa, 0xe9, 0x5a, 0xe7, 0x12, 0x1a, 0x47 },
+ .iv = "\xca\xfe\xba\xbe\xfa\xce\xdb\xad"
+ "\xde\xca\xf8\x88",
+ .input = "\x42\x83\x1e\xc2\x21\x77\x74\x24"
+ "\x4b\x72\x21\xb7\x84\xd0\xd4\x9c"
+ "\xe3\xaa\x21\x2f\x2c\x02\xa4\xe0"
+ "\x35\xc1\x7e\x23\x29\xac\xa1\x2e"
+ "\x21\xd5\x14\xb2\x54\x66\x93\x1c"
+ "\x7d\x8f\x6a\x5a\xac\x84\xaa\x05"
+ "\x1b\xa3\x0b\x39\x6a\x0a\xac\x97"
+ "\x3d\x58\xe0\x91"
+ "\x5b\xc9\x4f\xbc\x32\x21\xa5\xdb"
+ "\x94\xfa\xe9\x5a\xe7\x12\x1a\x47",
.ilen = 76,
- .assoc = { 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xab, 0xad, 0xda, 0xd2 },
+ .assoc = "\xfe\xed\xfa\xce\xde\xad\xbe\xef"
+ "\xfe\xed\xfa\xce\xde\xad\xbe\xef"
+ "\xab\xad\xda\xd2",
.alen = 20,
- .result = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
- 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
- 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
- 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
- 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
- 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
- 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
- 0xba, 0x63, 0x7b, 0x39 },
+ .result = "\xd9\x31\x32\x25\xf8\x84\x06\xe5"
+ "\xa5\x59\x09\xc5\xaf\xf5\x26\x9a"
+ "\x86\xa7\xa9\x53\x15\x34\xf7\xda"
+ "\x2e\x4c\x30\x3d\x8a\x31\x8a\x72"
+ "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
+ "\x2f\xcf\x0e\x24\x49\xa6\xb5\x25"
+ "\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57"
+ "\xba\x63\x7b\x39",
.rlen = 60,
}, {
+ .key = zeroed_string,
.klen = 24,
- .input = { 0x98, 0xe7, 0x24, 0x7c, 0x07, 0xf0, 0xfe, 0x41,
- 0x1c, 0x26, 0x7e, 0x43, 0x84, 0xb0, 0xf6, 0x00,
- 0x2f, 0xf5, 0x8d, 0x80, 0x03, 0x39, 0x27, 0xab,
- 0x8e, 0xf4, 0xd4, 0x58, 0x75, 0x14, 0xf0, 0xfb },
+ .input = "\x98\xe7\x24\x7c\x07\xf0\xfe\x41"
+ "\x1c\x26\x7e\x43\x84\xb0\xf6\x00"
+ "\x2f\xf5\x8d\x80\x03\x39\x27\xab"
+ "\x8e\xf4\xd4\x58\x75\x14\xf0\xfb",
.ilen = 32,
+ .result = zeroed_string,
.rlen = 16,
}, {
- .key = { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
- 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c },
+ .key = "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08"
+ "\xfe\xff\xe9\x92\x86\x65\x73\x1c",
.klen = 24,
- .iv = { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88 },
- .input = { 0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41,
- 0xeb, 0x06, 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57,
- 0x85, 0x9e, 0x1c, 0xea, 0xa6, 0xef, 0xd9, 0x84,
- 0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, 0xe1, 0x9c,
- 0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25,
- 0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47,
- 0x18, 0xe2, 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9,
- 0xcc, 0xda, 0x27, 0x10, 0xac, 0xad, 0xe2, 0x56,
- 0x99, 0x24, 0xa7, 0xc8, 0x58, 0x73, 0x36, 0xbf,
- 0xb1, 0x18, 0x02, 0x4d, 0xb8, 0x67, 0x4a, 0x14 },
+ .iv = "\xca\xfe\xba\xbe\xfa\xce\xdb\xad"
+ "\xde\xca\xf8\x88",
+ .input = "\x39\x80\xca\x0b\x3c\x00\xe8\x41"
+ "\xeb\x06\xfa\xc4\x87\x2a\x27\x57"
+ "\x85\x9e\x1c\xea\xa6\xef\xd9\x84"
+ "\x62\x85\x93\xb4\x0c\xa1\xe1\x9c"
+ "\x7d\x77\x3d\x00\xc1\x44\xc5\x25"
+ "\xac\x61\x9d\x18\xc8\x4a\x3f\x47"
+ "\x18\xe2\x44\x8b\x2f\xe3\x24\xd9"
+ "\xcc\xda\x27\x10\xac\xad\xe2\x56"
+ "\x99\x24\xa7\xc8\x58\x73\x36\xbf"
+ "\xb1\x18\x02\x4d\xb8\x67\x4a\x14",
.ilen = 80,
- .result = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
- 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
- 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
- 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
- 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
- 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
- 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
- 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 },
+ .result = "\xd9\x31\x32\x25\xf8\x84\x06\xe5"
+ "\xa5\x59\x09\xc5\xaf\xf5\x26\x9a"
+ "\x86\xa7\xa9\x53\x15\x34\xf7\xda"
+ "\x2e\x4c\x30\x3d\x8a\x31\x8a\x72"
+ "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
+ "\x2f\xcf\x0e\x24\x49\xa6\xb5\x25"
+ "\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57"
+ "\xba\x63\x7b\x39\x1a\xaf\xd2\x55",
.rlen = 64,
}, {
- .key = { 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
- 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
- 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c },
+ .key = "\xfe\xff\xe9\x92\x86\x65\x73\x1c"
+ "\x6d\x6a\x8f\x94\x67\x30\x83\x08"
+ "\xfe\xff\xe9\x92\x86\x65\x73\x1c",
.klen = 24,
- .iv = { 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88 },
- .input = { 0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41,
- 0xeb, 0x06, 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57,
- 0x85, 0x9e, 0x1c, 0xea, 0xa6, 0xef, 0xd9, 0x84,
- 0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, 0xe1, 0x9c,
- 0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25,
- 0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47,
- 0x18, 0xe2, 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9,
- 0xcc, 0xda, 0x27, 0x10,
- 0x25, 0x19, 0x49, 0x8e, 0x80, 0xf1, 0x47, 0x8f,
- 0x37, 0xba, 0x55, 0xbd, 0x6d, 0x27, 0x61, 0x8c },
+ .iv = "\xca\xfe\xba\xbe\xfa\xce\xdb\xad"
+ "\xde\xca\xf8\x88",
+ .input = "\x39\x80\xca\x0b\x3c\x00\xe8\x41"
+ "\xeb\x06\xfa\xc4\x87\x2a\x27\x57"
+ "\x85\x9e\x1c\xea\xa6\xef\xd9\x84"
+ "\x62\x85\x93\xb4\x0c\xa1\xe1\x9c"
+ "\x7d\x77\x3d\x00\xc1\x44\xc5\x25"
+ "\xac\x61\x9d\x18\xc8\x4a\x3f\x47"
+ "\x18\xe2\x44\x8b\x2f\xe3\x24\xd9"
+ "\xcc\xda\x27\x10"
+ "\x25\x19\x49\x8e\x80\xf1\x47\x8f"
+ "\x37\xba\x55\xbd\x6d\x27\x61\x8c",
.ilen = 76,
- .assoc = { 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xab, 0xad, 0xda, 0xd2 },
+ .assoc = "\xfe\xed\xfa\xce\xde\xad\xbe\xef"
+ "\xfe\xed\xfa\xce\xde\xad\xbe\xef"
+ "\xab\xad\xda\xd2",
.alen = 20,
- .result = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
- 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
- 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
- 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
- 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
- 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
- 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
- 0xba, 0x63, 0x7b, 0x39 },
+ .result = "\xd9\x31\x32\x25\xf8\x84\x06\xe5"
+ "\xa5\x59\x09\xc5\xaf\xf5\x26\x9a"
+ "\x86\xa7\xa9\x53\x15\x34\xf7\xda"
+ "\x2e\x4c\x30\x3d\x8a\x31\x8a\x72"
+ "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
+ "\x2f\xcf\x0e\x24\x49\xa6\xb5\x25"
+ "\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57"
+ "\xba\x63\x7b\x39",
.rlen = 60,
}
};
static struct aead_testvec aes_ccm_enc_tv_template[] = {
{ /* From RFC 3610 */
- .key = { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf },
+ .key = "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf",
.klen = 16,
- .iv = { 0x01, 0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0x00, 0x00 },
- .assoc = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 },
+ .iv = "\x01\x00\x00\x00\x03\x02\x01\x00"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\x00\x00",
+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07",
.alen = 8,
- .input = { 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e },
+ .input = "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e",
.ilen = 23,
- .result = { 0x58, 0x8c, 0x97, 0x9a, 0x61, 0xc6, 0x63, 0xd2,
- 0xf0, 0x66, 0xd0, 0xc2, 0xc0, 0xf9, 0x89, 0x80,
- 0x6d, 0x5f, 0x6b, 0x61, 0xda, 0xc3, 0x84, 0x17,
- 0xe8, 0xd1, 0x2c, 0xfd, 0xf9, 0x26, 0xe0 },
+ .result = "\x58\x8c\x97\x9a\x61\xc6\x63\xd2"
+ "\xf0\x66\xd0\xc2\xc0\xf9\x89\x80"
+ "\x6d\x5f\x6b\x61\xda\xc3\x84\x17"
+ "\xe8\xd1\x2c\xfd\xf9\x26\xe0",
.rlen = 31,
}, {
- .key = { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf },
+ .key = "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf",
.klen = 16,
- .iv = { 0x01, 0x00, 0x00, 0x00, 0x07, 0x06, 0x05, 0x04,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0x00, 0x00 },
- .assoc = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b },
+ .iv = "\x01\x00\x00\x00\x07\x06\x05\x04"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\x00\x00",
+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b",
.alen = 12,
- .input = { 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13,
- 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b,
- 0x1c, 0x1d, 0x1e, 0x1f },
+ .input = "\x0c\x0d\x0e\x0f\x10\x11\x12\x13"
+ "\x14\x15\x16\x17\x18\x19\x1a\x1b"
+ "\x1c\x1d\x1e\x1f",
.ilen = 20,
- .result = { 0xdc, 0xf1, 0xfb, 0x7b, 0x5d, 0x9e, 0x23, 0xfb,
- 0x9d, 0x4e, 0x13, 0x12, 0x53, 0x65, 0x8a, 0xd8,
- 0x6e, 0xbd, 0xca, 0x3e, 0x51, 0xe8, 0x3f, 0x07,
- 0x7d, 0x9c, 0x2d, 0x93 },
+ .result = "\xdc\xf1\xfb\x7b\x5d\x9e\x23\xfb"
+ "\x9d\x4e\x13\x12\x53\x65\x8a\xd8"
+ "\x6e\xbd\xca\x3e\x51\xe8\x3f\x07"
+ "\x7d\x9c\x2d\x93",
.rlen = 28,
}, {
- .key = { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf },
+ .key = "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf",
.klen = 16,
- .iv = { 0x01, 0x00, 0x00, 0x00, 0x0b, 0x0a, 0x09, 0x08,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0x00, 0x00 },
- .assoc = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 },
+ .iv = "\x01\x00\x00\x00\x0b\x0a\x09\x08"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\x00\x00",
+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07",
.alen = 8,
- .input = { 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- 0x20 },
+ .input = "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
+ "\x20",
.ilen = 25,
- .result = { 0x82, 0x53, 0x1a, 0x60, 0xcc, 0x24, 0x94, 0x5a,
- 0x4b, 0x82, 0x79, 0x18, 0x1a, 0xb5, 0xc8, 0x4d,
- 0xf2, 0x1c, 0xe7, 0xf9, 0xb7, 0x3f, 0x42, 0xe1,
- 0x97, 0xea, 0x9c, 0x07, 0xe5, 0x6b, 0x5e, 0xb1,
- 0x7e, 0x5f, 0x4e },
+ .result = "\x82\x53\x1a\x60\xcc\x24\x94\x5a"
+ "\x4b\x82\x79\x18\x1a\xb5\xc8\x4d"
+ "\xf2\x1c\xe7\xf9\xb7\x3f\x42\xe1"
+ "\x97\xea\x9c\x07\xe5\x6b\x5e\xb1"
+ "\x7e\x5f\x4e",
.rlen = 35,
}, {
- .key = { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf },
+ .key = "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf",
.klen = 16,
- .iv = { 0x01, 0x00, 0x00, 0x00, 0x0c, 0x0b, 0x0a, 0x09,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0x00, 0x00 },
- .assoc = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b },
+ .iv = "\x01\x00\x00\x00\x0c\x0b\x0a\x09"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\x00\x00",
+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b",
.alen = 12,
- .input = { 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13,
- 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b,
- 0x1c, 0x1d, 0x1e },
+ .input = "\x0c\x0d\x0e\x0f\x10\x11\x12\x13"
+ "\x14\x15\x16\x17\x18\x19\x1a\x1b"
+ "\x1c\x1d\x1e",
.ilen = 19,
- .result = { 0x07, 0x34, 0x25, 0x94, 0x15, 0x77, 0x85, 0x15,
- 0x2b, 0x07, 0x40, 0x98, 0x33, 0x0a, 0xbb, 0x14,
- 0x1b, 0x94, 0x7b, 0x56, 0x6a, 0xa9, 0x40, 0x6b,
- 0x4d, 0x99, 0x99, 0x88, 0xdd },
+ .result = "\x07\x34\x25\x94\x15\x77\x85\x15"
+ "\x2b\x07\x40\x98\x33\x0a\xbb\x14"
+ "\x1b\x94\x7b\x56\x6a\xa9\x40\x6b"
+ "\x4d\x99\x99\x88\xdd",
.rlen = 29,
}, {
- .key = { 0xd7, 0x82, 0x8d, 0x13, 0xb2, 0xb0, 0xbd, 0xc3,
- 0x25, 0xa7, 0x62, 0x36, 0xdf, 0x93, 0xcc, 0x6b },
+ .key = "\xd7\x82\x8d\x13\xb2\xb0\xbd\xc3"
+ "\x25\xa7\x62\x36\xdf\x93\xcc\x6b",
.klen = 16,
- .iv = { 0x01, 0x00, 0x33, 0x56, 0x8e, 0xf7, 0xb2, 0x63,
- 0x3c, 0x96, 0x96, 0x76, 0x6c, 0xfa, 0x00, 0x00 },
- .assoc = { 0x63, 0x01, 0x8f, 0x76, 0xdc, 0x8a, 0x1b, 0xcb },
+ .iv = "\x01\x00\x33\x56\x8e\xf7\xb2\x63"
+ "\x3c\x96\x96\x76\x6c\xfa\x00\x00",
+ .assoc = "\x63\x01\x8f\x76\xdc\x8a\x1b\xcb",
.alen = 8,
- .input = { 0x90, 0x20, 0xea, 0x6f, 0x91, 0xbd, 0xd8, 0x5a,
- 0xfa, 0x00, 0x39, 0xba, 0x4b, 0xaf, 0xf9, 0xbf,
- 0xb7, 0x9c, 0x70, 0x28, 0x94, 0x9c, 0xd0, 0xec },
+ .input = "\x90\x20\xea\x6f\x91\xbd\xd8\x5a"
+ "\xfa\x00\x39\xba\x4b\xaf\xf9\xbf"
+ "\xb7\x9c\x70\x28\x94\x9c\xd0\xec",
.ilen = 24,
- .result = { 0x4c, 0xcb, 0x1e, 0x7c, 0xa9, 0x81, 0xbe, 0xfa,
- 0xa0, 0x72, 0x6c, 0x55, 0xd3, 0x78, 0x06, 0x12,
- 0x98, 0xc8, 0x5c, 0x92, 0x81, 0x4a, 0xbc, 0x33,
- 0xc5, 0x2e, 0xe8, 0x1d, 0x7d, 0x77, 0xc0, 0x8a },
+ .result = "\x4c\xcb\x1e\x7c\xa9\x81\xbe\xfa"
+ "\xa0\x72\x6c\x55\xd3\x78\x06\x12"
+ "\x98\xc8\x5c\x92\x81\x4a\xbc\x33"
+ "\xc5\x2e\xe8\x1d\x7d\x77\xc0\x8a",
.rlen = 32,
}, {
- .key = { 0xd7, 0x82, 0x8d, 0x13, 0xb2, 0xb0, 0xbd, 0xc3,
- 0x25, 0xa7, 0x62, 0x36, 0xdf, 0x93, 0xcc, 0x6b },
+ .key = "\xd7\x82\x8d\x13\xb2\xb0\xbd\xc3"
+ "\x25\xa7\x62\x36\xdf\x93\xcc\x6b",
.klen = 16,
- .iv = { 0x01, 0x00, 0xd5, 0x60, 0x91, 0x2d, 0x3f, 0x70,
- 0x3c, 0x96, 0x96, 0x76, 0x6c, 0xfa, 0x00, 0x00 },
- .assoc = { 0xcd, 0x90, 0x44, 0xd2, 0xb7, 0x1f, 0xdb, 0x81,
- 0x20, 0xea, 0x60, 0xc0 },
+ .iv = "\x01\x00\xd5\x60\x91\x2d\x3f\x70"
+ "\x3c\x96\x96\x76\x6c\xfa\x00\x00",
+ .assoc = "\xcd\x90\x44\xd2\xb7\x1f\xdb\x81"
+ "\x20\xea\x60\xc0",
.alen = 12,
- .input = { 0x64, 0x35, 0xac, 0xba, 0xfb, 0x11, 0xa8, 0x2e,
- 0x2f, 0x07, 0x1d, 0x7c, 0xa4, 0xa5, 0xeb, 0xd9,
- 0x3a, 0x80, 0x3b, 0xa8, 0x7f },
+ .input = "\x64\x35\xac\xba\xfb\x11\xa8\x2e"
+ "\x2f\x07\x1d\x7c\xa4\xa5\xeb\xd9"
+ "\x3a\x80\x3b\xa8\x7f",
.ilen = 21,
- .result = { 0x00, 0x97, 0x69, 0xec, 0xab, 0xdf, 0x48, 0x62,
- 0x55, 0x94, 0xc5, 0x92, 0x51, 0xe6, 0x03, 0x57,
- 0x22, 0x67, 0x5e, 0x04, 0xc8, 0x47, 0x09, 0x9e,
- 0x5a, 0xe0, 0x70, 0x45, 0x51 },
+ .result = "\x00\x97\x69\xec\xab\xdf\x48\x62"
+ "\x55\x94\xc5\x92\x51\xe6\x03\x57"
+ "\x22\x67\x5e\x04\xc8\x47\x09\x9e"
+ "\x5a\xe0\x70\x45\x51",
.rlen = 29,
}, {
- .key = { 0xd7, 0x82, 0x8d, 0x13, 0xb2, 0xb0, 0xbd, 0xc3,
- 0x25, 0xa7, 0x62, 0x36, 0xdf, 0x93, 0xcc, 0x6b },
+ .key = "\xd7\x82\x8d\x13\xb2\xb0\xbd\xc3"
+ "\x25\xa7\x62\x36\xdf\x93\xcc\x6b",
.klen = 16,
- .iv = { 0x01, 0x00, 0x42, 0xff, 0xf8, 0xf1, 0x95, 0x1c,
- 0x3c, 0x96, 0x96, 0x76, 0x6c, 0xfa, 0x00, 0x00 },
- .assoc = { 0xd8, 0x5b, 0xc7, 0xe6, 0x9f, 0x94, 0x4f, 0xb8 },
+ .iv = "\x01\x00\x42\xff\xf8\xf1\x95\x1c"
+ "\x3c\x96\x96\x76\x6c\xfa\x00\x00",
+ .assoc = "\xd8\x5b\xc7\xe6\x9f\x94\x4f\xb8",
.alen = 8,
- .input = { 0x8a, 0x19, 0xb9, 0x50, 0xbc, 0xf7, 0x1a, 0x01,
- 0x8e, 0x5e, 0x67, 0x01, 0xc9, 0x17, 0x87, 0x65,
- 0x98, 0x09, 0xd6, 0x7d, 0xbe, 0xdd, 0x18 },
+ .input = "\x8a\x19\xb9\x50\xbc\xf7\x1a\x01"
+ "\x8e\x5e\x67\x01\xc9\x17\x87\x65"
+ "\x98\x09\xd6\x7d\xbe\xdd\x18",
.ilen = 23,
- .result = { 0xbc, 0x21, 0x8d, 0xaa, 0x94, 0x74, 0x27, 0xb6,
- 0xdb, 0x38, 0x6a, 0x99, 0xac, 0x1a, 0xef, 0x23,
- 0xad, 0xe0, 0xb5, 0x29, 0x39, 0xcb, 0x6a, 0x63,
- 0x7c, 0xf9, 0xbe, 0xc2, 0x40, 0x88, 0x97, 0xc6,
- 0xba },
+ .result = "\xbc\x21\x8d\xaa\x94\x74\x27\xb6"
+ "\xdb\x38\x6a\x99\xac\x1a\xef\x23"
+ "\xad\xe0\xb5\x29\x39\xcb\x6a\x63"
+ "\x7c\xf9\xbe\xc2\x40\x88\x97\xc6"
+ "\xba",
.rlen = 33,
},
};
static struct aead_testvec aes_ccm_dec_tv_template[] = {
{ /* From RFC 3610 */
- .key = { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf },
+ .key = "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf",
.klen = 16,
- .iv = { 0x01, 0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0x00, 0x00 },
- .assoc = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 },
+ .iv = "\x01\x00\x00\x00\x03\x02\x01\x00"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\x00\x00",
+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07",
.alen = 8,
- .input = { 0x58, 0x8c, 0x97, 0x9a, 0x61, 0xc6, 0x63, 0xd2,
- 0xf0, 0x66, 0xd0, 0xc2, 0xc0, 0xf9, 0x89, 0x80,
- 0x6d, 0x5f, 0x6b, 0x61, 0xda, 0xc3, 0x84, 0x17,
- 0xe8, 0xd1, 0x2c, 0xfd, 0xf9, 0x26, 0xe0 },
+ .input = "\x58\x8c\x97\x9a\x61\xc6\x63\xd2"
+ "\xf0\x66\xd0\xc2\xc0\xf9\x89\x80"
+ "\x6d\x5f\x6b\x61\xda\xc3\x84\x17"
+ "\xe8\xd1\x2c\xfd\xf9\x26\xe0",
.ilen = 31,
- .result = { 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e },
+ .result = "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e",
.rlen = 23,
}, {
- .key = { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf },
+ .key = "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf",
.klen = 16,
- .iv = { 0x01, 0x00, 0x00, 0x00, 0x07, 0x06, 0x05, 0x04,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0x00, 0x00 },
- .assoc = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b },
+ .iv = "\x01\x00\x00\x00\x07\x06\x05\x04"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\x00\x00",
+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b",
.alen = 12,
- .input = { 0xdc, 0xf1, 0xfb, 0x7b, 0x5d, 0x9e, 0x23, 0xfb,
- 0x9d, 0x4e, 0x13, 0x12, 0x53, 0x65, 0x8a, 0xd8,
- 0x6e, 0xbd, 0xca, 0x3e, 0x51, 0xe8, 0x3f, 0x07,
- 0x7d, 0x9c, 0x2d, 0x93 },
+ .input = "\xdc\xf1\xfb\x7b\x5d\x9e\x23\xfb"
+ "\x9d\x4e\x13\x12\x53\x65\x8a\xd8"
+ "\x6e\xbd\xca\x3e\x51\xe8\x3f\x07"
+ "\x7d\x9c\x2d\x93",
.ilen = 28,
- .result = { 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13,
- 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b,
- 0x1c, 0x1d, 0x1e, 0x1f },
+ .result = "\x0c\x0d\x0e\x0f\x10\x11\x12\x13"
+ "\x14\x15\x16\x17\x18\x19\x1a\x1b"
+ "\x1c\x1d\x1e\x1f",
.rlen = 20,
}, {
- .key = { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf },
+ .key = "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf",
.klen = 16,
- .iv = { 0x01, 0x00, 0x00, 0x00, 0x0b, 0x0a, 0x09, 0x08,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0x00, 0x00 },
- .assoc = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 },
+ .iv = "\x01\x00\x00\x00\x0b\x0a\x09\x08"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\x00\x00",
+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07",
.alen = 8,
- .input = { 0x82, 0x53, 0x1a, 0x60, 0xcc, 0x24, 0x94, 0x5a,
- 0x4b, 0x82, 0x79, 0x18, 0x1a, 0xb5, 0xc8, 0x4d,
- 0xf2, 0x1c, 0xe7, 0xf9, 0xb7, 0x3f, 0x42, 0xe1,
- 0x97, 0xea, 0x9c, 0x07, 0xe5, 0x6b, 0x5e, 0xb1,
- 0x7e, 0x5f, 0x4e },
+ .input = "\x82\x53\x1a\x60\xcc\x24\x94\x5a"
+ "\x4b\x82\x79\x18\x1a\xb5\xc8\x4d"
+ "\xf2\x1c\xe7\xf9\xb7\x3f\x42\xe1"
+ "\x97\xea\x9c\x07\xe5\x6b\x5e\xb1"
+ "\x7e\x5f\x4e",
.ilen = 35,
- .result = { 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- 0x20 },
+ .result = "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
+ "\x20",
.rlen = 25,
}, {
- .key = { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf },
+ .key = "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf",
.klen = 16,
- .iv = { 0x01, 0x00, 0x00, 0x00, 0x0c, 0x0b, 0x0a, 0x09,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0x00, 0x00 },
- .assoc = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b },
+ .iv = "\x01\x00\x00\x00\x0c\x0b\x0a\x09"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\x00\x00",
+ .assoc = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b",
.alen = 12,
- .input = { 0x07, 0x34, 0x25, 0x94, 0x15, 0x77, 0x85, 0x15,
- 0x2b, 0x07, 0x40, 0x98, 0x33, 0x0a, 0xbb, 0x14,
- 0x1b, 0x94, 0x7b, 0x56, 0x6a, 0xa9, 0x40, 0x6b,
- 0x4d, 0x99, 0x99, 0x88, 0xdd },
+ .input = "\x07\x34\x25\x94\x15\x77\x85\x15"
+ "\x2b\x07\x40\x98\x33\x0a\xbb\x14"
+ "\x1b\x94\x7b\x56\x6a\xa9\x40\x6b"
+ "\x4d\x99\x99\x88\xdd",
.ilen = 29,
- .result = { 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13,
- 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b,
- 0x1c, 0x1d, 0x1e },
+ .result = "\x0c\x0d\x0e\x0f\x10\x11\x12\x13"
+ "\x14\x15\x16\x17\x18\x19\x1a\x1b"
+ "\x1c\x1d\x1e",
.rlen = 19,
}, {
- .key = { 0xd7, 0x82, 0x8d, 0x13, 0xb2, 0xb0, 0xbd, 0xc3,
- 0x25, 0xa7, 0x62, 0x36, 0xdf, 0x93, 0xcc, 0x6b },
+ .key = "\xd7\x82\x8d\x13\xb2\xb0\xbd\xc3"
+ "\x25\xa7\x62\x36\xdf\x93\xcc\x6b",
.klen = 16,
- .iv = { 0x01, 0x00, 0x33, 0x56, 0x8e, 0xf7, 0xb2, 0x63,
- 0x3c, 0x96, 0x96, 0x76, 0x6c, 0xfa, 0x00, 0x00 },
- .assoc = { 0x63, 0x01, 0x8f, 0x76, 0xdc, 0x8a, 0x1b, 0xcb },
+ .iv = "\x01\x00\x33\x56\x8e\xf7\xb2\x63"
+ "\x3c\x96\x96\x76\x6c\xfa\x00\x00",
+ .assoc = "\x63\x01\x8f\x76\xdc\x8a\x1b\xcb",
.alen = 8,
- .input = { 0x4c, 0xcb, 0x1e, 0x7c, 0xa9, 0x81, 0xbe, 0xfa,
- 0xa0, 0x72, 0x6c, 0x55, 0xd3, 0x78, 0x06, 0x12,
- 0x98, 0xc8, 0x5c, 0x92, 0x81, 0x4a, 0xbc, 0x33,
- 0xc5, 0x2e, 0xe8, 0x1d, 0x7d, 0x77, 0xc0, 0x8a },
+ .input = "\x4c\xcb\x1e\x7c\xa9\x81\xbe\xfa"
+ "\xa0\x72\x6c\x55\xd3\x78\x06\x12"
+ "\x98\xc8\x5c\x92\x81\x4a\xbc\x33"
+ "\xc5\x2e\xe8\x1d\x7d\x77\xc0\x8a",
.ilen = 32,
- .result = { 0x90, 0x20, 0xea, 0x6f, 0x91, 0xbd, 0xd8, 0x5a,
- 0xfa, 0x00, 0x39, 0xba, 0x4b, 0xaf, 0xf9, 0xbf,
- 0xb7, 0x9c, 0x70, 0x28, 0x94, 0x9c, 0xd0, 0xec },
+ .result = "\x90\x20\xea\x6f\x91\xbd\xd8\x5a"
+ "\xfa\x00\x39\xba\x4b\xaf\xf9\xbf"
+ "\xb7\x9c\x70\x28\x94\x9c\xd0\xec",
.rlen = 24,
}, {
- .key = { 0xd7, 0x82, 0x8d, 0x13, 0xb2, 0xb0, 0xbd, 0xc3,
- 0x25, 0xa7, 0x62, 0x36, 0xdf, 0x93, 0xcc, 0x6b },
+ .key = "\xd7\x82\x8d\x13\xb2\xb0\xbd\xc3"
+ "\x25\xa7\x62\x36\xdf\x93\xcc\x6b",
.klen = 16,
- .iv = { 0x01, 0x00, 0xd5, 0x60, 0x91, 0x2d, 0x3f, 0x70,
- 0x3c, 0x96, 0x96, 0x76, 0x6c, 0xfa, 0x00, 0x00 },
- .assoc = { 0xcd, 0x90, 0x44, 0xd2, 0xb7, 0x1f, 0xdb, 0x81,
- 0x20, 0xea, 0x60, 0xc0 },
+ .iv = "\x01\x00\xd5\x60\x91\x2d\x3f\x70"
+ "\x3c\x96\x96\x76\x6c\xfa\x00\x00",
+ .assoc = "\xcd\x90\x44\xd2\xb7\x1f\xdb\x81"
+ "\x20\xea\x60\xc0",
.alen = 12,
- .input = { 0x00, 0x97, 0x69, 0xec, 0xab, 0xdf, 0x48, 0x62,
- 0x55, 0x94, 0xc5, 0x92, 0x51, 0xe6, 0x03, 0x57,
- 0x22, 0x67, 0x5e, 0x04, 0xc8, 0x47, 0x09, 0x9e,
- 0x5a, 0xe0, 0x70, 0x45, 0x51 },
+ .input = "\x00\x97\x69\xec\xab\xdf\x48\x62"
+ "\x55\x94\xc5\x92\x51\xe6\x03\x57"
+ "\x22\x67\x5e\x04\xc8\x47\x09\x9e"
+ "\x5a\xe0\x70\x45\x51",
.ilen = 29,
- .result = { 0x64, 0x35, 0xac, 0xba, 0xfb, 0x11, 0xa8, 0x2e,
- 0x2f, 0x07, 0x1d, 0x7c, 0xa4, 0xa5, 0xeb, 0xd9,
- 0x3a, 0x80, 0x3b, 0xa8, 0x7f },
+ .result = "\x64\x35\xac\xba\xfb\x11\xa8\x2e"
+ "\x2f\x07\x1d\x7c\xa4\xa5\xeb\xd9"
+ "\x3a\x80\x3b\xa8\x7f",
.rlen = 21,
}, {
- .key = { 0xd7, 0x82, 0x8d, 0x13, 0xb2, 0xb0, 0xbd, 0xc3,
- 0x25, 0xa7, 0x62, 0x36, 0xdf, 0x93, 0xcc, 0x6b },
+ .key = "\xd7\x82\x8d\x13\xb2\xb0\xbd\xc3"
+ "\x25\xa7\x62\x36\xdf\x93\xcc\x6b",
.klen = 16,
- .iv = { 0x01, 0x00, 0x42, 0xff, 0xf8, 0xf1, 0x95, 0x1c,
- 0x3c, 0x96, 0x96, 0x76, 0x6c, 0xfa, 0x00, 0x00 },
- .assoc = { 0xd8, 0x5b, 0xc7, 0xe6, 0x9f, 0x94, 0x4f, 0xb8 },
+ .iv = "\x01\x00\x42\xff\xf8\xf1\x95\x1c"
+ "\x3c\x96\x96\x76\x6c\xfa\x00\x00",
+ .assoc = "\xd8\x5b\xc7\xe6\x9f\x94\x4f\xb8",
.alen = 8,
- .input = { 0xbc, 0x21, 0x8d, 0xaa, 0x94, 0x74, 0x27, 0xb6,
- 0xdb, 0x38, 0x6a, 0x99, 0xac, 0x1a, 0xef, 0x23,
- 0xad, 0xe0, 0xb5, 0x29, 0x39, 0xcb, 0x6a, 0x63,
- 0x7c, 0xf9, 0xbe, 0xc2, 0x40, 0x88, 0x97, 0xc6,
- 0xba },
+ .input = "\xbc\x21\x8d\xaa\x94\x74\x27\xb6"
+ "\xdb\x38\x6a\x99\xac\x1a\xef\x23"
+ "\xad\xe0\xb5\x29\x39\xcb\x6a\x63"
+ "\x7c\xf9\xbe\xc2\x40\x88\x97\xc6"
+ "\xba",
.ilen = 33,
- .result = { 0x8a, 0x19, 0xb9, 0x50, 0xbc, 0xf7, 0x1a, 0x01,
- 0x8e, 0x5e, 0x67, 0x01, 0xc9, 0x17, 0x87, 0x65,
- 0x98, 0x09, 0xd6, 0x7d, 0xbe, 0xdd, 0x18 },
+ .result = "\x8a\x19\xb9\x50\xbc\xf7\x1a\x01"
+ "\x8e\x5e\x67\x01\xc9\x17\x87\x65"
+ "\x98\x09\xd6\x7d\xbe\xdd\x18",
.rlen = 23,
},
};
static struct cipher_testvec cast5_enc_tv_template[] = {
{
- .key = { 0x01, 0x23, 0x45, 0x67, 0x12, 0x34, 0x56, 0x78,
- 0x23, 0x45, 0x67, 0x89, 0x34, 0x56, 0x78, 0x9a },
+ .key = "\x01\x23\x45\x67\x12\x34\x56\x78"
+ "\x23\x45\x67\x89\x34\x56\x78\x9a",
.klen = 16,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.ilen = 8,
- .result = { 0x23, 0x8b, 0x4f, 0xe5, 0x84, 0x7e, 0x44, 0xb2 },
+ .result = "\x23\x8b\x4f\xe5\x84\x7e\x44\xb2",
.rlen = 8,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x12, 0x34, 0x56, 0x78,
- 0x23, 0x45 },
+ .key = "\x01\x23\x45\x67\x12\x34\x56\x78"
+ "\x23\x45",
.klen = 10,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.ilen = 8,
- .result = { 0xeb, 0x6a, 0x71, 0x1a, 0x2c, 0x02, 0x27, 0x1b },
+ .result = "\xeb\x6a\x71\x1a\x2c\x02\x27\x1b",
.rlen = 8,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x12 },
+ .key = "\x01\x23\x45\x67\x12",
.klen = 5,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.ilen = 8,
- .result = { 0x7a, 0xc8, 0x16, 0xd1, 0x6e, 0x9b, 0x30, 0x2e },
+ .result = "\x7a\xc8\x16\xd1\x6e\x9b\x30\x2e",
.rlen = 8,
},
};
static struct cipher_testvec cast5_dec_tv_template[] = {
{
- .key = { 0x01, 0x23, 0x45, 0x67, 0x12, 0x34, 0x56, 0x78,
- 0x23, 0x45, 0x67, 0x89, 0x34, 0x56, 0x78, 0x9a },
+ .key = "\x01\x23\x45\x67\x12\x34\x56\x78"
+ "\x23\x45\x67\x89\x34\x56\x78\x9a",
.klen = 16,
- .input = { 0x23, 0x8b, 0x4f, 0xe5, 0x84, 0x7e, 0x44, 0xb2 },
+ .input = "\x23\x8b\x4f\xe5\x84\x7e\x44\xb2",
.ilen = 8,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.rlen = 8,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x12, 0x34, 0x56, 0x78,
- 0x23, 0x45 },
+ .key = "\x01\x23\x45\x67\x12\x34\x56\x78"
+ "\x23\x45",
.klen = 10,
- .input = { 0xeb, 0x6a, 0x71, 0x1a, 0x2c, 0x02, 0x27, 0x1b },
+ .input = "\xeb\x6a\x71\x1a\x2c\x02\x27\x1b",
.ilen = 8,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.rlen = 8,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x12 },
+ .key = "\x01\x23\x45\x67\x12",
.klen = 5,
- .input = { 0x7a, 0xc8, 0x16, 0xd1, 0x6e, 0x9b, 0x30, 0x2e },
+ .input = "\x7a\xc8\x16\xd1\x6e\x9b\x30\x2e",
.ilen = 8,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.rlen = 8,
},
};
static struct cipher_testvec arc4_enc_tv_template[] = {
{
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.ilen = 8,
- .result = { 0x75, 0xb7, 0x87, 0x80, 0x99, 0xe0, 0xc5, 0x96 },
+ .result = "\x75\xb7\x87\x80\x99\xe0\xc5\x96",
.rlen = 8,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00",
.ilen = 8,
- .result = { 0x74, 0x94, 0xc2, 0xe7, 0x10, 0x4b, 0x08, 0x79 },
+ .result = "\x74\x94\xc2\xe7\x10\x4b\x08\x79",
.rlen = 8,
}, {
- .key = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 8,
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00",
.ilen = 8,
- .result = { 0xde, 0x18, 0x89, 0x41, 0xa3, 0x37, 0x5d, 0x3a },
+ .result = "\xde\x18\x89\x41\xa3\x37\x5d\x3a",
.rlen = 8,
}, {
- .key = { 0xef, 0x01, 0x23, 0x45},
+ .key = "\xef\x01\x23\x45",
.klen = 4,
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00 },
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00",
.ilen = 20,
- .result = { 0xd6, 0xa1, 0x41, 0xa7, 0xec, 0x3c, 0x38, 0xdf,
- 0xbd, 0x61, 0x5a, 0x11, 0x62, 0xe1, 0xc7, 0xba,
- 0x36, 0xb6, 0x78, 0x58 },
+ .result = "\xd6\xa1\x41\xa7\xec\x3c\x38\xdf"
+ "\xbd\x61\x5a\x11\x62\xe1\xc7\xba"
+ "\x36\xb6\x78\x58",
.rlen = 20,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0,
- 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0,
- 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0,
- 0x12, 0x34, 0x56, 0x78 },
+ .input = "\x12\x34\x56\x78\x9A\xBC\xDE\xF0"
+ "\x12\x34\x56\x78\x9A\xBC\xDE\xF0"
+ "\x12\x34\x56\x78\x9A\xBC\xDE\xF0"
+ "\x12\x34\x56\x78",
.ilen = 28,
- .result = { 0x66, 0xa0, 0x94, 0x9f, 0x8a, 0xf7, 0xd6, 0x89,
- 0x1f, 0x7f, 0x83, 0x2b, 0xa8, 0x33, 0xc0, 0x0c,
- 0x89, 0x2e, 0xbe, 0x30, 0x14, 0x3c, 0xe2, 0x87,
- 0x40, 0x01, 0x1e, 0xcf },
+ .result = "\x66\xa0\x94\x9f\x8a\xf7\xd6\x89"
+ "\x1f\x7f\x83\x2b\xa8\x33\xc0\x0c"
+ "\x89\x2e\xbe\x30\x14\x3c\xe2\x87"
+ "\x40\x01\x1e\xcf",
.rlen = 28,
}, {
- .key = { 0xef, 0x01, 0x23, 0x45 },
+ .key = "\xef\x01\x23\x45",
.klen = 4,
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00 },
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00",
.ilen = 10,
- .result = { 0xd6, 0xa1, 0x41, 0xa7, 0xec, 0x3c, 0x38, 0xdf,
- 0xbd, 0x61 },
+ .result = "\xd6\xa1\x41\xa7\xec\x3c\x38\xdf"
+ "\xbd\x61",
.rlen = 10,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 16,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF },
+ .input = "\x01\x23\x45\x67\x89\xAB\xCD\xEF",
.ilen = 8,
- .result = { 0x69, 0x72, 0x36, 0x59, 0x1B, 0x52, 0x42, 0xB1 },
+ .result = "\x69\x72\x36\x59\x1B\x52\x42\xB1",
.rlen = 8,
},
};
static struct cipher_testvec arc4_dec_tv_template[] = {
{
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x75, 0xb7, 0x87, 0x80, 0x99, 0xe0, 0xc5, 0x96 },
+ .input = "\x75\xb7\x87\x80\x99\xe0\xc5\x96",
.ilen = 8,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.rlen = 8,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x74, 0x94, 0xc2, 0xe7, 0x10, 0x4b, 0x08, 0x79 },
+ .input = "\x74\x94\xc2\xe7\x10\x4b\x08\x79",
.ilen = 8,
- .result = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .result = "\x00\x00\x00\x00\x00\x00\x00\x00",
.rlen = 8,
}, {
- .key = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 8,
- .input = { 0xde, 0x18, 0x89, 0x41, 0xa3, 0x37, 0x5d, 0x3a },
+ .input = "\xde\x18\x89\x41\xa3\x37\x5d\x3a",
.ilen = 8,
- .result = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .result = "\x00\x00\x00\x00\x00\x00\x00\x00",
.rlen = 8,
}, {
- .key = { 0xef, 0x01, 0x23, 0x45},
+ .key = "\xef\x01\x23\x45",
.klen = 4,
- .input = { 0xd6, 0xa1, 0x41, 0xa7, 0xec, 0x3c, 0x38, 0xdf,
- 0xbd, 0x61, 0x5a, 0x11, 0x62, 0xe1, 0xc7, 0xba,
- 0x36, 0xb6, 0x78, 0x58 },
+ .input = "\xd6\xa1\x41\xa7\xec\x3c\x38\xdf"
+ "\xbd\x61\x5a\x11\x62\xe1\xc7\xba"
+ "\x36\xb6\x78\x58",
.ilen = 20,
- .result = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00 },
+ .result = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00",
.rlen = 20,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef",
.klen = 8,
- .input = { 0x66, 0xa0, 0x94, 0x9f, 0x8a, 0xf7, 0xd6, 0x89,
- 0x1f, 0x7f, 0x83, 0x2b, 0xa8, 0x33, 0xc0, 0x0c,
- 0x89, 0x2e, 0xbe, 0x30, 0x14, 0x3c, 0xe2, 0x87,
- 0x40, 0x01, 0x1e, 0xcf },
+ .input = "\x66\xa0\x94\x9f\x8a\xf7\xd6\x89"
+ "\x1f\x7f\x83\x2b\xa8\x33\xc0\x0c"
+ "\x89\x2e\xbe\x30\x14\x3c\xe2\x87"
+ "\x40\x01\x1e\xcf",
.ilen = 28,
- .result = { 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0,
- 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0,
- 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0,
- 0x12, 0x34, 0x56, 0x78 },
+ .result = "\x12\x34\x56\x78\x9A\xBC\xDE\xF0"
+ "\x12\x34\x56\x78\x9A\xBC\xDE\xF0"
+ "\x12\x34\x56\x78\x9A\xBC\xDE\xF0"
+ "\x12\x34\x56\x78",
.rlen = 28,
}, {
- .key = { 0xef, 0x01, 0x23, 0x45 },
+ .key = "\xef\x01\x23\x45",
.klen = 4,
- .input = { 0xd6, 0xa1, 0x41, 0xa7, 0xec, 0x3c, 0x38, 0xdf,
- 0xbd, 0x61 },
+ .input = "\xd6\xa1\x41\xa7\xec\x3c\x38\xdf"
+ "\xbd\x61",
.ilen = 10,
- .result = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00 },
+ .result = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00",
.rlen = 10,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 16,
- .input = { 0x69, 0x72, 0x36, 0x59, 0x1B, 0x52, 0x42, 0xB1 },
+ .input = "\x69\x72\x36\x59\x1B\x52\x42\xB1",
.ilen = 8,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF },
+ .result = "\x01\x23\x45\x67\x89\xAB\xCD\xEF",
.rlen = 8,
},
};
static struct cipher_testvec tea_enc_tv_template[] = {
{
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .input = { [0 ... 8] = 0x00 },
+ .input = zeroed_string,
.ilen = 8,
- .result = { 0x0a, 0x3a, 0xea, 0x41, 0x40, 0xa9, 0xba, 0x94 },
+ .result = "\x0a\x3a\xea\x41\x40\xa9\xba\x94",
.rlen = 8,
}, {
- .key = { 0x2b, 0x02, 0x05, 0x68, 0x06, 0x14, 0x49, 0x76,
- 0x77, 0x5d, 0x0e, 0x26, 0x6c, 0x28, 0x78, 0x43 },
+ .key = "\x2b\x02\x05\x68\x06\x14\x49\x76"
+ "\x77\x5d\x0e\x26\x6c\x28\x78\x43",
.klen = 16,
- .input = { 0x74, 0x65, 0x73, 0x74, 0x20, 0x6d, 0x65, 0x2e },
+ .input = "\x74\x65\x73\x74\x20\x6d\x65\x2e",
.ilen = 8,
- .result = { 0x77, 0x5d, 0x2a, 0x6a, 0xf6, 0xce, 0x92, 0x09 },
+ .result = "\x77\x5d\x2a\x6a\xf6\xce\x92\x09",
.rlen = 8,
}, {
- .key = { 0x09, 0x65, 0x43, 0x11, 0x66, 0x44, 0x39, 0x25,
- 0x51, 0x3a, 0x16, 0x10, 0x0a, 0x08, 0x12, 0x6e },
+ .key = "\x09\x65\x43\x11\x66\x44\x39\x25"
+ "\x51\x3a\x16\x10\x0a\x08\x12\x6e",
.klen = 16,
- .input = { 0x6c, 0x6f, 0x6e, 0x67, 0x65, 0x72, 0x5f, 0x74,
- 0x65, 0x73, 0x74, 0x5f, 0x76, 0x65, 0x63, 0x74 },
+ .input = "\x6c\x6f\x6e\x67\x65\x72\x5f\x74"
+ "\x65\x73\x74\x5f\x76\x65\x63\x74",
.ilen = 16,
- .result = { 0xbe, 0x7a, 0xbb, 0x81, 0x95, 0x2d, 0x1f, 0x1e,
- 0xdd, 0x89, 0xa1, 0x25, 0x04, 0x21, 0xdf, 0x95 },
+ .result = "\xbe\x7a\xbb\x81\x95\x2d\x1f\x1e"
+ "\xdd\x89\xa1\x25\x04\x21\xdf\x95",
.rlen = 16,
}, {
- .key = { 0x4d, 0x76, 0x32, 0x17, 0x05, 0x3f, 0x75, 0x2c,
- 0x5d, 0x04, 0x16, 0x36, 0x15, 0x72, 0x63, 0x2f },
+ .key = "\x4d\x76\x32\x17\x05\x3f\x75\x2c"
+ "\x5d\x04\x16\x36\x15\x72\x63\x2f",
.klen = 16,
- .input = { 0x54, 0x65, 0x61, 0x20, 0x69, 0x73, 0x20, 0x67,
- 0x6f, 0x6f, 0x64, 0x20, 0x66, 0x6f, 0x72, 0x20,
- 0x79, 0x6f, 0x75, 0x21, 0x21, 0x21, 0x20, 0x72,
- 0x65, 0x61, 0x6c, 0x6c, 0x79, 0x21, 0x21, 0x21 },
+ .input = "\x54\x65\x61\x20\x69\x73\x20\x67"
+ "\x6f\x6f\x64\x20\x66\x6f\x72\x20"
+ "\x79\x6f\x75\x21\x21\x21\x20\x72"
+ "\x65\x61\x6c\x6c\x79\x21\x21\x21",
.ilen = 32,
- .result = { 0xe0, 0x4d, 0x5d, 0x3c, 0xb7, 0x8c, 0x36, 0x47,
- 0x94, 0x18, 0x95, 0x91, 0xa9, 0xfc, 0x49, 0xf8,
- 0x44, 0xd1, 0x2d, 0xc2, 0x99, 0xb8, 0x08, 0x2a,
- 0x07, 0x89, 0x73, 0xc2, 0x45, 0x92, 0xc6, 0x90 },
+ .result = "\xe0\x4d\x5d\x3c\xb7\x8c\x36\x47"
+ "\x94\x18\x95\x91\xa9\xfc\x49\xf8"
+ "\x44\xd1\x2d\xc2\x99\xb8\x08\x2a"
+ "\x07\x89\x73\xc2\x45\x92\xc6\x90",
.rlen = 32,
}
};
static struct cipher_testvec tea_dec_tv_template[] = {
{
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .input = { 0x0a, 0x3a, 0xea, 0x41, 0x40, 0xa9, 0xba, 0x94 },
+ .input = "\x0a\x3a\xea\x41\x40\xa9\xba\x94",
.ilen = 8,
- .result = { [0 ... 8] = 0x00 },
+ .result = zeroed_string,
.rlen = 8,
}, {
- .key = { 0x2b, 0x02, 0x05, 0x68, 0x06, 0x14, 0x49, 0x76,
- 0x77, 0x5d, 0x0e, 0x26, 0x6c, 0x28, 0x78, 0x43 },
+ .key = "\x2b\x02\x05\x68\x06\x14\x49\x76"
+ "\x77\x5d\x0e\x26\x6c\x28\x78\x43",
.klen = 16,
- .input = { 0x77, 0x5d, 0x2a, 0x6a, 0xf6, 0xce, 0x92, 0x09 },
+ .input = "\x77\x5d\x2a\x6a\xf6\xce\x92\x09",
.ilen = 8,
- .result = { 0x74, 0x65, 0x73, 0x74, 0x20, 0x6d, 0x65, 0x2e },
+ .result = "\x74\x65\x73\x74\x20\x6d\x65\x2e",
.rlen = 8,
}, {
- .key = { 0x09, 0x65, 0x43, 0x11, 0x66, 0x44, 0x39, 0x25,
- 0x51, 0x3a, 0x16, 0x10, 0x0a, 0x08, 0x12, 0x6e },
+ .key = "\x09\x65\x43\x11\x66\x44\x39\x25"
+ "\x51\x3a\x16\x10\x0a\x08\x12\x6e",
.klen = 16,
- .input = { 0xbe, 0x7a, 0xbb, 0x81, 0x95, 0x2d, 0x1f, 0x1e,
- 0xdd, 0x89, 0xa1, 0x25, 0x04, 0x21, 0xdf, 0x95 },
+ .input = "\xbe\x7a\xbb\x81\x95\x2d\x1f\x1e"
+ "\xdd\x89\xa1\x25\x04\x21\xdf\x95",
.ilen = 16,
- .result = { 0x6c, 0x6f, 0x6e, 0x67, 0x65, 0x72, 0x5f, 0x74,
- 0x65, 0x73, 0x74, 0x5f, 0x76, 0x65, 0x63, 0x74 },
+ .result = "\x6c\x6f\x6e\x67\x65\x72\x5f\x74"
+ "\x65\x73\x74\x5f\x76\x65\x63\x74",
.rlen = 16,
}, {
- .key = { 0x4d, 0x76, 0x32, 0x17, 0x05, 0x3f, 0x75, 0x2c,
- 0x5d, 0x04, 0x16, 0x36, 0x15, 0x72, 0x63, 0x2f },
+ .key = "\x4d\x76\x32\x17\x05\x3f\x75\x2c"
+ "\x5d\x04\x16\x36\x15\x72\x63\x2f",
.klen = 16,
- .input = { 0xe0, 0x4d, 0x5d, 0x3c, 0xb7, 0x8c, 0x36, 0x47,
- 0x94, 0x18, 0x95, 0x91, 0xa9, 0xfc, 0x49, 0xf8,
- 0x44, 0xd1, 0x2d, 0xc2, 0x99, 0xb8, 0x08, 0x2a,
- 0x07, 0x89, 0x73, 0xc2, 0x45, 0x92, 0xc6, 0x90 },
+ .input = "\xe0\x4d\x5d\x3c\xb7\x8c\x36\x47"
+ "\x94\x18\x95\x91\xa9\xfc\x49\xf8"
+ "\x44\xd1\x2d\xc2\x99\xb8\x08\x2a"
+ "\x07\x89\x73\xc2\x45\x92\xc6\x90",
.ilen = 32,
- .result = { 0x54, 0x65, 0x61, 0x20, 0x69, 0x73, 0x20, 0x67,
- 0x6f, 0x6f, 0x64, 0x20, 0x66, 0x6f, 0x72, 0x20,
- 0x79, 0x6f, 0x75, 0x21, 0x21, 0x21, 0x20, 0x72,
- 0x65, 0x61, 0x6c, 0x6c, 0x79, 0x21, 0x21, 0x21 },
+ .result = "\x54\x65\x61\x20\x69\x73\x20\x67"
+ "\x6f\x6f\x64\x20\x66\x6f\x72\x20"
+ "\x79\x6f\x75\x21\x21\x21\x20\x72"
+ "\x65\x61\x6c\x6c\x79\x21\x21\x21",
.rlen = 32,
}
};
static struct cipher_testvec xtea_enc_tv_template[] = {
{
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .input = { [0 ... 8] = 0x00 },
+ .input = zeroed_string,
.ilen = 8,
- .result = { 0xd8, 0xd4, 0xe9, 0xde, 0xd9, 0x1e, 0x13, 0xf7 },
+ .result = "\xd8\xd4\xe9\xde\xd9\x1e\x13\xf7",
.rlen = 8,
}, {
- .key = { 0x2b, 0x02, 0x05, 0x68, 0x06, 0x14, 0x49, 0x76,
- 0x77, 0x5d, 0x0e, 0x26, 0x6c, 0x28, 0x78, 0x43 },
+ .key = "\x2b\x02\x05\x68\x06\x14\x49\x76"
+ "\x77\x5d\x0e\x26\x6c\x28\x78\x43",
.klen = 16,
- .input = { 0x74, 0x65, 0x73, 0x74, 0x20, 0x6d, 0x65, 0x2e },
+ .input = "\x74\x65\x73\x74\x20\x6d\x65\x2e",
.ilen = 8,
- .result = { 0x94, 0xeb, 0xc8, 0x96, 0x84, 0x6a, 0x49, 0xa8 },
+ .result = "\x94\xeb\xc8\x96\x84\x6a\x49\xa8",
.rlen = 8,
}, {
- .key = { 0x09, 0x65, 0x43, 0x11, 0x66, 0x44, 0x39, 0x25,
- 0x51, 0x3a, 0x16, 0x10, 0x0a, 0x08, 0x12, 0x6e },
+ .key = "\x09\x65\x43\x11\x66\x44\x39\x25"
+ "\x51\x3a\x16\x10\x0a\x08\x12\x6e",
.klen = 16,
- .input = { 0x3e, 0xce, 0xae, 0x22, 0x60, 0x56, 0xa8, 0x9d,
- 0x65, 0x73, 0x74, 0x5f, 0x76, 0x65, 0x63, 0x74 },
+ .input = "\x6c\x6f\x6e\x67\x65\x72\x5f\x74"
+ "\x65\x73\x74\x5f\x76\x65\x63\x74",
.ilen = 16,
- .result = { 0xe2, 0x04, 0xdb, 0xf2, 0x89, 0x85, 0x9e, 0xea,
- 0x61, 0x35, 0xaa, 0xed, 0xb5, 0xcb, 0x71, 0x2c },
+ .result = "\x3e\xce\xae\x22\x60\x56\xa8\x9d"
+ "\x77\x4d\xd4\xb4\x87\x24\xe3\x9a",
.rlen = 16,
}, {
- .key = { 0x4d, 0x76, 0x32, 0x17, 0x05, 0x3f, 0x75, 0x2c,
- 0x5d, 0x04, 0x16, 0x36, 0x15, 0x72, 0x63, 0x2f },
+ .key = "\x4d\x76\x32\x17\x05\x3f\x75\x2c"
+ "\x5d\x04\x16\x36\x15\x72\x63\x2f",
.klen = 16,
- .input = { 0x54, 0x65, 0x61, 0x20, 0x69, 0x73, 0x20, 0x67,
- 0x6f, 0x6f, 0x64, 0x20, 0x66, 0x6f, 0x72, 0x20,
- 0x79, 0x6f, 0x75, 0x21, 0x21, 0x21, 0x20, 0x72,
- 0x65, 0x61, 0x6c, 0x6c, 0x79, 0x21, 0x21, 0x21 },
+ .input = "\x54\x65\x61\x20\x69\x73\x20\x67"
+ "\x6f\x6f\x64\x20\x66\x6f\x72\x20"
+ "\x79\x6f\x75\x21\x21\x21\x20\x72"
+ "\x65\x61\x6c\x6c\x79\x21\x21\x21",
.ilen = 32,
- .result = { 0x99, 0x81, 0x9f, 0x5d, 0x6f, 0x4b, 0x31, 0x3a,
- 0x86, 0xff, 0x6f, 0xd0, 0xe3, 0x87, 0x70, 0x07,
- 0x4d, 0xb8, 0xcf, 0xf3, 0x99, 0x50, 0xb3, 0xd4,
- 0x73, 0xa2, 0xfa, 0xc9, 0x16, 0x59, 0x5d, 0x81 },
+ .result = "\x99\x81\x9f\x5d\x6f\x4b\x31\x3a"
+ "\x86\xff\x6f\xd0\xe3\x87\x70\x07"
+ "\x4d\xb8\xcf\xf3\x99\x50\xb3\xd4"
+ "\x73\xa2\xfa\xc9\x16\x59\x5d\x81",
.rlen = 32,
}
};
static struct cipher_testvec xtea_dec_tv_template[] = {
{
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .input = { 0xd8, 0xd4, 0xe9, 0xde, 0xd9, 0x1e, 0x13, 0xf7 },
+ .input = "\xd8\xd4\xe9\xde\xd9\x1e\x13\xf7",
.ilen = 8,
- .result = { [0 ... 8] = 0x00 },
+ .result = zeroed_string,
.rlen = 8,
}, {
- .key = { 0x2b, 0x02, 0x05, 0x68, 0x06, 0x14, 0x49, 0x76,
- 0x77, 0x5d, 0x0e, 0x26, 0x6c, 0x28, 0x78, 0x43 },
+ .key = "\x2b\x02\x05\x68\x06\x14\x49\x76"
+ "\x77\x5d\x0e\x26\x6c\x28\x78\x43",
.klen = 16,
- .input = { 0x94, 0xeb, 0xc8, 0x96, 0x84, 0x6a, 0x49, 0xa8 },
+ .input = "\x94\xeb\xc8\x96\x84\x6a\x49\xa8",
.ilen = 8,
- .result = { 0x74, 0x65, 0x73, 0x74, 0x20, 0x6d, 0x65, 0x2e },
+ .result = "\x74\x65\x73\x74\x20\x6d\x65\x2e",
.rlen = 8,
}, {
- .key = { 0x09, 0x65, 0x43, 0x11, 0x66, 0x44, 0x39, 0x25,
- 0x51, 0x3a, 0x16, 0x10, 0x0a, 0x08, 0x12, 0x6e },
+ .key = "\x09\x65\x43\x11\x66\x44\x39\x25"
+ "\x51\x3a\x16\x10\x0a\x08\x12\x6e",
.klen = 16,
- .input = { 0x3e, 0xce, 0xae, 0x22, 0x60, 0x56, 0xa8, 0x9d,
- 0x77, 0x4d, 0xd4, 0xb4, 0x87, 0x24, 0xe3, 0x9a },
+ .input = "\x3e\xce\xae\x22\x60\x56\xa8\x9d"
+ "\x77\x4d\xd4\xb4\x87\x24\xe3\x9a",
.ilen = 16,
- .result = { 0x6c, 0x6f, 0x6e, 0x67, 0x65, 0x72, 0x5f, 0x74,
- 0x65, 0x73, 0x74, 0x5f, 0x76, 0x65, 0x63, 0x74 },
+ .result = "\x6c\x6f\x6e\x67\x65\x72\x5f\x74"
+ "\x65\x73\x74\x5f\x76\x65\x63\x74",
.rlen = 16,
}, {
- .key = { 0x4d, 0x76, 0x32, 0x17, 0x05, 0x3f, 0x75, 0x2c,
- 0x5d, 0x04, 0x16, 0x36, 0x15, 0x72, 0x63, 0x2f },
+ .key = "\x4d\x76\x32\x17\x05\x3f\x75\x2c"
+ "\x5d\x04\x16\x36\x15\x72\x63\x2f",
.klen = 16,
- .input = { 0x99, 0x81, 0x9f, 0x5d, 0x6f, 0x4b, 0x31, 0x3a,
- 0x86, 0xff, 0x6f, 0xd0, 0xe3, 0x87, 0x70, 0x07,
- 0x4d, 0xb8, 0xcf, 0xf3, 0x99, 0x50, 0xb3, 0xd4,
- 0x73, 0xa2, 0xfa, 0xc9, 0x16, 0x59, 0x5d, 0x81 },
+ .input = "\x99\x81\x9f\x5d\x6f\x4b\x31\x3a"
+ "\x86\xff\x6f\xd0\xe3\x87\x70\x07"
+ "\x4d\xb8\xcf\xf3\x99\x50\xb3\xd4"
+ "\x73\xa2\xfa\xc9\x16\x59\x5d\x81",
.ilen = 32,
- .result = { 0x54, 0x65, 0x61, 0x20, 0x69, 0x73, 0x20, 0x67,
- 0x6f, 0x6f, 0x64, 0x20, 0x66, 0x6f, 0x72, 0x20,
- 0x79, 0x6f, 0x75, 0x21, 0x21, 0x21, 0x20, 0x72,
- 0x65, 0x61, 0x6c, 0x6c, 0x79, 0x21, 0x21, 0x21 },
+ .result = "\x54\x65\x61\x20\x69\x73\x20\x67"
+ "\x6f\x6f\x64\x20\x66\x6f\x72\x20"
+ "\x79\x6f\x75\x21\x21\x21\x20\x72"
+ "\x65\x61\x6c\x6c\x79\x21\x21\x21",
.rlen = 32,
}
};
static struct cipher_testvec khazad_enc_tv_template[] = {
{
- .key = { 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x80\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 16,
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00",
.ilen = 8,
- .result = { 0x49, 0xa4, 0xce, 0x32, 0xac, 0x19, 0x0e, 0x3f },
+ .result = "\x49\xa4\xce\x32\xac\x19\x0e\x3f",
.rlen = 8,
}, {
- .key = { 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38,
- 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38 },
+ .key = "\x38\x38\x38\x38\x38\x38\x38\x38"
+ "\x38\x38\x38\x38\x38\x38\x38\x38",
.klen = 16,
- .input = { 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38 },
+ .input = "\x38\x38\x38\x38\x38\x38\x38\x38",
.ilen = 8,
- .result = { 0x7e, 0x82, 0x12, 0xa1, 0Xd9, 0X5b, 0Xe4, 0Xf9 },
+ .result = "\x7e\x82\x12\xa1\xd9\x5b\xe4\xf9",
.rlen = 8,
}, {
- .key = { 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2,
- 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2 },
+ .key = "\xa2\xa2\xa2\xa2\xa2\xa2\xa2\xa2"
+ "\xa2\xa2\xa2\xa2\xa2\xa2\xa2\xa2",
.klen = 16,
- .input = { 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2 },
+ .input = "\xa2\xa2\xa2\xa2\xa2\xa2\xa2\xa2",
.ilen = 8,
- .result = { 0Xaa, 0Xbe, 0Xc1, 0X95, 0Xc5, 0X94, 0X1a, 0X9c },
+ .result = "\xaa\xbe\xc1\x95\xc5\x94\x1a\x9c",
.rlen = 8,
}, {
- .key = { 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f,
- 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f },
+ .key = "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f"
+ "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f",
.klen = 16,
- .input = { 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f },
+ .input = "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f",
.ilen = 8,
- .result = { 0X04, 0X74, 0Xf5, 0X70, 0X50, 0X16, 0Xd3, 0Xb8 },
+ .result = "\x04\x74\xf5\x70\x50\x16\xd3\xb8",
.rlen = 8,
}, {
- .key = { 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f,
- 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f },
+ .key = "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f"
+ "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f",
.klen = 16,
- .input = { 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f ,
- 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f },
+ .input = "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f"
+ "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f",
.ilen = 16,
- .result = { 0X04, 0X74, 0Xf5, 0X70, 0X50, 0X16, 0Xd3, 0Xb8 ,
- 0X04, 0X74, 0Xf5, 0X70, 0X50, 0X16, 0Xd3, 0Xb8 },
+ .result = "\x04\x74\xf5\x70\x50\x16\xd3\xb8"
+ "\x04\x74\xf5\x70\x50\x16\xd3\xb8",
.rlen = 16,
},
};
static struct cipher_testvec khazad_dec_tv_template[] = {
{
- .key = { 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x80\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 16,
- .input = { 0X49, 0Xa4, 0Xce, 0X32, 0Xac, 0X19, 0X0e, 0X3f },
+ .input = "\x49\xa4\xce\x32\xac\x19\x0e\x3f",
.ilen = 8,
- .result = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .result = "\x00\x00\x00\x00\x00\x00\x00\x00",
.rlen = 8,
}, {
- .key = { 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38,
- 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38 },
+ .key = "\x38\x38\x38\x38\x38\x38\x38\x38"
+ "\x38\x38\x38\x38\x38\x38\x38\x38",
.klen = 16,
- .input = { 0X7e, 0X82, 0X12, 0Xa1, 0Xd9, 0X5b, 0Xe4, 0Xf9 },
+ .input = "\x7e\x82\x12\xa1\xd9\x5b\xe4\xf9",
.ilen = 8,
- .result = { 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38 },
+ .result = "\x38\x38\x38\x38\x38\x38\x38\x38",
.rlen = 8,
}, {
- .key = { 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2,
- 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2 },
+ .key = "\xa2\xa2\xa2\xa2\xa2\xa2\xa2\xa2"
+ "\xa2\xa2\xa2\xa2\xa2\xa2\xa2\xa2",
.klen = 16,
- .input = { 0Xaa, 0Xbe, 0Xc1, 0X95, 0Xc5, 0X94, 0X1a, 0X9c },
+ .input = "\xaa\xbe\xc1\x95\xc5\x94\x1a\x9c",
.ilen = 8,
- .result = { 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2, 0Xa2 },
+ .result = "\xa2\xa2\xa2\xa2\xa2\xa2\xa2\xa2",
.rlen = 8,
}, {
- .key = { 0x2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f,
- 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f },
+ .key = "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f"
+ "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f",
.klen = 16,
- .input = { 0X04, 0X74, 0Xf5, 0X70, 0X50, 0X16, 0Xd3, 0Xb8 },
+ .input = "\x04\x74\xf5\x70\x50\x16\xd3\xb8",
.ilen = 8,
- .result = { 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f },
+ .result = "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f",
.rlen = 8,
}, {
- .key = { 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f,
- 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f },
+ .key = "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f"
+ "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f",
.klen = 16,
- .input = { 0X04, 0X74, 0Xf5, 0X70, 0X50, 0X16, 0Xd3, 0Xb8 ,
- 0X04, 0X74, 0Xf5, 0X70, 0X50, 0X16, 0Xd3, 0Xb8 },
+ .input = "\x04\x74\xf5\x70\x50\x16\xd3\xb8"
+ "\x04\x74\xf5\x70\x50\x16\xd3\xb8",
.ilen = 16,
- .result = { 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f ,
- 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f, 0X2f },
+ .result = "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f"
+ "\x2f\x2f\x2f\x2f\x2f\x2f\x2f\x2f",
.rlen = 16,
},
};
static struct cipher_testvec anubis_enc_tv_template[] = {
{
- .key = { 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe },
+ .key = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
.klen = 16,
- .input = { 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe },
+ .input = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
.ilen = 16,
- .result = { 0x6d, 0xc5, 0xda, 0xa2, 0x26, 0x7d, 0x62, 0x6f,
- 0x08, 0xb7, 0x52, 0x8e, 0x6e, 0x6e, 0x86, 0x90 },
+ .result = "\x6d\xc5\xda\xa2\x26\x7d\x62\x6f"
+ "\x08\xb7\x52\x8e\x6e\x6e\x86\x90",
.rlen = 16,
}, {
- .key = { 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03 },
+ .key = "\x03\x03\x03\x03\x03\x03\x03\x03"
+ "\x03\x03\x03\x03\x03\x03\x03\x03"
+ "\x03\x03\x03\x03",
.klen = 20,
- .input = { 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 },
+ .input = "\x03\x03\x03\x03\x03\x03\x03\x03"
+ "\x03\x03\x03\x03\x03\x03\x03\x03",
.ilen = 16,
- .result = { 0xdb, 0xf1, 0x42, 0xf4, 0xd1, 0x8a, 0xc7, 0x49,
- 0x87, 0x41, 0x6f, 0x82, 0x0a, 0x98, 0x64, 0xae },
+ .result = "\xdb\xf1\x42\xf4\xd1\x8a\xc7\x49"
+ "\x87\x41\x6f\x82\x0a\x98\x64\xae",
.rlen = 16,
}, {
- .key = { 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24,
- 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24,
- 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24,
- 0x24, 0x24, 0x24, 0x24 },
+ .key = "\x24\x24\x24\x24\x24\x24\x24\x24"
+ "\x24\x24\x24\x24\x24\x24\x24\x24"
+ "\x24\x24\x24\x24\x24\x24\x24\x24"
+ "\x24\x24\x24\x24",
.klen = 28,
- .input = { 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24,
- 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24 },
+ .input = "\x24\x24\x24\x24\x24\x24\x24\x24"
+ "\x24\x24\x24\x24\x24\x24\x24\x24",
.ilen = 16,
- .result = { 0xfd, 0x1b, 0x4a, 0xe3, 0xbf, 0xf0, 0xad, 0x3d,
- 0x06, 0xd3, 0x61, 0x27, 0xfd, 0x13, 0x9e, 0xde },
+ .result = "\xfd\x1b\x4a\xe3\xbf\xf0\xad\x3d"
+ "\x06\xd3\x61\x27\xfd\x13\x9e\xde",
.rlen = 16,
}, {
- .key = { 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
- 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
- 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
- 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25 },
+ .key = "\x25\x25\x25\x25\x25\x25\x25\x25"
+ "\x25\x25\x25\x25\x25\x25\x25\x25"
+ "\x25\x25\x25\x25\x25\x25\x25\x25"
+ "\x25\x25\x25\x25\x25\x25\x25\x25",
.klen = 32,
- .input = { 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
- 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25 },
+ .input = "\x25\x25\x25\x25\x25\x25\x25\x25"
+ "\x25\x25\x25\x25\x25\x25\x25\x25",
.ilen = 16,
- .result = { 0x1a, 0x91, 0xfb, 0x2b, 0xb7, 0x78, 0x6b, 0xc4,
- 0x17, 0xd9, 0xff, 0x40, 0x3b, 0x0e, 0xe5, 0xfe },
+ .result = "\x1a\x91\xfb\x2b\xb7\x78\x6b\xc4"
+ "\x17\xd9\xff\x40\x3b\x0e\xe5\xfe",
.rlen = 16,
}, {
- .key = { 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35 },
+ .key = "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35",
.klen = 40,
- .input = { 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35 },
+ .input = "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35",
.ilen = 16,
- .result = { 0xa5, 0x2c, 0x85, 0x6f, 0x9c, 0xba, 0xa0, 0x97,
- 0x9e, 0xc6, 0x84, 0x0f, 0x17, 0x21, 0x07, 0xee },
+ .result = "\xa5\x2c\x85\x6f\x9c\xba\xa0\x97"
+ "\x9e\xc6\x84\x0f\x17\x21\x07\xee",
.rlen = 16,
},
};
static struct cipher_testvec anubis_dec_tv_template[] = {
{
- .key = { 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe },
+ .key = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
.klen = 16,
- .input = { 0x6d, 0xc5, 0xda, 0xa2, 0x26, 0x7d, 0x62, 0x6f,
- 0x08, 0xb7, 0x52, 0x8e, 0x6e, 0x6e, 0x86, 0x90 },
+ .input = "\x6d\xc5\xda\xa2\x26\x7d\x62\x6f"
+ "\x08\xb7\x52\x8e\x6e\x6e\x86\x90",
.ilen = 16,
- .result = { 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe },
+ .result = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
.rlen = 16,
}, {
- .key = { 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03 },
+ .key = "\x03\x03\x03\x03\x03\x03\x03\x03"
+ "\x03\x03\x03\x03\x03\x03\x03\x03"
+ "\x03\x03\x03\x03",
.klen = 20,
- .input = { 0xdb, 0xf1, 0x42, 0xf4, 0xd1, 0x8a, 0xc7, 0x49,
- 0x87, 0x41, 0x6f, 0x82, 0x0a, 0x98, 0x64, 0xae },
+ .input = "\xdb\xf1\x42\xf4\xd1\x8a\xc7\x49"
+ "\x87\x41\x6f\x82\x0a\x98\x64\xae",
.ilen = 16,
- .result = { 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 },
+ .result = "\x03\x03\x03\x03\x03\x03\x03\x03"
+ "\x03\x03\x03\x03\x03\x03\x03\x03",
.rlen = 16,
}, {
- .key = { 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24,
- 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24,
- 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24,
- 0x24, 0x24, 0x24, 0x24 },
+ .key = "\x24\x24\x24\x24\x24\x24\x24\x24"
+ "\x24\x24\x24\x24\x24\x24\x24\x24"
+ "\x24\x24\x24\x24\x24\x24\x24\x24"
+ "\x24\x24\x24\x24",
.klen = 28,
- .input = { 0xfd, 0x1b, 0x4a, 0xe3, 0xbf, 0xf0, 0xad, 0x3d,
- 0x06, 0xd3, 0x61, 0x27, 0xfd, 0x13, 0x9e, 0xde },
+ .input = "\xfd\x1b\x4a\xe3\xbf\xf0\xad\x3d"
+ "\x06\xd3\x61\x27\xfd\x13\x9e\xde",
.ilen = 16,
- .result = { 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24,
- 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24 },
+ .result = "\x24\x24\x24\x24\x24\x24\x24\x24"
+ "\x24\x24\x24\x24\x24\x24\x24\x24",
.rlen = 16,
}, {
- .key = { 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
- 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
- 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
- 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25 },
+ .key = "\x25\x25\x25\x25\x25\x25\x25\x25"
+ "\x25\x25\x25\x25\x25\x25\x25\x25"
+ "\x25\x25\x25\x25\x25\x25\x25\x25"
+ "\x25\x25\x25\x25\x25\x25\x25\x25",
.klen = 32,
- .input = { 0x1a, 0x91, 0xfb, 0x2b, 0xb7, 0x78, 0x6b, 0xc4,
- 0x17, 0xd9, 0xff, 0x40, 0x3b, 0x0e, 0xe5, 0xfe },
+ .input = "\x1a\x91\xfb\x2b\xb7\x78\x6b\xc4"
+ "\x17\xd9\xff\x40\x3b\x0e\xe5\xfe",
.ilen = 16,
- .result = { 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25,
- 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25 },
+ .result = "\x25\x25\x25\x25\x25\x25\x25\x25"
+ "\x25\x25\x25\x25\x25\x25\x25\x25",
.rlen = 16,
}, {
- .key = { 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35 },
- .input = { 0xa5, 0x2c, 0x85, 0x6f, 0x9c, 0xba, 0xa0, 0x97,
- 0x9e, 0xc6, 0x84, 0x0f, 0x17, 0x21, 0x07, 0xee },
+ .key = "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35",
+ .input = "\xa5\x2c\x85\x6f\x9c\xba\xa0\x97"
+ "\x9e\xc6\x84\x0f\x17\x21\x07\xee",
.klen = 40,
.ilen = 16,
- .result = { 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35 },
+ .result = "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35",
.rlen = 16,
},
};
static struct cipher_testvec anubis_cbc_enc_tv_template[] = {
{
- .key = { 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe },
+ .key = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
.klen = 16,
- .input = { 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe },
+ .input = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
.ilen = 32,
- .result = { 0x6d, 0xc5, 0xda, 0xa2, 0x26, 0x7d, 0x62, 0x6f,
- 0x08, 0xb7, 0x52, 0x8e, 0x6e, 0x6e, 0x86, 0x90,
- 0x86, 0xd8, 0xb5, 0x6f, 0x98, 0x5e, 0x8a, 0x66,
- 0x4f, 0x1f, 0x78, 0xa1, 0xbb, 0x37, 0xf1, 0xbe },
+ .result = "\x6d\xc5\xda\xa2\x26\x7d\x62\x6f"
+ "\x08\xb7\x52\x8e\x6e\x6e\x86\x90"
+ "\x86\xd8\xb5\x6f\x98\x5e\x8a\x66"
+ "\x4f\x1f\x78\xa1\xbb\x37\xf1\xbe",
.rlen = 32,
}, {
- .key = { 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35 },
+ .key = "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35",
.klen = 40,
- .input = { 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35 },
+ .input = "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35",
.ilen = 32,
- .result = { 0xa5, 0x2c, 0x85, 0x6f, 0x9c, 0xba, 0xa0, 0x97,
- 0x9e, 0xc6, 0x84, 0x0f, 0x17, 0x21, 0x07, 0xee,
- 0xa2, 0xbc, 0x06, 0x98, 0xc6, 0x4b, 0xda, 0x75,
- 0x2e, 0xaa, 0xbe, 0x58, 0xce, 0x01, 0x5b, 0xc7 },
+ .result = "\xa5\x2c\x85\x6f\x9c\xba\xa0\x97"
+ "\x9e\xc6\x84\x0f\x17\x21\x07\xee"
+ "\xa2\xbc\x06\x98\xc6\x4b\xda\x75"
+ "\x2e\xaa\xbe\x58\xce\x01\x5b\xc7",
.rlen = 32,
},
};
static struct cipher_testvec anubis_cbc_dec_tv_template[] = {
{
- .key = { 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe },
+ .key = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
.klen = 16,
- .input = { 0x6d, 0xc5, 0xda, 0xa2, 0x26, 0x7d, 0x62, 0x6f,
- 0x08, 0xb7, 0x52, 0x8e, 0x6e, 0x6e, 0x86, 0x90,
- 0x86, 0xd8, 0xb5, 0x6f, 0x98, 0x5e, 0x8a, 0x66,
- 0x4f, 0x1f, 0x78, 0xa1, 0xbb, 0x37, 0xf1, 0xbe },
+ .input = "\x6d\xc5\xda\xa2\x26\x7d\x62\x6f"
+ "\x08\xb7\x52\x8e\x6e\x6e\x86\x90"
+ "\x86\xd8\xb5\x6f\x98\x5e\x8a\x66"
+ "\x4f\x1f\x78\xa1\xbb\x37\xf1\xbe",
.ilen = 32,
- .result = { 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe },
+ .result = "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
.rlen = 32,
}, {
- .key = { 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35 },
+ .key = "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35",
.klen = 40,
- .input = { 0xa5, 0x2c, 0x85, 0x6f, 0x9c, 0xba, 0xa0, 0x97,
- 0x9e, 0xc6, 0x84, 0x0f, 0x17, 0x21, 0x07, 0xee,
- 0xa2, 0xbc, 0x06, 0x98, 0xc6, 0x4b, 0xda, 0x75,
- 0x2e, 0xaa, 0xbe, 0x58, 0xce, 0x01, 0x5b, 0xc7 },
+ .input = "\xa5\x2c\x85\x6f\x9c\xba\xa0\x97"
+ "\x9e\xc6\x84\x0f\x17\x21\x07\xee"
+ "\xa2\xbc\x06\x98\xc6\x4b\xda\x75"
+ "\x2e\xaa\xbe\x58\xce\x01\x5b\xc7",
.ilen = 32,
- .result = { 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35,
- 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35 },
+ .result = "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35"
+ "\x35\x35\x35\x35\x35\x35\x35\x35",
.rlen = 32,
},
};
static struct cipher_testvec xeta_enc_tv_template[] = {
{
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .input = { [0 ... 8] = 0x00 },
+ .input = zeroed_string,
.ilen = 8,
- .result = { 0xaa, 0x22, 0x96, 0xe5, 0x6c, 0x61, 0xf3, 0x45 },
+ .result = "\xaa\x22\x96\xe5\x6c\x61\xf3\x45",
.rlen = 8,
}, {
- .key = { 0x2b, 0x02, 0x05, 0x68, 0x06, 0x14, 0x49, 0x76,
- 0x77, 0x5d, 0x0e, 0x26, 0x6c, 0x28, 0x78, 0x43 },
+ .key = "\x2b\x02\x05\x68\x06\x14\x49\x76"
+ "\x77\x5d\x0e\x26\x6c\x28\x78\x43",
.klen = 16,
- .input = { 0x74, 0x65, 0x73, 0x74, 0x20, 0x6d, 0x65, 0x2e },
+ .input = "\x74\x65\x73\x74\x20\x6d\x65\x2e",
.ilen = 8,
- .result = { 0x82, 0x3e, 0xeb, 0x35, 0xdc, 0xdd, 0xd9, 0xc3 },
+ .result = "\x82\x3e\xeb\x35\xdc\xdd\xd9\xc3",
.rlen = 8,
}, {
- .key = { 0x09, 0x65, 0x43, 0x11, 0x66, 0x44, 0x39, 0x25,
- 0x51, 0x3a, 0x16, 0x10, 0x0a, 0x08, 0x12, 0x6e },
+ .key = "\x09\x65\x43\x11\x66\x44\x39\x25"
+ "\x51\x3a\x16\x10\x0a\x08\x12\x6e",
.klen = 16,
- .input = { 0x6c, 0x6f, 0x6e, 0x67, 0x65, 0x72, 0x5f, 0x74,
- 0x65, 0x73, 0x74, 0x5f, 0x76, 0x65, 0x63, 0x74 },
+ .input = "\x6c\x6f\x6e\x67\x65\x72\x5f\x74"
+ "\x65\x73\x74\x5f\x76\x65\x63\x74",
.ilen = 16,
- .result = { 0xe2, 0x04, 0xdb, 0xf2, 0x89, 0x85, 0x9e, 0xea,
- 0x61, 0x35, 0xaa, 0xed, 0xb5, 0xcb, 0x71, 0x2c },
+ .result = "\xe2\x04\xdb\xf2\x89\x85\x9e\xea"
+ "\x61\x35\xaa\xed\xb5\xcb\x71\x2c",
.rlen = 16,
}, {
- .key = { 0x4d, 0x76, 0x32, 0x17, 0x05, 0x3f, 0x75, 0x2c,
- 0x5d, 0x04, 0x16, 0x36, 0x15, 0x72, 0x63, 0x2f },
+ .key = "\x4d\x76\x32\x17\x05\x3f\x75\x2c"
+ "\x5d\x04\x16\x36\x15\x72\x63\x2f",
.klen = 16,
- .input = { 0x54, 0x65, 0x61, 0x20, 0x69, 0x73, 0x20, 0x67,
- 0x6f, 0x6f, 0x64, 0x20, 0x66, 0x6f, 0x72, 0x20,
- 0x79, 0x6f, 0x75, 0x21, 0x21, 0x21, 0x20, 0x72,
- 0x65, 0x61, 0x6c, 0x6c, 0x79, 0x21, 0x21, 0x21 },
+ .input = "\x54\x65\x61\x20\x69\x73\x20\x67"
+ "\x6f\x6f\x64\x20\x66\x6f\x72\x20"
+ "\x79\x6f\x75\x21\x21\x21\x20\x72"
+ "\x65\x61\x6c\x6c\x79\x21\x21\x21",
.ilen = 32,
- .result = { 0x0b, 0x03, 0xcd, 0x8a, 0xbe, 0x95, 0xfd, 0xb1,
- 0xc1, 0x44, 0x91, 0x0b, 0xa5, 0xc9, 0x1b, 0xb4,
- 0xa9, 0xda, 0x1e, 0x9e, 0xb1, 0x3e, 0x2a, 0x8f,
- 0xea, 0xa5, 0x6a, 0x85, 0xd1, 0xf4, 0xa8, 0xa5 },
+ .result = "\x0b\x03\xcd\x8a\xbe\x95\xfd\xb1"
+ "\xc1\x44\x91\x0b\xa5\xc9\x1b\xb4"
+ "\xa9\xda\x1e\x9e\xb1\x3e\x2a\x8f"
+ "\xea\xa5\x6a\x85\xd1\xf4\xa8\xa5",
.rlen = 32,
}
};
static struct cipher_testvec xeta_dec_tv_template[] = {
{
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .input = { 0xaa, 0x22, 0x96, 0xe5, 0x6c, 0x61, 0xf3, 0x45 },
+ .input = "\xaa\x22\x96\xe5\x6c\x61\xf3\x45",
.ilen = 8,
- .result = { [0 ... 8] = 0x00 },
+ .result = zeroed_string,
.rlen = 8,
}, {
- .key = { 0x2b, 0x02, 0x05, 0x68, 0x06, 0x14, 0x49, 0x76,
- 0x77, 0x5d, 0x0e, 0x26, 0x6c, 0x28, 0x78, 0x43 },
+ .key = "\x2b\x02\x05\x68\x06\x14\x49\x76"
+ "\x77\x5d\x0e\x26\x6c\x28\x78\x43",
.klen = 16,
- .input = { 0x82, 0x3e, 0xeb, 0x35, 0xdc, 0xdd, 0xd9, 0xc3 },
+ .input = "\x82\x3e\xeb\x35\xdc\xdd\xd9\xc3",
.ilen = 8,
- .result = { 0x74, 0x65, 0x73, 0x74, 0x20, 0x6d, 0x65, 0x2e },
+ .result = "\x74\x65\x73\x74\x20\x6d\x65\x2e",
.rlen = 8,
}, {
- .key = { 0x09, 0x65, 0x43, 0x11, 0x66, 0x44, 0x39, 0x25,
- 0x51, 0x3a, 0x16, 0x10, 0x0a, 0x08, 0x12, 0x6e },
+ .key = "\x09\x65\x43\x11\x66\x44\x39\x25"
+ "\x51\x3a\x16\x10\x0a\x08\x12\x6e",
.klen = 16,
- .input = { 0xe2, 0x04, 0xdb, 0xf2, 0x89, 0x85, 0x9e, 0xea,
- 0x61, 0x35, 0xaa, 0xed, 0xb5, 0xcb, 0x71, 0x2c },
+ .input = "\xe2\x04\xdb\xf2\x89\x85\x9e\xea"
+ "\x61\x35\xaa\xed\xb5\xcb\x71\x2c",
.ilen = 16,
- .result = { 0x6c, 0x6f, 0x6e, 0x67, 0x65, 0x72, 0x5f, 0x74,
- 0x65, 0x73, 0x74, 0x5f, 0x76, 0x65, 0x63, 0x74 },
+ .result = "\x6c\x6f\x6e\x67\x65\x72\x5f\x74"
+ "\x65\x73\x74\x5f\x76\x65\x63\x74",
.rlen = 16,
}, {
- .key = { 0x4d, 0x76, 0x32, 0x17, 0x05, 0x3f, 0x75, 0x2c,
- 0x5d, 0x04, 0x16, 0x36, 0x15, 0x72, 0x63, 0x2f },
+ .key = "\x4d\x76\x32\x17\x05\x3f\x75\x2c"
+ "\x5d\x04\x16\x36\x15\x72\x63\x2f",
.klen = 16,
- .input = { 0x0b, 0x03, 0xcd, 0x8a, 0xbe, 0x95, 0xfd, 0xb1,
- 0xc1, 0x44, 0x91, 0x0b, 0xa5, 0xc9, 0x1b, 0xb4,
- 0xa9, 0xda, 0x1e, 0x9e, 0xb1, 0x3e, 0x2a, 0x8f,
- 0xea, 0xa5, 0x6a, 0x85, 0xd1, 0xf4, 0xa8, 0xa5 },
+ .input = "\x0b\x03\xcd\x8a\xbe\x95\xfd\xb1"
+ "\xc1\x44\x91\x0b\xa5\xc9\x1b\xb4"
+ "\xa9\xda\x1e\x9e\xb1\x3e\x2a\x8f"
+ "\xea\xa5\x6a\x85\xd1\xf4\xa8\xa5",
.ilen = 32,
- .result = { 0x54, 0x65, 0x61, 0x20, 0x69, 0x73, 0x20, 0x67,
- 0x6f, 0x6f, 0x64, 0x20, 0x66, 0x6f, 0x72, 0x20,
- 0x79, 0x6f, 0x75, 0x21, 0x21, 0x21, 0x20, 0x72,
- 0x65, 0x61, 0x6c, 0x6c, 0x79, 0x21, 0x21, 0x21 },
+ .result = "\x54\x65\x61\x20\x69\x73\x20\x67"
+ "\x6f\x6f\x64\x20\x66\x6f\x72\x20"
+ "\x79\x6f\x75\x21\x21\x21\x20\x72"
+ "\x65\x61\x6c\x6c\x79\x21\x21\x21",
.rlen = 32,
}
};
static struct cipher_testvec fcrypt_pcbc_enc_tv_template[] = {
{ /* http://www.openafs.org/pipermail/openafs-devel/2000-December/005320.html */
- .key = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 8,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00",
.ilen = 8,
- .result = { 0x0E, 0x09, 0x00, 0xC7, 0x3E, 0xF7, 0xED, 0x41 },
+ .result = "\x0E\x09\x00\xC7\x3E\xF7\xED\x41",
.rlen = 8,
}, {
- .key = { 0x11, 0x44, 0x77, 0xAA, 0xDD, 0x00, 0x33, 0x66 },
+ .key = "\x11\x44\x77\xAA\xDD\x00\x33\x66",
.klen = 8,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x12\x34\x56\x78\x9A\xBC\xDE\xF0",
.ilen = 8,
- .result = { 0xD8, 0xED, 0x78, 0x74, 0x77, 0xEC, 0x06, 0x80 },
+ .result = "\xD8\xED\x78\x74\x77\xEC\x06\x80",
.rlen = 8,
}, { /* From Arla */
- .key = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87 },
+ .key = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
.klen = 8,
- .iv = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .iv = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.input = "The quick brown fox jumps over the lazy dogs.\0\0",
.ilen = 48,
- .result = { 0x00, 0xf0, 0xe, 0x11, 0x75, 0xe6, 0x23, 0x82,
- 0xee, 0xac, 0x98, 0x62, 0x44, 0x51, 0xe4, 0x84,
- 0xc3, 0x59, 0xd8, 0xaa, 0x64, 0x60, 0xae, 0xf7,
- 0xd2, 0xd9, 0x13, 0x79, 0x72, 0xa3, 0x45, 0x03,
- 0x23, 0xb5, 0x62, 0xd7, 0x0c, 0xf5, 0x27, 0xd1,
- 0xf8, 0x91, 0x3c, 0xac, 0x44, 0x22, 0x92, 0xef },
+ .result = "\x00\xf0\x0e\x11\x75\xe6\x23\x82"
+ "\xee\xac\x98\x62\x44\x51\xe4\x84"
+ "\xc3\x59\xd8\xaa\x64\x60\xae\xf7"
+ "\xd2\xd9\x13\x79\x72\xa3\x45\x03"
+ "\x23\xb5\x62\xd7\x0c\xf5\x27\xd1"
+ "\xf8\x91\x3c\xac\x44\x22\x92\xef",
.rlen = 48,
}, {
- .key = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .key = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.klen = 8,
- .iv = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87 },
+ .iv = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
.input = "The quick brown fox jumps over the lazy dogs.\0\0",
.ilen = 48,
- .result = { 0xca, 0x90, 0xf5, 0x9d, 0xcb, 0xd4, 0xd2, 0x3c,
- 0x01, 0x88, 0x7f, 0x3e, 0x31, 0x6e, 0x62, 0x9d,
- 0xd8, 0xe0, 0x57, 0xa3, 0x06, 0x3a, 0x42, 0x58,
- 0x2a, 0x28, 0xfe, 0x72, 0x52, 0x2f, 0xdd, 0xe0,
- 0x19, 0x89, 0x09, 0x1c, 0x2a, 0x8e, 0x8c, 0x94,
- 0xfc, 0xc7, 0x68, 0xe4, 0x88, 0xaa, 0xde, 0x0f },
+ .result = "\xca\x90\xf5\x9d\xcb\xd4\xd2\x3c"
+ "\x01\x88\x7f\x3e\x31\x6e\x62\x9d"
+ "\xd8\xe0\x57\xa3\x06\x3a\x42\x58"
+ "\x2a\x28\xfe\x72\x52\x2f\xdd\xe0"
+ "\x19\x89\x09\x1c\x2a\x8e\x8c\x94"
+ "\xfc\xc7\x68\xe4\x88\xaa\xde\x0f",
.rlen = 48,
}, { /* split-page version */
- .key = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .key = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.klen = 8,
- .iv = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87 },
+ .iv = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
.input = "The quick brown fox jumps over the lazy dogs.\0\0",
.ilen = 48,
- .result = { 0xca, 0x90, 0xf5, 0x9d, 0xcb, 0xd4, 0xd2, 0x3c,
- 0x01, 0x88, 0x7f, 0x3e, 0x31, 0x6e, 0x62, 0x9d,
- 0xd8, 0xe0, 0x57, 0xa3, 0x06, 0x3a, 0x42, 0x58,
- 0x2a, 0x28, 0xfe, 0x72, 0x52, 0x2f, 0xdd, 0xe0,
- 0x19, 0x89, 0x09, 0x1c, 0x2a, 0x8e, 0x8c, 0x94,
- 0xfc, 0xc7, 0x68, 0xe4, 0x88, 0xaa, 0xde, 0x0f },
+ .result = "\xca\x90\xf5\x9d\xcb\xd4\xd2\x3c"
+ "\x01\x88\x7f\x3e\x31\x6e\x62\x9d"
+ "\xd8\xe0\x57\xa3\x06\x3a\x42\x58"
+ "\x2a\x28\xfe\x72\x52\x2f\xdd\xe0"
+ "\x19\x89\x09\x1c\x2a\x8e\x8c\x94"
+ "\xfc\xc7\x68\xe4\x88\xaa\xde\x0f",
.rlen = 48,
.np = 2,
.tap = { 20, 28 },
static struct cipher_testvec fcrypt_pcbc_dec_tv_template[] = {
{ /* http://www.openafs.org/pipermail/openafs-devel/2000-December/005320.html */
- .key = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 8,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0x0E, 0x09, 0x00, 0xC7, 0x3E, 0xF7, 0xED, 0x41 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x0E\x09\x00\xC7\x3E\xF7\xED\x41",
.ilen = 8,
- .result = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .result = "\x00\x00\x00\x00\x00\x00\x00\x00",
.rlen = 8,
}, {
- .key = { 0x11, 0x44, 0x77, 0xAA, 0xDD, 0x00, 0x33, 0x66 },
+ .key = "\x11\x44\x77\xAA\xDD\x00\x33\x66",
.klen = 8,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = { 0xD8, 0xED, 0x78, 0x74, 0x77, 0xEC, 0x06, 0x80 },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\xD8\xED\x78\x74\x77\xEC\x06\x80",
.ilen = 8,
- .result = { 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0 },
+ .result = "\x12\x34\x56\x78\x9A\xBC\xDE\xF0",
.rlen = 8,
}, { /* From Arla */
- .key = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87 },
+ .key = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
.klen = 8,
- .iv = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
- .input = { 0x00, 0xf0, 0xe, 0x11, 0x75, 0xe6, 0x23, 0x82,
- 0xee, 0xac, 0x98, 0x62, 0x44, 0x51, 0xe4, 0x84,
- 0xc3, 0x59, 0xd8, 0xaa, 0x64, 0x60, 0xae, 0xf7,
- 0xd2, 0xd9, 0x13, 0x79, 0x72, 0xa3, 0x45, 0x03,
- 0x23, 0xb5, 0x62, 0xd7, 0x0c, 0xf5, 0x27, 0xd1,
- 0xf8, 0x91, 0x3c, 0xac, 0x44, 0x22, 0x92, 0xef },
+ .iv = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
+ .input = "\x00\xf0\x0e\x11\x75\xe6\x23\x82"
+ "\xee\xac\x98\x62\x44\x51\xe4\x84"
+ "\xc3\x59\xd8\xaa\x64\x60\xae\xf7"
+ "\xd2\xd9\x13\x79\x72\xa3\x45\x03"
+ "\x23\xb5\x62\xd7\x0c\xf5\x27\xd1"
+ "\xf8\x91\x3c\xac\x44\x22\x92\xef",
.ilen = 48,
.result = "The quick brown fox jumps over the lazy dogs.\0\0",
.rlen = 48,
}, {
- .key = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .key = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.klen = 8,
- .iv = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87 },
- .input = { 0xca, 0x90, 0xf5, 0x9d, 0xcb, 0xd4, 0xd2, 0x3c,
- 0x01, 0x88, 0x7f, 0x3e, 0x31, 0x6e, 0x62, 0x9d,
- 0xd8, 0xe0, 0x57, 0xa3, 0x06, 0x3a, 0x42, 0x58,
- 0x2a, 0x28, 0xfe, 0x72, 0x52, 0x2f, 0xdd, 0xe0,
- 0x19, 0x89, 0x09, 0x1c, 0x2a, 0x8e, 0x8c, 0x94,
- 0xfc, 0xc7, 0x68, 0xe4, 0x88, 0xaa, 0xde, 0x0f },
+ .iv = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
+ .input = "\xca\x90\xf5\x9d\xcb\xd4\xd2\x3c"
+ "\x01\x88\x7f\x3e\x31\x6e\x62\x9d"
+ "\xd8\xe0\x57\xa3\x06\x3a\x42\x58"
+ "\x2a\x28\xfe\x72\x52\x2f\xdd\xe0"
+ "\x19\x89\x09\x1c\x2a\x8e\x8c\x94"
+ "\xfc\xc7\x68\xe4\x88\xaa\xde\x0f",
.ilen = 48,
.result = "The quick brown fox jumps over the lazy dogs.\0\0",
.rlen = 48,
}, { /* split-page version */
- .key = { 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .key = "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.klen = 8,
- .iv = { 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87 },
- .input = { 0xca, 0x90, 0xf5, 0x9d, 0xcb, 0xd4, 0xd2, 0x3c,
- 0x01, 0x88, 0x7f, 0x3e, 0x31, 0x6e, 0x62, 0x9d,
- 0xd8, 0xe0, 0x57, 0xa3, 0x06, 0x3a, 0x42, 0x58,
- 0x2a, 0x28, 0xfe, 0x72, 0x52, 0x2f, 0xdd, 0xe0,
- 0x19, 0x89, 0x09, 0x1c, 0x2a, 0x8e, 0x8c, 0x94,
- 0xfc, 0xc7, 0x68, 0xe4, 0x88, 0xaa, 0xde, 0x0f },
+ .iv = "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
+ .input = "\xca\x90\xf5\x9d\xcb\xd4\xd2\x3c"
+ "\x01\x88\x7f\x3e\x31\x6e\x62\x9d"
+ "\xd8\xe0\x57\xa3\x06\x3a\x42\x58"
+ "\x2a\x28\xfe\x72\x52\x2f\xdd\xe0"
+ "\x19\x89\x09\x1c\x2a\x8e\x8c\x94"
+ "\xfc\xc7\x68\xe4\x88\xaa\xde\x0f",
.ilen = 48,
.result = "The quick brown fox jumps over the lazy dogs.\0\0",
.rlen = 48,
static struct cipher_testvec camellia_enc_tv_template[] = {
{
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.klen = 16,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.ilen = 16,
- .result = { 0x67, 0x67, 0x31, 0x38, 0x54, 0x96, 0x69, 0x73,
- 0x08, 0x57, 0x06, 0x56, 0x48, 0xea, 0xbe, 0x43 },
+ .result = "\x67\x67\x31\x38\x54\x96\x69\x73"
+ "\x08\x57\x06\x56\x48\xea\xbe\x43",
.rlen = 16,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10"
+ "\x00\x11\x22\x33\x44\x55\x66\x77",
.klen = 24,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.ilen = 16,
- .result = { 0xb4, 0x99, 0x34, 0x01, 0xb3, 0xe9, 0x96, 0xf8,
- 0x4e, 0xe5, 0xce, 0xe7, 0xd7, 0x9b, 0x09, 0xb9 },
+ .result = "\xb4\x99\x34\x01\xb3\xe9\x96\xf8"
+ "\x4e\xe5\xce\xe7\xd7\x9b\x09\xb9",
.rlen = 16,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10"
+ "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x88\x99\xaa\xbb\xcc\xdd\xee\xff",
.klen = 32,
- .input = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .input = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.ilen = 16,
- .result = { 0x9a, 0xcc, 0x23, 0x7d, 0xff, 0x16, 0xd7, 0x6c,
- 0x20, 0xef, 0x7c, 0x91, 0x9e, 0x3a, 0x75, 0x09 },
+ .result = "\x9a\xcc\x23\x7d\xff\x16\xd7\x6c"
+ "\x20\xef\x7c\x91\x9e\x3a\x75\x09",
.rlen = 16,
},
};
static struct cipher_testvec camellia_dec_tv_template[] = {
{
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.klen = 16,
- .input = { 0x67, 0x67, 0x31, 0x38, 0x54, 0x96, 0x69, 0x73,
- 0x08, 0x57, 0x06, 0x56, 0x48, 0xea, 0xbe, 0x43 },
+ .input = "\x67\x67\x31\x38\x54\x96\x69\x73"
+ "\x08\x57\x06\x56\x48\xea\xbe\x43",
.ilen = 16,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.rlen = 16,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10"
+ "\x00\x11\x22\x33\x44\x55\x66\x77",
.klen = 24,
- .input = { 0xb4, 0x99, 0x34, 0x01, 0xb3, 0xe9, 0x96, 0xf8,
- 0x4e, 0xe5, 0xce, 0xe7, 0xd7, 0x9b, 0x09, 0xb9 },
+ .input = "\xb4\x99\x34\x01\xb3\xe9\x96\xf8"
+ "\x4e\xe5\xce\xe7\xd7\x9b\x09\xb9",
.ilen = 16,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.rlen = 16,
}, {
- .key = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
- 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff },
+ .key = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10"
+ "\x00\x11\x22\x33\x44\x55\x66\x77"
+ "\x88\x99\xaa\xbb\xcc\xdd\xee\xff",
.klen = 32,
- .input = { 0x9a, 0xcc, 0x23, 0x7d, 0xff, 0x16, 0xd7, 0x6c,
- 0x20, 0xef, 0x7c, 0x91, 0x9e, 0x3a, 0x75, 0x09 },
+ .input = "\x9a\xcc\x23\x7d\xff\x16\xd7\x6c"
+ "\x20\xef\x7c\x91\x9e\x3a\x75\x09",
.ilen = 16,
- .result = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
- 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 },
+ .result = "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ "\xfe\xdc\xba\x98\x76\x54\x32\x10",
.rlen = 16,
},
};
static struct cipher_testvec camellia_cbc_enc_tv_template[] = {
{
- .key = { 0x06, 0xa9, 0x21, 0x40, 0x36, 0xb8, 0xa1, 0x5b,
- 0x51, 0x2e, 0x03, 0xd5, 0x34, 0x12, 0x00, 0x06 },
+ .key = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b"
+ "\x51\x2e\x03\xd5\x34\x12\x00\x06",
.klen = 16,
- .iv = { 0x3d, 0xaf, 0xba, 0x42, 0x9d, 0x9e, 0xb4, 0x30,
- 0xb4, 0x22, 0xda, 0x80, 0x2c, 0x9f, 0xac, 0x41 },
- .input = { "Single block msg" },
+ .iv = "\x3d\xaf\xba\x42\x9d\x9e\xb4\x30"
+ "\xb4\x22\xda\x80\x2c\x9f\xac\x41",
+ .input = "Single block msg",
.ilen = 16,
- .result = { 0xea, 0x32, 0x12, 0x76, 0x3b, 0x50, 0x10, 0xe7,
- 0x18, 0xf6, 0xfd, 0x5d, 0xf6, 0x8f, 0x13, 0x51 },
+ .result = "\xea\x32\x12\x76\x3b\x50\x10\xe7"
+ "\x18\xf6\xfd\x5d\xf6\x8f\x13\x51",
.rlen = 16,
}, {
- .key = { 0xc2, 0x86, 0x69, 0x6d, 0x88, 0x7c, 0x9a, 0xa0,
- 0x61, 0x1b, 0xbb, 0x3e, 0x20, 0x25, 0xa4, 0x5a },
+ .key = "\xc2\x86\x69\x6d\x88\x7c\x9a\xa0"
+ "\x61\x1b\xbb\x3e\x20\x25\xa4\x5a",
.klen = 16,
- .iv = { 0x56, 0x2e, 0x17, 0x99, 0x6d, 0x09, 0x3d, 0x28,
- 0xdd, 0xb3, 0xba, 0x69, 0x5a, 0x2e, 0x6f, 0x58 },
- .input = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .iv = "\x56\x2e\x17\x99\x6d\x09\x3d\x28"
+ "\xdd\xb3\xba\x69\x5a\x2e\x6f\x58",
+ .input = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.ilen = 32,
- .result = { 0xa5, 0xdf, 0x6e, 0x50, 0xda, 0x70, 0x6c, 0x01,
- 0x4a, 0xab, 0xf3, 0xf2, 0xd6, 0xfc, 0x6c, 0xfd,
- 0x19, 0xb4, 0x3e, 0x57, 0x1c, 0x02, 0x5e, 0xa0,
- 0x15, 0x78, 0xe0, 0x5e, 0xf2, 0xcb, 0x87, 0x16 },
+ .result = "\xa5\xdf\x6e\x50\xda\x70\x6c\x01"
+ "\x4a\xab\xf3\xf2\xd6\xfc\x6c\xfd"
+ "\x19\xb4\x3e\x57\x1c\x02\x5e\xa0"
+ "\x15\x78\xe0\x5e\xf2\xcb\x87\x16",
.rlen = 32,
},
};
static struct cipher_testvec camellia_cbc_dec_tv_template[] = {
{
- .key = { 0x06, 0xa9, 0x21, 0x40, 0x36, 0xb8, 0xa1, 0x5b,
- 0x51, 0x2e, 0x03, 0xd5, 0x34, 0x12, 0x00, 0x06 },
+ .key = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b"
+ "\x51\x2e\x03\xd5\x34\x12\x00\x06",
.klen = 16,
- .iv = { 0x3d, 0xaf, 0xba, 0x42, 0x9d, 0x9e, 0xb4, 0x30,
- 0xb4, 0x22, 0xda, 0x80, 0x2c, 0x9f, 0xac, 0x41 },
- .input = { 0xea, 0x32, 0x12, 0x76, 0x3b, 0x50, 0x10, 0xe7,
- 0x18, 0xf6, 0xfd, 0x5d, 0xf6, 0x8f, 0x13, 0x51 },
+ .iv = "\x3d\xaf\xba\x42\x9d\x9e\xb4\x30"
+ "\xb4\x22\xda\x80\x2c\x9f\xac\x41",
+ .input = "\xea\x32\x12\x76\x3b\x50\x10\xe7"
+ "\x18\xf6\xfd\x5d\xf6\x8f\x13\x51",
.ilen = 16,
- .result = { "Single block msg" },
+ .result = "Single block msg",
.rlen = 16,
}, {
- .key = { 0xc2, 0x86, 0x69, 0x6d, 0x88, 0x7c, 0x9a, 0xa0,
- 0x61, 0x1b, 0xbb, 0x3e, 0x20, 0x25, 0xa4, 0x5a },
+ .key = "\xc2\x86\x69\x6d\x88\x7c\x9a\xa0"
+ "\x61\x1b\xbb\x3e\x20\x25\xa4\x5a",
.klen = 16,
- .iv = { 0x56, 0x2e, 0x17, 0x99, 0x6d, 0x09, 0x3d, 0x28,
- 0xdd, 0xb3, 0xba, 0x69, 0x5a, 0x2e, 0x6f, 0x58 },
- .input = { 0xa5, 0xdf, 0x6e, 0x50, 0xda, 0x70, 0x6c, 0x01,
- 0x4a, 0xab, 0xf3, 0xf2, 0xd6, 0xfc, 0x6c, 0xfd,
- 0x19, 0xb4, 0x3e, 0x57, 0x1c, 0x02, 0x5e, 0xa0,
- 0x15, 0x78, 0xe0, 0x5e, 0xf2, 0xcb, 0x87, 0x16 },
+ .iv = "\x56\x2e\x17\x99\x6d\x09\x3d\x28"
+ "\xdd\xb3\xba\x69\x5a\x2e\x6f\x58",
+ .input = "\xa5\xdf\x6e\x50\xda\x70\x6c\x01"
+ "\x4a\xab\xf3\xf2\xd6\xfc\x6c\xfd"
+ "\x19\xb4\x3e\x57\x1c\x02\x5e\xa0"
+ "\x15\x78\xe0\x5e\xf2\xcb\x87\x16",
.ilen = 32,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.rlen = 32,
},
};
static struct cipher_testvec seed_enc_tv_template[] = {
{
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .input = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .input = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.ilen = 16,
- .result = { 0x5e, 0xba, 0xc6, 0xe0, 0x05, 0x4e, 0x16, 0x68,
- 0x19, 0xaf, 0xf1, 0xcc, 0x6d, 0x34, 0x6c, 0xdb },
+ .result = "\x5e\xba\xc6\xe0\x05\x4e\x16\x68"
+ "\x19\xaf\xf1\xcc\x6d\x34\x6c\xdb",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.klen = 16,
- .input = { [0 ... 15] = 0x00 },
+ .input = zeroed_string,
.ilen = 16,
- .result = { 0xc1, 0x1f, 0x22, 0xf2, 0x01, 0x40, 0x50, 0x50,
- 0x84, 0x48, 0x35, 0x97, 0xe4, 0x37, 0x0f, 0x43 },
+ .result = "\xc1\x1f\x22\xf2\x01\x40\x50\x50"
+ "\x84\x48\x35\x97\xe4\x37\x0f\x43",
.rlen = 16,
}, {
- .key = { 0x47, 0x06, 0x48, 0x08, 0x51, 0xe6, 0x1b, 0xe8,
- 0x5d, 0x74, 0xbf, 0xb3, 0xfd, 0x95, 0x61, 0x85 },
+ .key = "\x47\x06\x48\x08\x51\xe6\x1b\xe8"
+ "\x5d\x74\xbf\xb3\xfd\x95\x61\x85",
.klen = 16,
- .input = { 0x83, 0xa2, 0xf8, 0xa2, 0x88, 0x64, 0x1f, 0xb9,
- 0xa4, 0xe9, 0xa5, 0xcc, 0x2f, 0x13, 0x1c, 0x7d },
+ .input = "\x83\xa2\xf8\xa2\x88\x64\x1f\xb9"
+ "\xa4\xe9\xa5\xcc\x2f\x13\x1c\x7d",
.ilen = 16,
- .result = { 0xee, 0x54, 0xd1, 0x3e, 0xbc, 0xae, 0x70, 0x6d,
- 0x22, 0x6b, 0xc3, 0x14, 0x2c, 0xd4, 0x0d, 0x4a },
+ .result = "\xee\x54\xd1\x3e\xbc\xae\x70\x6d"
+ "\x22\x6b\xc3\x14\x2c\xd4\x0d\x4a",
.rlen = 16,
}, {
- .key = { 0x28, 0xdb, 0xc3, 0xbc, 0x49, 0xff, 0xd8, 0x7d,
- 0xcf, 0xa5, 0x09, 0xb1, 0x1d, 0x42, 0x2b, 0xe7 },
+ .key = "\x28\xdb\xc3\xbc\x49\xff\xd8\x7d"
+ "\xcf\xa5\x09\xb1\x1d\x42\x2b\xe7",
.klen = 16,
- .input = { 0xb4, 0x1e, 0x6b, 0xe2, 0xeb, 0xa8, 0x4a, 0x14,
- 0x8e, 0x2e, 0xed, 0x84, 0x59, 0x3c, 0x5e, 0xc7 },
+ .input = "\xb4\x1e\x6b\xe2\xeb\xa8\x4a\x14"
+ "\x8e\x2e\xed\x84\x59\x3c\x5e\xc7",
.ilen = 16,
- .result = { 0x9b, 0x9b, 0x7b, 0xfc, 0xd1, 0x81, 0x3c, 0xb9,
- 0x5d, 0x0b, 0x36, 0x18, 0xf4, 0x0f, 0x51, 0x22 },
+ .result = "\x9b\x9b\x7b\xfc\xd1\x81\x3c\xb9"
+ "\x5d\x0b\x36\x18\xf4\x0f\x51\x22",
.rlen = 16,
}
};
static struct cipher_testvec seed_dec_tv_template[] = {
{
- .key = { [0 ... 15] = 0x00 },
+ .key = zeroed_string,
.klen = 16,
- .input = { 0x5e, 0xba, 0xc6, 0xe0, 0x05, 0x4e, 0x16, 0x68,
- 0x19, 0xaf, 0xf1, 0xcc, 0x6d, 0x34, 0x6c, 0xdb },
+ .input = "\x5e\xba\xc6\xe0\x05\x4e\x16\x68"
+ "\x19\xaf\xf1\xcc\x6d\x34\x6c\xdb",
.ilen = 16,
- .result = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .result = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.rlen = 16,
}, {
- .key = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
.klen = 16,
- .input = { 0xc1, 0x1f, 0x22, 0xf2, 0x01, 0x40, 0x50, 0x50,
- 0x84, 0x48, 0x35, 0x97, 0xe4, 0x37, 0x0f, 0x43 },
+ .input = "\xc1\x1f\x22\xf2\x01\x40\x50\x50"
+ "\x84\x48\x35\x97\xe4\x37\x0f\x43",
.ilen = 16,
- .result = { [0 ... 15] = 0x00 },
+ .result = zeroed_string,
.rlen = 16,
}, {
- .key = { 0x47, 0x06, 0x48, 0x08, 0x51, 0xe6, 0x1b, 0xe8,
- 0x5d, 0x74, 0xbf, 0xb3, 0xfd, 0x95, 0x61, 0x85 },
+ .key = "\x47\x06\x48\x08\x51\xe6\x1b\xe8"
+ "\x5d\x74\xbf\xb3\xfd\x95\x61\x85",
.klen = 16,
- .input = { 0xee, 0x54, 0xd1, 0x3e, 0xbc, 0xae, 0x70, 0x6d,
- 0x22, 0x6b, 0xc3, 0x14, 0x2c, 0xd4, 0x0d, 0x4a },
+ .input = "\xee\x54\xd1\x3e\xbc\xae\x70\x6d"
+ "\x22\x6b\xc3\x14\x2c\xd4\x0d\x4a",
.ilen = 16,
- .result = { 0x83, 0xa2, 0xf8, 0xa2, 0x88, 0x64, 0x1f, 0xb9,
- 0xa4, 0xe9, 0xa5, 0xcc, 0x2f, 0x13, 0x1c, 0x7d },
+ .result = "\x83\xa2\xf8\xa2\x88\x64\x1f\xb9"
+ "\xa4\xe9\xa5\xcc\x2f\x13\x1c\x7d",
.rlen = 16,
}, {
- .key = { 0x28, 0xdb, 0xc3, 0xbc, 0x49, 0xff, 0xd8, 0x7d,
- 0xcf, 0xa5, 0x09, 0xb1, 0x1d, 0x42, 0x2b, 0xe7 },
+ .key = "\x28\xdb\xc3\xbc\x49\xff\xd8\x7d"
+ "\xcf\xa5\x09\xb1\x1d\x42\x2b\xe7",
.klen = 16,
- .input = { 0x9b, 0x9b, 0x7b, 0xfc, 0xd1, 0x81, 0x3c, 0xb9,
- 0x5d, 0x0b, 0x36, 0x18, 0xf4, 0x0f, 0x51, 0x22 },
+ .input = "\x9b\x9b\x7b\xfc\xd1\x81\x3c\xb9"
+ "\x5d\x0b\x36\x18\xf4\x0f\x51\x22",
.ilen = 16,
- .result = { 0xb4, 0x1e, 0x6b, 0xe2, 0xeb, 0xa8, 0x4a, 0x14,
- 0x8e, 0x2e, 0xed, 0x84, 0x59, 0x3c, 0x5e, 0xc7 },
+ .result = "\xb4\x1e\x6b\xe2\xeb\xa8\x4a\x14"
+ "\x8e\x2e\xed\x84\x59\x3c\x5e\xc7",
.rlen = 16,
}
};
* of input length.
*/
{ /* Set 3, vector 0 */
- .key = {
- 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
- },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0A\x0B\x0C\x0D\x0E\x0F",
.klen = 16,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00",
.ilen = 39,
- .result = {
- 0x2D, 0xD5, 0xC3, 0xF7, 0xBA, 0x2B, 0x20, 0xF7,
- 0x68, 0x02, 0x41, 0x0C, 0x68, 0x86, 0x88, 0x89,
- 0x5A, 0xD8, 0xC1, 0xBD, 0x4E, 0xA6, 0xC9, 0xB1,
- 0x40, 0xFB, 0x9B, 0x90, 0xE2, 0x10, 0x49, 0xBF,
- 0x58, 0x3F, 0x52, 0x79, 0x70, 0xEB, 0xC1,
- },
+ .result = "\x2D\xD5\xC3\xF7\xBA\x2B\x20\xF7"
+ "\x68\x02\x41\x0C\x68\x86\x88\x89"
+ "\x5A\xD8\xC1\xBD\x4E\xA6\xC9\xB1"
+ "\x40\xFB\x9B\x90\xE2\x10\x49\xBF"
+ "\x58\x3F\x52\x79\x70\xEB\xC1",
.rlen = 39,
}, { /* Set 5, vector 0 */
- .key = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 16,
- .iv = { 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- },
+ .iv = "\x80\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.ilen = 64,
- .result = {
- 0xB6, 0x6C, 0x1E, 0x44, 0x46, 0xDD, 0x95, 0x57,
- 0xE5, 0x78, 0xE2, 0x23, 0xB0, 0xB7, 0x68, 0x01,
- 0x7B, 0x23, 0xB2, 0x67, 0xBB, 0x02, 0x34, 0xAE,
- 0x46, 0x26, 0xBF, 0x44, 0x3F, 0x21, 0x97, 0x76,
- 0x43, 0x6F, 0xB1, 0x9F, 0xD0, 0xE8, 0x86, 0x6F,
- 0xCD, 0x0D, 0xE9, 0xA9, 0x53, 0x8F, 0x4A, 0x09,
- 0xCA, 0x9A, 0xC0, 0x73, 0x2E, 0x30, 0xBC, 0xF9,
- 0x8E, 0x4F, 0x13, 0xE4, 0xB9, 0xE2, 0x01, 0xD9,
- },
+ .result = "\xB6\x6C\x1E\x44\x46\xDD\x95\x57"
+ "\xE5\x78\xE2\x23\xB0\xB7\x68\x01"
+ "\x7B\x23\xB2\x67\xBB\x02\x34\xAE"
+ "\x46\x26\xBF\x44\x3F\x21\x97\x76"
+ "\x43\x6F\xB1\x9F\xD0\xE8\x86\x6F"
+ "\xCD\x0D\xE9\xA9\x53\x8F\x4A\x09"
+ "\xCA\x9A\xC0\x73\x2E\x30\xBC\xF9"
+ "\x8E\x4F\x13\xE4\xB9\xE2\x01\xD9",
.rlen = 64,
}, { /* Set 3, vector 27 */
- .key = {
- 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22,
- 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A,
- 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32,
- 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A
- },
+ .key = "\x1B\x1C\x1D\x1E\x1F\x20\x21\x22"
+ "\x23\x24\x25\x26\x27\x28\x29\x2A"
+ "\x2B\x2C\x2D\x2E\x2F\x30\x31\x32"
+ "\x33\x34\x35\x36\x37\x38\x39\x3A",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
- .input = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00",
.ilen = 111,
- .result = {
- 0xAE, 0x39, 0x50, 0x8E, 0xAC, 0x9A, 0xEC, 0xE7,
- 0xBF, 0x97, 0xBB, 0x20, 0xB9, 0xDE, 0xE4, 0x1F,
- 0x87, 0xD9, 0x47, 0xF8, 0x28, 0x91, 0x35, 0x98,
- 0xDB, 0x72, 0xCC, 0x23, 0x29, 0x48, 0x56, 0x5E,
- 0x83, 0x7E, 0x0B, 0xF3, 0x7D, 0x5D, 0x38, 0x7B,
- 0x2D, 0x71, 0x02, 0xB4, 0x3B, 0xB5, 0xD8, 0x23,
- 0xB0, 0x4A, 0xDF, 0x3C, 0xEC, 0xB6, 0xD9, 0x3B,
- 0x9B, 0xA7, 0x52, 0xBE, 0xC5, 0xD4, 0x50, 0x59,
-
- 0x15, 0x14, 0xB4, 0x0E, 0x40, 0xE6, 0x53, 0xD1,
- 0x83, 0x9C, 0x5B, 0xA0, 0x92, 0x29, 0x6B, 0x5E,
- 0x96, 0x5B, 0x1E, 0x2F, 0xD3, 0xAC, 0xC1, 0x92,
- 0xB1, 0x41, 0x3F, 0x19, 0x2F, 0xC4, 0x3B, 0xC6,
- 0x95, 0x46, 0x45, 0x54, 0xE9, 0x75, 0x03, 0x08,
- 0x44, 0xAF, 0xE5, 0x8A, 0x81, 0x12, 0x09,
- },
+ .result = "\xAE\x39\x50\x8E\xAC\x9A\xEC\xE7"
+ "\xBF\x97\xBB\x20\xB9\xDE\xE4\x1F"
+ "\x87\xD9\x47\xF8\x28\x91\x35\x98"
+ "\xDB\x72\xCC\x23\x29\x48\x56\x5E"
+ "\x83\x7E\x0B\xF3\x7D\x5D\x38\x7B"
+ "\x2D\x71\x02\xB4\x3B\xB5\xD8\x23"
+ "\xB0\x4A\xDF\x3C\xEC\xB6\xD9\x3B"
+ "\x9B\xA7\x52\xBE\xC5\xD4\x50\x59"
+ "\x15\x14\xB4\x0E\x40\xE6\x53\xD1"
+ "\x83\x9C\x5B\xA0\x92\x29\x6B\x5E"
+ "\x96\x5B\x1E\x2F\xD3\xAC\xC1\x92"
+ "\xB1\x41\x3F\x19\x2F\xC4\x3B\xC6"
+ "\x95\x46\x45\x54\xE9\x75\x03\x08"
+ "\x44\xAF\xE5\x8A\x81\x12\x09",
.rlen = 111,
-
}, { /* Set 5, vector 27 */
- .key = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
.klen = 32,
- .iv = { 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00 },
- .input = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- 0x00,
- },
+ .iv = "\x00\x00\x00\x10\x00\x00\x00\x00",
+ .input = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00",
.ilen = 129,
- .result = {
- 0xD2, 0xDB, 0x1A, 0x5C, 0xF1, 0xC1, 0xAC, 0xDB,
- 0xE8, 0x1A, 0x7A, 0x43, 0x40, 0xEF, 0x53, 0x43,
- 0x5E, 0x7F, 0x4B, 0x1A, 0x50, 0x52, 0x3F, 0x8D,
- 0x28, 0x3D, 0xCF, 0x85, 0x1D, 0x69, 0x6E, 0x60,
- 0xF2, 0xDE, 0x74, 0x56, 0x18, 0x1B, 0x84, 0x10,
- 0xD4, 0x62, 0xBA, 0x60, 0x50, 0xF0, 0x61, 0xF2,
- 0x1C, 0x78, 0x7F, 0xC1, 0x24, 0x34, 0xAF, 0x58,
- 0xBF, 0x2C, 0x59, 0xCA, 0x90, 0x77, 0xF3, 0xB0,
-
- 0x5B, 0x4A, 0xDF, 0x89, 0xCE, 0x2C, 0x2F, 0xFC,
- 0x67, 0xF0, 0xE3, 0x45, 0xE8, 0xB3, 0xB3, 0x75,
- 0xA0, 0x95, 0x71, 0xA1, 0x29, 0x39, 0x94, 0xCA,
- 0x45, 0x2F, 0xBD, 0xCB, 0x10, 0xB6, 0xBE, 0x9F,
- 0x8E, 0xF9, 0xB2, 0x01, 0x0A, 0x5A, 0x0A, 0xB7,
- 0x6B, 0x9D, 0x70, 0x8E, 0x4B, 0xD6, 0x2F, 0xCD,
- 0x2E, 0x40, 0x48, 0x75, 0xE9, 0xE2, 0x21, 0x45,
- 0x0B, 0xC9, 0xB6, 0xB5, 0x66, 0xBC, 0x9A, 0x59,
-
- 0x5A,
- },
+ .result = "\xD2\xDB\x1A\x5C\xF1\xC1\xAC\xDB"
+ "\xE8\x1A\x7A\x43\x40\xEF\x53\x43"
+ "\x5E\x7F\x4B\x1A\x50\x52\x3F\x8D"
+ "\x28\x3D\xCF\x85\x1D\x69\x6E\x60"
+ "\xF2\xDE\x74\x56\x18\x1B\x84\x10"
+ "\xD4\x62\xBA\x60\x50\xF0\x61\xF2"
+ "\x1C\x78\x7F\xC1\x24\x34\xAF\x58"
+ "\xBF\x2C\x59\xCA\x90\x77\xF3\xB0"
+ "\x5B\x4A\xDF\x89\xCE\x2C\x2F\xFC"
+ "\x67\xF0\xE3\x45\xE8\xB3\xB3\x75"
+ "\xA0\x95\x71\xA1\x29\x39\x94\xCA"
+ "\x45\x2F\xBD\xCB\x10\xB6\xBE\x9F"
+ "\x8E\xF9\xB2\x01\x0A\x5A\x0A\xB7"
+ "\x6B\x9D\x70\x8E\x4B\xD6\x2F\xCD"
+ "\x2E\x40\x48\x75\xE9\xE2\x21\x45"
+ "\x0B\xC9\xB6\xB5\x66\xBC\x9A\x59"
+ "\x5A",
.rlen = 129,
}, { /* large test vector generated using Crypto++ */
- .key = {
- 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- },
+ .key = "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f",
.klen = 32,
- .iv = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- },
- .input = {
- 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
- 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
- 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
- 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
- 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
- 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
- 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
- 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
- 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
- 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
- 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
- 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
- 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
- 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
- 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
- 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
- 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
- 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
- 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
- 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
- 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
- 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
- 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
- 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
- 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
- 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
- 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
- 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
- 0x00, 0x03, 0x06, 0x09, 0x0c, 0x0f, 0x12, 0x15,
- 0x18, 0x1b, 0x1e, 0x21, 0x24, 0x27, 0x2a, 0x2d,
- 0x30, 0x33, 0x36, 0x39, 0x3c, 0x3f, 0x42, 0x45,
- 0x48, 0x4b, 0x4e, 0x51, 0x54, 0x57, 0x5a, 0x5d,
- 0x60, 0x63, 0x66, 0x69, 0x6c, 0x6f, 0x72, 0x75,
- 0x78, 0x7b, 0x7e, 0x81, 0x84, 0x87, 0x8a, 0x8d,
- 0x90, 0x93, 0x96, 0x99, 0x9c, 0x9f, 0xa2, 0xa5,
- 0xa8, 0xab, 0xae, 0xb1, 0xb4, 0xb7, 0xba, 0xbd,
- 0xc0, 0xc3, 0xc6, 0xc9, 0xcc, 0xcf, 0xd2, 0xd5,
- 0xd8, 0xdb, 0xde, 0xe1, 0xe4, 0xe7, 0xea, 0xed,
- 0xf0, 0xf3, 0xf6, 0xf9, 0xfc, 0xff, 0x02, 0x05,
- 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x17, 0x1a, 0x1d,
- 0x20, 0x23, 0x26, 0x29, 0x2c, 0x2f, 0x32, 0x35,
- 0x38, 0x3b, 0x3e, 0x41, 0x44, 0x47, 0x4a, 0x4d,
- 0x50, 0x53, 0x56, 0x59, 0x5c, 0x5f, 0x62, 0x65,
- 0x68, 0x6b, 0x6e, 0x71, 0x74, 0x77, 0x7a, 0x7d,
- 0x80, 0x83, 0x86, 0x89, 0x8c, 0x8f, 0x92, 0x95,
- 0x98, 0x9b, 0x9e, 0xa1, 0xa4, 0xa7, 0xaa, 0xad,
- 0xb0, 0xb3, 0xb6, 0xb9, 0xbc, 0xbf, 0xc2, 0xc5,
- 0xc8, 0xcb, 0xce, 0xd1, 0xd4, 0xd7, 0xda, 0xdd,
- 0xe0, 0xe3, 0xe6, 0xe9, 0xec, 0xef, 0xf2, 0xf5,
- 0xf8, 0xfb, 0xfe, 0x01, 0x04, 0x07, 0x0a, 0x0d,
- 0x10, 0x13, 0x16, 0x19, 0x1c, 0x1f, 0x22, 0x25,
- 0x28, 0x2b, 0x2e, 0x31, 0x34, 0x37, 0x3a, 0x3d,
- 0x40, 0x43, 0x46, 0x49, 0x4c, 0x4f, 0x52, 0x55,
- 0x58, 0x5b, 0x5e, 0x61, 0x64, 0x67, 0x6a, 0x6d,
- 0x70, 0x73, 0x76, 0x79, 0x7c, 0x7f, 0x82, 0x85,
- 0x88, 0x8b, 0x8e, 0x91, 0x94, 0x97, 0x9a, 0x9d,
- 0xa0, 0xa3, 0xa6, 0xa9, 0xac, 0xaf, 0xb2, 0xb5,
- 0xb8, 0xbb, 0xbe, 0xc1, 0xc4, 0xc7, 0xca, 0xcd,
- 0xd0, 0xd3, 0xd6, 0xd9, 0xdc, 0xdf, 0xe2, 0xe5,
- 0xe8, 0xeb, 0xee, 0xf1, 0xf4, 0xf7, 0xfa, 0xfd,
- 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 0x1e, 0x23,
- 0x28, 0x2d, 0x32, 0x37, 0x3c, 0x41, 0x46, 0x4b,
- 0x50, 0x55, 0x5a, 0x5f, 0x64, 0x69, 0x6e, 0x73,
- 0x78, 0x7d, 0x82, 0x87, 0x8c, 0x91, 0x96, 0x9b,
- 0xa0, 0xa5, 0xaa, 0xaf, 0xb4, 0xb9, 0xbe, 0xc3,
- 0xc8, 0xcd, 0xd2, 0xd7, 0xdc, 0xe1, 0xe6, 0xeb,
- 0xf0, 0xf5, 0xfa, 0xff, 0x04, 0x09, 0x0e, 0x13,
- 0x18, 0x1d, 0x22, 0x27, 0x2c, 0x31, 0x36, 0x3b,
- 0x40, 0x45, 0x4a, 0x4f, 0x54, 0x59, 0x5e, 0x63,
- 0x68, 0x6d, 0x72, 0x77, 0x7c, 0x81, 0x86, 0x8b,
- 0x90, 0x95, 0x9a, 0x9f, 0xa4, 0xa9, 0xae, 0xb3,
- 0xb8, 0xbd, 0xc2, 0xc7, 0xcc, 0xd1, 0xd6, 0xdb,
- 0xe0, 0xe5, 0xea, 0xef, 0xf4, 0xf9, 0xfe, 0x03,
- 0x08, 0x0d, 0x12, 0x17, 0x1c, 0x21, 0x26, 0x2b,
- 0x30, 0x35, 0x3a, 0x3f, 0x44, 0x49, 0x4e, 0x53,
- 0x58, 0x5d, 0x62, 0x67, 0x6c, 0x71, 0x76, 0x7b,
- 0x80, 0x85, 0x8a, 0x8f, 0x94, 0x99, 0x9e, 0xa3,
- 0xa8, 0xad, 0xb2, 0xb7, 0xbc, 0xc1, 0xc6, 0xcb,
- 0xd0, 0xd5, 0xda, 0xdf, 0xe4, 0xe9, 0xee, 0xf3,
- 0xf8, 0xfd, 0x02, 0x07, 0x0c, 0x11, 0x16, 0x1b,
- 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3e, 0x43,
- 0x48, 0x4d, 0x52, 0x57, 0x5c, 0x61, 0x66, 0x6b,
- 0x70, 0x75, 0x7a, 0x7f, 0x84, 0x89, 0x8e, 0x93,
- 0x98, 0x9d, 0xa2, 0xa7, 0xac, 0xb1, 0xb6, 0xbb,
- 0xc0, 0xc5, 0xca, 0xcf, 0xd4, 0xd9, 0xde, 0xe3,
- 0xe8, 0xed, 0xf2, 0xf7, 0xfc, 0x01, 0x06, 0x0b,
- 0x10, 0x15, 0x1a, 0x1f, 0x24, 0x29, 0x2e, 0x33,
- 0x38, 0x3d, 0x42, 0x47, 0x4c, 0x51, 0x56, 0x5b,
- 0x60, 0x65, 0x6a, 0x6f, 0x74, 0x79, 0x7e, 0x83,
- 0x88, 0x8d, 0x92, 0x97, 0x9c, 0xa1, 0xa6, 0xab,
- 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9, 0xce, 0xd3,
- 0xd8, 0xdd, 0xe2, 0xe7, 0xec, 0xf1, 0xf6, 0xfb,
- 0x00, 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31,
- 0x38, 0x3f, 0x46, 0x4d, 0x54, 0x5b, 0x62, 0x69,
- 0x70, 0x77, 0x7e, 0x85, 0x8c, 0x93, 0x9a, 0xa1,
- 0xa8, 0xaf, 0xb6, 0xbd, 0xc4, 0xcb, 0xd2, 0xd9,
- 0xe0, 0xe7, 0xee, 0xf5, 0xfc, 0x03, 0x0a, 0x11,
- 0x18, 0x1f, 0x26, 0x2d, 0x34, 0x3b, 0x42, 0x49,
- 0x50, 0x57, 0x5e, 0x65, 0x6c, 0x73, 0x7a, 0x81,
- 0x88, 0x8f, 0x96, 0x9d, 0xa4, 0xab, 0xb2, 0xb9,
- 0xc0, 0xc7, 0xce, 0xd5, 0xdc, 0xe3, 0xea, 0xf1,
- 0xf8, 0xff, 0x06, 0x0d, 0x14, 0x1b, 0x22, 0x29,
- 0x30, 0x37, 0x3e, 0x45, 0x4c, 0x53, 0x5a, 0x61,
- 0x68, 0x6f, 0x76, 0x7d, 0x84, 0x8b, 0x92, 0x99,
- 0xa0, 0xa7, 0xae, 0xb5, 0xbc, 0xc3, 0xca, 0xd1,
- 0xd8, 0xdf, 0xe6, 0xed, 0xf4, 0xfb, 0x02, 0x09,
- 0x10, 0x17, 0x1e, 0x25, 0x2c, 0x33, 0x3a, 0x41,
- 0x48, 0x4f, 0x56, 0x5d, 0x64, 0x6b, 0x72, 0x79,
- 0x80, 0x87, 0x8e, 0x95, 0x9c, 0xa3, 0xaa, 0xb1,
- 0xb8, 0xbf, 0xc6, 0xcd, 0xd4, 0xdb, 0xe2, 0xe9,
- 0xf0, 0xf7, 0xfe, 0x05, 0x0c, 0x13, 0x1a, 0x21,
- 0x28, 0x2f, 0x36, 0x3d, 0x44, 0x4b, 0x52, 0x59,
- 0x60, 0x67, 0x6e, 0x75, 0x7c, 0x83, 0x8a, 0x91,
- 0x98, 0x9f, 0xa6, 0xad, 0xb4, 0xbb, 0xc2, 0xc9,
- 0xd0, 0xd7, 0xde, 0xe5, 0xec, 0xf3, 0xfa, 0x01,
- 0x08, 0x0f, 0x16, 0x1d, 0x24, 0x2b, 0x32, 0x39,
- 0x40, 0x47, 0x4e, 0x55, 0x5c, 0x63, 0x6a, 0x71,
- 0x78, 0x7f, 0x86, 0x8d, 0x94, 0x9b, 0xa2, 0xa9,
- 0xb0, 0xb7, 0xbe, 0xc5, 0xcc, 0xd3, 0xda, 0xe1,
- 0xe8, 0xef, 0xf6, 0xfd, 0x04, 0x0b, 0x12, 0x19,
- 0x20, 0x27, 0x2e, 0x35, 0x3c, 0x43, 0x4a, 0x51,
- 0x58, 0x5f, 0x66, 0x6d, 0x74, 0x7b, 0x82, 0x89,
- 0x90, 0x97, 0x9e, 0xa5, 0xac, 0xb3, 0xba, 0xc1,
- 0xc8, 0xcf, 0xd6, 0xdd, 0xe4, 0xeb, 0xf2, 0xf9,
- 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
- 0x48, 0x51, 0x5a, 0x63, 0x6c, 0x75, 0x7e, 0x87,
- 0x90, 0x99, 0xa2, 0xab, 0xb4, 0xbd, 0xc6, 0xcf,
- 0xd8, 0xe1, 0xea, 0xf3, 0xfc, 0x05, 0x0e, 0x17,
- 0x20, 0x29, 0x32, 0x3b, 0x44, 0x4d, 0x56, 0x5f,
- 0x68, 0x71, 0x7a, 0x83, 0x8c, 0x95, 0x9e, 0xa7,
- 0xb0, 0xb9, 0xc2, 0xcb, 0xd4, 0xdd, 0xe6, 0xef,
- 0xf8, 0x01, 0x0a, 0x13, 0x1c, 0x25, 0x2e, 0x37,
- 0x40, 0x49, 0x52, 0x5b, 0x64, 0x6d, 0x76, 0x7f,
- 0x88, 0x91, 0x9a, 0xa3, 0xac, 0xb5, 0xbe, 0xc7,
- 0xd0, 0xd9, 0xe2, 0xeb, 0xf4, 0xfd, 0x06, 0x0f,
- 0x18, 0x21, 0x2a, 0x33, 0x3c, 0x45, 0x4e, 0x57,
- 0x60, 0x69, 0x72, 0x7b, 0x84, 0x8d, 0x96, 0x9f,
- 0xa8, 0xb1, 0xba, 0xc3, 0xcc, 0xd5, 0xde, 0xe7,
- 0xf0, 0xf9, 0x02, 0x0b, 0x14, 0x1d, 0x26, 0x2f,
- 0x38, 0x41, 0x4a, 0x53, 0x5c, 0x65, 0x6e, 0x77,
- 0x80, 0x89, 0x92, 0x9b, 0xa4, 0xad, 0xb6, 0xbf,
- 0xc8, 0xd1, 0xda, 0xe3, 0xec, 0xf5, 0xfe, 0x07,
- 0x10, 0x19, 0x22, 0x2b, 0x34, 0x3d, 0x46, 0x4f,
- 0x58, 0x61, 0x6a, 0x73, 0x7c, 0x85, 0x8e, 0x97,
- 0xa0, 0xa9, 0xb2, 0xbb, 0xc4, 0xcd, 0xd6, 0xdf,
- 0xe8, 0xf1, 0xfa, 0x03, 0x0c, 0x15, 0x1e, 0x27,
- 0x30, 0x39, 0x42, 0x4b, 0x54, 0x5d, 0x66, 0x6f,
- 0x78, 0x81, 0x8a, 0x93, 0x9c, 0xa5, 0xae, 0xb7,
- 0xc0, 0xc9, 0xd2, 0xdb, 0xe4, 0xed, 0xf6, 0xff,
- 0x08, 0x11, 0x1a, 0x23, 0x2c, 0x35, 0x3e, 0x47,
- 0x50, 0x59, 0x62, 0x6b, 0x74, 0x7d, 0x86, 0x8f,
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- 0x88, 0x9f, 0xb6, 0xcd, 0xe4, 0xfb, 0x12, 0x29,
- 0x40, 0x57, 0x6e, 0x85, 0x9c, 0xb3, 0xca, 0xe1,
- 0xf8, 0x0f, 0x26, 0x3d, 0x54, 0x6b, 0x82, 0x99,
- 0xb0, 0xc7, 0xde, 0xf5, 0x0c, 0x23, 0x3a, 0x51,
- 0x68, 0x7f, 0x96, 0xad, 0xc4, 0xdb, 0xf2, 0x09,
- 0x20, 0x37, 0x4e, 0x65, 0x7c, 0x93, 0xaa, 0xc1,
- 0xd8, 0xef, 0x06, 0x1d, 0x34, 0x4b, 0x62, 0x79,
- 0x90, 0xa7, 0xbe, 0xd5, 0xec, 0x03, 0x1a, 0x31,
- 0x48, 0x5f, 0x76, 0x8d, 0xa4, 0xbb, 0xd2, 0xe9,
- 0x00, 0x19, 0x32, 0x4b, 0x64, 0x7d, 0x96, 0xaf,
- 0xc8, 0xe1, 0xfa, 0x13, 0x2c, 0x45, 0x5e, 0x77,
- 0x90, 0xa9, 0xc2, 0xdb, 0xf4, 0x0d, 0x26, 0x3f,
- 0x58, 0x71, 0x8a, 0xa3, 0xbc, 0xd5, 0xee, 0x07,
- 0x20, 0x39, 0x52, 0x6b, 0x84, 0x9d, 0xb6, 0xcf,
- 0xe8, 0x01, 0x1a, 0x33, 0x4c, 0x65, 0x7e, 0x97,
- 0xb0, 0xc9, 0xe2, 0xfb, 0x14, 0x2d, 0x46, 0x5f,
- 0x78, 0x91, 0xaa, 0xc3, 0xdc, 0xf5, 0x0e, 0x27,
- 0x40, 0x59, 0x72, 0x8b, 0xa4, 0xbd, 0xd6, 0xef,
- 0x08, 0x21, 0x3a, 0x53, 0x6c, 0x85, 0x9e, 0xb7,
- 0xd0, 0xe9, 0x02, 0x1b, 0x34, 0x4d, 0x66, 0x7f,
- 0x98, 0xb1, 0xca, 0xe3, 0xfc, 0x15, 0x2e, 0x47,
- 0x60, 0x79, 0x92, 0xab, 0xc4, 0xdd, 0xf6, 0x0f,
- 0x28, 0x41, 0x5a, 0x73, 0x8c, 0xa5, 0xbe, 0xd7,
- 0xf0, 0x09, 0x22, 0x3b, 0x54, 0x6d, 0x86, 0x9f,
- 0xb8, 0xd1, 0xea, 0x03, 0x1c, 0x35, 0x4e, 0x67,
- 0x80, 0x99, 0xb2, 0xcb, 0xe4, 0xfd, 0x16, 0x2f,
- 0x48, 0x61, 0x7a, 0x93, 0xac, 0xc5, 0xde, 0xf7,
- 0x10, 0x29, 0x42, 0x5b, 0x74, 0x8d, 0xa6, 0xbf,
- 0xd8, 0xf1, 0x0a, 0x23, 0x3c, 0x55, 0x6e, 0x87,
- 0xa0, 0xb9, 0xd2, 0xeb, 0x04, 0x1d, 0x36, 0x4f,
- 0x68, 0x81, 0x9a, 0xb3, 0xcc, 0xe5, 0xfe, 0x17,
- 0x30, 0x49, 0x62, 0x7b, 0x94, 0xad, 0xc6, 0xdf,
- 0xf8, 0x11, 0x2a, 0x43, 0x5c, 0x75, 0x8e, 0xa7,
- 0xc0, 0xd9, 0xf2, 0x0b, 0x24, 0x3d, 0x56, 0x6f,
- 0x88, 0xa1, 0xba, 0xd3, 0xec, 0x05, 0x1e, 0x37,
- 0x50, 0x69, 0x82, 0x9b, 0xb4, 0xcd, 0xe6, 0xff,
- 0x18, 0x31, 0x4a, 0x63, 0x7c, 0x95, 0xae, 0xc7,
- 0xe0, 0xf9, 0x12, 0x2b, 0x44, 0x5d, 0x76, 0x8f,
- 0xa8, 0xc1, 0xda, 0xf3, 0x0c, 0x25, 0x3e, 0x57,
- 0x70, 0x89, 0xa2, 0xbb, 0xd4, 0xed, 0x06, 0x1f,
- 0x38, 0x51, 0x6a, 0x83, 0x9c, 0xb5, 0xce, 0xe7,
- 0x00, 0x1b, 0x36, 0x51, 0x6c, 0x87, 0xa2, 0xbd,
- 0xd8, 0xf3, 0x0e, 0x29, 0x44, 0x5f, 0x7a, 0x95,
- 0xb0, 0xcb, 0xe6, 0x01, 0x1c, 0x37, 0x52, 0x6d,
- 0x88, 0xa3, 0xbe, 0xd9, 0xf4, 0x0f, 0x2a, 0x45,
- 0x60, 0x7b, 0x96, 0xb1, 0xcc, 0xe7, 0x02, 0x1d,
- 0x38, 0x53, 0x6e, 0x89, 0xa4, 0xbf, 0xda, 0xf5,
- 0x10, 0x2b, 0x46, 0x61, 0x7c, 0x97, 0xb2, 0xcd,
- 0xe8, 0x03, 0x1e, 0x39, 0x54, 0x6f, 0x8a, 0xa5,
- 0xc0, 0xdb, 0xf6, 0x11, 0x2c, 0x47, 0x62, 0x7d,
- 0x98, 0xb3, 0xce, 0xe9, 0x04, 0x1f, 0x3a, 0x55,
- 0x70, 0x8b, 0xa6, 0xc1, 0xdc, 0xf7, 0x12, 0x2d,
- 0x48, 0x63, 0x7e, 0x99, 0xb4, 0xcf, 0xea, 0x05,
- 0x20, 0x3b, 0x56, 0x71, 0x8c, 0xa7, 0xc2, 0xdd,
- 0xf8, 0x13, 0x2e, 0x49, 0x64, 0x7f, 0x9a, 0xb5,
- 0xd0, 0xeb, 0x06, 0x21, 0x3c, 0x57, 0x72, 0x8d,
- 0xa8, 0xc3, 0xde, 0xf9, 0x14, 0x2f, 0x4a, 0x65,
- 0x80, 0x9b, 0xb6, 0xd1, 0xec, 0x07, 0x22, 0x3d,
- 0x58, 0x73, 0x8e, 0xa9, 0xc4, 0xdf, 0xfa, 0x15,
- 0x30, 0x4b, 0x66, 0x81, 0x9c, 0xb7, 0xd2, 0xed,
- 0x08, 0x23, 0x3e, 0x59, 0x74, 0x8f, 0xaa, 0xc5,
- 0xe0, 0xfb, 0x16, 0x31, 0x4c, 0x67, 0x82, 0x9d,
- 0xb8, 0xd3, 0xee, 0x09, 0x24, 0x3f, 0x5a, 0x75,
- 0x90, 0xab, 0xc6, 0xe1, 0xfc, 0x17, 0x32, 0x4d,
- 0x68, 0x83, 0x9e, 0xb9, 0xd4, 0xef, 0x0a, 0x25,
- 0x40, 0x5b, 0x76, 0x91, 0xac, 0xc7, 0xe2, 0xfd,
- 0x18, 0x33, 0x4e, 0x69, 0x84, 0x9f, 0xba, 0xd5,
- 0xf0, 0x0b, 0x26, 0x41, 0x5c, 0x77, 0x92, 0xad,
- 0xc8, 0xe3, 0xfe, 0x19, 0x34, 0x4f, 0x6a, 0x85,
- 0xa0, 0xbb, 0xd6, 0xf1, 0x0c, 0x27, 0x42, 0x5d,
- 0x78, 0x93, 0xae, 0xc9, 0xe4, 0xff, 0x1a, 0x35,
- 0x50, 0x6b, 0x86, 0xa1, 0xbc, 0xd7, 0xf2, 0x0d,
- 0x28, 0x43, 0x5e, 0x79, 0x94, 0xaf, 0xca, 0xe5,
- 0x00, 0x1d, 0x3a, 0x57, 0x74, 0x91, 0xae, 0xcb,
- 0xe8, 0x05, 0x22, 0x3f, 0x5c, 0x79, 0x96, 0xb3,
- 0xd0, 0xed, 0x0a, 0x27, 0x44, 0x61, 0x7e, 0x9b,
- 0xb8, 0xd5, 0xf2, 0x0f, 0x2c, 0x49, 0x66, 0x83,
- 0xa0, 0xbd, 0xda, 0xf7, 0x14, 0x31, 0x4e, 0x6b,
- 0x88, 0xa5, 0xc2, 0xdf, 0xfc, 0x19, 0x36, 0x53,
- 0x70, 0x8d, 0xaa, 0xc7, 0xe4, 0x01, 0x1e, 0x3b,
- 0x58, 0x75, 0x92, 0xaf, 0xcc, 0xe9, 0x06, 0x23,
- 0x40, 0x5d, 0x7a, 0x97, 0xb4, 0xd1, 0xee, 0x0b,
- 0x28, 0x45, 0x62, 0x7f, 0x9c, 0xb9, 0xd6, 0xf3,
- 0x10, 0x2d, 0x4a, 0x67, 0x84, 0xa1, 0xbe, 0xdb,
- 0xf8, 0x15, 0x32, 0x4f, 0x6c, 0x89, 0xa6, 0xc3,
- 0xe0, 0xfd, 0x1a, 0x37, 0x54, 0x71, 0x8e, 0xab,
- 0xc8, 0xe5, 0x02, 0x1f, 0x3c, 0x59, 0x76, 0x93,
- 0xb0, 0xcd, 0xea, 0x07, 0x24, 0x41, 0x5e, 0x7b,
- 0x98, 0xb5, 0xd2, 0xef, 0x0c, 0x29, 0x46, 0x63,
- 0x80, 0x9d, 0xba, 0xd7, 0xf4, 0x11, 0x2e, 0x4b,
- 0x68, 0x85, 0xa2, 0xbf, 0xdc, 0xf9, 0x16, 0x33,
- 0x50, 0x6d, 0x8a, 0xa7, 0xc4, 0xe1, 0xfe, 0x1b,
- 0x38, 0x55, 0x72, 0x8f, 0xac, 0xc9, 0xe6, 0x03,
- 0x20, 0x3d, 0x5a, 0x77, 0x94, 0xb1, 0xce, 0xeb,
- 0x08, 0x25, 0x42, 0x5f, 0x7c, 0x99, 0xb6, 0xd3,
- 0xf0, 0x0d, 0x2a, 0x47, 0x64, 0x81, 0x9e, 0xbb,
- 0xd8, 0xf5, 0x12, 0x2f, 0x4c, 0x69, 0x86, 0xa3,
- 0xc0, 0xdd, 0xfa, 0x17, 0x34, 0x51, 0x6e, 0x8b,
- 0xa8, 0xc5, 0xe2, 0xff, 0x1c, 0x39, 0x56, 0x73,
- 0x90, 0xad, 0xca, 0xe7, 0x04, 0x21, 0x3e, 0x5b,
- 0x78, 0x95, 0xb2, 0xcf, 0xec, 0x09, 0x26, 0x43,
- 0x60, 0x7d, 0x9a, 0xb7, 0xd4, 0xf1, 0x0e, 0x2b,
- 0x48, 0x65, 0x82, 0x9f, 0xbc, 0xd9, 0xf6, 0x13,
- 0x30, 0x4d, 0x6a, 0x87, 0xa4, 0xc1, 0xde, 0xfb,
- 0x18, 0x35, 0x52, 0x6f, 0x8c, 0xa9, 0xc6, 0xe3,
- 0x00, 0x1f, 0x3e, 0x5d, 0x7c, 0x9b, 0xba, 0xd9,
- 0xf8, 0x17, 0x36, 0x55, 0x74, 0x93, 0xb2, 0xd1,
- 0xf0, 0x0f, 0x2e, 0x4d, 0x6c, 0x8b, 0xaa, 0xc9,
- 0xe8, 0x07, 0x26, 0x45, 0x64, 0x83, 0xa2, 0xc1,
- 0xe0, 0xff, 0x1e, 0x3d, 0x5c, 0x7b, 0x9a, 0xb9,
- 0xd8, 0xf7, 0x16, 0x35, 0x54, 0x73, 0x92, 0xb1,
- 0xd0, 0xef, 0x0e, 0x2d, 0x4c, 0x6b, 0x8a, 0xa9,
- 0xc8, 0xe7, 0x06, 0x25, 0x44, 0x63, 0x82, 0xa1,
- 0xc0, 0xdf, 0xfe, 0x1d, 0x3c, 0x5b, 0x7a, 0x99,
- 0xb8, 0xd7, 0xf6, 0x15, 0x34, 0x53, 0x72, 0x91,
- 0xb0, 0xcf, 0xee, 0x0d, 0x2c, 0x4b, 0x6a, 0x89,
- 0xa8, 0xc7, 0xe6, 0x05, 0x24, 0x43, 0x62, 0x81,
- 0xa0, 0xbf, 0xde, 0xfd, 0x1c, 0x3b, 0x5a, 0x79,
- 0x98, 0xb7, 0xd6, 0xf5, 0x14, 0x33, 0x52, 0x71,
- 0x90, 0xaf, 0xce, 0xed, 0x0c, 0x2b, 0x4a, 0x69,
- 0x88, 0xa7, 0xc6, 0xe5, 0x04, 0x23, 0x42, 0x61,
- 0x80, 0x9f, 0xbe, 0xdd, 0xfc, 0x1b, 0x3a, 0x59,
- 0x78, 0x97, 0xb6, 0xd5, 0xf4, 0x13, 0x32, 0x51,
- 0x70, 0x8f, 0xae, 0xcd, 0xec, 0x0b, 0x2a, 0x49,
- 0x68, 0x87, 0xa6, 0xc5, 0xe4, 0x03, 0x22, 0x41,
- 0x60, 0x7f, 0x9e, 0xbd, 0xdc, 0xfb, 0x1a, 0x39,
- 0x58, 0x77, 0x96, 0xb5, 0xd4, 0xf3, 0x12, 0x31,
- 0x50, 0x6f, 0x8e, 0xad, 0xcc, 0xeb, 0x0a, 0x29,
- 0x48, 0x67, 0x86, 0xa5, 0xc4, 0xe3, 0x02, 0x21,
- 0x40, 0x5f, 0x7e, 0x9d, 0xbc, 0xdb, 0xfa, 0x19,
- 0x38, 0x57, 0x76, 0x95, 0xb4, 0xd3, 0xf2, 0x11,
- 0x30, 0x4f, 0x6e, 0x8d, 0xac, 0xcb, 0xea, 0x09,
- 0x28, 0x47, 0x66, 0x85, 0xa4, 0xc3, 0xe2, 0x01,
- 0x20, 0x3f, 0x5e, 0x7d, 0x9c, 0xbb, 0xda, 0xf9,
- 0x18, 0x37, 0x56, 0x75, 0x94, 0xb3, 0xd2, 0xf1,
- 0x10, 0x2f, 0x4e, 0x6d, 0x8c, 0xab, 0xca, 0xe9,
- 0x08, 0x27, 0x46, 0x65, 0x84, 0xa3, 0xc2, 0xe1,
- 0x00, 0x21, 0x42, 0x63,
- },
+ .iv = "\x00\x00\x00\x00\x00\x00\x00\x00"
+ "\x00\x00\x00\x00\x00\x00\x00\x00",
+ .input =
+ "\x00\x01\x02\x03\x04\x05\x06\x07"
+ "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f"
+ "\x10\x11\x12\x13\x14\x15\x16\x17"
+ "\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f"
+ "\x20\x21\x22\x23\x24\x25\x26\x27"
+ "\x28\x29\x2a\x2b\x2c\x2d\x2e\x2f"
+ "\x30\x31\x32\x33\x34\x35\x36\x37"
+ "\x38\x39\x3a\x3b\x3c\x3d\x3e\x3f"
+ "\x40\x41\x42\x43\x44\x45\x46\x47"
+ "\x48\x49\x4a\x4b\x4c\x4d\x4e\x4f"
+ "\x50\x51\x52\x53\x54\x55\x56\x57"
+ "\x58\x59\x5a\x5b\x5c\x5d\x5e\x5f"
+ "\x60\x61\x62\x63\x64\x65\x66\x67"
+ "\x68\x69\x6a\x6b\x6c\x6d\x6e\x6f"
+ "\x70\x71\x72\x73\x74\x75\x76\x77"
+ "\x78\x79\x7a\x7b\x7c\x7d\x7e\x7f"
+ "\x80\x81\x82\x83\x84\x85\x86\x87"
+ "\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f"
+ "\x90\x91\x92\x93\x94\x95\x96\x97"
+ "\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f"
+ "\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7"
+ "\xa8\xa9\xaa\xab\xac\xad\xae\xaf"
+ "\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7"
+ "\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf"
+ "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf"
+ "\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7"
+ "\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf"
+ "\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7"
+ "\xe8\xe9\xea\xeb\xec\xed\xee\xef"
+ "\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7"
+ "\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"
+ "\x00\x03\x06\x09\x0c\x0f\x12\x15"
+ "\x18\x1b\x1e\x21\x24\x27\x2a\x2d"
+ "\x30\x33\x36\x39\x3c\x3f\x42\x45"
+ "\x48\x4b\x4e\x51\x54\x57\x5a\x5d"
+ "\x60\x63\x66\x69\x6c\x6f\x72\x75"
+ "\x78\x7b\x7e\x81\x84\x87\x8a\x8d"
+ "\x90\x93\x96\x99\x9c\x9f\xa2\xa5"
+ "\xa8\xab\xae\xb1\xb4\xb7\xba\xbd"
+ "\xc0\xc3\xc6\xc9\xcc\xcf\xd2\xd5"
+ "\xd8\xdb\xde\xe1\xe4\xe7\xea\xed"
+ "\xf0\xf3\xf6\xf9\xfc\xff\x02\x05"
+ "\x08\x0b\x0e\x11\x14\x17\x1a\x1d"
+ "\x20\x23\x26\x29\x2c\x2f\x32\x35"
+ "\x38\x3b\x3e\x41\x44\x47\x4a\x4d"
+ "\x50\x53\x56\x59\x5c\x5f\x62\x65"
+ "\x68\x6b\x6e\x71\x74\x77\x7a\x7d"
+ "\x80\x83\x86\x89\x8c\x8f\x92\x95"
+ "\x98\x9b\x9e\xa1\xa4\xa7\xaa\xad"
+ "\xb0\xb3\xb6\xb9\xbc\xbf\xc2\xc5"
+ "\xc8\xcb\xce\xd1\xd4\xd7\xda\xdd"
+ "\xe0\xe3\xe6\xe9\xec\xef\xf2\xf5"
+ "\xf8\xfb\xfe\x01\x04\x07\x0a\x0d"
+ "\x10\x13\x16\x19\x1c\x1f\x22\x25"
+ "\x28\x2b\x2e\x31\x34\x37\x3a\x3d"
+ "\x40\x43\x46\x49\x4c\x4f\x52\x55"
+ "\x58\x5b\x5e\x61\x64\x67\x6a\x6d"
+ "\x70\x73\x76\x79\x7c\x7f\x82\x85"
+ "\x88\x8b\x8e\x91\x94\x97\x9a\x9d"
+ "\xa0\xa3\xa6\xa9\xac\xaf\xb2\xb5"
+ "\xb8\xbb\xbe\xc1\xc4\xc7\xca\xcd"
+ "\xd0\xd3\xd6\xd9\xdc\xdf\xe2\xe5"
+ "\xe8\xeb\xee\xf1\xf4\xf7\xfa\xfd"
+ "\x00\x05\x0a\x0f\x14\x19\x1e\x23"
+ "\x28\x2d\x32\x37\x3c\x41\x46\x4b"
+ "\x50\x55\x5a\x5f\x64\x69\x6e\x73"
+ "\x78\x7d\x82\x87\x8c\x91\x96\x9b"
+ "\xa0\xa5\xaa\xaf\xb4\xb9\xbe\xc3"
+ "\xc8\xcd\xd2\xd7\xdc\xe1\xe6\xeb"
+ "\xf0\xf5\xfa\xff\x04\x09\x0e\x13"
+ "\x18\x1d\x22\x27\x2c\x31\x36\x3b"
+ "\x40\x45\x4a\x4f\x54\x59\x5e\x63"
+ "\x68\x6d\x72\x77\x7c\x81\x86\x8b"
+ "\x90\x95\x9a\x9f\xa4\xa9\xae\xb3"
+ "\xb8\xbd\xc2\xc7\xcc\xd1\xd6\xdb"
+ "\xe0\xe5\xea\xef\xf4\xf9\xfe\x03"
+ "\x08\x0d\x12\x17\x1c\x21\x26\x2b"
+ "\x30\x35\x3a\x3f\x44\x49\x4e\x53"
+ "\x58\x5d\x62\x67\x6c\x71\x76\x7b"
+ "\x80\x85\x8a\x8f\x94\x99\x9e\xa3"
+ "\xa8\xad\xb2\xb7\xbc\xc1\xc6\xcb"
+ "\xd0\xd5\xda\xdf\xe4\xe9\xee\xf3"
+ "\xf8\xfd\x02\x07\x0c\x11\x16\x1b"
+ "\x20\x25\x2a\x2f\x34\x39\x3e\x43"
+ "\x48\x4d\x52\x57\x5c\x61\x66\x6b"
+ "\x70\x75\x7a\x7f\x84\x89\x8e\x93"
+ "\x98\x9d\xa2\xa7\xac\xb1\xb6\xbb"
+ "\xc0\xc5\xca\xcf\xd4\xd9\xde\xe3"
+ "\xe8\xed\xf2\xf7\xfc\x01\x06\x0b"
+ "\x10\x15\x1a\x1f\x24\x29\x2e\x33"
+ "\x38\x3d\x42\x47\x4c\x51\x56\x5b"
+ "\x60\x65\x6a\x6f\x74\x79\x7e\x83"
+ "\x88\x8d\x92\x97\x9c\xa1\xa6\xab"
+ "\xb0\xb5\xba\xbf\xc4\xc9\xce\xd3"
+ "\xd8\xdd\xe2\xe7\xec\xf1\xf6\xfb"
+ "\x00\x07\x0e\x15\x1c\x23\x2a\x31"
+ "\x38\x3f\x46\x4d\x54\x5b\x62\x69"
+ "\x70\x77\x7e\x85\x8c\x93\x9a\xa1"
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+ "\x88\x9f\xb6\xcd\xe4\xfb\x12\x29"
+ "\x40\x57\x6e\x85\x9c\xb3\xca\xe1"
+ "\xf8\x0f\x26\x3d\x54\x6b\x82\x99"
+ "\xb0\xc7\xde\xf5\x0c\x23\x3a\x51"
+ "\x68\x7f\x96\xad\xc4\xdb\xf2\x09"
+ "\x20\x37\x4e\x65\x7c\x93\xaa\xc1"
+ "\xd8\xef\x06\x1d\x34\x4b\x62\x79"
+ "\x90\xa7\xbe\xd5\xec\x03\x1a\x31"
+ "\x48\x5f\x76\x8d\xa4\xbb\xd2\xe9"
+ "\x00\x19\x32\x4b\x64\x7d\x96\xaf"
+ "\xc8\xe1\xfa\x13\x2c\x45\x5e\x77"
+ "\x90\xa9\xc2\xdb\xf4\x0d\x26\x3f"
+ "\x58\x71\x8a\xa3\xbc\xd5\xee\x07"
+ "\x20\x39\x52\x6b\x84\x9d\xb6\xcf"
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+ "\xb0\xc9\xe2\xfb\x14\x2d\x46\x5f"
+ "\x78\x91\xaa\xc3\xdc\xf5\x0e\x27"
+ "\x40\x59\x72\x8b\xa4\xbd\xd6\xef"
+ "\x08\x21\x3a\x53\x6c\x85\x9e\xb7"
+ "\xd0\xe9\x02\x1b\x34\x4d\x66\x7f"
+ "\x98\xb1\xca\xe3\xfc\x15\x2e\x47"
+ "\x60\x79\x92\xab\xc4\xdd\xf6\x0f"
+ "\x28\x41\x5a\x73\x8c\xa5\xbe\xd7"
+ "\xf0\x09\x22\x3b\x54\x6d\x86\x9f"
+ "\xb8\xd1\xea\x03\x1c\x35\x4e\x67"
+ "\x80\x99\xb2\xcb\xe4\xfd\x16\x2f"
+ "\x48\x61\x7a\x93\xac\xc5\xde\xf7"
+ "\x10\x29\x42\x5b\x74\x8d\xa6\xbf"
+ "\xd8\xf1\x0a\x23\x3c\x55\x6e\x87"
+ "\xa0\xb9\xd2\xeb\x04\x1d\x36\x4f"
+ "\x68\x81\x9a\xb3\xcc\xe5\xfe\x17"
+ "\x30\x49\x62\x7b\x94\xad\xc6\xdf"
+ "\xf8\x11\x2a\x43\x5c\x75\x8e\xa7"
+ "\xc0\xd9\xf2\x0b\x24\x3d\x56\x6f"
+ "\x88\xa1\xba\xd3\xec\x05\x1e\x37"
+ "\x50\x69\x82\x9b\xb4\xcd\xe6\xff"
+ "\x18\x31\x4a\x63\x7c\x95\xae\xc7"
+ "\xe0\xf9\x12\x2b\x44\x5d\x76\x8f"
+ "\xa8\xc1\xda\xf3\x0c\x25\x3e\x57"
+ "\x70\x89\xa2\xbb\xd4\xed\x06\x1f"
+ "\x38\x51\x6a\x83\x9c\xb5\xce\xe7"
+ "\x00\x1b\x36\x51\x6c\x87\xa2\xbd"
+ "\xd8\xf3\x0e\x29\x44\x5f\x7a\x95"
+ "\xb0\xcb\xe6\x01\x1c\x37\x52\x6d"
+ "\x88\xa3\xbe\xd9\xf4\x0f\x2a\x45"
+ "\x60\x7b\x96\xb1\xcc\xe7\x02\x1d"
+ "\x38\x53\x6e\x89\xa4\xbf\xda\xf5"
+ "\x10\x2b\x46\x61\x7c\x97\xb2\xcd"
+ "\xe8\x03\x1e\x39\x54\x6f\x8a\xa5"
+ "\xc0\xdb\xf6\x11\x2c\x47\x62\x7d"
+ "\x98\xb3\xce\xe9\x04\x1f\x3a\x55"
+ "\x70\x8b\xa6\xc1\xdc\xf7\x12\x2d"
+ "\x48\x63\x7e\x99\xb4\xcf\xea\x05"
+ "\x20\x3b\x56\x71\x8c\xa7\xc2\xdd"
+ "\xf8\x13\x2e\x49\x64\x7f\x9a\xb5"
+ "\xd0\xeb\x06\x21\x3c\x57\x72\x8d"
+ "\xa8\xc3\xde\xf9\x14\x2f\x4a\x65"
+ "\x80\x9b\xb6\xd1\xec\x07\x22\x3d"
+ "\x58\x73\x8e\xa9\xc4\xdf\xfa\x15"
+ "\x30\x4b\x66\x81\x9c\xb7\xd2\xed"
+ "\x08\x23\x3e\x59\x74\x8f\xaa\xc5"
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+ "\xb8\xd3\xee\x09\x24\x3f\x5a\x75"
+ "\x90\xab\xc6\xe1\xfc\x17\x32\x4d"
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+ "\x78\x93\xae\xc9\xe4\xff\x1a\x35"
+ "\x50\x6b\x86\xa1\xbc\xd7\xf2\x0d"
+ "\x28\x43\x5e\x79\x94\xaf\xca\xe5"
+ "\x00\x1d\x3a\x57\x74\x91\xae\xcb"
+ "\xe8\x05\x22\x3f\x5c\x79\x96\xb3"
+ "\xd0\xed\x0a\x27\x44\x61\x7e\x9b"
+ "\xb8\xd5\xf2\x0f\x2c\x49\x66\x83"
+ "\xa0\xbd\xda\xf7\x14\x31\x4e\x6b"
+ "\x88\xa5\xc2\xdf\xfc\x19\x36\x53"
+ "\x70\x8d\xaa\xc7\xe4\x01\x1e\x3b"
+ "\x58\x75\x92\xaf\xcc\xe9\x06\x23"
+ "\x40\x5d\x7a\x97\xb4\xd1\xee\x0b"
+ "\x28\x45\x62\x7f\x9c\xb9\xd6\xf3"
+ "\x10\x2d\x4a\x67\x84\xa1\xbe\xdb"
+ "\xf8\x15\x32\x4f\x6c\x89\xa6\xc3"
+ "\xe0\xfd\x1a\x37\x54\x71\x8e\xab"
+ "\xc8\xe5\x02\x1f\x3c\x59\x76\x93"
+ "\xb0\xcd\xea\x07\x24\x41\x5e\x7b"
+ "\x98\xb5\xd2\xef\x0c\x29\x46\x63"
+ "\x80\x9d\xba\xd7\xf4\x11\x2e\x4b"
+ "\x68\x85\xa2\xbf\xdc\xf9\x16\x33"
+ "\x50\x6d\x8a\xa7\xc4\xe1\xfe\x1b"
+ "\x38\x55\x72\x8f\xac\xc9\xe6\x03"
+ "\x20\x3d\x5a\x77\x94\xb1\xce\xeb"
+ "\x08\x25\x42\x5f\x7c\x99\xb6\xd3"
+ "\xf0\x0d\x2a\x47\x64\x81\x9e\xbb"
+ "\xd8\xf5\x12\x2f\x4c\x69\x86\xa3"
+ "\xc0\xdd\xfa\x17\x34\x51\x6e\x8b"
+ "\xa8\xc5\xe2\xff\x1c\x39\x56\x73"
+ "\x90\xad\xca\xe7\x04\x21\x3e\x5b"
+ "\x78\x95\xb2\xcf\xec\x09\x26\x43"
+ "\x60\x7d\x9a\xb7\xd4\xf1\x0e\x2b"
+ "\x48\x65\x82\x9f\xbc\xd9\xf6\x13"
+ "\x30\x4d\x6a\x87\xa4\xc1\xde\xfb"
+ "\x18\x35\x52\x6f\x8c\xa9\xc6\xe3"
+ "\x00\x1f\x3e\x5d\x7c\x9b\xba\xd9"
+ "\xf8\x17\x36\x55\x74\x93\xb2\xd1"
+ "\xf0\x0f\x2e\x4d\x6c\x8b\xaa\xc9"
+ "\xe8\x07\x26\x45\x64\x83\xa2\xc1"
+ "\xe0\xff\x1e\x3d\x5c\x7b\x9a\xb9"
+ "\xd8\xf7\x16\x35\x54\x73\x92\xb1"
+ "\xd0\xef\x0e\x2d\x4c\x6b\x8a\xa9"
+ "\xc8\xe7\x06\x25\x44\x63\x82\xa1"
+ "\xc0\xdf\xfe\x1d\x3c\x5b\x7a\x99"
+ "\xb8\xd7\xf6\x15\x34\x53\x72\x91"
+ "\xb0\xcf\xee\x0d\x2c\x4b\x6a\x89"
+ "\xa8\xc7\xe6\x05\x24\x43\x62\x81"
+ "\xa0\xbf\xde\xfd\x1c\x3b\x5a\x79"
+ "\x98\xb7\xd6\xf5\x14\x33\x52\x71"
+ "\x90\xaf\xce\xed\x0c\x2b\x4a\x69"
+ "\x88\xa7\xc6\xe5\x04\x23\x42\x61"
+ "\x80\x9f\xbe\xdd\xfc\x1b\x3a\x59"
+ "\x78\x97\xb6\xd5\xf4\x13\x32\x51"
+ "\x70\x8f\xae\xcd\xec\x0b\x2a\x49"
+ "\x68\x87\xa6\xc5\xe4\x03\x22\x41"
+ "\x60\x7f\x9e\xbd\xdc\xfb\x1a\x39"
+ "\x58\x77\x96\xb5\xd4\xf3\x12\x31"
+ "\x50\x6f\x8e\xad\xcc\xeb\x0a\x29"
+ "\x48\x67\x86\xa5\xc4\xe3\x02\x21"
+ "\x40\x5f\x7e\x9d\xbc\xdb\xfa\x19"
+ "\x38\x57\x76\x95\xb4\xd3\xf2\x11"
+ "\x30\x4f\x6e\x8d\xac\xcb\xea\x09"
+ "\x28\x47\x66\x85\xa4\xc3\xe2\x01"
+ "\x20\x3f\x5e\x7d\x9c\xbb\xda\xf9"
+ "\x18\x37\x56\x75\x94\xb3\xd2\xf1"
+ "\x10\x2f\x4e\x6d\x8c\xab\xca\xe9"
+ "\x08\x27\x46\x65\x84\xa3\xc2\xe1"
+ "\x00\x21\x42\x63",
.ilen = 4100,
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- 0xae, 0xab, 0x86, 0x09, 0x89, 0xc9, 0xc2, 0x40,
- 0x39, 0x2c, 0x81, 0xb3, 0xb8, 0x17, 0x67, 0xc2,
- 0x0d, 0x32, 0x4a, 0x3a, 0x67, 0x81, 0xd7, 0x1a,
- 0x34, 0x52, 0xc5, 0xdb, 0x0a, 0xf5, 0x63, 0x39,
- 0xea, 0x1f, 0xe1, 0x7c, 0xa1, 0x9e, 0xc1, 0x35,
- 0xe3, 0xb1, 0x18, 0x45, 0x67, 0xf9, 0x22, 0x38,
- 0x95, 0xd9, 0x34, 0x34, 0x86, 0xc6, 0x41, 0x94,
- 0x15, 0xf9, 0x5b, 0x41, 0xa6, 0x87, 0x8b, 0xf8,
- 0xd5, 0xe1, 0x1b, 0xe2, 0x5b, 0xf3, 0x86, 0x10,
- 0xff, 0xe6, 0xae, 0x69, 0x76, 0xbc, 0x0d, 0xb4,
- 0x09, 0x90, 0x0c, 0xa2, 0x65, 0x0c, 0xad, 0x74,
- 0xf5, 0xd7, 0xff, 0xda, 0xc1, 0xce, 0x85, 0xbe,
- 0x00, 0xa7, 0xff, 0x4d, 0x2f, 0x65, 0xd3, 0x8c,
- 0x86, 0x2d, 0x05, 0xe8, 0xed, 0x3e, 0x6b, 0x8b,
- 0x0f, 0x3d, 0x83, 0x8c, 0xf1, 0x1d, 0x5b, 0x96,
- 0x2e, 0xb1, 0x9c, 0xc2, 0x98, 0xe1, 0x70, 0xb9,
- 0xba, 0x5c, 0x8a, 0x43, 0xd6, 0x34, 0xa7, 0x2d,
- 0xc9, 0x92, 0xae, 0xf2, 0xa5, 0x7b, 0x05, 0x49,
- 0xa7, 0x33, 0x34, 0x86, 0xca, 0xe4, 0x96, 0x23,
- 0x76, 0x5b, 0xf2, 0xc6, 0xf1, 0x51, 0x28, 0x42,
- 0x7b, 0xcc, 0x76, 0x8f, 0xfa, 0xa2, 0xad, 0x31,
- 0xd4, 0xd6, 0x7a, 0x6d, 0x25, 0x25, 0x54, 0xe4,
- 0x3f, 0x50, 0x59, 0xe1, 0x5c, 0x05, 0xb7, 0x27,
- 0x48, 0xbf, 0x07, 0xec, 0x1b, 0x13, 0xbe, 0x2b,
- 0xa1, 0x57, 0x2b, 0xd5, 0xab, 0xd7, 0xd0, 0x4c,
- 0x1e, 0xcb, 0x71, 0x9b, 0xc5, 0x90, 0x85, 0xd3,
- 0xde, 0x59, 0xec, 0x71, 0xeb, 0x89, 0xbb, 0xd0,
- 0x09, 0x50, 0xe1, 0x16, 0x3f, 0xfd, 0x1c, 0x34,
- 0xc3, 0x1c, 0xa1, 0x10, 0x77, 0x53, 0x98, 0xef,
- 0xf2, 0xfd, 0xa5, 0x01, 0x59, 0xc2, 0x9b, 0x26,
- 0xc7, 0x42, 0xd9, 0x49, 0xda, 0x58, 0x2b, 0x6e,
- 0x9f, 0x53, 0x19, 0x76, 0x7e, 0xd9, 0xc9, 0x0e,
- 0x68, 0xc8, 0x7f, 0x51, 0x22, 0x42, 0xef, 0x49,
- 0xa4, 0x55, 0xb6, 0x36, 0xac, 0x09, 0xc7, 0x31,
- 0x88, 0x15, 0x4b, 0x2e, 0x8f, 0x3a, 0x08, 0xf7,
- 0xd8, 0xf7, 0xa8, 0xc5, 0xa9, 0x33, 0xa6, 0x45,
- 0xe4, 0xc4, 0x94, 0x76, 0xf3, 0x0d, 0x8f, 0x7e,
- 0xc8, 0xf6, 0xbc, 0x23, 0x0a, 0xb6, 0x4c, 0xd3,
- 0x6a, 0xcd, 0x36, 0xc2, 0x90, 0x5c, 0x5c, 0x3c,
- 0x65, 0x7b, 0xc2, 0xd6, 0xcc, 0xe6, 0x0d, 0x87,
- 0x73, 0x2e, 0x71, 0x79, 0x16, 0x06, 0x63, 0x28,
- 0x09, 0x15, 0xd8, 0x89, 0x38, 0x38, 0x3d, 0xb5,
- 0x42, 0x1c, 0x08, 0x24, 0xf7, 0x2a, 0xd2, 0x9d,
- 0xc8, 0xca, 0xef, 0xf9, 0x27, 0xd8, 0x07, 0x86,
- 0xf7, 0x43, 0x0b, 0x55, 0x15, 0x3f, 0x9f, 0x83,
- 0xef, 0xdc, 0x49, 0x9d, 0x2a, 0xc1, 0x54, 0x62,
- 0xbd, 0x9b, 0x66, 0x55, 0x9f, 0xb7, 0x12, 0xf3,
- 0x1b, 0x4d, 0x9d, 0x2a, 0x5c, 0xed, 0x87, 0x75,
- 0x87, 0x26, 0xec, 0x61, 0x2c, 0xb4, 0x0f, 0x89,
- 0xb0, 0xfb, 0x2e, 0x68, 0x5d, 0x15, 0xc7, 0x8d,
- 0x2e, 0xc0, 0xd9, 0xec, 0xaf, 0x4f, 0xd2, 0x25,
- 0x29, 0xe8, 0xd2, 0x26, 0x2b, 0x67, 0xe9, 0xfc,
- 0x2b, 0xa8, 0x67, 0x96, 0x12, 0x1f, 0x5b, 0x96,
- 0xc6, 0x14, 0x53, 0xaf, 0x44, 0xea, 0xd6, 0xe2,
- 0x94, 0x98, 0xe4, 0x12, 0x93, 0x4c, 0x92, 0xe0,
- 0x18, 0xa5, 0x8d, 0x2d, 0xe4, 0x71, 0x3c, 0x47,
- 0x4c, 0xf7, 0xe6, 0x47, 0x9e, 0xc0, 0x68, 0xdf,
- 0xd4, 0xf5, 0x5a, 0x74, 0xb1, 0x2b, 0x29, 0x03,
- 0x19, 0x07, 0xaf, 0x90, 0x62, 0x5c, 0x68, 0x98,
- 0x48, 0x16, 0x11, 0x02, 0x9d, 0xee, 0xb4, 0x9b,
- 0xe5, 0x42, 0x7f, 0x08, 0xfd, 0x16, 0x32, 0x0b,
- 0xd0, 0xb3, 0xfa, 0x2b, 0xb7, 0x99, 0xf9, 0x29,
- 0xcd, 0x20, 0x45, 0x9f, 0xb3, 0x1a, 0x5d, 0xa2,
- 0xaf, 0x4d, 0xe0, 0xbd, 0x42, 0x0d, 0xbc, 0x74,
- 0x99, 0x9c, 0x8e, 0x53, 0x1a, 0xb4, 0x3e, 0xbd,
- 0xa2, 0x9a, 0x2d, 0xf7, 0xf8, 0x39, 0x0f, 0x67,
- 0x63, 0xfc, 0x6b, 0xc0, 0xaf, 0xb3, 0x4b, 0x4f,
- 0x55, 0xc4, 0xcf, 0xa7, 0xc8, 0x04, 0x11, 0x3e,
- 0x14, 0x32, 0xbb, 0x1b, 0x38, 0x77, 0xd6, 0x7f,
- 0x54, 0x4c, 0xdf, 0x75, 0xf3, 0x07, 0x2d, 0x33,
- 0x9b, 0xa8, 0x20, 0xe1, 0x7b, 0x12, 0xb5, 0xf3,
- 0xef, 0x2f, 0xce, 0x72, 0xe5, 0x24, 0x60, 0xc1,
- 0x30, 0xe2, 0xab, 0xa1, 0x8e, 0x11, 0x09, 0xa8,
- 0x21, 0x33, 0x44, 0xfe, 0x7f, 0x35, 0x32, 0x93,
- 0x39, 0xa7, 0xad, 0x8b, 0x79, 0x06, 0xb2, 0xcb,
- 0x4e, 0xa9, 0x5f, 0xc7, 0xba, 0x74, 0x29, 0xec,
- 0x93, 0xa0, 0x4e, 0x54, 0x93, 0xc0, 0xbc, 0x55,
- 0x64, 0xf0, 0x48, 0xe5, 0x57, 0x99, 0xee, 0x75,
- 0xd6, 0x79, 0x0f, 0x66, 0xb7, 0xc6, 0x57, 0x76,
- 0xf7, 0xb7, 0xf3, 0x9c, 0xc5, 0x60, 0xe8, 0x7f,
- 0x83, 0x76, 0xd6, 0x0e, 0xaa, 0xe6, 0x90, 0x39,
- 0x1d, 0xa6, 0x32, 0x6a, 0x34, 0xe3, 0x55, 0xf8,
- 0x58, 0xa0, 0x58, 0x7d, 0x33, 0xe0, 0x22, 0x39,
- 0x44, 0x64, 0x87, 0x86, 0x5a, 0x2f, 0xa7, 0x7e,
- 0x0f, 0x38, 0xea, 0xb0, 0x30, 0xcc, 0x61, 0xa5,
- 0x6a, 0x32, 0xae, 0x1e, 0xf7, 0xe9, 0xd0, 0xa9,
- 0x0c, 0x32, 0x4b, 0xb5, 0x49, 0x28, 0xab, 0x85,
- 0x2f, 0x8e, 0x01, 0x36, 0x38, 0x52, 0xd0, 0xba,
- 0xd6, 0x02, 0x78, 0xf8, 0x0e, 0x3e, 0x9c, 0x8b,
- 0x6b, 0x45, 0x99, 0x3f, 0x5c, 0xfe, 0x58, 0xf1,
- 0x5c, 0x94, 0x04, 0xe1, 0xf5, 0x18, 0x6d, 0x51,
- 0xb2, 0x5d, 0x18, 0x20, 0xb6, 0xc2, 0x9a, 0x42,
- 0x1d, 0xb3, 0xab, 0x3c, 0xb6, 0x3a, 0x13, 0x03,
- 0xb2, 0x46, 0x82, 0x4f, 0xfc, 0x64, 0xbc, 0x4f,
- 0xca, 0xfa, 0x9c, 0xc0, 0xd5, 0xa7, 0xbd, 0x11,
- 0xb7, 0xe4, 0x5a, 0xf6, 0x6f, 0x4d, 0x4d, 0x54,
- 0xea, 0xa4, 0x98, 0x66, 0xd4, 0x22, 0x3b, 0xd3,
- 0x8f, 0x34, 0x47, 0xd9, 0x7c, 0xf4, 0x72, 0x3b,
- 0x4d, 0x02, 0x77, 0xf6, 0xd6, 0xdd, 0x08, 0x0a,
- 0x81, 0xe1, 0x86, 0x89, 0x3e, 0x56, 0x10, 0x3c,
- 0xba, 0xd7, 0x81, 0x8c, 0x08, 0xbc, 0x8b, 0xe2,
- 0x53, 0xec, 0xa7, 0x89, 0xee, 0xc8, 0x56, 0xb5,
- 0x36, 0x2c, 0xb2, 0x03, 0xba, 0x99, 0xdd, 0x7c,
- 0x48, 0xa0, 0xb0, 0xbc, 0x91, 0x33, 0xe9, 0xa8,
- 0xcb, 0xcd, 0xcf, 0x59, 0x5f, 0x1f, 0x15, 0xe2,
- 0x56, 0xf5, 0x4e, 0x01, 0x35, 0x27, 0x45, 0x77,
- 0x47, 0xc8, 0xbc, 0xcb, 0x7e, 0x39, 0xc1, 0x97,
- 0x28, 0xd3, 0x84, 0xfc, 0x2c, 0x3e, 0xc8, 0xad,
- 0x9c, 0xf8, 0x8a, 0x61, 0x9c, 0x28, 0xaa, 0xc5,
- 0x99, 0x20, 0x43, 0x85, 0x9d, 0xa5, 0xe2, 0x8b,
- 0xb8, 0xae, 0xeb, 0xd0, 0x32, 0x0d, 0x52, 0x78,
- 0x09, 0x56, 0x3f, 0xc7, 0xd8, 0x7e, 0x26, 0xfc,
- 0x37, 0xfb, 0x6f, 0x04, 0xfc, 0xfa, 0x92, 0x10,
- 0xac, 0xf8, 0x3e, 0x21, 0xdc, 0x8c, 0x21, 0x16,
- 0x7d, 0x67, 0x6e, 0xf6, 0xcd, 0xda, 0xb6, 0x98,
- 0x23, 0xab, 0x23, 0x3c, 0xb2, 0x10, 0xa0, 0x53,
- 0x5a, 0x56, 0x9f, 0xc5, 0xd0, 0xff, 0xbb, 0xe4,
- 0x98, 0x3c, 0x69, 0x1e, 0xdb, 0x38, 0x8f, 0x7e,
- 0x0f, 0xd2, 0x98, 0x88, 0x81, 0x8b, 0x45, 0x67,
- 0xea, 0x33, 0xf1, 0xeb, 0xe9, 0x97, 0x55, 0x2e,
- 0xd9, 0xaa, 0xeb, 0x5a, 0xec, 0xda, 0xe1, 0x68,
- 0xa8, 0x9d, 0x3c, 0x84, 0x7c, 0x05, 0x3d, 0x62,
- 0x87, 0x8f, 0x03, 0x21, 0x28, 0x95, 0x0c, 0x89,
- 0x25, 0x22, 0x4a, 0xb0, 0x93, 0xa9, 0x50, 0xa2,
- 0x2f, 0x57, 0x6e, 0x18, 0x42, 0x19, 0x54, 0x0c,
- 0x55, 0x67, 0xc6, 0x11, 0x49, 0xf4, 0x5c, 0xd2,
- 0xe9, 0x3d, 0xdd, 0x8b, 0x48, 0x71, 0x21, 0x00,
- 0xc3, 0x9a, 0x6c, 0x85, 0x74, 0x28, 0x83, 0x4a,
- 0x1b, 0x31, 0x05, 0xe1, 0x06, 0x92, 0xe7, 0xda,
- 0x85, 0x73, 0x78, 0x45, 0x20, 0x7f, 0xae, 0x13,
- 0x7c, 0x33, 0x06, 0x22, 0xf4, 0x83, 0xf9, 0x35,
- 0x3f, 0x6c, 0x71, 0xa8, 0x4e, 0x48, 0xbe, 0x9b,
- 0xce, 0x8a, 0xba, 0xda, 0xbe, 0x28, 0x08, 0xf7,
- 0xe2, 0x14, 0x8c, 0x71, 0xea, 0x72, 0xf9, 0x33,
- 0xf2, 0x88, 0x3f, 0xd7, 0xbb, 0x69, 0x6c, 0x29,
- 0x19, 0xdc, 0x84, 0xce, 0x1f, 0x12, 0x4f, 0xc8,
- 0xaf, 0xa5, 0x04, 0xba, 0x5a, 0xab, 0xb0, 0xd9,
- 0x14, 0x1f, 0x6c, 0x68, 0x98, 0x39, 0x89, 0x7a,
- 0xd9, 0xd8, 0x2f, 0xdf, 0xa8, 0x47, 0x4a, 0x25,
- 0xe2, 0xfb, 0x33, 0xf4, 0x59, 0x78, 0xe1, 0x68,
- 0x85, 0xcf, 0xfe, 0x59, 0x20, 0xd4, 0x05, 0x1d,
- 0x80, 0x99, 0xae, 0xbc, 0xca, 0xae, 0x0f, 0x2f,
- 0x65, 0x43, 0x34, 0x8e, 0x7e, 0xac, 0xd3, 0x93,
- 0x2f, 0xac, 0x6d, 0x14, 0x3d, 0x02, 0x07, 0x70,
- 0x9d, 0xa4, 0xf3, 0x1b, 0x5c, 0x36, 0xfc, 0x01,
- 0x73, 0x34, 0x85, 0x0c, 0x6c, 0xd6, 0xf1, 0xbd,
- 0x3f, 0xdf, 0xee, 0xf5, 0xd9, 0xba, 0x56, 0xef,
- 0xf4, 0x9b, 0x6b, 0xee, 0x9f, 0x5a, 0x78, 0x6d,
- 0x32, 0x19, 0xf4, 0xf7, 0xf8, 0x4c, 0x69, 0x0b,
- 0x4b, 0xbc, 0xbb, 0xb7, 0xf2, 0x85, 0xaf, 0x70,
- 0x75, 0x24, 0x6c, 0x54, 0xa7, 0x0e, 0x4d, 0x1d,
- 0x01, 0xbf, 0x08, 0xac, 0xcf, 0x7f, 0x2c, 0xe3,
- 0x14, 0x89, 0x5e, 0x70, 0x5a, 0x99, 0x92, 0xcd,
- 0x01, 0x84, 0xc8, 0xd2, 0xab, 0xe5, 0x4f, 0x58,
- 0xe7, 0x0f, 0x2f, 0x0e, 0xff, 0x68, 0xea, 0xfd,
- 0x15, 0xb3, 0x17, 0xe6, 0xb0, 0xe7, 0x85, 0xd8,
- 0x23, 0x2e, 0x05, 0xc7, 0xc9, 0xc4, 0x46, 0x1f,
- 0xe1, 0x9e, 0x49, 0x20, 0x23, 0x24, 0x4d, 0x7e,
- 0x29, 0x65, 0xff, 0xf4, 0xb6, 0xfd, 0x1a, 0x85,
- 0xc4, 0x16, 0xec, 0xfc, 0xea, 0x7b, 0xd6, 0x2c,
- 0x43, 0xf8, 0xb7, 0xbf, 0x79, 0xc0, 0x85, 0xcd,
- 0xef, 0xe1, 0x98, 0xd3, 0xa5, 0xf7, 0x90, 0x8c,
- 0xe9, 0x7f, 0x80, 0x6b, 0xd2, 0xac, 0x4c, 0x30,
- 0xa7, 0xc6, 0x61, 0x6c, 0xd2, 0xf9, 0x2c, 0xff,
- 0x30, 0xbc, 0x22, 0x81, 0x7d, 0x93, 0x12, 0xe4,
- 0x0a, 0xcd, 0xaf, 0xdd, 0xe8, 0xab, 0x0a, 0x1e,
- 0x13, 0xa4, 0x27, 0xc3, 0x5f, 0xf7, 0x4b, 0xbb,
- 0x37, 0x09, 0x4b, 0x91, 0x6f, 0x92, 0x4f, 0xaf,
- 0x52, 0xee, 0xdf, 0xef, 0x09, 0x6f, 0xf7, 0x5c,
- 0x6e, 0x12, 0x17, 0x72, 0x63, 0x57, 0xc7, 0xba,
- 0x3b, 0x6b, 0x38, 0x32, 0x73, 0x1b, 0x9c, 0x80,
- 0xc1, 0x7a, 0xc6, 0xcf, 0xcd, 0x35, 0xc0, 0x6b,
- 0x31, 0x1a, 0x6b, 0xe9, 0xd8, 0x2c, 0x29, 0x3f,
- 0x96, 0xfb, 0xb6, 0xcd, 0x13, 0x91, 0x3b, 0xc2,
- 0xd2, 0xa3, 0x31, 0x8d, 0xa4, 0xcd, 0x57, 0xcd,
- 0x13, 0x3d, 0x64, 0xfd, 0x06, 0xce, 0xe6, 0xdc,
- 0x0c, 0x24, 0x43, 0x31, 0x40, 0x57, 0xf1, 0x72,
- 0x17, 0xe3, 0x3a, 0x63, 0x6d, 0x35, 0xcf, 0x5d,
- 0x97, 0x40, 0x59, 0xdd, 0xf7, 0x3c, 0x02, 0xf7,
- 0x1c, 0x7e, 0x05, 0xbb, 0xa9, 0x0d, 0x01, 0xb1,
- 0x8e, 0xc0, 0x30, 0xa9, 0x53, 0x24, 0xc9, 0x89,
- 0x84, 0x6d, 0xaa, 0xd0, 0xcd, 0x91, 0xc2, 0x4d,
- 0x91, 0xb0, 0x89, 0xe2, 0xbf, 0x83, 0x44, 0xaa,
- 0x28, 0x72, 0x23, 0xa0, 0xc2, 0xad, 0xad, 0x1c,
- 0xfc, 0x3f, 0x09, 0x7a, 0x0b, 0xdc, 0xc5, 0x1b,
- 0x87, 0x13, 0xc6, 0x5b, 0x59, 0x8d, 0xf2, 0xc8,
- 0xaf, 0xdf, 0x11, 0x95,
- },
+ .result =
+ "\xb5\x81\xf5\x64\x18\x73\xe3\xf0"
+ "\x4c\x13\xf2\x77\x18\x60\x65\x5e"
+ "\x29\x01\xce\x98\x55\x53\xf9\x0c"
+ "\x2a\x08\xd5\x09\xb3\x57\x55\x56"
+ "\xc5\xe9\x56\x90\xcb\x6a\xa3\xc0"
+ "\xff\xc4\x79\xb4\xd2\x97\x5d\xc4"
+ "\x43\xd1\xfe\x94\x7b\x88\x06\x5a"
+ "\xb2\x9e\x2c\xfc\x44\x03\xb7\x90"
+ "\xa0\xc1\xba\x6a\x33\xb8\xc7\xb2"
+ "\x9d\xe1\x12\x4f\xc0\x64\xd4\x01"
+ "\xfe\x8c\x7a\x66\xf7\xe6\x5a\x91"
+ "\xbb\xde\x56\x86\xab\x65\x21\x30"
+ "\x00\x84\x65\x24\xa5\x7d\x85\xb4"
+ "\xe3\x17\xed\x3a\xb7\x6f\xb4\x0b"
+ "\x0b\xaf\x15\xae\x5a\x8f\xf2\x0c"
+ "\x2f\x27\xf4\x09\xd8\xd2\x96\xb7"
+ "\x71\xf2\xc5\x99\x4d\x7e\x7f\x75"
+ "\x77\x89\x30\x8b\x59\xdb\xa2\xb2"
+ "\xa0\xf3\x19\x39\x2b\xc5\x7e\x3f"
+ "\x4f\xd9\xd3\x56\x28\x97\x44\xdc"
+ "\xc0\x8b\x77\x24\xd9\x52\xe7\xc5"
+ "\xaf\xf6\x7d\x59\xb2\x44\x05\x1d"
+ "\xb1\xb0\x11\xa5\x0f\xec\x33\xe1"
+ "\x6d\x1b\x4e\x1f\xff\x57\x91\xb4"
+ "\x5b\x9a\x96\xc5\x53\xbc\xae\x20"
+ "\x3c\xbb\x14\xe2\xe8\x22\x33\xc1"
+ "\x5e\x76\x9e\x46\x99\xf6\x2a\x15"
+ "\xc6\x97\x02\xa0\x66\x43\xd1\xa6"
+ "\x31\xa6\x9f\xfb\xf4\xd3\x69\xe5"
+ "\xcd\x76\x95\xb8\x7a\x82\x7f\x21"
+ "\x45\xff\x3f\xce\x55\xf6\x95\x10"
+ "\x08\x77\x10\x43\xc6\xf3\x09\xe5"
+ "\x68\xe7\x3c\xad\x00\x52\x45\x0d"
+ "\xfe\x2d\xc6\xc2\x94\x8c\x12\x1d"
+ "\xe6\x25\xae\x98\x12\x8e\x19\x9c"
+ "\x81\x68\xb1\x11\xf6\x69\xda\xe3"
+ "\x62\x08\x18\x7a\x25\x49\x28\xac"
+ "\xba\x71\x12\x0b\xe4\xa2\xe5\xc7"
+ "\x5d\x8e\xec\x49\x40\x21\xbf\x5a"
+ "\x98\xf3\x02\x68\x55\x03\x7f\x8a"
+ "\xe5\x94\x0c\x32\x5c\x07\x82\x63"
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+ "\x82\x36\x6a\x0c\x46\x22\x15\xe9"
+ "\xff\x72\x41\x91\x91\x7d\x3a\xb7"
+ "\xdd\x65\x99\x70\xf6\x8d\x84\xf8"
+ "\x67\x15\x20\x11\xd6\xb2\x55\x7b"
+ "\xdb\x87\xee\xef\x55\x89\x2a\x59"
+ "\x2b\x07\x8f\x43\x8a\x59\x3c\x01"
+ "\x8b\x65\x54\xa1\x66\xd5\x38\xbd"
+ "\xc6\x30\xa9\xcc\x49\xb6\xa8\x1b"
+ "\xb8\xc0\x0e\xe3\x45\x28\xe2\xff"
+ "\x41\x9f\x7e\x7c\xd1\xae\x9e\x25"
+ "\x3f\x4c\x7c\x7c\xf4\xa8\x26\x4d"
+ "\x5c\xfd\x4b\x27\x18\xf9\x61\x76"
+ "\x48\xba\x0c\x6b\xa9\x4d\xfc\xf5"
+ "\x3b\x35\x7e\x2f\x4a\xa9\xc2\x9a"
+ "\xae\xab\x86\x09\x89\xc9\xc2\x40"
+ "\x39\x2c\x81\xb3\xb8\x17\x67\xc2"
+ "\x0d\x32\x4a\x3a\x67\x81\xd7\x1a"
+ "\x34\x52\xc5\xdb\x0a\xf5\x63\x39"
+ "\xea\x1f\xe1\x7c\xa1\x9e\xc1\x35"
+ "\xe3\xb1\x18\x45\x67\xf9\x22\x38"
+ "\x95\xd9\x34\x34\x86\xc6\x41\x94"
+ "\x15\xf9\x5b\x41\xa6\x87\x8b\xf8"
+ "\xd5\xe1\x1b\xe2\x5b\xf3\x86\x10"
+ "\xff\xe6\xae\x69\x76\xbc\x0d\xb4"
+ "\x09\x90\x0c\xa2\x65\x0c\xad\x74"
+ "\xf5\xd7\xff\xda\xc1\xce\x85\xbe"
+ "\x00\xa7\xff\x4d\x2f\x65\xd3\x8c"
+ "\x86\x2d\x05\xe8\xed\x3e\x6b\x8b"
+ "\x0f\x3d\x83\x8c\xf1\x1d\x5b\x96"
+ "\x2e\xb1\x9c\xc2\x98\xe1\x70\xb9"
+ "\xba\x5c\x8a\x43\xd6\x34\xa7\x2d"
+ "\xc9\x92\xae\xf2\xa5\x7b\x05\x49"
+ "\xa7\x33\x34\x86\xca\xe4\x96\x23"
+ "\x76\x5b\xf2\xc6\xf1\x51\x28\x42"
+ "\x7b\xcc\x76\x8f\xfa\xa2\xad\x31"
+ "\xd4\xd6\x7a\x6d\x25\x25\x54\xe4"
+ "\x3f\x50\x59\xe1\x5c\x05\xb7\x27"
+ "\x48\xbf\x07\xec\x1b\x13\xbe\x2b"
+ "\xa1\x57\x2b\xd5\xab\xd7\xd0\x4c"
+ "\x1e\xcb\x71\x9b\xc5\x90\x85\xd3"
+ "\xde\x59\xec\x71\xeb\x89\xbb\xd0"
+ "\x09\x50\xe1\x16\x3f\xfd\x1c\x34"
+ "\xc3\x1c\xa1\x10\x77\x53\x98\xef"
+ "\xf2\xfd\xa5\x01\x59\xc2\x9b\x26"
+ "\xc7\x42\xd9\x49\xda\x58\x2b\x6e"
+ "\x9f\x53\x19\x76\x7e\xd9\xc9\x0e"
+ "\x68\xc8\x7f\x51\x22\x42\xef\x49"
+ "\xa4\x55\xb6\x36\xac\x09\xc7\x31"
+ "\x88\x15\x4b\x2e\x8f\x3a\x08\xf7"
+ "\xd8\xf7\xa8\xc5\xa9\x33\xa6\x45"
+ "\xe4\xc4\x94\x76\xf3\x0d\x8f\x7e"
+ "\xc8\xf6\xbc\x23\x0a\xb6\x4c\xd3"
+ "\x6a\xcd\x36\xc2\x90\x5c\x5c\x3c"
+ "\x65\x7b\xc2\xd6\xcc\xe6\x0d\x87"
+ "\x73\x2e\x71\x79\x16\x06\x63\x28"
+ "\x09\x15\xd8\x89\x38\x38\x3d\xb5"
+ "\x42\x1c\x08\x24\xf7\x2a\xd2\x9d"
+ "\xc8\xca\xef\xf9\x27\xd8\x07\x86"
+ "\xf7\x43\x0b\x55\x15\x3f\x9f\x83"
+ "\xef\xdc\x49\x9d\x2a\xc1\x54\x62"
+ "\xbd\x9b\x66\x55\x9f\xb7\x12\xf3"
+ "\x1b\x4d\x9d\x2a\x5c\xed\x87\x75"
+ "\x87\x26\xec\x61\x2c\xb4\x0f\x89"
+ "\xb0\xfb\x2e\x68\x5d\x15\xc7\x8d"
+ "\x2e\xc0\xd9\xec\xaf\x4f\xd2\x25"
+ "\x29\xe8\xd2\x26\x2b\x67\xe9\xfc"
+ "\x2b\xa8\x67\x96\x12\x1f\x5b\x96"
+ "\xc6\x14\x53\xaf\x44\xea\xd6\xe2"
+ "\x94\x98\xe4\x12\x93\x4c\x92\xe0"
+ "\x18\xa5\x8d\x2d\xe4\x71\x3c\x47"
+ "\x4c\xf7\xe6\x47\x9e\xc0\x68\xdf"
+ "\xd4\xf5\x5a\x74\xb1\x2b\x29\x03"
+ "\x19\x07\xaf\x90\x62\x5c\x68\x98"
+ "\x48\x16\x11\x02\x9d\xee\xb4\x9b"
+ "\xe5\x42\x7f\x08\xfd\x16\x32\x0b"
+ "\xd0\xb3\xfa\x2b\xb7\x99\xf9\x29"
+ "\xcd\x20\x45\x9f\xb3\x1a\x5d\xa2"
+ "\xaf\x4d\xe0\xbd\x42\x0d\xbc\x74"
+ "\x99\x9c\x8e\x53\x1a\xb4\x3e\xbd"
+ "\xa2\x9a\x2d\xf7\xf8\x39\x0f\x67"
+ "\x63\xfc\x6b\xc0\xaf\xb3\x4b\x4f"
+ "\x55\xc4\xcf\xa7\xc8\x04\x11\x3e"
+ "\x14\x32\xbb\x1b\x38\x77\xd6\x7f"
+ "\x54\x4c\xdf\x75\xf3\x07\x2d\x33"
+ "\x9b\xa8\x20\xe1\x7b\x12\xb5\xf3"
+ "\xef\x2f\xce\x72\xe5\x24\x60\xc1"
+ "\x30\xe2\xab\xa1\x8e\x11\x09\xa8"
+ "\x21\x33\x44\xfe\x7f\x35\x32\x93"
+ "\x39\xa7\xad\x8b\x79\x06\xb2\xcb"
+ "\x4e\xa9\x5f\xc7\xba\x74\x29\xec"
+ "\x93\xa0\x4e\x54\x93\xc0\xbc\x55"
+ "\x64\xf0\x48\xe5\x57\x99\xee\x75"
+ "\xd6\x79\x0f\x66\xb7\xc6\x57\x76"
+ "\xf7\xb7\xf3\x9c\xc5\x60\xe8\x7f"
+ "\x83\x76\xd6\x0e\xaa\xe6\x90\x39"
+ "\x1d\xa6\x32\x6a\x34\xe3\x55\xf8"
+ "\x58\xa0\x58\x7d\x33\xe0\x22\x39"
+ "\x44\x64\x87\x86\x5a\x2f\xa7\x7e"
+ "\x0f\x38\xea\xb0\x30\xcc\x61\xa5"
+ "\x6a\x32\xae\x1e\xf7\xe9\xd0\xa9"
+ "\x0c\x32\x4b\xb5\x49\x28\xab\x85"
+ "\x2f\x8e\x01\x36\x38\x52\xd0\xba"
+ "\xd6\x02\x78\xf8\x0e\x3e\x9c\x8b"
+ "\x6b\x45\x99\x3f\x5c\xfe\x58\xf1"
+ "\x5c\x94\x04\xe1\xf5\x18\x6d\x51"
+ "\xb2\x5d\x18\x20\xb6\xc2\x9a\x42"
+ "\x1d\xb3\xab\x3c\xb6\x3a\x13\x03"
+ "\xb2\x46\x82\x4f\xfc\x64\xbc\x4f"
+ "\xca\xfa\x9c\xc0\xd5\xa7\xbd\x11"
+ "\xb7\xe4\x5a\xf6\x6f\x4d\x4d\x54"
+ "\xea\xa4\x98\x66\xd4\x22\x3b\xd3"
+ "\x8f\x34\x47\xd9\x7c\xf4\x72\x3b"
+ "\x4d\x02\x77\xf6\xd6\xdd\x08\x0a"
+ "\x81\xe1\x86\x89\x3e\x56\x10\x3c"
+ "\xba\xd7\x81\x8c\x08\xbc\x8b\xe2"
+ "\x53\xec\xa7\x89\xee\xc8\x56\xb5"
+ "\x36\x2c\xb2\x03\xba\x99\xdd\x7c"
+ "\x48\xa0\xb0\xbc\x91\x33\xe9\xa8"
+ "\xcb\xcd\xcf\x59\x5f\x1f\x15\xe2"
+ "\x56\xf5\x4e\x01\x35\x27\x45\x77"
+ "\x47\xc8\xbc\xcb\x7e\x39\xc1\x97"
+ "\x28\xd3\x84\xfc\x2c\x3e\xc8\xad"
+ "\x9c\xf8\x8a\x61\x9c\x28\xaa\xc5"
+ "\x99\x20\x43\x85\x9d\xa5\xe2\x8b"
+ "\xb8\xae\xeb\xd0\x32\x0d\x52\x78"
+ "\x09\x56\x3f\xc7\xd8\x7e\x26\xfc"
+ "\x37\xfb\x6f\x04\xfc\xfa\x92\x10"
+ "\xac\xf8\x3e\x21\xdc\x8c\x21\x16"
+ "\x7d\x67\x6e\xf6\xcd\xda\xb6\x98"
+ "\x23\xab\x23\x3c\xb2\x10\xa0\x53"
+ "\x5a\x56\x9f\xc5\xd0\xff\xbb\xe4"
+ "\x98\x3c\x69\x1e\xdb\x38\x8f\x7e"
+ "\x0f\xd2\x98\x88\x81\x8b\x45\x67"
+ "\xea\x33\xf1\xeb\xe9\x97\x55\x2e"
+ "\xd9\xaa\xeb\x5a\xec\xda\xe1\x68"
+ "\xa8\x9d\x3c\x84\x7c\x05\x3d\x62"
+ "\x87\x8f\x03\x21\x28\x95\x0c\x89"
+ "\x25\x22\x4a\xb0\x93\xa9\x50\xa2"
+ "\x2f\x57\x6e\x18\x42\x19\x54\x0c"
+ "\x55\x67\xc6\x11\x49\xf4\x5c\xd2"
+ "\xe9\x3d\xdd\x8b\x48\x71\x21\x00"
+ "\xc3\x9a\x6c\x85\x74\x28\x83\x4a"
+ "\x1b\x31\x05\xe1\x06\x92\xe7\xda"
+ "\x85\x73\x78\x45\x20\x7f\xae\x13"
+ "\x7c\x33\x06\x22\xf4\x83\xf9\x35"
+ "\x3f\x6c\x71\xa8\x4e\x48\xbe\x9b"
+ "\xce\x8a\xba\xda\xbe\x28\x08\xf7"
+ "\xe2\x14\x8c\x71\xea\x72\xf9\x33"
+ "\xf2\x88\x3f\xd7\xbb\x69\x6c\x29"
+ "\x19\xdc\x84\xce\x1f\x12\x4f\xc8"
+ "\xaf\xa5\x04\xba\x5a\xab\xb0\xd9"
+ "\x14\x1f\x6c\x68\x98\x39\x89\x7a"
+ "\xd9\xd8\x2f\xdf\xa8\x47\x4a\x25"
+ "\xe2\xfb\x33\xf4\x59\x78\xe1\x68"
+ "\x85\xcf\xfe\x59\x20\xd4\x05\x1d"
+ "\x80\x99\xae\xbc\xca\xae\x0f\x2f"
+ "\x65\x43\x34\x8e\x7e\xac\xd3\x93"
+ "\x2f\xac\x6d\x14\x3d\x02\x07\x70"
+ "\x9d\xa4\xf3\x1b\x5c\x36\xfc\x01"
+ "\x73\x34\x85\x0c\x6c\xd6\xf1\xbd"
+ "\x3f\xdf\xee\xf5\xd9\xba\x56\xef"
+ "\xf4\x9b\x6b\xee\x9f\x5a\x78\x6d"
+ "\x32\x19\xf4\xf7\xf8\x4c\x69\x0b"
+ "\x4b\xbc\xbb\xb7\xf2\x85\xaf\x70"
+ "\x75\x24\x6c\x54\xa7\x0e\x4d\x1d"
+ "\x01\xbf\x08\xac\xcf\x7f\x2c\xe3"
+ "\x14\x89\x5e\x70\x5a\x99\x92\xcd"
+ "\x01\x84\xc8\xd2\xab\xe5\x4f\x58"
+ "\xe7\x0f\x2f\x0e\xff\x68\xea\xfd"
+ "\x15\xb3\x17\xe6\xb0\xe7\x85\xd8"
+ "\x23\x2e\x05\xc7\xc9\xc4\x46\x1f"
+ "\xe1\x9e\x49\x20\x23\x24\x4d\x7e"
+ "\x29\x65\xff\xf4\xb6\xfd\x1a\x85"
+ "\xc4\x16\xec\xfc\xea\x7b\xd6\x2c"
+ "\x43\xf8\xb7\xbf\x79\xc0\x85\xcd"
+ "\xef\xe1\x98\xd3\xa5\xf7\x90\x8c"
+ "\xe9\x7f\x80\x6b\xd2\xac\x4c\x30"
+ "\xa7\xc6\x61\x6c\xd2\xf9\x2c\xff"
+ "\x30\xbc\x22\x81\x7d\x93\x12\xe4"
+ "\x0a\xcd\xaf\xdd\xe8\xab\x0a\x1e"
+ "\x13\xa4\x27\xc3\x5f\xf7\x4b\xbb"
+ "\x37\x09\x4b\x91\x6f\x92\x4f\xaf"
+ "\x52\xee\xdf\xef\x09\x6f\xf7\x5c"
+ "\x6e\x12\x17\x72\x63\x57\xc7\xba"
+ "\x3b\x6b\x38\x32\x73\x1b\x9c\x80"
+ "\xc1\x7a\xc6\xcf\xcd\x35\xc0\x6b"
+ "\x31\x1a\x6b\xe9\xd8\x2c\x29\x3f"
+ "\x96\xfb\xb6\xcd\x13\x91\x3b\xc2"
+ "\xd2\xa3\x31\x8d\xa4\xcd\x57\xcd"
+ "\x13\x3d\x64\xfd\x06\xce\xe6\xdc"
+ "\x0c\x24\x43\x31\x40\x57\xf1\x72"
+ "\x17\xe3\x3a\x63\x6d\x35\xcf\x5d"
+ "\x97\x40\x59\xdd\xf7\x3c\x02\xf7"
+ "\x1c\x7e\x05\xbb\xa9\x0d\x01\xb1"
+ "\x8e\xc0\x30\xa9\x53\x24\xc9\x89"
+ "\x84\x6d\xaa\xd0\xcd\x91\xc2\x4d"
+ "\x91\xb0\x89\xe2\xbf\x83\x44\xaa"
+ "\x28\x72\x23\xa0\xc2\xad\xad\x1c"
+ "\xfc\x3f\x09\x7a\x0b\xdc\xc5\x1b"
+ "\x87\x13\xc6\x5b\x59\x8d\xf2\xc8"
+ "\xaf\xdf\x11\x95",
.rlen = 4100,
},
};
+/*
+ * CTS (Cipher Text Stealing) mode tests
+ */
+#define CTS_MODE_ENC_TEST_VECTORS 6
+#define CTS_MODE_DEC_TEST_VECTORS 6
+static struct cipher_testvec cts_mode_enc_tv_template[] = {
+ { /* from rfc3962 */
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .ilen = 17,
+ .input = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20",
+ .rlen = 17,
+ .result = "\xc6\x35\x35\x68\xf2\xbf\x8c\xb4"
+ "\xd8\xa5\x80\x36\x2d\xa7\xff\x7f"
+ "\x97",
+ }, {
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .ilen = 31,
+ .input = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20\x47\x65\x6e\x65\x72\x61\x6c"
+ "\x20\x47\x61\x75\x27\x73\x20",
+ .rlen = 31,
+ .result = "\xfc\x00\x78\x3e\x0e\xfd\xb2\xc1"
+ "\xd4\x45\xd4\xc8\xef\xf7\xed\x22"
+ "\x97\x68\x72\x68\xd6\xec\xcc\xc0"
+ "\xc0\x7b\x25\xe2\x5e\xcf\xe5",
+ }, {
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .ilen = 32,
+ .input = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20\x47\x65\x6e\x65\x72\x61\x6c"
+ "\x20\x47\x61\x75\x27\x73\x20\x43",
+ .rlen = 32,
+ .result = "\x39\x31\x25\x23\xa7\x86\x62\xd5"
+ "\xbe\x7f\xcb\xcc\x98\xeb\xf5\xa8"
+ "\x97\x68\x72\x68\xd6\xec\xcc\xc0"
+ "\xc0\x7b\x25\xe2\x5e\xcf\xe5\x84",
+ }, {
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .ilen = 47,
+ .input = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20\x47\x65\x6e\x65\x72\x61\x6c"
+ "\x20\x47\x61\x75\x27\x73\x20\x43"
+ "\x68\x69\x63\x6b\x65\x6e\x2c\x20"
+ "\x70\x6c\x65\x61\x73\x65\x2c",
+ .rlen = 47,
+ .result = "\x97\x68\x72\x68\xd6\xec\xcc\xc0"
+ "\xc0\x7b\x25\xe2\x5e\xcf\xe5\x84"
+ "\xb3\xff\xfd\x94\x0c\x16\xa1\x8c"
+ "\x1b\x55\x49\xd2\xf8\x38\x02\x9e"
+ "\x39\x31\x25\x23\xa7\x86\x62\xd5"
+ "\xbe\x7f\xcb\xcc\x98\xeb\xf5",
+ }, {
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .ilen = 48,
+ .input = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20\x47\x65\x6e\x65\x72\x61\x6c"
+ "\x20\x47\x61\x75\x27\x73\x20\x43"
+ "\x68\x69\x63\x6b\x65\x6e\x2c\x20"
+ "\x70\x6c\x65\x61\x73\x65\x2c\x20",
+ .rlen = 48,
+ .result = "\x97\x68\x72\x68\xd6\xec\xcc\xc0"
+ "\xc0\x7b\x25\xe2\x5e\xcf\xe5\x84"
+ "\x9d\xad\x8b\xbb\x96\xc4\xcd\xc0"
+ "\x3b\xc1\x03\xe1\xa1\x94\xbb\xd8"
+ "\x39\x31\x25\x23\xa7\x86\x62\xd5"
+ "\xbe\x7f\xcb\xcc\x98\xeb\xf5\xa8",
+ }, {
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .ilen = 64,
+ .input = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20\x47\x65\x6e\x65\x72\x61\x6c"
+ "\x20\x47\x61\x75\x27\x73\x20\x43"
+ "\x68\x69\x63\x6b\x65\x6e\x2c\x20"
+ "\x70\x6c\x65\x61\x73\x65\x2c\x20"
+ "\x61\x6e\x64\x20\x77\x6f\x6e\x74"
+ "\x6f\x6e\x20\x73\x6f\x75\x70\x2e",
+ .rlen = 64,
+ .result = "\x97\x68\x72\x68\xd6\xec\xcc\xc0"
+ "\xc0\x7b\x25\xe2\x5e\xcf\xe5\x84"
+ "\x39\x31\x25\x23\xa7\x86\x62\xd5"
+ "\xbe\x7f\xcb\xcc\x98\xeb\xf5\xa8"
+ "\x48\x07\xef\xe8\x36\xee\x89\xa5"
+ "\x26\x73\x0d\xbc\x2f\x7b\xc8\x40"
+ "\x9d\xad\x8b\xbb\x96\xc4\xcd\xc0"
+ "\x3b\xc1\x03\xe1\xa1\x94\xbb\xd8",
+ }
+};
+
+static struct cipher_testvec cts_mode_dec_tv_template[] = {
+ { /* from rfc3962 */
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .rlen = 17,
+ .result = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20",
+ .ilen = 17,
+ .input = "\xc6\x35\x35\x68\xf2\xbf\x8c\xb4"
+ "\xd8\xa5\x80\x36\x2d\xa7\xff\x7f"
+ "\x97",
+ }, {
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .rlen = 31,
+ .result = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20\x47\x65\x6e\x65\x72\x61\x6c"
+ "\x20\x47\x61\x75\x27\x73\x20",
+ .ilen = 31,
+ .input = "\xfc\x00\x78\x3e\x0e\xfd\xb2\xc1"
+ "\xd4\x45\xd4\xc8\xef\xf7\xed\x22"
+ "\x97\x68\x72\x68\xd6\xec\xcc\xc0"
+ "\xc0\x7b\x25\xe2\x5e\xcf\xe5",
+ }, {
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .rlen = 32,
+ .result = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20\x47\x65\x6e\x65\x72\x61\x6c"
+ "\x20\x47\x61\x75\x27\x73\x20\x43",
+ .ilen = 32,
+ .input = "\x39\x31\x25\x23\xa7\x86\x62\xd5"
+ "\xbe\x7f\xcb\xcc\x98\xeb\xf5\xa8"
+ "\x97\x68\x72\x68\xd6\xec\xcc\xc0"
+ "\xc0\x7b\x25\xe2\x5e\xcf\xe5\x84",
+ }, {
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .rlen = 47,
+ .result = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20\x47\x65\x6e\x65\x72\x61\x6c"
+ "\x20\x47\x61\x75\x27\x73\x20\x43"
+ "\x68\x69\x63\x6b\x65\x6e\x2c\x20"
+ "\x70\x6c\x65\x61\x73\x65\x2c",
+ .ilen = 47,
+ .input = "\x97\x68\x72\x68\xd6\xec\xcc\xc0"
+ "\xc0\x7b\x25\xe2\x5e\xcf\xe5\x84"
+ "\xb3\xff\xfd\x94\x0c\x16\xa1\x8c"
+ "\x1b\x55\x49\xd2\xf8\x38\x02\x9e"
+ "\x39\x31\x25\x23\xa7\x86\x62\xd5"
+ "\xbe\x7f\xcb\xcc\x98\xeb\xf5",
+ }, {
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .rlen = 48,
+ .result = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20\x47\x65\x6e\x65\x72\x61\x6c"
+ "\x20\x47\x61\x75\x27\x73\x20\x43"
+ "\x68\x69\x63\x6b\x65\x6e\x2c\x20"
+ "\x70\x6c\x65\x61\x73\x65\x2c\x20",
+ .ilen = 48,
+ .input = "\x97\x68\x72\x68\xd6\xec\xcc\xc0"
+ "\xc0\x7b\x25\xe2\x5e\xcf\xe5\x84"
+ "\x9d\xad\x8b\xbb\x96\xc4\xcd\xc0"
+ "\x3b\xc1\x03\xe1\xa1\x94\xbb\xd8"
+ "\x39\x31\x25\x23\xa7\x86\x62\xd5"
+ "\xbe\x7f\xcb\xcc\x98\xeb\xf5\xa8",
+ }, {
+ .klen = 16,
+ .key = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+ "\x74\x65\x72\x69\x79\x61\x6b\x69",
+ .rlen = 64,
+ .result = "\x49\x20\x77\x6f\x75\x6c\x64\x20"
+ "\x6c\x69\x6b\x65\x20\x74\x68\x65"
+ "\x20\x47\x65\x6e\x65\x72\x61\x6c"
+ "\x20\x47\x61\x75\x27\x73\x20\x43"
+ "\x68\x69\x63\x6b\x65\x6e\x2c\x20"
+ "\x70\x6c\x65\x61\x73\x65\x2c\x20"
+ "\x61\x6e\x64\x20\x77\x6f\x6e\x74"
+ "\x6f\x6e\x20\x73\x6f\x75\x70\x2e",
+ .ilen = 64,
+ .input = "\x97\x68\x72\x68\xd6\xec\xcc\xc0"
+ "\xc0\x7b\x25\xe2\x5e\xcf\xe5\x84"
+ "\x39\x31\x25\x23\xa7\x86\x62\xd5"
+ "\xbe\x7f\xcb\xcc\x98\xeb\xf5\xa8"
+ "\x48\x07\xef\xe8\x36\xee\x89\xa5"
+ "\x26\x73\x0d\xbc\x2f\x7b\xc8\x40"
+ "\x9d\xad\x8b\xbb\x96\xc4\xcd\xc0"
+ "\x3b\xc1\x03\xe1\xa1\x94\xbb\xd8",
+ }
+};
+
/*
* Compression stuff.
*/
{
.inlen = 70,
.outlen = 38,
- .input = "Join us now and share the software "
- "Join us now and share the software ",
- .output = { 0xf3, 0xca, 0xcf, 0xcc, 0x53, 0x28, 0x2d, 0x56,
- 0xc8, 0xcb, 0x2f, 0x57, 0x48, 0xcc, 0x4b, 0x51,
- 0x28, 0xce, 0x48, 0x2c, 0x4a, 0x55, 0x28, 0xc9,
- 0x48, 0x55, 0x28, 0xce, 0x4f, 0x2b, 0x29, 0x07,
- 0x71, 0xbc, 0x08, 0x2b, 0x01, 0x00 },
+ .input = "Join us now and share the software "
+ "Join us now and share the software ",
+ .output = "\xf3\xca\xcf\xcc\x53\x28\x2d\x56"
+ "\xc8\xcb\x2f\x57\x48\xcc\x4b\x51"
+ "\x28\xce\x48\x2c\x4a\x55\x28\xc9"
+ "\x48\x55\x28\xce\x4f\x2b\x29\x07"
+ "\x71\xbc\x08\x2b\x01\x00",
}, {
.inlen = 191,
.outlen = 122,
.input = "This document describes a compression method based on the DEFLATE"
- "compression algorithm. This document defines the application of "
- "the DEFLATE algorithm to the IP Payload Compression Protocol.",
- .output = { 0x5d, 0x8d, 0x31, 0x0e, 0xc2, 0x30, 0x10, 0x04,
- 0xbf, 0xb2, 0x2f, 0xc8, 0x1f, 0x10, 0x04, 0x09,
- 0x89, 0xc2, 0x85, 0x3f, 0x70, 0xb1, 0x2f, 0xf8,
- 0x24, 0xdb, 0x67, 0xd9, 0x47, 0xc1, 0xef, 0x49,
- 0x68, 0x12, 0x51, 0xae, 0x76, 0x67, 0xd6, 0x27,
- 0x19, 0x88, 0x1a, 0xde, 0x85, 0xab, 0x21, 0xf2,
- 0x08, 0x5d, 0x16, 0x1e, 0x20, 0x04, 0x2d, 0xad,
- 0xf3, 0x18, 0xa2, 0x15, 0x85, 0x2d, 0x69, 0xc4,
- 0x42, 0x83, 0x23, 0xb6, 0x6c, 0x89, 0x71, 0x9b,
- 0xef, 0xcf, 0x8b, 0x9f, 0xcf, 0x33, 0xca, 0x2f,
- 0xed, 0x62, 0xa9, 0x4c, 0x80, 0xff, 0x13, 0xaf,
- 0x52, 0x37, 0xed, 0x0e, 0x52, 0x6b, 0x59, 0x02,
- 0xd9, 0x4e, 0xe8, 0x7a, 0x76, 0x1d, 0x02, 0x98,
- 0xfe, 0x8a, 0x87, 0x83, 0xa3, 0x4f, 0x56, 0x8a,
- 0xb8, 0x9e, 0x8e, 0x5c, 0x57, 0xd3, 0xa0, 0x79,
- 0xfa, 0x02 },
+ "compression algorithm. This document defines the application of "
+ "the DEFLATE algorithm to the IP Payload Compression Protocol.",
+ .output = "\x5d\x8d\x31\x0e\xc2\x30\x10\x04"
+ "\xbf\xb2\x2f\xc8\x1f\x10\x04\x09"
+ "\x89\xc2\x85\x3f\x70\xb1\x2f\xf8"
+ "\x24\xdb\x67\xd9\x47\xc1\xef\x49"
+ "\x68\x12\x51\xae\x76\x67\xd6\x27"
+ "\x19\x88\x1a\xde\x85\xab\x21\xf2"
+ "\x08\x5d\x16\x1e\x20\x04\x2d\xad"
+ "\xf3\x18\xa2\x15\x85\x2d\x69\xc4"
+ "\x42\x83\x23\xb6\x6c\x89\x71\x9b"
+ "\xef\xcf\x8b\x9f\xcf\x33\xca\x2f"
+ "\xed\x62\xa9\x4c\x80\xff\x13\xaf"
+ "\x52\x37\xed\x0e\x52\x6b\x59\x02"
+ "\xd9\x4e\xe8\x7a\x76\x1d\x02\x98"
+ "\xfe\x8a\x87\x83\xa3\x4f\x56\x8a"
+ "\xb8\x9e\x8e\x5c\x57\xd3\xa0\x79"
+ "\xfa\x02",
},
};
{
.inlen = 122,
.outlen = 191,
- .input = { 0x5d, 0x8d, 0x31, 0x0e, 0xc2, 0x30, 0x10, 0x04,
- 0xbf, 0xb2, 0x2f, 0xc8, 0x1f, 0x10, 0x04, 0x09,
- 0x89, 0xc2, 0x85, 0x3f, 0x70, 0xb1, 0x2f, 0xf8,
- 0x24, 0xdb, 0x67, 0xd9, 0x47, 0xc1, 0xef, 0x49,
- 0x68, 0x12, 0x51, 0xae, 0x76, 0x67, 0xd6, 0x27,
- 0x19, 0x88, 0x1a, 0xde, 0x85, 0xab, 0x21, 0xf2,
- 0x08, 0x5d, 0x16, 0x1e, 0x20, 0x04, 0x2d, 0xad,
- 0xf3, 0x18, 0xa2, 0x15, 0x85, 0x2d, 0x69, 0xc4,
- 0x42, 0x83, 0x23, 0xb6, 0x6c, 0x89, 0x71, 0x9b,
- 0xef, 0xcf, 0x8b, 0x9f, 0xcf, 0x33, 0xca, 0x2f,
- 0xed, 0x62, 0xa9, 0x4c, 0x80, 0xff, 0x13, 0xaf,
- 0x52, 0x37, 0xed, 0x0e, 0x52, 0x6b, 0x59, 0x02,
- 0xd9, 0x4e, 0xe8, 0x7a, 0x76, 0x1d, 0x02, 0x98,
- 0xfe, 0x8a, 0x87, 0x83, 0xa3, 0x4f, 0x56, 0x8a,
- 0xb8, 0x9e, 0x8e, 0x5c, 0x57, 0xd3, 0xa0, 0x79,
- 0xfa, 0x02 },
+ .input = "\x5d\x8d\x31\x0e\xc2\x30\x10\x04"
+ "\xbf\xb2\x2f\xc8\x1f\x10\x04\x09"
+ "\x89\xc2\x85\x3f\x70\xb1\x2f\xf8"
+ "\x24\xdb\x67\xd9\x47\xc1\xef\x49"
+ "\x68\x12\x51\xae\x76\x67\xd6\x27"
+ "\x19\x88\x1a\xde\x85\xab\x21\xf2"
+ "\x08\x5d\x16\x1e\x20\x04\x2d\xad"
+ "\xf3\x18\xa2\x15\x85\x2d\x69\xc4"
+ "\x42\x83\x23\xb6\x6c\x89\x71\x9b"
+ "\xef\xcf\x8b\x9f\xcf\x33\xca\x2f"
+ "\xed\x62\xa9\x4c\x80\xff\x13\xaf"
+ "\x52\x37\xed\x0e\x52\x6b\x59\x02"
+ "\xd9\x4e\xe8\x7a\x76\x1d\x02\x98"
+ "\xfe\x8a\x87\x83\xa3\x4f\x56\x8a"
+ "\xb8\x9e\x8e\x5c\x57\xd3\xa0\x79"
+ "\xfa\x02",
.output = "This document describes a compression method based on the DEFLATE"
- "compression algorithm. This document defines the application of "
- "the DEFLATE algorithm to the IP Payload Compression Protocol.",
+ "compression algorithm. This document defines the application of "
+ "the DEFLATE algorithm to the IP Payload Compression Protocol.",
}, {
.inlen = 38,
.outlen = 70,
- .input = { 0xf3, 0xca, 0xcf, 0xcc, 0x53, 0x28, 0x2d, 0x56,
- 0xc8, 0xcb, 0x2f, 0x57, 0x48, 0xcc, 0x4b, 0x51,
- 0x28, 0xce, 0x48, 0x2c, 0x4a, 0x55, 0x28, 0xc9,
- 0x48, 0x55, 0x28, 0xce, 0x4f, 0x2b, 0x29, 0x07,
- 0x71, 0xbc, 0x08, 0x2b, 0x01, 0x00 },
+ .input = "\xf3\xca\xcf\xcc\x53\x28\x2d\x56"
+ "\xc8\xcb\x2f\x57\x48\xcc\x4b\x51"
+ "\x28\xce\x48\x2c\x4a\x55\x28\xc9"
+ "\x48\x55\x28\xce\x4f\x2b\x29\x07"
+ "\x71\xbc\x08\x2b\x01\x00",
.output = "Join us now and share the software "
- "Join us now and share the software ",
+ "Join us now and share the software ",
},
};
.inlen = 70,
.outlen = 46,
.input = "Join us now and share the software "
- "Join us now and share the software ",
- .output = { 0x00, 0x0d, 0x4a, 0x6f, 0x69, 0x6e, 0x20, 0x75,
- 0x73, 0x20, 0x6e, 0x6f, 0x77, 0x20, 0x61, 0x6e,
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- 0x3d, 0x88, 0x00, 0x11, 0x00, 0x00 },
+ "Join us now and share the software ",
+ .output = "\x00\x0d\x4a\x6f\x69\x6e\x20\x75"
+ "\x73\x20\x6e\x6f\x77\x20\x61\x6e"
+ "\x64\x20\x73\x68\x61\x72\x65\x20"
+ "\x74\x68\x65\x20\x73\x6f\x66\x74"
+ "\x77\x70\x01\x01\x4a\x6f\x69\x6e"
+ "\x3d\x88\x00\x11\x00\x00",
}, {
.inlen = 159,
.outlen = 133,
.input = "This document describes a compression method based on the LZO "
- "compression algorithm. This document defines the application of "
- "the LZO algorithm used in UBIFS.",
- .output = { 0x00, 0x2b, 0x54, 0x68, 0x69, 0x73, 0x20, 0x64,
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- 0x20, 0x69, 0x6e, 0x20, 0x55, 0x42, 0x49, 0x46,
- 0x53, 0x2e, 0x11, 0x00, 0x00 },
+ "compression algorithm. This document defines the application of "
+ "the LZO algorithm used in UBIFS.",
+ .output = "\x00\x2b\x54\x68\x69\x73\x20\x64"
+ "\x6f\x63\x75\x6d\x65\x6e\x74\x20"
+ "\x64\x65\x73\x63\x72\x69\x62\x65"
+ "\x73\x20\x61\x20\x63\x6f\x6d\x70"
+ "\x72\x65\x73\x73\x69\x6f\x6e\x20"
+ "\x6d\x65\x74\x68\x6f\x64\x20\x62"
+ "\x61\x73\x65\x64\x20\x6f\x6e\x20"
+ "\x74\x68\x65\x20\x4c\x5a\x4f\x2b"
+ "\x8c\x00\x0d\x61\x6c\x67\x6f\x72"
+ "\x69\x74\x68\x6d\x2e\x20\x20\x54"
+ "\x68\x69\x73\x2a\x54\x01\x02\x66"
+ "\x69\x6e\x65\x73\x94\x06\x05\x61"
+ "\x70\x70\x6c\x69\x63\x61\x74\x76"
+ "\x0a\x6f\x66\x88\x02\x60\x09\x27"
+ "\xf0\x00\x0c\x20\x75\x73\x65\x64"
+ "\x20\x69\x6e\x20\x55\x42\x49\x46"
+ "\x53\x2e\x11\x00\x00",
},
};
{
.inlen = 133,
.outlen = 159,
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- 0x53, 0x2e, 0x11, 0x00, 0x00 },
+ .input = "\x00\x2b\x54\x68\x69\x73\x20\x64"
+ "\x6f\x63\x75\x6d\x65\x6e\x74\x20"
+ "\x64\x65\x73\x63\x72\x69\x62\x65"
+ "\x73\x20\x61\x20\x63\x6f\x6d\x70"
+ "\x72\x65\x73\x73\x69\x6f\x6e\x20"
+ "\x6d\x65\x74\x68\x6f\x64\x20\x62"
+ "\x61\x73\x65\x64\x20\x6f\x6e\x20"
+ "\x74\x68\x65\x20\x4c\x5a\x4f\x2b"
+ "\x8c\x00\x0d\x61\x6c\x67\x6f\x72"
+ "\x69\x74\x68\x6d\x2e\x20\x20\x54"
+ "\x68\x69\x73\x2a\x54\x01\x02\x66"
+ "\x69\x6e\x65\x73\x94\x06\x05\x61"
+ "\x70\x70\x6c\x69\x63\x61\x74\x76"
+ "\x0a\x6f\x66\x88\x02\x60\x09\x27"
+ "\xf0\x00\x0c\x20\x75\x73\x65\x64"
+ "\x20\x69\x6e\x20\x55\x42\x49\x46"
+ "\x53\x2e\x11\x00\x00",
.output = "This document describes a compression method based on the LZO "
- "compression algorithm. This document defines the application of "
- "the LZO algorithm used in UBIFS.",
+ "compression algorithm. This document defines the application of "
+ "the LZO algorithm used in UBIFS.",
}, {
.inlen = 46,
.outlen = 70,
- .input = { 0x00, 0x0d, 0x4a, 0x6f, 0x69, 0x6e, 0x20, 0x75,
- 0x73, 0x20, 0x6e, 0x6f, 0x77, 0x20, 0x61, 0x6e,
- 0x64, 0x20, 0x73, 0x68, 0x61, 0x72, 0x65, 0x20,
- 0x74, 0x68, 0x65, 0x20, 0x73, 0x6f, 0x66, 0x74,
- 0x77, 0x70, 0x01, 0x01, 0x4a, 0x6f, 0x69, 0x6e,
- 0x3d, 0x88, 0x00, 0x11, 0x00, 0x00 },
+ .input = "\x00\x0d\x4a\x6f\x69\x6e\x20\x75"
+ "\x73\x20\x6e\x6f\x77\x20\x61\x6e"
+ "\x64\x20\x73\x68\x61\x72\x65\x20"
+ "\x74\x68\x65\x20\x73\x6f\x66\x74"
+ "\x77\x70\x01\x01\x4a\x6f\x69\x6e"
+ "\x3d\x88\x00\x11\x00\x00",
.output = "Join us now and share the software "
- "Join us now and share the software ",
+ "Join us now and share the software ",
},
};
static struct hash_testvec michael_mic_tv_template[] = {
{
- .key = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .key = "\x00\x00\x00\x00\x00\x00\x00\x00",
.ksize = 8,
- .plaintext = { },
+ .plaintext = zeroed_string,
.psize = 0,
- .digest = { 0x82, 0x92, 0x5c, 0x1c, 0xa1, 0xd1, 0x30, 0xb8 }
+ .digest = "\x82\x92\x5c\x1c\xa1\xd1\x30\xb8",
},
{
- .key = { 0x82, 0x92, 0x5c, 0x1c, 0xa1, 0xd1, 0x30, 0xb8 },
+ .key = "\x82\x92\x5c\x1c\xa1\xd1\x30\xb8",
.ksize = 8,
- .plaintext = { 'M' },
+ .plaintext = "M",
.psize = 1,
- .digest = { 0x43, 0x47, 0x21, 0xca, 0x40, 0x63, 0x9b, 0x3f }
+ .digest = "\x43\x47\x21\xca\x40\x63\x9b\x3f",
},
{
- .key = { 0x43, 0x47, 0x21, 0xca, 0x40, 0x63, 0x9b, 0x3f },
+ .key = "\x43\x47\x21\xca\x40\x63\x9b\x3f",
.ksize = 8,
- .plaintext = { 'M', 'i' },
+ .plaintext = "Mi",
.psize = 2,
- .digest = { 0xe8, 0xf9, 0xbe, 0xca, 0xe9, 0x7e, 0x5d, 0x29 }
+ .digest = "\xe8\xf9\xbe\xca\xe9\x7e\x5d\x29",
},
{
- .key = { 0xe8, 0xf9, 0xbe, 0xca, 0xe9, 0x7e, 0x5d, 0x29 },
+ .key = "\xe8\xf9\xbe\xca\xe9\x7e\x5d\x29",
.ksize = 8,
- .plaintext = { 'M', 'i', 'c' },
+ .plaintext = "Mic",
.psize = 3,
- .digest = { 0x90, 0x03, 0x8f, 0xc6, 0xcf, 0x13, 0xc1, 0xdb }
+ .digest = "\x90\x03\x8f\xc6\xcf\x13\xc1\xdb",
},
{
- .key = { 0x90, 0x03, 0x8f, 0xc6, 0xcf, 0x13, 0xc1, 0xdb },
+ .key = "\x90\x03\x8f\xc6\xcf\x13\xc1\xdb",
.ksize = 8,
- .plaintext = { 'M', 'i', 'c', 'h' },
+ .plaintext = "Mich",
.psize = 4,
- .digest = { 0xd5, 0x5e, 0x10, 0x05, 0x10, 0x12, 0x89, 0x86 }
+ .digest = "\xd5\x5e\x10\x05\x10\x12\x89\x86",
},
{
- .key = { 0xd5, 0x5e, 0x10, 0x05, 0x10, 0x12, 0x89, 0x86 },
+ .key = "\xd5\x5e\x10\x05\x10\x12\x89\x86",
.ksize = 8,
- .plaintext = { 'M', 'i', 'c', 'h', 'a', 'e', 'l' },
+ .plaintext = "Michael",
.psize = 7,
- .digest = { 0x0a, 0x94, 0x2b, 0x12, 0x4e, 0xca, 0xa5, 0x46 },
+ .digest = "\x0a\x94\x2b\x12\x4e\xca\xa5\x46",
}
};
static struct hash_testvec crc32c_tv_template[] = {
{
.psize = 0,
- .digest = { 0x00, 0x00, 0x00, 0x00 }
+ .digest = "\x00\x00\x00\x00",
},
{
- .key = { 0x87, 0xa9, 0xcb, 0xed },
+ .key = "\x87\xa9\xcb\xed",
.ksize = 4,
.psize = 0,
- .digest = { 0x78, 0x56, 0x34, 0x12 },
+ .digest = "\x78\x56\x34\x12",
},
{
- .key = { 0xff, 0xff, 0xff, 0xff },
+ .key = "\xff\xff\xff\xff",
.ksize = 4,
- .plaintext = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
- 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
- 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
- 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20,
- 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28 },
+ .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18"
+ "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
+ "\x21\x22\x23\x24\x25\x26\x27\x28",
.psize = 40,
- .digest = { 0x7f, 0x15, 0x2c, 0x0e }
+ .digest = "\x7f\x15\x2c\x0e",
},
{
- .key = { 0xff, 0xff, 0xff, 0xff },
+ .key = "\xff\xff\xff\xff",
.ksize = 4,
- .plaintext = { 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30,
- 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38,
- 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40,
- 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
- 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50 },
+ .plaintext = "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30"
+ "\x31\x32\x33\x34\x35\x36\x37\x38"
+ "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40"
+ "\x41\x42\x43\x44\x45\x46\x47\x48"
+ "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50",
.psize = 40,
- .digest = { 0xf6, 0xeb, 0x80, 0xe9 }
+ .digest = "\xf6\xeb\x80\xe9",
},
{
- .key = { 0xff, 0xff, 0xff, 0xff },
+ .key = "\xff\xff\xff\xff",
.ksize = 4,
- .plaintext = { 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
- 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60,
- 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
- 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
- 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78 },
+ .plaintext = "\x51\x52\x53\x54\x55\x56\x57\x58"
+ "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60"
+ "\x61\x62\x63\x64\x65\x66\x67\x68"
+ "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70"
+ "\x71\x72\x73\x74\x75\x76\x77\x78",
.psize = 40,
- .digest = { 0xed, 0xbd, 0x74, 0xde }
+ .digest = "\xed\xbd\x74\xde",
},
{
- .key = { 0xff, 0xff, 0xff, 0xff },
+ .key = "\xff\xff\xff\xff",
.ksize = 4,
- .plaintext = { 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 0x80,
- 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88,
- 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90,
- 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
- 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0 },
+ .plaintext = "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80"
+ "\x81\x82\x83\x84\x85\x86\x87\x88"
+ "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90"
+ "\x91\x92\x93\x94\x95\x96\x97\x98"
+ "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0",
.psize = 40,
- .digest = { 0x62, 0xc8, 0x79, 0xd5 }
+ .digest = "\x62\xc8\x79\xd5",
},
{
- .key = { 0xff, 0xff, 0xff, 0xff },
+ .key = "\xff\xff\xff\xff",
.ksize = 4,
- .plaintext = { 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8,
- 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0,
- 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8,
- 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0,
- 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8 },
+ .plaintext = "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8"
+ "\xa9\xaa\xab\xac\xad\xae\xaf\xb0"
+ "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8"
+ "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0"
+ "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8",
.psize = 40,
- .digest = { 0xd0, 0x9a, 0x97, 0xba }
+ .digest = "\xd0\x9a\x97\xba",
},
{
- .key = { 0xff, 0xff, 0xff, 0xff },
+ .key = "\xff\xff\xff\xff",
.ksize = 4,
- .plaintext = { 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0,
- 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8,
- 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 0xe0,
- 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8,
- 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xf0 },
+ .plaintext = "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0"
+ "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8"
+ "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0"
+ "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8"
+ "\xe9\xea\xeb\xec\xed\xee\xef\xf0",
.psize = 40,
- .digest = { 0x13, 0xd9, 0x29, 0x2b }
+ .digest = "\x13\xd9\x29\x2b",
},
{
- .key = { 0x80, 0xea, 0xd3, 0xf1 },
+ .key = "\x80\xea\xd3\xf1",
.ksize = 4,
- .plaintext = { 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30,
- 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38,
- 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40,
- 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
- 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50 },
+ .plaintext = "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30"
+ "\x31\x32\x33\x34\x35\x36\x37\x38"
+ "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40"
+ "\x41\x42\x43\x44\x45\x46\x47\x48"
+ "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50",
.psize = 40,
- .digest = { 0x0c, 0xb5, 0xe2, 0xa2 }
+ .digest = "\x0c\xb5\xe2\xa2",
},
{
- .key = { 0xf3, 0x4a, 0x1d, 0x5d },
+ .key = "\xf3\x4a\x1d\x5d",
.ksize = 4,
- .plaintext = { 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
- 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60,
- 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
- 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
- 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78 },
+ .plaintext = "\x51\x52\x53\x54\x55\x56\x57\x58"
+ "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60"
+ "\x61\x62\x63\x64\x65\x66\x67\x68"
+ "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70"
+ "\x71\x72\x73\x74\x75\x76\x77\x78",
.psize = 40,
- .digest = { 0xd1, 0x7f, 0xfb, 0xa6 }
+ .digest = "\xd1\x7f\xfb\xa6",
},
{
- .key = { 0x2e, 0x80, 0x04, 0x59 },
+ .key = "\x2e\x80\x04\x59",
.ksize = 4,
- .plaintext = { 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 0x80,
- 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88,
- 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90,
- 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
- 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0 },
+ .plaintext = "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80"
+ "\x81\x82\x83\x84\x85\x86\x87\x88"
+ "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90"
+ "\x91\x92\x93\x94\x95\x96\x97\x98"
+ "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0",
.psize = 40,
- .digest = { 0x59, 0x33, 0xe6, 0x7a }
+ .digest = "\x59\x33\xe6\x7a",
},
{
- .key = { 0xa6, 0xcc, 0x19, 0x85 },
+ .key = "\xa6\xcc\x19\x85",
.ksize = 4,
- .plaintext = { 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8,
- 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0,
- 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8,
- 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0,
- 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8 },
+ .plaintext = "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8"
+ "\xa9\xaa\xab\xac\xad\xae\xaf\xb0"
+ "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8"
+ "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0"
+ "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8",
.psize = 40,
- .digest = { 0xbe, 0x03, 0x01, 0xd2 }
+ .digest = "\xbe\x03\x01\xd2",
},
{
- .key = { 0x41, 0xfc, 0xfe, 0x2d },
+ .key = "\x41\xfc\xfe\x2d",
.ksize = 4,
- .plaintext = { 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0,
- 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8,
- 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 0xe0,
- 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8,
- 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xf0 },
+ .plaintext = "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0"
+ "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8"
+ "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0"
+ "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8"
+ "\xe9\xea\xeb\xec\xed\xee\xef\xf0",
.psize = 40,
- .digest = { 0x75, 0xd3, 0xc5, 0x24 }
+ .digest = "\x75\xd3\xc5\x24",
},
{
- .key = { 0xff, 0xff, 0xff, 0xff },
+ .key = "\xff\xff\xff\xff",
.ksize = 4,
- .plaintext = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
- 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
- 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
- 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20,
- 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28,
- 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30,
- 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38,
- 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40,
- 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
- 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50,
- 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
- 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60,
- 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
- 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
- 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
- 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 0x80,
- 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88,
- 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90,
- 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
- 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0,
- 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8,
- 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0,
- 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8,
- 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0,
- 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8,
- 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0,
- 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8,
- 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 0xe0,
- 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8,
- 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xf0 },
+ .plaintext = "\x01\x02\x03\x04\x05\x06\x07\x08"
+ "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+ "\x11\x12\x13\x14\x15\x16\x17\x18"
+ "\x19\x1a\x1b\x1c\x1d\x1e\x1f\x20"
+ "\x21\x22\x23\x24\x25\x26\x27\x28"
+ "\x29\x2a\x2b\x2c\x2d\x2e\x2f\x30"
+ "\x31\x32\x33\x34\x35\x36\x37\x38"
+ "\x39\x3a\x3b\x3c\x3d\x3e\x3f\x40"
+ "\x41\x42\x43\x44\x45\x46\x47\x48"
+ "\x49\x4a\x4b\x4c\x4d\x4e\x4f\x50"
+ "\x51\x52\x53\x54\x55\x56\x57\x58"
+ "\x59\x5a\x5b\x5c\x5d\x5e\x5f\x60"
+ "\x61\x62\x63\x64\x65\x66\x67\x68"
+ "\x69\x6a\x6b\x6c\x6d\x6e\x6f\x70"
+ "\x71\x72\x73\x74\x75\x76\x77\x78"
+ "\x79\x7a\x7b\x7c\x7d\x7e\x7f\x80"
+ "\x81\x82\x83\x84\x85\x86\x87\x88"
+ "\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90"
+ "\x91\x92\x93\x94\x95\x96\x97\x98"
+ "\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0"
+ "\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8"
+ "\xa9\xaa\xab\xac\xad\xae\xaf\xb0"
+ "\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8"
+ "\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0"
+ "\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8"
+ "\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0"
+ "\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8"
+ "\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0"
+ "\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8"
+ "\xe9\xea\xeb\xec\xed\xee\xef\xf0",
.psize = 240,
- .digest = { 0x75, 0xd3, 0xc5, 0x24 },
+ .digest = "\x75\xd3\xc5\x24",
.np = 2,
.tap = { 31, 209 }
},
/*
* Cipher speed tests
*/
-static struct cipher_speed aes_speed_template[] = {
- { .klen = 16, .blen = 16, },
- { .klen = 16, .blen = 64, },
- { .klen = 16, .blen = 256, },
- { .klen = 16, .blen = 1024, },
- { .klen = 16, .blen = 8192, },
- { .klen = 24, .blen = 16, },
- { .klen = 24, .blen = 64, },
- { .klen = 24, .blen = 256, },
- { .klen = 24, .blen = 1024, },
- { .klen = 24, .blen = 8192, },
- { .klen = 32, .blen = 16, },
- { .klen = 32, .blen = 64, },
- { .klen = 32, .blen = 256, },
- { .klen = 32, .blen = 1024, },
- { .klen = 32, .blen = 8192, },
-
- /* End marker */
- { .klen = 0, .blen = 0, }
-};
-
-static struct cipher_speed aes_lrw_speed_template[] = {
- { .klen = 32, .blen = 16, },
- { .klen = 32, .blen = 64, },
- { .klen = 32, .blen = 256, },
- { .klen = 32, .blen = 1024, },
- { .klen = 32, .blen = 8192, },
- { .klen = 40, .blen = 16, },
- { .klen = 40, .blen = 64, },
- { .klen = 40, .blen = 256, },
- { .klen = 40, .blen = 1024, },
- { .klen = 40, .blen = 8192, },
- { .klen = 48, .blen = 16, },
- { .klen = 48, .blen = 64, },
- { .klen = 48, .blen = 256, },
- { .klen = 48, .blen = 1024, },
- { .klen = 48, .blen = 8192, },
-
- /* End marker */
- { .klen = 0, .blen = 0, }
-};
-
-static struct cipher_speed aes_xts_speed_template[] = {
- { .klen = 32, .blen = 16, },
- { .klen = 32, .blen = 64, },
- { .klen = 32, .blen = 256, },
- { .klen = 32, .blen = 1024, },
- { .klen = 32, .blen = 8192, },
- { .klen = 48, .blen = 16, },
- { .klen = 48, .blen = 64, },
- { .klen = 48, .blen = 256, },
- { .klen = 48, .blen = 1024, },
- { .klen = 48, .blen = 8192, },
- { .klen = 64, .blen = 16, },
- { .klen = 64, .blen = 64, },
- { .klen = 64, .blen = 256, },
- { .klen = 64, .blen = 1024, },
- { .klen = 64, .blen = 8192, },
-
- /* End marker */
- { .klen = 0, .blen = 0, }
-};
-
-static struct cipher_speed des3_ede_speed_template[] = {
- { .klen = 24, .blen = 16, },
- { .klen = 24, .blen = 64, },
- { .klen = 24, .blen = 256, },
- { .klen = 24, .blen = 1024, },
- { .klen = 24, .blen = 8192, },
-
- /* End marker */
- { .klen = 0, .blen = 0, }
-};
-
-static struct cipher_speed twofish_speed_template[] = {
- { .klen = 16, .blen = 16, },
- { .klen = 16, .blen = 64, },
- { .klen = 16, .blen = 256, },
- { .klen = 16, .blen = 1024, },
- { .klen = 16, .blen = 8192, },
- { .klen = 24, .blen = 16, },
- { .klen = 24, .blen = 64, },
- { .klen = 24, .blen = 256, },
- { .klen = 24, .blen = 1024, },
- { .klen = 24, .blen = 8192, },
- { .klen = 32, .blen = 16, },
- { .klen = 32, .blen = 64, },
- { .klen = 32, .blen = 256, },
- { .klen = 32, .blen = 1024, },
- { .klen = 32, .blen = 8192, },
-
- /* End marker */
- { .klen = 0, .blen = 0, }
-};
-
-static struct cipher_speed blowfish_speed_template[] = {
- /* Don't support blowfish keys > 256 bit in this test */
- { .klen = 8, .blen = 16, },
- { .klen = 8, .blen = 64, },
- { .klen = 8, .blen = 256, },
- { .klen = 8, .blen = 1024, },
- { .klen = 8, .blen = 8192, },
- { .klen = 32, .blen = 16, },
- { .klen = 32, .blen = 64, },
- { .klen = 32, .blen = 256, },
- { .klen = 32, .blen = 1024, },
- { .klen = 32, .blen = 8192, },
-
- /* End marker */
- { .klen = 0, .blen = 0, }
-};
-
-static struct cipher_speed des_speed_template[] = {
- { .klen = 8, .blen = 16, },
- { .klen = 8, .blen = 64, },
- { .klen = 8, .blen = 256, },
- { .klen = 8, .blen = 1024, },
- { .klen = 8, .blen = 8192, },
-
- /* End marker */
- { .klen = 0, .blen = 0, }
-};
+static u8 speed_template_8[] = {8, 0};
+static u8 speed_template_24[] = {24, 0};
+static u8 speed_template_8_32[] = {8, 32, 0};
+static u8 speed_template_16_32[] = {16, 32, 0};
+static u8 speed_template_16_24_32[] = {16, 24, 32, 0};
+static u8 speed_template_32_40_48[] = {32, 40, 48, 0};
+static u8 speed_template_32_48_64[] = {32, 48, 64, 0};
/*
* Digest speed tests
*/
static struct hash_speed generic_hash_speed_template[] = {
- { .blen = 16, .plen = 16, },
+ { .blen = 16, .plen = 16, },
{ .blen = 64, .plen = 16, },
{ .blen = 64, .plen = 64, },
{ .blen = 256, .plen = 16, },
{ .blen = 0, .plen = 0, }
};
-static struct cipher_speed camellia_speed_template[] = {
- { .klen = 16, .blen = 16, },
- { .klen = 16, .blen = 64, },
- { .klen = 16, .blen = 256, },
- { .klen = 16, .blen = 1024, },
- { .klen = 16, .blen = 8192, },
- { .klen = 24, .blen = 16, },
- { .klen = 24, .blen = 64, },
- { .klen = 24, .blen = 256, },
- { .klen = 24, .blen = 1024, },
- { .klen = 24, .blen = 8192, },
- { .klen = 32, .blen = 16, },
- { .klen = 32, .blen = 64, },
- { .klen = 32, .blen = 256, },
- { .klen = 32, .blen = 1024, },
- { .klen = 32, .blen = 8192, },
-
- /* End marker */
- { .klen = 0, .blen = 0, }
-};
-
-static struct cipher_speed salsa20_speed_template[] = {
- { .klen = 16, .blen = 16, },
- { .klen = 16, .blen = 64, },
- { .klen = 16, .blen = 256, },
- { .klen = 16, .blen = 1024, },
- { .klen = 16, .blen = 8192, },
- { .klen = 32, .blen = 16, },
- { .klen = 32, .blen = 64, },
- { .klen = 32, .blen = 256, },
- { .klen = 32, .blen = 1024, },
- { .klen = 32, .blen = 8192, },
-
- /* End marker */
- { .klen = 0, .blen = 0, }
-};
-
#endif /* _CRYPTO_TCRYPT_H */
.cia_decrypt = xeta_decrypt } }
};
-static int __init init(void)
+static int __init tea_mod_init(void)
{
int ret = 0;
return ret;
}
-static void __exit fini(void)
+static void __exit tea_mod_fini(void)
{
crypto_unregister_alg(&tea_alg);
crypto_unregister_alg(&xtea_alg);
MODULE_ALIAS("xtea");
MODULE_ALIAS("xeta");
-module_init(init);
-module_exit(fini);
+module_init(tea_mod_init);
+module_exit(tea_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("TEA, XTEA & XETA Cryptographic Algorithms");
.dia_final = tgr128_final}}
};
-static int __init init(void)
+static int __init tgr192_mod_init(void)
{
int ret = 0;
return ret;
}
-static void __exit fini(void)
+static void __exit tgr192_mod_fini(void)
{
crypto_unregister_alg(&tgr192);
crypto_unregister_alg(&tgr160);
MODULE_ALIAS("tgr160");
MODULE_ALIAS("tgr128");
-module_init(init);
-module_exit(fini);
+module_init(tgr192_mod_init);
+module_exit(tgr192_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Tiger Message Digest Algorithm");
.cia_decrypt = twofish_decrypt } }
};
-static int __init init(void)
+static int __init twofish_mod_init(void)
{
return crypto_register_alg(&alg);
}
-static void __exit fini(void)
+static void __exit twofish_mod_fini(void)
{
crypto_unregister_alg(&alg);
}
-module_init(init);
-module_exit(fini);
+module_init(twofish_mod_init);
+module_exit(twofish_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION ("Twofish Cipher Algorithm");
.dia_final = wp256_final } }
};
-static int __init init(void)
+static int __init wp512_mod_init(void)
{
int ret = 0;
return ret;
}
-static void __exit fini(void)
+static void __exit wp512_mod_fini(void)
{
crypto_unregister_alg(&wp512);
crypto_unregister_alg(&wp384);
MODULE_ALIAS("wp384");
MODULE_ALIAS("wp256");
-module_init(init);
-module_exit(fini);
+module_init(wp512_mod_init);
+module_exit(wp512_mod_fini);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Whirlpool Message Digest Algorithm");
static int acpi_ac_remove(struct acpi_device *device, int type);
static int acpi_ac_resume(struct acpi_device *device);
-const static struct acpi_device_id ac_device_ids[] = {
+static const struct acpi_device_id ac_device_ids[] = {
{"ACPI0003", 0},
{"", 0},
};
* Migrate task to the cpu pointed by pr.
*/
saved_mask = current->cpus_allowed;
- set_cpus_allowed(current, cpumask_of_cpu(pr->id));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(pr->id));
ret = pr->throttling.acpi_processor_get_throttling(pr);
/* restore the previous state */
- set_cpus_allowed(current, saved_mask);
+ set_cpus_allowed_ptr(current, &saved_mask);
return ret;
}
* it can be called only for the cpu pointed by pr.
*/
if (p_throttling->shared_type == DOMAIN_COORD_TYPE_SW_ANY) {
- set_cpus_allowed(current, cpumask_of_cpu(pr->id));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(pr->id));
ret = p_throttling->acpi_processor_set_throttling(pr,
t_state.target_state);
} else {
continue;
}
t_state.cpu = i;
- set_cpus_allowed(current, cpumask_of_cpu(i));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(i));
ret = match_pr->throttling.
acpi_processor_set_throttling(
match_pr, t_state.target_state);
&t_state);
}
/* restore the previous state */
- set_cpus_allowed(current, saved_mask);
+ set_cpus_allowed_ptr(current, &saved_mask);
return ret;
}
static int ahci_pci_device_resume(struct pci_dev *pdev);
#endif
-static struct class_device_attribute *ahci_shost_attrs[] = {
- &class_device_attr_link_power_management_policy,
+static struct device_attribute *ahci_shost_attrs[] = {
+ &dev_attr_link_power_management_policy,
NULL
};
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
-#include <asm/semaphore.h>
#include <asm/byteorder.h>
#include <linux/cdrom.h>
return NULL;
}
-static ssize_t ata_scsi_lpm_put(struct class_device *class_dev,
- const char *buf, size_t count)
+static ssize_t ata_scsi_lpm_put(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ata_port *ap = ata_shost_to_port(shost);
enum link_pm policy = 0;
int i;
}
static ssize_t
-ata_scsi_lpm_show(struct class_device *class_dev, char *buf)
+ata_scsi_lpm_show(struct device *dev, struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ata_port *ap = ata_shost_to_port(shost);
const char *policy =
ata_scsi_lpm_get(ap->pm_policy);
return snprintf(buf, 23, "%s\n", policy);
}
-CLASS_DEVICE_ATTR(link_power_management_policy, S_IRUGO | S_IWUSR,
+DEVICE_ATTR(link_power_management_policy, S_IRUGO | S_IWUSR,
ata_scsi_lpm_show, ata_scsi_lpm_put);
-EXPORT_SYMBOL_GPL(class_device_attr_link_power_management_policy);
+EXPORT_SYMBOL_GPL(dev_attr_link_power_management_policy);
static void ata_scsi_invalid_field(struct scsi_cmnd *cmd,
void (*done)(struct scsi_cmnd *))
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
+#include <linux/mbus.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
+#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
+#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
+
enum {
/* DMA boundary 0xffff is required by the s/g splitting
* we need on /length/ in mv_fill-sg().
return 0;
}
+static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
+ struct mbus_dram_target_info *dram)
+{
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ writel(0, hpriv->base + WINDOW_CTRL(i));
+ writel(0, hpriv->base + WINDOW_BASE(i));
+ }
+
+ for (i = 0; i < dram->num_cs; i++) {
+ struct mbus_dram_window *cs = dram->cs + i;
+
+ writel(((cs->size - 1) & 0xffff0000) |
+ (cs->mbus_attr << 8) |
+ (dram->mbus_dram_target_id << 4) | 1,
+ hpriv->base + WINDOW_CTRL(i));
+ writel(cs->base, hpriv->base + WINDOW_BASE(i));
+ }
+}
+
/**
* mv_platform_probe - handle a positive probe of an soc Marvell
* host
res->end - res->start + 1);
hpriv->base -= MV_SATAHC0_REG_BASE;
+ /*
+ * (Re-)program MBUS remapping windows if we are asked to.
+ */
+ if (mv_platform_data->dram != NULL)
+ mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
+
rc = mv_create_dma_pools(hpriv, &pdev->dev);
if (rc)
return rc;
struct internal_container {
struct klist_node node;
struct attribute_container *cont;
- struct class_device classdev;
+ struct device classdev;
};
static void internal_container_klist_get(struct klist_node *n)
{
struct internal_container *ic =
container_of(n, struct internal_container, node);
- class_device_get(&ic->classdev);
+ get_device(&ic->classdev);
}
static void internal_container_klist_put(struct klist_node *n)
{
struct internal_container *ic =
container_of(n, struct internal_container, node);
- class_device_put(&ic->classdev);
+ put_device(&ic->classdev);
}
* Returns the container associated with this classdev.
*/
struct attribute_container *
-attribute_container_classdev_to_container(struct class_device *classdev)
+attribute_container_classdev_to_container(struct device *classdev)
{
struct internal_container *ic =
container_of(classdev, struct internal_container, classdev);
EXPORT_SYMBOL_GPL(attribute_container_unregister);
/* private function used as class release */
-static void attribute_container_release(struct class_device *classdev)
+static void attribute_container_release(struct device *classdev)
{
struct internal_container *ic
= container_of(classdev, struct internal_container, classdev);
- struct device *dev = classdev->dev;
+ struct device *dev = classdev->parent;
kfree(ic);
put_device(dev);
* This function allocates storage for the class device(s) to be
* attached to dev (one for each matching attribute_container). If no
* fn is provided, the code will simply register the class device via
- * class_device_add. If a function is provided, it is expected to add
+ * device_add. If a function is provided, it is expected to add
* the class device at the appropriate time. One of the things that
* might be necessary is to allocate and initialise the classdev and
* then add it a later time. To do this, call this routine for
* allocation and initialisation and then use
- * attribute_container_device_trigger() to call class_device_add() on
+ * attribute_container_device_trigger() to call device_add() on
* it. Note: after this, the class device contains a reference to dev
* which is not relinquished until the release of the classdev.
*/
attribute_container_add_device(struct device *dev,
int (*fn)(struct attribute_container *,
struct device *,
- struct class_device *))
+ struct device *))
{
struct attribute_container *cont;
}
ic->cont = cont;
- class_device_initialize(&ic->classdev);
- ic->classdev.dev = get_device(dev);
+ device_initialize(&ic->classdev);
+ ic->classdev.parent = get_device(dev);
ic->classdev.class = cont->class;
- cont->class->release = attribute_container_release;
- strcpy(ic->classdev.class_id, dev->bus_id);
+ cont->class->dev_release = attribute_container_release;
+ strcpy(ic->classdev.bus_id, dev->bus_id);
if (fn)
fn(cont, dev, &ic->classdev);
else
* @fn: A function to call to remove the device
*
* This routine triggers device removal. If fn is NULL, then it is
- * simply done via class_device_unregister (note that if something
+ * simply done via device_unregister (note that if something
* still has a reference to the classdev, then the memory occupied
* will not be freed until the classdev is released). If you want a
* two phase release: remove from visibility and then delete the
* device, then you should use this routine with a fn that calls
- * class_device_del() and then use
- * attribute_container_device_trigger() to do the final put on the
- * classdev.
+ * device_del() and then use attribute_container_device_trigger()
+ * to do the final put on the classdev.
*/
void
attribute_container_remove_device(struct device *dev,
void (*fn)(struct attribute_container *,
struct device *,
- struct class_device *))
+ struct device *))
{
struct attribute_container *cont;
continue;
klist_for_each_entry(ic, &cont->containers, node, &iter) {
- if (dev != ic->classdev.dev)
+ if (dev != ic->classdev.parent)
continue;
klist_del(&ic->node);
if (fn)
fn(cont, dev, &ic->classdev);
else {
attribute_container_remove_attrs(&ic->classdev);
- class_device_unregister(&ic->classdev);
+ device_unregister(&ic->classdev);
}
}
}
attribute_container_device_trigger(struct device *dev,
int (*fn)(struct attribute_container *,
struct device *,
- struct class_device *))
+ struct device *))
{
struct attribute_container *cont;
}
klist_for_each_entry(ic, &cont->containers, node, &iter) {
- if (dev == ic->classdev.dev)
+ if (dev == ic->classdev.parent)
fn(cont, dev, &ic->classdev);
}
}
* attributes listed in the container
*/
int
-attribute_container_add_attrs(struct class_device *classdev)
+attribute_container_add_attrs(struct device *classdev)
{
struct attribute_container *cont =
attribute_container_classdev_to_container(classdev);
- struct class_device_attribute **attrs = cont->attrs;
+ struct device_attribute **attrs = cont->attrs;
int i, error;
BUG_ON(attrs && cont->grp);
return sysfs_create_group(&classdev->kobj, cont->grp);
for (i = 0; attrs[i]; i++) {
- error = class_device_create_file(classdev, attrs[i]);
+ error = device_create_file(classdev, attrs[i]);
if (error)
return error;
}
}
/**
- * attribute_container_add_class_device - same function as class_device_add
+ * attribute_container_add_class_device - same function as device_add
*
* @classdev: the class device to add
*
- * This performs essentially the same function as class_device_add except for
+ * This performs essentially the same function as device_add except for
* attribute containers, namely add the classdev to the system and then
* create the attribute files
*/
int
-attribute_container_add_class_device(struct class_device *classdev)
+attribute_container_add_class_device(struct device *classdev)
{
- int error = class_device_add(classdev);
+ int error = device_add(classdev);
if (error)
return error;
return attribute_container_add_attrs(classdev);
int
attribute_container_add_class_device_adapter(struct attribute_container *cont,
struct device *dev,
- struct class_device *classdev)
+ struct device *classdev)
{
return attribute_container_add_class_device(classdev);
}
*
*/
void
-attribute_container_remove_attrs(struct class_device *classdev)
+attribute_container_remove_attrs(struct device *classdev)
{
struct attribute_container *cont =
attribute_container_classdev_to_container(classdev);
- struct class_device_attribute **attrs = cont->attrs;
+ struct device_attribute **attrs = cont->attrs;
int i;
if (!attrs && !cont->grp)
}
for (i = 0; attrs[i]; i++)
- class_device_remove_file(classdev, attrs[i]);
+ device_remove_file(classdev, attrs[i]);
}
/**
* @classdev: the class device
*
* This function simply removes all the attribute files and then calls
- * class_device_del.
+ * device_del.
*/
void
-attribute_container_class_device_del(struct class_device *classdev)
+attribute_container_class_device_del(struct device *classdev)
{
attribute_container_remove_attrs(classdev);
- class_device_del(classdev);
+ device_del(classdev);
}
/**
* Looks up the device in the container's list of class devices and returns
* the corresponding class_device.
*/
-struct class_device *
+struct device *
attribute_container_find_class_device(struct attribute_container *cont,
struct device *dev)
{
- struct class_device *cdev = NULL;
+ struct device *cdev = NULL;
struct internal_container *ic;
struct klist_iter iter;
klist_for_each_entry(ic, &cont->containers, node, &iter) {
- if (ic->classdev.dev == dev) {
+ if (ic->classdev.parent == dev) {
cdev = &ic->classdev;
/* FIXME: must exit iterator then break */
klist_iter_exit(&iter);
{
struct driver_private *drv_priv = to_driver(kobj);
- pr_debug("driver: '%s': %s\n", kobject_name(kobj), __FUNCTION__);
+ pr_debug("driver: '%s': %s\n", kobject_name(kobj), __func__);
kfree(drv_priv);
}
int ret = 0;
if (bus) {
- dev->is_registered = 1;
if (bus->p->drivers_autoprobe)
ret = device_attach(dev);
WARN_ON(ret < 0);
if (ret >= 0)
klist_add_tail(&dev->knode_bus, &bus->p->klist_devices);
- else
- dev->is_registered = 0;
}
}
sysfs_remove_link(&dev->bus->p->devices_kset->kobj,
dev->bus_id);
device_remove_attrs(dev->bus, dev);
- if (dev->is_registered) {
- dev->is_registered = 0;
+ if (klist_node_attached(&dev->knode_bus))
klist_del(&dev->knode_bus);
- }
+
pr_debug("bus: '%s': remove device %s\n",
dev->bus->name, dev->bus_id);
device_release_driver(dev);
error = driver_create_file(drv, &driver_attr_uevent);
if (error) {
printk(KERN_ERR "%s: uevent attr (%s) failed\n",
- __FUNCTION__, drv->name);
+ __func__, drv->name);
}
error = driver_add_attrs(bus, drv);
if (error) {
/* How the hell do we get out of this pickle? Give up */
printk(KERN_ERR "%s: driver_add_attrs(%s) failed\n",
- __FUNCTION__, drv->name);
+ __func__, drv->name);
}
error = add_bind_files(drv);
if (error) {
/* Ditto */
printk(KERN_ERR "%s: add_bind_files(%s) failed\n",
- __FUNCTION__, drv->name);
+ __func__, drv->name);
}
kobject_uevent(&priv->kobj, KOBJ_ADD);
static void class_create_release(struct class *cls)
{
- pr_debug("%s called for %s\n", __FUNCTION__, cls->name);
+ pr_debug("%s called for %s\n", __func__, cls->name);
kfree(cls);
}
static void class_device_create_release(struct class_device *class_dev)
{
- pr_debug("%s called for %s\n", __FUNCTION__, class_dev->class_id);
+ pr_debug("%s called for %s\n", __func__, class_dev->class_id);
kfree(class_dev);
}
static int class_device_create_uevent(struct class_device *class_dev,
struct kobj_uevent_env *env)
{
- pr_debug("%s called for %s\n", __FUNCTION__, class_dev->class_id);
+ pr_debug("%s called for %s\n", __func__, class_dev->class_id);
return 0;
}
struct device *dev = class_dev->dev;
int retval = 0;
- pr_debug("%s - name = %s\n", __FUNCTION__, class_dev->class_id);
+ pr_debug("%s - name = %s\n", __func__, class_dev->class_id);
if (MAJOR(class_dev->devt)) {
add_uevent_var(env, "MAJOR=%u", MAJOR(class_dev->devt));
#include <linux/notifier.h>
#include <linux/genhd.h>
#include <linux/kallsyms.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include "base.h"
#include "power/power.h"
retval = dev->bus->uevent(dev, env);
if (retval)
pr_debug("device: '%s': %s: bus uevent() returned %d\n",
- dev->bus_id, __FUNCTION__, retval);
+ dev->bus_id, __func__, retval);
}
/* have the class specific function add its stuff */
if (retval)
pr_debug("device: '%s': %s: class uevent() "
"returned %d\n", dev->bus_id,
- __FUNCTION__, retval);
+ __func__, retval);
}
/* have the device type specific fuction add its stuff */
if (retval)
pr_debug("device: '%s': %s: dev_type uevent() "
"returned %d\n", dev->bus_id,
- __FUNCTION__, retval);
+ __func__, retval);
}
return retval;
goto Done;
}
- pr_debug("device: '%s': %s\n", dev->bus_id, __FUNCTION__);
+ pr_debug("device: '%s': %s\n", dev->bus_id, __func__);
parent = get_device(dev->parent);
setup_parent(dev, parent);
error = device_add_attrs(dev);
if (error)
goto AttrsError;
- error = dpm_sysfs_add(dev);
- if (error)
- goto PMError;
- device_pm_add(dev);
error = bus_add_device(dev);
if (error)
goto BusError;
+ error = device_pm_add(dev);
+ if (error)
+ goto PMError;
kobject_uevent(&dev->kobj, KOBJ_ADD);
bus_attach_device(dev);
if (parent)
Done:
put_device(dev);
return error;
- BusError:
- device_pm_remove(dev);
PMError:
+ bus_remove_device(dev);
+ BusError:
if (dev->bus)
blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
BUS_NOTIFY_DEL_DEVICE, dev);
*/
void device_unregister(struct device *dev)
{
- pr_debug("device: '%s': %s\n", dev->bus_id, __FUNCTION__);
+ pr_debug("device: '%s': %s\n", dev->bus_id, __func__);
device_del(dev);
put_device(dev);
}
static void device_create_release(struct device *dev)
{
- pr_debug("device: '%s': %s\n", dev->bus_id, __FUNCTION__);
+ pr_debug("device: '%s': %s\n", dev->bus_id, __func__);
kfree(dev);
}
}
EXPORT_SYMBOL_GPL(device_destroy);
-#ifdef CONFIG_PM_SLEEP
-/**
- * destroy_suspended_device - asks the PM core to remove a suspended device
- * @class: pointer to the struct class that this device was registered with
- * @devt: the dev_t of the device that was previously registered
- *
- * This call notifies the PM core of the necessity to unregister a suspended
- * device created with a call to device_create() (devices cannot be
- * unregistered directly while suspended, since the PM core holds their
- * semaphores at that time).
- *
- * It can only be called within the scope of a system sleep transition. In
- * practice this means it has to be directly or indirectly invoked either by
- * a suspend or resume method, or by the PM core (e.g. via
- * disable_nonboot_cpus() or enable_nonboot_cpus()).
- */
-void destroy_suspended_device(struct class *class, dev_t devt)
-{
- struct device *dev;
-
- dev = class_find_device(class, &devt, __match_devt);
- if (dev) {
- device_pm_schedule_removal(dev);
- put_device(dev);
- }
-}
-EXPORT_SYMBOL_GPL(destroy_suspended_device);
-#endif /* CONFIG_PM_SLEEP */
-
/**
* device_rename - renames a device
* @dev: the pointer to the struct device to be renamed
return -EINVAL;
pr_debug("device: '%s': %s: renaming to '%s'\n", dev->bus_id,
- __FUNCTION__, new_name);
+ __func__, new_name);
#ifdef CONFIG_SYSFS_DEPRECATED
if ((dev->class) && (dev->parent))
dev->bus_id);
if (error) {
dev_err(dev, "%s: sysfs_create_symlink failed (%d)\n",
- __FUNCTION__, error);
+ __func__, error);
}
}
#endif
new_parent_kobj = get_device_parent(dev, new_parent);
pr_debug("device: '%s': %s: moving to '%s'\n", dev->bus_id,
- __FUNCTION__, new_parent ? new_parent->bus_id : "<NULL>");
+ __func__, new_parent ? new_parent->bus_id : "<NULL>");
error = kobject_move(&dev->kobj, new_parent_kobj);
if (error) {
cleanup_glue_dir(dev, new_parent_kobj);
return sprintf(buf, "%u\n", !!cpu_online(cpu->sysdev.id));
}
-static ssize_t store_online(struct sys_device *dev, const char *buf,
+static ssize_t __ref store_online(struct sys_device *dev, const char *buf,
size_t count)
{
struct cpu *cpu = container_of(dev, struct cpu, sysdev);
}
static SYSDEV_ATTR(online, 0644, show_online, store_online);
-static void __devinit register_cpu_control(struct cpu *cpu)
+static void __cpuinit register_cpu_control(struct cpu *cpu)
{
sysdev_create_file(&cpu->sysdev, &attr_online);
}
static SYSDEV_ATTR(crash_notes, 0400, show_crash_notes, NULL);
#endif
+/*
+ * Print cpu online, possible, present, and system maps
+ */
+static ssize_t print_cpus_map(char *buf, cpumask_t *map)
+{
+ int n = cpulist_scnprintf(buf, PAGE_SIZE-2, *map);
+
+ buf[n++] = '\n';
+ buf[n] = '\0';
+ return n;
+}
+
+#define print_cpus_func(type) \
+static ssize_t print_cpus_##type(struct sysdev_class *class, char *buf) \
+{ \
+ return print_cpus_map(buf, &cpu_##type##_map); \
+} \
+struct sysdev_class_attribute attr_##type##_map = \
+ _SYSDEV_CLASS_ATTR(type, 0444, print_cpus_##type, NULL)
+
+print_cpus_func(online);
+print_cpus_func(possible);
+print_cpus_func(present);
+
+struct sysdev_class_attribute *cpu_state_attr[] = {
+ &attr_online_map,
+ &attr_possible_map,
+ &attr_present_map,
+};
+
+static int cpu_states_init(void)
+{
+ int i;
+ int err = 0;
+
+ for (i = 0; i < ARRAY_SIZE(cpu_state_attr); i++) {
+ int ret;
+ ret = sysdev_class_create_file(&cpu_sysdev_class,
+ cpu_state_attr[i]);
+ if (!err)
+ err = ret;
+ }
+ return err;
+}
+
/*
* register_cpu - Setup a sysfs device for a CPU.
* @cpu - cpu->hotpluggable field set to 1 will generate a control file in
int err;
err = sysdev_class_register(&cpu_sysdev_class);
+ if (!err)
+ err = cpu_states_init();
+
#if defined(CONFIG_SCHED_MC) || defined(CONFIG_SCHED_SMT)
if (!err)
err = sched_create_sysfs_power_savings_entries(&cpu_sysdev_class);
{
if (klist_node_attached(&dev->knode_driver)) {
printk(KERN_WARNING "%s: device %s already bound\n",
- __FUNCTION__, kobject_name(&dev->kobj));
+ __func__, kobject_name(&dev->kobj));
return;
}
pr_debug("driver: '%s': %s: bound to device '%s'\n", dev->bus_id,
- __FUNCTION__, dev->driver->name);
+ __func__, dev->driver->name);
if (dev->bus)
blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
atomic_inc(&probe_count);
pr_debug("bus: '%s': %s: probing driver %s with device %s\n",
- drv->bus->name, __FUNCTION__, drv->name, dev->bus_id);
+ drv->bus->name, __func__, drv->name, dev->bus_id);
WARN_ON(!list_empty(&dev->devres_head));
dev->driver = drv;
if (driver_sysfs_add(dev)) {
printk(KERN_ERR "%s: driver_sysfs_add(%s) failed\n",
- __FUNCTION__, dev->bus_id);
+ __func__, dev->bus_id);
goto probe_failed;
}
driver_bound(dev);
ret = 1;
pr_debug("bus: '%s': %s: bound device %s to driver %s\n",
- drv->bus->name, __FUNCTION__, dev->bus_id, drv->name);
+ drv->bus->name, __func__, dev->bus_id, drv->name);
goto done;
probe_failed:
*/
int driver_probe_done(void)
{
- pr_debug("%s: probe_count = %d\n", __FUNCTION__,
+ pr_debug("%s: probe_count = %d\n", __func__,
atomic_read(&probe_count));
if (atomic_read(&probe_count))
return -EBUSY;
goto done;
pr_debug("bus: '%s': %s: matched device %s with driver %s\n",
- drv->bus->name, __FUNCTION__, dev->bus_id, drv->name);
+ drv->bus->name, __func__, dev->bus_id, drv->name);
ret = really_probe(dev, drv);
}
/* fallthrough */
default:
- printk(KERN_ERR "%s: unexpected value (%d)\n", __FUNCTION__,
+ printk(KERN_ERR "%s: unexpected value (%d)\n", __func__,
loading);
/* fallthrough */
case -1:
new_size = ALIGN(min_size, PAGE_SIZE);
new_data = vmalloc(new_size);
if (!new_data) {
- printk(KERN_ERR "%s: unable to alloc buffer\n", __FUNCTION__);
+ printk(KERN_ERR "%s: unable to alloc buffer\n", __func__);
/* Make sure that we don't keep incomplete data */
fw_load_abort(fw_priv);
return -ENOMEM;
*dev_p = NULL;
if (!fw_priv || !f_dev) {
- printk(KERN_ERR "%s: kmalloc failed\n", __FUNCTION__);
+ printk(KERN_ERR "%s: kmalloc failed\n", __func__);
retval = -ENOMEM;
goto error_kfree;
}
retval = device_register(f_dev);
if (retval) {
printk(KERN_ERR "%s: device_register failed\n",
- __FUNCTION__);
+ __func__);
goto error_kfree;
}
*dev_p = f_dev;
retval = sysfs_create_bin_file(&f_dev->kobj, &fw_priv->attr_data);
if (retval) {
printk(KERN_ERR "%s: sysfs_create_bin_file failed\n",
- __FUNCTION__);
+ __func__);
goto error_unreg;
}
retval = device_create_file(f_dev, &dev_attr_loading);
if (retval) {
printk(KERN_ERR "%s: device_create_file failed\n",
- __FUNCTION__);
+ __func__);
goto error_unreg;
}
*firmware_p = firmware = kzalloc(sizeof(*firmware), GFP_KERNEL);
if (!firmware) {
printk(KERN_ERR "%s: kmalloc(struct firmware) failed\n",
- __FUNCTION__);
+ __func__);
retval = -ENOMEM;
goto out;
}
int error;
error = class_register(&firmware_class);
if (error) {
- printk(KERN_ERR "%s: class_register failed\n", __FUNCTION__);
+ printk(KERN_ERR "%s: class_register failed\n", __func__);
return error;
}
error = class_create_file(&firmware_class, &class_attr_timeout);
if (error) {
printk(KERN_ERR "%s: class_create_file failed\n",
- __FUNCTION__);
+ __func__);
class_unregister(&firmware_class);
}
return error;
#include <linux/kobject.h>
#include <linux/memory_hotplug.h>
#include <linux/mm.h>
+#include <linux/mutex.h>
#include <asm/atomic.h>
#include <asm/uaccess.h>
/*
* register_memory - Setup a sysfs device for a memory block
*/
-int register_memory(struct memory_block *memory, struct mem_section *section,
- struct node *root)
+static
+int register_memory(struct memory_block *memory, struct mem_section *section)
{
int error;
memory->sysdev.id = __section_nr(section);
error = sysdev_register(&memory->sysdev);
-
- if (root && !error)
- error = sysfs_create_link(&root->sysdev.kobj,
- &memory->sysdev.kobj,
- kobject_name(&memory->sysdev.kobj));
-
return error;
}
static void
-unregister_memory(struct memory_block *memory, struct mem_section *section,
- struct node *root)
+unregister_memory(struct memory_block *memory, struct mem_section *section)
{
BUG_ON(memory->sysdev.cls != &memory_sysdev_class);
BUG_ON(memory->sysdev.id != __section_nr(section));
+ /* drop the ref. we got in remove_memory_block() */
+ kobject_put(&memory->sysdev.kobj);
sysdev_unregister(&memory->sysdev);
- if (root)
- sysfs_remove_link(&root->sysdev.kobj,
- kobject_name(&memory->sysdev.kobj));
}
/*
break;
default:
printk(KERN_WARNING "%s(%p, %ld) unknown action: %ld\n",
- __FUNCTION__, mem, action, action);
+ __func__, mem, action, action);
WARN_ON(1);
ret = -EINVAL;
}
unsigned long to_state, unsigned long from_state_req)
{
int ret = 0;
- down(&mem->state_sem);
+ mutex_lock(&mem->state_mutex);
if (mem->state != from_state_req) {
ret = -EINVAL;
mem->state = to_state;
out:
- up(&mem->state_sem);
+ mutex_unlock(&mem->state_mutex);
return ret;
}
mem->phys_index = __section_nr(section);
mem->state = state;
- init_MUTEX(&mem->state_sem);
+ mutex_init(&mem->state_mutex);
mem->phys_device = phys_device;
- ret = register_memory(mem, section, NULL);
+ ret = register_memory(mem, section);
if (!ret)
ret = mem_create_simple_file(mem, phys_index);
if (!ret)
mem_remove_simple_file(mem, phys_index);
mem_remove_simple_file(mem, state);
mem_remove_simple_file(mem, phys_device);
- unregister_memory(mem, section, NULL);
+ unregister_memory(mem, section);
return 0;
}
ret = err;
out:
if (ret)
- printk(KERN_ERR "%s() failed: %d\n", __FUNCTION__, ret);
+ printk(KERN_ERR "%s() failed: %d\n", __func__, ret);
return ret;
}
};
-static ssize_t node_read_cpumap(struct sys_device * dev, char * buf)
+static ssize_t node_read_cpumap(struct sys_device *dev, int type, char *buf)
{
struct node *node_dev = to_node(dev);
- cpumask_t mask = node_to_cpumask(node_dev->sysdev.id);
+ node_to_cpumask_ptr(mask, node_dev->sysdev.id);
int len;
- /* 2004/06/03: buf currently PAGE_SIZE, need > 1 char per 4 bits. */
- BUILD_BUG_ON(MAX_NUMNODES/4 > PAGE_SIZE/2);
+ /* 2008/04/07: buf currently PAGE_SIZE, need 9 chars per 32 bits. */
+ BUILD_BUG_ON((NR_CPUS/32 * 9) > (PAGE_SIZE-1));
- len = cpumask_scnprintf(buf, PAGE_SIZE-1, mask);
- len += sprintf(buf + len, "\n");
+ len = type?
+ cpulist_scnprintf(buf, PAGE_SIZE-2, *mask):
+ cpumask_scnprintf(buf, PAGE_SIZE-2, *mask);
+ buf[len++] = '\n';
+ buf[len] = '\0';
return len;
}
-static SYSDEV_ATTR(cpumap, S_IRUGO, node_read_cpumap, NULL);
+static inline ssize_t node_read_cpumask(struct sys_device *dev, char *buf)
+{
+ return node_read_cpumap(dev, 0, buf);
+}
+static inline ssize_t node_read_cpulist(struct sys_device *dev, char *buf)
+{
+ return node_read_cpumap(dev, 1, buf);
+}
+
+static SYSDEV_ATTR(cpumap, S_IRUGO, node_read_cpumask, NULL);
+static SYSDEV_ATTR(cpulist, S_IRUGO, node_read_cpulist, NULL);
#define K(x) ((x) << (PAGE_SHIFT - 10))
static ssize_t node_read_meminfo(struct sys_device * dev, char * buf)
if (!error){
sysdev_create_file(&node->sysdev, &attr_cpumap);
+ sysdev_create_file(&node->sysdev, &attr_cpulist);
sysdev_create_file(&node->sysdev, &attr_meminfo);
sysdev_create_file(&node->sysdev, &attr_numastat);
sysdev_create_file(&node->sysdev, &attr_distance);
void unregister_node(struct node *node)
{
sysdev_remove_file(&node->sysdev, &attr_cpumap);
+ sysdev_remove_file(&node->sysdev, &attr_cpulist);
sysdev_remove_file(&node->sysdev, &attr_meminfo);
sysdev_remove_file(&node->sysdev, &attr_numastat);
sysdev_remove_file(&node->sysdev, &attr_distance);
LIST_HEAD(dpm_active);
static LIST_HEAD(dpm_off);
static LIST_HEAD(dpm_off_irq);
-static LIST_HEAD(dpm_destroy);
static DEFINE_MUTEX(dpm_list_mtx);
-static DECLARE_RWSEM(pm_sleep_rwsem);
-
-int (*platform_enable_wakeup)(struct device *dev, int is_on);
+/* 'true' if all devices have been suspended, protected by dpm_list_mtx */
+static bool all_sleeping;
/**
* device_pm_add - add a device to the list of active devices
* @dev: Device to be added to the list
*/
-void device_pm_add(struct device *dev)
+int device_pm_add(struct device *dev)
{
+ int error;
+
pr_debug("PM: Adding info for %s:%s\n",
dev->bus ? dev->bus->name : "No Bus",
kobject_name(&dev->kobj));
mutex_lock(&dpm_list_mtx);
- list_add_tail(&dev->power.entry, &dpm_active);
+ if ((dev->parent && dev->parent->power.sleeping) || all_sleeping) {
+ if (dev->parent->power.sleeping)
+ dev_warn(dev, "parent %s is sleeping\n",
+ dev->parent->bus_id);
+ else
+ dev_warn(dev, "all devices are sleeping\n");
+ WARN_ON(true);
+ }
+ error = dpm_sysfs_add(dev);
+ if (!error)
+ list_add_tail(&dev->power.entry, &dpm_active);
mutex_unlock(&dpm_list_mtx);
+ return error;
}
/**
mutex_unlock(&dpm_list_mtx);
}
-/**
- * device_pm_schedule_removal - schedule the removal of a suspended device
- * @dev: Device to destroy
- *
- * Moves the device to the dpm_destroy list for further processing by
- * unregister_dropped_devices().
- */
-void device_pm_schedule_removal(struct device *dev)
-{
- pr_debug("PM: Preparing for removal: %s:%s\n",
- dev->bus ? dev->bus->name : "No Bus",
- kobject_name(&dev->kobj));
- mutex_lock(&dpm_list_mtx);
- list_move_tail(&dev->power.entry, &dpm_destroy);
- mutex_unlock(&dpm_list_mtx);
-}
-EXPORT_SYMBOL_GPL(device_pm_schedule_removal);
-
-/**
- * pm_sleep_lock - mutual exclusion for registration and suspend
- *
- * Returns 0 if no suspend is underway and device registration
- * may proceed, otherwise -EBUSY.
- */
-int pm_sleep_lock(void)
-{
- if (down_read_trylock(&pm_sleep_rwsem))
- return 0;
-
- return -EBUSY;
-}
-
-/**
- * pm_sleep_unlock - mutual exclusion for registration and suspend
- *
- * This routine undoes the effect of device_pm_add_lock
- * when a device's registration is complete.
- */
-void pm_sleep_unlock(void)
-{
- up_read(&pm_sleep_rwsem);
-}
-
-
/*------------------------- Resume routines -------------------------*/
/**
static void dpm_resume(void)
{
mutex_lock(&dpm_list_mtx);
+ all_sleeping = false;
while(!list_empty(&dpm_off)) {
struct list_head *entry = dpm_off.next;
struct device *dev = to_device(entry);
list_move_tail(entry, &dpm_active);
+ dev->power.sleeping = false;
mutex_unlock(&dpm_list_mtx);
resume_device(dev);
mutex_lock(&dpm_list_mtx);
mutex_unlock(&dpm_list_mtx);
}
-/**
- * unregister_dropped_devices - Unregister devices scheduled for removal
- *
- * Unregister all devices on the dpm_destroy list.
- */
-static void unregister_dropped_devices(void)
-{
- mutex_lock(&dpm_list_mtx);
- while (!list_empty(&dpm_destroy)) {
- struct list_head *entry = dpm_destroy.next;
- struct device *dev = to_device(entry);
-
- mutex_unlock(&dpm_list_mtx);
- /* This also removes the device from the list */
- device_unregister(dev);
- mutex_lock(&dpm_list_mtx);
- }
- mutex_unlock(&dpm_list_mtx);
-}
-
/**
* device_resume - Restore state of each device in system.
*
{
might_sleep();
dpm_resume();
- unregister_dropped_devices();
- up_write(&pm_sleep_rwsem);
}
EXPORT_SYMBOL_GPL(device_resume);
down(&dev->sem);
- if (dev->power.power_state.event) {
- dev_dbg(dev, "PM: suspend %d-->%d\n",
- dev->power.power_state.event, state.event);
- }
-
if (dev->class && dev->class->suspend) {
suspend_device_dbg(dev, state, "class ");
error = dev->class->suspend(dev, state);
struct list_head *entry = dpm_active.prev;
struct device *dev = to_device(entry);
+ WARN_ON(dev->parent && dev->parent->power.sleeping);
+
+ dev->power.sleeping = true;
mutex_unlock(&dpm_list_mtx);
error = suspend_device(dev, state);
mutex_lock(&dpm_list_mtx);
(error == -EAGAIN ?
" (please convert to suspend_late)" :
""));
+ dev->power.sleeping = false;
break;
}
if (!list_empty(&dev->power.entry))
list_move(&dev->power.entry, &dpm_off);
}
+ if (!error)
+ all_sleeping = true;
mutex_unlock(&dpm_list_mtx);
return error;
int error;
might_sleep();
- down_write(&pm_sleep_rwsem);
error = dpm_suspend(state);
if (error)
device_resume();
return container_of(entry, struct device, power.entry);
}
-extern void device_pm_add(struct device *);
+extern int device_pm_add(struct device *);
extern void device_pm_remove(struct device *);
-extern int pm_sleep_lock(void);
-extern void pm_sleep_unlock(void);
#else /* CONFIG_PM_SLEEP */
-
-static inline void device_pm_add(struct device *dev)
-{
-}
-
-static inline void device_pm_remove(struct device *dev)
-{
-}
-
-static inline int pm_sleep_lock(void)
-{
- return 0;
-}
-
-static inline void pm_sleep_unlock(void)
-{
-}
+static inline int device_pm_add(struct device *dev) { return 0; }
+static inline void device_pm_remove(struct device *dev) {}
#endif
#include <linux/string.h>
#include "power.h"
+int (*platform_enable_wakeup)(struct device *dev, int is_on);
+
/*
* wakeup - Report/change current wakeup option for device
{
int err = 0;
+ if (!cls) {
+ printk(KERN_WARNING "sysdev: invalid class passed to "
+ "sysdev_driver_register!\n");
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ /* Check whether this driver has already been added to a class. */
+ if ((drv->entry.next != drv->entry.prev) ||
+ (drv->entry.next != NULL)) {
+ printk(KERN_WARNING "sysdev: class %s: driver (%p) has already"
+ " been registered to a class, something is wrong, but "
+ "will forge on!\n", cls->name, drv);
+ WARN_ON(1);
+ }
+
mutex_lock(&sysdev_drivers_lock);
if (cls && kset_get(&cls->kset)) {
list_add_tail(&drv->entry, &cls->drivers);
}
} else {
err = -EINVAL;
- printk(KERN_ERR "%s: invalid device class\n", __FUNCTION__);
+ printk(KERN_ERR "%s: invalid device class\n", __func__);
WARN_ON(1);
}
mutex_unlock(&sysdev_drivers_lock);
return sprintf(buf, "%d\n", topology_##name(cpu)); \
}
-#define define_siblings_show_func(name) \
-static ssize_t show_##name(struct sys_device *dev, char *buf) \
+static ssize_t show_cpumap(int type, cpumask_t *mask, char *buf)
+{
+ ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
+ int n = 0;
+
+ if (len > 1) {
+ n = type?
+ cpulist_scnprintf(buf, len-2, *mask):
+ cpumask_scnprintf(buf, len-2, *mask);
+ buf[n++] = '\n';
+ buf[n] = '\0';
+ }
+ return n;
+}
+
+#define define_siblings_show_map(name) \
+static inline ssize_t show_##name(struct sys_device *dev, char *buf) \
{ \
- ssize_t len = -1; \
unsigned int cpu = dev->id; \
- len = cpumask_scnprintf(buf, NR_CPUS+1, topology_##name(cpu)); \
- return (len + sprintf(buf + len, "\n")); \
+ return show_cpumap(0, &(topology_##name(cpu)), buf); \
}
+#define define_siblings_show_list(name) \
+static inline ssize_t show_##name##_list(struct sys_device *dev, char *buf) \
+{ \
+ unsigned int cpu = dev->id; \
+ return show_cpumap(1, &(topology_##name(cpu)), buf); \
+}
+
+#define define_siblings_show_func(name) \
+ define_siblings_show_map(name); define_siblings_show_list(name)
+
#ifdef topology_physical_package_id
define_id_show_func(physical_package_id);
define_one_ro(physical_package_id);
#ifdef topology_thread_siblings
define_siblings_show_func(thread_siblings);
define_one_ro(thread_siblings);
-#define ref_thread_siblings_attr &attr_thread_siblings.attr,
+define_one_ro(thread_siblings_list);
+#define ref_thread_siblings_attr \
+ &attr_thread_siblings.attr, &attr_thread_siblings_list.attr,
#else
#define ref_thread_siblings_attr
#endif
#ifdef topology_core_siblings
define_siblings_show_func(core_siblings);
define_one_ro(core_siblings);
-#define ref_core_siblings_attr &attr_core_siblings.attr,
+define_one_ro(core_siblings_list);
+#define ref_core_siblings_attr \
+ &attr_core_siblings.attr, &attr_core_siblings_list.attr,
#else
#define ref_core_siblings_attr
#endif
static int anon_transport_dummy_function(struct transport_container *tc,
struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
/* do nothing */
return 0;
static int transport_setup_classdev(struct attribute_container *cont,
struct device *dev,
- struct class_device *classdev)
+ struct device *classdev)
{
struct transport_class *tclass = class_to_transport_class(cont->class);
struct transport_container *tcont = attribute_container_to_transport_container(cont);
static int transport_add_class_device(struct attribute_container *cont,
struct device *dev,
- struct class_device *classdev)
+ struct device *classdev)
{
int error = attribute_container_add_class_device(classdev);
struct transport_container *tcont =
static int transport_configure(struct attribute_container *cont,
struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct transport_class *tclass = class_to_transport_class(cont->class);
struct transport_container *tcont = attribute_container_to_transport_container(cont);
static int transport_remove_classdev(struct attribute_container *cont,
struct device *dev,
- struct class_device *classdev)
+ struct device *classdev)
{
struct transport_container *tcont =
attribute_container_to_transport_container(cont);
static void transport_destroy_classdev(struct attribute_container *cont,
struct device *dev,
- struct class_device *classdev)
+ struct device *classdev)
{
struct transport_class *tclass = class_to_transport_class(cont->class);
if (tclass->remove != anon_transport_dummy_function)
- class_device_put(classdev);
+ put_device(classdev);
}
#ifndef CONFIG_BLK_DEV_XIP
gfp_flags |= __GFP_HIGHMEM;
#endif
- page = alloc_page(GFP_NOIO | __GFP_HIGHMEM | __GFP_ZERO);
+ page = alloc_page(gfp_flags);
if (!page)
return NULL;
spin_lock_irqsave(CCISS_LOCK(h->ctlr), flags);
h->drv[drv_index].busy_configuring = 1;
spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags);
+
+ /* deregister_disk sets h->drv[drv_index].queue = NULL */
+ /* which keeps the interrupt handler from starting */
+ /* the queue. */
ret = deregister_disk(h->gendisk[drv_index],
&h->drv[drv_index], 0);
h->drv[drv_index].busy_configuring = 0;
blk_queue_hardsect_size(disk->queue,
hba[ctlr]->drv[drv_index].block_size);
+ /* Make sure all queue data is written out before */
+ /* setting h->drv[drv_index].queue, as setting this */
+ /* allows the interrupt handler to start the queue */
+ wmb();
h->drv[drv_index].queue = disk->queue;
add_disk(disk);
}
continue;
blk_queue_hardsect_size(q, drv->block_size);
set_capacity(disk, drv->nr_blocks);
- add_disk(disk);
j++;
} while (j <= hba[i]->highest_lun);
+ /* Make sure all queue data is written out before */
+ /* interrupt handler, triggered by add_disk, */
+ /* is allowed to start them. */
+ wmb();
+
+ for (j = 0; j <= hba[i]->highest_lun; j++)
+ add_disk(hba[i]->gendisk[j]);
+
return 1;
clean4:
/* set scsi_host to NULL so our detect routine will
find us on register */
sa->scsi_host = NULL;
+ spin_unlock_irqrestore(CCISS_LOCK(ctlr), flags);
scsi_cmd_stack_free(ctlr);
kfree(sa);
- spin_unlock_irqrestore(CCISS_LOCK(ctlr), flags);
}
static int
#include <linux/blkdev.h>
#include <linux/loop.h>
#include <linux/scatterlist.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
MODULE_LICENSE("GPL");
static LIST_HEAD(loop_devices);
static DEFINE_MUTEX(loop_devices_mutex);
+static int max_part;
+static int part_shift;
+
/*
* Transfer functions
*/
goto out_putf;
fput(old_file);
+ if (max_part > 0)
+ ioctl_by_bdev(bdev, BLKRRPART, 0);
return 0;
out_putf:
}
lo->lo_state = Lo_bound;
wake_up_process(lo->lo_thread);
+ if (max_part > 0)
+ ioctl_by_bdev(bdev, BLKRRPART, 0);
return 0;
out_clr:
fput(filp);
/* This is safe: open() is still holding a reference. */
module_put(THIS_MODULE);
+ if (max_part > 0)
+ ioctl_by_bdev(bdev, BLKRRPART, 0);
return 0;
}
static int max_loop;
module_param(max_loop, int, 0);
MODULE_PARM_DESC(max_loop, "Maximum number of loop devices");
+module_param(max_part, int, 0);
+MODULE_PARM_DESC(max_part, "Maximum number of partitions per loop device");
MODULE_LICENSE("GPL");
MODULE_ALIAS_BLOCKDEV_MAJOR(LOOP_MAJOR);
if (!lo->lo_queue)
goto out_free_dev;
- disk = lo->lo_disk = alloc_disk(1);
+ disk = lo->lo_disk = alloc_disk(1 << part_shift);
if (!disk)
goto out_free_queue;
init_waitqueue_head(&lo->lo_event);
spin_lock_init(&lo->lo_lock);
disk->major = LOOP_MAJOR;
- disk->first_minor = i;
+ disk->first_minor = i << part_shift;
disk->fops = &lo_fops;
disk->private_data = lo;
disk->queue = lo->lo_queue;
* themselves and have kernel automatically instantiate actual
* device on-demand.
*/
- if (max_loop > 1UL << MINORBITS)
+
+ part_shift = 0;
+ if (max_part > 0)
+ part_shift = fls(max_part);
+
+ if (max_loop > 1UL << (MINORBITS - part_shift))
return -EINVAL;
if (max_loop) {
range = max_loop;
} else {
nr = 8;
- range = 1UL << MINORBITS;
+ range = 1UL << (MINORBITS - part_shift);
}
if (register_blkdev(LOOP_MAJOR, "loop"))
unsigned long range;
struct loop_device *lo, *next;
- range = max_loop ? max_loop : 1UL << MINORBITS;
+ range = max_loop ? max_loop : 1UL << (MINORBITS - part_shift);
list_for_each_entry_safe(lo, next, &loop_devices, lo_list)
loop_del_one(lo);
/* note: prints function name for you */
#ifdef CARM_DEBUG
-#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
+#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
#ifdef CARM_VERBOSE_DEBUG
-#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
+#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
#else
#define VPRINTK(fmt, args...)
#endif /* CARM_VERBOSE_DEBUG */
#define assert(expr) \
if(unlikely(!(expr))) { \
printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
- #expr,__FILE__,__FUNCTION__,__LINE__); \
+ #expr, __FILE__, __func__, __LINE__); \
}
#endif
enum {
PARTITION_SHIFT = 3,
MAX_DISKNO = HVMAXARCHITECTEDVIRTUALDISKS,
- MAX_DISK_NAME = sizeof(((struct gendisk *)0)->disk_name)
+ MAX_DISK_NAME = FIELD_SIZEOF(struct gendisk, disk_name)
};
static DEFINE_SPINLOCK(viodasd_spinlock);
static int cdrom_get_disc_info(struct cdrom_device_info *cdi, disc_information *di);
-#ifdef CONFIG_SYSCTL
static void cdrom_sysctl_register(void);
-#endif /* CONFIG_SYSCTL */
-static struct cdrom_device_info *topCdromPtr;
+
+static LIST_HEAD(cdrom_list);
static int cdrom_dummy_generic_packet(struct cdrom_device_info *cdi,
struct packet_command *cgc)
cdinfo(CD_OPEN, "entering register_cdrom\n");
if (cdo->open == NULL || cdo->release == NULL)
- return -2;
+ return -EINVAL;
if (!banner_printed) {
printk(KERN_INFO "Uniform CD-ROM driver " REVISION "\n");
banner_printed = 1;
-#ifdef CONFIG_SYSCTL
cdrom_sysctl_register();
-#endif /* CONFIG_SYSCTL */
}
ENSURE(drive_status, CDC_DRIVE_STATUS );
cdinfo(CD_REG_UNREG, "drive \"/dev/%s\" registered\n", cdi->name);
mutex_lock(&cdrom_mutex);
- cdi->next = topCdromPtr;
- topCdromPtr = cdi;
+ list_add(&cdi->list, &cdrom_list);
mutex_unlock(&cdrom_mutex);
return 0;
}
#undef ENSURE
-int unregister_cdrom(struct cdrom_device_info *unreg)
+void unregister_cdrom(struct cdrom_device_info *cdi)
{
- struct cdrom_device_info *cdi, *prev;
cdinfo(CD_OPEN, "entering unregister_cdrom\n");
- prev = NULL;
mutex_lock(&cdrom_mutex);
- cdi = topCdromPtr;
- while (cdi && cdi != unreg) {
- prev = cdi;
- cdi = cdi->next;
- }
-
- if (cdi == NULL) {
- mutex_unlock(&cdrom_mutex);
- return -2;
- }
- if (prev)
- prev->next = cdi->next;
- else
- topCdromPtr = cdi->next;
-
+ list_del(&cdi->list);
mutex_unlock(&cdrom_mutex);
if (cdi->exit)
cdi->ops->n_minors--;
cdinfo(CD_REG_UNREG, "drive \"/dev/%s\" unregistered\n", cdi->name);
- return 0;
}
int cdrom_get_media_event(struct cdrom_device_info *cdi,
struct media_event_desc *med)
{
struct packet_command cgc;
- unsigned char buffer[8];
- struct event_header *eh = (struct event_header *) buffer;
+ unsigned char *buffer;
+ struct event_header *eh;
+ int ret = 1;
- init_cdrom_command(&cgc, buffer, sizeof(buffer), CGC_DATA_READ);
+ buffer = kmalloc(8, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
+
+ eh = (struct event_header *)buffer;
+
+ init_cdrom_command(&cgc, buffer, 8, CGC_DATA_READ);
cgc.cmd[0] = GPCMD_GET_EVENT_STATUS_NOTIFICATION;
cgc.cmd[1] = 1; /* IMMED */
cgc.cmd[4] = 1 << 4; /* media event */
- cgc.cmd[8] = sizeof(buffer);
+ cgc.cmd[8] = 8;
cgc.quiet = 1;
if (cdi->ops->generic_packet(cdi, &cgc))
- return 1;
+ goto err;
if (be16_to_cpu(eh->data_len) < sizeof(*med))
- return 1;
+ goto err;
if (eh->nea || eh->notification_class != 0x4)
- return 1;
+ goto err;
- memcpy(med, &buffer[sizeof(*eh)], sizeof(*med));
- return 0;
+ memcpy(med, buffer + sizeof(*eh), sizeof(*med));
+ ret = 0;
+err:
+ kfree(buffer);
+ return ret;
}
/*
static int cdrom_mrw_probe_pc(struct cdrom_device_info *cdi)
{
struct packet_command cgc;
- char buffer[16];
+ char *buffer;
+ int ret = 1;
- init_cdrom_command(&cgc, buffer, sizeof(buffer), CGC_DATA_READ);
+ buffer = kmalloc(16, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
+
+ init_cdrom_command(&cgc, buffer, 16, CGC_DATA_READ);
cgc.timeout = HZ;
cgc.quiet = 1;
if (!cdrom_mode_sense(cdi, &cgc, MRW_MODE_PC, 0)) {
cdi->mrw_mode_page = MRW_MODE_PC;
- return 0;
+ ret = 0;
} else if (!cdrom_mode_sense(cdi, &cgc, MRW_MODE_PC_PRE1, 0)) {
cdi->mrw_mode_page = MRW_MODE_PC_PRE1;
- return 0;
+ ret = 0;
}
-
- return 1;
+ kfree(buffer);
+ return ret;
}
static int cdrom_is_mrw(struct cdrom_device_info *cdi, int *write)
{
struct packet_command cgc;
struct mrw_feature_desc *mfd;
- unsigned char buffer[16];
+ unsigned char *buffer;
int ret;
*write = 0;
+ buffer = kmalloc(16, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
- init_cdrom_command(&cgc, buffer, sizeof(buffer), CGC_DATA_READ);
+ init_cdrom_command(&cgc, buffer, 16, CGC_DATA_READ);
cgc.cmd[0] = GPCMD_GET_CONFIGURATION;
cgc.cmd[3] = CDF_MRW;
- cgc.cmd[8] = sizeof(buffer);
+ cgc.cmd[8] = 16;
cgc.quiet = 1;
if ((ret = cdi->ops->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
mfd = (struct mrw_feature_desc *)&buffer[sizeof(struct feature_header)];
- if (be16_to_cpu(mfd->feature_code) != CDF_MRW)
- return 1;
+ if (be16_to_cpu(mfd->feature_code) != CDF_MRW) {
+ ret = 1;
+ goto err;
+ }
*write = mfd->write;
if ((ret = cdrom_mrw_probe_pc(cdi))) {
*write = 0;
- return ret;
}
-
- return 0;
+err:
+ kfree(buffer);
+ return ret;
}
static int cdrom_mrw_bgformat(struct cdrom_device_info *cdi, int cont)
{
struct packet_command cgc;
- unsigned char buffer[12];
+ unsigned char *buffer;
int ret;
printk(KERN_INFO "cdrom: %sstarting format\n", cont ? "Re" : "");
+ buffer = kmalloc(12, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
+
/*
* FmtData bit set (bit 4), format type is 1
*/
- init_cdrom_command(&cgc, buffer, sizeof(buffer), CGC_DATA_WRITE);
+ init_cdrom_command(&cgc, buffer, 12, CGC_DATA_WRITE);
cgc.cmd[0] = GPCMD_FORMAT_UNIT;
cgc.cmd[1] = (1 << 4) | 1;
if (ret)
printk(KERN_INFO "cdrom: bgformat failed\n");
+ kfree(buffer);
return ret;
}
{
struct packet_command cgc;
struct mode_page_header *mph;
- char buffer[16];
+ char *buffer;
int ret, offset, size;
- init_cdrom_command(&cgc, buffer, sizeof(buffer), CGC_DATA_READ);
+ buffer = kmalloc(16, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
- cgc.buffer = buffer;
- cgc.buflen = sizeof(buffer);
+ init_cdrom_command(&cgc, buffer, 16, CGC_DATA_READ);
if ((ret = cdrom_mode_sense(cdi, &cgc, cdi->mrw_mode_page, 0)))
- return ret;
+ goto err;
mph = (struct mode_page_header *) buffer;
offset = be16_to_cpu(mph->desc_length);
cgc.buflen = size;
if ((ret = cdrom_mode_select(cdi, &cgc)))
- return ret;
+ goto err;
printk(KERN_INFO "cdrom: %s: mrw address space %s selected\n", cdi->name, mrw_address_space[space]);
- return 0;
+ ret = 0;
+err:
+ kfree(buffer);
+ return ret;
}
static int cdrom_get_random_writable(struct cdrom_device_info *cdi,
struct rwrt_feature_desc *rfd)
{
struct packet_command cgc;
- char buffer[24];
+ char *buffer;
int ret;
- init_cdrom_command(&cgc, buffer, sizeof(buffer), CGC_DATA_READ);
+ buffer = kmalloc(24, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
+
+ init_cdrom_command(&cgc, buffer, 24, CGC_DATA_READ);
cgc.cmd[0] = GPCMD_GET_CONFIGURATION; /* often 0x46 */
cgc.cmd[3] = CDF_RWRT; /* often 0x0020 */
- cgc.cmd[8] = sizeof(buffer); /* often 0x18 */
+ cgc.cmd[8] = 24; /* often 0x18 */
cgc.quiet = 1;
if ((ret = cdi->ops->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
memcpy(rfd, &buffer[sizeof(struct feature_header)], sizeof (*rfd));
- return 0;
+ ret = 0;
+err:
+ kfree(buffer);
+ return ret;
}
static int cdrom_has_defect_mgt(struct cdrom_device_info *cdi)
{
struct packet_command cgc;
- char buffer[16];
+ char *buffer;
__be16 *feature_code;
int ret;
- init_cdrom_command(&cgc, buffer, sizeof(buffer), CGC_DATA_READ);
+ buffer = kmalloc(16, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
+
+ init_cdrom_command(&cgc, buffer, 16, CGC_DATA_READ);
cgc.cmd[0] = GPCMD_GET_CONFIGURATION;
cgc.cmd[3] = CDF_HWDM;
- cgc.cmd[8] = sizeof(buffer);
+ cgc.cmd[8] = 16;
cgc.quiet = 1;
if ((ret = cdi->ops->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
feature_code = (__be16 *) &buffer[sizeof(struct feature_header)];
if (be16_to_cpu(*feature_code) == CDF_HWDM)
- return 0;
-
- return 1;
+ ret = 0;
+err:
+ kfree(buffer);
+ return ret;
}
static int mo_open_write(struct cdrom_device_info *cdi)
{
struct packet_command cgc;
- char buffer[255];
+ char *buffer;
int ret;
- init_cdrom_command(&cgc, &buffer, 4, CGC_DATA_READ);
+ buffer = kmalloc(255, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
+
+ init_cdrom_command(&cgc, buffer, 4, CGC_DATA_READ);
cgc.quiet = 1;
/*
}
/* drive gave us no info, let the user go ahead */
- if (ret)
- return 0;
+ if (ret) {
+ ret = 0;
+ goto err;
+ }
- return buffer[3] & 0x80;
+ ret = buffer[3] & 0x80;
+err:
+ kfree(buffer);
+ return ret;
}
static int cdrom_ram_open_write(struct cdrom_device_info *cdi)
static void cdrom_mmc3_profile(struct cdrom_device_info *cdi)
{
struct packet_command cgc;
- char buffer[32];
+ char *buffer;
int ret, mmc3_profile;
- init_cdrom_command(&cgc, buffer, sizeof(buffer), CGC_DATA_READ);
+ buffer = kmalloc(32, GFP_KERNEL);
+ if (!buffer)
+ return;
+
+ init_cdrom_command(&cgc, buffer, 32, CGC_DATA_READ);
cgc.cmd[0] = GPCMD_GET_CONFIGURATION;
cgc.cmd[1] = 0;
cgc.cmd[2] = cgc.cmd[3] = 0; /* Starting Feature Number */
- cgc.cmd[8] = sizeof(buffer); /* Allocation Length */
+ cgc.cmd[8] = 32; /* Allocation Length */
cgc.quiet = 1;
if ((ret = cdi->ops->generic_packet(cdi, &cgc)))
mmc3_profile = (buffer[6] << 8) | buffer[7];
cdi->mmc3_profile = mmc3_profile;
+ kfree(buffer);
}
static int cdrom_is_dvd_rw(struct cdrom_device_info *cdi)
static int dvd_do_auth(struct cdrom_device_info *cdi, dvd_authinfo *ai)
{
int ret;
- u_char buf[20];
+ u_char *buf;
struct packet_command cgc;
struct cdrom_device_ops *cdo = cdi->ops;
- rpc_state_t rpc_state;
+ rpc_state_t *rpc_state;
+
+ buf = kzalloc(20, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
- memset(buf, 0, sizeof(buf));
init_cdrom_command(&cgc, buf, 0, CGC_DATA_READ);
switch (ai->type) {
setup_report_key(&cgc, ai->lsa.agid, 0);
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
ai->lsa.agid = buf[7] >> 6;
/* Returning data, let host change state */
setup_report_key(&cgc, ai->lsk.agid, 2);
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
copy_key(ai->lsk.key, &buf[4]);
/* Returning data, let host change state */
setup_report_key(&cgc, ai->lsc.agid, 1);
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
copy_chal(ai->lsc.chal, &buf[4]);
/* Returning data, let host change state */
cgc.cmd[2] = ai->lstk.lba >> 24;
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
ai->lstk.cpm = (buf[4] >> 7) & 1;
ai->lstk.cp_sec = (buf[4] >> 6) & 1;
setup_report_key(&cgc, ai->lsasf.agid, 5);
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
ai->lsasf.asf = buf[7] & 1;
break;
copy_chal(&buf[4], ai->hsc.chal);
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
ai->type = DVD_LU_SEND_KEY1;
break;
if ((ret = cdo->generic_packet(cdi, &cgc))) {
ai->type = DVD_AUTH_FAILURE;
- return ret;
+ goto err;
}
ai->type = DVD_AUTH_ESTABLISHED;
break;
cdinfo(CD_DVD, "entering DVD_INVALIDATE_AGID\n");
setup_report_key(&cgc, ai->lsa.agid, 0x3f);
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
break;
/* Get region settings */
case DVD_LU_SEND_RPC_STATE:
cdinfo(CD_DVD, "entering DVD_LU_SEND_RPC_STATE\n");
setup_report_key(&cgc, 0, 8);
- memset(&rpc_state, 0, sizeof(rpc_state_t));
- cgc.buffer = (char *) &rpc_state;
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
- ai->lrpcs.type = rpc_state.type_code;
- ai->lrpcs.vra = rpc_state.vra;
- ai->lrpcs.ucca = rpc_state.ucca;
- ai->lrpcs.region_mask = rpc_state.region_mask;
- ai->lrpcs.rpc_scheme = rpc_state.rpc_scheme;
+ rpc_state = (rpc_state_t *)buf;
+ ai->lrpcs.type = rpc_state->type_code;
+ ai->lrpcs.vra = rpc_state->vra;
+ ai->lrpcs.ucca = rpc_state->ucca;
+ ai->lrpcs.region_mask = rpc_state->region_mask;
+ ai->lrpcs.rpc_scheme = rpc_state->rpc_scheme;
break;
/* Set region settings */
buf[4] = ai->hrpcs.pdrc;
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
break;
default:
cdinfo(CD_WARNING, "Invalid DVD key ioctl (%d)\n", ai->type);
- return -ENOTTY;
+ ret = -ENOTTY;
+ goto err;
}
-
- return 0;
+ ret = 0;
+err:
+ kfree(buf);
+ return ret;
}
static int dvd_read_physical(struct cdrom_device_info *cdi, dvd_struct *s)
{
- unsigned char buf[21], *base;
+ unsigned char *buf, *base;
struct dvd_layer *layer;
struct packet_command cgc;
struct cdrom_device_ops *cdo = cdi->ops;
if (layer_num >= DVD_LAYERS)
return -EINVAL;
- init_cdrom_command(&cgc, buf, sizeof(buf), CGC_DATA_READ);
+ buf = kmalloc(21, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ init_cdrom_command(&cgc, buf, 21, CGC_DATA_READ);
cgc.cmd[0] = GPCMD_READ_DVD_STRUCTURE;
cgc.cmd[6] = layer_num;
cgc.cmd[7] = s->type;
cgc.quiet = 1;
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
base = &buf[4];
layer = &s->physical.layer[layer_num];
layer->end_sector_l0 = base[13] << 16 | base[14] << 8 | base[15];
layer->bca = base[16] >> 7;
- return 0;
+ ret = 0;
+err:
+ kfree(buf);
+ return ret;
}
static int dvd_read_copyright(struct cdrom_device_info *cdi, dvd_struct *s)
{
int ret;
- u_char buf[8];
+ u_char *buf;
struct packet_command cgc;
struct cdrom_device_ops *cdo = cdi->ops;
- init_cdrom_command(&cgc, buf, sizeof(buf), CGC_DATA_READ);
+ buf = kmalloc(8, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ init_cdrom_command(&cgc, buf, 8, CGC_DATA_READ);
cgc.cmd[0] = GPCMD_READ_DVD_STRUCTURE;
cgc.cmd[6] = s->copyright.layer_num;
cgc.cmd[7] = s->type;
cgc.cmd[9] = cgc.buflen & 0xff;
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
s->copyright.cpst = buf[4];
s->copyright.rmi = buf[5];
- return 0;
+ ret = 0;
+err:
+ kfree(buf);
+ return ret;
}
static int dvd_read_disckey(struct cdrom_device_info *cdi, dvd_struct *s)
static int dvd_read_bca(struct cdrom_device_info *cdi, dvd_struct *s)
{
int ret;
- u_char buf[4 + 188];
+ u_char *buf;
struct packet_command cgc;
struct cdrom_device_ops *cdo = cdi->ops;
- init_cdrom_command(&cgc, buf, sizeof(buf), CGC_DATA_READ);
+ buf = kmalloc(4 + 188, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ init_cdrom_command(&cgc, buf, 4 + 188, CGC_DATA_READ);
cgc.cmd[0] = GPCMD_READ_DVD_STRUCTURE;
cgc.cmd[7] = s->type;
cgc.cmd[9] = cgc.buflen & 0xff;
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
s->bca.len = buf[0] << 8 | buf[1];
if (s->bca.len < 12 || s->bca.len > 188) {
cdinfo(CD_WARNING, "Received invalid BCA length (%d)\n", s->bca.len);
- return -EIO;
+ ret = -EIO;
+ goto err;
}
memcpy(s->bca.value, &buf[4], s->bca.len);
-
- return 0;
+ ret = 0;
+err:
+ kfree(buf);
+ return ret;
}
static int dvd_read_manufact(struct cdrom_device_info *cdi, dvd_struct *s)
{
struct cdrom_device_ops *cdo = cdi->ops;
struct packet_command cgc;
- char buffer[32];
+ char *buffer;
int ret;
+ buffer = kmalloc(32, GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
+
init_cdrom_command(&cgc, buffer, 16, CGC_DATA_READ);
cgc.cmd[0] = GPCMD_READ_SUBCHANNEL;
cgc.cmd[1] = 2; /* MSF addressing */
cgc.cmd[8] = 16;
if ((ret = cdo->generic_packet(cdi, &cgc)))
- return ret;
+ goto err;
subchnl->cdsc_audiostatus = cgc.buffer[1];
subchnl->cdsc_format = CDROM_MSF;
subchnl->cdsc_absaddr.msf.second = cgc.buffer[10];
subchnl->cdsc_absaddr.msf.frame = cgc.buffer[11];
- return 0;
+ ret = 0;
+err:
+ kfree(buffer);
+ return ret;
}
/*
*pos += ret;
- for (cdi = topCdromPtr; cdi; cdi = cdi->next) {
+ list_for_each_entry(cdi, &cdrom_list, list) {
switch (option) {
case CTL_NAME:
ret = scnprintf(info + *pos, max_size - *pos,
{
struct cdrom_device_info *cdi;
- for (cdi = topCdromPtr; cdi != NULL; cdi = cdi->next) {
+ mutex_lock(&cdrom_mutex);
+ list_for_each_entry(cdi, &cdrom_list, list) {
if (autoclose && CDROM_CAN(CDC_CLOSE_TRAY))
cdi->options |= CDO_AUTO_CLOSE;
else if (!autoclose)
else
cdi->options &= ~CDO_CHECK_TYPE;
}
+ mutex_unlock(&cdrom_mutex);
}
static int cdrom_sysctl_handler(ctl_table *ctl, int write, struct file * filp,
unregister_sysctl_table(cdrom_sysctl_header);
}
+#else /* CONFIG_SYSCTL */
+
+static void cdrom_sysctl_register(void)
+{
+}
+
+static void cdrom_sysctl_unregister(void)
+{
+}
+
#endif /* CONFIG_SYSCTL */
static int __init cdrom_init(void)
{
-#ifdef CONFIG_SYSCTL
cdrom_sysctl_register();
-#endif
+
return 0;
}
static void __exit cdrom_exit(void)
{
printk(KERN_INFO "Uniform CD-ROM driver unloaded\n");
-#ifdef CONFIG_SYSCTL
cdrom_sysctl_unregister();
-#endif
}
module_init(cdrom_init);
del_gendisk(gd.disk);
if (gdrom_major)
unregister_blkdev(gdrom_major, GDROM_DEV_NAME);
- return unregister_cdrom(gd.cd_info);
+ unregister_cdrom(gd.cd_info);
+
+ return 0;
}
static struct platform_driver gdrom_driver = {
{
struct disk_info *d = &viocd_diskinfo[vdev->unit_address];
- if (unregister_cdrom(&d->viocd_info) != 0)
- printk(VIOCD_KERN_WARNING
- "Cannot unregister viocd CD-ROM %s!\n",
- d->viocd_info.name);
+ unregister_cdrom(&d->viocd_info);
del_gendisk(d->viocd_disk);
blk_cleanup_queue(d->viocd_disk->queue);
put_disk(d->viocd_disk);
config RTC
tristate "Enhanced Real Time Clock Support"
- depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV && !ARM && !SUPERH && !S390
+ depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV && !ARM && !SUPERH && !S390 && !AVR32
---help---
If you say Y here and create a character special file /dev/rtc with
major number 10 and minor number 135 using mknod ("man mknod"), you
config GEN_RTC
tristate "Generic /dev/rtc emulation"
- depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH
+ depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH && !AVR32
---help---
If you say Y here and create a character special file /dev/rtc with
major number 10 and minor number 135 using mknod ("man mknod"), you
struct drm_device *dev;
struct proc_dir_entry *dev_root; /**< proc directory entry */
dev_t device; /**< Device number for mknod */
- struct class_device *dev_class;
};
/**
#include <linux/interrupt.h>
#include <linux/tty_flip.h>
#include <linux/delay.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#define DEBUG
for (rest = cnt; rest > 0; rest -= nlen) {
nlen = (rest > 16) ? 16 : rest;
memcpy(kb, buf, nlen);
- beat_put_term_char(vtermno, rest, kb[0], kb[1]);
- rest -= nlen;
+ beat_put_term_char(vtermno, nlen, kb[0], kb[1]);
+ buf += nlen;
}
return cnt;
}
NULL);
-static void unregister_miscdev(bool suspended)
+static void unregister_miscdev(void)
{
device_remove_file(rng_miscdev.this_device, &dev_attr_rng_available);
device_remove_file(rng_miscdev.this_device, &dev_attr_rng_current);
- __misc_deregister(&rng_miscdev, suspended);
+ misc_deregister(&rng_miscdev);
}
static int register_miscdev(void)
}
EXPORT_SYMBOL_GPL(hwrng_register);
-void __hwrng_unregister(struct hwrng *rng, bool suspended)
+void hwrng_unregister(struct hwrng *rng)
{
int err;
}
}
if (list_empty(&rng_list))
- unregister_miscdev(suspended);
+ unregister_miscdev();
mutex_unlock(&rng_mutex);
}
-EXPORT_SYMBOL_GPL(__hwrng_unregister);
+EXPORT_SYMBOL_GPL(hwrng_unregister);
MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver");
/*
- * drivers/char/hw_random/omap-rng.c
- *
- * RNG driver for TI OMAP CPU family
+ * omap-rng.c - RNG driver for TI OMAP CPU family
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
- *
- * TODO:
- *
- * - Make status updated be interrupt driven so we don't poll
- *
*/
#include <linux/module.h>
static struct clk *rng_ick;
static struct platform_device *rng_dev;
-static u32 omap_rng_read_reg(int reg)
+static inline u32 omap_rng_read_reg(int reg)
{
return __raw_readl(rng_base + reg);
}
-static void omap_rng_write_reg(int reg, u32 val)
+static inline void omap_rng_write_reg(int reg, u32 val)
{
__raw_writel(val, rng_base + reg);
}
-/* REVISIT: Does the status bit really work on 16xx? */
static int omap_rng_data_present(struct hwrng *rng, int wait)
{
int data, i;
data = omap_rng_read_reg(RNG_STAT_REG) ? 0 : 1;
if (data || !wait)
break;
+ /* RNG produces data fast enough (2+ MBit/sec, even
+ * during "rngtest" loads, that these delays don't
+ * seem to trigger. We *could* use the RNG IRQ, but
+ * that'd be higher overhead ... so why bother?
+ */
udelay(10);
}
return data;
* A bit ugly, and it will never actually happen but there can
* be only one RNG and this catches any bork
*/
- BUG_ON(rng_dev);
+ if (rng_dev)
+ return -EBUSY;
if (cpu_is_omap24xx()) {
rng_ick = clk_get(NULL, "rng_ick");
return -EBUSY;
dev_set_drvdata(&pdev->dev, mem);
- rng_base = (u32 __iomem *)io_p2v(res->start);
+ rng_base = (u32 __force __iomem *)io_p2v(res->start);
ret = hwrng_register(&omap_rng_ops);
if (ret) {
#endif
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:omap_rng");
static struct platform_driver omap_rng_driver = {
.driver = {
#if defined(CONFIG_X86) || defined(CONFIG_IA64) || defined(CONFIG_ALPHA) ||\
defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_SPARC) ||\
defined(CONFIG_PARISC) || defined(CONFIG_SUPERH) ||\
- (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC))
+ (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC)) ||\
+ defined(CONFIG_AVR32)
#define HW_RAW(dev) (test_bit(EV_MSC, dev->evbit) && test_bit(MSC_RAW, dev->mscbit) &&\
((dev)->id.bustype == BUS_I8042) && ((dev)->id.vendor == 0x0001) && ((dev)->id.product == 0x0001))
}
/**
- * __misc_deregister - unregister a miscellaneous device
+ * misc_deregister - unregister a miscellaneous device
* @misc: device to unregister
- * @suspended: to be set if the function is used during suspend/resume
*
* Unregister a miscellaneous device that was previously
* successfully registered with misc_register(). Success
* indicates an error.
*/
-int __misc_deregister(struct miscdevice *misc, bool suspended)
+int misc_deregister(struct miscdevice *misc)
{
int i = misc->minor;
mutex_lock(&misc_mtx);
list_del(&misc->list);
- if (suspended)
- destroy_suspended_device(misc_class,
- MKDEV(MISC_MAJOR, misc->minor));
- else
- device_destroy(misc_class, MKDEV(MISC_MAJOR, misc->minor));
+ device_destroy(misc_class, MKDEV(MISC_MAJOR, misc->minor));
if (i < DYNAMIC_MINORS && i>0) {
misc_minors[i>>3] &= ~(1 << (misc->minor & 7));
}
}
EXPORT_SYMBOL(misc_register);
-EXPORT_SYMBOL(__misc_deregister);
+EXPORT_SYMBOL(misc_deregister);
static int __init misc_init(void)
{
static irqreturn_t UartInterrupt(int irq, void *dev_id)
{
+ int irqno = (int)(unsigned long) dev_id;
+
PRINTK_3(TRACE_TP3780I,
- "tp3780i::UartInterrupt entry irq %x dev_id %p\n", irq, dev_id);
+ "tp3780i::UartInterrupt entry irq %x dev_id %p\n", irqno, dev_id);
return IRQ_HANDLED;
}
static irqreturn_t DspInterrupt(int irq, void *dev_id)
{
+ int irqno = (int)(unsigned long) dev_id;
+
pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd;
DSP_3780I_CONFIG_SETTINGS *pSettings = &pDrvData->rBDData.rDspSettings;
unsigned short usDspBaseIO = pSettings->usDspBaseIO;
unsigned short usIPCSource = 0, usIsolationMask, usPCNum;
PRINTK_3(TRACE_TP3780I,
- "tp3780i::DspInterrupt entry irq %x dev_id %p\n", irq, dev_id);
+ "tp3780i::DspInterrupt entry irq %x dev_id %p\n", irqno, dev_id);
if (dsp3780I_GetIPCSource(usDspBaseIO, &usIPCSource) == 0) {
PRINTK_2(TRACE_TP3780I,
pSettings->bPllBypass = TP_CFG_PllBypass;
pSettings->usChipletEnable = TP_CFG_ChipletEnable;
- if (request_irq(pSettings->usUartIrq, &UartInterrupt, 0, "mwave_uart", NULL)) {
+ if (request_irq(pSettings->usUartIrq, &UartInterrupt, 0, "mwave_uart",
+ (void *)(unsigned long) pSettings->usUartIrq)) {
PRINTK_ERROR(KERN_ERR_MWAVE "tp3780i::tp3780I_EnableDSP: Error: Could not get UART IRQ %x\n", pSettings->usUartIrq);
goto exit_cleanup;
} else { /* no conflict just release */
free_irq(pSettings->usUartIrq, NULL);
}
- if (request_irq(pSettings->usDspIrq, &DspInterrupt, 0, "mwave_3780i", NULL)) {
+ if (request_irq(pSettings->usDspIrq, &DspInterrupt, 0, "mwave_3780i",
+ (void *)(unsigned long) pSettings->usDspIrq)) {
PRINTK_ERROR("tp3780i::tp3780I_EnableDSP: Error: Could not get 3780i IRQ %x\n", pSettings->usDspIrq);
goto exit_cleanup;
} else {
* irq interrupt number that caused interrupt
* dev_id device ID supplied during interrupt registration
*/
-static irqreturn_t mgslpc_isr(int irq, void *dev_id)
+static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
{
- MGSLPC_INFO * info = (MGSLPC_INFO *)dev_id;
+ MGSLPC_INFO *info = dev_id;
unsigned short isr;
unsigned char gis, pis;
int count=0;
if (debug_level >= DEBUG_LEVEL_ISR)
- printk("mgslpc_isr(%d) entry.\n", irq);
- if (!info)
- return IRQ_NONE;
+ printk("mgslpc_isr(%d) entry.\n", info->irq_level);
if (!(info->p_dev->_locked))
return IRQ_HANDLED;
if (debug_level >= DEBUG_LEVEL_ISR)
printk("%s(%d):mgslpc_isr(%d)exit.\n",
- __FILE__,__LINE__,irq);
+ __FILE__, __LINE__, info->irq_level);
return IRQ_HANDLED;
}
#include <linux/termios.h>
#include <linux/serial.h>
#include <linux/vmalloc.h>
-#include <asm/semaphore.h>
#include <linux/generic_serial.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/string.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <linux/termios.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/string.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <linux/termios.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/string.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <linux/termios.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/string.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <linux/termios.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/string.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <linux/termios.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/string.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <linux/termios.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/string.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <linux/termios.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/string.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <linux/termios.h>
#include <linux/kobject.h>
#include <linux/fs.h>
#include <linux/cdev.h>
+#include <linux/semaphore.h>
#include <asm/sn/types.h>
-#include <asm/semaphore.h>
#define CHUNKSIZE 127
return 0;
}
-const static struct acpi_device_id sonypi_device_ids[] = {
+static const struct acpi_device_id sonypi_device_ids[] = {
{"SNY6001", 0},
{"", 0},
};
spin_unlock_irqrestore(&bp->lock, flags);
if (irq) {
printk (KERN_INFO "Missed interrupt... Calling int from timer. \n");
- sx_interrupt (((struct specialix_board *)data)->irq,
- (void*)data);
+ sx_interrupt (-1, bp);
}
mod_timer(&missed_irq_timer, jiffies + sx_poll);
}
/* The main interrupt processing routine */
-static irqreturn_t sx_interrupt(int irq, void *dev_id)
+static irqreturn_t sx_interrupt(int dummy, void *dev_id)
{
unsigned char status;
unsigned char ack;
- struct specialix_board *bp;
+ struct specialix_board *bp = dev_id;
unsigned long loop = 0;
int saved_reg;
unsigned long flags;
func_enter();
- bp = dev_id;
spin_lock_irqsave(&bp->lock, flags);
dprintk (SX_DEBUG_FLOW, "enter %s port %d room: %ld\n", __FUNCTION__, port_No(sx_get_port(bp, "INT")), SERIAL_XMIT_SIZE - sx_get_port(bp, "ITN")->xmit_cnt - 1);
if (!(bp->flags & SX_BOARD_ACTIVE)) {
- dprintk (SX_DEBUG_IRQ, "sx: False interrupt. irq %d.\n", irq);
+ dprintk (SX_DEBUG_IRQ, "sx: False interrupt. irq %d.\n", bp->irq);
spin_unlock_irqrestore(&bp->lock, flags);
func_exit();
return IRQ_NONE;
{
struct stlbrd *brdp = dev_id;
- pr_debug("stl_intr(brdp=%p,irq=%d)\n", brdp, irq);
+ pr_debug("stl_intr(brdp=%p,irq=%d)\n", brdp, brdp->irq);
return IRQ_RETVAL((* brdp->isr)(brdp));
}
*
* Return Value: None
*/
-static irqreturn_t mgsl_interrupt(int irq, void *dev_id)
+static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
{
- struct mgsl_struct * info;
+ struct mgsl_struct *info = dev_id;
u16 UscVector;
u16 DmaVector;
if ( debug_level >= DEBUG_LEVEL_ISR )
- printk("%s(%d):mgsl_interrupt(%d)entry.\n",
- __FILE__,__LINE__,irq);
+ printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
+ __FILE__, __LINE__, info->irq_level);
- info = (struct mgsl_struct *)dev_id;
- if (!info)
- return IRQ_NONE;
-
spin_lock(&info->irq_spinlock);
for(;;) {
mgsl_isr_receive_dma(info);
if ( info->isr_overflow ) {
- printk(KERN_ERR"%s(%d):%s isr overflow irq=%d\n",
- __FILE__,__LINE__,info->device_name, irq);
+ printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
+ __FILE__, __LINE__, info->device_name, info->irq_level);
usc_DisableMasterIrqBit(info);
usc_DisableDmaInterrupts(info,DICR_MASTER);
break;
spin_unlock(&info->irq_spinlock);
if ( debug_level >= DEBUG_LEVEL_ISR )
- printk("%s(%d):mgsl_interrupt(%d)exit.\n",
- __FILE__,__LINE__,irq);
+ printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
+ __FILE__, __LINE__, info->irq_level);
+
return IRQ_HANDLED;
} /* end of mgsl_interrupt() */
static void isr_rdma(struct slgt_info *info);
static void isr_txeom(struct slgt_info *info, unsigned short status);
static void isr_tdma(struct slgt_info *info);
-static irqreturn_t slgt_interrupt(int irq, void *dev_id);
static int alloc_dma_bufs(struct slgt_info *info);
static void free_dma_bufs(struct slgt_info *info);
* irq interrupt number
* dev_id device ID supplied during interrupt registration
*/
-static irqreturn_t slgt_interrupt(int irq, void *dev_id)
+static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
{
- struct slgt_info *info;
+ struct slgt_info *info = dev_id;
unsigned int gsr;
unsigned int i;
- DBGISR(("slgt_interrupt irq=%d entry\n", irq));
-
- info = dev_id;
- if (!info)
- return IRQ_NONE;
+ DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
spin_lock(&info->lock);
spin_unlock(&info->lock);
- DBGISR(("slgt_interrupt irq=%d exit\n", irq));
+ DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
return IRQ_HANDLED;
}
* dev_id device ID supplied during interrupt registration
* regs interrupted processor context
*/
-static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id)
+static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
{
- SLMP_INFO * info;
+ SLMP_INFO *info = dev_id;
unsigned char status, status0, status1=0;
unsigned char dmastatus, dmastatus0, dmastatus1=0;
unsigned char timerstatus0, timerstatus1=0;
unsigned short tmp;
if ( debug_level >= DEBUG_LEVEL_ISR )
- printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
- __FILE__,__LINE__,irq);
-
- info = (SLMP_INFO *)dev_id;
- if (!info)
- return IRQ_NONE;
+ printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
+ __FILE__, __LINE__, info->irq_level);
spin_lock(&info->lock);
timerstatus0 = read_reg(info, ISR2);
if ( debug_level >= DEBUG_LEVEL_ISR )
- printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
- __FILE__,__LINE__,info->device_name,
- status0,dmastatus0,timerstatus0);
+ printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
+ __FILE__, __LINE__, info->device_name,
+ status0, dmastatus0, timerstatus0);
if (info->port_count == 4) {
/* get status for SCA1 (ports 2-3) */
spin_unlock(&info->lock);
if ( debug_level >= DEBUG_LEVEL_ISR )
- printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
- __FILE__,__LINE__,irq);
+ printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
+ __FILE__, __LINE__, info->irq_level);
return IRQ_HANDLED;
}
return IRQ_HANDLED;
}
-static irqreturn_t tis_int_handler(int irq, void *dev_id)
+static irqreturn_t tis_int_handler(int dummy, void *dev_id)
{
struct tpm_chip *chip = dev_id;
u32 interrupt;
/**
* buffer_icap_get_status - Get the contents of the status register.
- * @base_address: is the base address of the device
+ * @drvdata: a pointer to the drvdata.
*
* The status register contains the ICAP status and the done bit.
*
* D1 - Always 1
* D0 - Done bit
**/
-static inline u32 buffer_icap_get_status(void __iomem *base_address)
+u32 buffer_icap_get_status(struct hwicap_drvdata *drvdata)
{
- return in_be32(base_address + XHI_STATUS_REG_OFFSET);
+ return in_be32(drvdata->base_address + XHI_STATUS_REG_OFFSET);
}
/**
**/
static inline bool buffer_icap_busy(void __iomem *base_address)
{
- return (buffer_icap_get_status(base_address) & 1) == XHI_NOT_FINISHED;
-}
-
-/**
- * buffer_icap_busy - Return true if the icap device is not busy
- * @base_address: is the base address of the device
- *
- * The queries the low order bit of the status register, which
- * indicates whether the current configuration or readback operation
- * has completed.
- **/
-static inline bool buffer_icap_done(void __iomem *base_address)
-{
- return (buffer_icap_get_status(base_address) & 1) == XHI_FINISHED;
+ u32 status = in_be32(base_address + XHI_STATUS_REG_OFFSET);
+ return (status & 1) == XHI_NOT_FINISHED;
}
/**
#include <asm/io.h>
#include "xilinx_hwicap.h"
-void buffer_icap_reset(struct hwicap_drvdata *drvdata);
-
/* Loads a partial bitstream from system memory. */
int buffer_icap_set_configuration(struct hwicap_drvdata *drvdata, u32 *data,
u32 Size);
int buffer_icap_get_configuration(struct hwicap_drvdata *drvdata, u32 *data,
u32 Size);
+u32 buffer_icap_get_status(struct hwicap_drvdata *drvdata);
+void buffer_icap_reset(struct hwicap_drvdata *drvdata);
+
#endif
#define XHI_CR_READ_MASK 0x00000002 /* Read from ICAP to FIFO */
#define XHI_CR_WRITE_MASK 0x00000001 /* Write from FIFO to ICAP */
-/* Status Register (SR) */
-#define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */
-#define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */
-#define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */
-#define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */
-#define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask */
-
#define XHI_WFO_MAX_VACANCY 1024 /* Max Write FIFO Vacancy, in words */
#define XHI_RFO_MAX_OCCUPANCY 256 /* Max Read FIFO Occupancy, in words */
dev_dbg(drvdata->dev, "readback started\n");
}
+/**
+ * fifo_icap_get_status - Get the contents of the status register.
+ * @drvdata: a pointer to the drvdata.
+ *
+ * The status register contains the ICAP status and the done bit.
+ *
+ * D8 - cfgerr
+ * D7 - dalign
+ * D6 - rip
+ * D5 - in_abort_l
+ * D4 - Always 1
+ * D3 - Always 1
+ * D2 - Always 1
+ * D1 - Always 1
+ * D0 - Done bit
+ **/
+u32 fifo_icap_get_status(struct hwicap_drvdata *drvdata)
+{
+ u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET);
+ dev_dbg(drvdata->dev, "Getting status = %x\n", status);
+ return status;
+}
+
/**
* fifo_icap_busy - Return true if the ICAP is still processing a transaction.
* @drvdata: a pointer to the drvdata.
static inline u32 fifo_icap_busy(struct hwicap_drvdata *drvdata)
{
u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET);
- dev_dbg(drvdata->dev, "Getting status = %x\n", status);
return (status & XHI_SR_DONE_MASK) ? 0 : 1;
}
u32 *FrameBuffer,
u32 NumWords);
+u32 fifo_icap_get_status(struct hwicap_drvdata *drvdata);
void fifo_icap_reset(struct hwicap_drvdata *drvdata);
void fifo_icap_flush_fifo(struct hwicap_drvdata *drvdata);
*****************************************************************************/
/*
- * This is the code behind /dev/xilinx_icap -- it allows a user-space
+ * This is the code behind /dev/icap* -- it allows a user-space
* application to use the Xilinx ICAP subsystem.
*
* The following operations are possible:
* user-space application code that uses this device. The simplest
* way to use this interface is simply:
*
- * cp foo.bit /dev/xilinx_icap
+ * cp foo.bit /dev/icap0
*
* Note that unless foo.bit is an appropriately constructed partial
* bitstream, this has a high likelyhood of overwriting the design
#include "buffer_icap.h"
#include "fifo_icap.h"
-#define DRIVER_NAME "xilinx_icap"
+#define DRIVER_NAME "icap"
#define HWICAP_REGS (0x10000)
-/* dynamically allocate device number */
-static int xhwicap_major;
-static int xhwicap_minor;
+#define XHWICAP_MAJOR 259
+#define XHWICAP_MINOR 0
#define HWICAP_DEVICES 1
-module_param(xhwicap_major, int, S_IRUGO);
-module_param(xhwicap_minor, int, S_IRUGO);
-
/* An array, which is set to true when the device is registered. */
static bool probed_devices[HWICAP_DEVICES];
static struct mutex icap_sem;
* Create the data to be written to the ICAP.
*/
buffer[index++] = XHI_DUMMY_PACKET;
+ buffer[index++] = XHI_NOOP_PACKET;
buffer[index++] = XHI_SYNC_PACKET;
buffer[index++] = XHI_NOOP_PACKET;
+ buffer[index++] = XHI_NOOP_PACKET;
+
+ /*
+ * Write the data to the FIFO and initiate the transfer of data present
+ * in the FIFO to the ICAP device.
+ */
+ status = drvdata->config->set_configuration(drvdata,
+ &buffer[0], index);
+ if (status)
+ return status;
+
+ /* If the syncword was not found, then we need to start over. */
+ status = drvdata->config->get_status(drvdata);
+ if ((status & XHI_SR_DALIGN_MASK) != XHI_SR_DALIGN_MASK)
+ return -EIO;
+
+ index = 0;
buffer[index++] = hwicap_type_1_read(reg) | 1;
buffer[index++] = XHI_NOOP_PACKET;
buffer[index++] = XHI_NOOP_PACKET;
probed_devices[id] = 1;
mutex_unlock(&icap_sem);
- devt = MKDEV(xhwicap_major, xhwicap_minor + id);
+ devt = MKDEV(XHWICAP_MAJOR, XHWICAP_MINOR + id);
drvdata = kzalloc(sizeof(struct hwicap_drvdata), GFP_KERNEL);
if (!drvdata) {
static struct hwicap_driver_config buffer_icap_config = {
.get_configuration = buffer_icap_get_configuration,
.set_configuration = buffer_icap_set_configuration,
+ .get_status = buffer_icap_get_status,
.reset = buffer_icap_reset,
};
static struct hwicap_driver_config fifo_icap_config = {
.get_configuration = fifo_icap_get_configuration,
.set_configuration = fifo_icap_set_configuration,
+ .get_status = fifo_icap_get_status,
.reset = fifo_icap_reset,
};
dev_set_drvdata(dev, NULL);
mutex_lock(&icap_sem);
- probed_devices[MINOR(dev->devt)-xhwicap_minor] = 0;
+ probed_devices[MINOR(dev->devt)-XHWICAP_MINOR] = 0;
mutex_unlock(&icap_sem);
return 0; /* success */
}
icap_class = class_create(THIS_MODULE, "xilinx_config");
mutex_init(&icap_sem);
- if (xhwicap_major) {
- devt = MKDEV(xhwicap_major, xhwicap_minor);
- retval = register_chrdev_region(
- devt,
- HWICAP_DEVICES,
- DRIVER_NAME);
- if (retval < 0)
- return retval;
- } else {
- retval = alloc_chrdev_region(&devt,
- xhwicap_minor,
- HWICAP_DEVICES,
- DRIVER_NAME);
- if (retval < 0)
- return retval;
- xhwicap_major = MAJOR(devt);
- }
+ devt = MKDEV(XHWICAP_MAJOR, XHWICAP_MINOR);
+ retval = register_chrdev_region(devt,
+ HWICAP_DEVICES,
+ DRIVER_NAME);
+ if (retval < 0)
+ return retval;
retval = platform_driver_register(&hwicap_platform_driver);
static void __exit hwicap_module_cleanup(void)
{
- dev_t devt = MKDEV(xhwicap_major, xhwicap_minor);
+ dev_t devt = MKDEV(XHWICAP_MAJOR, XHWICAP_MINOR);
class_destroy(icap_class);
};
struct hwicap_driver_config {
+ /* Read configuration data given by size into the data buffer.
+ Return 0 if successful. */
int (*get_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
u32 size);
+ /* Write configuration data given by size from the data buffer.
+ Return 0 if successful. */
int (*set_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
u32 size);
+ /* Get the status register, bit pattern given by:
+ * D8 - 0 = configuration error
+ * D7 - 1 = alignment found
+ * D6 - 1 = readback in progress
+ * D5 - 0 = abort in progress
+ * D4 - Always 1
+ * D3 - Always 1
+ * D2 - Always 1
+ * D1 - Always 1
+ * D0 - 1 = operation completed
+ */
+ u32 (*get_status)(struct hwicap_drvdata *drvdata);
+ /* Reset the hw */
void (*reset)(struct hwicap_drvdata *drvdata);
};
/* Constant to use for CRC check when CRC has been disabled */
#define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL
+/* Meanings of the bits returned by get_status */
+#define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */
+#define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */
+#define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */
+#define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */
+#define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask */
+
/**
* hwicap_type_1_read - Generates a Type 1 read packet header.
* @reg: is the address of the register to be read back.
+obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
--- /dev/null
+#include <linux/init.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/atmel_tc.h>
+
+
+/*
+ * We're configured to use a specific TC block, one that's not hooked
+ * up to external hardware, to provide a time solution:
+ *
+ * - Two channels combine to create a free-running 32 bit counter
+ * with a base rate of 5+ MHz, packaged as a clocksource (with
+ * resolution better than 200 nsec).
+ *
+ * - The third channel may be used to provide a 16-bit clockevent
+ * source, used in either periodic or oneshot mode. This runs
+ * at 32 KiHZ, and can handle delays of up to two seconds.
+ *
+ * A boot clocksource and clockevent source are also currently needed,
+ * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
+ * this code can be used when init_timers() is called, well before most
+ * devices are set up. (Some low end AT91 parts, which can run uClinux,
+ * have only the timers in one TC block... they currently don't support
+ * the tclib code, because of that initialization issue.)
+ *
+ * REVISIT behavior during system suspend states... we should disable
+ * all clocks and save the power. Easily done for clockevent devices,
+ * but clocksources won't necessarily get the needed notifications.
+ * For deeper system sleep states, this will be mandatory...
+ */
+
+static void __iomem *tcaddr;
+
+static cycle_t tc_get_cycles(void)
+{
+ unsigned long flags;
+ u32 lower, upper;
+
+ raw_local_irq_save(flags);
+ do {
+ upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
+ lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
+ } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
+
+ raw_local_irq_restore(flags);
+ return (upper << 16) | lower;
+}
+
+static struct clocksource clksrc = {
+ .name = "tcb_clksrc",
+ .rating = 200,
+ .read = tc_get_cycles,
+ .mask = CLOCKSOURCE_MASK(32),
+ .shift = 18,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+#ifdef CONFIG_GENERIC_CLOCKEVENTS
+
+struct tc_clkevt_device {
+ struct clock_event_device clkevt;
+ struct clk *clk;
+ void __iomem *regs;
+};
+
+static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
+{
+ return container_of(clkevt, struct tc_clkevt_device, clkevt);
+}
+
+/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
+ * because using one of the divided clocks would usually mean the
+ * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
+ *
+ * A divided clock could be good for high resolution timers, since
+ * 30.5 usec resolution can seem "low".
+ */
+static u32 timer_clock;
+
+static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
+{
+ struct tc_clkevt_device *tcd = to_tc_clkevt(d);
+ void __iomem *regs = tcd->regs;
+
+ if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
+ || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
+ __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
+ __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
+ clk_disable(tcd->clk);
+ }
+
+ switch (m) {
+
+ /* By not making the gentime core emulate periodic mode on top
+ * of oneshot, we get lower overhead and improved accuracy.
+ */
+ case CLOCK_EVT_MODE_PERIODIC:
+ clk_enable(tcd->clk);
+
+ /* slow clock, count up to RC, then irq and restart */
+ __raw_writel(timer_clock
+ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
+ regs + ATMEL_TC_REG(2, CMR));
+ __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
+
+ /* Enable clock and interrupts on RC compare */
+ __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+
+ /* go go gadget! */
+ __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+ regs + ATMEL_TC_REG(2, CCR));
+ break;
+
+ case CLOCK_EVT_MODE_ONESHOT:
+ clk_enable(tcd->clk);
+
+ /* slow clock, count up to RC, then irq and stop */
+ __raw_writel(timer_clock | ATMEL_TC_CPCSTOP
+ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
+ regs + ATMEL_TC_REG(2, CMR));
+ __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+
+ /* set_next_event() configures and starts the timer */
+ break;
+
+ default:
+ break;
+ }
+}
+
+static int tc_next_event(unsigned long delta, struct clock_event_device *d)
+{
+ __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
+
+ /* go go gadget! */
+ __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
+ tcaddr + ATMEL_TC_REG(2, CCR));
+ return 0;
+}
+
+static struct tc_clkevt_device clkevt = {
+ .clkevt = {
+ .name = "tc_clkevt",
+ .features = CLOCK_EVT_FEAT_PERIODIC
+ | CLOCK_EVT_FEAT_ONESHOT,
+ .shift = 32,
+ /* Should be lower than at91rm9200's system timer */
+ .rating = 125,
+ .cpumask = CPU_MASK_CPU0,
+ .set_next_event = tc_next_event,
+ .set_mode = tc_mode,
+ },
+};
+
+static irqreturn_t ch2_irq(int irq, void *handle)
+{
+ struct tc_clkevt_device *dev = handle;
+ unsigned int sr;
+
+ sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
+ if (sr & ATMEL_TC_CPCS) {
+ dev->clkevt.event_handler(&dev->clkevt);
+ return IRQ_HANDLED;
+ }
+
+ return IRQ_NONE;
+}
+
+static struct irqaction tc_irqaction = {
+ .name = "tc_clkevt",
+ .flags = IRQF_TIMER | IRQF_DISABLED,
+ .handler = ch2_irq,
+};
+
+static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
+{
+ struct clk *t2_clk = tc->clk[2];
+ int irq = tc->irq[2];
+
+ clkevt.regs = tc->regs;
+ clkevt.clk = t2_clk;
+ tc_irqaction.dev_id = &clkevt;
+
+ timer_clock = clk32k_divisor_idx;
+
+ clkevt.clkevt.mult = div_sc(32768, NSEC_PER_SEC, clkevt.clkevt.shift);
+ clkevt.clkevt.max_delta_ns
+ = clockevent_delta2ns(0xffff, &clkevt.clkevt);
+ clkevt.clkevt.min_delta_ns = clockevent_delta2ns(1, &clkevt.clkevt) + 1;
+
+ setup_irq(irq, &tc_irqaction);
+
+ clockevents_register_device(&clkevt.clkevt);
+}
+
+#else /* !CONFIG_GENERIC_CLOCKEVENTS */
+
+static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
+{
+ /* NOTHING */
+}
+
+#endif
+
+static int __init tcb_clksrc_init(void)
+{
+ static char bootinfo[] __initdata
+ = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
+
+ struct platform_device *pdev;
+ struct atmel_tc *tc;
+ struct clk *t0_clk;
+ u32 rate, divided_rate = 0;
+ int best_divisor_idx = -1;
+ int clk32k_divisor_idx = -1;
+ int i;
+
+ tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
+ if (!tc) {
+ pr_debug("can't alloc TC for clocksource\n");
+ return -ENODEV;
+ }
+ tcaddr = tc->regs;
+ pdev = tc->pdev;
+
+ t0_clk = tc->clk[0];
+ clk_enable(t0_clk);
+
+ /* How fast will we be counting? Pick something over 5 MHz. */
+ rate = (u32) clk_get_rate(t0_clk);
+ for (i = 0; i < 5; i++) {
+ unsigned divisor = atmel_tc_divisors[i];
+ unsigned tmp;
+
+ /* remember 32 KiHz clock for later */
+ if (!divisor) {
+ clk32k_divisor_idx = i;
+ continue;
+ }
+
+ tmp = rate / divisor;
+ pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
+ if (best_divisor_idx > 0) {
+ if (tmp < 5 * 1000 * 1000)
+ continue;
+ }
+ divided_rate = tmp;
+ best_divisor_idx = i;
+ }
+
+ clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
+
+ printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
+ divided_rate / 1000000,
+ ((divided_rate + 500000) % 1000000) / 1000);
+
+ /* tclib will give us three clocks no matter what the
+ * underlying platform supports.
+ */
+ clk_enable(tc->clk[1]);
+
+ /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
+ __raw_writel(best_divisor_idx /* likely divide-by-8 */
+ | ATMEL_TC_WAVE
+ | ATMEL_TC_WAVESEL_UP /* free-run */
+ | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
+ | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
+ tcaddr + ATMEL_TC_REG(0, CMR));
+ __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
+ __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
+ __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
+ __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+
+ /* channel 1: waveform mode, input TIOA0 */
+ __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
+ | ATMEL_TC_WAVE
+ | ATMEL_TC_WAVESEL_UP, /* free-run */
+ tcaddr + ATMEL_TC_REG(1, CMR));
+ __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
+ __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
+
+ /* chain channel 0 to channel 1, then reset all the timers */
+ __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
+ __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+
+ /* and away we go! */
+ clocksource_register(&clksrc);
+
+ /* channel 2: periodic and oneshot timer support */
+ setup_clkevents(tc, clk32k_divisor_idx);
+
+ return 0;
+}
+arch_initcall(tcb_clksrc_init);
tristate "PadLock driver for AES algorithm"
depends on CRYPTO_DEV_PADLOCK
select CRYPTO_BLKCIPHER
+ select CRYPTO_AES
help
Use VIA PadLock for AES algorithm.
This version of SHA implements a 256 bit hash with 128 bits of
security against collision attacks.
+config CRYPTO_SHA512_S390
+ tristate "SHA384 and SHA512 digest algorithm"
+ depends on S390
+ select CRYPTO_ALGAPI
+ help
+ This is the s390 hardware accelerated implementation of the
+ SHA512 secure hash standard.
+
+ This version of SHA implements a 512 bit hash with 256 bits of
+ security against collision attacks. The code also includes SHA-384,
+ a 384 bit hash with 192 bits of security against collision attacks.
+
+
config CRYPTO_DES_S390
tristate "DES and Triple DES cipher algorithms"
depends on S390
*
* Copyright (c) 2004 Michal Ludvig <michal@logix.cz>
*
- * Key expansion routine taken from crypto/aes_generic.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * ---------------------------------------------------------------------------
- * Copyright (c) 2002, Dr Brian Gladman <brg@gladman.me.uk>, Worcester, UK.
- * All rights reserved.
- *
- * LICENSE TERMS
- *
- * The free distribution and use of this software in both source and binary
- * form is allowed (with or without changes) provided that:
- *
- * 1. distributions of this source code include the above copyright
- * notice, this list of conditions and the following disclaimer;
- *
- * 2. distributions in binary form include the above copyright
- * notice, this list of conditions and the following disclaimer
- * in the documentation and/or other associated materials;
- *
- * 3. the copyright holder's name is not used to endorse products
- * built using this software without specific written permission.
- *
- * ALTERNATIVELY, provided that this notice is retained in full, this product
- * may be distributed under the terms of the GNU General Public License (GPL),
- * in which case the provisions of the GPL apply INSTEAD OF those given above.
- *
- * DISCLAIMER
- *
- * This software is provided 'as is' with no explicit or implied warranties
- * in respect of its properties, including, but not limited to, correctness
- * and/or fitness for purpose.
- * ---------------------------------------------------------------------------
*/
#include <crypto/algapi.h>
#include <asm/byteorder.h>
#include "padlock.h"
-#define AES_EXTENDED_KEY_SIZE 64 /* in uint32_t units */
-#define AES_EXTENDED_KEY_SIZE_B (AES_EXTENDED_KEY_SIZE * sizeof(uint32_t))
-
/* Control word. */
struct cword {
unsigned int __attribute__ ((__packed__))
/* Whenever making any changes to the following
* structure *make sure* you keep E, d_data
- * and cword aligned on 16 Bytes boundaries!!! */
+ * and cword aligned on 16 Bytes boundaries and
+ * the Hardware can access 16 * 16 bytes of E and d_data
+ * (only the first 15 * 16 bytes matter but the HW reads
+ * more).
+ */
struct aes_ctx {
+ u32 E[AES_MAX_KEYLENGTH_U32]
+ __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
+ u32 d_data[AES_MAX_KEYLENGTH_U32]
+ __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
struct {
struct cword encrypt;
struct cword decrypt;
} cword;
u32 *D;
- int key_length;
- u32 E[AES_EXTENDED_KEY_SIZE]
- __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
- u32 d_data[AES_EXTENDED_KEY_SIZE]
- __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
};
-/* ====== Key management routines ====== */
-
-static inline uint32_t
-generic_rotr32 (const uint32_t x, const unsigned bits)
-{
- const unsigned n = bits % 32;
- return (x >> n) | (x << (32 - n));
-}
-
-static inline uint32_t
-generic_rotl32 (const uint32_t x, const unsigned bits)
-{
- const unsigned n = bits % 32;
- return (x << n) | (x >> (32 - n));
-}
-
-#define rotl generic_rotl32
-#define rotr generic_rotr32
-
-/*
- * #define byte(x, nr) ((unsigned char)((x) >> (nr*8)))
- */
-static inline uint8_t
-byte(const uint32_t x, const unsigned n)
-{
- return x >> (n << 3);
-}
-
-#define E_KEY ctx->E
-#define D_KEY ctx->D
-
-static uint8_t pow_tab[256];
-static uint8_t log_tab[256];
-static uint8_t sbx_tab[256];
-static uint8_t isb_tab[256];
-static uint32_t rco_tab[10];
-static uint32_t ft_tab[4][256];
-static uint32_t it_tab[4][256];
-
-static uint32_t fl_tab[4][256];
-static uint32_t il_tab[4][256];
-
-static inline uint8_t
-f_mult (uint8_t a, uint8_t b)
-{
- uint8_t aa = log_tab[a], cc = aa + log_tab[b];
-
- return pow_tab[cc + (cc < aa ? 1 : 0)];
-}
-
-#define ff_mult(a,b) (a && b ? f_mult(a, b) : 0)
-
-#define f_rn(bo, bi, n, k) \
- bo[n] = ft_tab[0][byte(bi[n],0)] ^ \
- ft_tab[1][byte(bi[(n + 1) & 3],1)] ^ \
- ft_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
- ft_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n)
-
-#define i_rn(bo, bi, n, k) \
- bo[n] = it_tab[0][byte(bi[n],0)] ^ \
- it_tab[1][byte(bi[(n + 3) & 3],1)] ^ \
- it_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
- it_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n)
-
-#define ls_box(x) \
- ( fl_tab[0][byte(x, 0)] ^ \
- fl_tab[1][byte(x, 1)] ^ \
- fl_tab[2][byte(x, 2)] ^ \
- fl_tab[3][byte(x, 3)] )
-
-#define f_rl(bo, bi, n, k) \
- bo[n] = fl_tab[0][byte(bi[n],0)] ^ \
- fl_tab[1][byte(bi[(n + 1) & 3],1)] ^ \
- fl_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
- fl_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n)
-
-#define i_rl(bo, bi, n, k) \
- bo[n] = il_tab[0][byte(bi[n],0)] ^ \
- il_tab[1][byte(bi[(n + 3) & 3],1)] ^ \
- il_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
- il_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n)
-
-static void
-gen_tabs (void)
-{
- uint32_t i, t;
- uint8_t p, q;
-
- /* log and power tables for GF(2**8) finite field with
- 0x011b as modular polynomial - the simplest prmitive
- root is 0x03, used here to generate the tables */
-
- for (i = 0, p = 1; i < 256; ++i) {
- pow_tab[i] = (uint8_t) p;
- log_tab[p] = (uint8_t) i;
-
- p ^= (p << 1) ^ (p & 0x80 ? 0x01b : 0);
- }
-
- log_tab[1] = 0;
-
- for (i = 0, p = 1; i < 10; ++i) {
- rco_tab[i] = p;
-
- p = (p << 1) ^ (p & 0x80 ? 0x01b : 0);
- }
-
- for (i = 0; i < 256; ++i) {
- p = (i ? pow_tab[255 - log_tab[i]] : 0);
- q = ((p >> 7) | (p << 1)) ^ ((p >> 6) | (p << 2));
- p ^= 0x63 ^ q ^ ((q >> 6) | (q << 2));
- sbx_tab[i] = p;
- isb_tab[p] = (uint8_t) i;
- }
-
- for (i = 0; i < 256; ++i) {
- p = sbx_tab[i];
-
- t = p;
- fl_tab[0][i] = t;
- fl_tab[1][i] = rotl (t, 8);
- fl_tab[2][i] = rotl (t, 16);
- fl_tab[3][i] = rotl (t, 24);
-
- t = ((uint32_t) ff_mult (2, p)) |
- ((uint32_t) p << 8) |
- ((uint32_t) p << 16) | ((uint32_t) ff_mult (3, p) << 24);
-
- ft_tab[0][i] = t;
- ft_tab[1][i] = rotl (t, 8);
- ft_tab[2][i] = rotl (t, 16);
- ft_tab[3][i] = rotl (t, 24);
-
- p = isb_tab[i];
-
- t = p;
- il_tab[0][i] = t;
- il_tab[1][i] = rotl (t, 8);
- il_tab[2][i] = rotl (t, 16);
- il_tab[3][i] = rotl (t, 24);
-
- t = ((uint32_t) ff_mult (14, p)) |
- ((uint32_t) ff_mult (9, p) << 8) |
- ((uint32_t) ff_mult (13, p) << 16) |
- ((uint32_t) ff_mult (11, p) << 24);
-
- it_tab[0][i] = t;
- it_tab[1][i] = rotl (t, 8);
- it_tab[2][i] = rotl (t, 16);
- it_tab[3][i] = rotl (t, 24);
- }
-}
-
-#define star_x(x) (((x) & 0x7f7f7f7f) << 1) ^ ((((x) & 0x80808080) >> 7) * 0x1b)
-
-#define imix_col(y,x) \
- u = star_x(x); \
- v = star_x(u); \
- w = star_x(v); \
- t = w ^ (x); \
- (y) = u ^ v ^ w; \
- (y) ^= rotr(u ^ t, 8) ^ \
- rotr(v ^ t, 16) ^ \
- rotr(t,24)
-
-/* initialise the key schedule from the user supplied key */
-
-#define loop4(i) \
-{ t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \
- t ^= E_KEY[4 * i]; E_KEY[4 * i + 4] = t; \
- t ^= E_KEY[4 * i + 1]; E_KEY[4 * i + 5] = t; \
- t ^= E_KEY[4 * i + 2]; E_KEY[4 * i + 6] = t; \
- t ^= E_KEY[4 * i + 3]; E_KEY[4 * i + 7] = t; \
-}
-
-#define loop6(i) \
-{ t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \
- t ^= E_KEY[6 * i]; E_KEY[6 * i + 6] = t; \
- t ^= E_KEY[6 * i + 1]; E_KEY[6 * i + 7] = t; \
- t ^= E_KEY[6 * i + 2]; E_KEY[6 * i + 8] = t; \
- t ^= E_KEY[6 * i + 3]; E_KEY[6 * i + 9] = t; \
- t ^= E_KEY[6 * i + 4]; E_KEY[6 * i + 10] = t; \
- t ^= E_KEY[6 * i + 5]; E_KEY[6 * i + 11] = t; \
-}
-
-#define loop8(i) \
-{ t = rotr(t, 8); ; t = ls_box(t) ^ rco_tab[i]; \
- t ^= E_KEY[8 * i]; E_KEY[8 * i + 8] = t; \
- t ^= E_KEY[8 * i + 1]; E_KEY[8 * i + 9] = t; \
- t ^= E_KEY[8 * i + 2]; E_KEY[8 * i + 10] = t; \
- t ^= E_KEY[8 * i + 3]; E_KEY[8 * i + 11] = t; \
- t = E_KEY[8 * i + 4] ^ ls_box(t); \
- E_KEY[8 * i + 12] = t; \
- t ^= E_KEY[8 * i + 5]; E_KEY[8 * i + 13] = t; \
- t ^= E_KEY[8 * i + 6]; E_KEY[8 * i + 14] = t; \
- t ^= E_KEY[8 * i + 7]; E_KEY[8 * i + 15] = t; \
-}
-
/* Tells whether the ACE is capable to generate
the extended key for a given key_len. */
static inline int
struct aes_ctx *ctx = aes_ctx(tfm);
const __le32 *key = (const __le32 *)in_key;
u32 *flags = &tfm->crt_flags;
- uint32_t i, t, u, v, w;
- uint32_t P[AES_EXTENDED_KEY_SIZE];
- uint32_t rounds;
+ struct crypto_aes_ctx gen_aes;
if (key_len % 8) {
*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
return -EINVAL;
}
- ctx->key_length = key_len;
-
/*
* If the hardware is capable of generating the extended key
* itself we must supply the plain key for both encryption
*/
ctx->D = ctx->E;
- E_KEY[0] = le32_to_cpu(key[0]);
- E_KEY[1] = le32_to_cpu(key[1]);
- E_KEY[2] = le32_to_cpu(key[2]);
- E_KEY[3] = le32_to_cpu(key[3]);
+ ctx->E[0] = le32_to_cpu(key[0]);
+ ctx->E[1] = le32_to_cpu(key[1]);
+ ctx->E[2] = le32_to_cpu(key[2]);
+ ctx->E[3] = le32_to_cpu(key[3]);
/* Prepare control words. */
memset(&ctx->cword, 0, sizeof(ctx->cword));
ctx->cword.encrypt.keygen = 1;
ctx->cword.decrypt.keygen = 1;
- switch (key_len) {
- case 16:
- t = E_KEY[3];
- for (i = 0; i < 10; ++i)
- loop4 (i);
- break;
-
- case 24:
- E_KEY[4] = le32_to_cpu(key[4]);
- t = E_KEY[5] = le32_to_cpu(key[5]);
- for (i = 0; i < 8; ++i)
- loop6 (i);
- break;
-
- case 32:
- E_KEY[4] = le32_to_cpu(key[4]);
- E_KEY[5] = le32_to_cpu(key[5]);
- E_KEY[6] = le32_to_cpu(key[6]);
- t = E_KEY[7] = le32_to_cpu(key[7]);
- for (i = 0; i < 7; ++i)
- loop8 (i);
- break;
- }
-
- D_KEY[0] = E_KEY[0];
- D_KEY[1] = E_KEY[1];
- D_KEY[2] = E_KEY[2];
- D_KEY[3] = E_KEY[3];
-
- for (i = 4; i < key_len + 24; ++i) {
- imix_col (D_KEY[i], E_KEY[i]);
- }
-
- /* PadLock needs a different format of the decryption key. */
- rounds = 10 + (key_len - 16) / 4;
-
- for (i = 0; i < rounds; i++) {
- P[((i + 1) * 4) + 0] = D_KEY[((rounds - i - 1) * 4) + 0];
- P[((i + 1) * 4) + 1] = D_KEY[((rounds - i - 1) * 4) + 1];
- P[((i + 1) * 4) + 2] = D_KEY[((rounds - i - 1) * 4) + 2];
- P[((i + 1) * 4) + 3] = D_KEY[((rounds - i - 1) * 4) + 3];
+ if (crypto_aes_expand_key(&gen_aes, in_key, key_len)) {
+ *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+ return -EINVAL;
}
- P[0] = E_KEY[(rounds * 4) + 0];
- P[1] = E_KEY[(rounds * 4) + 1];
- P[2] = E_KEY[(rounds * 4) + 2];
- P[3] = E_KEY[(rounds * 4) + 3];
-
- memcpy(D_KEY, P, AES_EXTENDED_KEY_SIZE_B);
-
+ memcpy(ctx->E, gen_aes.key_enc, AES_MAX_KEYLENGTH);
+ memcpy(ctx->D, gen_aes.key_dec, AES_MAX_KEYLENGTH);
return 0;
}
return -ENODEV;
}
- gen_tabs();
if ((ret = crypto_register_alg(&aes_alg)))
goto aes_err;
*
* Each device has a kref, which is initialized to 1 when the device is
* registered. A kref_get is done for each device registered. When the
- * device is released, the coresponding kref_put is done in the release
+ * device is released, the corresponding kref_put is done in the release
* method. Every time one of the device's channels is allocated to a client,
- * a kref_get occurs. When the channel is freed, the coresponding kref_put
+ * a kref_get occurs. When the channel is freed, the corresponding kref_put
* happens. The device's release function does a completion, so
* unregister_device does a remove event, device_unregister, a kref_put
* for the first reference, then waits on the completion for all other
* Each channel has an open-coded implementation of Rusty Russell's "bigref,"
* with a kref and a per_cpu local_t. A dma_chan_get is called when a client
* signals that it wants to use a channel, and dma_chan_put is called when
- * a channel is removed or a client using it is unregesitered. A client can
+ * a channel is removed or a client using it is unregistered. A client can
* take extra references per outstanding transaction, as is the case with
* the NET DMA client. The release function does a kref_put on the device.
* -ChrisL, DanW
#include <linux/delay.h>
#include <linux/idr.h>
#include <linux/string.h>
-#include <asm/semaphore.h>
+#include <linux/rwsem.h>
+#include <linux/semaphore.h>
#include <asm/system.h>
#include <linux/ctype.h>
#include "fw-transaction.h"
#include <linux/list.h>
#include <linux/kthread.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include "fw-transaction.h"
#include "fw-topology.h"
information from userspace through /sys/class/dmi/id/ or if you want
DMI-based module auto-loading.
+config ISCSI_IBFT_FIND
+ bool "iSCSI Boot Firmware Table Attributes"
+ depends on X86
+ default n
+ help
+ This option enables the kernel to find the region of memory
+ in which the ISCSI Boot Firmware Table (iBFT) resides. This
+ is necessary for iSCSI Boot Firmware Table Attributes module to work
+ properly.
+
+config ISCSI_IBFT
+ tristate "iSCSI Boot Firmware Table Attributes module"
+ depends on ISCSI_IBFT_FIND
+ default n
+ help
+ This option enables support for detection and exposing of iSCSI
+ Boot Firmware Table (iBFT) via sysfs to userspace. If you wish to
+ detect iSCSI boot parameters dynamically during system boot, say Y.
+ Otherwise, say N.
+
endmenu
obj-$(CONFIG_DELL_RBU) += dell_rbu.o
obj-$(CONFIG_DCDBAS) += dcdbas.o
obj-$(CONFIG_DMIID) += dmi-id.o
+obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
+obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
#include <linux/types.h>
#include <linux/mutex.h>
#include <asm/io.h>
-#include <asm/semaphore.h>
#include "dcdbas.h"
/* SMI requires CPU 0 */
old_mask = current->cpus_allowed;
- set_cpus_allowed(current, cpumask_of_cpu(0));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(0));
if (smp_processor_id() != 0) {
dev_dbg(&dcdbas_pdev->dev, "%s: failed to get CPU 0\n",
__FUNCTION__);
);
out:
- set_cpus_allowed(current, old_mask);
+ set_cpus_allowed_ptr(current, &old_mask);
return ret;
}
--- /dev/null
+/*
+ * Copyright 2007 Red Hat, Inc.
+ * by Peter Jones <pjones@redhat.com>
+ * Copyright 2008 IBM, Inc.
+ * by Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Copyright 2008
+ * by Konrad Rzeszutek <ketuzsezr@darnok.org>
+ *
+ * This code exposes the iSCSI Boot Format Table to userland via sysfs.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2.0 as published by
+ * the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Changelog:
+ *
+ * 14 Mar 2008 - Konrad Rzeszutek <ketuzsezr@darnok.org>
+ * Updated comments and copyrights. (v0.4.9)
+ *
+ * 11 Feb 2008 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Converted to using ibft_addr. (v0.4.8)
+ *
+ * 8 Feb 2008 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Combined two functions in one: reserve_ibft_region. (v0.4.7)
+ *
+ * 30 Jan 2008 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Added logic to handle IPv6 addresses. (v0.4.6)
+ *
+ * 25 Jan 2008 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Added logic to handle badly not-to-spec iBFT. (v0.4.5)
+ *
+ * 4 Jan 2008 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Added __init to function declarations. (v0.4.4)
+ *
+ * 21 Dec 2007 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Updated kobject registration, combined unregister functions in one
+ * and code and style cleanup. (v0.4.3)
+ *
+ * 5 Dec 2007 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Added end-markers to enums and re-organized kobject registration. (v0.4.2)
+ *
+ * 4 Dec 2007 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Created 'device' sysfs link to the NIC and style cleanup. (v0.4.1)
+ *
+ * 28 Nov 2007 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Added sysfs-ibft documentation, moved 'find_ibft' function to
+ * in its own file and added text attributes for every struct field. (v0.4)
+ *
+ * 21 Nov 2007 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Added text attributes emulating OpenFirmware /proc/device-tree naming.
+ * Removed binary /sysfs interface (v0.3)
+ *
+ * 29 Aug 2007 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Added functionality in setup.c to reserve iBFT region. (v0.2)
+ *
+ * 27 Aug 2007 - Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * First version exposing iBFT data via a binary /sysfs. (v0.1)
+ *
+ */
+
+
+#include <linux/blkdev.h>
+#include <linux/capability.h>
+#include <linux/ctype.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/iscsi_ibft.h>
+#include <linux/limits.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#define IBFT_ISCSI_VERSION "0.4.9"
+#define IBFT_ISCSI_DATE "2008-Mar-14"
+
+MODULE_AUTHOR("Peter Jones <pjones@redhat.com> and \
+Konrad Rzeszutek <ketuzsezr@darnok.org>");
+MODULE_DESCRIPTION("sysfs interface to BIOS iBFT information");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(IBFT_ISCSI_VERSION);
+
+struct ibft_hdr {
+ u8 id;
+ u8 version;
+ u16 length;
+ u8 index;
+ u8 flags;
+} __attribute__((__packed__));
+
+struct ibft_control {
+ struct ibft_hdr hdr;
+ u16 extensions;
+ u16 initiator_off;
+ u16 nic0_off;
+ u16 tgt0_off;
+ u16 nic1_off;
+ u16 tgt1_off;
+} __attribute__((__packed__));
+
+struct ibft_initiator {
+ struct ibft_hdr hdr;
+ char isns_server[16];
+ char slp_server[16];
+ char pri_radius_server[16];
+ char sec_radius_server[16];
+ u16 initiator_name_len;
+ u16 initiator_name_off;
+} __attribute__((__packed__));
+
+struct ibft_nic {
+ struct ibft_hdr hdr;
+ char ip_addr[16];
+ u8 subnet_mask_prefix;
+ u8 origin;
+ char gateway[16];
+ char primary_dns[16];
+ char secondary_dns[16];
+ char dhcp[16];
+ u16 vlan;
+ char mac[6];
+ u16 pci_bdf;
+ u16 hostname_len;
+ u16 hostname_off;
+} __attribute__((__packed__));
+
+struct ibft_tgt {
+ struct ibft_hdr hdr;
+ char ip_addr[16];
+ u16 port;
+ char lun[8];
+ u8 chap_type;
+ u8 nic_assoc;
+ u16 tgt_name_len;
+ u16 tgt_name_off;
+ u16 chap_name_len;
+ u16 chap_name_off;
+ u16 chap_secret_len;
+ u16 chap_secret_off;
+ u16 rev_chap_name_len;
+ u16 rev_chap_name_off;
+ u16 rev_chap_secret_len;
+ u16 rev_chap_secret_off;
+} __attribute__((__packed__));
+
+/*
+ * The kobject different types and its names.
+ *
+*/
+enum ibft_id {
+ id_reserved = 0, /* We don't support. */
+ id_control = 1, /* Should show up only once and is not exported. */
+ id_initiator = 2,
+ id_nic = 3,
+ id_target = 4,
+ id_extensions = 5, /* We don't support. */
+ id_end_marker,
+};
+
+/*
+ * We do not support the other types, hence the usage of NULL.
+ * This maps to the enum ibft_id.
+ */
+static const char *ibft_id_names[] =
+ {NULL, NULL, "initiator", "ethernet%d", "target%d", NULL, NULL};
+
+/*
+ * The text attributes names for each of the kobjects.
+*/
+enum ibft_eth_properties_enum {
+ ibft_eth_index,
+ ibft_eth_flags,
+ ibft_eth_ip_addr,
+ ibft_eth_subnet_mask,
+ ibft_eth_origin,
+ ibft_eth_gateway,
+ ibft_eth_primary_dns,
+ ibft_eth_secondary_dns,
+ ibft_eth_dhcp,
+ ibft_eth_vlan,
+ ibft_eth_mac,
+ /* ibft_eth_pci_bdf - this is replaced by link to the device itself. */
+ ibft_eth_hostname,
+ ibft_eth_end_marker,
+};
+
+static const char *ibft_eth_properties[] =
+ {"index", "flags", "ip-addr", "subnet-mask", "origin", "gateway",
+ "primary-dns", "secondary-dns", "dhcp", "vlan", "mac", "hostname",
+ NULL};
+
+enum ibft_tgt_properties_enum {
+ ibft_tgt_index,
+ ibft_tgt_flags,
+ ibft_tgt_ip_addr,
+ ibft_tgt_port,
+ ibft_tgt_lun,
+ ibft_tgt_chap_type,
+ ibft_tgt_nic_assoc,
+ ibft_tgt_name,
+ ibft_tgt_chap_name,
+ ibft_tgt_chap_secret,
+ ibft_tgt_rev_chap_name,
+ ibft_tgt_rev_chap_secret,
+ ibft_tgt_end_marker,
+};
+
+static const char *ibft_tgt_properties[] =
+ {"index", "flags", "ip-addr", "port", "lun", "chap-type", "nic-assoc",
+ "target-name", "chap-name", "chap-secret", "rev-chap-name",
+ "rev-chap-name-secret", NULL};
+
+enum ibft_initiator_properties_enum {
+ ibft_init_index,
+ ibft_init_flags,
+ ibft_init_isns_server,
+ ibft_init_slp_server,
+ ibft_init_pri_radius_server,
+ ibft_init_sec_radius_server,
+ ibft_init_initiator_name,
+ ibft_init_end_marker,
+};
+
+static const char *ibft_initiator_properties[] =
+ {"index", "flags", "isns-server", "slp-server", "pri-radius-server",
+ "sec-radius-server", "initiator-name", NULL};
+
+/*
+ * The kobject and attribute structures.
+ */
+
+struct ibft_kobject {
+ struct ibft_table_header *header;
+ union {
+ struct ibft_initiator *initiator;
+ struct ibft_nic *nic;
+ struct ibft_tgt *tgt;
+ struct ibft_hdr *hdr;
+ };
+ struct kobject kobj;
+ struct list_head node;
+};
+
+struct ibft_attribute {
+ struct attribute attr;
+ ssize_t (*show) (struct ibft_kobject *entry,
+ struct ibft_attribute *attr, char *buf);
+ union {
+ struct ibft_initiator *initiator;
+ struct ibft_nic *nic;
+ struct ibft_tgt *tgt;
+ struct ibft_hdr *hdr;
+ };
+ struct kobject *kobj;
+ int type; /* The enum of the type. This can be any value of:
+ ibft_eth_properties_enum, ibft_tgt_properties_enum,
+ or ibft_initiator_properties_enum. */
+ struct list_head node;
+};
+
+static LIST_HEAD(ibft_attr_list);
+static LIST_HEAD(ibft_kobject_list);
+
+static const char nulls[16];
+
+/*
+ * Helper functions to parse data properly.
+ */
+static ssize_t sprintf_ipaddr(char *buf, u8 *ip)
+{
+ char *str = buf;
+
+ if (ip[0] == 0 && ip[1] == 0 && ip[2] == 0 && ip[3] == 0 &&
+ ip[4] == 0 && ip[5] == 0 && ip[6] == 0 && ip[7] == 0 &&
+ ip[8] == 0 && ip[9] == 0 && ip[10] == 0xff && ip[11] == 0xff) {
+ /*
+ * IPV4
+ */
+ str += sprintf(buf, NIPQUAD_FMT, ip[12],
+ ip[13], ip[14], ip[15]);
+ } else {
+ /*
+ * IPv6
+ */
+ str += sprintf(str, NIP6_FMT, ntohs(ip[0]), ntohs(ip[1]),
+ ntohs(ip[2]), ntohs(ip[3]), ntohs(ip[4]),
+ ntohs(ip[5]), ntohs(ip[6]), ntohs(ip[7]));
+ }
+ str += sprintf(str, "\n");
+ return str - buf;
+}
+
+static ssize_t sprintf_string(char *str, int len, char *buf)
+{
+ return sprintf(str, "%.*s\n", len, buf);
+}
+
+/*
+ * Helper function to verify the IBFT header.
+ */
+static int ibft_verify_hdr(char *t, struct ibft_hdr *hdr, int id, int length)
+{
+ if (hdr->id != id) {
+ printk(KERN_ERR "iBFT error: We expected the " \
+ "field header.id to have %d but " \
+ "found %d instead!\n", id, hdr->id);
+ return -ENODEV;
+ }
+ if (hdr->length != length) {
+ printk(KERN_ERR "iBFT error: We expected the " \
+ "field header.length to have %d but " \
+ "found %d instead!\n", length, hdr->length);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void ibft_release(struct kobject *kobj)
+{
+ struct ibft_kobject *ibft =
+ container_of(kobj, struct ibft_kobject, kobj);
+ kfree(ibft);
+}
+
+/*
+ * Routines for parsing the iBFT data to be human readable.
+ */
+ssize_t ibft_attr_show_initiator(struct ibft_kobject *entry,
+ struct ibft_attribute *attr,
+ char *buf)
+{
+ struct ibft_initiator *initiator = entry->initiator;
+ void *ibft_loc = entry->header;
+ char *str = buf;
+
+ if (!initiator)
+ return 0;
+
+ switch (attr->type) {
+ case ibft_init_index:
+ str += sprintf(str, "%d\n", initiator->hdr.index);
+ break;
+ case ibft_init_flags:
+ str += sprintf(str, "%d\n", initiator->hdr.flags);
+ break;
+ case ibft_init_isns_server:
+ str += sprintf_ipaddr(str, initiator->isns_server);
+ break;
+ case ibft_init_slp_server:
+ str += sprintf_ipaddr(str, initiator->slp_server);
+ break;
+ case ibft_init_pri_radius_server:
+ str += sprintf_ipaddr(str, initiator->pri_radius_server);
+ break;
+ case ibft_init_sec_radius_server:
+ str += sprintf_ipaddr(str, initiator->sec_radius_server);
+ break;
+ case ibft_init_initiator_name:
+ str += sprintf_string(str, initiator->initiator_name_len,
+ (char *)ibft_loc +
+ initiator->initiator_name_off);
+ break;
+ default:
+ break;
+ }
+
+ return str - buf;
+}
+
+ssize_t ibft_attr_show_nic(struct ibft_kobject *entry,
+ struct ibft_attribute *attr,
+ char *buf)
+{
+ struct ibft_nic *nic = entry->nic;
+ void *ibft_loc = entry->header;
+ char *str = buf;
+ char *mac;
+ int val;
+
+ if (!nic)
+ return 0;
+
+ switch (attr->type) {
+ case ibft_eth_index:
+ str += sprintf(str, "%d\n", nic->hdr.index);
+ break;
+ case ibft_eth_flags:
+ str += sprintf(str, "%d\n", nic->hdr.flags);
+ break;
+ case ibft_eth_ip_addr:
+ str += sprintf_ipaddr(str, nic->ip_addr);
+ break;
+ case ibft_eth_subnet_mask:
+ val = ~((1 << (32-nic->subnet_mask_prefix))-1);
+ str += sprintf(str, NIPQUAD_FMT,
+ (u8)(val >> 24), (u8)(val >> 16),
+ (u8)(val >> 8), (u8)(val));
+ break;
+ case ibft_eth_origin:
+ str += sprintf(str, "%d\n", nic->origin);
+ break;
+ case ibft_eth_gateway:
+ str += sprintf_ipaddr(str, nic->gateway);
+ break;
+ case ibft_eth_primary_dns:
+ str += sprintf_ipaddr(str, nic->primary_dns);
+ break;
+ case ibft_eth_secondary_dns:
+ str += sprintf_ipaddr(str, nic->secondary_dns);
+ break;
+ case ibft_eth_dhcp:
+ str += sprintf_ipaddr(str, nic->dhcp);
+ break;
+ case ibft_eth_vlan:
+ str += sprintf(str, "%d\n", nic->vlan);
+ break;
+ case ibft_eth_mac:
+ mac = nic->mac;
+ str += sprintf(str, "%02x:%02x:%02x:%02x:%02x:%02x\n",
+ (u8)mac[0], (u8)mac[1], (u8)mac[2],
+ (u8)mac[3], (u8)mac[4], (u8)mac[5]);
+ break;
+ case ibft_eth_hostname:
+ str += sprintf_string(str, nic->hostname_len,
+ (char *)ibft_loc + nic->hostname_off);
+ break;
+ default:
+ break;
+ }
+
+ return str - buf;
+};
+
+ssize_t ibft_attr_show_target(struct ibft_kobject *entry,
+ struct ibft_attribute *attr,
+ char *buf)
+{
+ struct ibft_tgt *tgt = entry->tgt;
+ void *ibft_loc = entry->header;
+ char *str = buf;
+ int i;
+
+ if (!tgt)
+ return 0;
+
+ switch (attr->type) {
+ case ibft_tgt_index:
+ str += sprintf(str, "%d\n", tgt->hdr.index);
+ break;
+ case ibft_tgt_flags:
+ str += sprintf(str, "%d\n", tgt->hdr.flags);
+ break;
+ case ibft_tgt_ip_addr:
+ str += sprintf_ipaddr(str, tgt->ip_addr);
+ break;
+ case ibft_tgt_port:
+ str += sprintf(str, "%d\n", tgt->port);
+ break;
+ case ibft_tgt_lun:
+ for (i = 0; i < 8; i++)
+ str += sprintf(str, "%x", (u8)tgt->lun[i]);
+ str += sprintf(str, "\n");
+ break;
+ case ibft_tgt_nic_assoc:
+ str += sprintf(str, "%d\n", tgt->nic_assoc);
+ break;
+ case ibft_tgt_chap_type:
+ str += sprintf(str, "%d\n", tgt->chap_type);
+ break;
+ case ibft_tgt_name:
+ str += sprintf_string(str, tgt->tgt_name_len,
+ (char *)ibft_loc + tgt->tgt_name_off);
+ break;
+ case ibft_tgt_chap_name:
+ str += sprintf_string(str, tgt->chap_name_len,
+ (char *)ibft_loc + tgt->chap_name_off);
+ break;
+ case ibft_tgt_chap_secret:
+ str += sprintf_string(str, tgt->chap_secret_len,
+ (char *)ibft_loc + tgt->chap_secret_off);
+ break;
+ case ibft_tgt_rev_chap_name:
+ str += sprintf_string(str, tgt->rev_chap_name_len,
+ (char *)ibft_loc +
+ tgt->rev_chap_name_off);
+ break;
+ case ibft_tgt_rev_chap_secret:
+ str += sprintf_string(str, tgt->rev_chap_secret_len,
+ (char *)ibft_loc +
+ tgt->rev_chap_secret_off);
+ break;
+ default:
+ break;
+ }
+
+ return str - buf;
+}
+
+/*
+ * The routine called for all sysfs attributes.
+ */
+static ssize_t ibft_show_attribute(struct kobject *kobj,
+ struct attribute *attr,
+ char *buf)
+{
+ struct ibft_kobject *dev =
+ container_of(kobj, struct ibft_kobject, kobj);
+ struct ibft_attribute *ibft_attr =
+ container_of(attr, struct ibft_attribute, attr);
+ ssize_t ret = -EIO;
+ char *str = buf;
+
+ if (!capable(CAP_SYS_ADMIN))
+ return -EACCES;
+
+ if (ibft_attr->show)
+ ret = ibft_attr->show(dev, ibft_attr, str);
+
+ return ret;
+}
+
+static struct sysfs_ops ibft_attr_ops = {
+ .show = ibft_show_attribute,
+};
+
+static struct kobj_type ibft_ktype = {
+ .release = ibft_release,
+ .sysfs_ops = &ibft_attr_ops,
+};
+
+static struct kset *ibft_kset;
+
+static int __init ibft_check_device(void)
+{
+ int len;
+ u8 *pos;
+ u8 csum = 0;
+
+ len = ibft_addr->length;
+
+ /* Sanity checking of iBFT. */
+ if (ibft_addr->revision != 1) {
+ printk(KERN_ERR "iBFT module supports only revision 1, " \
+ "while this is %d.\n", ibft_addr->revision);
+ return -ENOENT;
+ }
+ for (pos = (u8 *)ibft_addr; pos < (u8 *)ibft_addr + len; pos++)
+ csum += *pos;
+
+ if (csum) {
+ printk(KERN_ERR "iBFT has incorrect checksum (0x%x)!\n", csum);
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+/*
+ * Helper function for ibft_register_kobjects.
+ */
+static int __init ibft_create_kobject(struct ibft_table_header *header,
+ struct ibft_hdr *hdr,
+ struct list_head *list)
+{
+ struct ibft_kobject *ibft_kobj = NULL;
+ struct ibft_nic *nic = (struct ibft_nic *)hdr;
+ struct pci_dev *pci_dev;
+ int rc = 0;
+
+ ibft_kobj = kzalloc(sizeof(*ibft_kobj), GFP_KERNEL);
+ if (!ibft_kobj)
+ return -ENOMEM;
+
+ ibft_kobj->header = header;
+ ibft_kobj->hdr = hdr;
+
+ switch (hdr->id) {
+ case id_initiator:
+ rc = ibft_verify_hdr("initiator", hdr, id_initiator,
+ sizeof(*ibft_kobj->initiator));
+ break;
+ case id_nic:
+ rc = ibft_verify_hdr("ethernet", hdr, id_nic,
+ sizeof(*ibft_kobj->nic));
+ break;
+ case id_target:
+ rc = ibft_verify_hdr("target", hdr, id_target,
+ sizeof(*ibft_kobj->tgt));
+ break;
+ case id_reserved:
+ case id_control:
+ case id_extensions:
+ /* Fields which we don't support. Ignore them */
+ rc = 1;
+ break;
+ default:
+ printk(KERN_ERR "iBFT has unknown structure type (%d). " \
+ "Report this bug to %.6s!\n", hdr->id,
+ header->oem_id);
+ rc = 1;
+ break;
+ }
+
+ if (rc) {
+ /* Skip adding this kobject, but exit with non-fatal error. */
+ kfree(ibft_kobj);
+ goto out_invalid_struct;
+ }
+
+ ibft_kobj->kobj.kset = ibft_kset;
+
+ rc = kobject_init_and_add(&ibft_kobj->kobj, &ibft_ktype,
+ NULL, ibft_id_names[hdr->id], hdr->index);
+
+ if (rc) {
+ kfree(ibft_kobj);
+ goto out;
+ }
+
+ kobject_uevent(&ibft_kobj->kobj, KOBJ_ADD);
+
+ if (hdr->id == id_nic) {
+ /*
+ * We don't search for the device in other domains than
+ * zero. This is because on x86 platforms the BIOS
+ * executes only devices which are in domain 0. Furthermore, the
+ * iBFT spec doesn't have a domain id field :-(
+ */
+ pci_dev = pci_get_bus_and_slot((nic->pci_bdf & 0xff00) >> 8,
+ (nic->pci_bdf & 0xff));
+ if (pci_dev) {
+ rc = sysfs_create_link(&ibft_kobj->kobj,
+ &pci_dev->dev.kobj, "device");
+ pci_dev_put(pci_dev);
+ }
+ }
+
+ /* Nothing broke so lets add it to the list. */
+ list_add_tail(&ibft_kobj->node, list);
+out:
+ return rc;
+out_invalid_struct:
+ /* Unsupported structs are skipped. */
+ return 0;
+}
+
+/*
+ * Scan the IBFT table structure for the NIC and Target fields. When
+ * found add them on the passed-in list. We do not support the other
+ * fields at this point, so they are skipped.
+ */
+static int __init ibft_register_kobjects(struct ibft_table_header *header,
+ struct list_head *list)
+{
+ struct ibft_control *control = NULL;
+ void *ptr, *end;
+ int rc = 0;
+ u16 offset;
+ u16 eot_offset;
+
+ control = (void *)header + sizeof(*header);
+ end = (void *)control + control->hdr.length;
+ eot_offset = (void *)header + header->length -
+ (void *)control - sizeof(*header);
+ rc = ibft_verify_hdr("control", (struct ibft_hdr *)control, id_control,
+ sizeof(*control));
+
+ /* iBFT table safety checking */
+ rc |= ((control->hdr.index) ? -ENODEV : 0);
+ if (rc) {
+ printk(KERN_ERR "iBFT error: Control header is invalid!\n");
+ return rc;
+ }
+ for (ptr = &control->initiator_off; ptr < end; ptr += sizeof(u16)) {
+ offset = *(u16 *)ptr;
+ if (offset && offset < header->length && offset < eot_offset) {
+ rc = ibft_create_kobject(header,
+ (void *)header + offset,
+ list);
+ if (rc)
+ break;
+ }
+ }
+
+ return rc;
+}
+
+static void ibft_unregister(struct list_head *attr_list,
+ struct list_head *kobj_list)
+{
+ struct ibft_kobject *data = NULL, *n;
+ struct ibft_attribute *attr = NULL, *m;
+
+ list_for_each_entry_safe(attr, m, attr_list, node) {
+ sysfs_remove_file(attr->kobj, &attr->attr);
+ list_del(&attr->node);
+ kfree(attr);
+ };
+ list_del_init(attr_list);
+
+ list_for_each_entry_safe(data, n, kobj_list, node) {
+ list_del(&data->node);
+ if (data->hdr->id == id_nic)
+ sysfs_remove_link(&data->kobj, "device");
+ kobject_put(&data->kobj);
+ };
+ list_del_init(kobj_list);
+}
+
+static int __init ibft_create_attribute(struct ibft_kobject *kobj_data,
+ int type,
+ const char *name,
+ ssize_t (*show)(struct ibft_kobject *,
+ struct ibft_attribute*,
+ char *buf),
+ struct list_head *list)
+{
+ struct ibft_attribute *attr = NULL;
+ struct ibft_hdr *hdr = kobj_data->hdr;
+
+ attr = kmalloc(sizeof(*attr), GFP_KERNEL);
+ if (!attr)
+ return -ENOMEM;
+
+ attr->attr.name = name;
+ attr->attr.mode = S_IRUSR;
+ attr->attr.owner = THIS_MODULE;
+
+ attr->hdr = hdr;
+ attr->show = show;
+ attr->kobj = &kobj_data->kobj;
+ attr->type = type;
+
+ list_add_tail(&attr->node, list);
+
+ return 0;
+}
+
+/*
+ * Helper routiners to check to determine if the entry is valid
+ * in the proper iBFT structure.
+ */
+static int __init ibft_check_nic_for(struct ibft_nic *nic, int entry)
+{
+ int rc = 0;
+
+ switch (entry) {
+ case ibft_eth_index:
+ case ibft_eth_flags:
+ rc = 1;
+ break;
+ case ibft_eth_ip_addr:
+ if (!memcmp(nic->dhcp, nulls, sizeof(nic->dhcp)))
+ rc = 1;
+ break;
+ case ibft_eth_subnet_mask:
+ if (!memcmp(nic->dhcp, nulls, sizeof(nic->dhcp)))
+ rc = 1;
+ break;
+ case ibft_eth_origin:
+ rc = 1;
+ break;
+ case ibft_eth_gateway:
+ if (memcmp(nic->gateway, nulls, sizeof(nic->gateway)))
+ rc = 1;
+ break;
+ case ibft_eth_primary_dns:
+ if (memcmp(nic->primary_dns, nulls,
+ sizeof(nic->primary_dns)))
+ rc = 1;
+ break;
+ case ibft_eth_secondary_dns:
+ if (memcmp(nic->secondary_dns, nulls,
+ sizeof(nic->secondary_dns)))
+ rc = 1;
+ break;
+ case ibft_eth_dhcp:
+ if (memcmp(nic->dhcp, nulls, sizeof(nic->dhcp)))
+ rc = 1;
+ break;
+ case ibft_eth_vlan:
+ case ibft_eth_mac:
+ rc = 1;
+ break;
+ case ibft_eth_hostname:
+ if (nic->hostname_off)
+ rc = 1;
+ break;
+ default:
+ break;
+ }
+
+ return rc;
+}
+
+static int __init ibft_check_tgt_for(struct ibft_tgt *tgt, int entry)
+{
+ int rc = 0;
+
+ switch (entry) {
+ case ibft_tgt_index:
+ case ibft_tgt_flags:
+ case ibft_tgt_ip_addr:
+ case ibft_tgt_port:
+ case ibft_tgt_lun:
+ case ibft_tgt_nic_assoc:
+ case ibft_tgt_chap_type:
+ rc = 1;
+ case ibft_tgt_name:
+ if (tgt->tgt_name_len)
+ rc = 1;
+ break;
+ case ibft_tgt_chap_name:
+ case ibft_tgt_chap_secret:
+ if (tgt->chap_name_len)
+ rc = 1;
+ break;
+ case ibft_tgt_rev_chap_name:
+ case ibft_tgt_rev_chap_secret:
+ if (tgt->rev_chap_name_len)
+ rc = 1;
+ break;
+ default:
+ break;
+ }
+
+ return rc;
+}
+
+static int __init ibft_check_initiator_for(struct ibft_initiator *init,
+ int entry)
+{
+ int rc = 0;
+
+ switch (entry) {
+ case ibft_init_index:
+ case ibft_init_flags:
+ rc = 1;
+ break;
+ case ibft_init_isns_server:
+ if (memcmp(init->isns_server, nulls,
+ sizeof(init->isns_server)))
+ rc = 1;
+ break;
+ case ibft_init_slp_server:
+ if (memcmp(init->slp_server, nulls,
+ sizeof(init->slp_server)))
+ rc = 1;
+ break;
+ case ibft_init_pri_radius_server:
+ if (memcmp(init->pri_radius_server, nulls,
+ sizeof(init->pri_radius_server)))
+ rc = 1;
+ break;
+ case ibft_init_sec_radius_server:
+ if (memcmp(init->sec_radius_server, nulls,
+ sizeof(init->sec_radius_server)))
+ rc = 1;
+ break;
+ case ibft_init_initiator_name:
+ if (init->initiator_name_len)
+ rc = 1;
+ break;
+ default:
+ break;
+ }
+
+ return rc;
+}
+
+/*
+ * Register the attributes for all of the kobjects.
+ */
+static int __init ibft_register_attributes(struct list_head *kobject_list,
+ struct list_head *attr_list)
+{
+ int rc = 0, i = 0;
+ struct ibft_kobject *data = NULL;
+ struct ibft_attribute *attr = NULL, *m;
+
+ list_for_each_entry(data, kobject_list, node) {
+ switch (data->hdr->id) {
+ case id_nic:
+ for (i = 0; i < ibft_eth_end_marker && !rc; i++)
+ if (ibft_check_nic_for(data->nic, i))
+ rc = ibft_create_attribute(data, i,
+ ibft_eth_properties[i],
+ ibft_attr_show_nic, attr_list);
+ break;
+ case id_target:
+ for (i = 0; i < ibft_tgt_end_marker && !rc; i++)
+ if (ibft_check_tgt_for(data->tgt, i))
+ rc = ibft_create_attribute(data, i,
+ ibft_tgt_properties[i],
+ ibft_attr_show_target,
+ attr_list);
+ break;
+ case id_initiator:
+ for (i = 0; i < ibft_init_end_marker && !rc; i++)
+ if (ibft_check_initiator_for(
+ data->initiator, i))
+ rc = ibft_create_attribute(data, i,
+ ibft_initiator_properties[i],
+ ibft_attr_show_initiator,
+ attr_list);
+ break;
+ default:
+ break;
+ }
+ if (rc)
+ break;
+ }
+ list_for_each_entry_safe(attr, m, attr_list, node) {
+ rc = sysfs_create_file(attr->kobj, &attr->attr);
+ if (rc) {
+ list_del(&attr->node);
+ kfree(attr);
+ break;
+ }
+ }
+
+ return rc;
+}
+
+/*
+ * ibft_init() - creates sysfs tree entries for the iBFT data.
+ */
+static int __init ibft_init(void)
+{
+ int rc = 0;
+
+ ibft_kset = kset_create_and_add("ibft", NULL, firmware_kobj);
+ if (!ibft_kset)
+ return -ENOMEM;
+
+ if (ibft_addr) {
+ printk(KERN_INFO "iBFT detected at 0x%lx.\n",
+ virt_to_phys((void *)ibft_addr));
+
+ rc = ibft_check_device();
+ if (rc)
+ goto out_firmware_unregister;
+
+ /* Scan the IBFT for data and register the kobjects. */
+ rc = ibft_register_kobjects(ibft_addr, &ibft_kobject_list);
+ if (rc)
+ goto out_free;
+
+ /* Register the attributes */
+ rc = ibft_register_attributes(&ibft_kobject_list,
+ &ibft_attr_list);
+ if (rc)
+ goto out_free;
+ } else
+ printk(KERN_INFO "No iBFT detected.\n");
+
+ return 0;
+
+out_free:
+ ibft_unregister(&ibft_attr_list, &ibft_kobject_list);
+out_firmware_unregister:
+ kset_unregister(ibft_kset);
+ return rc;
+}
+
+static void __exit ibft_exit(void)
+{
+ ibft_unregister(&ibft_attr_list, &ibft_kobject_list);
+ kset_unregister(ibft_kset);
+}
+
+module_init(ibft_init);
+module_exit(ibft_exit);
--- /dev/null
+/*
+ * Copyright 2007 Red Hat, Inc.
+ * by Peter Jones <pjones@redhat.com>
+ * Copyright 2007 IBM, Inc.
+ * by Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Copyright 2008
+ * by Konrad Rzeszutek <ketuzsezr@darnok.org>
+ *
+ * This code finds the iSCSI Boot Format Table.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2.0 as published by
+ * the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/bootmem.h>
+#include <linux/blkdev.h>
+#include <linux/ctype.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/limits.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include <asm/mmzone.h>
+
+/*
+ * Physical location of iSCSI Boot Format Table.
+ */
+struct ibft_table_header *ibft_addr;
+EXPORT_SYMBOL_GPL(ibft_addr);
+
+#define IBFT_SIGN "iBFT"
+#define IBFT_SIGN_LEN 4
+#define IBFT_START 0x80000 /* 512kB */
+#define IBFT_END 0x100000 /* 1MB */
+#define VGA_MEM 0xA0000 /* VGA buffer */
+#define VGA_SIZE 0x20000 /* 128kB */
+
+
+/*
+ * Routine used to find the iSCSI Boot Format Table. The logical
+ * kernel address is set in the ibft_addr global variable.
+ */
+void __init reserve_ibft_region(void)
+{
+ unsigned long pos;
+ unsigned int len = 0;
+ void *virt;
+
+ ibft_addr = 0;
+
+ for (pos = IBFT_START; pos < IBFT_END; pos += 16) {
+ /* The table can't be inside the VGA BIOS reserved space,
+ * so skip that area */
+ if (pos == VGA_MEM)
+ pos += VGA_SIZE;
+ virt = phys_to_virt(pos);
+ if (memcmp(virt, IBFT_SIGN, IBFT_SIGN_LEN) == 0) {
+ unsigned long *addr =
+ (unsigned long *)phys_to_virt(pos + 4);
+ len = *addr;
+ /* if the length of the table extends past 1M,
+ * the table cannot be valid. */
+ if (pos + len <= (IBFT_END-1)) {
+ ibft_addr = (struct ibft_table_header *)virt;
+ break;
+ }
+ }
+ }
+ if (ibft_addr)
+ reserve_bootmem(pos, PAGE_ALIGN(len), BOOTMEM_DEFAULT);
+}
+EXPORT_SYMBOL_GPL(reserve_ibft_region);
#ifdef CONFIG_HID_DEBUG
int hid_debug = 0;
-module_param_named(debug, hid_debug, bool, 0600);
-MODULE_PARM_DESC(debug, "Turn HID debugging mode on and off");
+module_param_named(debug, hid_debug, int, 0600);
+MODULE_PARM_DESC(debug, "HID debugging (0=off, 1=probing info, 2=continuous data dumping)");
EXPORT_SYMBOL_GPL(hid_debug);
#endif
field->index = report->maxfield++;
report->field[field->index] = field;
field->usage = (struct hid_usage *)(field + 1);
- field->value = (unsigned *)(field->usage + usages);
+ field->value = (s32 *)(field->usage + usages);
field->report = report;
return field;
* reporting to the layer).
*/
-void hid_input_field(struct hid_device *hid, struct hid_field *field, __u8 *data, int interrupt)
+static void hid_input_field(struct hid_device *hid, struct hid_field *field,
+ __u8 *data, int interrupt)
{
unsigned n;
unsigned count = field->report_count;
exit:
kfree(value);
}
-EXPORT_SYMBOL_GPL(hid_input_field);
/*
* Output the field into the report.
if ((hid->claimed & HID_CLAIMED_HIDDEV) && hid->hiddev_report_event)
hid->hiddev_report_event(hid, report);
- if (hid->claimed & HID_CLAIMED_HIDRAW)
- hidraw_report_event(hid, data, size);
+ if (hid->claimed & HID_CLAIMED_HIDRAW) {
+ /* numbered reports need to be passed with the report num */
+ if (report_enum->numbered)
+ hidraw_report_event(hid, data - 1, size + 1);
+ else
+ hidraw_report_event(hid, data, size);
+ }
for (n = 0; n < report->maxfield; n++)
hid_input_field(hid, report->field[n], data, interrupt);
EXPORT_SYMBOL_GPL(hid_dump_device);
void hid_dump_input(struct hid_usage *usage, __s32 value) {
- if (!hid_debug)
+ if (hid_debug < 2)
return;
printk(KERN_DEBUG "hid-debug: input ");
return 1;
}
+static int quirk_sunplus_wdesktop(struct hid_usage *usage, struct input_dev *input,
+ unsigned long **bit, int *max)
+{
+ if ((usage->hid & HID_USAGE_PAGE) != HID_UP_CONSUMER)
+ return 0;
+
+ switch (usage->hid & HID_USAGE) {
+ case 0x2003: map_key_clear(KEY_ZOOMIN); break;
+ case 0x2103: map_key_clear(KEY_ZOOMOUT); break;
+ default:
+ return 0;
+ }
+ return 1;
+}
+
#define VENDOR_ID_BELKIN 0x1020
#define DEVICE_ID_BELKIN_WIRELESS_KEYBOARD 0x0006
#define VENDOR_ID_PETALYNX 0x18b1
#define DEVICE_ID_PETALYNX_MAXTER_REMOTE 0x0037
+#define VENDOR_ID_SUNPLUS 0x04fc
+#define DEVICE_ID_SUNPLUS_WDESKTOP 0x05d8
+
static const struct hid_input_blacklist {
__u16 idVendor;
__u16 idProduct;
{ VENDOR_ID_MONTEREY, DEVICE_ID_GENIUS_KB29E, quirk_cherry_genius_29e },
{ VENDOR_ID_PETALYNX, DEVICE_ID_PETALYNX_MAXTER_REMOTE, quirk_petalynx_remote },
-
- { 0, 0, 0 }
+
+ { VENDOR_ID_SUNPLUS, DEVICE_ID_SUNPLUS_WDESKTOP, quirk_sunplus_wdesktop },
+
+ { 0, 0, NULL }
};
int hidinput_mapping_quirks(struct hid_usage *usage,
Note: if you say N here, this device will still be supported, but without
force feedback.
+config LOGIRUMBLEPAD2_FF
+ bool "Logitech Rumblepad 2 support"
+ depends on HID_FF
+ select INPUT_FF_MEMLESS if USB_HID
+ help
+ Say Y here if you want to enable force feedback support for Logitech
+ Rumblepad 2 devices.
+
config PANTHERLORD_FF
bool "PantherLord/GreenAsia based device support"
depends on HID_FF
or adapter and want to enable force feedback support for it.
config THRUSTMASTER_FF
- bool "ThrustMaster devices support (EXPERIMENTAL)"
- depends on HID_FF && EXPERIMENTAL
+ bool "ThrustMaster devices support"
+ depends on HID_FF
select INPUT_FF_MEMLESS if USB_HID
help
Say Y here if you have a THRUSTMASTER FireStore Dual Power 2 or
ifeq ($(CONFIG_LOGITECH_FF),y)
usbhid-objs += hid-lgff.o
endif
+ifeq ($(CONFIG_LOGIRUMBLEPAD2_FF),y)
+ usbhid-objs += hid-lg2ff.o
+endif
ifeq ($(CONFIG_PANTHERLORD_FF),y)
usbhid-objs += hid-plff.o
endif
spin_lock_irqsave(&usbhid->inlock, flags);
if (hid->open > 0 && !test_bit(HID_SUSPENDED, &usbhid->iofl) &&
+ !test_bit(HID_DISCONNECTED, &usbhid->iofl) &&
!test_and_set_bit(HID_IN_RUNNING, &usbhid->iofl)) {
rc = usb_submit_urb(usbhid->urbin, GFP_ATOMIC);
if (rc != 0)
spin_lock_irqsave(&usbhid->inlock, flags);
/* Stop when disconnected */
- if (usb_get_intfdata(usbhid->intf) == NULL)
+ if (test_bit(HID_DISCONNECTED, &usbhid->iofl))
goto done;
/* If it has been a while since the last error, we'll assume
if (usbhid->outhead != usbhid->outtail) {
if (hid_submit_out(hid)) {
clear_bit(HID_OUT_RUNNING, &usbhid->iofl);
- wake_up(&hid->wait);
+ wake_up(&usbhid->wait);
}
spin_unlock_irqrestore(&usbhid->outlock, flags);
return;
clear_bit(HID_OUT_RUNNING, &usbhid->iofl);
spin_unlock_irqrestore(&usbhid->outlock, flags);
- wake_up(&hid->wait);
+ wake_up(&usbhid->wait);
}
/*
if (usbhid->ctrlhead != usbhid->ctrltail) {
if (hid_submit_ctrl(hid)) {
clear_bit(HID_CTRL_RUNNING, &usbhid->iofl);
- wake_up(&hid->wait);
+ wake_up(&usbhid->wait);
}
spin_unlock_irqrestore(&usbhid->ctrllock, flags);
return;
clear_bit(HID_CTRL_RUNNING, &usbhid->iofl);
spin_unlock_irqrestore(&usbhid->ctrllock, flags);
- wake_up(&hid->wait);
+ wake_up(&usbhid->wait);
}
void usbhid_submit_report(struct hid_device *hid, struct hid_report *report, unsigned char dir)
{
struct usbhid_device *usbhid = hid->driver_data;
- if (!wait_event_timeout(hid->wait, (!test_bit(HID_CTRL_RUNNING, &usbhid->iofl) &&
- !test_bit(HID_OUT_RUNNING, &usbhid->iofl)),
+ if (!wait_event_timeout(usbhid->wait,
+ (!test_bit(HID_CTRL_RUNNING, &usbhid->iofl) &&
+ !test_bit(HID_OUT_RUNNING, &usbhid->iofl)),
10*HZ)) {
dbg_hid("timeout waiting for ctrl or out queue to clear\n");
return -1;
/*
* Traverse the supplied list of reports and find the longest
*/
-static void hid_find_max_report(struct hid_device *hid, unsigned int type, int *max)
+static void hid_find_max_report(struct hid_device *hid, unsigned int type,
+ unsigned int *max)
{
struct hid_report *report;
- int size;
+ unsigned int size;
list_for_each_entry(report, &hid->report_enum[type].report_list, list) {
size = ((report->size - 1) >> 3) + 1;
struct hid_descriptor *hdesc;
struct hid_device *hid;
u32 quirks = 0;
- unsigned rsize = 0;
+ unsigned int insize = 0, rsize = 0;
char *rdesc;
- int n, len, insize = 0;
+ int n, len;
struct usbhid_device *usbhid;
quirks = usbhid_lookup_quirk(le16_to_cpu(dev->descriptor.idVendor),
goto fail;
}
+ hid->name[0] = 0;
+
+ if (dev->manufacturer)
+ strlcpy(hid->name, dev->manufacturer, sizeof(hid->name));
+
+ if (dev->product) {
+ if (dev->manufacturer)
+ strlcat(hid->name, " ", sizeof(hid->name));
+ strlcat(hid->name, dev->product, sizeof(hid->name));
+ }
+
+ if (!strlen(hid->name))
+ snprintf(hid->name, sizeof(hid->name), "HID %04x:%04x",
+ le16_to_cpu(dev->descriptor.idVendor),
+ le16_to_cpu(dev->descriptor.idProduct));
+
for (n = 0; n < interface->desc.bNumEndpoints; n++) {
struct usb_endpoint_descriptor *endpoint;
interval = endpoint->bInterval;
+ /* Some vendors give fullspeed interval on highspeed devides */
+ if (quirks & HID_QUIRK_FULLSPEED_INTERVAL &&
+ dev->speed == USB_SPEED_HIGH) {
+ interval = fls(endpoint->bInterval*8);
+ printk(KERN_INFO "%s: Fixing fullspeed to highspeed interval: %d -> %d\n",
+ hid->name, endpoint->bInterval, interval);
+ }
+
/* Change the polling interval of mice. */
if (hid->collection->usage == HID_GD_MOUSE && hid_mousepoll_interval > 0)
interval = hid_mousepoll_interval;
goto fail;
}
- init_waitqueue_head(&hid->wait);
-
+ init_waitqueue_head(&usbhid->wait);
INIT_WORK(&usbhid->reset_work, hid_reset);
setup_timer(&usbhid->io_retry, hid_retry_timeout, (unsigned long) hid);
usbhid->intf = intf;
usbhid->ifnum = interface->desc.bInterfaceNumber;
- hid->name[0] = 0;
-
- if (dev->manufacturer)
- strlcpy(hid->name, dev->manufacturer, sizeof(hid->name));
-
- if (dev->product) {
- if (dev->manufacturer)
- strlcat(hid->name, " ", sizeof(hid->name));
- strlcat(hid->name, dev->product, sizeof(hid->name));
- }
-
- if (!strlen(hid->name))
- snprintf(hid->name, sizeof(hid->name), "HID %04x:%04x",
- le16_to_cpu(dev->descriptor.idVendor),
- le16_to_cpu(dev->descriptor.idProduct));
-
hid->bus = BUS_USB;
hid->vendor = le16_to_cpu(dev->descriptor.idVendor);
hid->product = le16_to_cpu(dev->descriptor.idProduct);
spin_lock_irq(&usbhid->inlock); /* Sync with error handler */
usb_set_intfdata(intf, NULL);
+ set_bit(HID_DISCONNECTED, &usbhid->iofl);
spin_unlock_irq(&usbhid->inlock);
usb_kill_urb(usbhid->urbin);
usb_kill_urb(usbhid->urbout);
{ 0x46d, 0xc295, hid_lgff_init }, /* Logitech MOMO force wheel */
{ 0x46d, 0xca03, hid_lgff_init }, /* Logitech MOMO force wheel */
#endif
+#ifdef CONFIG_LOGIRUMBLEPAD2_FF
+ { 0x46d, 0xc218, hid_lg2ff_init }, /* Logitech Rumblepad 2 */
+#endif
#ifdef CONFIG_PANTHERLORD_FF
{ 0x810, 0x0001, hid_plff_init }, /* "Twin USB Joystick" */
{ 0xe8f, 0x0003, hid_plff_init }, /* "GreenAsia Inc. USB Joystick " */
--- /dev/null
+/*
+ * Force feedback support for Logitech Rumblepad 2
+ *
+ * Copyright (c) 2008 Anssi Hannula <anssi.hannula@gmail.com>
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+
+#include <linux/input.h>
+#include <linux/usb.h>
+#include <linux/hid.h>
+#include "usbhid.h"
+
+struct lg2ff_device {
+ struct hid_report *report;
+};
+
+static int play_effect(struct input_dev *dev, void *data,
+ struct ff_effect *effect)
+{
+ struct hid_device *hid = input_get_drvdata(dev);
+ struct lg2ff_device *lg2ff = data;
+ int weak, strong;
+
+ strong = effect->u.rumble.strong_magnitude;
+ weak = effect->u.rumble.weak_magnitude;
+
+ if (weak || strong) {
+ weak = weak * 0xff / 0xffff;
+ strong = strong * 0xff / 0xffff;
+
+ lg2ff->report->field[0]->value[0] = 0x51;
+ lg2ff->report->field[0]->value[2] = weak;
+ lg2ff->report->field[0]->value[4] = strong;
+ } else {
+ lg2ff->report->field[0]->value[0] = 0xf3;
+ lg2ff->report->field[0]->value[2] = 0x00;
+ lg2ff->report->field[0]->value[4] = 0x00;
+ }
+
+ usbhid_submit_report(hid, lg2ff->report, USB_DIR_OUT);
+ return 0;
+}
+
+int hid_lg2ff_init(struct hid_device *hid)
+{
+ struct lg2ff_device *lg2ff;
+ struct hid_report *report;
+ struct hid_input *hidinput = list_entry(hid->inputs.next,
+ struct hid_input, list);
+ struct list_head *report_list =
+ &hid->report_enum[HID_OUTPUT_REPORT].report_list;
+ struct input_dev *dev = hidinput->input;
+ int error;
+
+ if (list_empty(report_list)) {
+ printk(KERN_ERR "hid-lg2ff: no output report found\n");
+ return -ENODEV;
+ }
+
+ report = list_entry(report_list->next, struct hid_report, list);
+
+ if (report->maxfield < 1) {
+ printk(KERN_ERR "hid-lg2ff: output report is empty\n");
+ return -ENODEV;
+ }
+ if (report->field[0]->report_count < 7) {
+ printk(KERN_ERR "hid-lg2ff: not enough values in the field\n");
+ return -ENODEV;
+ }
+
+ lg2ff = kmalloc(sizeof(struct lg2ff_device), GFP_KERNEL);
+ if (!lg2ff)
+ return -ENOMEM;
+
+ set_bit(FF_RUMBLE, dev->ffbit);
+
+ error = input_ff_create_memless(dev, lg2ff, play_effect);
+ if (error) {
+ kfree(lg2ff);
+ return error;
+ }
+
+ lg2ff->report = report;
+ report->field[0]->value[0] = 0xf3;
+ report->field[0]->value[1] = 0x00;
+ report->field[0]->value[2] = 0x00;
+ report->field[0]->value[3] = 0x00;
+ report->field[0]->value[4] = 0x00;
+ report->field[0]->value[5] = 0x00;
+ report->field[0]->value[6] = 0x00;
+
+ usbhid_submit_report(hid, report, USB_DIR_OUT);
+
+ printk(KERN_INFO "Force feedback for Logitech Rumblepad 2 by "
+ "Anssi Hannula <anssi.hannula@gmail.com>\n");
+
+ return 0;
+}
#define USB_VENDOR_ID_ADS_TECH 0x06e1
#define USB_DEVICE_ID_ADS_TECH_RADIO_SI470X 0xa155
+#define USB_VENDOR_ID_AFATECH 0x15a4
+#define USB_DEVICE_ID_AFATECH_AF9016 0x9016
+
#define USB_VENDOR_ID_AIPTEK 0x08ca
#define USB_DEVICE_ID_AIPTEK_01 0x0001
#define USB_DEVICE_ID_AIPTEK_10 0x0010
#define USB_DEVICE_ID_DELORME_EARTHMATE 0x0100
#define USB_DEVICE_ID_DELORME_EM_LT20 0x0200
+#define USB_VENDOR_ID_DMI 0x0c0b
+#define USB_DEVICE_ID_DMI_ENC 0x5fab
+
#define USB_VENDOR_ID_ELO 0x04E7
#define USB_DEVICE_ID_ELO_TS2700 0x0020
#define USB_DEVICE_ID_GTCO_502 0x0502
#define USB_DEVICE_ID_GTCO_503 0x0503
#define USB_DEVICE_ID_GTCO_504 0x0504
-#define USB_DEVICE_ID_GTCO_600 0x0600
-#define USB_DEVICE_ID_GTCO_601 0x0601
-#define USB_DEVICE_ID_GTCO_602 0x0602
-#define USB_DEVICE_ID_GTCO_603 0x0603
-#define USB_DEVICE_ID_GTCO_604 0x0604
-#define USB_DEVICE_ID_GTCO_605 0x0605
-#define USB_DEVICE_ID_GTCO_606 0x0606
-#define USB_DEVICE_ID_GTCO_607 0x0607
-#define USB_DEVICE_ID_GTCO_608 0x0608
-#define USB_DEVICE_ID_GTCO_609 0x0609
-#define USB_DEVICE_ID_GTCO_609 0x0609
#define USB_DEVICE_ID_GTCO_1000 0x1000
#define USB_DEVICE_ID_GTCO_1001 0x1001
#define USB_DEVICE_ID_GTCO_1002 0x1002
#define USB_DEVICE_ID_LOGITECH_CORDLESS_DESKTOP_LX500 0xc512
#define USB_DEVICE_ID_MX3000_RECEIVER 0xc513
#define USB_DEVICE_ID_DINOVO_EDGE 0xc714
+#define USB_DEVICE_ID_DINOVO_MINI 0xc71f
#define USB_VENDOR_ID_MCC 0x09db
#define USB_DEVICE_ID_MCC_PMD1024LS 0x0076
#define USB_VENDOR_ID_MICROSOFT 0x045e
#define USB_DEVICE_ID_SIDEWINDER_GV 0x003b
#define USB_DEVICE_ID_WIRELESS_OPTICAL_DESKTOP_3_0 0x009d
+#define USB_DEVICE_ID_DESKTOP_RECV_1028 0x00f9
#define USB_DEVICE_ID_MS_NE4K 0x00db
#define USB_DEVICE_ID_MS_LK6K 0x00f9
#define USB_VENDOR_ID_SUN 0x0430
#define USB_DEVICE_ID_RARITAN_KVM_DONGLE 0xcdab
+#define USB_VENDOR_ID_SUNPLUS 0x04fc
+#define USB_DEVICE_ID_SUNPLUS_WDESKTOP 0x05d8
+
#define USB_VENDOR_ID_TOPMAX 0x0663
#define USB_DEVICE_ID_TOPMAX_COBRAPAD 0x0103
{ USB_VENDOR_ID_TOPMAX, USB_DEVICE_ID_TOPMAX_COBRAPAD, HID_QUIRK_BADPAD },
{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_DINOVO_EDGE, HID_QUIRK_DUPLICATE_USAGES },
+ { USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_DINOVO_MINI, HID_QUIRK_DUPLICATE_USAGES },
+
+ { USB_VENDOR_ID_AFATECH, USB_DEVICE_ID_AFATECH_AF9016, HID_QUIRK_FULLSPEED_INTERVAL },
{ USB_VENDOR_ID_BELKIN, USB_DEVICE_ID_FLIP_KVM, HID_QUIRK_HIDDEV },
{ USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL4, HID_QUIRK_HIDDEV | HID_QUIRK_IGNORE_HIDINPUT },
+ { USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_IR_REMOTE, HID_QUIRK_HIDDEV | HID_QUIRK_IGNORE_HIDINPUT },
{ USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_SIDEWINDER_GV, HID_QUIRK_HIDINPUT },
{ USB_VENDOR_ID_EZKEY, USB_DEVICE_ID_BTC_8193, HID_QUIRK_HWHEEL_WHEEL_INVERT },
{ USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_502, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_503, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_504, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_600, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_601, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_602, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_603, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_604, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_605, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_606, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_607, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_608, HID_QUIRK_IGNORE },
- { USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_609, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_1000, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_1001, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_GTCO, USB_DEVICE_ID_GTCO_1002, HID_QUIRK_IGNORE },
{ USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_2PORTKVM, HID_QUIRK_NOGET },
{ USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_4PORTKVM, HID_QUIRK_NOGET },
{ USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_4PORTKVMC, HID_QUIRK_NOGET },
+ { USB_VENDOR_ID_DMI, USB_DEVICE_ID_DMI_ENC, HID_QUIRK_NOGET },
{ USB_VENDOR_ID_ELO, USB_DEVICE_ID_ELO_TS2700, HID_QUIRK_NOGET },
{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_EXTREME_3D, HID_QUIRK_NOGET },
{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_WHEEL, HID_QUIRK_NOGET },
{ USB_VENDOR_ID_PETALYNX, USB_DEVICE_ID_PETALYNX_MAXTER_REMOTE, HID_QUIRK_NOGET },
{ USB_VENDOR_ID_SUN, USB_DEVICE_ID_RARITAN_KVM_DONGLE, HID_QUIRK_NOGET },
{ USB_VENDOR_ID_TURBOX, USB_DEVICE_ID_TURBOX_KEYBOARD, HID_QUIRK_NOGET },
- { USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_DUAL_USB_JOYPAD, HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT },
+ { USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_DUAL_USB_JOYPAD, HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT | HID_QUIRK_SKIP_OUTPUT_REPORTS },
{ USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_QUAD_USB_JOYPAD, HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT },
{ USB_VENDOR_ID_WISEGROUP_LTD, USB_DEVICE_ID_SMARTJOY_DUAL_PLUS, HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT },
{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_MX3000_RECEIVER, HID_QUIRK_RDESC_LOGITECH },
{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_S510_RECEIVER, HID_QUIRK_RDESC_LOGITECH },
{ USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_S510_RECEIVER_2, HID_QUIRK_RDESC_LOGITECH },
+ { USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_DESKTOP_RECV_1028, HID_QUIRK_RDESC_MICROSOFT_RECV_1028 },
{ USB_VENDOR_ID_MONTEREY, USB_DEVICE_ID_GENIUS_KB29E, HID_QUIRK_RDESC_BUTTON_CONSUMER },
{ USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_IR_REMOTE, HID_QUIRK_RDESC_SAMSUNG_REMOTE },
+ { USB_VENDOR_ID_SUNPLUS, USB_DEVICE_ID_SUNPLUS_WDESKTOP, HID_QUIRK_RDESC_SUNPLUS_WDESKTOP },
+
{ USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_1, HID_QUIRK_RDESC_SWAPPED_MIN_MAX },
{ USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_2, HID_QUIRK_RDESC_SWAPPED_MIN_MAX },
*
* Returns: 0 OK, -error on failure.
*/
-int usbhid_modify_dquirk(const u16 idVendor, const u16 idProduct,
- const u32 quirks)
+static int usbhid_modify_dquirk(const u16 idVendor, const u16 idProduct,
+ const u32 quirks)
{
struct quirks_list_struct *q_new, *q;
int list_edited = 0;
}
}
+static void usbhid_fixup_sunplus_wdesktop(unsigned char *rdesc, int rsize)
+{
+ if (rsize >= 107 && rdesc[104] == 0x26
+ && rdesc[105] == 0x80
+ && rdesc[106] == 0x03) {
+ printk(KERN_INFO "Fixing up Sunplus Wireless Desktop report descriptor\n");
+ rdesc[105] = rdesc[110] = 0x03;
+ rdesc[106] = rdesc[111] = 0x21;
+ }
+}
+
/*
* Samsung IrDA remote controller (reports as Cypress USB Mouse).
*
}
}
+/*
+ * Microsoft Wireless Desktop Receiver (Model 1028) has several
+ * 'Usage Min/Max' where it ought to have 'Physical Min/Max'
+ */
+static void usbhid_fixup_microsoft_descriptor(unsigned char *rdesc, int rsize)
+{
+ if (rsize == 571 && rdesc[284] == 0x19
+ && rdesc[286] == 0x2a
+ && rdesc[304] == 0x19
+ && rdesc[306] == 0x29
+ && rdesc[352] == 0x1a
+ && rdesc[355] == 0x2a
+ && rdesc[557] == 0x19
+ && rdesc[559] == 0x29) {
+ printk(KERN_INFO "Fixing up Microsoft Wireless Receiver Model 1028 report descriptor\n");
+ rdesc[284] = rdesc[304] = rdesc[558] = 0x35;
+ rdesc[352] = 0x36;
+ rdesc[286] = rdesc[355] = 0x46;
+ rdesc[306] = rdesc[559] = 0x45;
+ }
+}
+
static void __usbhid_fixup_report_descriptor(__u32 quirks, char *rdesc, unsigned rsize)
{
if ((quirks & HID_QUIRK_RDESC_CYMOTION))
if (quirks & HID_QUIRK_RDESC_SAMSUNG_REMOTE)
usbhid_fixup_samsung_irda_descriptor(rdesc, rsize);
+ if (quirks & HID_QUIRK_RDESC_MICROSOFT_RECV_1028)
+ usbhid_fixup_microsoft_descriptor(rdesc, rsize);
+
+ if (quirks & HID_QUIRK_RDESC_SUNPLUS_WDESKTOP)
+ usbhid_fixup_sunplus_wdesktop(rdesc, rsize);
}
/**
else if (paramVendor == idVendor && paramProduct == idProduct)
__usbhid_fixup_report_descriptor(quirks, rdesc, rsize);
}
-
}
/*
* "ioctl" file op
*/
+static noinline int hiddev_ioctl_usage(struct hiddev *hiddev, unsigned int cmd, void __user *user_arg)
+{
+ struct hid_device *hid = hiddev->hid;
+ struct hiddev_report_info rinfo;
+ struct hiddev_usage_ref_multi *uref_multi = NULL;
+ struct hiddev_usage_ref *uref;
+ struct hid_report *report;
+ struct hid_field *field;
+ int i;
+
+ uref_multi = kmalloc(sizeof(struct hiddev_usage_ref_multi), GFP_KERNEL);
+ if (!uref_multi)
+ return -ENOMEM;
+ uref = &uref_multi->uref;
+ if (cmd == HIDIOCGUSAGES || cmd == HIDIOCSUSAGES) {
+ if (copy_from_user(uref_multi, user_arg,
+ sizeof(*uref_multi)))
+ goto fault;
+ } else {
+ if (copy_from_user(uref, user_arg, sizeof(*uref)))
+ goto fault;
+ }
+
+ switch (cmd) {
+ case HIDIOCGUCODE:
+ rinfo.report_type = uref->report_type;
+ rinfo.report_id = uref->report_id;
+ if ((report = hiddev_lookup_report(hid, &rinfo)) == NULL)
+ goto inval;
+
+ if (uref->field_index >= report->maxfield)
+ goto inval;
+
+ field = report->field[uref->field_index];
+ if (uref->usage_index >= field->maxusage)
+ goto inval;
+
+ uref->usage_code = field->usage[uref->usage_index].hid;
+
+ if (copy_to_user(user_arg, uref, sizeof(*uref)))
+ goto fault;
+
+ kfree(uref_multi);
+ return 0;
+
+ default:
+ if (cmd != HIDIOCGUSAGE &&
+ cmd != HIDIOCGUSAGES &&
+ uref->report_type == HID_REPORT_TYPE_INPUT)
+ goto inval;
+
+ if (uref->report_id == HID_REPORT_ID_UNKNOWN) {
+ field = hiddev_lookup_usage(hid, uref);
+ if (field == NULL)
+ goto inval;
+ } else {
+ rinfo.report_type = uref->report_type;
+ rinfo.report_id = uref->report_id;
+ if ((report = hiddev_lookup_report(hid, &rinfo)) == NULL)
+ goto inval;
+
+ if (uref->field_index >= report->maxfield)
+ goto inval;
+
+ field = report->field[uref->field_index];
+
+ if (cmd == HIDIOCGCOLLECTIONINDEX) {
+ if (uref->usage_index >= field->maxusage)
+ goto inval;
+ } else if (uref->usage_index >= field->report_count)
+ goto inval;
+
+ else if ((cmd == HIDIOCGUSAGES || cmd == HIDIOCSUSAGES) &&
+ (uref_multi->num_values > HID_MAX_MULTI_USAGES ||
+ uref->usage_index + uref_multi->num_values > field->report_count))
+ goto inval;
+ }
+
+ switch (cmd) {
+ case HIDIOCGUSAGE:
+ uref->value = field->value[uref->usage_index];
+ if (copy_to_user(user_arg, uref, sizeof(*uref)))
+ goto fault;
+ goto goodreturn;
+
+ case HIDIOCSUSAGE:
+ field->value[uref->usage_index] = uref->value;
+ goto goodreturn;
+
+ case HIDIOCGCOLLECTIONINDEX:
+ kfree(uref_multi);
+ return field->usage[uref->usage_index].collection_index;
+ case HIDIOCGUSAGES:
+ for (i = 0; i < uref_multi->num_values; i++)
+ uref_multi->values[i] =
+ field->value[uref->usage_index + i];
+ if (copy_to_user(user_arg, uref_multi,
+ sizeof(*uref_multi)))
+ goto fault;
+ goto goodreturn;
+ case HIDIOCSUSAGES:
+ for (i = 0; i < uref_multi->num_values; i++)
+ field->value[uref->usage_index + i] =
+ uref_multi->values[i];
+ goto goodreturn;
+ }
+
+goodreturn:
+ kfree(uref_multi);
+ return 0;
+fault:
+ kfree(uref_multi);
+ return -EFAULT;
+inval:
+ kfree(uref_multi);
+ return -EINVAL;
+ }
+}
+
+static noinline int hiddev_ioctl_string(struct hiddev *hiddev, unsigned int cmd, void __user *user_arg)
+{
+ struct hid_device *hid = hiddev->hid;
+ struct usb_device *dev = hid_to_usb_dev(hid);
+ int idx, len;
+ char *buf;
+
+ if (get_user(idx, (int __user *)user_arg))
+ return -EFAULT;
+
+ if ((buf = kmalloc(HID_STRING_SIZE, GFP_KERNEL)) == NULL)
+ return -ENOMEM;
+
+ if ((len = usb_string(dev, idx, buf, HID_STRING_SIZE-1)) < 0) {
+ kfree(buf);
+ return -EINVAL;
+ }
+
+ if (copy_to_user(user_arg+sizeof(int), buf, len+1)) {
+ kfree(buf);
+ return -EFAULT;
+ }
+
+ kfree(buf);
+
+ return len;
+}
+
static int hiddev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
{
struct hiddev_list *list = file->private_data;
struct hiddev_collection_info cinfo;
struct hiddev_report_info rinfo;
struct hiddev_field_info finfo;
- struct hiddev_usage_ref_multi *uref_multi = NULL;
- struct hiddev_usage_ref *uref;
struct hiddev_devinfo dinfo;
struct hid_report *report;
struct hid_field *field;
}
case HIDIOCGSTRING:
- {
- int idx, len;
- char *buf;
-
- if (get_user(idx, (int __user *)arg))
- return -EFAULT;
-
- if ((buf = kmalloc(HID_STRING_SIZE, GFP_KERNEL)) == NULL)
- return -ENOMEM;
-
- if ((len = usb_string(dev, idx, buf, HID_STRING_SIZE-1)) < 0) {
- kfree(buf);
- return -EINVAL;
- }
-
- if (copy_to_user(user_arg+sizeof(int), buf, len+1)) {
- kfree(buf);
- return -EFAULT;
- }
-
- kfree(buf);
-
- return len;
- }
+ return hiddev_ioctl_string(hiddev, cmd, user_arg);
case HIDIOCINITREPORT:
usbhid_init_reports(hid);
return 0;
case HIDIOCGUCODE:
- uref_multi = kmalloc(sizeof(struct hiddev_usage_ref_multi), GFP_KERNEL);
- if (!uref_multi)
- return -ENOMEM;
- uref = &uref_multi->uref;
- if (copy_from_user(uref, user_arg, sizeof(*uref)))
- goto fault;
-
- rinfo.report_type = uref->report_type;
- rinfo.report_id = uref->report_id;
- if ((report = hiddev_lookup_report(hid, &rinfo)) == NULL)
- goto inval;
-
- if (uref->field_index >= report->maxfield)
- goto inval;
-
- field = report->field[uref->field_index];
- if (uref->usage_index >= field->maxusage)
- goto inval;
-
- uref->usage_code = field->usage[uref->usage_index].hid;
-
- if (copy_to_user(user_arg, uref, sizeof(*uref)))
- goto fault;
-
- kfree(uref_multi);
- return 0;
-
+ /* fall through */
case HIDIOCGUSAGE:
case HIDIOCSUSAGE:
case HIDIOCGUSAGES:
case HIDIOCSUSAGES:
case HIDIOCGCOLLECTIONINDEX:
- uref_multi = kmalloc(sizeof(struct hiddev_usage_ref_multi), GFP_KERNEL);
- if (!uref_multi)
- return -ENOMEM;
- uref = &uref_multi->uref;
- if (cmd == HIDIOCGUSAGES || cmd == HIDIOCSUSAGES) {
- if (copy_from_user(uref_multi, user_arg,
- sizeof(*uref_multi)))
- goto fault;
- } else {
- if (copy_from_user(uref, user_arg, sizeof(*uref)))
- goto fault;
- }
-
- if (cmd != HIDIOCGUSAGE &&
- cmd != HIDIOCGUSAGES &&
- uref->report_type == HID_REPORT_TYPE_INPUT)
- goto inval;
-
- if (uref->report_id == HID_REPORT_ID_UNKNOWN) {
- field = hiddev_lookup_usage(hid, uref);
- if (field == NULL)
- goto inval;
- } else {
- rinfo.report_type = uref->report_type;
- rinfo.report_id = uref->report_id;
- if ((report = hiddev_lookup_report(hid, &rinfo)) == NULL)
- goto inval;
-
- if (uref->field_index >= report->maxfield)
- goto inval;
-
- field = report->field[uref->field_index];
-
- if (cmd == HIDIOCGCOLLECTIONINDEX) {
- if (uref->usage_index >= field->maxusage)
- goto inval;
- } else if (uref->usage_index >= field->report_count)
- goto inval;
-
- else if ((cmd == HIDIOCGUSAGES || cmd == HIDIOCSUSAGES) &&
- (uref_multi->num_values > HID_MAX_MULTI_USAGES ||
- uref->usage_index + uref_multi->num_values > field->report_count))
- goto inval;
- }
-
- switch (cmd) {
- case HIDIOCGUSAGE:
- uref->value = field->value[uref->usage_index];
- if (copy_to_user(user_arg, uref, sizeof(*uref)))
- goto fault;
- goto goodreturn;
-
- case HIDIOCSUSAGE:
- field->value[uref->usage_index] = uref->value;
- goto goodreturn;
-
- case HIDIOCGCOLLECTIONINDEX:
- kfree(uref_multi);
- return field->usage[uref->usage_index].collection_index;
- case HIDIOCGUSAGES:
- for (i = 0; i < uref_multi->num_values; i++)
- uref_multi->values[i] =
- field->value[uref->usage_index + i];
- if (copy_to_user(user_arg, uref_multi,
- sizeof(*uref_multi)))
- goto fault;
- goto goodreturn;
- case HIDIOCSUSAGES:
- for (i = 0; i < uref_multi->num_values; i++)
- field->value[uref->usage_index + i] =
- uref_multi->values[i];
- goto goodreturn;
- }
-
-goodreturn:
- kfree(uref_multi);
- return 0;
-fault:
- kfree(uref_multi);
- return -EFAULT;
-inval:
- kfree(uref_multi);
- return -EINVAL;
+ return hiddev_ioctl_usage(hiddev, cmd, user_arg);
case HIDIOCGCOLLECTIONINFO:
if (copy_from_user(&cinfo, user_arg, sizeof(cinfo)))
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/timer.h>
+#include <linux/wait.h>
#include <linux/workqueue.h>
#include <linux/input.h>
unsigned long stop_retry; /* Time to give up, in jiffies */
unsigned int retry_delay; /* Delay length in ms */
struct work_struct reset_work; /* Task context for resets */
-
+ wait_queue_head_t wait; /* For sleeping */
};
#define hid_to_usb_dev(hid_dev) \
#
-# Character device configuration
+# I2C algorithm drivers configuration
#
-menu "I2C Algorithms"
-
config I2C_ALGOBIT
- tristate "I2C bit-banging interfaces"
- help
- This allows you to use a range of I2C adapters called bit-banging
- adapters. Say Y if you own an I2C adapter belonging to this class
- and then say Y to the specific driver for you adapter below.
-
- This support is also available as a module. If so, the module
- will be called i2c-algo-bit.
+ tristate
config I2C_ALGOPCF
- tristate "I2C PCF 8584 interfaces"
- help
- This allows you to use a range of I2C adapters called PCF adapters.
- Say Y if you own an I2C adapter belonging to this class and then say
- Y to the specific driver for you adapter below.
-
- This support is also available as a module. If so, the module
- will be called i2c-algo-pcf.
+ tristate
config I2C_ALGOPCA
- tristate "I2C PCA 9564 interfaces"
- help
- This allows you to use a range of I2C adapters called PCA adapters.
- Say Y if you own an I2C adapter belonging to this class and then say
- Y to the specific driver for you adapter below.
-
- This support is also available as a module. If so, the module
- will be called i2c-algo-pca.
+ tristate
config I2C_ALGO_SGI
- tristate "I2C SGI interfaces"
+ tristate
depends on SGI_IP22 || SGI_IP32 || X86_VISWS
- help
- Supports the SGI interfaces like the ones found on SGI Indy VINO
- or SGI O2 MACE.
-
-endmenu
-
/*
- * i2c-algo-pca.c i2c driver algorithms for PCA9564 adapters
+ * i2c-algo-pca.c i2c driver algorithms for PCA9564 adapters
* Copyright (C) 2004 Arcom Control Systems
+ * Copyright (C) 2008 Pengutronix
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/delay.h>
-#include <linux/slab.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-pca.h>
-#include "i2c-algo-pca.h"
-
-#define DRIVER "i2c-algo-pca"
#define DEB1(fmt, args...) do { if (i2c_debug>=1) printk(fmt, ## args); } while(0)
#define DEB2(fmt, args...) do { if (i2c_debug>=2) printk(fmt, ## args); } while(0)
static int i2c_debug;
-#define pca_outw(adap, reg, val) adap->write_byte(adap, reg, val)
-#define pca_inw(adap, reg) adap->read_byte(adap, reg)
+#define pca_outw(adap, reg, val) adap->write_byte(adap->data, reg, val)
+#define pca_inw(adap, reg) adap->read_byte(adap->data, reg)
#define pca_status(adap) pca_inw(adap, I2C_PCA_STA)
-#define pca_clock(adap) adap->get_clock(adap)
-#define pca_own(adap) adap->get_own(adap)
+#define pca_clock(adap) adap->i2c_clock
#define pca_set_con(adap, val) pca_outw(adap, I2C_PCA_CON, val)
#define pca_get_con(adap) pca_inw(adap, I2C_PCA_CON)
-#define pca_wait(adap) adap->wait_for_interrupt(adap)
+#define pca_wait(adap) adap->wait_for_completion(adap->data)
+#define pca_reset(adap) adap->reset_chip(adap->data)
/*
* Generate a start condition on the i2c bus.
*
* returns after the address has been sent
*/
-static void pca_address(struct i2c_algo_pca_data *adap,
+static void pca_address(struct i2c_algo_pca_data *adap,
struct i2c_msg *msg)
{
int sta = pca_get_con(adap);
addr = ( (0x7f & msg->addr) << 1 );
if (msg->flags & I2C_M_RD )
addr |= 1;
- DEB2("=== SLAVE ADDRESS %#04x+%c=%#04x\n",
+ DEB2("=== SLAVE ADDRESS %#04x+%c=%#04x\n",
msg->addr, msg->flags & I2C_M_RD ? 'R' : 'W', addr);
-
+
pca_outw(adap, I2C_PCA_DAT, addr);
sta &= ~(I2C_PCA_CON_STO|I2C_PCA_CON_STA|I2C_PCA_CON_SI);
*
* Returns after the byte has been transmitted
*/
-static void pca_tx_byte(struct i2c_algo_pca_data *adap,
+static void pca_tx_byte(struct i2c_algo_pca_data *adap,
__u8 b)
{
int sta = pca_get_con(adap);
*
* returns immediately.
*/
-static void pca_rx_byte(struct i2c_algo_pca_data *adap,
+static void pca_rx_byte(struct i2c_algo_pca_data *adap,
__u8 *b, int ack)
{
*b = pca_inw(adap, I2C_PCA_DAT);
DEB2("=== READ %#04x %s\n", *b, ack ? "ACK" : "NACK");
}
-/*
+/*
* Setup ACK or NACK for next received byte and wait for it to arrive.
*
* Returns after next byte has arrived.
*/
-static void pca_rx_ack(struct i2c_algo_pca_data *adap,
+static void pca_rx_ack(struct i2c_algo_pca_data *adap,
int ack)
{
int sta = pca_get_con(adap);
pca_wait(adap);
}
-/*
- * Reset the i2c bus / SIO
- */
-static void pca_reset(struct i2c_algo_pca_data *adap)
-{
- /* apparently only an external reset will do it. not a lot can be done */
- printk(KERN_ERR DRIVER ": Haven't figured out how to do a reset yet\n");
-}
-
static int pca_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg *msgs,
int num)
int numbytes = 0;
int state;
int ret;
- int timeout = 100;
+ int timeout = i2c_adap->timeout;
while ((state = pca_status(adap)) != 0xf8 && timeout--) {
msleep(10);
for (curmsg = 0; curmsg < num; curmsg++) {
int addr, i;
msg = &msgs[curmsg];
-
+
addr = (0x7f & msg->addr) ;
-
+
if (msg->flags & I2C_M_RD )
- printk(KERN_INFO " [%02d] RD %d bytes from %#02x [%#02x, ...]\n",
+ printk(KERN_INFO " [%02d] RD %d bytes from %#02x [%#02x, ...]\n",
curmsg, msg->len, addr, (addr<<1) | 1);
else {
- printk(KERN_INFO " [%02d] WR %d bytes to %#02x [%#02x%s",
+ printk(KERN_INFO " [%02d] WR %d bytes to %#02x [%#02x%s",
curmsg, msg->len, addr, addr<<1,
msg->len == 0 ? "" : ", ");
for(i=0; i < msg->len; i++)
case 0x10: /* A repeated start condition has been transmitted */
pca_address(adap, msg);
break;
-
+
case 0x18: /* SLA+W has been transmitted; ACK has been received */
case 0x28: /* Data byte in I2CDAT has been transmitted; ACK has been received */
if (numbytes < msg->len) {
case 0x38: /* Arbitration lost during SLA+W, SLA+R or data bytes */
DEB2("Arbitration lost\n");
goto out;
-
+
case 0x58: /* Data byte has been received; NOT ACK has been returned */
if ( numbytes == msg->len - 1 ) {
pca_rx_byte(adap, &msg->buf[numbytes], 0);
pca_reset(adap);
goto out;
default:
- printk(KERN_ERR DRIVER ": unhandled SIO state 0x%02x\n", state);
+ dev_err(&i2c_adap->dev, "unhandled SIO state 0x%02x\n", state);
break;
}
-
+
}
ret = curmsg;
out:
DEB1(KERN_CRIT "}}} transfered %d/%d messages. "
- "status is %#04x. control is %#04x\n",
+ "status is %#04x. control is %#04x\n",
curmsg, num, pca_status(adap),
pca_get_con(adap));
return ret;
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
-static int pca_init(struct i2c_algo_pca_data *adap)
+static const struct i2c_algorithm pca_algo = {
+ .master_xfer = pca_xfer,
+ .functionality = pca_func,
+};
+
+static int pca_init(struct i2c_adapter *adap)
{
static int freqs[] = {330,288,217,146,88,59,44,36};
- int own, clock;
+ int clock;
+ struct i2c_algo_pca_data *pca_data = adap->algo_data;
+
+ if (pca_data->i2c_clock > 7) {
+ printk(KERN_WARNING "%s: Invalid I2C clock speed selected. Trying default.\n",
+ adap->name);
+ pca_data->i2c_clock = I2C_PCA_CON_59kHz;
+ }
+
+ adap->algo = &pca_algo;
- own = pca_own(adap);
- clock = pca_clock(adap);
- DEB1(KERN_INFO DRIVER ": own address is %#04x\n", own);
- DEB1(KERN_INFO DRIVER ": clock freqeuncy is %dkHz\n", freqs[clock]);
+ pca_reset(pca_data);
- pca_outw(adap, I2C_PCA_ADR, own << 1);
+ clock = pca_clock(pca_data);
+ DEB1(KERN_INFO "%s: Clock frequency is %dkHz\n", adap->name, freqs[clock]);
- pca_set_con(adap, I2C_PCA_CON_ENSIO | clock);
- udelay(500); /* 500 µs for oscilator to stabilise */
+ pca_set_con(pca_data, I2C_PCA_CON_ENSIO | clock);
+ udelay(500); /* 500 us for oscilator to stabilise */
return 0;
}
-static const struct i2c_algorithm pca_algo = {
- .master_xfer = pca_xfer,
- .functionality = pca_func,
-};
-
-/*
- * registering functions to load algorithms at runtime
+/*
+ * registering functions to load algorithms at runtime
*/
int i2c_pca_add_bus(struct i2c_adapter *adap)
{
- struct i2c_algo_pca_data *pca_adap = adap->algo_data;
int rval;
- /* register new adapter to i2c module... */
- adap->algo = &pca_algo;
+ rval = pca_init(adap);
+ if (rval)
+ return rval;
- adap->timeout = 100; /* default values, should */
- adap->retries = 3; /* be replaced by defines */
+ return i2c_add_adapter(adap);
+}
+EXPORT_SYMBOL(i2c_pca_add_bus);
- if ((rval = pca_init(pca_adap)))
- return rval;
+int i2c_pca_add_numbered_bus(struct i2c_adapter *adap)
+{
+ int rval;
- rval = i2c_add_adapter(adap);
+ rval = pca_init(adap);
+ if (rval)
+ return rval;
- return rval;
+ return i2c_add_numbered_adapter(adap);
}
-EXPORT_SYMBOL(i2c_pca_add_bus);
+EXPORT_SYMBOL(i2c_pca_add_numbered_bus);
-MODULE_AUTHOR("Ian Campbell <icampbell@arcom.com>");
+MODULE_AUTHOR("Ian Campbell <icampbell@arcom.com>, "
+ "Wolfram Sang <w.sang@pengutronix.de>");
MODULE_DESCRIPTION("I2C-Bus PCA9564 algorithm");
MODULE_LICENSE("GPL");
+++ /dev/null
-#ifndef I2C_PCA9564_H
-#define I2C_PCA9564_H 1
-
-#define I2C_PCA_STA 0x00 /* STATUS Read Only */
-#define I2C_PCA_TO 0x00 /* TIMEOUT Write Only */
-#define I2C_PCA_DAT 0x01 /* DATA Read/Write */
-#define I2C_PCA_ADR 0x02 /* OWN ADR Read/Write */
-#define I2C_PCA_CON 0x03 /* CONTROL Read/Write */
-
-#define I2C_PCA_CON_AA 0x80 /* Assert Acknowledge */
-#define I2C_PCA_CON_ENSIO 0x40 /* Enable */
-#define I2C_PCA_CON_STA 0x20 /* Start */
-#define I2C_PCA_CON_STO 0x10 /* Stop */
-#define I2C_PCA_CON_SI 0x08 /* Serial Interrupt */
-#define I2C_PCA_CON_CR 0x07 /* Clock Rate (MASK) */
-
-#define I2C_PCA_CON_330kHz 0x00
-#define I2C_PCA_CON_288kHz 0x01
-#define I2C_PCA_CON_217kHz 0x02
-#define I2C_PCA_CON_146kHz 0x03
-#define I2C_PCA_CON_88kHz 0x04
-#define I2C_PCA_CON_59kHz 0x05
-#define I2C_PCA_CON_44kHz 0x06
-#define I2C_PCA_CON_36kHz 0x07
-
-#endif /* I2C_PCA9564_H */
config I2C_BLACKFIN_TWI
tristate "Blackfin TWI I2C support"
- depends on BF534 || BF536 || BF537
+ depends on BLACKFIN
help
- This is the TWI I2C device driver for Blackfin 534/536/537/54x.
+ This is the TWI I2C device driver for Blackfin BF522, BF525,
+ BF527, BF534, BF536, BF537 and BF54x. For other Blackfin processors,
+ please don't use this driver.
+
This driver can also be built as a module. If so, the module
will be called i2c-bfin-twi.
This supports the PCF8584 ISA bus I2C adapter. Say Y if you own
such an adapter.
- This support is also available as a module. If so, the module
+ This support is also available as a module. If so, the module
will be called i2c-elektor.
config I2C_GPIO
select I2C_ALGOBIT
help
If you say yes to this option, support will be included for the Intel
- 810/815 family of mainboard I2C interfaces. Specifically, the
+ 810/815 family of mainboard I2C interfaces. Specifically, the
following versions of the chipset are supported:
i810AA
i810AB
config I2C_IBM_IIC
tristate "IBM PPC 4xx on-chip I2C interface"
- depends on IBM_OCP
+ depends on 4xx
help
- Say Y here if you want to use IIC peripheral found on
- embedded IBM PPC 4xx based systems.
+ Say Y here if you want to use IIC peripheral found on
+ embedded IBM PPC 4xx based systems.
This driver can also be built as a module. If so, the module
will be called i2c-ibm_iic.
depends on ARCH_IXP2000
select I2C_ALGOBIT
help
- Say Y here if you have an Intel IXP2000 (2400, 2800, 2850) based
+ Say Y here if you have an Intel IXP2000 (2400, 2800, 2850) based
system and are using GPIO lines for an I2C bus.
This support is also available as a module. If so, the module
on the parport driver. This is meant for embedded systems. Don't say
Y here if you intend to say Y or M there.
- This support is also available as a module. If so, the module
+ This support is also available as a module. If so, the module
will be called i2c-parport.
config I2C_PARPORT_LIGHT
the clean but heavy parport handling is not an option. The
drawback is a reduced portability and the impossibility to
daisy-chain other parallel port devices.
-
+
Don't say Y here if you said Y or M to i2c-parport. Saying M to
both is possible but both modules should not be loaded at the same
time.
- This support is also available as a module. If so, the module
+ This support is also available as a module. If so, the module
will be called i2c-parport-light.
config I2C_PASEMI
This driver is deprecated in favor of the savagefb driver.
- This support is also available as a module. If so, the module
+ This support is also available as a module. If so, the module
will be called i2c-prosavage.
config I2C_S3C2410
depends on PCI
select I2C_ALGOBIT
help
- If you say yes to this option, support will be included for the
+ If you say yes to this option, support will be included for the
S3 Savage 4 I2C interface.
This driver is deprecated in favor of the savagefb driver.
If you don't know what to do here, say N.
- This support is also available as a module. If so, the module
+ This support is also available as a module. If so, the module
will be called scx200_i2c.
This driver is deprecated and will be dropped soon. Use i2c-gpio
If you don't know what to do here, say N.
- This support is also available as a module. If so, the module
+ This support is also available as a module. If so, the module
will be called scx200_acb.
config I2C_SIS5595
tristate "SiS 5595"
depends on PCI
help
- If you say yes to this option, support will be included for the
+ If you say yes to this option, support will be included for the
SiS5595 SMBus (a subset of I2C) interface.
This driver can also be built as a module. If so, the module
tristate "SiS 630/730"
depends on PCI
help
- If you say yes to this option, support will be included for the
+ If you say yes to this option, support will be included for the
SiS630 and SiS730 SMBus (a subset of I2C) interface.
This driver can also be built as a module. If so, the module
select I2C_ALGOPCA
default n
help
- This driver supports ISA boards using the Philips PCA 9564
- Parallel bus to I2C bus controller
-
+ This driver supports ISA boards using the Philips PCA9564
+ parallel bus to I2C bus controller.
+
This driver can also be built as a module. If so, the module
will be called i2c-pca-isa.
delays when I2C/SMBus chip drivers are loaded (e.g. at boot
time). If unsure, say N.
+config I2C_PCA_PLATFORM
+ tristate "PCA9564 as platform device"
+ select I2C_ALGOPCA
+ default n
+ help
+ This driver supports a memory mapped Philips PCA9564
+ parallel bus to I2C bus controller.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-pca-platform.
+
config I2C_MV64XXX
tristate "Marvell mv64xxx I2C Controller"
- depends on (MV64X60 || ARCH_ORION) && EXPERIMENTAL
+ depends on (MV64X60 || PLAT_ORION) && EXPERIMENTAL
help
If you say yes to this option, support will be included for the
built-in I2C interface on the Marvell 64xxx line of host bridges.
This driver can also be built as module. If so, the module
will be called i2c-pmcmsp.
+config I2C_SH7760
+ tristate "Renesas SH7760 I2C Controller"
+ depends on CPU_SUBTYPE_SH7760
+ help
+ This driver supports the 2 I2C interfaces on the Renesas SH7760.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-sh7760.
+
+config I2C_SH_MOBILE
+ tristate "SuperH Mobile I2C Controller"
+ depends on SUPERH
+ help
+ If you say yes to this option, support will be included for the
+ built-in I2C interface on the Renesas SH-Mobile processor.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-sh_mobile.
+
endmenu
obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o
obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
+obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o
obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o
obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o
obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
obj-$(CONFIG_I2C_SAVAGE4) += i2c-savage4.o
+obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
+obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
obj-$(CONFIG_I2C_SIS5595) += i2c-sis5595.o
#endif
/* work with "modprobe at91_i2c" from hotplugging or coldplugging */
-MODULE_ALIAS("at91_i2c");
+MODULE_ALIAS("platform:at91_i2c");
static struct platform_driver at91_i2c_driver = {
.probe = at91_i2c_probe,
MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:au1xpsc_smbus");
module_init (i2c_au1550_init);
module_exit (i2c_au1550_exit);
/*
- * drivers/i2c/busses/i2c-bfin-twi.c
+ * Blackfin On-Chip Two Wire Interface Driver
*
- * Description: Driver for Blackfin Two Wire Interface
+ * Copyright 2005-2007 Analog Devices Inc.
*
- * Author: sonicz <sonic.zhang@analog.com>
+ * Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (c) 2005-2007 Analog Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * Licensed under the GPL-2 or later.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <asm/blackfin.h>
+#include <asm/portmux.h>
#include <asm/irq.h>
#define POLL_TIMEOUT (2 * HZ)
/* SMBus mode*/
-#define TWI_I2C_MODE_STANDARD 0x01
-#define TWI_I2C_MODE_STANDARDSUB 0x02
-#define TWI_I2C_MODE_COMBINED 0x04
+#define TWI_I2C_MODE_STANDARD 1
+#define TWI_I2C_MODE_STANDARDSUB 2
+#define TWI_I2C_MODE_COMBINED 3
+#define TWI_I2C_MODE_REPEAT 4
struct bfin_twi_iface {
int irq;
struct timer_list timeout_timer;
struct i2c_adapter adap;
struct completion complete;
+ struct i2c_msg *pmsg;
+ int msg_num;
+ int cur_msg;
+ void __iomem *regs_base;
};
-static struct bfin_twi_iface twi_iface;
+
+#define DEFINE_TWI_REG(reg, off) \
+static inline u16 read_##reg(struct bfin_twi_iface *iface) \
+ { return bfin_read16(iface->regs_base + (off)); } \
+static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
+ { bfin_write16(iface->regs_base + (off), v); }
+
+DEFINE_TWI_REG(CLKDIV, 0x00)
+DEFINE_TWI_REG(CONTROL, 0x04)
+DEFINE_TWI_REG(SLAVE_CTL, 0x08)
+DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
+DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
+DEFINE_TWI_REG(MASTER_CTL, 0x14)
+DEFINE_TWI_REG(MASTER_STAT, 0x18)
+DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
+DEFINE_TWI_REG(INT_STAT, 0x20)
+DEFINE_TWI_REG(INT_MASK, 0x24)
+DEFINE_TWI_REG(FIFO_CTL, 0x28)
+DEFINE_TWI_REG(FIFO_STAT, 0x2C)
+DEFINE_TWI_REG(XMT_DATA8, 0x80)
+DEFINE_TWI_REG(XMT_DATA16, 0x84)
+DEFINE_TWI_REG(RCV_DATA8, 0x88)
+DEFINE_TWI_REG(RCV_DATA16, 0x8C)
+
+static const u16 pin_req[2][3] = {
+ {P_TWI0_SCL, P_TWI0_SDA, 0},
+ {P_TWI1_SCL, P_TWI1_SDA, 0},
+};
static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
{
- unsigned short twi_int_status = bfin_read_TWI_INT_STAT();
- unsigned short mast_stat = bfin_read_TWI_MASTER_STAT();
+ unsigned short twi_int_status = read_INT_STAT(iface);
+ unsigned short mast_stat = read_MASTER_STAT(iface);
if (twi_int_status & XMTSERV) {
/* Transmit next data */
if (iface->writeNum > 0) {
- bfin_write_TWI_XMT_DATA8(*(iface->transPtr++));
+ write_XMT_DATA8(iface, *(iface->transPtr++));
iface->writeNum--;
}
/* start receive immediately after complete sending in
* combine mode.
*/
- else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
- bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
- | MDIR | RSTART);
- } else if (iface->manual_stop)
- bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
- | STOP);
+ else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) | MDIR | RSTART);
+ else if (iface->manual_stop)
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) | STOP);
+ else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
+ iface->cur_msg+1 < iface->msg_num)
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) | RSTART);
SSYNC();
/* Clear status */
- bfin_write_TWI_INT_STAT(XMTSERV);
+ write_INT_STAT(iface, XMTSERV);
SSYNC();
}
if (twi_int_status & RCVSERV) {
if (iface->readNum > 0) {
/* Receive next data */
- *(iface->transPtr) = bfin_read_TWI_RCV_DATA8();
+ *(iface->transPtr) = read_RCV_DATA8(iface);
if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
/* Change combine mode into sub mode after
* read first data.
iface->transPtr++;
iface->readNum--;
} else if (iface->manual_stop) {
- bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
- | STOP);
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) | STOP);
+ SSYNC();
+ } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
+ iface->cur_msg+1 < iface->msg_num) {
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) | RSTART);
SSYNC();
}
/* Clear interrupt source */
- bfin_write_TWI_INT_STAT(RCVSERV);
+ write_INT_STAT(iface, RCVSERV);
SSYNC();
}
if (twi_int_status & MERR) {
- bfin_write_TWI_INT_STAT(MERR);
- bfin_write_TWI_INT_MASK(0);
- bfin_write_TWI_MASTER_STAT(0x3e);
- bfin_write_TWI_MASTER_CTL(0);
+ write_INT_STAT(iface, MERR);
+ write_INT_MASK(iface, 0);
+ write_MASTER_STAT(iface, 0x3e);
+ write_MASTER_CTL(iface, 0);
SSYNC();
- iface->result = -1;
+ iface->result = -EIO;
/* if both err and complete int stats are set, return proper
* results.
*/
if (twi_int_status & MCOMP) {
- bfin_write_TWI_INT_STAT(MCOMP);
- bfin_write_TWI_INT_MASK(0);
- bfin_write_TWI_MASTER_CTL(0);
+ write_INT_STAT(iface, MCOMP);
+ write_INT_MASK(iface, 0);
+ write_MASTER_CTL(iface, 0);
SSYNC();
/* If it is a quick transfer, only address bug no data,
* not an err, return 1.
return;
}
if (twi_int_status & MCOMP) {
- bfin_write_TWI_INT_STAT(MCOMP);
+ write_INT_STAT(iface, MCOMP);
SSYNC();
if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
if (iface->readNum == 0) {
*/
iface->readNum = 1;
iface->manual_stop = 1;
- bfin_write_TWI_MASTER_CTL(
- bfin_read_TWI_MASTER_CTL()
- | (0xff << 6));
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) | (0xff << 6));
} else {
/* set the readd number in other
* combine mode.
*/
- bfin_write_TWI_MASTER_CTL(
- (bfin_read_TWI_MASTER_CTL() &
+ write_MASTER_CTL(iface,
+ (read_MASTER_CTL(iface) &
(~(0xff << 6))) |
- ( iface->readNum << 6));
+ (iface->readNum << 6));
+ }
+ /* remove restart bit and enable master receive */
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) & ~RSTART);
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) | MEN | MDIR);
+ SSYNC();
+ } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
+ iface->cur_msg+1 < iface->msg_num) {
+ iface->cur_msg++;
+ iface->transPtr = iface->pmsg[iface->cur_msg].buf;
+ iface->writeNum = iface->readNum =
+ iface->pmsg[iface->cur_msg].len;
+ /* Set Transmit device address */
+ write_MASTER_ADDR(iface,
+ iface->pmsg[iface->cur_msg].addr);
+ if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
+ iface->read_write = I2C_SMBUS_READ;
+ else {
+ iface->read_write = I2C_SMBUS_WRITE;
+ /* Transmit first data */
+ if (iface->writeNum > 0) {
+ write_XMT_DATA8(iface,
+ *(iface->transPtr++));
+ iface->writeNum--;
+ SSYNC();
+ }
+ }
+
+ if (iface->pmsg[iface->cur_msg].len <= 255)
+ write_MASTER_CTL(iface,
+ iface->pmsg[iface->cur_msg].len << 6);
+ else {
+ write_MASTER_CTL(iface, 0xff << 6);
+ iface->manual_stop = 1;
}
/* remove restart bit and enable master receive */
- bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() &
- ~RSTART);
- bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() |
- MEN | MDIR);
+ write_MASTER_CTL(iface,
+ read_MASTER_CTL(iface) & ~RSTART);
+ write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
+ MEN | ((iface->read_write == I2C_SMBUS_READ) ?
+ MDIR : 0));
SSYNC();
} else {
iface->result = 1;
- bfin_write_TWI_INT_MASK(0);
- bfin_write_TWI_MASTER_CTL(0);
+ write_INT_MASK(iface, 0);
+ write_MASTER_CTL(iface, 0);
SSYNC();
complete(&iface->complete);
}
{
struct bfin_twi_iface *iface = adap->algo_data;
struct i2c_msg *pmsg;
- int i, ret;
int rc = 0;
- if (!(bfin_read_TWI_CONTROL() & TWI_ENA))
+ if (!(read_CONTROL(iface) & TWI_ENA))
return -ENXIO;
- while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) {
+ while (read_MASTER_STAT(iface) & BUSBUSY)
yield();
+
+ iface->pmsg = msgs;
+ iface->msg_num = num;
+ iface->cur_msg = 0;
+
+ pmsg = &msgs[0];
+ if (pmsg->flags & I2C_M_TEN) {
+ dev_err(&adap->dev, "10 bits addr not supported!\n");
+ return -EINVAL;
}
- ret = 0;
- for (i = 0; rc >= 0 && i < num; i++) {
- pmsg = &msgs[i];
- if (pmsg->flags & I2C_M_TEN) {
- dev_err(&(adap->dev), "i2c-bfin-twi: 10 bits addr "
- "not supported !\n");
- rc = -EINVAL;
- break;
- }
+ iface->cur_mode = TWI_I2C_MODE_REPEAT;
+ iface->manual_stop = 0;
+ iface->transPtr = pmsg->buf;
+ iface->writeNum = iface->readNum = pmsg->len;
+ iface->result = 0;
+ iface->timeout_count = 10;
+ init_completion(&(iface->complete));
+ /* Set Transmit device address */
+ write_MASTER_ADDR(iface, pmsg->addr);
- iface->cur_mode = TWI_I2C_MODE_STANDARD;
- iface->manual_stop = 0;
- iface->transPtr = pmsg->buf;
- iface->writeNum = iface->readNum = pmsg->len;
- iface->result = 0;
- iface->timeout_count = 10;
- /* Set Transmit device address */
- bfin_write_TWI_MASTER_ADDR(pmsg->addr);
-
- /* FIFO Initiation. Data in FIFO should be
- * discarded before start a new operation.
- */
- bfin_write_TWI_FIFO_CTL(0x3);
- SSYNC();
- bfin_write_TWI_FIFO_CTL(0);
- SSYNC();
+ /* FIFO Initiation. Data in FIFO should be
+ * discarded before start a new operation.
+ */
+ write_FIFO_CTL(iface, 0x3);
+ SSYNC();
+ write_FIFO_CTL(iface, 0);
+ SSYNC();
- if (pmsg->flags & I2C_M_RD)
- iface->read_write = I2C_SMBUS_READ;
- else {
- iface->read_write = I2C_SMBUS_WRITE;
- /* Transmit first data */
- if (iface->writeNum > 0) {
- bfin_write_TWI_XMT_DATA8(*(iface->transPtr++));
- iface->writeNum--;
- SSYNC();
- }
+ if (pmsg->flags & I2C_M_RD)
+ iface->read_write = I2C_SMBUS_READ;
+ else {
+ iface->read_write = I2C_SMBUS_WRITE;
+ /* Transmit first data */
+ if (iface->writeNum > 0) {
+ write_XMT_DATA8(iface, *(iface->transPtr++));
+ iface->writeNum--;
+ SSYNC();
}
+ }
- /* clear int stat */
- bfin_write_TWI_INT_STAT(MERR|MCOMP|XMTSERV|RCVSERV);
+ /* clear int stat */
+ write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
- /* Interrupt mask . Enable XMT, RCV interrupt */
- bfin_write_TWI_INT_MASK(MCOMP | MERR |
- ((iface->read_write == I2C_SMBUS_READ)?
- RCVSERV : XMTSERV));
- SSYNC();
+ /* Interrupt mask . Enable XMT, RCV interrupt */
+ write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
+ SSYNC();
- if (pmsg->len > 0 && pmsg->len <= 255)
- bfin_write_TWI_MASTER_CTL(pmsg->len << 6);
- else if (pmsg->len > 255) {
- bfin_write_TWI_MASTER_CTL(0xff << 6);
- iface->manual_stop = 1;
- } else
- break;
+ if (pmsg->len <= 255)
+ write_MASTER_CTL(iface, pmsg->len << 6);
+ else {
+ write_MASTER_CTL(iface, 0xff << 6);
+ iface->manual_stop = 1;
+ }
- iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
- add_timer(&iface->timeout_timer);
+ iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
+ add_timer(&iface->timeout_timer);
- /* Master enable */
- bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
- ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
- ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
- SSYNC();
+ /* Master enable */
+ write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
+ ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
+ ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
+ SSYNC();
- wait_for_completion(&iface->complete);
+ wait_for_completion(&iface->complete);
- rc = iface->result;
- if (rc == 1)
- ret++;
- else if (rc == -1)
- break;
- }
+ rc = iface->result;
- return ret;
+ if (rc == 1)
+ return num;
+ else
+ return rc;
}
/*
struct bfin_twi_iface *iface = adap->algo_data;
int rc = 0;
- if (!(bfin_read_TWI_CONTROL() & TWI_ENA))
+ if (!(read_CONTROL(iface) & TWI_ENA))
return -ENXIO;
- while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) {
+ while (read_MASTER_STAT(iface) & BUSBUSY)
yield();
- }
iface->writeNum = 0;
iface->readNum = 0;
iface->read_write = read_write;
iface->command = command;
iface->timeout_count = 10;
+ init_completion(&(iface->complete));
/* FIFO Initiation. Data in FIFO should be discarded before
* start a new operation.
*/
- bfin_write_TWI_FIFO_CTL(0x3);
+ write_FIFO_CTL(iface, 0x3);
SSYNC();
- bfin_write_TWI_FIFO_CTL(0);
+ write_FIFO_CTL(iface, 0);
/* clear int stat */
- bfin_write_TWI_INT_STAT(MERR|MCOMP|XMTSERV|RCVSERV);
+ write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
/* Set Transmit device address */
- bfin_write_TWI_MASTER_ADDR(addr);
+ write_MASTER_ADDR(iface, addr);
SSYNC();
iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
switch (iface->cur_mode) {
case TWI_I2C_MODE_STANDARDSUB:
- bfin_write_TWI_XMT_DATA8(iface->command);
- bfin_write_TWI_INT_MASK(MCOMP | MERR |
+ write_XMT_DATA8(iface, iface->command);
+ write_INT_MASK(iface, MCOMP | MERR |
((iface->read_write == I2C_SMBUS_READ) ?
RCVSERV : XMTSERV));
SSYNC();
if (iface->writeNum + 1 <= 255)
- bfin_write_TWI_MASTER_CTL((iface->writeNum + 1) << 6);
+ write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
else {
- bfin_write_TWI_MASTER_CTL(0xff << 6);
+ write_MASTER_CTL(iface, 0xff << 6);
iface->manual_stop = 1;
}
/* Master enable */
- bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
+ write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
break;
case TWI_I2C_MODE_COMBINED:
- bfin_write_TWI_XMT_DATA8(iface->command);
- bfin_write_TWI_INT_MASK(MCOMP | MERR | RCVSERV | XMTSERV);
+ write_XMT_DATA8(iface, iface->command);
+ write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
SSYNC();
if (iface->writeNum > 0)
- bfin_write_TWI_MASTER_CTL((iface->writeNum + 1) << 6);
+ write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
else
- bfin_write_TWI_MASTER_CTL(0x1 << 6);
+ write_MASTER_CTL(iface, 0x1 << 6);
/* Master enable */
- bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
+ write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
break;
default:
- bfin_write_TWI_MASTER_CTL(0);
+ write_MASTER_CTL(iface, 0);
if (size != I2C_SMBUS_QUICK) {
/* Don't access xmit data register when this is a
* read operation.
*/
if (iface->read_write != I2C_SMBUS_READ) {
if (iface->writeNum > 0) {
- bfin_write_TWI_XMT_DATA8(*(iface->transPtr++));
+ write_XMT_DATA8(iface,
+ *(iface->transPtr++));
if (iface->writeNum <= 255)
- bfin_write_TWI_MASTER_CTL(iface->writeNum << 6);
+ write_MASTER_CTL(iface,
+ iface->writeNum << 6);
else {
- bfin_write_TWI_MASTER_CTL(0xff << 6);
+ write_MASTER_CTL(iface,
+ 0xff << 6);
iface->manual_stop = 1;
}
iface->writeNum--;
} else {
- bfin_write_TWI_XMT_DATA8(iface->command);
- bfin_write_TWI_MASTER_CTL(1 << 6);
+ write_XMT_DATA8(iface, iface->command);
+ write_MASTER_CTL(iface, 1 << 6);
}
} else {
if (iface->readNum > 0 && iface->readNum <= 255)
- bfin_write_TWI_MASTER_CTL(iface->readNum << 6);
+ write_MASTER_CTL(iface,
+ iface->readNum << 6);
else if (iface->readNum > 255) {
- bfin_write_TWI_MASTER_CTL(0xff << 6);
+ write_MASTER_CTL(iface, 0xff << 6);
iface->manual_stop = 1;
} else {
del_timer(&iface->timeout_timer);
}
}
}
- bfin_write_TWI_INT_MASK(MCOMP | MERR |
+ write_INT_MASK(iface, MCOMP | MERR |
((iface->read_write == I2C_SMBUS_READ) ?
RCVSERV : XMTSERV));
SSYNC();
/* Master enable */
- bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
+ write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
break;
static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
{
-/* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/
+ struct bfin_twi_iface *iface = platform_get_drvdata(dev);
/* Disable TWI */
- bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA);
+ write_CONTROL(iface, read_CONTROL(iface) & ~TWI_ENA);
SSYNC();
return 0;
static int i2c_bfin_twi_resume(struct platform_device *dev)
{
-/* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/
+ struct bfin_twi_iface *iface = platform_get_drvdata(dev);
/* Enable TWI */
- bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
+ write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
SSYNC();
return 0;
}
-static int i2c_bfin_twi_probe(struct platform_device *dev)
+static int i2c_bfin_twi_probe(struct platform_device *pdev)
{
- struct bfin_twi_iface *iface = &twi_iface;
+ struct bfin_twi_iface *iface;
struct i2c_adapter *p_adap;
+ struct resource *res;
int rc;
+ iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
+ if (!iface) {
+ dev_err(&pdev->dev, "Cannot allocate memory\n");
+ rc = -ENOMEM;
+ goto out_error_nomem;
+ }
+
spin_lock_init(&(iface->lock));
- init_completion(&(iface->complete));
- iface->irq = IRQ_TWI;
+
+ /* Find and map our resources */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
+ rc = -ENOENT;
+ goto out_error_get_res;
+ }
+
+ iface->regs_base = ioremap(res->start, res->end - res->start + 1);
+ if (iface->regs_base == NULL) {
+ dev_err(&pdev->dev, "Cannot map IO\n");
+ rc = -ENXIO;
+ goto out_error_ioremap;
+ }
+
+ iface->irq = platform_get_irq(pdev, 0);
+ if (iface->irq < 0) {
+ dev_err(&pdev->dev, "No IRQ specified\n");
+ rc = -ENOENT;
+ goto out_error_no_irq;
+ }
init_timer(&(iface->timeout_timer));
iface->timeout_timer.function = bfin_twi_timeout;
p_adap = &iface->adap;
p_adap->id = I2C_HW_BLACKFIN;
- p_adap->nr = dev->id;
- strlcpy(p_adap->name, dev->name, sizeof(p_adap->name));
+ p_adap->nr = pdev->id;
+ strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
p_adap->algo = &bfin_twi_algorithm;
p_adap->algo_data = iface;
p_adap->class = I2C_CLASS_ALL;
- p_adap->dev.parent = &dev->dev;
+ p_adap->dev.parent = &pdev->dev;
+
+ rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
+ if (rc) {
+ dev_err(&pdev->dev, "Can't setup pin mux!\n");
+ goto out_error_pin_mux;
+ }
rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
- IRQF_DISABLED, dev->name, iface);
+ IRQF_DISABLED, pdev->name, iface);
if (rc) {
- dev_err(&(p_adap->dev), "i2c-bfin-twi: can't get IRQ %d !\n",
- iface->irq);
- return -ENODEV;
+ dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
+ rc = -ENODEV;
+ goto out_error_req_irq;
}
/* Set TWI internal clock as 10MHz */
- bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
+ write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
/* Set Twi interface clock as specified */
- bfin_write_TWI_CLKDIV((( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ )
- << 8) | (( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ )
+ write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
+ << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
& 0xFF));
/* Enable TWI */
- bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
+ write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
SSYNC();
rc = i2c_add_numbered_adapter(p_adap);
- if (rc < 0)
- free_irq(iface->irq, iface);
- else
- platform_set_drvdata(dev, iface);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "Can't add i2c adapter!\n");
+ goto out_error_add_adapter;
+ }
+
+ platform_set_drvdata(pdev, iface);
+ dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
+ "regs_base@%p\n", iface->regs_base);
+
+ return 0;
+
+out_error_add_adapter:
+ free_irq(iface->irq, iface);
+out_error_req_irq:
+out_error_no_irq:
+ peripheral_free_list(pin_req[pdev->id]);
+out_error_pin_mux:
+ iounmap(iface->regs_base);
+out_error_ioremap:
+out_error_get_res:
+ kfree(iface);
+out_error_nomem:
return rc;
}
i2c_del_adapter(&(iface->adap));
free_irq(iface->irq, iface);
+ peripheral_free_list(pin_req[pdev->id]);
+ iounmap(iface->regs_base);
+ kfree(iface);
return 0;
}
static int __init i2c_bfin_twi_init(void)
{
- pr_info("I2C: Blackfin I2C TWI driver\n");
-
return platform_driver_register(&i2c_bfin_twi_driver);
}
platform_driver_unregister(&i2c_bfin_twi_driver);
}
-MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
-MODULE_DESCRIPTION("I2C-Bus adapter routines for Blackfin TWI");
-MODULE_LICENSE("GPL");
-
module_init(i2c_bfin_twi_init);
module_exit(i2c_bfin_twi_exit);
+
+MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
+MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:i2c-bfin-twi");
int i;
int ret;
- dev_dbg(dev->dev, "%s: msgs: %d\n", __FUNCTION__, num);
+ dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
ret = i2c_davinci_wait_bus_not_busy(dev, 1);
if (ret < 0) {
return ret;
}
- dev_dbg(dev->dev, "%s:%d ret: %d\n", __FUNCTION__, __LINE__, ret);
+ dev_dbg(dev->dev, "%s:%d ret: %d\n", __func__, __LINE__, ret);
return num;
}
u16 w;
while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
- dev_dbg(dev->dev, "%s: stat=0x%x\n", __FUNCTION__, stat);
+ dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
if (count++ == 100) {
dev_warn(dev->dev, "Too much work in one IRQ\n");
break;
return 0;
}
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:i2c_davinci");
+
static struct platform_driver davinci_i2c_driver = {
.probe = davinci_i2c_probe,
.remove = davinci_i2c_remove,
MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
MODULE_DESCRIPTION("Platform-independent bitbanging I2C driver");
MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:i2c-gpio");
* Copyright (c) 2003, 2004 Zultys Technologies.
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
*
+ * Copyright (c) 2008 PIKA Technologies
+ * Sean MacLennan <smaclennan@pikatech.com>
+ *
* Based on original work by
* Ian DaSilva <idasilva@mvista.com>
* Armin Kuster <akuster@mvista.com>
#include <asm/io.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
+
+#ifdef CONFIG_IBM_OCP
#include <asm/ocp.h>
#include <asm/ibm4xx.h>
+#else
+#include <linux/of_platform.h>
+#endif
#include "i2c-ibm_iic.h"
-#define DRIVER_VERSION "2.1"
+#define DRIVER_VERSION "2.2"
MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
MODULE_LICENSE("GPL");
opb /= 1000000;
if (opb < 20 || opb > 150){
- printk(KERN_CRIT "ibm-iic: invalid OPB clock frequency %u MHz\n",
+ printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n",
opb);
opb = opb < 20 ? 20 : 150;
}
return (u8)((opb + 9) / 10 - 1);
}
+#ifdef CONFIG_IBM_OCP
/*
* Register single IIC interface
*/
ocp->def->index);
if (!(dev = kzalloc(sizeof(*dev), GFP_KERNEL))) {
- printk(KERN_CRIT "ibm-iic%d: failed to allocate device data\n",
+ printk(KERN_ERR "ibm-iic%d: failed to allocate device data\n",
ocp->def->index);
return -ENOMEM;
}
}
if (!(dev->vaddr = ioremap(ocp->def->paddr, sizeof(struct iic_regs)))){
- printk(KERN_CRIT "ibm-iic%d: failed to ioremap device registers\n",
+ printk(KERN_ERR "ibm-iic%d: failed to ioremap device registers\n",
dev->idx);
ret = -ENXIO;
goto fail2;
adap->nr = dev->idx >= 0 ? dev->idx : 0;
if ((ret = i2c_add_numbered_adapter(adap)) < 0) {
- printk(KERN_CRIT "ibm-iic%d: failed to register i2c adapter\n",
+ printk(KERN_ERR "ibm-iic%d: failed to register i2c adapter\n",
dev->idx);
goto fail;
}
struct ibm_iic_private* dev = (struct ibm_iic_private*)ocp_get_drvdata(ocp);
BUG_ON(dev == NULL);
if (i2c_del_adapter(&dev->adap)){
- printk(KERN_CRIT "ibm-iic%d: failed to delete i2c adapter :(\n",
+ printk(KERN_ERR "ibm-iic%d: failed to delete i2c adapter :(\n",
dev->idx);
/* That's *very* bad, just shutdown IRQ ... */
if (dev->irq >= 0){
ocp_unregister_driver(&ibm_iic_driver);
}
+#else /* !CONFIG_IBM_OCP */
+
+static int __devinit iic_request_irq(struct of_device *ofdev,
+ struct ibm_iic_private *dev)
+{
+ struct device_node *np = ofdev->node;
+ int irq;
+
+ if (iic_force_poll)
+ return NO_IRQ;
+
+ irq = irq_of_parse_and_map(np, 0);
+ if (irq == NO_IRQ) {
+ dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
+ return NO_IRQ;
+ }
+
+ /* Disable interrupts until we finish initialization, assumes
+ * level-sensitive IRQ setup...
+ */
+ iic_interrupt_mode(dev, 0);
+ if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) {
+ dev_err(&ofdev->dev, "request_irq %d failed\n", irq);
+ /* Fallback to the polling mode */
+ return NO_IRQ;
+ }
+
+ return irq;
+}
+
+/*
+ * Register single IIC interface
+ */
+static int __devinit iic_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
+{
+ struct device_node *np = ofdev->node;
+ struct ibm_iic_private *dev;
+ struct i2c_adapter *adap;
+ const u32 *indexp, *freq;
+ int ret;
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev) {
+ dev_err(&ofdev->dev, "failed to allocate device data\n");
+ return -ENOMEM;
+ }
+
+ dev_set_drvdata(&ofdev->dev, dev);
+
+ indexp = of_get_property(np, "index", NULL);
+ if (!indexp) {
+ dev_err(&ofdev->dev, "no index specified\n");
+ ret = -EINVAL;
+ goto error_cleanup;
+ }
+ dev->idx = *indexp;
+
+ dev->vaddr = of_iomap(np, 0);
+ if (dev->vaddr == NULL) {
+ dev_err(&ofdev->dev, "failed to iomap device\n");
+ ret = -ENXIO;
+ goto error_cleanup;
+ }
+
+ init_waitqueue_head(&dev->wq);
+
+ dev->irq = iic_request_irq(ofdev, dev);
+ if (dev->irq == NO_IRQ)
+ dev_warn(&ofdev->dev, "using polling mode\n");
+
+ /* Board specific settings */
+ if (iic_force_fast || of_get_property(np, "fast-mode", NULL))
+ dev->fast_mode = 1;
+
+ freq = of_get_property(np, "clock-frequency", NULL);
+ if (freq == NULL) {
+ freq = of_get_property(np->parent, "clock-frequency", NULL);
+ if (freq == NULL) {
+ dev_err(&ofdev->dev, "Unable to get bus frequency\n");
+ ret = -EINVAL;
+ goto error_cleanup;
+ }
+ }
+
+ dev->clckdiv = iic_clckdiv(*freq);
+ dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv);
+
+ /* Initialize IIC interface */
+ iic_dev_init(dev);
+
+ /* Register it with i2c layer */
+ adap = &dev->adap;
+ adap->dev.parent = &ofdev->dev;
+ strlcpy(adap->name, "IBM IIC", sizeof(adap->name));
+ i2c_set_adapdata(adap, dev);
+ adap->id = I2C_HW_OCP;
+ adap->class = I2C_CLASS_HWMON;
+ adap->algo = &iic_algo;
+ adap->timeout = 1;
+ adap->nr = dev->idx;
+
+ ret = i2c_add_numbered_adapter(adap);
+ if (ret < 0) {
+ dev_err(&ofdev->dev, "failed to register i2c adapter\n");
+ goto error_cleanup;
+ }
+
+ dev_info(&ofdev->dev, "using %s mode\n",
+ dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
+
+ return 0;
+
+error_cleanup:
+ if (dev->irq != NO_IRQ) {
+ iic_interrupt_mode(dev, 0);
+ free_irq(dev->irq, dev);
+ }
+
+ if (dev->vaddr)
+ iounmap(dev->vaddr);
+
+ dev_set_drvdata(&ofdev->dev, NULL);
+ kfree(dev);
+ return ret;
+}
+
+/*
+ * Cleanup initialized IIC interface
+ */
+static int __devexit iic_remove(struct of_device *ofdev)
+{
+ struct ibm_iic_private *dev = dev_get_drvdata(&ofdev->dev);
+
+ dev_set_drvdata(&ofdev->dev, NULL);
+
+ i2c_del_adapter(&dev->adap);
+
+ if (dev->irq != NO_IRQ) {
+ iic_interrupt_mode(dev, 0);
+ free_irq(dev->irq, dev);
+ }
+
+ iounmap(dev->vaddr);
+ kfree(dev);
+
+ return 0;
+}
+
+static const struct of_device_id ibm_iic_match[] = {
+ { .compatible = "ibm,iic-405ex", },
+ { .compatible = "ibm,iic-405gp", },
+ { .compatible = "ibm,iic-440gp", },
+ { .compatible = "ibm,iic-440gpx", },
+ { .compatible = "ibm,iic-440grx", },
+ {}
+};
+
+static struct of_platform_driver ibm_iic_driver = {
+ .name = "ibm-iic",
+ .match_table = ibm_iic_match,
+ .probe = iic_probe,
+ .remove = __devexit_p(iic_remove),
+};
+
+static int __init iic_init(void)
+{
+ return of_register_platform_driver(&ibm_iic_driver);
+}
+
+static void __exit iic_exit(void)
+{
+ of_unregister_platform_driver(&ibm_iic_driver);
+}
+#endif /* CONFIG_IBM_OCP */
+
module_init(iic_init);
module_exit(iic_exit);
MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:IOP3xx-I2C");
MODULE_AUTHOR ("Deepak Saxena <dsaxena@plexity.net>");
MODULE_DESCRIPTION("IXP2000 GPIO-based I2C bus driver");
MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:IXP2000-I2C");
return 0;
};
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:fsl-i2c");
+
/* Structure for a device driver */
static struct platform_driver fsl_i2c_driver = {
.probe = fsl_i2c_probe,
return 0;
}
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:ocores-i2c");
+
static struct platform_driver ocores_i2c_driver = {
.probe = ocores_i2c_probe,
.remove = __devexit_p(ocores_i2c_remove),
MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:i2c_omap");
/*
* i2c-pca-isa.c driver for PCA9564 on ISA boards
* Copyright (C) 2004 Arcom Control Systems
+ * Copyright (C) 2008 Pengutronix
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/delay.h>
-#include <linux/slab.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
-
#include <linux/isa.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-pca.h>
#include <asm/io.h>
#include <asm/irq.h>
-#include "../algos/i2c-algo-pca.h"
-
+#define DRIVER "i2c-pca-isa"
#define IO_SIZE 4
-#undef DEBUG_IO
-//#define DEBUG_IO
-
static unsigned long base = 0x330;
static int irq = 10;
* in the actual clock rate */
static int clock = I2C_PCA_CON_59kHz;
-static int own = 0x55;
-
static wait_queue_head_t pca_wait;
-static int pca_isa_getown(struct i2c_algo_pca_data *adap)
-{
- return (own);
-}
-
-static int pca_isa_getclock(struct i2c_algo_pca_data *adap)
-{
- return (clock);
-}
-
-static void
-pca_isa_writebyte(struct i2c_algo_pca_data *adap, int reg, int val)
+static void pca_isa_writebyte(void *pd, int reg, int val)
{
#ifdef DEBUG_IO
static char *names[] = { "T/O", "DAT", "ADR", "CON" };
outb(val, base+reg);
}
-static int
-pca_isa_readbyte(struct i2c_algo_pca_data *adap, int reg)
+static int pca_isa_readbyte(void *pd, int reg)
{
int res = inb(base+reg);
#ifdef DEBUG_IO
{
- static char *names[] = { "STA", "DAT", "ADR", "CON" };
+ static char *names[] = { "STA", "DAT", "ADR", "CON" };
printk("*** read %s => %#04x\n", names[reg], res);
}
#endif
return res;
}
-static int pca_isa_waitforinterrupt(struct i2c_algo_pca_data *adap)
+static int pca_isa_waitforcompletion(void *pd)
{
int ret = 0;
if (irq > -1) {
ret = wait_event_interruptible(pca_wait,
- pca_isa_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI);
+ pca_isa_readbyte(pd, I2C_PCA_CON) & I2C_PCA_CON_SI);
} else {
- while ((pca_isa_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0)
+ while ((pca_isa_readbyte(pd, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0)
udelay(100);
}
return ret;
}
+static void pca_isa_resetchip(void *pd)
+{
+ /* apparently only an external reset will do it. not a lot can be done */
+ printk(KERN_WARNING DRIVER ": Haven't figured out how to do a reset yet\n");
+}
+
static irqreturn_t pca_handler(int this_irq, void *dev_id) {
wake_up_interruptible(&pca_wait);
return IRQ_HANDLED;
}
static struct i2c_algo_pca_data pca_isa_data = {
- .get_own = pca_isa_getown,
- .get_clock = pca_isa_getclock,
+ /* .data intentionally left NULL, not needed with ISA */
.write_byte = pca_isa_writebyte,
.read_byte = pca_isa_readbyte,
- .wait_for_interrupt = pca_isa_waitforinterrupt,
+ .wait_for_completion = pca_isa_waitforcompletion,
+ .reset_chip = pca_isa_resetchip,
};
static struct i2c_adapter pca_isa_ops = {
.id = I2C_HW_A_ISA,
.algo_data = &pca_isa_data,
.name = "PCA9564 ISA Adapter",
+ .timeout = 100,
};
static int __devinit pca_isa_probe(struct device *dev, unsigned int id)
}
}
+ pca_isa_data.i2c_clock = clock;
if (i2c_pca_add_bus(&pca_isa_ops) < 0) {
dev_err(dev, "Failed to add i2c bus\n");
goto out_irq;
.remove = __devexit_p(pca_isa_remove),
.driver = {
.owner = THIS_MODULE,
- .name = "i2c-pca-isa",
+ .name = DRIVER,
}
};
module_param(clock, int, 0);
MODULE_PARM_DESC(clock, "Clock rate as described in table 1 of PCA9564 datasheet");
-module_param(own, int, 0); /* the driver can't do slave mode, so there's no real point in this */
-
module_init(pca_isa_init);
module_exit(pca_isa_exit);
--- /dev/null
+/*
+ * i2c_pca_platform.c
+ *
+ * Platform driver for the PCA9564 I2C controller.
+ *
+ * Copyright (C) 2008 Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/i2c-algo-pca.h>
+#include <linux/i2c-pca-platform.h>
+#include <linux/gpio.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#define res_len(r) ((r)->end - (r)->start + 1)
+
+struct i2c_pca_pf_data {
+ void __iomem *reg_base;
+ int irq; /* if 0, use polling */
+ int gpio;
+ wait_queue_head_t wait;
+ struct i2c_adapter adap;
+ struct i2c_algo_pca_data algo_data;
+ unsigned long io_base;
+ unsigned long io_size;
+};
+
+/* Read/Write functions for different register alignments */
+
+static int i2c_pca_pf_readbyte8(void *pd, int reg)
+{
+ struct i2c_pca_pf_data *i2c = pd;
+ return ioread8(i2c->reg_base + reg);
+}
+
+static int i2c_pca_pf_readbyte16(void *pd, int reg)
+{
+ struct i2c_pca_pf_data *i2c = pd;
+ return ioread8(i2c->reg_base + reg * 2);
+}
+
+static int i2c_pca_pf_readbyte32(void *pd, int reg)
+{
+ struct i2c_pca_pf_data *i2c = pd;
+ return ioread8(i2c->reg_base + reg * 4);
+}
+
+static void i2c_pca_pf_writebyte8(void *pd, int reg, int val)
+{
+ struct i2c_pca_pf_data *i2c = pd;
+ iowrite8(val, i2c->reg_base + reg);
+}
+
+static void i2c_pca_pf_writebyte16(void *pd, int reg, int val)
+{
+ struct i2c_pca_pf_data *i2c = pd;
+ iowrite8(val, i2c->reg_base + reg * 2);
+}
+
+static void i2c_pca_pf_writebyte32(void *pd, int reg, int val)
+{
+ struct i2c_pca_pf_data *i2c = pd;
+ iowrite8(val, i2c->reg_base + reg * 4);
+}
+
+
+static int i2c_pca_pf_waitforcompletion(void *pd)
+{
+ struct i2c_pca_pf_data *i2c = pd;
+ int ret = 0;
+
+ if (i2c->irq) {
+ ret = wait_event_interruptible(i2c->wait,
+ i2c->algo_data.read_byte(i2c, I2C_PCA_CON)
+ & I2C_PCA_CON_SI);
+ } else {
+ /*
+ * Do polling...
+ * XXX: Could get stuck in extreme cases!
+ * Maybe add timeout, but using irqs is preferred anyhow.
+ */
+ while ((i2c->algo_data.read_byte(i2c, I2C_PCA_CON)
+ & I2C_PCA_CON_SI) == 0)
+ udelay(100);
+ }
+
+ return ret;
+}
+
+static void i2c_pca_pf_dummyreset(void *pd)
+{
+ struct i2c_pca_pf_data *i2c = pd;
+ printk(KERN_WARNING "%s: No reset-pin found. Chip may get stuck!\n",
+ i2c->adap.name);
+}
+
+static void i2c_pca_pf_resetchip(void *pd)
+{
+ struct i2c_pca_pf_data *i2c = pd;
+
+ gpio_set_value(i2c->gpio, 0);
+ ndelay(100);
+ gpio_set_value(i2c->gpio, 1);
+}
+
+static irqreturn_t i2c_pca_pf_handler(int this_irq, void *dev_id)
+{
+ struct i2c_pca_pf_data *i2c = dev_id;
+
+ if ((i2c->algo_data.read_byte(i2c, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0)
+ return IRQ_NONE;
+
+ wake_up_interruptible(&i2c->wait);
+
+ return IRQ_HANDLED;
+}
+
+
+static int __devinit i2c_pca_pf_probe(struct platform_device *pdev)
+{
+ struct i2c_pca_pf_data *i2c;
+ struct resource *res;
+ struct i2c_pca9564_pf_platform_data *platform_data =
+ pdev->dev.platform_data;
+ int ret = 0;
+ int irq;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ irq = platform_get_irq(pdev, 0);
+ /* If irq is 0, we do polling. */
+
+ if (res == NULL) {
+ ret = -ENODEV;
+ goto e_print;
+ }
+
+ if (!request_mem_region(res->start, res_len(res), res->name)) {
+ ret = -ENOMEM;
+ goto e_print;
+ }
+
+ i2c = kzalloc(sizeof(struct i2c_pca_pf_data), GFP_KERNEL);
+ if (!i2c) {
+ ret = -ENOMEM;
+ goto e_alloc;
+ }
+
+ init_waitqueue_head(&i2c->wait);
+
+ i2c->reg_base = ioremap(res->start, res_len(res));
+ if (!i2c->reg_base) {
+ ret = -EIO;
+ goto e_remap;
+ }
+ i2c->io_base = res->start;
+ i2c->io_size = res_len(res);
+ i2c->irq = irq;
+
+ i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0;
+ i2c->adap.owner = THIS_MODULE;
+ snprintf(i2c->adap.name, sizeof(i2c->adap.name), "PCA9564 at 0x%08lx",
+ (unsigned long) res->start);
+ i2c->adap.algo_data = &i2c->algo_data;
+ i2c->adap.dev.parent = &pdev->dev;
+ i2c->adap.timeout = platform_data->timeout;
+
+ i2c->algo_data.i2c_clock = platform_data->i2c_clock_speed;
+ i2c->algo_data.data = i2c;
+
+ switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
+ case IORESOURCE_MEM_32BIT:
+ i2c->algo_data.write_byte = i2c_pca_pf_writebyte32;
+ i2c->algo_data.read_byte = i2c_pca_pf_readbyte32;
+ break;
+ case IORESOURCE_MEM_16BIT:
+ i2c->algo_data.write_byte = i2c_pca_pf_writebyte16;
+ i2c->algo_data.read_byte = i2c_pca_pf_readbyte16;
+ break;
+ case IORESOURCE_MEM_8BIT:
+ default:
+ i2c->algo_data.write_byte = i2c_pca_pf_writebyte8;
+ i2c->algo_data.read_byte = i2c_pca_pf_readbyte8;
+ break;
+ }
+
+ i2c->algo_data.wait_for_completion = i2c_pca_pf_waitforcompletion;
+
+ i2c->gpio = platform_data->gpio;
+ i2c->algo_data.reset_chip = i2c_pca_pf_dummyreset;
+
+ /* Use gpio_is_valid() when in mainline */
+ if (i2c->gpio > -1) {
+ ret = gpio_request(i2c->gpio, i2c->adap.name);
+ if (ret == 0) {
+ gpio_direction_output(i2c->gpio, 1);
+ i2c->algo_data.reset_chip = i2c_pca_pf_resetchip;
+ } else {
+ printk(KERN_WARNING "%s: Registering gpio failed!\n",
+ i2c->adap.name);
+ i2c->gpio = ret;
+ }
+ }
+
+ if (irq) {
+ ret = request_irq(irq, i2c_pca_pf_handler,
+ IRQF_TRIGGER_FALLING, i2c->adap.name, i2c);
+ if (ret)
+ goto e_reqirq;
+ }
+
+ if (i2c_pca_add_numbered_bus(&i2c->adap) < 0) {
+ ret = -ENODEV;
+ goto e_adapt;
+ }
+
+ platform_set_drvdata(pdev, i2c);
+
+ printk(KERN_INFO "%s registered.\n", i2c->adap.name);
+
+ return 0;
+
+e_adapt:
+ if (irq)
+ free_irq(irq, i2c);
+e_reqirq:
+ if (i2c->gpio > -1)
+ gpio_free(i2c->gpio);
+
+ iounmap(i2c->reg_base);
+e_remap:
+ kfree(i2c);
+e_alloc:
+ release_mem_region(res->start, res_len(res));
+e_print:
+ printk(KERN_ERR "Registering PCA9564 FAILED! (%d)\n", ret);
+ return ret;
+}
+
+static int __devexit i2c_pca_pf_remove(struct platform_device *pdev)
+{
+ struct i2c_pca_pf_data *i2c = platform_get_drvdata(pdev);
+ platform_set_drvdata(pdev, NULL);
+
+ i2c_del_adapter(&i2c->adap);
+
+ if (i2c->irq)
+ free_irq(i2c->irq, i2c);
+
+ if (i2c->gpio > -1)
+ gpio_free(i2c->gpio);
+
+ iounmap(i2c->reg_base);
+ release_mem_region(i2c->io_base, i2c->io_size);
+ kfree(i2c);
+
+ return 0;
+}
+
+static struct platform_driver i2c_pca_pf_driver = {
+ .probe = i2c_pca_pf_probe,
+ .remove = __devexit_p(i2c_pca_pf_remove),
+ .driver = {
+ .name = "i2c-pca-platform",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init i2c_pca_pf_init(void)
+{
+ return platform_driver_register(&i2c_pca_pf_driver);
+}
+
+static void __exit i2c_pca_pf_exit(void)
+{
+ platform_driver_unregister(&i2c_pca_pf_driver);
+}
+
+MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
+MODULE_DESCRIPTION("I2C-PCA9564 platform driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_pca_pf_init);
+module_exit(i2c_pca_pf_exit);
+
(cmd->read_len == 0 || cmd->write_len == 0))) {
dev_err(&pmcmsptwi_adapter.dev,
"%s: Cannot transfer less than 1 byte\n",
- __FUNCTION__);
+ __func__);
return -EINVAL;
}
cmd->write_len > MSP_MAX_BYTES_PER_RW) {
dev_err(&pmcmsptwi_adapter.dev,
"%s: Cannot transfer more than %d bytes\n",
- __FUNCTION__, MSP_MAX_BYTES_PER_RW);
+ __func__, MSP_MAX_BYTES_PER_RW);
return -EINVAL;
}
.name = DRV_NAME,
};
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:" DRV_NAME);
+
static struct platform_driver pmcmsptwi_driver = {
.probe = pmcmsptwi_probe,
.remove = __devexit_p(pmcmsptwi_remove),
{
struct i2c_pnx_algo_data *alg_data = adap->algo_data;
- dev_dbg(&adap->dev, "%s(): addr 0x%x mode %d\n", __FUNCTION__,
+ dev_dbg(&adap->dev, "%s(): addr 0x%x mode %d\n", __func__,
slave_addr, alg_data->mif.mode);
/* Check for 7 bit slave addresses only */
iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
I2C_REG_STS(alg_data));
- dev_dbg(&adap->dev, "%s(): sending %#x\n", __FUNCTION__,
+ dev_dbg(&adap->dev, "%s(): sending %#x\n", __func__,
(slave_addr << 1) | start_bit | alg_data->mif.mode);
/* Write the slave address, START bit and R/W bit */
iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
I2C_REG_TX(alg_data));
- dev_dbg(&adap->dev, "%s(): exit\n", __FUNCTION__);
+ dev_dbg(&adap->dev, "%s(): exit\n", __func__);
return 0;
}
long timeout = 1000;
dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
- __FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
+ __func__, ioread32(I2C_REG_STS(alg_data)));
/* Write a STOP bit to TX FIFO */
iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
}
dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
- __FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
+ __func__, ioread32(I2C_REG_STS(alg_data)));
}
/**
u32 val;
dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
- __FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
+ __func__, ioread32(I2C_REG_STS(alg_data)));
if (alg_data->mif.len > 0) {
/* We still have something to talk about... */
alg_data->mif.len--;
iowrite32(val, I2C_REG_TX(alg_data));
- dev_dbg(&adap->dev, "%s(): xmit %#x [%d]\n", __FUNCTION__,
+ dev_dbg(&adap->dev, "%s(): xmit %#x [%d]\n", __func__,
val, alg_data->mif.len + 1);
if (alg_data->mif.len == 0) {
del_timer_sync(&alg_data->mif.timer);
dev_dbg(&adap->dev, "%s(): Waking up xfer routine.\n",
- __FUNCTION__);
+ __func__);
complete(&alg_data->mif.complete);
}
/* Stop timer. */
del_timer_sync(&alg_data->mif.timer);
dev_dbg(&adap->dev, "%s(): Waking up xfer routine after "
- "zero-xfer.\n", __FUNCTION__);
+ "zero-xfer.\n", __func__);
complete(&alg_data->mif.complete);
}
dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
- __FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
+ __func__, ioread32(I2C_REG_STS(alg_data)));
return 0;
}
u32 ctl = 0;
dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
- __FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
+ __func__, ioread32(I2C_REG_STS(alg_data)));
/* Check, whether there is already data,
* or we didn't 'ask' for it yet.
*/
if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
dev_dbg(&adap->dev, "%s(): Write dummy data to fill "
- "Rx-fifo...\n", __FUNCTION__);
+ "Rx-fifo...\n", __func__);
if (alg_data->mif.len == 1) {
/* Last byte, do not acknowledge next rcv. */
if (alg_data->mif.len > 0) {
val = ioread32(I2C_REG_RX(alg_data));
*alg_data->mif.buf++ = (u8) (val & 0xff);
- dev_dbg(&adap->dev, "%s(): rcv 0x%x [%d]\n", __FUNCTION__, val,
+ dev_dbg(&adap->dev, "%s(): rcv 0x%x [%d]\n", __func__, val,
alg_data->mif.len);
alg_data->mif.len--;
}
dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
- __FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
+ __func__, ioread32(I2C_REG_STS(alg_data)));
return 0;
}
struct i2c_pnx_algo_data *alg_data = adap->algo_data;
dev_dbg(&adap->dev, "%s(): mstat = %x mctrl = %x, mode = %d\n",
- __FUNCTION__,
+ __func__,
ioread32(I2C_REG_STS(alg_data)),
ioread32(I2C_REG_CTL(alg_data)),
alg_data->mif.mode);
/* Slave did not acknowledge, generate a STOP */
dev_dbg(&adap->dev, "%s(): "
"Slave did not acknowledge, generating a STOP.\n",
- __FUNCTION__);
+ __func__);
i2c_pnx_stop(adap);
/* Disable master interrupts. */
iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
dev_dbg(&adap->dev, "%s(): exiting, stat = %x ctrl = %x.\n",
- __FUNCTION__, ioread32(I2C_REG_STS(alg_data)),
+ __func__, ioread32(I2C_REG_STS(alg_data)),
ioread32(I2C_REG_CTL(alg_data)));
return IRQ_HANDLED;
u32 stat = ioread32(I2C_REG_STS(alg_data));
dev_dbg(&adap->dev, "%s(): entering: %d messages, stat = %04x.\n",
- __FUNCTION__, num, ioread32(I2C_REG_STS(alg_data)));
+ __func__, num, ioread32(I2C_REG_STS(alg_data)));
bus_reset_if_active(adap);
alg_data->mif.ret = 0;
alg_data->last = (i == num - 1);
- dev_dbg(&adap->dev, "%s(): mode %d, %d bytes\n", __FUNCTION__,
+ dev_dbg(&adap->dev, "%s(): mode %d, %d bytes\n", __func__,
alg_data->mif.mode,
alg_data->mif.len);
if (!(rc = alg_data->mif.ret))
completed++;
dev_dbg(&adap->dev, "%s(): Complete, return code = %d.\n",
- __FUNCTION__, rc);
+ __func__, rc);
/* Clear TDI and AFI bits in case they are set. */
if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
alg_data->mif.len = 0;
dev_dbg(&adap->dev, "%s(): exiting, stat = %x\n",
- __FUNCTION__, ioread32(I2C_REG_STS(alg_data)));
+ __func__, ioread32(I2C_REG_STS(alg_data)));
if (completed != num)
return ((rc < 0) ? rc : -EREMOTEIO);
if (!i2c_pnx || !i2c_pnx->adapter) {
dev_err(&pdev->dev, "%s: no platform data supplied\n",
- __FUNCTION__);
+ __func__);
ret = -EINVAL;
goto out;
}
MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pnx-i2c");
/* We need to make sure I2C is initialized before USB */
subsys_initcall(i2c_adap_pnx_init);
}
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:i2c-powermac");
+
static struct platform_driver i2c_powermac_driver = {
.probe = i2c_powermac_probe,
.remove = __devexit_p(i2c_powermac_remove),
#include <asm/io.h>
#include <asm/arch/i2c.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
struct pxa_i2c {
spinlock_t lock;
readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
}
-#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
+#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
#else
#define i2c_debug 0
}
MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pxa2xx-i2c");
module_init(i2c_adap_pxa_init);
module_exit(i2c_adap_pxa_exit);
switch (i2c->state) {
case STATE_IDLE:
- dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __FUNCTION__);
+ dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
goto out;
break;
case STATE_STOP:
- dev_err(i2c->dev, "%s: called in STATE_STOP\n", __FUNCTION__);
+ dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
s3c24xx_i2c_disable_irq(i2c);
goto out_ack;
MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:s3c2410-i2c");
--- /dev/null
+/*
+ * I2C bus driver for the SH7760 I2C Interfaces.
+ *
+ * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
+ *
+ * licensed under the terms outlined in the file COPYING.
+ *
+ */
+
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <asm/clock.h>
+#include <asm/i2c-sh7760.h>
+#include <asm/io.h>
+
+/* register offsets */
+#define I2CSCR 0x0 /* slave ctrl */
+#define I2CMCR 0x4 /* master ctrl */
+#define I2CSSR 0x8 /* slave status */
+#define I2CMSR 0xC /* master status */
+#define I2CSIER 0x10 /* slave irq enable */
+#define I2CMIER 0x14 /* master irq enable */
+#define I2CCCR 0x18 /* clock dividers */
+#define I2CSAR 0x1c /* slave address */
+#define I2CMAR 0x20 /* master address */
+#define I2CRXTX 0x24 /* data port */
+#define I2CFCR 0x28 /* fifo control */
+#define I2CFSR 0x2C /* fifo status */
+#define I2CFIER 0x30 /* fifo irq enable */
+#define I2CRFDR 0x34 /* rx fifo count */
+#define I2CTFDR 0x38 /* tx fifo count */
+
+#define REGSIZE 0x3C
+
+#define MCR_MDBS 0x80 /* non-fifo mode switch */
+#define MCR_FSCL 0x40 /* override SCL pin */
+#define MCR_FSDA 0x20 /* override SDA pin */
+#define MCR_OBPC 0x10 /* override pins */
+#define MCR_MIE 0x08 /* master if enable */
+#define MCR_TSBE 0x04
+#define MCR_FSB 0x02 /* force stop bit */
+#define MCR_ESG 0x01 /* en startbit gen. */
+
+#define MSR_MNR 0x40 /* nack received */
+#define MSR_MAL 0x20 /* arbitration lost */
+#define MSR_MST 0x10 /* sent a stop */
+#define MSR_MDE 0x08
+#define MSR_MDT 0x04
+#define MSR_MDR 0x02
+#define MSR_MAT 0x01 /* slave addr xfer done */
+
+#define MIE_MNRE 0x40 /* nack irq en */
+#define MIE_MALE 0x20 /* arblos irq en */
+#define MIE_MSTE 0x10 /* stop irq en */
+#define MIE_MDEE 0x08
+#define MIE_MDTE 0x04
+#define MIE_MDRE 0x02
+#define MIE_MATE 0x01 /* address sent irq en */
+
+#define FCR_RFRST 0x02 /* reset rx fifo */
+#define FCR_TFRST 0x01 /* reset tx fifo */
+
+#define FSR_TEND 0x04 /* last byte sent */
+#define FSR_RDF 0x02 /* rx fifo trigger */
+#define FSR_TDFE 0x01 /* tx fifo empty */
+
+#define FIER_TEIE 0x04 /* tx fifo empty irq en */
+#define FIER_RXIE 0x02 /* rx fifo trig irq en */
+#define FIER_TXIE 0x01 /* tx fifo trig irq en */
+
+#define FIFO_SIZE 16
+
+struct cami2c {
+ void __iomem *iobase;
+ struct i2c_adapter adap;
+
+ /* message processing */
+ struct i2c_msg *msg;
+#define IDF_SEND 1
+#define IDF_RECV 2
+#define IDF_STOP 4
+ int flags;
+
+#define IDS_DONE 1
+#define IDS_ARBLOST 2
+#define IDS_NACK 4
+ int status;
+ struct completion xfer_done;
+
+ int irq;
+ struct resource *ioarea;
+};
+
+static inline void OUT32(struct cami2c *cam, int reg, unsigned long val)
+{
+ ctrl_outl(val, (unsigned long)cam->iobase + reg);
+}
+
+static inline unsigned long IN32(struct cami2c *cam, int reg)
+{
+ return ctrl_inl((unsigned long)cam->iobase + reg);
+}
+
+static irqreturn_t sh7760_i2c_irq(int irq, void *ptr)
+{
+ struct cami2c *id = ptr;
+ struct i2c_msg *msg = id->msg;
+ char *data = msg->buf;
+ unsigned long msr, fsr, fier, len;
+
+ msr = IN32(id, I2CMSR);
+ fsr = IN32(id, I2CFSR);
+
+ /* arbitration lost */
+ if (msr & MSR_MAL) {
+ OUT32(id, I2CMCR, 0);
+ OUT32(id, I2CSCR, 0);
+ OUT32(id, I2CSAR, 0);
+ id->status |= IDS_DONE | IDS_ARBLOST;
+ goto out;
+ }
+
+ if (msr & MSR_MNR) {
+ /* NACK handling is very screwed up. After receiving a
+ * NAK IRQ one has to wait a bit before writing to any
+ * registers, or the ctl will lock up. After that delay
+ * do a normal i2c stop. Then wait at least 1 ms before
+ * attempting another transfer or ctl will stop working
+ */
+ udelay(100); /* wait or risk ctl hang */
+ OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
+ OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
+ OUT32(id, I2CFIER, 0);
+ OUT32(id, I2CMIER, MIE_MSTE);
+ OUT32(id, I2CSCR, 0);
+ OUT32(id, I2CSAR, 0);
+ id->status |= IDS_NACK;
+ msr &= ~MSR_MAT;
+ fsr = 0;
+ /* In some cases the MST bit is also set. */
+ }
+
+ /* i2c-stop was sent */
+ if (msr & MSR_MST) {
+ id->status |= IDS_DONE;
+ goto out;
+ }
+
+ /* i2c slave addr was sent; set to "normal" operation */
+ if (msr & MSR_MAT)
+ OUT32(id, I2CMCR, MCR_MIE);
+
+ fier = IN32(id, I2CFIER);
+
+ if (fsr & FSR_RDF) {
+ len = IN32(id, I2CRFDR);
+ if (msg->len <= len) {
+ if (id->flags & IDF_STOP) {
+ OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
+ OUT32(id, I2CFIER, 0);
+ /* manual says: wait >= 0.5 SCL times */
+ udelay(5);
+ /* next int should be MST */
+ } else {
+ id->status |= IDS_DONE;
+ /* keep the RDF bit: ctrl holds SCL low
+ * until the setup for the next i2c_msg
+ * clears this bit.
+ */
+ fsr &= ~FSR_RDF;
+ }
+ }
+ while (msg->len && len) {
+ *data++ = IN32(id, I2CRXTX);
+ msg->len--;
+ len--;
+ }
+
+ if (msg->len) {
+ len = (msg->len >= FIFO_SIZE) ? FIFO_SIZE - 1
+ : msg->len - 1;
+
+ OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xf) << 4));
+ }
+
+ } else if (id->flags & IDF_SEND) {
+ if ((fsr & FSR_TEND) && (msg->len < 1)) {
+ if (id->flags & IDF_STOP) {
+ OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
+ } else {
+ id->status |= IDS_DONE;
+ /* keep the TEND bit: ctl holds SCL low
+ * until the setup for the next i2c_msg
+ * clears this bit.
+ */
+ fsr &= ~FSR_TEND;
+ }
+ }
+ if (fsr & FSR_TDFE) {
+ while (msg->len && (IN32(id, I2CTFDR) < FIFO_SIZE)) {
+ OUT32(id, I2CRXTX, *data++);
+ msg->len--;
+ }
+
+ if (msg->len < 1) {
+ fier &= ~FIER_TXIE;
+ OUT32(id, I2CFIER, fier);
+ } else {
+ len = (msg->len >= FIFO_SIZE) ? 2 : 0;
+ OUT32(id, I2CFCR,
+ FCR_RFRST | ((len & 3) << 2));
+ }
+ }
+ }
+out:
+ if (id->status & IDS_DONE) {
+ OUT32(id, I2CMIER, 0);
+ OUT32(id, I2CFIER, 0);
+ id->msg = NULL;
+ complete(&id->xfer_done);
+ }
+ /* clear status flags and ctrl resumes work */
+ OUT32(id, I2CMSR, ~msr);
+ OUT32(id, I2CFSR, ~fsr);
+ OUT32(id, I2CSSR, 0);
+
+ return IRQ_HANDLED;
+}
+
+
+/* prepare and start a master receive operation */
+static void sh7760_i2c_mrecv(struct cami2c *id)
+{
+ int len;
+
+ id->flags |= IDF_RECV;
+
+ /* set the slave addr reg; otherwise rcv wont work! */
+ OUT32(id, I2CSAR, 0xfe);
+ OUT32(id, I2CMAR, (id->msg->addr << 1) | 1);
+
+ /* adjust rx fifo trigger */
+ if (id->msg->len >= FIFO_SIZE)
+ len = FIFO_SIZE - 1; /* trigger at fifo full */
+ else
+ len = id->msg->len - 1; /* trigger before all received */
+
+ OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
+ OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xF) << 4));
+
+ OUT32(id, I2CMSR, 0);
+ OUT32(id, I2CMCR, MCR_MIE | MCR_ESG);
+ OUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE);
+ OUT32(id, I2CFIER, FIER_RXIE);
+}
+
+/* prepare and start a master send operation */
+static void sh7760_i2c_msend(struct cami2c *id)
+{
+ int len;
+
+ id->flags |= IDF_SEND;
+
+ /* set the slave addr reg; otherwise xmit wont work! */
+ OUT32(id, I2CSAR, 0xfe);
+ OUT32(id, I2CMAR, (id->msg->addr << 1) | 0);
+
+ /* adjust tx fifo trigger */
+ if (id->msg->len >= FIFO_SIZE)
+ len = 2; /* trig: 2 bytes left in TX fifo */
+ else
+ len = 0; /* trig: 8 bytes left in TX fifo */
+
+ OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
+ OUT32(id, I2CFCR, FCR_RFRST | ((len & 3) << 2));
+
+ while (id->msg->len && IN32(id, I2CTFDR) < FIFO_SIZE) {
+ OUT32(id, I2CRXTX, *(id->msg->buf));
+ (id->msg->len)--;
+ (id->msg->buf)++;
+ }
+
+ OUT32(id, I2CMSR, 0);
+ OUT32(id, I2CMCR, MCR_MIE | MCR_ESG);
+ OUT32(id, I2CFSR, 0);
+ OUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE);
+ OUT32(id, I2CFIER, FIER_TEIE | (id->msg->len ? FIER_TXIE : 0));
+}
+
+static inline int sh7760_i2c_busy_check(struct cami2c *id)
+{
+ return (IN32(id, I2CMCR) & MCR_FSDA);
+}
+
+static int sh7760_i2c_master_xfer(struct i2c_adapter *adap,
+ struct i2c_msg *msgs,
+ int num)
+{
+ struct cami2c *id = adap->algo_data;
+ int i, retr;
+
+ if (sh7760_i2c_busy_check(id)) {
+ dev_err(&adap->dev, "sh7760-i2c%d: bus busy!\n", adap->nr);
+ return -EBUSY;
+ }
+
+ i = 0;
+ while (i < num) {
+ retr = adap->retries;
+retry:
+ id->flags = ((i == (num-1)) ? IDF_STOP : 0);
+ id->status = 0;
+ id->msg = msgs;
+ init_completion(&id->xfer_done);
+
+ if (msgs->flags & I2C_M_RD)
+ sh7760_i2c_mrecv(id);
+ else
+ sh7760_i2c_msend(id);
+
+ wait_for_completion(&id->xfer_done);
+
+ if (id->status == 0) {
+ num = -EIO;
+ break;
+ }
+
+ if (id->status & IDS_NACK) {
+ /* wait a bit or i2c module stops working */
+ mdelay(1);
+ num = -EREMOTEIO;
+ break;
+ }
+
+ if (id->status & IDS_ARBLOST) {
+ if (retr--) {
+ mdelay(2);
+ goto retry;
+ }
+ num = -EREMOTEIO;
+ break;
+ }
+
+ msgs++;
+ i++;
+ }
+
+ id->msg = NULL;
+ id->flags = 0;
+ id->status = 0;
+
+ OUT32(id, I2CMCR, 0);
+ OUT32(id, I2CMSR, 0);
+ OUT32(id, I2CMIER, 0);
+ OUT32(id, I2CFIER, 0);
+
+ /* reset slave module registers too: master mode enables slave
+ * module for receive ops (ack, data). Without this reset,
+ * eternal bus activity might be reported after NACK / ARBLOST.
+ */
+ OUT32(id, I2CSCR, 0);
+ OUT32(id, I2CSAR, 0);
+ OUT32(id, I2CSSR, 0);
+
+ return num;
+}
+
+static u32 sh7760_i2c_func(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
+}
+
+static const struct i2c_algorithm sh7760_i2c_algo = {
+ .master_xfer = sh7760_i2c_master_xfer,
+ .functionality = sh7760_i2c_func,
+};
+
+/* calculate CCR register setting for a desired scl clock. SCL clock is
+ * derived from I2C module clock (iclk) which in turn is derived from
+ * peripheral module clock (mclk, usually around 33MHz):
+ * iclk = mclk/(CDF + 1). iclk must be < 20MHz.
+ * scl = iclk/(SCGD*8 + 20).
+ */
+static int __devinit calc_CCR(unsigned long scl_hz)
+{
+ struct clk *mclk;
+ unsigned long mck, m1, dff, odff, iclk;
+ signed char cdf, cdfm;
+ int scgd, scgdm, scgds;
+
+ mclk = clk_get(NULL, "module_clk");
+ if (IS_ERR(mclk)) {
+ return PTR_ERR(mclk);
+ } else {
+ mck = mclk->rate;
+ clk_put(mclk);
+ }
+
+ odff = scl_hz;
+ scgdm = cdfm = m1 = 0;
+ for (cdf = 3; cdf >= 0; cdf--) {
+ iclk = mck / (1 + cdf);
+ if (iclk >= 20000000)
+ continue;
+ scgds = ((iclk / scl_hz) - 20) >> 3;
+ for (scgd = scgds; (scgd < 63) && scgd <= scgds + 1; scgd++) {
+ m1 = iclk / (20 + (scgd << 3));
+ dff = abs(scl_hz - m1);
+ if (dff < odff) {
+ odff = dff;
+ cdfm = cdf;
+ scgdm = scgd;
+ }
+ }
+ }
+ /* fail if more than 25% off of requested SCL */
+ if (odff > (scl_hz >> 2))
+ return -EINVAL;
+
+ /* create a CCR register value */
+ return ((scgdm << 2) | cdfm);
+}
+
+static int __devinit sh7760_i2c_probe(struct platform_device *pdev)
+{
+ struct sh7760_i2c_platdata *pd;
+ struct resource *res;
+ struct cami2c *id;
+ int ret;
+
+ pd = pdev->dev.platform_data;
+ if (!pd) {
+ dev_err(&pdev->dev, "no platform_data!\n");
+ ret = -ENODEV;
+ goto out0;
+ }
+
+ id = kzalloc(sizeof(struct cami2c), GFP_KERNEL);
+ if (!id) {
+ dev_err(&pdev->dev, "no mem for private data\n");
+ ret = -ENOMEM;
+ goto out0;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "no mmio resources\n");
+ ret = -ENODEV;
+ goto out1;
+ }
+
+ id->ioarea = request_mem_region(res->start, REGSIZE, pdev->name);
+ if (!id->ioarea) {
+ dev_err(&pdev->dev, "mmio already reserved\n");
+ ret = -EBUSY;
+ goto out1;
+ }
+
+ id->iobase = ioremap(res->start, REGSIZE);
+ if (!id->iobase) {
+ dev_err(&pdev->dev, "cannot ioremap\n");
+ ret = -ENODEV;
+ goto out2;
+ }
+
+ id->irq = platform_get_irq(pdev, 0);
+
+ id->adap.nr = pdev->id;
+ id->adap.algo = &sh7760_i2c_algo;
+ id->adap.class = I2C_CLASS_ALL;
+ id->adap.retries = 3;
+ id->adap.algo_data = id;
+ id->adap.dev.parent = &pdev->dev;
+ snprintf(id->adap.name, sizeof(id->adap.name),
+ "SH7760 I2C at %08lx", (unsigned long)res->start);
+
+ OUT32(id, I2CMCR, 0);
+ OUT32(id, I2CMSR, 0);
+ OUT32(id, I2CMIER, 0);
+ OUT32(id, I2CMAR, 0);
+ OUT32(id, I2CSIER, 0);
+ OUT32(id, I2CSAR, 0);
+ OUT32(id, I2CSCR, 0);
+ OUT32(id, I2CSSR, 0);
+ OUT32(id, I2CFIER, 0);
+ OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
+ OUT32(id, I2CFSR, 0);
+
+ ret = calc_CCR(pd->speed_khz * 1000);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "invalid SCL clock: %dkHz\n",
+ pd->speed_khz);
+ goto out3;
+ }
+ OUT32(id, I2CCCR, ret);
+
+ if (request_irq(id->irq, sh7760_i2c_irq, IRQF_DISABLED,
+ SH7760_I2C_DEVNAME, id)) {
+ dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
+ ret = -EBUSY;
+ goto out3;
+ }
+
+ ret = i2c_add_numbered_adapter(&id->adap);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "reg adap failed: %d\n", ret);
+ goto out4;
+ }
+
+ platform_set_drvdata(pdev, id);
+
+ dev_info(&pdev->dev, "%d kHz mmio %08x irq %d\n",
+ pd->speed_khz, res->start, id->irq);
+
+ return 0;
+
+out4:
+ free_irq(id->irq, id);
+out3:
+ iounmap(id->iobase);
+out2:
+ release_resource(id->ioarea);
+ kfree(id->ioarea);
+out1:
+ kfree(id);
+out0:
+ return ret;
+}
+
+static int __devexit sh7760_i2c_remove(struct platform_device *pdev)
+{
+ struct cami2c *id = platform_get_drvdata(pdev);
+
+ i2c_del_adapter(&id->adap);
+ free_irq(id->irq, id);
+ iounmap(id->iobase);
+ release_resource(id->ioarea);
+ kfree(id->ioarea);
+ kfree(id);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver sh7760_i2c_drv = {
+ .driver = {
+ .name = SH7760_I2C_DEVNAME,
+ .owner = THIS_MODULE,
+ },
+ .probe = sh7760_i2c_probe,
+ .remove = __devexit_p(sh7760_i2c_remove),
+};
+
+static int __init sh7760_i2c_init(void)
+{
+ return platform_driver_register(&sh7760_i2c_drv);
+}
+
+static void __exit sh7760_i2c_exit(void)
+{
+ platform_driver_unregister(&sh7760_i2c_drv);
+}
+
+module_init(sh7760_i2c_init);
+module_exit(sh7760_i2c_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("SH7760 I2C bus driver");
+MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");
--- /dev/null
+/*
+ * SuperH Mobile I2C Controller
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * Portions of the code based on out-of-tree driver i2c-sh7343.c
+ * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+enum sh_mobile_i2c_op {
+ OP_START = 0,
+ OP_TX_ONLY,
+ OP_TX_STOP,
+ OP_TX_TO_RX,
+ OP_RX_ONLY,
+ OP_RX_STOP,
+};
+
+struct sh_mobile_i2c_data {
+ struct device *dev;
+ void __iomem *reg;
+ struct i2c_adapter adap;
+
+ struct clk *clk;
+ u_int8_t iccl;
+ u_int8_t icch;
+
+ spinlock_t lock;
+ wait_queue_head_t wait;
+ struct i2c_msg *msg;
+ int pos;
+ int sr;
+};
+
+#define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */
+
+/* Register offsets */
+#define ICDR(pd) (pd->reg + 0x00)
+#define ICCR(pd) (pd->reg + 0x04)
+#define ICSR(pd) (pd->reg + 0x08)
+#define ICIC(pd) (pd->reg + 0x0c)
+#define ICCL(pd) (pd->reg + 0x10)
+#define ICCH(pd) (pd->reg + 0x14)
+
+/* Register bits */
+#define ICCR_ICE 0x80
+#define ICCR_RACK 0x40
+#define ICCR_TRS 0x10
+#define ICCR_BBSY 0x04
+#define ICCR_SCP 0x01
+
+#define ICSR_SCLM 0x80
+#define ICSR_SDAM 0x40
+#define SW_DONE 0x20
+#define ICSR_BUSY 0x10
+#define ICSR_AL 0x08
+#define ICSR_TACK 0x04
+#define ICSR_WAIT 0x02
+#define ICSR_DTE 0x01
+
+#define ICIC_ALE 0x08
+#define ICIC_TACKE 0x04
+#define ICIC_WAITE 0x02
+#define ICIC_DTEE 0x01
+
+static void activate_ch(struct sh_mobile_i2c_data *pd)
+{
+ /* Make sure the clock is enabled */
+ clk_enable(pd->clk);
+
+ /* Enable channel and configure rx ack */
+ iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
+
+ /* Mask all interrupts */
+ iowrite8(0, ICIC(pd));
+
+ /* Set the clock */
+ iowrite8(pd->iccl, ICCL(pd));
+ iowrite8(pd->icch, ICCH(pd));
+}
+
+static void deactivate_ch(struct sh_mobile_i2c_data *pd)
+{
+ /* Clear/disable interrupts */
+ iowrite8(0, ICSR(pd));
+ iowrite8(0, ICIC(pd));
+
+ /* Disable channel */
+ iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
+
+ /* Disable clock */
+ clk_disable(pd->clk);
+}
+
+static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
+ enum sh_mobile_i2c_op op, unsigned char data)
+{
+ unsigned char ret = 0;
+ unsigned long flags;
+
+ dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
+
+ spin_lock_irqsave(&pd->lock, flags);
+
+ switch (op) {
+ case OP_START:
+ iowrite8(0x94, ICCR(pd));
+ break;
+ case OP_TX_ONLY:
+ iowrite8(data, ICDR(pd));
+ break;
+ case OP_TX_STOP:
+ iowrite8(data, ICDR(pd));
+ iowrite8(0x90, ICCR(pd));
+ iowrite8(ICIC_ALE | ICIC_TACKE, ICIC(pd));
+ break;
+ case OP_TX_TO_RX:
+ iowrite8(data, ICDR(pd));
+ iowrite8(0x81, ICCR(pd));
+ break;
+ case OP_RX_ONLY:
+ ret = ioread8(ICDR(pd));
+ break;
+ case OP_RX_STOP:
+ ret = ioread8(ICDR(pd));
+ iowrite8(0xc0, ICCR(pd));
+ break;
+ }
+
+ spin_unlock_irqrestore(&pd->lock, flags);
+
+ dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
+ return ret;
+}
+
+static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
+{
+ struct platform_device *dev = dev_id;
+ struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
+ struct i2c_msg *msg = pd->msg;
+ unsigned char data, sr;
+ int wakeup = 0;
+
+ sr = ioread8(ICSR(pd));
+ pd->sr |= sr;
+
+ dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
+ (msg->flags & I2C_M_RD) ? "read" : "write",
+ pd->pos, msg->len);
+
+ if (sr & (ICSR_AL | ICSR_TACK)) {
+ iowrite8(0, ICIC(pd)); /* disable interrupts */
+ wakeup = 1;
+ goto do_wakeup;
+ }
+
+ if (pd->pos == msg->len) {
+ i2c_op(pd, OP_RX_ONLY, 0);
+ wakeup = 1;
+ goto do_wakeup;
+ }
+
+ if (pd->pos == -1) {
+ data = (msg->addr & 0x7f) << 1;
+ data |= (msg->flags & I2C_M_RD) ? 1 : 0;
+ } else
+ data = msg->buf[pd->pos];
+
+ if ((pd->pos == -1) || !(msg->flags & I2C_M_RD)) {
+ if (msg->flags & I2C_M_RD)
+ i2c_op(pd, OP_TX_TO_RX, data);
+ else if (pd->pos == (msg->len - 1)) {
+ i2c_op(pd, OP_TX_STOP, data);
+ wakeup = 1;
+ } else
+ i2c_op(pd, OP_TX_ONLY, data);
+ } else {
+ if (pd->pos == (msg->len - 1))
+ data = i2c_op(pd, OP_RX_STOP, 0);
+ else
+ data = i2c_op(pd, OP_RX_ONLY, 0);
+
+ msg->buf[pd->pos] = data;
+ }
+ pd->pos++;
+
+ do_wakeup:
+ if (wakeup) {
+ pd->sr |= SW_DONE;
+ wake_up(&pd->wait);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
+{
+ /* Initialize channel registers */
+ iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
+
+ /* Enable channel and configure rx ack */
+ iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
+
+ /* Set the clock */
+ iowrite8(pd->iccl, ICCL(pd));
+ iowrite8(pd->icch, ICCH(pd));
+
+ pd->msg = usr_msg;
+ pd->pos = -1;
+ pd->sr = 0;
+
+ /* Enable all interrupts except wait */
+ iowrite8(ioread8(ICIC(pd)) | ICIC_ALE | ICIC_TACKE | ICIC_DTEE,
+ ICIC(pd));
+ return 0;
+}
+
+static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
+ struct i2c_msg *msgs,
+ int num)
+{
+ struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
+ struct i2c_msg *msg;
+ int err = 0;
+ u_int8_t val;
+ int i, k, retry_count;
+
+ activate_ch(pd);
+
+ /* Process all messages */
+ for (i = 0; i < num; i++) {
+ msg = &msgs[i];
+
+ err = start_ch(pd, msg);
+ if (err)
+ break;
+
+ i2c_op(pd, OP_START, 0);
+
+ /* The interrupt handler takes care of the rest... */
+ k = wait_event_timeout(pd->wait,
+ pd->sr & (ICSR_TACK | SW_DONE),
+ 5 * HZ);
+ if (!k)
+ dev_err(pd->dev, "Transfer request timed out\n");
+
+ retry_count = 10;
+again:
+ val = ioread8(ICSR(pd));
+
+ dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
+
+ if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
+ err = -EIO;
+ break;
+ }
+
+ /* the interrupt handler may wake us up before the
+ * transfer is finished, so poll the hardware
+ * until we're done.
+ */
+
+ if (!(!(val & ICSR_BUSY) && (val & ICSR_SCLM) &&
+ (val & ICSR_SDAM))) {
+ msleep(1);
+ if (retry_count--)
+ goto again;
+
+ err = -EIO;
+ dev_err(pd->dev, "Polling timed out\n");
+ break;
+ }
+ }
+
+ deactivate_ch(pd);
+
+ if (!err)
+ err = num;
+ return err;
+}
+
+static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static struct i2c_algorithm sh_mobile_i2c_algorithm = {
+ .functionality = sh_mobile_i2c_func,
+ .master_xfer = sh_mobile_i2c_xfer,
+};
+
+static void sh_mobile_i2c_setup_channel(struct platform_device *dev)
+{
+ struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
+ unsigned long peripheral_clk = clk_get_rate(pd->clk);
+ u_int32_t num;
+ u_int32_t denom;
+ u_int32_t tmp;
+
+ spin_lock_init(&pd->lock);
+ init_waitqueue_head(&pd->wait);
+
+ /* Calculate the value for iccl. From the data sheet:
+ * iccl = (p clock / transfer rate) * (L / (L + H))
+ * where L and H are the SCL low/high ratio (5/4 in this case).
+ * We also round off the result.
+ */
+ num = peripheral_clk * 5;
+ denom = NORMAL_SPEED * 9;
+ tmp = num * 10 / denom;
+ if (tmp % 10 >= 5)
+ pd->iccl = (u_int8_t)((num/denom) + 1);
+ else
+ pd->iccl = (u_int8_t)(num/denom);
+
+ /* Calculate the value for icch. From the data sheet:
+ icch = (p clock / transfer rate) * (H / (L + H)) */
+ num = peripheral_clk * 4;
+ tmp = num * 10 / denom;
+ if (tmp % 10 >= 5)
+ pd->icch = (u_int8_t)((num/denom) + 1);
+ else
+ pd->icch = (u_int8_t)(num/denom);
+}
+
+static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
+{
+ struct resource *res;
+ int ret = -ENXIO;
+ int q, m;
+ int k = 0;
+ int n = 0;
+
+ while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
+ for (n = res->start; hook && n <= res->end; n++) {
+ if (request_irq(n, sh_mobile_i2c_isr, IRQF_DISABLED,
+ dev->dev.bus_id, dev))
+ goto rollback;
+ }
+ k++;
+ }
+
+ if (hook)
+ return k > 0 ? 0 : -ENOENT;
+
+ k--;
+ ret = 0;
+
+ rollback:
+ for (q = k; k >= 0; k--) {
+ for (m = n; m >= res->start; m--)
+ free_irq(m, dev);
+
+ res = platform_get_resource(dev, IORESOURCE_IRQ, k - 1);
+ m = res->end;
+ }
+
+ return ret;
+}
+
+static int sh_mobile_i2c_probe(struct platform_device *dev)
+{
+ struct sh_mobile_i2c_data *pd;
+ struct i2c_adapter *adap;
+ struct resource *res;
+ int size;
+ int ret;
+
+ pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
+ if (pd == NULL) {
+ dev_err(&dev->dev, "cannot allocate private data\n");
+ return -ENOMEM;
+ }
+
+ pd->clk = clk_get(&dev->dev, "peripheral_clk");
+ if (IS_ERR(pd->clk)) {
+ dev_err(&dev->dev, "cannot get peripheral clock\n");
+ ret = PTR_ERR(pd->clk);
+ goto err;
+ }
+
+ ret = sh_mobile_i2c_hook_irqs(dev, 1);
+ if (ret) {
+ dev_err(&dev->dev, "cannot request IRQ\n");
+ goto err_clk;
+ }
+
+ pd->dev = &dev->dev;
+ platform_set_drvdata(dev, pd);
+
+ res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ dev_err(&dev->dev, "cannot find IO resource\n");
+ ret = -ENOENT;
+ goto err_irq;
+ }
+
+ size = (res->end - res->start) + 1;
+
+ pd->reg = ioremap(res->start, size);
+ if (pd->reg == NULL) {
+ dev_err(&dev->dev, "cannot map IO\n");
+ ret = -ENXIO;
+ goto err_irq;
+ }
+
+ /* setup the private data */
+ adap = &pd->adap;
+ i2c_set_adapdata(adap, pd);
+
+ adap->owner = THIS_MODULE;
+ adap->algo = &sh_mobile_i2c_algorithm;
+ adap->dev.parent = &dev->dev;
+ adap->retries = 5;
+ adap->nr = dev->id;
+
+ strlcpy(adap->name, dev->name, sizeof(adap->name));
+
+ sh_mobile_i2c_setup_channel(dev);
+
+ ret = i2c_add_numbered_adapter(adap);
+ if (ret < 0) {
+ dev_err(&dev->dev, "cannot add numbered adapter\n");
+ goto err_all;
+ }
+
+ return 0;
+
+ err_all:
+ iounmap(pd->reg);
+ err_irq:
+ sh_mobile_i2c_hook_irqs(dev, 0);
+ err_clk:
+ clk_put(pd->clk);
+ err:
+ kfree(pd);
+ return ret;
+}
+
+static int sh_mobile_i2c_remove(struct platform_device *dev)
+{
+ struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
+
+ i2c_del_adapter(&pd->adap);
+ iounmap(pd->reg);
+ sh_mobile_i2c_hook_irqs(dev, 0);
+ clk_put(pd->clk);
+ kfree(pd);
+ return 0;
+}
+
+static struct platform_driver sh_mobile_i2c_driver = {
+ .driver = {
+ .name = "i2c-sh_mobile",
+ .owner = THIS_MODULE,
+ },
+ .probe = sh_mobile_i2c_probe,
+ .remove = sh_mobile_i2c_remove,
+};
+
+static int __init sh_mobile_i2c_adap_init(void)
+{
+ return platform_driver_register(&sh_mobile_i2c_driver);
+}
+
+static void __exit sh_mobile_i2c_adap_exit(void)
+{
+ platform_driver_unregister(&sh_mobile_i2c_driver);
+}
+
+module_init(sh_mobile_i2c_adap_init);
+module_exit(sh_mobile_i2c_adap_exit);
+
+MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
+MODULE_AUTHOR("Magnus Damm");
+MODULE_LICENSE("GPL v2");
/* device driver */
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:simtec-i2c");
+
static struct platform_driver simtec_i2c_driver = {
.driver = {
.name = "simtec-i2c",
MODULE_DESCRIPTION("ARM Versatile I2C bus driver");
MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:versatile-i2c");
if (iface == NULL)
return -ENOMEM;
- if (request_region(base, 8, iface->adapter.name) == 0) {
+ if (!request_region(base, 8, iface->adapter.name)) {
printk(KERN_ERR NAME ": can't allocate io 0x%lx-0x%lx\n",
base, base + 8 - 1);
rc = -EBUSY;
config TPS65010
tristate "TPS6501x Power Management chips"
+ depends on HAVE_GPIO_LIB
default y if MACH_OMAP_H2 || MACH_OMAP_H3 || MACH_OMAP_OSK
help
If you say yes here you get support for the TPS6501x series of
OTG_CTRL_REG |= OTG_PULLUP;
}
- check_state(isp, __FUNCTION__);
+ check_state(isp, __func__);
dump_regs(isp, "otg->isp1301");
}
if (otg_ctrl & OTG_DRIVER_SEL) {
switch (isp->otg.state) {
case OTG_STATE_A_IDLE:
- b_idle(isp, __FUNCTION__);
+ b_idle(isp, __func__);
break;
default:
break;
isp->otg.host->otg_port);
}
- check_state(isp, __FUNCTION__);
+ check_state(isp, __func__);
return ret;
}
if (!otg_dev)
return -ENODEV;
- dump_regs(isp, __FUNCTION__);
+ dump_regs(isp, __func__);
/* some of these values are board-specific... */
OTG_SYSCON_2_REG |= OTG_EN
/* for B-device: */
update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE));
update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS));
- check_state(isp, __FUNCTION__);
+ check_state(isp, __func__);
pr_debug("otg: %s, %s %06x\n",
- state_name(isp), __FUNCTION__, OTG_CTRL_REG);
+ state_name(isp), __func__, OTG_CTRL_REG);
OTG_IRQ_EN_REG = DRIVER_SWITCH | OPRT_CHG
| B_SRP_TMROUT | B_HNP_FAIL
OTG1_DP_PULLDOWN);
isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1,
OTG1_DP_PULLUP);
- dump_regs(isp, __FUNCTION__);
+ dump_regs(isp, __func__);
#endif
/* FALLTHROUGH */
case OTG_STATE_B_SRP_INIT:
- b_idle(isp, __FUNCTION__);
+ b_idle(isp, __func__);
OTG_CTRL_REG &= OTG_CTRL_REG & OTG_XCEIV_OUTPUTS;
/* FALLTHROUGH */
case OTG_STATE_B_IDLE:
*/
update_otg1(isp, isp_stat);
update_otg2(isp, isp_bstat);
- check_state(isp, __FUNCTION__);
+ check_state(isp, __func__);
#endif
dump_regs(isp, "isp1301->otg");
*/
isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_VBUS_DRV);
- dump_regs(isp, __FUNCTION__);
+ dump_regs(isp, __func__);
return 0;
isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING,
INTR_VBUS_VLD);
dev_info(&isp->client.dev, "B-Peripheral sessions ok\n");
- dump_regs(isp, __FUNCTION__);
+ dump_regs(isp, __func__);
/* If this has a Mini-AB connector, this mode is highly
* nonstandard ... but can be handy for testing, so long
pr_debug("otg: SRP, %s ... %06x\n", state_name(isp), OTG_CTRL_REG);
#ifdef CONFIG_USB_OTG
- check_state(isp, __FUNCTION__);
+ check_state(isp, __func__);
#endif
return 0;
}
}
pr_debug("otg: HNP %s, %06x ...\n",
state_name(isp), OTG_CTRL_REG);
- check_state(isp, __FUNCTION__);
+ check_state(isp, __func__);
return 0;
#else
/* srp-only */
update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS));
#endif
- dump_regs(isp, __FUNCTION__);
+ dump_regs(isp, __func__);
#ifdef VERBOSE
mod_timer(&isp->timer, jiffies + TIMER_JIFFIES);
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/mutex.h>
+#include <linux/platform_device.h>
#include <linux/i2c/tps65010.h>
+#include <asm/gpio.h>
+
+
/*-------------------------------------------------------------------------*/
#define DRIVER_VERSION "2 May 2005"
u8 chgstatus, regstatus, chgconf;
u8 nmask1, nmask2;
- /* not currently tracking GPIO state */
+ u8 outmask;
+ struct gpio_chip chip;
+ struct platform_device *leds;
};
#define POWER_POLL_DELAY msecs_to_jiffies(5000)
return IRQ_HANDLED;
}
+/*-------------------------------------------------------------------------*/
+
+/* offsets 0..3 == GPIO1..GPIO4
+ * offsets 4..5 == LED1/nPG, LED2 (we set one of the non-BLINK modes)
+ */
+static void
+tps65010_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ if (offset < 4)
+ tps65010_set_gpio_out_value(offset + 1, value);
+ else
+ tps65010_set_led(offset - 3, value ? ON : OFF);
+}
+
+static int
+tps65010_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+ /* GPIOs may be input-only */
+ if (offset < 4) {
+ struct tps65010 *tps;
+
+ tps = container_of(chip, struct tps65010, chip);
+ if (!(tps->outmask & (1 << offset)))
+ return -EINVAL;
+ tps65010_set_gpio_out_value(offset + 1, value);
+ } else
+ tps65010_set_led(offset - 3, value ? ON : OFF);
+
+ return 0;
+}
+
+static int tps65010_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ int value;
+ struct tps65010 *tps;
+
+ tps = container_of(chip, struct tps65010, chip);
+
+ if (offset < 4) {
+ value = i2c_smbus_read_byte_data(tps->client, TPS_DEFGPIO);
+ if (value < 0)
+ return 0;
+ if (value & (1 << (offset + 4))) /* output */
+ return !(value & (1 << offset));
+ else /* input */
+ return (value & (1 << offset));
+ }
+
+ /* REVISIT we *could* report LED1/nPG and LED2 state ... */
+ return 0;
+}
+
+
/*-------------------------------------------------------------------------*/
static struct tps65010 *the_tps;
static int __exit tps65010_remove(struct i2c_client *client)
{
struct tps65010 *tps = i2c_get_clientdata(client);
+ struct tps65010_board *board = client->dev.platform_data;
+ if (board && board->teardown) {
+ int status = board->teardown(client, board->context);
+ if (status < 0)
+ dev_dbg(&client->dev, "board %s %s err %d\n",
+ "teardown", client->name, status);
+ }
if (client->irq > 0)
free_irq(client->irq, tps);
cancel_delayed_work(&tps->work);
{
struct tps65010 *tps;
int status;
+ struct tps65010_board *board = client->dev.platform_data;
if (the_tps) {
dev_dbg(&client->dev, "only one tps6501x chip allowed\n");
tps->file = debugfs_create_file(DRIVER_NAME, S_IRUGO, NULL,
tps, DEBUG_FOPS);
+
+ /* optionally register GPIOs */
+ if (board && board->base > 0) {
+ tps->outmask = board->outmask;
+
+ tps->chip.label = client->name;
+
+ tps->chip.set = tps65010_gpio_set;
+ tps->chip.direction_output = tps65010_output;
+
+ /* NOTE: only partial support for inputs; nyet IRQs */
+ tps->chip.get = tps65010_gpio_get;
+
+ tps->chip.base = board->base;
+ tps->chip.ngpio = 6;
+ tps->chip.can_sleep = 1;
+
+ status = gpiochip_add(&tps->chip);
+ if (status < 0)
+ dev_err(&client->dev, "can't add gpiochip, err %d\n",
+ status);
+ else if (board->setup) {
+ status = board->setup(client, board->context);
+ if (status < 0) {
+ dev_dbg(&client->dev,
+ "board %s %s err %d\n",
+ "setup", client->name, status);
+ status = 0;
+ }
+ }
+ }
+
return 0;
fail1:
kfree(tps);
#include <linux/completion.h>
#include <linux/hardirq.h>
#include <linux/irqflags.h>
+#include <linux/semaphore.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include "i2c-core.h"
read_write = I2C_SMBUS_READ;
if (data->block[0] > I2C_SMBUS_BLOCK_MAX) {
dev_err(&adapter->dev, "%s called with invalid "
- "block proc call size (%d)\n", __FUNCTION__,
+ "block proc call size (%d)\n", __func__,
data->block[0]);
return -1;
}
return device_for_each_child(&adapter->dev, &addr, i2cdev_check);
}
-static int i2cdev_ioctl(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg)
+static noinline int i2cdev_ioctl_rdrw(struct i2c_client *client,
+ unsigned long arg)
{
- struct i2c_client *client = (struct i2c_client *)file->private_data;
struct i2c_rdwr_ioctl_data rdwr_arg;
- struct i2c_smbus_ioctl_data data_arg;
- union i2c_smbus_data temp;
struct i2c_msg *rdwr_pa;
u8 __user **data_ptrs;
- int i,datasize,res;
+ int i, res;
+
+ if (copy_from_user(&rdwr_arg,
+ (struct i2c_rdwr_ioctl_data __user *)arg,
+ sizeof(rdwr_arg)))
+ return -EFAULT;
+
+ /* Put an arbitrary limit on the number of messages that can
+ * be sent at once */
+ if (rdwr_arg.nmsgs > I2C_RDRW_IOCTL_MAX_MSGS)
+ return -EINVAL;
+
+ rdwr_pa = (struct i2c_msg *)
+ kmalloc(rdwr_arg.nmsgs * sizeof(struct i2c_msg),
+ GFP_KERNEL);
+ if (!rdwr_pa)
+ return -ENOMEM;
+
+ if (copy_from_user(rdwr_pa, rdwr_arg.msgs,
+ rdwr_arg.nmsgs * sizeof(struct i2c_msg))) {
+ kfree(rdwr_pa);
+ return -EFAULT;
+ }
+
+ data_ptrs = kmalloc(rdwr_arg.nmsgs * sizeof(u8 __user *), GFP_KERNEL);
+ if (data_ptrs == NULL) {
+ kfree(rdwr_pa);
+ return -ENOMEM;
+ }
+
+ res = 0;
+ for (i = 0; i < rdwr_arg.nmsgs; i++) {
+ /* Limit the size of the message to a sane amount;
+ * and don't let length change either. */
+ if ((rdwr_pa[i].len > 8192) ||
+ (rdwr_pa[i].flags & I2C_M_RECV_LEN)) {
+ res = -EINVAL;
+ break;
+ }
+ data_ptrs[i] = (u8 __user *)rdwr_pa[i].buf;
+ rdwr_pa[i].buf = kmalloc(rdwr_pa[i].len, GFP_KERNEL);
+ if (rdwr_pa[i].buf == NULL) {
+ res = -ENOMEM;
+ break;
+ }
+ if (copy_from_user(rdwr_pa[i].buf, data_ptrs[i],
+ rdwr_pa[i].len)) {
+ ++i; /* Needs to be kfreed too */
+ res = -EFAULT;
+ break;
+ }
+ }
+ if (res < 0) {
+ int j;
+ for (j = 0; j < i; ++j)
+ kfree(rdwr_pa[j].buf);
+ kfree(data_ptrs);
+ kfree(rdwr_pa);
+ return res;
+ }
+
+ res = i2c_transfer(client->adapter, rdwr_pa, rdwr_arg.nmsgs);
+ while (i-- > 0) {
+ if (res >= 0 && (rdwr_pa[i].flags & I2C_M_RD)) {
+ if (copy_to_user(data_ptrs[i], rdwr_pa[i].buf,
+ rdwr_pa[i].len))
+ res = -EFAULT;
+ }
+ kfree(rdwr_pa[i].buf);
+ }
+ kfree(data_ptrs);
+ kfree(rdwr_pa);
+ return res;
+}
+
+static noinline int i2cdev_ioctl_smbus(struct i2c_client *client,
+ unsigned long arg)
+{
+ struct i2c_smbus_ioctl_data data_arg;
+ union i2c_smbus_data temp;
+ int datasize, res;
+
+ if (copy_from_user(&data_arg,
+ (struct i2c_smbus_ioctl_data __user *) arg,
+ sizeof(struct i2c_smbus_ioctl_data)))
+ return -EFAULT;
+ if ((data_arg.size != I2C_SMBUS_BYTE) &&
+ (data_arg.size != I2C_SMBUS_QUICK) &&
+ (data_arg.size != I2C_SMBUS_BYTE_DATA) &&
+ (data_arg.size != I2C_SMBUS_WORD_DATA) &&
+ (data_arg.size != I2C_SMBUS_PROC_CALL) &&
+ (data_arg.size != I2C_SMBUS_BLOCK_DATA) &&
+ (data_arg.size != I2C_SMBUS_I2C_BLOCK_BROKEN) &&
+ (data_arg.size != I2C_SMBUS_I2C_BLOCK_DATA) &&
+ (data_arg.size != I2C_SMBUS_BLOCK_PROC_CALL)) {
+ dev_dbg(&client->adapter->dev,
+ "size out of range (%x) in ioctl I2C_SMBUS.\n",
+ data_arg.size);
+ return -EINVAL;
+ }
+ /* Note that I2C_SMBUS_READ and I2C_SMBUS_WRITE are 0 and 1,
+ so the check is valid if size==I2C_SMBUS_QUICK too. */
+ if ((data_arg.read_write != I2C_SMBUS_READ) &&
+ (data_arg.read_write != I2C_SMBUS_WRITE)) {
+ dev_dbg(&client->adapter->dev,
+ "read_write out of range (%x) in ioctl I2C_SMBUS.\n",
+ data_arg.read_write);
+ return -EINVAL;
+ }
+
+ /* Note that command values are always valid! */
+
+ if ((data_arg.size == I2C_SMBUS_QUICK) ||
+ ((data_arg.size == I2C_SMBUS_BYTE) &&
+ (data_arg.read_write == I2C_SMBUS_WRITE)))
+ /* These are special: we do not use data */
+ return i2c_smbus_xfer(client->adapter, client->addr,
+ client->flags, data_arg.read_write,
+ data_arg.command, data_arg.size, NULL);
+
+ if (data_arg.data == NULL) {
+ dev_dbg(&client->adapter->dev,
+ "data is NULL pointer in ioctl I2C_SMBUS.\n");
+ return -EINVAL;
+ }
+
+ if ((data_arg.size == I2C_SMBUS_BYTE_DATA) ||
+ (data_arg.size == I2C_SMBUS_BYTE))
+ datasize = sizeof(data_arg.data->byte);
+ else if ((data_arg.size == I2C_SMBUS_WORD_DATA) ||
+ (data_arg.size == I2C_SMBUS_PROC_CALL))
+ datasize = sizeof(data_arg.data->word);
+ else /* size == smbus block, i2c block, or block proc. call */
+ datasize = sizeof(data_arg.data->block);
+
+ if ((data_arg.size == I2C_SMBUS_PROC_CALL) ||
+ (data_arg.size == I2C_SMBUS_BLOCK_PROC_CALL) ||
+ (data_arg.size == I2C_SMBUS_I2C_BLOCK_DATA) ||
+ (data_arg.read_write == I2C_SMBUS_WRITE)) {
+ if (copy_from_user(&temp, data_arg.data, datasize))
+ return -EFAULT;
+ }
+ if (data_arg.size == I2C_SMBUS_I2C_BLOCK_BROKEN) {
+ /* Convert old I2C block commands to the new
+ convention. This preserves binary compatibility. */
+ data_arg.size = I2C_SMBUS_I2C_BLOCK_DATA;
+ if (data_arg.read_write == I2C_SMBUS_READ)
+ temp.block[0] = I2C_SMBUS_BLOCK_MAX;
+ }
+ res = i2c_smbus_xfer(client->adapter, client->addr, client->flags,
+ data_arg.read_write, data_arg.command, data_arg.size, &temp);
+ if (!res && ((data_arg.size == I2C_SMBUS_PROC_CALL) ||
+ (data_arg.size == I2C_SMBUS_BLOCK_PROC_CALL) ||
+ (data_arg.read_write == I2C_SMBUS_READ))) {
+ if (copy_to_user(data_arg.data, &temp, datasize))
+ return -EFAULT;
+ }
+ return res;
+}
+
+static int i2cdev_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ struct i2c_client *client = (struct i2c_client *)file->private_data;
unsigned long funcs;
dev_dbg(&client->adapter->dev, "ioctl, cmd=0x%02x, arg=0x%02lx\n",
return put_user(funcs, (unsigned long __user *)arg);
case I2C_RDWR:
- if (copy_from_user(&rdwr_arg,
- (struct i2c_rdwr_ioctl_data __user *)arg,
- sizeof(rdwr_arg)))
- return -EFAULT;
-
- /* Put an arbitrary limit on the number of messages that can
- * be sent at once */
- if (rdwr_arg.nmsgs > I2C_RDRW_IOCTL_MAX_MSGS)
- return -EINVAL;
-
- rdwr_pa = (struct i2c_msg *)
- kmalloc(rdwr_arg.nmsgs * sizeof(struct i2c_msg),
- GFP_KERNEL);
-
- if (rdwr_pa == NULL) return -ENOMEM;
-
- if (copy_from_user(rdwr_pa, rdwr_arg.msgs,
- rdwr_arg.nmsgs * sizeof(struct i2c_msg))) {
- kfree(rdwr_pa);
- return -EFAULT;
- }
-
- data_ptrs = kmalloc(rdwr_arg.nmsgs * sizeof(u8 __user *), GFP_KERNEL);
- if (data_ptrs == NULL) {
- kfree(rdwr_pa);
- return -ENOMEM;
- }
-
- res = 0;
- for( i=0; i<rdwr_arg.nmsgs; i++ ) {
- /* Limit the size of the message to a sane amount;
- * and don't let length change either. */
- if ((rdwr_pa[i].len > 8192) ||
- (rdwr_pa[i].flags & I2C_M_RECV_LEN)) {
- res = -EINVAL;
- break;
- }
- data_ptrs[i] = (u8 __user *)rdwr_pa[i].buf;
- rdwr_pa[i].buf = kmalloc(rdwr_pa[i].len, GFP_KERNEL);
- if(rdwr_pa[i].buf == NULL) {
- res = -ENOMEM;
- break;
- }
- if(copy_from_user(rdwr_pa[i].buf,
- data_ptrs[i],
- rdwr_pa[i].len)) {
- ++i; /* Needs to be kfreed too */
- res = -EFAULT;
- break;
- }
- }
- if (res < 0) {
- int j;
- for (j = 0; j < i; ++j)
- kfree(rdwr_pa[j].buf);
- kfree(data_ptrs);
- kfree(rdwr_pa);
- return res;
- }
-
- res = i2c_transfer(client->adapter,
- rdwr_pa,
- rdwr_arg.nmsgs);
- while(i-- > 0) {
- if( res>=0 && (rdwr_pa[i].flags & I2C_M_RD)) {
- if(copy_to_user(
- data_ptrs[i],
- rdwr_pa[i].buf,
- rdwr_pa[i].len)) {
- res = -EFAULT;
- }
- }
- kfree(rdwr_pa[i].buf);
- }
- kfree(data_ptrs);
- kfree(rdwr_pa);
- return res;
+ return i2cdev_ioctl_rdrw(client, arg);
case I2C_SMBUS:
- if (copy_from_user(&data_arg,
- (struct i2c_smbus_ioctl_data __user *) arg,
- sizeof(struct i2c_smbus_ioctl_data)))
- return -EFAULT;
- if ((data_arg.size != I2C_SMBUS_BYTE) &&
- (data_arg.size != I2C_SMBUS_QUICK) &&
- (data_arg.size != I2C_SMBUS_BYTE_DATA) &&
- (data_arg.size != I2C_SMBUS_WORD_DATA) &&
- (data_arg.size != I2C_SMBUS_PROC_CALL) &&
- (data_arg.size != I2C_SMBUS_BLOCK_DATA) &&
- (data_arg.size != I2C_SMBUS_I2C_BLOCK_BROKEN) &&
- (data_arg.size != I2C_SMBUS_I2C_BLOCK_DATA) &&
- (data_arg.size != I2C_SMBUS_BLOCK_PROC_CALL)) {
- dev_dbg(&client->adapter->dev,
- "size out of range (%x) in ioctl I2C_SMBUS.\n",
- data_arg.size);
- return -EINVAL;
- }
- /* Note that I2C_SMBUS_READ and I2C_SMBUS_WRITE are 0 and 1,
- so the check is valid if size==I2C_SMBUS_QUICK too. */
- if ((data_arg.read_write != I2C_SMBUS_READ) &&
- (data_arg.read_write != I2C_SMBUS_WRITE)) {
- dev_dbg(&client->adapter->dev,
- "read_write out of range (%x) in ioctl I2C_SMBUS.\n",
- data_arg.read_write);
- return -EINVAL;
- }
-
- /* Note that command values are always valid! */
-
- if ((data_arg.size == I2C_SMBUS_QUICK) ||
- ((data_arg.size == I2C_SMBUS_BYTE) &&
- (data_arg.read_write == I2C_SMBUS_WRITE)))
- /* These are special: we do not use data */
- return i2c_smbus_xfer(client->adapter, client->addr,
- client->flags,
- data_arg.read_write,
- data_arg.command,
- data_arg.size, NULL);
-
- if (data_arg.data == NULL) {
- dev_dbg(&client->adapter->dev,
- "data is NULL pointer in ioctl I2C_SMBUS.\n");
- return -EINVAL;
- }
+ return i2cdev_ioctl_smbus(client, arg);
- if ((data_arg.size == I2C_SMBUS_BYTE_DATA) ||
- (data_arg.size == I2C_SMBUS_BYTE))
- datasize = sizeof(data_arg.data->byte);
- else if ((data_arg.size == I2C_SMBUS_WORD_DATA) ||
- (data_arg.size == I2C_SMBUS_PROC_CALL))
- datasize = sizeof(data_arg.data->word);
- else /* size == smbus block, i2c block, or block proc. call */
- datasize = sizeof(data_arg.data->block);
-
- if ((data_arg.size == I2C_SMBUS_PROC_CALL) ||
- (data_arg.size == I2C_SMBUS_BLOCK_PROC_CALL) ||
- (data_arg.size == I2C_SMBUS_I2C_BLOCK_DATA) ||
- (data_arg.read_write == I2C_SMBUS_WRITE)) {
- if (copy_from_user(&temp, data_arg.data, datasize))
- return -EFAULT;
- }
- if (data_arg.size == I2C_SMBUS_I2C_BLOCK_BROKEN) {
- /* Convert old I2C block commands to the new
- convention. This preserves binary compatibility. */
- data_arg.size = I2C_SMBUS_I2C_BLOCK_DATA;
- if (data_arg.read_write == I2C_SMBUS_READ)
- temp.block[0] = I2C_SMBUS_BLOCK_MAX;
- }
- res = i2c_smbus_xfer(client->adapter,client->addr,client->flags,
- data_arg.read_write,
- data_arg.command,data_arg.size,&temp);
- if (! res && ((data_arg.size == I2C_SMBUS_PROC_CALL) ||
- (data_arg.size == I2C_SMBUS_BLOCK_PROC_CALL) ||
- (data_arg.read_write == I2C_SMBUS_READ))) {
- if (copy_to_user(data_arg.data, &temp, datasize))
- return -EFAULT;
- }
- return res;
case I2C_RETRIES:
client->adapter->retries = arg;
break;
kfree(info->buffer);
kfree(info->toc);
- if (devinfo->handle == drive && unregister_cdrom(devinfo))
- printk(KERN_ERR "%s: %s failed to unregister device from the cdrom "
- "driver.\n", __FUNCTION__, drive->name);
+ if (devinfo->handle == drive)
+ unregister_cdrom(devinfo);
drive->dsc_overlap = 0;
drive->driver_data = NULL;
blk_queue_prep_rq(drive->queue, NULL);
#include <linux/moduleparam.h>
#include <linux/mutex.h>
#include <linux/freezer.h>
+#include <linux/semaphore.h>
#include <asm/atomic.h>
-#include <asm/semaphore.h>
#include "csr.h"
#include "highlevel.h"
.default_attrs = port_default_attrs
};
-static void ib_device_release(struct class_device *cdev)
+static void ib_device_release(struct device *device)
{
- struct ib_device *dev = container_of(cdev, struct ib_device, class_dev);
+ struct ib_device *dev = container_of(device, struct ib_device, dev);
kfree(dev);
}
-static int ib_device_uevent(struct class_device *cdev,
+static int ib_device_uevent(struct device *device,
struct kobj_uevent_env *env)
{
- struct ib_device *dev = container_of(cdev, struct ib_device, class_dev);
+ struct ib_device *dev = container_of(device, struct ib_device, dev);
if (add_uevent_var(env, "NAME=%s", dev->name))
return -ENOMEM;
return ret;
}
-static ssize_t show_node_type(struct class_device *cdev, char *buf)
+static ssize_t show_node_type(struct device *device,
+ struct device_attribute *attr, char *buf)
{
- struct ib_device *dev = container_of(cdev, struct ib_device, class_dev);
+ struct ib_device *dev = container_of(device, struct ib_device, dev);
if (!ibdev_is_alive(dev))
return -ENODEV;
}
}
-static ssize_t show_sys_image_guid(struct class_device *cdev, char *buf)
+static ssize_t show_sys_image_guid(struct device *device,
+ struct device_attribute *dev_attr, char *buf)
{
- struct ib_device *dev = container_of(cdev, struct ib_device, class_dev);
+ struct ib_device *dev = container_of(device, struct ib_device, dev);
struct ib_device_attr attr;
ssize_t ret;
be16_to_cpu(((__be16 *) &attr.sys_image_guid)[3]));
}
-static ssize_t show_node_guid(struct class_device *cdev, char *buf)
+static ssize_t show_node_guid(struct device *device,
+ struct device_attribute *attr, char *buf)
{
- struct ib_device *dev = container_of(cdev, struct ib_device, class_dev);
+ struct ib_device *dev = container_of(device, struct ib_device, dev);
if (!ibdev_is_alive(dev))
return -ENODEV;
be16_to_cpu(((__be16 *) &dev->node_guid)[3]));
}
-static ssize_t show_node_desc(struct class_device *cdev, char *buf)
+static ssize_t show_node_desc(struct device *device,
+ struct device_attribute *attr, char *buf)
{
- struct ib_device *dev = container_of(cdev, struct ib_device, class_dev);
+ struct ib_device *dev = container_of(device, struct ib_device, dev);
return sprintf(buf, "%.64s\n", dev->node_desc);
}
-static ssize_t set_node_desc(struct class_device *cdev, const char *buf,
- size_t count)
+static ssize_t set_node_desc(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct ib_device *dev = container_of(cdev, struct ib_device, class_dev);
+ struct ib_device *dev = container_of(device, struct ib_device, dev);
struct ib_device_modify desc = {};
int ret;
return count;
}
-static CLASS_DEVICE_ATTR(node_type, S_IRUGO, show_node_type, NULL);
-static CLASS_DEVICE_ATTR(sys_image_guid, S_IRUGO, show_sys_image_guid, NULL);
-static CLASS_DEVICE_ATTR(node_guid, S_IRUGO, show_node_guid, NULL);
-static CLASS_DEVICE_ATTR(node_desc, S_IRUGO | S_IWUSR, show_node_desc,
- set_node_desc);
-
-static struct class_device_attribute *ib_class_attributes[] = {
- &class_device_attr_node_type,
- &class_device_attr_sys_image_guid,
- &class_device_attr_node_guid,
- &class_device_attr_node_desc
+static DEVICE_ATTR(node_type, S_IRUGO, show_node_type, NULL);
+static DEVICE_ATTR(sys_image_guid, S_IRUGO, show_sys_image_guid, NULL);
+static DEVICE_ATTR(node_guid, S_IRUGO, show_node_guid, NULL);
+static DEVICE_ATTR(node_desc, S_IRUGO | S_IWUSR, show_node_desc, set_node_desc);
+
+static struct device_attribute *ib_class_attributes[] = {
+ &dev_attr_node_type,
+ &dev_attr_sys_image_guid,
+ &dev_attr_node_guid,
+ &dev_attr_node_desc
};
static struct class ib_class = {
.name = "infiniband",
- .release = ib_device_release,
- .uevent = ib_device_uevent,
+ .dev_release = ib_device_release,
+ .dev_uevent = ib_device_uevent,
};
int ib_device_register_sysfs(struct ib_device *device)
{
- struct class_device *class_dev = &device->class_dev;
+ struct device *class_dev = &device->dev;
int ret;
int i;
class_dev->class = &ib_class;
- class_dev->class_data = device;
- class_dev->dev = device->dma_device;
- strlcpy(class_dev->class_id, device->name, BUS_ID_SIZE);
+ class_dev->driver_data = device;
+ class_dev->parent = device->dma_device;
+ strlcpy(class_dev->bus_id, device->name, BUS_ID_SIZE);
INIT_LIST_HEAD(&device->port_list);
- ret = class_device_register(class_dev);
+ ret = device_register(class_dev);
if (ret)
goto err;
for (i = 0; i < ARRAY_SIZE(ib_class_attributes); ++i) {
- ret = class_device_create_file(class_dev, ib_class_attributes[i]);
+ ret = device_create_file(class_dev, ib_class_attributes[i]);
if (ret)
goto err_unregister;
}
kobject_put(&class_dev->kobj);
err_unregister:
- class_device_unregister(class_dev);
+ device_unregister(class_dev);
err:
return ret;
}
kobject_put(device->ports_parent);
- class_device_unregister(&device->class_dev);
+ device_unregister(&device->dev);
}
int ib_sysfs_setup(void)
struct ib_ucm_device {
int devnum;
- struct cdev dev;
- struct class_device class_dev;
+ struct cdev cdev;
+ struct device dev;
struct ib_device *ib_dev;
};
filp->private_data = file;
file->filp = filp;
- file->device = container_of(inode->i_cdev, struct ib_ucm_device, dev);
+ file->device = container_of(inode->i_cdev, struct ib_ucm_device, cdev);
return 0;
}
return 0;
}
-static void ucm_release_class_dev(struct class_device *class_dev)
+static void ib_ucm_release_dev(struct device *dev)
{
- struct ib_ucm_device *dev;
+ struct ib_ucm_device *ucm_dev;
- dev = container_of(class_dev, struct ib_ucm_device, class_dev);
- cdev_del(&dev->dev);
- clear_bit(dev->devnum, dev_map);
- kfree(dev);
+ ucm_dev = container_of(dev, struct ib_ucm_device, dev);
+ cdev_del(&ucm_dev->cdev);
+ clear_bit(ucm_dev->devnum, dev_map);
+ kfree(ucm_dev);
}
static const struct file_operations ucm_fops = {
.poll = ib_ucm_poll,
};
-static ssize_t show_ibdev(struct class_device *class_dev, char *buf)
+static ssize_t show_ibdev(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct ib_ucm_device *dev;
+ struct ib_ucm_device *ucm_dev;
- dev = container_of(class_dev, struct ib_ucm_device, class_dev);
- return sprintf(buf, "%s\n", dev->ib_dev->name);
+ ucm_dev = container_of(dev, struct ib_ucm_device, dev);
+ return sprintf(buf, "%s\n", ucm_dev->ib_dev->name);
}
-static CLASS_DEVICE_ATTR(ibdev, S_IRUGO, show_ibdev, NULL);
+static DEVICE_ATTR(ibdev, S_IRUGO, show_ibdev, NULL);
static void ib_ucm_add_one(struct ib_device *device)
{
set_bit(ucm_dev->devnum, dev_map);
- cdev_init(&ucm_dev->dev, &ucm_fops);
- ucm_dev->dev.owner = THIS_MODULE;
- kobject_set_name(&ucm_dev->dev.kobj, "ucm%d", ucm_dev->devnum);
- if (cdev_add(&ucm_dev->dev, IB_UCM_BASE_DEV + ucm_dev->devnum, 1))
+ cdev_init(&ucm_dev->cdev, &ucm_fops);
+ ucm_dev->cdev.owner = THIS_MODULE;
+ kobject_set_name(&ucm_dev->cdev.kobj, "ucm%d", ucm_dev->devnum);
+ if (cdev_add(&ucm_dev->cdev, IB_UCM_BASE_DEV + ucm_dev->devnum, 1))
goto err;
- ucm_dev->class_dev.class = &cm_class;
- ucm_dev->class_dev.dev = device->dma_device;
- ucm_dev->class_dev.devt = ucm_dev->dev.dev;
- ucm_dev->class_dev.release = ucm_release_class_dev;
- snprintf(ucm_dev->class_dev.class_id, BUS_ID_SIZE, "ucm%d",
+ ucm_dev->dev.class = &cm_class;
+ ucm_dev->dev.parent = device->dma_device;
+ ucm_dev->dev.devt = ucm_dev->cdev.dev;
+ ucm_dev->dev.release = ib_ucm_release_dev;
+ snprintf(ucm_dev->dev.bus_id, BUS_ID_SIZE, "ucm%d",
ucm_dev->devnum);
- if (class_device_register(&ucm_dev->class_dev))
+ if (device_register(&ucm_dev->dev))
goto err_cdev;
- if (class_device_create_file(&ucm_dev->class_dev,
- &class_device_attr_ibdev))
- goto err_class;
+ if (device_create_file(&ucm_dev->dev, &dev_attr_ibdev))
+ goto err_dev;
ib_set_client_data(device, &ucm_client, ucm_dev);
return;
-err_class:
- class_device_unregister(&ucm_dev->class_dev);
+err_dev:
+ device_unregister(&ucm_dev->dev);
err_cdev:
- cdev_del(&ucm_dev->dev);
+ cdev_del(&ucm_dev->cdev);
clear_bit(ucm_dev->devnum, dev_map);
err:
kfree(ucm_dev);
if (!ucm_dev)
return;
- class_device_unregister(&ucm_dev->class_dev);
+ device_unregister(&ucm_dev->dev);
}
static ssize_t show_abi_version(struct class *class, char *buf)
#include <linux/mutex.h>
#include <linux/kref.h>
#include <linux/compat.h>
+#include <linux/semaphore.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <rdma/ib_mad.h>
#include <rdma/ib_user_mad.h>
*/
struct ib_umad_port {
- struct cdev *dev;
- struct class_device *class_dev;
+ struct cdev *cdev;
+ struct device *dev;
- struct cdev *sm_dev;
- struct class_device *sm_class_dev;
+ struct cdev *sm_cdev;
+ struct device *sm_dev;
struct semaphore sm_sem;
struct mutex file_mutex;
.remove = ib_umad_remove_one
};
-static ssize_t show_ibdev(struct class_device *class_dev, char *buf)
+static ssize_t show_ibdev(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct ib_umad_port *port = class_get_devdata(class_dev);
+ struct ib_umad_port *port = dev_get_drvdata(dev);
if (!port)
return -ENODEV;
return sprintf(buf, "%s\n", port->ib_dev->name);
}
-static CLASS_DEVICE_ATTR(ibdev, S_IRUGO, show_ibdev, NULL);
+static DEVICE_ATTR(ibdev, S_IRUGO, show_ibdev, NULL);
-static ssize_t show_port(struct class_device *class_dev, char *buf)
+static ssize_t show_port(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct ib_umad_port *port = class_get_devdata(class_dev);
+ struct ib_umad_port *port = dev_get_drvdata(dev);
if (!port)
return -ENODEV;
return sprintf(buf, "%d\n", port->port_num);
}
-static CLASS_DEVICE_ATTR(port, S_IRUGO, show_port, NULL);
+static DEVICE_ATTR(port, S_IRUGO, show_port, NULL);
static ssize_t show_abi_version(struct class *class, char *buf)
{
mutex_init(&port->file_mutex);
INIT_LIST_HEAD(&port->file_list);
- port->dev = cdev_alloc();
- if (!port->dev)
+ port->cdev = cdev_alloc();
+ if (!port->cdev)
return -1;
- port->dev->owner = THIS_MODULE;
- port->dev->ops = &umad_fops;
- kobject_set_name(&port->dev->kobj, "umad%d", port->dev_num);
- if (cdev_add(port->dev, base_dev + port->dev_num, 1))
+ port->cdev->owner = THIS_MODULE;
+ port->cdev->ops = &umad_fops;
+ kobject_set_name(&port->cdev->kobj, "umad%d", port->dev_num);
+ if (cdev_add(port->cdev, base_dev + port->dev_num, 1))
goto err_cdev;
- port->class_dev = class_device_create(umad_class, NULL, port->dev->dev,
- device->dma_device,
- "umad%d", port->dev_num);
- if (IS_ERR(port->class_dev))
+ port->dev = device_create(umad_class, device->dma_device,
+ port->cdev->dev, "umad%d", port->dev_num);
+ if (IS_ERR(port->dev))
goto err_cdev;
- if (class_device_create_file(port->class_dev, &class_device_attr_ibdev))
- goto err_class;
- if (class_device_create_file(port->class_dev, &class_device_attr_port))
- goto err_class;
-
- port->sm_dev = cdev_alloc();
- if (!port->sm_dev)
- goto err_class;
- port->sm_dev->owner = THIS_MODULE;
- port->sm_dev->ops = &umad_sm_fops;
- kobject_set_name(&port->sm_dev->kobj, "issm%d", port->dev_num);
- if (cdev_add(port->sm_dev, base_dev + port->dev_num + IB_UMAD_MAX_PORTS, 1))
+ if (device_create_file(port->dev, &dev_attr_ibdev))
+ goto err_dev;
+ if (device_create_file(port->dev, &dev_attr_port))
+ goto err_dev;
+
+ port->sm_cdev = cdev_alloc();
+ if (!port->sm_cdev)
+ goto err_dev;
+ port->sm_cdev->owner = THIS_MODULE;
+ port->sm_cdev->ops = &umad_sm_fops;
+ kobject_set_name(&port->sm_cdev->kobj, "issm%d", port->dev_num);
+ if (cdev_add(port->sm_cdev, base_dev + port->dev_num + IB_UMAD_MAX_PORTS, 1))
goto err_sm_cdev;
- port->sm_class_dev = class_device_create(umad_class, NULL, port->sm_dev->dev,
- device->dma_device,
- "issm%d", port->dev_num);
- if (IS_ERR(port->sm_class_dev))
+ port->sm_dev = device_create(umad_class, device->dma_device,
+ port->sm_cdev->dev,
+ "issm%d", port->dev_num);
+ if (IS_ERR(port->sm_dev))
goto err_sm_cdev;
- class_set_devdata(port->class_dev, port);
- class_set_devdata(port->sm_class_dev, port);
+ dev_set_drvdata(port->dev, port);
+ dev_set_drvdata(port->sm_dev, port);
- if (class_device_create_file(port->sm_class_dev, &class_device_attr_ibdev))
- goto err_sm_class;
- if (class_device_create_file(port->sm_class_dev, &class_device_attr_port))
- goto err_sm_class;
+ if (device_create_file(port->sm_dev, &dev_attr_ibdev))
+ goto err_sm_dev;
+ if (device_create_file(port->sm_dev, &dev_attr_port))
+ goto err_sm_dev;
spin_lock(&port_lock);
umad_port[port->dev_num] = port;
return 0;
-err_sm_class:
- class_device_destroy(umad_class, port->sm_dev->dev);
+err_sm_dev:
+ device_destroy(umad_class, port->sm_cdev->dev);
err_sm_cdev:
- cdev_del(port->sm_dev);
+ cdev_del(port->sm_cdev);
-err_class:
- class_device_destroy(umad_class, port->dev->dev);
+err_dev:
+ device_destroy(umad_class, port->cdev->dev);
err_cdev:
- cdev_del(port->dev);
+ cdev_del(port->cdev);
clear_bit(port->dev_num, dev_map);
return -1;
int already_dead;
int id;
- class_set_devdata(port->class_dev, NULL);
- class_set_devdata(port->sm_class_dev, NULL);
+ dev_set_drvdata(port->dev, NULL);
+ dev_set_drvdata(port->sm_dev, NULL);
- class_device_destroy(umad_class, port->dev->dev);
- class_device_destroy(umad_class, port->sm_dev->dev);
+ device_destroy(umad_class, port->cdev->dev);
+ device_destroy(umad_class, port->sm_cdev->dev);
- cdev_del(port->dev);
- cdev_del(port->sm_dev);
+ cdev_del(port->cdev);
+ cdev_del(port->sm_cdev);
spin_lock(&port_lock);
umad_port[port->dev_num] = NULL;
struct kref ref;
struct completion comp;
int devnum;
- struct cdev *dev;
- struct class_device *class_dev;
+ struct cdev *cdev;
+ struct device *dev;
struct ib_device *ib_dev;
int num_comp_vectors;
};
.remove = ib_uverbs_remove_one
};
-static ssize_t show_ibdev(struct class_device *class_dev, char *buf)
+static ssize_t show_ibdev(struct device *device, struct device_attribute *attr,
+ char *buf)
{
- struct ib_uverbs_device *dev = class_get_devdata(class_dev);
+ struct ib_uverbs_device *dev = dev_get_drvdata(device);
if (!dev)
return -ENODEV;
return sprintf(buf, "%s\n", dev->ib_dev->name);
}
-static CLASS_DEVICE_ATTR(ibdev, S_IRUGO, show_ibdev, NULL);
+static DEVICE_ATTR(ibdev, S_IRUGO, show_ibdev, NULL);
-static ssize_t show_dev_abi_version(struct class_device *class_dev, char *buf)
+static ssize_t show_dev_abi_version(struct device *device,
+ struct device_attribute *attr, char *buf)
{
- struct ib_uverbs_device *dev = class_get_devdata(class_dev);
+ struct ib_uverbs_device *dev = dev_get_drvdata(device);
if (!dev)
return -ENODEV;
return sprintf(buf, "%d\n", dev->ib_dev->uverbs_abi_ver);
}
-static CLASS_DEVICE_ATTR(abi_version, S_IRUGO, show_dev_abi_version, NULL);
+static DEVICE_ATTR(abi_version, S_IRUGO, show_dev_abi_version, NULL);
static ssize_t show_abi_version(struct class *class, char *buf)
{
uverbs_dev->ib_dev = device;
uverbs_dev->num_comp_vectors = device->num_comp_vectors;
- uverbs_dev->dev = cdev_alloc();
- if (!uverbs_dev->dev)
+ uverbs_dev->cdev = cdev_alloc();
+ if (!uverbs_dev->cdev)
goto err;
- uverbs_dev->dev->owner = THIS_MODULE;
- uverbs_dev->dev->ops = device->mmap ? &uverbs_mmap_fops : &uverbs_fops;
- kobject_set_name(&uverbs_dev->dev->kobj, "uverbs%d", uverbs_dev->devnum);
- if (cdev_add(uverbs_dev->dev, IB_UVERBS_BASE_DEV + uverbs_dev->devnum, 1))
+ uverbs_dev->cdev->owner = THIS_MODULE;
+ uverbs_dev->cdev->ops = device->mmap ? &uverbs_mmap_fops : &uverbs_fops;
+ kobject_set_name(&uverbs_dev->cdev->kobj, "uverbs%d", uverbs_dev->devnum);
+ if (cdev_add(uverbs_dev->cdev, IB_UVERBS_BASE_DEV + uverbs_dev->devnum, 1))
goto err_cdev;
- uverbs_dev->class_dev = class_device_create(uverbs_class, NULL,
- uverbs_dev->dev->dev,
- device->dma_device,
- "uverbs%d", uverbs_dev->devnum);
- if (IS_ERR(uverbs_dev->class_dev))
+ uverbs_dev->dev = device_create(uverbs_class, device->dma_device,
+ uverbs_dev->cdev->dev,
+ "uverbs%d", uverbs_dev->devnum);
+ if (IS_ERR(uverbs_dev->dev))
goto err_cdev;
- class_set_devdata(uverbs_dev->class_dev, uverbs_dev);
+ dev_set_drvdata(uverbs_dev->dev, uverbs_dev);
- if (class_device_create_file(uverbs_dev->class_dev, &class_device_attr_ibdev))
+ if (device_create_file(uverbs_dev->dev, &dev_attr_ibdev))
goto err_class;
- if (class_device_create_file(uverbs_dev->class_dev, &class_device_attr_abi_version))
+ if (device_create_file(uverbs_dev->dev, &dev_attr_abi_version))
goto err_class;
spin_lock(&map_lock);
return;
err_class:
- class_device_destroy(uverbs_class, uverbs_dev->dev->dev);
+ device_destroy(uverbs_class, uverbs_dev->cdev->dev);
err_cdev:
- cdev_del(uverbs_dev->dev);
+ cdev_del(uverbs_dev->cdev);
clear_bit(uverbs_dev->devnum, dev_map);
err:
if (!uverbs_dev)
return;
- class_set_devdata(uverbs_dev->class_dev, NULL);
- class_device_destroy(uverbs_class, uverbs_dev->dev->dev);
- cdev_del(uverbs_dev->dev);
+ dev_set_drvdata(uverbs_dev->dev, NULL);
+ device_destroy(uverbs_class, uverbs_dev->cdev->dev);
+ cdev_del(uverbs_dev->cdev);
spin_lock(&map_lock);
dev_table[uverbs_dev->devnum] = NULL;
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/idr.h>
-#include <asm/semaphore.h>
#include "c2_provider.h"
#include "c2_mq.h"
return err;
}
-static ssize_t show_rev(struct class_device *cdev, char *buf)
+static ssize_t show_rev(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct c2_dev *dev = container_of(cdev, struct c2_dev, ibdev.class_dev);
+ struct c2_dev *c2dev = container_of(dev, struct c2_dev, ibdev.dev);
pr_debug("%s:%u\n", __func__, __LINE__);
- return sprintf(buf, "%x\n", dev->props.hw_ver);
+ return sprintf(buf, "%x\n", c2dev->props.hw_ver);
}
-static ssize_t show_fw_ver(struct class_device *cdev, char *buf)
+static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct c2_dev *dev = container_of(cdev, struct c2_dev, ibdev.class_dev);
+ struct c2_dev *c2dev = container_of(dev, struct c2_dev, ibdev.dev);
pr_debug("%s:%u\n", __func__, __LINE__);
return sprintf(buf, "%x.%x.%x\n",
- (int) (dev->props.fw_ver >> 32),
- (int) (dev->props.fw_ver >> 16) & 0xffff,
- (int) (dev->props.fw_ver & 0xffff));
+ (int) (c2dev->props.fw_ver >> 32),
+ (int) (c2dev->props.fw_ver >> 16) & 0xffff,
+ (int) (c2dev->props.fw_ver & 0xffff));
}
-static ssize_t show_hca(struct class_device *cdev, char *buf)
+static ssize_t show_hca(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
pr_debug("%s:%u\n", __func__, __LINE__);
return sprintf(buf, "AMSO1100\n");
}
-static ssize_t show_board(struct class_device *cdev, char *buf)
+static ssize_t show_board(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
pr_debug("%s:%u\n", __func__, __LINE__);
return sprintf(buf, "%.*s\n", 32, "AMSO1100 Board ID");
}
-static CLASS_DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
-static CLASS_DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
-static CLASS_DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
-static CLASS_DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
+static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
+static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
+static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
+static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
-static struct class_device_attribute *c2_class_attributes[] = {
- &class_device_attr_hw_rev,
- &class_device_attr_fw_ver,
- &class_device_attr_hca_type,
- &class_device_attr_board_id
+static struct device_attribute *c2_dev_attributes[] = {
+ &dev_attr_hw_rev,
+ &dev_attr_fw_ver,
+ &dev_attr_hca_type,
+ &dev_attr_board_id
};
static int c2_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
if (ret)
goto out1;
- for (i = 0; i < ARRAY_SIZE(c2_class_attributes); ++i) {
- ret = class_device_create_file(&dev->ibdev.class_dev,
- c2_class_attributes[i]);
+ for (i = 0; i < ARRAY_SIZE(c2_dev_attributes); ++i) {
+ ret = device_create_file(&dev->ibdev.dev,
+ c2_dev_attributes[i]);
if (ret)
goto out0;
}
return 0;
}
-static ssize_t show_rev(struct class_device *cdev, char *buf)
+static ssize_t show_rev(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct iwch_dev *dev = container_of(cdev, struct iwch_dev,
- ibdev.class_dev);
- PDBG("%s class dev 0x%p\n", __func__, cdev);
- return sprintf(buf, "%d\n", dev->rdev.t3cdev_p->type);
+ struct iwch_dev *iwch_dev = container_of(dev, struct iwch_dev,
+ ibdev.dev);
+ PDBG("%s dev 0x%p\n", __func__, dev);
+ return sprintf(buf, "%d\n", iwch_dev->rdev.t3cdev_p->type);
}
-static ssize_t show_fw_ver(struct class_device *cdev, char *buf)
+static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr, char *buf)
{
- struct iwch_dev *dev = container_of(cdev, struct iwch_dev,
- ibdev.class_dev);
+ struct iwch_dev *iwch_dev = container_of(dev, struct iwch_dev,
+ ibdev.dev);
struct ethtool_drvinfo info;
- struct net_device *lldev = dev->rdev.t3cdev_p->lldev;
+ struct net_device *lldev = iwch_dev->rdev.t3cdev_p->lldev;
- PDBG("%s class dev 0x%p\n", __func__, cdev);
- rtnl_lock();
+ PDBG("%s dev 0x%p\n", __func__, dev);
lldev->ethtool_ops->get_drvinfo(lldev, &info);
- rtnl_unlock();
return sprintf(buf, "%s\n", info.fw_version);
}
-static ssize_t show_hca(struct class_device *cdev, char *buf)
+static ssize_t show_hca(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct iwch_dev *dev = container_of(cdev, struct iwch_dev,
- ibdev.class_dev);
+ struct iwch_dev *iwch_dev = container_of(dev, struct iwch_dev,
+ ibdev.dev);
struct ethtool_drvinfo info;
- struct net_device *lldev = dev->rdev.t3cdev_p->lldev;
+ struct net_device *lldev = iwch_dev->rdev.t3cdev_p->lldev;
- PDBG("%s class dev 0x%p\n", __func__, cdev);
- rtnl_lock();
+ PDBG("%s dev 0x%p\n", __func__, dev);
lldev->ethtool_ops->get_drvinfo(lldev, &info);
- rtnl_unlock();
return sprintf(buf, "%s\n", info.driver);
}
-static ssize_t show_board(struct class_device *cdev, char *buf)
+static ssize_t show_board(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct iwch_dev *dev = container_of(cdev, struct iwch_dev,
- ibdev.class_dev);
- PDBG("%s class dev 0x%p\n", __func__, dev);
- return sprintf(buf, "%x.%x\n", dev->rdev.rnic_info.pdev->vendor,
- dev->rdev.rnic_info.pdev->device);
+ struct iwch_dev *iwch_dev = container_of(dev, struct iwch_dev,
+ ibdev.dev);
+ PDBG("%s dev 0x%p\n", __func__, dev);
+ return sprintf(buf, "%x.%x\n", iwch_dev->rdev.rnic_info.pdev->vendor,
+ iwch_dev->rdev.rnic_info.pdev->device);
}
-static CLASS_DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
-static CLASS_DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
-static CLASS_DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
-static CLASS_DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
+static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
+static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
+static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
+static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
-static struct class_device_attribute *iwch_class_attributes[] = {
- &class_device_attr_hw_rev,
- &class_device_attr_fw_ver,
- &class_device_attr_hca_type,
- &class_device_attr_board_id
+static struct device_attribute *iwch_class_attributes[] = {
+ &dev_attr_hw_rev,
+ &dev_attr_fw_ver,
+ &dev_attr_hca_type,
+ &dev_attr_board_id
};
int iwch_register_device(struct iwch_dev *dev)
goto bail1;
for (i = 0; i < ARRAY_SIZE(iwch_class_attributes); ++i) {
- ret = class_device_create_file(&dev->ibdev.class_dev,
- iwch_class_attributes[i]);
+ ret = device_create_file(&dev->ibdev.dev,
+ iwch_class_attributes[i]);
if (ret) {
goto bail2;
}
PDBG("%s iwch_dev %p\n", __func__, dev);
for (i = 0; i < ARRAY_SIZE(iwch_class_attributes); ++i)
- class_device_remove_file(&dev->ibdev.class_dev,
- iwch_class_attributes[i]);
+ device_remove_file(&dev->ibdev.dev,
+ iwch_class_attributes[i]);
ib_unregister_device(&dev->ibdev);
return;
}
config INFINIBAND_IPATH
tristate "QLogic InfiniPath Driver"
- depends on (PCI_MSI || HT_IRQ) && 64BIT && NET
+ depends on 64BIT && NET
---help---
This is a driver for QLogic InfiniPath host channel adapters,
including InfiniBand verbs support. This driver allows these
ipath_user_pages.o \
ipath_user_sdma.o \
ipath_verbs_mcast.o \
- ipath_verbs.o
+ ipath_verbs.o \
+ ipath_iba7220.o \
+ ipath_sd7220.o \
+ ipath_sd7220_img.o
ib_ipath-$(CONFIG_HT_IRQ) += ipath_iba6110.o
ib_ipath-$(CONFIG_PCI_MSI) += ipath_iba6120.o
-ib_ipath-$(CONFIG_PCI_MSI) += ipath_iba7220.o ipath_sd7220.o ipath_sd7220_img.o
ib_ipath-$(CONFIG_X86_64) += ipath_wc_x86_64.o
ib_ipath-$(CONFIG_PPC64) += ipath_wc_ppc64.o
static atomic_t diagpkt_count = ATOMIC_INIT(0);
static struct cdev *diagpkt_cdev;
-static struct class_device *diagpkt_class_dev;
+static struct device *diagpkt_dev;
int ipath_diag_add(struct ipath_devdata *dd)
{
if (atomic_inc_return(&diagpkt_count) == 1) {
ret = ipath_cdev_init(IPATH_DIAGPKT_MINOR,
"ipath_diagpkt", &diagpkt_file_ops,
- &diagpkt_cdev, &diagpkt_class_dev);
+ &diagpkt_cdev, &diagpkt_dev);
if (ret) {
ipath_dev_err(dd, "Couldn't create ipath_diagpkt "
ret = ipath_cdev_init(IPATH_DIAG_MINOR_BASE + dd->ipath_unit, name,
&diag_file_ops, &dd->diag_cdev,
- &dd->diag_class_dev);
+ &dd->diag_dev);
if (ret)
ipath_dev_err(dd, "Couldn't create %s device: %d",
name, ret);
void ipath_diag_remove(struct ipath_devdata *dd)
{
if (atomic_dec_and_test(&diagpkt_count))
- ipath_cdev_cleanup(&diagpkt_cdev, &diagpkt_class_dev);
+ ipath_cdev_cleanup(&diagpkt_cdev, &diagpkt_dev);
- ipath_cdev_cleanup(&dd->diag_cdev, &dd->diag_class_dev);
+ ipath_cdev_cleanup(&dd->diag_cdev, &dd->diag_dev);
}
/**
case PCI_DEVICE_ID_INFINIPATH_7220:
#ifndef CONFIG_PCI_MSI
ipath_dbg("CONFIG_PCI_MSI is not enabled, "
- "using IntX for unit %u\n", dd->ipath_unit);
+ "using INTx for unit %u\n", dd->ipath_unit);
#endif
ipath_init_iba7220_funcs(dd);
break;
static struct class *ipath_class;
static int init_cdev(int minor, char *name, const struct file_operations *fops,
- struct cdev **cdevp, struct class_device **class_devp)
+ struct cdev **cdevp, struct device **devp)
{
const dev_t dev = MKDEV(IPATH_MAJOR, minor);
struct cdev *cdev = NULL;
- struct class_device *class_dev = NULL;
+ struct device *device = NULL;
int ret;
cdev = cdev_alloc();
goto err_cdev;
}
- class_dev = class_device_create(ipath_class, NULL, dev, NULL, name);
+ device = device_create(ipath_class, NULL, dev, name);
- if (IS_ERR(class_dev)) {
- ret = PTR_ERR(class_dev);
+ if (IS_ERR(device)) {
+ ret = PTR_ERR(device);
printk(KERN_ERR IPATH_DRV_NAME ": Could not create "
- "class_dev for minor %d, %s (err %d)\n",
+ "device for minor %d, %s (err %d)\n",
minor, name, -ret);
goto err_cdev;
}
done:
if (ret >= 0) {
*cdevp = cdev;
- *class_devp = class_dev;
+ *devp = device;
} else {
*cdevp = NULL;
- *class_devp = NULL;
+ *devp = NULL;
}
return ret;
}
int ipath_cdev_init(int minor, char *name, const struct file_operations *fops,
- struct cdev **cdevp, struct class_device **class_devp)
+ struct cdev **cdevp, struct device **devp)
{
- return init_cdev(minor, name, fops, cdevp, class_devp);
+ return init_cdev(minor, name, fops, cdevp, devp);
}
static void cleanup_cdev(struct cdev **cdevp,
- struct class_device **class_devp)
+ struct device **devp)
{
- struct class_device *class_dev = *class_devp;
+ struct device *dev = *devp;
- if (class_dev) {
- class_device_unregister(class_dev);
- *class_devp = NULL;
+ if (dev) {
+ device_unregister(dev);
+ *devp = NULL;
}
if (*cdevp) {
}
void ipath_cdev_cleanup(struct cdev **cdevp,
- struct class_device **class_devp)
+ struct device **devp)
{
- cleanup_cdev(cdevp, class_devp);
+ cleanup_cdev(cdevp, devp);
}
static struct cdev *wildcard_cdev;
-static struct class_device *wildcard_class_dev;
+static struct device *wildcard_dev;
static const dev_t dev = MKDEV(IPATH_MAJOR, 0);
goto bail;
}
ret = init_cdev(0, "ipath", &ipath_file_ops, &wildcard_cdev,
- &wildcard_class_dev);
+ &wildcard_dev);
if (ret < 0) {
ipath_dev_err(dd, "Could not create wildcard "
"minor: error %d\n", -ret);
snprintf(name, sizeof(name), "ipath%d", dd->ipath_unit);
ret = init_cdev(dd->ipath_unit + 1, name, &ipath_file_ops,
- &dd->user_cdev, &dd->user_class_dev);
+ &dd->user_cdev, &dd->user_dev);
if (ret < 0)
ipath_dev_err(dd, "Could not create user minor %d, %s\n",
dd->ipath_unit + 1, name);
void ipath_user_remove(struct ipath_devdata *dd)
{
- cleanup_cdev(&dd->user_cdev, &dd->user_class_dev);
+ cleanup_cdev(&dd->user_cdev, &dd->user_dev);
if (atomic_dec_return(&user_count) == 0) {
if (atomic_read(&user_setup) == 0)
goto bail;
- cleanup_cdev(&wildcard_cdev, &wildcard_class_dev);
+ cleanup_cdev(&wildcard_cdev, &wildcard_dev);
user_cleanup();
atomic_set(&user_setup, 0);
/*
* disable msi interrupt if enabled, and clear the flag.
- * flag is used primarily for the fallback to IntX, but
+ * flag is used primarily for the fallback to INTx, but
* is also used in reinit after reset as a flag.
*/
static void ipath_7220_nomsi(struct ipath_devdata *dd)
{
dd->ipath_msi_lo = 0;
-#ifdef CONFIG_PCI_MSI
+
if (ipath_msi_enabled(dd->pcidev)) {
/*
* free, but don't zero; later kernels require
free_irq(dd->ipath_irq, dd);
pci_disable_msi(dd->pcidev);
}
-#endif
}
/*
u32 boardrev;
dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
-#ifdef CONFIG_PCI_MSI
+
pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
if (!strcmp(int_type, "force_msi") || !strcmp(int_type, "auto"))
ret = pci_enable_msi(pdev);
} else
ipath_dev_err(dd, "Can't find MSI capability, "
"can't save MSI settings for reset\n");
-#else
- ipath_dbg("PCI_MSI not configured, using IntX interrupts\n");
- ipath_enable_intx(pdev);
-#endif
dd->ipath_irq = pdev->irq;
static int ipath_reinit_msi(struct ipath_devdata *dd)
{
int ret = 0;
-#ifdef CONFIG_PCI_MSI
+
int pos;
u16 control;
if (!dd->ipath_msi_lo) /* Using intX, or init problem */
((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
dd->ipath_msi_data);
ret = 1;
+
bail:
-#endif
if (!ret) {
- ipath_dbg("Using IntX, MSI disabled or not configured\n");
+ ipath_dbg("Using INTx, MSI disabled or not configured\n");
ipath_enable_intx(dd->pcidev);
ret = 1;
}
counters[i] = ipath_snap_cntr(dd, i);
}
-/* if we are using MSI, try to fallback to IntX */
+/* if we are using MSI, try to fallback to INTx */
static int ipath_7220_intr_fallback(struct ipath_devdata *dd)
{
if (dd->ipath_msi_lo) {
dev_info(&dd->pcidev->dev, "MSI interrupt not detected,"
- " trying IntX interrupts\n");
+ " trying INTx interrupts\n");
ipath_7220_nomsi(dd);
ipath_enable_intx(dd->pcidev);
/*
if (request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
IPATH_DRV_NAME, dd))
ipath_dev_err(dd,
- "Could not re-request_irq for IntX\n");
+ "Could not re-request_irq for INTx\n");
return 1;
}
return 0;
struct pci_dev *pcidev;
struct cdev *user_cdev;
struct cdev *diag_cdev;
- struct class_device *user_class_dev;
- struct class_device *diag_class_dev;
+ struct device *user_dev;
+ struct device *diag_dev;
/* timer used to prevent stats overflow, error throttling, etc. */
struct timer_list ipath_stats_timer;
/* timer to verify interrupts work, and fallback if possible */
struct file_operations;
int ipath_cdev_init(int minor, char *name, const struct file_operations *fops,
- struct cdev **cdevp, struct class_device **class_devp);
+ struct cdev **cdevp, struct device **devp);
void ipath_cdev_cleanup(struct cdev **cdevp,
- struct class_device **class_devp);
+ struct device **devp);
int ipath_diag_add(struct ipath_devdata *);
void ipath_diag_remove(struct ipath_devdata *);
static unsigned int ib_ipath_disable_sma;
module_param_named(disable_sma, ib_ipath_disable_sma, uint, S_IWUSR | S_IRUGO);
-MODULE_PARM_DESC(ib_ipath_disable_sma, "Disable the SMA");
+MODULE_PARM_DESC(disable_sma, "Disable the SMA");
const int ib_ipath_state_ops[IB_QPS_ERR + 1] = {
[IB_QPS_RESET] = 0,
dev->phys_port_cnt = 1;
dev->num_comp_vectors = 1;
dev->dma_device = &dd->pcidev->dev;
- dev->class_dev.dev = dev->dma_device;
dev->query_device = ipath_query_device;
dev->modify_device = ipath_modify_device;
dev->query_port = ipath_query_port;
ib_dealloc_device(ibdev);
}
-static ssize_t show_rev(struct class_device *cdev, char *buf)
+static ssize_t show_rev(struct device *device, struct device_attribute *attr,
+ char *buf)
{
struct ipath_ibdev *dev =
- container_of(cdev, struct ipath_ibdev, ibdev.class_dev);
+ container_of(device, struct ipath_ibdev, ibdev.dev);
return sprintf(buf, "%x\n", dev->dd->ipath_pcirev);
}
-static ssize_t show_hca(struct class_device *cdev, char *buf)
+static ssize_t show_hca(struct device *device, struct device_attribute *attr,
+ char *buf)
{
struct ipath_ibdev *dev =
- container_of(cdev, struct ipath_ibdev, ibdev.class_dev);
+ container_of(device, struct ipath_ibdev, ibdev.dev);
int ret;
ret = dev->dd->ipath_f_get_boardname(dev->dd, buf, 128);
return ret;
}
-static ssize_t show_stats(struct class_device *cdev, char *buf)
+static ssize_t show_stats(struct device *device, struct device_attribute *attr,
+ char *buf)
{
struct ipath_ibdev *dev =
- container_of(cdev, struct ipath_ibdev, ibdev.class_dev);
+ container_of(device, struct ipath_ibdev, ibdev.dev);
int i;
int len;
return len;
}
-static CLASS_DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
-static CLASS_DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
-static CLASS_DEVICE_ATTR(board_id, S_IRUGO, show_hca, NULL);
-static CLASS_DEVICE_ATTR(stats, S_IRUGO, show_stats, NULL);
+static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
+static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
+static DEVICE_ATTR(board_id, S_IRUGO, show_hca, NULL);
+static DEVICE_ATTR(stats, S_IRUGO, show_stats, NULL);
-static struct class_device_attribute *ipath_class_attributes[] = {
- &class_device_attr_hw_rev,
- &class_device_attr_hca_type,
- &class_device_attr_board_id,
- &class_device_attr_stats
+static struct device_attribute *ipath_class_attributes[] = {
+ &dev_attr_hw_rev,
+ &dev_attr_hca_type,
+ &dev_attr_board_id,
+ &dev_attr_stats
};
static int ipath_verbs_register_sysfs(struct ib_device *dev)
int ret;
for (i = 0; i < ARRAY_SIZE(ipath_class_attributes); ++i)
- if (class_device_create_file(&dev->class_dev,
- ipath_class_attributes[i])) {
+ if (device_create_file(&dev->dev,
+ ipath_class_attributes[i])) {
ret = 1;
goto bail;
}
return err;
}
-static ssize_t show_hca(struct class_device *cdev, char *buf)
+static ssize_t show_hca(struct device *device, struct device_attribute *attr,
+ char *buf)
{
- struct mlx4_ib_dev *dev = container_of(cdev, struct mlx4_ib_dev, ib_dev.class_dev);
+ struct mlx4_ib_dev *dev =
+ container_of(device, struct mlx4_ib_dev, ib_dev.dev);
return sprintf(buf, "MT%d\n", dev->dev->pdev->device);
}
-static ssize_t show_fw_ver(struct class_device *cdev, char *buf)
+static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
+ char *buf)
{
- struct mlx4_ib_dev *dev = container_of(cdev, struct mlx4_ib_dev, ib_dev.class_dev);
+ struct mlx4_ib_dev *dev =
+ container_of(device, struct mlx4_ib_dev, ib_dev.dev);
return sprintf(buf, "%d.%d.%d\n", (int) (dev->dev->caps.fw_ver >> 32),
(int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
(int) dev->dev->caps.fw_ver & 0xffff);
}
-static ssize_t show_rev(struct class_device *cdev, char *buf)
+static ssize_t show_rev(struct device *device, struct device_attribute *attr,
+ char *buf)
{
- struct mlx4_ib_dev *dev = container_of(cdev, struct mlx4_ib_dev, ib_dev.class_dev);
+ struct mlx4_ib_dev *dev =
+ container_of(device, struct mlx4_ib_dev, ib_dev.dev);
return sprintf(buf, "%x\n", dev->dev->rev_id);
}
-static ssize_t show_board(struct class_device *cdev, char *buf)
+static ssize_t show_board(struct device *device, struct device_attribute *attr,
+ char *buf)
{
- struct mlx4_ib_dev *dev = container_of(cdev, struct mlx4_ib_dev, ib_dev.class_dev);
- return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, dev->dev->board_id);
+ struct mlx4_ib_dev *dev =
+ container_of(device, struct mlx4_ib_dev, ib_dev.dev);
+ return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
+ dev->dev->board_id);
}
-static CLASS_DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
-static CLASS_DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
-static CLASS_DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
-static CLASS_DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
+static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
+static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
+static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
+static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
-static struct class_device_attribute *mlx4_class_attributes[] = {
- &class_device_attr_hw_rev,
- &class_device_attr_fw_ver,
- &class_device_attr_hca_type,
- &class_device_attr_board_id
+static struct device_attribute *mlx4_class_attributes[] = {
+ &dev_attr_hw_rev,
+ &dev_attr_fw_ver,
+ &dev_attr_hca_type,
+ &dev_attr_board_id
};
static void *mlx4_ib_add(struct mlx4_dev *dev)
goto err_reg;
for (i = 0; i < ARRAY_SIZE(mlx4_class_attributes); ++i) {
- if (class_device_create_file(&ibdev->ib_dev.class_dev,
- mlx4_class_attributes[i]))
+ if (device_create_file(&ibdev->ib_dev.dev,
+ mlx4_class_attributes[i]))
goto err_reg;
}
#include <linux/timer.h>
#include <linux/mutex.h>
#include <linux/list.h>
-
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include "mthca_provider.h"
#include "mthca_doorbell.h"
return 0;
}
-static ssize_t show_rev(struct class_device *cdev, char *buf)
+static ssize_t show_rev(struct device *device, struct device_attribute *attr,
+ char *buf)
{
- struct mthca_dev *dev = container_of(cdev, struct mthca_dev, ib_dev.class_dev);
+ struct mthca_dev *dev =
+ container_of(device, struct mthca_dev, ib_dev.dev);
return sprintf(buf, "%x\n", dev->rev_id);
}
-static ssize_t show_fw_ver(struct class_device *cdev, char *buf)
+static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
+ char *buf)
{
- struct mthca_dev *dev = container_of(cdev, struct mthca_dev, ib_dev.class_dev);
+ struct mthca_dev *dev =
+ container_of(device, struct mthca_dev, ib_dev.dev);
return sprintf(buf, "%d.%d.%d\n", (int) (dev->fw_ver >> 32),
(int) (dev->fw_ver >> 16) & 0xffff,
(int) dev->fw_ver & 0xffff);
}
-static ssize_t show_hca(struct class_device *cdev, char *buf)
+static ssize_t show_hca(struct device *device, struct device_attribute *attr,
+ char *buf)
{
- struct mthca_dev *dev = container_of(cdev, struct mthca_dev, ib_dev.class_dev);
+ struct mthca_dev *dev =
+ container_of(device, struct mthca_dev, ib_dev.dev);
switch (dev->pdev->device) {
case PCI_DEVICE_ID_MELLANOX_TAVOR:
return sprintf(buf, "MT23108\n");
}
}
-static ssize_t show_board(struct class_device *cdev, char *buf)
+static ssize_t show_board(struct device *device, struct device_attribute *attr,
+ char *buf)
{
- struct mthca_dev *dev = container_of(cdev, struct mthca_dev, ib_dev.class_dev);
+ struct mthca_dev *dev =
+ container_of(device, struct mthca_dev, ib_dev.dev);
return sprintf(buf, "%.*s\n", MTHCA_BOARD_ID_LEN, dev->board_id);
}
-static CLASS_DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
-static CLASS_DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
-static CLASS_DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
-static CLASS_DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
+static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
+static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
+static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
+static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
-static struct class_device_attribute *mthca_class_attributes[] = {
- &class_device_attr_hw_rev,
- &class_device_attr_fw_ver,
- &class_device_attr_hca_type,
- &class_device_attr_board_id
+static struct device_attribute *mthca_dev_attributes[] = {
+ &dev_attr_hw_rev,
+ &dev_attr_fw_ver,
+ &dev_attr_hca_type,
+ &dev_attr_board_id
};
static int mthca_init_node_data(struct mthca_dev *dev)
if (ret)
return ret;
- for (i = 0; i < ARRAY_SIZE(mthca_class_attributes); ++i) {
- ret = class_device_create_file(&dev->ib_dev.class_dev,
- mthca_class_attributes[i]);
+ for (i = 0; i < ARRAY_SIZE(mthca_dev_attributes); ++i) {
+ ret = device_create_file(&dev->ib_dev.dev,
+ mthca_dev_attributes[i]);
if (ret) {
ib_unregister_device(&dev->ib_dev);
return ret;
atomic_t qps_destroyed;
-static void nes_print_macaddr(struct net_device *netdev);
-static irqreturn_t nes_interrupt(int, void *);
-static int __devinit nes_probe(struct pci_dev *, const struct pci_device_id *);
-static void __devexit nes_remove(struct pci_dev *);
-static int __init nes_init_module(void);
-static void __exit nes_exit_module(void);
static unsigned int ee_flsh_adapter;
static unsigned int sysfs_nonidx_addr;
static unsigned int sysfs_idx_addr;
#include <linux/dma-mapping.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
-#include <asm/semaphore.h>
#include <linux/version.h>
#include <asm/io.h>
#include <linux/crc32c.h>
| NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
static int debug = -1;
-
-static int nes_netdev_open(struct net_device *);
-static int nes_netdev_stop(struct net_device *);
-static int nes_netdev_start_xmit(struct sk_buff *, struct net_device *);
-static struct net_device_stats *nes_netdev_get_stats(struct net_device *);
-static void nes_netdev_tx_timeout(struct net_device *);
-static int nes_netdev_set_mac_address(struct net_device *, void *);
-static int nes_netdev_change_mtu(struct net_device *, int);
-
/**
* nes_netdev_poll
*/
/**
* show_rev
*/
-static ssize_t show_rev(struct class_device *cdev, char *buf)
+static ssize_t show_rev(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
struct nes_ib_device *nesibdev =
- container_of(cdev, struct nes_ib_device, ibdev.class_dev);
+ container_of(dev, struct nes_ib_device, ibdev.dev);
struct nes_vnic *nesvnic = nesibdev->nesvnic;
nes_debug(NES_DBG_INIT, "\n");
/**
* show_fw_ver
*/
-static ssize_t show_fw_ver(struct class_device *cdev, char *buf)
+static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
struct nes_ib_device *nesibdev =
- container_of(cdev, struct nes_ib_device, ibdev.class_dev);
+ container_of(dev, struct nes_ib_device, ibdev.dev);
struct nes_vnic *nesvnic = nesibdev->nesvnic;
nes_debug(NES_DBG_INIT, "\n");
/**
* show_hca
*/
-static ssize_t show_hca(struct class_device *cdev, char *buf)
+static ssize_t show_hca(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
nes_debug(NES_DBG_INIT, "\n");
return sprintf(buf, "NES020\n");
/**
* show_board
*/
-static ssize_t show_board(struct class_device *cdev, char *buf)
+static ssize_t show_board(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
nes_debug(NES_DBG_INIT, "\n");
return sprintf(buf, "%.*s\n", 32, "NES020 Board ID");
}
-static CLASS_DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
-static CLASS_DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
-static CLASS_DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
-static CLASS_DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
+static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
+static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
+static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
+static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
-static struct class_device_attribute *nes_class_attributes[] = {
- &class_device_attr_hw_rev,
- &class_device_attr_fw_ver,
- &class_device_attr_hca_type,
- &class_device_attr_board_id
+static struct device_attribute *nes_dev_attributes[] = {
+ &dev_attr_hw_rev,
+ &dev_attr_fw_ver,
+ &dev_attr_hca_type,
+ &dev_attr_board_id
};
nesibdev->ibdev.phys_port_cnt = 1;
nesibdev->ibdev.num_comp_vectors = 1;
nesibdev->ibdev.dma_device = &nesdev->pcidev->dev;
- nesibdev->ibdev.class_dev.dev = &nesdev->pcidev->dev;
+ nesibdev->ibdev.dev.parent = &nesdev->pcidev->dev;
nesibdev->ibdev.query_device = nes_query_device;
nesibdev->ibdev.query_port = nes_query_port;
nesibdev->ibdev.modify_port = nes_modify_port;
nesibdev->max_qp = (nesadapter->max_qp-NES_FIRST_QPN) / nesadapter->port_count;
nesibdev->max_pd = nesadapter->max_pd / nesadapter->port_count;
- for (i = 0; i < ARRAY_SIZE(nes_class_attributes); ++i) {
- ret = class_device_create_file(&nesibdev->ibdev.class_dev, nes_class_attributes[i]);
+ for (i = 0; i < ARRAY_SIZE(nes_dev_attributes); ++i) {
+ ret = device_create_file(&nesibdev->ibdev.dev, nes_dev_attributes[i]);
if (ret) {
while (i > 0) {
i--;
- class_device_remove_file(&nesibdev->ibdev.class_dev,
- nes_class_attributes[i]);
+ device_remove_file(&nesibdev->ibdev.dev,
+ nes_dev_attributes[i]);
}
ib_unregister_device(&nesibdev->ibdev);
return ret;
struct nes_vnic *nesvnic = nesibdev->nesvnic;
int i;
- for (i = 0; i < ARRAY_SIZE(nes_class_attributes); ++i) {
- class_device_remove_file(&nesibdev->ibdev.class_dev, nes_class_attributes[i]);
+ for (i = 0; i < ARRAY_SIZE(nes_dev_attributes); ++i) {
+ device_remove_file(&nesibdev->ibdev.dev, nes_dev_attributes[i]);
}
if (nesvnic->of_device_registered) {
if (!iu->buf)
goto out_free_iu;
- iu->dma = ib_dma_map_single(host->dev->dev, iu->buf, size, direction);
- if (ib_dma_mapping_error(host->dev->dev, iu->dma))
+ iu->dma = ib_dma_map_single(host->srp_dev->dev, iu->buf, size,
+ direction);
+ if (ib_dma_mapping_error(host->srp_dev->dev, iu->dma))
goto out_free_buf;
iu->size = size;
if (!iu)
return;
- ib_dma_unmap_single(host->dev->dev, iu->dma, iu->size, iu->direction);
+ ib_dma_unmap_single(host->srp_dev->dev, iu->dma, iu->size,
+ iu->direction);
kfree(iu->buf);
kfree(iu);
}
if (!attr)
return -ENOMEM;
- ret = ib_find_cached_pkey(target->srp_host->dev->dev,
+ ret = ib_find_cached_pkey(target->srp_host->srp_dev->dev,
target->srp_host->port,
be16_to_cpu(target->path.pkey),
&attr->pkey_index);
{
struct ib_cm_id *new_cm_id;
- new_cm_id = ib_create_cm_id(target->srp_host->dev->dev,
+ new_cm_id = ib_create_cm_id(target->srp_host->srp_dev->dev,
srp_cm_handler, target);
if (IS_ERR(new_cm_id))
return PTR_ERR(new_cm_id);
if (!init_attr)
return -ENOMEM;
- target->cq = ib_create_cq(target->srp_host->dev->dev, srp_completion,
- NULL, target, SRP_CQ_SIZE, 0);
+ target->cq = ib_create_cq(target->srp_host->srp_dev->dev,
+ srp_completion, NULL, target, SRP_CQ_SIZE, 0);
if (IS_ERR(target->cq)) {
ret = PTR_ERR(target->cq);
goto out;
init_attr->send_cq = target->cq;
init_attr->recv_cq = target->cq;
- target->qp = ib_create_qp(target->srp_host->dev->pd, init_attr);
+ target->qp = ib_create_qp(target->srp_host->srp_dev->pd, init_attr);
if (IS_ERR(target->qp)) {
ret = PTR_ERR(target->qp);
ib_destroy_cq(target->cq);
init_completion(&target->done);
target->path_query_id = ib_sa_path_rec_get(&srp_sa_client,
- target->srp_host->dev->dev,
+ target->srp_host->srp_dev->dev,
target->srp_host->port,
&target->path,
IB_SA_PATH_REC_SERVICE_ID |
(unsigned long long) be64_to_cpu(target->ioc_guid));
memset(req->priv.initiator_port_id, 0, 8);
memcpy(req->priv.initiator_port_id + 8,
- &target->srp_host->dev->dev->node_guid, 8);
+ &target->srp_host->srp_dev->dev->node_guid, 8);
}
status = ib_send_cm_req(target->cm_id, &req->param);
req->fmr = NULL;
}
- ib_dma_unmap_sg(target->srp_host->dev->dev, scsi_sglist(scmnd),
+ ib_dma_unmap_sg(target->srp_host->srp_dev->dev, scsi_sglist(scmnd),
scsi_sg_count(scmnd), scmnd->sc_data_direction);
}
int page_cnt;
int i, j;
int ret;
- struct srp_device *dev = target->srp_host->dev;
+ struct srp_device *dev = target->srp_host->srp_dev;
struct ib_device *ibdev = dev->dev;
struct scatterlist *sg;
nents = scsi_sg_count(scmnd);
scat = scsi_sglist(scmnd);
- dev = target->srp_host->dev;
+ dev = target->srp_host->srp_dev;
ibdev = dev->dev;
count = ib_dma_map_sg(ibdev, scat, nents, scmnd->sc_data_direction);
buf->table_desc.va =
cpu_to_be64(req->cmd->dma + sizeof *cmd + sizeof *buf);
buf->table_desc.key =
- cpu_to_be32(target->srp_host->dev->mr->rkey);
+ cpu_to_be32(target->srp_host->srp_dev->mr->rkey);
buf->table_desc.len =
cpu_to_be32(count * sizeof (struct srp_direct_buf));
iu = target->rx_ring[wc->wr_id & ~SRP_OP_RECV];
- dev = target->srp_host->dev->dev;
+ dev = target->srp_host->srp_dev->dev;
ib_dma_sync_single_for_cpu(dev, iu->dma, target->max_ti_iu_len,
DMA_FROM_DEVICE);
list.addr = iu->dma;
list.length = iu->size;
- list.lkey = target->srp_host->dev->mr->lkey;
+ list.lkey = target->srp_host->srp_dev->mr->lkey;
wr.next = NULL;
wr.sg_list = &list;
list.addr = iu->dma;
list.length = len;
- list.lkey = target->srp_host->dev->mr->lkey;
+ list.lkey = target->srp_host->srp_dev->mr->lkey;
wr.next = NULL;
wr.wr_id = target->tx_head & SRP_SQ_SIZE;
if (!iu)
goto err;
- dev = target->srp_host->dev->dev;
+ dev = target->srp_host->srp_dev->dev;
ib_dma_sync_single_for_cpu(dev, iu->dma, srp_max_iu_len,
DMA_TO_DEVICE);
return ret;
}
-static ssize_t show_id_ext(struct class_device *cdev, char *buf)
+static ssize_t show_id_ext(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct srp_target_port *target = host_to_target(class_to_shost(cdev));
+ struct srp_target_port *target = host_to_target(class_to_shost(dev));
if (target->state == SRP_TARGET_DEAD ||
target->state == SRP_TARGET_REMOVED)
(unsigned long long) be64_to_cpu(target->id_ext));
}
-static ssize_t show_ioc_guid(struct class_device *cdev, char *buf)
+static ssize_t show_ioc_guid(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct srp_target_port *target = host_to_target(class_to_shost(cdev));
+ struct srp_target_port *target = host_to_target(class_to_shost(dev));
if (target->state == SRP_TARGET_DEAD ||
target->state == SRP_TARGET_REMOVED)
(unsigned long long) be64_to_cpu(target->ioc_guid));
}
-static ssize_t show_service_id(struct class_device *cdev, char *buf)
+static ssize_t show_service_id(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct srp_target_port *target = host_to_target(class_to_shost(cdev));
+ struct srp_target_port *target = host_to_target(class_to_shost(dev));
if (target->state == SRP_TARGET_DEAD ||
target->state == SRP_TARGET_REMOVED)
(unsigned long long) be64_to_cpu(target->service_id));
}
-static ssize_t show_pkey(struct class_device *cdev, char *buf)
+static ssize_t show_pkey(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct srp_target_port *target = host_to_target(class_to_shost(cdev));
+ struct srp_target_port *target = host_to_target(class_to_shost(dev));
if (target->state == SRP_TARGET_DEAD ||
target->state == SRP_TARGET_REMOVED)
return sprintf(buf, "0x%04x\n", be16_to_cpu(target->path.pkey));
}
-static ssize_t show_dgid(struct class_device *cdev, char *buf)
+static ssize_t show_dgid(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct srp_target_port *target = host_to_target(class_to_shost(cdev));
+ struct srp_target_port *target = host_to_target(class_to_shost(dev));
if (target->state == SRP_TARGET_DEAD ||
target->state == SRP_TARGET_REMOVED)
be16_to_cpu(((__be16 *) target->path.dgid.raw)[7]));
}
-static ssize_t show_orig_dgid(struct class_device *cdev, char *buf)
+static ssize_t show_orig_dgid(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct srp_target_port *target = host_to_target(class_to_shost(cdev));
+ struct srp_target_port *target = host_to_target(class_to_shost(dev));
if (target->state == SRP_TARGET_DEAD ||
target->state == SRP_TARGET_REMOVED)
be16_to_cpu(target->orig_dgid[7]));
}
-static ssize_t show_zero_req_lim(struct class_device *cdev, char *buf)
+static ssize_t show_zero_req_lim(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct srp_target_port *target = host_to_target(class_to_shost(cdev));
+ struct srp_target_port *target = host_to_target(class_to_shost(dev));
if (target->state == SRP_TARGET_DEAD ||
target->state == SRP_TARGET_REMOVED)
return sprintf(buf, "%d\n", target->zero_req_lim);
}
-static ssize_t show_local_ib_port(struct class_device *cdev, char *buf)
+static ssize_t show_local_ib_port(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct srp_target_port *target = host_to_target(class_to_shost(cdev));
+ struct srp_target_port *target = host_to_target(class_to_shost(dev));
return sprintf(buf, "%d\n", target->srp_host->port);
}
-static ssize_t show_local_ib_device(struct class_device *cdev, char *buf)
+static ssize_t show_local_ib_device(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct srp_target_port *target = host_to_target(class_to_shost(cdev));
+ struct srp_target_port *target = host_to_target(class_to_shost(dev));
- return sprintf(buf, "%s\n", target->srp_host->dev->dev->name);
+ return sprintf(buf, "%s\n", target->srp_host->srp_dev->dev->name);
}
-static CLASS_DEVICE_ATTR(id_ext, S_IRUGO, show_id_ext, NULL);
-static CLASS_DEVICE_ATTR(ioc_guid, S_IRUGO, show_ioc_guid, NULL);
-static CLASS_DEVICE_ATTR(service_id, S_IRUGO, show_service_id, NULL);
-static CLASS_DEVICE_ATTR(pkey, S_IRUGO, show_pkey, NULL);
-static CLASS_DEVICE_ATTR(dgid, S_IRUGO, show_dgid, NULL);
-static CLASS_DEVICE_ATTR(orig_dgid, S_IRUGO, show_orig_dgid, NULL);
-static CLASS_DEVICE_ATTR(zero_req_lim, S_IRUGO, show_zero_req_lim, NULL);
-static CLASS_DEVICE_ATTR(local_ib_port, S_IRUGO, show_local_ib_port, NULL);
-static CLASS_DEVICE_ATTR(local_ib_device, S_IRUGO, show_local_ib_device, NULL);
-
-static struct class_device_attribute *srp_host_attrs[] = {
- &class_device_attr_id_ext,
- &class_device_attr_ioc_guid,
- &class_device_attr_service_id,
- &class_device_attr_pkey,
- &class_device_attr_dgid,
- &class_device_attr_orig_dgid,
- &class_device_attr_zero_req_lim,
- &class_device_attr_local_ib_port,
- &class_device_attr_local_ib_device,
+static DEVICE_ATTR(id_ext, S_IRUGO, show_id_ext, NULL);
+static DEVICE_ATTR(ioc_guid, S_IRUGO, show_ioc_guid, NULL);
+static DEVICE_ATTR(service_id, S_IRUGO, show_service_id, NULL);
+static DEVICE_ATTR(pkey, S_IRUGO, show_pkey, NULL);
+static DEVICE_ATTR(dgid, S_IRUGO, show_dgid, NULL);
+static DEVICE_ATTR(orig_dgid, S_IRUGO, show_orig_dgid, NULL);
+static DEVICE_ATTR(zero_req_lim, S_IRUGO, show_zero_req_lim, NULL);
+static DEVICE_ATTR(local_ib_port, S_IRUGO, show_local_ib_port, NULL);
+static DEVICE_ATTR(local_ib_device, S_IRUGO, show_local_ib_device, NULL);
+
+static struct device_attribute *srp_host_attrs[] = {
+ &dev_attr_id_ext,
+ &dev_attr_ioc_guid,
+ &dev_attr_service_id,
+ &dev_attr_pkey,
+ &dev_attr_dgid,
+ &dev_attr_orig_dgid,
+ &dev_attr_zero_req_lim,
+ &dev_attr_local_ib_port,
+ &dev_attr_local_ib_device,
NULL
};
sprintf(target->target_name, "SRP.T10:%016llX",
(unsigned long long) be64_to_cpu(target->id_ext));
- if (scsi_add_host(target->scsi_host, host->dev->dev->dma_device))
+ if (scsi_add_host(target->scsi_host, host->srp_dev->dev->dma_device))
return -ENODEV;
memcpy(ids.port_id, &target->id_ext, 8);
return 0;
}
-static void srp_release_class_dev(struct class_device *class_dev)
+static void srp_release_dev(struct device *dev)
{
struct srp_host *host =
- container_of(class_dev, struct srp_host, class_dev);
+ container_of(dev, struct srp_host, dev);
complete(&host->released);
}
static struct class srp_class = {
.name = "infiniband_srp",
- .release = srp_release_class_dev
+ .dev_release = srp_release_dev
};
/*
return ret;
}
-static ssize_t srp_create_target(struct class_device *class_dev,
+static ssize_t srp_create_target(struct device *dev,
+ struct device_attribute *attr,
const char *buf, size_t count)
{
struct srp_host *host =
- container_of(class_dev, struct srp_host, class_dev);
+ container_of(dev, struct srp_host, dev);
struct Scsi_Host *target_host;
struct srp_target_port *target;
int ret;
if (ret)
goto err;
- ib_get_cached_gid(host->dev->dev, host->port, 0, &target->path.sgid);
+ ib_get_cached_gid(host->srp_dev->dev, host->port, 0,
+ &target->path.sgid);
shost_printk(KERN_DEBUG, target->scsi_host, PFX
"new target: id_ext %016llx ioc_guid %016llx pkey %04x "
return ret;
}
-static CLASS_DEVICE_ATTR(add_target, S_IWUSR, NULL, srp_create_target);
+static DEVICE_ATTR(add_target, S_IWUSR, NULL, srp_create_target);
-static ssize_t show_ibdev(struct class_device *class_dev, char *buf)
+static ssize_t show_ibdev(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct srp_host *host =
- container_of(class_dev, struct srp_host, class_dev);
+ struct srp_host *host = container_of(dev, struct srp_host, dev);
- return sprintf(buf, "%s\n", host->dev->dev->name);
+ return sprintf(buf, "%s\n", host->srp_dev->dev->name);
}
-static CLASS_DEVICE_ATTR(ibdev, S_IRUGO, show_ibdev, NULL);
+static DEVICE_ATTR(ibdev, S_IRUGO, show_ibdev, NULL);
-static ssize_t show_port(struct class_device *class_dev, char *buf)
+static ssize_t show_port(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct srp_host *host =
- container_of(class_dev, struct srp_host, class_dev);
+ struct srp_host *host = container_of(dev, struct srp_host, dev);
return sprintf(buf, "%d\n", host->port);
}
-static CLASS_DEVICE_ATTR(port, S_IRUGO, show_port, NULL);
+static DEVICE_ATTR(port, S_IRUGO, show_port, NULL);
static struct srp_host *srp_add_port(struct srp_device *device, u8 port)
{
INIT_LIST_HEAD(&host->target_list);
spin_lock_init(&host->target_lock);
init_completion(&host->released);
- host->dev = device;
+ host->srp_dev = device;
host->port = port;
- host->class_dev.class = &srp_class;
- host->class_dev.dev = device->dev->dma_device;
- snprintf(host->class_dev.class_id, BUS_ID_SIZE, "srp-%s-%d",
+ host->dev.class = &srp_class;
+ host->dev.parent = device->dev->dma_device;
+ snprintf(host->dev.bus_id, BUS_ID_SIZE, "srp-%s-%d",
device->dev->name, port);
- if (class_device_register(&host->class_dev))
+ if (device_register(&host->dev))
goto free_host;
- if (class_device_create_file(&host->class_dev, &class_device_attr_add_target))
+ if (device_create_file(&host->dev, &dev_attr_add_target))
goto err_class;
- if (class_device_create_file(&host->class_dev, &class_device_attr_ibdev))
+ if (device_create_file(&host->dev, &dev_attr_ibdev))
goto err_class;
- if (class_device_create_file(&host->class_dev, &class_device_attr_port))
+ if (device_create_file(&host->dev, &dev_attr_port))
goto err_class;
return host;
err_class:
- class_device_unregister(&host->class_dev);
+ device_unregister(&host->dev);
free_host:
kfree(host);
srp_dev = ib_get_client_data(device, &srp_client);
list_for_each_entry_safe(host, tmp_host, &srp_dev->dev_list, list) {
- class_device_unregister(&host->class_dev);
+ device_unregister(&host->dev);
/*
* Wait for the sysfs entry to go away, so that no new
* target ports can be created.
};
struct srp_host {
- struct srp_device *dev;
+ struct srp_device *srp_dev;
u8 port;
- struct class_device class_dev;
+ struct device dev;
struct list_head target_list;
spinlock_t target_lock;
struct completion released;
To compile this driver as a module, choose M here: the
module will be called bf54x-keys.
+config KEYBOARD_SH_KEYSC
+ tristate "SuperH KEYSC keypad support"
+ depends on SUPERH
+ help
+ Say Y here if you want to use a keypad attached to the KEYSC block
+ on SuperH processors such as sh7722 and sh7343.
+
+ To compile this driver as a module, choose M here: the
+ module will be called sh_keysc.
endif
obj-$(CONFIG_KEYBOARD_HP7XX) += jornada720_kbd.o
obj-$(CONFIG_KEYBOARD_MAPLE) += maple_keyb.o
obj-$(CONFIG_KEYBOARD_BFIN) += bf54x-keys.o
+obj-$(CONFIG_KEYBOARD_SH_KEYSC) += sh_keysc.o
#include <asm/arch/corgi.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/hardware/scoop.h>
#define KB_ROWS 8
--- /dev/null
+/*
+ * SuperH KEYSC Keypad Driver
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * Based on gpio_keys.c, Copyright 2005 Phil Blundell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <asm/sh_keysc.h>
+
+#define KYCR1_OFFS 0x00
+#define KYCR2_OFFS 0x04
+#define KYINDR_OFFS 0x08
+#define KYOUTDR_OFFS 0x0c
+
+#define KYCR2_IRQ_LEVEL 0x10
+#define KYCR2_IRQ_DISABLED 0x00
+
+static const struct {
+ unsigned char kymd, keyout, keyin;
+} sh_keysc_mode[] = {
+ [SH_KEYSC_MODE_1] = { 0, 6, 5 },
+ [SH_KEYSC_MODE_2] = { 1, 5, 6 },
+ [SH_KEYSC_MODE_3] = { 2, 4, 7 },
+};
+
+struct sh_keysc_priv {
+ void __iomem *iomem_base;
+ unsigned long last_keys;
+ struct input_dev *input;
+ struct sh_keysc_info pdata;
+};
+
+static irqreturn_t sh_keysc_isr(int irq, void *dev_id)
+{
+ struct platform_device *pdev = dev_id;
+ struct sh_keysc_priv *priv = platform_get_drvdata(pdev);
+ struct sh_keysc_info *pdata = &priv->pdata;
+ unsigned long keys, keys1, keys0, mask;
+ unsigned char keyin_set, tmp;
+ int i, k;
+
+ dev_dbg(&pdev->dev, "isr!\n");
+
+ keys1 = ~0;
+ keys0 = 0;
+
+ do {
+ keys = 0;
+ keyin_set = 0;
+
+ iowrite16(KYCR2_IRQ_DISABLED, priv->iomem_base + KYCR2_OFFS);
+
+ for (i = 0; i < sh_keysc_mode[pdata->mode].keyout; i++) {
+ iowrite16(0xfff ^ (3 << (i * 2)),
+ priv->iomem_base + KYOUTDR_OFFS);
+ udelay(pdata->delay);
+ tmp = ioread16(priv->iomem_base + KYINDR_OFFS);
+ keys |= tmp << (sh_keysc_mode[pdata->mode].keyin * i);
+ tmp ^= (1 << sh_keysc_mode[pdata->mode].keyin) - 1;
+ keyin_set |= tmp;
+ }
+
+ iowrite16(0, priv->iomem_base + KYOUTDR_OFFS);
+ iowrite16(KYCR2_IRQ_LEVEL | (keyin_set << 8),
+ priv->iomem_base + KYCR2_OFFS);
+
+ keys ^= ~0;
+ keys &= (1 << (sh_keysc_mode[pdata->mode].keyin *
+ sh_keysc_mode[pdata->mode].keyout)) - 1;
+ keys1 &= keys;
+ keys0 |= keys;
+
+ dev_dbg(&pdev->dev, "keys 0x%08lx\n", keys);
+
+ } while (ioread16(priv->iomem_base + KYCR2_OFFS) & 0x01);
+
+ dev_dbg(&pdev->dev, "last_keys 0x%08lx keys0 0x%08lx keys1 0x%08lx\n",
+ priv->last_keys, keys0, keys1);
+
+ for (i = 0; i < SH_KEYSC_MAXKEYS; i++) {
+ k = pdata->keycodes[i];
+ if (!k)
+ continue;
+
+ mask = 1 << i;
+
+ if (!((priv->last_keys ^ keys0) & mask))
+ continue;
+
+ if ((keys1 | keys0) & mask) {
+ input_event(priv->input, EV_KEY, k, 1);
+ priv->last_keys |= mask;
+ }
+
+ if (!(keys1 & mask)) {
+ input_event(priv->input, EV_KEY, k, 0);
+ priv->last_keys &= ~mask;
+ }
+
+ }
+ input_sync(priv->input);
+
+ return IRQ_HANDLED;
+}
+
+#define res_size(res) ((res)->end - (res)->start + 1)
+
+static int __devinit sh_keysc_probe(struct platform_device *pdev)
+{
+ struct sh_keysc_priv *priv;
+ struct sh_keysc_info *pdata;
+ struct resource *res;
+ struct input_dev *input;
+ int i, k;
+ int irq, error;
+
+ if (!pdev->dev.platform_data) {
+ dev_err(&pdev->dev, "no platform data defined\n");
+ error = -EINVAL;
+ goto err0;
+ }
+
+ error = -ENXIO;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "failed to get I/O memory\n");
+ goto err0;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "failed to get irq\n");
+ goto err0;
+ }
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (priv == NULL) {
+ dev_err(&pdev->dev, "failed to allocate driver data\n");
+ error = -ENOMEM;
+ goto err0;
+ }
+
+ platform_set_drvdata(pdev, priv);
+ memcpy(&priv->pdata, pdev->dev.platform_data, sizeof(priv->pdata));
+ pdata = &priv->pdata;
+
+ res = request_mem_region(res->start, res_size(res), pdev->name);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "failed to request I/O memory\n");
+ error = -EBUSY;
+ goto err1;
+ }
+
+ priv->iomem_base = ioremap_nocache(res->start, res_size(res));
+ if (priv->iomem_base == NULL) {
+ dev_err(&pdev->dev, "failed to remap I/O memory\n");
+ error = -ENXIO;
+ goto err2;
+ }
+
+ priv->input = input_allocate_device();
+ if (!priv->input) {
+ dev_err(&pdev->dev, "failed to allocate input device\n");
+ error = -ENOMEM;
+ goto err3;
+ }
+
+ input = priv->input;
+ input->evbit[0] = BIT_MASK(EV_KEY);
+
+ input->name = pdev->name;
+ input->phys = "sh-keysc-keys/input0";
+ input->dev.parent = &pdev->dev;
+
+ input->id.bustype = BUS_HOST;
+ input->id.vendor = 0x0001;
+ input->id.product = 0x0001;
+ input->id.version = 0x0100;
+
+ error = request_irq(irq, sh_keysc_isr, 0, pdev->name, pdev);
+ if (error) {
+ dev_err(&pdev->dev, "failed to request IRQ\n");
+ goto err4;
+ }
+
+ for (i = 0; i < SH_KEYSC_MAXKEYS; i++) {
+ k = pdata->keycodes[i];
+ if (k)
+ input_set_capability(input, EV_KEY, k);
+ }
+
+ error = input_register_device(input);
+ if (error) {
+ dev_err(&pdev->dev, "failed to register input device\n");
+ goto err5;
+ }
+
+ iowrite16((sh_keysc_mode[pdata->mode].kymd << 8) |
+ pdata->scan_timing, priv->iomem_base + KYCR1_OFFS);
+ iowrite16(0, priv->iomem_base + KYOUTDR_OFFS);
+ iowrite16(KYCR2_IRQ_LEVEL, priv->iomem_base + KYCR2_OFFS);
+ return 0;
+ err5:
+ free_irq(irq, pdev);
+ err4:
+ input_free_device(input);
+ err3:
+ iounmap(priv->iomem_base);
+ err2:
+ release_mem_region(res->start, res_size(res));
+ err1:
+ platform_set_drvdata(pdev, NULL);
+ kfree(priv);
+ err0:
+ return error;
+}
+
+static int __devexit sh_keysc_remove(struct platform_device *pdev)
+{
+ struct sh_keysc_priv *priv = platform_get_drvdata(pdev);
+ struct resource *res;
+
+ iowrite16(KYCR2_IRQ_DISABLED, priv->iomem_base + KYCR2_OFFS);
+
+ input_unregister_device(priv->input);
+ free_irq(platform_get_irq(pdev, 0), pdev);
+ iounmap(priv->iomem_base);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(res->start, res_size(res));
+
+ platform_set_drvdata(pdev, NULL);
+ kfree(priv);
+ return 0;
+}
+
+
+#define sh_keysc_suspend NULL
+#define sh_keysc_resume NULL
+
+struct platform_driver sh_keysc_device_driver = {
+ .probe = sh_keysc_probe,
+ .remove = __devexit_p(sh_keysc_remove),
+ .suspend = sh_keysc_suspend,
+ .resume = sh_keysc_resume,
+ .driver = {
+ .name = "sh_keysc",
+ }
+};
+
+static int __init sh_keysc_init(void)
+{
+ return platform_driver_register(&sh_keysc_device_driver);
+}
+
+static void __exit sh_keysc_exit(void)
+{
+ platform_driver_unregister(&sh_keysc_device_driver);
+}
+
+module_init(sh_keysc_init);
+module_exit(sh_keysc_exit);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("SuperH KEYSC Keypad Driver");
+MODULE_LICENSE("GPL");
#include <asm/arch/spitz.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#define KB_ROWS 7
#define KB_COLS 11
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#define PREFIX "HP SDC MLC: "
#include <linux/spi/ads7846.h>
#include <asm/irq.h>
-#ifdef CONFIG_ARM
-#include <asm/mach-types.h>
-#ifdef CONFIG_ARCH_OMAP
-#include <asm/arch/gpio.h>
-#endif
-#endif
-
/*
* This code has been heavily tested on a Nokia 770, and lightly
static int __init ads7846_init(void)
{
- /* grr, board-specific init should stay out of drivers!! */
-
-#ifdef CONFIG_ARCH_OMAP
- if (machine_is_omap_osk()) {
- /* GPIO4 = PENIRQ; GPIO6 = BUSY */
- omap_request_gpio(4);
- omap_set_gpio_direction(4, 1);
- omap_request_gpio(6);
- omap_set_gpio_direction(6, 1);
- }
- // also TI 1510 Innovator, bitbanging through FPGA
- // also Nokia 770
- // also Palm Tungsten T2
-#endif
-
- // PXA:
- // also Dell Axim X50
- // also HP iPaq H191x/H192x/H415x/H435x
- // also Intel Lubbock (additional to UCB1400; as temperature sensor)
- // also Sharp Zaurus C7xx, C8xx (corgi/sheperd/husky)
-
- // Atmel at91sam9261-EK uses ads7843
-
- // also various AMD Au1x00 devel boards
-
return spi_register_driver(&ads7846_driver);
}
module_init(ads7846_init);
static void __exit ads7846_exit(void)
{
spi_unregister_driver(&ads7846_driver);
-
-#ifdef CONFIG_ARCH_OMAP
- if (machine_is_omap_osk()) {
- omap_free_gpio(4);
- omap_free_gpio(6);
- }
-#endif
-
}
module_exit(ads7846_exit);
#include <asm/arch/sharpsl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#define PWR_MODE_ACTIVE 0
#include "hscx.h"
#include "isdnl1.h"
-extern const char *CardType[];
-
static const char *Asuscom_revision = "$Revision: 1.14.2.4 $";
#define byteout(addr,val) outb(val,addr)
cs->irq = card->para[0];
if (!request_region(cs->hw.asus.cfg_reg, bytecnt, "asuscom isdn")) {
printk(KERN_WARNING
- "HiSax: %s config port %x-%x already in use\n",
- CardType[card->typ],
+ "HiSax: ISDNLink config port %x-%x already in use\n",
cs->hw.asus.cfg_reg,
cs->hw.asus.cfg_reg + bytecnt);
return (0);
#include "hscx.h"
#include "isdnl1.h"
-extern const char *CardType[];
static const char *avm_revision = "$Revision: 2.15.2.4 $";
#define AVM_A1_STAT_ISAC 0x01
cs->irq = card->para[0];
if (!request_region(cs->hw.avm.cfg_reg, 8, "avm cfg")) {
printk(KERN_WARNING
- "HiSax: %s config port %x-%x already in use\n",
- CardType[card->typ],
+ "HiSax: AVM A1 config port %x-%x already in use\n",
cs->hw.avm.cfg_reg,
cs->hw.avm.cfg_reg + 8);
return (0);
}
if (!request_region(cs->hw.avm.isac + 32, 32, "HiSax isac")) {
printk(KERN_WARNING
- "HiSax: %s isac ports %x-%x already in use\n",
- CardType[cs->typ],
+ "HiSax: AVM A1 isac ports %x-%x already in use\n",
cs->hw.avm.isac + 32,
cs->hw.avm.isac + 64);
release_ioregs(cs, 0);
}
if (!request_region(cs->hw.avm.isacfifo, 1, "HiSax isac fifo")) {
printk(KERN_WARNING
- "HiSax: %s isac fifo port %x already in use\n",
- CardType[cs->typ],
+ "HiSax: AVM A1 isac fifo port %x already in use\n",
cs->hw.avm.isacfifo);
release_ioregs(cs, 1);
return (0);
}
if (!request_region(cs->hw.avm.hscx[0] + 32, 32, "HiSax hscx A")) {
printk(KERN_WARNING
- "HiSax: %s hscx A ports %x-%x already in use\n",
- CardType[cs->typ],
+ "HiSax: AVM A1 hscx A ports %x-%x already in use\n",
cs->hw.avm.hscx[0] + 32,
cs->hw.avm.hscx[0] + 64);
release_ioregs(cs, 3);
}
if (!request_region(cs->hw.avm.hscxfifo[0], 1, "HiSax hscx A fifo")) {
printk(KERN_WARNING
- "HiSax: %s hscx A fifo port %x already in use\n",
- CardType[cs->typ],
+ "HiSax: AVM A1 hscx A fifo port %x already in use\n",
cs->hw.avm.hscxfifo[0]);
release_ioregs(cs, 7);
return (0);
}
if (!request_region(cs->hw.avm.hscx[1] + 32, 32, "HiSax hscx B")) {
printk(KERN_WARNING
- "HiSax: %s hscx B ports %x-%x already in use\n",
- CardType[cs->typ],
+ "HiSax: AVM A1 hscx B ports %x-%x already in use\n",
cs->hw.avm.hscx[1] + 32,
cs->hw.avm.hscx[1] + 64);
release_ioregs(cs, 0xf);
}
if (!request_region(cs->hw.avm.hscxfifo[1], 1, "HiSax hscx B fifo")) {
printk(KERN_WARNING
- "HiSax: %s hscx B fifo port %x already in use\n",
- CardType[cs->typ],
+ "HiSax: AVM A1 hscx B fifo port %x already in use\n",
cs->hw.avm.hscxfifo[1]);
release_ioregs(cs, 0x1f);
return (0);
printk(KERN_INFO "AVM A1: Byte at %x is %x\n",
cs->hw.avm.cfg_reg, val);
- printk(KERN_INFO
- "HiSax: %s config irq:%d cfg:0x%X\n",
- CardType[cs->typ], cs->irq,
+ printk(KERN_INFO "HiSax: AVM A1 config irq:%d cfg:0x%X\n",
+ cs->irq,
cs->hw.avm.cfg_reg);
printk(KERN_INFO
"HiSax: isac:0x%X/0x%X\n",
#include <linux/pci.h>
#include "bkm_ax.h"
-extern const char *CardType[];
-
static const char *bkm_a4t_revision = "$Revision: 1.22.2.4 $";
I20_REGISTER_FILE *pI20_Regs;
if (!cs->irq) { /* IRQ range check ?? */
- printk(KERN_WARNING "HiSax: %s: No IRQ\n", CardType[card->typ]);
+ printk(KERN_WARNING "HiSax: Telekom A4T: No IRQ\n");
return (0);
}
cs->hw.ax.base = (long) ioremap(pci_memaddr, 4096);
/* Check suspecious address */
pI20_Regs = (I20_REGISTER_FILE *) (cs->hw.ax.base);
if ((pI20_Regs->i20IntStatus & 0x8EFFFFFF) != 0) {
- printk(KERN_WARNING "HiSax: %s address %lx-%lx suspecious\n",
- CardType[card->typ], cs->hw.ax.base, cs->hw.ax.base + 4096);
+ printk(KERN_WARNING "HiSax: Telekom A4T address "
+ "%lx-%lx suspicious\n",
+ cs->hw.ax.base, cs->hw.ax.base + 4096);
iounmap((void *) cs->hw.ax.base);
cs->hw.ax.base = 0;
return (0);
cs->hw.ax.isac_ale = GCS_1;
cs->hw.ax.jade_ale = GCS_3;
- printk(KERN_INFO "HiSax: %s: Card configured at 0x%lX IRQ %d\n",
- CardType[card->typ], cs->hw.ax.base, cs->irq);
+ printk(KERN_INFO "HiSax: Telekom A4T: Card configured at "
+ "0x%lX IRQ %d\n",
+ cs->hw.ax.base, cs->irq);
setup_isac(cs);
cs->readisac = &ReadISAC;
break;
}
if (!found) {
- printk(KERN_WARNING "HiSax: %s: Card not found\n", CardType[card->typ]);
+ printk(KERN_WARNING "HiSax: Telekom A4T: Card not found\n");
return (0);
}
if (!pci_memaddr) {
- printk(KERN_WARNING "HiSax: %s: No Memory base address\n", CardType[card->typ]);
+ printk(KERN_WARNING "HiSax: Telekom A4T: "
+ "No Memory base address\n");
return (0);
}
#define ATTEMPT_PCI_REMAPPING /* Required for PLX rev 1 */
-extern const char *CardType[];
-
static const char sct_quadro_revision[] = "$Revision: 1.22.2.4 $";
static const char *sct_quadro_subtypes[] =
goto Start_IPAC;
}
if (!icnt)
- printk(KERN_WARNING "HiSax: %s (%s) IRQ LOOP\n",
- CardType[cs->typ],
+ printk(KERN_WARNING "HiSax: Scitel Quadro (%s) IRQ LOOP\n",
sct_quadro_subtypes[cs->subtyp]);
writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
cs->subtyp = card->para[0];
else {
- printk(KERN_WARNING "HiSax: %s: Invalid subcontroller in configuration, default to 1\n",
- CardType[card->typ]);
+ printk(KERN_WARNING "HiSax: Scitel Quadro: Invalid "
+ "subcontroller in configuration, default to 1\n");
return (0);
}
if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) ||
}
}
if (!found) {
- printk(KERN_WARNING "HiSax: %s (%s): Card not found\n",
- CardType[card->typ],
+ printk(KERN_WARNING "HiSax: Scitel Quadro (%s): "
+ "Card not found\n",
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
#ifdef ATTEMPT_PCI_REMAPPING
/* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
if ((pci_ioaddr1 & 0x80) && (dev_a8->revision == 1)) {
- printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
- CardType[card->typ],
+ printk(KERN_WARNING "HiSax: Scitel Quadro (%s): "
+ "PLX rev 1, remapping required!\n",
sct_quadro_subtypes[cs->subtyp]);
/* Restart PCI negotiation */
pci_write_config_dword(dev_a8, PCI_BASE_ADDRESS_1, (u_int) - 1);
#endif /* End HACK */
}
if (!pci_irq) { /* IRQ range check ?? */
- printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
- CardType[card->typ],
+ printk(KERN_WARNING "HiSax: Scitel Quadro (%s): No IRQ\n",
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
- printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
- CardType[card->typ],
+ printk(KERN_WARNING "HiSax: Scitel Quadro (%s): "
+ "No IO base address(es)\n",
sct_quadro_subtypes[cs->subtyp]);
return (0);
}
/* For isac and hscx data path */
cs->hw.ax.data_adr = cs->hw.ax.base + 4;
- printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
- CardType[card->typ],
+ printk(KERN_INFO "HiSax: Scitel Quadro (%s) configured at "
+ "0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
sct_quadro_subtypes[cs->subtyp],
cs->hw.ax.plx_adr,
cs->hw.ax.base,
cs->cardmsg = &BKM_card_msg;
cs->irq_func = &bkm_interrupt_ipac;
- printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
- CardType[card->typ],
+ printk(KERN_INFO "HiSax: Scitel Quadro (%s): IPAC Version %d\n",
sct_quadro_subtypes[cs->subtyp],
readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
return (1);
/* Used from an exported function but calls __devinit functions.
* Tell modpost not to warn (__ref)
*/
-static int __ref checkcard(int cardnr, char *id, int *busy_flag, struct module *lockowner)
+static int __ref checkcard(int cardnr, char *id, int *busy_flag,
+ struct module *lockowner,
+ hisax_setup_func_t card_setup)
{
int ret;
struct IsdnCard *card = cards + cardnr;
(card->protocol == ISDN_PTYPE_NI1) ? "NI1" :
"NONE", cs->iif.id, cs->myid);
- ret = hisax_cs_setup_card(card);
+ ret = card_setup(card);
if (!ret) {
ll_unload(cs);
goto outf_cs;
else
sprintf(ids, "%s%d", id, i);
}
- if (checkcard(i, ids, busy_flag, THIS_MODULE)) {
+ if (checkcard(i, ids, busy_flag, THIS_MODULE,
+ hisax_cs_setup_card)) {
foundcards++;
i++;
} else {
sprintf(ids, "HiSax%d", nrcards);
else
sprintf(ids, "HiSax");
- if (!checkcard(nrcards, ids, busy_flag, THIS_MODULE))
+ if (!checkcard(nrcards, ids, busy_flag, THIS_MODULE,
+ hisax_cs_setup_card))
goto error;
ret = nrcards;
cards[i].protocol = protocol;
sprintf(id, "%s%d", name, i);
nrcards++;
- retval = checkcard(i, id, NULL, hisax_d_if->owner);
+ retval = checkcard(i, id, NULL, hisax_d_if->owner, hisax_cs_setup_card);
if (retval == 0) { // yuck
cards[i].typ = 0;
nrcards--;
val = serial_inp(cs, UART_IIR);
if (!(val & UART_IIR_NO_INT)) {
debugl1(cs,"IIR %02x", val);
- rs_interrupt_elsa(intno, cs);
+ rs_interrupt_elsa(cs);
}
}
#endif
val = serial_inp(cs, UART_IIR);
if (!(val & UART_IIR_NO_INT)) {
debugl1(cs,"IIR %02x", val);
- rs_interrupt_elsa(intno, cs);
+ rs_interrupt_elsa(cs);
}
}
#endif
}
-static void rs_interrupt_elsa(int irq, struct IsdnCardState *cs)
+static void rs_interrupt_elsa(struct IsdnCardState *cs)
{
int status, iir, msr;
int pass_counter = 0;
#ifdef SERIAL_DEBUG_INTR
- printk("rs_interrupt_single(%d)...", irq);
+ printk(KERN_DEBUG "rs_interrupt_single(%d)...", cs->irq);
#endif
do {
#include "ipac.h"
#include <linux/pci.h>
-extern const char *CardType[];
static const char *gazel_revision = "$Revision: 2.19.2.4 $";
#define R647 1
return 0;
error:
- printk(KERN_WARNING "Gazel: %s io ports 0x%x-0x%x already in use\n",
- CardType[cs->typ], adr, adr + len);
+ printk(KERN_WARNING "Gazel: io ports 0x%x-0x%x already in use\n",
+ adr, adr + len);
return 1;
}
#include <linux/pci.h>
#include <linux/interrupt.h>
-extern const char *CardType[];
-
static const char *hfcpci_revision = "$Revision: 1.48.2.4 $";
/* table entry in the PCI devices list */
#include <linux/interrupt.h>
#include <linux/isapnp.h>
-extern const char *CardType[];
-
static const char *hfcsx_revision = "$Revision: 1.12.2.5 $";
/***************************************/
int (*cardmsg) (struct IsdnCardState *, int, void *);
void (*setstack_d) (struct PStack *, struct IsdnCardState *);
void (*DC_Close) (struct IsdnCardState *);
- int (*irq_func) (int, void *);
+ irq_handler_t irq_func;
int (*auxcmd) (struct IsdnCardState *, isdn_ctrl *);
struct Channel channel[2+MAX_WAITING_CALLS];
struct BCState bcs[2+MAX_WAITING_CALLS];
IsdnCardState_t *cs;
};
+typedef int (*hisax_setup_func_t)(struct IsdnCard *card);
+
extern void HiSax_closecard(int);
extern int hisax_init_pcmcia(void *, int *, IsdnCard_t *);
#include "isdnl1.h"
#include <linux/isapnp.h>
-extern const char *CardType[];
-
static const char *ISurf_revision = "$Revision: 1.12.2.4 $";
#define byteout(addr,val) outb(val,addr)
return(0);
}
#else
- printk(KERN_WARNING "HiSax: %s port/mem not set\n",
- CardType[card->typ]);
+ printk(KERN_WARNING "HiSax: Siemens I-Surf port/mem not set\n");
return (0);
#endif
}
if (!request_region(cs->hw.isurf.reset, 1, "isurf isdn")) {
printk(KERN_WARNING
- "HiSax: %s config port %x already in use\n",
- CardType[card->typ],
+ "HiSax: Siemens I-Surf config port %x already in use\n",
cs->hw.isurf.reset);
return (0);
}
if (!request_region(cs->hw.isurf.phymem, ISURF_IOMEM_SIZE, "isurf iomem")) {
- printk(KERN_WARNING
- "HiSax: %s memory region %lx-%lx already in use\n",
- CardType[card->typ],
+ printk(KERN_WARNING "HiSax: Siemens I-Surf memory region "
+ "%lx-%lx already in use\n",
cs->hw.isurf.phymem,
cs->hw.isurf.phymem + ISURF_IOMEM_SIZE);
release_region(cs->hw.isurf.reset, 1);
#include "hscx.h"
#include "isdnl1.h"
-extern const char *CardType[];
static const char *ix1_revision = "$Revision: 2.12.2.4 $";
#define byteout(addr,val) outb(val,addr)
if (cs->hw.ix1.cfg_reg) {
if (!request_region(cs->hw.ix1.cfg_reg, 4, "ix1micro cfg")) {
printk(KERN_WARNING
- "HiSax: %s config port %x-%x already in use\n",
- CardType[card->typ],
+ "HiSax: ITK ix1-micro Rev.2 config port "
+ "%x-%x already in use\n",
cs->hw.ix1.cfg_reg,
cs->hw.ix1.cfg_reg + 4);
return (0);
}
}
- printk(KERN_INFO "HiSax: %s config irq:%d io:0x%X\n",
- CardType[cs->typ], cs->irq, cs->hw.ix1.cfg_reg);
+ printk(KERN_INFO "HiSax: ITK ix1-micro Rev.2 config irq:%d io:0x%X\n",
+ cs->irq, cs->hw.ix1.cfg_reg);
setup_isac(cs);
cs->readisac = &ReadISAC;
cs->writeisac = &WriteISAC;
#include "hscx.h"
#include "isdnl1.h"
-extern const char *CardType[];
-
static const char *mic_revision = "$Revision: 1.12.2.4 $";
#define byteout(addr,val) outb(val,addr)
if (!request_region(cs->hw.mic.cfg_reg, bytecnt, "mic isdn")) {
printk(KERN_WARNING
- "HiSax: %s config port %x-%x already in use\n",
- CardType[card->typ],
+ "HiSax: ith mic config port %x-%x already in use\n",
cs->hw.mic.cfg_reg,
cs->hw.mic.cfg_reg + bytecnt);
return (0);
*
*/
-extern const char *CardType[];
-
#define byteout(addr,val) outb(val,addr)
#define bytein(addr) inb(addr)
#include <linux/pci.h>
#include <linux/isapnp.h>
-extern const char *CardType[];
static const char *niccy_revision = "$Revision: 1.21.2.4 $";
#define byteout(addr,val) outb(val,addr)
cs->subtyp = NICCY_PNP;
cs->irq = card->para[0];
if (!request_region(cs->hw.niccy.isac, 2, "niccy data")) {
- printk(KERN_WARNING "HiSax: %s data port %x-%x "
- "already in use\n", CardType[card->typ],
+ printk(KERN_WARNING "HiSax: NICCY data port %x-%x "
+ "already in use\n",
cs->hw.niccy.isac, cs->hw.niccy.isac + 1);
return 0;
}
if (!request_region(cs->hw.niccy.isac_ale, 2, "niccy addr")) {
- printk(KERN_WARNING "HiSax: %s address port %x-%x "
- "already in use\n", CardType[card->typ],
+ printk(KERN_WARNING "HiSax: NICCY address port %x-%x "
+ "already in use\n",
cs->hw.niccy.isac_ale,
cs->hw.niccy.isac_ale + 1);
release_region(cs->hw.niccy.isac, 2);
cs->hw.niccy.hscx_ale = pci_ioaddr + HSCX_PCI_ADDR;
if (!request_region(cs->hw.niccy.isac, 4, "niccy")) {
printk(KERN_WARNING
- "HiSax: %s data port %x-%x already in use\n",
- CardType[card->typ],
+ "HiSax: NICCY data port %x-%x already in use\n",
cs->hw.niccy.isac, cs->hw.niccy.isac + 4);
return 0;
}
if (!request_region(cs->hw.niccy.cfg_reg, 0x40, "niccy pci")) {
printk(KERN_WARNING
- "HiSax: %s pci port %x-%x already in use\n",
- CardType[card->typ],
+ "HiSax: NICCY pci port %x-%x already in use\n",
cs->hw.niccy.cfg_reg,
cs->hw.niccy.cfg_reg + 0x40);
release_region(cs->hw.niccy.isac, 4);
return 0;
#endif /* CONFIG_PCI_LEGACY */
}
- printk(KERN_INFO "HiSax: %s %s config irq:%d data:0x%X ale:0x%X\n",
- CardType[cs->typ], (cs->subtyp == 1) ? "PnP" : "PCI",
+ printk(KERN_INFO "HiSax: NICCY %s config irq:%d data:0x%X ale:0x%X\n",
+ (cs->subtyp == 1) ? "PnP" : "PCI",
cs->irq, cs->hw.niccy.isac, cs->hw.niccy.isac_ale);
setup_isac(cs);
cs->readisac = &ReadISAC;
cs->subtyp ? "TJ320" : "TJ300", cs->hw.njet.base, cs->irq);
if (!request_region(cs->hw.njet.base, bytecnt, "netjet-s isdn")) {
printk(KERN_WARNING
- "HiSax: %s config port %#lx-%#lx already in use\n",
- CardType[card->typ],
+ "HiSax: NETjet-S config port %#lx-%#lx already in use\n",
cs->hw.njet.base,
cs->hw.njet.base + bytecnt);
return (0);
cs->hw.njet.base, cs->irq);
if (!request_region(cs->hw.njet.base, bytecnt, "netspider-u isdn")) {
printk(KERN_WARNING
- "HiSax: %s config port %#lx-%#lx already in use\n",
- CardType[card->typ],
+ "HiSax: NETspider-U config port %#lx-%#lx "
+ "already in use\n",
cs->hw.njet.base,
cs->hw.njet.base + bytecnt);
return (0);
#include "hscx.h"
#include "isdnl1.h"
-extern const char *CardType[];
static const char *s0box_revision = "$Revision: 2.6.2.4 $";
static inline void
cs->hw.teles3.hscxfifo[1] = cs->hw.teles3.hscx[1] + 0x3e;
cs->irq = card->para[0];
if (!request_region(cs->hw.teles3.cfg_reg,8, "S0Box parallel I/O")) {
- printk(KERN_WARNING
- "HiSax: %s ports %x-%x already in use\n",
- CardType[cs->typ],
+ printk(KERN_WARNING "HiSax: S0Box ports %x-%x already in use\n",
cs->hw.teles3.cfg_reg,
cs->hw.teles3.cfg_reg + 7);
return 0;
}
- printk(KERN_INFO
- "HiSax: %s config irq:%d isac:0x%x cfg:0x%x\n",
- CardType[cs->typ], cs->irq,
+ printk(KERN_INFO "HiSax: S0Box config irq:%d isac:0x%x cfg:0x%x\n",
+ cs->irq,
cs->hw.teles3.isac, cs->hw.teles3.cfg_reg);
- printk(KERN_INFO
- "HiSax: hscx A:0x%x hscx B:0x%x\n",
+ printk(KERN_INFO "HiSax: hscx A:0x%x hscx B:0x%x\n",
cs->hw.teles3.hscx[0], cs->hw.teles3.hscx[1]);
setup_isac(cs);
cs->readisac = &ReadISAC;
#include "hscx.h"
#include "isdnl1.h"
-extern const char *CardType[];
static char *saphir_rev = "$Revision: 1.10.2.4 $";
#define byteout(addr,val) outb(val,addr)
cs->irq = card->para[0];
if (!request_region(cs->hw.saphir.cfg_reg, 6, "saphir")) {
printk(KERN_WARNING
- "HiSax: %s config port %x-%x already in use\n",
- CardType[card->typ],
+ "HiSax: HST Saphir config port %x-%x already in use\n",
cs->hw.saphir.cfg_reg,
cs->hw.saphir.cfg_reg + 5);
return (0);
}
- printk(KERN_INFO "HiSax: %s config irq:%d io:0x%X\n",
- CardType[cs->typ], cs->irq, cs->hw.saphir.cfg_reg);
+ printk(KERN_INFO "HiSax: HST Saphir config irq:%d io:0x%X\n",
+ cs->irq, cs->hw.saphir.cfg_reg);
setup_isac(cs);
cs->hw.saphir.timer.function = (void *) SaphirWatchDog;
#include "hscx.h"
#include "isdnl1.h"
-extern const char *CardType[];
static const char *sportster_revision = "$Revision: 1.16.2.4 $";
#define byteout(addr,val) outb(val,addr)
for (i=0;i<64;i++) {
adr = cs->hw.spt.cfg_reg + i *1024;
if (!request_region(adr, 8, "sportster")) {
- printk(KERN_WARNING
- "HiSax: %s config port %x-%x already in use\n",
- CardType[cs->typ], adr, adr + 8);
+ printk(KERN_WARNING "HiSax: USR Sportster config port "
+ "%x-%x already in use\n",
+ adr, adr + 8);
break;
}
}
printk(KERN_WARNING "Sportster: wrong IRQ\n");
return(0);
}
- printk(KERN_INFO "HiSax: %s config irq:%d cfg:0x%X\n",
- CardType[cs->typ], cs->irq, cs->hw.spt.cfg_reg);
+ printk(KERN_INFO "HiSax: USR Sportster config irq:%d cfg:0x%X\n",
+ cs->irq, cs->hw.spt.cfg_reg);
setup_isac(cs);
cs->readisac = &ReadISAC;
cs->writeisac = &WriteISAC;
#include "hfc_2bs0.h"
#include "isdnl1.h"
-extern const char *CardType[];
-
static const char *TeleInt_revision = "$Revision: 1.16.2.5 $";
#define byteout(addr,val) outb(val,addr)
init_timer(&cs->hw.hfc.timer);
if (!request_region(cs->hw.hfc.addr, 2, "TeleInt isdn")) {
printk(KERN_WARNING
- "HiSax: %s config port %x-%x already in use\n",
- CardType[card->typ],
+ "HiSax: TeleInt config port %x-%x already in use\n",
cs->hw.hfc.addr,
cs->hw.hfc.addr + 2);
return (0);
#include "isdnl1.h"
#include <linux/pci.h>
-extern const char *CardType[];
static const char *telespci_revision = "$Revision: 2.23.2.3 $";
#define ZORAN_PO_RQ_PEN 0x02000000
/* writel(0x00800000, cs->hw.teles0.membase + 0x200); */
printk(KERN_INFO
- "HiSax: %s config irq:%d mem:%p\n",
- CardType[cs->typ], cs->irq,
+ "HiSax: Teles PCI config irq:%d mem:%p\n",
+ cs->irq,
cs->hw.teles0.membase);
setup_isac(cs);
#define W6692_DYNALINK 1
#define W6692_USR 2
-extern const char *CardType[];
-
static const char *w6692_revision = "$Revision: 1.18.2.4 $";
#define DBUSY_TIMER_VALUE 80
This option enables support for the LEDs on Sharp Zaurus
SL-Cxx00 series (C1000, C3000, C3100).
-config LEDS_TOSA
- tristate "LED Support for the Sharp SL-6000 series"
- depends on LEDS_CLASS && PXA_SHARPSL
- help
- This option enables support for the LEDs on Sharp Zaurus
- SL-6000 series.
-
config LEDS_S3C24XX
tristate "LED Support for Samsung S3C24XX GPIO LEDs"
depends on LEDS_CLASS && ARCH_S3C2410
obj-$(CONFIG_LEDS_CORGI) += leds-corgi.o
obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o
obj-$(CONFIG_LEDS_SPITZ) += leds-spitz.o
-obj-$(CONFIG_LEDS_TOSA) += leds-tosa.o
obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o
obj-$(CONFIG_LEDS_AMS_DELTA) += leds-ams-delta.o
obj-$(CONFIG_LEDS_NET48XX) += leds-net48xx.o
/**
* __led_classdev_unregister - unregisters a object of led_properties class.
* @led_cdev: the led device to unregister
- * @suspended: indicates whether system-wide suspend or resume is in progress
*
* Unregisters a previously registered via led_classdev_register object.
*/
-void __led_classdev_unregister(struct led_classdev *led_cdev,
- bool suspended)
+void led_classdev_unregister(struct led_classdev *led_cdev)
{
device_remove_file(led_cdev->dev, &dev_attr_brightness);
#ifdef CONFIG_LEDS_TRIGGERS
up_write(&led_cdev->trigger_lock);
#endif
- if (suspended)
- device_pm_schedule_removal(led_cdev->dev);
- else
- device_unregister(led_cdev->dev);
+ device_unregister(led_cdev->dev);
down_write(&leds_list_lock);
list_del(&led_cdev->node);
up_write(&leds_list_lock);
}
-EXPORT_SYMBOL_GPL(__led_classdev_unregister);
+EXPORT_SYMBOL_GPL(led_classdev_unregister);
static int __init leds_init(void)
{
+++ /dev/null
-/*
- * LED Triggers Core
- *
- * Copyright 2005 Dirk Opfer
- *
- * Author: Dirk Opfer <Dirk@Opfer-Online.de>
- * based on spitz.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <asm/hardware/scoop.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/tosa.h>
-
-static void tosaled_amber_set(struct led_classdev *led_cdev,
- enum led_brightness value)
-{
- if (value)
- set_scoop_gpio(&tosascoop_jc_device.dev,
- TOSA_SCOOP_JC_CHRG_ERR_LED);
- else
- reset_scoop_gpio(&tosascoop_jc_device.dev,
- TOSA_SCOOP_JC_CHRG_ERR_LED);
-}
-
-static void tosaled_green_set(struct led_classdev *led_cdev,
- enum led_brightness value)
-{
- if (value)
- set_scoop_gpio(&tosascoop_jc_device.dev,
- TOSA_SCOOP_JC_NOTE_LED);
- else
- reset_scoop_gpio(&tosascoop_jc_device.dev,
- TOSA_SCOOP_JC_NOTE_LED);
-}
-
-static struct led_classdev tosa_amber_led = {
- .name = "tosa:amber:charge",
- .default_trigger = "sharpsl-charge",
- .brightness_set = tosaled_amber_set,
-};
-
-static struct led_classdev tosa_green_led = {
- .name = "tosa:green:mail",
- .default_trigger = "nand-disk",
- .brightness_set = tosaled_green_set,
-};
-
-#ifdef CONFIG_PM
-static int tosaled_suspend(struct platform_device *dev, pm_message_t state)
-{
-#ifdef CONFIG_LEDS_TRIGGERS
- if (tosa_amber_led.trigger && strcmp(tosa_amber_led.trigger->name,
- "sharpsl-charge"))
-#endif
- led_classdev_suspend(&tosa_amber_led);
- led_classdev_suspend(&tosa_green_led);
- return 0;
-}
-
-static int tosaled_resume(struct platform_device *dev)
-{
- led_classdev_resume(&tosa_amber_led);
- led_classdev_resume(&tosa_green_led);
- return 0;
-}
-#else
-#define tosaled_suspend NULL
-#define tosaled_resume NULL
-#endif
-
-static int tosaled_probe(struct platform_device *pdev)
-{
- int ret;
-
- ret = led_classdev_register(&pdev->dev, &tosa_amber_led);
- if (ret < 0)
- return ret;
-
- ret = led_classdev_register(&pdev->dev, &tosa_green_led);
- if (ret < 0)
- led_classdev_unregister(&tosa_amber_led);
-
- return ret;
-}
-
-static int tosaled_remove(struct platform_device *pdev)
-{
- led_classdev_unregister(&tosa_amber_led);
- led_classdev_unregister(&tosa_green_led);
-
- return 0;
-}
-
-static struct platform_driver tosaled_driver = {
- .probe = tosaled_probe,
- .remove = tosaled_remove,
- .suspend = tosaled_suspend,
- .resume = tosaled_resume,
- .driver = {
- .name = "tosa-led",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init tosaled_init(void)
-{
- return platform_driver_register(&tosaled_driver);
-}
-
-static void __exit tosaled_exit(void)
-{
- platform_driver_unregister(&tosaled_driver);
-}
-
-module_init(tosaled_init);
-module_exit(tosaled_exit);
-
-MODULE_AUTHOR("Dirk Opfer <Dirk@Opfer-Online.de>");
-MODULE_DESCRIPTION("Tosa LED driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:tosa-led");
#include <linux/wait.h>
#include <linux/hrtimer.h>
#include <linux/err.h>
-#include <asm/semaphore.h>
#include <asm/lguest.h>
#include <linux/device.h>
#include <linux/kthread.h>
#include <linux/platform_device.h>
+#include <linux/semaphore.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#ifdef CONFIG_PPC
#include <asm/prom.h>
#include <asm/machdep.h>
#include <linux/init.h>
#include <linux/wait.h>
#include <linux/i2c.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include <asm/prom.h>
#include <asm/smu.h>
#include <asm/pmac_low_i2c.h>
return 0;
busy:
- printk(KERN_WARNING "md: cannot remove active disk %s from %s ... \n",
+ printk(KERN_WARNING "md: cannot remove active disk %s from %s ...\n",
bdevname(rdev->bdev,b), mdname(mddev));
return -EBUSY;
}
Less code and more efficient that loading a buffer on the stack with
the bytes to send and then calling or51132_writebuf() on that. */
#define or51132_writebytes(state, data...) \
- ({ const static u8 _data[] = {data}; \
+ ({ static const u8 _data[] = {data}; \
or51132_writebuf(state, _data, sizeof(_data)); })
/* Read data from demod into buffer. Returns 0 on success. */
static int or51132_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
{
struct or51132_state* state = fe->demodulator_priv;
- const static u8 run_buf[] = {0x7F,0x01};
+ static const u8 run_buf[] = {0x7F,0x01};
u8 rec_buf[8];
u32 firmwareAsize, firmwareBsize;
int i,ret;
#include <asm/uaccess.h> /* copy to/from user */
#include <linux/videodev2.h> /* kernel radio structs */
#include <media/v4l2-common.h>
-#include <asm/semaphore.h> /* Lock for the I/O */
#include <linux/version.h> /* for KERNEL_VERSION MACRO */
#define RADIO_VERSION KERNEL_VERSION(0,0,2)
#include <linux/i2c.h>
#include <linux/i2c-id.h>
#include <linux/workqueue.h>
-#include <asm/semaphore.h>
#include <media/ir-common.h>
#include <media/ir-kbd-i2c.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/pagemap.h>
-#include <asm/semaphore.h>
#include <asm/processor.h>
#include <linux/mm.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/slab.h>
-#include <asm/semaphore.h>
static void pvr2_context_destroy(struct pvr2_context *mp)
#include <linux/firmware.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
-#include <asm/semaphore.h>
#include "pvrusb2.h"
#include "pvrusb2-std.h"
#include "pvrusb2-util.h"
#include <linux/string.h>
#include <linux/slab.h>
-#include <asm/semaphore.h>
#include "pvrusb2-sysfs.h"
#include "pvrusb2-hdw.h"
#include "pvrusb2-debug.h"
Register adresses must be < 256.
*/
#define sn9c102_write_const_regs(sn9c102_device, data...) \
- ({ const static u8 _valreg[][2] = {data}; \
+ ({ static const u8 _valreg[][2] = {data}; \
sn9c102_write_regs(sn9c102_device, _valreg, ARRAY_SIZE(_valreg)); })
/*****************************************************************************/
/* ----------------------------------------------------------------- */
-const static unsigned int palette2pixelformat[] = {
+static const unsigned int palette2pixelformat[] = {
[VIDEO_PALETTE_GREY] = V4L2_PIX_FMT_GREY,
[VIDEO_PALETTE_RGB555] = V4L2_PIX_FMT_RGB555,
[VIDEO_PALETTE_RGB565] = V4L2_PIX_FMT_RGB565,
.resume = memstick_device_resume
};
-static void memstick_free(struct class_device *cdev)
+static void memstick_free(struct device *dev)
{
- struct memstick_host *host = container_of(cdev, struct memstick_host,
- cdev);
+ struct memstick_host *host = container_of(dev, struct memstick_host,
+ dev);
kfree(host);
}
static struct class memstick_host_class = {
.name = "memstick_host",
- .release = memstick_free
+ .dev_release = memstick_free
};
static void memstick_free_card(struct device *dev)
if (card) {
card->host = host;
snprintf(card->dev.bus_id, sizeof(card->dev.bus_id),
- "%s", host->cdev.class_id);
- card->dev.parent = host->cdev.dev;
+ "%s", host->dev.bus_id);
+ card->dev.parent = &host->dev;
card->dev.bus = &memstick_bus_type;
card->dev.release = memstick_free_card;
card->check = memstick_dummy_check;
media_checker);
struct memstick_dev *card;
- dev_dbg(host->cdev.dev, "memstick_check started\n");
+ dev_dbg(&host->dev, "memstick_check started\n");
mutex_lock(&host->lock);
if (!host->card)
memstick_power_on(host);
host->card = NULL;
}
} else {
- dev_dbg(host->cdev.dev, "new card %02x, %02x, %02x\n",
+ dev_dbg(&host->dev, "new card %02x, %02x, %02x\n",
card->id.type, card->id.category, card->id.class);
if (host->card) {
if (memstick_set_rw_addr(host->card)
host->set_param(host, MEMSTICK_POWER, MEMSTICK_POWER_OFF);
mutex_unlock(&host->lock);
- dev_dbg(host->cdev.dev, "memstick_check finished\n");
+ dev_dbg(&host->dev, "memstick_check finished\n");
}
/**
if (host) {
mutex_init(&host->lock);
INIT_WORK(&host->media_checker, memstick_check);
- host->cdev.class = &memstick_host_class;
- host->cdev.dev = dev;
- class_device_initialize(&host->cdev);
+ host->dev.class = &memstick_host_class;
+ host->dev.parent = dev;
+ device_initialize(&host->dev);
}
return host;
}
if (rc)
return rc;
- snprintf(host->cdev.class_id, BUS_ID_SIZE,
- "memstick%u", host->id);
+ snprintf(host->dev.bus_id, BUS_ID_SIZE, "memstick%u", host->id);
- rc = class_device_add(&host->cdev);
+ rc = device_add(&host->dev);
if (rc) {
spin_lock(&memstick_host_lock);
idr_remove(&memstick_host_idr, host->id);
spin_lock(&memstick_host_lock);
idr_remove(&memstick_host_idr, host->id);
spin_unlock(&memstick_host_lock);
- class_device_del(&host->cdev);
+ device_del(&host->dev);
}
EXPORT_SYMBOL(memstick_remove_host);
void memstick_free_host(struct memstick_host *host)
{
mutex_destroy(&host->lock);
- class_device_put(&host->cdev);
+ put_device(&host->dev);
}
EXPORT_SYMBOL(memstick_free_host);
u64 limit = BLK_BOUNCE_HIGH;
unsigned long capacity;
- if (host->cdev.dev->dma_mask && *(host->cdev.dev->dma_mask))
- limit = *(host->cdev.dev->dma_mask);
+ if (host->dev.dma_mask && *(host->dev.dma_mask))
+ limit = *(host->dev.dma_mask);
for (rc = 0; msb->attr_group.attrs[rc]; ++rc) {
s_attr = mspro_from_sysfs_attr(msb->attr_group.attrs[rc]);
unsigned int data_len, cmd, t_val;
if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) {
- dev_dbg(msh->cdev.dev, "no media status\n");
+ dev_dbg(&msh->dev, "no media status\n");
host->req->error = -ETIME;
return host->req->error;
}
- dev_dbg(msh->cdev.dev, "control %08x\n",
+ dev_dbg(&msh->dev, "control %08x\n",
readl(host->addr + HOST_CONTROL));
- dev_dbg(msh->cdev.dev, "status %08x\n", readl(host->addr + INT_STATUS));
- dev_dbg(msh->cdev.dev, "hstatus %08x\n", readl(host->addr + STATUS));
+ dev_dbg(&msh->dev, "status %08x\n", readl(host->addr + INT_STATUS));
+ dev_dbg(&msh->dev, "hstatus %08x\n", readl(host->addr + STATUS));
host->cmd_flags = 0;
host->block_pos = 0;
host->req->error = 0;
writel(cmd, host->addr + TPC);
- dev_dbg(msh->cdev.dev, "executing TPC %08x, len %x\n", cmd, data_len);
+ dev_dbg(&msh->dev, "executing TPC %08x, len %x\n", cmd, data_len);
return 0;
}
del_timer(&host->timer);
- dev_dbg(msh->cdev.dev, "c control %08x\n",
+ dev_dbg(&msh->dev, "c control %08x\n",
readl(host->addr + HOST_CONTROL));
- dev_dbg(msh->cdev.dev, "c status %08x\n",
+ dev_dbg(&msh->dev, "c status %08x\n",
readl(host->addr + INT_STATUS));
- dev_dbg(msh->cdev.dev, "c hstatus %08x\n", readl(host->addr + STATUS));
+ dev_dbg(&msh->dev, "c hstatus %08x\n", readl(host->addr + STATUS));
host->req->int_reg = readl(host->addr + STATUS) & 0xff;
}
static ssize_t
-mptscsih_version_fw_show(struct class_device *cdev, char *buf)
+mptscsih_version_fw_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
(ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
ioc->facts.FWVersion.Word & 0x000000FF);
}
-static CLASS_DEVICE_ATTR(version_fw, S_IRUGO, mptscsih_version_fw_show, NULL);
+static DEVICE_ATTR(version_fw, S_IRUGO, mptscsih_version_fw_show, NULL);
static ssize_t
-mptscsih_version_bios_show(struct class_device *cdev, char *buf)
+mptscsih_version_bios_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
(ioc->biosVersion & 0x0000FF00) >> 8,
ioc->biosVersion & 0x000000FF);
}
-static CLASS_DEVICE_ATTR(version_bios, S_IRUGO, mptscsih_version_bios_show, NULL);
+static DEVICE_ATTR(version_bios, S_IRUGO, mptscsih_version_bios_show, NULL);
static ssize_t
-mptscsih_version_mpi_show(struct class_device *cdev, char *buf)
+mptscsih_version_mpi_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
return snprintf(buf, PAGE_SIZE, "%03x\n", ioc->facts.MsgVersion);
}
-static CLASS_DEVICE_ATTR(version_mpi, S_IRUGO, mptscsih_version_mpi_show, NULL);
+static DEVICE_ATTR(version_mpi, S_IRUGO, mptscsih_version_mpi_show, NULL);
static ssize_t
-mptscsih_version_product_show(struct class_device *cdev, char *buf)
+mptscsih_version_product_show(struct device *dev,
+ struct device_attribute *attr,
+char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
return snprintf(buf, PAGE_SIZE, "%s\n", ioc->prod_name);
}
-static CLASS_DEVICE_ATTR(version_product, S_IRUGO,
+static DEVICE_ATTR(version_product, S_IRUGO,
mptscsih_version_product_show, NULL);
static ssize_t
-mptscsih_version_nvdata_persistent_show(struct class_device *cdev, char *buf)
+mptscsih_version_nvdata_persistent_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
return snprintf(buf, PAGE_SIZE, "%02xh\n",
ioc->nvdata_version_persistent);
}
-static CLASS_DEVICE_ATTR(version_nvdata_persistent, S_IRUGO,
+static DEVICE_ATTR(version_nvdata_persistent, S_IRUGO,
mptscsih_version_nvdata_persistent_show, NULL);
static ssize_t
-mptscsih_version_nvdata_default_show(struct class_device *cdev, char *buf)
+mptscsih_version_nvdata_default_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
return snprintf(buf, PAGE_SIZE, "%02xh\n",ioc->nvdata_version_default);
}
-static CLASS_DEVICE_ATTR(version_nvdata_default, S_IRUGO,
+static DEVICE_ATTR(version_nvdata_default, S_IRUGO,
mptscsih_version_nvdata_default_show, NULL);
static ssize_t
-mptscsih_board_name_show(struct class_device *cdev, char *buf)
+mptscsih_board_name_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
return snprintf(buf, PAGE_SIZE, "%s\n", ioc->board_name);
}
-static CLASS_DEVICE_ATTR(board_name, S_IRUGO, mptscsih_board_name_show, NULL);
+static DEVICE_ATTR(board_name, S_IRUGO, mptscsih_board_name_show, NULL);
static ssize_t
-mptscsih_board_assembly_show(struct class_device *cdev, char *buf)
+mptscsih_board_assembly_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
return snprintf(buf, PAGE_SIZE, "%s\n", ioc->board_assembly);
}
-static CLASS_DEVICE_ATTR(board_assembly, S_IRUGO,
+static DEVICE_ATTR(board_assembly, S_IRUGO,
mptscsih_board_assembly_show, NULL);
static ssize_t
-mptscsih_board_tracer_show(struct class_device *cdev, char *buf)
+mptscsih_board_tracer_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
return snprintf(buf, PAGE_SIZE, "%s\n", ioc->board_tracer);
}
-static CLASS_DEVICE_ATTR(board_tracer, S_IRUGO,
+static DEVICE_ATTR(board_tracer, S_IRUGO,
mptscsih_board_tracer_show, NULL);
static ssize_t
-mptscsih_io_delay_show(struct class_device *cdev, char *buf)
+mptscsih_io_delay_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
return snprintf(buf, PAGE_SIZE, "%02d\n", ioc->io_missing_delay);
}
-static CLASS_DEVICE_ATTR(io_delay, S_IRUGO,
+static DEVICE_ATTR(io_delay, S_IRUGO,
mptscsih_io_delay_show, NULL);
static ssize_t
-mptscsih_device_delay_show(struct class_device *cdev, char *buf)
+mptscsih_device_delay_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
return snprintf(buf, PAGE_SIZE, "%02d\n", ioc->device_missing_delay);
}
-static CLASS_DEVICE_ATTR(device_delay, S_IRUGO,
+static DEVICE_ATTR(device_delay, S_IRUGO,
mptscsih_device_delay_show, NULL);
static ssize_t
-mptscsih_debug_level_show(struct class_device *cdev, char *buf)
+mptscsih_debug_level_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
return snprintf(buf, PAGE_SIZE, "%08xh\n", ioc->debug_level);
}
static ssize_t
-mptscsih_debug_level_store(struct class_device *cdev, const char *buf,
- size_t count)
+mptscsih_debug_level_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
MPT_SCSI_HOST *hd = shost_priv(host);
MPT_ADAPTER *ioc = hd->ioc;
int val = 0;
ioc->name, ioc->debug_level);
return strlen(buf);
}
-static CLASS_DEVICE_ATTR(debug_level, S_IRUGO | S_IWUSR,
- mptscsih_debug_level_show, mptscsih_debug_level_store);
-
-struct class_device_attribute *mptscsih_host_attrs[] = {
- &class_device_attr_version_fw,
- &class_device_attr_version_bios,
- &class_device_attr_version_mpi,
- &class_device_attr_version_product,
- &class_device_attr_version_nvdata_persistent,
- &class_device_attr_version_nvdata_default,
- &class_device_attr_board_name,
- &class_device_attr_board_assembly,
- &class_device_attr_board_tracer,
- &class_device_attr_io_delay,
- &class_device_attr_device_delay,
- &class_device_attr_debug_level,
+static DEVICE_ATTR(debug_level, S_IRUGO | S_IWUSR,
+ mptscsih_debug_level_show, mptscsih_debug_level_store);
+
+struct device_attribute *mptscsih_host_attrs[] = {
+ &dev_attr_version_fw,
+ &dev_attr_version_bios,
+ &dev_attr_version_mpi,
+ &dev_attr_version_product,
+ &dev_attr_version_nvdata_persistent,
+ &dev_attr_version_nvdata_default,
+ &dev_attr_board_name,
+ &dev_attr_board_assembly,
+ &dev_attr_board_tracer,
+ &dev_attr_io_delay,
+ &dev_attr_device_delay,
+ &dev_attr_debug_level,
NULL,
};
EXPORT_SYMBOL(mptscsih_host_attrs);
extern int mptscsih_TMHandler(MPT_SCSI_HOST *hd, u8 type, u8 channel, u8 id, int lun, int ctx2abort, ulong timeout);
extern u8 mptscsih_raid_id_to_num(MPT_ADAPTER *ioc, u8 channel, u8 id);
extern int mptscsih_is_phys_disk(MPT_ADAPTER *ioc, u8 channel, u8 id);
-extern struct class_device_attribute *mptscsih_host_attrs[];
+extern struct device_attribute *mptscsih_host_attrs[];
This driver supports the ASIC3 multifunction chip found on many
PDAs (mainly iPAQ and HTC based ones)
+config HTC_EGPIO
+ bool "HTC EGPIO support"
+ depends on GENERIC_HARDIRQS && HAVE_GPIO_LIB
+ help
+ This driver supports the CPLD egpio chip present on
+ several HTC phones. It provides basic support for input
+ pins, output pins, and irqs.
+
+config HTC_PASIC3
+ tristate "HTC PASIC3 LED/DS1WM chip support"
+ help
+ This core driver provides register access for the LED/DS1WM
+ chips labeled "AIC2" and "AIC3", found on HTC Blueangel and
+ HTC Magician devices, respectively. Actual functionality is
+ handled by the leds-pasic3 and ds1wm drivers.
+
endmenu
menu "Multimedia Capabilities Port drivers"
obj-$(CONFIG_MFD_SM501) += sm501.o
obj-$(CONFIG_MFD_ASIC3) += asic3.o
+obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
+obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o
+
obj-$(CONFIG_MCP) += mcp-core.o
obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o
obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o
--- /dev/null
+/*
+ * Support for the GPIO/IRQ expander chips present on several HTC phones.
+ * These are implemented in CPLD chips present on the board.
+ *
+ * Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
+ * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This file may be distributed under the terms of the GNU GPL license.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/mfd/htc-egpio.h>
+
+struct egpio_chip {
+ int reg_start;
+ int cached_values;
+ unsigned long is_out;
+ struct device *dev;
+ struct gpio_chip chip;
+};
+
+struct egpio_info {
+ spinlock_t lock;
+
+ /* iomem info */
+ void __iomem *base_addr;
+ int bus_shift; /* byte shift */
+ int reg_shift; /* bit shift */
+ int reg_mask;
+
+ /* irq info */
+ int ack_register;
+ int ack_write;
+ u16 irqs_enabled;
+ uint irq_start;
+ int nirqs;
+ uint chained_irq;
+
+ /* egpio info */
+ struct egpio_chip *chip;
+ int nchips;
+};
+
+static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
+{
+ writew(value, ei->base_addr + (reg << ei->bus_shift));
+}
+
+static inline u16 egpio_readw(struct egpio_info *ei, int reg)
+{
+ return readw(ei->base_addr + (reg << ei->bus_shift));
+}
+
+/*
+ * IRQs
+ */
+
+static inline void ack_irqs(struct egpio_info *ei)
+{
+ egpio_writew(ei->ack_write, ei, ei->ack_register);
+ pr_debug("EGPIO ack - write %x to base+%x\n",
+ ei->ack_write, ei->ack_register << ei->bus_shift);
+}
+
+static void egpio_ack(unsigned int irq)
+{
+}
+
+/* There does not appear to be a way to proactively mask interrupts
+ * on the egpio chip itself. So, we simply ignore interrupts that
+ * aren't desired. */
+static void egpio_mask(unsigned int irq)
+{
+ struct egpio_info *ei = get_irq_chip_data(irq);
+ ei->irqs_enabled &= ~(1 << (irq - ei->irq_start));
+ pr_debug("EGPIO mask %d %04x\n", irq, ei->irqs_enabled);
+}
+static void egpio_unmask(unsigned int irq)
+{
+ struct egpio_info *ei = get_irq_chip_data(irq);
+ ei->irqs_enabled |= 1 << (irq - ei->irq_start);
+ pr_debug("EGPIO unmask %d %04x\n", irq, ei->irqs_enabled);
+}
+
+static struct irq_chip egpio_muxed_chip = {
+ .name = "htc-egpio",
+ .ack = egpio_ack,
+ .mask = egpio_mask,
+ .unmask = egpio_unmask,
+};
+
+static void egpio_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct egpio_info *ei = get_irq_data(irq);
+ int irqpin;
+
+ /* Read current pins. */
+ unsigned long readval = egpio_readw(ei, ei->ack_register);
+ pr_debug("IRQ reg: %x\n", (unsigned int)readval);
+ /* Ack/unmask interrupts. */
+ ack_irqs(ei);
+ /* Process all set pins. */
+ readval &= ei->irqs_enabled;
+ for_each_bit(irqpin, &readval, ei->nirqs) {
+ /* Run irq handler */
+ pr_debug("got IRQ %d\n", irqpin);
+ irq = ei->irq_start + irqpin;
+ desc = &irq_desc[irq];
+ desc->handle_irq(irq, desc);
+ }
+}
+
+int htc_egpio_get_wakeup_irq(struct device *dev)
+{
+ struct egpio_info *ei = dev_get_drvdata(dev);
+
+ /* Read current pins. */
+ u16 readval = egpio_readw(ei, ei->ack_register);
+ /* Ack/unmask interrupts. */
+ ack_irqs(ei);
+ /* Return first set pin. */
+ readval &= ei->irqs_enabled;
+ return ei->irq_start + ffs(readval) - 1;
+}
+EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);
+
+static inline int egpio_pos(struct egpio_info *ei, int bit)
+{
+ return bit >> ei->reg_shift;
+}
+
+static inline int egpio_bit(struct egpio_info *ei, int bit)
+{
+ return 1 << (bit & ((1 << ei->reg_shift)-1));
+}
+
+/*
+ * Input pins
+ */
+
+static int egpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct egpio_chip *egpio;
+ struct egpio_info *ei;
+ unsigned bit;
+ int reg;
+ int value;
+
+ pr_debug("egpio_get_value(%d)\n", chip->base + offset);
+
+ egpio = container_of(chip, struct egpio_chip, chip);
+ ei = dev_get_drvdata(egpio->dev);
+ bit = egpio_bit(ei, offset);
+ reg = egpio->reg_start + egpio_pos(ei, offset);
+
+ value = egpio_readw(ei, reg);
+ pr_debug("readw(%p + %x) = %x\n",
+ ei->base_addr, reg << ei->bus_shift, value);
+ return value & bit;
+}
+
+static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct egpio_chip *egpio;
+
+ egpio = container_of(chip, struct egpio_chip, chip);
+ return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
+}
+
+
+/*
+ * Output pins
+ */
+
+static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ unsigned long flag;
+ struct egpio_chip *egpio;
+ struct egpio_info *ei;
+ unsigned bit;
+ int pos;
+ int reg;
+ int shift;
+
+ pr_debug("egpio_set(%s, %d(%d), %d)\n",
+ chip->label, offset, offset+chip->base, value);
+
+ egpio = container_of(chip, struct egpio_chip, chip);
+ ei = dev_get_drvdata(egpio->dev);
+ bit = egpio_bit(ei, offset);
+ pos = egpio_pos(ei, offset);
+ reg = egpio->reg_start + pos;
+ shift = pos << ei->reg_shift;
+
+ pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
+ reg, (egpio->cached_values >> shift) & ei->reg_mask);
+
+ spin_lock_irqsave(&ei->lock, flag);
+ if (value)
+ egpio->cached_values |= (1 << offset);
+ else
+ egpio->cached_values &= ~(1 << offset);
+ egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
+ spin_unlock_irqrestore(&ei->lock, flag);
+}
+
+static int egpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ struct egpio_chip *egpio;
+
+ egpio = container_of(chip, struct egpio_chip, chip);
+ if (test_bit(offset, &egpio->is_out)) {
+ egpio_set(chip, offset, value);
+ return 0;
+ } else {
+ return -EINVAL;
+ }
+}
+
+static void egpio_write_cache(struct egpio_info *ei)
+{
+ int i;
+ struct egpio_chip *egpio;
+ int shift;
+
+ for (i = 0; i < ei->nchips; i++) {
+ egpio = &(ei->chip[i]);
+ if (!egpio->is_out)
+ continue;
+
+ for (shift = 0; shift < egpio->chip.ngpio;
+ shift += (1<<ei->reg_shift)) {
+
+ int reg = egpio->reg_start + egpio_pos(ei, shift);
+
+ if (!((egpio->is_out >> shift) & ei->reg_mask))
+ continue;
+
+ pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
+ (egpio->cached_values >> shift) & ei->reg_mask,
+ egpio_readw(ei, reg));
+
+ egpio_writew((egpio->cached_values >> shift)
+ & ei->reg_mask, ei, reg);
+ }
+ }
+}
+
+
+/*
+ * Setup
+ */
+
+static int __init egpio_probe(struct platform_device *pdev)
+{
+ struct htc_egpio_platform_data *pdata = pdev->dev.platform_data;
+ struct resource *res;
+ struct egpio_info *ei;
+ struct gpio_chip *chip;
+ unsigned int irq, irq_end;
+ int i;
+ int ret;
+
+ /* Initialize ei data structure. */
+ ei = kzalloc(sizeof(*ei), GFP_KERNEL);
+ if (!ei)
+ return -ENOMEM;
+
+ spin_lock_init(&ei->lock);
+
+ /* Find chained irq */
+ ret = -EINVAL;
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (res)
+ ei->chained_irq = res->start;
+
+ /* Map egpio chip into virtual address space. */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ goto fail;
+ ei->base_addr = ioremap_nocache(res->start, res->end - res->start);
+ if (!ei->base_addr)
+ goto fail;
+ pr_debug("EGPIO phys=%08x virt=%p\n", res->start, ei->base_addr);
+
+ if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
+ goto fail;
+ ei->bus_shift = fls(pdata->bus_width - 1) - 3;
+ pr_debug("bus_shift = %d\n", ei->bus_shift);
+
+ if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
+ goto fail;
+ ei->reg_shift = fls(pdata->reg_width - 1);
+ pr_debug("reg_shift = %d\n", ei->reg_shift);
+
+ ei->reg_mask = (1 << pdata->reg_width) - 1;
+
+ platform_set_drvdata(pdev, ei);
+
+ ei->nchips = pdata->num_chips;
+ ei->chip = kzalloc(sizeof(struct egpio_chip) * ei->nchips, GFP_KERNEL);
+ if (!ei) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+ for (i = 0; i < ei->nchips; i++) {
+ ei->chip[i].reg_start = pdata->chip[i].reg_start;
+ ei->chip[i].cached_values = pdata->chip[i].initial_values;
+ ei->chip[i].is_out = pdata->chip[i].direction;
+ ei->chip[i].dev = &(pdev->dev);
+ chip = &(ei->chip[i].chip);
+ chip->label = "htc-egpio";
+ chip->get = egpio_get;
+ chip->set = egpio_set;
+ chip->direction_input = egpio_direction_input;
+ chip->direction_output = egpio_direction_output;
+ chip->base = pdata->chip[i].gpio_base;
+ chip->ngpio = pdata->chip[i].num_gpios;
+
+ gpiochip_add(chip);
+ }
+
+ /* Set initial pin values */
+ egpio_write_cache(ei);
+
+ ei->irq_start = pdata->irq_base;
+ ei->nirqs = pdata->num_irqs;
+ ei->ack_register = pdata->ack_register;
+
+ if (ei->chained_irq) {
+ /* Setup irq handlers */
+ ei->ack_write = 0xFFFF;
+ if (pdata->invert_acks)
+ ei->ack_write = 0;
+ irq_end = ei->irq_start + ei->nirqs;
+ for (irq = ei->irq_start; irq < irq_end; irq++) {
+ set_irq_chip(irq, &egpio_muxed_chip);
+ set_irq_chip_data(irq, ei);
+ set_irq_handler(irq, handle_simple_irq);
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+ }
+ set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
+ set_irq_data(ei->chained_irq, ei);
+ set_irq_chained_handler(ei->chained_irq, egpio_handler);
+ ack_irqs(ei);
+
+ device_init_wakeup(&pdev->dev, 1);
+ }
+
+ return 0;
+
+fail:
+ printk(KERN_ERR "EGPIO failed to setup\n");
+ kfree(ei);
+ return ret;
+}
+
+static int __exit egpio_remove(struct platform_device *pdev)
+{
+ struct egpio_info *ei = platform_get_drvdata(pdev);
+ unsigned int irq, irq_end;
+
+ if (ei->chained_irq) {
+ irq_end = ei->irq_start + ei->nirqs;
+ for (irq = ei->irq_start; irq < irq_end; irq++) {
+ set_irq_chip(irq, NULL);
+ set_irq_handler(irq, NULL);
+ set_irq_flags(irq, 0);
+ }
+ set_irq_chained_handler(ei->chained_irq, NULL);
+ device_init_wakeup(&pdev->dev, 0);
+ }
+ iounmap(ei->base_addr);
+ kfree(ei->chip);
+ kfree(ei);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct egpio_info *ei = platform_get_drvdata(pdev);
+
+ if (ei->chained_irq && device_may_wakeup(&pdev->dev))
+ enable_irq_wake(ei->chained_irq);
+ return 0;
+}
+
+static int egpio_resume(struct platform_device *pdev)
+{
+ struct egpio_info *ei = platform_get_drvdata(pdev);
+
+ if (ei->chained_irq && device_may_wakeup(&pdev->dev))
+ disable_irq_wake(ei->chained_irq);
+
+ /* Update registers from the cache, in case
+ the CPLD was powered off during suspend */
+ egpio_write_cache(ei);
+ return 0;
+}
+#else
+#define egpio_suspend NULL
+#define egpio_resume NULL
+#endif
+
+
+static struct platform_driver egpio_driver = {
+ .driver = {
+ .name = "htc-egpio",
+ },
+ .remove = __exit_p(egpio_remove),
+ .suspend = egpio_suspend,
+ .resume = egpio_resume,
+};
+
+static int __init egpio_init(void)
+{
+ return platform_driver_probe(&egpio_driver, egpio_probe);
+}
+
+static void __exit egpio_exit(void)
+{
+ platform_driver_unregister(&egpio_driver);
+}
+
+/* start early for dependencies */
+subsys_initcall(egpio_init);
+module_exit(egpio_exit)
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kevin O'Connor <kevin@koconnor.net>");
--- /dev/null
+/*
+ * Core driver for HTC PASIC3 LED/DS1WM chip.
+ *
+ * Copyright (C) 2006 Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <linux/ds1wm.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/htc-pasic3.h>
+
+#include <asm/arch/pxa-regs.h>
+
+struct pasic3_data {
+ void __iomem *mapping;
+ unsigned int bus_shift;
+ struct platform_device *ds1wm_pdev;
+ struct platform_device *led_pdev;
+};
+
+#define REG_ADDR 5
+#define REG_DATA 6
+#define NUM_REGS 7
+
+#define READ_MODE 0x80
+
+/*
+ * write to a secondary register on the PASIC3
+ */
+void pasic3_write_register(struct device *dev, u32 reg, u8 val)
+{
+ struct pasic3_data *asic = dev->driver_data;
+ int bus_shift = asic->bus_shift;
+ void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift);
+ void __iomem *data = asic->mapping + (REG_DATA << bus_shift);
+
+ __raw_writeb(~READ_MODE & reg, addr);
+ __raw_writeb(val, data);
+}
+EXPORT_SYMBOL(pasic3_write_register); /* for leds-pasic3 */
+
+/*
+ * read from a secondary register on the PASIC3
+ */
+u8 pasic3_read_register(struct device *dev, u32 reg)
+{
+ struct pasic3_data *asic = dev->driver_data;
+ int bus_shift = asic->bus_shift;
+ void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift);
+ void __iomem *data = asic->mapping + (REG_DATA << bus_shift);
+
+ __raw_writeb(READ_MODE | reg, addr);
+ return __raw_readb(data);
+}
+EXPORT_SYMBOL(pasic3_read_register); /* for leds-pasic3 */
+
+/*
+ * LEDs
+ */
+
+static int led_device_add(struct device *pasic3_dev,
+ const struct pasic3_leds_machinfo *pdata)
+{
+ struct pasic3_data *asic = pasic3_dev->driver_data;
+ struct platform_device *pdev;
+ int ret;
+
+ pdev = platform_device_alloc("pasic3-led", -1);
+ if (!pdev) {
+ dev_dbg(pasic3_dev, "failed to allocate LED platform device\n");
+ return -ENOMEM;
+ }
+
+ ret = platform_device_add_data(pdev, pdata,
+ sizeof(struct pasic3_leds_machinfo));
+ if (ret < 0) {
+ dev_dbg(pasic3_dev, "failed to add LED platform data\n");
+ goto exit_pdev_put;
+ }
+
+ pdev->dev.parent = pasic3_dev;
+ ret = platform_device_add(pdev);
+ if (ret < 0) {
+ dev_dbg(pasic3_dev, "failed to add LED platform device\n");
+ goto exit_pdev_put;
+ }
+
+ asic->led_pdev = pdev;
+ return 0;
+
+exit_pdev_put:
+ platform_device_put(pdev);
+ return ret;
+}
+
+/*
+ * DS1WM
+ */
+
+static void ds1wm_enable(struct platform_device *pdev)
+{
+ struct device *dev = pdev->dev.parent;
+ int c;
+
+ c = pasic3_read_register(dev, 0x28);
+ pasic3_write_register(dev, 0x28, c & 0x7f);
+
+ dev_dbg(dev, "DS1WM OWM_EN low (active) %02x\n", c & 0x7f);
+}
+
+static void ds1wm_disable(struct platform_device *pdev)
+{
+ struct device *dev = pdev->dev.parent;
+ int c;
+
+ c = pasic3_read_register(dev, 0x28);
+ pasic3_write_register(dev, 0x28, c | 0x80);
+
+ dev_dbg(dev, "DS1WM OWM_EN high (inactive) %02x\n", c | 0x80);
+}
+
+static struct ds1wm_platform_data ds1wm_pdata = {
+ .bus_shift = 2,
+ .enable = ds1wm_enable,
+ .disable = ds1wm_disable,
+};
+
+static int ds1wm_device_add(struct device *pasic3_dev, int bus_shift)
+{
+ struct pasic3_data *asic = pasic3_dev->driver_data;
+ struct platform_device *pdev;
+ int ret;
+
+ pdev = platform_device_alloc("ds1wm", -1);
+ if (!pdev) {
+ dev_dbg(pasic3_dev, "failed to allocate DS1WM platform device\n");
+ return -ENOMEM;
+ }
+
+ ret = platform_device_add_resources(pdev, pdev->resource,
+ pdev->num_resources);
+ if (ret < 0) {
+ dev_dbg(pasic3_dev, "failed to add DS1WM resources\n");
+ goto exit_pdev_put;
+ }
+
+ ds1wm_pdata.bus_shift = asic->bus_shift;
+ ret = platform_device_add_data(pdev, &ds1wm_pdata,
+ sizeof(struct ds1wm_platform_data));
+ if (ret < 0) {
+ dev_dbg(pasic3_dev, "failed to add DS1WM platform data\n");
+ goto exit_pdev_put;
+ }
+
+ pdev->dev.parent = pasic3_dev;
+ ret = platform_device_add(pdev);
+ if (ret < 0) {
+ dev_dbg(pasic3_dev, "failed to add DS1WM platform device\n");
+ goto exit_pdev_put;
+ }
+
+ asic->ds1wm_pdev = pdev;
+ return 0;
+
+exit_pdev_put:
+ platform_device_put(pdev);
+ return ret;
+}
+
+static int __init pasic3_probe(struct platform_device *pdev)
+{
+ struct pasic3_platform_data *pdata = pdev->dev.platform_data;
+ struct device *dev = &pdev->dev;
+ struct pasic3_data *asic;
+ struct resource *r;
+ int ret;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!r)
+ return -ENXIO;
+
+ if (!request_mem_region(r->start, r->end - r->start + 1, "pasic3"))
+ return -EBUSY;
+
+ asic = kzalloc(sizeof(struct pasic3_data), GFP_KERNEL);
+ if (!asic)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, asic);
+
+ if (pdata && pdata->bus_shift)
+ asic->bus_shift = pdata->bus_shift;
+ else
+ asic->bus_shift = 2;
+
+ asic->mapping = ioremap(r->start, r->end - r->start + 1);
+ if (!asic->mapping) {
+ dev_err(dev, "couldn't ioremap PASIC3\n");
+ kfree(asic);
+ return -ENOMEM;
+ }
+
+ ret = ds1wm_device_add(dev, asic->bus_shift);
+ if (ret < 0)
+ dev_warn(dev, "failed to register DS1WM\n");
+
+ if (pdata->led_pdata) {
+ ret = led_device_add(dev, pdata->led_pdata);
+ if (ret < 0)
+ dev_warn(dev, "failed to register LED device\n");
+ }
+
+ return 0;
+}
+
+static int pasic3_remove(struct platform_device *pdev)
+{
+ struct pasic3_data *asic = platform_get_drvdata(pdev);
+ struct resource *r;
+
+ if (asic->led_pdev)
+ platform_device_unregister(asic->led_pdev);
+ if (asic->ds1wm_pdev)
+ platform_device_unregister(asic->ds1wm_pdev);
+
+ iounmap(asic->mapping);
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(r->start, r->end - r->start + 1);
+ kfree(asic);
+ return 0;
+}
+
+static struct platform_driver pasic3_driver = {
+ .driver = {
+ .name = "pasic3",
+ },
+ .remove = pasic3_remove,
+};
+
+static int __init pasic3_base_init(void)
+{
+ return platform_driver_probe(&pasic3_driver, pasic3_probe);
+}
+
+static void __exit pasic3_base_exit(void)
+{
+ platform_driver_unregister(&pasic3_driver);
+}
+
+module_init(pasic3_base_init);
+module_exit(pasic3_base_exit);
+
+MODULE_AUTHOR("Philipp Zabel <philipp.zabel@gmail.com>");
+MODULE_DESCRIPTION("Core driver for HTC PASIC3");
+MODULE_LICENSE("GPL");
#include <linux/kthread.h>
#include <asm/dma.h>
-#include <asm/semaphore.h>
#include <asm/arch/collie.h>
#include <asm/mach-types.h>
purposes including software controlled power-efficent backlights
on LCD displays, motor control, and waveform generation.
+config ATMEL_TCLIB
+ bool "Atmel AT32/AT91 Timer/Counter Library"
+ depends on (AVR32 || ARCH_AT91)
+ help
+ Select this if you want a library to allocate the Timer/Counter
+ blocks found on many Atmel processors. This facilitates using
+ these blocks by different drivers despite processor differences.
+
+config ATMEL_TCB_CLKSRC
+ bool "TC Block Clocksource"
+ depends on ATMEL_TCLIB && GENERIC_TIME
+ default y
+ help
+ Select this to get a high precision clocksource based on a
+ TC block with a 5+ MHz base clock rate. Two timer channels
+ are combined to make a single 32-bit timer.
+
+ When GENERIC_CLOCKEVENTS is defined, the third timer channel
+ may be used as a clock event device supporting oneshot mode
+ (delays of up to two seconds) based on the 32 KiHz clock.
+
+config ATMEL_TCB_CLKSRC_BLOCK
+ int
+ depends on ATMEL_TCB_CLKSRC
+ prompt "TC Block" if ARCH_AT91RM9200 || ARCH_AT91SAM9260 || CPU_AT32AP700X
+ default 0
+ range 0 1
+ help
+ Some chips provide more than one TC block, so you have the
+ choice of which one to use for the clock framework. The other
+ TC can be used for other purposes, such as PWM generation and
+ interval timing.
+
config IBM_ASM
tristate "Device driver for IBM RSA service processor"
depends on X86 && PCI && INPUT && EXPERIMENTAL
driver (SCSI/ATA) which supports enclosures
or a SCSI enclosure device (SES) to use these services.
+config SGI_XP
+ tristate "Support communication between SGI SSIs"
+ depends on IA64_GENERIC || IA64_SGI_SN2
+ select IA64_UNCACHED_ALLOCATOR if IA64_GENERIC || IA64_SGI_SN2
+ select GENERIC_ALLOCATOR if IA64_GENERIC || IA64_SGI_SN2
+ ---help---
+ An SGI machine can be divided into multiple Single System
+ Images which act independently of each other and have
+ hardware based memory protection from the others. Enabling
+ this feature will allow for direct communication between SSIs
+ based on a network adapter and DMA messaging.
+
endif # MISC_DEVICES
obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
+obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o
obj-$(CONFIG_LKDTM) += lkdtm.o
obj-$(CONFIG_TIFM_CORE) += tifm_core.o
obj-$(CONFIG_INTEL_MENLOW) += intel_menlow.o
obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o
obj-$(CONFIG_KGDB_TESTS) += kgdbts.o
+obj-$(CONFIG_SGI_XP) += sgi-xp/
--- /dev/null
+#include <linux/atmel_tc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+/* Number of bytes to reserve for the iomem resource */
+#define ATMEL_TC_IOMEM_SIZE 256
+
+
+/*
+ * This is a thin library to solve the problem of how to portably allocate
+ * one of the TC blocks. For simplicity, it doesn't currently expect to
+ * share individual timers between different drivers.
+ */
+
+#if defined(CONFIG_AVR32)
+/* AVR32 has these divide PBB */
+const u8 atmel_tc_divisors[5] = { 0, 4, 8, 16, 32, };
+EXPORT_SYMBOL(atmel_tc_divisors);
+
+#elif defined(CONFIG_ARCH_AT91)
+/* AT91 has these divide MCK */
+const u8 atmel_tc_divisors[5] = { 2, 8, 32, 128, 0, };
+EXPORT_SYMBOL(atmel_tc_divisors);
+
+#endif
+
+static DEFINE_SPINLOCK(tc_list_lock);
+static LIST_HEAD(tc_list);
+
+/**
+ * atmel_tc_alloc - allocate a specified TC block
+ * @block: which block to allocate
+ * @name: name to be associated with the iomem resource
+ *
+ * Caller allocates a block. If it is available, a pointer to a
+ * pre-initialized struct atmel_tc is returned. The caller can access
+ * the registers directly through the "regs" field.
+ */
+struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name)
+{
+ struct atmel_tc *tc;
+ struct platform_device *pdev = NULL;
+ struct resource *r;
+
+ spin_lock(&tc_list_lock);
+ list_for_each_entry(tc, &tc_list, node) {
+ if (tc->pdev->id == block) {
+ pdev = tc->pdev;
+ break;
+ }
+ }
+
+ if (!pdev || tc->iomem)
+ goto fail;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ r = request_mem_region(r->start, ATMEL_TC_IOMEM_SIZE, name);
+ if (!r)
+ goto fail;
+
+ tc->regs = ioremap(r->start, ATMEL_TC_IOMEM_SIZE);
+ if (!tc->regs)
+ goto fail_ioremap;
+
+ tc->iomem = r;
+
+out:
+ spin_unlock(&tc_list_lock);
+ return tc;
+
+fail_ioremap:
+ release_resource(r);
+fail:
+ tc = NULL;
+ goto out;
+}
+EXPORT_SYMBOL_GPL(atmel_tc_alloc);
+
+/**
+ * atmel_tc_free - release a specified TC block
+ * @tc: Timer/counter block that was returned by atmel_tc_alloc()
+ *
+ * This reverses the effect of atmel_tc_alloc(), unmapping the I/O
+ * registers, invalidating the resource returned by that routine and
+ * making the TC available to other drivers.
+ */
+void atmel_tc_free(struct atmel_tc *tc)
+{
+ spin_lock(&tc_list_lock);
+ if (tc->regs) {
+ iounmap(tc->regs);
+ release_resource(tc->iomem);
+ tc->regs = NULL;
+ tc->iomem = NULL;
+ }
+ spin_unlock(&tc_list_lock);
+}
+EXPORT_SYMBOL_GPL(atmel_tc_free);
+
+static int __init tc_probe(struct platform_device *pdev)
+{
+ struct atmel_tc *tc;
+ struct clk *clk;
+ int irq;
+
+ if (!platform_get_resource(pdev, IORESOURCE_MEM, 0))
+ return -EINVAL;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return -EINVAL;
+
+ tc = kzalloc(sizeof(struct atmel_tc), GFP_KERNEL);
+ if (!tc)
+ return -ENOMEM;
+
+ tc->pdev = pdev;
+
+ clk = clk_get(&pdev->dev, "t0_clk");
+ if (IS_ERR(clk)) {
+ kfree(tc);
+ return -EINVAL;
+ }
+
+ tc->clk[0] = clk;
+ tc->clk[1] = clk_get(&pdev->dev, "t1_clk");
+ if (IS_ERR(tc->clk[1]))
+ tc->clk[1] = clk;
+ tc->clk[2] = clk_get(&pdev->dev, "t2_clk");
+ if (IS_ERR(tc->clk[2]))
+ tc->clk[2] = clk;
+
+ tc->irq[0] = irq;
+ tc->irq[1] = platform_get_irq(pdev, 1);
+ if (tc->irq[1] < 0)
+ tc->irq[1] = irq;
+ tc->irq[2] = platform_get_irq(pdev, 2);
+ if (tc->irq[2] < 0)
+ tc->irq[2] = irq;
+
+ spin_lock(&tc_list_lock);
+ list_add_tail(&tc->node, &tc_list);
+ spin_unlock(&tc_list_lock);
+
+ return 0;
+}
+
+static struct platform_driver tc_driver = {
+ .driver.name = "atmel_tcb",
+};
+
+static int __init tc_init(void)
+{
+ return platform_driver_probe(&tc_driver, tc_probe);
+}
+arch_initcall(tc_init);
* Looks through the list of registered enclosures to see
* if it can find a match for a device. Returns NULL if no
* enclosure is found. Obtains a reference to the enclosure class
- * device which must be released with class_device_put().
+ * device which must be released with device_put().
*/
struct enclosure_device *enclosure_find(struct device *dev)
{
- struct enclosure_device *edev = NULL;
+ struct enclosure_device *edev;
mutex_lock(&container_list_lock);
list_for_each_entry(edev, &container_list, node) {
- if (edev->cdev.dev == dev) {
- class_device_get(&edev->cdev);
+ if (edev->edev.parent == dev) {
+ get_device(&edev->edev);
mutex_unlock(&container_list_lock);
return edev;
}
edev->components = components;
- edev->cdev.class = &enclosure_class;
- edev->cdev.dev = get_device(dev);
+ edev->edev.class = &enclosure_class;
+ edev->edev.parent = get_device(dev);
edev->cb = cb;
- snprintf(edev->cdev.class_id, BUS_ID_SIZE, "%s", name);
- err = class_device_register(&edev->cdev);
+ snprintf(edev->edev.bus_id, BUS_ID_SIZE, "%s", name);
+ err = device_register(&edev->edev);
if (err)
goto err;
return edev;
err:
- put_device(edev->cdev.dev);
+ put_device(edev->edev.parent);
kfree(edev);
return ERR_PTR(err);
}
for (i = 0; i < edev->components; i++)
if (edev->component[i].number != -1)
- class_device_unregister(&edev->component[i].cdev);
+ device_unregister(&edev->component[i].cdev);
/* prevent any callbacks into service user */
edev->cb = &enclosure_null_callbacks;
- class_device_unregister(&edev->cdev);
+ device_unregister(&edev->edev);
}
EXPORT_SYMBOL_GPL(enclosure_unregister);
-static void enclosure_release(struct class_device *cdev)
+static void enclosure_release(struct device *cdev)
{
struct enclosure_device *edev = to_enclosure_device(cdev);
- put_device(cdev->dev);
+ put_device(cdev->parent);
kfree(edev);
}
-static void enclosure_component_release(struct class_device *cdev)
+static void enclosure_component_release(struct device *dev)
{
- if (cdev->dev)
- put_device(cdev->dev);
- class_device_put(cdev->parent);
+ struct enclosure_component *cdev = to_enclosure_component(dev);
+
+ put_device(cdev->dev);
+ put_device(dev->parent);
}
/**
const char *name)
{
struct enclosure_component *ecomp;
- struct class_device *cdev;
+ struct device *cdev;
int err;
if (number >= edev->components)
ecomp->type = type;
ecomp->number = number;
cdev = &ecomp->cdev;
- cdev->parent = class_device_get(&edev->cdev);
+ cdev->parent = get_device(&edev->edev);
cdev->class = &enclosure_component_class;
if (name)
- snprintf(cdev->class_id, BUS_ID_SIZE, "%s", name);
+ snprintf(cdev->bus_id, BUS_ID_SIZE, "%s", name);
else
- snprintf(cdev->class_id, BUS_ID_SIZE, "%u", number);
+ snprintf(cdev->bus_id, BUS_ID_SIZE, "%u", number);
- err = class_device_register(cdev);
+ err = device_register(cdev);
if (err)
ERR_PTR(err);
int enclosure_add_device(struct enclosure_device *edev, int component,
struct device *dev)
{
- struct class_device *cdev;
+ struct enclosure_component *cdev;
if (!edev || component >= edev->components)
return -EINVAL;
- cdev = &edev->component[component].cdev;
+ cdev = &edev->component[component];
- class_device_del(cdev);
- if (cdev->dev)
- put_device(cdev->dev);
+ device_del(&cdev->cdev);
+ put_device(cdev->dev);
cdev->dev = get_device(dev);
- return class_device_add(cdev);
+ return device_add(&cdev->cdev);
}
EXPORT_SYMBOL_GPL(enclosure_add_device);
*/
int enclosure_remove_device(struct enclosure_device *edev, int component)
{
- struct class_device *cdev;
+ struct enclosure_component *cdev;
if (!edev || component >= edev->components)
return -EINVAL;
- cdev = &edev->component[component].cdev;
+ cdev = &edev->component[component];
- class_device_del(cdev);
- if (cdev->dev)
- put_device(cdev->dev);
+ device_del(&cdev->cdev);
+ put_device(cdev->dev);
cdev->dev = NULL;
- return class_device_add(cdev);
+ return device_add(&cdev->cdev);
}
EXPORT_SYMBOL_GPL(enclosure_remove_device);
* sysfs pieces below
*/
-static ssize_t enclosure_show_components(struct class_device *cdev, char *buf)
+static ssize_t enclosure_show_components(struct device *cdev,
+ struct device_attribute *attr,
+ char *buf)
{
struct enclosure_device *edev = to_enclosure_device(cdev);
return snprintf(buf, 40, "%d\n", edev->components);
}
-static struct class_device_attribute enclosure_attrs[] = {
+static struct device_attribute enclosure_attrs[] = {
__ATTR(components, S_IRUGO, enclosure_show_components, NULL),
__ATTR_NULL
};
static struct class enclosure_class = {
.name = "enclosure",
.owner = THIS_MODULE,
- .release = enclosure_release,
- .class_dev_attrs = enclosure_attrs,
+ .dev_release = enclosure_release,
+ .dev_attrs = enclosure_attrs,
};
static const char *const enclosure_status [] = {
[ENCLOSURE_COMPONENT_ARRAY_DEVICE] = "array device",
};
-static ssize_t get_component_fault(struct class_device *cdev, char *buf)
+static ssize_t get_component_fault(struct device *cdev,
+ struct device_attribute *attr, char *buf)
{
struct enclosure_device *edev = to_enclosure_device(cdev->parent);
struct enclosure_component *ecomp = to_enclosure_component(cdev);
return snprintf(buf, 40, "%d\n", ecomp->fault);
}
-static ssize_t set_component_fault(struct class_device *cdev, const char *buf,
- size_t count)
+static ssize_t set_component_fault(struct device *cdev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
struct enclosure_device *edev = to_enclosure_device(cdev->parent);
struct enclosure_component *ecomp = to_enclosure_component(cdev);
return count;
}
-static ssize_t get_component_status(struct class_device *cdev, char *buf)
+static ssize_t get_component_status(struct device *cdev,
+ struct device_attribute *attr,char *buf)
{
struct enclosure_device *edev = to_enclosure_device(cdev->parent);
struct enclosure_component *ecomp = to_enclosure_component(cdev);
return snprintf(buf, 40, "%s\n", enclosure_status[ecomp->status]);
}
-static ssize_t set_component_status(struct class_device *cdev, const char *buf,
- size_t count)
+static ssize_t set_component_status(struct device *cdev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
struct enclosure_device *edev = to_enclosure_device(cdev->parent);
struct enclosure_component *ecomp = to_enclosure_component(cdev);
return -EINVAL;
}
-static ssize_t get_component_active(struct class_device *cdev, char *buf)
+static ssize_t get_component_active(struct device *cdev,
+ struct device_attribute *attr, char *buf)
{
struct enclosure_device *edev = to_enclosure_device(cdev->parent);
struct enclosure_component *ecomp = to_enclosure_component(cdev);
return snprintf(buf, 40, "%d\n", ecomp->active);
}
-static ssize_t set_component_active(struct class_device *cdev, const char *buf,
- size_t count)
+static ssize_t set_component_active(struct device *cdev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
struct enclosure_device *edev = to_enclosure_device(cdev->parent);
struct enclosure_component *ecomp = to_enclosure_component(cdev);
return count;
}
-static ssize_t get_component_locate(struct class_device *cdev, char *buf)
+static ssize_t get_component_locate(struct device *cdev,
+ struct device_attribute *attr, char *buf)
{
struct enclosure_device *edev = to_enclosure_device(cdev->parent);
struct enclosure_component *ecomp = to_enclosure_component(cdev);
return snprintf(buf, 40, "%d\n", ecomp->locate);
}
-static ssize_t set_component_locate(struct class_device *cdev, const char *buf,
- size_t count)
+static ssize_t set_component_locate(struct device *cdev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
struct enclosure_device *edev = to_enclosure_device(cdev->parent);
struct enclosure_component *ecomp = to_enclosure_component(cdev);
return count;
}
-static ssize_t get_component_type(struct class_device *cdev, char *buf)
+static ssize_t get_component_type(struct device *cdev,
+ struct device_attribute *attr, char *buf)
{
struct enclosure_component *ecomp = to_enclosure_component(cdev);
}
-static struct class_device_attribute enclosure_component_attrs[] = {
+static struct device_attribute enclosure_component_attrs[] = {
__ATTR(fault, S_IRUGO | S_IWUSR, get_component_fault,
set_component_fault),
__ATTR(status, S_IRUGO | S_IWUSR, get_component_status,
static struct class enclosure_component_class = {
.name = "enclosure_component",
.owner = THIS_MODULE,
- .class_dev_attrs = enclosure_component_attrs,
- .release = enclosure_component_release,
+ .dev_attrs = enclosure_component_attrs,
+ .dev_release = enclosure_component_release,
};
static int __init enclosure_init(void)
return 0;
}
-const static struct acpi_device_id intel_menlow_memory_ids[] = {
+static const struct acpi_device_id intel_menlow_memory_ids[] = {
{"INT0002", 0},
{"", 0},
};
--- /dev/null
+#
+# Makefile for SGI's XP devices.
+#
+
+obj-$(CONFIG_SGI_XP) += xp.o
+xp-y := xp_main.o xp_nofault.o
+
+obj-$(CONFIG_SGI_XP) += xpc.o
+xpc-y := xpc_main.o xpc_channel.o xpc_partition.o
+
+obj-$(CONFIG_SGI_XP) += xpnet.o
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2004-2005 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2004-2008 Silicon Graphics, Inc. All rights reserved.
*/
-
/*
* External Cross Partition (XP) structures and defines.
*/
-
-#ifndef _ASM_IA64_SN_XP_H
-#define _ASM_IA64_SN_XP_H
-
+#ifndef _DRIVERS_MISC_SGIXP_XP_H
+#define _DRIVERS_MISC_SGIXP_XP_H
#include <linux/cache.h>
#include <linux/hardirq.h>
#include <asm/sn/types.h>
#include <asm/sn/bte.h>
-
#ifdef USE_DBUG_ON
#define DBUG_ON(condition) BUG_ON(condition)
#else
#define DBUG_ON(condition)
#endif
-
/*
* Define the maximum number of logically defined partitions the system
* can support. It is constrained by the maximum number of hardware
*/
#define XP_MAX_PARTITIONS 64
-
/*
* Define the number of u64s required to represent all the C-brick nasids
* as a bitmap. The cross-partition kernel modules deal only with
#define XP_NASID_MASK_BYTES ((XP_MAX_PHYSNODE_ID + 7) / 8)
#define XP_NASID_MASK_WORDS ((XP_MAX_PHYSNODE_ID + 63) / 64)
-
/*
* Wrapper for bte_copy() that should it return a failure status will retry
* the bte_copy() once in the hope that the failure was due to a temporary
bte_result_t ret;
u64 pdst = ia64_tpa(vdst);
-
/*
* Ensure that the physically mapped memory is contiguous.
*
ret = bte_copy(src, pdst, len, mode, notification);
if ((ret != BTE_SUCCESS) && BTE_ERROR_RETRY(ret)) {
- if (!in_interrupt()) {
+ if (!in_interrupt())
cond_resched();
- }
+
ret = bte_copy(src, pdst, len, mode, notification);
}
return ret;
}
-
/*
* XPC establishes channel connections between the local partition and any
* other partition that is currently up. Over these channels, kernel-level
#error XPC_NCHANNELS exceeds MAXIMUM allowed.
#endif
-
/*
* The format of an XPC message is as follows:
*
u64 payload; /* user defined portion of message */
};
-
#define XPC_MSG_PAYLOAD_OFFSET (u64) (&((struct xpc_msg *)0)->payload)
#define XPC_MSG_SIZE(_payload_size) \
L1_CACHE_ALIGN(XPC_MSG_PAYLOAD_OFFSET + (_payload_size))
-
/*
* Define the return values and values passed to user's callout functions.
* (It is important to add new value codes at the end just preceding
/* 115: BTE end */
xpcBteSh2End = xpcBteSh2Start + BTEFAIL_SH2_ALL,
- xpcUnknownReason /* 116: unknown reason -- must be last in list */
+ xpcUnknownReason /* 116: unknown reason - must be last in enum */
};
-
/*
* Define the callout function types used by XPC to update the user on
* connection activity and state changes (via the user function registered by
* =====================+================================+=====================
*/
-typedef void (*xpc_channel_func)(enum xpc_retval reason, partid_t partid,
- int ch_number, void *data, void *key);
-
-typedef void (*xpc_notify_func)(enum xpc_retval reason, partid_t partid,
- int ch_number, void *key);
+typedef void (*xpc_channel_func) (enum xpc_retval reason, partid_t partid,
+ int ch_number, void *data, void *key);
+typedef void (*xpc_notify_func) (enum xpc_retval reason, partid_t partid,
+ int ch_number, void *key);
/*
* The following is a registration entry. There is a global array of these,
*/
struct xpc_registration {
struct mutex mutex;
- xpc_channel_func func; /* function to call */
- void *key; /* pointer to user's key */
- u16 nentries; /* #of msg entries in local msg queue */
- u16 msg_size; /* message queue's message size */
- u32 assigned_limit; /* limit on #of assigned kthreads */
- u32 idle_limit; /* limit on #of idle kthreads */
+ xpc_channel_func func; /* function to call */
+ void *key; /* pointer to user's key */
+ u16 nentries; /* #of msg entries in local msg queue */
+ u16 msg_size; /* message queue's message size */
+ u32 assigned_limit; /* limit on #of assigned kthreads */
+ u32 idle_limit; /* limit on #of idle kthreads */
} ____cacheline_aligned;
-
#define XPC_CHANNEL_REGISTERED(_c) (xpc_registrations[_c].func != NULL)
-
/* the following are valid xpc_allocate() flags */
-#define XPC_WAIT 0 /* wait flag */
-#define XPC_NOWAIT 1 /* no wait flag */
-
+#define XPC_WAIT 0 /* wait flag */
+#define XPC_NOWAIT 1 /* no wait flag */
struct xpc_interface {
- void (*connect)(int);
- void (*disconnect)(int);
- enum xpc_retval (*allocate)(partid_t, int, u32, void **);
- enum xpc_retval (*send)(partid_t, int, void *);
- enum xpc_retval (*send_notify)(partid_t, int, void *,
- xpc_notify_func, void *);
- void (*received)(partid_t, int, void *);
- enum xpc_retval (*partid_to_nasids)(partid_t, void *);
+ void (*connect) (int);
+ void (*disconnect) (int);
+ enum xpc_retval (*allocate) (partid_t, int, u32, void **);
+ enum xpc_retval (*send) (partid_t, int, void *);
+ enum xpc_retval (*send_notify) (partid_t, int, void *,
+ xpc_notify_func, void *);
+ void (*received) (partid_t, int, void *);
+ enum xpc_retval (*partid_to_nasids) (partid_t, void *);
};
-
extern struct xpc_interface xpc_interface;
extern void xpc_set_interface(void (*)(int),
- void (*)(int),
- enum xpc_retval (*)(partid_t, int, u32, void **),
- enum xpc_retval (*)(partid_t, int, void *),
- enum xpc_retval (*)(partid_t, int, void *, xpc_notify_func,
- void *),
- void (*)(partid_t, int, void *),
- enum xpc_retval (*)(partid_t, void *));
+ void (*)(int),
+ enum xpc_retval (*)(partid_t, int, u32, void **),
+ enum xpc_retval (*)(partid_t, int, void *),
+ enum xpc_retval (*)(partid_t, int, void *,
+ xpc_notify_func, void *),
+ void (*)(partid_t, int, void *),
+ enum xpc_retval (*)(partid_t, void *));
extern void xpc_clear_interface(void);
-
extern enum xpc_retval xpc_connect(int, xpc_channel_func, void *, u16,
- u16, u32, u32);
+ u16, u32, u32);
extern void xpc_disconnect(int);
static inline enum xpc_retval
static inline enum xpc_retval
xpc_send_notify(partid_t partid, int ch_number, void *payload,
- xpc_notify_func func, void *key)
+ xpc_notify_func func, void *key)
{
return xpc_interface.send_notify(partid, ch_number, payload, func, key);
}
return xpc_interface.partid_to_nasids(partid, nasids);
}
-
extern u64 xp_nofault_PIOR_target;
extern int xp_nofault_PIOR(void *);
extern int xp_error_PIOR(void);
-
-#endif /* _ASM_IA64_SN_XP_H */
-
+#endif /* _DRIVERS_MISC_SGIXP_XP_H */
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (c) 2004-2005 Silicon Graphics, Inc. All Rights Reserved.
+ * Copyright (c) 2004-2008 Silicon Graphics, Inc. All Rights Reserved.
*/
-
/*
* Cross Partition (XP) base.
*
*
*/
-
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <asm/sn/intr.h>
#include <asm/sn/sn_sal.h>
-#include <asm/sn/xp.h>
-
+#include "xp.h"
/*
- * Target of nofault PIO read.
+ * The export of xp_nofault_PIOR needs to happen here since it is defined
+ * in drivers/misc/sgi-xp/xp_nofault.S. The target of the nofault read is
+ * defined here.
*/
-u64 xp_nofault_PIOR_target;
+EXPORT_SYMBOL_GPL(xp_nofault_PIOR);
+u64 xp_nofault_PIOR_target;
+EXPORT_SYMBOL_GPL(xp_nofault_PIOR_target);
/*
* xpc_registrations[] keeps track of xpc_connect()'s done by the kernel-level
* users of XPC.
*/
struct xpc_registration xpc_registrations[XPC_NCHANNELS];
-
+EXPORT_SYMBOL_GPL(xpc_registrations);
/*
* Initialize the XPC interface to indicate that XPC isn't loaded.
*/
-static enum xpc_retval xpc_notloaded(void) { return xpcNotLoaded; }
+static enum xpc_retval
+xpc_notloaded(void)
+{
+ return xpcNotLoaded;
+}
struct xpc_interface xpc_interface = {
- (void (*)(int)) xpc_notloaded,
- (void (*)(int)) xpc_notloaded,
- (enum xpc_retval (*)(partid_t, int, u32, void **)) xpc_notloaded,
- (enum xpc_retval (*)(partid_t, int, void *)) xpc_notloaded,
- (enum xpc_retval (*)(partid_t, int, void *, xpc_notify_func, void *))
- xpc_notloaded,
- (void (*)(partid_t, int, void *)) xpc_notloaded,
- (enum xpc_retval (*)(partid_t, void *)) xpc_notloaded
+ (void (*)(int))xpc_notloaded,
+ (void (*)(int))xpc_notloaded,
+ (enum xpc_retval(*)(partid_t, int, u32, void **))xpc_notloaded,
+ (enum xpc_retval(*)(partid_t, int, void *))xpc_notloaded,
+ (enum xpc_retval(*)(partid_t, int, void *, xpc_notify_func, void *))
+ xpc_notloaded,
+ (void (*)(partid_t, int, void *))xpc_notloaded,
+ (enum xpc_retval(*)(partid_t, void *))xpc_notloaded
};
-
+EXPORT_SYMBOL_GPL(xpc_interface);
/*
* XPC calls this when it (the XPC module) has been loaded.
*/
void
-xpc_set_interface(void (*connect)(int),
- void (*disconnect)(int),
- enum xpc_retval (*allocate)(partid_t, int, u32, void **),
- enum xpc_retval (*send)(partid_t, int, void *),
- enum xpc_retval (*send_notify)(partid_t, int, void *,
- xpc_notify_func, void *),
- void (*received)(partid_t, int, void *),
- enum xpc_retval (*partid_to_nasids)(partid_t, void *))
+xpc_set_interface(void (*connect) (int),
+ void (*disconnect) (int),
+ enum xpc_retval (*allocate) (partid_t, int, u32, void **),
+ enum xpc_retval (*send) (partid_t, int, void *),
+ enum xpc_retval (*send_notify) (partid_t, int, void *,
+ xpc_notify_func, void *),
+ void (*received) (partid_t, int, void *),
+ enum xpc_retval (*partid_to_nasids) (partid_t, void *))
{
xpc_interface.connect = connect;
xpc_interface.disconnect = disconnect;
xpc_interface.received = received;
xpc_interface.partid_to_nasids = partid_to_nasids;
}
-
+EXPORT_SYMBOL_GPL(xpc_set_interface);
/*
* XPC calls this when it (the XPC module) is being unloaded.
void
xpc_clear_interface(void)
{
- xpc_interface.connect = (void (*)(int)) xpc_notloaded;
- xpc_interface.disconnect = (void (*)(int)) xpc_notloaded;
- xpc_interface.allocate = (enum xpc_retval (*)(partid_t, int, u32,
- void **)) xpc_notloaded;
- xpc_interface.send = (enum xpc_retval (*)(partid_t, int, void *))
- xpc_notloaded;
- xpc_interface.send_notify = (enum xpc_retval (*)(partid_t, int, void *,
- xpc_notify_func, void *)) xpc_notloaded;
+ xpc_interface.connect = (void (*)(int))xpc_notloaded;
+ xpc_interface.disconnect = (void (*)(int))xpc_notloaded;
+ xpc_interface.allocate = (enum xpc_retval(*)(partid_t, int, u32,
+ void **))xpc_notloaded;
+ xpc_interface.send = (enum xpc_retval(*)(partid_t, int, void *))
+ xpc_notloaded;
+ xpc_interface.send_notify = (enum xpc_retval(*)(partid_t, int, void *,
+ xpc_notify_func,
+ void *))xpc_notloaded;
xpc_interface.received = (void (*)(partid_t, int, void *))
- xpc_notloaded;
- xpc_interface.partid_to_nasids = (enum xpc_retval (*)(partid_t, void *))
- xpc_notloaded;
+ xpc_notloaded;
+ xpc_interface.partid_to_nasids = (enum xpc_retval(*)(partid_t, void *))
+ xpc_notloaded;
}
-
+EXPORT_SYMBOL_GPL(xpc_clear_interface);
/*
* Register for automatic establishment of a channel connection whenever
*/
enum xpc_retval
xpc_connect(int ch_number, xpc_channel_func func, void *key, u16 payload_size,
- u16 nentries, u32 assigned_limit, u32 idle_limit)
+ u16 nentries, u32 assigned_limit, u32 idle_limit)
{
struct xpc_registration *registration;
-
DBUG_ON(ch_number < 0 || ch_number >= XPC_NCHANNELS);
DBUG_ON(payload_size == 0 || nentries == 0);
DBUG_ON(func == NULL);
registration = &xpc_registrations[ch_number];
- if (mutex_lock_interruptible(®istration->mutex) != 0) {
+ if (mutex_lock_interruptible(®istration->mutex) != 0)
return xpcInterrupted;
- }
/* if XPC_CHANNEL_REGISTERED(ch_number) */
if (registration->func != NULL) {
return xpcSuccess;
}
-
+EXPORT_SYMBOL_GPL(xpc_connect);
/*
* Remove the registration for automatic connection of the specified channel
{
struct xpc_registration *registration;
-
DBUG_ON(ch_number < 0 || ch_number >= XPC_NCHANNELS);
registration = &xpc_registrations[ch_number];
return;
}
-
+EXPORT_SYMBOL_GPL(xpc_disconnect);
int __init
xp_init(void)
{
int ret, ch_number;
- u64 func_addr = *(u64 *) xp_nofault_PIOR;
- u64 err_func_addr = *(u64 *) xp_error_PIOR;
+ u64 func_addr = *(u64 *)xp_nofault_PIOR;
+ u64 err_func_addr = *(u64 *)xp_error_PIOR;
-
- if (!ia64_platform_is("sn2")) {
+ if (!ia64_platform_is("sn2"))
return -ENODEV;
- }
/*
* Register a nofault code region which performs a cross-partition
* least some CPUs on Shubs <= v1.2, which unfortunately we have to
* work around).
*/
- if ((ret = sn_register_nofault_code(func_addr, err_func_addr,
- err_func_addr, 1, 1)) != 0) {
+ ret = sn_register_nofault_code(func_addr, err_func_addr, err_func_addr,
+ 1, 1);
+ if (ret != 0) {
printk(KERN_ERR "XP: can't register nofault code, error=%d\n",
- ret);
+ ret);
}
/*
* Setup the nofault PIO read target. (There is no special reason why
* SH_IPI_ACCESS was selected.)
*/
- if (is_shub2()) {
+ if (is_shub2())
xp_nofault_PIOR_target = SH2_IPI_ACCESS0;
- } else {
+ else
xp_nofault_PIOR_target = SH1_IPI_ACCESS;
- }
/* initialize the connection registration mutex */
- for (ch_number = 0; ch_number < XPC_NCHANNELS; ch_number++) {
+ for (ch_number = 0; ch_number < XPC_NCHANNELS; ch_number++)
mutex_init(&xpc_registrations[ch_number].mutex);
- }
return 0;
}
-module_init(xp_init);
+module_init(xp_init);
void __exit
xp_exit(void)
{
- u64 func_addr = *(u64 *) xp_nofault_PIOR;
- u64 err_func_addr = *(u64 *) xp_error_PIOR;
-
+ u64 func_addr = *(u64 *)xp_nofault_PIOR;
+ u64 err_func_addr = *(u64 *)xp_error_PIOR;
/* unregister the PIO read nofault code region */
- (void) sn_register_nofault_code(func_addr, err_func_addr,
- err_func_addr, 1, 0);
+ (void)sn_register_nofault_code(func_addr, err_func_addr,
+ err_func_addr, 1, 0);
}
-module_exit(xp_exit);
+module_exit(xp_exit);
MODULE_AUTHOR("Silicon Graphics, Inc.");
MODULE_DESCRIPTION("Cross Partition (XP) base");
MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(xp_nofault_PIOR);
-EXPORT_SYMBOL(xp_nofault_PIOR_target);
-EXPORT_SYMBOL(xpc_registrations);
-EXPORT_SYMBOL(xpc_interface);
-EXPORT_SYMBOL(xpc_clear_interface);
-EXPORT_SYMBOL(xpc_set_interface);
-EXPORT_SYMBOL(xpc_connect);
-EXPORT_SYMBOL(xpc_disconnect);
-
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (c) 2004-2007 Silicon Graphics, Inc. All Rights Reserved.
+ * Copyright (c) 2004-2008 Silicon Graphics, Inc. All Rights Reserved.
*/
-
/*
* The xp_nofault_PIOR function takes a pointer to a remote PIO register
* and attempts to load and consume a value from it. This function
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (c) 2004-2007 Silicon Graphics, Inc. All Rights Reserved.
+ * Copyright (c) 2004-2008 Silicon Graphics, Inc. All Rights Reserved.
*/
-
/*
* Cross Partition Communication (XPC) structures and macros.
*/
-#ifndef _ASM_IA64_SN_XPC_H
-#define _ASM_IA64_SN_XPC_H
-
+#ifndef _DRIVERS_MISC_SGIXP_XPC_H
+#define _DRIVERS_MISC_SGIXP_XPC_H
#include <linux/interrupt.h>
#include <linux/sysctl.h>
#include <asm/sn/addrs.h>
#include <asm/sn/mspec.h>
#include <asm/sn/shub_mmr.h>
-#include <asm/sn/xp.h>
-
+#include "xp.h"
/*
* XPC Version numbers consist of a major and minor number. XPC can always
#define XPC_VERSION_MAJOR(_v) ((_v) >> 4)
#define XPC_VERSION_MINOR(_v) ((_v) & 0xf)
-
/*
* The next macros define word or bit representations for given
* C-brick nasid in either the SAL provided bit array representing
/* define the process name of the discovery thread */
#define XPC_DISCOVERY_THREAD_NAME "xpc_discovery"
-
/*
* the reserved page
*
u8 partid; /* SAL: partition ID */
u8 version;
u8 pad1[6]; /* align to next u64 in cacheline */
- volatile u64 vars_pa;
+ u64 vars_pa; /* physical address of struct xpc_vars */
struct timespec stamp; /* time when reserved page was setup by XPC */
u64 pad2[9]; /* align to last u64 in cacheline */
u64 nasids_size; /* SAL: size of each nasid mask in bytes */
};
-#define XPC_RP_VERSION _XPC_VERSION(1,1) /* version 1.1 of the reserved page */
+#define XPC_RP_VERSION _XPC_VERSION(1, 1) /* version 1.1 of the reserved page */
#define XPC_SUPPORTS_RP_STAMP(_version) \
- (_version >= _XPC_VERSION(1,1))
+ (_version >= _XPC_VERSION(1, 1))
/*
* compare stamps - the return value is:
{
int ret;
-
- if ((ret = stamp1->tv_sec - stamp2->tv_sec) == 0) {
+ ret = stamp1->tv_sec - stamp2->tv_sec;
+ if (ret == 0)
ret = stamp1->tv_nsec - stamp2->tv_nsec;
- }
+
return ret;
}
-
/*
* Define the structures by which XPC variables can be exported to other
* partitions. (There are two: struct xpc_vars and struct xpc_vars_part)
AMO_t *amos_page; /* vaddr of page of AMOs from MSPEC driver */
};
-#define XPC_V_VERSION _XPC_VERSION(3,1) /* version 3.1 of the cross vars */
+#define XPC_V_VERSION _XPC_VERSION(3, 1) /* version 3.1 of the cross vars */
#define XPC_SUPPORTS_DISENGAGE_REQUEST(_version) \
- (_version >= _XPC_VERSION(3,1))
-
+ (_version >= _XPC_VERSION(3, 1))
static inline int
xpc_hb_allowed(partid_t partid, struct xpc_vars *vars)
old_mask = vars->heartbeating_to_mask;
new_mask = (old_mask | (1UL << partid));
} while (cmpxchg(&vars->heartbeating_to_mask, old_mask, new_mask) !=
- old_mask);
+ old_mask);
}
static inline void
old_mask = vars->heartbeating_to_mask;
new_mask = (old_mask & ~(1UL << partid));
} while (cmpxchg(&vars->heartbeating_to_mask, old_mask, new_mask) !=
- old_mask);
+ old_mask);
}
-
/*
* The AMOs page consists of a number of AMO variables which are divided into
* four groups, The first two groups are used to identify an IRQ's sender.
#define XPC_ENGAGED_PARTITIONS_AMO (XPC_ACTIVATE_IRQ_AMOS + XP_NASID_MASK_WORDS)
#define XPC_DISENGAGE_REQUEST_AMO (XPC_ENGAGED_PARTITIONS_AMO + 1)
-
/*
* The following structure describes the per partition specific variables.
*
* occupies half a cacheline.
*/
struct xpc_vars_part {
- volatile u64 magic;
+ u64 magic;
u64 openclose_args_pa; /* physical address of open and close args */
u64 GPs_pa; /* physical address of Get/Put values */
* MAGIC2 indicates that this partition has pulled the remote partititions
* per partition variables that pertain to this partition.
*/
-#define XPC_VP_MAGIC1 0x0053524156435058L /* 'XPCVARS\0'L (little endian) */
-#define XPC_VP_MAGIC2 0x0073726176435058L /* 'XPCvars\0'L (little endian) */
-
+#define XPC_VP_MAGIC1 0x0053524156435058L /* 'XPCVARS\0'L (little endian) */
+#define XPC_VP_MAGIC2 0x0073726176435058L /* 'XPCvars\0'L (little endian) */
/* the reserved page sizes and offsets */
#define XPC_RP_HEADER_SIZE L1_CACHE_ALIGN(sizeof(struct xpc_rsvd_page))
-#define XPC_RP_VARS_SIZE L1_CACHE_ALIGN(sizeof(struct xpc_vars))
+#define XPC_RP_VARS_SIZE L1_CACHE_ALIGN(sizeof(struct xpc_vars))
-#define XPC_RP_PART_NASIDS(_rp) (u64 *) ((u8 *) _rp + XPC_RP_HEADER_SIZE)
+#define XPC_RP_PART_NASIDS(_rp) ((u64 *)((u8 *)(_rp) + XPC_RP_HEADER_SIZE))
#define XPC_RP_MACH_NASIDS(_rp) (XPC_RP_PART_NASIDS(_rp) + xp_nasid_mask_words)
-#define XPC_RP_VARS(_rp) ((struct xpc_vars *) XPC_RP_MACH_NASIDS(_rp) + xp_nasid_mask_words)
-#define XPC_RP_VARS_PART(_rp) (struct xpc_vars_part *) ((u8 *) XPC_RP_VARS(rp) + XPC_RP_VARS_SIZE)
-
+#define XPC_RP_VARS(_rp) ((struct xpc_vars *)(XPC_RP_MACH_NASIDS(_rp) + \
+ xp_nasid_mask_words))
+#define XPC_RP_VARS_PART(_rp) ((struct xpc_vars_part *) \
+ ((u8 *)XPC_RP_VARS(_rp) + XPC_RP_VARS_SIZE))
/*
* Functions registered by add_timer() or called by kernel_thread() only
#define XPC_UNPACK_ARG1(_args) (((u64) _args) & 0xffffffff)
#define XPC_UNPACK_ARG2(_args) ((((u64) _args) >> 32) & 0xffffffff)
-
-
/*
* Define a Get/Put value pair (pointers) used with a message queue.
*/
struct xpc_gp {
- volatile s64 get; /* Get value */
- volatile s64 put; /* Put value */
+ s64 get; /* Get value */
+ s64 put; /* Put value */
};
#define XPC_GP_SIZE \
L1_CACHE_ALIGN(sizeof(struct xpc_gp) * XPC_NCHANNELS)
-
-
/*
* Define a structure that contains arguments associated with opening and
* closing a channel.
#define XPC_OPENCLOSE_ARGS_SIZE \
L1_CACHE_ALIGN(sizeof(struct xpc_openclose_args) * XPC_NCHANNELS)
-
-
/* struct xpc_msg flags */
#define XPC_M_DONE 0x01 /* msg has been received/consumed */
#define XPC_M_READY 0x02 /* msg is ready to be sent */
#define XPC_M_INTERRUPT 0x04 /* send interrupt when msg consumed */
-
#define XPC_MSG_ADDRESS(_payload) \
((struct xpc_msg *)((u8 *)(_payload) - XPC_MSG_PAYLOAD_OFFSET))
-
-
/*
* Defines notify entry.
*
* and consumed by the intended recipient.
*/
struct xpc_notify {
- volatile u8 type; /* type of notification */
+ u8 type; /* type of notification */
/* the following two fields are only used if type == XPC_N_CALL */
- xpc_notify_func func; /* user's notify function */
- void *key; /* pointer to user's key */
+ xpc_notify_func func; /* user's notify function */
+ void *key; /* pointer to user's key */
};
/* struct xpc_notify type of notification */
#define XPC_N_CALL 0x01 /* notify function provided by user */
-
-
/*
* Define the structure that manages all the stuff required by a channel. In
* particular, they are used to manage the messages sent across the channel.
* messages.
*/
struct xpc_channel {
- partid_t partid; /* ID of remote partition connected */
- spinlock_t lock; /* lock for updating this structure */
- u32 flags; /* general flags */
+ partid_t partid; /* ID of remote partition connected */
+ spinlock_t lock; /* lock for updating this structure */
+ u32 flags; /* general flags */
- enum xpc_retval reason; /* reason why channel is disconnect'g */
- int reason_line; /* line# disconnect initiated from */
+ enum xpc_retval reason; /* reason why channel is disconnect'g */
+ int reason_line; /* line# disconnect initiated from */
- u16 number; /* channel # */
+ u16 number; /* channel # */
- u16 msg_size; /* sizeof each msg entry */
- u16 local_nentries; /* #of msg entries in local msg queue */
- u16 remote_nentries; /* #of msg entries in remote msg queue*/
+ u16 msg_size; /* sizeof each msg entry */
+ u16 local_nentries; /* #of msg entries in local msg queue */
+ u16 remote_nentries; /* #of msg entries in remote msg queue */
void *local_msgqueue_base; /* base address of kmalloc'd space */
struct xpc_msg *local_msgqueue; /* local message queue */
void *remote_msgqueue_base; /* base address of kmalloc'd space */
- struct xpc_msg *remote_msgqueue;/* cached copy of remote partition's */
- /* local message queue */
- u64 remote_msgqueue_pa; /* phys addr of remote partition's */
- /* local message queue */
+ struct xpc_msg *remote_msgqueue; /* cached copy of remote partition's */
+ /* local message queue */
+ u64 remote_msgqueue_pa; /* phys addr of remote partition's */
+ /* local message queue */
- atomic_t references; /* #of external references to queues */
+ atomic_t references; /* #of external references to queues */
- atomic_t n_on_msg_allocate_wq; /* #on msg allocation wait queue */
- wait_queue_head_t msg_allocate_wq; /* msg allocation wait queue */
+ atomic_t n_on_msg_allocate_wq; /* #on msg allocation wait queue */
+ wait_queue_head_t msg_allocate_wq; /* msg allocation wait queue */
- u8 delayed_IPI_flags; /* IPI flags received, but delayed */
- /* action until channel disconnected */
+ u8 delayed_IPI_flags; /* IPI flags received, but delayed */
+ /* action until channel disconnected */
/* queue of msg senders who want to be notified when msg received */
- atomic_t n_to_notify; /* #of msg senders to notify */
- struct xpc_notify *notify_queue;/* notify queue for messages sent */
+ atomic_t n_to_notify; /* #of msg senders to notify */
+ struct xpc_notify *notify_queue; /* notify queue for messages sent */
- xpc_channel_func func; /* user's channel function */
- void *key; /* pointer to user's key */
+ xpc_channel_func func; /* user's channel function */
+ void *key; /* pointer to user's key */
struct mutex msg_to_pull_mutex; /* next msg to pull serialization */
- struct completion wdisconnect_wait; /* wait for channel disconnect */
+ struct completion wdisconnect_wait; /* wait for channel disconnect */
struct xpc_openclose_args *local_openclose_args; /* args passed on */
- /* opening or closing of channel */
+ /* opening or closing of channel */
/* various flavors of local and remote Get/Put values */
struct xpc_gp remote_GP; /* remote Get/Put values */
struct xpc_gp w_local_GP; /* working local Get/Put values */
struct xpc_gp w_remote_GP; /* working remote Get/Put values */
- s64 next_msg_to_pull; /* Put value of next msg to pull */
+ s64 next_msg_to_pull; /* Put value of next msg to pull */
/* kthread management related fields */
-// >>> rethink having kthreads_assigned_limit and kthreads_idle_limit; perhaps
-// >>> allow the assigned limit be unbounded and let the idle limit be dynamic
-// >>> dependent on activity over the last interval of time
atomic_t kthreads_assigned; /* #of kthreads assigned to channel */
- u32 kthreads_assigned_limit; /* limit on #of kthreads assigned */
- atomic_t kthreads_idle; /* #of kthreads idle waiting for work */
+ u32 kthreads_assigned_limit; /* limit on #of kthreads assigned */
+ atomic_t kthreads_idle; /* #of kthreads idle waiting for work */
u32 kthreads_idle_limit; /* limit on #of kthreads idle */
atomic_t kthreads_active; /* #of kthreads actively working */
- // >>> following field is temporary
- u32 kthreads_created; /* total #of kthreads created */
wait_queue_head_t idle_wq; /* idle kthread wait queue */
} ____cacheline_aligned;
-
/* struct xpc_channel flags */
-#define XPC_C_WASCONNECTED 0x00000001 /* channel was connected */
+#define XPC_C_WASCONNECTED 0x00000001 /* channel was connected */
-#define XPC_C_ROPENREPLY 0x00000002 /* remote open channel reply */
-#define XPC_C_OPENREPLY 0x00000004 /* local open channel reply */
-#define XPC_C_ROPENREQUEST 0x00000008 /* remote open channel request */
-#define XPC_C_OPENREQUEST 0x00000010 /* local open channel request */
+#define XPC_C_ROPENREPLY 0x00000002 /* remote open channel reply */
+#define XPC_C_OPENREPLY 0x00000004 /* local open channel reply */
+#define XPC_C_ROPENREQUEST 0x00000008 /* remote open channel request */
+#define XPC_C_OPENREQUEST 0x00000010 /* local open channel request */
#define XPC_C_SETUP 0x00000020 /* channel's msgqueues are alloc'd */
-#define XPC_C_CONNECTEDCALLOUT 0x00000040 /* connected callout initiated */
+#define XPC_C_CONNECTEDCALLOUT 0x00000040 /* connected callout initiated */
#define XPC_C_CONNECTEDCALLOUT_MADE \
- 0x00000080 /* connected callout completed */
-#define XPC_C_CONNECTED 0x00000100 /* local channel is connected */
-#define XPC_C_CONNECTING 0x00000200 /* channel is being connected */
+ 0x00000080 /* connected callout completed */
+#define XPC_C_CONNECTED 0x00000100 /* local channel is connected */
+#define XPC_C_CONNECTING 0x00000200 /* channel is being connected */
-#define XPC_C_RCLOSEREPLY 0x00000400 /* remote close channel reply */
-#define XPC_C_CLOSEREPLY 0x00000800 /* local close channel reply */
-#define XPC_C_RCLOSEREQUEST 0x00001000 /* remote close channel request */
-#define XPC_C_CLOSEREQUEST 0x00002000 /* local close channel request */
+#define XPC_C_RCLOSEREPLY 0x00000400 /* remote close channel reply */
+#define XPC_C_CLOSEREPLY 0x00000800 /* local close channel reply */
+#define XPC_C_RCLOSEREQUEST 0x00001000 /* remote close channel request */
+#define XPC_C_CLOSEREQUEST 0x00002000 /* local close channel request */
-#define XPC_C_DISCONNECTED 0x00004000 /* channel is disconnected */
-#define XPC_C_DISCONNECTING 0x00008000 /* channel is being disconnected */
+#define XPC_C_DISCONNECTED 0x00004000 /* channel is disconnected */
+#define XPC_C_DISCONNECTING 0x00008000 /* channel is being disconnected */
#define XPC_C_DISCONNECTINGCALLOUT \
0x00010000 /* disconnecting callout initiated */
#define XPC_C_DISCONNECTINGCALLOUT_MADE \
0x00020000 /* disconnecting callout completed */
-#define XPC_C_WDISCONNECT 0x00040000 /* waiting for channel disconnect */
-
-
+#define XPC_C_WDISCONNECT 0x00040000 /* waiting for channel disconnect */
/*
* Manages channels on a partition basis. There is one of these structures
/* XPC HB infrastructure */
- u8 remote_rp_version; /* version# of partition's rsvd pg */
- struct timespec remote_rp_stamp;/* time when rsvd pg was initialized */
- u64 remote_rp_pa; /* phys addr of partition's rsvd pg */
- u64 remote_vars_pa; /* phys addr of partition's vars */
+ u8 remote_rp_version; /* version# of partition's rsvd pg */
+ struct timespec remote_rp_stamp; /* time when rsvd pg was initialized */
+ u64 remote_rp_pa; /* phys addr of partition's rsvd pg */
+ u64 remote_vars_pa; /* phys addr of partition's vars */
u64 remote_vars_part_pa; /* phys addr of partition's vars part */
- u64 last_heartbeat; /* HB at last read */
+ u64 last_heartbeat; /* HB at last read */
u64 remote_amos_page_pa; /* phys addr of partition's amos page */
- int remote_act_nasid; /* active part's act/deact nasid */
+ int remote_act_nasid; /* active part's act/deact nasid */
int remote_act_phys_cpuid; /* active part's act/deact phys cpuid */
- u32 act_IRQ_rcvd; /* IRQs since activation */
- spinlock_t act_lock; /* protect updating of act_state */
- u8 act_state; /* from XPC HB viewpoint */
- u8 remote_vars_version; /* version# of partition's vars */
- enum xpc_retval reason; /* reason partition is deactivating */
- int reason_line; /* line# deactivation initiated from */
- int reactivate_nasid; /* nasid in partition to reactivate */
-
- unsigned long disengage_request_timeout; /* timeout in jiffies */
+ u32 act_IRQ_rcvd; /* IRQs since activation */
+ spinlock_t act_lock; /* protect updating of act_state */
+ u8 act_state; /* from XPC HB viewpoint */
+ u8 remote_vars_version; /* version# of partition's vars */
+ enum xpc_retval reason; /* reason partition is deactivating */
+ int reason_line; /* line# deactivation initiated from */
+ int reactivate_nasid; /* nasid in partition to reactivate */
+
+ unsigned long disengage_request_timeout; /* timeout in jiffies */
struct timer_list disengage_request_timer;
-
/* XPC infrastructure referencing and teardown control */
- volatile u8 setup_state; /* infrastructure setup state */
+ u8 setup_state; /* infrastructure setup state */
wait_queue_head_t teardown_wq; /* kthread waiting to teardown infra */
- atomic_t references; /* #of references to infrastructure */
-
+ atomic_t references; /* #of references to infrastructure */
/*
* NONE OF THE PRECEDING FIELDS OF THIS STRUCTURE WILL BE CLEARED WHEN
* 'nchannels' FIELD MUST BE THE FIRST OF THE FIELDS TO BE CLEARED.)
*/
-
- u8 nchannels; /* #of defined channels supported */
- atomic_t nchannels_active; /* #of channels that are not DISCONNECTED */
- atomic_t nchannels_engaged;/* #of channels engaged with remote part */
- struct xpc_channel *channels;/* array of channel structures */
-
- void *local_GPs_base; /* base address of kmalloc'd space */
- struct xpc_gp *local_GPs; /* local Get/Put values */
- void *remote_GPs_base; /* base address of kmalloc'd space */
- struct xpc_gp *remote_GPs;/* copy of remote partition's local Get/Put */
- /* values */
- u64 remote_GPs_pa; /* phys address of remote partition's local */
- /* Get/Put values */
-
+ u8 nchannels; /* #of defined channels supported */
+ atomic_t nchannels_active; /* #of channels that are not DISCONNECTED */
+ atomic_t nchannels_engaged; /* #of channels engaged with remote part */
+ struct xpc_channel *channels; /* array of channel structures */
+
+ void *local_GPs_base; /* base address of kmalloc'd space */
+ struct xpc_gp *local_GPs; /* local Get/Put values */
+ void *remote_GPs_base; /* base address of kmalloc'd space */
+ struct xpc_gp *remote_GPs; /* copy of remote partition's local */
+ /* Get/Put values */
+ u64 remote_GPs_pa; /* phys address of remote partition's local */
+ /* Get/Put values */
/* fields used to pass args when opening or closing a channel */
- void *local_openclose_args_base; /* base address of kmalloc'd space */
- struct xpc_openclose_args *local_openclose_args; /* local's args */
- void *remote_openclose_args_base; /* base address of kmalloc'd space */
+ void *local_openclose_args_base; /* base address of kmalloc'd space */
+ struct xpc_openclose_args *local_openclose_args; /* local's args */
+ void *remote_openclose_args_base; /* base address of kmalloc'd space */
struct xpc_openclose_args *remote_openclose_args; /* copy of remote's */
- /* args */
- u64 remote_openclose_args_pa; /* phys addr of remote's args */
-
+ /* args */
+ u64 remote_openclose_args_pa; /* phys addr of remote's args */
/* IPI sending, receiving and handling related fields */
- int remote_IPI_nasid; /* nasid of where to send IPIs */
- int remote_IPI_phys_cpuid; /* phys CPU ID of where to send IPIs */
- AMO_t *remote_IPI_amo_va; /* address of remote IPI AMO_t structure */
-
- AMO_t *local_IPI_amo_va; /* address of IPI AMO_t structure */
- u64 local_IPI_amo; /* IPI amo flags yet to be handled */
- char IPI_owner[8]; /* IPI owner's name */
- struct timer_list dropped_IPI_timer; /* dropped IPI timer */
+ int remote_IPI_nasid; /* nasid of where to send IPIs */
+ int remote_IPI_phys_cpuid; /* phys CPU ID of where to send IPIs */
+ AMO_t *remote_IPI_amo_va; /* address of remote IPI AMO_t structure */
- spinlock_t IPI_lock; /* IPI handler lock */
+ AMO_t *local_IPI_amo_va; /* address of IPI AMO_t structure */
+ u64 local_IPI_amo; /* IPI amo flags yet to be handled */
+ char IPI_owner[8]; /* IPI owner's name */
+ struct timer_list dropped_IPI_timer; /* dropped IPI timer */
+ spinlock_t IPI_lock; /* IPI handler lock */
/* channel manager related fields */
atomic_t channel_mgr_requests; /* #of requests to activate chan mgr */
- wait_queue_head_t channel_mgr_wq; /* channel mgr's wait queue */
+ wait_queue_head_t channel_mgr_wq; /* channel mgr's wait queue */
} ____cacheline_aligned;
-
/* struct xpc_partition act_state values (for XPC HB) */
#define XPC_P_INACTIVE 0x00 /* partition is not active */
#define XPC_P_ACTIVE 0x03 /* xpc_partition_up() was called */
#define XPC_P_DEACTIVATING 0x04 /* partition deactivation initiated */
-
#define XPC_DEACTIVATE_PARTITION(_p, _reason) \
xpc_deactivate_partition(__LINE__, (_p), (_reason))
-
/* struct xpc_partition setup_state values */
#define XPC_P_UNSET 0x00 /* infrastructure was never setup */
#define XPC_P_WTEARDOWN 0x02 /* waiting to teardown infrastructure */
#define XPC_P_TORNDOWN 0x03 /* infrastructure is torndown */
-
-
/*
* struct xpc_partition IPI_timer #of seconds to wait before checking for
* dropped IPIs. These occur whenever an IPI amo write doesn't complete until
*/
#define XPC_P_DROPPED_IPI_WAIT (0.25 * HZ)
-
/* number of seconds to wait for other partitions to disengage */
#define XPC_DISENGAGE_REQUEST_DEFAULT_TIMELIMIT 90
/* interval in seconds to print 'waiting disengagement' messages */
#define XPC_DISENGAGE_PRINTMSG_INTERVAL 10
-
#define XPC_PARTID(_p) ((partid_t) ((_p) - &xpc_partitions[0]))
-
-
/* found in xp_main.c */
extern struct xpc_registration xpc_registrations[];
-
/* found in xpc_main.c */
extern struct device *xpc_part;
extern struct device *xpc_chan;
extern void xpc_create_kthreads(struct xpc_channel *, int, int);
extern void xpc_disconnect_wait(int);
-
/* found in xpc_partition.c */
extern int xpc_exiting;
extern struct xpc_vars *xpc_vars;
extern void xpc_discovery(void);
extern void xpc_check_remote_hb(void);
extern void xpc_deactivate_partition(const int, struct xpc_partition *,
- enum xpc_retval);
+ enum xpc_retval);
extern enum xpc_retval xpc_initiate_partid_to_nasids(partid_t, void *);
-
/* found in xpc_channel.c */
extern void xpc_initiate_connect(int);
extern void xpc_initiate_disconnect(int);
extern void xpc_connected_callout(struct xpc_channel *);
extern void xpc_deliver_msg(struct xpc_channel *);
extern void xpc_disconnect_channel(const int, struct xpc_channel *,
- enum xpc_retval, unsigned long *);
+ enum xpc_retval, unsigned long *);
extern void xpc_disconnect_callout(struct xpc_channel *, enum xpc_retval);
extern void xpc_partition_going_down(struct xpc_partition *, enum xpc_retval);
extern void xpc_teardown_infrastructure(struct xpc_partition *);
-
-
static inline void
xpc_wakeup_channel_mgr(struct xpc_partition *part)
{
- if (atomic_inc_return(&part->channel_mgr_requests) == 1) {
+ if (atomic_inc_return(&part->channel_mgr_requests) == 1)
wake_up(&part->channel_mgr_wq);
- }
}
-
-
/*
* These next two inlines are used to keep us from tearing down a channel's
* msg queues while a thread may be referencing them.
s32 refs = atomic_dec_return(&ch->references);
DBUG_ON(refs < 0);
- if (refs == 0) {
+ if (refs == 0)
xpc_wakeup_channel_mgr(&xpc_partitions[ch->partid]);
- }
}
-
-
#define XPC_DISCONNECT_CHANNEL(_ch, _reason, _irqflgs) \
xpc_disconnect_channel(__LINE__, _ch, _reason, _irqflgs)
-
/*
* These two inlines are used to keep us from tearing down a partition's
* setup infrastructure while a thread may be referencing it.
{
s32 refs = atomic_dec_return(&part->references);
-
DBUG_ON(refs < 0);
- if (refs == 0 && part->setup_state == XPC_P_WTEARDOWN) {
+ if (refs == 0 && part->setup_state == XPC_P_WTEARDOWN)
wake_up(&part->teardown_wq);
- }
}
static inline int
{
int setup;
-
atomic_inc(&part->references);
setup = (part->setup_state == XPC_P_SETUP);
- if (!setup) {
+ if (!setup)
xpc_part_deref(part);
- }
+
return setup;
}
-
-
/*
* The following macro is to be used for the setting of the reason and
* reason_line fields in both the struct xpc_channel and struct xpc_partition
(_p)->reason_line = _line; \
}
-
-
/*
* This next set of inlines are used to keep track of when a partition is
* potentially engaged in accessing memory belonging to another partition.
xpc_mark_partition_engaged(struct xpc_partition *part)
{
unsigned long irq_flags;
- AMO_t *amo = (AMO_t *) __va(part->remote_amos_page_pa +
- (XPC_ENGAGED_PARTITIONS_AMO * sizeof(AMO_t)));
-
+ AMO_t *amo = (AMO_t *)__va(part->remote_amos_page_pa +
+ (XPC_ENGAGED_PARTITIONS_AMO *
+ sizeof(AMO_t)));
local_irq_save(irq_flags);
/* set bit corresponding to our partid in remote partition's AMO */
- FETCHOP_STORE_OP(TO_AMO((u64) &amo->variable), FETCHOP_OR,
- (1UL << sn_partition_id));
+ FETCHOP_STORE_OP(TO_AMO((u64)&amo->variable), FETCHOP_OR,
+ (1UL << sn_partition_id));
/*
* We must always use the nofault function regardless of whether we
* are on a Shub 1.1 system or a Shub 1.2 slice 0xc processor. If we
* didn't, we'd never know that the other partition is down and would
* keep sending IPIs and AMOs to it until the heartbeat times out.
*/
- (void) xp_nofault_PIOR((u64 *) GLOBAL_MMR_ADDR(NASID_GET(&amo->
- variable), xp_nofault_PIOR_target));
+ (void)xp_nofault_PIOR((u64 *)GLOBAL_MMR_ADDR(NASID_GET(&amo->
+ variable),
+ xp_nofault_PIOR_target));
local_irq_restore(irq_flags);
}
xpc_mark_partition_disengaged(struct xpc_partition *part)
{
unsigned long irq_flags;
- AMO_t *amo = (AMO_t *) __va(part->remote_amos_page_pa +
- (XPC_ENGAGED_PARTITIONS_AMO * sizeof(AMO_t)));
-
+ AMO_t *amo = (AMO_t *)__va(part->remote_amos_page_pa +
+ (XPC_ENGAGED_PARTITIONS_AMO *
+ sizeof(AMO_t)));
local_irq_save(irq_flags);
/* clear bit corresponding to our partid in remote partition's AMO */
- FETCHOP_STORE_OP(TO_AMO((u64) &amo->variable), FETCHOP_AND,
- ~(1UL << sn_partition_id));
+ FETCHOP_STORE_OP(TO_AMO((u64)&amo->variable), FETCHOP_AND,
+ ~(1UL << sn_partition_id));
/*
* We must always use the nofault function regardless of whether we
* are on a Shub 1.1 system or a Shub 1.2 slice 0xc processor. If we
* didn't, we'd never know that the other partition is down and would
* keep sending IPIs and AMOs to it until the heartbeat times out.
*/
- (void) xp_nofault_PIOR((u64 *) GLOBAL_MMR_ADDR(NASID_GET(&amo->
- variable), xp_nofault_PIOR_target));
+ (void)xp_nofault_PIOR((u64 *)GLOBAL_MMR_ADDR(NASID_GET(&amo->
+ variable),
+ xp_nofault_PIOR_target));
local_irq_restore(irq_flags);
}
xpc_request_partition_disengage(struct xpc_partition *part)
{
unsigned long irq_flags;
- AMO_t *amo = (AMO_t *) __va(part->remote_amos_page_pa +
- (XPC_DISENGAGE_REQUEST_AMO * sizeof(AMO_t)));
-
+ AMO_t *amo = (AMO_t *)__va(part->remote_amos_page_pa +
+ (XPC_DISENGAGE_REQUEST_AMO * sizeof(AMO_t)));
local_irq_save(irq_flags);
/* set bit corresponding to our partid in remote partition's AMO */
- FETCHOP_STORE_OP(TO_AMO((u64) &amo->variable), FETCHOP_OR,
- (1UL << sn_partition_id));
+ FETCHOP_STORE_OP(TO_AMO((u64)&amo->variable), FETCHOP_OR,
+ (1UL << sn_partition_id));
/*
* We must always use the nofault function regardless of whether we
* are on a Shub 1.1 system or a Shub 1.2 slice 0xc processor. If we
* didn't, we'd never know that the other partition is down and would
* keep sending IPIs and AMOs to it until the heartbeat times out.
*/
- (void) xp_nofault_PIOR((u64 *) GLOBAL_MMR_ADDR(NASID_GET(&amo->
- variable), xp_nofault_PIOR_target));
+ (void)xp_nofault_PIOR((u64 *)GLOBAL_MMR_ADDR(NASID_GET(&amo->
+ variable),
+ xp_nofault_PIOR_target));
local_irq_restore(irq_flags);
}
xpc_cancel_partition_disengage_request(struct xpc_partition *part)
{
unsigned long irq_flags;
- AMO_t *amo = (AMO_t *) __va(part->remote_amos_page_pa +
- (XPC_DISENGAGE_REQUEST_AMO * sizeof(AMO_t)));
-
+ AMO_t *amo = (AMO_t *)__va(part->remote_amos_page_pa +
+ (XPC_DISENGAGE_REQUEST_AMO * sizeof(AMO_t)));
local_irq_save(irq_flags);
/* clear bit corresponding to our partid in remote partition's AMO */
- FETCHOP_STORE_OP(TO_AMO((u64) &amo->variable), FETCHOP_AND,
- ~(1UL << sn_partition_id));
+ FETCHOP_STORE_OP(TO_AMO((u64)&amo->variable), FETCHOP_AND,
+ ~(1UL << sn_partition_id));
/*
* We must always use the nofault function regardless of whether we
* are on a Shub 1.1 system or a Shub 1.2 slice 0xc processor. If we
* didn't, we'd never know that the other partition is down and would
* keep sending IPIs and AMOs to it until the heartbeat times out.
*/
- (void) xp_nofault_PIOR((u64 *) GLOBAL_MMR_ADDR(NASID_GET(&amo->
- variable), xp_nofault_PIOR_target));
+ (void)xp_nofault_PIOR((u64 *)GLOBAL_MMR_ADDR(NASID_GET(&amo->
+ variable),
+ xp_nofault_PIOR_target));
local_irq_restore(irq_flags);
}
{
AMO_t *amo = xpc_vars->amos_page + XPC_ENGAGED_PARTITIONS_AMO;
-
/* return our partition's AMO variable ANDed with partid_mask */
- return (FETCHOP_LOAD_OP(TO_AMO((u64) &amo->variable), FETCHOP_LOAD) &
- partid_mask);
+ return (FETCHOP_LOAD_OP(TO_AMO((u64)&amo->variable), FETCHOP_LOAD) &
+ partid_mask);
}
static inline u64
{
AMO_t *amo = xpc_vars->amos_page + XPC_DISENGAGE_REQUEST_AMO;
-
/* return our partition's AMO variable ANDed with partid_mask */
- return (FETCHOP_LOAD_OP(TO_AMO((u64) &amo->variable), FETCHOP_LOAD) &
- partid_mask);
+ return (FETCHOP_LOAD_OP(TO_AMO((u64)&amo->variable), FETCHOP_LOAD) &
+ partid_mask);
}
static inline void
{
AMO_t *amo = xpc_vars->amos_page + XPC_ENGAGED_PARTITIONS_AMO;
-
/* clear bit(s) based on partid_mask in our partition's AMO */
- FETCHOP_STORE_OP(TO_AMO((u64) &amo->variable), FETCHOP_AND,
- ~partid_mask);
+ FETCHOP_STORE_OP(TO_AMO((u64)&amo->variable), FETCHOP_AND,
+ ~partid_mask);
}
static inline void
{
AMO_t *amo = xpc_vars->amos_page + XPC_DISENGAGE_REQUEST_AMO;
-
/* clear bit(s) based on partid_mask in our partition's AMO */
- FETCHOP_STORE_OP(TO_AMO((u64) &amo->variable), FETCHOP_AND,
- ~partid_mask);
+ FETCHOP_STORE_OP(TO_AMO((u64)&amo->variable), FETCHOP_AND,
+ ~partid_mask);
}
-
-
/*
* The following set of macros and inlines are used for the sending and
* receiving of IPIs (also known as IRQs). There are two flavors of IPIs,
static inline u64
xpc_IPI_receive(AMO_t *amo)
{
- return FETCHOP_LOAD_OP(TO_AMO((u64) &amo->variable), FETCHOP_CLEAR);
+ return FETCHOP_LOAD_OP(TO_AMO((u64)&amo->variable), FETCHOP_CLEAR);
}
-
static inline enum xpc_retval
xpc_IPI_send(AMO_t *amo, u64 flag, int nasid, int phys_cpuid, int vector)
{
int ret = 0;
unsigned long irq_flags;
-
local_irq_save(irq_flags);
- FETCHOP_STORE_OP(TO_AMO((u64) &amo->variable), FETCHOP_OR, flag);
+ FETCHOP_STORE_OP(TO_AMO((u64)&amo->variable), FETCHOP_OR, flag);
sn_send_IPI_phys(nasid, phys_cpuid, vector, 0);
/*
* didn't, we'd never know that the other partition is down and would
* keep sending IPIs and AMOs to it until the heartbeat times out.
*/
- ret = xp_nofault_PIOR((u64 *) GLOBAL_MMR_ADDR(NASID_GET(&amo->variable),
- xp_nofault_PIOR_target));
+ ret = xp_nofault_PIOR((u64 *)GLOBAL_MMR_ADDR(NASID_GET(&amo->variable),
+ xp_nofault_PIOR_target));
local_irq_restore(irq_flags);
return ((ret == 0) ? xpcSuccess : xpcPioReadError);
}
-
/*
* IPIs associated with SGI_XPC_ACTIVATE IRQ.
*/
*/
static inline void
xpc_activate_IRQ_send(u64 amos_page_pa, int from_nasid, int to_nasid,
- int to_phys_cpuid)
+ int to_phys_cpuid)
{
int w_index = XPC_NASID_W_INDEX(from_nasid);
int b_index = XPC_NASID_B_INDEX(from_nasid);
- AMO_t *amos = (AMO_t *) __va(amos_page_pa +
- (XPC_ACTIVATE_IRQ_AMOS * sizeof(AMO_t)));
+ AMO_t *amos = (AMO_t *)__va(amos_page_pa +
+ (XPC_ACTIVATE_IRQ_AMOS * sizeof(AMO_t)));
-
- (void) xpc_IPI_send(&amos[w_index], (1UL << b_index), to_nasid,
- to_phys_cpuid, SGI_XPC_ACTIVATE);
+ (void)xpc_IPI_send(&amos[w_index], (1UL << b_index), to_nasid,
+ to_phys_cpuid, SGI_XPC_ACTIVATE);
}
static inline void
xpc_IPI_send_activate(struct xpc_vars *vars)
{
xpc_activate_IRQ_send(vars->amos_page_pa, cnodeid_to_nasid(0),
- vars->act_nasid, vars->act_phys_cpuid);
+ vars->act_nasid, vars->act_phys_cpuid);
}
static inline void
xpc_IPI_send_activated(struct xpc_partition *part)
{
xpc_activate_IRQ_send(part->remote_amos_page_pa, cnodeid_to_nasid(0),
- part->remote_act_nasid, part->remote_act_phys_cpuid);
+ part->remote_act_nasid,
+ part->remote_act_phys_cpuid);
}
static inline void
xpc_IPI_send_reactivate(struct xpc_partition *part)
{
xpc_activate_IRQ_send(xpc_vars->amos_page_pa, part->reactivate_nasid,
- xpc_vars->act_nasid, xpc_vars->act_phys_cpuid);
+ xpc_vars->act_nasid, xpc_vars->act_phys_cpuid);
}
static inline void
xpc_IPI_send_disengage(struct xpc_partition *part)
{
xpc_activate_IRQ_send(part->remote_amos_page_pa, cnodeid_to_nasid(0),
- part->remote_act_nasid, part->remote_act_phys_cpuid);
+ part->remote_act_nasid,
+ part->remote_act_phys_cpuid);
}
-
/*
* IPIs associated with SGI_XPC_NOTIFY IRQ.
*/
static inline void
xpc_notify_IRQ_send(struct xpc_channel *ch, u8 ipi_flag, char *ipi_flag_string,
- unsigned long *irq_flags)
+ unsigned long *irq_flags)
{
struct xpc_partition *part = &xpc_partitions[ch->partid];
enum xpc_retval ret;
-
if (likely(part->act_state != XPC_P_DEACTIVATING)) {
ret = xpc_IPI_send(part->remote_IPI_amo_va,
- (u64) ipi_flag << (ch->number * 8),
- part->remote_IPI_nasid,
- part->remote_IPI_phys_cpuid,
- SGI_XPC_NOTIFY);
+ (u64)ipi_flag << (ch->number * 8),
+ part->remote_IPI_nasid,
+ part->remote_IPI_phys_cpuid, SGI_XPC_NOTIFY);
dev_dbg(xpc_chan, "%s sent to partid=%d, channel=%d, ret=%d\n",
ipi_flag_string, ch->partid, ch->number, ret);
if (unlikely(ret != xpcSuccess)) {
- if (irq_flags != NULL) {
+ if (irq_flags != NULL)
spin_unlock_irqrestore(&ch->lock, *irq_flags);
- }
XPC_DEACTIVATE_PARTITION(part, ret);
- if (irq_flags != NULL) {
+ if (irq_flags != NULL)
spin_lock_irqsave(&ch->lock, *irq_flags);
- }
}
}
}
-
/*
* Make it look like the remote partition, which is associated with the
* specified channel, sent us an IPI. This faked IPI will be handled
static inline void
xpc_notify_IRQ_send_local(struct xpc_channel *ch, u8 ipi_flag,
- char *ipi_flag_string)
+ char *ipi_flag_string)
{
struct xpc_partition *part = &xpc_partitions[ch->partid];
-
- FETCHOP_STORE_OP(TO_AMO((u64) &part->local_IPI_amo_va->variable),
- FETCHOP_OR, ((u64) ipi_flag << (ch->number * 8)));
+ FETCHOP_STORE_OP(TO_AMO((u64)&part->local_IPI_amo_va->variable),
+ FETCHOP_OR, ((u64)ipi_flag << (ch->number * 8)));
dev_dbg(xpc_chan, "%s sent local from partid=%d, channel=%d\n",
ipi_flag_string, ch->partid, ch->number);
}
-
/*
* The sending and receiving of IPIs includes the setting of an AMO variable
* to indicate the reason the IPI was sent. The 64-bit variable is divided
#define XPC_IPI_OPENREPLY 0x08
#define XPC_IPI_MSGREQUEST 0x10
-
/* given an AMO variable and a channel#, get its associated IPI flags */
#define XPC_GET_IPI_FLAGS(_amo, _c) ((u8) (((_amo) >> ((_c) * 8)) & 0xff))
#define XPC_SET_IPI_FLAGS(_amo, _c, _f) (_amo) |= ((u64) (_f) << ((_c) * 8))
-#define XPC_ANY_OPENCLOSE_IPI_FLAGS_SET(_amo) ((_amo) & __IA64_UL_CONST(0x0f0f0f0f0f0f0f0f))
-#define XPC_ANY_MSG_IPI_FLAGS_SET(_amo) ((_amo) & __IA64_UL_CONST(0x1010101010101010))
-
+#define XPC_ANY_OPENCLOSE_IPI_FLAGS_SET(_amo) ((_amo) & 0x0f0f0f0f0f0f0f0fUL)
+#define XPC_ANY_MSG_IPI_FLAGS_SET(_amo) ((_amo) & 0x1010101010101010UL)
static inline void
xpc_IPI_send_closerequest(struct xpc_channel *ch, unsigned long *irq_flags)
{
struct xpc_openclose_args *args = ch->local_openclose_args;
-
args->reason = ch->reason;
XPC_NOTIFY_IRQ_SEND(ch, XPC_IPI_CLOSEREQUEST, irq_flags);
{
struct xpc_openclose_args *args = ch->local_openclose_args;
-
args->msg_size = ch->msg_size;
args->local_nentries = ch->local_nentries;
{
struct xpc_openclose_args *args = ch->local_openclose_args;
-
args->remote_nentries = ch->remote_nentries;
args->local_nentries = ch->local_nentries;
args->local_msgqueue_pa = __pa(ch->local_msgqueue);
XPC_NOTIFY_IRQ_SEND_LOCAL(ch, XPC_IPI_MSGREQUEST);
}
-
/*
* Memory for XPC's AMO variables is allocated by the MSPEC driver. These
* pages are located in the lowest granule. The lowest granule uses 4k pages
{
AMO_t *amo = xpc_vars->amos_page + index;
-
- (void) xpc_IPI_receive(amo); /* clear AMO variable */
+ (void)xpc_IPI_receive(amo); /* clear AMO variable */
return amo;
}
-
-
static inline enum xpc_retval
xpc_map_bte_errors(bte_result_t error)
{
return xpcBteUnmappedError;
}
switch (error) {
- case BTE_SUCCESS: return xpcSuccess;
- case BTEFAIL_DIR: return xpcBteDirectoryError;
- case BTEFAIL_POISON: return xpcBtePoisonError;
- case BTEFAIL_WERR: return xpcBteWriteError;
- case BTEFAIL_ACCESS: return xpcBteAccessError;
- case BTEFAIL_PWERR: return xpcBtePWriteError;
- case BTEFAIL_PRERR: return xpcBtePReadError;
- case BTEFAIL_TOUT: return xpcBteTimeOutError;
- case BTEFAIL_XTERR: return xpcBteXtalkError;
- case BTEFAIL_NOTAVAIL: return xpcBteNotAvailable;
- default: return xpcBteUnmappedError;
+ case BTE_SUCCESS:
+ return xpcSuccess;
+ case BTEFAIL_DIR:
+ return xpcBteDirectoryError;
+ case BTEFAIL_POISON:
+ return xpcBtePoisonError;
+ case BTEFAIL_WERR:
+ return xpcBteWriteError;
+ case BTEFAIL_ACCESS:
+ return xpcBteAccessError;
+ case BTEFAIL_PWERR:
+ return xpcBtePWriteError;
+ case BTEFAIL_PRERR:
+ return xpcBtePReadError;
+ case BTEFAIL_TOUT:
+ return xpcBteTimeOutError;
+ case BTEFAIL_XTERR:
+ return xpcBteXtalkError;
+ case BTEFAIL_NOTAVAIL:
+ return xpcBteNotAvailable;
+ default:
+ return xpcBteUnmappedError;
}
}
-
-
/*
* Check to see if there is any channel activity to/from the specified
* partition.
u64 IPI_amo;
unsigned long irq_flags;
-
IPI_amo = xpc_IPI_receive(part->local_IPI_amo_va);
- if (IPI_amo == 0) {
+ if (IPI_amo == 0)
return;
- }
spin_lock_irqsave(&part->IPI_lock, irq_flags);
part->local_IPI_amo |= IPI_amo;
xpc_wakeup_channel_mgr(part);
}
-
-#endif /* _ASM_IA64_SN_XPC_H */
-
+#endif /* _DRIVERS_MISC_SGIXP_XPC_H */
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (c) 2004-2006 Silicon Graphics, Inc. All Rights Reserved.
+ * Copyright (c) 2004-2008 Silicon Graphics, Inc. All Rights Reserved.
*/
-
/*
* Cross Partition Communication (XPC) channel support.
*
*
*/
-
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/completion.h>
#include <asm/sn/bte.h>
#include <asm/sn/sn_sal.h>
-#include <asm/sn/xpc.h>
-
+#include "xpc.h"
/*
* Guarantee that the kzalloc'd memory is cacheline aligned.
{
/* see if kzalloc will give us cachline aligned memory by default */
*base = kzalloc(size, flags);
- if (*base == NULL) {
+ if (*base == NULL)
return NULL;
- }
- if ((u64) *base == L1_CACHE_ALIGN((u64) *base)) {
+
+ if ((u64)*base == L1_CACHE_ALIGN((u64)*base))
return *base;
- }
+
kfree(*base);
/* nope, we'll have to do it ourselves */
*base = kzalloc(size + L1_CACHE_BYTES, flags);
- if (*base == NULL) {
+ if (*base == NULL)
return NULL;
- }
- return (void *) L1_CACHE_ALIGN((u64) *base);
-}
+ return (void *)L1_CACHE_ALIGN((u64)*base);
+}
/*
* Set up the initial values for the XPartition Communication channels.
int ch_number;
struct xpc_channel *ch;
-
for (ch_number = 0; ch_number < part->nchannels; ch_number++) {
ch = &part->channels[ch_number];
ch->local_GP = &part->local_GPs[ch_number];
ch->local_openclose_args =
- &part->local_openclose_args[ch_number];
+ &part->local_openclose_args[ch_number];
atomic_set(&ch->kthreads_assigned, 0);
atomic_set(&ch->kthreads_idle, 0);
}
}
-
/*
* Setup the infrastructure necessary to support XPartition Communication
* between the specified remote partition and the local one.
struct timer_list *timer;
partid_t partid = XPC_PARTID(part);
-
/*
* Zero out MOST of the entry for this partition. Only the fields
* starting with `nchannels' will be zeroed. The preceding fields must
* referenced during this memset() operation.
*/
memset(&part->nchannels, 0, sizeof(struct xpc_partition) -
- offsetof(struct xpc_partition, nchannels));
+ offsetof(struct xpc_partition, nchannels));
/*
* Allocate all of the channel structures as a contiguous chunk of
* memory.
*/
part->channels = kzalloc(sizeof(struct xpc_channel) * XPC_NCHANNELS,
- GFP_KERNEL);
+ GFP_KERNEL);
if (part->channels == NULL) {
dev_err(xpc_chan, "can't get memory for channels\n");
return xpcNoMemory;
part->nchannels = XPC_NCHANNELS;
-
/* allocate all the required GET/PUT values */
part->local_GPs = xpc_kzalloc_cacheline_aligned(XPC_GP_SIZE,
- GFP_KERNEL, &part->local_GPs_base);
+ GFP_KERNEL,
+ &part->local_GPs_base);
if (part->local_GPs == NULL) {
kfree(part->channels);
part->channels = NULL;
}
part->remote_GPs = xpc_kzalloc_cacheline_aligned(XPC_GP_SIZE,
- GFP_KERNEL, &part->remote_GPs_base);
+ GFP_KERNEL,
+ &part->
+ remote_GPs_base);
if (part->remote_GPs == NULL) {
dev_err(xpc_chan, "can't get memory for remote get/put "
"values\n");
return xpcNoMemory;
}
-
/* allocate all the required open and close args */
- part->local_openclose_args = xpc_kzalloc_cacheline_aligned(
- XPC_OPENCLOSE_ARGS_SIZE, GFP_KERNEL,
- &part->local_openclose_args_base);
+ part->local_openclose_args =
+ xpc_kzalloc_cacheline_aligned(XPC_OPENCLOSE_ARGS_SIZE, GFP_KERNEL,
+ &part->local_openclose_args_base);
if (part->local_openclose_args == NULL) {
dev_err(xpc_chan, "can't get memory for local connect args\n");
kfree(part->remote_GPs_base);
return xpcNoMemory;
}
- part->remote_openclose_args = xpc_kzalloc_cacheline_aligned(
- XPC_OPENCLOSE_ARGS_SIZE, GFP_KERNEL,
- &part->remote_openclose_args_base);
+ part->remote_openclose_args =
+ xpc_kzalloc_cacheline_aligned(XPC_OPENCLOSE_ARGS_SIZE, GFP_KERNEL,
+ &part->remote_openclose_args_base);
if (part->remote_openclose_args == NULL) {
dev_err(xpc_chan, "can't get memory for remote connect args\n");
kfree(part->local_openclose_args_base);
return xpcNoMemory;
}
-
xpc_initialize_channels(part, partid);
atomic_set(&part->nchannels_active, 0);
atomic_set(&part->nchannels_engaged, 0);
-
/* local_IPI_amo were set to 0 by an earlier memset() */
/* Initialize this partitions AMO_t structure */
sprintf(part->IPI_owner, "xpc%02d", partid);
ret = request_irq(SGI_XPC_NOTIFY, xpc_notify_IRQ_handler, IRQF_SHARED,
- part->IPI_owner, (void *) (u64) partid);
+ part->IPI_owner, (void *)(u64)partid);
if (ret != 0) {
dev_err(xpc_chan, "can't register NOTIFY IRQ handler, "
"errno=%d\n", -ret);
/* Setup a timer to check for dropped IPIs */
timer = &part->dropped_IPI_timer;
init_timer(timer);
- timer->function = (void (*)(unsigned long)) xpc_dropped_IPI_check;
- timer->data = (unsigned long) part;
+ timer->function = (void (*)(unsigned long))xpc_dropped_IPI_check;
+ timer->data = (unsigned long)part;
timer->expires = jiffies + XPC_P_DROPPED_IPI_WAIT;
add_timer(timer);
*/
part->setup_state = XPC_P_SETUP;
-
/*
* Setup the per partition specific variables required by the
* remote partition to establish channel connections with us.
*/
xpc_vars_part[partid].GPs_pa = __pa(part->local_GPs);
xpc_vars_part[partid].openclose_args_pa =
- __pa(part->local_openclose_args);
+ __pa(part->local_openclose_args);
xpc_vars_part[partid].IPI_amo_pa = __pa(part->local_IPI_amo_va);
cpuid = raw_smp_processor_id(); /* any CPU in this partition will do */
xpc_vars_part[partid].IPI_nasid = cpuid_to_nasid(cpuid);
return xpcSuccess;
}
-
/*
* Create a wrapper that hides the underlying mechanism for pulling a cacheline
* (or multiple cachelines) from a remote partition.
*/
static enum xpc_retval
xpc_pull_remote_cachelines(struct xpc_partition *part, void *dst,
- const void *src, size_t cnt)
+ const void *src, size_t cnt)
{
bte_result_t bte_ret;
-
- DBUG_ON((u64) src != L1_CACHE_ALIGN((u64) src));
- DBUG_ON((u64) dst != L1_CACHE_ALIGN((u64) dst));
+ DBUG_ON((u64)src != L1_CACHE_ALIGN((u64)src));
+ DBUG_ON((u64)dst != L1_CACHE_ALIGN((u64)dst));
DBUG_ON(cnt != L1_CACHE_ALIGN(cnt));
- if (part->act_state == XPC_P_DEACTIVATING) {
+ if (part->act_state == XPC_P_DEACTIVATING)
return part->reason;
- }
- bte_ret = xp_bte_copy((u64) src, (u64) dst, (u64) cnt,
- (BTE_NORMAL | BTE_WACQUIRE), NULL);
- if (bte_ret == BTE_SUCCESS) {
+ bte_ret = xp_bte_copy((u64)src, (u64)dst, (u64)cnt,
+ (BTE_NORMAL | BTE_WACQUIRE), NULL);
+ if (bte_ret == BTE_SUCCESS)
return xpcSuccess;
- }
dev_dbg(xpc_chan, "xp_bte_copy() from partition %d failed, ret=%d\n",
XPC_PARTID(part), bte_ret);
return xpc_map_bte_errors(bte_ret);
}
-
/*
* Pull the remote per partition specific variables from the specified
* partition.
{
u8 buffer[L1_CACHE_BYTES * 2];
struct xpc_vars_part *pulled_entry_cacheline =
- (struct xpc_vars_part *) L1_CACHE_ALIGN((u64) buffer);
+ (struct xpc_vars_part *)L1_CACHE_ALIGN((u64)buffer);
struct xpc_vars_part *pulled_entry;
u64 remote_entry_cacheline_pa, remote_entry_pa;
partid_t partid = XPC_PARTID(part);
enum xpc_retval ret;
-
/* pull the cacheline that contains the variables we're interested in */
DBUG_ON(part->remote_vars_part_pa !=
- L1_CACHE_ALIGN(part->remote_vars_part_pa));
+ L1_CACHE_ALIGN(part->remote_vars_part_pa));
DBUG_ON(sizeof(struct xpc_vars_part) != L1_CACHE_BYTES / 2);
remote_entry_pa = part->remote_vars_part_pa +
- sn_partition_id * sizeof(struct xpc_vars_part);
+ sn_partition_id * sizeof(struct xpc_vars_part);
remote_entry_cacheline_pa = (remote_entry_pa & ~(L1_CACHE_BYTES - 1));
- pulled_entry = (struct xpc_vars_part *) ((u64) pulled_entry_cacheline +
- (remote_entry_pa & (L1_CACHE_BYTES - 1)));
+ pulled_entry = (struct xpc_vars_part *)((u64)pulled_entry_cacheline +
+ (remote_entry_pa &
+ (L1_CACHE_BYTES - 1)));
ret = xpc_pull_remote_cachelines(part, pulled_entry_cacheline,
- (void *) remote_entry_cacheline_pa,
- L1_CACHE_BYTES);
+ (void *)remote_entry_cacheline_pa,
+ L1_CACHE_BYTES);
if (ret != xpcSuccess) {
dev_dbg(xpc_chan, "failed to pull XPC vars_part from "
"partition %d, ret=%d\n", partid, ret);
return ret;
}
-
/* see if they've been set up yet */
if (pulled_entry->magic != XPC_VP_MAGIC1 &&
- pulled_entry->magic != XPC_VP_MAGIC2) {
+ pulled_entry->magic != XPC_VP_MAGIC2) {
if (pulled_entry->magic != 0) {
dev_dbg(xpc_chan, "partition %d's XPC vars_part for "
/* validate the variables */
if (pulled_entry->GPs_pa == 0 ||
- pulled_entry->openclose_args_pa == 0 ||
- pulled_entry->IPI_amo_pa == 0) {
+ pulled_entry->openclose_args_pa == 0 ||
+ pulled_entry->IPI_amo_pa == 0) {
dev_err(xpc_chan, "partition %d's XPC vars_part for "
"partition %d are not valid\n", partid,
part->remote_GPs_pa = pulled_entry->GPs_pa;
part->remote_openclose_args_pa =
- pulled_entry->openclose_args_pa;
+ pulled_entry->openclose_args_pa;
part->remote_IPI_amo_va =
- (AMO_t *) __va(pulled_entry->IPI_amo_pa);
+ (AMO_t *)__va(pulled_entry->IPI_amo_pa);
part->remote_IPI_nasid = pulled_entry->IPI_nasid;
part->remote_IPI_phys_cpuid = pulled_entry->IPI_phys_cpuid;
- if (part->nchannels > pulled_entry->nchannels) {
+ if (part->nchannels > pulled_entry->nchannels)
part->nchannels = pulled_entry->nchannels;
- }
/* let the other side know that we've pulled their variables */
xpc_vars_part[partid].magic = XPC_VP_MAGIC2;
}
- if (pulled_entry->magic == XPC_VP_MAGIC1) {
+ if (pulled_entry->magic == XPC_VP_MAGIC1)
return xpcRetry;
- }
return xpcSuccess;
}
-
/*
* Get the IPI flags and pull the openclose args and/or remote GPs as needed.
*/
u64 IPI_amo;
enum xpc_retval ret;
-
/*
* See if there are any IPI flags to be handled.
*/
spin_lock_irqsave(&part->IPI_lock, irq_flags);
- if ((IPI_amo = part->local_IPI_amo) != 0) {
+ IPI_amo = part->local_IPI_amo;
+ if (IPI_amo != 0)
part->local_IPI_amo = 0;
- }
- spin_unlock_irqrestore(&part->IPI_lock, irq_flags);
+ spin_unlock_irqrestore(&part->IPI_lock, irq_flags);
if (XPC_ANY_OPENCLOSE_IPI_FLAGS_SET(IPI_amo)) {
ret = xpc_pull_remote_cachelines(part,
- part->remote_openclose_args,
- (void *) part->remote_openclose_args_pa,
- XPC_OPENCLOSE_ARGS_SIZE);
+ part->remote_openclose_args,
+ (void *)part->
+ remote_openclose_args_pa,
+ XPC_OPENCLOSE_ARGS_SIZE);
if (ret != xpcSuccess) {
XPC_DEACTIVATE_PARTITION(part, ret);
if (XPC_ANY_MSG_IPI_FLAGS_SET(IPI_amo)) {
ret = xpc_pull_remote_cachelines(part, part->remote_GPs,
- (void *) part->remote_GPs_pa,
- XPC_GP_SIZE);
+ (void *)part->remote_GPs_pa,
+ XPC_GP_SIZE);
if (ret != xpcSuccess) {
XPC_DEACTIVATE_PARTITION(part, ret);
return IPI_amo;
}
-
/*
* Allocate the local message queue and the notify queue.
*/
int nentries;
size_t nbytes;
-
- // >>> may want to check for ch->flags & XPC_C_DISCONNECTING between
- // >>> iterations of the for-loop, bail if set?
-
- // >>> should we impose a minimum #of entries? like 4 or 8?
for (nentries = ch->local_nentries; nentries > 0; nentries--) {
nbytes = nentries * ch->msg_size;
ch->local_msgqueue = xpc_kzalloc_cacheline_aligned(nbytes,
- GFP_KERNEL,
- &ch->local_msgqueue_base);
- if (ch->local_msgqueue == NULL) {
+ GFP_KERNEL,
+ &ch->local_msgqueue_base);
+ if (ch->local_msgqueue == NULL)
continue;
- }
nbytes = nentries * sizeof(struct xpc_notify);
ch->notify_queue = kzalloc(nbytes, GFP_KERNEL);
return xpcNoMemory;
}
-
/*
* Allocate the cached remote message queue.
*/
int nentries;
size_t nbytes;
-
DBUG_ON(ch->remote_nentries <= 0);
- // >>> may want to check for ch->flags & XPC_C_DISCONNECTING between
- // >>> iterations of the for-loop, bail if set?
-
- // >>> should we impose a minimum #of entries? like 4 or 8?
for (nentries = ch->remote_nentries; nentries > 0; nentries--) {
nbytes = nentries * ch->msg_size;
ch->remote_msgqueue = xpc_kzalloc_cacheline_aligned(nbytes,
- GFP_KERNEL,
- &ch->remote_msgqueue_base);
- if (ch->remote_msgqueue == NULL) {
+ GFP_KERNEL,
+ &ch->remote_msgqueue_base);
+ if (ch->remote_msgqueue == NULL)
continue;
- }
spin_lock_irqsave(&ch->lock, irq_flags);
if (nentries < ch->remote_nentries) {
return xpcNoMemory;
}
-
/*
* Allocate message queues and other stuff associated with a channel.
*
unsigned long irq_flags;
enum xpc_retval ret;
-
DBUG_ON(ch->flags & XPC_C_SETUP);
- if ((ret = xpc_allocate_local_msgqueue(ch)) != xpcSuccess) {
+ ret = xpc_allocate_local_msgqueue(ch);
+ if (ret != xpcSuccess)
return ret;
- }
- if ((ret = xpc_allocate_remote_msgqueue(ch)) != xpcSuccess) {
+ ret = xpc_allocate_remote_msgqueue(ch);
+ if (ret != xpcSuccess) {
kfree(ch->local_msgqueue_base);
ch->local_msgqueue = NULL;
kfree(ch->notify_queue);
return xpcSuccess;
}
-
/*
* Process a connect message from a remote partition.
*
{
enum xpc_retval ret;
-
DBUG_ON(!spin_is_locked(&ch->lock));
if (!(ch->flags & XPC_C_OPENREQUEST) ||
- !(ch->flags & XPC_C_ROPENREQUEST)) {
+ !(ch->flags & XPC_C_ROPENREQUEST)) {
/* nothing more to do for now */
return;
}
ret = xpc_allocate_msgqueues(ch);
spin_lock_irqsave(&ch->lock, *irq_flags);
- if (ret != xpcSuccess) {
+ if (ret != xpcSuccess)
XPC_DISCONNECT_CHANNEL(ch, ret, irq_flags);
- }
- if (ch->flags & (XPC_C_CONNECTED | XPC_C_DISCONNECTING)) {
+
+ if (ch->flags & (XPC_C_CONNECTED | XPC_C_DISCONNECTING))
return;
- }
DBUG_ON(!(ch->flags & XPC_C_SETUP));
DBUG_ON(ch->local_msgqueue == NULL);
xpc_IPI_send_openreply(ch, irq_flags);
}
- if (!(ch->flags & XPC_C_ROPENREPLY)) {
+ if (!(ch->flags & XPC_C_ROPENREPLY))
return;
- }
DBUG_ON(ch->remote_msgqueue_pa == 0);
ch->flags = (XPC_C_CONNECTED | XPC_C_SETUP); /* clear all else */
dev_info(xpc_chan, "channel %d to partition %d connected\n",
- ch->number, ch->partid);
+ ch->number, ch->partid);
spin_unlock_irqrestore(&ch->lock, *irq_flags);
xpc_create_kthreads(ch, 1, 0);
spin_lock_irqsave(&ch->lock, *irq_flags);
}
-
/*
* Notify those who wanted to be notified upon delivery of their message.
*/
u8 notify_type;
s64 get = ch->w_remote_GP.get - 1;
-
while (++get < put && atomic_read(&ch->n_to_notify) > 0) {
notify = &ch->notify_queue[get % ch->local_nentries];
*/
notify_type = notify->type;
if (notify_type == 0 ||
- cmpxchg(¬ify->type, notify_type, 0) !=
- notify_type) {
+ cmpxchg(¬ify->type, notify_type, 0) != notify_type) {
continue;
}
if (notify->func != NULL) {
dev_dbg(xpc_chan, "notify->func() called, notify=0x%p, "
"msg_number=%ld, partid=%d, channel=%d\n",
- (void *) notify, get, ch->partid, ch->number);
+ (void *)notify, get, ch->partid, ch->number);
notify->func(reason, ch->partid, ch->number,
- notify->key);
+ notify->key);
dev_dbg(xpc_chan, "notify->func() returned, "
"notify=0x%p, msg_number=%ld, partid=%d, "
- "channel=%d\n", (void *) notify, get,
+ "channel=%d\n", (void *)notify, get,
ch->partid, ch->number);
}
}
}
-
/*
* Free up message queues and other stuff that were allocated for the specified
* channel.
}
}
-
/*
* spin_lock_irqsave() is expected to be held on entry.
*/
struct xpc_partition *part = &xpc_partitions[ch->partid];
u32 channel_was_connected = (ch->flags & XPC_C_WASCONNECTED);
-
DBUG_ON(!spin_is_locked(&ch->lock));
- if (!(ch->flags & XPC_C_DISCONNECTING)) {
+ if (!(ch->flags & XPC_C_DISCONNECTING))
return;
- }
DBUG_ON(!(ch->flags & XPC_C_CLOSEREQUEST));
/* make sure all activity has settled down first */
if (atomic_read(&ch->kthreads_assigned) > 0 ||
- atomic_read(&ch->references) > 0) {
+ atomic_read(&ch->references) > 0) {
return;
}
DBUG_ON((ch->flags & XPC_C_CONNECTEDCALLOUT_MADE) &&
- !(ch->flags & XPC_C_DISCONNECTINGCALLOUT_MADE));
+ !(ch->flags & XPC_C_DISCONNECTINGCALLOUT_MADE));
if (part->act_state == XPC_P_DEACTIVATING) {
/* can't proceed until the other side disengages from us */
- if (xpc_partition_engaged(1UL << ch->partid)) {
+ if (xpc_partition_engaged(1UL << ch->partid))
return;
- }
} else {
/* as long as the other side is up do the full protocol */
- if (!(ch->flags & XPC_C_RCLOSEREQUEST)) {
+ if (!(ch->flags & XPC_C_RCLOSEREQUEST))
return;
- }
if (!(ch->flags & XPC_C_CLOSEREPLY)) {
ch->flags |= XPC_C_CLOSEREPLY;
xpc_IPI_send_closereply(ch, irq_flags);
}
- if (!(ch->flags & XPC_C_RCLOSEREPLY)) {
+ if (!(ch->flags & XPC_C_RCLOSEREPLY))
return;
- }
}
/* wake those waiting for notify completion */
if (channel_was_connected) {
dev_info(xpc_chan, "channel %d to partition %d disconnected, "
- "reason=%d\n", ch->number, ch->partid, ch->reason);
+ "reason=%d\n", ch->number, ch->partid, ch->reason);
}
if (ch->flags & XPC_C_WDISCONNECT) {
/* time to take action on any delayed IPI flags */
spin_lock(&part->IPI_lock);
XPC_SET_IPI_FLAGS(part->local_IPI_amo, ch->number,
- ch->delayed_IPI_flags);
+ ch->delayed_IPI_flags);
spin_unlock(&part->IPI_lock);
}
ch->delayed_IPI_flags = 0;
}
}
-
/*
* Process a change in the channel's remote connection state.
*/
static void
xpc_process_openclose_IPI(struct xpc_partition *part, int ch_number,
- u8 IPI_flags)
+ u8 IPI_flags)
{
unsigned long irq_flags;
struct xpc_openclose_args *args =
- &part->remote_openclose_args[ch_number];
+ &part->remote_openclose_args[ch_number];
struct xpc_channel *ch = &part->channels[ch_number];
enum xpc_retval reason;
-
-
spin_lock_irqsave(&ch->lock, irq_flags);
again:
if ((ch->flags & XPC_C_DISCONNECTED) &&
- (ch->flags & XPC_C_WDISCONNECT)) {
+ (ch->flags & XPC_C_WDISCONNECT)) {
/*
* Delay processing IPI flags until thread waiting disconnect
* has had a chance to see that the channel is disconnected.
return;
}
-
if (IPI_flags & XPC_IPI_CLOSEREQUEST) {
dev_dbg(xpc_chan, "XPC_IPI_CLOSEREQUEST (reason=%d) received "
if (ch->flags & XPC_C_DISCONNECTED) {
if (!(IPI_flags & XPC_IPI_OPENREQUEST)) {
if ((XPC_GET_IPI_FLAGS(part->local_IPI_amo,
- ch_number) & XPC_IPI_OPENREQUEST)) {
+ ch_number) &
+ XPC_IPI_OPENREQUEST)) {
DBUG_ON(ch->delayed_IPI_flags != 0);
spin_lock(&part->IPI_lock);
XPC_SET_IPI_FLAGS(part->local_IPI_amo,
- ch_number,
- XPC_IPI_CLOSEREQUEST);
+ ch_number,
+ XPC_IPI_CLOSEREQUEST);
spin_unlock(&part->IPI_lock);
}
spin_unlock_irqrestore(&ch->lock, irq_flags);
if (!(ch->flags & XPC_C_DISCONNECTING)) {
reason = args->reason;
- if (reason <= xpcSuccess || reason > xpcUnknownReason) {
+ if (reason <= xpcSuccess || reason > xpcUnknownReason)
reason = xpcUnknownReason;
- } else if (reason == xpcUnregistering) {
+ else if (reason == xpcUnregistering)
reason = xpcOtherUnregistering;
- }
XPC_DISCONNECT_CHANNEL(ch, reason, &irq_flags);
xpc_process_disconnect(ch, &irq_flags);
}
-
if (IPI_flags & XPC_IPI_CLOSEREPLY) {
dev_dbg(xpc_chan, "XPC_IPI_CLOSEREPLY received from partid=%d,"
if (!(ch->flags & XPC_C_RCLOSEREQUEST)) {
if ((XPC_GET_IPI_FLAGS(part->local_IPI_amo, ch_number)
- & XPC_IPI_CLOSEREQUEST)) {
+ & XPC_IPI_CLOSEREQUEST)) {
DBUG_ON(ch->delayed_IPI_flags != 0);
spin_lock(&part->IPI_lock);
XPC_SET_IPI_FLAGS(part->local_IPI_amo,
- ch_number, XPC_IPI_CLOSEREPLY);
+ ch_number,
+ XPC_IPI_CLOSEREPLY);
spin_unlock(&part->IPI_lock);
}
spin_unlock_irqrestore(&ch->lock, irq_flags);
}
}
-
if (IPI_flags & XPC_IPI_OPENREQUEST) {
dev_dbg(xpc_chan, "XPC_IPI_OPENREQUEST (msg_size=%d, "
ch->partid, ch->number);
if (part->act_state == XPC_P_DEACTIVATING ||
- (ch->flags & XPC_C_ROPENREQUEST)) {
+ (ch->flags & XPC_C_ROPENREQUEST)) {
spin_unlock_irqrestore(&ch->lock, irq_flags);
return;
}
return;
}
DBUG_ON(!(ch->flags & (XPC_C_DISCONNECTED |
- XPC_C_OPENREQUEST)));
+ XPC_C_OPENREQUEST)));
DBUG_ON(ch->flags & (XPC_C_ROPENREQUEST | XPC_C_ROPENREPLY |
- XPC_C_OPENREPLY | XPC_C_CONNECTED));
+ XPC_C_OPENREPLY | XPC_C_CONNECTED));
/*
* The meaningful OPENREQUEST connection state fields are:
ch->flags |= (XPC_C_ROPENREQUEST | XPC_C_CONNECTING);
ch->remote_nentries = args->local_nentries;
-
if (ch->flags & XPC_C_OPENREQUEST) {
if (args->msg_size != ch->msg_size) {
XPC_DISCONNECT_CHANNEL(ch, xpcUnequalMsgSizes,
- &irq_flags);
+ &irq_flags);
spin_unlock_irqrestore(&ch->lock, irq_flags);
return;
}
xpc_process_connect(ch, &irq_flags);
}
-
if (IPI_flags & XPC_IPI_OPENREPLY) {
dev_dbg(xpc_chan, "XPC_IPI_OPENREPLY (local_msgqueue_pa=0x%lx, "
}
if (!(ch->flags & XPC_C_OPENREQUEST)) {
XPC_DISCONNECT_CHANNEL(ch, xpcOpenCloseError,
- &irq_flags);
+ &irq_flags);
spin_unlock_irqrestore(&ch->lock, irq_flags);
return;
}
/*
* The meaningful OPENREPLY connection state fields are:
* local_msgqueue_pa = physical address of remote
- * partition's local_msgqueue
+ * partition's local_msgqueue
* local_nentries = remote partition's local_nentries
* remote_nentries = remote partition's remote_nentries
*/
spin_unlock_irqrestore(&ch->lock, irq_flags);
}
-
/*
* Attempt to establish a channel connection to a remote partition.
*/
unsigned long irq_flags;
struct xpc_registration *registration = &xpc_registrations[ch->number];
-
- if (mutex_trylock(®istration->mutex) == 0) {
+ if (mutex_trylock(®istration->mutex) == 0)
return xpcRetry;
- }
if (!XPC_CHANNEL_REGISTERED(ch->number)) {
mutex_unlock(®istration->mutex);
return ch->reason;
}
-
/* add info from the channel connect registration to the channel */
ch->kthreads_assigned_limit = registration->assigned_limit;
*/
mutex_unlock(®istration->mutex);
XPC_DISCONNECT_CHANNEL(ch, xpcUnequalMsgSizes,
- &irq_flags);
+ &irq_flags);
spin_unlock_irqrestore(&ch->lock, irq_flags);
return xpcUnequalMsgSizes;
}
mutex_unlock(®istration->mutex);
-
/* initiate the connection */
ch->flags |= (XPC_C_OPENREQUEST | XPC_C_CONNECTING);
return xpcSuccess;
}
-
/*
* Clear some of the msg flags in the local message queue.
*/
struct xpc_msg *msg;
s64 get;
-
get = ch->w_remote_GP.get;
do {
- msg = (struct xpc_msg *) ((u64) ch->local_msgqueue +
- (get % ch->local_nentries) * ch->msg_size);
+ msg = (struct xpc_msg *)((u64)ch->local_msgqueue +
+ (get % ch->local_nentries) *
+ ch->msg_size);
msg->flags = 0;
- } while (++get < (volatile s64) ch->remote_GP.get);
+ } while (++get < ch->remote_GP.get);
}
-
/*
* Clear some of the msg flags in the remote message queue.
*/
struct xpc_msg *msg;
s64 put;
-
put = ch->w_remote_GP.put;
do {
- msg = (struct xpc_msg *) ((u64) ch->remote_msgqueue +
- (put % ch->remote_nentries) * ch->msg_size);
+ msg = (struct xpc_msg *)((u64)ch->remote_msgqueue +
+ (put % ch->remote_nentries) *
+ ch->msg_size);
msg->flags = 0;
- } while (++put < (volatile s64) ch->remote_GP.put);
+ } while (++put < ch->remote_GP.put);
}
-
static void
xpc_process_msg_IPI(struct xpc_partition *part, int ch_number)
{
struct xpc_channel *ch = &part->channels[ch_number];
int nmsgs_sent;
-
ch->remote_GP = part->remote_GPs[ch_number];
-
/* See what, if anything, has changed for each connected channel */
xpc_msgqueue_ref(ch);
if (ch->w_remote_GP.get == ch->remote_GP.get &&
- ch->w_remote_GP.put == ch->remote_GP.put) {
+ ch->w_remote_GP.put == ch->remote_GP.put) {
/* nothing changed since GPs were last pulled */
xpc_msgqueue_deref(ch);
return;
}
- if (!(ch->flags & XPC_C_CONNECTED)){
+ if (!(ch->flags & XPC_C_CONNECTED)) {
xpc_msgqueue_deref(ch);
return;
}
-
/*
* First check to see if messages recently sent by us have been
* received by the other side. (The remote GET value will have
* received and delivered by the other side.
*/
xpc_notify_senders(ch, xpcMsgDelivered,
- ch->remote_GP.get);
+ ch->remote_GP.get);
}
/*
* If anyone was waiting for message queue entries to become
* available, wake them up.
*/
- if (atomic_read(&ch->n_on_msg_allocate_wq) > 0) {
+ if (atomic_read(&ch->n_on_msg_allocate_wq) > 0)
wake_up(&ch->msg_allocate_wq);
- }
}
-
/*
* Now check for newly sent messages by the other side. (The remote
* PUT value will have changed since we last looked at it.)
"delivered=%d, partid=%d, channel=%d\n",
nmsgs_sent, ch->partid, ch->number);
- if (ch->flags & XPC_C_CONNECTEDCALLOUT_MADE) {
+ if (ch->flags & XPC_C_CONNECTEDCALLOUT_MADE)
xpc_activate_kthreads(ch, nmsgs_sent);
- }
}
}
xpc_msgqueue_deref(ch);
}
-
void
xpc_process_channel_activity(struct xpc_partition *part)
{
int ch_number;
u32 ch_flags;
-
IPI_amo = xpc_get_IPI_flags(part);
/*
for (ch_number = 0; ch_number < part->nchannels; ch_number++) {
ch = &part->channels[ch_number];
-
/*
* Process any open or close related IPI flags, and then deal
* with connecting or disconnecting the channel as required.
IPI_flags = XPC_GET_IPI_FLAGS(IPI_amo, ch_number);
- if (XPC_ANY_OPENCLOSE_IPI_FLAGS_SET(IPI_flags)) {
+ if (XPC_ANY_OPENCLOSE_IPI_FLAGS_SET(IPI_flags))
xpc_process_openclose_IPI(part, ch_number, IPI_flags);
- }
ch_flags = ch->flags; /* need an atomic snapshot of flags */
continue;
}
- if (part->act_state == XPC_P_DEACTIVATING) {
+ if (part->act_state == XPC_P_DEACTIVATING)
continue;
- }
if (!(ch_flags & XPC_C_CONNECTED)) {
if (!(ch_flags & XPC_C_OPENREQUEST)) {
DBUG_ON(ch_flags & XPC_C_SETUP);
- (void) xpc_connect_channel(ch);
+ (void)xpc_connect_channel(ch);
} else {
spin_lock_irqsave(&ch->lock, irq_flags);
xpc_process_connect(ch, &irq_flags);
continue;
}
-
/*
* Process any message related IPI flags, this may involve the
* activation of kthreads to deliver any pending messages sent
* from the other partition.
*/
- if (XPC_ANY_MSG_IPI_FLAGS_SET(IPI_flags)) {
+ if (XPC_ANY_MSG_IPI_FLAGS_SET(IPI_flags))
xpc_process_msg_IPI(part, ch_number);
- }
}
}
-
/*
* XPC's heartbeat code calls this function to inform XPC that a partition is
* going down. XPC responds by tearing down the XPartition Communication
int ch_number;
struct xpc_channel *ch;
-
dev_dbg(xpc_chan, "deactivating partition %d, reason=%d\n",
XPC_PARTID(part), reason);
return;
}
-
/* disconnect channels associated with the partition going down */
for (ch_number = 0; ch_number < part->nchannels; ch_number++) {
xpc_part_deref(part);
}
-
/*
* Teardown the infrastructure necessary to support XPartition Communication
* between the specified remote partition and the local one.
{
partid_t partid = XPC_PARTID(part);
-
/*
* We start off by making this partition inaccessible to local
* processes by marking it as no longer setup. Then we make it
xpc_vars_part[partid].magic = 0;
-
- free_irq(SGI_XPC_NOTIFY, (void *) (u64) partid);
-
+ free_irq(SGI_XPC_NOTIFY, (void *)(u64)partid);
/*
* Before proceeding with the teardown we have to wait until all
*/
wait_event(part->teardown_wq, (atomic_read(&part->references) == 0));
-
/* now we can begin tearing down the infrastructure */
part->setup_state = XPC_P_TORNDOWN;
part->local_IPI_amo_va = NULL;
}
-
/*
* Called by XP at the time of channel connection registration to cause
* XPC to establish connections to all currently active partitions.
struct xpc_partition *part;
struct xpc_channel *ch;
-
DBUG_ON(ch_number < 0 || ch_number >= XPC_NCHANNELS);
for (partid = 1; partid < XP_MAX_PARTITIONS; partid++) {
}
}
-
void
xpc_connected_callout(struct xpc_channel *ch)
{
"partid=%d, channel=%d\n", ch->partid, ch->number);
ch->func(xpcConnected, ch->partid, ch->number,
- (void *) (u64) ch->local_nentries, ch->key);
+ (void *)(u64)ch->local_nentries, ch->key);
dev_dbg(xpc_chan, "ch->func() returned, reason=xpcConnected, "
"partid=%d, channel=%d\n", ch->partid, ch->number);
}
}
-
/*
* Called by XP at the time of channel connection unregistration to cause
* XPC to teardown all current connections for the specified channel.
struct xpc_partition *part;
struct xpc_channel *ch;
-
DBUG_ON(ch_number < 0 || ch_number >= XPC_NCHANNELS);
/* initiate the channel disconnect for every active partition */
ch->flags |= XPC_C_WDISCONNECT;
XPC_DISCONNECT_CHANNEL(ch, xpcUnregistering,
- &irq_flags);
+ &irq_flags);
}
spin_unlock_irqrestore(&ch->lock, irq_flags);
xpc_disconnect_wait(ch_number);
}
-
/*
* To disconnect a channel, and reflect it back to all who may be waiting.
*
*/
void
xpc_disconnect_channel(const int line, struct xpc_channel *ch,
- enum xpc_retval reason, unsigned long *irq_flags)
+ enum xpc_retval reason, unsigned long *irq_flags)
{
u32 channel_was_connected = (ch->flags & XPC_C_CONNECTED);
-
DBUG_ON(!spin_is_locked(&ch->lock));
- if (ch->flags & (XPC_C_DISCONNECTING | XPC_C_DISCONNECTED)) {
+ if (ch->flags & (XPC_C_DISCONNECTING | XPC_C_DISCONNECTED))
return;
- }
+
DBUG_ON(!(ch->flags & (XPC_C_CONNECTING | XPC_C_CONNECTED)));
dev_dbg(xpc_chan, "reason=%d, line=%d, partid=%d, channel=%d\n",
ch->flags |= (XPC_C_CLOSEREQUEST | XPC_C_DISCONNECTING);
/* some of these may not have been set */
ch->flags &= ~(XPC_C_OPENREQUEST | XPC_C_OPENREPLY |
- XPC_C_ROPENREQUEST | XPC_C_ROPENREPLY |
- XPC_C_CONNECTING | XPC_C_CONNECTED);
+ XPC_C_ROPENREQUEST | XPC_C_ROPENREPLY |
+ XPC_C_CONNECTING | XPC_C_CONNECTED);
xpc_IPI_send_closerequest(ch, irq_flags);
- if (channel_was_connected) {
+ if (channel_was_connected)
ch->flags |= XPC_C_WASCONNECTED;
- }
spin_unlock_irqrestore(&ch->lock, *irq_flags);
wake_up_all(&ch->idle_wq);
} else if ((ch->flags & XPC_C_CONNECTEDCALLOUT_MADE) &&
- !(ch->flags & XPC_C_DISCONNECTINGCALLOUT)) {
+ !(ch->flags & XPC_C_DISCONNECTINGCALLOUT)) {
/* start a kthread that will do the xpcDisconnecting callout */
xpc_create_kthreads(ch, 1, 1);
}
/* wake those waiting to allocate an entry from the local msg queue */
- if (atomic_read(&ch->n_on_msg_allocate_wq) > 0) {
+ if (atomic_read(&ch->n_on_msg_allocate_wq) > 0)
wake_up(&ch->msg_allocate_wq);
- }
spin_lock_irqsave(&ch->lock, *irq_flags);
}
-
void
xpc_disconnect_callout(struct xpc_channel *ch, enum xpc_retval reason)
{
}
}
-
/*
* Wait for a message entry to become available for the specified channel,
* but don't wait any longer than 1 jiffy.
{
enum xpc_retval ret;
-
if (ch->flags & XPC_C_DISCONNECTING) {
- DBUG_ON(ch->reason == xpcInterrupted); // >>> Is this true?
+ DBUG_ON(ch->reason == xpcInterrupted);
return ch->reason;
}
if (ch->flags & XPC_C_DISCONNECTING) {
ret = ch->reason;
- DBUG_ON(ch->reason == xpcInterrupted); // >>> Is this true?
+ DBUG_ON(ch->reason == xpcInterrupted);
} else if (ret == 0) {
ret = xpcTimeout;
} else {
return ret;
}
-
/*
* Allocate an entry for a message from the message queue associated with the
* specified channel.
*/
static enum xpc_retval
xpc_allocate_msg(struct xpc_channel *ch, u32 flags,
- struct xpc_msg **address_of_msg)
+ struct xpc_msg **address_of_msg)
{
struct xpc_msg *msg;
enum xpc_retval ret;
s64 put;
-
/* this reference will be dropped in xpc_send_msg() */
xpc_msgqueue_ref(ch);
return xpcNotConnected;
}
-
/*
* Get the next available message entry from the local message queue.
* If none are available, we'll make sure that we grab the latest
while (1) {
- put = (volatile s64) ch->w_local_GP.put;
- if (put - (volatile s64) ch->w_remote_GP.get <
- ch->local_nentries) {
+ put = ch->w_local_GP.put;
+ rmb(); /* guarantee that .put loads before .get */
+ if (put - ch->w_remote_GP.get < ch->local_nentries) {
/* There are available message entries. We need to try
* to secure one for ourselves. We'll do this by trying
* to increment w_local_GP.put as long as someone else
* doesn't beat us to it. If they do, we'll have to
* try again.
- */
- if (cmpxchg(&ch->w_local_GP.put, put, put + 1) ==
- put) {
+ */
+ if (cmpxchg(&ch->w_local_GP.put, put, put + 1) == put) {
/* we got the entry referenced by put */
break;
}
continue; /* try again */
}
-
/*
* There aren't any available msg entries at this time.
*
* that will cause the IPI handler to fetch the latest
* GP values as if an IPI was sent by the other side.
*/
- if (ret == xpcTimeout) {
+ if (ret == xpcTimeout)
xpc_IPI_send_local_msgrequest(ch);
- }
if (flags & XPC_NOWAIT) {
xpc_msgqueue_deref(ch);
}
}
-
/* get the message's address and initialize it */
- msg = (struct xpc_msg *) ((u64) ch->local_msgqueue +
- (put % ch->local_nentries) * ch->msg_size);
-
+ msg = (struct xpc_msg *)((u64)ch->local_msgqueue +
+ (put % ch->local_nentries) * ch->msg_size);
DBUG_ON(msg->flags != 0);
msg->number = put;
dev_dbg(xpc_chan, "w_local_GP.put changed to %ld; msg=0x%p, "
"msg_number=%ld, partid=%d, channel=%d\n", put + 1,
- (void *) msg, msg->number, ch->partid, ch->number);
+ (void *)msg, msg->number, ch->partid, ch->number);
*address_of_msg = msg;
return xpcSuccess;
}
-
/*
* Allocate an entry for a message from the message queue associated with the
* specified channel. NOTE that this routine can sleep waiting for a message
enum xpc_retval ret = xpcUnknownReason;
struct xpc_msg *msg = NULL;
-
DBUG_ON(partid <= 0 || partid >= XP_MAX_PARTITIONS);
DBUG_ON(ch_number < 0 || ch_number >= part->nchannels);
ret = xpc_allocate_msg(&part->channels[ch_number], flags, &msg);
xpc_part_deref(part);
- if (msg != NULL) {
+ if (msg != NULL)
*payload = &msg->payload;
- }
}
return ret;
}
-
/*
* Now we actually send the messages that are ready to be sent by advancing
* the local message queue's Put value and then send an IPI to the recipient
s64 put = initial_put + 1;
int send_IPI = 0;
-
while (1) {
while (1) {
- if (put == (volatile s64) ch->w_local_GP.put) {
+ if (put == ch->w_local_GP.put)
break;
- }
- msg = (struct xpc_msg *) ((u64) ch->local_msgqueue +
- (put % ch->local_nentries) * ch->msg_size);
+ msg = (struct xpc_msg *)((u64)ch->local_msgqueue +
+ (put % ch->local_nentries) *
+ ch->msg_size);
- if (!(msg->flags & XPC_M_READY)) {
+ if (!(msg->flags & XPC_M_READY))
break;
- }
put++;
}
}
if (cmpxchg_rel(&ch->local_GP->put, initial_put, put) !=
- initial_put) {
+ initial_put) {
/* someone else beat us to it */
- DBUG_ON((volatile s64) ch->local_GP->put < initial_put);
+ DBUG_ON(ch->local_GP->put < initial_put);
break;
}
initial_put = put;
}
- if (send_IPI) {
+ if (send_IPI)
xpc_IPI_send_msgrequest(ch);
- }
}
-
/*
* Common code that does the actual sending of the message by advancing the
* local message queue's Put value and sends an IPI to the partition the
*/
static enum xpc_retval
xpc_send_msg(struct xpc_channel *ch, struct xpc_msg *msg, u8 notify_type,
- xpc_notify_func func, void *key)
+ xpc_notify_func func, void *key)
{
enum xpc_retval ret = xpcSuccess;
struct xpc_notify *notify = notify;
s64 put, msg_number = msg->number;
-
DBUG_ON(notify_type == XPC_N_CALL && func == NULL);
- DBUG_ON((((u64) msg - (u64) ch->local_msgqueue) / ch->msg_size) !=
- msg_number % ch->local_nentries);
+ DBUG_ON((((u64)msg - (u64)ch->local_msgqueue) / ch->msg_size) !=
+ msg_number % ch->local_nentries);
DBUG_ON(msg->flags & XPC_M_READY);
if (ch->flags & XPC_C_DISCONNECTING) {
notify->key = key;
notify->type = notify_type;
- // >>> is a mb() needed here?
+ /* >>> is a mb() needed here? */
if (ch->flags & XPC_C_DISCONNECTING) {
/*
* the notify entry.
*/
if (cmpxchg(¬ify->type, notify_type, 0) ==
- notify_type) {
+ notify_type) {
atomic_dec(&ch->n_to_notify);
ret = ch->reason;
}
/* see if the message is next in line to be sent, if so send it */
put = ch->local_GP->put;
- if (put == msg_number) {
+ if (put == msg_number)
xpc_send_msgs(ch, put);
- }
/* drop the reference grabbed in xpc_allocate_msg() */
xpc_msgqueue_deref(ch);
return ret;
}
-
/*
* Send a message previously allocated using xpc_initiate_allocate() on the
* specified channel connected to the specified partition.
struct xpc_msg *msg = XPC_MSG_ADDRESS(payload);
enum xpc_retval ret;
-
- dev_dbg(xpc_chan, "msg=0x%p, partid=%d, channel=%d\n", (void *) msg,
+ dev_dbg(xpc_chan, "msg=0x%p, partid=%d, channel=%d\n", (void *)msg,
partid, ch_number);
DBUG_ON(partid <= 0 || partid >= XP_MAX_PARTITIONS);
return ret;
}
-
/*
* Send a message previously allocated using xpc_initiate_allocate on the
* specified channel connected to the specified partition.
*/
enum xpc_retval
xpc_initiate_send_notify(partid_t partid, int ch_number, void *payload,
- xpc_notify_func func, void *key)
+ xpc_notify_func func, void *key)
{
struct xpc_partition *part = &xpc_partitions[partid];
struct xpc_msg *msg = XPC_MSG_ADDRESS(payload);
enum xpc_retval ret;
-
- dev_dbg(xpc_chan, "msg=0x%p, partid=%d, channel=%d\n", (void *) msg,
+ dev_dbg(xpc_chan, "msg=0x%p, partid=%d, channel=%d\n", (void *)msg,
partid, ch_number);
DBUG_ON(partid <= 0 || partid >= XP_MAX_PARTITIONS);
DBUG_ON(func == NULL);
ret = xpc_send_msg(&part->channels[ch_number], msg, XPC_N_CALL,
- func, key);
+ func, key);
return ret;
}
-
static struct xpc_msg *
xpc_pull_remote_msg(struct xpc_channel *ch, s64 get)
{
u64 msg_offset;
enum xpc_retval ret;
-
if (mutex_lock_interruptible(&ch->msg_to_pull_mutex) != 0) {
/* we were interrupted by a signal */
return NULL;
msg_index = ch->next_msg_to_pull % ch->remote_nentries;
- DBUG_ON(ch->next_msg_to_pull >=
- (volatile s64) ch->w_remote_GP.put);
- nmsgs = (volatile s64) ch->w_remote_GP.put -
- ch->next_msg_to_pull;
+ DBUG_ON(ch->next_msg_to_pull >= ch->w_remote_GP.put);
+ nmsgs = ch->w_remote_GP.put - ch->next_msg_to_pull;
if (msg_index + nmsgs > ch->remote_nentries) {
/* ignore the ones that wrap the msg queue for now */
nmsgs = ch->remote_nentries - msg_index;
}
msg_offset = msg_index * ch->msg_size;
- msg = (struct xpc_msg *) ((u64) ch->remote_msgqueue +
- msg_offset);
- remote_msg = (struct xpc_msg *) (ch->remote_msgqueue_pa +
- msg_offset);
+ msg = (struct xpc_msg *)((u64)ch->remote_msgqueue + msg_offset);
+ remote_msg = (struct xpc_msg *)(ch->remote_msgqueue_pa +
+ msg_offset);
- if ((ret = xpc_pull_remote_cachelines(part, msg, remote_msg,
- nmsgs * ch->msg_size)) != xpcSuccess) {
+ ret = xpc_pull_remote_cachelines(part, msg, remote_msg,
+ nmsgs * ch->msg_size);
+ if (ret != xpcSuccess) {
dev_dbg(xpc_chan, "failed to pull %d msgs starting with"
" msg %ld from partition %d, channel=%d, "
return NULL;
}
- mb(); /* >>> this may not be needed, we're not sure */
-
ch->next_msg_to_pull += nmsgs;
}
/* return the message we were looking for */
msg_offset = (get % ch->remote_nentries) * ch->msg_size;
- msg = (struct xpc_msg *) ((u64) ch->remote_msgqueue + msg_offset);
+ msg = (struct xpc_msg *)((u64)ch->remote_msgqueue + msg_offset);
return msg;
}
-
/*
* Get a message to be delivered.
*/
struct xpc_msg *msg = NULL;
s64 get;
-
do {
- if ((volatile u32) ch->flags & XPC_C_DISCONNECTING) {
+ if (ch->flags & XPC_C_DISCONNECTING)
break;
- }
- get = (volatile s64) ch->w_local_GP.get;
- if (get == (volatile s64) ch->w_remote_GP.put) {
+ get = ch->w_local_GP.get;
+ rmb(); /* guarantee that .get loads before .put */
+ if (get == ch->w_remote_GP.put)
break;
- }
/* There are messages waiting to be pulled and delivered.
* We need to try to secure one for ourselves. We'll do this
* by trying to increment w_local_GP.get and hope that no one
* else beats us to it. If they do, we'll we'll simply have
* to try again for the next one.
- */
+ */
if (cmpxchg(&ch->w_local_GP.get, get, get + 1) == get) {
/* we got the entry referenced by get */
return msg;
}
-
/*
* Deliver a message to its intended recipient.
*/
{
struct xpc_msg *msg;
-
- if ((msg = xpc_get_deliverable_msg(ch)) != NULL) {
+ msg = xpc_get_deliverable_msg(ch);
+ if (msg != NULL) {
/*
* This ref is taken to protect the payload itself from being
if (ch->func != NULL) {
dev_dbg(xpc_chan, "ch->func() called, msg=0x%p, "
"msg_number=%ld, partid=%d, channel=%d\n",
- (void *) msg, msg->number, ch->partid,
+ (void *)msg, msg->number, ch->partid,
ch->number);
/* deliver the message to its intended recipient */
ch->func(xpcMsgReceived, ch->partid, ch->number,
- &msg->payload, ch->key);
+ &msg->payload, ch->key);
dev_dbg(xpc_chan, "ch->func() returned, msg=0x%p, "
"msg_number=%ld, partid=%d, channel=%d\n",
- (void *) msg, msg->number, ch->partid,
+ (void *)msg, msg->number, ch->partid,
ch->number);
}
}
}
-
/*
* Now we actually acknowledge the messages that have been delivered and ack'd
* by advancing the cached remote message queue's Get value and if requested
s64 get = initial_get + 1;
int send_IPI = 0;
-
while (1) {
while (1) {
- if (get == (volatile s64) ch->w_local_GP.get) {
+ if (get == ch->w_local_GP.get)
break;
- }
- msg = (struct xpc_msg *) ((u64) ch->remote_msgqueue +
- (get % ch->remote_nentries) * ch->msg_size);
+ msg = (struct xpc_msg *)((u64)ch->remote_msgqueue +
+ (get % ch->remote_nentries) *
+ ch->msg_size);
- if (!(msg->flags & XPC_M_DONE)) {
+ if (!(msg->flags & XPC_M_DONE))
break;
- }
msg_flags |= msg->flags;
get++;
}
if (cmpxchg_rel(&ch->local_GP->get, initial_get, get) !=
- initial_get) {
+ initial_get) {
/* someone else beat us to it */
- DBUG_ON((volatile s64) ch->local_GP->get <=
- initial_get);
+ DBUG_ON(ch->local_GP->get <= initial_get);
break;
}
initial_get = get;
}
- if (send_IPI) {
+ if (send_IPI)
xpc_IPI_send_msgrequest(ch);
- }
}
-
/*
* Acknowledge receipt of a delivered message.
*
struct xpc_msg *msg = XPC_MSG_ADDRESS(payload);
s64 get, msg_number = msg->number;
-
DBUG_ON(partid <= 0 || partid >= XP_MAX_PARTITIONS);
DBUG_ON(ch_number < 0 || ch_number >= part->nchannels);
ch = &part->channels[ch_number];
dev_dbg(xpc_chan, "msg=0x%p, msg_number=%ld, partid=%d, channel=%d\n",
- (void *) msg, msg_number, ch->partid, ch->number);
+ (void *)msg, msg_number, ch->partid, ch->number);
- DBUG_ON((((u64) msg - (u64) ch->remote_msgqueue) / ch->msg_size) !=
- msg_number % ch->remote_nentries);
+ DBUG_ON((((u64)msg - (u64)ch->remote_msgqueue) / ch->msg_size) !=
+ msg_number % ch->remote_nentries);
DBUG_ON(msg->flags & XPC_M_DONE);
msg->flags |= XPC_M_DONE;
* been delivered.
*/
get = ch->local_GP->get;
- if (get == msg_number) {
+ if (get == msg_number)
xpc_acknowledge_msgs(ch, get, msg->flags);
- }
/* the call to xpc_msgqueue_ref() was done by xpc_deliver_msg() */
xpc_msgqueue_deref(ch);
}
-
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (c) 2004-2007 Silicon Graphics, Inc. All Rights Reserved.
+ * Copyright (c) 2004-2008 Silicon Graphics, Inc. All Rights Reserved.
*/
-
/*
* Cross Partition Communication (XPC) support - standard version.
*
*
*/
-
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/syscalls.h>
#include <linux/cache.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/reboot.h>
#include <linux/completion.h>
#include <linux/kdebug.h>
+#include <linux/kthread.h>
+#include <linux/uaccess.h>
#include <asm/sn/intr.h>
#include <asm/sn/sn_sal.h>
-#include <asm/uaccess.h>
-#include <asm/sn/xpc.h>
-
+#include "xpc.h"
/* define two XPC debug device structures to be used with dev_dbg() et al */
struct device *xpc_part = &xpc_part_dbg_subname;
struct device *xpc_chan = &xpc_chan_dbg_subname;
-
static int xpc_kdebug_ignore;
-
/* systune related variables for /proc/sys directories */
static int xpc_hb_interval = XPC_HB_DEFAULT_INTERVAL;
static int xpc_hb_check_max_interval = 120;
int xpc_disengage_request_timelimit = XPC_DISENGAGE_REQUEST_DEFAULT_TIMELIMIT;
-static int xpc_disengage_request_min_timelimit = 0;
+static int xpc_disengage_request_min_timelimit; /* = 0 */
static int xpc_disengage_request_max_timelimit = 120;
static ctl_table xpc_sys_xpc_hb_dir[] = {
{
- .ctl_name = CTL_UNNUMBERED,
- .procname = "hb_interval",
- .data = &xpc_hb_interval,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = &proc_dointvec_minmax,
- .strategy = &sysctl_intvec,
- .extra1 = &xpc_hb_min_interval,
- .extra2 = &xpc_hb_max_interval
- },
+ .ctl_name = CTL_UNNUMBERED,
+ .procname = "hb_interval",
+ .data = &xpc_hb_interval,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec_minmax,
+ .strategy = &sysctl_intvec,
+ .extra1 = &xpc_hb_min_interval,
+ .extra2 = &xpc_hb_max_interval},
{
- .ctl_name = CTL_UNNUMBERED,
- .procname = "hb_check_interval",
- .data = &xpc_hb_check_interval,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = &proc_dointvec_minmax,
- .strategy = &sysctl_intvec,
- .extra1 = &xpc_hb_check_min_interval,
- .extra2 = &xpc_hb_check_max_interval
- },
+ .ctl_name = CTL_UNNUMBERED,
+ .procname = "hb_check_interval",
+ .data = &xpc_hb_check_interval,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec_minmax,
+ .strategy = &sysctl_intvec,
+ .extra1 = &xpc_hb_check_min_interval,
+ .extra2 = &xpc_hb_check_max_interval},
{}
};
static ctl_table xpc_sys_xpc_dir[] = {
{
- .ctl_name = CTL_UNNUMBERED,
- .procname = "hb",
- .mode = 0555,
- .child = xpc_sys_xpc_hb_dir
- },
+ .ctl_name = CTL_UNNUMBERED,
+ .procname = "hb",
+ .mode = 0555,
+ .child = xpc_sys_xpc_hb_dir},
{
- .ctl_name = CTL_UNNUMBERED,
- .procname = "disengage_request_timelimit",
- .data = &xpc_disengage_request_timelimit,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = &proc_dointvec_minmax,
- .strategy = &sysctl_intvec,
- .extra1 = &xpc_disengage_request_min_timelimit,
- .extra2 = &xpc_disengage_request_max_timelimit
- },
+ .ctl_name = CTL_UNNUMBERED,
+ .procname = "disengage_request_timelimit",
+ .data = &xpc_disengage_request_timelimit,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec_minmax,
+ .strategy = &sysctl_intvec,
+ .extra1 = &xpc_disengage_request_min_timelimit,
+ .extra2 = &xpc_disengage_request_max_timelimit},
{}
};
static ctl_table xpc_sys_dir[] = {
{
- .ctl_name = CTL_UNNUMBERED,
- .procname = "xpc",
- .mode = 0555,
- .child = xpc_sys_xpc_dir
- },
+ .ctl_name = CTL_UNNUMBERED,
+ .procname = "xpc",
+ .mode = 0555,
+ .child = xpc_sys_xpc_dir},
{}
};
static struct ctl_table_header *xpc_sysctl;
/* notification that the xpc_discovery thread has exited */
static DECLARE_COMPLETION(xpc_discovery_exited);
-
static struct timer_list xpc_hb_timer;
-
static void xpc_kthread_waitmsgs(struct xpc_partition *, struct xpc_channel *);
-
static int xpc_system_reboot(struct notifier_block *, unsigned long, void *);
static struct notifier_block xpc_reboot_notifier = {
.notifier_call = xpc_system_reboot,
.notifier_call = xpc_system_die,
};
-
/*
* Timer function to enforce the timelimit on the partition disengage request.
*/
static void
xpc_timeout_partition_disengage_request(unsigned long data)
{
- struct xpc_partition *part = (struct xpc_partition *) data;
-
+ struct xpc_partition *part = (struct xpc_partition *)data;
DBUG_ON(time_before(jiffies, part->disengage_request_timeout));
- (void) xpc_partition_disengaged(part);
+ (void)xpc_partition_disengaged(part);
DBUG_ON(part->disengage_request_timeout != 0);
DBUG_ON(xpc_partition_engaged(1UL << XPC_PARTID(part)) != 0);
}
-
/*
* Notify the heartbeat check thread that an IRQ has been received.
*/
return IRQ_HANDLED;
}
-
/*
* Timer to produce the heartbeat. The timer structures function is
* already set when this is initially called. A tunable is used to
{
xpc_vars->heartbeat++;
- if (time_after_eq(jiffies, xpc_hb_check_timeout)) {
+ if (time_after_eq(jiffies, xpc_hb_check_timeout))
wake_up_interruptible(&xpc_act_IRQ_wq);
- }
xpc_hb_timer.expires = jiffies + (xpc_hb_interval * HZ);
add_timer(&xpc_hb_timer);
}
-
/*
* This thread is responsible for nearly all of the partition
* activation/deactivation.
{
int last_IRQ_count = 0;
int new_IRQ_count;
- int force_IRQ=0;
-
+ int force_IRQ = 0;
/* this thread was marked active by xpc_hb_init() */
- daemonize(XPC_HB_CHECK_THREAD_NAME);
-
set_cpus_allowed(current, cpumask_of_cpu(XPC_HB_CHECK_CPU));
/* set our heartbeating to other partitions into motion */
xpc_hb_check_timeout = jiffies + (xpc_hb_check_interval * HZ);
xpc_hb_beater(0);
- while (!(volatile int) xpc_exiting) {
+ while (!xpc_exiting) {
dev_dbg(xpc_part, "woke up with %d ticks rem; %d IRQs have "
"been received\n",
- (int) (xpc_hb_check_timeout - jiffies),
+ (int)(xpc_hb_check_timeout - jiffies),
atomic_read(&xpc_act_IRQ_rcvd) - last_IRQ_count);
-
/* checking of remote heartbeats is skewed by IRQ handling */
if (time_after_eq(jiffies, xpc_hb_check_timeout)) {
dev_dbg(xpc_part, "checking remote heartbeats\n");
force_IRQ = 1;
}
-
/* check for outstanding IRQs */
new_IRQ_count = atomic_read(&xpc_act_IRQ_rcvd);
if (last_IRQ_count < new_IRQ_count || force_IRQ != 0) {
last_IRQ_count += xpc_identify_act_IRQ_sender();
if (last_IRQ_count < new_IRQ_count) {
/* retry once to help avoid missing AMO */
- (void) xpc_identify_act_IRQ_sender();
+ (void)xpc_identify_act_IRQ_sender();
}
last_IRQ_count = new_IRQ_count;
xpc_hb_check_timeout = jiffies +
- (xpc_hb_check_interval * HZ);
+ (xpc_hb_check_interval * HZ);
}
/* wait for IRQ or timeout */
- (void) wait_event_interruptible(xpc_act_IRQ_wq,
- (last_IRQ_count < atomic_read(&xpc_act_IRQ_rcvd) ||
- time_after_eq(jiffies, xpc_hb_check_timeout) ||
- (volatile int) xpc_exiting));
+ (void)wait_event_interruptible(xpc_act_IRQ_wq,
+ (last_IRQ_count <
+ atomic_read(&xpc_act_IRQ_rcvd)
+ || time_after_eq(jiffies,
+ xpc_hb_check_timeout) ||
+ xpc_exiting));
}
dev_dbg(xpc_part, "heartbeat checker is exiting\n");
-
/* mark this thread as having exited */
complete(&xpc_hb_checker_exited);
return 0;
}
-
/*
* This thread will attempt to discover other partitions to activate
* based on info provided by SAL. This new thread is short lived and
static int
xpc_initiate_discovery(void *ignore)
{
- daemonize(XPC_DISCOVERY_THREAD_NAME);
-
xpc_discovery();
dev_dbg(xpc_part, "discovery thread is exiting\n");
return 0;
}
-
/*
* Establish first contact with the remote partititon. This involves pulling
* the XPC per partition variables from the remote partition and waiting for
{
enum xpc_retval ret;
-
while ((ret = xpc_pull_remote_vars_part(part)) != xpcSuccess) {
if (ret != xpcRetry) {
XPC_DEACTIVATE_PARTITION(part, ret);
"partition %d\n", XPC_PARTID(part));
/* wait a 1/4 of a second or so */
- (void) msleep_interruptible(250);
+ (void)msleep_interruptible(250);
- if (part->act_state == XPC_P_DEACTIVATING) {
+ if (part->act_state == XPC_P_DEACTIVATING)
return part->reason;
- }
}
return xpc_mark_partition_active(part);
}
-
/*
* The first kthread assigned to a newly activated partition is the one
* created by XPC HB with which it calls xpc_partition_up(). XPC hangs on to
xpc_channel_mgr(struct xpc_partition *part)
{
while (part->act_state != XPC_P_DEACTIVATING ||
- atomic_read(&part->nchannels_active) > 0 ||
- !xpc_partition_disengaged(part)) {
+ atomic_read(&part->nchannels_active) > 0 ||
+ !xpc_partition_disengaged(part)) {
xpc_process_channel_activity(part);
-
/*
* Wait until we've been requested to activate kthreads or
* all of the channel's message queues have been torn down or
* wake him up.
*/
atomic_dec(&part->channel_mgr_requests);
- (void) wait_event_interruptible(part->channel_mgr_wq,
+ (void)wait_event_interruptible(part->channel_mgr_wq,
(atomic_read(&part->channel_mgr_requests) > 0 ||
- (volatile u64) part->local_IPI_amo != 0 ||
- ((volatile u8) part->act_state ==
- XPC_P_DEACTIVATING &&
- atomic_read(&part->nchannels_active) == 0 &&
- xpc_partition_disengaged(part))));
+ part->local_IPI_amo != 0 ||
+ (part->act_state == XPC_P_DEACTIVATING &&
+ atomic_read(&part->nchannels_active) == 0 &&
+ xpc_partition_disengaged(part))));
atomic_set(&part->channel_mgr_requests, 1);
-
- // >>> Does it need to wakeup periodically as well? In case we
- // >>> miscalculated the #of kthreads to wakeup or create?
}
}
-
/*
* When XPC HB determines that a partition has come up, it will create a new
* kthread and that kthread will call this function to attempt to set up the
dev_dbg(xpc_chan, "activating partition %d\n", XPC_PARTID(part));
- if (xpc_setup_infrastructure(part) != xpcSuccess) {
+ if (xpc_setup_infrastructure(part) != xpcSuccess)
return;
- }
/*
* The kthread that XPC HB called us with will become the
* has been dismantled.
*/
- (void) xpc_part_ref(part); /* this will always succeed */
+ (void)xpc_part_ref(part); /* this will always succeed */
- if (xpc_make_first_contact(part) == xpcSuccess) {
+ if (xpc_make_first_contact(part) == xpcSuccess)
xpc_channel_mgr(part);
- }
xpc_part_deref(part);
xpc_teardown_infrastructure(part);
}
-
static int
xpc_activating(void *__partid)
{
- partid_t partid = (u64) __partid;
+ partid_t partid = (u64)__partid;
struct xpc_partition *part = &xpc_partitions[partid];
unsigned long irq_flags;
- struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 };
- int ret;
-
DBUG_ON(partid <= 0 || partid >= XP_MAX_PARTITIONS);
dev_dbg(xpc_part, "bringing partition %d up\n", partid);
- daemonize("xpc%02d", partid);
-
- /*
- * This thread needs to run at a realtime priority to prevent a
- * significant performance degradation.
- */
- ret = sched_setscheduler(current, SCHED_FIFO, ¶m);
- if (ret != 0) {
- dev_warn(xpc_part, "unable to set pid %d to a realtime "
- "priority, ret=%d\n", current->pid, ret);
- }
-
- /* allow this thread and its children to run on any CPU */
- set_cpus_allowed(current, CPU_MASK_ALL);
-
/*
* Register the remote partition's AMOs with SAL so it can handle
* and cleanup errors within that address range should the remote
* reloads and system reboots.
*/
if (sn_register_xp_addr_region(part->remote_amos_page_pa,
- PAGE_SIZE, 1) < 0) {
+ PAGE_SIZE, 1) < 0) {
dev_warn(xpc_part, "xpc_partition_up(%d) failed to register "
- "xp_addr region\n", partid);
+ "xp_addr region\n", partid);
spin_lock_irqsave(&part->act_lock, irq_flags);
part->act_state = XPC_P_INACTIVE;
xpc_allow_hb(partid, xpc_vars);
xpc_IPI_send_activated(part);
-
/*
* xpc_partition_up() holds this thread and marks this partition as
* XPC_P_ACTIVE by calling xpc_hb_mark_active().
*/
- (void) xpc_partition_up(part);
+ (void)xpc_partition_up(part);
xpc_disallow_hb(partid, xpc_vars);
xpc_mark_partition_inactive(part);
return 0;
}
-
void
xpc_activate_partition(struct xpc_partition *part)
{
partid_t partid = XPC_PARTID(part);
unsigned long irq_flags;
- pid_t pid;
-
+ struct task_struct *kthread;
spin_lock_irqsave(&part->act_lock, irq_flags);
spin_unlock_irqrestore(&part->act_lock, irq_flags);
- pid = kernel_thread(xpc_activating, (void *) ((u64) partid), 0);
-
- if (unlikely(pid <= 0)) {
+ kthread = kthread_run(xpc_activating, (void *)((u64)partid), "xpc%02d",
+ partid);
+ if (IS_ERR(kthread)) {
spin_lock_irqsave(&part->act_lock, irq_flags);
part->act_state = XPC_P_INACTIVE;
XPC_SET_REASON(part, xpcCloneKThreadFailed, __LINE__);
}
}
-
/*
* Handle the receipt of a SGI_XPC_NOTIFY IRQ by seeing whether the specified
* partition actually sent it. Since SGI_XPC_NOTIFY IRQs may be shared by more
* than one partition, we use an AMO_t structure per partition to indicate
- * whether a partition has sent an IPI or not. >>> If it has, then wake up the
+ * whether a partition has sent an IPI or not. If it has, then wake up the
* associated kthread to handle it.
*
* All SGI_XPC_NOTIFY IRQs received by XPC are the result of IPIs sent by XPC
irqreturn_t
xpc_notify_IRQ_handler(int irq, void *dev_id)
{
- partid_t partid = (partid_t) (u64) dev_id;
+ partid_t partid = (partid_t) (u64)dev_id;
struct xpc_partition *part = &xpc_partitions[partid];
-
DBUG_ON(partid <= 0 || partid >= XP_MAX_PARTITIONS);
if (xpc_part_ref(part)) {
return IRQ_HANDLED;
}
-
/*
* Check to see if xpc_notify_IRQ_handler() dropped any IPIs on the floor
* because the write to their associated IPI amo completed after the IRQ/IPI
xpc_check_for_channel_activity(part);
part->dropped_IPI_timer.expires = jiffies +
- XPC_P_DROPPED_IPI_WAIT;
+ XPC_P_DROPPED_IPI_WAIT;
add_timer(&part->dropped_IPI_timer);
xpc_part_deref(part);
}
}
-
void
xpc_activate_kthreads(struct xpc_channel *ch, int needed)
{
int assigned = atomic_read(&ch->kthreads_assigned);
int wakeup;
-
DBUG_ON(needed <= 0);
if (idle > 0) {
wake_up_nr(&ch->idle_wq, wakeup);
}
- if (needed <= 0) {
+ if (needed <= 0)
return;
- }
if (needed + assigned > ch->kthreads_assigned_limit) {
needed = ch->kthreads_assigned_limit - assigned;
- // >>>should never be less than 0
- if (needed <= 0) {
+ if (needed <= 0)
return;
- }
}
dev_dbg(xpc_chan, "create %d new kthreads, partid=%d, channel=%d\n",
xpc_create_kthreads(ch, needed, 0);
}
-
/*
* This function is where XPC's kthreads wait for messages to deliver.
*/
do {
/* deliver messages to their intended recipients */
- while ((volatile s64) ch->w_local_GP.get <
- (volatile s64) ch->w_remote_GP.put &&
- !((volatile u32) ch->flags &
- XPC_C_DISCONNECTING)) {
+ while (ch->w_local_GP.get < ch->w_remote_GP.put &&
+ !(ch->flags & XPC_C_DISCONNECTING)) {
xpc_deliver_msg(ch);
}
if (atomic_inc_return(&ch->kthreads_idle) >
- ch->kthreads_idle_limit) {
+ ch->kthreads_idle_limit) {
/* too many idle kthreads on this channel */
atomic_dec(&ch->kthreads_idle);
break;
dev_dbg(xpc_chan, "idle kthread calling "
"wait_event_interruptible_exclusive()\n");
- (void) wait_event_interruptible_exclusive(ch->idle_wq,
- ((volatile s64) ch->w_local_GP.get <
- (volatile s64) ch->w_remote_GP.put ||
- ((volatile u32) ch->flags &
- XPC_C_DISCONNECTING)));
+ (void)wait_event_interruptible_exclusive(ch->idle_wq,
+ (ch->w_local_GP.get < ch->w_remote_GP.put ||
+ (ch->flags & XPC_C_DISCONNECTING)));
atomic_dec(&ch->kthreads_idle);
- } while (!((volatile u32) ch->flags & XPC_C_DISCONNECTING));
+ } while (!(ch->flags & XPC_C_DISCONNECTING));
}
-
static int
-xpc_daemonize_kthread(void *args)
+xpc_kthread_start(void *args)
{
partid_t partid = XPC_UNPACK_ARG1(args);
u16 ch_number = XPC_UNPACK_ARG2(args);
int n_needed;
unsigned long irq_flags;
-
- daemonize("xpc%02dc%d", partid, ch_number);
-
dev_dbg(xpc_chan, "kthread starting, partid=%d, channel=%d\n",
partid, ch_number);
* need one less than total #of messages to deliver.
*/
n_needed = ch->w_remote_GP.put - ch->w_local_GP.get - 1;
- if (n_needed > 0 &&
- !(ch->flags & XPC_C_DISCONNECTING)) {
+ if (n_needed > 0 && !(ch->flags & XPC_C_DISCONNECTING))
xpc_activate_kthreads(ch, n_needed);
- }
+
} else {
spin_unlock_irqrestore(&ch->lock, irq_flags);
}
spin_lock_irqsave(&ch->lock, irq_flags);
if ((ch->flags & XPC_C_CONNECTEDCALLOUT_MADE) &&
- !(ch->flags & XPC_C_DISCONNECTINGCALLOUT)) {
+ !(ch->flags & XPC_C_DISCONNECTINGCALLOUT)) {
ch->flags |= XPC_C_DISCONNECTINGCALLOUT;
spin_unlock_irqrestore(&ch->lock, irq_flags);
return 0;
}
-
/*
* For each partition that XPC has established communications with, there is
* a minimum of one kernel thread assigned to perform any operation that
*/
void
xpc_create_kthreads(struct xpc_channel *ch, int needed,
- int ignore_disconnecting)
+ int ignore_disconnecting)
{
unsigned long irq_flags;
- pid_t pid;
u64 args = XPC_PACK_ARGS(ch->partid, ch->number);
struct xpc_partition *part = &xpc_partitions[ch->partid];
-
+ struct task_struct *kthread;
while (needed-- > 0) {
if (!atomic_inc_not_zero(&ch->kthreads_assigned)) {
/* kthreads assigned had gone to zero */
BUG_ON(!(ch->flags &
- XPC_C_DISCONNECTINGCALLOUT_MADE));
+ XPC_C_DISCONNECTINGCALLOUT_MADE));
break;
}
if (atomic_inc_return(&part->nchannels_engaged) == 1)
xpc_mark_partition_engaged(part);
}
- (void) xpc_part_ref(part);
+ (void)xpc_part_ref(part);
xpc_msgqueue_ref(ch);
- pid = kernel_thread(xpc_daemonize_kthread, (void *) args, 0);
- if (pid < 0) {
+ kthread = kthread_run(xpc_kthread_start, (void *)args,
+ "xpc%02dc%d", ch->partid, ch->number);
+ if (IS_ERR(kthread)) {
/* the fork failed */
/*
* to this channel are blocked in the channel's
* registerer, because the only thing that will unblock
* them is the xpcDisconnecting callout that this
- * failed kernel_thread would have made.
+ * failed kthread_run() would have made.
*/
if (atomic_dec_return(&ch->kthreads_assigned) == 0 &&
xpc_part_deref(part);
if (atomic_read(&ch->kthreads_assigned) <
- ch->kthreads_idle_limit) {
+ ch->kthreads_idle_limit) {
/*
* Flag this as an error only if we have an
* insufficient #of kthreads for the channel
*/
spin_lock_irqsave(&ch->lock, irq_flags);
XPC_DISCONNECT_CHANNEL(ch, xpcLackOfResources,
- &irq_flags);
+ &irq_flags);
spin_unlock_irqrestore(&ch->lock, irq_flags);
}
break;
}
-
- ch->kthreads_created++; // >>> temporary debug only!!!
}
}
-
void
xpc_disconnect_wait(int ch_number)
{
struct xpc_channel *ch;
int wakeup_channel_mgr;
-
/* now wait for all callouts to the caller's function to cease */
for (partid = 1; partid < XP_MAX_PARTITIONS; partid++) {
part = &xpc_partitions[partid];
- if (!xpc_part_ref(part)) {
+ if (!xpc_part_ref(part))
continue;
- }
ch = &part->channels[ch_number];
if (part->act_state != XPC_P_DEACTIVATING) {
spin_lock(&part->IPI_lock);
XPC_SET_IPI_FLAGS(part->local_IPI_amo,
- ch->number, ch->delayed_IPI_flags);
+ ch->number,
+ ch->delayed_IPI_flags);
spin_unlock(&part->IPI_lock);
wakeup_channel_mgr = 1;
}
ch->flags &= ~XPC_C_WDISCONNECT;
spin_unlock_irqrestore(&ch->lock, irq_flags);
- if (wakeup_channel_mgr) {
+ if (wakeup_channel_mgr)
xpc_wakeup_channel_mgr(part);
- }
xpc_part_deref(part);
}
}
-
static void
xpc_do_exit(enum xpc_retval reason)
{
struct xpc_partition *part;
unsigned long printmsg_time, disengage_request_timeout = 0;
-
/* a 'rmmod XPC' and a 'reboot' cannot both end up here together */
DBUG_ON(xpc_exiting == 1);
/* wait for the heartbeat checker thread to exit */
wait_for_completion(&xpc_hb_checker_exited);
-
/* sleep for a 1/3 of a second or so */
- (void) msleep_interruptible(300);
-
+ (void)msleep_interruptible(300);
/* wait for all partitions to become inactive */
part = &xpc_partitions[partid];
if (xpc_partition_disengaged(part) &&
- part->act_state == XPC_P_INACTIVE) {
+ part->act_state == XPC_P_INACTIVE) {
continue;
}
XPC_DEACTIVATE_PARTITION(part, reason);
if (part->disengage_request_timeout >
- disengage_request_timeout) {
+ disengage_request_timeout) {
disengage_request_timeout =
- part->disengage_request_timeout;
+ part->disengage_request_timeout;
}
}
if (xpc_partition_engaged(-1UL)) {
if (time_after(jiffies, printmsg_time)) {
dev_info(xpc_part, "waiting for remote "
- "partitions to disengage, timeout in "
- "%ld seconds\n",
- (disengage_request_timeout - jiffies)
- / HZ);
+ "partitions to disengage, timeout in "
+ "%ld seconds\n",
+ (disengage_request_timeout - jiffies)
+ / HZ);
printmsg_time = jiffies +
- (XPC_DISENGAGE_PRINTMSG_INTERVAL * HZ);
+ (XPC_DISENGAGE_PRINTMSG_INTERVAL * HZ);
printed_waiting_msg = 1;
}
} else if (active_part_count > 0) {
if (printed_waiting_msg) {
dev_info(xpc_part, "waiting for local partition"
- " to disengage\n");
+ " to disengage\n");
printed_waiting_msg = 0;
}
} else {
if (!xpc_disengage_request_timedout) {
dev_info(xpc_part, "all partitions have "
- "disengaged\n");
+ "disengaged\n");
}
break;
}
/* sleep for a 1/3 of a second or so */
- (void) msleep_interruptible(300);
+ (void)msleep_interruptible(300);
} while (1);
DBUG_ON(xpc_partition_engaged(-1UL));
-
/* indicate to others that our reserved page is uninitialized */
xpc_rsvd_page->vars_pa = 0;
if (reason == xpcUnloading) {
/* take ourselves off of the reboot_notifier_list */
- (void) unregister_reboot_notifier(&xpc_reboot_notifier);
+ (void)unregister_reboot_notifier(&xpc_reboot_notifier);
/* take ourselves off of the die_notifier list */
- (void) unregister_die_notifier(&xpc_die_notifier);
+ (void)unregister_die_notifier(&xpc_die_notifier);
}
/* close down protections for IPI operations */
xpc_restrict_IPI_ops();
-
/* clear the interface to XPC's functions */
xpc_clear_interface();
- if (xpc_sysctl) {
+ if (xpc_sysctl)
unregister_sysctl_table(xpc_sysctl);
- }
kfree(xpc_remote_copy_buffer_base);
}
-
/*
* This function is called when the system is being rebooted.
*/
{
enum xpc_retval reason;
-
switch (event) {
case SYS_RESTART:
reason = xpcSystemReboot;
return NOTIFY_DONE;
}
-
/*
* Notify other partitions to disengage from all references to our memory.
*/
unsigned long engaged;
long time, printmsg_time, disengage_request_timeout;
-
/* keep xpc_hb_checker thread from doing anything (just in case) */
xpc_exiting = 1;
- xpc_vars->heartbeating_to_mask = 0; /* indicate we're deactivated */
+ xpc_vars->heartbeating_to_mask = 0; /* indicate we're deactivated */
for (partid = 1; partid < XP_MAX_PARTITIONS; partid++) {
part = &xpc_partitions[partid];
if (!XPC_SUPPORTS_DISENGAGE_REQUEST(part->
- remote_vars_version)) {
+ remote_vars_version)) {
/* just in case it was left set by an earlier XPC */
xpc_clear_partition_engaged(1UL << partid);
}
if (xpc_partition_engaged(1UL << partid) ||
- part->act_state != XPC_P_INACTIVE) {
+ part->act_state != XPC_P_INACTIVE) {
xpc_request_partition_disengage(part);
xpc_mark_partition_disengaged(part);
xpc_IPI_send_disengage(part);
time = rtc_time();
printmsg_time = time +
- (XPC_DISENGAGE_PRINTMSG_INTERVAL * sn_rtc_cycles_per_second);
+ (XPC_DISENGAGE_PRINTMSG_INTERVAL * sn_rtc_cycles_per_second);
disengage_request_timeout = time +
- (xpc_disengage_request_timelimit * sn_rtc_cycles_per_second);
+ (xpc_disengage_request_timelimit * sn_rtc_cycles_per_second);
/* wait for all other partitions to disengage from us */
for (partid = 1; partid < XP_MAX_PARTITIONS; partid++) {
if (engaged & (1UL << partid)) {
dev_info(xpc_part, "disengage from "
- "remote partition %d timed "
- "out\n", partid);
+ "remote partition %d timed "
+ "out\n", partid);
}
}
break;
if (time >= printmsg_time) {
dev_info(xpc_part, "waiting for remote partitions to "
- "disengage, timeout in %ld seconds\n",
- (disengage_request_timeout - time) /
- sn_rtc_cycles_per_second);
+ "disengage, timeout in %ld seconds\n",
+ (disengage_request_timeout - time) /
+ sn_rtc_cycles_per_second);
printmsg_time = time +
- (XPC_DISENGAGE_PRINTMSG_INTERVAL *
- sn_rtc_cycles_per_second);
+ (XPC_DISENGAGE_PRINTMSG_INTERVAL *
+ sn_rtc_cycles_per_second);
}
}
}
-
/*
* This function is called when the system is being restarted or halted due
* to some sort of system failure. If this is the case we need to notify the
case DIE_KDEBUG_ENTER:
/* Should lack of heartbeat be ignored by other partitions? */
- if (!xpc_kdebug_ignore) {
+ if (!xpc_kdebug_ignore)
break;
- }
+
/* fall through */
case DIE_MCA_MONARCH_ENTER:
case DIE_INIT_MONARCH_ENTER:
case DIE_KDEBUG_LEAVE:
/* Is lack of heartbeat being ignored by other partitions? */
- if (!xpc_kdebug_ignore) {
+ if (!xpc_kdebug_ignore)
break;
- }
+
/* fall through */
case DIE_MCA_MONARCH_LEAVE:
case DIE_INIT_MONARCH_LEAVE:
return NOTIFY_DONE;
}
-
int __init
xpc_init(void)
{
int ret;
partid_t partid;
struct xpc_partition *part;
- pid_t pid;
+ struct task_struct *kthread;
size_t buf_size;
-
- if (!ia64_platform_is("sn2")) {
+ if (!ia64_platform_is("sn2"))
return -ENODEV;
- }
-
buf_size = max(XPC_RP_VARS_SIZE,
- XPC_RP_HEADER_SIZE + XP_NASID_MASK_BYTES);
+ XPC_RP_HEADER_SIZE + XP_NASID_MASK_BYTES);
xpc_remote_copy_buffer = xpc_kmalloc_cacheline_aligned(buf_size,
- GFP_KERNEL, &xpc_remote_copy_buffer_base);
+ GFP_KERNEL,
+ &xpc_remote_copy_buffer_base);
if (xpc_remote_copy_buffer == NULL)
return -ENOMEM;
for (partid = 1; partid < XP_MAX_PARTITIONS; partid++) {
part = &xpc_partitions[partid];
- DBUG_ON((u64) part != L1_CACHE_ALIGN((u64) part));
+ DBUG_ON((u64)part != L1_CACHE_ALIGN((u64)part));
part->act_IRQ_rcvd = 0;
spin_lock_init(&part->act_lock);
init_timer(&part->disengage_request_timer);
part->disengage_request_timer.function =
- xpc_timeout_partition_disengage_request;
- part->disengage_request_timer.data = (unsigned long) part;
+ xpc_timeout_partition_disengage_request;
+ part->disengage_request_timer.data = (unsigned long)part;
part->setup_state = XPC_P_UNSET;
init_waitqueue_head(&part->teardown_wq);
* but rather immediately process the interrupt.
*/
ret = request_irq(SGI_XPC_ACTIVATE, xpc_act_IRQ_handler, 0,
- "xpc hb", NULL);
+ "xpc hb", NULL);
if (ret != 0) {
dev_err(xpc_part, "can't register ACTIVATE IRQ handler, "
"errno=%d\n", -ret);
xpc_restrict_IPI_ops();
- if (xpc_sysctl) {
+ if (xpc_sysctl)
unregister_sysctl_table(xpc_sysctl);
- }
kfree(xpc_remote_copy_buffer_base);
return -EBUSY;
free_irq(SGI_XPC_ACTIVATE, NULL);
xpc_restrict_IPI_ops();
- if (xpc_sysctl) {
+ if (xpc_sysctl)
unregister_sysctl_table(xpc_sysctl);
- }
kfree(xpc_remote_copy_buffer_base);
return -EBUSY;
}
-
/* add ourselves to the reboot_notifier_list */
ret = register_reboot_notifier(&xpc_reboot_notifier);
- if (ret != 0) {
+ if (ret != 0)
dev_warn(xpc_part, "can't register reboot notifier\n");
- }
/* add ourselves to the die_notifier list */
ret = register_die_notifier(&xpc_die_notifier);
- if (ret != 0) {
+ if (ret != 0)
dev_warn(xpc_part, "can't register die notifier\n");
- }
init_timer(&xpc_hb_timer);
xpc_hb_timer.function = xpc_hb_beater;
* The real work-horse behind xpc. This processes incoming
* interrupts and monitors remote heartbeats.
*/
- pid = kernel_thread(xpc_hb_checker, NULL, 0);
- if (pid < 0) {
+ kthread = kthread_run(xpc_hb_checker, NULL, XPC_HB_CHECK_THREAD_NAME);
+ if (IS_ERR(kthread)) {
dev_err(xpc_part, "failed while forking hb check thread\n");
/* indicate to others that our reserved page is uninitialized */
xpc_rsvd_page->vars_pa = 0;
/* take ourselves off of the reboot_notifier_list */
- (void) unregister_reboot_notifier(&xpc_reboot_notifier);
+ (void)unregister_reboot_notifier(&xpc_reboot_notifier);
/* take ourselves off of the die_notifier list */
- (void) unregister_die_notifier(&xpc_die_notifier);
+ (void)unregister_die_notifier(&xpc_die_notifier);
del_timer_sync(&xpc_hb_timer);
free_irq(SGI_XPC_ACTIVATE, NULL);
xpc_restrict_IPI_ops();
- if (xpc_sysctl) {
+ if (xpc_sysctl)
unregister_sysctl_table(xpc_sysctl);
- }
kfree(xpc_remote_copy_buffer_base);
return -EBUSY;
}
-
/*
* Startup a thread that will attempt to discover other partitions to
* activate based on info provided by SAL. This new thread is short
* lived and will exit once discovery is complete.
*/
- pid = kernel_thread(xpc_initiate_discovery, NULL, 0);
- if (pid < 0) {
+ kthread = kthread_run(xpc_initiate_discovery, NULL,
+ XPC_DISCOVERY_THREAD_NAME);
+ if (IS_ERR(kthread)) {
dev_err(xpc_part, "failed while forking discovery thread\n");
/* mark this new thread as a non-starter */
return -EBUSY;
}
-
/* set the interface to point at XPC's functions */
xpc_set_interface(xpc_initiate_connect, xpc_initiate_disconnect,
xpc_initiate_allocate, xpc_initiate_send,
return 0;
}
-module_init(xpc_init);
+module_init(xpc_init);
void __exit
xpc_exit(void)
{
xpc_do_exit(xpcUnloading);
}
-module_exit(xpc_exit);
+module_exit(xpc_exit);
MODULE_AUTHOR("Silicon Graphics, Inc.");
MODULE_DESCRIPTION("Cross Partition Communication (XPC) support");
module_param(xpc_hb_interval, int, 0);
MODULE_PARM_DESC(xpc_hb_interval, "Number of seconds between "
- "heartbeat increments.");
+ "heartbeat increments.");
module_param(xpc_hb_check_interval, int, 0);
MODULE_PARM_DESC(xpc_hb_check_interval, "Number of seconds between "
- "heartbeat checks.");
+ "heartbeat checks.");
module_param(xpc_disengage_request_timelimit, int, 0);
MODULE_PARM_DESC(xpc_disengage_request_timelimit, "Number of seconds to wait "
- "for disengage request to complete.");
+ "for disengage request to complete.");
module_param(xpc_kdebug_ignore, int, 0);
MODULE_PARM_DESC(xpc_kdebug_ignore, "Should lack of heartbeat be ignored by "
- "other partitions when dropping into kdebug.");
-
+ "other partitions when dropping into kdebug.");
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (c) 2004-2006 Silicon Graphics, Inc. All Rights Reserved.
+ * Copyright (c) 2004-2008 Silicon Graphics, Inc. All Rights Reserved.
*/
-
/*
* Cross Partition Communication (XPC) partition support.
*
*
*/
-
#include <linux/kernel.h>
#include <linux/sysctl.h>
#include <linux/cache.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/nodepda.h>
#include <asm/sn/addrs.h>
-#include <asm/sn/xpc.h>
-
+#include "xpc.h"
/* XPC is exiting flag */
int xpc_exiting;
-
/* SH_IPI_ACCESS shub register value on startup */
static u64 xpc_sh1_IPI_access;
static u64 xpc_sh2_IPI_access0;
static u64 xpc_sh2_IPI_access2;
static u64 xpc_sh2_IPI_access3;
-
/* original protection values for each node */
u64 xpc_prot_vec[MAX_NUMNODES];
-
/* this partition's reserved page pointers */
struct xpc_rsvd_page *xpc_rsvd_page;
static u64 *xpc_part_nasids;
static int xp_nasid_mask_bytes; /* actual size in bytes of nasid mask */
static int xp_nasid_mask_words; /* actual size in words of nasid mask */
-
/*
* For performance reasons, each entry of xpc_partitions[] is cacheline
* aligned. And xpc_partitions[] is padded with an additional entry at the
*/
struct xpc_partition xpc_partitions[XP_MAX_PARTITIONS + 1];
-
/*
* Generic buffer used to store a local copy of portions of a remote
* partition's reserved page (either its header and part_nasids mask,
char *xpc_remote_copy_buffer;
void *xpc_remote_copy_buffer_base;
-
/*
* Guarantee that the kmalloc'd memory is cacheline aligned.
*/
{
/* see if kmalloc will give us cachline aligned memory by default */
*base = kmalloc(size, flags);
- if (*base == NULL) {
+ if (*base == NULL)
return NULL;
- }
- if ((u64) *base == L1_CACHE_ALIGN((u64) *base)) {
+
+ if ((u64)*base == L1_CACHE_ALIGN((u64)*base))
return *base;
- }
+
kfree(*base);
/* nope, we'll have to do it ourselves */
*base = kmalloc(size + L1_CACHE_BYTES, flags);
- if (*base == NULL) {
+ if (*base == NULL)
return NULL;
- }
- return (void *) L1_CACHE_ALIGN((u64) *base);
-}
+ return (void *)L1_CACHE_ALIGN((u64)*base);
+}
/*
* Given a nasid, get the physical address of the partition's reserved page
u64 buf_len = 0;
void *buf_base = NULL;
-
while (1) {
status = sn_partition_reserved_page_pa(buf, &cookie, &rp_pa,
- &len);
+ &len);
dev_dbg(xpc_part, "SAL returned with status=%li, cookie="
"0x%016lx, address=0x%016lx, len=0x%016lx\n",
status, cookie, rp_pa, len);
- if (status != SALRET_MORE_PASSES) {
+ if (status != SALRET_MORE_PASSES)
break;
- }
if (L1_CACHE_ALIGN(len) > buf_len) {
kfree(buf_base);
buf_len = L1_CACHE_ALIGN(len);
- buf = (u64) xpc_kmalloc_cacheline_aligned(buf_len,
- GFP_KERNEL, &buf_base);
+ buf = (u64)xpc_kmalloc_cacheline_aligned(buf_len,
+ GFP_KERNEL,
+ &buf_base);
if (buf_base == NULL) {
dev_err(xpc_part, "unable to kmalloc "
"len=0x%016lx\n", buf_len);
}
bte_res = xp_bte_copy(rp_pa, buf, buf_len,
- (BTE_NOTIFY | BTE_WACQUIRE), NULL);
+ (BTE_NOTIFY | BTE_WACQUIRE), NULL);
if (bte_res != BTE_SUCCESS) {
dev_dbg(xpc_part, "xp_bte_copy failed %i\n", bte_res);
status = SALRET_ERROR;
kfree(buf_base);
- if (status != SALRET_OK) {
+ if (status != SALRET_OK)
rp_pa = 0;
- }
+
dev_dbg(xpc_part, "reserved page at phys address 0x%016lx\n", rp_pa);
return rp_pa;
}
-
/*
* Fill the partition reserved page with the information needed by
* other partitions to discover we are alive and establish initial
u64 rp_pa, nasid_array = 0;
int i, ret;
-
/* get the local reserved page's address */
preempt_disable();
dev_err(xpc_part, "SAL failed to locate the reserved page\n");
return NULL;
}
- rp = (struct xpc_rsvd_page *) __va(rp_pa);
+ rp = (struct xpc_rsvd_page *)__va(rp_pa);
if (rp->partid != sn_partition_id) {
dev_err(xpc_part, "the reserved page's partid of %d should be "
* on subsequent loads of XPC. This AMO page is never freed, and its
* memory protections are never restricted.
*/
- if ((amos_page = xpc_vars->amos_page) == NULL) {
- amos_page = (AMO_t *) TO_AMO(uncached_alloc_page(0));
+ amos_page = xpc_vars->amos_page;
+ if (amos_page == NULL) {
+ amos_page = (AMO_t *)TO_AMO(uncached_alloc_page(0));
if (amos_page == NULL) {
dev_err(xpc_part, "can't allocate page of AMOs\n");
return NULL;
* when xpc_allow_IPI_ops() is called via xpc_hb_init().
*/
if (!enable_shub_wars_1_1()) {
- ret = sn_change_memprotect(ia64_tpa((u64) amos_page),
- PAGE_SIZE, SN_MEMPROT_ACCESS_CLASS_1,
- &nasid_array);
+ ret = sn_change_memprotect(ia64_tpa((u64)amos_page),
+ PAGE_SIZE,
+ SN_MEMPROT_ACCESS_CLASS_1,
+ &nasid_array);
if (ret != 0) {
dev_err(xpc_part, "can't change memory "
"protections\n");
uncached_free_page(__IA64_UNCACHED_OFFSET |
- TO_PHYS((u64) amos_page));
+ TO_PHYS((u64)amos_page));
return NULL;
}
}
- } else if (!IS_AMO_ADDRESS((u64) amos_page)) {
+ } else if (!IS_AMO_ADDRESS((u64)amos_page)) {
/*
* EFI's XPBOOT can also set amos_page in the reserved page,
* but it happens to leave it as an uncached physical address
* and we need it to be an uncached virtual, so we'll have to
* convert it.
*/
- if (!IS_AMO_PHYS_ADDRESS((u64) amos_page)) {
+ if (!IS_AMO_PHYS_ADDRESS((u64)amos_page)) {
dev_err(xpc_part, "previously used amos_page address "
- "is bad = 0x%p\n", (void *) amos_page);
+ "is bad = 0x%p\n", (void *)amos_page);
return NULL;
}
- amos_page = (AMO_t *) TO_AMO((u64) amos_page);
+ amos_page = (AMO_t *)TO_AMO((u64)amos_page);
}
/* clear xpc_vars */
xpc_vars->act_nasid = cpuid_to_nasid(0);
xpc_vars->act_phys_cpuid = cpu_physical_id(0);
xpc_vars->vars_part_pa = __pa(xpc_vars_part);
- xpc_vars->amos_page_pa = ia64_tpa((u64) amos_page);
- xpc_vars->amos_page = amos_page; /* save for next load of XPC */
-
+ xpc_vars->amos_page_pa = ia64_tpa((u64)amos_page);
+ xpc_vars->amos_page = amos_page; /* save for next load of XPC */
/* clear xpc_vars_part */
- memset((u64 *) xpc_vars_part, 0, sizeof(struct xpc_vars_part) *
- XP_MAX_PARTITIONS);
+ memset((u64 *)xpc_vars_part, 0, sizeof(struct xpc_vars_part) *
+ XP_MAX_PARTITIONS);
/* initialize the activate IRQ related AMO variables */
- for (i = 0; i < xp_nasid_mask_words; i++) {
- (void) xpc_IPI_init(XPC_ACTIVATE_IRQ_AMOS + i);
- }
+ for (i = 0; i < xp_nasid_mask_words; i++)
+ (void)xpc_IPI_init(XPC_ACTIVATE_IRQ_AMOS + i);
/* initialize the engaged remote partitions related AMO variables */
- (void) xpc_IPI_init(XPC_ENGAGED_PARTITIONS_AMO);
- (void) xpc_IPI_init(XPC_DISENGAGE_REQUEST_AMO);
+ (void)xpc_IPI_init(XPC_ENGAGED_PARTITIONS_AMO);
+ (void)xpc_IPI_init(XPC_DISENGAGE_REQUEST_AMO);
/* timestamp of when reserved page was setup by XPC */
rp->stamp = CURRENT_TIME;
return rp;
}
-
/*
* Change protections to allow IPI operations (and AMO operations on
* Shub 1.1 systems).
int node;
int nasid;
-
- // >>> Change SH_IPI_ACCESS code to use SAL call once it is available.
+ /* >>> Change SH_IPI_ACCESS code to use SAL call once it is available */
if (is_shub2()) {
xpc_sh2_IPI_access0 =
- (u64) HUB_L((u64 *) LOCAL_MMR_ADDR(SH2_IPI_ACCESS0));
+ (u64)HUB_L((u64 *)LOCAL_MMR_ADDR(SH2_IPI_ACCESS0));
xpc_sh2_IPI_access1 =
- (u64) HUB_L((u64 *) LOCAL_MMR_ADDR(SH2_IPI_ACCESS1));
+ (u64)HUB_L((u64 *)LOCAL_MMR_ADDR(SH2_IPI_ACCESS1));
xpc_sh2_IPI_access2 =
- (u64) HUB_L((u64 *) LOCAL_MMR_ADDR(SH2_IPI_ACCESS2));
+ (u64)HUB_L((u64 *)LOCAL_MMR_ADDR(SH2_IPI_ACCESS2));
xpc_sh2_IPI_access3 =
- (u64) HUB_L((u64 *) LOCAL_MMR_ADDR(SH2_IPI_ACCESS3));
+ (u64)HUB_L((u64 *)LOCAL_MMR_ADDR(SH2_IPI_ACCESS3));
for_each_online_node(node) {
nasid = cnodeid_to_nasid(node);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS0),
- -1UL);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS1),
- -1UL);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS2),
- -1UL);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS3),
- -1UL);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS0),
+ -1UL);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS1),
+ -1UL);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS2),
+ -1UL);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS3),
+ -1UL);
}
} else {
xpc_sh1_IPI_access =
- (u64) HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_IPI_ACCESS));
+ (u64)HUB_L((u64 *)LOCAL_MMR_ADDR(SH1_IPI_ACCESS));
for_each_online_node(node) {
nasid = cnodeid_to_nasid(node);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid, SH1_IPI_ACCESS),
- -1UL);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid, SH1_IPI_ACCESS),
+ -1UL);
/*
* Since the BIST collides with memory operations on
*/
if (enable_shub_wars_1_1()) {
/* open up everything */
- xpc_prot_vec[node] = (u64) HUB_L((u64 *)
- GLOBAL_MMR_ADDR(nasid,
- SH1_MD_DQLP_MMR_DIR_PRIVEC0));
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid,
- SH1_MD_DQLP_MMR_DIR_PRIVEC0),
- -1UL);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid,
- SH1_MD_DQRP_MMR_DIR_PRIVEC0),
- -1UL);
+ xpc_prot_vec[node] = (u64)HUB_L((u64 *)
+ GLOBAL_MMR_ADDR
+ (nasid,
+ SH1_MD_DQLP_MMR_DIR_PRIVEC0));
+ HUB_S((u64 *)
+ GLOBAL_MMR_ADDR(nasid,
+ SH1_MD_DQLP_MMR_DIR_PRIVEC0),
+ -1UL);
+ HUB_S((u64 *)
+ GLOBAL_MMR_ADDR(nasid,
+ SH1_MD_DQRP_MMR_DIR_PRIVEC0),
+ -1UL);
}
}
}
}
-
/*
* Restrict protections to disallow IPI operations (and AMO operations on
* Shub 1.1 systems).
int node;
int nasid;
-
- // >>> Change SH_IPI_ACCESS code to use SAL call once it is available.
+ /* >>> Change SH_IPI_ACCESS code to use SAL call once it is available */
if (is_shub2()) {
for_each_online_node(node) {
nasid = cnodeid_to_nasid(node);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS0),
- xpc_sh2_IPI_access0);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS1),
- xpc_sh2_IPI_access1);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS2),
- xpc_sh2_IPI_access2);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS3),
- xpc_sh2_IPI_access3);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS0),
+ xpc_sh2_IPI_access0);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS1),
+ xpc_sh2_IPI_access1);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS2),
+ xpc_sh2_IPI_access2);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid, SH2_IPI_ACCESS3),
+ xpc_sh2_IPI_access3);
}
} else {
for_each_online_node(node) {
nasid = cnodeid_to_nasid(node);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid, SH1_IPI_ACCESS),
- xpc_sh1_IPI_access);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid, SH1_IPI_ACCESS),
+ xpc_sh1_IPI_access);
if (enable_shub_wars_1_1()) {
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid,
- SH1_MD_DQLP_MMR_DIR_PRIVEC0),
- xpc_prot_vec[node]);
- HUB_S((u64 *) GLOBAL_MMR_ADDR(nasid,
- SH1_MD_DQRP_MMR_DIR_PRIVEC0),
- xpc_prot_vec[node]);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid,
+ SH1_MD_DQLP_MMR_DIR_PRIVEC0),
+ xpc_prot_vec[node]);
+ HUB_S((u64 *)GLOBAL_MMR_ADDR(nasid,
+ SH1_MD_DQRP_MMR_DIR_PRIVEC0),
+ xpc_prot_vec[node]);
}
}
}
}
-
/*
* At periodic intervals, scan through all active partitions and ensure
* their heartbeat is still active. If not, the partition is deactivated.
partid_t partid;
bte_result_t bres;
-
- remote_vars = (struct xpc_vars *) xpc_remote_copy_buffer;
+ remote_vars = (struct xpc_vars *)xpc_remote_copy_buffer;
for (partid = 1; partid < XP_MAX_PARTITIONS; partid++) {
- if (xpc_exiting) {
+ if (xpc_exiting)
break;
- }
- if (partid == sn_partition_id) {
+ if (partid == sn_partition_id)
continue;
- }
part = &xpc_partitions[partid];
if (part->act_state == XPC_P_INACTIVE ||
- part->act_state == XPC_P_DEACTIVATING) {
+ part->act_state == XPC_P_DEACTIVATING) {
continue;
}
/* pull the remote_hb cache line */
bres = xp_bte_copy(part->remote_vars_pa,
- (u64) remote_vars,
- XPC_RP_VARS_SIZE,
- (BTE_NOTIFY | BTE_WACQUIRE), NULL);
+ (u64)remote_vars,
+ XPC_RP_VARS_SIZE,
+ (BTE_NOTIFY | BTE_WACQUIRE), NULL);
if (bres != BTE_SUCCESS) {
XPC_DEACTIVATE_PARTITION(part,
- xpc_map_bte_errors(bres));
+ xpc_map_bte_errors(bres));
continue;
}
remote_vars->heartbeating_to_mask);
if (((remote_vars->heartbeat == part->last_heartbeat) &&
- (remote_vars->heartbeat_offline == 0)) ||
- !xpc_hb_allowed(sn_partition_id, remote_vars)) {
+ (remote_vars->heartbeat_offline == 0)) ||
+ !xpc_hb_allowed(sn_partition_id, remote_vars)) {
XPC_DEACTIVATE_PARTITION(part, xpcNoHeartbeat);
continue;
}
}
-
/*
* Get a copy of a portion of the remote partition's rsvd page.
*
*/
static enum xpc_retval
xpc_get_remote_rp(int nasid, u64 *discovered_nasids,
- struct xpc_rsvd_page *remote_rp, u64 *remote_rp_pa)
+ struct xpc_rsvd_page *remote_rp, u64 *remote_rp_pa)
{
int bres, i;
-
/* get the reserved page's physical address */
*remote_rp_pa = xpc_get_rsvd_page_pa(nasid);
- if (*remote_rp_pa == 0) {
+ if (*remote_rp_pa == 0)
return xpcNoRsvdPageAddr;
- }
-
/* pull over the reserved page header and part_nasids mask */
- bres = xp_bte_copy(*remote_rp_pa, (u64) remote_rp,
- XPC_RP_HEADER_SIZE + xp_nasid_mask_bytes,
- (BTE_NOTIFY | BTE_WACQUIRE), NULL);
- if (bres != BTE_SUCCESS) {
+ bres = xp_bte_copy(*remote_rp_pa, (u64)remote_rp,
+ XPC_RP_HEADER_SIZE + xp_nasid_mask_bytes,
+ (BTE_NOTIFY | BTE_WACQUIRE), NULL);
+ if (bres != BTE_SUCCESS)
return xpc_map_bte_errors(bres);
- }
-
if (discovered_nasids != NULL) {
u64 *remote_part_nasids = XPC_RP_PART_NASIDS(remote_rp);
-
- for (i = 0; i < xp_nasid_mask_words; i++) {
+ for (i = 0; i < xp_nasid_mask_words; i++)
discovered_nasids[i] |= remote_part_nasids[i];
- }
}
-
/* check that the partid is for another partition */
if (remote_rp->partid < 1 ||
- remote_rp->partid > (XP_MAX_PARTITIONS - 1)) {
+ remote_rp->partid > (XP_MAX_PARTITIONS - 1)) {
return xpcInvalidPartid;
}
- if (remote_rp->partid == sn_partition_id) {
+ if (remote_rp->partid == sn_partition_id)
return xpcLocalPartid;
- }
-
if (XPC_VERSION_MAJOR(remote_rp->version) !=
- XPC_VERSION_MAJOR(XPC_RP_VERSION)) {
+ XPC_VERSION_MAJOR(XPC_RP_VERSION)) {
return xpcBadVersion;
}
return xpcSuccess;
}
-
/*
* Get a copy of the remote partition's XPC variables from the reserved page.
*
{
int bres;
-
- if (remote_vars_pa == 0) {
+ if (remote_vars_pa == 0)
return xpcVarsNotSet;
- }
/* pull over the cross partition variables */
- bres = xp_bte_copy(remote_vars_pa, (u64) remote_vars, XPC_RP_VARS_SIZE,
- (BTE_NOTIFY | BTE_WACQUIRE), NULL);
- if (bres != BTE_SUCCESS) {
+ bres = xp_bte_copy(remote_vars_pa, (u64)remote_vars, XPC_RP_VARS_SIZE,
+ (BTE_NOTIFY | BTE_WACQUIRE), NULL);
+ if (bres != BTE_SUCCESS)
return xpc_map_bte_errors(bres);
- }
if (XPC_VERSION_MAJOR(remote_vars->version) !=
- XPC_VERSION_MAJOR(XPC_V_VERSION)) {
+ XPC_VERSION_MAJOR(XPC_V_VERSION)) {
return xpcBadVersion;
}
return xpcSuccess;
}
-
/*
* Update the remote partition's info.
*/
static void
xpc_update_partition_info(struct xpc_partition *part, u8 remote_rp_version,
- struct timespec *remote_rp_stamp, u64 remote_rp_pa,
- u64 remote_vars_pa, struct xpc_vars *remote_vars)
+ struct timespec *remote_rp_stamp, u64 remote_rp_pa,
+ u64 remote_vars_pa, struct xpc_vars *remote_vars)
{
part->remote_rp_version = remote_rp_version;
dev_dbg(xpc_part, " remote_rp_version = 0x%016x\n",
part->remote_vars_version);
}
-
/*
* Prior code has determined the nasid which generated an IPI. Inspect
* that nasid to determine if its partition needs to be activated or
struct xpc_partition *part;
enum xpc_retval ret;
-
/* pull over the reserved page structure */
- remote_rp = (struct xpc_rsvd_page *) xpc_remote_copy_buffer;
+ remote_rp = (struct xpc_rsvd_page *)xpc_remote_copy_buffer;
ret = xpc_get_remote_rp(nasid, NULL, remote_rp, &remote_rp_pa);
if (ret != xpcSuccess) {
dev_warn(xpc_part, "unable to get reserved page from nasid %d, "
- "which sent interrupt, reason=%d\n", nasid, ret);
+ "which sent interrupt, reason=%d\n", nasid, ret);
return;
}
remote_vars_pa = remote_rp->vars_pa;
remote_rp_version = remote_rp->version;
- if (XPC_SUPPORTS_RP_STAMP(remote_rp_version)) {
+ if (XPC_SUPPORTS_RP_STAMP(remote_rp_version))
remote_rp_stamp = remote_rp->stamp;
- }
+
partid = remote_rp->partid;
part = &xpc_partitions[partid];
-
/* pull over the cross partition variables */
- remote_vars = (struct xpc_vars *) xpc_remote_copy_buffer;
+ remote_vars = (struct xpc_vars *)xpc_remote_copy_buffer;
ret = xpc_get_remote_vars(remote_vars_pa, remote_vars);
if (ret != xpcSuccess) {
dev_warn(xpc_part, "unable to get XPC variables from nasid %d, "
- "which sent interrupt, reason=%d\n", nasid, ret);
+ "which sent interrupt, reason=%d\n", nasid, ret);
XPC_DEACTIVATE_PARTITION(part, ret);
return;
}
-
part->act_IRQ_rcvd++;
dev_dbg(xpc_part, "partid for nasid %d is %d; IRQs = %d; HB = "
- "%ld:0x%lx\n", (int) nasid, (int) partid, part->act_IRQ_rcvd,
+ "%ld:0x%lx\n", (int)nasid, (int)partid, part->act_IRQ_rcvd,
remote_vars->heartbeat, remote_vars->heartbeating_to_mask);
if (xpc_partition_disengaged(part) &&
- part->act_state == XPC_P_INACTIVE) {
+ part->act_state == XPC_P_INACTIVE) {
xpc_update_partition_info(part, remote_rp_version,
- &remote_rp_stamp, remote_rp_pa,
- remote_vars_pa, remote_vars);
+ &remote_rp_stamp, remote_rp_pa,
+ remote_vars_pa, remote_vars);
if (XPC_SUPPORTS_DISENGAGE_REQUEST(part->remote_vars_version)) {
if (xpc_partition_disengage_requested(1UL << partid)) {
if (!XPC_SUPPORTS_RP_STAMP(part->remote_rp_version)) {
DBUG_ON(XPC_SUPPORTS_DISENGAGE_REQUEST(part->
- remote_vars_version));
+ remote_vars_version));
if (!XPC_SUPPORTS_RP_STAMP(remote_rp_version)) {
DBUG_ON(XPC_SUPPORTS_DISENGAGE_REQUEST(remote_vars->
- version));
+ version));
/* see if the other side rebooted */
if (part->remote_amos_page_pa ==
- remote_vars->amos_page_pa &&
- xpc_hb_allowed(sn_partition_id,
- remote_vars)) {
+ remote_vars->amos_page_pa &&
+ xpc_hb_allowed(sn_partition_id, remote_vars)) {
/* doesn't look that way, so ignore the IPI */
return;
}
*/
xpc_update_partition_info(part, remote_rp_version,
- &remote_rp_stamp, remote_rp_pa,
- remote_vars_pa, remote_vars);
+ &remote_rp_stamp, remote_rp_pa,
+ remote_vars_pa, remote_vars);
part->reactivate_nasid = nasid;
XPC_DEACTIVATE_PARTITION(part, xpcReactivating);
return;
xpc_clear_partition_disengage_request(1UL << partid);
xpc_update_partition_info(part, remote_rp_version,
- &remote_rp_stamp, remote_rp_pa,
- remote_vars_pa, remote_vars);
+ &remote_rp_stamp, remote_rp_pa,
+ remote_vars_pa, remote_vars);
reactivate = 1;
} else {
DBUG_ON(!XPC_SUPPORTS_DISENGAGE_REQUEST(remote_vars->version));
stamp_diff = xpc_compare_stamps(&part->remote_rp_stamp,
- &remote_rp_stamp);
+ &remote_rp_stamp);
if (stamp_diff != 0) {
DBUG_ON(stamp_diff >= 0);
DBUG_ON(xpc_partition_engaged(1UL << partid));
DBUG_ON(xpc_partition_disengage_requested(1UL <<
- partid));
+ partid));
xpc_update_partition_info(part, remote_rp_version,
- &remote_rp_stamp, remote_rp_pa,
- remote_vars_pa, remote_vars);
+ &remote_rp_stamp,
+ remote_rp_pa, remote_vars_pa,
+ remote_vars);
reactivate = 1;
}
}
if (part->disengage_request_timeout > 0 &&
- !xpc_partition_disengaged(part)) {
+ !xpc_partition_disengaged(part)) {
/* still waiting on other side to disengage from us */
return;
}
XPC_DEACTIVATE_PARTITION(part, xpcReactivating);
} else if (XPC_SUPPORTS_DISENGAGE_REQUEST(part->remote_vars_version) &&
- xpc_partition_disengage_requested(1UL << partid)) {
+ xpc_partition_disengage_requested(1UL << partid)) {
XPC_DEACTIVATE_PARTITION(part, xpcOtherGoingDown);
}
}
-
/*
* Loop through the activation AMO variables and process any bits
* which are set. Each bit indicates a nasid sending a partition
{
int word, bit;
u64 nasid_mask;
- u64 nasid; /* remote nasid */
+ u64 nasid; /* remote nasid */
int n_IRQs_detected = 0;
AMO_t *act_amos;
-
act_amos = xpc_vars->amos_page + XPC_ACTIVATE_IRQ_AMOS;
-
/* scan through act AMO variable looking for non-zero entries */
for (word = 0; word < xp_nasid_mask_words; word++) {
- if (xpc_exiting) {
+ if (xpc_exiting)
break;
- }
nasid_mask = xpc_IPI_receive(&act_amos[word]);
if (nasid_mask == 0) {
dev_dbg(xpc_part, "AMO[%d] gave back 0x%lx\n", word,
nasid_mask);
-
/*
* If this nasid has been added to the machine since
* our partition was reset, this will retain the
*/
xpc_mach_nasids[word] |= nasid_mask;
-
/* locate the nasid(s) which sent interrupts */
for (bit = 0; bit < (8 * sizeof(u64)); bit++) {
return n_IRQs_detected;
}
-
/*
* See if the other side has responded to a partition disengage request
* from us.
partid_t partid = XPC_PARTID(part);
int disengaged;
-
disengaged = (xpc_partition_engaged(1UL << partid) == 0);
if (part->disengage_request_timeout) {
if (!disengaged) {
- if (time_before(jiffies, part->disengage_request_timeout)) {
+ if (time_before(jiffies,
+ part->disengage_request_timeout)) {
/* timelimit hasn't been reached yet */
return 0;
}
*/
dev_info(xpc_part, "disengage from remote partition %d "
- "timed out\n", partid);
+ "timed out\n", partid);
xpc_disengage_request_timedout = 1;
xpc_clear_partition_engaged(1UL << partid);
disengaged = 1;
/* cancel the timer function, provided it's not us */
if (!in_interrupt()) {
del_singleshot_timer_sync(&part->
- disengage_request_timer);
+ disengage_request_timer);
}
DBUG_ON(part->act_state != XPC_P_DEACTIVATING &&
- part->act_state != XPC_P_INACTIVE);
- if (part->act_state != XPC_P_INACTIVE) {
+ part->act_state != XPC_P_INACTIVE);
+ if (part->act_state != XPC_P_INACTIVE)
xpc_wakeup_channel_mgr(part);
- }
- if (XPC_SUPPORTS_DISENGAGE_REQUEST(part->remote_vars_version)) {
+ if (XPC_SUPPORTS_DISENGAGE_REQUEST(part->remote_vars_version))
xpc_cancel_partition_disengage_request(part);
- }
}
return disengaged;
}
-
/*
* Mark specified partition as active.
*/
unsigned long irq_flags;
enum xpc_retval ret;
-
dev_dbg(xpc_part, "setting partition %d to ACTIVE\n", XPC_PARTID(part));
spin_lock_irqsave(&part->act_lock, irq_flags);
return ret;
}
-
/*
* Notify XPC that the partition is down.
*/
void
xpc_deactivate_partition(const int line, struct xpc_partition *part,
- enum xpc_retval reason)
+ enum xpc_retval reason)
{
unsigned long irq_flags;
-
spin_lock_irqsave(&part->act_lock, irq_flags);
if (part->act_state == XPC_P_INACTIVE) {
}
if (part->act_state == XPC_P_DEACTIVATING) {
if ((part->reason == xpcUnloading && reason != xpcUnloading) ||
- reason == xpcReactivating) {
+ reason == xpcReactivating) {
XPC_SET_REASON(part, reason, line);
}
spin_unlock_irqrestore(&part->act_lock, irq_flags);
/* set a timelimit on the disengage request */
part->disengage_request_timeout = jiffies +
- (xpc_disengage_request_timelimit * HZ);
+ (xpc_disengage_request_timelimit * HZ);
part->disengage_request_timer.expires =
- part->disengage_request_timeout;
+ part->disengage_request_timeout;
add_timer(&part->disengage_request_timer);
}
xpc_partition_going_down(part, reason);
}
-
/*
* Mark specified partition as inactive.
*/
{
unsigned long irq_flags;
-
dev_dbg(xpc_part, "setting partition %d to INACTIVE\n",
XPC_PARTID(part));
part->remote_rp_pa = 0;
}
-
/*
* SAL has provided a partition and machine mask. The partition mask
* contains a bit for each even nasid in our partition. The machine
u64 *discovered_nasids;
enum xpc_retval ret;
-
remote_rp = xpc_kmalloc_cacheline_aligned(XPC_RP_HEADER_SIZE +
- xp_nasid_mask_bytes,
- GFP_KERNEL, &remote_rp_base);
- if (remote_rp == NULL) {
+ xp_nasid_mask_bytes,
+ GFP_KERNEL, &remote_rp_base);
+ if (remote_rp == NULL)
return;
- }
- remote_vars = (struct xpc_vars *) remote_rp;
+ remote_vars = (struct xpc_vars *)remote_rp;
discovered_nasids = kzalloc(sizeof(u64) * xp_nasid_mask_words,
- GFP_KERNEL);
+ GFP_KERNEL);
if (discovered_nasids == NULL) {
kfree(remote_rp_base);
return;
}
- rp = (struct xpc_rsvd_page *) xpc_rsvd_page;
+ rp = (struct xpc_rsvd_page *)xpc_rsvd_page;
/*
* The term 'region' in this context refers to the minimum number of
for (region = 0; region < max_regions; region++) {
- if ((volatile int) xpc_exiting) {
+ if (xpc_exiting)
break;
- }
dev_dbg(xpc_part, "searching region %d\n", region);
for (nasid = (region * region_size * 2);
- nasid < ((region + 1) * region_size * 2);
- nasid += 2) {
+ nasid < ((region + 1) * region_size * 2); nasid += 2) {
- if ((volatile int) xpc_exiting) {
+ if (xpc_exiting)
break;
- }
dev_dbg(xpc_part, "checking nasid %d\n", nasid);
-
if (XPC_NASID_IN_ARRAY(nasid, xpc_part_nasids)) {
dev_dbg(xpc_part, "PROM indicates Nasid %d is "
"part of the local partition; skipping "
continue;
}
-
/* pull over the reserved page structure */
ret = xpc_get_remote_rp(nasid, discovered_nasids,
- remote_rp, &remote_rp_pa);
+ remote_rp, &remote_rp_pa);
if (ret != xpcSuccess) {
dev_dbg(xpc_part, "unable to get reserved page "
"from nasid %d, reason=%d\n", nasid,
ret);
- if (ret == xpcLocalPartid) {
+ if (ret == xpcLocalPartid)
break;
- }
+
continue;
}
partid = remote_rp->partid;
part = &xpc_partitions[partid];
-
/* pull over the cross partition variables */
ret = xpc_get_remote_vars(remote_vars_pa, remote_vars);
* get the same page for remote_act_amos_pa after
* module reloads and system reboots.
*/
- if (sn_register_xp_addr_region(
- remote_vars->amos_page_pa,
- PAGE_SIZE, 1) < 0) {
- dev_dbg(xpc_part, "partition %d failed to "
+ if (sn_register_xp_addr_region
+ (remote_vars->amos_page_pa, PAGE_SIZE, 1) < 0) {
+ dev_dbg(xpc_part,
+ "partition %d failed to "
"register xp_addr region 0x%016lx\n",
partid, remote_vars->amos_page_pa);
XPC_SET_REASON(part, xpcPhysAddrRegFailed,
- __LINE__);
+ __LINE__);
break;
}
remote_vars->act_phys_cpuid);
if (XPC_SUPPORTS_DISENGAGE_REQUEST(remote_vars->
- version)) {
+ version)) {
part->remote_amos_page_pa =
- remote_vars->amos_page_pa;
+ remote_vars->amos_page_pa;
xpc_mark_partition_disengaged(part);
xpc_cancel_partition_disengage_request(part);
}
kfree(remote_rp_base);
}
-
/*
* Given a partid, get the nasids owned by that partition from the
* remote partition's reserved page.
u64 part_nasid_pa;
int bte_res;
-
part = &xpc_partitions[partid];
- if (part->remote_rp_pa == 0) {
+ if (part->remote_rp_pa == 0)
return xpcPartitionDown;
- }
memset(nasid_mask, 0, XP_NASID_MASK_BYTES);
- part_nasid_pa = (u64) XPC_RP_PART_NASIDS(part->remote_rp_pa);
+ part_nasid_pa = (u64)XPC_RP_PART_NASIDS(part->remote_rp_pa);
- bte_res = xp_bte_copy(part_nasid_pa, (u64) nasid_mask,
- xp_nasid_mask_bytes, (BTE_NOTIFY | BTE_WACQUIRE), NULL);
+ bte_res = xp_bte_copy(part_nasid_pa, (u64)nasid_mask,
+ xp_nasid_mask_bytes, (BTE_NOTIFY | BTE_WACQUIRE),
+ NULL);
return xpc_map_bte_errors(bte_res);
}
-
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 1999-2008 Silicon Graphics, Inc. All rights reserved.
*/
-
/*
* Cross Partition Network Interface (XPNET) support
*
*
*/
-
#include <linux/module.h>
+#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <asm/sn/bte.h>
#include <asm/sn/io.h>
#include <asm/sn/sn_sal.h>
-#include <asm/types.h>
#include <asm/atomic.h>
-#include <asm/sn/xp.h>
-
+#include "xp.h"
/*
* The message payload transferred by XPC.
#define XPNET_MSG_ALIGNED_SIZE (L1_CACHE_ALIGN(XPNET_MSG_SIZE))
#define XPNET_MSG_NENTRIES (PAGE_SIZE / XPNET_MSG_ALIGNED_SIZE)
-
#define XPNET_MAX_KTHREADS (XPNET_MSG_NENTRIES + 1)
#define XPNET_MAX_IDLE_KTHREADS (XPNET_MSG_NENTRIES + 1)
#define XPNET_VERSION_MAJOR(_v) ((_v) >> 4)
#define XPNET_VERSION_MINOR(_v) ((_v) & 0xf)
-#define XPNET_VERSION _XPNET_VERSION(1,0) /* version 1.0 */
-#define XPNET_VERSION_EMBED _XPNET_VERSION(1,1) /* version 1.1 */
-#define XPNET_MAGIC 0x88786984 /* "XNET" */
+#define XPNET_VERSION _XPNET_VERSION(1, 0) /* version 1.0 */
+#define XPNET_VERSION_EMBED _XPNET_VERSION(1, 1) /* version 1.1 */
+#define XPNET_MAGIC 0x88786984 /* "XNET" */
#define XPNET_VALID_MSG(_m) \
((XPNET_VERSION_MAJOR(_m->version) == XPNET_VERSION_MAJOR(XPNET_VERSION)) \
#define XPNET_DEVICE_NAME "xp0"
-
/*
* When messages are queued with xpc_send_notify, a kmalloc'd buffer
* of the following type is passed as a notification cookie. When the
/* 32KB has been determined to be the ideal */
#define XPNET_DEF_MTU (0x8000UL)
-
/*
* The partition id is encapsulated in the MAC address. The following
* define locates the octet the partid is in.
#define XPNET_PARTID_OCTET 1
#define XPNET_LICENSE_OCTET 2
-
/*
* Define the XPNET debug device structure that is to be used with dev_dbg(),
* dev_err(), dev_warn(), and dev_info().
};
struct device xpnet_dbg_subname = {
- .bus_id = {0}, /* set to "" */
+ .bus_id = {0}, /* set to "" */
.driver = &xpnet_dbg_name
};
struct sk_buff *skb;
bte_result_t bret;
struct xpnet_dev_private *priv =
- (struct xpnet_dev_private *) xpnet_device->priv;
-
+ (struct xpnet_dev_private *)xpnet_device->priv;
if (!XPNET_VALID_MSG(msg)) {
/*
* Packet with a different XPC version. Ignore.
*/
- xpc_received(partid, channel, (void *) msg);
+ xpc_received(partid, channel, (void *)msg);
priv->stats.rx_errors++;
dev_dbg(xpnet, "received 0x%lx, %d, %d, %d\n", msg->buf_pa, msg->size,
msg->leadin_ignore, msg->tailout_ignore);
-
/* reserve an extra cache line */
skb = dev_alloc_skb(msg->size + L1_CACHE_BYTES);
if (!skb) {
dev_err(xpnet, "failed on dev_alloc_skb(%d)\n",
msg->size + L1_CACHE_BYTES);
- xpc_received(partid, channel, (void *) msg);
+ xpc_received(partid, channel, (void *)msg);
priv->stats.rx_errors++;
* Move the data over from the other side.
*/
if ((XPNET_VERSION_MINOR(msg->version) == 1) &&
- (msg->embedded_bytes != 0)) {
+ (msg->embedded_bytes != 0)) {
dev_dbg(xpnet, "copying embedded message. memcpy(0x%p, 0x%p, "
"%lu)\n", skb->data, &msg->data,
- (size_t) msg->embedded_bytes);
+ (size_t)msg->embedded_bytes);
- skb_copy_to_linear_data(skb, &msg->data, (size_t)msg->embedded_bytes);
+ skb_copy_to_linear_data(skb, &msg->data,
+ (size_t)msg->embedded_bytes);
} else {
dev_dbg(xpnet, "transferring buffer to the skb->data area;\n\t"
"bte_copy(0x%p, 0x%p, %hu)\n", (void *)msg->buf_pa,
msg->size, (BTE_NOTIFY | BTE_WACQUIRE), NULL);
if (bret != BTE_SUCCESS) {
- // >>> Need better way of cleaning skb. Currently skb
- // >>> appears in_use and we can't just call
- // >>> dev_kfree_skb.
+ /*
+ * >>> Need better way of cleaning skb. Currently skb
+ * >>> appears in_use and we can't just call
+ * >>> dev_kfree_skb.
+ */
dev_err(xpnet, "bte_copy(0x%p, 0x%p, 0x%hx) returned "
"error=0x%x\n", (void *)msg->buf_pa,
(void *)__pa((u64)skb->data &
- ~(L1_CACHE_BYTES - 1)),
+ ~(L1_CACHE_BYTES - 1)),
msg->size, bret);
- xpc_received(partid, channel, (void *) msg);
+ xpc_received(partid, channel, (void *)msg);
priv->stats.rx_errors++;
}
dev_dbg(xpnet, "<skb->head=0x%p skb->data=0x%p skb->tail=0x%p "
- "skb->end=0x%p skb->len=%d\n", (void *) skb->head,
+ "skb->end=0x%p skb->len=%d\n", (void *)skb->head,
(void *)skb->data, skb_tail_pointer(skb), skb_end_pointer(skb),
skb->len);
(void *)skb->head, (void *)skb->data, skb_tail_pointer(skb),
skb_end_pointer(skb), skb->len);
-
xpnet_device->last_rx = jiffies;
priv->stats.rx_packets++;
priv->stats.rx_bytes += skb->len + ETH_HLEN;
netif_rx_ni(skb);
- xpc_received(partid, channel, (void *) msg);
+ xpc_received(partid, channel, (void *)msg);
}
-
/*
* This is the handler which XPC calls during any sort of change in
* state or message reception on a connection.
{
long bp;
-
DBUG_ON(partid <= 0 || partid >= XP_MAX_PARTITIONS);
DBUG_ON(channel != XPC_NET_CHANNEL);
- switch(reason) {
+ switch (reason) {
case xpcMsgReceived: /* message received */
DBUG_ON(data == NULL);
- xpnet_receive(partid, channel, (struct xpnet_message *) data);
+ xpnet_receive(partid, channel, (struct xpnet_message *)data);
break;
case xpcConnected: /* connection completed to a partition */
spin_lock_bh(&xpnet_broadcast_lock);
- xpnet_broadcast_partitions |= 1UL << (partid -1 );
+ xpnet_broadcast_partitions |= 1UL << (partid - 1);
bp = xpnet_broadcast_partitions;
spin_unlock_bh(&xpnet_broadcast_lock);
default:
spin_lock_bh(&xpnet_broadcast_lock);
- xpnet_broadcast_partitions &= ~(1UL << (partid -1 ));
+ xpnet_broadcast_partitions &= ~(1UL << (partid - 1));
bp = xpnet_broadcast_partitions;
spin_unlock_bh(&xpnet_broadcast_lock);
- if (bp == 0) {
+ if (bp == 0)
netif_carrier_off(xpnet_device);
- }
dev_dbg(xpnet, "%s disconnected from partition %d; "
"xpnet_broadcast_partitions=0x%lx\n",
}
}
-
static int
xpnet_dev_open(struct net_device *dev)
{
enum xpc_retval ret;
-
dev_dbg(xpnet, "calling xpc_connect(%d, 0x%p, NULL, %ld, %ld, %ld, "
"%ld)\n", XPC_NET_CHANNEL, xpnet_connection_activity,
XPNET_MSG_SIZE, XPNET_MSG_NENTRIES, XPNET_MAX_KTHREADS,
return 0;
}
-
static int
xpnet_dev_stop(struct net_device *dev)
{
return 0;
}
-
static int
xpnet_dev_change_mtu(struct net_device *dev, int new_mtu)
{
return 0;
}
-
/*
* Required for the net_device structure.
*/
return 0;
}
-
/*
* Return statistics to the caller.
*/
{
struct xpnet_dev_private *priv;
-
- priv = (struct xpnet_dev_private *) dev->priv;
+ priv = (struct xpnet_dev_private *)dev->priv;
return &priv->stats;
}
-
/*
* Notification that the other end has received the message and
* DMA'd the skb information. At this point, they are done with
*/
static void
xpnet_send_completed(enum xpc_retval reason, partid_t partid, int channel,
- void *__qm)
+ void *__qm)
{
- struct xpnet_pending_msg *queued_msg =
- (struct xpnet_pending_msg *) __qm;
-
+ struct xpnet_pending_msg *queued_msg = (struct xpnet_pending_msg *)__qm;
DBUG_ON(queued_msg == NULL);
if (atomic_dec_return(&queued_msg->use_count) == 0) {
dev_dbg(xpnet, "all acks for skb->head=-x%p\n",
- (void *) queued_msg->skb->head);
+ (void *)queued_msg->skb->head);
dev_kfree_skb_any(queued_msg->skb);
kfree(queued_msg);
}
}
-
/*
* Network layer has formatted a packet (skb) and is ready to place it
* "on the wire". Prepare and send an xpnet_message to all partitions
struct xpnet_dev_private *priv;
u16 embedded_bytes;
-
- priv = (struct xpnet_dev_private *) dev->priv;
-
+ priv = (struct xpnet_dev_private *)dev->priv;
dev_dbg(xpnet, ">skb->head=0x%p skb->data=0x%p skb->tail=0x%p "
- "skb->end=0x%p skb->len=%d\n", (void *) skb->head,
+ "skb->end=0x%p skb->len=%d\n", (void *)skb->head,
(void *)skb->data, skb_tail_pointer(skb), skb_end_pointer(skb),
skb->len);
-
/*
* The xpnet_pending_msg tracks how many outstanding
* xpc_send_notifies are relying on this skb. When none
queued_msg = kmalloc(sizeof(struct xpnet_pending_msg), GFP_ATOMIC);
if (queued_msg == NULL) {
dev_warn(xpnet, "failed to kmalloc %ld bytes; dropping "
- "packet\n", sizeof(struct xpnet_pending_msg));
+ "packet\n", sizeof(struct xpnet_pending_msg));
priv->stats.tx_errors++;
return -ENOMEM;
}
-
/* get the beginning of the first cacheline and end of last */
- start_addr = ((u64) skb->data & ~(L1_CACHE_BYTES - 1));
+ start_addr = ((u64)skb->data & ~(L1_CACHE_BYTES - 1));
end_addr = L1_CACHE_ALIGN((u64)skb_tail_pointer(skb));
/* calculate how many bytes to embed in the XPC message */
embedded_bytes = skb->len;
}
-
/*
* Since the send occurs asynchronously, we set the count to one
* and begin sending. Any sends that happen to complete before
atomic_set(&queued_msg->use_count, 1);
queued_msg->skb = skb;
-
second_mac_octet = skb->data[XPNET_PARTID_OCTET];
if (second_mac_octet == 0xff) {
/* we are being asked to broadcast to all partitions */
dp = xpnet_broadcast_partitions;
} else if (second_mac_octet != 0) {
dp = xpnet_broadcast_partitions &
- (1UL << (second_mac_octet - 1));
+ (1UL << (second_mac_octet - 1));
} else {
/* 0 is an invalid partid. Ignore */
dp = 0;
for (dest_partid = 1; dp && dest_partid < XP_MAX_PARTITIONS;
dest_partid++) {
-
if (!(dp & (1UL << (dest_partid - 1)))) {
/* not destined for this partition */
continue;
/* remove this partition from the destinations mask */
dp &= ~(1UL << (dest_partid - 1));
-
/* found a partition to send to */
ret = xpc_allocate(dest_partid, XPC_NET_CHANNEL,
XPC_NOWAIT, (void **)&msg);
- if (unlikely(ret != xpcSuccess)) {
+ if (unlikely(ret != xpcSuccess))
continue;
- }
msg->embedded_bytes = embedded_bytes;
if (unlikely(embedded_bytes != 0)) {
msg->version = XPNET_VERSION_EMBED;
dev_dbg(xpnet, "calling memcpy(0x%p, 0x%p, 0x%lx)\n",
- &msg->data, skb->data, (size_t) embedded_bytes);
+ &msg->data, skb->data, (size_t)embedded_bytes);
skb_copy_from_linear_data(skb, &msg->data,
(size_t)embedded_bytes);
} else {
}
msg->magic = XPNET_MAGIC;
msg->size = end_addr - start_addr;
- msg->leadin_ignore = (u64) skb->data - start_addr;
+ msg->leadin_ignore = (u64)skb->data - start_addr;
msg->tailout_ignore = end_addr - (u64)skb_tail_pointer(skb);
msg->buf_pa = __pa(start_addr);
dest_partid, XPC_NET_CHANNEL, msg->buf_pa, msg->size,
msg->leadin_ignore, msg->tailout_ignore);
-
atomic_inc(&queued_msg->use_count);
ret = xpc_send_notify(dest_partid, XPC_NET_CHANNEL, msg,
atomic_dec(&queued_msg->use_count);
continue;
}
-
}
if (atomic_dec_return(&queued_msg->use_count) == 0) {
dev_dbg(xpnet, "no partitions to receive packet destined for "
"%d\n", dest_partid);
-
dev_kfree_skb(skb);
kfree(queued_msg);
}
return 0;
}
-
/*
* Deal with transmit timeouts coming from the network layer.
*/
static void
-xpnet_dev_tx_timeout (struct net_device *dev)
+xpnet_dev_tx_timeout(struct net_device *dev)
{
struct xpnet_dev_private *priv;
-
- priv = (struct xpnet_dev_private *) dev->priv;
+ priv = (struct xpnet_dev_private *)dev->priv;
priv->stats.tx_errors++;
return;
}
-
static int __init
xpnet_init(void)
{
u32 license_num;
int result = -ENOMEM;
-
- if (!ia64_platform_is("sn2")) {
+ if (!ia64_platform_is("sn2"))
return -ENODEV;
- }
dev_info(xpnet, "registering network device %s\n", XPNET_DEVICE_NAME);
*/
xpnet_device = alloc_netdev(sizeof(struct xpnet_dev_private),
XPNET_DEVICE_NAME, ether_setup);
- if (xpnet_device == NULL) {
+ if (xpnet_device == NULL)
return -ENOMEM;
- }
netif_carrier_off(xpnet_device);
license_num = sn_partition_serial_number_val();
for (i = 3; i >= 0; i--) {
xpnet_device->dev_addr[XPNET_LICENSE_OCTET + i] =
- license_num & 0xff;
+ license_num & 0xff;
license_num = license_num >> 8;
}
xpnet_device->features = NETIF_F_NO_CSUM;
result = register_netdev(xpnet_device);
- if (result != 0) {
+ if (result != 0)
free_netdev(xpnet_device);
- }
return result;
}
-module_init(xpnet_init);
+module_init(xpnet_init);
static void __exit
xpnet_exit(void)
{
dev_info(xpnet, "unregistering network device %s\n",
- xpnet_device[0].name);
+ xpnet_device[0].name);
unregister_netdev(xpnet_device);
free_netdev(xpnet_device);
}
-module_exit(xpnet_exit);
+module_exit(xpnet_exit);
MODULE_AUTHOR("Silicon Graphics, Inc.");
MODULE_DESCRIPTION("Cross Partition Network adapter (XPNET)");
MODULE_LICENSE("GPL");
-
#include "sd_ops.h"
#include "sdio_ops.h"
-extern int mmc_attach_mmc(struct mmc_host *host, u32 ocr);
-extern int mmc_attach_sd(struct mmc_host *host, u32 ocr);
-extern int mmc_attach_sdio(struct mmc_host *host, u32 ocr);
-
static struct workqueue_struct *workqueue;
/*
/*
* Cleanup when the last reference to the bus operator is dropped.
*/
-void __mmc_release_bus(struct mmc_host *host)
+static void __mmc_release_bus(struct mmc_host *host)
{
BUG_ON(!host);
BUG_ON(host->bus_refs);
void mmc_start_host(struct mmc_host *host);
void mmc_stop_host(struct mmc_host *host);
+int mmc_attach_mmc(struct mmc_host *host, u32 ocr);
+int mmc_attach_sd(struct mmc_host *host, u32 ocr);
+int mmc_attach_sdio(struct mmc_host *host, u32 ocr);
+
extern int use_spi_crc;
#endif
* linux/drivers/mmc/core/host.c
*
* Copyright (C) 2003 Russell King, All Rights Reserved.
- * Copyright (C) 2007 Pierre Ossman
+ * Copyright (C) 2007-2008 Pierre Ossman
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
*/
struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
{
+ int err;
struct mmc_host *host;
+ if (!idr_pre_get(&mmc_host_idr, GFP_KERNEL))
+ return NULL;
+
host = kzalloc(sizeof(struct mmc_host) + extra, GFP_KERNEL);
if (!host)
return NULL;
+ spin_lock(&mmc_host_lock);
+ err = idr_get_new(&mmc_host_idr, host, &host->index);
+ spin_unlock(&mmc_host_lock);
+ if (err)
+ goto free;
+
+ snprintf(host->class_dev.bus_id, BUS_ID_SIZE,
+ "mmc%d", host->index);
+
host->parent = dev;
host->class_dev.parent = dev;
host->class_dev.class = &mmc_host_class;
host->max_blk_count = PAGE_CACHE_SIZE / 512;
return host;
+
+free:
+ kfree(host);
+ return NULL;
}
EXPORT_SYMBOL(mmc_alloc_host);
WARN_ON((host->caps & MMC_CAP_SDIO_IRQ) &&
!host->ops->enable_sdio_irq);
- if (!idr_pre_get(&mmc_host_idr, GFP_KERNEL))
- return -ENOMEM;
-
- spin_lock(&mmc_host_lock);
- err = idr_get_new(&mmc_host_idr, host, &host->index);
- spin_unlock(&mmc_host_lock);
- if (err)
- return err;
-
- snprintf(host->class_dev.bus_id, BUS_ID_SIZE,
- "mmc%d", host->index);
-
led_trigger_register_simple(host->class_dev.bus_id, &host->led);
err = device_add(&host->class_dev);
device_del(&host->class_dev);
led_trigger_unregister_simple(host->led);
-
- spin_lock(&mmc_host_lock);
- idr_remove(&mmc_host_idr, host->index);
- spin_unlock(&mmc_host_lock);
}
EXPORT_SYMBOL(mmc_remove_host);
*/
void mmc_free_host(struct mmc_host *host)
{
+ spin_lock(&mmc_host_lock);
+ idr_remove(&mmc_host_idr, host->index);
+ spin_unlock(&mmc_host_lock);
+
put_device(&host->class_dev);
}
}
}
- set_task_state(current, TASK_INTERRUPTIBLE);
+ set_current_state(TASK_INTERRUPTIBLE);
if (host->caps & MMC_CAP_SDIO_IRQ)
host->ops->enable_sdio_irq(host, 1);
if (!kthread_should_stop())
schedule_timeout(period);
- set_task_state(current, TASK_RUNNING);
+ set_current_state(TASK_RUNNING);
} while (!kthread_should_stop());
if (host->caps & MMC_CAP_SDIO_IRQ)
#include <linux/mmc/sdio.h>
#include "core.h"
+#include "sdio_ops.h"
int mmc_send_io_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
{
#include <asm/mach-types.h>
#include <asm/arch/board.h>
+#include <asm/arch/mmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/dma.h>
#include <asm/arch/mux.h>
/* Specifies how often in millisecs to poll for card status changes
* when the cover switch is open */
-#define OMAP_MMC_SWITCH_POLL_DELAY 500
-
-static int mmc_omap_enable_poll = 1;
+#define OMAP_MMC_COVER_POLL_DELAY 500
+
+struct mmc_omap_host;
+
+struct mmc_omap_slot {
+ int id;
+ unsigned int vdd;
+ u16 saved_con;
+ u16 bus_mode;
+ unsigned int fclk_freq;
+ unsigned powered:1;
+
+ struct tasklet_struct cover_tasklet;
+ struct timer_list cover_timer;
+ unsigned cover_open;
+
+ struct mmc_request *mrq;
+ struct mmc_omap_host *host;
+ struct mmc_host *mmc;
+ struct omap_mmc_slot_data *pdata;
+};
struct mmc_omap_host {
int initialized;
unsigned char bus_mode;
unsigned char hw_bus_mode;
+ struct work_struct cmd_abort_work;
+ unsigned abort:1;
+ struct timer_list cmd_abort_timer;
+
+ struct work_struct slot_release_work;
+ struct mmc_omap_slot *next_slot;
+ struct work_struct send_stop_work;
+ struct mmc_data *stop_data;
+
unsigned int sg_len;
int sg_idx;
u16 * buffer;
unsigned dma_len;
short power_pin;
- short wp_pin;
- int switch_pin;
- struct work_struct switch_work;
- struct timer_list switch_timer;
- int switch_last_state;
+ struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
+ struct mmc_omap_slot *current_slot;
+ spinlock_t slot_lock;
+ wait_queue_head_t slot_wq;
+ int nr_slots;
+
+ struct timer_list clk_timer;
+ spinlock_t clk_lock; /* for changing enabled state */
+ unsigned int fclk_enabled:1;
+
+ struct omap_mmc_platform_data *pdata;
};
-static inline int
-mmc_omap_cover_is_open(struct mmc_omap_host *host)
+void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
{
- if (host->switch_pin < 0)
- return 0;
- return omap_get_gpio_datain(host->switch_pin);
+ unsigned long tick_ns;
+
+ if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
+ tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
+ ndelay(8 * tick_ns);
+ }
}
-static ssize_t
-mmc_omap_show_cover_switch(struct device *dev,
- struct device_attribute *attr, char *buf)
+void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
{
- struct mmc_omap_host *host = dev_get_drvdata(dev);
+ unsigned long flags;
- return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
- "closed");
+ spin_lock_irqsave(&host->clk_lock, flags);
+ if (host->fclk_enabled != enable) {
+ host->fclk_enabled = enable;
+ if (enable)
+ clk_enable(host->fclk);
+ else
+ clk_disable(host->fclk);
+ }
+ spin_unlock_irqrestore(&host->clk_lock, flags);
}
-static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
+static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
+{
+ struct mmc_omap_host *host = slot->host;
+ unsigned long flags;
-static ssize_t
-mmc_omap_show_enable_poll(struct device *dev,
- struct device_attribute *attr, char *buf)
+ if (claimed)
+ goto no_claim;
+ spin_lock_irqsave(&host->slot_lock, flags);
+ while (host->mmc != NULL) {
+ spin_unlock_irqrestore(&host->slot_lock, flags);
+ wait_event(host->slot_wq, host->mmc == NULL);
+ spin_lock_irqsave(&host->slot_lock, flags);
+ }
+ host->mmc = slot->mmc;
+ spin_unlock_irqrestore(&host->slot_lock, flags);
+no_claim:
+ del_timer(&host->clk_timer);
+ if (host->current_slot != slot || !claimed)
+ mmc_omap_fclk_offdelay(host->current_slot);
+
+ if (host->current_slot != slot) {
+ OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
+ if (host->pdata->switch_slot != NULL)
+ host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
+ host->current_slot = slot;
+ }
+
+ if (claimed) {
+ mmc_omap_fclk_enable(host, 1);
+
+ /* Doing the dummy read here seems to work around some bug
+ * at least in OMAP24xx silicon where the command would not
+ * start after writing the CMD register. Sigh. */
+ OMAP_MMC_READ(host, CON);
+
+ OMAP_MMC_WRITE(host, CON, slot->saved_con);
+ } else
+ mmc_omap_fclk_enable(host, 0);
+}
+
+static void mmc_omap_start_request(struct mmc_omap_host *host,
+ struct mmc_request *req);
+
+static void mmc_omap_slot_release_work(struct work_struct *work)
{
- return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
+ struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
+ slot_release_work);
+ struct mmc_omap_slot *next_slot = host->next_slot;
+ struct mmc_request *rq;
+
+ host->next_slot = NULL;
+ mmc_omap_select_slot(next_slot, 1);
+
+ rq = next_slot->mrq;
+ next_slot->mrq = NULL;
+ mmc_omap_start_request(host, rq);
}
-static ssize_t
-mmc_omap_store_enable_poll(struct device *dev,
- struct device_attribute *attr, const char *buf,
- size_t size)
+static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
{
- int enable_poll;
+ struct mmc_omap_host *host = slot->host;
+ unsigned long flags;
+ int i;
+
+ BUG_ON(slot == NULL || host->mmc == NULL);
+
+ if (clk_enabled)
+ /* Keeps clock running for at least 8 cycles on valid freq */
+ mod_timer(&host->clk_timer, jiffies + HZ/10);
+ else {
+ del_timer(&host->clk_timer);
+ mmc_omap_fclk_offdelay(slot);
+ mmc_omap_fclk_enable(host, 0);
+ }
- if (sscanf(buf, "%10d", &enable_poll) != 1)
- return -EINVAL;
+ spin_lock_irqsave(&host->slot_lock, flags);
+ /* Check for any pending requests */
+ for (i = 0; i < host->nr_slots; i++) {
+ struct mmc_omap_slot *new_slot;
- if (enable_poll != mmc_omap_enable_poll) {
- struct mmc_omap_host *host = dev_get_drvdata(dev);
+ if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
+ continue;
- mmc_omap_enable_poll = enable_poll;
- if (enable_poll && host->switch_pin >= 0)
- schedule_work(&host->switch_work);
+ BUG_ON(host->next_slot != NULL);
+ new_slot = host->slots[i];
+ /* The current slot should not have a request in queue */
+ BUG_ON(new_slot == host->current_slot);
+
+ host->next_slot = new_slot;
+ host->mmc = new_slot->mmc;
+ spin_unlock_irqrestore(&host->slot_lock, flags);
+ schedule_work(&host->slot_release_work);
+ return;
}
- return size;
+
+ host->mmc = NULL;
+ wake_up(&host->slot_wq);
+ spin_unlock_irqrestore(&host->slot_lock, flags);
+}
+
+static inline
+int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
+{
+ if (slot->pdata->get_cover_state)
+ return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
+ slot->id);
+ return 0;
+}
+
+static ssize_t
+mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
+ struct mmc_omap_slot *slot = mmc_priv(mmc);
+
+ return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
+ "closed");
}
-static DEVICE_ATTR(enable_poll, 0664,
- mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
+static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
+
+static ssize_t
+mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
+ struct mmc_omap_slot *slot = mmc_priv(mmc);
+
+ return sprintf(buf, "%s\n", slot->pdata->name);
+}
+
+static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
static void
mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
- if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
+ if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
cmdreg |= 1 << 6;
if (cmd->flags & MMC_RSP_BUSY)
if (host->data && !(host->data->flags & MMC_DATA_WRITE))
cmdreg |= 1 << 15;
- clk_enable(host->fclk);
+ mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
OMAP_MMC_WRITE(host, CTO, 200);
OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
OMAP_MMC_WRITE(host, CMD, cmdreg);
}
+static void
+mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
+ int abort)
+{
+ enum dma_data_direction dma_data_dir;
+
+ BUG_ON(host->dma_ch < 0);
+ if (data->error)
+ omap_stop_dma(host->dma_ch);
+ /* Release DMA channel lazily */
+ mod_timer(&host->dma_timer, jiffies + HZ);
+ if (data->flags & MMC_DATA_WRITE)
+ dma_data_dir = DMA_TO_DEVICE;
+ else
+ dma_data_dir = DMA_FROM_DEVICE;
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
+ dma_data_dir);
+}
+
+static void mmc_omap_send_stop_work(struct work_struct *work)
+{
+ struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
+ send_stop_work);
+ struct mmc_omap_slot *slot = host->current_slot;
+ struct mmc_data *data = host->stop_data;
+ unsigned long tick_ns;
+
+ tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
+ ndelay(8*tick_ns);
+
+ mmc_omap_start_command(host, data->stop);
+}
+
static void
mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
{
- if (host->dma_in_use) {
- enum dma_data_direction dma_data_dir;
-
- BUG_ON(host->dma_ch < 0);
- if (data->error)
- omap_stop_dma(host->dma_ch);
- /* Release DMA channel lazily */
- mod_timer(&host->dma_timer, jiffies + HZ);
- if (data->flags & MMC_DATA_WRITE)
- dma_data_dir = DMA_TO_DEVICE;
- else
- dma_data_dir = DMA_FROM_DEVICE;
- dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
- dma_data_dir);
- }
+ if (host->dma_in_use)
+ mmc_omap_release_dma(host, data, data->error);
+
host->data = NULL;
host->sg_len = 0;
- clk_disable(host->fclk);
/* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
* dozens of requests until the card finishes writing data.
*/
if (!data->stop) {
+ struct mmc_host *mmc;
+
host->mrq = NULL;
- mmc_request_done(host->mmc, data->mrq);
+ mmc = host->mmc;
+ mmc_omap_release_slot(host->current_slot, 1);
+ mmc_request_done(mmc, data->mrq);
return;
}
- mmc_omap_start_command(host, data->stop);
+ host->stop_data = data;
+ schedule_work(&host->send_stop_work);
+}
+
+static void
+mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
+{
+ struct mmc_omap_slot *slot = host->current_slot;
+ unsigned int restarts, passes, timeout;
+ u16 stat = 0;
+
+ /* Sending abort takes 80 clocks. Have some extra and round up */
+ timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
+ restarts = 0;
+ while (restarts < maxloops) {
+ OMAP_MMC_WRITE(host, STAT, 0xFFFF);
+ OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
+
+ passes = 0;
+ while (passes < timeout) {
+ stat = OMAP_MMC_READ(host, STAT);
+ if (stat & OMAP_MMC_STAT_END_OF_CMD)
+ goto out;
+ udelay(1);
+ passes++;
+ }
+
+ restarts++;
+ }
+out:
+ OMAP_MMC_WRITE(host, STAT, stat);
+}
+
+static void
+mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
+{
+ if (host->dma_in_use)
+ mmc_omap_release_dma(host, data, 1);
+
+ host->data = NULL;
+ host->sg_len = 0;
+
+ mmc_omap_send_abort(host, 10000);
}
static void
{
host->cmd = NULL;
+ del_timer(&host->cmd_abort_timer);
+
if (cmd->flags & MMC_RSP_PRESENT) {
if (cmd->flags & MMC_RSP_136) {
/* response type 2 */
}
if (host->data == NULL || cmd->error) {
+ struct mmc_host *mmc;
+
+ if (host->data != NULL)
+ mmc_omap_abort_xfer(host, host->data);
host->mrq = NULL;
- clk_disable(host->fclk);
- mmc_request_done(host->mmc, cmd->mrq);
+ mmc = host->mmc;
+ mmc_omap_release_slot(host->current_slot, 1);
+ mmc_request_done(mmc, cmd->mrq);
+ }
+}
+
+/*
+ * Abort stuck command. Can occur when card is removed while it is being
+ * read.
+ */
+static void mmc_omap_abort_command(struct work_struct *work)
+{
+ struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
+ cmd_abort_work);
+ BUG_ON(!host->cmd);
+
+ dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
+ host->cmd->opcode);
+
+ if (host->cmd->error == 0)
+ host->cmd->error = -ETIMEDOUT;
+
+ if (host->data == NULL) {
+ struct mmc_command *cmd;
+ struct mmc_host *mmc;
+
+ cmd = host->cmd;
+ host->cmd = NULL;
+ mmc_omap_send_abort(host, 10000);
+
+ host->mrq = NULL;
+ mmc = host->mmc;
+ mmc_omap_release_slot(host->current_slot, 1);
+ mmc_request_done(mmc, cmd->mrq);
+ } else
+ mmc_omap_cmd_done(host, host->cmd);
+
+ host->abort = 0;
+ enable_irq(host->irq);
+}
+
+static void
+mmc_omap_cmd_timer(unsigned long data)
+{
+ struct mmc_omap_host *host = (struct mmc_omap_host *) data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->slot_lock, flags);
+ if (host->cmd != NULL && !host->abort) {
+ OMAP_MMC_WRITE(host, IE, 0);
+ disable_irq(host->irq);
+ host->abort = 1;
+ schedule_work(&host->cmd_abort_work);
}
+ spin_unlock_irqrestore(&host->slot_lock, flags);
}
/* PIO only */
host->buffer_bytes_left = host->total_bytes_left;
}
+static void
+mmc_omap_clk_timer(unsigned long data)
+{
+ struct mmc_omap_host *host = (struct mmc_omap_host *) data;
+
+ mmc_omap_fclk_enable(host, 0);
+}
+
/* PIO only */
static void
mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
u16 status;
int end_command;
int end_transfer;
- int transfer_error;
+ int transfer_error, cmd_error;
if (host->cmd == NULL && host->data == NULL) {
status = OMAP_MMC_READ(host, STAT);
- dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
+ dev_info(mmc_dev(host->slots[0]->mmc),
+ "Spurious IRQ 0x%04x\n", status);
if (status != 0) {
OMAP_MMC_WRITE(host, STAT, status);
OMAP_MMC_WRITE(host, IE, 0);
end_command = 0;
end_transfer = 0;
transfer_error = 0;
+ cmd_error = 0;
while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
+ int cmd;
+
OMAP_MMC_WRITE(host, STAT, status);
+ if (host->cmd != NULL)
+ cmd = host->cmd->opcode;
+ else
+ cmd = -1;
#ifdef CONFIG_MMC_DEBUG
dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
- status, host->cmd != NULL ? host->cmd->opcode : -1);
+ status, cmd);
mmc_omap_report_irq(status);
printk("\n");
#endif
mmc_omap_xfer_data(host, 1);
}
- if (status & OMAP_MMC_STAT_END_OF_DATA) {
+ if (status & OMAP_MMC_STAT_END_OF_DATA)
end_transfer = 1;
- }
if (status & OMAP_MMC_STAT_DATA_TOUT) {
- dev_dbg(mmc_dev(host->mmc), "data timeout\n");
+ dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
+ cmd);
if (host->data) {
host->data->error = -ETIMEDOUT;
transfer_error = 1;
if (status & OMAP_MMC_STAT_CMD_TOUT) {
/* Timeouts are routine with some commands */
if (host->cmd) {
- if (host->cmd->opcode != MMC_ALL_SEND_CID &&
- host->cmd->opcode !=
- MMC_SEND_OP_COND &&
- host->cmd->opcode !=
- MMC_APP_CMD &&
- !mmc_omap_cover_is_open(host))
+ struct mmc_omap_slot *slot =
+ host->current_slot;
+ if (slot == NULL ||
+ !mmc_omap_cover_is_open(slot))
dev_err(mmc_dev(host->mmc),
- "command timeout, CMD %d\n",
- host->cmd->opcode);
+ "command timeout (CMD%d)\n",
+ cmd);
host->cmd->error = -ETIMEDOUT;
end_command = 1;
+ cmd_error = 1;
}
}
if (host->cmd) {
dev_err(mmc_dev(host->mmc),
"command CRC error (CMD%d, arg 0x%08x)\n",
- host->cmd->opcode, host->cmd->arg);
+ cmd, host->cmd->arg);
host->cmd->error = -EILSEQ;
end_command = 1;
+ cmd_error = 1;
} else
dev_err(mmc_dev(host->mmc),
"command CRC error without cmd?\n");
if (status & OMAP_MMC_STAT_CARD_ERR) {
dev_dbg(mmc_dev(host->mmc),
"ignoring card status error (CMD%d)\n",
- host->cmd->opcode);
+ cmd);
end_command = 1;
}
/*
* NOTE: On 1610 the END_OF_CMD may come too early when
- * starting a write
+ * starting a write
*/
if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
(!(status & OMAP_MMC_STAT_A_EMPTY))) {
}
}
- if (end_command) {
+ if (cmd_error && host->data) {
+ del_timer(&host->cmd_abort_timer);
+ host->abort = 1;
+ OMAP_MMC_WRITE(host, IE, 0);
+ disable_irq(host->irq);
+ schedule_work(&host->cmd_abort_work);
+ return IRQ_HANDLED;
+ }
+
+ if (end_command)
mmc_omap_cmd_done(host, host->cmd);
+ if (host->data != NULL) {
+ if (transfer_error)
+ mmc_omap_xfer_done(host, host->data);
+ else if (end_transfer)
+ mmc_omap_end_of_data(host, host->data);
}
- if (transfer_error)
- mmc_omap_xfer_done(host, host->data);
- else if (end_transfer)
- mmc_omap_end_of_data(host, host->data);
return IRQ_HANDLED;
}
-static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
+void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
{
- struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
+ int cover_open;
+ struct mmc_omap_host *host = dev_get_drvdata(dev);
+ struct mmc_omap_slot *slot = host->slots[num];
- schedule_work(&host->switch_work);
+ BUG_ON(num >= host->nr_slots);
- return IRQ_HANDLED;
+ /* Other subsystems can call in here before we're initialised. */
+ if (host->nr_slots == 0 || !host->slots[num])
+ return;
+
+ cover_open = mmc_omap_cover_is_open(slot);
+ if (cover_open != slot->cover_open) {
+ slot->cover_open = cover_open;
+ sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
+ }
+
+ tasklet_hi_schedule(&slot->cover_tasklet);
}
-static void mmc_omap_switch_timer(unsigned long arg)
+static void mmc_omap_cover_timer(unsigned long arg)
{
- struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
-
- schedule_work(&host->switch_work);
+ struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
+ tasklet_schedule(&slot->cover_tasklet);
}
-static void mmc_omap_switch_handler(struct work_struct *work)
+static void mmc_omap_cover_handler(unsigned long param)
{
- struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
- struct mmc_card *card;
- static int complained = 0;
- int cards = 0, cover_open;
+ struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
+ int cover_open = mmc_omap_cover_is_open(slot);
- if (host->switch_pin == -1)
+ mmc_detect_change(slot->mmc, 0);
+ if (!cover_open)
return;
- cover_open = mmc_omap_cover_is_open(host);
- if (cover_open != host->switch_last_state) {
- kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
- host->switch_last_state = cover_open;
- }
- mmc_detect_change(host->mmc, 0);
- list_for_each_entry(card, &host->mmc->cards, node) {
- if (mmc_card_present(card))
- cards++;
- }
- if (mmc_omap_cover_is_open(host)) {
- if (!complained) {
- dev_info(mmc_dev(host->mmc), "cover is open\n");
- complained = 1;
- }
- if (mmc_omap_enable_poll)
- mod_timer(&host->switch_timer, jiffies +
- msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
- } else {
- complained = 0;
- }
+
+ /*
+ * If no card is inserted, we postpone polling until
+ * the cover has been closed.
+ */
+ if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
+ return;
+
+ mod_timer(&slot->cover_timer,
+ jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
}
/* Prepare to transfer the next segment of a scatterlist */
static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
{
- int timeout;
+ unsigned int timeout, cycle_ns;
u16 reg;
- /* Convert ns to clock cycles by assuming 20MHz frequency
- * 1 cycle at 20MHz = 500 ns
- */
- timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
+ cycle_ns = 1000000000 / host->current_slot->fclk_freq;
+ timeout = req->data->timeout_ns / cycle_ns;
+ timeout += req->data->timeout_clks;
/* Check if we need to use timeout multiplier register */
reg = OMAP_MMC_READ(host, SDIO);
}
}
-static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
+static void mmc_omap_start_request(struct mmc_omap_host *host,
+ struct mmc_request *req)
{
- struct mmc_omap_host *host = mmc_priv(mmc);
-
- WARN_ON(host->mrq != NULL);
+ BUG_ON(host->mrq != NULL);
host->mrq = req;
mmc_omap_start_command(host, req->cmd);
if (host->dma_in_use)
omap_start_dma(host->dma_ch);
+ BUG_ON(irqs_disabled());
}
-static void innovator_fpga_socket_power(int on)
+static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
{
-#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
- if (on) {
- fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
- OMAP1510_FPGA_POWER);
- } else {
- fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
- OMAP1510_FPGA_POWER);
- }
-#endif
+ struct mmc_omap_slot *slot = mmc_priv(mmc);
+ struct mmc_omap_host *host = slot->host;
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->slot_lock, flags);
+ if (host->mmc != NULL) {
+ BUG_ON(slot->mrq != NULL);
+ slot->mrq = req;
+ spin_unlock_irqrestore(&host->slot_lock, flags);
+ return;
+ } else
+ host->mmc = mmc;
+ spin_unlock_irqrestore(&host->slot_lock, flags);
+ mmc_omap_select_slot(slot, 1);
+ mmc_omap_start_request(host, req);
}
-/*
- * Turn the socket power on/off. Innovator uses FPGA, most boards
- * probably use GPIO.
- */
-static void mmc_omap_power(struct mmc_omap_host *host, int on)
+static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
+ int vdd)
{
- if (on) {
- if (machine_is_omap_innovator())
- innovator_fpga_socket_power(1);
- else if (machine_is_omap_h2())
- tps65010_set_gpio_out_value(GPIO3, HIGH);
- else if (machine_is_omap_h3())
- /* GPIO 4 of TPS65010 sends SD_EN signal */
- tps65010_set_gpio_out_value(GPIO4, HIGH);
- else if (cpu_is_omap24xx()) {
- u16 reg = OMAP_MMC_READ(host, CON);
- OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
- } else
- if (host->power_pin >= 0)
- omap_set_gpio_dataout(host->power_pin, 1);
- } else {
- if (machine_is_omap_innovator())
- innovator_fpga_socket_power(0);
- else if (machine_is_omap_h2())
- tps65010_set_gpio_out_value(GPIO3, LOW);
- else if (machine_is_omap_h3())
- tps65010_set_gpio_out_value(GPIO4, LOW);
- else if (cpu_is_omap24xx()) {
- u16 reg = OMAP_MMC_READ(host, CON);
- OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
- } else
- if (host->power_pin >= 0)
- omap_set_gpio_dataout(host->power_pin, 0);
+ struct mmc_omap_host *host;
+
+ host = slot->host;
+
+ if (slot->pdata->set_power != NULL)
+ slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
+ vdd);
+
+ if (cpu_is_omap24xx()) {
+ u16 w;
+
+ if (power_on) {
+ w = OMAP_MMC_READ(host, CON);
+ OMAP_MMC_WRITE(host, CON, w | (1 << 11));
+ } else {
+ w = OMAP_MMC_READ(host, CON);
+ OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
+ }
}
}
static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
{
- struct mmc_omap_host *host = mmc_priv(mmc);
+ struct mmc_omap_slot *slot = mmc_priv(mmc);
+ struct mmc_omap_host *host = slot->host;
int func_clk_rate = clk_get_rate(host->fclk);
int dsor;
if (dsor > 250)
dsor = 250;
- dsor++;
+
+ slot->fclk_freq = func_clk_rate / dsor;
if (ios->bus_width == MMC_BUS_WIDTH_4)
dsor |= 1 << 15;
static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
- struct mmc_omap_host *host = mmc_priv(mmc);
- int dsor;
- int i;
+ struct mmc_omap_slot *slot = mmc_priv(mmc);
+ struct mmc_omap_host *host = slot->host;
+ int i, dsor;
+ int clk_enabled;
+
+ mmc_omap_select_slot(slot, 0);
dsor = mmc_omap_calc_divisor(mmc, ios);
- host->bus_mode = ios->bus_mode;
- host->hw_bus_mode = host->bus_mode;
+ if (ios->vdd != slot->vdd)
+ slot->vdd = ios->vdd;
+
+ clk_enabled = 0;
switch (ios->power_mode) {
case MMC_POWER_OFF:
- mmc_omap_power(host, 0);
+ mmc_omap_set_power(slot, 0, ios->vdd);
break;
case MMC_POWER_UP:
/* Cannot touch dsor yet, just power up MMC */
- mmc_omap_power(host, 1);
- return;
+ mmc_omap_set_power(slot, 1, ios->vdd);
+ goto exit;
case MMC_POWER_ON:
+ mmc_omap_fclk_enable(host, 1);
+ clk_enabled = 1;
dsor |= 1 << 11;
break;
}
- clk_enable(host->fclk);
+ if (slot->bus_mode != ios->bus_mode) {
+ if (slot->pdata->set_bus_mode != NULL)
+ slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
+ ios->bus_mode);
+ slot->bus_mode = ios->bus_mode;
+ }
/* On insanely high arm_per frequencies something sometimes
* goes somehow out of sync, and the POW bit is not being set,
* Writing to the CON register twice seems to do the trick. */
for (i = 0; i < 2; i++)
OMAP_MMC_WRITE(host, CON, dsor);
+ slot->saved_con = dsor;
if (ios->power_mode == MMC_POWER_ON) {
+ /* worst case at 400kHz, 80 cycles makes 200 microsecs */
+ int usecs = 250;
+
/* Send clock cycles, poll completion */
OMAP_MMC_WRITE(host, IE, 0);
OMAP_MMC_WRITE(host, STAT, 0xffff);
OMAP_MMC_WRITE(host, CMD, 1 << 7);
- while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
+ while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
+ udelay(1);
+ usecs--;
+ }
OMAP_MMC_WRITE(host, STAT, 1);
}
- clk_disable(host->fclk);
-}
-
-static int mmc_omap_get_ro(struct mmc_host *mmc)
-{
- struct mmc_omap_host *host = mmc_priv(mmc);
- return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
+exit:
+ mmc_omap_release_slot(slot, clk_enabled);
}
static const struct mmc_host_ops mmc_omap_ops = {
.request = mmc_omap_request,
.set_ios = mmc_omap_set_ios,
- .get_ro = mmc_omap_get_ro,
};
-static int __init mmc_omap_probe(struct platform_device *pdev)
+static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
{
- struct omap_mmc_conf *minfo = pdev->dev.platform_data;
+ struct mmc_omap_slot *slot = NULL;
struct mmc_host *mmc;
+ int r;
+
+ mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
+ if (mmc == NULL)
+ return -ENOMEM;
+
+ slot = mmc_priv(mmc);
+ slot->host = host;
+ slot->mmc = mmc;
+ slot->id = id;
+ slot->pdata = &host->pdata->slots[id];
+
+ host->slots[id] = slot;
+
+ mmc->caps = MMC_CAP_MULTIWRITE;
+ if (host->pdata->conf.wire4)
+ mmc->caps |= MMC_CAP_4_BIT_DATA;
+
+ mmc->ops = &mmc_omap_ops;
+ mmc->f_min = 400000;
+
+ if (cpu_class_is_omap2())
+ mmc->f_max = 48000000;
+ else
+ mmc->f_max = 24000000;
+ if (host->pdata->max_freq)
+ mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
+ mmc->ocr_avail = slot->pdata->ocr_mask;
+
+ /* Use scatterlist DMA to reduce per-transfer costs.
+ * NOTE max_seg_size assumption that small blocks aren't
+ * normally used (except e.g. for reading SD registers).
+ */
+ mmc->max_phys_segs = 32;
+ mmc->max_hw_segs = 32;
+ mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
+ mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
+ mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
+ mmc->max_seg_size = mmc->max_req_size;
+
+ r = mmc_add_host(mmc);
+ if (r < 0)
+ goto err_remove_host;
+
+ if (slot->pdata->name != NULL) {
+ r = device_create_file(&mmc->class_dev,
+ &dev_attr_slot_name);
+ if (r < 0)
+ goto err_remove_host;
+ }
+
+ if (slot->pdata->get_cover_state != NULL) {
+ r = device_create_file(&mmc->class_dev,
+ &dev_attr_cover_switch);
+ if (r < 0)
+ goto err_remove_slot_name;
+
+ setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
+ (unsigned long)slot);
+ tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
+ (unsigned long)slot);
+ tasklet_schedule(&slot->cover_tasklet);
+ }
+
+ return 0;
+
+err_remove_slot_name:
+ if (slot->pdata->name != NULL)
+ device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
+err_remove_host:
+ mmc_remove_host(mmc);
+ mmc_free_host(mmc);
+ return r;
+}
+
+static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
+{
+ struct mmc_host *mmc = slot->mmc;
+
+ if (slot->pdata->name != NULL)
+ device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
+ if (slot->pdata->get_cover_state != NULL)
+ device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
+
+ tasklet_kill(&slot->cover_tasklet);
+ del_timer_sync(&slot->cover_timer);
+ flush_scheduled_work();
+
+ mmc_remove_host(mmc);
+ mmc_free_host(mmc);
+}
+
+static int __init mmc_omap_probe(struct platform_device *pdev)
+{
+ struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
struct mmc_omap_host *host = NULL;
struct resource *res;
- int ret = 0;
+ int i, ret = 0;
int irq;
- if (minfo == NULL) {
+ if (pdata == NULL) {
dev_err(&pdev->dev, "platform data missing\n");
return -ENXIO;
}
+ if (pdata->nr_slots == 0) {
+ dev_err(&pdev->dev, "no slots\n");
+ return -ENXIO;
+ }
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
return -ENXIO;
res = request_mem_region(res->start, res->end - res->start + 1,
- pdev->name);
+ pdev->name);
if (res == NULL)
return -EBUSY;
- mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
- if (mmc == NULL) {
+ host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
+ if (host == NULL) {
ret = -ENOMEM;
goto err_free_mem_region;
}
- host = mmc_priv(mmc);
- host->mmc = mmc;
+ INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
+ INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
+
+ INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
+ setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
+ (unsigned long) host);
+
+ spin_lock_init(&host->clk_lock);
+ setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
spin_lock_init(&host->dma_lock);
- init_timer(&host->dma_timer);
- host->dma_timer.function = mmc_omap_dma_timer;
- host->dma_timer.data = (unsigned long) host;
+ setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
+ spin_lock_init(&host->slot_lock);
+ init_waitqueue_head(&host->slot_wq);
+
+ host->pdata = pdata;
+ host->dev = &pdev->dev;
+ platform_set_drvdata(pdev, host);
host->id = pdev->id;
host->mem_res = res;
host->irq = irq;
+ host->use_dma = 1;
+ host->dma_ch = -1;
+
+ host->irq = irq;
+ host->phys_base = host->mem_res->start;
+ host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
+
if (cpu_is_omap24xx()) {
host->iclk = clk_get(&pdev->dev, "mmc_ick");
if (IS_ERR(host->iclk))
goto err_free_iclk;
}
- /* REVISIT:
- * Also, use minfo->cover to decide how to manage
- * the card detect sensing.
- */
- host->power_pin = minfo->power_pin;
- host->switch_pin = minfo->switch_pin;
- host->wp_pin = minfo->wp_pin;
- host->use_dma = 1;
- host->dma_ch = -1;
-
- host->irq = irq;
- host->phys_base = host->mem_res->start;
- host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
-
- mmc->ops = &mmc_omap_ops;
- mmc->f_min = 400000;
- mmc->f_max = 24000000;
- mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
- mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
-
- if (minfo->wire4)
- mmc->caps |= MMC_CAP_4_BIT_DATA;
-
- /* Use scatterlist DMA to reduce per-transfer costs.
- * NOTE max_seg_size assumption that small blocks aren't
- * normally used (except e.g. for reading SD registers).
- */
- mmc->max_phys_segs = 32;
- mmc->max_hw_segs = 32;
- mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
- mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
- mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
- mmc->max_seg_size = mmc->max_req_size;
-
- if (host->power_pin >= 0) {
- if ((ret = omap_request_gpio(host->power_pin)) != 0) {
- dev_err(mmc_dev(host->mmc),
- "Unable to get GPIO pin for MMC power\n");
- goto err_free_fclk;
- }
- omap_set_gpio_direction(host->power_pin, 0);
- }
-
ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
if (ret)
- goto err_free_power_gpio;
+ goto err_free_fclk;
- host->dev = &pdev->dev;
- platform_set_drvdata(pdev, host);
+ if (pdata->init != NULL) {
+ ret = pdata->init(&pdev->dev);
+ if (ret < 0)
+ goto err_free_irq;
+ }
- if (host->switch_pin >= 0) {
- INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
- init_timer(&host->switch_timer);
- host->switch_timer.function = mmc_omap_switch_timer;
- host->switch_timer.data = (unsigned long) host;
- if (omap_request_gpio(host->switch_pin) != 0) {
- dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
- host->switch_pin = -1;
- goto no_switch;
- }
+ host->nr_slots = pdata->nr_slots;
+ for (i = 0; i < pdata->nr_slots; i++) {
+ ret = mmc_omap_new_slot(host, i);
+ if (ret < 0) {
+ while (--i >= 0)
+ mmc_omap_remove_slot(host->slots[i]);
- omap_set_gpio_direction(host->switch_pin, 1);
- ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
- mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
- if (ret) {
- dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
- omap_free_gpio(host->switch_pin);
- host->switch_pin = -1;
- goto no_switch;
- }
- ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
- if (ret == 0) {
- ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
- if (ret != 0)
- device_remove_file(&pdev->dev, &dev_attr_cover_switch);
+ goto err_plat_cleanup;
}
- if (ret) {
- dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
- free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
- omap_free_gpio(host->switch_pin);
- host->switch_pin = -1;
- goto no_switch;
- }
- if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
- schedule_work(&host->switch_work);
}
- mmc_add_host(mmc);
-
return 0;
-no_switch:
- /* FIXME: Free other resources too. */
- if (host) {
- if (host->iclk && !IS_ERR(host->iclk))
- clk_put(host->iclk);
- if (host->fclk && !IS_ERR(host->fclk))
- clk_put(host->fclk);
- mmc_free_host(host->mmc);
- }
-err_free_power_gpio:
- if (host->power_pin >= 0)
- omap_free_gpio(host->power_pin);
+err_plat_cleanup:
+ if (pdata->cleanup)
+ pdata->cleanup(&pdev->dev);
+err_free_irq:
+ free_irq(host->irq, host);
err_free_fclk:
clk_put(host->fclk);
err_free_iclk:
clk_put(host->iclk);
}
err_free_mmc_host:
- mmc_free_host(host->mmc);
+ kfree(host);
err_free_mem_region:
release_mem_region(res->start, res->end - res->start + 1);
return ret;
static int mmc_omap_remove(struct platform_device *pdev)
{
struct mmc_omap_host *host = platform_get_drvdata(pdev);
+ int i;
platform_set_drvdata(pdev, NULL);
BUG_ON(host == NULL);
- mmc_remove_host(host->mmc);
- free_irq(host->irq, host);
+ for (i = 0; i < host->nr_slots; i++)
+ mmc_omap_remove_slot(host->slots[i]);
+
+ if (host->pdata->cleanup)
+ host->pdata->cleanup(&pdev->dev);
- if (host->power_pin >= 0)
- omap_free_gpio(host->power_pin);
- if (host->switch_pin >= 0) {
- device_remove_file(&pdev->dev, &dev_attr_enable_poll);
- device_remove_file(&pdev->dev, &dev_attr_cover_switch);
- free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
- omap_free_gpio(host->switch_pin);
- host->switch_pin = -1;
- del_timer_sync(&host->switch_timer);
- flush_scheduled_work();
- }
if (host->iclk && !IS_ERR(host->iclk))
clk_put(host->iclk);
if (host->fclk && !IS_ERR(host->fclk))
release_mem_region(pdev->resource[0].start,
pdev->resource[0].end - pdev->resource[0].start + 1);
- mmc_free_host(host->mmc);
+ kfree(host);
return 0;
}
#ifdef CONFIG_PM
static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
{
- int ret = 0;
+ int i, ret = 0;
struct mmc_omap_host *host = platform_get_drvdata(pdev);
- if (host && host->suspended)
+ if (host == NULL || host->suspended)
return 0;
- if (host) {
- ret = mmc_suspend_host(host->mmc, mesg);
- if (ret == 0)
- host->suspended = 1;
+ for (i = 0; i < host->nr_slots; i++) {
+ struct mmc_omap_slot *slot;
+
+ slot = host->slots[i];
+ ret = mmc_suspend_host(slot->mmc, mesg);
+ if (ret < 0) {
+ while (--i >= 0) {
+ slot = host->slots[i];
+ mmc_resume_host(slot->mmc);
+ }
+ return ret;
+ }
}
- return ret;
+ host->suspended = 1;
+ return 0;
}
static int mmc_omap_resume(struct platform_device *pdev)
{
- int ret = 0;
+ int i, ret = 0;
struct mmc_omap_host *host = platform_get_drvdata(pdev);
- if (host && !host->suspended)
+ if (host == NULL || !host->suspended)
return 0;
- if (host) {
- ret = mmc_resume_host(host->mmc);
- if (ret == 0)
- host->suspended = 0;
- }
+ for (i = 0; i < host->nr_slots; i++) {
+ struct mmc_omap_slot *slot;
+ slot = host->slots[i];
+ ret = mmc_resume_host(slot->mmc);
+ if (ret < 0)
+ return ret;
- return ret;
+ host->suspended = 0;
+ }
+ return 0;
}
#else
#define mmc_omap_suspend NULL
/*
* linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
*
- * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
+ * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <linux/dma-mapping.h>
#include <linux/scatterlist.h>
+#include <linux/leds.h>
+
#include <linux/mmc/host.h>
#include "sdhci.h"
static unsigned int debug_quirks = 0;
-/* For multi controllers in one platform case */
-static u16 chip_index = 0;
-static spinlock_t index_lock;
-
/*
* Different quirks to handle when the hardware deviates from a strict
* interpretation of the SDHCI specification.
#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
/* Controller has bad caps bits, but really supports DMA */
#define SDHCI_QUIRK_FORCE_DMA (1<<1)
-/* Controller doesn't like some resets when there is no card inserted. */
+/* Controller doesn't like to be reset when there is no card inserted. */
#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
/* Controller doesn't like clearing the power reg before a change */
#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
{
.vendor = PCI_VENDOR_ID_RICOH,
.device = PCI_DEVICE_ID_RICOH_R5C822,
- .subvendor = PCI_ANY_ID,
+ .subvendor = PCI_VENDOR_ID_SAMSUNG,
.subdevice = PCI_ANY_ID,
.driver_data = SDHCI_QUIRK_FORCE_DMA |
SDHCI_QUIRK_NO_CARD_NO_RESET,
},
+ {
+ .vendor = PCI_VENDOR_ID_RICOH,
+ .device = PCI_DEVICE_ID_RICOH_R5C822,
+ .subvendor = PCI_ANY_ID,
+ .subdevice = PCI_ANY_ID,
+ .driver_data = SDHCI_QUIRK_FORCE_DMA,
+ },
+
{
.vendor = PCI_VENDOR_ID_TI,
.device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
}
+#ifdef CONFIG_LEDS_CLASS
+static void sdhci_led_control(struct led_classdev *led,
+ enum led_brightness brightness)
+{
+ struct sdhci_host *host = container_of(led, struct sdhci_host, led);
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ if (brightness == LED_OFF)
+ sdhci_deactivate_led(host);
+ else
+ sdhci_activate_led(host);
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+#endif
+
/*****************************************************************************\
* *
* Core functions *
WARN_ON(host->mrq != NULL);
+#ifndef CONFIG_LEDS_CLASS
sdhci_activate_led(host);
+#endif
host->mrq = mrq;
host->cmd = NULL;
host->data = NULL;
+#ifndef CONFIG_LEDS_CLASS
sdhci_deactivate_led(host);
+#endif
mmiowb();
spin_unlock_irqrestore(&host->lock, flags);
goto out;
}
- DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
+ DBG("*** %s got interrupt: 0x%08x\n",
+ mmc_hostname(host->mmc), intmask);
if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
if (chip->hosts[i]->flags & SDHCI_USE_DMA)
pci_set_master(pdev);
ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
- IRQF_SHARED, chip->hosts[i]->slot_descr,
+ IRQF_SHARED, mmc_hostname(chip->hosts[i]->mmc),
chip->hosts[i]);
if (ret)
return ret;
DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
- snprintf(host->slot_descr, 20, "sdhc%d:slot%d", chip->index, slot);
-
- ret = pci_request_region(pdev, host->bar, host->slot_descr);
+ ret = pci_request_region(pdev, host->bar, mmc_hostname(mmc));
if (ret)
goto free;
version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
if (version > 1) {
printk(KERN_ERR "%s: Unknown controller version (%d). "
- "You may experience problems.\n", host->slot_descr,
+ "You may experience problems.\n", mmc_hostname(mmc),
version);
}
(host->flags & SDHCI_USE_DMA)) {
printk(KERN_WARNING "%s: Will use DMA "
"mode even though HW doesn't fully "
- "claim to support it.\n", host->slot_descr);
+ "claim to support it.\n", mmc_hostname(mmc));
}
if (host->flags & SDHCI_USE_DMA) {
if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
printk(KERN_WARNING "%s: No suitable DMA available. "
- "Falling back to PIO.\n", host->slot_descr);
+ "Falling back to PIO.\n", mmc_hostname(mmc));
host->flags &= ~SDHCI_USE_DMA;
}
}
(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
if (host->max_clk == 0) {
printk(KERN_ERR "%s: Hardware doesn't specify base clock "
- "frequency.\n", host->slot_descr);
+ "frequency.\n", mmc_hostname(mmc));
ret = -ENODEV;
goto unmap;
}
(caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
if (host->timeout_clk == 0) {
printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
- "frequency.\n", host->slot_descr);
+ "frequency.\n", mmc_hostname(mmc));
ret = -ENODEV;
goto unmap;
}
if (mmc->ocr_avail == 0) {
printk(KERN_ERR "%s: Hardware doesn't report any "
- "support voltages.\n", host->slot_descr);
+ "support voltages.\n", mmc_hostname(mmc));
ret = -ENODEV;
goto unmap;
}
*/
mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
if (mmc->max_blk_size >= 3) {
- printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
- host->slot_descr);
+ printk(KERN_WARNING "%s: Invalid maximum block size, "
+ "assuming 512 bytes\n", mmc_hostname(mmc));
mmc->max_blk_size = 512;
} else
mmc->max_blk_size = 512 << mmc->max_blk_size;
setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
- host->slot_descr, host);
+ mmc_hostname(mmc), host);
if (ret)
goto untasklet;
sdhci_dumpregs(host);
#endif
+#ifdef CONFIG_LEDS_CLASS
+ host->led.name = mmc_hostname(mmc);
+ host->led.brightness = LED_OFF;
+ host->led.default_trigger = mmc_hostname(mmc);
+ host->led.brightness_set = sdhci_led_control;
+
+ ret = led_classdev_register(&pdev->dev, &host->led);
+ if (ret)
+ goto reset;
+#endif
+
mmiowb();
mmc_add_host(mmc);
- printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
- host->addr, host->irq,
+ printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n",
+ mmc_hostname(mmc), host->addr, host->irq,
(host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
return 0;
+#ifdef CONFIG_LEDS_CLASS
+reset:
+ sdhci_reset(host, SDHCI_RESET_ALL);
+ free_irq(host->irq, host);
+#endif
untasklet:
tasklet_kill(&host->card_tasklet);
tasklet_kill(&host->finish_tasklet);
mmc_remove_host(mmc);
+#ifdef CONFIG_LEDS_CLASS
+ led_classdev_unregister(&host->led);
+#endif
+
sdhci_reset(host, SDHCI_RESET_ALL);
free_irq(host->irq, host);
chip->num_slots = slots;
pci_set_drvdata(pdev, chip);
- /* Add for multi controller case */
- spin_lock(&index_lock);
- chip->index = chip_index++;
- spin_unlock(&index_lock);
-
for (i = 0;i < slots;i++) {
ret = sdhci_probe_slot(pdev, i);
if (ret) {
": Secure Digital Host Controller Interface driver\n");
printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
- spin_lock_init(&index_lock);
-
return pci_register_driver(&sdhci_driver);
}
/*
* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
*
- * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
+ * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
struct sdhci_chip *chip;
struct mmc_host *mmc; /* MMC structure */
+#ifdef CONFIG_LEDS_CLASS
+ struct led_classdev led; /* LED control */
+#endif
+
spinlock_t lock; /* Mutex */
int flags; /* Host attributes */
int offset; /* Offset into current sg */
int remain; /* Bytes left in current */
- char slot_descr[20]; /* Name for reservations */
-
int irq; /* Device IRQ */
int bar; /* PCI BAR index */
unsigned long addr; /* Bus address */
unsigned long quirks;
- int index; /* Index for chip0, chip1 ...*/
int num_slots; /* Slots on controller */
struct sdhci_host *hosts[0]; /* Pointers to hosts */
};
config MTD_NAND_ORION
tristate "NAND Flash support for Marvell Orion SoC"
- depends on ARCH_ORION && MTD_NAND
+ depends on PLAT_ORION && MTD_NAND
help
This enables the NAND flash controller on Orion machines.
#include <linux/mtd/partitions.h>
#include <asm/io.h>
-
+#include <asm/fsl_lbc.h>
#define MAX_BANKS 8
#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
-struct elbc_bank {
- __be32 br; /**< Base Register */
-#define BR_BA 0xFFFF8000
-#define BR_BA_SHIFT 15
-#define BR_PS 0x00001800
-#define BR_PS_SHIFT 11
-#define BR_PS_8 0x00000800 /* Port Size 8 bit */
-#define BR_PS_16 0x00001000 /* Port Size 16 bit */
-#define BR_PS_32 0x00001800 /* Port Size 32 bit */
-#define BR_DECC 0x00000600
-#define BR_DECC_SHIFT 9
-#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
-#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
-#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
-#define BR_WP 0x00000100
-#define BR_WP_SHIFT 8
-#define BR_MSEL 0x000000E0
-#define BR_MSEL_SHIFT 5
-#define BR_MS_GPCM 0x00000000 /* GPCM */
-#define BR_MS_FCM 0x00000020 /* FCM */
-#define BR_MS_SDRAM 0x00000060 /* SDRAM */
-#define BR_MS_UPMA 0x00000080 /* UPMA */
-#define BR_MS_UPMB 0x000000A0 /* UPMB */
-#define BR_MS_UPMC 0x000000C0 /* UPMC */
-#define BR_V 0x00000001
-#define BR_V_SHIFT 0
-#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
-
- __be32 or; /**< Base Register */
-#define OR0 0x5004
-#define OR1 0x500C
-#define OR2 0x5014
-#define OR3 0x501C
-#define OR4 0x5024
-#define OR5 0x502C
-#define OR6 0x5034
-#define OR7 0x503C
-
-#define OR_FCM_AM 0xFFFF8000
-#define OR_FCM_AM_SHIFT 15
-#define OR_FCM_BCTLD 0x00001000
-#define OR_FCM_BCTLD_SHIFT 12
-#define OR_FCM_PGS 0x00000400
-#define OR_FCM_PGS_SHIFT 10
-#define OR_FCM_CSCT 0x00000200
-#define OR_FCM_CSCT_SHIFT 9
-#define OR_FCM_CST 0x00000100
-#define OR_FCM_CST_SHIFT 8
-#define OR_FCM_CHT 0x00000080
-#define OR_FCM_CHT_SHIFT 7
-#define OR_FCM_SCY 0x00000070
-#define OR_FCM_SCY_SHIFT 4
-#define OR_FCM_SCY_1 0x00000010
-#define OR_FCM_SCY_2 0x00000020
-#define OR_FCM_SCY_3 0x00000030
-#define OR_FCM_SCY_4 0x00000040
-#define OR_FCM_SCY_5 0x00000050
-#define OR_FCM_SCY_6 0x00000060
-#define OR_FCM_SCY_7 0x00000070
-#define OR_FCM_RST 0x00000008
-#define OR_FCM_RST_SHIFT 3
-#define OR_FCM_TRLX 0x00000004
-#define OR_FCM_TRLX_SHIFT 2
-#define OR_FCM_EHTR 0x00000002
-#define OR_FCM_EHTR_SHIFT 1
-};
-
-struct elbc_regs {
- struct elbc_bank bank[8];
- u8 res0[0x28];
- __be32 mar; /**< UPM Address Register */
- u8 res1[0x4];
- __be32 mamr; /**< UPMA Mode Register */
- __be32 mbmr; /**< UPMB Mode Register */
- __be32 mcmr; /**< UPMC Mode Register */
- u8 res2[0x8];
- __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
- __be32 mdr; /**< UPM Data Register */
- u8 res3[0x4];
- __be32 lsor; /**< Special Operation Initiation Register */
- __be32 lsdmr; /**< SDRAM Mode Register */
- u8 res4[0x8];
- __be32 lurt; /**< UPM Refresh Timer */
- __be32 lsrt; /**< SDRAM Refresh Timer */
- u8 res5[0x8];
- __be32 ltesr; /**< Transfer Error Status Register */
-#define LTESR_BM 0x80000000
-#define LTESR_FCT 0x40000000
-#define LTESR_PAR 0x20000000
-#define LTESR_WP 0x04000000
-#define LTESR_ATMW 0x00800000
-#define LTESR_ATMR 0x00400000
-#define LTESR_CS 0x00080000
-#define LTESR_CC 0x00000001
-#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
- __be32 ltedr; /**< Transfer Error Disable Register */
- __be32 lteir; /**< Transfer Error Interrupt Register */
- __be32 lteatr; /**< Transfer Error Attributes Register */
- __be32 ltear; /**< Transfer Error Address Register */
- u8 res6[0xC];
- __be32 lbcr; /**< Configuration Register */
-#define LBCR_LDIS 0x80000000
-#define LBCR_LDIS_SHIFT 31
-#define LBCR_BCTLC 0x00C00000
-#define LBCR_BCTLC_SHIFT 22
-#define LBCR_AHD 0x00200000
-#define LBCR_LPBSE 0x00020000
-#define LBCR_LPBSE_SHIFT 17
-#define LBCR_EPAR 0x00010000
-#define LBCR_EPAR_SHIFT 16
-#define LBCR_BMT 0x0000FF00
-#define LBCR_BMT_SHIFT 8
-#define LBCR_INIT 0x00040000
- __be32 lcrr; /**< Clock Ratio Register */
-#define LCRR_DBYP 0x80000000
-#define LCRR_DBYP_SHIFT 31
-#define LCRR_BUFCMDC 0x30000000
-#define LCRR_BUFCMDC_SHIFT 28
-#define LCRR_ECL 0x03000000
-#define LCRR_ECL_SHIFT 24
-#define LCRR_EADC 0x00030000
-#define LCRR_EADC_SHIFT 16
-#define LCRR_CLKDIV 0x0000000F
-#define LCRR_CLKDIV_SHIFT 0
- u8 res7[0x8];
- __be32 fmr; /**< Flash Mode Register */
-#define FMR_CWTO 0x0000F000
-#define FMR_CWTO_SHIFT 12
-#define FMR_BOOT 0x00000800
-#define FMR_ECCM 0x00000100
-#define FMR_AL 0x00000030
-#define FMR_AL_SHIFT 4
-#define FMR_OP 0x00000003
-#define FMR_OP_SHIFT 0
- __be32 fir; /**< Flash Instruction Register */
-#define FIR_OP0 0xF0000000
-#define FIR_OP0_SHIFT 28
-#define FIR_OP1 0x0F000000
-#define FIR_OP1_SHIFT 24
-#define FIR_OP2 0x00F00000
-#define FIR_OP2_SHIFT 20
-#define FIR_OP3 0x000F0000
-#define FIR_OP3_SHIFT 16
-#define FIR_OP4 0x0000F000
-#define FIR_OP4_SHIFT 12
-#define FIR_OP5 0x00000F00
-#define FIR_OP5_SHIFT 8
-#define FIR_OP6 0x000000F0
-#define FIR_OP6_SHIFT 4
-#define FIR_OP7 0x0000000F
-#define FIR_OP7_SHIFT 0
-#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
-#define FIR_OP_CA 0x1 /* Issue current column address */
-#define FIR_OP_PA 0x2 /* Issue current block+page address */
-#define FIR_OP_UA 0x3 /* Issue user defined address */
-#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
-#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
-#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
-#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
-#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
-#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
-#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
-#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
-#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
-#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
-#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
-#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
- __be32 fcr; /**< Flash Command Register */
-#define FCR_CMD0 0xFF000000
-#define FCR_CMD0_SHIFT 24
-#define FCR_CMD1 0x00FF0000
-#define FCR_CMD1_SHIFT 16
-#define FCR_CMD2 0x0000FF00
-#define FCR_CMD2_SHIFT 8
-#define FCR_CMD3 0x000000FF
-#define FCR_CMD3_SHIFT 0
- __be32 fbar; /**< Flash Block Address Register */
-#define FBAR_BLK 0x00FFFFFF
- __be32 fpar; /**< Flash Page Address Register */
-#define FPAR_SP_PI 0x00007C00
-#define FPAR_SP_PI_SHIFT 10
-#define FPAR_SP_MS 0x00000200
-#define FPAR_SP_CI 0x000001FF
-#define FPAR_SP_CI_SHIFT 0
-#define FPAR_LP_PI 0x0003F000
-#define FPAR_LP_PI_SHIFT 12
-#define FPAR_LP_MS 0x00000800
-#define FPAR_LP_CI 0x000007FF
-#define FPAR_LP_CI_SHIFT 0
- __be32 fbcr; /**< Flash Byte Count Register */
-#define FBCR_BC 0x00000FFF
- u8 res11[0x8];
- u8 res8[0xF00];
-};
-
struct fsl_elbc_ctrl;
/* mtd information per set */
/* device info */
struct device *dev;
- struct elbc_regs __iomem *regs;
+ struct fsl_lbc_regs __iomem *regs;
int irq;
wait_queue_head_t irq_wait;
unsigned int irq_status; /* status read from LTESR by irq handler */
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
int buf_num;
ctrl->page = page_addr;
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
/* Setup the FMR[OP] to execute without write protection */
out_be32(&lbc->fmr, priv->fmr | 3);
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
if (priv->page_size) {
out_be32(&lbc->fir,
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
ctrl->use_mdr = 0;
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
if (ctrl->status != LTESR_CC)
return NAND_STATUS_FAIL;
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
unsigned int al;
/* calculate FMR Address Length field */
static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
{
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
struct nand_chip *chip = &priv->chip;
dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
struct device_node *node)
{
- struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
struct fsl_elbc_mtd *priv;
struct resource res;
#ifdef CONFIG_MTD_PARTITIONS
static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
{
- struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
/* clear event registers */
setbits32(&lbc->ltesr, LTESR_NAND_MASK);
static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
{
struct fsl_elbc_ctrl *ctrl = data;
- struct elbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
__be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
if (status) {
#include <linux/mtd/partitions.h>
#include <asm/io.h>
#include <asm/sizes.h>
-#include <asm/arch/platform.h>
#include <asm/arch/hardware.h>
+#include <asm/plat-orion/orion_nand.h>
#ifdef CONFIG_MTD_CMDLINE_PARTS
static const char *part_probes[] = { "cmdlinepart", NULL };
#include <linux/ethtool.h>
#include <linux/completion.h>
#include <linux/bitops.h>
+#include <linux/semaphore.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/io.h>
config MV643XX_ETH
tristate "Marvell Discovery (643XX) and Orion ethernet support"
- depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || ARCH_ORION
+ depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || PLAT_ORION
select MII
help
This driver supports the gigabit ethernet MACs in the
obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
obj-$(CONFIG_DM9000) += dm9000.o
obj-$(CONFIG_FEC_8XX) += fec_8xx/
-obj-$(CONFIG_PASEMI_MAC) += pasemi_mac.o
+obj-$(CONFIG_PASEMI_MAC) += pasemi_mac_driver.o
+pasemi_mac_driver-objs := pasemi_mac.o pasemi_mac_ethtool.o
obj-$(CONFIG_MLX4_CORE) += mlx4/
obj-$(CONFIG_ENC28J60) += enc28j60.o
} else if (machine_is_csb337()) {
/* mix link activity status into LED2 link state */
write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
- }
+ } else if (machine_is_ecbat91())
+ write_phy(phy_address, MII_LEDCTRL_REG, 0x156A);
+
disable_mdi();
spin_unlock_irq(&lp->lock);
#include <linux/mutex.h>
#include <linux/bitops.h>
#include "t3cdev.h"
-#include <asm/semaphore.h>
#include <asm/io.h>
struct vlan_group;
#include <linux/list.h>
#include <asm/atomic.h>
-#include <asm/semaphore.h>
#include <linux/netdevice.h>
#include <linux/proc_fs.h>
#include <linux/skbuff.h>
#include <linux/init.h>
#include <linux/ip.h>
#include <linux/tcp.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include <asm/atomic.h>
#define SIXPACK_VERSION "Revision: 0.3.0"
#include <linux/in.h>
#include <linux/ip.h>
#include <net/net_namespace.h>
-#include <asm/semaphore.h>
#include <asm/hvcall.h>
#include <asm/atomic.h>
#include <asm/vio.h>
#include <asm/hardware.h>
#include <asm/arch/irda.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#ifdef CONFIG_MACH_MAINSTONE
#include <asm/arch/mainstone.h>
if (err)
goto err_mem_5;
+ if (si->pdata->startup)
+ err = si->pdata->startup(si->dev);
+ if (err)
+ goto err_startup;
+
dev->hard_start_xmit = pxa_irda_hard_xmit;
dev->open = pxa_irda_start;
dev->stop = pxa_irda_stop;
dev_set_drvdata(&pdev->dev, dev);
if (err) {
+ if (si->pdata->shutdown)
+ si->pdata->shutdown(si->dev);
+err_startup:
kfree(si->tx_buff.head);
err_mem_5:
kfree(si->rx_buff.head);
if (dev) {
struct pxa_irda *si = netdev_priv(dev);
unregister_netdev(dev);
+ if (si->pdata->shutdown)
+ si->pdata->shutdown(si->dev);
kfree(si->tx_buff.head);
kfree(si->rx_buff.head);
clk_put(si->fir_clk);
static int veth_allocate_events(HvLpIndex rlp, int number)
{
- struct veth_allocation vc = { COMPLETION_INITIALIZER(vc.c), 0 };
+ struct veth_allocation vc =
+ { COMPLETION_INITIALIZER_ONSTACK(vc.c), 0 };
mf_allocate_lp_events(rlp, HvLpEvent_Type_VirtualLan,
sizeof(struct veth_lpevent), number,
#include <linux/kernel.h>
#include <linux/version.h>
-#include <asm/semaphore.h>
#include <linux/spinlock.h>
#include <asm/irq.h>
#include <linux/init.h>
* - Multiqueue RX/TX
*/
-
-/* Must be a power of two */
-#define RX_RING_SIZE 2048
-#define TX_RING_SIZE 4096
-
#define LRO_MAX_AGGR 64
#define PE_MIN_MTU 64
-#define PE_MAX_MTU 1500
+#define PE_MAX_MTU 9000
#define PE_DEF_MTU ETH_DATA_LEN
#define DEFAULT_MSG_ENABLE \
NETIF_MSG_RX_ERR | \
NETIF_MSG_TX_ERR)
-#define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)])
-#define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)])
-#define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
-#define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
-#define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)])
-
-#define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
- & ((ring)->size - 1))
-#define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
-
MODULE_LICENSE("GPL");
MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
+extern const struct ethtool_ops pasemi_mac_ethtool_ops;
+
static int translation_enabled(void)
{
#if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
return (nfrags + 3) & ~1;
}
+static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac)
+{
+ struct pasemi_mac_csring *ring;
+ u32 val;
+ unsigned int cfg;
+ int chno;
+
+ ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring),
+ offsetof(struct pasemi_mac_csring, chan));
+
+ if (!ring) {
+ dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n");
+ goto out_chan;
+ }
+
+ chno = ring->chan.chno;
+
+ ring->size = CS_RING_SIZE;
+ ring->next_to_fill = 0;
+
+ /* Allocate descriptors */
+ if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE))
+ goto out_ring_desc;
+
+ write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
+ PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
+ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
+ val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3);
+
+ write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
+
+ ring->events[0] = pasemi_dma_alloc_flag();
+ ring->events[1] = pasemi_dma_alloc_flag();
+ if (ring->events[0] < 0 || ring->events[1] < 0)
+ goto out_flags;
+
+ pasemi_dma_clear_flag(ring->events[0]);
+ pasemi_dma_clear_flag(ring->events[1]);
+
+ ring->fun = pasemi_dma_alloc_fun();
+ if (ring->fun < 0)
+ goto out_fun;
+
+ cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP |
+ PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) |
+ PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ;
+
+ if (translation_enabled())
+ cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
+
+ write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
+
+ /* enable channel */
+ pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
+ PAS_DMA_TXCHAN_TCMDSTA_DB |
+ PAS_DMA_TXCHAN_TCMDSTA_DE |
+ PAS_DMA_TXCHAN_TCMDSTA_DA);
+
+ return ring;
+
+out_fun:
+out_flags:
+ if (ring->events[0] >= 0)
+ pasemi_dma_free_flag(ring->events[0]);
+ if (ring->events[1] >= 0)
+ pasemi_dma_free_flag(ring->events[1]);
+ pasemi_dma_free_ring(&ring->chan);
+out_ring_desc:
+ pasemi_dma_free_chan(&ring->chan);
+out_chan:
+
+ return NULL;
+}
+
+static void pasemi_mac_setup_csrings(struct pasemi_mac *mac)
+{
+ int i;
+ mac->cs[0] = pasemi_mac_setup_csring(mac);
+ if (mac->type == MAC_TYPE_XAUI)
+ mac->cs[1] = pasemi_mac_setup_csring(mac);
+ else
+ mac->cs[1] = 0;
+
+ for (i = 0; i < MAX_CS; i++)
+ if (mac->cs[i])
+ mac->num_cs++;
+}
+
+static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring)
+{
+ pasemi_dma_stop_chan(&csring->chan);
+ pasemi_dma_free_flag(csring->events[0]);
+ pasemi_dma_free_flag(csring->events[1]);
+ pasemi_dma_free_ring(&csring->chan);
+ pasemi_dma_free_chan(&csring->chan);
+ pasemi_dma_free_fun(csring->fun);
+}
+
static int pasemi_mac_setup_rx_resources(const struct net_device *dev)
{
struct pasemi_mac_rxring *ring;
cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
PAS_DMA_TXCHAN_CFG_UP |
- PAS_DMA_TXCHAN_CFG_WT(2);
+ PAS_DMA_TXCHAN_CFG_WT(4);
if (translation_enabled())
cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
u64 mactx = TX_DESC(txring, i);
struct sk_buff *skb;
- skb = TX_DESC_INFO(txring, i+1).skb;
- nr_frags = TX_DESC_INFO(txring, i).dma;
-
if ((mactx & XCT_MACTX_E) ||
(*chan->status & PAS_STATUS_ERROR))
pasemi_mac_tx_error(mac, mactx);
+ /* Skip over control descriptors */
+ if (!(mactx & XCT_MACTX_LLEN_M)) {
+ TX_DESC(txring, i) = 0;
+ TX_DESC(txring, i+1) = 0;
+ buf_count = 2;
+ continue;
+ }
+
+ skb = TX_DESC_INFO(txring, i+1).skb;
+ nr_frags = TX_DESC_INFO(txring, i).dma;
+
if (unlikely(mactx & XCT_MACTX_O))
/* Not yet transmitted */
break;
{
struct pasemi_mac *mac = netdev_priv(dev);
unsigned int flags;
- int ret;
-
- /* enable rx section */
- write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
-
- /* enable tx section */
- write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
+ int i, ret;
flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
if (!mac->tx)
goto out_tx_ring;
+ /* We might already have allocated rings in case mtu was changed
+ * before interface was brought up.
+ */
+ if (dev->mtu > 1500 && !mac->num_cs) {
+ pasemi_mac_setup_csrings(mac);
+ if (!mac->num_cs)
+ goto out_tx_ring;
+ }
+
+ /* Zero out rmon counters */
+ for (i = 0; i < 32; i++)
+ write_mac_reg(mac, PAS_MAC_RMON(i), 0);
+
/* 0x3ff with 33MHz clock is about 31us */
write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff));
{
struct pasemi_mac *mac = netdev_priv(dev);
unsigned int sta;
- int rxch, txch;
+ int rxch, txch, i;
rxch = rx_ring(mac)->chan.chno;
txch = tx_ring(mac)->chan.chno;
free_irq(mac->tx->chan.irq, mac->tx);
free_irq(mac->rx->chan.irq, mac->rx);
+ for (i = 0; i < mac->num_cs; i++) {
+ pasemi_mac_free_csring(mac->cs[i]);
+ mac->cs[i] = NULL;
+ }
+
+ mac->num_cs = 0;
+
/* Free resources */
pasemi_mac_free_rx_resources(mac);
pasemi_mac_free_tx_resources(mac);
return 0;
}
+static void pasemi_mac_queue_csdesc(const struct sk_buff *skb,
+ const dma_addr_t *map,
+ const unsigned int *map_size,
+ struct pasemi_mac_txring *txring,
+ struct pasemi_mac_csring *csring)
+{
+ u64 fund;
+ dma_addr_t cs_dest;
+ const int nh_off = skb_network_offset(skb);
+ const int nh_len = skb_network_header_len(skb);
+ const int nfrags = skb_shinfo(skb)->nr_frags;
+ int cs_size, i, fill, hdr, cpyhdr, evt;
+ dma_addr_t csdma;
+
+ fund = XCT_FUN_ST | XCT_FUN_RR_8BRES |
+ XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
+ XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) |
+ XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE;
+
+ switch (ip_hdr(skb)->protocol) {
+ case IPPROTO_TCP:
+ fund |= XCT_FUN_SIG_TCP4;
+ /* TCP checksum is 16 bytes into the header */
+ cs_dest = map[0] + skb_transport_offset(skb) + 16;
+ break;
+ case IPPROTO_UDP:
+ fund |= XCT_FUN_SIG_UDP4;
+ /* UDP checksum is 6 bytes into the header */
+ cs_dest = map[0] + skb_transport_offset(skb) + 6;
+ break;
+ default:
+ BUG();
+ }
+
+ /* Do the checksum offloaded */
+ fill = csring->next_to_fill;
+ hdr = fill;
+
+ CS_DESC(csring, fill++) = fund;
+ /* Room for 8BRES. Checksum result is really 2 bytes into it */
+ csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2;
+ CS_DESC(csring, fill++) = 0;
+
+ CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off);
+ for (i = 1; i <= nfrags; i++)
+ CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
+
+ fill += i;
+ if (fill & 1)
+ fill++;
+
+ /* Copy the result into the TCP packet */
+ cpyhdr = fill;
+ CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
+ XCT_FUN_LLEN(2) | XCT_FUN_SE;
+ CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T;
+ CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma);
+ fill++;
+
+ evt = !csring->last_event;
+ csring->last_event = evt;
+
+ /* Event handshaking with MAC TX */
+ CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
+ CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]);
+ CS_DESC(csring, fill++) = 0;
+ CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
+ CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]);
+ CS_DESC(csring, fill++) = 0;
+ csring->next_to_fill = fill & (CS_RING_SIZE-1);
+
+ cs_size = fill - hdr;
+ write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1);
+
+ /* TX-side event handshaking */
+ fill = txring->next_to_fill;
+ TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
+ CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]);
+ TX_DESC(txring, fill++) = 0;
+ TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
+ CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]);
+ TX_DESC(txring, fill++) = 0;
+ txring->next_to_fill = fill;
+
+ write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2);
+
+ return;
+}
+
static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
{
- struct pasemi_mac *mac = netdev_priv(dev);
- struct pasemi_mac_txring *txring;
- u64 dflags, mactx;
+ struct pasemi_mac * const mac = netdev_priv(dev);
+ struct pasemi_mac_txring * const txring = tx_ring(mac);
+ struct pasemi_mac_csring *csring;
+ u64 dflags = 0;
+ u64 mactx;
dma_addr_t map[MAX_SKB_FRAGS+1];
unsigned int map_size[MAX_SKB_FRAGS+1];
unsigned long flags;
int i, nfrags;
int fill;
+ const int nh_off = skb_network_offset(skb);
+ const int nh_len = skb_network_header_len(skb);
- dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
-
- if (skb->ip_summed == CHECKSUM_PARTIAL) {
- const unsigned char *nh = skb_network_header(skb);
+ prefetch(&txring->ring_info);
- switch (ip_hdr(skb)->protocol) {
- case IPPROTO_TCP:
- dflags |= XCT_MACTX_CSUM_TCP;
- dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
- dflags |= XCT_MACTX_IPO(nh - skb->data);
- break;
- case IPPROTO_UDP:
- dflags |= XCT_MACTX_CSUM_UDP;
- dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
- dflags |= XCT_MACTX_IPO(nh - skb->data);
- break;
- }
- }
+ dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
nfrags = skb_shinfo(skb)->nr_frags;
}
}
- mactx = dflags | XCT_MACTX_LLEN(skb->len);
+ if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) {
+ switch (ip_hdr(skb)->protocol) {
+ case IPPROTO_TCP:
+ dflags |= XCT_MACTX_CSUM_TCP;
+ dflags |= XCT_MACTX_IPH(nh_len >> 2);
+ dflags |= XCT_MACTX_IPO(nh_off);
+ break;
+ case IPPROTO_UDP:
+ dflags |= XCT_MACTX_CSUM_UDP;
+ dflags |= XCT_MACTX_IPH(nh_len >> 2);
+ dflags |= XCT_MACTX_IPO(nh_off);
+ break;
+ default:
+ WARN_ON(1);
+ }
+ }
- txring = tx_ring(mac);
+ mactx = dflags | XCT_MACTX_LLEN(skb->len);
spin_lock_irqsave(&txring->lock, flags);
- fill = txring->next_to_fill;
-
/* Avoid stepping on the same cache line that the DMA controller
* is currently about to send, so leave at least 8 words available.
* Total free space needed is mactx + fragments + 8
*/
- if (RING_AVAIL(txring) < nfrags + 10) {
+ if (RING_AVAIL(txring) < nfrags + 14) {
/* no room -- stop the queue and wait for tx intr */
netif_stop_queue(dev);
goto out_err;
}
+ /* Queue up checksum + event descriptors, if needed */
+ if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) {
+ csring = mac->cs[mac->last_cs];
+ mac->last_cs = (mac->last_cs + 1) % mac->num_cs;
+
+ pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring);
+ }
+
+ fill = txring->next_to_fill;
TX_DESC(txring, fill) = mactx;
TX_DESC_INFO(txring, fill).dma = nfrags;
fill++;
return pkts;
}
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/*
+ * Polling 'interrupt' - used by things like netconsole to send skbs
+ * without having to re-enable interrupts. It's not called while
+ * the interrupt routine is executing.
+ */
+static void pasemi_mac_netpoll(struct net_device *dev)
+{
+ const struct pasemi_mac *mac = netdev_priv(dev);
+
+ disable_irq(mac->tx->chan.irq);
+ pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx);
+ enable_irq(mac->tx->chan.irq);
+
+ disable_irq(mac->rx->chan.irq);
+ pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx);
+ enable_irq(mac->rx->chan.irq);
+}
+#endif
+
static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu)
{
struct pasemi_mac *mac = netdev_priv(dev);
unsigned int reg;
- unsigned int rcmdsta;
+ unsigned int rcmdsta = 0;
int running;
+ int ret = 0;
if (new_mtu < PE_MIN_MTU || new_mtu > PE_MAX_MTU)
return -EINVAL;
pasemi_mac_pause_rxint(mac);
pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
pasemi_mac_free_rx_buffers(mac);
+
+ }
+
+ /* Setup checksum channels if large MTU and none already allocated */
+ if (new_mtu > 1500 && !mac->num_cs) {
+ pasemi_mac_setup_csrings(mac);
+ if (!mac->num_cs) {
+ ret = -ENOMEM;
+ goto out;
+ }
}
/* Change maxf, i.e. what size frames are accepted.
/* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
+out:
if (running) {
write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN);
pasemi_mac_intf_enable(mac);
}
- return 0;
+ return ret;
}
static int __devinit
netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG |
- NETIF_F_HIGHDMA;
+ NETIF_F_HIGHDMA | NETIF_F_GSO;
mac->lro_mgr.max_aggr = LRO_MAX_AGGR;
mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
dev->mtu = PE_DEF_MTU;
/* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ dev->poll_controller = pasemi_mac_netpoll;
+#endif
dev->change_mtu = pasemi_mac_change_mtu;
+ dev->ethtool_ops = &pasemi_mac_ethtool_ops;
if (err)
goto out;
#include <linux/spinlock.h>
#include <linux/phy.h>
+/* Must be a power of two */
+#define RX_RING_SIZE 2048
+#define TX_RING_SIZE 4096
+#define CS_RING_SIZE (TX_RING_SIZE*2)
+
+
#define MAX_LRO_DESCRIPTORS 8
+#define MAX_CS 2
struct pasemi_mac_txring {
struct pasemi_dmachan chan; /* Must be first */
struct pasemi_mac *mac; /* Needed in intr handler */
};
+struct pasemi_mac_csring {
+ struct pasemi_dmachan chan;
+ unsigned int size;
+ unsigned int next_to_fill;
+ int events[2];
+ int last_event;
+ int fun;
+};
+
struct pasemi_mac {
struct net_device *netdev;
struct pci_dev *pdev;
struct napi_struct napi;
int bufsz; /* RX ring buffer size */
+ int last_cs;
+ int num_cs;
+ u32 dma_if;
u8 type;
#define MAC_TYPE_GMAC 1
#define MAC_TYPE_XAUI 2
- u32 dma_if;
u8 mac_addr[6];
struct pasemi_mac_txring *tx;
struct pasemi_mac_rxring *rx;
+ struct pasemi_mac_csring *cs[MAX_CS];
char tx_irq_name[10]; /* "eth%d tx" */
char rx_irq_name[10]; /* "eth%d rx" */
int link;
dma_addr_t dma;
};
+#define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)])
+#define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)])
+#define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
+#define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
+#define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)])
+#define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)])
+
+#define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
+ & ((ring)->size - 1))
+#define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
/* PCI register offsets and formats */
PAS_MAC_CFG_ADR0 = 0x8c,
PAS_MAC_CFG_ADR1 = 0x90,
PAS_MAC_CFG_TXP = 0x98,
+ PAS_MAC_CFG_RMON = 0x100,
PAS_MAC_IPC_CHNL = 0x208,
};
#define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
PAS_MAC_CFG_TXP_TIFG_M)
+#define PAS_MAC_RMON(r) (0x100+(r)*4)
+
#define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000
#define PAS_MAC_IPC_CHNL_DCHNO_S 16
#define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
#define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
PAS_MAC_IPC_CHNL_BCH_M)
+
#endif /* PASEMI_MAC_H */
--- /dev/null
+/*
+ * Copyright (C) 2006-2008 PA Semi, Inc
+ *
+ * Ethtool hooks for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+#include <linux/pci.h>
+#include <linux/inet_lro.h>
+
+#include <asm/pasemi_dma.h>
+#include "pasemi_mac.h"
+
+static struct {
+ const char str[ETH_GSTRING_LEN];
+} ethtool_stats_keys[] = {
+ { "rx-drops" },
+ { "rx-bytes" },
+ { "rx-packets" },
+ { "rx-broadcast-packets" },
+ { "rx-multicast-packets" },
+ { "rx-crc-errors" },
+ { "rx-undersize-errors" },
+ { "rx-oversize-errors" },
+ { "rx-short-fragment-errors" },
+ { "rx-jabber-errors" },
+ { "rx-64-byte-packets" },
+ { "rx-65-127-byte-packets" },
+ { "rx-128-255-byte-packets" },
+ { "rx-256-511-byte-packets" },
+ { "rx-512-1023-byte-packets" },
+ { "rx-1024-1518-byte-packets" },
+ { "rx-pause-frames" },
+ { "tx-bytes" },
+ { "tx-packets" },
+ { "tx-broadcast-packets" },
+ { "tx-multicast-packets" },
+ { "tx-collisions" },
+ { "tx-late-collisions" },
+ { "tx-excessive-collisions" },
+ { "tx-crc-errors" },
+ { "tx-undersize-errors" },
+ { "tx-oversize-errors" },
+ { "tx-64-byte-packets" },
+ { "tx-65-127-byte-packets" },
+ { "tx-128-255-byte-packets" },
+ { "tx-256-511-byte-packets" },
+ { "tx-512-1023-byte-packets" },
+ { "tx-1024-1518-byte-packets" },
+};
+
+static int
+pasemi_mac_ethtool_get_settings(struct net_device *netdev,
+ struct ethtool_cmd *cmd)
+{
+ struct pasemi_mac *mac = netdev_priv(netdev);
+ struct phy_device *phydev = mac->phydev;
+
+ return phy_ethtool_gset(phydev, cmd);
+}
+
+static void
+pasemi_mac_ethtool_get_drvinfo(struct net_device *netdev,
+ struct ethtool_drvinfo *drvinfo)
+{
+ struct pasemi_mac *mac;
+ mac = netdev_priv(netdev);
+
+ /* clear and fill out info */
+ memset(drvinfo, 0, sizeof(struct ethtool_drvinfo));
+ strncpy(drvinfo->driver, "pasemi_mac", 12);
+ strcpy(drvinfo->version, "N/A");
+ strcpy(drvinfo->fw_version, "N/A");
+ strncpy(drvinfo->bus_info, pci_name(mac->pdev), 32);
+}
+
+static u32
+pasemi_mac_ethtool_get_msglevel(struct net_device *netdev)
+{
+ struct pasemi_mac *mac = netdev_priv(netdev);
+ return mac->msg_enable;
+}
+
+static void
+pasemi_mac_ethtool_set_msglevel(struct net_device *netdev,
+ u32 level)
+{
+ struct pasemi_mac *mac = netdev_priv(netdev);
+ mac->msg_enable = level;
+}
+
+
+static void
+pasemi_mac_ethtool_get_ringparam(struct net_device *netdev,
+ struct ethtool_ringparam *ering)
+{
+ struct pasemi_mac *mac = netdev->priv;
+
+ ering->tx_max_pending = TX_RING_SIZE/2;
+ ering->tx_pending = RING_USED(mac->tx)/2;
+ ering->rx_max_pending = RX_RING_SIZE/4;
+ ering->rx_pending = RING_USED(mac->rx)/4;
+}
+
+static int pasemi_mac_get_sset_count(struct net_device *netdev, int sset)
+{
+ switch (sset) {
+ case ETH_SS_STATS:
+ return ARRAY_SIZE(ethtool_stats_keys);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static void pasemi_mac_get_ethtool_stats(struct net_device *netdev,
+ struct ethtool_stats *stats, u64 *data)
+{
+ struct pasemi_mac *mac = netdev->priv;
+ int i;
+
+ data[0] = pasemi_read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if))
+ >> PAS_DMA_RXINT_RCMDSTA_DROPS_S;
+ for (i = 0; i < 32; i++)
+ data[1+i] = pasemi_read_mac_reg(mac->dma_if, PAS_MAC_RMON(i));
+}
+
+static void pasemi_mac_get_strings(struct net_device *netdev, u32 stringset,
+ u8 *data)
+{
+ memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
+}
+
+const struct ethtool_ops pasemi_mac_ethtool_ops = {
+ .get_settings = pasemi_mac_ethtool_get_settings,
+ .get_drvinfo = pasemi_mac_ethtool_get_drvinfo,
+ .get_msglevel = pasemi_mac_ethtool_get_msglevel,
+ .set_msglevel = pasemi_mac_ethtool_set_msglevel,
+ .get_link = ethtool_op_get_link,
+ .get_ringparam = pasemi_mac_ethtool_get_ringparam,
+ .get_strings = pasemi_mac_get_strings,
+ .get_sset_count = pasemi_mac_get_sset_count,
+ .get_ethtool_stats = pasemi_mac_get_ethtool_stats,
+};
+
return 0;
}
+static void gelic_net_get_wol(struct net_device *netdev,
+ struct ethtool_wolinfo *wol)
+{
+ if (0 <= ps3_compare_firmware_version(2, 2, 0))
+ wol->supported = WAKE_MAGIC;
+ else
+ wol->supported = 0;
+
+ wol->wolopts = ps3_sys_manager_get_wol() ? wol->supported : 0;
+ memset(&wol->sopass, 0, sizeof(wol->sopass));
+}
+static int gelic_net_set_wol(struct net_device *netdev,
+ struct ethtool_wolinfo *wol)
+{
+ int status;
+ struct gelic_card *card;
+ u64 v1, v2;
+
+ if (ps3_compare_firmware_version(2, 2, 0) < 0 ||
+ !capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ if (wol->wolopts & ~WAKE_MAGIC)
+ return -EINVAL;
+
+ card = netdev_card(netdev);
+ if (wol->wolopts & WAKE_MAGIC) {
+ status = lv1_net_control(bus_id(card), dev_id(card),
+ GELIC_LV1_SET_WOL,
+ GELIC_LV1_WOL_MAGIC_PACKET,
+ 0, GELIC_LV1_WOL_MP_ENABLE,
+ &v1, &v2);
+ if (status) {
+ pr_info("%s: enabling WOL failed %d\n", __func__,
+ status);
+ status = -EIO;
+ goto done;
+ }
+ status = lv1_net_control(bus_id(card), dev_id(card),
+ GELIC_LV1_SET_WOL,
+ GELIC_LV1_WOL_ADD_MATCH_ADDR,
+ 0, GELIC_LV1_WOL_MATCH_ALL,
+ &v1, &v2);
+ if (!status)
+ ps3_sys_manager_set_wol(1);
+ else {
+ pr_info("%s: enabling WOL filter failed %d\n",
+ __func__, status);
+ status = -EIO;
+ }
+ } else {
+ status = lv1_net_control(bus_id(card), dev_id(card),
+ GELIC_LV1_SET_WOL,
+ GELIC_LV1_WOL_MAGIC_PACKET,
+ 0, GELIC_LV1_WOL_MP_DISABLE,
+ &v1, &v2);
+ if (status) {
+ pr_info("%s: disabling WOL failed %d\n", __func__,
+ status);
+ status = -EIO;
+ goto done;
+ }
+ status = lv1_net_control(bus_id(card), dev_id(card),
+ GELIC_LV1_SET_WOL,
+ GELIC_LV1_WOL_DELETE_MATCH_ADDR,
+ 0, GELIC_LV1_WOL_MATCH_ALL,
+ &v1, &v2);
+ if (!status)
+ ps3_sys_manager_set_wol(0);
+ else {
+ pr_info("%s: removing WOL filter failed %d\n",
+ __func__, status);
+ status = -EIO;
+ }
+ }
+done:
+ return status;
+}
+
static struct ethtool_ops gelic_ether_ethtool_ops = {
.get_drvinfo = gelic_net_get_drvinfo,
.get_settings = gelic_ether_get_settings,
.set_tx_csum = ethtool_op_set_tx_csum,
.get_rx_csum = gelic_net_get_rx_csum,
.set_rx_csum = gelic_net_set_rx_csum,
+ .get_wol = gelic_net_get_wol,
+ .set_wol = gelic_net_set_wol,
};
/**
GELIC_LV1_GET_ETH_PORT_STATUS = 2,
GELIC_LV1_SET_NEGOTIATION_MODE = 3,
GELIC_LV1_GET_VLAN_ID = 4,
+ GELIC_LV1_SET_WOL = 5,
GELIC_LV1_GET_CHANNEL = 6,
GELIC_LV1_POST_WLAN_CMD = 9,
GELIC_LV1_GET_WLAN_CMD_RESULT = 10,
GELIC_LV1_GET_WLAN_EVENT = 11
};
+/* for GELIC_LV1_SET_WOL */
+enum gelic_lv1_wol_command {
+ GELIC_LV1_WOL_MAGIC_PACKET = 1,
+ GELIC_LV1_WOL_ADD_MATCH_ADDR = 6,
+ GELIC_LV1_WOL_DELETE_MATCH_ADDR = 7,
+};
+
+/* for GELIC_LV1_WOL_MAGIC_PACKET */
+enum gelic_lv1_wol_mp_arg {
+ GELIC_LV1_WOL_MP_DISABLE = 0,
+ GELIC_LV1_WOL_MP_ENABLE = 1,
+};
+
+/* for GELIC_LV1_WOL_{ADD,DELETE}_MATCH_ADDR */
+enum gelic_lv1_wol_match_arg {
+ GELIC_LV1_WOL_MATCH_INDIVIDUAL = 0,
+ GELIC_LV1_WOL_MATCH_ALL = 1,
+};
+
/* status returened from GET_ETH_PORT_STATUS */
enum gelic_lv1_ether_port_status {
GELIC_LV1_ETHER_LINK_UP = 0x0000000000000001L,
ugeth_vdbg("%s: IN", __FUNCTION__);
- prop = of_get_property(np, "device-id", NULL);
+ prop = of_get_property(np, "cell-index", NULL);
+ if (!prop) {
+ prop = of_get_property(np, "device-id", NULL);
+ if (!prop)
+ return -ENODEV;
+ }
+
ucc_num = *prop - 1;
if ((ucc_num < 0) || (ucc_num > 7))
return -ENODEV;
if ((res.start >= tempres.start) &&
(res.end <= tempres.end)) {
/* set this UCC to be the MII master */
- const u32 *id = of_get_property(tempnp, "device-id", NULL);
- if (id == NULL)
- goto bus_register_fail;
+ const u32 *id;
+
+ id = of_get_property(tempnp, "cell-index", NULL);
+ if (!id) {
+ id = of_get_property(tempnp, "device-id", NULL);
+ if (!id)
+ goto bus_register_fail;
+ }
ucc_set_qe_mux_mii_mng(*id - 1);
#include <linux/dma-mapping.h>
#include <linux/wait.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <asm/byteorder.h>
#undef DEBUG
{
if (!led->dev)
return;
- if (led->dev->suspend_in_progress)
- led_classdev_unregister_suspended(&led->led_dev);
- else
- led_classdev_unregister(&led->led_dev);
+ led_classdev_unregister(&led->led_dev);
b43_led_turn_off(led->dev, led->index, led->activelow);
led->dev = NULL;
}
return (sizeof(u16));
}
-static void b43_rng_exit(struct b43_wl *wl, bool suspended)
+static void b43_rng_exit(struct b43_wl *wl)
{
if (wl->rng_initialized)
- __hwrng_unregister(&wl->rng, suspended);
+ hwrng_unregister(&wl->rng);
}
static int b43_rng_init(struct b43_wl *wl)
if (!dev->suspend_in_progress) {
b43_leds_exit(dev);
- b43_rng_exit(dev->wl, false);
+ b43_rng_exit(dev->wl);
}
b43_dma_free(dev);
b43_pio_free(dev);
err = b43_wireless_core_start(wldev);
if (err) {
b43_leds_exit(wldev);
- b43_rng_exit(wldev->wl, true);
+ b43_rng_exit(wldev->wl);
b43_wireless_core_exit(wldev);
b43err(wl, "Resume failed at core start\n");
goto out;
config OF_DEVICE
def_bool y
depends on OF && (SPARC || PPC_OF)
+
+config OF_GPIO
+ def_bool y
+ depends on OF && PPC_OF && HAVE_GPIO_LIB
+ help
+ OpenFirmware GPIO accessors
+
+config OF_I2C
+ def_tristate I2C
+ depends on PPC_OF && I2C
+ help
+ OpenFirmware I2C accessors
obj-y = base.o
obj-$(CONFIG_OF_DEVICE) += device.o platform.o
+obj-$(CONFIG_OF_GPIO) += gpio.o
+obj-$(CONFIG_OF_I2C) += of_i2c.o
}
EXPORT_SYMBOL(of_device_is_compatible);
+/**
+ * of_device_is_available - check if a device is available for use
+ *
+ * @device: Node to check for availability
+ *
+ * Returns 1 if the status property is absent or set to "okay" or "ok",
+ * 0 otherwise
+ */
+int of_device_is_available(const struct device_node *device)
+{
+ const char *status;
+ int statlen;
+
+ status = of_get_property(device, "status", &statlen);
+ if (status == NULL)
+ return 1;
+
+ if (statlen > 0) {
+ if (!strcmp(status, "okay") || !strcmp(status, "ok"))
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(of_device_is_available);
+
/**
* of_get_parent - Get a node's parent if any
* @node: Node to get parent
--- /dev/null
+/*
+ * OF helpers for the GPIO API
+ *
+ * Copyright (c) 2007-2008 MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <asm/prom.h>
+
+/**
+ * of_get_gpio - Get a GPIO number from the device tree to use with GPIO API
+ * @np: device node to get GPIO from
+ * @index: index of the GPIO
+ *
+ * Returns GPIO number to use with Linux generic GPIO API, or one of the errno
+ * value on the error condition.
+ */
+int of_get_gpio(struct device_node *np, int index)
+{
+ int ret = -EINVAL;
+ struct device_node *gc;
+ struct of_gpio_chip *of_gc = NULL;
+ int size;
+ const u32 *gpios;
+ u32 nr_cells;
+ int i;
+ const void *gpio_spec;
+ const u32 *gpio_cells;
+ int gpio_index = 0;
+
+ gpios = of_get_property(np, "gpios", &size);
+ if (!gpios) {
+ ret = -ENOENT;
+ goto err0;
+ }
+ nr_cells = size / sizeof(u32);
+
+ for (i = 0; i < nr_cells; gpio_index++) {
+ const phandle *gpio_phandle;
+
+ gpio_phandle = gpios + i;
+ gpio_spec = gpio_phandle + 1;
+
+ /* one cell hole in the gpios = <>; */
+ if (!*gpio_phandle) {
+ if (gpio_index == index)
+ return -ENOENT;
+ i++;
+ continue;
+ }
+
+ gc = of_find_node_by_phandle(*gpio_phandle);
+ if (!gc) {
+ pr_debug("%s: could not find phandle for gpios\n",
+ np->full_name);
+ goto err0;
+ }
+
+ of_gc = gc->data;
+ if (!of_gc) {
+ pr_debug("%s: gpio controller %s isn't registered\n",
+ np->full_name, gc->full_name);
+ goto err1;
+ }
+
+ gpio_cells = of_get_property(gc, "#gpio-cells", &size);
+ if (!gpio_cells || size != sizeof(*gpio_cells) ||
+ *gpio_cells != of_gc->gpio_cells) {
+ pr_debug("%s: wrong #gpio-cells for %s\n",
+ np->full_name, gc->full_name);
+ goto err1;
+ }
+
+ /* Next phandle is at phandle cells + #gpio-cells */
+ i += sizeof(*gpio_phandle) / sizeof(u32) + *gpio_cells;
+ if (i >= nr_cells + 1) {
+ pr_debug("%s: insufficient gpio-spec length\n",
+ np->full_name);
+ goto err1;
+ }
+
+ if (gpio_index == index)
+ break;
+
+ of_gc = NULL;
+ of_node_put(gc);
+ }
+
+ if (!of_gc) {
+ ret = -ENOENT;
+ goto err0;
+ }
+
+ ret = of_gc->xlate(of_gc, np, gpio_spec);
+ if (ret < 0)
+ goto err1;
+
+ ret += of_gc->gc.base;
+err1:
+ of_node_put(gc);
+err0:
+ pr_debug("%s exited with status %d\n", __func__, ret);
+ return ret;
+}
+EXPORT_SYMBOL(of_get_gpio);
+
+/**
+ * of_gpio_simple_xlate - translate gpio_spec to the GPIO number
+ * @of_gc: pointer to the of_gpio_chip structure
+ * @np: device node of the GPIO chip
+ * @gpio_spec: gpio specifier as found in the device tree
+ *
+ * This is simple translation function, suitable for the most 1:1 mapped
+ * gpio chips. This function performs only one sanity check: whether gpio
+ * is less than ngpios (that is specified in the gpio_chip).
+ */
+int of_gpio_simple_xlate(struct of_gpio_chip *of_gc, struct device_node *np,
+ const void *gpio_spec)
+{
+ const u32 *gpio = gpio_spec;
+
+ if (*gpio > of_gc->gc.ngpio)
+ return -EINVAL;
+
+ return *gpio;
+}
+EXPORT_SYMBOL(of_gpio_simple_xlate);
+
+/* Should be sufficient for now, later we'll use dynamic bases. */
+#if defined(CONFIG_PPC32) || defined(CONFIG_SPARC32)
+#define GPIOS_PER_CHIP 32
+#else
+#define GPIOS_PER_CHIP 64
+#endif
+
+static int of_get_gpiochip_base(struct device_node *np)
+{
+ struct device_node *gc = NULL;
+ int gpiochip_base = 0;
+
+ while ((gc = of_find_all_nodes(gc))) {
+ if (!of_get_property(gc, "gpio-controller", NULL))
+ continue;
+
+ if (gc != np) {
+ gpiochip_base += GPIOS_PER_CHIP;
+ continue;
+ }
+
+ of_node_put(gc);
+
+ if (gpiochip_base >= ARCH_NR_GPIOS)
+ return -ENOSPC;
+
+ return gpiochip_base;
+ }
+
+ return -ENOENT;
+}
+
+/**
+ * of_mm_gpiochip_add - Add memory mapped GPIO chip (bank)
+ * @np: device node of the GPIO chip
+ * @mm_gc: pointer to the of_mm_gpio_chip allocated structure
+ *
+ * To use this function you should allocate and fill mm_gc with:
+ *
+ * 1) In the gpio_chip structure:
+ * - all the callbacks
+ *
+ * 2) In the of_gpio_chip structure:
+ * - gpio_cells
+ * - xlate callback (optional)
+ *
+ * 3) In the of_mm_gpio_chip structure:
+ * - save_regs callback (optional)
+ *
+ * If succeeded, this function will map bank's memory and will
+ * do all necessary work for you. Then you'll able to use .regs
+ * to manage GPIOs from the callbacks.
+ */
+int of_mm_gpiochip_add(struct device_node *np,
+ struct of_mm_gpio_chip *mm_gc)
+{
+ int ret = -ENOMEM;
+ struct of_gpio_chip *of_gc = &mm_gc->of_gc;
+ struct gpio_chip *gc = &of_gc->gc;
+
+ gc->label = kstrdup(np->full_name, GFP_KERNEL);
+ if (!gc->label)
+ goto err0;
+
+ mm_gc->regs = of_iomap(np, 0);
+ if (!mm_gc->regs)
+ goto err1;
+
+ gc->base = of_get_gpiochip_base(np);
+ if (gc->base < 0) {
+ ret = gc->base;
+ goto err1;
+ }
+
+ if (!of_gc->xlate)
+ of_gc->xlate = of_gpio_simple_xlate;
+
+ if (mm_gc->save_regs)
+ mm_gc->save_regs(mm_gc);
+
+ np->data = of_gc;
+
+ ret = gpiochip_add(gc);
+ if (ret)
+ goto err2;
+
+ /* We don't want to lose the node and its ->data */
+ of_node_get(np);
+
+ pr_debug("%s: registered as generic GPIO chip, base is %d\n",
+ np->full_name, gc->base);
+ return 0;
+err2:
+ np->data = NULL;
+ iounmap(mm_gc->regs);
+err1:
+ kfree(gc->label);
+err0:
+ pr_err("%s: GPIO chip registration failed with status %d\n",
+ np->full_name, ret);
+ return ret;
+}
+EXPORT_SYMBOL(of_mm_gpiochip_add);
--- /dev/null
+/*
+ * OF helpers for the I2C API
+ *
+ * Copyright (c) 2008 Jochen Friedrich <jochen@scram.de>
+ *
+ * Based on a previous patch from Jon Smirl <jonsmirl@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/i2c.h>
+#include <linux/of.h>
+
+struct i2c_driver_device {
+ char *of_device;
+ char *i2c_type;
+};
+
+static struct i2c_driver_device i2c_devices[] = {
+ { "dallas,ds1374", "rtc-ds1374" },
+};
+
+static int of_find_i2c_driver(struct device_node *node,
+ struct i2c_board_info *info)
+{
+ int i, cplen;
+ const char *compatible;
+ const char *p;
+
+ /* 1. search for exception list entry */
+ for (i = 0; i < ARRAY_SIZE(i2c_devices); i++) {
+ if (!of_device_is_compatible(node, i2c_devices[i].of_device))
+ continue;
+ if (strlcpy(info->type, i2c_devices[i].i2c_type,
+ I2C_NAME_SIZE) >= I2C_NAME_SIZE)
+ return -ENOMEM;
+
+ return 0;
+ }
+
+ compatible = of_get_property(node, "compatible", &cplen);
+ if (!compatible)
+ return -ENODEV;
+
+ /* 2. search for linux,<i2c-type> entry */
+ p = compatible;
+ while (cplen > 0) {
+ if (!strncmp(p, "linux,", 6)) {
+ p += 6;
+ if (strlcpy(info->type, p,
+ I2C_NAME_SIZE) >= I2C_NAME_SIZE)
+ return -ENOMEM;
+ return 0;
+ }
+
+ i = strlen(p) + 1;
+ p += i;
+ cplen -= i;
+ }
+
+ /* 3. take fist compatible entry and strip manufacturer */
+ p = strchr(compatible, ',');
+ if (!p)
+ return -ENODEV;
+ p++;
+ if (strlcpy(info->type, p, I2C_NAME_SIZE) >= I2C_NAME_SIZE)
+ return -ENOMEM;
+ return 0;
+}
+
+void of_register_i2c_devices(struct i2c_adapter *adap,
+ struct device_node *adap_node)
+{
+ void *result;
+ struct device_node *node;
+
+ for_each_child_of_node(adap_node, node) {
+ struct i2c_board_info info = {};
+ const u32 *addr;
+ int len;
+
+ addr = of_get_property(node, "reg", &len);
+ if (!addr || len < sizeof(int) || *addr > (1 << 10) - 1) {
+ printk(KERN_ERR
+ "of-i2c: invalid i2c device entry\n");
+ continue;
+ }
+
+ info.irq = irq_of_parse_and_map(node, 0);
+ if (info.irq == NO_IRQ)
+ info.irq = -1;
+
+ if (of_find_i2c_driver(node, &info) < 0) {
+ irq_dispose_mapping(info.irq);
+ continue;
+ }
+
+ info.addr = *addr;
+
+ request_module(info.type);
+
+ result = i2c_new_device(adap, &info);
+ if (result == NULL) {
+ printk(KERN_ERR
+ "of-i2c: Failed to load driver for %s\n",
+ info.type);
+ irq_dispose_mapping(info.irq);
+ continue;
+ }
+ }
+}
+EXPORT_SYMBOL(of_register_i2c_devices);
list_for_each_safe(ln, tmp_ln, &bus->devices) {
struct pci_dev *dev = pci_dev_b(ln);
- list_del(&dev->global_list);
list_del(&dev->bus_list);
}
config PARPORT_PC
tristate "PC-style hardware"
depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \
- (!M68K || ISA) && !MN10300
+ (!M68K || ISA) && !MN10300 && !AVR32
---help---
You should say Y here if you have a PC-style parallel port. All
IBM PC compatible computers and some Alphas have PC-style
+#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/sched.h>
PCI_USER_WRITE_CONFIG(word, u16)
PCI_USER_WRITE_CONFIG(dword, u32)
+/* VPD access through PCI 2.2+ VPD capability */
+
+#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
+
+struct pci_vpd_pci22 {
+ struct pci_vpd base;
+ spinlock_t lock; /* controls access to hardware and the flags */
+ u8 cap;
+ bool busy;
+ bool flag; /* value of F bit to wait for */
+};
+
+/* Wait for last operation to complete */
+static int pci_vpd_pci22_wait(struct pci_dev *dev)
+{
+ struct pci_vpd_pci22 *vpd =
+ container_of(dev->vpd, struct pci_vpd_pci22, base);
+ u16 flag, status;
+ int wait;
+ int ret;
+
+ if (!vpd->busy)
+ return 0;
+
+ flag = vpd->flag ? PCI_VPD_ADDR_F : 0;
+ wait = vpd->flag ? 10 : 1000; /* read: 100 us; write: 10 ms */
+ for (;;) {
+ ret = pci_user_read_config_word(dev,
+ vpd->cap + PCI_VPD_ADDR,
+ &status);
+ if (ret < 0)
+ return ret;
+ if ((status & PCI_VPD_ADDR_F) == flag) {
+ vpd->busy = false;
+ return 0;
+ }
+ if (wait-- == 0)
+ return -ETIMEDOUT;
+ udelay(10);
+ }
+}
+
+static int pci_vpd_pci22_read(struct pci_dev *dev, int pos, int size,
+ char *buf)
+{
+ struct pci_vpd_pci22 *vpd =
+ container_of(dev->vpd, struct pci_vpd_pci22, base);
+ u32 val;
+ int ret;
+ int begin, end, i;
+
+ if (pos < 0 || pos > PCI_VPD_PCI22_SIZE ||
+ size > PCI_VPD_PCI22_SIZE - pos)
+ return -EINVAL;
+ if (size == 0)
+ return 0;
+
+ spin_lock_irq(&vpd->lock);
+ ret = pci_vpd_pci22_wait(dev);
+ if (ret < 0)
+ goto out;
+ ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
+ pos & ~3);
+ if (ret < 0)
+ goto out;
+ vpd->busy = true;
+ vpd->flag = 1;
+ ret = pci_vpd_pci22_wait(dev);
+ if (ret < 0)
+ goto out;
+ ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA,
+ &val);
+out:
+ spin_unlock_irq(&vpd->lock);
+ if (ret < 0)
+ return ret;
+
+ /* Convert to bytes */
+ begin = pos & 3;
+ end = min(4, begin + size);
+ for (i = 0; i < end; ++i) {
+ if (i >= begin)
+ *buf++ = val;
+ val >>= 8;
+ }
+ return end - begin;
+}
+
+static int pci_vpd_pci22_write(struct pci_dev *dev, int pos, int size,
+ const char *buf)
+{
+ struct pci_vpd_pci22 *vpd =
+ container_of(dev->vpd, struct pci_vpd_pci22, base);
+ u32 val;
+ int ret;
+
+ if (pos < 0 || pos > PCI_VPD_PCI22_SIZE || pos & 3 ||
+ size > PCI_VPD_PCI22_SIZE - pos || size < 4)
+ return -EINVAL;
+
+ val = (u8) *buf++;
+ val |= ((u8) *buf++) << 8;
+ val |= ((u8) *buf++) << 16;
+ val |= ((u32)(u8) *buf++) << 24;
+
+ spin_lock_irq(&vpd->lock);
+ ret = pci_vpd_pci22_wait(dev);
+ if (ret < 0)
+ goto out;
+ ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA,
+ val);
+ if (ret < 0)
+ goto out;
+ ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
+ pos | PCI_VPD_ADDR_F);
+ if (ret < 0)
+ goto out;
+ vpd->busy = true;
+ vpd->flag = 0;
+ ret = pci_vpd_pci22_wait(dev);
+out:
+ spin_unlock_irq(&vpd->lock);
+ if (ret < 0)
+ return ret;
+
+ return 4;
+}
+
+static int pci_vpd_pci22_get_size(struct pci_dev *dev)
+{
+ return PCI_VPD_PCI22_SIZE;
+}
+
+static void pci_vpd_pci22_release(struct pci_dev *dev)
+{
+ kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
+}
+
+static struct pci_vpd_ops pci_vpd_pci22_ops = {
+ .read = pci_vpd_pci22_read,
+ .write = pci_vpd_pci22_write,
+ .get_size = pci_vpd_pci22_get_size,
+ .release = pci_vpd_pci22_release,
+};
+
+int pci_vpd_pci22_init(struct pci_dev *dev)
+{
+ struct pci_vpd_pci22 *vpd;
+ u8 cap;
+
+ cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
+ if (!cap)
+ return -ENODEV;
+ vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
+ if (!vpd)
+ return -ENOMEM;
+
+ vpd->base.ops = &pci_vpd_pci22_ops;
+ spin_lock_init(&vpd->lock);
+ vpd->cap = cap;
+ vpd->busy = false;
+ dev->vpd = &vpd->base;
+ return 0;
+}
+
/**
* pci_block_user_cfg_access - Block userspace PCI config reads/writes
* @dev: pci device struct
if (retval)
return retval;
- down_write(&pci_bus_sem);
- list_add_tail(&dev->global_list, &pci_devices);
- up_write(&pci_bus_sem);
-
+ dev->is_added = 1;
pci_proc_attach_device(dev);
pci_create_sysfs_dev_files(dev);
return 0;
int retval;
list_for_each_entry(dev, &bus->devices, bus_list) {
- /*
- * Skip already-present devices (which are on the
- * global device list.)
- */
- if (!list_empty(&dev->global_list))
+ /* Skip already-added devices */
+ if (dev->is_added)
continue;
retval = pci_bus_add_device(dev);
if (retval)
}
list_for_each_entry(dev, &bus->devices, bus_list) {
-
- BUG_ON(list_empty(&dev->global_list));
+ BUG_ON(!dev->is_added);
/*
* If there is an unattached subordinate bus, attach
config HOTPLUG_PCI_IBM
tristate "IBM PCI Hotplug driver"
- depends on X86_IO_APIC && X86 && PCI_BIOS && PCI_LEGACY
+ depends on X86_IO_APIC && X86 && PCI_BIOS
help
Say Y here if you have a motherboard with a IBM PCI Hotplug
controller.
config HOTPLUG_PCI_CPCI_GENERIC
tristate "Generic port I/O CompactPCI Hotplug driver"
- depends on HOTPLUG_PCI_CPCI && X86 && PCI_LEGACY
+ depends on HOTPLUG_PCI_CPCI && X86
help
Say Y here if you have a CompactPCI system card that exposes the #ENUM
hotswap signal as a bit in a system register that can be read through
#define MY_NAME "acpi_pcihp"
-#define dbg(fmt, arg...) do { if (debug_acpi) printk(KERN_DEBUG "%s: %s: " fmt , MY_NAME , __FUNCTION__ , ## arg); } while (0)
+#define dbg(fmt, arg...) do { if (debug_acpi) printk(KERN_DEBUG "%s: %s: " fmt , MY_NAME , __func__ , ## arg); } while (0)
#define err(format, arg...) printk(KERN_ERR "%s: " format , MY_NAME , ## arg)
#define info(format, arg...) printk(KERN_INFO "%s: " format , MY_NAME , ## arg)
#define warn(format, arg...) printk(KERN_WARNING "%s: " format , MY_NAME , ## arg)
default:
printk(KERN_WARNING
"%s: Type 0 Revision %d record not supported\n",
- __FUNCTION__, revision);
+ __func__, revision);
return AE_ERROR;
}
return AE_OK;
default:
printk(KERN_WARNING
"%s: Type 1 Revision %d record not supported\n",
- __FUNCTION__, revision);
+ __func__, revision);
return AE_ERROR;
}
return AE_OK;
default:
printk(KERN_WARNING
"%s: Type 2 Revision %d record not supported\n",
- __FUNCTION__, revision);
+ __func__, revision);
return AE_ERROR;
}
return AE_OK;
break;
default:
printk(KERN_ERR "%s: Type %d record not supported\n",
- __FUNCTION__, type);
+ __func__, type);
status = AE_ERROR;
goto exit;
}
ret_buf.pointer = kmalloc (ret_buf.length, GFP_KERNEL);
if (!ret_buf.pointer) {
printk(KERN_ERR "%s:%s alloc for _HPP fail\n",
- __FUNCTION__, (char *)string.pointer);
+ __func__, (char *)string.pointer);
kfree(string.pointer);
return AE_NO_MEMORY;
}
break;
default:
if (ACPI_FAILURE(status)) {
- pr_debug("%s:%s _HPP fail=0x%x\n", __FUNCTION__,
+ pr_debug("%s:%s _HPP fail=0x%x\n", __func__,
(char *)string.pointer, status);
kfree(string.pointer);
return status;
ext_obj = (union acpi_object *) ret_buf.pointer;
if (ext_obj->type != ACPI_TYPE_PACKAGE) {
- printk(KERN_ERR "%s:%s _HPP obj not a package\n", __FUNCTION__,
+ printk(KERN_ERR "%s:%s _HPP obj not a package\n", __func__,
(char *)string.pointer);
status = AE_ERROR;
goto free_and_return;
break;
default:
printk(KERN_ERR "%s:%s _HPP obj type incorrect\n",
- __FUNCTION__, (char *)string.pointer);
+ __func__, (char *)string.pointer);
status = AE_ERROR;
goto free_and_return;
}
if (ACPI_FAILURE(status))
if (status != AE_NOT_FOUND)
printk(KERN_ERR "%s:%s OSHP fails=0x%x\n",
- __FUNCTION__, (char *)string.pointer, status);
+ __func__, (char *)string.pointer, status);
else
dbg("%s:%s OSHP not found\n",
- __FUNCTION__, (char *)string.pointer);
+ __func__, (char *)string.pointer);
else
- pr_debug("%s:%s OSHP passes\n", __FUNCTION__,
+ pr_debug("%s:%s OSHP passes\n", __func__,
(char *)string.pointer);
kfree(string.pointer);
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
/* enable the specified slot */
return acpiphp_enable_slot(slot->acpi_slot);
struct slot *slot = hotplug_slot->private;
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
/* disable the specified slot */
retval = acpiphp_disable_slot(slot->acpi_slot);
{
int retval = -ENODEV;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
if (attention_info && try_module_get(attention_info->owner)) {
retval = attention_info->set_attn(hotplug_slot, status);
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = acpiphp_get_power_status(slot->acpi_slot);
{
int retval = -EINVAL;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
if (attention_info && try_module_get(attention_info->owner)) {
retval = attention_info->get_attn(hotplug_slot, value);
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = acpiphp_get_latch_status(slot->acpi_slot);
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = acpiphp_get_adapter_status(slot->acpi_slot);
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = acpiphp_get_address(slot->acpi_slot);
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
kfree(slot->hotplug_slot);
kfree(slot);
/* use default numbers */
printk(KERN_WARNING
"%s: Could not get hotplug parameters. Use defaults\n",
- __FUNCTION__);
+ __func__);
bridge->hpp.t0 = &bridge->hpp.type0_data;
bridge->hpp.t0->revision = 0;
bridge->hpp.t0->cache_line_size = 0x10;
status = acpi_evaluate_integer(handle, "_ADR", NULL, &tmp);
if (ACPI_FAILURE(status)) {
- dbg("%s: _ADR evaluation failure\n", __FUNCTION__);
+ dbg("%s: _ADR evaluation failure\n", __func__);
return AE_OK;
}
if (ACPI_SUCCESS(status)) {
status = acpi_evaluate_integer(handle, "_STA", NULL, &tmp);
if (ACPI_FAILURE(status)) {
- dbg("%s: _STA evaluation failure\n", __FUNCTION__);
+ dbg("%s: _STA evaluation failure\n", __func__);
return 0;
}
if ((tmp & ACPI_STA_FUNCTIONING) == 0)
func = list_entry(l, struct acpiphp_func, sibling);
if (func->flags & FUNC_HAS_PS0) {
- dbg("%s: executing _PS0\n", __FUNCTION__);
+ dbg("%s: executing _PS0\n", __func__);
status = acpi_evaluate_object(func->handle, "_PS0", NULL, NULL);
if (ACPI_FAILURE(status)) {
- warn("%s: _PS0 failed\n", __FUNCTION__);
+ warn("%s: _PS0 failed\n", __func__);
retval = -1;
goto err_exit;
} else
if (func->flags & FUNC_HAS_PS3) {
status = acpi_evaluate_object(func->handle, "_PS3", NULL, NULL);
if (ACPI_FAILURE(status)) {
- warn("%s: _PS3 failed\n", __FUNCTION__);
+ warn("%s: _PS3 failed\n", __func__);
retval = -1;
goto err_exit;
} else
status = acpi_evaluate_object(func->handle, "_EJ0", &arg_list, NULL);
if (ACPI_FAILURE(status)) {
- warn("%s: _EJ0 failed\n", __FUNCTION__);
+ warn("%s: _EJ0 failed\n", __func__);
return -1;
} else
break;
}
}
- dbg("%s: %d enabled, %d disabled\n", __FUNCTION__, enabled, disabled);
+ dbg("%s: %d enabled, %d disabled\n", __func__, enabled, disabled);
err_exit:
return retval;
if (bridge) {
acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
dbg("%s: re-enumerating slots under %s\n",
- __FUNCTION__, objname);
+ __func__, objname);
acpiphp_check_bridge(bridge);
}
return AE_OK ;
switch (type) {
case ACPI_NOTIFY_BUS_CHECK:
/* bus re-enumerate */
- dbg("%s: Bus check notify on %s\n", __FUNCTION__, objname);
+ dbg("%s: Bus check notify on %s\n", __func__, objname);
if (bridge) {
dbg("%s: re-enumerating slots under %s\n",
- __FUNCTION__, objname);
+ __func__, objname);
acpiphp_check_bridge(bridge);
}
if (num_sub_bridges)
case ACPI_NOTIFY_DEVICE_CHECK:
/* device check */
- dbg("%s: Device check notify on %s\n", __FUNCTION__, objname);
+ dbg("%s: Device check notify on %s\n", __func__, objname);
acpiphp_check_bridge(bridge);
break;
case ACPI_NOTIFY_DEVICE_WAKE:
/* wake event */
- dbg("%s: Device wake notify on %s\n", __FUNCTION__, objname);
+ dbg("%s: Device wake notify on %s\n", __func__, objname);
break;
case ACPI_NOTIFY_EJECT_REQUEST:
/* request device eject */
- dbg("%s: Device eject notify on %s\n", __FUNCTION__, objname);
+ dbg("%s: Device eject notify on %s\n", __func__, objname);
if ((bridge->type != BRIDGE_TYPE_HOST) &&
(bridge->flags & BRIDGE_HAS_EJ0)) {
struct acpiphp_slot *slot;
switch (type) {
case ACPI_NOTIFY_BUS_CHECK:
/* bus re-enumerate */
- dbg("%s: Bus check notify on %s\n", __FUNCTION__, objname);
+ dbg("%s: Bus check notify on %s\n", __func__, objname);
acpiphp_enable_slot(func->slot);
break;
case ACPI_NOTIFY_DEVICE_CHECK:
/* device check : re-enumerate from parent bus */
- dbg("%s: Device check notify on %s\n", __FUNCTION__, objname);
+ dbg("%s: Device check notify on %s\n", __func__, objname);
acpiphp_check_bridge(func->slot->bridge);
break;
case ACPI_NOTIFY_DEVICE_WAKE:
/* wake event */
- dbg("%s: Device wake notify on %s\n", __FUNCTION__, objname);
+ dbg("%s: Device wake notify on %s\n", __func__, objname);
break;
case ACPI_NOTIFY_EJECT_REQUEST:
/* request device eject */
- dbg("%s: Device eject notify on %s\n", __FUNCTION__, objname);
+ dbg("%s: Device eject notify on %s\n", __func__, objname);
if (!(acpiphp_disable_slot(func->slot)))
acpiphp_eject_slot(func->slot);
break;
if (retval)
power_off_slot(slot);
} else {
- dbg("%s: Slot status is not ACPI_STA_ALL\n", __FUNCTION__);
+ dbg("%s: Slot status is not ACPI_STA_ALL\n", __func__);
power_off_slot(slot);
}
ibm_slot = ibm_slot_from_id(hpslot_to_sun(slot));
- dbg("%s: set slot %d (%d) attention status to %d\n", __FUNCTION__,
+ dbg("%s: set slot %d (%d) attention status to %d\n", __func__,
ibm_slot->slot.slot_num, ibm_slot->slot.slot_id,
(status ? 1 : 0));
else
*status = 0;
- dbg("%s: get slot %d (%d) attention status is %d\n", __FUNCTION__,
+ dbg("%s: get slot %d (%d) attention status is %d\n", __func__,
ibm_slot->slot.slot_num, ibm_slot->slot.slot_id,
*status);
u8 subevent = event & 0xf0;
struct notification *note = context;
- dbg("%s: Received notification %02x\n", __FUNCTION__, event);
+ dbg("%s: Received notification %02x\n", __func__, event);
if (subevent == 0x80) {
- dbg("%s: generationg bus event\n", __FUNCTION__);
+ dbg("%s: generationg bus event\n", __func__);
acpi_bus_generate_proc_event(note->device, note->event, detail);
acpi_bus_generate_netlink_event(note->device->pnp.device_class,
note->device->dev.bus_id,
status = acpi_evaluate_object(ibm_acpi_handle, "APCI", NULL, &buffer);
if (ACPI_FAILURE(status)) {
- err("%s: APCI evaluation failed\n", __FUNCTION__);
+ err("%s: APCI evaluation failed\n", __func__);
return -ENODEV;
}
if (!(package) ||
(package->type != ACPI_TYPE_PACKAGE) ||
!(package->package.elements)) {
- err("%s: Invalid APCI object\n", __FUNCTION__);
+ err("%s: Invalid APCI object\n", __func__);
goto read_table_done;
}
for(size = 0, i = 0; i < package->package.count; i++) {
if (package->package.elements[i].type != ACPI_TYPE_BUFFER) {
- err("%s: Invalid APCI element %d\n", __FUNCTION__, i);
+ err("%s: Invalid APCI element %d\n", __func__, i);
goto read_table_done;
}
size += package->package.elements[i].buffer.length;
lbuf = kzalloc(size, GFP_KERNEL);
dbg("%s: element count: %i, ASL table size: %i, &table = 0x%p\n",
- __FUNCTION__, package->package.count, size, lbuf);
+ __func__, package->package.count, size, lbuf);
if (lbuf) {
*bufp = lbuf;
int bytes_read = -EINVAL;
char *table = NULL;
- dbg("%s: pos = %d, size = %zd\n", __FUNCTION__, (int)pos, size);
+ dbg("%s: pos = %d, size = %zd\n", __func__, (int)pos, size);
if (pos == 0) {
bytes_read = ibm_get_table_from_acpi(&table);
status = acpi_get_object_info(handle, &info_buffer);
if (ACPI_FAILURE(status)) {
err("%s: Failed to get device information status=0x%x\n",
- __FUNCTION__, status);
+ __func__, status);
return retval;
}
info = info_buffer.pointer;
struct acpi_device *device;
struct kobject *sysdir = &pci_hotplug_slots_kset->kobj;
- dbg("%s\n", __FUNCTION__);
+ dbg("%s\n", __func__);
if (acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
ACPI_UINT32_MAX, ibm_find_acpi_device,
&ibm_acpi_handle, NULL) != FOUND_APCI) {
- err("%s: acpi_walk_namespace failed\n", __FUNCTION__);
+ err("%s: acpi_walk_namespace failed\n", __func__);
retval = -ENODEV;
goto init_return;
}
- dbg("%s: found IBM aPCI device\n", __FUNCTION__);
+ dbg("%s: found IBM aPCI device\n", __func__);
if (acpi_bus_get_device(ibm_acpi_handle, &device)) {
- err("%s: acpi_bus_get_device failed\n", __FUNCTION__);
+ err("%s: acpi_bus_get_device failed\n", __func__);
retval = -ENODEV;
goto init_return;
}
&ibm_note);
if (ACPI_FAILURE(status)) {
err("%s: Failed to register notification handler\n",
- __FUNCTION__);
+ __func__);
retval = -EBUSY;
goto init_cleanup;
}
acpi_status status;
struct kobject *sysdir = &pci_hotplug_slots_kset->kobj;
- dbg("%s\n", __FUNCTION__);
+ dbg("%s\n", __func__);
if (acpiphp_unregister_attention(&ibm_attention_info))
- err("%s: attention info deregistration failed", __FUNCTION__);
+ err("%s: attention info deregistration failed", __func__);
status = acpi_remove_notify_handler(
ibm_acpi_handle,
ACPI_DEVICE_NOTIFY,
ibm_handle_events);
if (ACPI_FAILURE(status))
- err("%s: Notification handler removal failed\n", __FUNCTION__);
+ err("%s: Notification handler removal failed\n", __func__);
/* remove the /sys entries */
sysfs_remove_bin_file(sysdir, &ibm_apci_table_attr);
}
struct slot *slot = hotplug_slot->private;
int retval = 0;
- dbg("%s - physical_slot = %s", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s", __func__, hotplug_slot->name);
if (controller->ops->set_power)
retval = controller->ops->set_power(slot, 1);
struct slot *slot = hotplug_slot->private;
int retval = 0;
- dbg("%s - physical_slot = %s", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s", __func__, hotplug_slot->name);
down_write(&list_rwsem);
/* Unconfigure device */
dbg("%s - unconfiguring slot %s",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
if ((retval = cpci_unconfigure_slot(slot))) {
err("%s - could not unconfigure slot %s",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
goto disable_error;
}
dbg("%s - finished unconfiguring slot %s",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
/* Clear EXT (by setting it) */
if (cpci_clear_ext(slot)) {
err("%s - could not clear EXT for slot %s",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
retval = -ENODEV;
goto disable_error;
}
struct slot *slot;
struct pci_dev* dev;
- dbg("%s - enter", __FUNCTION__);
+ dbg("%s - enter", __func__);
down_read(&list_rwsem);
if (!slots) {
up_read(&list_rwsem);
}
list_for_each_entry(slot, &slot_list, slot_list) {
dbg("%s - looking at slot %s",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
if (clear_ins && cpci_check_and_clear_ins(slot))
dbg("%s - cleared INS for slot %s",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
dev = pci_get_slot(slot->bus, PCI_DEVFN(slot->number, 0));
if (dev) {
if (update_adapter_status(slot->hotplug_slot, 1))
}
}
up_read(&list_rwsem);
- dbg("%s - exit", __FUNCTION__);
+ dbg("%s - exit", __func__);
return 0;
}
extracted = inserted = 0;
list_for_each_entry(slot, &slot_list, slot_list) {
dbg("%s - looking at slot %s",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
if (cpci_check_and_clear_ins(slot)) {
/*
* Some broken hardware (e.g. PLX 9054AB) asserts
/* Process insertion */
dbg("%s - slot %s inserted",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
/* GSM, debug */
hs_csr = cpci_get_hs_csr(slot);
dbg("%s - slot %s HS_CSR (1) = %04x",
- __FUNCTION__, slot->hotplug_slot->name, hs_csr);
+ __func__, slot->hotplug_slot->name, hs_csr);
/* Configure device */
dbg("%s - configuring slot %s",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
if (cpci_configure_slot(slot)) {
err("%s - could not configure slot %s",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
continue;
}
dbg("%s - finished configuring slot %s",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
/* GSM, debug */
hs_csr = cpci_get_hs_csr(slot);
dbg("%s - slot %s HS_CSR (2) = %04x",
- __FUNCTION__, slot->hotplug_slot->name, hs_csr);
+ __func__, slot->hotplug_slot->name, hs_csr);
if (update_latch_status(slot->hotplug_slot, 1))
warn("failure to update latch file");
/* GSM, debug */
hs_csr = cpci_get_hs_csr(slot);
dbg("%s - slot %s HS_CSR (3) = %04x",
- __FUNCTION__, slot->hotplug_slot->name, hs_csr);
+ __func__, slot->hotplug_slot->name, hs_csr);
inserted++;
} else if (cpci_check_ext(slot)) {
/* Process extraction request */
dbg("%s - slot %s extracted",
- __FUNCTION__, slot->hotplug_slot->name);
+ __func__, slot->hotplug_slot->name);
/* GSM, debug */
hs_csr = cpci_get_hs_csr(slot);
dbg("%s - slot %s HS_CSR = %04x",
- __FUNCTION__, slot->hotplug_slot->name, hs_csr);
+ __func__, slot->hotplug_slot->name, hs_csr);
if (!slot->extracting) {
if (update_latch_status(slot->hotplug_slot, 0)) {
{
int rc;
- dbg("%s - event thread started", __FUNCTION__);
+ dbg("%s - event thread started", __func__);
while (1) {
dbg("event thread sleeping");
set_current_state(TASK_INTERRUPTIBLE);
/* Give userspace a chance to handle extraction */
msleep(500);
} else if (rc < 0) {
- dbg("%s - error checking slots", __FUNCTION__);
+ dbg("%s - error checking slots", __func__);
thread_finished = 1;
goto out;
}
break;
/* Re-enable ENUM# interrupt */
- dbg("%s - re-enabling irq", __FUNCTION__);
+ dbg("%s - re-enabling irq", __func__);
controller->ops->enable_irq();
}
out:
/* Give userspace a chance to handle extraction */
msleep(500);
} else if (rc < 0) {
- dbg("%s - error checking slots", __FUNCTION__);
+ dbg("%s - error checking slots", __func__);
thread_finished = 1;
goto out;
}
status = -ENODEV;
}
dbg("%s - acquired controller irq %d",
- __FUNCTION__, new_controller->irq);
+ __func__, new_controller->irq);
}
if (!status)
controller = new_controller;
static int first = 1;
int status;
- dbg("%s - enter", __FUNCTION__);
+ dbg("%s - enter", __func__);
if (!controller)
return -ENODEV;
status = cpci_start_thread();
if (status)
return status;
- dbg("%s - thread started", __FUNCTION__);
+ dbg("%s - thread started", __func__);
if (controller->irq) {
/* Start enum interrupt processing */
- dbg("%s - enabling irq", __FUNCTION__);
+ dbg("%s - enabling irq", __func__);
controller->ops->enable_irq();
}
- dbg("%s - exit", __FUNCTION__);
+ dbg("%s - exit", __func__);
return 0;
}
return -ENODEV;
if (controller->irq) {
/* Stop enum interrupt processing */
- dbg("%s - disabling irq", __FUNCTION__);
+ dbg("%s - disabling irq", __func__);
controller->ops->disable_irq();
}
cpci_stop_thread();
struct pci_bus *parent;
int fn;
- dbg("%s - enter", __FUNCTION__);
+ dbg("%s - enter", __func__);
if (slot->dev == NULL) {
dbg("pci_dev null, finding %02x:%02x:%x",
* we will only call this case when lookup fails.
*/
n = pci_scan_slot(slot->bus, slot->devfn);
- dbg("%s: pci_scan_slot returned %d", __FUNCTION__, n);
+ dbg("%s: pci_scan_slot returned %d", __func__, n);
slot->dev = pci_get_slot(slot->bus, slot->devfn);
if (slot->dev == NULL) {
err("Could not find PCI device for slot %02x", slot->number);
pci_bus_add_devices(parent);
pci_enable_bridges(parent);
- dbg("%s - exit", __FUNCTION__);
+ dbg("%s - exit", __func__);
return 0;
}
int i;
struct pci_dev *dev;
- dbg("%s - enter", __FUNCTION__);
+ dbg("%s - enter", __func__);
if (!slot->dev) {
err("No device for slot %02x\n", slot->number);
return -ENODEV;
pci_dev_put(slot->dev);
slot->dev = NULL;
- dbg("%s - exit", __FUNCTION__);
+ dbg("%s - exit", __func__);
return 0;
}
if(!r)
return -EBUSY;
- dev = pci_find_slot(bridge_busnr, PCI_DEVFN(bridge_slot, 0));
+ bus = pci_find_bus(0, bridge_busnr);
+ if (!bus) {
+ err("Invalid bus number %d", bridge_busnr);
+ return -EINVAL;
+ }
+ dev = pci_get_slot(bus, PCI_DEVFN(bridge_slot, 0));
if(!dev || dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
err("Invalid bridge device %s", bridge);
return -EINVAL;
}
bus = dev->subordinate;
+ pci_dev_put(dev);
memset(&generic_hpc, 0, sizeof (struct cpci_hp_controller));
generic_hpc_ops.query_enum = query_enum;
hp_slot = slot->device - ctrl->slot_device_offset;
dbg("%s: slot->device = %d, ctrl->slot_device_offset = %d \n",
- __FUNCTION__, slot->device, ctrl->slot_device_offset);
+ __func__, slot->device, ctrl->slot_device_offset);
status = (readl(ctrl->hpc_reg + INT_INPUT_CLEAR) & (0x01L << hp_slot));
DECLARE_WAITQUEUE(wait, current);
int retval = 0;
- dbg("%s - start\n", __FUNCTION__);
+ dbg("%s - start\n", __func__);
add_wait_queue(&ctrl->queue, &wait);
/* Sleep for up to 1 second to wait for the LED to change. */
msleep_interruptible(1000);
if (signal_pending(current))
retval = -EINTR;
- dbg("%s - end\n", __FUNCTION__);
+ dbg("%s - end\n", __func__);
return retval;
}
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
kfree(slot->hotplug_slot->info);
kfree(slot->hotplug_slot->name);
void __iomem *slot_entry= NULL;
int result = -ENOMEM;
- dbg("%s\n", __FUNCTION__);
+ dbg("%s\n", __func__);
tempdword = readl(ctrl->hpc_reg + INT_INPUT_CLEAR);
u8 tbus, tdevice, tslot, bridgeSlot;
- dbg("%s: %p, %d, %d, %p\n", __FUNCTION__, bus, bus_num, dev_num, slot);
+ dbg("%s: %p, %d, %d, %p\n", __func__, bus, bus_num, dev_num, slot);
bridgeSlot = 0xFF;
u8 device;
u8 function;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
if (cpqhp_get_bus_dev(ctrl, &bus, &devfn, slot->number) == -1)
return -ENODEV;
u8 device;
u8 function;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
if (cpqhp_get_bus_dev(ctrl, &bus, &devfn, slot->number) == -1)
return -ENODEV;
u8 device;
u8 function;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
if (cpqhp_get_bus_dev(ctrl, &bus, &devfn, slot->number) == -1)
return -ENODEV;
if (!slot_func)
return -ENODEV;
- dbg("In %s, slot_func = %p, ctrl = %p\n", __FUNCTION__, slot_func, ctrl);
+ dbg("In %s, slot_func = %p, ctrl = %p\n", __func__, slot_func, ctrl);
return cpqhp_process_SS(ctrl, slot_func);
}
struct slot *slot = hotplug_slot->private;
struct controller *ctrl = slot->ctrl;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
return cpqhp_hardware_test(ctrl, value);
}
struct slot *slot = hotplug_slot->private;
struct controller *ctrl = slot->ctrl;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = get_slot_enabled(ctrl, slot);
return 0;
struct slot *slot = hotplug_slot->private;
struct controller *ctrl = slot->ctrl;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = cpq_get_attention_status(ctrl, slot);
return 0;
struct slot *slot = hotplug_slot->private;
struct controller *ctrl = slot->ctrl;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = cpq_get_latch_status(ctrl, slot);
struct slot *slot = hotplug_slot->private;
struct controller *ctrl = slot->ctrl;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = get_presence_status(ctrl, slot);
struct slot *slot = hotplug_slot->private;
struct controller *ctrl = slot->ctrl;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = ctrl->speed_capability;
struct slot *slot = hotplug_slot->private;
struct controller *ctrl = slot->ctrl;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = ctrl->speed;
// TODO: This code can be made to support non-Compaq or Intel subsystem IDs
rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vid);
if (rc) {
- err("%s : pci_read_config_word failed\n", __FUNCTION__);
+ err("%s : pci_read_config_word failed\n", __func__);
goto err_disable_device;
}
dbg("Subsystem Vendor ID: %x\n", subsystem_vid);
ctrl = kzalloc(sizeof(struct controller), GFP_KERNEL);
if (!ctrl) {
- err("%s : out of memory\n", __FUNCTION__);
+ err("%s : out of memory\n", __func__);
rc = -ENOMEM;
goto err_disable_device;
}
rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsystem_deviceid);
if (rc) {
- err("%s : pci_read_config_word failed\n", __FUNCTION__);
+ err("%s : pci_read_config_word failed\n", __func__);
goto err_free_ctrl;
}
rc = cpqhp_save_config(ctrl, ctrl->bus, readb(ctrl->hpc_reg + SLOT_MASK));
if (rc) {
err("%s: unable to save PCI configuration data, error %d\n",
- __FUNCTION__, rc);
+ __func__, rc);
goto err_iounmap;
}
if (rc) {
err(msg_initialization_err, 6);
err("%s: unable to save PCI configuration data, error %d\n",
- __FUNCTION__, rc);
+ __func__, rc);
goto err_iounmap;
}
for (node = *head; node; node = node->next) {
dbg("%s: req_size =%x node=%p, base=%x, length=%x\n",
- __FUNCTION__, size, node, node->base, node->length);
+ __func__, size, node, node->base, node->length);
if (node->length < size)
continue;
if (node->base & (size - 1)) {
- dbg("%s: not aligned\n", __FUNCTION__);
+ dbg("%s: not aligned\n", __func__);
/* this one isn't base aligned properly
* so we'll make a new entry and split it up */
temp_dword = (node->base | (size-1)) + 1;
/* Don't need to check if too small since we already did */
if (node->length > size) {
- dbg("%s: too big\n", __FUNCTION__);
+ dbg("%s: too big\n", __func__);
/* this one is longer than we need
* so we'll make a new entry and split it up */
split_node = kmalloc(sizeof(*split_node), GFP_KERNEL);
node->next = split_node;
} /* End of too big on top end */
- dbg("%s: got one!!!\n", __FUNCTION__);
+ dbg("%s: got one!!!\n", __func__);
/* If we got here, then it is the right size
* Now take it out of the list */
if (*head == node) {
struct pci_resource *node2;
int out_of_order = 1;
- dbg("%s: head = %p, *head = %p\n", __FUNCTION__, head, *head);
+ dbg("%s: head = %p, *head = %p\n", __func__, head, *head);
if (!(*head))
return 1;
/* Read to clear posted writes */
misc = readw(ctrl->hpc_reg + MISC);
- dbg ("%s - waking up\n", __FUNCTION__);
+ dbg ("%s - waking up\n", __func__);
wake_up_interruptible(&ctrl->queue);
}
hp_slot = func->device - ctrl->slot_device_offset;
dbg("%s: func->device, slot_offset, hp_slot = %d, %d ,%d\n",
- __FUNCTION__, func->device, ctrl->slot_device_offset, hp_slot);
+ __func__, func->device, ctrl->slot_device_offset, hp_slot);
mutex_lock(&ctrl->crit_sect);
/* turn on board and blink green LED */
- dbg("%s: before down\n", __FUNCTION__);
+ dbg("%s: before down\n", __func__);
mutex_lock(&ctrl->crit_sect);
- dbg("%s: after down\n", __FUNCTION__);
+ dbg("%s: after down\n", __func__);
- dbg("%s: before slot_enable\n", __FUNCTION__);
+ dbg("%s: before slot_enable\n", __func__);
slot_enable (ctrl, hp_slot);
- dbg("%s: before green_LED_blink\n", __FUNCTION__);
+ dbg("%s: before green_LED_blink\n", __func__);
green_LED_blink (ctrl, hp_slot);
- dbg("%s: before amber_LED_blink\n", __FUNCTION__);
+ dbg("%s: before amber_LED_blink\n", __func__);
amber_LED_off (ctrl, hp_slot);
- dbg("%s: before set_SOGO\n", __FUNCTION__);
+ dbg("%s: before set_SOGO\n", __func__);
set_SOGO(ctrl);
/* Wait for SOBS to be unset */
- dbg("%s: before wait_for_ctrl_irq\n", __FUNCTION__);
+ dbg("%s: before wait_for_ctrl_irq\n", __func__);
wait_for_ctrl_irq (ctrl);
- dbg("%s: after wait_for_ctrl_irq\n", __FUNCTION__);
+ dbg("%s: after wait_for_ctrl_irq\n", __func__);
- dbg("%s: before up\n", __FUNCTION__);
+ dbg("%s: before up\n", __func__);
mutex_unlock(&ctrl->crit_sect);
- dbg("%s: after up\n", __FUNCTION__);
+ dbg("%s: after up\n", __func__);
/* Wait for ~1 second because of hot plug spec */
- dbg("%s: before long_delay\n", __FUNCTION__);
+ dbg("%s: before long_delay\n", __func__);
long_delay(1*HZ);
- dbg("%s: after long_delay\n", __FUNCTION__);
+ dbg("%s: after long_delay\n", __func__);
- dbg("%s: func status = %x\n", __FUNCTION__, func->status);
+ dbg("%s: func status = %x\n", __func__, func->status);
/* Check for a power fault */
if (func->status == 0xFF) {
/* power fault occurred, but it was benign */
temp_register = 0xFFFFFFFF;
- dbg("%s: temp register set to %x by power fault\n", __FUNCTION__, temp_register);
+ dbg("%s: temp register set to %x by power fault\n", __func__, temp_register);
rc = POWER_FAILURE;
func->status = 0;
} else {
/* Get vendor/device ID u32 */
ctrl->pci_bus->number = func->bus;
rc = pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(func->device, func->function), PCI_VENDOR_ID, &temp_register);
- dbg("%s: pci_read_config_dword returns %d\n", __FUNCTION__, rc);
- dbg("%s: temp_register is %x\n", __FUNCTION__, temp_register);
+ dbg("%s: pci_read_config_dword returns %d\n", __func__, rc);
+ dbg("%s: temp_register is %x\n", __func__, temp_register);
if (rc != 0) {
/* Something's wrong here */
temp_register = 0xFFFFFFFF;
- dbg("%s: temp register set to %x by error\n", __FUNCTION__, temp_register);
+ dbg("%s: temp register set to %x by error\n", __func__, temp_register);
}
/* Preset return code. It will be changed later if things go okay. */
rc = NO_ADAPTER_PRESENT;
rc = configure_new_device(ctrl, func, 0, &res_lists);
- dbg("%s: back from configure_new_device\n", __FUNCTION__);
+ dbg("%s: back from configure_new_device\n", __func__);
ctrl->io_head = res_lists.io_head;
ctrl->mem_head = res_lists.mem_head;
ctrl->p_mem_head = res_lists.p_mem_head;
/* next, we will instantiate the linux pci_dev structures (with
* appropriate driver notification, if already present) */
- dbg("%s: configure linux pci_dev structure\n", __FUNCTION__);
+ dbg("%s: configure linux pci_dev structure\n", __func__);
index = 0;
do {
new_slot = cpqhp_slot_find(ctrl->bus, func->device, index++);
device = func->device;
hp_slot = func->device - ctrl->slot_device_offset;
- dbg("In %s, hp_slot = %d\n", __FUNCTION__, hp_slot);
+ dbg("In %s, hp_slot = %d\n", __func__, hp_slot);
/* When we get here, it is safe to change base address registers.
* We will attempt to save the base address register lengths */
func = cpqhp_slot_find(p_slot->bus, p_slot->device, 0);
dbg("In power_down_board, func = %p, ctrl = %p\n", func, ctrl);
if (!func) {
- dbg("Error! func NULL in %s\n", __FUNCTION__);
+ dbg("Error! func NULL in %s\n", __func__);
return ;
}
func = cpqhp_slot_find(p_slot->bus, p_slot->device, 0);
dbg("In add_board, func = %p, ctrl = %p\n", func, ctrl);
if (!func) {
- dbg("Error! func NULL in %s\n", __FUNCTION__);
+ dbg("Error! func NULL in %s\n", __func__);
return ;
}
}
if (rc) {
- dbg("%s: rc = %d\n", __FUNCTION__, rc);
+ dbg("%s: rc = %d\n", __func__, rc);
}
if (p_slot)
new_slot = func;
- dbg("%s\n", __FUNCTION__);
+ dbg("%s\n", __func__);
/* Check for Multi-function device */
ctrl->pci_bus->number = func->bus;
rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(func->device, func->function), 0x0E, &temp_byte);
if (rc) {
- dbg("%s: rc = %d\n", __FUNCTION__, rc);
+ dbg("%s: rc = %d\n", __func__, rc);
return rc;
}
(temp6 == 'Q')) {
result = 1;
}
- dbg ("%s - returned %d\n", __FUNCTION__, result);
+ dbg ("%s - returned %d\n", __func__, result);
return result;
}
{
int j;
- dbg("%s: bus/dev/func = %x/%x/%x\n", __FUNCTION__, func->bus, func->device, func->function);
+ dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function);
for (j=0; j<8 ; j++) {
struct pci_dev* temp = pci_find_slot(func->bus, PCI_DEVFN(func->device, j));
fakedev->bus = fakebus;
fakebus->number = bus_num;
dbg("%s: dev %d, bus %d, pin %d, num %d\n",
- __FUNCTION__, dev_num, bus_num, int_pin, irq_num);
+ __func__, dev_num, bus_num, int_pin, irq_num);
rc = pcibios_set_irq_routing(fakedev, int_pin - 0x0a, irq_num);
kfree(fakedev);
kfree(fakebus);
- dbg("%s: rc %d\n", __FUNCTION__, rc);
+ dbg("%s: rc %d\n", __func__, rc);
if (!rc)
return !rc;
int rc = 0;
struct pci_resource *node;
struct pci_resource *t_node;
- dbg("%s\n", __FUNCTION__);
+ dbg("%s\n", __func__);
if (!func)
return 1;
/* mis-use enable_slot for rescanning of the pci bus */
cancel_work_sync(&pci_rescan_work);
queue_work(dummyphp_wq, &pci_rescan_work);
- return -ENODEV;
+ return 0;
}
/* find the hotplug_slot for the pci_dev */
return -ENODEV;
dslot = slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, slot->name);
/* don't disable bridged devices just yet, we can't handle them easily... */
if (dslot->dev->subordinate) {
len = (rtable->size - sizeof(struct irq_routing_table)) /
sizeof(struct irq_info);
- if (!len)
+ if (!len) {
+ kfree(rtable);
return -1;
+ }
for (loop = 0; loop < len; loop++) {
if ((*cur_slot)->number == rtable->slots[loop].slot) {
if ((*cur_slot)->bus == rtable->slots[loop].bus) {
debug("rtable->slots[loop].irq[3].link = %x\n",
rtable->slots[loop].irq[3].link);
debug("end of init_devno\n");
+ kfree(rtable);
return 0;
}
}
}
+ kfree(rtable);
return -1;
}
struct slot *pslot;
u8 mode = 0;
- debug("%s - Entry hotplug_slot[%p] pvalue[%p]\n", __FUNCTION__,
+ debug("%s - Entry hotplug_slot[%p] pvalue[%p]\n", __func__,
hotplug_slot, value);
ibmphp_lock_operations();
}
ibmphp_unlock_operations();
- debug("%s - Exit rc[%d] value[%x]\n", __FUNCTION__, rc, *value);
+ debug("%s - Exit rc[%d] value[%x]\n", __func__, rc, *value);
return rc;
}
struct slot *pslot;
u8 mode = 0;
- debug("%s - Entry hotplug_slot[%p] pvalue[%p]\n", __FUNCTION__,
+ debug("%s - Entry hotplug_slot[%p] pvalue[%p]\n", __func__,
hotplug_slot, value);
ibmphp_lock_operations();
}
ibmphp_unlock_operations();
- debug("%s - Exit rc[%d] value[%x]\n", __FUNCTION__, rc, *value);
+ debug("%s - Exit rc[%d] value[%x]\n", __func__, rc, *value);
return rc;
}
struct list_head * tmp;
struct list_head * next;
- debug("%s -- enter\n", __FUNCTION__);
+ debug("%s -- enter\n", __func__);
list_for_each_safe(tmp, next, &ibmphp_slot_head) {
slot_cur = list_entry(tmp, struct slot, ibm_slot_list);
pci_hp_deregister(slot_cur->hotplug_slot);
}
- debug("%s -- exit\n", __FUNCTION__);
+ debug("%s -- exit\n", __func__);
}
static void ibm_unconfigure_device(struct pci_func *func)
struct pci_dev *temp;
u8 j;
- debug("inside %s\n", __FUNCTION__);
+ debug("inside %s\n", __func__);
debug("func->device = %x, func->function = %x\n",
func->device, func->function);
debug("func->device << 3 | 0x0 = %x\n", func->device << 3 | 0x0);
bus = kmalloc(sizeof(*bus), GFP_KERNEL);
if (!bus) {
- err("%s - out of memory\n", __FUNCTION__);
+ err("%s - out of memory\n", __func__);
return 1;
}
dev = kmalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
kfree(bus);
- err("%s - out of memory\n", __FUNCTION__);
+ err("%s - out of memory\n", __func__);
return 1;
}
if (!pci_read_config_word(dev, PCI_VENDOR_ID, &l) &&
(l != 0x0000) && (l != 0xffff)) {
debug("%s - Inside bus_struture_fixup()\n",
- __FUNCTION__);
+ __func__);
pci_scan_bus(busno, ibmphp_pci_bus->ops, NULL);
break;
}
{ },
};
- debug("%s - entry slot # %d\n", __FUNCTION__, slot_cur->number);
+ debug("%s - entry slot # %d\n", __func__, slot_cur->number);
if (SET_BUS_STATUS(slot_cur->ctrl) && is_bus_empty(slot_cur)) {
rc = slot_update(&slot_cur);
if (rc)
/* This is for x440, once Brandon fixes the firmware,
will not need this delay */
msleep(1000);
- debug("%s -Exit\n", __FUNCTION__);
+ debug("%s -Exit\n", __func__);
return 0;
}
list_for_each (ptr1, &bus_info_head) {
ptr = list_entry (ptr1, struct bus_info, bus_info_list);
- debug ("%s - slot_min = %x\n", __FUNCTION__, ptr->slot_min);
- debug ("%s - slot_max = %x\n", __FUNCTION__, ptr->slot_max);
- debug ("%s - slot_count = %x\n", __FUNCTION__, ptr->slot_count);
- debug ("%s - bus# = %x\n", __FUNCTION__, ptr->busno);
- debug ("%s - current_speed = %x\n", __FUNCTION__, ptr->current_speed);
- debug ("%s - controller_id = %x\n", __FUNCTION__, ptr->controller_id);
+ debug ("%s - slot_min = %x\n", __func__, ptr->slot_min);
+ debug ("%s - slot_max = %x\n", __func__, ptr->slot_max);
+ debug ("%s - slot_count = %x\n", __func__, ptr->slot_count);
+ debug ("%s - bus# = %x\n", __func__, ptr->busno);
+ debug ("%s - current_speed = %x\n", __func__, ptr->current_speed);
+ debug ("%s - controller_id = %x\n", __func__, ptr->controller_id);
- debug ("%s - slots_at_33_conv = %x\n", __FUNCTION__, ptr->slots_at_33_conv);
- debug ("%s - slots_at_66_conv = %x\n", __FUNCTION__, ptr->slots_at_66_conv);
- debug ("%s - slots_at_66_pcix = %x\n", __FUNCTION__, ptr->slots_at_66_pcix);
- debug ("%s - slots_at_100_pcix = %x\n", __FUNCTION__, ptr->slots_at_100_pcix);
- debug ("%s - slots_at_133_pcix = %x\n", __FUNCTION__, ptr->slots_at_133_pcix);
+ debug ("%s - slots_at_33_conv = %x\n", __func__, ptr->slots_at_33_conv);
+ debug ("%s - slots_at_66_conv = %x\n", __func__, ptr->slots_at_66_conv);
+ debug ("%s - slots_at_66_pcix = %x\n", __func__, ptr->slots_at_66_pcix);
+ debug ("%s - slots_at_100_pcix = %x\n", __func__, ptr->slots_at_100_pcix);
+ debug ("%s - slots_at_133_pcix = %x\n", __func__, ptr->slots_at_133_pcix);
}
}
debug ("print_lo_info ----\n");
list_for_each (ptr1, &rio_lo_head) {
ptr = list_entry (ptr1, struct rio_detail, rio_detail_list);
- debug ("%s - rio_node_id = %x\n", __FUNCTION__, ptr->rio_node_id);
- debug ("%s - rio_type = %x\n", __FUNCTION__, ptr->rio_type);
- debug ("%s - owner_id = %x\n", __FUNCTION__, ptr->owner_id);
- debug ("%s - first_slot_num = %x\n", __FUNCTION__, ptr->first_slot_num);
- debug ("%s - wpindex = %x\n", __FUNCTION__, ptr->wpindex);
- debug ("%s - chassis_num = %x\n", __FUNCTION__, ptr->chassis_num);
+ debug ("%s - rio_node_id = %x\n", __func__, ptr->rio_node_id);
+ debug ("%s - rio_type = %x\n", __func__, ptr->rio_type);
+ debug ("%s - owner_id = %x\n", __func__, ptr->owner_id);
+ debug ("%s - first_slot_num = %x\n", __func__, ptr->first_slot_num);
+ debug ("%s - wpindex = %x\n", __func__, ptr->wpindex);
+ debug ("%s - chassis_num = %x\n", __func__, ptr->chassis_num);
}
}
{
struct rio_detail *ptr;
struct list_head *ptr1;
- debug ("%s ---\n", __FUNCTION__);
+ debug ("%s ---\n", __func__);
list_for_each (ptr1, &rio_vg_head) {
ptr = list_entry (ptr1, struct rio_detail, rio_detail_list);
- debug ("%s - rio_node_id = %x\n", __FUNCTION__, ptr->rio_node_id);
- debug ("%s - rio_type = %x\n", __FUNCTION__, ptr->rio_type);
- debug ("%s - owner_id = %x\n", __FUNCTION__, ptr->owner_id);
- debug ("%s - first_slot_num = %x\n", __FUNCTION__, ptr->first_slot_num);
- debug ("%s - wpindex = %x\n", __FUNCTION__, ptr->wpindex);
- debug ("%s - chassis_num = %x\n", __FUNCTION__, ptr->chassis_num);
+ debug ("%s - rio_node_id = %x\n", __func__, ptr->rio_node_id);
+ debug ("%s - rio_type = %x\n", __func__, ptr->rio_type);
+ debug ("%s - owner_id = %x\n", __func__, ptr->owner_id);
+ debug ("%s - first_slot_num = %x\n", __func__, ptr->first_slot_num);
+ debug ("%s - wpindex = %x\n", __func__, ptr->wpindex);
+ debug ("%s - chassis_num = %x\n", __func__, ptr->chassis_num);
}
}
list_for_each (ptr1, &ibmphp_ebda_pci_rsrc_head) {
ptr = list_entry (ptr1, struct ebda_pci_rsrc, ebda_pci_rsrc_list);
debug ("%s - rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n",
- __FUNCTION__, ptr->rsrc_type ,ptr->bus_num, ptr->dev_fun,ptr->start_addr, ptr->end_addr);
+ __func__, ptr->rsrc_type ,ptr->bus_num, ptr->dev_fun,ptr->start_addr, ptr->end_addr);
}
}
list_for_each (ptr1, &ibmphp_slot_head) {
ptr = list_entry (ptr1, struct slot, ibm_slot_list);
- debug ("%s - slot_number: %x\n", __FUNCTION__, ptr->number);
+ debug ("%s - slot_number: %x\n", __func__, ptr->number);
}
}
{
struct opt_rio *ptr;
struct list_head *ptr1;
- debug ("%s ---\n", __FUNCTION__);
+ debug ("%s ---\n", __func__);
list_for_each (ptr1, &opt_vg_head) {
ptr = list_entry (ptr1, struct opt_rio, opt_rio_list);
- debug ("%s - rio_type %x\n", __FUNCTION__, ptr->rio_type);
- debug ("%s - chassis_num: %x\n", __FUNCTION__, ptr->chassis_num);
- debug ("%s - first_slot_num: %x\n", __FUNCTION__, ptr->first_slot_num);
- debug ("%s - middle_num: %x\n", __FUNCTION__, ptr->middle_num);
+ debug ("%s - rio_type %x\n", __func__, ptr->rio_type);
+ debug ("%s - chassis_num: %x\n", __func__, ptr->chassis_num);
+ debug ("%s - first_slot_num: %x\n", __func__, ptr->first_slot_num);
+ debug ("%s - middle_num: %x\n", __func__, ptr->middle_num);
}
}
hpc_ptr = list_entry (ptr1, struct controller, ebda_hpc_list);
for (index = 0; index < hpc_ptr->slot_count; index++) {
- debug ("%s - physical slot#: %x\n", __FUNCTION__, hpc_ptr->slots[index].slot_num);
- debug ("%s - pci bus# of the slot: %x\n", __FUNCTION__, hpc_ptr->slots[index].slot_bus_num);
- debug ("%s - index into ctlr addr: %x\n", __FUNCTION__, hpc_ptr->slots[index].ctl_index);
- debug ("%s - cap of the slot: %x\n", __FUNCTION__, hpc_ptr->slots[index].slot_cap);
+ debug ("%s - physical slot#: %x\n", __func__, hpc_ptr->slots[index].slot_num);
+ debug ("%s - pci bus# of the slot: %x\n", __func__, hpc_ptr->slots[index].slot_bus_num);
+ debug ("%s - index into ctlr addr: %x\n", __func__, hpc_ptr->slots[index].ctl_index);
+ debug ("%s - cap of the slot: %x\n", __func__, hpc_ptr->slots[index].slot_cap);
}
for (index = 0; index < hpc_ptr->bus_count; index++) {
- debug ("%s - bus# of each bus controlled by this ctlr: %x\n", __FUNCTION__, hpc_ptr->buses[index].bus_num);
+ debug ("%s - bus# of each bus controlled by this ctlr: %x\n", __func__, hpc_ptr->buses[index].bus_num);
}
- debug ("%s - type of hpc: %x\n", __FUNCTION__, hpc_ptr->ctlr_type);
+ debug ("%s - type of hpc: %x\n", __func__, hpc_ptr->ctlr_type);
switch (hpc_ptr->ctlr_type) {
case 1:
- debug ("%s - bus: %x\n", __FUNCTION__, hpc_ptr->u.pci_ctlr.bus);
- debug ("%s - dev_fun: %x\n", __FUNCTION__, hpc_ptr->u.pci_ctlr.dev_fun);
- debug ("%s - irq: %x\n", __FUNCTION__, hpc_ptr->irq);
+ debug ("%s - bus: %x\n", __func__, hpc_ptr->u.pci_ctlr.bus);
+ debug ("%s - dev_fun: %x\n", __func__, hpc_ptr->u.pci_ctlr.dev_fun);
+ debug ("%s - irq: %x\n", __func__, hpc_ptr->irq);
break;
case 0:
- debug ("%s - io_start: %x\n", __FUNCTION__, hpc_ptr->u.isa_ctlr.io_start);
- debug ("%s - io_end: %x\n", __FUNCTION__, hpc_ptr->u.isa_ctlr.io_end);
- debug ("%s - irq: %x\n", __FUNCTION__, hpc_ptr->irq);
+ debug ("%s - io_start: %x\n", __func__, hpc_ptr->u.isa_ctlr.io_start);
+ debug ("%s - io_end: %x\n", __func__, hpc_ptr->u.isa_ctlr.io_end);
+ debug ("%s - irq: %x\n", __func__, hpc_ptr->irq);
break;
case 2:
case 4:
- debug ("%s - wpegbbar: %lx\n", __FUNCTION__, hpc_ptr->u.wpeg_ctlr.wpegbbar);
- debug ("%s - i2c_addr: %x\n", __FUNCTION__, hpc_ptr->u.wpeg_ctlr.i2c_addr);
- debug ("%s - irq: %x\n", __FUNCTION__, hpc_ptr->irq);
+ debug ("%s - wpegbbar: %lx\n", __func__, hpc_ptr->u.wpeg_ctlr.wpegbbar);
+ debug ("%s - i2c_addr: %x\n", __func__, hpc_ptr->u.wpeg_ctlr.i2c_addr);
+ debug ("%s - irq: %x\n", __func__, hpc_ptr->irq);
break;
}
}
*---------------------------------------------------------------------*/
void __init ibmphp_hpc_initvars (void)
{
- debug ("%s - Entry\n", __FUNCTION__);
+ debug ("%s - Entry\n", __func__);
mutex_init(&sem_hpcaccess);
init_MUTEX (&semOperations);
init_MUTEX_LOCKED (&sem_exit);
to_debug = 0;
- debug ("%s - Exit\n", __FUNCTION__);
+ debug ("%s - Exit\n", __func__);
}
/*----------------------------------------------------------------------
unsigned long ultemp;
unsigned long data; // actual data HILO format
- debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __FUNCTION__, WPGBbar, index);
+ debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __func__, WPGBbar, index);
//--------------------------------------------------------------------
// READ - step 1
i--;
}
if (i == 0) {
- debug ("%s - Error : WPG timeout\n", __FUNCTION__);
+ debug ("%s - Error : WPG timeout\n", __func__);
return HPC_ERROR;
}
//--------------------------------------------------------------------
status = (u8) data;
- debug_polling ("%s - Exit index[%x] status[%x]\n", __FUNCTION__, index, status);
+ debug_polling ("%s - Exit index[%x] status[%x]\n", __func__, index, status);
return (status);
}
unsigned long data; // actual data HILO format
int i;
- debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __FUNCTION__, WPGBbar, index, cmd);
+ debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __func__, WPGBbar, index, cmd);
rc = 0;
//--------------------------------------------------------------------
i--;
}
if (i == 0) {
- debug ("%s - Exit Error:WPG timeout\n", __FUNCTION__);
+ debug ("%s - Exit Error:WPG timeout\n", __func__);
rc = HPC_ERROR;
}
rc = HPC_ERROR;
}
- debug_polling ("%s Exit rc[%x]\n", __FUNCTION__, rc);
+ debug_polling ("%s Exit rc[%x]\n", __func__, rc);
return (rc);
}
int rc = 0;
int busindex;
- debug_polling ("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __FUNCTION__, pslot, cmd, pstatus);
+ debug_polling ("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __func__, pslot, cmd, pstatus);
if ((pslot == NULL)
|| ((pstatus == NULL) && (cmd != READ_ALLSTAT) && (cmd != READ_BUSSTATUS))) {
rc = -EINVAL;
- err ("%s - Error invalid pointer, rc[%d]\n", __FUNCTION__, rc);
+ err ("%s - Error invalid pointer, rc[%d]\n", __func__, rc);
return rc;
}
busindex = ibmphp_get_bus_index (pslot->bus);
if (busindex < 0) {
rc = -EINVAL;
- err ("%s - Exit Error:invalid bus, rc[%d]\n", __FUNCTION__, rc);
+ err ("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc);
return rc;
} else
index = (u8) busindex;
if (index == HPC_ERROR) {
rc = -EINVAL;
- err ("%s - Exit Error:invalid index, rc[%d]\n", __FUNCTION__, rc);
+ err ("%s - Exit Error:invalid index, rc[%d]\n", __func__, rc);
return rc;
}
ctrl_read (ctlr_ptr, wpg_bbar,
index + WPG_1ST_EXTSLOT_INDEX);
} else {
- err ("%s - Error ctrl_read failed\n", __FUNCTION__);
+ err ("%s - Error ctrl_read failed\n", __func__);
rc = -EINVAL;
break;
}
free_hpc_access ();
- debug_polling ("%s - Exit rc[%d]\n", __FUNCTION__, rc);
+ debug_polling ("%s - Exit rc[%d]\n", __func__, rc);
return rc;
}
int rc = 0;
int timeout;
- debug_polling ("%s - Entry pslot[%p] cmd[%x]\n", __FUNCTION__, pslot, cmd);
+ debug_polling ("%s - Entry pslot[%p] cmd[%x]\n", __func__, pslot, cmd);
if (pslot == NULL) {
rc = -EINVAL;
- err ("%s - Error Exit rc[%d]\n", __FUNCTION__, rc);
+ err ("%s - Error Exit rc[%d]\n", __func__, rc);
return rc;
}
busindex = ibmphp_get_bus_index (pslot->bus);
if (busindex < 0) {
rc = -EINVAL;
- err ("%s - Exit Error:invalid bus, rc[%d]\n", __FUNCTION__, rc);
+ err ("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc);
return rc;
} else
index = (u8) busindex;
if (index == HPC_ERROR) {
rc = -EINVAL;
- err ("%s - Error Exit rc[%d]\n", __FUNCTION__, rc);
+ err ("%s - Error Exit rc[%d]\n", __func__, rc);
return rc;
}
if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) {
wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
- debug ("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __FUNCTION__,
+ debug ("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __func__,
ctlr_ptr->ctlr_id, (ulong) (ctlr_ptr->u.wpeg_ctlr.wpegbbar), (ulong) wpg_bbar,
ctlr_ptr->u.wpeg_ctlr.i2c_addr);
}
msleep(1000);
if (timeout < 1) {
done = 1;
- err ("%s - Error command complete timeout\n", __FUNCTION__);
+ err ("%s - Error command complete timeout\n", __func__);
rc = -EFAULT;
} else
timeout--;
iounmap (wpg_bbar);
free_hpc_access ();
- debug_polling ("%s - Exit rc[%d]\n", __FUNCTION__, rc);
+ debug_polling ("%s - Exit rc[%d]\n", __func__, rc);
return rc;
}
*---------------------------------------------------------------------*/
void ibmphp_unlock_operations (void)
{
- debug ("%s - Entry\n", __FUNCTION__);
+ debug ("%s - Entry\n", __func__);
up (&semOperations);
to_debug = 0;
- debug ("%s - Exit\n", __FUNCTION__);
+ debug ("%s - Exit\n", __func__);
}
/*----------------------------------------------------------------------
int poll_count = 0;
u8 ctrl_count = 0x00;
- debug ("%s - Entry\n", __FUNCTION__);
+ debug ("%s - Entry\n", __func__);
while (!kthread_should_stop()) {
/* try to get the lock to do some kind of hardware access */
msleep(100);
}
up (&sem_exit);
- debug ("%s - Exit\n", __FUNCTION__);
+ debug ("%s - Exit\n", __func__);
return 0;
}
ibmphp_update_slot_info (pslot);
}
- debug ("%s - Exit rc[%d] disable[%x] update[%x]\n", __FUNCTION__, rc, disable, update);
+ debug ("%s - Exit rc[%d] disable[%x] update[%x]\n", __func__, rc, disable, update);
return rc;
}
u8 mask;
int rc = 0;
- debug ("%s - Entry old[%x], new[%x]\n", __FUNCTION__, old, new);
+ debug ("%s - Entry old[%x], new[%x]\n", __func__, old, new);
// bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots
for (i = ctrl->starting_slot_num; i <= ctrl->ending_slot_num; i++) {
if (pslot) {
memcpy ((void *) &myslot, (void *) pslot, sizeof (struct slot));
rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL);
- debug ("%s - call process_changeinstatus for slot[%d]\n", __FUNCTION__, i);
+ debug ("%s - call process_changeinstatus for slot[%d]\n", __func__, i);
process_changeinstatus (pslot, &myslot);
} else {
rc = -EINVAL;
- err ("%s - Error bad pointer for slot[%d]\n", __FUNCTION__, i);
+ err ("%s - Error bad pointer for slot[%d]\n", __func__, i);
}
}
}
- debug ("%s - Exit rc[%d]\n", __FUNCTION__, rc);
+ debug ("%s - Exit rc[%d]\n", __func__, rc);
return rc;
}
*---------------------------------------------------------------------*/
int __init ibmphp_hpc_start_poll_thread (void)
{
- debug ("%s - Entry\n", __FUNCTION__);
+ debug ("%s - Entry\n", __func__);
ibmphp_poll_thread = kthread_run(poll_hpc, NULL, "hpc_poll");
if (IS_ERR(ibmphp_poll_thread)) {
- err ("%s - Error, thread not started\n", __FUNCTION__);
+ err ("%s - Error, thread not started\n", __func__);
return PTR_ERR(ibmphp_poll_thread);
}
return 0;
*---------------------------------------------------------------------*/
void __exit ibmphp_hpc_stop_poll_thread (void)
{
- debug ("%s - Entry\n", __FUNCTION__);
+ debug ("%s - Entry\n", __func__);
kthread_stop(ibmphp_poll_thread);
debug ("before locking operations \n");
up (&sem_exit);
debug ("after sem exit up\n");
- debug ("%s - Exit\n", __FUNCTION__);
+ debug ("%s - Exit\n", __func__);
}
/*----------------------------------------------------------------------
struct resource_node *pfmem[6];
unsigned int devfn;
- debug ("%s - inside\n", __FUNCTION__);
+ debug ("%s - inside\n", __func__);
devfn = PCI_DEVFN(func->device, func->function);
ibmphp_pci_bus->number = func->busno;
u8 irq;
int retval;
- debug ("%s - enter\n", __FUNCTION__);
+ debug ("%s - enter\n", __func__);
devfn = PCI_DEVFN(func->function, func->device);
ibmphp_pci_bus->number = func->busno;
u32 tmp_address;
unsigned int devfn;
- debug ("%s - enter\n", __FUNCTION__);
+ debug ("%s - enter\n", __func__);
bus = ibmphp_find_res_bus (busno);
if (!bus) {
bus_no = (int) busno;
debug ("busno is %x\n", busno);
pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_PRIMARY_BUS, &pri_number);
- debug ("%s - busno = %x, primary_number = %x\n", __FUNCTION__, busno, pri_number);
+ debug ("%s - busno = %x, primary_number = %x\n", __func__, busno, pri_number);
pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_number);
debug ("sec_number is %x\n", sec_number);
}
} /* end of mem */
} /* end of for */
- debug ("%s - exiting, returning success\n", __FUNCTION__);
+ debug ("%s - exiting, returning success\n", __func__);
return 0;
}
unsigned int devfn;
u8 valid_device = 0x00; /* To see if we are ever able to find valid device and read it */
- debug ("%s - enter\n", __FUNCTION__);
+ debug ("%s - enter\n", __func__);
device = slot_cur->device;
busno = slot_cur->bus;
/* found correct device!!! */
++valid_device;
- debug ("%s - found correct device\n", __FUNCTION__);
+ debug ("%s - found correct device\n", __func__);
/* header: x x x x x x x x
* | |___________|=> 1=PPB bridge, 0=normal device, 2=CardBus Bridge
struct pci_func *cur_func = NULL;
struct pci_func *temp_func;
- debug ("%s - enter\n", __FUNCTION__);
+ debug ("%s - enter\n", __func__);
if (!the_end) {
/* Need to unconfigure the card */
sl->func = NULL;
*slot_cur = sl;
- debug ("%s - exit\n", __FUNCTION__);
+ debug ("%s - exit\n", __func__);
return 0;
}
struct range_node *range;
struct resource_node *res;
- debug ("%s - bus_cur->busno = %d\n", __FUNCTION__, bus_cur->busno);
+ debug ("%s - bus_cur->busno = %d\n", __func__, bus_cur->busno);
if (bus_cur->needIOUpdate) {
res = bus_cur->firstIO;
struct range_node *range_cur = NULL;
struct resource_node *res_start = NULL;
- debug ("%s - enter\n", __FUNCTION__);
+ debug ("%s - enter\n", __func__);
if (!res) {
err ("NULL passed to add\n");
}
}
- debug ("%s - exit\n", __FUNCTION__);
+ debug ("%s - exit\n", __func__);
return 0;
}
return -EINVAL;
}
- debug ("%s - enter\n", __FUNCTION__);
+ debug ("%s - enter\n", __func__);
debug ("bus_cur->busno is %d\n", bus_cur->busno);
/* This is a quick fix to not mess up with the code very much. i.e.,
while (res_cur) {
range = find_range (bus_cur, res_cur);
- debug ("%s - rangeno = %d\n", __FUNCTION__, res_cur->rangeno);
+ debug ("%s - rangeno = %d\n", __func__, res_cur->rangeno);
if (!range) {
err ("no range for the device exists... bailing out...\n");
return -ENODEV;
ibmphp_pci_bus->number = bus_cur->busno;
- debug ("inside %s\n", __FUNCTION__);
+ debug ("inside %s\n", __func__);
debug ("bus_cur->busno = %x\n", bus_cur->busno);
for (device = 0; device < 32; device++) {
#define MY_NAME "pci_hotplug"
-#define dbg(fmt, arg...) do { if (debug) printk(KERN_DEBUG "%s: %s: " fmt , MY_NAME , __FUNCTION__ , ## arg); } while (0)
+#define dbg(fmt, arg...) do { if (debug) printk(KERN_DEBUG "%s: %s: " fmt , MY_NAME , __func__ , ## arg); } while (0)
#define err(format, arg...) printk(KERN_ERR "%s: " format , MY_NAME , ## arg)
#define info(format, arg...) printk(KERN_INFO "%s: " format , MY_NAME , ## arg)
#define warn(format, arg...) printk(KERN_WARNING "%s: " format , MY_NAME , ## arg)
return slot;
}
- err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device);
+ err("%s: slot (device=0x%x) not found\n", __func__, device);
return NULL;
}
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
kfree(slot->hotplug_slot->info);
kfree(slot->hotplug_slot);
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
hotplug_slot->info->attention_status = status;
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
return pciehp_sysfs_enable_slot(slot);
}
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
return pciehp_sysfs_disable_slot(slot);
}
struct slot *slot = hotplug_slot->private;
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_power_status(slot, value);
if (retval < 0)
struct slot *slot = hotplug_slot->private;
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_attention_status(slot, value);
if (retval < 0)
struct slot *slot = hotplug_slot->private;
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_latch_status(slot, value);
if (retval < 0)
struct slot *slot = hotplug_slot->private;
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_adapter_status(slot, value);
if (retval < 0)
struct slot *slot = hotplug_slot->private;
struct pci_bus *bus = slot->ctrl->pci_dev->subordinate;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = (pci_domain_nr(bus) << 16) | (slot->bus << 8) | slot->device;
struct slot *slot = hotplug_slot->private;
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_max_bus_speed(slot, value);
if (retval < 0)
struct slot *slot = hotplug_slot->private;
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_cur_bus_speed(slot, value);
if (retval < 0)
ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
if (!ctrl) {
- err("%s : out of memory\n", __FUNCTION__);
+ err("%s : out of memory\n", __func__);
goto err_out_none;
}
INIT_LIST_HEAD(&ctrl->slot_list);
pci_set_drvdata(pdev, ctrl);
dbg("%s: ctrl bus=0x%x, device=%x, function=%x, irq=%x\n",
- __FUNCTION__, pdev->bus->number, PCI_SLOT(pdev->devfn),
+ __func__, pdev->bus->number, PCI_SLOT(pdev->devfn),
PCI_FUNC(pdev->devfn), pdev->irq);
/* Setup the slot information structures */
#ifdef CONFIG_PM
static int pciehp_suspend (struct pcie_device *dev, pm_message_t state)
{
- printk("%s ENTRY\n", __FUNCTION__);
+ printk("%s ENTRY\n", __func__);
return 0;
}
static int pciehp_resume (struct pcie_device *dev)
{
- printk("%s ENTRY\n", __FUNCTION__);
+ printk("%s ENTRY\n", __func__);
if (pciehp_force) {
struct pci_dev *pdev = dev->port;
struct controller *ctrl = pci_get_drvdata(pdev);
dbg("pcie_port_service_register = %d\n", retval);
info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
if (retval)
- dbg("%s: Failure to register service\n", __FUNCTION__);
+ dbg("%s: Failure to register service\n", __func__);
return retval;
}
if (POWER_CTRL(ctrl->ctrlcap)) {
if (pslot->hpc_ops->power_off_slot(pslot)) {
err("%s: Issue of Slot Power Off command failed\n",
- __FUNCTION__);
+ __func__);
return;
}
}
if (ATTN_LED(ctrl->ctrlcap)) {
if (pslot->hpc_ops->set_attention_status(pslot, 1)) {
err("%s: Issue of Set Attention Led command failed\n",
- __FUNCTION__);
+ __func__);
return;
}
}
struct controller *ctrl = p_slot->ctrl;
dbg("%s: slot device, slot offset, hp slot = %d, %d ,%d\n",
- __FUNCTION__, p_slot->device,
+ __func__, p_slot->device,
ctrl->slot_device_offset, p_slot->hp_slot);
if (POWER_CTRL(ctrl->ctrlcap)) {
/* Check link training status */
retval = p_slot->hpc_ops->check_lnk_status(ctrl);
if (retval) {
- err("%s: Failed to check link status\n", __FUNCTION__);
+ err("%s: Failed to check link status\n", __func__);
set_slot_off(ctrl, p_slot);
return retval;
}
/* Check for a power fault */
if (p_slot->hpc_ops->query_power_fault(p_slot)) {
- dbg("%s: power fault detected\n", __FUNCTION__);
+ dbg("%s: power fault detected\n", __func__);
retval = POWER_FAILURE;
goto err_exit;
}
if (retval)
return retval;
- dbg("In %s, hp_slot = %d\n", __FUNCTION__, p_slot->hp_slot);
+ dbg("In %s, hp_slot = %d\n", __func__, p_slot->hp_slot);
if (POWER_CTRL(ctrl->ctrlcap)) {
/* power off slot */
retval = p_slot->hpc_ops->power_off_slot(p_slot);
if (retval) {
err("%s: Issue of Slot Disable command failed\n",
- __FUNCTION__);
+ __func__);
return retval;
}
}
case POWEROFF_STATE:
mutex_unlock(&p_slot->lock);
dbg("%s: disabling bus:device(%x:%x)\n",
- __FUNCTION__, p_slot->bus, p_slot->device);
+ __func__, p_slot->bus, p_slot->device);
pciehp_disable_slot(p_slot);
mutex_lock(&p_slot->lock);
p_slot->state = STATIC_STATE;
info = kmalloc(sizeof(*info), GFP_KERNEL);
if (!info) {
- err("%s: Cannot allocate memory\n", __FUNCTION__);
+ err("%s: Cannot allocate memory\n", __func__);
return;
}
info->p_slot = p_slot;
* expires to cancel hot-add or hot-remove
*/
info("Button cancel on Slot(%s)\n", p_slot->name);
- dbg("%s: button cancel\n", __FUNCTION__);
+ dbg("%s: button cancel\n", __func__);
cancel_delayed_work(&p_slot->work);
if (p_slot->state == BLINKINGOFF_STATE) {
if (PWR_LED(ctrl->ctrlcap))
info = kmalloc(sizeof(*info), GFP_KERNEL);
if (!info) {
- err("%s: Cannot allocate memory\n", __FUNCTION__);
+ err("%s: Cannot allocate memory\n", __func__);
return;
}
info->p_slot = p_slot;
rc = p_slot->hpc_ops->get_adapter_status(p_slot, &getstatus);
if (rc || !getstatus) {
- info("%s: no adapter on slot(%s)\n", __FUNCTION__,
+ info("%s: no adapter on slot(%s)\n", __func__,
p_slot->name);
mutex_unlock(&p_slot->ctrl->crit_sect);
return -ENODEV;
if (MRL_SENS(p_slot->ctrl->ctrlcap)) {
rc = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
if (rc || getstatus) {
- info("%s: latch open on slot(%s)\n", __FUNCTION__,
+ info("%s: latch open on slot(%s)\n", __func__,
p_slot->name);
mutex_unlock(&p_slot->ctrl->crit_sect);
return -ENODEV;
if (POWER_CTRL(p_slot->ctrl->ctrlcap)) {
rc = p_slot->hpc_ops->get_power_status(p_slot, &getstatus);
if (rc || getstatus) {
- info("%s: already enabled on slot(%s)\n", __FUNCTION__,
+ info("%s: already enabled on slot(%s)\n", __func__,
p_slot->name);
mutex_unlock(&p_slot->ctrl->crit_sect);
return -EINVAL;
if (!HP_SUPR_RM(p_slot->ctrl->ctrlcap)) {
ret = p_slot->hpc_ops->get_adapter_status(p_slot, &getstatus);
if (ret || !getstatus) {
- info("%s: no adapter on slot(%s)\n", __FUNCTION__,
+ info("%s: no adapter on slot(%s)\n", __func__,
p_slot->name);
mutex_unlock(&p_slot->ctrl->crit_sect);
return -ENODEV;
if (MRL_SENS(p_slot->ctrl->ctrlcap)) {
ret = p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
if (ret || getstatus) {
- info("%s: latch open on slot(%s)\n", __FUNCTION__,
+ info("%s: latch open on slot(%s)\n", __func__,
p_slot->name);
mutex_unlock(&p_slot->ctrl->crit_sect);
return -ENODEV;
if (POWER_CTRL(p_slot->ctrl->ctrlcap)) {
ret = p_slot->hpc_ops->get_power_status(p_slot, &getstatus);
if (ret || !getstatus) {
- info("%s: already disabled slot(%s)\n", __FUNCTION__,
+ info("%s: already disabled slot(%s)\n", __func__,
p_slot->name);
mutex_unlock(&p_slot->ctrl->crit_sect);
return -EINVAL;
retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (retval) {
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
goto out;
}
proceed forward to issue the next command according
to spec. Just print out the error message */
dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
- __FUNCTION__);
+ __func__);
}
spin_lock_irqsave(&ctrl->lock, flags);
retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (retval) {
- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTCTRL register\n", __func__);
goto out_spin_unlock;
}
ctrl->cmd_busy = 1;
retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
if (retval)
- err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
+ err("%s: Cannot write to SLOTCTRL register\n", __func__);
out_spin_unlock:
spin_unlock_irqrestore(&ctrl->lock, flags);
retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
if (retval) {
- err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read LNKSTATUS register\n", __func__);
return retval;
}
- dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
+ dbg("%s: lnk_status = %x\n", __func__, lnk_status);
if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
!(lnk_status & NEG_LINK_WD)) {
- err("%s : Link Training Error occurs \n", __FUNCTION__);
+ err("%s : Link Training Error occurs \n", __func__);
retval = -1;
return retval;
}
retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (retval) {
- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTCTRL register\n", __func__);
return retval;
}
dbg("%s: SLOTCTRL %x, value read %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
+ __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (retval) {
- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTCTRL register\n", __func__);
return retval;
}
dbg("%s: SLOTCTRL %x value read %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
+ __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (retval) {
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
return retval;
}
retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (retval) {
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
return retval;
}
card_state = (u8)((slot_status & PRSN_STATE) >> 6);
retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (retval) {
- err("%s: Cannot check for power fault\n", __FUNCTION__);
+ err("%s: Cannot check for power fault\n", __func__);
return retval;
}
pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (retval) {
- err("%s : Cannot check EMI status\n", __FUNCTION__);
+ err("%s : Cannot check EMI status\n", __func__);
return retval;
}
*status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
dbg("%s: SLOTCTRL %x write cmd %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
return rc;
}
pcie_write_cmd(slot, slot_cmd, cmd_mask);
dbg("%s: SLOTCTRL %x write cmd %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
}
static void hpc_set_green_led_off(struct slot *slot)
pcie_write_cmd(slot, slot_cmd, cmd_mask);
dbg("%s: SLOTCTRL %x write cmd %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
}
static void hpc_set_green_led_blink(struct slot *slot)
pcie_write_cmd(slot, slot_cmd, cmd_mask);
dbg("%s: SLOTCTRL %x write cmd %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
}
static void hpc_release_ctlr(struct controller *ctrl)
u16 slot_status;
int retval = 0;
- dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
+ dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
/* Clear sticky power-fault bit from previous power failures */
retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (retval) {
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
return retval;
}
slot_status &= PWR_FAULT_DETECTED;
retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
if (retval) {
err("%s: Cannot write to SLOTSTATUS register\n",
- __FUNCTION__);
+ __func__);
return retval;
}
}
retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
if (retval) {
- err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
+ err("%s: Write %x command failed!\n", __func__, slot_cmd);
return -1;
}
dbg("%s: SLOTCTRL %x write cmd %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
return retval;
}
int retval = 0;
int changed;
- dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
+ dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
/*
* Set Bad DLLP Mask bit in Correctable Error Mask
retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
if (retval) {
- err("%s: Write command failed!\n", __FUNCTION__);
+ err("%s: Write command failed!\n", __func__);
retval = -1;
goto out;
}
dbg("%s: SLOTCTRL %x write cmd %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
/*
* After turning power off, we must wait for at least 1 second
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (rc) {
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
return IRQ_NONE;
}
if ( !intr_loc )
return IRQ_NONE;
- dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
+ dbg("%s: intr_loc %x\n", __func__, intr_loc);
/* Mask Hot-plug Interrupt Enable */
if (!pciehp_poll_mode) {
spin_lock_irqsave(&ctrl->lock, flags);
rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
if (rc) {
err("%s: Cannot read SLOT_CTRL register\n",
- __FUNCTION__);
+ __func__);
spin_unlock_irqrestore(&ctrl->lock, flags);
return IRQ_NONE;
}
dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n",
- __FUNCTION__, temp_word);
+ __func__, temp_word);
temp_word = (temp_word & ~HP_INTR_ENABLE &
~CMD_CMPL_INTR_ENABLE) | 0x00;
rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
if (rc) {
err("%s: Cannot write to SLOTCTRL register\n",
- __FUNCTION__);
+ __func__);
spin_unlock_irqrestore(&ctrl->lock, flags);
return IRQ_NONE;
}
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (rc) {
err("%s: Cannot read SLOT_STATUS register\n",
- __FUNCTION__);
+ __func__);
return IRQ_NONE;
}
dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n",
- __FUNCTION__, slot_status);
+ __func__, slot_status);
/* Clear command complete interrupt caused by this write */
temp_word = 0x1f;
rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
if (rc) {
err("%s: Cannot write to SLOTSTATUS register\n",
- __FUNCTION__);
+ __func__);
return IRQ_NONE;
}
}
temp_word = 0x1F;
rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
if (rc) {
- err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot write to SLOTSTATUS register\n", __func__);
return IRQ_NONE;
}
/* Unmask Hot-plug Interrupt Enable */
rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
if (rc) {
err("%s: Cannot read SLOTCTRL register\n",
- __FUNCTION__);
+ __func__);
spin_unlock_irqrestore(&ctrl->lock, flags);
return IRQ_NONE;
}
- dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
+ dbg("%s: Unmask Hot-plug Interrupt Enable\n", __func__);
temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
if (rc) {
err("%s: Cannot write to SLOTCTRL register\n",
- __FUNCTION__);
+ __func__);
spin_unlock_irqrestore(&ctrl->lock, flags);
return IRQ_NONE;
}
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (rc) {
err("%s: Cannot read SLOT_STATUS register\n",
- __FUNCTION__);
+ __func__);
return IRQ_NONE;
}
rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
if (rc) {
err("%s: Cannot write to SLOTSTATUS failed\n",
- __FUNCTION__);
+ __func__);
return IRQ_NONE;
}
dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n",
- __FUNCTION__, temp_word);
+ __func__, temp_word);
}
return IRQ_HANDLED;
retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
if (retval) {
- err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
+ err("%s: Cannot read LNKCAP register\n", __func__);
return retval;
}
retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
if (retval) {
- err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
+ err("%s: Cannot read LNKCAP register\n", __func__);
return retval;
}
retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
if (retval) {
- err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read LNKSTATUS register\n", __func__);
return retval;
}
retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
if (retval) {
- err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read LNKSTATUS register\n", __func__);
return retval;
}
rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
if (rc) {
- err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTCAP register\n", __func__);
return -1;
}
/* Mask Hot-plug Interrupt Enable */
rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
if (rc) {
- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTCTRL register\n", __func__);
return -1;
}
dbg("%s: SLOTCTRL %x value read %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
+ __func__, ctrl->cap_base + SLOTCTRL, temp_word);
temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) |
0x00;
rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
if (rc) {
- err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
+ err("%s: Cannot write to SLOTCTRL register\n", __func__);
return -1;
}
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (rc) {
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
return -1;
}
temp_word = 0x1F; /* Clear all events */
rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
if (rc) {
- err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot write to SLOTSTATUS register\n", __func__);
return -1;
}
return 0;
rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
if (rc) {
- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTCTRL register\n", __func__);
goto abort;
}
rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
if (rc) {
- err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTCAP register\n", __func__);
goto abort;
}
*/
rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
if (rc) {
- err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
+ err("%s: Cannot write to SLOTCTRL register\n", __func__);
goto abort;
}
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (rc) {
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
goto abort_disable_intr;
}
temp_word = 0x1F; /* Clear all events */
rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
if (rc) {
- err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot write to SLOTSTATUS register\n", __func__);
goto abort_disable_intr;
}
rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
}
if (rc)
- err("%s : disabling interrupts failed\n", __FUNCTION__);
+ err("%s : disabling interrupts failed\n", __func__);
abort:
return -1;
}
ctrl->pci_dev = pdev; /* save pci_dev in context */
dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
- __FUNCTION__, pdev->vendor, pdev->device);
+ __func__, pdev->vendor, pdev->device);
cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
if (cap_base == 0) {
- dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
+ dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __func__);
goto abort;
}
ctrl->cap_base = cap_base;
- dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
+ dbg("%s: pcie_cap_base %x\n", __func__, cap_base);
rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
if (rc) {
- err("%s: Cannot read CAPREG register\n", __FUNCTION__);
+ err("%s: Cannot read CAPREG register\n", __func__);
goto abort;
}
dbg("%s: CAPREG offset %x cap_reg %x\n",
- __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
+ __func__, ctrl->cap_base + CAPREG, cap_reg);
if (((cap_reg & SLOT_IMPL) == 0) ||
(((cap_reg & DEV_PORT_TYPE) != 0x0040)
&& ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
dbg("%s : This is not a root port or the port is not "
- "connected to a slot\n", __FUNCTION__);
+ "connected to a slot\n", __func__);
goto abort;
}
rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
if (rc) {
- err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTCAP register\n", __func__);
goto abort;
}
dbg("%s: SLOTCAP offset %x slot_cap %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
+ __func__, ctrl->cap_base + SLOTCAP, slot_cap);
if (!(slot_cap & HP_CAP)) {
- dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
+ dbg("%s : This slot is not hot-plug capable\n", __func__);
goto abort;
}
/* For debugging purpose */
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
if (rc) {
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
goto abort;
}
dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
+ __func__, ctrl->cap_base + SLOTSTATUS, slot_status);
rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
if (rc) {
- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
+ err("%s: Cannot read SLOTCTRL register\n", __func__);
goto abort;
}
dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
+ __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
if (pci_resource_len(pdev, rc) > 0)
rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
MY_NAME, (void *)ctrl);
dbg("%s: request_irq %d for hpc%d (returns %d)\n",
- __FUNCTION__, ctrl->pci_dev->irq,
+ __func__, ctrl->pci_dev->irq,
atomic_read(&pciehp_num_controllers), rc);
if (rc) {
err("Can't get irq %d for the hotplug controller\n",
if (hpp->revision > 1) {
printk(KERN_WARNING "%s: Rev.%d type0 record not supported\n",
- __FUNCTION__, hpp->revision);
+ __func__, hpp->revision);
return;
}
if (hpp->revision > 1) {
printk(KERN_WARNING "%s: Rev.%d type2 record not supported\n",
- __FUNCTION__, hpp->revision);
+ __func__, hpp->revision);
return;
}
if (pciehp_get_hp_params_from_firmware(dev, &hpp)) {
printk(KERN_WARNING "%s: Could not get hotplug parameters\n",
- __FUNCTION__);
+ __func__);
return;
}
struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
u16 command;
- dbg("%s: bus/dev = %x/%x\n", __FUNCTION__, p_slot->bus,
+ dbg("%s: bus/dev = %x/%x\n", __func__, p_slot->bus,
p_slot->device);
ret = p_slot->hpc_ops->get_adapter_status(p_slot, &presence);
if (ret)
struct slot *slot = hotplug_slot->private;
int retval = 0;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
/*
* Fill in code here to enable the specified slot
struct slot *slot = hotplug_slot->private;
int retval = 0;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
/*
* Fill in code here to disable the specified slot
struct slot *slot = hotplug_slot->private;
int retval = 0;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
switch (status) {
case 0:
struct slot *slot = hotplug_slot->private;
int retval = 0;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
switch (value) {
case 0:
struct slot *slot = hotplug_slot->private;
int retval = 0;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
/*
* Fill in logic to get the current power status of the specific
struct slot *slot = hotplug_slot->private;
int retval = 0;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
/*
* Fill in logic to get the current attention status of the specific
struct slot *slot = hotplug_slot->private;
int retval = 0;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
/*
* Fill in logic to get the current latch status of the specific
struct slot *slot = hotplug_slot->private;
int retval = 0;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
/*
* Fill in logic to get the current adapter status of the specific
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
kfree(slot->hotplug_slot->info);
kfree(slot->hotplug_slot);
kfree(slot);
dev = of_create_pci_dev(dn, phb->bus, pdn->devfn);
if (!dev) {
printk(KERN_ERR "%s: failed to create pci dev for %s\n",
- __FUNCTION__, dn->full_name);
+ __func__, dn->full_name);
return;
}
dev = dlpar_find_new_dev(phb->bus, dn);
if (!dev) {
- printk(KERN_ERR "%s: unable to add bus %s\n", __FUNCTION__,
+ printk(KERN_ERR "%s: unable to add bus %s\n", __func__,
drc_name);
return -EIO;
}
if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
printk(KERN_ERR "%s: unexpected header type %d, unable to add bus %s\n",
- __FUNCTION__, dev->hdr_type, drc_name);
+ __func__, dev->hdr_type, drc_name);
return -EIO;
}
/* Add hotplug slot */
if (rpaphp_add_slot(dn)) {
printk(KERN_ERR "%s: unable to add hotplug slot %s\n",
- __FUNCTION__, drc_name);
+ __func__, drc_name);
return -EIO;
}
return 0;
if (rpaphp_deregister_slot(slot)) {
printk(KERN_ERR
"%s: unable to remove hotplug slot %s\n",
- __FUNCTION__, drc_name);
+ __func__, drc_name);
return -EIO;
}
}
if (rpaphp_add_slot(dn)) {
printk(KERN_ERR "%s: unable to add hotplug slot %s\n",
- __FUNCTION__, drc_name);
+ __func__, drc_name);
return -EIO;
}
return 0;
if (!vio_register_device_node(dn)) {
printk(KERN_ERR
"%s: failed to register vio node %s\n",
- __FUNCTION__, drc_name);
+ __func__, drc_name);
return -EIO;
}
return 0;
if (rpaphp_deregister_slot(slot)) {
printk(KERN_ERR
"%s: unable to remove hotplug slot %s\n",
- __FUNCTION__, drc_name);
+ __func__, drc_name);
return -EIO;
}
} else
if (pcibios_unmap_io_space(bus)) {
printk(KERN_ERR "%s: failed to unmap bus range\n",
- __FUNCTION__);
+ __func__);
return -ERANGE;
}
if (!is_dlpar_capable()) {
printk(KERN_WARNING "%s: partition not DLPAR capable\n",
- __FUNCTION__);
+ __func__);
return -EPERM;
}
if (!is_php_dn(dn, &indexes, &names, &types, &power_domains))
return 0;
- dbg("Entry %s: dn->full_name=%s\n", __FUNCTION__, dn->full_name);
+ dbg("Entry %s: dn->full_name=%s\n", __func__, dn->full_name);
/* register PCI devices */
name = (char *) &names[1];
name += strlen(name) + 1;
type += strlen(type) + 1;
}
- dbg("%s - Exit: rc[%d]\n", __FUNCTION__, retval);
+ dbg("%s - Exit: rc[%d]\n", __func__, retval);
/* XXX FIXME: reports a failure only if last entry in loop failed */
return retval;
} else if (state == EMPTY) {
slot->state = EMPTY;
} else {
- err("%s: slot[%s] is in invalid state\n", __FUNCTION__, slot->name);
+ err("%s: slot[%s] is in invalid state\n", __func__, slot->name);
slot->state = NOT_VALID;
return -EINVAL;
}
if (rc < 0) {
if (rc == -EFAULT || rc == -EEXIST) {
dbg("%s: slot must be power up to get sensor-state\n",
- __FUNCTION__);
+ __func__);
/* some slots have to be powered up
* before get-sensor will succeed.
&setlevel);
if (rc < 0) {
dbg("%s: power on slot[%s] failed rc=%d.\n",
- __FUNCTION__, slot->name, rc);
+ __func__, slot->name, rc);
} else {
rc = rtas_get_sensor(DR_ENTITY_SENSE,
slot->index, state);
}
} else if (rc == -ENODEV)
- info("%s: slot is unusable\n", __FUNCTION__);
+ info("%s: slot is unusable\n", __func__);
else
- err("%s failed to get sensor state\n", __FUNCTION__);
+ err("%s failed to get sensor state\n", __func__);
}
return rc;
}
bus = pcibios_find_pci_bus(slot->dn);
if (!bus) {
- err("%s: no pci_bus for dn %s\n", __FUNCTION__, slot->dn->full_name);
+ err("%s: no pci_bus for dn %s\n", __func__, slot->dn->full_name);
return -EINVAL;
}
/* non-empty slot has to have child */
if (!slot->dn->child) {
err("%s: slot[%s]'s device_node doesn't have child for adapter\n",
- __FUNCTION__, slot->name);
+ __func__, slot->name);
return -EINVAL;
}
if (debug) {
struct pci_dev *dev;
- dbg("%s: pci_devs of slot[%s]\n", __FUNCTION__, slot->dn->full_name);
+ dbg("%s: pci_devs of slot[%s]\n", __func__, slot->dn->full_name);
list_for_each_entry (dev, &bus->devices, bus_list)
dbg("\t%s\n", pci_name(dev));
}
struct hotplug_slot *php_slot = slot->hotplug_slot;
dbg("%s - Entry: deregistering slot=%s\n",
- __FUNCTION__, slot->name);
+ __func__, slot->name);
list_del(&slot->rpaphp_slot_list);
if (retval)
err("Problem unregistering a slot %s\n", slot->name);
- dbg("%s - Exit: rc[%d]\n", __FUNCTION__, retval);
+ dbg("%s - Exit: rc[%d]\n", __func__, retval);
return retval;
}
EXPORT_SYMBOL_GPL(rpaphp_deregister_slot);
int retval;
dbg("%s registering slot:path[%s] index[%x], name[%s] pdomain[%x] type[%d]\n",
- __FUNCTION__, slot->dn->full_name, slot->index, slot->name,
+ __func__, slot->dn->full_name, slot->index, slot->name,
slot->power_domain, slot->type);
/* should not try to register the same slot twice */
ret = acpi_load_table((struct acpi_table_header *)ssdt);
if (ACPI_FAILURE(ret)) {
printk(KERN_ERR "%s: acpi_load_table failed (0x%x)\n",
- __FUNCTION__, ret);
+ __func__, ret);
/* try to continue on */
}
}
if (ACPI_FAILURE(ret)) {
printk(KERN_ERR "%s: acpi_bus_add "
"failed (0x%x) for slot %d "
- "func %d\n", __FUNCTION__,
+ "func %d\n", __func__,
ret, (int)(adr>>16),
(int)(adr&0xffff));
/* try to continue on */
if (ACPI_FAILURE(ret)) {
printk(KERN_ERR "%s: acpi_unload_table_id "
"failed (0x%x) for id %d\n",
- __FUNCTION__, ret, ssdt_id);
+ __func__, ret, ssdt_id);
/* try to continue on */
}
}
if (!sn_prom_feature_available(PRF_HOTPLUG_SUPPORT)) {
printk(KERN_ERR "%s: PROM version does not support hotplug.\n",
- __FUNCTION__);
+ __func__);
return -EPERM;
}
return slot;
}
- err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device);
+ err("%s: slot (device=0x%x) not found\n", __func__, device);
return NULL;
}
pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
if (perr_set) {
- dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);
+ dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__func__ , perr_set);
pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
}
pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
rse_set = pcix_mem_base_reg & RSE_MASK;
if (rse_set) {
- dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );
+ dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__func__ );
pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
}
{
struct slot *slot = hotplug_slot->private;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
kfree(slot->hotplug_slot->info);
kfree(slot->hotplug_slot);
{
struct slot *slot = get_slot(hotplug_slot);
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
hotplug_slot->info->attention_status = status;
slot->hpc_ops->set_attention_status(slot, status);
{
struct slot *slot = get_slot(hotplug_slot);
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
return shpchp_sysfs_enable_slot(slot);
}
{
struct slot *slot = get_slot(hotplug_slot);
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
return shpchp_sysfs_disable_slot(slot);
}
struct slot *slot = get_slot(hotplug_slot);
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_power_status(slot, value);
if (retval < 0)
struct slot *slot = get_slot(hotplug_slot);
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_attention_status(slot, value);
if (retval < 0)
struct slot *slot = get_slot(hotplug_slot);
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_latch_status(slot, value);
if (retval < 0)
struct slot *slot = get_slot(hotplug_slot);
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_adapter_status(slot, value);
if (retval < 0)
struct slot *slot = get_slot(hotplug_slot);
struct pci_bus *bus = slot->ctrl->pci_dev->subordinate;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
*value = (pci_domain_nr(bus) << 16) | (slot->bus << 8) | slot->device;
struct slot *slot = get_slot(hotplug_slot);
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_max_bus_speed(slot, value);
if (retval < 0)
struct slot *slot = get_slot(hotplug_slot);
int retval;
- dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name);
+ dbg("%s - physical_slot = %s\n", __func__, hotplug_slot->name);
retval = slot->hpc_ops->get_cur_bus_speed(slot, value);
if (retval < 0)
ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
if (!ctrl) {
- err("%s : out of memory\n", __FUNCTION__);
+ err("%s : out of memory\n", __func__);
goto err_out_none;
}
INIT_LIST_HEAD(&ctrl->slot_list);
int retval = 0;
retval = pci_register_driver(&shpc_driver);
- dbg("%s: pci_register_driver = %d\n", __FUNCTION__, retval);
+ dbg("%s: pci_register_driver = %d\n", __func__, retval);
info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
return retval;
}
p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
p_slot->hpc_ops->get_adapter_status(p_slot, &(p_slot->presence_save));
p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
- dbg("%s: Card present %x Power status %x\n", __FUNCTION__,
+ dbg("%s: Card present %x Power status %x\n", __func__,
p_slot->presence_save, p_slot->pwr_save);
if (getstatus) {
{
int rc = 0;
- dbg("%s: change to speed %d\n", __FUNCTION__, speed);
+ dbg("%s: change to speed %d\n", __func__, speed);
if ((rc = p_slot->hpc_ops->set_bus_speed_mode(p_slot, speed))) {
err("%s: Issue of set bus speed mode command failed\n",
- __FUNCTION__);
+ __func__);
return WRONG_BUS_FREQUENCY;
}
return rc;
if (flag) {
if (asp < bsp) {
err("%s: speed of bus %x and adapter %x mismatch\n",
- __FUNCTION__, bsp, asp);
+ __func__, bsp, asp);
rc = WRONG_BUS_FREQUENCY;
}
return rc;
hp_slot = p_slot->device - ctrl->slot_device_offset;
dbg("%s: p_slot->device, slot_offset, hp_slot = %d, %d ,%d\n",
- __FUNCTION__, p_slot->device,
+ __func__, p_slot->device,
ctrl->slot_device_offset, hp_slot);
/* Power on slot without connecting to bus */
rc = p_slot->hpc_ops->power_on_slot(p_slot);
if (rc) {
- err("%s: Failed to power on slot\n", __FUNCTION__);
+ err("%s: Failed to power on slot\n", __func__);
return -1;
}
return WRONG_BUS_FREQUENCY;
if ((rc = p_slot->hpc_ops->set_bus_speed_mode(p_slot, PCI_SPEED_33MHz))) {
- err("%s: Issue of set bus speed mode command failed\n", __FUNCTION__);
+ err("%s: Issue of set bus speed mode command failed\n", __func__);
return WRONG_BUS_FREQUENCY;
}
/* turn on board, blink green LED, turn off Amber LED */
if ((rc = p_slot->hpc_ops->slot_enable(p_slot))) {
- err("%s: Issue of Slot Enable command failed\n", __FUNCTION__);
+ err("%s: Issue of Slot Enable command failed\n", __func__);
return rc;
}
}
rc = p_slot->hpc_ops->get_adapter_speed(p_slot, &asp);
if (rc) {
err("%s: Can't get adapter speed or bus mode mismatch\n",
- __FUNCTION__);
+ __func__);
return WRONG_BUS_FREQUENCY;
}
rc = p_slot->hpc_ops->get_cur_bus_speed(p_slot, &bsp);
if (rc) {
- err("%s: Can't get bus operation speed\n", __FUNCTION__);
+ err("%s: Can't get bus operation speed\n", __func__);
return WRONG_BUS_FREQUENCY;
}
rc = p_slot->hpc_ops->get_max_bus_speed(p_slot, &msp);
if (rc) {
- err("%s: Can't get max bus operation speed\n", __FUNCTION__);
+ err("%s: Can't get max bus operation speed\n", __func__);
msp = bsp;
}
slots_not_empty = 1;
dbg("%s: slots_not_empty %d, adapter_speed %d, bus_speed %d, "
- "max_bus_speed %d\n", __FUNCTION__, slots_not_empty, asp,
+ "max_bus_speed %d\n", __func__, slots_not_empty, asp,
bsp, msp);
rc = fix_bus_speed(ctrl, p_slot, slots_not_empty, asp, bsp, msp);
/* turn on board, blink green LED, turn off Amber LED */
if ((rc = p_slot->hpc_ops->slot_enable(p_slot))) {
- err("%s: Issue of Slot Enable command failed\n", __FUNCTION__);
+ err("%s: Issue of Slot Enable command failed\n", __func__);
return rc;
}
/* Wait for ~1 second */
msleep(1000);
- dbg("%s: slot status = %x\n", __FUNCTION__, p_slot->status);
+ dbg("%s: slot status = %x\n", __func__, p_slot->status);
/* Check for a power fault */
if (p_slot->status == 0xFF) {
/* power fault occurred, but it was benign */
- dbg("%s: power fault\n", __FUNCTION__);
+ dbg("%s: power fault\n", __func__);
rc = POWER_FAILURE;
p_slot->status = 0;
goto err_exit;
/* turn off slot, turn on Amber LED, turn off Green LED */
rc = p_slot->hpc_ops->slot_disable(p_slot);
if (rc) {
- err("%s: Issue of Slot Disable command failed\n", __FUNCTION__);
+ err("%s: Issue of Slot Disable command failed\n", __func__);
return rc;
}
hp_slot = p_slot->device - ctrl->slot_device_offset;
p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
- dbg("In %s, hp_slot = %d\n", __FUNCTION__, hp_slot);
+ dbg("In %s, hp_slot = %d\n", __func__, hp_slot);
/* Change status to shutdown */
if (p_slot->is_a_board)
/* turn off slot, turn on Amber LED, turn off Green LED */
rc = p_slot->hpc_ops->slot_disable(p_slot);
if (rc) {
- err("%s: Issue of Slot Disable command failed\n", __FUNCTION__);
+ err("%s: Issue of Slot Disable command failed\n", __func__);
return rc;
}
rc = p_slot->hpc_ops->set_attention_status(p_slot, 0);
if (rc) {
- err("%s: Issue of Set Attention command failed\n", __FUNCTION__);
+ err("%s: Issue of Set Attention command failed\n", __func__);
return rc;
}
info = kmalloc(sizeof(*info), GFP_KERNEL);
if (!info) {
- err("%s: Cannot allocate memory\n", __FUNCTION__);
+ err("%s: Cannot allocate memory\n", __func__);
return;
}
info->p_slot = p_slot;
* expires to cancel hot-add or hot-remove
*/
info("Button cancel on Slot(%s)\n", p_slot->name);
- dbg("%s: button cancel\n", __FUNCTION__);
+ dbg("%s: button cancel\n", __func__);
cancel_delayed_work(&p_slot->work);
if (p_slot->state == BLINKINGOFF_STATE)
p_slot->hpc_ops->green_led_on(p_slot);
handle_button_press_event(p_slot);
break;
case INT_POWER_FAULT:
- dbg("%s: power fault\n", __FUNCTION__);
+ dbg("%s: power fault\n", __func__);
p_slot->hpc_ops->set_attention_status(p_slot, 1);
p_slot->hpc_ops->green_led_off(p_slot);
break;
/* We have to save the presence info for these slots */
p_slot->hpc_ops->get_adapter_status(p_slot, &(p_slot->presence_save));
p_slot->hpc_ops->get_power_status(p_slot, &(p_slot->pwr_save));
- dbg("%s: p_slot->pwr_save %x\n", __FUNCTION__, p_slot->pwr_save);
+ dbg("%s: p_slot->pwr_save %x\n", __func__, p_slot->pwr_save);
p_slot->hpc_ops->get_latch_status(p_slot, &getstatus);
if(((p_slot->ctrl->pci_dev->vendor == PCI_VENDOR_ID_AMD) ||
if (!shpc_poll_ctrl_busy(ctrl)) {
/* After 1 sec and and the controller is still busy */
err("%s : Controller is still busy after 1 sec.\n",
- __FUNCTION__);
+ __func__);
retval = -EBUSY;
goto out;
}
++t_slot;
temp_word = (t_slot << 8) | (cmd & 0xFF);
- dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
+ dbg("%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
/* To make sure the Controller Busy bit is 0 before we send out the
* command.
cmd_status = hpc_check_cmd_status(slot->ctrl);
if (cmd_status) {
err("%s: Failed to issued command 0x%x (error code = %d)\n",
- __FUNCTION__, cmd, cmd_status);
+ __func__, cmd, cmd_status);
retval = -EIO;
}
out:
break;
case 1:
retval = SWITCH_OPEN;
- err("%s: Switch opened!\n", __FUNCTION__);
+ err("%s: Switch opened!\n", __func__);
break;
case 2:
retval = INVALID_CMD;
- err("%s: Invalid HPC command!\n", __FUNCTION__);
+ err("%s: Invalid HPC command!\n", __func__);
break;
case 4:
retval = INVALID_SPEED_MODE;
- err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
+ err("%s: Invalid bus speed/mode!\n", __func__);
break;
default:
retval = cmd_status;
}
dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
- __FUNCTION__, slot_reg, pcix_cap, m66_cap);
+ __func__, slot_reg, pcix_cap, m66_cap);
switch (pcix_cap) {
case 0x0:
retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
if (retval)
- err("%s: Write command failed!\n", __FUNCTION__);
+ err("%s: Write command failed!\n", __func__);
return retval;
}
retval = shpc_write_cmd(slot, slot->hp_slot,
SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
if (retval)
- err("%s: Write command failed!\n", __FUNCTION__);
+ err("%s: Write command failed!\n", __func__);
return retval;
}
retval = shpc_write_cmd(slot, slot->hp_slot,
SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
if (retval)
- err("%s: Write command failed!\n", __FUNCTION__);
+ err("%s: Write command failed!\n", __func__);
return retval;
}
retval = shpc_write_cmd(slot, 0, cmd);
if (retval)
- err("%s: Write command failed!\n", __FUNCTION__);
+ err("%s: Write command failed!\n", __func__);
return retval;
}
if (!intr_loc)
return IRQ_NONE;
- dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
+ dbg("%s: intr_loc = %x\n",__func__, intr_loc);
if(!shpchp_poll_mode) {
/*
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
intr_loc2 = shpc_readl(ctrl, INTR_LOC);
- dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
+ dbg("%s: intr_loc2 = %x\n",__func__, intr_loc2);
}
if (intr_loc & CMD_INTR_PENDING) {
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
dbg("%s: Slot %x with intr, slot register = %x\n",
- __FUNCTION__, hp_slot, slot_reg);
+ __func__, hp_slot, slot_reg);
if (slot_reg & MRL_CHANGE_DETECTED)
shpchp_handle_switch_change(hp_slot, ctrl);
} else {
ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
if (!ctrl->cap_offset) {
- err("%s : cap_offset == 0\n", __FUNCTION__);
+ err("%s : cap_offset == 0\n", __func__);
goto abort;
}
- dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
+ dbg("%s: cap_offset = %x\n", __func__, ctrl->cap_offset);
rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
if (rc) {
- err("%s: cannot read base_offset\n", __FUNCTION__);
+ err("%s: cannot read base_offset\n", __func__);
goto abort;
}
rc = shpc_indirect_read(ctrl, 3, &tempdword);
if (rc) {
- err("%s: cannot read slot config\n", __FUNCTION__);
+ err("%s: cannot read slot config\n", __func__);
goto abort;
}
num_slots = tempdword & SLOT_NUM;
- dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
+ dbg("%s: num_slots (indirect) %x\n", __func__, num_slots);
for (i = 0; i < 9 + num_slots; i++) {
rc = shpc_indirect_read(ctrl, i, &tempdword);
if (rc) {
err("%s: cannot read creg (index = %d)\n",
- __FUNCTION__, i);
+ __func__, i);
goto abort;
}
- dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
+ dbg("%s: offset %d: value %x\n", __func__,i,
tempdword);
}
rc = pci_enable_device(pdev);
if (rc) {
- err("%s: pci_enable_device failed\n", __FUNCTION__);
+ err("%s: pci_enable_device failed\n", __func__);
goto abort;
}
if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
- err("%s: cannot reserve MMIO region\n", __FUNCTION__);
+ err("%s: cannot reserve MMIO region\n", __func__);
rc = -1;
goto abort;
}
ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
if (!ctrl->creg) {
- err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
+ err("%s: cannot remap MMIO region %lx @ %lx\n", __func__,
ctrl->mmio_size, ctrl->mmio_base);
release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
rc = -1;
goto abort;
}
- dbg("%s: ctrl->creg %p\n", __FUNCTION__, ctrl->creg);
+ dbg("%s: ctrl->creg %p\n", __func__, ctrl->creg);
mutex_init(&ctrl->crit_sect);
mutex_init(&ctrl->cmd_lock);
/* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
- dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
+ dbg("%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword);
tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
COMMAND_INTR_MASK | ARBITER_SERR_MASK);
tempdword &= ~SERR_INTR_RSVDZ_MASK;
shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
- dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
+ dbg("%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword);
/* Mask the MRL sensor SERR Mask of individual slot in
* Slot SERR-INT Mask & clear all the existing event if any
*/
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
- dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
+ dbg("%s: Default Logical Slot Register %d value %x\n", __func__,
hp_slot, slot_reg);
slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
MY_NAME, (void *)ctrl);
dbg("%s: request_irq %d for hpc%d (returns %d)\n",
- __FUNCTION__, ctrl->pci_dev->irq,
+ __func__, ctrl->pci_dev->irq,
atomic_read(&shpchp_num_controllers), rc);
if (rc) {
err("Can't get irq %d for the hotplug controller\n",
goto abort_iounmap;
}
}
- dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
+ dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __func__,
pdev->bus->number, PCI_SLOT(pdev->devfn),
PCI_FUNC(pdev->devfn), pdev->irq);
get_hp_hw_control_from_firmware(pdev);
*/
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
- dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
+ dbg("%s: Default Logical Slot Register %d value %x\n", __func__,
hp_slot, slot_reg);
slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
SERR_INTR_RSVDZ_MASK);
shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
- dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
+ dbg("%s: SERR_INTR_ENABLE = %x\n", __func__, tempdword);
}
return 0;
!hpp.t0 || (hpp.t0->revision > 1)) {
printk(KERN_WARNING
"%s: Could not get hotplug parameters. Use defaults\n",
- __FUNCTION__);
+ __func__);
hpp.t0 = &hpp.type0_data;
hpp.t0->revision = 0;
hpp.t0->cache_line_size = 8;
u8 bctl = 0;
struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
- dbg("%s: bus/dev = %x/%x\n", __FUNCTION__, p_slot->bus, p_slot->device);
+ dbg("%s: bus/dev = %x/%x\n", __func__, p_slot->bus, p_slot->device);
for (j=0; j<8 ; j++) {
struct pci_dev* temp = pci_get_slot(parent,
#include <linux/init.h>
#include <linux/bitmap.h>
+#include <linux/debugfs.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/dmar.h>
#include <linux/dma-mapping.h>
#include <linux/mempool.h>
+#include <linux/timer.h>
#include "iova.h"
#include "intel-iommu.h"
#include <asm/proto.h> /* force_iommu in this header in x86-64*/
#define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
+
+static void flush_unmaps_timeout(unsigned long data);
+
+DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
+
+static struct intel_iommu *g_iommus;
+
+#define HIGH_WATER_MARK 250
+struct deferred_flush_tables {
+ int next;
+ struct iova *iova[HIGH_WATER_MARK];
+ struct dmar_domain *domain[HIGH_WATER_MARK];
+};
+
+static struct deferred_flush_tables *deferred_flush;
+
+/* bitmap for indexing intel_iommus */
+static int g_num_of_iommus;
+
+static DEFINE_SPINLOCK(async_umap_flush_lock);
+static LIST_HEAD(unmaps_to_do);
+
+static int timer_on;
+static long list_size;
+
static void domain_remove_dev_info(struct dmar_domain *domain);
static int dmar_disabled;
static int __initdata dmar_map_gfx = 1;
static int dmar_forcedac;
+static int intel_iommu_strict;
#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
static DEFINE_SPINLOCK(device_domain_lock);
printk(KERN_INFO
"Intel-IOMMU: disable GFX device mapping\n");
} else if (!strncmp(str, "forcedac", 8)) {
- printk (KERN_INFO
+ printk(KERN_INFO
"Intel-IOMMU: Forcing DAC for PCI devices\n");
dmar_forcedac = 1;
+ } else if (!strncmp(str, "strict", 6)) {
+ printk(KERN_INFO
+ "Intel-IOMMU: disable batched IOTLB flush\n");
+ intel_iommu_strict = 1;
}
str += strcspn(str, ",");
set_bit(0, iommu->domain_ids);
return 0;
}
-
-static struct intel_iommu *alloc_iommu(struct dmar_drhd_unit *drhd)
+static struct intel_iommu *alloc_iommu(struct intel_iommu *iommu,
+ struct dmar_drhd_unit *drhd)
{
- struct intel_iommu *iommu;
int ret;
int map_size;
u32 ver;
- iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
- if (!iommu)
- return NULL;
iommu->reg = ioremap(drhd->reg_base_addr, PAGE_SIZE_4K);
if (!iommu->reg) {
printk(KERN_ERR "IOMMU: can't map the region\n");
int index;
while (dev) {
- for (index = 0; index < cnt; index ++)
+ for (index = 0; index < cnt; index++)
if (dev == devices[index])
return 1;
struct dmar_rmrr_unit *rmrr;
struct pci_dev *pdev;
struct intel_iommu *iommu;
- int ret, unit = 0;
+ int i, ret, unit = 0;
/*
* for each drhd
for_each_drhd_unit(drhd) {
if (drhd->ignored)
continue;
- iommu = alloc_iommu(drhd);
+ g_num_of_iommus++;
+ /*
+ * lock not needed as this is only incremented in the single
+ * threaded kernel __init code path all other access are read
+ * only
+ */
+ }
+
+ g_iommus = kzalloc(g_num_of_iommus * sizeof(*iommu), GFP_KERNEL);
+ if (!g_iommus) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ deferred_flush = kzalloc(g_num_of_iommus *
+ sizeof(struct deferred_flush_tables), GFP_KERNEL);
+ if (!deferred_flush) {
+ kfree(g_iommus);
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ i = 0;
+ for_each_drhd_unit(drhd) {
+ if (drhd->ignored)
+ continue;
+ iommu = alloc_iommu(&g_iommus[i], drhd);
+ i++;
if (!iommu) {
ret = -ENOMEM;
goto error;
* endfor
*/
for_each_rmrr_units(rmrr) {
- int i;
for (i = 0; i < rmrr->devices_cnt; i++) {
pdev = rmrr->devices[i];
/* some BIOS lists non-exist devices in DMAR table */
iommu = drhd->iommu;
free_iommu(iommu);
}
+ kfree(g_iommus);
return ret;
}
return 0;
}
+static void flush_unmaps(void)
+{
+ int i, j;
+
+ timer_on = 0;
+
+ /* just flush them all */
+ for (i = 0; i < g_num_of_iommus; i++) {
+ if (deferred_flush[i].next) {
+ iommu_flush_iotlb_global(&g_iommus[i], 0);
+ for (j = 0; j < deferred_flush[i].next; j++) {
+ __free_iova(&deferred_flush[i].domain[j]->iovad,
+ deferred_flush[i].iova[j]);
+ }
+ deferred_flush[i].next = 0;
+ }
+ }
+
+ list_size = 0;
+}
+
+static void flush_unmaps_timeout(unsigned long data)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&async_umap_flush_lock, flags);
+ flush_unmaps();
+ spin_unlock_irqrestore(&async_umap_flush_lock, flags);
+}
+
+static void add_unmap(struct dmar_domain *dom, struct iova *iova)
+{
+ unsigned long flags;
+ int next, iommu_id;
+
+ spin_lock_irqsave(&async_umap_flush_lock, flags);
+ if (list_size == HIGH_WATER_MARK)
+ flush_unmaps();
+
+ iommu_id = dom->iommu - g_iommus;
+ next = deferred_flush[iommu_id].next;
+ deferred_flush[iommu_id].domain[next] = dom;
+ deferred_flush[iommu_id].iova[next] = iova;
+ deferred_flush[iommu_id].next++;
+
+ if (!timer_on) {
+ mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
+ timer_on = 1;
+ }
+ list_size++;
+ spin_unlock_irqrestore(&async_umap_flush_lock, flags);
+}
+
static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr,
size_t size, int dir)
{
dma_pte_clear_range(domain, start_addr, start_addr + size);
/* free page tables */
dma_pte_free_pagetable(domain, start_addr, start_addr + size);
-
- if (iommu_flush_iotlb_psi(domain->iommu, domain->id, start_addr,
- size >> PAGE_SHIFT_4K, 0))
- iommu_flush_write_buffer(domain->iommu);
-
- /* free iova */
- __free_iova(&domain->iovad, iova);
+ if (intel_iommu_strict) {
+ if (iommu_flush_iotlb_psi(domain->iommu,
+ domain->id, start_addr, size >> PAGE_SHIFT_4K, 0))
+ iommu_flush_write_buffer(domain->iommu);
+ /* free iova */
+ __free_iova(&domain->iovad, iova);
+ } else {
+ add_unmap(domain, iova);
+ /*
+ * queue up the release of the unmap to save the 1/6th of the
+ * cpu used up by the iotlb flush operation...
+ */
+ }
}
static void * intel_alloc_coherent(struct device *hwdev, size_t size,
printk(KERN_INFO
"PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
+ init_timer(&unmap_timer);
force_iommu = 1;
dma_ops = &intel_dma_ops;
return 0;
return pad_size;
}
-static int __alloc_iova_range(struct iova_domain *iovad, unsigned long size,
- unsigned long limit_pfn, struct iova *new, bool size_aligned)
+static int __alloc_and_insert_iova_range(struct iova_domain *iovad,
+ unsigned long size, unsigned long limit_pfn,
+ struct iova *new, bool size_aligned)
{
- struct rb_node *curr = NULL;
+ struct rb_node *prev, *curr = NULL;
unsigned long flags;
unsigned long saved_pfn;
unsigned int pad_size = 0;
spin_lock_irqsave(&iovad->iova_rbtree_lock, flags);
saved_pfn = limit_pfn;
curr = __get_cached_rbnode(iovad, &limit_pfn);
+ prev = curr;
while (curr) {
struct iova *curr_iova = container_of(curr, struct iova, node);
+
if (limit_pfn < curr_iova->pfn_lo)
goto move_left;
else if (limit_pfn < curr_iova->pfn_hi)
adjust_limit_pfn:
limit_pfn = curr_iova->pfn_lo - 1;
move_left:
+ prev = curr;
curr = rb_prev(curr);
}
new->pfn_lo = limit_pfn - (size + pad_size) + 1;
new->pfn_hi = new->pfn_lo + size - 1;
+ /* Insert the new_iova into domain rbtree by holding writer lock */
+ /* Add new node and rebalance tree. */
+ {
+ struct rb_node **entry = &((prev)), *parent = NULL;
+ /* Figure out where to put new node */
+ while (*entry) {
+ struct iova *this = container_of(*entry,
+ struct iova, node);
+ parent = *entry;
+
+ if (new->pfn_lo < this->pfn_lo)
+ entry = &((*entry)->rb_left);
+ else if (new->pfn_lo > this->pfn_lo)
+ entry = &((*entry)->rb_right);
+ else
+ BUG(); /* this should not happen */
+ }
+
+ /* Add new node and rebalance tree. */
+ rb_link_node(&new->node, parent, entry);
+ rb_insert_color(&new->node, &iovad->rbroot);
+ }
+ __cached_rbnode_insert_update(iovad, saved_pfn, new);
+
spin_unlock_irqrestore(&iovad->iova_rbtree_lock, flags);
+
+
return 0;
}
size = __roundup_pow_of_two(size);
spin_lock_irqsave(&iovad->iova_alloc_lock, flags);
- ret = __alloc_iova_range(iovad, size, limit_pfn, new_iova,
- size_aligned);
+ ret = __alloc_and_insert_iova_range(iovad, size, limit_pfn,
+ new_iova, size_aligned);
+ spin_unlock_irqrestore(&iovad->iova_alloc_lock, flags);
if (ret) {
- spin_unlock_irqrestore(&iovad->iova_alloc_lock, flags);
free_iova_mem(new_iova);
return NULL;
}
- /* Insert the new_iova into domain rbtree by holding writer lock */
- spin_lock(&iovad->iova_rbtree_lock);
- iova_insert_rbtree(&iovad->rbroot, new_iova);
- __cached_rbnode_insert_update(iovad, limit_pfn, new_iova);
- spin_unlock(&iovad->iova_rbtree_lock);
-
- spin_unlock_irqrestore(&iovad->iova_alloc_lock, flags);
-
return new_iova;
}
struct mempolicy *oldpol;
cpumask_t oldmask = current->cpus_allowed;
int node = pcibus_to_node(dev->bus);
- if (node >= 0 && node_online(node))
- set_cpus_allowed(current, node_to_cpumask(node));
+
+ if (node >= 0) {
+ node_to_cpumask_ptr(nodecpumask, node);
+ set_cpus_allowed_ptr(current, nodecpumask);
+ }
/* And set default memory allocation policy */
oldpol = current->mempolicy;
current->mempolicy = NULL; /* fall back to system default policy */
#endif
error = drv->probe(dev, id);
#ifdef CONFIG_NUMA
- set_cpus_allowed(current, oldmask);
+ set_cpus_allowed_ptr(current, &oldmask);
current->mempolicy = oldpol;
#endif
return error;
#include <linux/topology.h>
#include <linux/mm.h>
#include <linux/capability.h>
+#include <linux/pci-aspm.h>
#include "pci.h"
static int sysfs_initialized; /* = 0 */
mask = pcibus_to_cpumask(to_pci_dev(dev)->bus);
len = cpumask_scnprintf(buf, PAGE_SIZE-2, mask);
- strcat(buf,"\n");
- return 1+len;
+ buf[len++] = '\n';
+ buf[len] = '\0';
+ return len;
+}
+
+
+static ssize_t local_cpulist_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ cpumask_t mask;
+ int len;
+
+ mask = pcibus_to_cpumask(to_pci_dev(dev)->bus);
+ len = cpulist_scnprintf(buf, PAGE_SIZE-2, mask);
+ buf[len++] = '\n';
+ buf[len] = '\0';
+ return len;
}
/* show resources */
__ATTR_RO(class),
__ATTR_RO(irq),
__ATTR_RO(local_cpus),
+ __ATTR_RO(local_cpulist),
__ATTR_RO(modalias),
#ifdef CONFIG_NUMA
__ATTR_RO(numa_node),
return count;
}
+static ssize_t
+pci_read_vpd(struct kobject *kobj, struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ struct pci_dev *dev =
+ to_pci_dev(container_of(kobj, struct device, kobj));
+ int end;
+ int ret;
+
+ if (off > bin_attr->size)
+ count = 0;
+ else if (count > bin_attr->size - off)
+ count = bin_attr->size - off;
+ end = off + count;
+
+ while (off < end) {
+ ret = dev->vpd->ops->read(dev, off, end - off, buf);
+ if (ret < 0)
+ return ret;
+ buf += ret;
+ off += ret;
+ }
+
+ return count;
+}
+
+static ssize_t
+pci_write_vpd(struct kobject *kobj, struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ struct pci_dev *dev =
+ to_pci_dev(container_of(kobj, struct device, kobj));
+ int end;
+ int ret;
+
+ if (off > bin_attr->size)
+ count = 0;
+ else if (count > bin_attr->size - off)
+ count = bin_attr->size - off;
+ end = off + count;
+
+ while (off < end) {
+ ret = dev->vpd->ops->write(dev, off, end - off, buf);
+ if (ret < 0)
+ return ret;
+ buf += ret;
+ off += ret;
+ }
+
+ return count;
+}
+
#ifdef HAVE_PCI_LEGACY
/**
* pci_read_legacy_io - read byte(s) from legacy I/O port space
int __must_check pci_create_sysfs_dev_files (struct pci_dev *pdev)
{
- struct bin_attribute *rom_attr = NULL;
+ struct bin_attribute *attr = NULL;
int retval;
if (!sysfs_initialized)
if (retval)
goto err;
+ /* If the device has VPD, try to expose it in sysfs. */
+ if (pdev->vpd) {
+ attr = kzalloc(sizeof(*attr), GFP_ATOMIC);
+ if (attr) {
+ pdev->vpd->attr = attr;
+ attr->size = pdev->vpd->ops->get_size(pdev);
+ attr->attr.name = "vpd";
+ attr->attr.mode = S_IRUGO | S_IWUSR;
+ attr->read = pci_read_vpd;
+ attr->write = pci_write_vpd;
+ retval = sysfs_create_bin_file(&pdev->dev.kobj, attr);
+ if (retval)
+ goto err_vpd;
+ } else {
+ retval = -ENOMEM;
+ goto err_config_file;
+ }
+ }
+
retval = pci_create_resource_files(pdev);
if (retval)
- goto err_bin_file;
+ goto err_vpd_file;
/* If the device has a ROM, try to expose it in sysfs. */
if (pci_resource_len(pdev, PCI_ROM_RESOURCE) ||
(pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW)) {
- rom_attr = kzalloc(sizeof(*rom_attr), GFP_ATOMIC);
- if (rom_attr) {
- pdev->rom_attr = rom_attr;
- rom_attr->size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
- rom_attr->attr.name = "rom";
- rom_attr->attr.mode = S_IRUSR;
- rom_attr->read = pci_read_rom;
- rom_attr->write = pci_write_rom;
- retval = sysfs_create_bin_file(&pdev->dev.kobj, rom_attr);
+ attr = kzalloc(sizeof(*attr), GFP_ATOMIC);
+ if (attr) {
+ pdev->rom_attr = attr;
+ attr->size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
+ attr->attr.name = "rom";
+ attr->attr.mode = S_IRUSR;
+ attr->read = pci_read_rom;
+ attr->write = pci_write_rom;
+ retval = sysfs_create_bin_file(&pdev->dev.kobj, attr);
if (retval)
goto err_rom;
} else {
if (pcibios_add_platform_entries(pdev))
goto err_rom_file;
+ pcie_aspm_create_sysfs_dev_files(pdev);
+
return 0;
err_rom_file:
if (pci_resource_len(pdev, PCI_ROM_RESOURCE))
- sysfs_remove_bin_file(&pdev->dev.kobj, rom_attr);
+ sysfs_remove_bin_file(&pdev->dev.kobj, pdev->rom_attr);
err_rom:
- kfree(rom_attr);
+ kfree(pdev->rom_attr);
err_resource_files:
pci_remove_resource_files(pdev);
-err_bin_file:
+err_vpd_file:
+ if (pdev->vpd) {
+ sysfs_remove_bin_file(&pdev->dev.kobj, pdev->vpd->attr);
+err_vpd:
+ kfree(pdev->vpd->attr);
+ }
+err_config_file:
if (pdev->cfg_size < 4096)
sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr);
else
if (!sysfs_initialized)
return;
+ pcie_aspm_remove_sysfs_dev_files(pdev);
+
+ if (pdev->vpd) {
+ sysfs_remove_bin_file(&pdev->dev.kobj, pdev->vpd->attr);
+ kfree(pdev->vpd->attr);
+ }
if (pdev->cfg_size < 4096)
sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr);
else
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/log2.h>
+#include <linux/pci-aspm.h>
#include <asm/dma.h> /* isa_dma_bridge_buggy */
#include "pci.h"
*/
if (state != PCI_D0 && dev->current_state > state) {
printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
- __FUNCTION__, pci_name(dev), state, dev->current_state);
+ __func__, pci_name(dev), state, dev->current_state);
return -EINVAL;
} else if (dev->current_state == state)
return 0; /* we're already there */
if (need_restore)
pci_restore_bars(dev);
+ if (dev->bus->self)
+ pcie_aspm_pm_state_change(dev->bus->self);
+
return 0;
}
extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
+struct pci_vpd_ops {
+ int (*read)(struct pci_dev *dev, int pos, int size, char *buf);
+ int (*write)(struct pci_dev *dev, int pos, int size, const char *buf);
+ int (*get_size)(struct pci_dev *dev);
+ void (*release)(struct pci_dev *dev);
+};
+
+struct pci_vpd {
+ struct pci_vpd_ops *ops;
+ struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
+};
+
+extern int pci_vpd_pci22_init(struct pci_dev *dev);
+static inline void pci_vpd_release(struct pci_dev *dev)
+{
+ if (dev->vpd)
+ dev->vpd->ops->release(dev);
+}
+
/* PCI /proc functions */
#ifdef CONFIG_PROC_FS
extern int pci_proc_attach_device(struct pci_dev *dev);
When in doubt, say N.
source "drivers/pci/pcie/aer/Kconfig"
+
+#
+# PCI Express ASPM
+#
+config PCIEASPM
+ bool "PCI Express ASPM support(Experimental)"
+ depends on PCI && EXPERIMENTAL && PCIEPORTBUS
+ default y
+ help
+ This enables PCI Express ASPM (Active State Power Management) and
+ Clock Power Management. ASPM supports state L0/L0s/L1.
+
+ When in doubt, say N.
+config PCIEASPM_DEBUG
+ bool "Debug PCI Express ASPM"
+ depends on PCIEASPM
+ default n
+ help
+ This enables PCI Express ASPM debug support. It will add per-device
+ interface to control ASPM.
# Makefile for PCI-Express PORT Driver
#
+# Build PCI Express ASPM if needed
+obj-$(CONFIG_PCIEASPM) += aspm.o
+
pcieportdrv-y := portdrv_core.o portdrv_pci.o portdrv_bus.o
obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o
/* Alloc rpc data structure */
if (!(rpc = aer_alloc_rpc(dev))) {
printk(KERN_DEBUG "%s: Alloc rpc fails on PCIE device[%s]\n",
- __FUNCTION__, device->bus_id);
+ __func__, device->bus_id);
aer_remove(dev);
return -ENOMEM;
}
if ((status = request_irq(dev->irq, aer_irq, IRQF_SHARED, "aerdrv",
dev))) {
printk(KERN_DEBUG "%s: Request ISR fails on PCIE device[%s]\n",
- __FUNCTION__, device->bus_id);
+ __func__, device->bus_id);
aer_remove(dev);
return status;
}
struct pci_dev *pdev = pciedev->port;
acpi_handle handle = 0;
+ if (acpi_pci_disabled)
+ return -1;
+
/* Find root host bridge */
- while (pdev->bus && pdev->bus->self)
+ while (pdev->bus->self)
pdev = pdev->bus->self;
handle = acpi_get_pci_rootbridge_handle(
pci_domain_nr(pdev->bus), pdev->bus->number);
return 0;
}
+#if 0
int pci_cleanup_aer_correct_error_status(struct pci_dev *dev)
{
int pos;
return 0;
}
+#endif /* 0 */
static int find_device_iter(struct device *device, void *data)
{
e_info.flags |= AER_MULTI_ERROR_VALID_FLAG;
if (!(s_device = find_source_device(p_device->port, id))) {
printk(KERN_DEBUG "%s->can't find device of ID%04x\n",
- __FUNCTION__, id);
+ __func__, id);
continue;
}
if (get_device_error_info(to_pci_dev(s_device), &e_info) ==
EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
EXPORT_SYMBOL_GPL(pci_cleanup_aer_uncorrect_error_status);
-EXPORT_SYMBOL_GPL(pci_cleanup_aer_correct_error_status);
--- /dev/null
+/*
+ * File: drivers/pci/pcie/aspm.c
+ * Enabling PCIE link L0s/L1 state and Clock Power Management
+ *
+ * Copyright (C) 2007 Intel
+ * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
+ * Copyright (C) Shaohua Li (shaohua.li@intel.com)
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/pci.h>
+#include <linux/pci_regs.h>
+#include <linux/errno.h>
+#include <linux/pm.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/pci-aspm.h>
+#include "../pci.h"
+
+#ifdef MODULE_PARAM_PREFIX
+#undef MODULE_PARAM_PREFIX
+#endif
+#define MODULE_PARAM_PREFIX "pcie_aspm."
+
+struct endpoint_state {
+ unsigned int l0s_acceptable_latency;
+ unsigned int l1_acceptable_latency;
+};
+
+struct pcie_link_state {
+ struct list_head sibiling;
+ struct pci_dev *pdev;
+
+ /* ASPM state */
+ unsigned int support_state;
+ unsigned int enabled_state;
+ unsigned int bios_aspm_state;
+ /* upstream component */
+ unsigned int l0s_upper_latency;
+ unsigned int l1_upper_latency;
+ /* downstream component */
+ unsigned int l0s_down_latency;
+ unsigned int l1_down_latency;
+ /* Clock PM state*/
+ unsigned int clk_pm_capable;
+ unsigned int clk_pm_enabled;
+ unsigned int bios_clk_state;
+
+ /*
+ * A pcie downstream port only has one slot under it, so at most there
+ * are 8 functions
+ */
+ struct endpoint_state endpoints[8];
+};
+
+static int aspm_disabled;
+static DEFINE_MUTEX(aspm_lock);
+static LIST_HEAD(link_list);
+
+#define POLICY_DEFAULT 0 /* BIOS default setting */
+#define POLICY_PERFORMANCE 1 /* high performance */
+#define POLICY_POWERSAVE 2 /* high power saving */
+static int aspm_policy;
+static const char *policy_str[] = {
+ [POLICY_DEFAULT] = "default",
+ [POLICY_PERFORMANCE] = "performance",
+ [POLICY_POWERSAVE] = "powersave"
+};
+
+static int policy_to_aspm_state(struct pci_dev *pdev)
+{
+ struct pcie_link_state *link_state = pdev->link_state;
+
+ switch (aspm_policy) {
+ case POLICY_PERFORMANCE:
+ /* Disable ASPM and Clock PM */
+ return 0;
+ case POLICY_POWERSAVE:
+ /* Enable ASPM L0s/L1 */
+ return PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1;
+ case POLICY_DEFAULT:
+ return link_state->bios_aspm_state;
+ }
+ return 0;
+}
+
+static int policy_to_clkpm_state(struct pci_dev *pdev)
+{
+ struct pcie_link_state *link_state = pdev->link_state;
+
+ switch (aspm_policy) {
+ case POLICY_PERFORMANCE:
+ /* Disable ASPM and Clock PM */
+ return 0;
+ case POLICY_POWERSAVE:
+ /* Disable Clock PM */
+ return 1;
+ case POLICY_DEFAULT:
+ return link_state->bios_clk_state;
+ }
+ return 0;
+}
+
+static void pcie_set_clock_pm(struct pci_dev *pdev, int enable)
+{
+ struct pci_dev *child_dev;
+ int pos;
+ u16 reg16;
+ struct pcie_link_state *link_state = pdev->link_state;
+
+ list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
+ pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
+ if (!pos)
+ return;
+ pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, ®16);
+ if (enable)
+ reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
+ else
+ reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
+ pci_write_config_word(child_dev, pos + PCI_EXP_LNKCTL, reg16);
+ }
+ link_state->clk_pm_enabled = !!enable;
+}
+
+static void pcie_check_clock_pm(struct pci_dev *pdev)
+{
+ int pos;
+ u32 reg32;
+ u16 reg16;
+ int capable = 1, enabled = 1;
+ struct pci_dev *child_dev;
+ struct pcie_link_state *link_state = pdev->link_state;
+
+ /* All functions should have the same cap and state, take the worst */
+ list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
+ pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
+ if (!pos)
+ return;
+ pci_read_config_dword(child_dev, pos + PCI_EXP_LNKCAP, ®32);
+ if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
+ capable = 0;
+ enabled = 0;
+ break;
+ }
+ pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, ®16);
+ if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
+ enabled = 0;
+ }
+ link_state->clk_pm_capable = capable;
+ link_state->clk_pm_enabled = enabled;
+ link_state->bios_clk_state = enabled;
+ pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev));
+}
+
+/*
+ * pcie_aspm_configure_common_clock: check if the 2 ends of a link
+ * could use common clock. If they are, configure them to use the
+ * common clock. That will reduce the ASPM state exit latency.
+ */
+static void pcie_aspm_configure_common_clock(struct pci_dev *pdev)
+{
+ int pos, child_pos;
+ u16 reg16 = 0;
+ struct pci_dev *child_dev;
+ int same_clock = 1;
+
+ /*
+ * all functions of a slot should have the same Slot Clock
+ * Configuration, so just check one function
+ * */
+ child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev,
+ bus_list);
+ BUG_ON(!child_dev->is_pcie);
+
+ /* Check downstream component if bit Slot Clock Configuration is 1 */
+ child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
+ pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKSTA, ®16);
+ if (!(reg16 & PCI_EXP_LNKSTA_SLC))
+ same_clock = 0;
+
+ /* Check upstream component if bit Slot Clock Configuration is 1 */
+ pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+ pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16);
+ if (!(reg16 & PCI_EXP_LNKSTA_SLC))
+ same_clock = 0;
+
+ /* Configure downstream component, all functions */
+ list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
+ child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
+ pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKCTL,
+ ®16);
+ if (same_clock)
+ reg16 |= PCI_EXP_LNKCTL_CCC;
+ else
+ reg16 &= ~PCI_EXP_LNKCTL_CCC;
+ pci_write_config_word(child_dev, child_pos + PCI_EXP_LNKCTL,
+ reg16);
+ }
+
+ /* Configure upstream component */
+ pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
+ if (same_clock)
+ reg16 |= PCI_EXP_LNKCTL_CCC;
+ else
+ reg16 &= ~PCI_EXP_LNKCTL_CCC;
+ pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
+
+ /* retrain link */
+ reg16 |= PCI_EXP_LNKCTL_RL;
+ pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
+
+ /* Wait for link training end */
+ while (1) {
+ pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16);
+ if (!(reg16 & PCI_EXP_LNKSTA_LT))
+ break;
+ cpu_relax();
+ }
+}
+
+/*
+ * calc_L0S_latency: Convert L0s latency encoding to ns
+ */
+static unsigned int calc_L0S_latency(unsigned int latency_encoding, int ac)
+{
+ unsigned int ns = 64;
+
+ if (latency_encoding == 0x7) {
+ if (ac)
+ ns = -1U;
+ else
+ ns = 5*1000; /* > 4us */
+ } else
+ ns *= (1 << latency_encoding);
+ return ns;
+}
+
+/*
+ * calc_L1_latency: Convert L1 latency encoding to ns
+ */
+static unsigned int calc_L1_latency(unsigned int latency_encoding, int ac)
+{
+ unsigned int ns = 1000;
+
+ if (latency_encoding == 0x7) {
+ if (ac)
+ ns = -1U;
+ else
+ ns = 65*1000; /* > 64us */
+ } else
+ ns *= (1 << latency_encoding);
+ return ns;
+}
+
+static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state,
+ unsigned int *l0s, unsigned int *l1, unsigned int *enabled)
+{
+ int pos;
+ u16 reg16;
+ u32 reg32;
+ unsigned int latency;
+
+ pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+ pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32);
+ *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
+ if (*state != PCIE_LINK_STATE_L0S &&
+ *state != (PCIE_LINK_STATE_L1|PCIE_LINK_STATE_L0S))
+ *state = 0;
+ if (*state == 0)
+ return;
+
+ latency = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
+ *l0s = calc_L0S_latency(latency, 0);
+ if (*state & PCIE_LINK_STATE_L1) {
+ latency = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
+ *l1 = calc_L1_latency(latency, 0);
+ }
+ pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
+ *enabled = reg16 & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1);
+}
+
+static void pcie_aspm_cap_init(struct pci_dev *pdev)
+{
+ struct pci_dev *child_dev;
+ u32 state, tmp;
+ struct pcie_link_state *link_state = pdev->link_state;
+
+ /* upstream component states */
+ pcie_aspm_get_cap_device(pdev, &link_state->support_state,
+ &link_state->l0s_upper_latency,
+ &link_state->l1_upper_latency,
+ &link_state->enabled_state);
+ /* downstream component states, all functions have the same setting */
+ child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev,
+ bus_list);
+ pcie_aspm_get_cap_device(child_dev, &state,
+ &link_state->l0s_down_latency,
+ &link_state->l1_down_latency,
+ &tmp);
+ link_state->support_state &= state;
+ if (!link_state->support_state)
+ return;
+ link_state->enabled_state &= link_state->support_state;
+ link_state->bios_aspm_state = link_state->enabled_state;
+
+ /* ENDPOINT states*/
+ list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
+ int pos;
+ u32 reg32;
+ unsigned int latency;
+ struct endpoint_state *ep_state =
+ &link_state->endpoints[PCI_FUNC(child_dev->devfn)];
+
+ if (child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
+ child_dev->pcie_type != PCI_EXP_TYPE_LEG_END)
+ continue;
+
+ pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
+ pci_read_config_dword(child_dev, pos + PCI_EXP_DEVCAP, ®32);
+ latency = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
+ latency = calc_L0S_latency(latency, 1);
+ ep_state->l0s_acceptable_latency = latency;
+ if (link_state->support_state & PCIE_LINK_STATE_L1) {
+ latency = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
+ latency = calc_L1_latency(latency, 1);
+ ep_state->l1_acceptable_latency = latency;
+ }
+ }
+}
+
+static unsigned int __pcie_aspm_check_state_one(struct pci_dev *pdev,
+ unsigned int state)
+{
+ struct pci_dev *parent_dev, *tmp_dev;
+ unsigned int latency, l1_latency = 0;
+ struct pcie_link_state *link_state;
+ struct endpoint_state *ep_state;
+
+ parent_dev = pdev->bus->self;
+ link_state = parent_dev->link_state;
+ state &= link_state->support_state;
+ if (state == 0)
+ return 0;
+ ep_state = &link_state->endpoints[PCI_FUNC(pdev->devfn)];
+
+ /*
+ * Check latency for endpoint device.
+ * TBD: The latency from the endpoint to root complex vary per
+ * switch's upstream link state above the device. Here we just do a
+ * simple check which assumes all links above the device can be in L1
+ * state, that is we just consider the worst case. If switch's upstream
+ * link can't be put into L0S/L1, then our check is too strictly.
+ */
+ tmp_dev = pdev;
+ while (state & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
+ parent_dev = tmp_dev->bus->self;
+ link_state = parent_dev->link_state;
+ if (state & PCIE_LINK_STATE_L0S) {
+ latency = max_t(unsigned int,
+ link_state->l0s_upper_latency,
+ link_state->l0s_down_latency);
+ if (latency > ep_state->l0s_acceptable_latency)
+ state &= ~PCIE_LINK_STATE_L0S;
+ }
+ if (state & PCIE_LINK_STATE_L1) {
+ latency = max_t(unsigned int,
+ link_state->l1_upper_latency,
+ link_state->l1_down_latency);
+ if (latency + l1_latency >
+ ep_state->l1_acceptable_latency)
+ state &= ~PCIE_LINK_STATE_L1;
+ }
+ if (!parent_dev->bus->self) /* parent_dev is a root port */
+ break;
+ else {
+ /*
+ * parent_dev is the downstream port of a switch, make
+ * tmp_dev the upstream port of the switch
+ */
+ tmp_dev = parent_dev->bus->self;
+ /*
+ * every switch on the path to root complex need 1 more
+ * microsecond for L1. Spec doesn't mention L0S.
+ */
+ if (state & PCIE_LINK_STATE_L1)
+ l1_latency += 1000;
+ }
+ }
+ return state;
+}
+
+static unsigned int pcie_aspm_check_state(struct pci_dev *pdev,
+ unsigned int state)
+{
+ struct pci_dev *child_dev;
+
+ /* If no child, disable the link */
+ if (list_empty(&pdev->subordinate->devices))
+ return 0;
+ list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
+ if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
+ /*
+ * If downstream component of a link is pci bridge, we
+ * disable ASPM for now for the link
+ * */
+ state = 0;
+ break;
+ }
+ if ((child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
+ child_dev->pcie_type != PCI_EXP_TYPE_LEG_END))
+ continue;
+ /* Device not in D0 doesn't need check latency */
+ if (child_dev->current_state == PCI_D1 ||
+ child_dev->current_state == PCI_D2 ||
+ child_dev->current_state == PCI_D3hot ||
+ child_dev->current_state == PCI_D3cold)
+ continue;
+ state = __pcie_aspm_check_state_one(child_dev, state);
+ }
+ return state;
+}
+
+static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state)
+{
+ u16 reg16;
+ int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+
+ pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
+ reg16 &= ~0x3;
+ reg16 |= state;
+ pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
+}
+
+static void __pcie_aspm_config_link(struct pci_dev *pdev, unsigned int state)
+{
+ struct pci_dev *child_dev;
+ int valid = 1;
+ struct pcie_link_state *link_state = pdev->link_state;
+
+ /*
+ * if the downstream component has pci bridge function, don't do ASPM
+ * now
+ */
+ list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
+ if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
+ valid = 0;
+ break;
+ }
+ }
+ if (!valid)
+ return;
+
+ /*
+ * spec 2.0 suggests all functions should be configured the same
+ * setting for ASPM. Enabling ASPM L1 should be done in upstream
+ * component first and then downstream, and vice versa for disabling
+ * ASPM L1. Spec doesn't mention L0S.
+ */
+ if (state & PCIE_LINK_STATE_L1)
+ __pcie_aspm_config_one_dev(pdev, state);
+
+ list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list)
+ __pcie_aspm_config_one_dev(child_dev, state);
+
+ if (!(state & PCIE_LINK_STATE_L1))
+ __pcie_aspm_config_one_dev(pdev, state);
+
+ link_state->enabled_state = state;
+}
+
+static void __pcie_aspm_configure_link_state(struct pci_dev *pdev,
+ unsigned int state)
+{
+ struct pcie_link_state *link_state = pdev->link_state;
+
+ if (link_state->support_state == 0)
+ return;
+ state &= PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1;
+
+ /* state 0 means disabling aspm */
+ state = pcie_aspm_check_state(pdev, state);
+ if (link_state->enabled_state == state)
+ return;
+ __pcie_aspm_config_link(pdev, state);
+}
+
+/*
+ * pcie_aspm_configure_link_state: enable/disable PCI express link state
+ * @pdev: the root port or switch downstream port
+ */
+static void pcie_aspm_configure_link_state(struct pci_dev *pdev,
+ unsigned int state)
+{
+ down_read(&pci_bus_sem);
+ mutex_lock(&aspm_lock);
+ __pcie_aspm_configure_link_state(pdev, state);
+ mutex_unlock(&aspm_lock);
+ up_read(&pci_bus_sem);
+}
+
+static void free_link_state(struct pci_dev *pdev)
+{
+ kfree(pdev->link_state);
+ pdev->link_state = NULL;
+}
+
+/*
+ * pcie_aspm_init_link_state: Initiate PCI express link state.
+ * It is called after the pcie and its children devices are scaned.
+ * @pdev: the root port or switch downstream port
+ */
+void pcie_aspm_init_link_state(struct pci_dev *pdev)
+{
+ unsigned int state;
+ struct pcie_link_state *link_state;
+ int error = 0;
+
+ if (aspm_disabled || !pdev->is_pcie || pdev->link_state)
+ return;
+ if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
+ pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
+ return;
+ down_read(&pci_bus_sem);
+ if (list_empty(&pdev->subordinate->devices))
+ goto out;
+
+ mutex_lock(&aspm_lock);
+
+ link_state = kzalloc(sizeof(*link_state), GFP_KERNEL);
+ if (!link_state)
+ goto unlock_out;
+ pdev->link_state = link_state;
+
+ pcie_aspm_configure_common_clock(pdev);
+
+ pcie_aspm_cap_init(pdev);
+
+ /* config link state to avoid BIOS error */
+ state = pcie_aspm_check_state(pdev, policy_to_aspm_state(pdev));
+ __pcie_aspm_config_link(pdev, state);
+
+ pcie_check_clock_pm(pdev);
+
+ link_state->pdev = pdev;
+ list_add(&link_state->sibiling, &link_list);
+
+unlock_out:
+ if (error)
+ free_link_state(pdev);
+ mutex_unlock(&aspm_lock);
+out:
+ up_read(&pci_bus_sem);
+}
+
+/* @pdev: the endpoint device */
+void pcie_aspm_exit_link_state(struct pci_dev *pdev)
+{
+ struct pci_dev *parent = pdev->bus->self;
+ struct pcie_link_state *link_state = parent->link_state;
+
+ if (aspm_disabled || !pdev->is_pcie || !parent || !link_state)
+ return;
+ if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
+ parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
+ return;
+ down_read(&pci_bus_sem);
+ mutex_lock(&aspm_lock);
+
+ /*
+ * All PCIe functions are in one slot, remove one function will remove
+ * the the whole slot, so just wait
+ */
+ if (!list_empty(&parent->subordinate->devices))
+ goto out;
+
+ /* All functions are removed, so just disable ASPM for the link */
+ __pcie_aspm_config_one_dev(parent, 0);
+ list_del(&link_state->sibiling);
+ /* Clock PM is for endpoint device */
+
+ free_link_state(parent);
+out:
+ mutex_unlock(&aspm_lock);
+ up_read(&pci_bus_sem);
+}
+
+/* @pdev: the root port or switch downstream port */
+void pcie_aspm_pm_state_change(struct pci_dev *pdev)
+{
+ struct pcie_link_state *link_state = pdev->link_state;
+
+ if (aspm_disabled || !pdev->is_pcie || !pdev->link_state)
+ return;
+ if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
+ pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
+ return;
+ /*
+ * devices changed PM state, we should recheck if latency meets all
+ * functions' requirement
+ */
+ pcie_aspm_configure_link_state(pdev, link_state->enabled_state);
+}
+
+/*
+ * pci_disable_link_state - disable pci device's link state, so the link will
+ * never enter specific states
+ */
+void pci_disable_link_state(struct pci_dev *pdev, int state)
+{
+ struct pci_dev *parent = pdev->bus->self;
+ struct pcie_link_state *link_state;
+
+ if (aspm_disabled || !pdev->is_pcie)
+ return;
+ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
+ pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
+ parent = pdev;
+ if (!parent || !parent->link_state)
+ return;
+
+ down_read(&pci_bus_sem);
+ mutex_lock(&aspm_lock);
+ link_state = parent->link_state;
+ link_state->support_state &=
+ ~(state & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1));
+ if (state & PCIE_LINK_STATE_CLKPM)
+ link_state->clk_pm_capable = 0;
+
+ __pcie_aspm_configure_link_state(parent, link_state->enabled_state);
+ if (!link_state->clk_pm_capable && link_state->clk_pm_enabled)
+ pcie_set_clock_pm(parent, 0);
+ mutex_unlock(&aspm_lock);
+ up_read(&pci_bus_sem);
+}
+EXPORT_SYMBOL(pci_disable_link_state);
+
+static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
+{
+ int i;
+ struct pci_dev *pdev;
+ struct pcie_link_state *link_state;
+
+ for (i = 0; i < ARRAY_SIZE(policy_str); i++)
+ if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
+ break;
+ if (i >= ARRAY_SIZE(policy_str))
+ return -EINVAL;
+ if (i == aspm_policy)
+ return 0;
+
+ down_read(&pci_bus_sem);
+ mutex_lock(&aspm_lock);
+ aspm_policy = i;
+ list_for_each_entry(link_state, &link_list, sibiling) {
+ pdev = link_state->pdev;
+ __pcie_aspm_configure_link_state(pdev,
+ policy_to_aspm_state(pdev));
+ if (link_state->clk_pm_capable &&
+ link_state->clk_pm_enabled != policy_to_clkpm_state(pdev))
+ pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev));
+
+ }
+ mutex_unlock(&aspm_lock);
+ up_read(&pci_bus_sem);
+ return 0;
+}
+
+static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
+{
+ int i, cnt = 0;
+ for (i = 0; i < ARRAY_SIZE(policy_str); i++)
+ if (i == aspm_policy)
+ cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
+ else
+ cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
+ return cnt;
+}
+
+module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
+ NULL, 0644);
+
+#ifdef CONFIG_PCIEASPM_DEBUG
+static ssize_t link_state_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct pci_dev *pci_device = to_pci_dev(dev);
+ struct pcie_link_state *link_state = pci_device->link_state;
+
+ return sprintf(buf, "%d\n", link_state->enabled_state);
+}
+
+static ssize_t link_state_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t n)
+{
+ struct pci_dev *pci_device = to_pci_dev(dev);
+ int state;
+
+ if (n < 1)
+ return -EINVAL;
+ state = buf[0]-'0';
+ if (state >= 0 && state <= 3) {
+ /* setup link aspm state */
+ pcie_aspm_configure_link_state(pci_device, state);
+ return n;
+ }
+
+ return -EINVAL;
+}
+
+static ssize_t clk_ctl_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct pci_dev *pci_device = to_pci_dev(dev);
+ struct pcie_link_state *link_state = pci_device->link_state;
+
+ return sprintf(buf, "%d\n", link_state->clk_pm_enabled);
+}
+
+static ssize_t clk_ctl_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t n)
+{
+ struct pci_dev *pci_device = to_pci_dev(dev);
+ int state;
+
+ if (n < 1)
+ return -EINVAL;
+ state = buf[0]-'0';
+
+ down_read(&pci_bus_sem);
+ mutex_lock(&aspm_lock);
+ pcie_set_clock_pm(pci_device, !!state);
+ mutex_unlock(&aspm_lock);
+ up_read(&pci_bus_sem);
+
+ return n;
+}
+
+static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
+static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
+
+static char power_group[] = "power";
+void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
+{
+ struct pcie_link_state *link_state = pdev->link_state;
+
+ if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
+ pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
+ return;
+
+ if (link_state->support_state)
+ sysfs_add_file_to_group(&pdev->dev.kobj,
+ &dev_attr_link_state.attr, power_group);
+ if (link_state->clk_pm_capable)
+ sysfs_add_file_to_group(&pdev->dev.kobj,
+ &dev_attr_clk_ctl.attr, power_group);
+}
+
+void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
+{
+ struct pcie_link_state *link_state = pdev->link_state;
+
+ if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
+ pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
+ return;
+
+ if (link_state->support_state)
+ sysfs_remove_file_from_group(&pdev->dev.kobj,
+ &dev_attr_link_state.attr, power_group);
+ if (link_state->clk_pm_capable)
+ sysfs_remove_file_from_group(&pdev->dev.kobj,
+ &dev_attr_clk_ctl.attr, power_group);
+}
+#endif
+
+static int __init pcie_aspm_disable(char *str)
+{
+ aspm_disabled = 1;
+ return 1;
+}
+
+__setup("pcie_noaspm", pcie_aspm_disable);
+
+#ifdef CONFIG_ACPI
+#include <acpi/acpi_bus.h>
+#include <linux/pci-acpi.h>
+static void pcie_aspm_platform_init(void)
+{
+ pcie_osc_support_set(OSC_ACTIVE_STATE_PWR_SUPPORT|
+ OSC_CLOCK_PWR_CAPABILITY_SUPPORT);
+}
+#else
+static inline void pcie_aspm_platform_init(void) { }
+#endif
+
+static int __init pcie_aspm_init(void)
+{
+ if (aspm_disabled)
+ return 0;
+ pcie_aspm_platform_init();
+ return 0;
+}
+
+fs_initcall(pcie_aspm_init);
if (pos) {
struct msix_entry msix_entries[PCIE_PORT_DEVICE_MAXSERVICES] =
{{0, 0}, {0, 1}, {0, 2}, {0, 3}};
- printk("%s Found MSIX capability\n", __FUNCTION__);
+ printk("%s Found MSIX capability\n", __func__);
status = pci_enable_msix(dev, msix_entries, nvec);
if (!status) {
int j = 0;
if (status) {
pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
if (pos) {
- printk("%s Found MSI capability\n", __FUNCTION__);
+ printk("%s Found MSI capability\n", __func__);
status = pci_enable_msi(dev);
if (!status) {
interrupt_mode = PCIE_PORT_MSI_MODE;
if (!dev->irq && dev->pin) {
printk(KERN_WARNING
"%s->Dev[%04x:%04x] has invalid IRQ. Check vendor BIOS\n",
- __FUNCTION__, dev->vendor, dev->device);
+ __func__, dev->vendor, dev->device);
}
if (pcie_port_device_register(dev)) {
pci_disable_device(dev);
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/cpumask.h>
+#include <linux/pci-aspm.h>
#include "pci.h"
#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
LIST_HEAD(pci_root_buses);
EXPORT_SYMBOL(pci_root_buses);
-LIST_HEAD(pci_devices);
+
+static int find_anything(struct device *dev, void *data)
+{
+ return 1;
+}
/*
* Some device drivers need know if pci is initiated.
* Basically, we think pci is not initiated when there
- * is no device in list of pci_devices.
+ * is no device to be found on the pci_bus_type.
*/
int no_pci_devices(void)
{
- return list_empty(&pci_devices);
-}
+ struct device *dev;
+ int no_devices;
+ dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
+ no_devices = (dev == NULL);
+ put_device(dev);
+ return no_devices;
+}
EXPORT_SYMBOL(no_pci_devices);
#ifdef HAVE_PCI_LEGACY
* PCI Bus Class Devices
*/
static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
+ int type,
struct device_attribute *attr,
char *buf)
{
cpumask_t cpumask;
cpumask = pcibus_to_cpumask(to_pci_bus(dev));
- ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
- if (ret < PAGE_SIZE)
- buf[ret++] = '\n';
+ ret = type?
+ cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask):
+ cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
+ buf[ret++] = '\n';
+ buf[ret] = '\0';
return ret;
}
-DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
+
+static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
+}
+
+static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
+}
+
+DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
+DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
/*
* PCI Bus Class
res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
}
res->end = res->start + (unsigned long) sz;
- res->flags |= pci_calc_resource_flags(l);
+ res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
if (is_64bit_memory(l)) {
u32 szhi, lhi;
if (sz) {
res->flags = (l & IORESOURCE_ROM_ENABLE) |
IORESOURCE_MEM | IORESOURCE_PREFETCH |
- IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
+ IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
+ IORESOURCE_SIZEALIGN;
res->start = l & PCI_ROM_ADDRESS_MASK;
res->end = res->start + (unsigned long) sz;
}
return b;
}
-static struct pci_bus * __devinit
-pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
+static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
+ struct pci_dev *bridge, int busnr)
{
struct pci_bus *child;
int i;
pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
}
- sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
+ sprintf(child->name,
+ (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
+ pci_domain_nr(bus), child->number);
/* Has only triggered on CardBus, fixup is in yenta_socket */
while (bus->parent) {
struct pci_dev *pci_dev;
pci_dev = to_pci_dev(dev);
+ pci_vpd_release(pci_dev);
kfree(pci_dev);
}
if (!dev)
return NULL;
- INIT_LIST_HEAD(&dev->global_list);
INIT_LIST_HEAD(&dev->bus_list);
pci_msi_init_pci_dev(dev);
* Read the config data for a PCI device, sanity-check it
* and fill in the dev structure...
*/
-static struct pci_dev * __devinit
-pci_scan_device(struct pci_bus *bus, int devfn)
+static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
{
struct pci_dev *dev;
u32 l;
return NULL;
}
+ pci_vpd_pci22_init(dev);
+
return dev;
}
* Add the device to our list of discovered devices
* and the bus list for fixup functions, etc.
*/
- INIT_LIST_HEAD(&dev->global_list);
down_write(&pci_bus_sem);
list_add_tail(&dev->bus_list, &bus->devices);
up_write(&pci_bus_sem);
*
* Scan a PCI slot on the specified PCI bus for devices, adding
* discovered devices to the @bus->devices list. New devices
- * will have an empty dev->global_list head.
+ * will not have is_added set.
*/
int pci_scan_slot(struct pci_bus *bus, int devfn)
{
break;
}
}
+
+ if (bus->self)
+ pcie_aspm_init_link_state(bus->self);
+
return nr;
}
list_move_tail(&a->dev.knode_bus.n_node, list);
}
-static void __init pci_sort_breadthfirst_klist(void)
+void __init pci_sort_breadthfirst(void)
{
LIST_HEAD(sorted_devices);
struct list_head *pos, *tmp;
list_splice(&sorted_devices, &device_klist->k_list);
spin_unlock(&device_klist->k_lock);
}
-
-static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list)
-{
- struct pci_dev *b;
-
- list_for_each_entry(b, list, global_list) {
- if (pci_sort_bf_cmp(a, b) <= 0) {
- list_move_tail(&a->global_list, &b->global_list);
- return;
- }
- }
- list_move_tail(&a->global_list, list);
-}
-
-static void __init pci_sort_breadthfirst_devices(void)
-{
- LIST_HEAD(sorted_devices);
- struct pci_dev *dev, *tmp;
-
- down_write(&pci_bus_sem);
- list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) {
- pci_insertion_sort_devices(dev, &sorted_devices);
- }
- list_splice(&sorted_devices, &pci_devices);
- up_write(&pci_bus_sem);
-}
-
-void __init pci_sort_breadthfirst(void)
-{
- pci_sort_breadthfirst_devices();
- pci_sort_breadthfirst_klist();
-}
-
if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
(f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
#ifdef DEBUG
- dev_dbg(&dev->dev, "calling quirk 0x%p", f->hook);
- print_fn_descriptor_symbol(": %s()\n",
+ dev_dbg(&dev->dev, "calling ");
+ print_fn_descriptor_symbol("%s()\n",
(unsigned long) f->hook);
#endif
f->hook(dev);
/* Turn off PCI Bus Parking */
pci_write_config_byte(dev, 0x76, b ^ 0x40);
+ dev_info(&dev->dev,
+ "Disabling VIA CX700 PCI parking\n");
+ }
+ }
+
+ if (pci_read_config_byte(dev, 0x72, &b) == 0) {
+ if (b != 0) {
/* Turn off PCI Master read caching */
pci_write_config_byte(dev, 0x72, 0x0);
+
+ /* Set PCI Master Bus time-out to "1x16 PCLK" */
pci_write_config_byte(dev, 0x75, 0x1);
+
+ /* Disable "Read FIFO Timer" */
pci_write_config_byte(dev, 0x77, 0x0);
dev_info(&dev->dev,
- "Disabling VIA CX700 PCI parking/caching\n");
+ "Disabling VIA CX700 PCI caching\n");
}
}
}
#include <linux/pci.h>
#include <linux/module.h>
+#include <linux/pci-aspm.h>
#include "pci.h"
static void pci_free_resources(struct pci_dev *dev)
static void pci_stop_dev(struct pci_dev *dev)
{
- if (!dev->global_list.next)
- return;
-
- if (!list_empty(&dev->global_list)) {
+ if (dev->is_added) {
pci_proc_detach_device(dev);
pci_remove_sysfs_dev_files(dev);
device_unregister(&dev->dev);
- down_write(&pci_bus_sem);
- list_del(&dev->global_list);
- dev->global_list.next = dev->global_list.prev = NULL;
- up_write(&pci_bus_sem);
+ dev->is_added = 0;
}
+
+ if (dev->bus->self)
+ pcie_aspm_exit_link_state(dev);
}
static void pci_destroy_dev(struct pci_dev *dev)
}
#ifdef CONFIG_PCI_LEGACY
-
/**
* pci_find_slot - locate PCI device from a given PCI slot
* @bus: number of PCI bus on which desired PCI device resides
- * @devfn: encodes number of PCI slot in which the desired PCI
- * device resides and the logical device number within that slot
+ * @devfn: encodes number of PCI slot in which the desired PCI
+ * device resides and the logical device number within that slot
* in case of multi-function devices.
*
- * Given a PCI bus and slot/function number, the desired PCI device
+ * Given a PCI bus and slot/function number, the desired PCI device
* is located in system global list of PCI devices. If the device
- * is found, a pointer to its data structure is returned. If no
+ * is found, a pointer to its data structure is returned. If no
* device is found, %NULL is returned.
+ *
+ * NOTE: Do not use this function any more; use pci_get_slot() instead, as
+ * the PCI device returned by this function can disappear at any moment in
+ * time.
*/
-struct pci_dev *
-pci_find_slot(unsigned int bus, unsigned int devfn)
+struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
{
struct pci_dev *dev = NULL;
- while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
- if (dev->bus->number == bus && dev->devfn == devfn)
+ while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+ if (dev->bus->number == bus && dev->devfn == devfn) {
+ pci_dev_put(dev);
return dev;
+ }
}
return NULL;
}
+EXPORT_SYMBOL(pci_find_slot);
+
+/**
+ * pci_find_device - begin or continue searching for a PCI device by vendor/device id
+ * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
+ * @device: PCI device id to match, or %PCI_ANY_ID to match all device ids
+ * @from: Previous PCI device found in search, or %NULL for new search.
+ *
+ * Iterates through the list of known PCI devices. If a PCI device is found
+ * with a matching @vendor and @device, a pointer to its device structure is
+ * returned. Otherwise, %NULL is returned.
+ * A new search is initiated by passing %NULL as the @from argument.
+ * Otherwise if @from is not %NULL, searches continue from next device
+ * on the global list.
+ *
+ * NOTE: Do not use this function any more; use pci_get_device() instead, as
+ * the PCI device returned by this function can disappear at any moment in
+ * time.
+ */
+struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device,
+ const struct pci_dev *from)
+{
+ struct pci_dev *pdev;
+ pdev = pci_get_subsys(vendor, device, PCI_ANY_ID, PCI_ANY_ID, from);
+ pci_dev_put(pdev);
+ return pdev;
+}
+EXPORT_SYMBOL(pci_find_device);
#endif /* CONFIG_PCI_LEGACY */
/**
return NULL;
}
-#ifdef CONFIG_PCI_LEGACY
-/**
- * pci_find_subsys - begin or continue searching for a PCI device by vendor/subvendor/device/subdevice id
- * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
- * @device: PCI device id to match, or %PCI_ANY_ID to match all device ids
- * @ss_vendor: PCI subsystem vendor id to match, or %PCI_ANY_ID to match all vendor ids
- * @ss_device: PCI subsystem device id to match, or %PCI_ANY_ID to match all device ids
- * @from: Previous PCI device found in search, or %NULL for new search.
- *
- * Iterates through the list of known PCI devices. If a PCI device is
- * found with a matching @vendor, @device, @ss_vendor and @ss_device, a
- * pointer to its device structure is returned. Otherwise, %NULL is returned.
- * A new search is initiated by passing %NULL as the @from argument.
- * Otherwise if @from is not %NULL, searches continue from next device
- * on the global list.
- *
- * NOTE: Do not use this function any more; use pci_get_subsys() instead, as
- * the PCI device returned by this function can disappear at any moment in
- * time.
- */
-static struct pci_dev * pci_find_subsys(unsigned int vendor,
- unsigned int device,
- unsigned int ss_vendor,
- unsigned int ss_device,
- const struct pci_dev *from)
+static int match_pci_dev_by_id(struct device *dev, void *data)
{
- struct list_head *n;
- struct pci_dev *dev;
-
- WARN_ON(in_interrupt());
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct pci_device_id *id = data;
- /*
- * pci_find_subsys() can be called on the ide_setup() path, super-early
- * in boot. But the down_read() will enable local interrupts, which
- * can cause some machines to crash. So here we detect and flag that
- * situation and bail out early.
- */
- if (unlikely(no_pci_devices()))
- return NULL;
- down_read(&pci_bus_sem);
- n = from ? from->global_list.next : pci_devices.next;
-
- while (n && (n != &pci_devices)) {
- dev = pci_dev_g(n);
- if ((vendor == PCI_ANY_ID || dev->vendor == vendor) &&
- (device == PCI_ANY_ID || dev->device == device) &&
- (ss_vendor == PCI_ANY_ID || dev->subsystem_vendor == ss_vendor) &&
- (ss_device == PCI_ANY_ID || dev->subsystem_device == ss_device))
- goto exit;
- n = n->next;
- }
- dev = NULL;
-exit:
- up_read(&pci_bus_sem);
- return dev;
+ if (pci_match_one_device(id, pdev))
+ return 1;
+ return 0;
}
-/**
- * pci_find_device - begin or continue searching for a PCI device by vendor/device id
- * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
- * @device: PCI device id to match, or %PCI_ANY_ID to match all device ids
+/*
+ * pci_get_dev_by_id - begin or continue searching for a PCI device by id
+ * @id: pointer to struct pci_device_id to match for the device
* @from: Previous PCI device found in search, or %NULL for new search.
*
* Iterates through the list of known PCI devices. If a PCI device is found
- * with a matching @vendor and @device, a pointer to its device structure is
- * returned. Otherwise, %NULL is returned.
- * A new search is initiated by passing %NULL as the @from argument.
- * Otherwise if @from is not %NULL, searches continue from next device
- * on the global list.
- *
- * NOTE: Do not use this function any more; use pci_get_device() instead, as
- * the PCI device returned by this function can disappear at any moment in
- * time.
+ * with a matching id a pointer to its device structure is returned, and the
+ * reference count to the device is incremented. Otherwise, %NULL is returned.
+ * A new search is initiated by passing %NULL as the @from argument. Otherwise
+ * if @from is not %NULL, searches continue from next device on the global
+ * list. The reference count for @from is always decremented if it is not
+ * %NULL.
+ *
+ * This is an internal function for use by the other search functions in
+ * this file.
*/
-struct pci_dev *
-pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
+static struct pci_dev *pci_get_dev_by_id(const struct pci_device_id *id,
+ const struct pci_dev *from)
{
- return pci_find_subsys(vendor, device, PCI_ANY_ID, PCI_ANY_ID, from);
+ struct device *dev;
+ struct device *dev_start = NULL;
+ struct pci_dev *pdev = NULL;
+
+ WARN_ON(in_interrupt());
+ if (from) {
+ /* FIXME
+ * take the cast off, when bus_find_device is made const.
+ */
+ dev_start = (struct device *)&from->dev;
+ }
+ dev = bus_find_device(&pci_bus_type, dev_start, (void *)id,
+ match_pci_dev_by_id);
+ if (dev)
+ pdev = to_pci_dev(dev);
+ return pdev;
}
-#endif /* CONFIG_PCI_LEGACY */
/**
* pci_get_subsys - begin or continue searching for a PCI device by vendor/subvendor/device/subdevice id
* searches continue from next device on the global list.
* The reference count for @from is always decremented if it is not %NULL.
*/
-struct pci_dev *
-pci_get_subsys(unsigned int vendor, unsigned int device,
- unsigned int ss_vendor, unsigned int ss_device,
- struct pci_dev *from)
+struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
+ unsigned int ss_vendor, unsigned int ss_device,
+ const struct pci_dev *from)
{
- struct list_head *n;
- struct pci_dev *dev;
-
- WARN_ON(in_interrupt());
+ struct pci_dev *pdev;
+ struct pci_device_id *id;
/*
- * pci_get_subsys() can potentially be called by drivers super-early
- * in boot. But the down_read() will enable local interrupts, which
- * can cause some machines to crash. So here we detect and flag that
- * situation and bail out early.
+ * pci_find_subsys() can be called on the ide_setup() path,
+ * super-early in boot. But the down_read() will enable local
+ * interrupts, which can cause some machines to crash. So here we
+ * detect and flag that situation and bail out early.
*/
if (unlikely(no_pci_devices()))
return NULL;
- down_read(&pci_bus_sem);
- n = from ? from->global_list.next : pci_devices.next;
-
- while (n && (n != &pci_devices)) {
- dev = pci_dev_g(n);
- if ((vendor == PCI_ANY_ID || dev->vendor == vendor) &&
- (device == PCI_ANY_ID || dev->device == device) &&
- (ss_vendor == PCI_ANY_ID || dev->subsystem_vendor == ss_vendor) &&
- (ss_device == PCI_ANY_ID || dev->subsystem_device == ss_device))
- goto exit;
- n = n->next;
- }
- dev = NULL;
-exit:
- dev = pci_dev_get(dev);
- up_read(&pci_bus_sem);
- pci_dev_put(from);
- return dev;
+
+ id = kzalloc(sizeof(*id), GFP_KERNEL);
+ if (!id)
+ return NULL;
+ id->vendor = vendor;
+ id->device = device;
+ id->subvendor = ss_vendor;
+ id->subdevice = ss_device;
+
+ pdev = pci_get_dev_by_id(id, from);
+ kfree(id);
+
+ return pdev;
}
/**
return pci_get_subsys(vendor, device, PCI_ANY_ID, PCI_ANY_ID, from);
}
-/**
- * pci_get_device_reverse - begin or continue searching for a PCI device by vendor/device id
- * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
- * @device: PCI device id to match, or %PCI_ANY_ID to match all device ids
- * @from: Previous PCI device found in search, or %NULL for new search.
- *
- * Iterates through the list of known PCI devices in the reverse order of
- * pci_get_device.
- * If a PCI device is found with a matching @vendor and @device, the reference
- * count to the device is incremented and a pointer to its device structure
- * is returned Otherwise, %NULL is returned. A new search is initiated by
- * passing %NULL as the @from argument. Otherwise if @from is not %NULL,
- * searches continue from next device on the global list. The reference
- * count for @from is always decremented if it is not %NULL.
- */
-struct pci_dev *
-pci_get_device_reverse(unsigned int vendor, unsigned int device, struct pci_dev *from)
-{
- struct list_head *n;
- struct pci_dev *dev;
-
- WARN_ON(in_interrupt());
- down_read(&pci_bus_sem);
- n = from ? from->global_list.prev : pci_devices.prev;
-
- while (n && (n != &pci_devices)) {
- dev = pci_dev_g(n);
- if ((vendor == PCI_ANY_ID || dev->vendor == vendor) &&
- (device == PCI_ANY_ID || dev->device == device))
- goto exit;
- n = n->prev;
- }
- dev = NULL;
-exit:
- dev = pci_dev_get(dev);
- up_read(&pci_bus_sem);
- pci_dev_put(from);
- return dev;
-}
-
/**
* pci_get_class - begin or continue searching for a PCI device by class
* @class: search for a PCI device with this class designation
*/
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
{
- struct list_head *n;
struct pci_dev *dev;
+ struct pci_device_id *id;
- WARN_ON(in_interrupt());
- down_read(&pci_bus_sem);
- n = from ? from->global_list.next : pci_devices.next;
+ id = kzalloc(sizeof(*id), GFP_KERNEL);
+ if (!id)
+ return NULL;
+ id->vendor = id->device = id->subvendor = id->subdevice = PCI_ANY_ID;
+ id->class_mask = PCI_ANY_ID;
+ id->class = class;
- while (n && (n != &pci_devices)) {
- dev = pci_dev_g(n);
- if (dev->class == class)
- goto exit;
- n = n->next;
- }
- dev = NULL;
-exit:
- dev = pci_dev_get(dev);
- up_read(&pci_bus_sem);
- pci_dev_put(from);
+ dev = pci_get_dev_by_id(id, from);
+ kfree(id);
return dev;
}
-const struct pci_device_id *pci_find_present(const struct pci_device_id *ids)
-{
- struct pci_dev *dev;
- const struct pci_device_id *found = NULL;
-
- WARN_ON(in_interrupt());
- down_read(&pci_bus_sem);
- while (ids->vendor || ids->subvendor || ids->class_mask) {
- list_for_each_entry(dev, &pci_devices, global_list) {
- if ((found = pci_match_one_device(ids, dev)) != NULL)
- goto exit;
- }
- ids++;
- }
-exit:
- up_read(&pci_bus_sem);
- return found;
-}
-
/**
* pci_dev_present - Returns 1 if device matching the device list is present, 0 if not.
* @ids: A pointer to a null terminated list of struct pci_device_id structures
*/
int pci_dev_present(const struct pci_device_id *ids)
{
- return pci_find_present(ids) == NULL ? 0 : 1;
-}
+ struct pci_dev *found = NULL;
+ WARN_ON(in_interrupt());
+ while (ids->vendor || ids->subvendor || ids->class_mask) {
+ found = pci_get_dev_by_id(ids, NULL);
+ if (found)
+ goto exit;
+ ids++;
+ }
+exit:
+ if (found)
+ return 1;
+ return 0;
+}
EXPORT_SYMBOL(pci_dev_present);
-EXPORT_SYMBOL(pci_find_present);
-
-#ifdef CONFIG_PCI_LEGACY
-EXPORT_SYMBOL(pci_find_device);
-EXPORT_SYMBOL(pci_find_slot);
-#endif /* CONFIG_PCI_LEGACY */
/* For boot time work */
EXPORT_SYMBOL(pci_find_bus);
EXPORT_SYMBOL(pci_find_next_bus);
/* For everyone */
EXPORT_SYMBOL(pci_get_device);
-EXPORT_SYMBOL(pci_get_device_reverse);
EXPORT_SYMBOL(pci_get_subsys);
EXPORT_SYMBOL(pci_get_slot);
EXPORT_SYMBOL(pci_get_bus_and_slot);
res = list->res;
idx = res - &list->dev->resource[0];
if (pci_assign_resource(list->dev, idx)) {
+ /* FIXME: get rid of this */
res->start = 0;
res->end = 0;
res->flags = 0;
config space writes, so it's quite possible that an I/O window of
the bridge will have some undesirable address (e.g. 0) after the
first write. Ditto 64-bit prefetchable MMIO. */
-static void __devinit
-pci_setup_bridge(struct pci_bus *bus)
+static void pci_setup_bridge(struct pci_bus *bus)
{
struct pci_dev *bridge = bus->self;
struct pci_bus_region region;
/* Alignment of the IO window is always 4K */
b_res->start = 4096;
b_res->end = b_res->start + size - 1;
+ b_res->flags |= IORESOURCE_STARTALIGN;
}
/* Calculate the size of the bus and minimal alignment which
}
b_res->start = min_align;
b_res->end = size + min_align - 1;
+ b_res->flags |= IORESOURCE_STARTALIGN;
return 1;
}
-static void __devinit
-pci_bus_size_cardbus(struct pci_bus *bus)
+static void pci_bus_size_cardbus(struct pci_bus *bus)
{
struct pci_dev *bridge = bus->self;
struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
* Reserve some resources for CardBus. We reserve
* a fixed amount of bus space for CardBus bridges.
*/
- b_res[0].start = pci_cardbus_io_size;
- b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
- b_res[0].flags |= IORESOURCE_IO;
+ b_res[0].start = 0;
+ b_res[0].end = pci_cardbus_io_size - 1;
+ b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
- b_res[1].start = pci_cardbus_io_size;
- b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
- b_res[1].flags |= IORESOURCE_IO;
+ b_res[1].start = 0;
+ b_res[1].end = pci_cardbus_io_size - 1;
+ b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
/*
* Check whether prefetchable memory is supported
* twice the size.
*/
if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
- b_res[2].start = pci_cardbus_mem_size;
- b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
- b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
+ b_res[2].start = 0;
+ b_res[2].end = pci_cardbus_mem_size - 1;
+ b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
- b_res[3].start = pci_cardbus_mem_size;
- b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1;
- b_res[3].flags |= IORESOURCE_MEM;
+ b_res[3].start = 0;
+ b_res[3].end = pci_cardbus_mem_size - 1;
+ b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
} else {
- b_res[3].start = pci_cardbus_mem_size * 2;
- b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1;
- b_res[3].flags |= IORESOURCE_MEM;
+ b_res[3].start = 0;
+ b_res[3].end = pci_cardbus_mem_size * 2 - 1;
+ b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
}
}
size = res->end - res->start + 1;
min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
- /* The bridge resources are special, as their
- size != alignment. Sizing routines return
- required alignment in the "start" field. */
- align = (resno < PCI_BRIDGE_RESOURCES) ? size : res->start;
+
+ align = resource_alignment(res);
+ if (!align) {
+ printk(KERN_ERR "PCI: Cannot allocate resource (bogus "
+ "alignment) %d [%llx:%llx] (flags %lx) of %s\n",
+ resno, (unsigned long long)res->start,
+ (unsigned long long)res->end, res->flags,
+ pci_name(dev));
+ return -EINVAL;
+ }
/* First, try exact prefetching match.. */
ret = pci_bus_alloc_resource(bus, res, size, align, min,
res->flags & IORESOURCE_IO ? "I/O" : "mem",
resno, (unsigned long long)size,
(unsigned long long)res->start, pci_name(dev));
- } else if (resno < PCI_BRIDGE_RESOURCES) {
- pci_update_resource(dev, res, resno);
+ } else {
+ res->flags &= ~IORESOURCE_STARTALIGN;
+ if (resno < PCI_BRIDGE_RESOURCES)
+ pci_update_resource(dev, res, resno);
}
return ret;
}
-#ifdef CONFIG_EMBEDDED
+#if 0
int pci_assign_resource_fixed(struct pci_dev *dev, int resno)
{
struct pci_bus *bus = dev->bus;
if (r->flags & IORESOURCE_PCI_FIXED)
continue;
- r_align = r->end - r->start;
-
if (!(r->flags) || r->parent)
continue;
+
+ r_align = resource_alignment(r);
if (!r_align) {
- printk(KERN_WARNING "PCI: Ignore bogus resource %d "
- "[%llx:%llx] of %s\n",
+ printk(KERN_WARNING "PCI: bogus alignment of resource "
+ "%d [%llx:%llx] (flags %lx) of %s\n",
i, (unsigned long long)r->start,
- (unsigned long long)r->end, pci_name(dev));
+ (unsigned long long)r->end, r->flags,
+ pci_name(dev));
continue;
}
- r_align = (i < PCI_BRIDGE_RESOURCES) ? r_align + 1 : r->start;
for (list = head; ; list = list->next) {
resource_size_t align = 0;
struct resource_list *ln = list->next;
- int idx;
- if (ln) {
- idx = ln->res - &ln->dev->resource[0];
- align = (idx < PCI_BRIDGE_RESOURCES) ?
- ln->res->end - ln->res->start + 1 :
- ln->res->start;
- }
+ if (ln)
+ align = resource_alignment(ln->res);
+
if (r_align > align) {
tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
if (!tmp)
}
}
}
+
+int pci_enable_resources(struct pci_dev *dev, int mask)
+{
+ u16 cmd, old_cmd;
+ int i;
+ struct resource *r;
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ old_cmd = cmd;
+
+ for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+ if (!(mask & (1 << i)))
+ continue;
+
+ r = &dev->resource[i];
+
+ if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
+ continue;
+ if ((i == PCI_ROM_RESOURCE) &&
+ (!(r->flags & IORESOURCE_ROM_ENABLE)))
+ continue;
+
+ if (!r->parent) {
+ dev_err(&dev->dev, "device not available because of "
+ "BAR %d [%llx:%llx] collisions\n", i,
+ (unsigned long long) r->start,
+ (unsigned long long) r->end);
+ return -EINVAL;
+ }
+
+ if (r->flags & IORESOURCE_IO)
+ cmd |= PCI_COMMAND_IO;
+ if (r->flags & IORESOURCE_MEM)
+ cmd |= PCI_COMMAND_MEMORY;
+ }
+
+ if (cmd != old_cmd) {
+ dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
+ old_cmd, cmd);
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+ }
+ return 0;
+}
config PCMCIA_SA1100
tristate "SA1100 support"
depends on ARM && ARCH_SA1100 && PCMCIA
+ depends on ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL || MACH_ARMCORE
help
Say Y here to include support for SA11x0-based PCMCIA or CF
sockets, found on HP iPAQs, Yopy, and other StrongARM(R)/
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/cm-x270.h>
#include "soc_common.h"
while (!(res->irq_resource[i].flags & IORESOURCE_UNSET) &&
i < PNP_MAX_IRQ)
i++;
- if (i >= PNP_MAX_IRQ && !warned) {
- printk(KERN_WARNING "pnpacpi: exceeded the max number of IRQ "
- "resources: %d \n", PNP_MAX_IRQ);
- warned = 1;
+ if (i >= PNP_MAX_IRQ) {
+ if (!warned) {
+ printk(KERN_WARNING "pnpacpi: exceeded the max number"
+ " of IRQ resources: %d\n", PNP_MAX_IRQ);
+ warned = 1;
+ }
return;
}
/*
#include <linux/reboot.h>
#include <asm/firmware.h>
+#include <asm/lv1call.h>
#include <asm/ps3.h>
#include "vuart.h"
* controller, and bluetooth controller.
* @PS3_SM_WAKE_RTC:
* @PS3_SM_WAKE_RTC_ERROR:
+ * @PS3_SM_WAKE_W_O_L: Ether or wireless LAN.
* @PS3_SM_WAKE_P_O_R: Power on reset.
*
* Additional wakeup sources when specifying PS3_SM_NEXT_OP_SYS_SHUTDOWN.
PS3_SM_WAKE_DEFAULT = 0,
PS3_SM_WAKE_RTC = 0x00000040,
PS3_SM_WAKE_RTC_ERROR = 0x00000080,
+ PS3_SM_WAKE_W_O_L = 0x00000400,
PS3_SM_WAKE_P_O_R = 0x80000000,
};
+/**
+ * user_wake_sources - User specified wakeup sources.
+ *
+ * Logical OR of enum ps3_sys_manager_wake_source types.
+ */
+
+static u32 user_wake_sources = PS3_SM_WAKE_DEFAULT;
+
/**
* enum ps3_sys_manager_cmd - Command from system manager to guest.
*
return -EIO;
}
+static void ps3_sys_manager_fin(struct ps3_system_bus_device *dev)
+{
+ ps3_sys_manager_send_request_shutdown(dev);
+
+ pr_emerg("System Halted, OK to turn off power\n");
+
+ while (ps3_sys_manager_handle_msg(dev)) {
+ /* pause until next DEC interrupt */
+ lv1_pause(0);
+ }
+
+ while (1) {
+ /* pause, ignoring DEC interrupt */
+ lv1_pause(1);
+ }
+}
+
/**
* ps3_sys_manager_final_power_off - The final platform machine_power_off routine.
*
ps3_vuart_cancel_async(dev);
ps3_sys_manager_send_next_op(dev, PS3_SM_NEXT_OP_SYS_SHUTDOWN,
- PS3_SM_WAKE_DEFAULT);
- ps3_sys_manager_send_request_shutdown(dev);
-
- pr_emerg("System Halted, OK to turn off power\n");
+ user_wake_sources);
- while (1)
- ps3_sys_manager_handle_msg(dev);
+ ps3_sys_manager_fin(dev);
}
/**
ps3_sys_manager_send_attr(dev, 0);
ps3_sys_manager_send_next_op(dev, PS3_SM_NEXT_OP_SYS_REBOOT,
- PS3_SM_WAKE_DEFAULT);
- ps3_sys_manager_send_request_shutdown(dev);
+ user_wake_sources);
- pr_emerg("System Halted, OK to turn off power\n");
+ ps3_sys_manager_fin(dev);
+}
+
+/**
+ * ps3_sys_manager_get_wol - Get wake-on-lan setting.
+ */
+
+int ps3_sys_manager_get_wol(void)
+{
+ pr_debug("%s:%d\n", __func__, __LINE__);
+
+ return (user_wake_sources & PS3_SM_WAKE_W_O_L) != 0;
+}
+EXPORT_SYMBOL_GPL(ps3_sys_manager_get_wol);
+
+/**
+ * ps3_sys_manager_set_wol - Set wake-on-lan setting.
+ */
+
+void ps3_sys_manager_set_wol(int state)
+{
+ static DEFINE_MUTEX(mutex);
+
+ mutex_lock(&mutex);
+
+ pr_debug("%s:%d: %d\n", __func__, __LINE__, state);
- while (1)
- ps3_sys_manager_handle_msg(dev);
+ if (state)
+ user_wake_sources |= PS3_SM_WAKE_W_O_L;
+ else
+ user_wake_sources &= ~PS3_SM_WAKE_W_O_L;
+ mutex_unlock(&mutex);
}
+EXPORT_SYMBOL_GPL(ps3_sys_manager_set_wol);
/**
* ps3_sys_manager_work - Asynchronous read handler.
*/
#include <linux/kernel.h>
+#include <asm/lv1call.h>
#include <asm/ps3.h>
/**
if (ps3_sys_manager_ops.power_off)
ps3_sys_manager_ops.power_off(ps3_sys_manager_ops.dev);
- printk(KERN_EMERG "System Halted, OK to turn off power\n");
- local_irq_disable();
- while (1)
- (void)0;
+ ps3_sys_manager_halt();
}
void ps3_sys_manager_restart(void)
if (ps3_sys_manager_ops.restart)
ps3_sys_manager_ops.restart(ps3_sys_manager_ops.dev);
- printk(KERN_EMERG "System Halted, OK to turn off power\n");
+ ps3_sys_manager_halt();
+}
+
+void ps3_sys_manager_halt(void)
+{
+ pr_emerg("System Halted, OK to turn off power\n");
local_irq_disable();
while (1)
- (void)0;
+ lv1_pause(1);
}
+
/*
* SuperH On-Chip RTC Support
*
- * Copyright (C) 2006, 2007 Paul Mundt
+ * Copyright (C) 2006, 2007, 2008 Paul Mundt
* Copyright (C) 2006 Jamie Lenehan
+ * Copyright (C) 2008 Angelo Castello
*
* Based on the old arch/sh/kernel/cpu/rtc.c by:
*
#include <asm/rtc.h>
#define DRV_NAME "sh-rtc"
-#define DRV_VERSION "0.1.6"
+#define DRV_VERSION "0.2.0"
#define RTC_REG(r) ((r) * rtc_reg_size)
/* ALARM Bits - or with BCD encoded value */
#define AR_ENB 0x80 /* Enable for alarm cmp */
+/* Period Bits */
+#define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
+#define PF_COUNT 0x200 /* Half periodic counter */
+#define PF_OXS 0x400 /* Periodic One x Second */
+#define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
+#define PF_MASK 0xf00
+
/* RCR1 Bits */
#define RCR1_CF 0x80 /* Carry Flag */
#define RCR1_CIE 0x10 /* Carry Interrupt Enable */
unsigned int alarm_irq, periodic_irq, carry_irq;
struct rtc_device *rtc_dev;
spinlock_t lock;
- int rearm_aie;
unsigned long capabilities; /* See asm-sh/rtc.h for cap bits */
+ unsigned short periodic_freq;
};
static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
{
- struct platform_device *pdev = to_platform_device(dev_id);
- struct sh_rtc *rtc = platform_get_drvdata(pdev);
- unsigned int tmp, events = 0;
+ struct sh_rtc *rtc = dev_id;
+ unsigned int tmp;
spin_lock(&rtc->lock);
tmp = readb(rtc->regbase + RCR1);
tmp &= ~RCR1_CF;
-
- if (rtc->rearm_aie) {
- if (tmp & RCR1_AF)
- tmp &= ~RCR1_AF; /* try to clear AF again */
- else {
- tmp |= RCR1_AIE; /* AF has cleared, rearm IRQ */
- rtc->rearm_aie = 0;
- }
- }
-
writeb(tmp, rtc->regbase + RCR1);
- rtc_update_irq(rtc->rtc_dev, 1, events);
+ /* Users have requested One x Second IRQ */
+ if (rtc->periodic_freq & PF_OXS)
+ rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
spin_unlock(&rtc->lock);
static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
{
- struct platform_device *pdev = to_platform_device(dev_id);
- struct sh_rtc *rtc = platform_get_drvdata(pdev);
- unsigned int tmp, events = 0;
+ struct sh_rtc *rtc = dev_id;
+ unsigned int tmp;
spin_lock(&rtc->lock);
tmp = readb(rtc->regbase + RCR1);
-
- /*
- * If AF is set then the alarm has triggered. If we clear AF while
- * the alarm time still matches the RTC time then AF will
- * immediately be set again, and if AIE is enabled then the alarm
- * interrupt will immediately be retrigger. So we clear AIE here
- * and use rtc->rearm_aie so that the carry interrupt will keep
- * trying to clear AF and once it stays cleared it'll re-enable
- * AIE.
- */
- if (tmp & RCR1_AF) {
- events |= RTC_AF | RTC_IRQF;
-
- tmp &= ~(RCR1_AF|RCR1_AIE);
-
+ tmp &= ~(RCR1_AF | RCR1_AIE);
writeb(tmp, rtc->regbase + RCR1);
- rtc->rearm_aie = 1;
-
- rtc_update_irq(rtc->rtc_dev, 1, events);
- }
+ rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
spin_unlock(&rtc->lock);
+
return IRQ_HANDLED;
}
static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
{
- struct platform_device *pdev = to_platform_device(dev_id);
- struct sh_rtc *rtc = platform_get_drvdata(pdev);
+ struct sh_rtc *rtc = dev_id;
+ struct rtc_device *rtc_dev = rtc->rtc_dev;
+ unsigned int tmp;
spin_lock(&rtc->lock);
- rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
+ tmp = readb(rtc->regbase + RCR2);
+ tmp &= ~RCR2_PEF;
+ writeb(tmp, rtc->regbase + RCR2);
+
+ /* Half period enabled than one skipped and the next notified */
+ if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
+ rtc->periodic_freq &= ~PF_COUNT;
+ else {
+ if (rtc->periodic_freq & PF_HP)
+ rtc->periodic_freq |= PF_COUNT;
+ if (rtc->periodic_freq & PF_KOU) {
+ spin_lock(&rtc_dev->irq_task_lock);
+ if (rtc_dev->irq_task)
+ rtc_dev->irq_task->func(rtc_dev->irq_task->private_data);
+ spin_unlock(&rtc_dev->irq_task_lock);
+ } else
+ rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
+ }
spin_unlock(&rtc->lock);
tmp = readb(rtc->regbase + RCR2);
if (enable) {
- tmp &= ~RCR2_PESMASK;
- tmp |= RCR2_PEF | (2 << 4);
+ tmp &= ~RCR2_PEF; /* Clear PES bit */
+ tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */
} else
tmp &= ~(RCR2_PESMASK | RCR2_PEF);
spin_unlock_irq(&rtc->lock);
}
-static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
+static inline int sh_rtc_setfreq(struct device *dev, unsigned int freq)
{
struct sh_rtc *rtc = dev_get_drvdata(dev);
- unsigned int tmp;
+ int tmp, ret = 0;
spin_lock_irq(&rtc->lock);
+ tmp = rtc->periodic_freq & PF_MASK;
- tmp = readb(rtc->regbase + RCR1);
-
- if (!enable) {
- tmp &= ~RCR1_AIE;
- rtc->rearm_aie = 0;
- } else if (rtc->rearm_aie == 0)
- tmp |= RCR1_AIE;
+ switch (freq) {
+ case 0:
+ rtc->periodic_freq = 0x00;
+ break;
+ case 1:
+ rtc->periodic_freq = 0x60;
+ break;
+ case 2:
+ rtc->periodic_freq = 0x50;
+ break;
+ case 4:
+ rtc->periodic_freq = 0x40;
+ break;
+ case 8:
+ rtc->periodic_freq = 0x30 | PF_HP;
+ break;
+ case 16:
+ rtc->periodic_freq = 0x30;
+ break;
+ case 32:
+ rtc->periodic_freq = 0x20 | PF_HP;
+ break;
+ case 64:
+ rtc->periodic_freq = 0x20;
+ break;
+ case 128:
+ rtc->periodic_freq = 0x10 | PF_HP;
+ break;
+ case 256:
+ rtc->periodic_freq = 0x10;
+ break;
+ default:
+ ret = -ENOTSUPP;
+ }
- writeb(tmp, rtc->regbase + RCR1);
+ if (ret == 0) {
+ rtc->periodic_freq |= tmp;
+ rtc->rtc_dev->irq_freq = freq;
+ }
spin_unlock_irq(&rtc->lock);
+ return ret;
}
-static int sh_rtc_open(struct device *dev)
+static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
{
struct sh_rtc *rtc = dev_get_drvdata(dev);
unsigned int tmp;
- int ret;
-
- tmp = readb(rtc->regbase + RCR1);
- tmp &= ~RCR1_CF;
- tmp |= RCR1_CIE;
- writeb(tmp, rtc->regbase + RCR1);
- ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, IRQF_DISABLED,
- "sh-rtc period", dev);
- if (unlikely(ret)) {
- dev_err(dev, "request period IRQ failed with %d, IRQ %d\n",
- ret, rtc->periodic_irq);
- return ret;
- }
-
- ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED,
- "sh-rtc carry", dev);
- if (unlikely(ret)) {
- dev_err(dev, "request carry IRQ failed with %d, IRQ %d\n",
- ret, rtc->carry_irq);
- free_irq(rtc->periodic_irq, dev);
- goto err_bad_carry;
- }
+ spin_lock_irq(&rtc->lock);
- ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, IRQF_DISABLED,
- "sh-rtc alarm", dev);
- if (unlikely(ret)) {
- dev_err(dev, "request alarm IRQ failed with %d, IRQ %d\n",
- ret, rtc->alarm_irq);
- goto err_bad_alarm;
- }
+ tmp = readb(rtc->regbase + RCR1);
- return 0;
+ if (!enable)
+ tmp &= ~RCR1_AIE;
+ else
+ tmp |= RCR1_AIE;
-err_bad_alarm:
- free_irq(rtc->carry_irq, dev);
-err_bad_carry:
- free_irq(rtc->periodic_irq, dev);
+ writeb(tmp, rtc->regbase + RCR1);
- return ret;
+ spin_unlock_irq(&rtc->lock);
}
static void sh_rtc_release(struct device *dev)
{
- struct sh_rtc *rtc = dev_get_drvdata(dev);
-
sh_rtc_setpie(dev, 0);
sh_rtc_setaie(dev, 0);
-
- free_irq(rtc->periodic_irq, dev);
- free_irq(rtc->carry_irq, dev);
- free_irq(rtc->alarm_irq, dev);
}
static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
unsigned int tmp;
tmp = readb(rtc->regbase + RCR1);
- seq_printf(seq, "carry_IRQ\t: %s\n",
- (tmp & RCR1_CIE) ? "yes" : "no");
+ seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
tmp = readb(rtc->regbase + RCR2);
seq_printf(seq, "periodic_IRQ\t: %s\n",
- (tmp & RCR2_PEF) ? "yes" : "no");
+ (tmp & RCR2_PESMASK) ? "yes" : "no");
return 0;
}
static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
- unsigned int ret = -ENOIOCTLCMD;
+ struct sh_rtc *rtc = dev_get_drvdata(dev);
+ unsigned int ret = 0;
switch (cmd) {
case RTC_PIE_OFF:
case RTC_PIE_ON:
sh_rtc_setpie(dev, cmd == RTC_PIE_ON);
- ret = 0;
break;
case RTC_AIE_OFF:
case RTC_AIE_ON:
sh_rtc_setaie(dev, cmd == RTC_AIE_ON);
- ret = 0;
break;
+ case RTC_UIE_OFF:
+ rtc->periodic_freq &= ~PF_OXS;
+ break;
+ case RTC_UIE_ON:
+ rtc->periodic_freq |= PF_OXS;
+ break;
+ case RTC_IRQP_READ:
+ ret = put_user(rtc->rtc_dev->irq_freq,
+ (unsigned long __user *)arg);
+ break;
+ case RTC_IRQP_SET:
+ ret = sh_rtc_setfreq(dev, arg);
+ break;
+ default:
+ ret = -ENOIOCTLCMD;
}
return ret;
{
struct platform_device *pdev = to_platform_device(dev);
struct sh_rtc *rtc = platform_get_drvdata(pdev);
- struct rtc_time* tm = &wkalrm->time;
+ struct rtc_time *tm = &wkalrm->time;
spin_lock_irq(&rtc->lock);
writeb(BIN2BCD(value) | AR_ENB, rtc->regbase + reg_off);
}
-static int sh_rtc_check_alarm(struct rtc_time* tm)
+static int sh_rtc_check_alarm(struct rtc_time *tm)
{
/*
* The original rtc says anything > 0xc0 is "don't care" or "match
/* disable alarm interrupt and clear the alarm flag */
rcr1 = readb(rtc->regbase + RCR1);
- rcr1 &= ~(RCR1_AF|RCR1_AIE);
+ rcr1 &= ~(RCR1_AF | RCR1_AIE);
writeb(rcr1, rtc->regbase + RCR1);
- rtc->rearm_aie = 0;
-
/* set alarm time */
sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
return 0;
}
+static int sh_rtc_irq_set_state(struct device *dev, int enabled)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct sh_rtc *rtc = platform_get_drvdata(pdev);
+
+ if (enabled) {
+ rtc->periodic_freq |= PF_KOU;
+ return sh_rtc_ioctl(dev, RTC_PIE_ON, 0);
+ } else {
+ rtc->periodic_freq &= ~PF_KOU;
+ return sh_rtc_ioctl(dev, RTC_PIE_OFF, 0);
+ }
+}
+
+static int sh_rtc_irq_set_freq(struct device *dev, int freq)
+{
+ return sh_rtc_ioctl(dev, RTC_IRQP_SET, freq);
+}
+
static struct rtc_class_ops sh_rtc_ops = {
- .open = sh_rtc_open,
.release = sh_rtc_release,
.ioctl = sh_rtc_ioctl,
.read_time = sh_rtc_read_time,
.set_time = sh_rtc_set_time,
.read_alarm = sh_rtc_read_alarm,
.set_alarm = sh_rtc_set_alarm,
+ .irq_set_state = sh_rtc_irq_set_state,
+ .irq_set_freq = sh_rtc_irq_set_freq,
.proc = sh_rtc_proc,
};
{
struct sh_rtc *rtc;
struct resource *res;
+ unsigned int tmp;
int ret = -ENOENT;
rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL);
spin_lock_init(&rtc->lock);
+ /* get periodic/carry/alarm irqs */
rtc->periodic_irq = platform_get_irq(pdev, 0);
if (unlikely(rtc->periodic_irq < 0)) {
dev_err(&pdev->dev, "No IRQ for period\n");
rtc->capabilities |= pinfo->capabilities;
}
+ rtc->rtc_dev->max_user_freq = 256;
+ rtc->rtc_dev->irq_freq = 1;
+ rtc->periodic_freq = 0x60;
+
platform_set_drvdata(pdev, rtc);
+ /* register periodic/carry/alarm irqs */
+ ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, IRQF_DISABLED,
+ "sh-rtc period", rtc);
+ if (unlikely(ret)) {
+ dev_err(&pdev->dev,
+ "request period IRQ failed with %d, IRQ %d\n", ret,
+ rtc->periodic_irq);
+ goto err_badmap;
+ }
+
+ ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED,
+ "sh-rtc carry", rtc);
+ if (unlikely(ret)) {
+ dev_err(&pdev->dev,
+ "request carry IRQ failed with %d, IRQ %d\n", ret,
+ rtc->carry_irq);
+ free_irq(rtc->periodic_irq, rtc);
+ goto err_badmap;
+ }
+
+ ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, IRQF_DISABLED,
+ "sh-rtc alarm", rtc);
+ if (unlikely(ret)) {
+ dev_err(&pdev->dev,
+ "request alarm IRQ failed with %d, IRQ %d\n", ret,
+ rtc->alarm_irq);
+ free_irq(rtc->carry_irq, rtc);
+ free_irq(rtc->periodic_irq, rtc);
+ goto err_badmap;
+ }
+
+ tmp = readb(rtc->regbase + RCR1);
+ tmp &= ~RCR1_CF;
+ tmp |= RCR1_CIE;
+ writeb(tmp, rtc->regbase + RCR1);
+
return 0;
err_badmap:
sh_rtc_setpie(&pdev->dev, 0);
sh_rtc_setaie(&pdev->dev, 0);
+ free_irq(rtc->carry_irq, rtc);
+ free_irq(rtc->periodic_irq, rtc);
+ free_irq(rtc->alarm_irq, rtc);
+
release_resource(rtc->res);
platform_set_drvdata(pdev, NULL);
MODULE_DESCRIPTION("SuperH on-chip RTC driver");
MODULE_VERSION(DRV_VERSION);
-MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, Jamie Lenehan <lenehan@twibble.org>");
+MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
+ "Jamie Lenehan <lenehan@twibble.org>, "
+ "Angelo Castello <angelo.castello@st.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
#include <linux/ctype.h>
#include <linux/dcache.h>
-#include <asm/semaphore.h>
#include <asm/ccwdev.h>
#include <asm/ccwgroup.h>
#include <linux/proc_fs.h>
#include <linux/timer.h>
#include <linux/mempool.h>
+#include <linux/semaphore.h>
#include <asm/ccwdev.h>
#include <asm/io.h>
#include <asm/atomic.h>
-#include <asm/semaphore.h>
#include <asm/timex.h>
#include <asm/debug.h>
/* Functions */
/* Show some statistics about the card */
-static ssize_t twa_show_stats(struct class_device *class_dev, char *buf)
+static ssize_t twa_show_stats(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *host = class_to_shost(class_dev);
+ struct Scsi_Host *host = class_to_shost(dev);
TW_Device_Extension *tw_dev = (TW_Device_Extension *)host->hostdata;
unsigned long flags = 0;
ssize_t len;
} /* End twa_change_queue_depth() */
/* Create sysfs 'stats' entry */
-static struct class_device_attribute twa_host_stats_attr = {
+static struct device_attribute twa_host_stats_attr = {
.attr = {
.name = "stats",
.mode = S_IRUGO,
};
/* Host attributes initializer */
-static struct class_device_attribute *twa_host_attrs[] = {
+static struct device_attribute *twa_host_attrs[] = {
&twa_host_stats_attr,
NULL,
};
} /* End tw_state_request_start() */
/* Show some statistics about the card */
-static ssize_t tw_show_stats(struct class_device *class_dev, char *buf)
+static ssize_t tw_show_stats(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(class_dev);
+ struct Scsi_Host *host = class_to_shost(dev);
TW_Device_Extension *tw_dev = (TW_Device_Extension *)host->hostdata;
unsigned long flags = 0;
ssize_t len;
} /* End tw_change_queue_depth() */
/* Create sysfs 'stats' entry */
-static struct class_device_attribute tw_host_stats_attr = {
+static struct device_attribute tw_host_stats_attr = {
.attr = {
.name = "stats",
.mode = S_IRUGO,
};
/* Host attributes initializer */
-static struct class_device_attribute *tw_host_attrs[] = {
+static struct device_attribute *tw_host_attrs[] = {
&tw_host_stats_attr,
NULL,
};
#include <linux/slab.h>
#include <linux/completion.h>
#include <linux/blkdev.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <linux/highmem.h> /* For flush_kernel_dcache_page */
tmp>>24,(tmp>>16)&0xff,tmp&0xff,
le32_to_cpu(dev->adapter_info.biosbuild));
buffer[0] = '\0';
- if (aac_show_serial_number(
+ if (aac_get_serial_number(
shost_to_class(dev->scsi_host_ptr), buffer))
printk(KERN_INFO "%s%d: serial %s",
dev->name, dev->id, buffer);
int aac_scsi_cmd(struct scsi_cmnd *cmd);
int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg);
#ifndef shost_to_class
-#define shost_to_class(shost) &shost->shost_classdev
+#define shost_to_class(shost) &shost->shost_dev
#endif
-ssize_t aac_show_serial_number(struct class_device *class_dev, char *buf);
+ssize_t aac_get_serial_number(struct device *dev, char *buf);
int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg);
int aac_rx_init(struct aac_dev *dev);
int aac_rkt_init(struct aac_dev *dev);
#include <linux/blkdev.h>
#include <linux/delay.h> /* ssleep prototype */
#include <linux/kthread.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include <asm/uaccess.h>
#include "aacraid.h"
#include <linux/completion.h>
#include <linux/mm.h>
#include <scsi/scsi_host.h>
-#include <asm/semaphore.h>
#include "aacraid.h"
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/interrupt.h>
+#include <linux/semaphore.h>
#include <scsi/scsi.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_cmnd.h>
-#include <asm/semaphore.h>
#include "aacraid.h"
#include <linux/slab.h>
#include <linux/completion.h>
#include <linux/blkdev.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include "aacraid.h"
#include <linux/syscalls.h>
#include <linux/delay.h>
#include <linux/kthread.h>
-#include <asm/semaphore.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
}
#endif
-static ssize_t aac_show_model(struct class_device *class_dev,
- char *buf)
+static ssize_t aac_show_model(struct device *device,
+ struct device_attribute *attr, char *buf)
{
- struct aac_dev *dev = (struct aac_dev*)class_to_shost(class_dev)->hostdata;
+ struct aac_dev *dev = (struct aac_dev*)class_to_shost(device)->hostdata;
int len;
if (dev->supplement_adapter_info.AdapterTypeText[0]) {
return len;
}
-static ssize_t aac_show_vendor(struct class_device *class_dev,
- char *buf)
+static ssize_t aac_show_vendor(struct device *device,
+ struct device_attribute *attr, char *buf)
{
- struct aac_dev *dev = (struct aac_dev*)class_to_shost(class_dev)->hostdata;
+ struct aac_dev *dev = (struct aac_dev*)class_to_shost(device)->hostdata;
int len;
if (dev->supplement_adapter_info.AdapterTypeText[0]) {
return len;
}
-static ssize_t aac_show_flags(struct class_device *class_dev, char *buf)
+static ssize_t aac_show_flags(struct device *cdev,
+ struct device_attribute *attr, char *buf)
{
int len = 0;
- struct aac_dev *dev = (struct aac_dev*)class_to_shost(class_dev)->hostdata;
+ struct aac_dev *dev = (struct aac_dev*)class_to_shost(cdev)->hostdata;
if (nblank(dprintk(x)))
len = snprintf(buf, PAGE_SIZE, "dprintk\n");
return len;
}
-static ssize_t aac_show_kernel_version(struct class_device *class_dev,
- char *buf)
+static ssize_t aac_show_kernel_version(struct device *device,
+ struct device_attribute *attr,
+ char *buf)
{
- struct aac_dev *dev = (struct aac_dev*)class_to_shost(class_dev)->hostdata;
+ struct aac_dev *dev = (struct aac_dev*)class_to_shost(device)->hostdata;
int len, tmp;
tmp = le32_to_cpu(dev->adapter_info.kernelrev);
return len;
}
-static ssize_t aac_show_monitor_version(struct class_device *class_dev,
- char *buf)
+static ssize_t aac_show_monitor_version(struct device *device,
+ struct device_attribute *attr,
+ char *buf)
{
- struct aac_dev *dev = (struct aac_dev*)class_to_shost(class_dev)->hostdata;
+ struct aac_dev *dev = (struct aac_dev*)class_to_shost(device)->hostdata;
int len, tmp;
tmp = le32_to_cpu(dev->adapter_info.monitorrev);
return len;
}
-static ssize_t aac_show_bios_version(struct class_device *class_dev,
- char *buf)
+static ssize_t aac_show_bios_version(struct device *device,
+ struct device_attribute *attr,
+ char *buf)
{
- struct aac_dev *dev = (struct aac_dev*)class_to_shost(class_dev)->hostdata;
+ struct aac_dev *dev = (struct aac_dev*)class_to_shost(device)->hostdata;
int len, tmp;
tmp = le32_to_cpu(dev->adapter_info.biosrev);
return len;
}
-ssize_t aac_show_serial_number(struct class_device *class_dev, char *buf)
+ssize_t aac_show_serial_number(struct device *device,
+ struct device_attribute *attr, char *buf)
{
- struct aac_dev *dev = (struct aac_dev*)class_to_shost(class_dev)->hostdata;
+ struct aac_dev *dev = (struct aac_dev*)class_to_shost(device)->hostdata;
int len = 0;
if (le32_to_cpu(dev->adapter_info.serial[0]) != 0xBAD0)
return len;
}
-static ssize_t aac_show_max_channel(struct class_device *class_dev, char *buf)
+static ssize_t aac_show_max_channel(struct device *device,
+ struct device_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%d\n",
- class_to_shost(class_dev)->max_channel);
+ class_to_shost(device)->max_channel);
}
-static ssize_t aac_show_max_id(struct class_device *class_dev, char *buf)
+static ssize_t aac_show_max_id(struct device *device,
+ struct device_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%d\n",
- class_to_shost(class_dev)->max_id);
+ class_to_shost(device)->max_id);
}
-static ssize_t aac_store_reset_adapter(struct class_device *class_dev,
- const char *buf, size_t count)
+static ssize_t aac_store_reset_adapter(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
int retval = -EACCES;
if (!capable(CAP_SYS_ADMIN))
return retval;
- retval = aac_reset_adapter((struct aac_dev*)class_to_shost(class_dev)->hostdata, buf[0] == '!');
+ retval = aac_reset_adapter((struct aac_dev*)class_to_shost(device)->hostdata, buf[0] == '!');
if (retval >= 0)
retval = count;
return retval;
}
-static ssize_t aac_show_reset_adapter(struct class_device *class_dev,
- char *buf)
+static ssize_t aac_show_reset_adapter(struct device *device,
+ struct device_attribute *attr,
+ char *buf)
{
- struct aac_dev *dev = (struct aac_dev*)class_to_shost(class_dev)->hostdata;
+ struct aac_dev *dev = (struct aac_dev*)class_to_shost(device)->hostdata;
int len, tmp;
tmp = aac_adapter_check_health(dev);
return len;
}
-static struct class_device_attribute aac_model = {
+static struct device_attribute aac_model = {
.attr = {
.name = "model",
.mode = S_IRUGO,
},
.show = aac_show_model,
};
-static struct class_device_attribute aac_vendor = {
+static struct device_attribute aac_vendor = {
.attr = {
.name = "vendor",
.mode = S_IRUGO,
},
.show = aac_show_vendor,
};
-static struct class_device_attribute aac_flags = {
+static struct device_attribute aac_flags = {
.attr = {
.name = "flags",
.mode = S_IRUGO,
},
.show = aac_show_flags,
};
-static struct class_device_attribute aac_kernel_version = {
+static struct device_attribute aac_kernel_version = {
.attr = {
.name = "hba_kernel_version",
.mode = S_IRUGO,
},
.show = aac_show_kernel_version,
};
-static struct class_device_attribute aac_monitor_version = {
+static struct device_attribute aac_monitor_version = {
.attr = {
.name = "hba_monitor_version",
.mode = S_IRUGO,
},
.show = aac_show_monitor_version,
};
-static struct class_device_attribute aac_bios_version = {
+static struct device_attribute aac_bios_version = {
.attr = {
.name = "hba_bios_version",
.mode = S_IRUGO,
},
.show = aac_show_bios_version,
};
-static struct class_device_attribute aac_serial_number = {
+static struct device_attribute aac_serial_number = {
.attr = {
.name = "serial_number",
.mode = S_IRUGO,
},
.show = aac_show_serial_number,
};
-static struct class_device_attribute aac_max_channel = {
+static struct device_attribute aac_max_channel = {
.attr = {
.name = "max_channel",
.mode = S_IRUGO,
},
.show = aac_show_max_channel,
};
-static struct class_device_attribute aac_max_id = {
+static struct device_attribute aac_max_id = {
.attr = {
.name = "max_id",
.mode = S_IRUGO,
},
.show = aac_show_max_id,
};
-static struct class_device_attribute aac_reset = {
+static struct device_attribute aac_reset = {
.attr = {
.name = "reset_host",
.mode = S_IWUSR|S_IRUGO,
.show = aac_show_reset_adapter,
};
-static struct class_device_attribute *aac_attrs[] = {
+static struct device_attribute *aac_attrs[] = {
&aac_model,
&aac_vendor,
&aac_flags,
NULL
};
+ssize_t aac_get_serial_number(struct device *device, char *buf)
+{
+ return aac_show_serial_number(device, &aac_serial_number, buf);
+}
static const struct file_operations aac_cfg_fops = {
.owner = THIS_MODULE,
#include <linux/completion.h>
#include <linux/time.h>
#include <linux/interrupt.h>
-#include <asm/semaphore.h>
#include <scsi/scsi_host.h>
#include <linux/completion.h>
#include <linux/time.h>
#include <linux/interrupt.h>
-#include <asm/semaphore.h>
#include <scsi/scsi_host.h>
*/
#include <linux/interrupt.h>
-struct class_device_attribute;
+struct device_attribute;
/*The limit of outstanding scsi command that firmware can handle*/
#define ARCMSR_MAX_OUTSTANDING_CMD 256
#define ARCMSR_MAX_FREECCB_NUM 320
extern void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *);
extern void arcmsr_iop_message_read(struct AdapterControlBlock *);
extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *);
-extern struct class_device_attribute *arcmsr_host_attrs[];
+extern struct device_attribute *arcmsr_host_attrs[];
extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *);
void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);
#include <scsi/scsi_transport.h>
#include "arcmsr.h"
-struct class_device_attribute *arcmsr_host_attrs[];
+struct device_attribute *arcmsr_host_attrs[];
static ssize_t arcmsr_sysfs_iop_message_read(struct kobject *kobj,
struct bin_attribute *bin,
char *buf, loff_t off,
size_t count)
{
- struct class_device *cdev = container_of(kobj,struct class_device,kobj);
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct device *dev = container_of(kobj,struct device,kobj);
+ struct Scsi_Host *host = class_to_shost(dev);
struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
uint8_t *pQbuffer,*ptmpQbuffer;
int32_t allxfer_len = 0;
char *buf, loff_t off,
size_t count)
{
- struct class_device *cdev = container_of(kobj,struct class_device,kobj);
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct device *dev = container_of(kobj,struct device,kobj);
+ struct Scsi_Host *host = class_to_shost(dev);
struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
uint8_t *pQbuffer, *ptmpuserbuffer;
char *buf, loff_t off,
size_t count)
{
- struct class_device *cdev = container_of(kobj,struct class_device,kobj);
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct device *dev = container_of(kobj,struct device,kobj);
+ struct Scsi_Host *host = class_to_shost(dev);
struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
uint8_t *pQbuffer;
struct Scsi_Host *host = acb->host;
int error;
- error = sysfs_create_bin_file(&host->shost_classdev.kobj, &arcmsr_sysfs_message_read_attr);
+ error = sysfs_create_bin_file(&host->shost_dev.kobj, &arcmsr_sysfs_message_read_attr);
if (error) {
printk(KERN_ERR "arcmsr: alloc sysfs mu_read failed\n");
goto error_bin_file_message_read;
}
- error = sysfs_create_bin_file(&host->shost_classdev.kobj, &arcmsr_sysfs_message_write_attr);
+ error = sysfs_create_bin_file(&host->shost_dev.kobj, &arcmsr_sysfs_message_write_attr);
if (error) {
printk(KERN_ERR "arcmsr: alloc sysfs mu_write failed\n");
goto error_bin_file_message_write;
}
- error = sysfs_create_bin_file(&host->shost_classdev.kobj, &arcmsr_sysfs_message_clear_attr);
+ error = sysfs_create_bin_file(&host->shost_dev.kobj, &arcmsr_sysfs_message_clear_attr);
if (error) {
printk(KERN_ERR "arcmsr: alloc sysfs mu_clear failed\n");
goto error_bin_file_message_clear;
}
return 0;
error_bin_file_message_clear:
- sysfs_remove_bin_file(&host->shost_classdev.kobj, &arcmsr_sysfs_message_write_attr);
+ sysfs_remove_bin_file(&host->shost_dev.kobj, &arcmsr_sysfs_message_write_attr);
error_bin_file_message_write:
- sysfs_remove_bin_file(&host->shost_classdev.kobj, &arcmsr_sysfs_message_read_attr);
+ sysfs_remove_bin_file(&host->shost_dev.kobj, &arcmsr_sysfs_message_read_attr);
error_bin_file_message_read:
return error;
}
-void
-arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb) {
+void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb)
+{
struct Scsi_Host *host = acb->host;
- sysfs_remove_bin_file(&host->shost_classdev.kobj, &arcmsr_sysfs_message_clear_attr);
- sysfs_remove_bin_file(&host->shost_classdev.kobj, &arcmsr_sysfs_message_write_attr);
- sysfs_remove_bin_file(&host->shost_classdev.kobj, &arcmsr_sysfs_message_read_attr);
+ sysfs_remove_bin_file(&host->shost_dev.kobj, &arcmsr_sysfs_message_clear_attr);
+ sysfs_remove_bin_file(&host->shost_dev.kobj, &arcmsr_sysfs_message_write_attr);
+ sysfs_remove_bin_file(&host->shost_dev.kobj, &arcmsr_sysfs_message_read_attr);
}
static ssize_t
-arcmsr_attr_host_driver_version(struct class_device *cdev, char *buf) {
+arcmsr_attr_host_driver_version(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
return snprintf(buf, PAGE_SIZE,
"%s\n",
ARCMSR_DRIVER_VERSION);
}
static ssize_t
-arcmsr_attr_host_driver_posted_cmd(struct class_device *cdev, char *buf) {
- struct Scsi_Host *host = class_to_shost(cdev);
- struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
+arcmsr_attr_host_driver_posted_cmd(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct Scsi_Host *host = class_to_shost(dev);
+ struct AdapterControlBlock *acb =
+ (struct AdapterControlBlock *) host->hostdata;
return snprintf(buf, PAGE_SIZE,
"%4d\n",
atomic_read(&acb->ccboutstandingcount));
}
static ssize_t
-arcmsr_attr_host_driver_reset(struct class_device *cdev, char *buf) {
- struct Scsi_Host *host = class_to_shost(cdev);
- struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
+arcmsr_attr_host_driver_reset(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct Scsi_Host *host = class_to_shost(dev);
+ struct AdapterControlBlock *acb =
+ (struct AdapterControlBlock *) host->hostdata;
return snprintf(buf, PAGE_SIZE,
"%4d\n",
acb->num_resets);
}
static ssize_t
-arcmsr_attr_host_driver_abort(struct class_device *cdev, char *buf) {
- struct Scsi_Host *host = class_to_shost(cdev);
- struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
+arcmsr_attr_host_driver_abort(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct Scsi_Host *host = class_to_shost(dev);
+ struct AdapterControlBlock *acb =
+ (struct AdapterControlBlock *) host->hostdata;
return snprintf(buf, PAGE_SIZE,
"%4d\n",
acb->num_aborts);
}
static ssize_t
-arcmsr_attr_host_fw_model(struct class_device *cdev, char *buf) {
- struct Scsi_Host *host = class_to_shost(cdev);
- struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
+arcmsr_attr_host_fw_model(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct Scsi_Host *host = class_to_shost(dev);
+ struct AdapterControlBlock *acb =
+ (struct AdapterControlBlock *) host->hostdata;
return snprintf(buf, PAGE_SIZE,
"%s\n",
acb->firm_model);
}
static ssize_t
-arcmsr_attr_host_fw_version(struct class_device *cdev, char *buf) {
- struct Scsi_Host *host = class_to_shost(cdev);
- struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
+arcmsr_attr_host_fw_version(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct Scsi_Host *host = class_to_shost(dev);
+ struct AdapterControlBlock *acb =
+ (struct AdapterControlBlock *) host->hostdata;
return snprintf(buf, PAGE_SIZE,
"%s\n",
}
static ssize_t
-arcmsr_attr_host_fw_request_len(struct class_device *cdev, char *buf) {
- struct Scsi_Host *host = class_to_shost(cdev);
- struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
+arcmsr_attr_host_fw_request_len(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct Scsi_Host *host = class_to_shost(dev);
+ struct AdapterControlBlock *acb =
+ (struct AdapterControlBlock *) host->hostdata;
return snprintf(buf, PAGE_SIZE,
"%4d\n",
}
static ssize_t
-arcmsr_attr_host_fw_numbers_queue(struct class_device *cdev, char *buf) {
- struct Scsi_Host *host = class_to_shost(cdev);
- struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
+arcmsr_attr_host_fw_numbers_queue(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct Scsi_Host *host = class_to_shost(dev);
+ struct AdapterControlBlock *acb =
+ (struct AdapterControlBlock *) host->hostdata;
return snprintf(buf, PAGE_SIZE,
"%4d\n",
}
static ssize_t
-arcmsr_attr_host_fw_sdram_size(struct class_device *cdev, char *buf) {
- struct Scsi_Host *host = class_to_shost(cdev);
- struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
+arcmsr_attr_host_fw_sdram_size(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct Scsi_Host *host = class_to_shost(dev);
+ struct AdapterControlBlock *acb =
+ (struct AdapterControlBlock *) host->hostdata;
return snprintf(buf, PAGE_SIZE,
"%4d\n",
}
static ssize_t
-arcmsr_attr_host_fw_hd_channels(struct class_device *cdev, char *buf) {
- struct Scsi_Host *host = class_to_shost(cdev);
- struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
+arcmsr_attr_host_fw_hd_channels(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct Scsi_Host *host = class_to_shost(dev);
+ struct AdapterControlBlock *acb =
+ (struct AdapterControlBlock *) host->hostdata;
return snprintf(buf, PAGE_SIZE,
"%4d\n",
acb->firm_hd_channels);
}
-static CLASS_DEVICE_ATTR(host_driver_version, S_IRUGO, arcmsr_attr_host_driver_version, NULL);
-static CLASS_DEVICE_ATTR(host_driver_posted_cmd, S_IRUGO, arcmsr_attr_host_driver_posted_cmd, NULL);
-static CLASS_DEVICE_ATTR(host_driver_reset, S_IRUGO, arcmsr_attr_host_driver_reset, NULL);
-static CLASS_DEVICE_ATTR(host_driver_abort, S_IRUGO, arcmsr_attr_host_driver_abort, NULL);
-static CLASS_DEVICE_ATTR(host_fw_model, S_IRUGO, arcmsr_attr_host_fw_model, NULL);
-static CLASS_DEVICE_ATTR(host_fw_version, S_IRUGO, arcmsr_attr_host_fw_version, NULL);
-static CLASS_DEVICE_ATTR(host_fw_request_len, S_IRUGO, arcmsr_attr_host_fw_request_len, NULL);
-static CLASS_DEVICE_ATTR(host_fw_numbers_queue, S_IRUGO, arcmsr_attr_host_fw_numbers_queue, NULL);
-static CLASS_DEVICE_ATTR(host_fw_sdram_size, S_IRUGO, arcmsr_attr_host_fw_sdram_size, NULL);
-static CLASS_DEVICE_ATTR(host_fw_hd_channels, S_IRUGO, arcmsr_attr_host_fw_hd_channels, NULL);
-
-struct class_device_attribute *arcmsr_host_attrs[] = {
- &class_device_attr_host_driver_version,
- &class_device_attr_host_driver_posted_cmd,
- &class_device_attr_host_driver_reset,
- &class_device_attr_host_driver_abort,
- &class_device_attr_host_fw_model,
- &class_device_attr_host_fw_version,
- &class_device_attr_host_fw_request_len,
- &class_device_attr_host_fw_numbers_queue,
- &class_device_attr_host_fw_sdram_size,
- &class_device_attr_host_fw_hd_channels,
+static DEVICE_ATTR(host_driver_version, S_IRUGO, arcmsr_attr_host_driver_version, NULL);
+static DEVICE_ATTR(host_driver_posted_cmd, S_IRUGO, arcmsr_attr_host_driver_posted_cmd, NULL);
+static DEVICE_ATTR(host_driver_reset, S_IRUGO, arcmsr_attr_host_driver_reset, NULL);
+static DEVICE_ATTR(host_driver_abort, S_IRUGO, arcmsr_attr_host_driver_abort, NULL);
+static DEVICE_ATTR(host_fw_model, S_IRUGO, arcmsr_attr_host_fw_model, NULL);
+static DEVICE_ATTR(host_fw_version, S_IRUGO, arcmsr_attr_host_fw_version, NULL);
+static DEVICE_ATTR(host_fw_request_len, S_IRUGO, arcmsr_attr_host_fw_request_len, NULL);
+static DEVICE_ATTR(host_fw_numbers_queue, S_IRUGO, arcmsr_attr_host_fw_numbers_queue, NULL);
+static DEVICE_ATTR(host_fw_sdram_size, S_IRUGO, arcmsr_attr_host_fw_sdram_size, NULL);
+static DEVICE_ATTR(host_fw_hd_channels, S_IRUGO, arcmsr_attr_host_fw_hd_channels, NULL);
+
+struct device_attribute *arcmsr_host_attrs[] = {
+ &dev_attr_host_driver_version,
+ &dev_attr_host_driver_posted_cmd,
+ &dev_attr_host_driver_reset,
+ &dev_attr_host_driver_abort,
+ &dev_attr_host_fw_model,
+ &dev_attr_host_fw_version,
+ &dev_attr_host_fw_request_len,
+ &dev_attr_host_fw_numbers_queue,
+ &dev_attr_host_fw_sdram_size,
+ &dev_attr_host_fw_hd_channels,
NULL,
};
static int ch_probe(struct device *dev)
{
struct scsi_device *sd = to_scsi_device(dev);
- struct class_device *class_dev;
+ struct device *class_dev;
int minor, ret = -ENOMEM;
scsi_changer *ch;
ch->minor = minor;
sprintf(ch->name,"ch%d",ch->minor);
- class_dev = class_device_create(ch_sysfs_class, NULL,
- MKDEV(SCSI_CHANGER_MAJOR, ch->minor),
- dev, "s%s", ch->name);
+ class_dev = device_create(ch_sysfs_class, dev,
+ MKDEV(SCSI_CHANGER_MAJOR,ch->minor),
+ "s%s", ch->name);
if (IS_ERR(class_dev)) {
- printk(KERN_WARNING "ch%d: class_device_create failed\n",
+ printk(KERN_WARNING "ch%d: device_create failed\n",
ch->minor);
ret = PTR_ERR(class_dev);
goto remove_idr;
idr_remove(&ch_index_idr, ch->minor);
spin_unlock(&ch_index_lock);
- class_device_destroy(ch_sysfs_class,
- MKDEV(SCSI_CHANGER_MAJOR,ch->minor));
+ device_destroy(ch_sysfs_class, MKDEV(SCSI_CHANGER_MAJOR,ch->minor));
kfree(ch->dt);
kfree(ch);
return 0;
#include <linux/i2o-dev.h>
-#include <asm/semaphore.h> /* Needed for MUTEX init macros */
#include <linux/version.h>
#include <linux/notifier.h>
#include <asm/atomic.h>
static int scsi_host_next_hn; /* host_no for next new host */
-static void scsi_host_cls_release(struct class_device *class_dev)
+static void scsi_host_cls_release(struct device *dev)
{
- put_device(&class_to_shost(class_dev)->shost_gendev);
+ put_device(&class_to_shost(dev)->shost_gendev);
}
static struct class shost_class = {
.name = "scsi_host",
- .release = scsi_host_cls_release,
+ .dev_release = scsi_host_cls_release,
};
/**
spin_unlock_irqrestore(shost->host_lock, flags);
transport_unregister_device(&shost->shost_gendev);
- class_device_unregister(&shost->shost_classdev);
+ device_unregister(&shost->shost_dev);
device_del(&shost->shost_gendev);
scsi_proc_hostdir_rm(shost->hostt);
}
scsi_host_set_state(shost, SHOST_RUNNING);
get_device(shost->shost_gendev.parent);
- error = class_device_add(&shost->shost_classdev);
+ error = device_add(&shost->shost_dev);
if (error)
goto out_del_gendev;
GFP_KERNEL);
if (shost->shost_data == NULL) {
error = -ENOMEM;
- goto out_del_classdev;
+ goto out_del_dev;
}
}
destroy_workqueue(shost->work_q);
out_free_shost_data:
kfree(shost->shost_data);
- out_del_classdev:
- class_device_del(&shost->shost_classdev);
+ out_del_dev:
+ device_del(&shost->shost_dev);
out_del_gendev:
device_del(&shost->shost_gendev);
out:
shost->host_no);
shost->shost_gendev.release = scsi_host_dev_release;
- class_device_initialize(&shost->shost_classdev);
- shost->shost_classdev.dev = &shost->shost_gendev;
- shost->shost_classdev.class = &shost_class;
- snprintf(shost->shost_classdev.class_id, BUS_ID_SIZE, "host%d",
- shost->host_no);
+ device_initialize(&shost->shost_dev);
+ shost->shost_dev.parent = &shost->shost_gendev;
+ shost->shost_dev.class = &shost_class;
+ snprintf(shost->shost_dev.bus_id, BUS_ID_SIZE, "host%d",
+ shost->host_no);
shost->ehandler = kthread_run(scsi_error_handler, shost,
"scsi_eh_%d", shost->host_no);
}
EXPORT_SYMBOL(scsi_unregister);
-static int __scsi_host_match(struct class_device *cdev, void *data)
+static int __scsi_host_match(struct device *dev, void *data)
{
struct Scsi_Host *p;
unsigned short *hostnum = (unsigned short *)data;
- p = class_to_shost(cdev);
+ p = class_to_shost(dev);
return p->host_no == *hostnum;
}
**/
struct Scsi_Host *scsi_host_lookup(unsigned short hostnum)
{
- struct class_device *cdev;
+ struct device *cdev;
struct Scsi_Host *shost = ERR_PTR(-ENXIO);
- cdev = class_find_child(&shost_class, &hostnum, __scsi_host_match);
+ cdev = class_find_device(&shost_class, &hostnum, __scsi_host_match);
if (cdev)
shost = scsi_host_get(class_to_shost(cdev));
return queue_depth;
}
-static ssize_t hptiop_show_version(struct class_device *class_dev, char *buf)
+static ssize_t hptiop_show_version(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%s\n", driver_ver);
}
-static ssize_t hptiop_show_fw_version(struct class_device *class_dev, char *buf)
+static ssize_t hptiop_show_fw_version(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *host = class_to_shost(class_dev);
+ struct Scsi_Host *host = class_to_shost(dev);
struct hptiop_hba *hba = (struct hptiop_hba *)host->hostdata;
return snprintf(buf, PAGE_SIZE, "%d.%d.%d.%d\n",
hba->firmware_version & 0xff);
}
-static struct class_device_attribute hptiop_attr_version = {
+static struct device_attribute hptiop_attr_version = {
.attr = {
.name = "driver-version",
.mode = S_IRUGO,
.show = hptiop_show_version,
};
-static struct class_device_attribute hptiop_attr_fw_version = {
+static struct device_attribute hptiop_attr_fw_version = {
.attr = {
.name = "firmware-version",
.mode = S_IRUGO,
.show = hptiop_show_fw_version,
};
-static struct class_device_attribute *hptiop_attrs[] = {
+static struct device_attribute *hptiop_attrs[] = {
&hptiop_attr_version,
&hptiop_attr_fw_version,
NULL
/* ------------------------------------------------------------
* sysfs attributes
*/
-static ssize_t show_host_srp_version(struct class_device *class_dev, char *buf)
+static ssize_t show_host_srp_version(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ibmvscsi_host_data *hostdata = shost_priv(shost);
int len;
return len;
}
-static struct class_device_attribute ibmvscsi_host_srp_version = {
+static struct device_attribute ibmvscsi_host_srp_version = {
.attr = {
.name = "srp_version",
.mode = S_IRUGO,
.show = show_host_srp_version,
};
-static ssize_t show_host_partition_name(struct class_device *class_dev,
+static ssize_t show_host_partition_name(struct device *dev,
+ struct device_attribute *attr,
char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ibmvscsi_host_data *hostdata = shost_priv(shost);
int len;
return len;
}
-static struct class_device_attribute ibmvscsi_host_partition_name = {
+static struct device_attribute ibmvscsi_host_partition_name = {
.attr = {
.name = "partition_name",
.mode = S_IRUGO,
.show = show_host_partition_name,
};
-static ssize_t show_host_partition_number(struct class_device *class_dev,
+static ssize_t show_host_partition_number(struct device *dev,
+ struct device_attribute *attr,
char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ibmvscsi_host_data *hostdata = shost_priv(shost);
int len;
return len;
}
-static struct class_device_attribute ibmvscsi_host_partition_number = {
+static struct device_attribute ibmvscsi_host_partition_number = {
.attr = {
.name = "partition_number",
.mode = S_IRUGO,
.show = show_host_partition_number,
};
-static ssize_t show_host_mad_version(struct class_device *class_dev, char *buf)
+static ssize_t show_host_mad_version(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ibmvscsi_host_data *hostdata = shost_priv(shost);
int len;
return len;
}
-static struct class_device_attribute ibmvscsi_host_mad_version = {
+static struct device_attribute ibmvscsi_host_mad_version = {
.attr = {
.name = "mad_version",
.mode = S_IRUGO,
.show = show_host_mad_version,
};
-static ssize_t show_host_os_type(struct class_device *class_dev, char *buf)
+static ssize_t show_host_os_type(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ibmvscsi_host_data *hostdata = shost_priv(shost);
int len;
return len;
}
-static struct class_device_attribute ibmvscsi_host_os_type = {
+static struct device_attribute ibmvscsi_host_os_type = {
.attr = {
.name = "os_type",
.mode = S_IRUGO,
.show = show_host_os_type,
};
-static ssize_t show_host_config(struct class_device *class_dev, char *buf)
+static ssize_t show_host_config(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ibmvscsi_host_data *hostdata = shost_priv(shost);
/* returns null-terminated host config data */
return 0;
}
-static struct class_device_attribute ibmvscsi_host_config = {
+static struct device_attribute ibmvscsi_host_config = {
.attr = {
.name = "config",
.mode = S_IRUGO,
.show = show_host_config,
};
-static struct class_device_attribute *ibmvscsi_attrs[] = {
+static struct device_attribute *ibmvscsi_attrs[] = {
&ibmvscsi_host_srp_version,
&ibmvscsi_host_partition_name,
&ibmvscsi_host_partition_number,
return 0;
}
-static ssize_t system_id_show(struct class_device *cdev, char *buf)
+static ssize_t system_id_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%s\n", system_id);
}
-static ssize_t partition_number_show(struct class_device *cdev, char *buf)
+static ssize_t partition_number_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%x\n", partition_number);
}
-static ssize_t unit_address_show(struct class_device *cdev, char *buf)
+static ssize_t unit_address_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct srp_target *target = host_to_srp_target(shost);
struct vio_port *vport = target_to_port(target);
return snprintf(buf, PAGE_SIZE, "%x\n", vport->dma_dev->unit_address);
}
-static CLASS_DEVICE_ATTR(system_id, S_IRUGO, system_id_show, NULL);
-static CLASS_DEVICE_ATTR(partition_number, S_IRUGO, partition_number_show, NULL);
-static CLASS_DEVICE_ATTR(unit_address, S_IRUGO, unit_address_show, NULL);
+static DEVICE_ATTR(system_id, S_IRUGO, system_id_show, NULL);
+static DEVICE_ATTR(partition_number, S_IRUGO, partition_number_show, NULL);
+static DEVICE_ATTR(unit_address, S_IRUGO, unit_address_show, NULL);
-static struct class_device_attribute *ibmvstgt_attrs[] = {
- &class_device_attr_system_id,
- &class_device_attr_partition_number,
- &class_device_attr_unit_address,
+static struct device_attribute *ibmvstgt_attrs[] = {
+ &dev_attr_system_id,
+ &dev_attr_partition_number,
+ &dev_attr_unit_address,
NULL,
};
}
spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
- kobject_uevent(&ioa_cfg->host->shost_classdev.kobj, KOBJ_CHANGE);
+ kobject_uevent(&ioa_cfg->host->shost_dev.kobj, KOBJ_CHANGE);
LEAVE;
}
struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
- struct class_device *cdev = container_of(kobj,struct class_device,kobj);
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
unsigned long lock_flags = 0;
int size = IPR_TRACE_SIZE;
/**
* ipr_show_write_caching - Show the write caching attribute
- * @class_dev: class device struct
- * @buf: buffer
+ * @dev: device struct
+ * @buf: buffer
*
* Return value:
* number of bytes printed to buffer
**/
-static ssize_t ipr_show_write_caching(struct class_device *class_dev, char *buf)
+static ssize_t ipr_show_write_caching(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
unsigned long lock_flags = 0;
int i, len = 0;
/**
* ipr_store_write_caching - Enable/disable adapter write cache
- * @class_dev: class_device struct
- * @buf: buffer
- * @count: buffer size
+ * @dev: device struct
+ * @buf: buffer
+ * @count: buffer size
*
* This function will enable/disable adapter write cache.
*
* Return value:
* count on success / other on failure
**/
-static ssize_t ipr_store_write_caching(struct class_device *class_dev,
- const char *buf, size_t count)
+static ssize_t ipr_store_write_caching(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
unsigned long lock_flags = 0;
enum ipr_cache_state new_state = CACHE_INVALID;
return count;
}
-static struct class_device_attribute ipr_ioa_cache_attr = {
+static struct device_attribute ipr_ioa_cache_attr = {
.attr = {
.name = "write_cache",
.mode = S_IRUGO | S_IWUSR,
/**
* ipr_show_fw_version - Show the firmware version
- * @class_dev: class device struct
- * @buf: buffer
+ * @dev: class device struct
+ * @buf: buffer
*
* Return value:
* number of bytes printed to buffer
**/
-static ssize_t ipr_show_fw_version(struct class_device *class_dev, char *buf)
+static ssize_t ipr_show_fw_version(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
unsigned long lock_flags = 0;
return len;
}
-static struct class_device_attribute ipr_fw_version_attr = {
+static struct device_attribute ipr_fw_version_attr = {
.attr = {
.name = "fw_version",
.mode = S_IRUGO,
/**
* ipr_show_log_level - Show the adapter's error logging level
- * @class_dev: class device struct
- * @buf: buffer
+ * @dev: class device struct
+ * @buf: buffer
*
* Return value:
* number of bytes printed to buffer
**/
-static ssize_t ipr_show_log_level(struct class_device *class_dev, char *buf)
+static ssize_t ipr_show_log_level(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
unsigned long lock_flags = 0;
int len;
/**
* ipr_store_log_level - Change the adapter's error logging level
- * @class_dev: class device struct
- * @buf: buffer
+ * @dev: class device struct
+ * @buf: buffer
*
* Return value:
* number of bytes printed to buffer
**/
-static ssize_t ipr_store_log_level(struct class_device *class_dev,
+static ssize_t ipr_store_log_level(struct device *dev,
+ struct device_attribute *attr,
const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
unsigned long lock_flags = 0;
return strlen(buf);
}
-static struct class_device_attribute ipr_log_level_attr = {
+static struct device_attribute ipr_log_level_attr = {
.attr = {
.name = "log_level",
.mode = S_IRUGO | S_IWUSR,
/**
* ipr_store_diagnostics - IOA Diagnostics interface
- * @class_dev: class_device struct
- * @buf: buffer
- * @count: buffer size
+ * @dev: device struct
+ * @buf: buffer
+ * @count: buffer size
*
* This function will reset the adapter and wait a reasonable
* amount of time for any errors that the adapter might log.
* Return value:
* count on success / other on failure
**/
-static ssize_t ipr_store_diagnostics(struct class_device *class_dev,
+static ssize_t ipr_store_diagnostics(struct device *dev,
+ struct device_attribute *attr,
const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
unsigned long lock_flags = 0;
int rc = count;
return rc;
}
-static struct class_device_attribute ipr_diagnostics_attr = {
+static struct device_attribute ipr_diagnostics_attr = {
.attr = {
.name = "run_diagnostics",
.mode = S_IWUSR,
/**
* ipr_show_adapter_state - Show the adapter's state
- * @class_dev: class device struct
- * @buf: buffer
+ * @class_dev: device struct
+ * @buf: buffer
*
* Return value:
* number of bytes printed to buffer
**/
-static ssize_t ipr_show_adapter_state(struct class_device *class_dev, char *buf)
+static ssize_t ipr_show_adapter_state(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
unsigned long lock_flags = 0;
int len;
/**
* ipr_store_adapter_state - Change adapter state
- * @class_dev: class_device struct
- * @buf: buffer
- * @count: buffer size
+ * @dev: device struct
+ * @buf: buffer
+ * @count: buffer size
*
* This function will change the adapter's state.
*
* Return value:
* count on success / other on failure
**/
-static ssize_t ipr_store_adapter_state(struct class_device *class_dev,
+static ssize_t ipr_store_adapter_state(struct device *dev,
+ struct device_attribute *attr,
const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
unsigned long lock_flags;
int result = count;
return result;
}
-static struct class_device_attribute ipr_ioa_state_attr = {
+static struct device_attribute ipr_ioa_state_attr = {
.attr = {
.name = "state",
.mode = S_IRUGO | S_IWUSR,
/**
* ipr_store_reset_adapter - Reset the adapter
- * @class_dev: class_device struct
- * @buf: buffer
- * @count: buffer size
+ * @dev: device struct
+ * @buf: buffer
+ * @count: buffer size
*
* This function will reset the adapter.
*
* Return value:
* count on success / other on failure
**/
-static ssize_t ipr_store_reset_adapter(struct class_device *class_dev,
+static ssize_t ipr_store_reset_adapter(struct device *dev,
+ struct device_attribute *attr,
const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
unsigned long lock_flags;
int result = count;
return result;
}
-static struct class_device_attribute ipr_ioa_reset_attr = {
+static struct device_attribute ipr_ioa_reset_attr = {
.attr = {
.name = "reset_host",
.mode = S_IWUSR,
/**
* ipr_store_update_fw - Update the firmware on the adapter
- * @class_dev: class_device struct
- * @buf: buffer
- * @count: buffer size
+ * @class_dev: device struct
+ * @buf: buffer
+ * @count: buffer size
*
* This function will update the firmware on the adapter.
*
* Return value:
* count on success / other on failure
**/
-static ssize_t ipr_store_update_fw(struct class_device *class_dev,
- const char *buf, size_t count)
+static ssize_t ipr_store_update_fw(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
struct ipr_ucode_image_header *image_hdr;
const struct firmware *fw_entry;
return result;
}
-static struct class_device_attribute ipr_update_fw_attr = {
+static struct device_attribute ipr_update_fw_attr = {
.attr = {
.name = "update_fw",
.mode = S_IWUSR,
.store = ipr_store_update_fw
};
-static struct class_device_attribute *ipr_ioa_attrs[] = {
+static struct device_attribute *ipr_ioa_attrs[] = {
&ipr_fw_version_attr,
&ipr_log_level_attr,
&ipr_diagnostics_attr,
struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
- struct class_device *cdev = container_of(kobj,struct class_device,kobj);
+ struct device *cdev = container_of(kobj, struct device, kobj);
struct Scsi_Host *shost = class_to_shost(cdev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
struct ipr_dump *dump;
struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
- struct class_device *cdev = container_of(kobj,struct class_device,kobj);
+ struct device *cdev = container_of(kobj, struct device, kobj);
struct Scsi_Host *shost = class_to_shost(cdev);
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
int rc;
ENTER;
- ipr_remove_trace_file(&ioa_cfg->host->shost_classdev.kobj,
+ ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
&ipr_trace_attr);
- ipr_remove_dump_file(&ioa_cfg->host->shost_classdev.kobj,
+ ipr_remove_dump_file(&ioa_cfg->host->shost_dev.kobj,
&ipr_dump_attr);
scsi_remove_host(ioa_cfg->host);
return rc;
}
- rc = ipr_create_trace_file(&ioa_cfg->host->shost_classdev.kobj,
+ rc = ipr_create_trace_file(&ioa_cfg->host->shost_dev.kobj,
&ipr_trace_attr);
if (rc) {
return rc;
}
- rc = ipr_create_dump_file(&ioa_cfg->host->shost_classdev.kobj,
+ rc = ipr_create_dump_file(&ioa_cfg->host->shost_dev.kobj,
&ipr_dump_attr);
if (rc) {
- ipr_remove_trace_file(&ioa_cfg->host->shost_classdev.kobj,
+ ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
&ipr_trace_attr);
scsi_remove_host(ioa_cfg->host);
__ipr_remove(pdev);
}
static ssize_t
-lpfc_drvr_version_show(struct class_device *cdev, char *buf)
+lpfc_drvr_version_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
return snprintf(buf, PAGE_SIZE, LPFC_MODULE_DESC "\n");
}
static ssize_t
-lpfc_info_show(struct class_device *cdev, char *buf)
+lpfc_info_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *host = class_to_shost(cdev);
+ struct Scsi_Host *host = class_to_shost(dev);
return snprintf(buf, PAGE_SIZE, "%s\n",lpfc_info(host));
}
static ssize_t
-lpfc_serialnum_show(struct class_device *cdev, char *buf)
+lpfc_serialnum_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
}
static ssize_t
-lpfc_temp_sensor_show(struct class_device *cdev, char *buf)
+lpfc_temp_sensor_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
return snprintf(buf, PAGE_SIZE, "%d\n",phba->temp_sensor_support);
}
static ssize_t
-lpfc_modeldesc_show(struct class_device *cdev, char *buf)
+lpfc_modeldesc_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
}
static ssize_t
-lpfc_modelname_show(struct class_device *cdev, char *buf)
+lpfc_modelname_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
}
static ssize_t
-lpfc_programtype_show(struct class_device *cdev, char *buf)
+lpfc_programtype_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
}
static ssize_t
-lpfc_vportnum_show(struct class_device *cdev, char *buf)
+lpfc_vportnum_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
}
static ssize_t
-lpfc_fwrev_show(struct class_device *cdev, char *buf)
+lpfc_fwrev_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
char fwrev[32];
}
static ssize_t
-lpfc_hdw_show(struct class_device *cdev, char *buf)
+lpfc_hdw_show(struct device *dev, struct device_attribute *attr, char *buf)
{
char hdw[9];
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
lpfc_vpd_t *vp = &phba->vpd;
return snprintf(buf, PAGE_SIZE, "%s\n", hdw);
}
static ssize_t
-lpfc_option_rom_version_show(struct class_device *cdev, char *buf)
+lpfc_option_rom_version_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
return snprintf(buf, PAGE_SIZE, "%s\n", phba->OptionROMVersion);
}
static ssize_t
-lpfc_state_show(struct class_device *cdev, char *buf)
+lpfc_state_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
int len = 0;
}
static ssize_t
-lpfc_num_discovered_ports_show(struct class_device *cdev, char *buf)
+lpfc_num_discovered_ports_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
return snprintf(buf, PAGE_SIZE, "%d\n",
}
static ssize_t
-lpfc_issue_reset(struct class_device *cdev, const char *buf, size_t count)
+lpfc_issue_reset(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
}
static ssize_t
-lpfc_nport_evt_cnt_show(struct class_device *cdev, char *buf)
+lpfc_nport_evt_cnt_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
}
static ssize_t
-lpfc_board_mode_show(struct class_device *cdev, char *buf)
+lpfc_board_mode_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
char * state;
}
static ssize_t
-lpfc_board_mode_store(struct class_device *cdev, const char *buf, size_t count)
+lpfc_board_mode_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
struct completion online_compl;
}
static ssize_t
-lpfc_max_rpi_show(struct class_device *cdev, char *buf)
+lpfc_max_rpi_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
uint32_t cnt;
}
static ssize_t
-lpfc_used_rpi_show(struct class_device *cdev, char *buf)
+lpfc_used_rpi_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
uint32_t cnt, acnt;
}
static ssize_t
-lpfc_max_xri_show(struct class_device *cdev, char *buf)
+lpfc_max_xri_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
uint32_t cnt;
}
static ssize_t
-lpfc_used_xri_show(struct class_device *cdev, char *buf)
+lpfc_used_xri_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
uint32_t cnt, acnt;
}
static ssize_t
-lpfc_max_vpi_show(struct class_device *cdev, char *buf)
+lpfc_max_vpi_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
uint32_t cnt;
}
static ssize_t
-lpfc_used_vpi_show(struct class_device *cdev, char *buf)
+lpfc_used_vpi_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
uint32_t cnt, acnt;
}
static ssize_t
-lpfc_npiv_info_show(struct class_device *cdev, char *buf)
+lpfc_npiv_info_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
}
static ssize_t
-lpfc_poll_show(struct class_device *cdev, char *buf)
+lpfc_poll_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
}
static ssize_t
-lpfc_poll_store(struct class_device *cdev, const char *buf,
- size_t count)
+lpfc_poll_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
uint32_t creg_val;
#define lpfc_param_show(attr) \
static ssize_t \
-lpfc_##attr##_show(struct class_device *cdev, char *buf) \
+lpfc_##attr##_show(struct device *dev, struct device_attribute *attr, \
+ char *buf) \
{ \
- struct Scsi_Host *shost = class_to_shost(cdev);\
+ struct Scsi_Host *shost = class_to_shost(dev);\
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;\
struct lpfc_hba *phba = vport->phba;\
int val = 0;\
#define lpfc_param_hex_show(attr) \
static ssize_t \
-lpfc_##attr##_show(struct class_device *cdev, char *buf) \
+lpfc_##attr##_show(struct device *dev, struct device_attribute *attr, \
+ char *buf) \
{ \
- struct Scsi_Host *shost = class_to_shost(cdev);\
+ struct Scsi_Host *shost = class_to_shost(dev);\
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;\
struct lpfc_hba *phba = vport->phba;\
int val = 0;\
#define lpfc_param_store(attr) \
static ssize_t \
-lpfc_##attr##_store(struct class_device *cdev, const char *buf, size_t count) \
+lpfc_##attr##_store(struct device *dev, struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
- struct Scsi_Host *shost = class_to_shost(cdev);\
+ struct Scsi_Host *shost = class_to_shost(dev);\
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;\
struct lpfc_hba *phba = vport->phba;\
int val=0;\
#define lpfc_vport_param_show(attr) \
static ssize_t \
-lpfc_##attr##_show(struct class_device *cdev, char *buf) \
+lpfc_##attr##_show(struct device *dev, struct device_attribute *attr, \
+ char *buf) \
{ \
- struct Scsi_Host *shost = class_to_shost(cdev);\
+ struct Scsi_Host *shost = class_to_shost(dev);\
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;\
int val = 0;\
val = vport->cfg_##attr;\
#define lpfc_vport_param_hex_show(attr) \
static ssize_t \
-lpfc_##attr##_show(struct class_device *cdev, char *buf) \
+lpfc_##attr##_show(struct device *dev, struct device_attribute *attr, \
+ char *buf) \
{ \
- struct Scsi_Host *shost = class_to_shost(cdev);\
+ struct Scsi_Host *shost = class_to_shost(dev);\
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;\
int val = 0;\
val = vport->cfg_##attr;\
#define lpfc_vport_param_store(attr) \
static ssize_t \
-lpfc_##attr##_store(struct class_device *cdev, const char *buf, size_t count) \
+lpfc_##attr##_store(struct device *dev, struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
- struct Scsi_Host *shost = class_to_shost(cdev);\
+ struct Scsi_Host *shost = class_to_shost(dev);\
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;\
int val=0;\
if (!isdigit(buf[0]))\
MODULE_PARM_DESC(lpfc_##name, desc);\
lpfc_param_show(name)\
lpfc_param_init(name, defval, minval, maxval)\
-static CLASS_DEVICE_ATTR(lpfc_##name, S_IRUGO , lpfc_##name##_show, NULL)
+static DEVICE_ATTR(lpfc_##name, S_IRUGO , lpfc_##name##_show, NULL)
#define LPFC_ATTR_RW(name, defval, minval, maxval, desc) \
static int lpfc_##name = defval;\
lpfc_param_init(name, defval, minval, maxval)\
lpfc_param_set(name, defval, minval, maxval)\
lpfc_param_store(name)\
-static CLASS_DEVICE_ATTR(lpfc_##name, S_IRUGO | S_IWUSR,\
- lpfc_##name##_show, lpfc_##name##_store)
+static DEVICE_ATTR(lpfc_##name, S_IRUGO | S_IWUSR,\
+ lpfc_##name##_show, lpfc_##name##_store)
#define LPFC_ATTR_HEX_R(name, defval, minval, maxval, desc) \
static int lpfc_##name = defval;\
MODULE_PARM_DESC(lpfc_##name, desc);\
lpfc_param_hex_show(name)\
lpfc_param_init(name, defval, minval, maxval)\
-static CLASS_DEVICE_ATTR(lpfc_##name, S_IRUGO , lpfc_##name##_show, NULL)
+static DEVICE_ATTR(lpfc_##name, S_IRUGO , lpfc_##name##_show, NULL)
#define LPFC_ATTR_HEX_RW(name, defval, minval, maxval, desc) \
static int lpfc_##name = defval;\
lpfc_param_init(name, defval, minval, maxval)\
lpfc_param_set(name, defval, minval, maxval)\
lpfc_param_store(name)\
-static CLASS_DEVICE_ATTR(lpfc_##name, S_IRUGO | S_IWUSR,\
- lpfc_##name##_show, lpfc_##name##_store)
+static DEVICE_ATTR(lpfc_##name, S_IRUGO | S_IWUSR,\
+ lpfc_##name##_show, lpfc_##name##_store)
#define LPFC_VPORT_ATTR(name, defval, minval, maxval, desc) \
static int lpfc_##name = defval;\
MODULE_PARM_DESC(lpfc_##name, desc);\
lpfc_vport_param_show(name)\
lpfc_vport_param_init(name, defval, minval, maxval)\
-static CLASS_DEVICE_ATTR(lpfc_##name, S_IRUGO , lpfc_##name##_show, NULL)
+static DEVICE_ATTR(lpfc_##name, S_IRUGO , lpfc_##name##_show, NULL)
#define LPFC_VPORT_ATTR_RW(name, defval, minval, maxval, desc) \
static int lpfc_##name = defval;\
lpfc_vport_param_init(name, defval, minval, maxval)\
lpfc_vport_param_set(name, defval, minval, maxval)\
lpfc_vport_param_store(name)\
-static CLASS_DEVICE_ATTR(lpfc_##name, S_IRUGO | S_IWUSR,\
- lpfc_##name##_show, lpfc_##name##_store)
+static DEVICE_ATTR(lpfc_##name, S_IRUGO | S_IWUSR,\
+ lpfc_##name##_show, lpfc_##name##_store)
#define LPFC_VPORT_ATTR_HEX_R(name, defval, minval, maxval, desc) \
static int lpfc_##name = defval;\
MODULE_PARM_DESC(lpfc_##name, desc);\
lpfc_vport_param_hex_show(name)\
lpfc_vport_param_init(name, defval, minval, maxval)\
-static CLASS_DEVICE_ATTR(lpfc_##name, S_IRUGO , lpfc_##name##_show, NULL)
+static DEVICE_ATTR(lpfc_##name, S_IRUGO , lpfc_##name##_show, NULL)
#define LPFC_VPORT_ATTR_HEX_RW(name, defval, minval, maxval, desc) \
static int lpfc_##name = defval;\
lpfc_vport_param_init(name, defval, minval, maxval)\
lpfc_vport_param_set(name, defval, minval, maxval)\
lpfc_vport_param_store(name)\
-static CLASS_DEVICE_ATTR(lpfc_##name, S_IRUGO | S_IWUSR,\
- lpfc_##name##_show, lpfc_##name##_store)
-
-static CLASS_DEVICE_ATTR(info, S_IRUGO, lpfc_info_show, NULL);
-static CLASS_DEVICE_ATTR(serialnum, S_IRUGO, lpfc_serialnum_show, NULL);
-static CLASS_DEVICE_ATTR(modeldesc, S_IRUGO, lpfc_modeldesc_show, NULL);
-static CLASS_DEVICE_ATTR(modelname, S_IRUGO, lpfc_modelname_show, NULL);
-static CLASS_DEVICE_ATTR(programtype, S_IRUGO, lpfc_programtype_show, NULL);
-static CLASS_DEVICE_ATTR(portnum, S_IRUGO, lpfc_vportnum_show, NULL);
-static CLASS_DEVICE_ATTR(fwrev, S_IRUGO, lpfc_fwrev_show, NULL);
-static CLASS_DEVICE_ATTR(hdw, S_IRUGO, lpfc_hdw_show, NULL);
-static CLASS_DEVICE_ATTR(state, S_IRUGO, lpfc_state_show, NULL);
-static CLASS_DEVICE_ATTR(option_rom_version, S_IRUGO,
- lpfc_option_rom_version_show, NULL);
-static CLASS_DEVICE_ATTR(num_discovered_ports, S_IRUGO,
- lpfc_num_discovered_ports_show, NULL);
-static CLASS_DEVICE_ATTR(nport_evt_cnt, S_IRUGO, lpfc_nport_evt_cnt_show, NULL);
-static CLASS_DEVICE_ATTR(lpfc_drvr_version, S_IRUGO, lpfc_drvr_version_show,
- NULL);
-static CLASS_DEVICE_ATTR(board_mode, S_IRUGO | S_IWUSR,
- lpfc_board_mode_show, lpfc_board_mode_store);
-static CLASS_DEVICE_ATTR(issue_reset, S_IWUSR, NULL, lpfc_issue_reset);
-static CLASS_DEVICE_ATTR(max_vpi, S_IRUGO, lpfc_max_vpi_show, NULL);
-static CLASS_DEVICE_ATTR(used_vpi, S_IRUGO, lpfc_used_vpi_show, NULL);
-static CLASS_DEVICE_ATTR(max_rpi, S_IRUGO, lpfc_max_rpi_show, NULL);
-static CLASS_DEVICE_ATTR(used_rpi, S_IRUGO, lpfc_used_rpi_show, NULL);
-static CLASS_DEVICE_ATTR(max_xri, S_IRUGO, lpfc_max_xri_show, NULL);
-static CLASS_DEVICE_ATTR(used_xri, S_IRUGO, lpfc_used_xri_show, NULL);
-static CLASS_DEVICE_ATTR(npiv_info, S_IRUGO, lpfc_npiv_info_show, NULL);
-static CLASS_DEVICE_ATTR(lpfc_temp_sensor, S_IRUGO, lpfc_temp_sensor_show,
- NULL);
+static DEVICE_ATTR(lpfc_##name, S_IRUGO | S_IWUSR,\
+ lpfc_##name##_show, lpfc_##name##_store)
+
+static DEVICE_ATTR(info, S_IRUGO, lpfc_info_show, NULL);
+static DEVICE_ATTR(serialnum, S_IRUGO, lpfc_serialnum_show, NULL);
+static DEVICE_ATTR(modeldesc, S_IRUGO, lpfc_modeldesc_show, NULL);
+static DEVICE_ATTR(modelname, S_IRUGO, lpfc_modelname_show, NULL);
+static DEVICE_ATTR(programtype, S_IRUGO, lpfc_programtype_show, NULL);
+static DEVICE_ATTR(portnum, S_IRUGO, lpfc_vportnum_show, NULL);
+static DEVICE_ATTR(fwrev, S_IRUGO, lpfc_fwrev_show, NULL);
+static DEVICE_ATTR(hdw, S_IRUGO, lpfc_hdw_show, NULL);
+static DEVICE_ATTR(state, S_IRUGO, lpfc_state_show, NULL);
+static DEVICE_ATTR(option_rom_version, S_IRUGO,
+ lpfc_option_rom_version_show, NULL);
+static DEVICE_ATTR(num_discovered_ports, S_IRUGO,
+ lpfc_num_discovered_ports_show, NULL);
+static DEVICE_ATTR(nport_evt_cnt, S_IRUGO, lpfc_nport_evt_cnt_show, NULL);
+static DEVICE_ATTR(lpfc_drvr_version, S_IRUGO, lpfc_drvr_version_show, NULL);
+static DEVICE_ATTR(board_mode, S_IRUGO | S_IWUSR,
+ lpfc_board_mode_show, lpfc_board_mode_store);
+static DEVICE_ATTR(issue_reset, S_IWUSR, NULL, lpfc_issue_reset);
+static DEVICE_ATTR(max_vpi, S_IRUGO, lpfc_max_vpi_show, NULL);
+static DEVICE_ATTR(used_vpi, S_IRUGO, lpfc_used_vpi_show, NULL);
+static DEVICE_ATTR(max_rpi, S_IRUGO, lpfc_max_rpi_show, NULL);
+static DEVICE_ATTR(used_rpi, S_IRUGO, lpfc_used_rpi_show, NULL);
+static DEVICE_ATTR(max_xri, S_IRUGO, lpfc_max_xri_show, NULL);
+static DEVICE_ATTR(used_xri, S_IRUGO, lpfc_used_xri_show, NULL);
+static DEVICE_ATTR(npiv_info, S_IRUGO, lpfc_npiv_info_show, NULL);
+static DEVICE_ATTR(lpfc_temp_sensor, S_IRUGO, lpfc_temp_sensor_show, NULL);
static char *lpfc_soft_wwn_key = "C99G71SL8032A";
static ssize_t
-lpfc_soft_wwn_enable_store(struct class_device *cdev, const char *buf,
- size_t count)
+lpfc_soft_wwn_enable_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
unsigned int cnt = count;
phba->soft_wwn_enable = 1;
return count;
}
-static CLASS_DEVICE_ATTR(lpfc_soft_wwn_enable, S_IWUSR, NULL,
- lpfc_soft_wwn_enable_store);
+static DEVICE_ATTR(lpfc_soft_wwn_enable, S_IWUSR, NULL,
+ lpfc_soft_wwn_enable_store);
static ssize_t
-lpfc_soft_wwpn_show(struct class_device *cdev, char *buf)
+lpfc_soft_wwpn_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
static ssize_t
-lpfc_soft_wwpn_store(struct class_device *cdev, const char *buf, size_t count)
+lpfc_soft_wwpn_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
struct completion online_compl;
"reinit adapter - %d\n", stat2);
return (stat1 || stat2) ? -EIO : count;
}
-static CLASS_DEVICE_ATTR(lpfc_soft_wwpn, S_IRUGO | S_IWUSR,\
- lpfc_soft_wwpn_show, lpfc_soft_wwpn_store);
+static DEVICE_ATTR(lpfc_soft_wwpn, S_IRUGO | S_IWUSR,\
+ lpfc_soft_wwpn_show, lpfc_soft_wwpn_store);
static ssize_t
-lpfc_soft_wwnn_show(struct class_device *cdev, char *buf)
+lpfc_soft_wwnn_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
return snprintf(buf, PAGE_SIZE, "0x%llx\n",
(unsigned long long)phba->cfg_soft_wwnn);
static ssize_t
-lpfc_soft_wwnn_store(struct class_device *cdev, const char *buf, size_t count)
+lpfc_soft_wwnn_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
unsigned int i, j, cnt=count;
u8 wwnn[8];
return count;
}
-static CLASS_DEVICE_ATTR(lpfc_soft_wwnn, S_IRUGO | S_IWUSR,\
- lpfc_soft_wwnn_show, lpfc_soft_wwnn_store);
+static DEVICE_ATTR(lpfc_soft_wwnn, S_IRUGO | S_IWUSR,\
+ lpfc_soft_wwnn_show, lpfc_soft_wwnn_store);
static int lpfc_poll = 0;
" 1 - poll with interrupts enabled"
" 3 - poll and disable FCP ring interrupts");
-static CLASS_DEVICE_ATTR(lpfc_poll, S_IRUGO | S_IWUSR,
- lpfc_poll_show, lpfc_poll_store);
+static DEVICE_ATTR(lpfc_poll, S_IRUGO | S_IWUSR,
+ lpfc_poll_show, lpfc_poll_store);
int lpfc_sli_mode = 0;
module_param(lpfc_sli_mode, int, 0);
MODULE_PARM_DESC(lpfc_enable_npiv, "Enable NPIV functionality");
lpfc_param_show(enable_npiv);
lpfc_param_init(enable_npiv, 0, 0, 1);
-static CLASS_DEVICE_ATTR(lpfc_enable_npiv, S_IRUGO,
+static DEVICE_ATTR(lpfc_enable_npiv, S_IRUGO,
lpfc_enable_npiv_show, NULL);
/*
"Seconds driver will hold I/O waiting "
"for a device to come back");
static ssize_t
-lpfc_nodev_tmo_show(struct class_device *cdev, char *buf)
+lpfc_nodev_tmo_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
int val = 0;
val = vport->cfg_devloss_tmo;
lpfc_vport_param_store(nodev_tmo)
-static CLASS_DEVICE_ATTR(lpfc_nodev_tmo, S_IRUGO | S_IWUSR,
- lpfc_nodev_tmo_show, lpfc_nodev_tmo_store);
+static DEVICE_ATTR(lpfc_nodev_tmo, S_IRUGO | S_IWUSR,
+ lpfc_nodev_tmo_show, lpfc_nodev_tmo_store);
/*
# lpfc_devloss_tmo: If set, it will hold all I/O errors on devices that
}
lpfc_vport_param_store(devloss_tmo)
-static CLASS_DEVICE_ATTR(lpfc_devloss_tmo, S_IRUGO | S_IWUSR,
- lpfc_devloss_tmo_show, lpfc_devloss_tmo_store);
+static DEVICE_ATTR(lpfc_devloss_tmo, S_IRUGO | S_IWUSR,
+ lpfc_devloss_tmo_show, lpfc_devloss_tmo_store);
/*
# lpfc_log_verbose: Only turn this flag on if you are willing to risk being
return 0;
}
lpfc_vport_param_store(restrict_login);
-static CLASS_DEVICE_ATTR(lpfc_restrict_login, S_IRUGO | S_IWUSR,
- lpfc_restrict_login_show, lpfc_restrict_login_store);
+static DEVICE_ATTR(lpfc_restrict_login, S_IRUGO | S_IWUSR,
+ lpfc_restrict_login_show, lpfc_restrict_login_store);
/*
# Some disk devices have a "select ID" or "select Target" capability.
lpfc_param_show(topology)
lpfc_param_init(topology, 0, 0, 6)
lpfc_param_store(topology)
-static CLASS_DEVICE_ATTR(lpfc_topology, S_IRUGO | S_IWUSR,
+static DEVICE_ATTR(lpfc_topology, S_IRUGO | S_IWUSR,
lpfc_topology_show, lpfc_topology_store);
/*
}
lpfc_param_store(link_speed)
-static CLASS_DEVICE_ATTR(lpfc_link_speed, S_IRUGO | S_IWUSR,
+static DEVICE_ATTR(lpfc_link_speed, S_IRUGO | S_IWUSR,
lpfc_link_speed_show, lpfc_link_speed_store);
/*
LPFC_ATTR_R(sg_seg_cnt, LPFC_DEFAULT_SG_SEG_CNT, LPFC_DEFAULT_SG_SEG_CNT,
LPFC_MAX_SG_SEG_CNT, "Max Scatter Gather Segment Count");
-struct class_device_attribute *lpfc_hba_attrs[] = {
- &class_device_attr_info,
- &class_device_attr_serialnum,
- &class_device_attr_modeldesc,
- &class_device_attr_modelname,
- &class_device_attr_programtype,
- &class_device_attr_portnum,
- &class_device_attr_fwrev,
- &class_device_attr_hdw,
- &class_device_attr_option_rom_version,
- &class_device_attr_state,
- &class_device_attr_num_discovered_ports,
- &class_device_attr_lpfc_drvr_version,
- &class_device_attr_lpfc_temp_sensor,
- &class_device_attr_lpfc_log_verbose,
- &class_device_attr_lpfc_lun_queue_depth,
- &class_device_attr_lpfc_hba_queue_depth,
- &class_device_attr_lpfc_peer_port_login,
- &class_device_attr_lpfc_nodev_tmo,
- &class_device_attr_lpfc_devloss_tmo,
- &class_device_attr_lpfc_fcp_class,
- &class_device_attr_lpfc_use_adisc,
- &class_device_attr_lpfc_ack0,
- &class_device_attr_lpfc_topology,
- &class_device_attr_lpfc_scan_down,
- &class_device_attr_lpfc_link_speed,
- &class_device_attr_lpfc_cr_delay,
- &class_device_attr_lpfc_cr_count,
- &class_device_attr_lpfc_multi_ring_support,
- &class_device_attr_lpfc_multi_ring_rctl,
- &class_device_attr_lpfc_multi_ring_type,
- &class_device_attr_lpfc_fdmi_on,
- &class_device_attr_lpfc_max_luns,
- &class_device_attr_lpfc_enable_npiv,
- &class_device_attr_nport_evt_cnt,
- &class_device_attr_board_mode,
- &class_device_attr_max_vpi,
- &class_device_attr_used_vpi,
- &class_device_attr_max_rpi,
- &class_device_attr_used_rpi,
- &class_device_attr_max_xri,
- &class_device_attr_used_xri,
- &class_device_attr_npiv_info,
- &class_device_attr_issue_reset,
- &class_device_attr_lpfc_poll,
- &class_device_attr_lpfc_poll_tmo,
- &class_device_attr_lpfc_use_msi,
- &class_device_attr_lpfc_soft_wwnn,
- &class_device_attr_lpfc_soft_wwpn,
- &class_device_attr_lpfc_soft_wwn_enable,
- &class_device_attr_lpfc_enable_hba_reset,
- &class_device_attr_lpfc_enable_hba_heartbeat,
- &class_device_attr_lpfc_sg_seg_cnt,
+struct device_attribute *lpfc_hba_attrs[] = {
+ &dev_attr_info,
+ &dev_attr_serialnum,
+ &dev_attr_modeldesc,
+ &dev_attr_modelname,
+ &dev_attr_programtype,
+ &dev_attr_portnum,
+ &dev_attr_fwrev,
+ &dev_attr_hdw,
+ &dev_attr_option_rom_version,
+ &dev_attr_state,
+ &dev_attr_num_discovered_ports,
+ &dev_attr_lpfc_drvr_version,
+ &dev_attr_lpfc_temp_sensor,
+ &dev_attr_lpfc_log_verbose,
+ &dev_attr_lpfc_lun_queue_depth,
+ &dev_attr_lpfc_hba_queue_depth,
+ &dev_attr_lpfc_peer_port_login,
+ &dev_attr_lpfc_nodev_tmo,
+ &dev_attr_lpfc_devloss_tmo,
+ &dev_attr_lpfc_fcp_class,
+ &dev_attr_lpfc_use_adisc,
+ &dev_attr_lpfc_ack0,
+ &dev_attr_lpfc_topology,
+ &dev_attr_lpfc_scan_down,
+ &dev_attr_lpfc_link_speed,
+ &dev_attr_lpfc_cr_delay,
+ &dev_attr_lpfc_cr_count,
+ &dev_attr_lpfc_multi_ring_support,
+ &dev_attr_lpfc_multi_ring_rctl,
+ &dev_attr_lpfc_multi_ring_type,
+ &dev_attr_lpfc_fdmi_on,
+ &dev_attr_lpfc_max_luns,
+ &dev_attr_lpfc_enable_npiv,
+ &dev_attr_nport_evt_cnt,
+ &dev_attr_board_mode,
+ &dev_attr_max_vpi,
+ &dev_attr_used_vpi,
+ &dev_attr_max_rpi,
+ &dev_attr_used_rpi,
+ &dev_attr_max_xri,
+ &dev_attr_used_xri,
+ &dev_attr_npiv_info,
+ &dev_attr_issue_reset,
+ &dev_attr_lpfc_poll,
+ &dev_attr_lpfc_poll_tmo,
+ &dev_attr_lpfc_use_msi,
+ &dev_attr_lpfc_soft_wwnn,
+ &dev_attr_lpfc_soft_wwpn,
+ &dev_attr_lpfc_soft_wwn_enable,
+ &dev_attr_lpfc_enable_hba_reset,
+ &dev_attr_lpfc_enable_hba_heartbeat,
+ &dev_attr_lpfc_sg_seg_cnt,
NULL,
};
-struct class_device_attribute *lpfc_vport_attrs[] = {
- &class_device_attr_info,
- &class_device_attr_state,
- &class_device_attr_num_discovered_ports,
- &class_device_attr_lpfc_drvr_version,
-
- &class_device_attr_lpfc_log_verbose,
- &class_device_attr_lpfc_lun_queue_depth,
- &class_device_attr_lpfc_nodev_tmo,
- &class_device_attr_lpfc_devloss_tmo,
- &class_device_attr_lpfc_hba_queue_depth,
- &class_device_attr_lpfc_peer_port_login,
- &class_device_attr_lpfc_restrict_login,
- &class_device_attr_lpfc_fcp_class,
- &class_device_attr_lpfc_use_adisc,
- &class_device_attr_lpfc_fdmi_on,
- &class_device_attr_lpfc_max_luns,
- &class_device_attr_nport_evt_cnt,
- &class_device_attr_npiv_info,
- &class_device_attr_lpfc_enable_da_id,
+struct device_attribute *lpfc_vport_attrs[] = {
+ &dev_attr_info,
+ &dev_attr_state,
+ &dev_attr_num_discovered_ports,
+ &dev_attr_lpfc_drvr_version,
+ &dev_attr_lpfc_log_verbose,
+ &dev_attr_lpfc_lun_queue_depth,
+ &dev_attr_lpfc_nodev_tmo,
+ &dev_attr_lpfc_devloss_tmo,
+ &dev_attr_lpfc_hba_queue_depth,
+ &dev_attr_lpfc_peer_port_login,
+ &dev_attr_lpfc_restrict_login,
+ &dev_attr_lpfc_fcp_class,
+ &dev_attr_lpfc_use_adisc,
+ &dev_attr_lpfc_fdmi_on,
+ &dev_attr_lpfc_max_luns,
+ &dev_attr_nport_evt_cnt,
+ &dev_attr_npiv_info,
+ &dev_attr_lpfc_enable_da_id,
NULL,
};
char *buf, loff_t off, size_t count)
{
size_t buf_off;
- struct class_device *cdev = container_of(kobj, struct class_device,
- kobj);
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
{
size_t buf_off;
uint32_t * tmp_ptr;
- struct class_device *cdev = container_of(kobj, struct class_device,
- kobj);
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
sysfs_mbox_write(struct kobject *kobj, struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
- struct class_device *cdev = container_of(kobj, struct class_device,
- kobj);
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
struct lpfcMboxq *mbox = NULL;
sysfs_mbox_read(struct kobject *kobj, struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
- struct class_device *cdev = container_of(kobj, struct class_device,
- kobj);
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct Scsi_Host *shost = class_to_shost(dev);
struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
struct lpfc_hba *phba = vport->phba;
int rc;
struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
int error;
- error = sysfs_create_bin_file(&shost->shost_classdev.kobj,
+ error = sysfs_create_bin_file(&shost->shost_dev.kobj,
&sysfs_ctlreg_attr);
if (error)
goto out;
- error = sysfs_create_bin_file(&shost->shost_classdev.kobj,
+ error = sysfs_create_bin_file(&shost->shost_dev.kobj,
&sysfs_mbox_attr);
if (error)
goto out_remove_ctlreg_attr;
return 0;
out_remove_ctlreg_attr:
- sysfs_remove_bin_file(&shost->shost_classdev.kobj, &sysfs_ctlreg_attr);
+ sysfs_remove_bin_file(&shost->shost_dev.kobj, &sysfs_ctlreg_attr);
out:
return error;
}
{
struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
- sysfs_remove_bin_file(&shost->shost_classdev.kobj, &sysfs_mbox_attr);
- sysfs_remove_bin_file(&shost->shost_classdev.kobj, &sysfs_ctlreg_attr);
+ sysfs_remove_bin_file(&shost->shost_dev.kobj, &sysfs_mbox_attr);
+ sysfs_remove_bin_file(&shost->shost_dev.kobj, &sysfs_ctlreg_attr);
}
#define lpfc_rport_show_function(field, format_string, sz, cast) \
static ssize_t \
-lpfc_show_rport_##field (struct class_device *cdev, char *buf) \
+lpfc_show_rport_##field (struct device *dev, \
+ struct device_attribute *attr, \
+ char *buf) \
{ \
- struct fc_rport *rport = transport_class_to_rport(cdev); \
+ struct fc_rport *rport = transport_class_to_rport(dev); \
struct lpfc_rport_data *rdata = rport->hostdata; \
return snprintf(buf, sz, format_string, \
(rdata->target) ? cast rdata->target->field : 0); \
void lpfc_get_vport_cfgparam(struct lpfc_vport *);
int lpfc_alloc_sysfs_attr(struct lpfc_vport *);
void lpfc_free_sysfs_attr(struct lpfc_vport *);
-extern struct class_device_attribute *lpfc_hba_attrs[];
-extern struct class_device_attribute *lpfc_vport_attrs[];
+extern struct device_attribute *lpfc_hba_attrs[];
+extern struct device_attribute *lpfc_vport_attrs[];
extern struct scsi_host_template lpfc_template;
extern struct scsi_host_template lpfc_vport_template;
extern struct fc_function_template lpfc_transport_functions;
#include <linux/list.h>
#include <linux/moduleparam.h>
#include <linux/dma-mapping.h>
-#include <asm/semaphore.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#define _MEGARAID_IOCTL_H_
#include <linux/types.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include "mbox_defs.h"
static void megaraid_mbox_dpc(unsigned long);
-static ssize_t megaraid_sysfs_show_app_hndl(struct class_device *, char *);
+static ssize_t megaraid_sysfs_show_app_hndl(struct device *, struct device_attribute *attr, char *);
static ssize_t megaraid_sysfs_show_ldnum(struct device *, struct device_attribute *attr, char *);
static int megaraid_cmm_register(adapter_t *);
// definitions for the device attributes for exporting logical drive number
// for a scsi address (Host, Channel, Id, Lun)
-CLASS_DEVICE_ATTR(megaraid_mbox_app_hndl, S_IRUSR, megaraid_sysfs_show_app_hndl,
+DEVICE_ATTR(megaraid_mbox_app_hndl, S_IRUSR, megaraid_sysfs_show_app_hndl,
NULL);
// Host template initializer for megaraid mbox sysfs device attributes
-static struct class_device_attribute *megaraid_shost_attrs[] = {
- &class_device_attr_megaraid_mbox_app_hndl,
+static struct device_attribute *megaraid_shost_attrs[] = {
+ &dev_attr_megaraid_mbox_app_hndl,
NULL,
};
* handle, since we do not interface with applications directly.
*/
static ssize_t
-megaraid_sysfs_show_app_hndl(struct class_device *cdev, char *buf)
+megaraid_sysfs_show_app_hndl(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(cdev);
+ struct Scsi_Host *shost = class_to_shost(dev);
adapter_t *adapter = (adapter_t *)SCSIHOST2ADAP(shost);
uint32_t app_hndl;
#undef next_wcmd
-static ssize_t show_ncr53c8xx_revision(struct class_device *dev, char *buf)
+static ssize_t show_ncr53c8xx_revision(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
struct Scsi_Host *host = class_to_shost(dev);
struct host_data *host_data = (struct host_data *)host->hostdata;
return snprintf(buf, 20, "0x%x\n", host_data->ncb->revision_id);
}
-static struct class_device_attribute ncr53c8xx_revision_attr = {
+static struct device_attribute ncr53c8xx_revision_attr = {
.attr = { .name = "revision", .mode = S_IRUGO, },
.show = show_ncr53c8xx_revision,
};
-static struct class_device_attribute *ncr53c8xx_host_attrs[] = {
+static struct device_attribute *ncr53c8xx_host_attrs[] = {
&ncr53c8xx_revision_attr,
NULL
};
* sysfs support for accessing ADR header information
*/
-static ssize_t osst_adr_rev_show(struct class_device *class_dev, char *buf)
+static ssize_t osst_adr_rev_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct osst_tape * STp = (struct osst_tape *) class_get_devdata (class_dev);
+ struct osst_tape * STp = (struct osst_tape *) dev_get_drvdata (dev);
ssize_t l = 0;
if (STp && STp->header_ok && STp->linux_media)
return l;
}
-CLASS_DEVICE_ATTR(ADR_rev, S_IRUGO, osst_adr_rev_show, NULL);
+DEVICE_ATTR(ADR_rev, S_IRUGO, osst_adr_rev_show, NULL);
-static ssize_t osst_linux_media_version_show(struct class_device *class_dev, char *buf)
+static ssize_t osst_linux_media_version_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
- struct osst_tape * STp = (struct osst_tape *) class_get_devdata (class_dev);
+ struct osst_tape * STp = (struct osst_tape *) dev_get_drvdata (dev);
ssize_t l = 0;
if (STp && STp->header_ok && STp->linux_media)
return l;
}
-CLASS_DEVICE_ATTR(media_version, S_IRUGO, osst_linux_media_version_show, NULL);
+DEVICE_ATTR(media_version, S_IRUGO, osst_linux_media_version_show, NULL);
-static ssize_t osst_capacity_show(struct class_device *class_dev, char *buf)
+static ssize_t osst_capacity_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct osst_tape * STp = (struct osst_tape *) class_get_devdata (class_dev);
+ struct osst_tape * STp = (struct osst_tape *) dev_get_drvdata (dev);
ssize_t l = 0;
if (STp && STp->header_ok && STp->linux_media)
return l;
}
-CLASS_DEVICE_ATTR(capacity, S_IRUGO, osst_capacity_show, NULL);
+DEVICE_ATTR(capacity, S_IRUGO, osst_capacity_show, NULL);
-static ssize_t osst_first_data_ppos_show(struct class_device *class_dev, char *buf)
+static ssize_t osst_first_data_ppos_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
- struct osst_tape * STp = (struct osst_tape *) class_get_devdata (class_dev);
+ struct osst_tape * STp = (struct osst_tape *) dev_get_drvdata (dev);
ssize_t l = 0;
if (STp && STp->header_ok && STp->linux_media)
return l;
}
-CLASS_DEVICE_ATTR(BOT_frame, S_IRUGO, osst_first_data_ppos_show, NULL);
+DEVICE_ATTR(BOT_frame, S_IRUGO, osst_first_data_ppos_show, NULL);
-static ssize_t osst_eod_frame_ppos_show(struct class_device *class_dev, char *buf)
+static ssize_t osst_eod_frame_ppos_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
- struct osst_tape * STp = (struct osst_tape *) class_get_devdata (class_dev);
+ struct osst_tape * STp = (struct osst_tape *) dev_get_drvdata (dev);
ssize_t l = 0;
if (STp && STp->header_ok && STp->linux_media)
return l;
}
-CLASS_DEVICE_ATTR(EOD_frame, S_IRUGO, osst_eod_frame_ppos_show, NULL);
+DEVICE_ATTR(EOD_frame, S_IRUGO, osst_eod_frame_ppos_show, NULL);
-static ssize_t osst_filemark_cnt_show(struct class_device *class_dev, char *buf)
+static ssize_t osst_filemark_cnt_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct osst_tape * STp = (struct osst_tape *) class_get_devdata (class_dev);
+ struct osst_tape * STp = (struct osst_tape *) dev_get_drvdata (dev);
ssize_t l = 0;
if (STp && STp->header_ok && STp->linux_media)
return l;
}
-CLASS_DEVICE_ATTR(file_count, S_IRUGO, osst_filemark_cnt_show, NULL);
+DEVICE_ATTR(file_count, S_IRUGO, osst_filemark_cnt_show, NULL);
static struct class *osst_sysfs_class;
static void osst_sysfs_destroy(dev_t dev)
{
- class_device_destroy(osst_sysfs_class, dev);
+ device_destroy(osst_sysfs_class, dev);
}
static int osst_sysfs_add(dev_t dev, struct device *device, struct osst_tape * STp, char * name)
{
- struct class_device *osst_class_member;
+ struct device *osst_member;
int err;
- osst_class_member = class_device_create(osst_sysfs_class, NULL, dev,
- device, "%s", name);
- if (IS_ERR(osst_class_member)) {
+ osst_member = device_create(osst_sysfs_class, device, dev, "%s", name);
+ if (IS_ERR(osst_member)) {
printk(KERN_WARNING "osst :W: Unable to add sysfs class member %s\n", name);
- return PTR_ERR(osst_class_member);
+ return PTR_ERR(osst_member);
}
- class_set_devdata(osst_class_member, STp);
- err = class_device_create_file(osst_class_member,
- &class_device_attr_ADR_rev);
+ dev_set_drvdata(osst_member, STp);
+ err = device_create_file(osst_member, &dev_attr_ADR_rev);
if (err)
goto err_out;
- err = class_device_create_file(osst_class_member,
- &class_device_attr_media_version);
+ err = device_create_file(osst_member, &dev_attr_media_version);
if (err)
goto err_out;
- err = class_device_create_file(osst_class_member,
- &class_device_attr_capacity);
+ err = device_create_file(osst_member, &dev_attr_capacity);
if (err)
goto err_out;
- err = class_device_create_file(osst_class_member,
- &class_device_attr_BOT_frame);
+ err = device_create_file(osst_member, &dev_attr_BOT_frame);
if (err)
goto err_out;
- err = class_device_create_file(osst_class_member,
- &class_device_attr_EOD_frame);
+ err = device_create_file(osst_member, &dev_attr_EOD_frame);
if (err)
goto err_out;
- err = class_device_create_file(osst_class_member,
- &class_device_attr_file_count);
+ err = device_create_file(osst_member, &dev_attr_file_count);
if (err)
goto err_out;
}
static ssize_t
-SYM53C500_show_pio(struct class_device *cdev, char *buf)
+SYM53C500_show_pio(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *SHp = class_to_shost(cdev);
+ struct Scsi_Host *SHp = class_to_shost(dev);
struct sym53c500_data *data =
(struct sym53c500_data *)SHp->hostdata;
}
static ssize_t
-SYM53C500_store_pio(struct class_device *cdev, const char *buf, size_t count)
+SYM53C500_store_pio(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
int pio;
- struct Scsi_Host *SHp = class_to_shost(cdev);
+ struct Scsi_Host *SHp = class_to_shost(dev);
struct sym53c500_data *data =
(struct sym53c500_data *)SHp->hostdata;
* SCSI HBA device attributes we want to
* make available via sysfs.
*/
-static struct class_device_attribute SYM53C500_pio_attr = {
+static struct device_attribute SYM53C500_pio_attr = {
.attr = {
.name = "fast_pio",
.mode = (S_IRUGO | S_IWUSR),
.store = SYM53C500_store_pio,
};
-static struct class_device_attribute *SYM53C500_shost_attrs[] = {
+static struct device_attribute *SYM53C500_shost_attrs[] = {
&SYM53C500_pio_attr,
NULL,
};
/* Scsi_Host attributes. */
static ssize_t
-qla2x00_drvr_version_show(struct class_device *cdev, char *buf)
+qla2x00_drvr_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%s\n", qla2x00_version_str);
}
static ssize_t
-qla2x00_fw_version_show(struct class_device *cdev, char *buf)
+qla2x00_fw_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
char fw_str[30];
return snprintf(buf, PAGE_SIZE, "%s\n",
}
static ssize_t
-qla2x00_serial_num_show(struct class_device *cdev, char *buf)
+qla2x00_serial_num_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
uint32_t sn;
if (IS_FWI2_CAPABLE(ha))
}
static ssize_t
-qla2x00_isp_name_show(struct class_device *cdev, char *buf)
+qla2x00_isp_name_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
return snprintf(buf, PAGE_SIZE, "ISP%04X\n", ha->pdev->device);
}
static ssize_t
-qla2x00_isp_id_show(struct class_device *cdev, char *buf)
+qla2x00_isp_id_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
return snprintf(buf, PAGE_SIZE, "%04x %04x %04x %04x\n",
ha->product_id[0], ha->product_id[1], ha->product_id[2],
ha->product_id[3]);
}
static ssize_t
-qla2x00_model_name_show(struct class_device *cdev, char *buf)
+qla2x00_model_name_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
return snprintf(buf, PAGE_SIZE, "%s\n", ha->model_number);
}
static ssize_t
-qla2x00_model_desc_show(struct class_device *cdev, char *buf)
+qla2x00_model_desc_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
return snprintf(buf, PAGE_SIZE, "%s\n",
ha->model_desc ? ha->model_desc: "");
}
static ssize_t
-qla2x00_pci_info_show(struct class_device *cdev, char *buf)
+qla2x00_pci_info_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
char pci_info[30];
return snprintf(buf, PAGE_SIZE, "%s\n",
}
static ssize_t
-qla2x00_state_show(struct class_device *cdev, char *buf)
+qla2x00_state_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
int len = 0;
if (atomic_read(&ha->loop_state) == LOOP_DOWN ||
}
static ssize_t
-qla2x00_zio_show(struct class_device *cdev, char *buf)
+qla2x00_zio_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
int len = 0;
switch (ha->zio_mode) {
}
static ssize_t
-qla2x00_zio_store(struct class_device *cdev, const char *buf, size_t count)
+qla2x00_zio_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
int val = 0;
uint16_t zio_mode;
}
static ssize_t
-qla2x00_zio_timer_show(struct class_device *cdev, char *buf)
+qla2x00_zio_timer_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
return snprintf(buf, PAGE_SIZE, "%d us\n", ha->zio_timer * 100);
}
static ssize_t
-qla2x00_zio_timer_store(struct class_device *cdev, const char *buf,
- size_t count)
+qla2x00_zio_timer_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
int val = 0;
uint16_t zio_timer;
}
static ssize_t
-qla2x00_beacon_show(struct class_device *cdev, char *buf)
+qla2x00_beacon_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
int len = 0;
if (ha->beacon_blink_led)
}
static ssize_t
-qla2x00_beacon_store(struct class_device *cdev, const char *buf,
- size_t count)
+qla2x00_beacon_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
int val = 0;
int rval;
}
static ssize_t
-qla2x00_optrom_bios_version_show(struct class_device *cdev, char *buf)
+qla2x00_optrom_bios_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
return snprintf(buf, PAGE_SIZE, "%d.%02d\n", ha->bios_revision[1],
ha->bios_revision[0]);
}
static ssize_t
-qla2x00_optrom_efi_version_show(struct class_device *cdev, char *buf)
+qla2x00_optrom_efi_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
return snprintf(buf, PAGE_SIZE, "%d.%02d\n", ha->efi_revision[1],
ha->efi_revision[0]);
}
static ssize_t
-qla2x00_optrom_fcode_version_show(struct class_device *cdev, char *buf)
+qla2x00_optrom_fcode_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
return snprintf(buf, PAGE_SIZE, "%d.%02d\n", ha->fcode_revision[1],
ha->fcode_revision[0]);
}
static ssize_t
-qla2x00_optrom_fw_version_show(struct class_device *cdev, char *buf)
+qla2x00_optrom_fw_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- scsi_qla_host_t *ha = shost_priv(class_to_shost(cdev));
+ scsi_qla_host_t *ha = shost_priv(class_to_shost(dev));
return snprintf(buf, PAGE_SIZE, "%d.%02d.%02d %d\n",
ha->fw_revision[0], ha->fw_revision[1], ha->fw_revision[2],
ha->fw_revision[3]);
}
-static CLASS_DEVICE_ATTR(driver_version, S_IRUGO, qla2x00_drvr_version_show,
- NULL);
-static CLASS_DEVICE_ATTR(fw_version, S_IRUGO, qla2x00_fw_version_show, NULL);
-static CLASS_DEVICE_ATTR(serial_num, S_IRUGO, qla2x00_serial_num_show, NULL);
-static CLASS_DEVICE_ATTR(isp_name, S_IRUGO, qla2x00_isp_name_show, NULL);
-static CLASS_DEVICE_ATTR(isp_id, S_IRUGO, qla2x00_isp_id_show, NULL);
-static CLASS_DEVICE_ATTR(model_name, S_IRUGO, qla2x00_model_name_show, NULL);
-static CLASS_DEVICE_ATTR(model_desc, S_IRUGO, qla2x00_model_desc_show, NULL);
-static CLASS_DEVICE_ATTR(pci_info, S_IRUGO, qla2x00_pci_info_show, NULL);
-static CLASS_DEVICE_ATTR(state, S_IRUGO, qla2x00_state_show, NULL);
-static CLASS_DEVICE_ATTR(zio, S_IRUGO | S_IWUSR, qla2x00_zio_show,
- qla2x00_zio_store);
-static CLASS_DEVICE_ATTR(zio_timer, S_IRUGO | S_IWUSR, qla2x00_zio_timer_show,
- qla2x00_zio_timer_store);
-static CLASS_DEVICE_ATTR(beacon, S_IRUGO | S_IWUSR, qla2x00_beacon_show,
- qla2x00_beacon_store);
-static CLASS_DEVICE_ATTR(optrom_bios_version, S_IRUGO,
- qla2x00_optrom_bios_version_show, NULL);
-static CLASS_DEVICE_ATTR(optrom_efi_version, S_IRUGO,
- qla2x00_optrom_efi_version_show, NULL);
-static CLASS_DEVICE_ATTR(optrom_fcode_version, S_IRUGO,
- qla2x00_optrom_fcode_version_show, NULL);
-static CLASS_DEVICE_ATTR(optrom_fw_version, S_IRUGO,
- qla2x00_optrom_fw_version_show, NULL);
-
-struct class_device_attribute *qla2x00_host_attrs[] = {
- &class_device_attr_driver_version,
- &class_device_attr_fw_version,
- &class_device_attr_serial_num,
- &class_device_attr_isp_name,
- &class_device_attr_isp_id,
- &class_device_attr_model_name,
- &class_device_attr_model_desc,
- &class_device_attr_pci_info,
- &class_device_attr_state,
- &class_device_attr_zio,
- &class_device_attr_zio_timer,
- &class_device_attr_beacon,
- &class_device_attr_optrom_bios_version,
- &class_device_attr_optrom_efi_version,
- &class_device_attr_optrom_fcode_version,
- &class_device_attr_optrom_fw_version,
+static DEVICE_ATTR(driver_version, S_IRUGO, qla2x00_drvr_version_show, NULL);
+static DEVICE_ATTR(fw_version, S_IRUGO, qla2x00_fw_version_show, NULL);
+static DEVICE_ATTR(serial_num, S_IRUGO, qla2x00_serial_num_show, NULL);
+static DEVICE_ATTR(isp_name, S_IRUGO, qla2x00_isp_name_show, NULL);
+static DEVICE_ATTR(isp_id, S_IRUGO, qla2x00_isp_id_show, NULL);
+static DEVICE_ATTR(model_name, S_IRUGO, qla2x00_model_name_show, NULL);
+static DEVICE_ATTR(model_desc, S_IRUGO, qla2x00_model_desc_show, NULL);
+static DEVICE_ATTR(pci_info, S_IRUGO, qla2x00_pci_info_show, NULL);
+static DEVICE_ATTR(state, S_IRUGO, qla2x00_state_show, NULL);
+static DEVICE_ATTR(zio, S_IRUGO | S_IWUSR, qla2x00_zio_show, qla2x00_zio_store);
+static DEVICE_ATTR(zio_timer, S_IRUGO | S_IWUSR, qla2x00_zio_timer_show,
+ qla2x00_zio_timer_store);
+static DEVICE_ATTR(beacon, S_IRUGO | S_IWUSR, qla2x00_beacon_show,
+ qla2x00_beacon_store);
+static DEVICE_ATTR(optrom_bios_version, S_IRUGO,
+ qla2x00_optrom_bios_version_show, NULL);
+static DEVICE_ATTR(optrom_efi_version, S_IRUGO,
+ qla2x00_optrom_efi_version_show, NULL);
+static DEVICE_ATTR(optrom_fcode_version, S_IRUGO,
+ qla2x00_optrom_fcode_version_show, NULL);
+static DEVICE_ATTR(optrom_fw_version, S_IRUGO, qla2x00_optrom_fw_version_show,
+ NULL);
+
+struct device_attribute *qla2x00_host_attrs[] = {
+ &dev_attr_driver_version,
+ &dev_attr_fw_version,
+ &dev_attr_serial_num,
+ &dev_attr_isp_name,
+ &dev_attr_isp_id,
+ &dev_attr_model_name,
+ &dev_attr_model_desc,
+ &dev_attr_pci_info,
+ &dev_attr_state,
+ &dev_attr_zio,
+ &dev_attr_zio_timer,
+ &dev_attr_beacon,
+ &dev_attr_optrom_bios_version,
+ &dev_attr_optrom_efi_version,
+ &dev_attr_optrom_fcode_version,
+ &dev_attr_optrom_fw_version,
NULL,
};
#include <linux/firmware.h>
#include <linux/aer.h>
#include <linux/mutex.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include <scsi/scsi.h>
#include <scsi/scsi_host.h>
/*
* Global Function Prototypes in qla_attr.c source file.
*/
-struct class_device_attribute;
-extern struct class_device_attribute *qla2x00_host_attrs[];
+struct device_attribute;
+extern struct device_attribute *qla2x00_host_attrs[];
struct fc_function_template;
extern struct fc_function_template qla2xxx_transport_functions;
extern struct fc_function_template qla2xxx_transport_vport_functions;
struct raid_template r;
struct raid_function_template *f;
/* The actual attributes */
- struct class_device_attribute private_attrs[RAID_NUM_ATTRS];
+ struct device_attribute private_attrs[RAID_NUM_ATTRS];
/* The array of null terminated pointers to attributes
* needed by scsi_sysfs.c */
- struct class_device_attribute *attrs[RAID_NUM_ATTRS + 1];
+ struct device_attribute *attrs[RAID_NUM_ATTRS + 1];
};
struct raid_component {
struct list_head node;
- struct class_device cdev;
+ struct device dev;
int num;
};
tc_to_raid_internal(tc); \
})
-#define class_device_to_raid_internal(cdev) ({ \
+#define device_to_raid_internal(dev) ({ \
struct attribute_container *ac = \
- attribute_container_classdev_to_container(cdev); \
+ attribute_container_classdev_to_container(dev); \
ac_to_raid_internal(ac); \
})
}
static int raid_setup(struct transport_container *tc, struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct raid_data *rd;
- BUG_ON(class_get_devdata(cdev));
+ BUG_ON(dev_get_drvdata(cdev));
rd = kzalloc(sizeof(*rd), GFP_KERNEL);
if (!rd)
return -ENOMEM;
INIT_LIST_HEAD(&rd->component_list);
- class_set_devdata(cdev, rd);
+ dev_set_drvdata(cdev, rd);
return 0;
}
static int raid_remove(struct transport_container *tc, struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
- struct raid_data *rd = class_get_devdata(cdev);
+ struct raid_data *rd = dev_get_drvdata(cdev);
struct raid_component *rc, *next;
dev_printk(KERN_ERR, dev, "RAID REMOVE\n");
- class_set_devdata(cdev, NULL);
+ dev_set_drvdata(cdev, NULL);
list_for_each_entry_safe(rc, next, &rd->component_list, node) {
list_del(&rc->node);
- dev_printk(KERN_ERR, rc->cdev.dev, "RAID COMPONENT REMOVE\n");
- class_device_unregister(&rc->cdev);
+ dev_printk(KERN_ERR, rc->dev.parent, "RAID COMPONENT REMOVE\n");
+ device_unregister(&rc->dev);
}
dev_printk(KERN_ERR, dev, "RAID REMOVE DONE\n");
kfree(rd);
}
#define raid_attr_show_internal(attr, fmt, var, code) \
-static ssize_t raid_show_##attr(struct class_device *cdev, char *buf) \
+static ssize_t raid_show_##attr(struct device *dev, \
+ struct device_attribute *attr, \
+ char *buf) \
{ \
- struct raid_data *rd = class_get_devdata(cdev); \
+ struct raid_data *rd = dev_get_drvdata(dev); \
code \
return snprintf(buf, 20, #fmt "\n", var); \
}
code \
name = raid_##states##_name(rd->attr); \
) \
-static CLASS_DEVICE_ATTR(attr, S_IRUGO, raid_show_##attr, NULL)
+static DEVICE_ATTR(attr, S_IRUGO, raid_show_##attr, NULL)
#define raid_attr_ro_internal(attr, code) \
raid_attr_show_internal(attr, %d, rd->attr, code) \
-static CLASS_DEVICE_ATTR(attr, S_IRUGO, raid_show_##attr, NULL)
+static DEVICE_ATTR(attr, S_IRUGO, raid_show_##attr, NULL)
#define ATTR_CODE(attr) \
- struct raid_internal *i = class_device_to_raid_internal(cdev); \
+ struct raid_internal *i = device_to_raid_internal(dev); \
if (i->f->get_##attr) \
- i->f->get_##attr(cdev->dev);
+ i->f->get_##attr(dev->parent);
#define raid_attr_ro(attr) raid_attr_ro_internal(attr, )
#define raid_attr_ro_fn(attr) raid_attr_ro_internal(attr, ATTR_CODE(attr))
raid_attr_ro_fn(resync);
raid_attr_ro_state_fn(state);
-static void raid_component_release(struct class_device *cdev)
+static void raid_component_release(struct device *dev)
{
- struct raid_component *rc = container_of(cdev, struct raid_component,
- cdev);
- dev_printk(KERN_ERR, rc->cdev.dev, "COMPONENT RELEASE\n");
- put_device(rc->cdev.dev);
+ struct raid_component *rc =
+ container_of(dev, struct raid_component, dev);
+ dev_printk(KERN_ERR, rc->dev.parent, "COMPONENT RELEASE\n");
+ put_device(rc->dev.parent);
kfree(rc);
}
int raid_component_add(struct raid_template *r,struct device *raid_dev,
struct device *component_dev)
{
- struct class_device *cdev =
+ struct device *cdev =
attribute_container_find_class_device(&r->raid_attrs.ac,
raid_dev);
struct raid_component *rc;
- struct raid_data *rd = class_get_devdata(cdev);
+ struct raid_data *rd = dev_get_drvdata(cdev);
int err;
rc = kzalloc(sizeof(*rc), GFP_KERNEL);
return -ENOMEM;
INIT_LIST_HEAD(&rc->node);
- class_device_initialize(&rc->cdev);
- rc->cdev.release = raid_component_release;
- rc->cdev.dev = get_device(component_dev);
+ device_initialize(&rc->dev);
+ rc->dev.release = raid_component_release;
+ rc->dev.parent = get_device(component_dev);
rc->num = rd->component_count++;
- snprintf(rc->cdev.class_id, sizeof(rc->cdev.class_id),
+ snprintf(rc->dev.bus_id, sizeof(rc->dev.bus_id),
"component-%d", rc->num);
list_add_tail(&rc->node, &rd->component_list);
- rc->cdev.parent = cdev;
- rc->cdev.class = &raid_class.class;
- err = class_device_add(&rc->cdev);
+ rc->dev.class = &raid_class.class;
+ err = device_add(&rc->dev);
if (err)
goto err_out;
attribute_container_register(&i->r.raid_attrs.ac);
- i->attrs[count++] = &class_device_attr_level;
- i->attrs[count++] = &class_device_attr_resync;
- i->attrs[count++] = &class_device_attr_state;
+ i->attrs[count++] = &dev_attr_level;
+ i->attrs[count++] = &dev_attr_resync;
+ i->attrs[count++] = &dev_attr_state;
i->attrs[count] = NULL;
BUG_ON(count > RAID_NUM_ATTRS);
"Notifying upper driver of completion "
"(result %x)\n", cmd->result));
- good_bytes = scsi_bufflen(cmd) + cmd->request->extra_len;
+ good_bytes = scsi_bufflen(cmd);
if (cmd->request->cmd_type != REQ_TYPE_BLOCK_PC) {
drv = scsi_cmd_to_driver(cmd);
if (drv->done)
struct sas_function_template *f;
struct sas_domain_function_template *dft;
- struct class_device_attribute private_host_attrs[SAS_HOST_ATTRS];
- struct class_device_attribute private_phy_attrs[SAS_PHY_ATTRS];
- struct class_device_attribute private_port_attrs[SAS_PORT_ATTRS];
- struct class_device_attribute private_rphy_attrs[SAS_RPORT_ATTRS];
- struct class_device_attribute private_end_dev_attrs[SAS_END_DEV_ATTRS];
- struct class_device_attribute private_expander_attrs[SAS_EXPANDER_ATTRS];
+ struct device_attribute private_host_attrs[SAS_HOST_ATTRS];
+ struct device_attribute private_phy_attrs[SAS_PHY_ATTRS];
+ struct device_attribute private_port_attrs[SAS_PORT_ATTRS];
+ struct device_attribute private_rphy_attrs[SAS_RPORT_ATTRS];
+ struct device_attribute private_end_dev_attrs[SAS_END_DEV_ATTRS];
+ struct device_attribute private_expander_attrs[SAS_EXPANDER_ATTRS];
struct transport_container phy_attr_cont;
struct transport_container port_attr_cont;
* The array of null terminated pointers to attributes
* needed by scsi_sysfs.c
*/
- struct class_device_attribute *host_attrs[SAS_HOST_ATTRS + 1];
- struct class_device_attribute *phy_attrs[SAS_PHY_ATTRS + 1];
- struct class_device_attribute *port_attrs[SAS_PORT_ATTRS + 1];
- struct class_device_attribute *rphy_attrs[SAS_RPORT_ATTRS + 1];
- struct class_device_attribute *end_dev_attrs[SAS_END_DEV_ATTRS + 1];
- struct class_device_attribute *expander_attrs[SAS_EXPANDER_ATTRS + 1];
+ struct device_attribute *host_attrs[SAS_HOST_ATTRS + 1];
+ struct device_attribute *phy_attrs[SAS_PHY_ATTRS + 1];
+ struct device_attribute *port_attrs[SAS_PORT_ATTRS + 1];
+ struct device_attribute *rphy_attrs[SAS_RPORT_ATTRS + 1];
+ struct device_attribute *end_dev_attrs[SAS_END_DEV_ATTRS + 1];
+ struct device_attribute *expander_attrs[SAS_EXPANDER_ATTRS + 1];
};
#define to_sas_internal(tmpl) container_of(tmpl, struct sas_internal, t)
*/
#define shost_show_function(name, field, format_string) \
static ssize_t \
-show_##name (struct class_device *class_dev, char *buf) \
+show_##name (struct device *dev, struct device_attribute *attr, \
+ char *buf) \
{ \
- struct Scsi_Host *shost = class_to_shost(class_dev); \
+ struct Scsi_Host *shost = class_to_shost(dev); \
return snprintf (buf, 20, format_string, shost->field); \
}
*/
#define shost_rd_attr2(name, field, format_string) \
shost_show_function(name, field, format_string) \
-static CLASS_DEVICE_ATTR(name, S_IRUGO, show_##name, NULL);
+static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL);
#define shost_rd_attr(field, format_string) \
shost_rd_attr2(field, field, format_string)
* Create the actual show/store functions and data structures.
*/
-static ssize_t store_scan(struct class_device *class_dev, const char *buf,
- size_t count)
+static ssize_t
+store_scan(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
int res;
res = scsi_scan(shost, buf);
res = count;
return res;
};
-static CLASS_DEVICE_ATTR(scan, S_IWUSR, NULL, store_scan);
+static DEVICE_ATTR(scan, S_IWUSR, NULL, store_scan);
static ssize_t
-store_shost_state(struct class_device *class_dev, const char *buf, size_t count)
+store_shost_state(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
int i;
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
enum scsi_host_state state = 0;
for (i = 0; i < ARRAY_SIZE(shost_states); i++) {
}
static ssize_t
-show_shost_state(struct class_device *class_dev, char *buf)
+show_shost_state(struct device *dev, struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
const char *name = scsi_host_state_name(shost->shost_state);
if (!name)
return snprintf(buf, 20, "%s\n", name);
}
-static CLASS_DEVICE_ATTR(state, S_IRUGO | S_IWUSR, show_shost_state, store_shost_state);
+/* DEVICE_ATTR(state) clashes with dev_attr_state for sdev */
+struct device_attribute dev_attr_hstate =
+ __ATTR(state, S_IRUGO | S_IWUSR, show_shost_state, store_shost_state);
static ssize_t
show_shost_mode(unsigned int mode, char *buf)
return len;
}
-static ssize_t show_shost_supported_mode(struct class_device *class_dev, char *buf)
+static ssize_t
+show_shost_supported_mode(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
unsigned int supported_mode = shost->hostt->supported_mode;
if (supported_mode == MODE_UNKNOWN)
return show_shost_mode(supported_mode, buf);
}
-static CLASS_DEVICE_ATTR(supported_mode, S_IRUGO | S_IWUSR, show_shost_supported_mode, NULL);
+static DEVICE_ATTR(supported_mode, S_IRUGO | S_IWUSR, show_shost_supported_mode, NULL);
-static ssize_t show_shost_active_mode(struct class_device *class_dev, char *buf)
+static ssize_t
+show_shost_active_mode(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = class_to_shost(class_dev);
+ struct Scsi_Host *shost = class_to_shost(dev);
if (shost->active_mode == MODE_UNKNOWN)
return snprintf(buf, 20, "unknown\n");
return show_shost_mode(shost->active_mode, buf);
}
-static CLASS_DEVICE_ATTR(active_mode, S_IRUGO | S_IWUSR, show_shost_active_mode, NULL);
+static DEVICE_ATTR(active_mode, S_IRUGO | S_IWUSR, show_shost_active_mode, NULL);
shost_rd_attr(unique_id, "%u\n");
shost_rd_attr(host_busy, "%hu\n");
shost_rd_attr(unchecked_isa_dma, "%d\n");
shost_rd_attr2(proc_name, hostt->proc_name, "%s\n");
-static struct class_device_attribute *scsi_sysfs_shost_attrs[] = {
- &class_device_attr_unique_id,
- &class_device_attr_host_busy,
- &class_device_attr_cmd_per_lun,
- &class_device_attr_can_queue,
- &class_device_attr_sg_tablesize,
- &class_device_attr_unchecked_isa_dma,
- &class_device_attr_proc_name,
- &class_device_attr_scan,
- &class_device_attr_state,
- &class_device_attr_supported_mode,
- &class_device_attr_active_mode,
+static struct device_attribute *scsi_sysfs_shost_attrs[] = {
+ &dev_attr_unique_id,
+ &dev_attr_host_busy,
+ &dev_attr_cmd_per_lun,
+ &dev_attr_can_queue,
+ &dev_attr_sg_tablesize,
+ &dev_attr_unchecked_isa_dma,
+ &dev_attr_proc_name,
+ &dev_attr_scan,
+ &dev_attr_hstate,
+ &dev_attr_supported_mode,
+ &dev_attr_active_mode,
NULL
};
-static void scsi_device_cls_release(struct class_device *class_dev)
+static void scsi_device_cls_release(struct device *class_dev)
{
struct scsi_device *sdev;
static struct class sdev_class = {
.name = "scsi_device",
- .release = scsi_device_cls_release,
+ .dev_release = scsi_device_cls_release,
};
/* all probing is done in the individual ->probe routines */
*/
#define sdev_show_function(field, format_string) \
static ssize_t \
-sdev_show_##field (struct device *dev, struct device_attribute *attr, char *buf) \
+sdev_show_##field (struct device *dev, struct device_attribute *attr, \
+ char *buf) \
{ \
struct scsi_device *sdev; \
sdev = to_scsi_device(dev); \
sdev_show_function(field, format_string) \
\
static ssize_t \
-sdev_store_##field (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
+sdev_store_##field (struct device *dev, struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
struct scsi_device *sdev; \
sdev = to_scsi_device(dev); \
sdev_show_function(field, "%d\n") \
\
static ssize_t \
-sdev_store_##field (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
+sdev_store_##field (struct device *dev, struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
int ret; \
struct scsi_device *sdev; \
}
static ssize_t
-sdev_store_timeout (struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+sdev_store_timeout (struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
struct scsi_device *sdev;
int timeout;
static DEVICE_ATTR(timeout, S_IRUGO | S_IWUSR, sdev_show_timeout, sdev_store_timeout);
static ssize_t
-store_rescan_field (struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+store_rescan_field (struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
scsi_rescan_device(dev);
return count;
scsi_remove_device(to_scsi_device(dev));
}
-static ssize_t sdev_store_delete(struct device *dev, struct device_attribute *attr, const char *buf,
- size_t count)
+static ssize_t
+sdev_store_delete(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
int rc;
static DEVICE_ATTR(delete, S_IWUSR, NULL, sdev_store_delete);
static ssize_t
-store_state_field(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+store_state_field(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
int i;
struct scsi_device *sdev = to_scsi_device(dev);
static DEVICE_ATTR(state, S_IRUGO | S_IWUSR, show_state_field, store_state_field);
static ssize_t
-show_queue_type_field(struct device *dev, struct device_attribute *attr, char *buf)
+show_queue_type_field(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
struct scsi_device *sdev = to_scsi_device(dev);
const char *name = "none";
static DEVICE_ATTR(queue_type, S_IRUGO, show_queue_type_field, NULL);
static ssize_t
-show_iostat_counterbits(struct device *dev, struct device_attribute *attr, char *buf)
+show_iostat_counterbits(struct device *dev, struct device_attribute *attr, char *buf)
{
return snprintf(buf, 20, "%d\n", (int)sizeof(atomic_t) * 8);
}
#define show_sdev_iostat(field) \
static ssize_t \
-show_iostat_##field(struct device *dev, struct device_attribute *attr, char *buf) \
+show_iostat_##field(struct device *dev, struct device_attribute *attr, \
+ char *buf) \
{ \
struct scsi_device *sdev = to_scsi_device(dev); \
unsigned long long count = atomic_read(&sdev->field); \
#define DECLARE_EVT_SHOW(name, Cap_name) \
static ssize_t \
sdev_show_evt_##name(struct device *dev, struct device_attribute *attr, \
- char *buf) \
+ char *buf) \
{ \
struct scsi_device *sdev = to_scsi_device(dev); \
int val = test_bit(SDEV_EVT_##Cap_name, sdev->supported_events);\
#define DECLARE_EVT_STORE(name, Cap_name) \
static ssize_t \
-sdev_store_evt_##name(struct device *dev, struct device_attribute *attr, \
+sdev_store_evt_##name(struct device *dev, struct device_attribute *attr,\
const char *buf, size_t count) \
{ \
struct scsi_device *sdev = to_scsi_device(dev); \
NULL
};
-static ssize_t sdev_store_queue_depth_rw(struct device *dev, struct device_attribute *attr, const char *buf,
- size_t count)
+static ssize_t
+sdev_store_queue_depth_rw(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
int depth, retval;
struct scsi_device *sdev = to_scsi_device(dev);
__ATTR(queue_depth, S_IRUGO | S_IWUSR, sdev_show_queue_depth,
sdev_store_queue_depth_rw);
-static ssize_t sdev_store_queue_type_rw(struct device *dev, struct device_attribute *attr, const char *buf,
- size_t count)
+static ssize_t
+sdev_store_queue_type_rw(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
struct scsi_device *sdev = to_scsi_device(dev);
struct scsi_host_template *sht = sdev->host->hostt;
printk(KERN_INFO "error 1\n");
return error;
}
- error = class_device_add(&sdev->sdev_classdev);
+ error = device_add(&sdev->sdev_dev);
if (error) {
printk(KERN_INFO "error 2\n");
goto clean_device;
}
- /* take a reference for the sdev_classdev; this is
+ /* take a reference for the sdev_dev; this is
* released by the sdev_class .release */
get_device(&sdev->sdev_gendev);
return;
bsg_unregister_queue(sdev->request_queue);
- class_device_unregister(&sdev->sdev_classdev);
+ device_unregister(&sdev->sdev_dev);
transport_remove_device(dev);
device_del(dev);
scsi_device_set_state(sdev, SDEV_DEL);
EXPORT_SYMBOL(scsi_register_interface);
-static struct class_device_attribute *class_attr_overridden(
- struct class_device_attribute **attrs,
- struct class_device_attribute *attr)
+static struct device_attribute *class_attr_overridden(
+ struct device_attribute **attrs,
+ struct device_attribute *attr)
{
int i;
return NULL;
}
-static int class_attr_add(struct class_device *classdev,
- struct class_device_attribute *attr)
+static int class_attr_add(struct device *classdev,
+ struct device_attribute *attr)
{
- struct class_device_attribute *base_attr;
+ struct device_attribute *base_attr;
/*
* Spare the caller from having to copy things it's not interested in.
attr->store = base_attr->store;
}
- return class_device_create_file(classdev, attr);
+ return device_create_file(classdev, attr);
}
/**
if (shost->hostt->shost_attrs) {
for (i = 0; shost->hostt->shost_attrs[i]; i++) {
- error = class_attr_add(&shost->shost_classdev,
+ error = class_attr_add(&shost->shost_dev,
shost->hostt->shost_attrs[i]);
if (error)
return error;
for (i = 0; scsi_sysfs_shost_attrs[i]; i++) {
if (!class_attr_overridden(shost->hostt->shost_attrs,
scsi_sysfs_shost_attrs[i])) {
- error = class_device_create_file(&shost->shost_classdev,
+ error = device_create_file(&shost->shost_dev,
scsi_sysfs_shost_attrs[i]);
if (error)
return error;
sdev->host->host_no, sdev->channel, sdev->id,
sdev->lun);
- class_device_initialize(&sdev->sdev_classdev);
- sdev->sdev_classdev.dev = &sdev->sdev_gendev;
- sdev->sdev_classdev.class = &sdev_class;
- snprintf(sdev->sdev_classdev.class_id, BUS_ID_SIZE,
+ device_initialize(&sdev->sdev_dev);
+ sdev->sdev_dev.parent = &sdev->sdev_gendev;
+ sdev->sdev_dev.class = &sdev_class;
+ snprintf(sdev->sdev_dev.bus_id, BUS_ID_SIZE,
"%d:%d:%d:%d", sdev->host->host_no,
sdev->channel, sdev->id, sdev->lun);
sdev->scsi_level = starget->scsi_level;
* Redefine so that we can have same named attributes in the
* sdev/starget/host objects.
*/
-#define FC_CLASS_DEVICE_ATTR(_prefix,_name,_mode,_show,_store) \
-struct class_device_attribute class_device_attr_##_prefix##_##_name = \
+#define FC_DEVICE_ATTR(_prefix,_name,_mode,_show,_store) \
+struct device_attribute device_attr_##_prefix##_##_name = \
__ATTR(_name,_mode,_show,_store)
#define fc_enum_name_search(title, table_type, table) \
* part of the midlayer. As the remote port is specific to the
* fc transport, we must provide the attribute container.
*/
- struct class_device_attribute private_starget_attrs[
+ struct device_attribute private_starget_attrs[
FC_STARGET_NUM_ATTRS];
- struct class_device_attribute *starget_attrs[FC_STARGET_NUM_ATTRS + 1];
+ struct device_attribute *starget_attrs[FC_STARGET_NUM_ATTRS + 1];
- struct class_device_attribute private_host_attrs[FC_HOST_NUM_ATTRS];
- struct class_device_attribute *host_attrs[FC_HOST_NUM_ATTRS + 1];
+ struct device_attribute private_host_attrs[FC_HOST_NUM_ATTRS];
+ struct device_attribute *host_attrs[FC_HOST_NUM_ATTRS + 1];
struct transport_container rport_attr_cont;
- struct class_device_attribute private_rport_attrs[FC_RPORT_NUM_ATTRS];
- struct class_device_attribute *rport_attrs[FC_RPORT_NUM_ATTRS + 1];
+ struct device_attribute private_rport_attrs[FC_RPORT_NUM_ATTRS];
+ struct device_attribute *rport_attrs[FC_RPORT_NUM_ATTRS + 1];
struct transport_container vport_attr_cont;
- struct class_device_attribute private_vport_attrs[FC_VPORT_NUM_ATTRS];
- struct class_device_attribute *vport_attrs[FC_VPORT_NUM_ATTRS + 1];
+ struct device_attribute private_vport_attrs[FC_VPORT_NUM_ATTRS];
+ struct device_attribute *vport_attrs[FC_VPORT_NUM_ATTRS + 1];
};
#define to_fc_internal(tmpl) container_of(tmpl, struct fc_internal, t)
static int fc_target_setup(struct transport_container *tc, struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct scsi_target *starget = to_scsi_target(dev);
struct fc_rport *rport = starget_to_rport(starget);
NULL);
static int fc_host_setup(struct transport_container *tc, struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct Scsi_Host *shost = dev_to_shost(dev);
struct fc_host_attrs *fc_host = shost_to_fc_host(shost);
#define fc_rport_show_function(field, format_string, sz, cast) \
static ssize_t \
-show_fc_rport_##field (struct class_device *cdev, char *buf) \
+show_fc_rport_##field (struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct fc_rport *rport = transport_class_to_rport(cdev); \
+ struct fc_rport *rport = transport_class_to_rport(dev); \
struct Scsi_Host *shost = rport_to_shost(rport); \
struct fc_internal *i = to_fc_internal(shost->transportt); \
if ((i->f->get_rport_##field) && \
#define fc_rport_store_function(field) \
static ssize_t \
-store_fc_rport_##field(struct class_device *cdev, const char *buf, \
- size_t count) \
+store_fc_rport_##field(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
int val; \
- struct fc_rport *rport = transport_class_to_rport(cdev); \
+ struct fc_rport *rport = transport_class_to_rport(dev); \
struct Scsi_Host *shost = rport_to_shost(rport); \
struct fc_internal *i = to_fc_internal(shost->transportt); \
char *cp; \
#define fc_rport_rd_attr(field, format_string, sz) \
fc_rport_show_function(field, format_string, sz, ) \
-static FC_CLASS_DEVICE_ATTR(rport, field, S_IRUGO, \
+static FC_DEVICE_ATTR(rport, field, S_IRUGO, \
show_fc_rport_##field, NULL)
#define fc_rport_rd_attr_cast(field, format_string, sz, cast) \
fc_rport_show_function(field, format_string, sz, (cast)) \
-static FC_CLASS_DEVICE_ATTR(rport, field, S_IRUGO, \
+static FC_DEVICE_ATTR(rport, field, S_IRUGO, \
show_fc_rport_##field, NULL)
#define fc_rport_rw_attr(field, format_string, sz) \
fc_rport_show_function(field, format_string, sz, ) \
fc_rport_store_function(field) \
-static FC_CLASS_DEVICE_ATTR(rport, field, S_IRUGO | S_IWUSR, \
+static FC_DEVICE_ATTR(rport, field, S_IRUGO | S_IWUSR, \
show_fc_rport_##field, \
store_fc_rport_##field)
#define fc_private_rport_show_function(field, format_string, sz, cast) \
static ssize_t \
-show_fc_rport_##field (struct class_device *cdev, char *buf) \
+show_fc_rport_##field (struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct fc_rport *rport = transport_class_to_rport(cdev); \
+ struct fc_rport *rport = transport_class_to_rport(dev); \
return snprintf(buf, sz, format_string, cast rport->field); \
}
#define fc_private_rport_rd_attr(field, format_string, sz) \
fc_private_rport_show_function(field, format_string, sz, ) \
-static FC_CLASS_DEVICE_ATTR(rport, field, S_IRUGO, \
+static FC_DEVICE_ATTR(rport, field, S_IRUGO, \
show_fc_rport_##field, NULL)
#define fc_private_rport_rd_attr_cast(field, format_string, sz, cast) \
fc_private_rport_show_function(field, format_string, sz, (cast)) \
-static FC_CLASS_DEVICE_ATTR(rport, field, S_IRUGO, \
+static FC_DEVICE_ATTR(rport, field, S_IRUGO, \
show_fc_rport_##field, NULL)
#define fc_private_rport_rd_enum_attr(title, maxlen) \
static ssize_t \
-show_fc_rport_##title (struct class_device *cdev, char *buf) \
+show_fc_rport_##title (struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct fc_rport *rport = transport_class_to_rport(cdev); \
+ struct fc_rport *rport = transport_class_to_rport(dev); \
const char *name; \
name = get_fc_##title##_name(rport->title); \
if (!name) \
return -EINVAL; \
return snprintf(buf, maxlen, "%s\n", name); \
} \
-static FC_CLASS_DEVICE_ATTR(rport, title, S_IRUGO, \
+static FC_DEVICE_ATTR(rport, title, S_IRUGO, \
show_fc_rport_##title, NULL)
#define SETUP_RPORT_ATTRIBUTE_RD(field) \
- i->private_rport_attrs[count] = class_device_attr_rport_##field; \
+ i->private_rport_attrs[count] = device_attr_rport_##field; \
i->private_rport_attrs[count].attr.mode = S_IRUGO; \
i->private_rport_attrs[count].store = NULL; \
i->rport_attrs[count] = &i->private_rport_attrs[count]; \
count++
#define SETUP_PRIVATE_RPORT_ATTRIBUTE_RD(field) \
- i->private_rport_attrs[count] = class_device_attr_rport_##field; \
+ i->private_rport_attrs[count] = device_attr_rport_##field; \
i->private_rport_attrs[count].attr.mode = S_IRUGO; \
i->private_rport_attrs[count].store = NULL; \
i->rport_attrs[count] = &i->private_rport_attrs[count]; \
count++
#define SETUP_RPORT_ATTRIBUTE_RW(field) \
- i->private_rport_attrs[count] = class_device_attr_rport_##field; \
+ i->private_rport_attrs[count] = device_attr_rport_##field; \
if (!i->f->set_rport_##field) { \
i->private_rport_attrs[count].attr.mode = S_IRUGO; \
i->private_rport_attrs[count].store = NULL; \
#define SETUP_PRIVATE_RPORT_ATTRIBUTE_RW(field) \
{ \
- i->private_rport_attrs[count] = class_device_attr_rport_##field; \
+ i->private_rport_attrs[count] = device_attr_rport_##field; \
i->rport_attrs[count] = &i->private_rport_attrs[count]; \
count++; \
}
fc_private_rport_rd_attr(maxframe_size, "%u bytes\n", 20);
static ssize_t
-show_fc_rport_supported_classes (struct class_device *cdev, char *buf)
+show_fc_rport_supported_classes (struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct fc_rport *rport = transport_class_to_rport(cdev);
+ struct fc_rport *rport = transport_class_to_rport(dev);
if (rport->supported_classes == FC_COS_UNSPECIFIED)
return snprintf(buf, 20, "unspecified\n");
return get_fc_cos_names(rport->supported_classes, buf);
}
-static FC_CLASS_DEVICE_ATTR(rport, supported_classes, S_IRUGO,
+static FC_DEVICE_ATTR(rport, supported_classes, S_IRUGO,
show_fc_rport_supported_classes, NULL);
/* Dynamic Remote Port Attributes */
*/
fc_rport_show_function(dev_loss_tmo, "%d\n", 20, )
static ssize_t
-store_fc_rport_dev_loss_tmo(struct class_device *cdev, const char *buf,
- size_t count)
+store_fc_rport_dev_loss_tmo(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
int val;
- struct fc_rport *rport = transport_class_to_rport(cdev);
+ struct fc_rport *rport = transport_class_to_rport(dev);
struct Scsi_Host *shost = rport_to_shost(rport);
struct fc_internal *i = to_fc_internal(shost->transportt);
char *cp;
i->f->set_rport_dev_loss_tmo(rport, val);
return count;
}
-static FC_CLASS_DEVICE_ATTR(rport, dev_loss_tmo, S_IRUGO | S_IWUSR,
+static FC_DEVICE_ATTR(rport, dev_loss_tmo, S_IRUGO | S_IWUSR,
show_fc_rport_dev_loss_tmo, store_fc_rport_dev_loss_tmo);
fc_private_rport_rd_attr(port_id, "0x%06x\n", 20);
static ssize_t
-show_fc_rport_roles (struct class_device *cdev, char *buf)
+show_fc_rport_roles (struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct fc_rport *rport = transport_class_to_rport(cdev);
+ struct fc_rport *rport = transport_class_to_rport(dev);
/* identify any roles that are port_id specific */
if ((rport->port_id != -1) &&
return get_fc_port_roles_names(rport->roles, buf);
}
}
-static FC_CLASS_DEVICE_ATTR(rport, roles, S_IRUGO,
+static FC_DEVICE_ATTR(rport, roles, S_IRUGO,
show_fc_rport_roles, NULL);
fc_private_rport_rd_enum_attr(port_state, FC_PORTSTATE_MAX_NAMELEN);
* fast_io_fail_tmo attribute
*/
static ssize_t
-show_fc_rport_fast_io_fail_tmo (struct class_device *cdev, char *buf)
+show_fc_rport_fast_io_fail_tmo (struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct fc_rport *rport = transport_class_to_rport(cdev);
+ struct fc_rport *rport = transport_class_to_rport(dev);
if (rport->fast_io_fail_tmo == -1)
return snprintf(buf, 5, "off\n");
}
static ssize_t
-store_fc_rport_fast_io_fail_tmo(struct class_device *cdev, const char *buf,
- size_t count)
+store_fc_rport_fast_io_fail_tmo(struct device *dev,
+ struct device_attribute *attr, const char *buf,
+ size_t count)
{
int val;
char *cp;
- struct fc_rport *rport = transport_class_to_rport(cdev);
+ struct fc_rport *rport = transport_class_to_rport(dev);
if ((rport->port_state == FC_PORTSTATE_BLOCKED) ||
(rport->port_state == FC_PORTSTATE_DELETED) ||
}
return count;
}
-static FC_CLASS_DEVICE_ATTR(rport, fast_io_fail_tmo, S_IRUGO | S_IWUSR,
+static FC_DEVICE_ATTR(rport, fast_io_fail_tmo, S_IRUGO | S_IWUSR,
show_fc_rport_fast_io_fail_tmo, store_fc_rport_fast_io_fail_tmo);
*/
#define fc_starget_show_function(field, format_string, sz, cast) \
static ssize_t \
-show_fc_starget_##field (struct class_device *cdev, char *buf) \
+show_fc_starget_##field (struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct scsi_target *starget = transport_class_to_starget(cdev); \
+ struct scsi_target *starget = transport_class_to_starget(dev); \
struct Scsi_Host *shost = dev_to_shost(starget->dev.parent); \
struct fc_internal *i = to_fc_internal(shost->transportt); \
struct fc_rport *rport = starget_to_rport(starget); \
#define fc_starget_rd_attr(field, format_string, sz) \
fc_starget_show_function(field, format_string, sz, ) \
-static FC_CLASS_DEVICE_ATTR(starget, field, S_IRUGO, \
+static FC_DEVICE_ATTR(starget, field, S_IRUGO, \
show_fc_starget_##field, NULL)
#define fc_starget_rd_attr_cast(field, format_string, sz, cast) \
fc_starget_show_function(field, format_string, sz, (cast)) \
-static FC_CLASS_DEVICE_ATTR(starget, field, S_IRUGO, \
+static FC_DEVICE_ATTR(starget, field, S_IRUGO, \
show_fc_starget_##field, NULL)
#define SETUP_STARGET_ATTRIBUTE_RD(field) \
- i->private_starget_attrs[count] = class_device_attr_starget_##field; \
+ i->private_starget_attrs[count] = device_attr_starget_##field; \
i->private_starget_attrs[count].attr.mode = S_IRUGO; \
i->private_starget_attrs[count].store = NULL; \
i->starget_attrs[count] = &i->private_starget_attrs[count]; \
count++
#define SETUP_STARGET_ATTRIBUTE_RW(field) \
- i->private_starget_attrs[count] = class_device_attr_starget_##field; \
+ i->private_starget_attrs[count] = device_attr_starget_##field; \
if (!i->f->set_starget_##field) { \
i->private_starget_attrs[count].attr.mode = S_IRUGO; \
i->private_starget_attrs[count].store = NULL; \
#define fc_vport_show_function(field, format_string, sz, cast) \
static ssize_t \
-show_fc_vport_##field (struct class_device *cdev, char *buf) \
+show_fc_vport_##field (struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct fc_vport *vport = transport_class_to_vport(cdev); \
+ struct fc_vport *vport = transport_class_to_vport(dev); \
struct Scsi_Host *shost = vport_to_shost(vport); \
struct fc_internal *i = to_fc_internal(shost->transportt); \
if ((i->f->get_vport_##field) && \
#define fc_vport_store_function(field) \
static ssize_t \
-store_fc_vport_##field(struct class_device *cdev, const char *buf, \
- size_t count) \
+store_fc_vport_##field(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
int val; \
- struct fc_vport *vport = transport_class_to_vport(cdev); \
+ struct fc_vport *vport = transport_class_to_vport(dev); \
struct Scsi_Host *shost = vport_to_shost(vport); \
struct fc_internal *i = to_fc_internal(shost->transportt); \
char *cp; \
#define fc_vport_store_str_function(field, slen) \
static ssize_t \
-store_fc_vport_##field(struct class_device *cdev, const char *buf, \
- size_t count) \
+store_fc_vport_##field(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
- struct fc_vport *vport = transport_class_to_vport(cdev); \
+ struct fc_vport *vport = transport_class_to_vport(dev); \
struct Scsi_Host *shost = vport_to_shost(vport); \
struct fc_internal *i = to_fc_internal(shost->transportt); \
unsigned int cnt=count; \
#define fc_vport_rd_attr(field, format_string, sz) \
fc_vport_show_function(field, format_string, sz, ) \
-static FC_CLASS_DEVICE_ATTR(vport, field, S_IRUGO, \
+static FC_DEVICE_ATTR(vport, field, S_IRUGO, \
show_fc_vport_##field, NULL)
#define fc_vport_rd_attr_cast(field, format_string, sz, cast) \
fc_vport_show_function(field, format_string, sz, (cast)) \
-static FC_CLASS_DEVICE_ATTR(vport, field, S_IRUGO, \
+static FC_DEVICE_ATTR(vport, field, S_IRUGO, \
show_fc_vport_##field, NULL)
#define fc_vport_rw_attr(field, format_string, sz) \
fc_vport_show_function(field, format_string, sz, ) \
fc_vport_store_function(field) \
-static FC_CLASS_DEVICE_ATTR(vport, field, S_IRUGO | S_IWUSR, \
+static FC_DEVICE_ATTR(vport, field, S_IRUGO | S_IWUSR, \
show_fc_vport_##field, \
store_fc_vport_##field)
#define fc_private_vport_show_function(field, format_string, sz, cast) \
static ssize_t \
-show_fc_vport_##field (struct class_device *cdev, char *buf) \
+show_fc_vport_##field (struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct fc_vport *vport = transport_class_to_vport(cdev); \
+ struct fc_vport *vport = transport_class_to_vport(dev); \
return snprintf(buf, sz, format_string, cast vport->field); \
}
#define fc_private_vport_store_u32_function(field) \
static ssize_t \
-store_fc_vport_##field(struct class_device *cdev, const char *buf, \
- size_t count) \
+store_fc_vport_##field(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
u32 val; \
- struct fc_vport *vport = transport_class_to_vport(cdev); \
+ struct fc_vport *vport = transport_class_to_vport(dev); \
char *cp; \
if (vport->flags & (FC_VPORT_DEL | FC_VPORT_CREATING)) \
return -EBUSY; \
#define fc_private_vport_rd_attr(field, format_string, sz) \
fc_private_vport_show_function(field, format_string, sz, ) \
-static FC_CLASS_DEVICE_ATTR(vport, field, S_IRUGO, \
+static FC_DEVICE_ATTR(vport, field, S_IRUGO, \
show_fc_vport_##field, NULL)
#define fc_private_vport_rd_attr_cast(field, format_string, sz, cast) \
fc_private_vport_show_function(field, format_string, sz, (cast)) \
-static FC_CLASS_DEVICE_ATTR(vport, field, S_IRUGO, \
+static FC_DEVICE_ATTR(vport, field, S_IRUGO, \
show_fc_vport_##field, NULL)
#define fc_private_vport_rw_u32_attr(field, format_string, sz) \
fc_private_vport_show_function(field, format_string, sz, ) \
fc_private_vport_store_u32_function(field) \
-static FC_CLASS_DEVICE_ATTR(vport, field, S_IRUGO | S_IWUSR, \
+static FC_DEVICE_ATTR(vport, field, S_IRUGO | S_IWUSR, \
show_fc_vport_##field, \
store_fc_vport_##field)
#define fc_private_vport_rd_enum_attr(title, maxlen) \
static ssize_t \
-show_fc_vport_##title (struct class_device *cdev, char *buf) \
+show_fc_vport_##title (struct device *dev, \
+ struct device_attribute *attr, \
+ char *buf) \
{ \
- struct fc_vport *vport = transport_class_to_vport(cdev); \
+ struct fc_vport *vport = transport_class_to_vport(dev); \
const char *name; \
name = get_fc_##title##_name(vport->title); \
if (!name) \
return -EINVAL; \
return snprintf(buf, maxlen, "%s\n", name); \
} \
-static FC_CLASS_DEVICE_ATTR(vport, title, S_IRUGO, \
+static FC_DEVICE_ATTR(vport, title, S_IRUGO, \
show_fc_vport_##title, NULL)
#define SETUP_VPORT_ATTRIBUTE_RD(field) \
- i->private_vport_attrs[count] = class_device_attr_vport_##field; \
+ i->private_vport_attrs[count] = device_attr_vport_##field; \
i->private_vport_attrs[count].attr.mode = S_IRUGO; \
i->private_vport_attrs[count].store = NULL; \
i->vport_attrs[count] = &i->private_vport_attrs[count]; \
/* NOTE: Above MACRO differs: checks function not show bit */
#define SETUP_PRIVATE_VPORT_ATTRIBUTE_RD(field) \
- i->private_vport_attrs[count] = class_device_attr_vport_##field; \
+ i->private_vport_attrs[count] = device_attr_vport_##field; \
i->private_vport_attrs[count].attr.mode = S_IRUGO; \
i->private_vport_attrs[count].store = NULL; \
i->vport_attrs[count] = &i->private_vport_attrs[count]; \
count++
#define SETUP_VPORT_ATTRIBUTE_WR(field) \
- i->private_vport_attrs[count] = class_device_attr_vport_##field; \
+ i->private_vport_attrs[count] = device_attr_vport_##field; \
i->vport_attrs[count] = &i->private_vport_attrs[count]; \
if (i->f->field) \
count++
/* NOTE: Above MACRO differs: checks function */
#define SETUP_VPORT_ATTRIBUTE_RW(field) \
- i->private_vport_attrs[count] = class_device_attr_vport_##field; \
+ i->private_vport_attrs[count] = device_attr_vport_##field; \
if (!i->f->set_vport_##field) { \
i->private_vport_attrs[count].attr.mode = S_IRUGO; \
i->private_vport_attrs[count].store = NULL; \
#define SETUP_PRIVATE_VPORT_ATTRIBUTE_RW(field) \
{ \
- i->private_vport_attrs[count] = class_device_attr_vport_##field; \
+ i->private_vport_attrs[count] = device_attr_vport_##field; \
i->vport_attrs[count] = &i->private_vport_attrs[count]; \
count++; \
}
fc_private_vport_rd_attr_cast(port_name, "0x%llx\n", 20, unsigned long long);
static ssize_t
-show_fc_vport_roles (struct class_device *cdev, char *buf)
+show_fc_vport_roles (struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct fc_vport *vport = transport_class_to_vport(cdev);
+ struct fc_vport *vport = transport_class_to_vport(dev);
if (vport->roles == FC_PORT_ROLE_UNKNOWN)
return snprintf(buf, 20, "unknown\n");
return get_fc_port_roles_names(vport->roles, buf);
}
-static FC_CLASS_DEVICE_ATTR(vport, roles, S_IRUGO, show_fc_vport_roles, NULL);
+static FC_DEVICE_ATTR(vport, roles, S_IRUGO, show_fc_vport_roles, NULL);
fc_private_vport_rd_enum_attr(vport_type, FC_PORTTYPE_MAX_NAMELEN);
fc_private_vport_show_function(symbolic_name, "%s\n",
FC_VPORT_SYMBOLIC_NAMELEN + 1, )
fc_vport_store_str_function(symbolic_name, FC_VPORT_SYMBOLIC_NAMELEN)
-static FC_CLASS_DEVICE_ATTR(vport, symbolic_name, S_IRUGO | S_IWUSR,
+static FC_DEVICE_ATTR(vport, symbolic_name, S_IRUGO | S_IWUSR,
show_fc_vport_symbolic_name, store_fc_vport_symbolic_name);
static ssize_t
-store_fc_vport_delete(struct class_device *cdev, const char *buf,
- size_t count)
+store_fc_vport_delete(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct fc_vport *vport = transport_class_to_vport(cdev);
+ struct fc_vport *vport = transport_class_to_vport(dev);
struct Scsi_Host *shost = vport_to_shost(vport);
fc_queue_work(shost, &vport->vport_delete_work);
return count;
}
-static FC_CLASS_DEVICE_ATTR(vport, vport_delete, S_IWUSR,
+static FC_DEVICE_ATTR(vport, vport_delete, S_IWUSR,
NULL, store_fc_vport_delete);
* Write "1" to disable, write "0" to enable
*/
static ssize_t
-store_fc_vport_disable(struct class_device *cdev, const char *buf,
+store_fc_vport_disable(struct device *dev, struct device_attribute *attr,
+ const char *buf,
size_t count)
{
- struct fc_vport *vport = transport_class_to_vport(cdev);
+ struct fc_vport *vport = transport_class_to_vport(dev);
struct Scsi_Host *shost = vport_to_shost(vport);
struct fc_internal *i = to_fc_internal(shost->transportt);
int stat;
stat = i->f->vport_disable(vport, ((*buf == '0') ? false : true));
return stat ? stat : count;
}
-static FC_CLASS_DEVICE_ATTR(vport, vport_disable, S_IWUSR,
+static FC_DEVICE_ATTR(vport, vport_disable, S_IWUSR,
NULL, store_fc_vport_disable);
#define fc_host_show_function(field, format_string, sz, cast) \
static ssize_t \
-show_fc_host_##field (struct class_device *cdev, char *buf) \
+show_fc_host_##field (struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct Scsi_Host *shost = transport_class_to_shost(cdev); \
+ struct Scsi_Host *shost = transport_class_to_shost(dev); \
struct fc_internal *i = to_fc_internal(shost->transportt); \
if (i->f->get_host_##field) \
i->f->get_host_##field(shost); \
#define fc_host_store_function(field) \
static ssize_t \
-store_fc_host_##field(struct class_device *cdev, const char *buf, \
- size_t count) \
+store_fc_host_##field(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
int val; \
- struct Scsi_Host *shost = transport_class_to_shost(cdev); \
+ struct Scsi_Host *shost = transport_class_to_shost(dev); \
struct fc_internal *i = to_fc_internal(shost->transportt); \
char *cp; \
\
#define fc_host_store_str_function(field, slen) \
static ssize_t \
-store_fc_host_##field(struct class_device *cdev, const char *buf, \
- size_t count) \
+store_fc_host_##field(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
- struct Scsi_Host *shost = transport_class_to_shost(cdev); \
+ struct Scsi_Host *shost = transport_class_to_shost(dev); \
struct fc_internal *i = to_fc_internal(shost->transportt); \
unsigned int cnt=count; \
\
#define fc_host_rd_attr(field, format_string, sz) \
fc_host_show_function(field, format_string, sz, ) \
-static FC_CLASS_DEVICE_ATTR(host, field, S_IRUGO, \
+static FC_DEVICE_ATTR(host, field, S_IRUGO, \
show_fc_host_##field, NULL)
#define fc_host_rd_attr_cast(field, format_string, sz, cast) \
fc_host_show_function(field, format_string, sz, (cast)) \
-static FC_CLASS_DEVICE_ATTR(host, field, S_IRUGO, \
+static FC_DEVICE_ATTR(host, field, S_IRUGO, \
show_fc_host_##field, NULL)
#define fc_host_rw_attr(field, format_string, sz) \
fc_host_show_function(field, format_string, sz, ) \
fc_host_store_function(field) \
-static FC_CLASS_DEVICE_ATTR(host, field, S_IRUGO | S_IWUSR, \
+static FC_DEVICE_ATTR(host, field, S_IRUGO | S_IWUSR, \
show_fc_host_##field, \
store_fc_host_##field)
#define fc_host_rd_enum_attr(title, maxlen) \
static ssize_t \
-show_fc_host_##title (struct class_device *cdev, char *buf) \
+show_fc_host_##title (struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct Scsi_Host *shost = transport_class_to_shost(cdev); \
+ struct Scsi_Host *shost = transport_class_to_shost(dev); \
struct fc_internal *i = to_fc_internal(shost->transportt); \
const char *name; \
if (i->f->get_host_##title) \
return -EINVAL; \
return snprintf(buf, maxlen, "%s\n", name); \
} \
-static FC_CLASS_DEVICE_ATTR(host, title, S_IRUGO, show_fc_host_##title, NULL)
+static FC_DEVICE_ATTR(host, title, S_IRUGO, show_fc_host_##title, NULL)
#define SETUP_HOST_ATTRIBUTE_RD(field) \
- i->private_host_attrs[count] = class_device_attr_host_##field; \
+ i->private_host_attrs[count] = device_attr_host_##field; \
i->private_host_attrs[count].attr.mode = S_IRUGO; \
i->private_host_attrs[count].store = NULL; \
i->host_attrs[count] = &i->private_host_attrs[count]; \
count++
#define SETUP_HOST_ATTRIBUTE_RD_NS(field) \
- i->private_host_attrs[count] = class_device_attr_host_##field; \
+ i->private_host_attrs[count] = device_attr_host_##field; \
i->private_host_attrs[count].attr.mode = S_IRUGO; \
i->private_host_attrs[count].store = NULL; \
i->host_attrs[count] = &i->private_host_attrs[count]; \
count++
#define SETUP_HOST_ATTRIBUTE_RW(field) \
- i->private_host_attrs[count] = class_device_attr_host_##field; \
+ i->private_host_attrs[count] = device_attr_host_##field; \
if (!i->f->set_host_##field) { \
i->private_host_attrs[count].attr.mode = S_IRUGO; \
i->private_host_attrs[count].store = NULL; \
#define fc_private_host_show_function(field, format_string, sz, cast) \
static ssize_t \
-show_fc_host_##field (struct class_device *cdev, char *buf) \
+show_fc_host_##field (struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct Scsi_Host *shost = transport_class_to_shost(cdev); \
+ struct Scsi_Host *shost = transport_class_to_shost(dev); \
return snprintf(buf, sz, format_string, cast fc_host_##field(shost)); \
}
#define fc_private_host_rd_attr(field, format_string, sz) \
fc_private_host_show_function(field, format_string, sz, ) \
-static FC_CLASS_DEVICE_ATTR(host, field, S_IRUGO, \
+static FC_DEVICE_ATTR(host, field, S_IRUGO, \
show_fc_host_##field, NULL)
#define fc_private_host_rd_attr_cast(field, format_string, sz, cast) \
fc_private_host_show_function(field, format_string, sz, (cast)) \
-static FC_CLASS_DEVICE_ATTR(host, field, S_IRUGO, \
+static FC_DEVICE_ATTR(host, field, S_IRUGO, \
show_fc_host_##field, NULL)
#define SETUP_PRIVATE_HOST_ATTRIBUTE_RD(field) \
- i->private_host_attrs[count] = class_device_attr_host_##field; \
+ i->private_host_attrs[count] = device_attr_host_##field; \
i->private_host_attrs[count].attr.mode = S_IRUGO; \
i->private_host_attrs[count].store = NULL; \
i->host_attrs[count] = &i->private_host_attrs[count]; \
#define SETUP_PRIVATE_HOST_ATTRIBUTE_RW(field) \
{ \
- i->private_host_attrs[count] = class_device_attr_host_##field; \
+ i->private_host_attrs[count] = device_attr_host_##field; \
i->host_attrs[count] = &i->private_host_attrs[count]; \
count++; \
}
/* Fixed Host Attributes */
static ssize_t
-show_fc_host_supported_classes (struct class_device *cdev, char *buf)
+show_fc_host_supported_classes (struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
if (fc_host_supported_classes(shost) == FC_COS_UNSPECIFIED)
return snprintf(buf, 20, "unspecified\n");
return get_fc_cos_names(fc_host_supported_classes(shost), buf);
}
-static FC_CLASS_DEVICE_ATTR(host, supported_classes, S_IRUGO,
+static FC_DEVICE_ATTR(host, supported_classes, S_IRUGO,
show_fc_host_supported_classes, NULL);
static ssize_t
-show_fc_host_supported_fc4s (struct class_device *cdev, char *buf)
+show_fc_host_supported_fc4s (struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
return (ssize_t)show_fc_fc4s(buf, fc_host_supported_fc4s(shost));
}
-static FC_CLASS_DEVICE_ATTR(host, supported_fc4s, S_IRUGO,
+static FC_DEVICE_ATTR(host, supported_fc4s, S_IRUGO,
show_fc_host_supported_fc4s, NULL);
static ssize_t
-show_fc_host_supported_speeds (struct class_device *cdev, char *buf)
+show_fc_host_supported_speeds (struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
if (fc_host_supported_speeds(shost) == FC_PORTSPEED_UNKNOWN)
return snprintf(buf, 20, "unknown\n");
return get_fc_port_speed_names(fc_host_supported_speeds(shost), buf);
}
-static FC_CLASS_DEVICE_ATTR(host, supported_speeds, S_IRUGO,
+static FC_DEVICE_ATTR(host, supported_speeds, S_IRUGO,
show_fc_host_supported_speeds, NULL);
/* Dynamic Host Attributes */
static ssize_t
-show_fc_host_active_fc4s (struct class_device *cdev, char *buf)
+show_fc_host_active_fc4s (struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
struct fc_internal *i = to_fc_internal(shost->transportt);
if (i->f->get_host_active_fc4s)
return (ssize_t)show_fc_fc4s(buf, fc_host_active_fc4s(shost));
}
-static FC_CLASS_DEVICE_ATTR(host, active_fc4s, S_IRUGO,
+static FC_DEVICE_ATTR(host, active_fc4s, S_IRUGO,
show_fc_host_active_fc4s, NULL);
static ssize_t
-show_fc_host_speed (struct class_device *cdev, char *buf)
+show_fc_host_speed (struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
struct fc_internal *i = to_fc_internal(shost->transportt);
if (i->f->get_host_speed)
return get_fc_port_speed_names(fc_host_speed(shost), buf);
}
-static FC_CLASS_DEVICE_ATTR(host, speed, S_IRUGO,
+static FC_DEVICE_ATTR(host, speed, S_IRUGO,
show_fc_host_speed, NULL);
fc_private_host_show_function(system_hostname, "%s\n",
FC_SYMBOLIC_NAME_SIZE + 1, )
fc_host_store_str_function(system_hostname, FC_SYMBOLIC_NAME_SIZE)
-static FC_CLASS_DEVICE_ATTR(host, system_hostname, S_IRUGO | S_IWUSR,
+static FC_DEVICE_ATTR(host, system_hostname, S_IRUGO | S_IWUSR,
show_fc_host_system_hostname, store_fc_host_system_hostname);
/* Private Host Attributes */
static ssize_t
-show_fc_private_host_tgtid_bind_type(struct class_device *cdev, char *buf)
+show_fc_private_host_tgtid_bind_type(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
const char *name;
name = get_fc_tgtid_bind_type_name(fc_host_tgtid_bind_type(shost));
pos = list_entry((head)->next, typeof(*pos), member)
static ssize_t
-store_fc_private_host_tgtid_bind_type(struct class_device *cdev,
- const char *buf, size_t count)
+store_fc_private_host_tgtid_bind_type(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
struct fc_rport *rport;
enum fc_tgtid_binding_type val;
unsigned long flags;
return count;
}
-static FC_CLASS_DEVICE_ATTR(host, tgtid_bind_type, S_IRUGO | S_IWUSR,
+static FC_DEVICE_ATTR(host, tgtid_bind_type, S_IRUGO | S_IWUSR,
show_fc_private_host_tgtid_bind_type,
store_fc_private_host_tgtid_bind_type);
static ssize_t
-store_fc_private_host_issue_lip(struct class_device *cdev,
- const char *buf, size_t count)
+store_fc_private_host_issue_lip(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
struct fc_internal *i = to_fc_internal(shost->transportt);
int ret;
return -ENOENT;
}
-static FC_CLASS_DEVICE_ATTR(host, issue_lip, S_IWUSR, NULL,
+static FC_DEVICE_ATTR(host, issue_lip, S_IWUSR, NULL,
store_fc_private_host_issue_lip);
fc_private_host_rd_attr(npiv_vports_inuse, "%u\n", 20);
/* Show a given an attribute in the statistics group */
static ssize_t
-fc_stat_show(const struct class_device *cdev, char *buf, unsigned long offset)
+fc_stat_show(const struct device *dev, char *buf, unsigned long offset)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
struct fc_internal *i = to_fc_internal(shost->transportt);
struct fc_host_statistics *stats;
ssize_t ret = -ENOENT;
/* generate a read-only statistics attribute */
#define fc_host_statistic(name) \
-static ssize_t show_fcstat_##name(struct class_device *cd, char *buf) \
+static ssize_t show_fcstat_##name(struct device *cd, \
+ struct device_attribute *attr, \
+ char *buf) \
{ \
return fc_stat_show(cd, buf, \
offsetof(struct fc_host_statistics, name)); \
} \
-static FC_CLASS_DEVICE_ATTR(host, name, S_IRUGO, show_fcstat_##name, NULL)
+static FC_DEVICE_ATTR(host, name, S_IRUGO, show_fcstat_##name, NULL)
fc_host_statistic(seconds_since_last_reset);
fc_host_statistic(tx_frames);
fc_host_statistic(fcp_output_megabytes);
static ssize_t
-fc_reset_statistics(struct class_device *cdev, const char *buf,
- size_t count)
+fc_reset_statistics(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
struct fc_internal *i = to_fc_internal(shost->transportt);
/* ignore any data value written to the attribute */
return -ENOENT;
}
-static FC_CLASS_DEVICE_ATTR(host, reset_statistics, S_IWUSR, NULL,
+static FC_DEVICE_ATTR(host, reset_statistics, S_IWUSR, NULL,
fc_reset_statistics);
static struct attribute *fc_statistics_attrs[] = {
- &class_device_attr_host_seconds_since_last_reset.attr,
- &class_device_attr_host_tx_frames.attr,
- &class_device_attr_host_tx_words.attr,
- &class_device_attr_host_rx_frames.attr,
- &class_device_attr_host_rx_words.attr,
- &class_device_attr_host_lip_count.attr,
- &class_device_attr_host_nos_count.attr,
- &class_device_attr_host_error_frames.attr,
- &class_device_attr_host_dumped_frames.attr,
- &class_device_attr_host_link_failure_count.attr,
- &class_device_attr_host_loss_of_sync_count.attr,
- &class_device_attr_host_loss_of_signal_count.attr,
- &class_device_attr_host_prim_seq_protocol_err_count.attr,
- &class_device_attr_host_invalid_tx_word_count.attr,
- &class_device_attr_host_invalid_crc_count.attr,
- &class_device_attr_host_fcp_input_requests.attr,
- &class_device_attr_host_fcp_output_requests.attr,
- &class_device_attr_host_fcp_control_requests.attr,
- &class_device_attr_host_fcp_input_megabytes.attr,
- &class_device_attr_host_fcp_output_megabytes.attr,
- &class_device_attr_host_reset_statistics.attr,
+ &device_attr_host_seconds_since_last_reset.attr,
+ &device_attr_host_tx_frames.attr,
+ &device_attr_host_tx_words.attr,
+ &device_attr_host_rx_frames.attr,
+ &device_attr_host_rx_words.attr,
+ &device_attr_host_lip_count.attr,
+ &device_attr_host_nos_count.attr,
+ &device_attr_host_error_frames.attr,
+ &device_attr_host_dumped_frames.attr,
+ &device_attr_host_link_failure_count.attr,
+ &device_attr_host_loss_of_sync_count.attr,
+ &device_attr_host_loss_of_signal_count.attr,
+ &device_attr_host_prim_seq_protocol_err_count.attr,
+ &device_attr_host_invalid_tx_word_count.attr,
+ &device_attr_host_invalid_crc_count.attr,
+ &device_attr_host_fcp_input_requests.attr,
+ &device_attr_host_fcp_output_requests.attr,
+ &device_attr_host_fcp_control_requests.attr,
+ &device_attr_host_fcp_input_megabytes.attr,
+ &device_attr_host_fcp_output_megabytes.attr,
+ &device_attr_host_reset_statistics.attr,
NULL
};
* as hex characters, and may *not* contain any prefixes (e.g. 0x, x, etc)
*/
static ssize_t
-store_fc_host_vport_create(struct class_device *cdev, const char *buf,
- size_t count)
+store_fc_host_vport_create(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
struct fc_vport_identifiers vid;
struct fc_vport *vport;
unsigned int cnt=count;
stat = fc_vport_create(shost, 0, &shost->shost_gendev, &vid, &vport);
return stat ? stat : count;
}
-static FC_CLASS_DEVICE_ATTR(host, vport_create, S_IWUSR, NULL,
+static FC_DEVICE_ATTR(host, vport_create, S_IWUSR, NULL,
store_fc_host_vport_create);
* any prefixes (e.g. 0x, x, etc)
*/
static ssize_t
-store_fc_host_vport_delete(struct class_device *cdev, const char *buf,
- size_t count)
+store_fc_host_vport_delete(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
struct fc_host_attrs *fc_host = shost_to_fc_host(shost);
struct fc_vport *vport;
u64 wwpn, wwnn;
stat = fc_vport_terminate(vport);
return stat ? stat : count;
}
-static FC_CLASS_DEVICE_ATTR(host, vport_delete, S_IWUSR, NULL,
+static FC_DEVICE_ATTR(host, vport_delete, S_IWUSR, NULL,
store_fc_host_vport_delete);
struct scsi_transport_template t;
struct iscsi_transport *iscsi_transport;
struct list_head list;
- struct class_device cdev;
+ struct device dev;
- struct class_device_attribute *host_attrs[ISCSI_HOST_ATTRS + 1];
+ struct device_attribute *host_attrs[ISCSI_HOST_ATTRS + 1];
struct transport_container conn_cont;
- struct class_device_attribute *conn_attrs[ISCSI_CONN_ATTRS + 1];
+ struct device_attribute *conn_attrs[ISCSI_CONN_ATTRS + 1];
struct transport_container session_cont;
- struct class_device_attribute *session_attrs[ISCSI_SESSION_ATTRS + 1];
+ struct device_attribute *session_attrs[ISCSI_SESSION_ATTRS + 1];
};
static atomic_t iscsi_session_nr; /* sysfs session id for next new session */
#define to_iscsi_internal(tmpl) \
container_of(tmpl, struct iscsi_internal, t)
-#define cdev_to_iscsi_internal(_cdev) \
- container_of(_cdev, struct iscsi_internal, cdev)
+#define dev_to_iscsi_internal(_dev) \
+ container_of(_dev, struct iscsi_internal, dev)
-static void iscsi_transport_release(struct class_device *cdev)
+static void iscsi_transport_release(struct device *dev)
{
- struct iscsi_internal *priv = cdev_to_iscsi_internal(cdev);
+ struct iscsi_internal *priv = dev_to_iscsi_internal(dev);
kfree(priv);
}
*/
static struct class iscsi_transport_class = {
.name = "iscsi_transport",
- .release = iscsi_transport_release,
+ .dev_release = iscsi_transport_release,
};
static ssize_t
-show_transport_handle(struct class_device *cdev, char *buf)
+show_transport_handle(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct iscsi_internal *priv = cdev_to_iscsi_internal(cdev);
+ struct iscsi_internal *priv = dev_to_iscsi_internal(dev);
return sprintf(buf, "%llu\n", (unsigned long long)iscsi_handle(priv->iscsi_transport));
}
-static CLASS_DEVICE_ATTR(handle, S_IRUGO, show_transport_handle, NULL);
+static DEVICE_ATTR(handle, S_IRUGO, show_transport_handle, NULL);
#define show_transport_attr(name, format) \
static ssize_t \
-show_transport_##name(struct class_device *cdev, char *buf) \
+show_transport_##name(struct device *dev, \
+ struct device_attribute *attr,char *buf) \
{ \
- struct iscsi_internal *priv = cdev_to_iscsi_internal(cdev); \
+ struct iscsi_internal *priv = dev_to_iscsi_internal(dev); \
return sprintf(buf, format"\n", priv->iscsi_transport->name); \
} \
-static CLASS_DEVICE_ATTR(name, S_IRUGO, show_transport_##name, NULL);
+static DEVICE_ATTR(name, S_IRUGO, show_transport_##name, NULL);
show_transport_attr(caps, "0x%x");
show_transport_attr(max_lun, "%d");
show_transport_attr(max_cmd_len, "%d");
static struct attribute *iscsi_transport_attrs[] = {
- &class_device_attr_handle.attr,
- &class_device_attr_caps.attr,
- &class_device_attr_max_lun.attr,
- &class_device_attr_max_conn.attr,
- &class_device_attr_max_cmd_len.attr,
+ &dev_attr_handle.attr,
+ &dev_attr_caps.attr,
+ &dev_attr_max_lun.attr,
+ &dev_attr_max_conn.attr,
+ &dev_attr_max_cmd_len.attr,
NULL,
};
static int iscsi_setup_host(struct transport_container *tc, struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct Scsi_Host *shost = dev_to_shost(dev);
struct iscsi_host *ihost = shost->shost_data;
}
static int iscsi_remove_host(struct transport_container *tc, struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct Scsi_Host *shost = dev_to_shost(dev);
struct iscsi_host *ihost = shost->shost_data;
mutex_unlock(&rx_queue_mutex);
}
-#define iscsi_cdev_to_conn(_cdev) \
- iscsi_dev_to_conn(_cdev->dev)
-
#define ISCSI_CLASS_ATTR(_prefix,_name,_mode,_show,_store) \
-struct class_device_attribute class_device_attr_##_prefix##_##_name = \
+struct device_attribute dev_attr_##_prefix##_##_name = \
__ATTR(_name,_mode,_show,_store)
/*
*/
#define iscsi_conn_attr_show(param) \
static ssize_t \
-show_conn_param_##param(struct class_device *cdev, char *buf) \
+show_conn_param_##param(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct iscsi_cls_conn *conn = iscsi_cdev_to_conn(cdev); \
+ struct iscsi_cls_conn *conn = iscsi_dev_to_conn(dev->parent); \
struct iscsi_transport *t = conn->transport; \
return t->get_conn_param(conn, param, buf); \
}
iscsi_conn_attr(ping_tmo, ISCSI_PARAM_PING_TMO);
iscsi_conn_attr(recv_tmo, ISCSI_PARAM_RECV_TMO);
-#define iscsi_cdev_to_session(_cdev) \
- iscsi_dev_to_session(_cdev->dev)
-
/*
* iSCSI session attrs
*/
#define iscsi_session_attr_show(param, perm) \
static ssize_t \
-show_session_param_##param(struct class_device *cdev, char *buf) \
+show_session_param_##param(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct iscsi_cls_session *session = iscsi_cdev_to_session(cdev); \
+ struct iscsi_cls_session *session = \
+ iscsi_dev_to_session(dev->parent); \
struct iscsi_transport *t = session->transport; \
\
if (perm && !capable(CAP_SYS_ADMIN)) \
iscsi_session_attr(lu_reset_tmo, ISCSI_PARAM_LU_RESET_TMO, 0);
static ssize_t
-show_priv_session_state(struct class_device *cdev, char *buf)
+show_priv_session_state(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct iscsi_cls_session *session = iscsi_cdev_to_session(cdev);
+ struct iscsi_cls_session *session = iscsi_dev_to_session(dev->parent);
return sprintf(buf, "%s\n", iscsi_session_state_name(session->state));
}
static ISCSI_CLASS_ATTR(priv_sess, state, S_IRUGO, show_priv_session_state,
#define iscsi_priv_session_attr_show(field, format) \
static ssize_t \
-show_priv_session_##field(struct class_device *cdev, char *buf) \
+show_priv_session_##field(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct iscsi_cls_session *session = iscsi_cdev_to_session(cdev);\
+ struct iscsi_cls_session *session = \
+ iscsi_dev_to_session(dev->parent); \
return sprintf(buf, format"\n", session->field); \
}
*/
#define iscsi_host_attr_show(param) \
static ssize_t \
-show_host_param_##param(struct class_device *cdev, char *buf) \
+show_host_param_##param(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct Scsi_Host *shost = transport_class_to_shost(cdev); \
+ struct Scsi_Host *shost = transport_class_to_shost(dev); \
struct iscsi_internal *priv = to_iscsi_internal(shost->transportt); \
return priv->iscsi_transport->get_host_param(shost, param, buf); \
}
#define SETUP_PRIV_SESSION_RD_ATTR(field) \
do { \
- priv->session_attrs[count] = &class_device_attr_priv_sess_##field; \
+ priv->session_attrs[count] = &dev_attr_priv_sess_##field; \
count++; \
} while (0)
#define SETUP_SESSION_RD_ATTR(field, param_flag) \
do { \
if (tt->param_mask & param_flag) { \
- priv->session_attrs[count] = &class_device_attr_sess_##field; \
+ priv->session_attrs[count] = &dev_attr_sess_##field; \
count++; \
} \
} while (0)
#define SETUP_CONN_RD_ATTR(field, param_flag) \
do { \
if (tt->param_mask & param_flag) { \
- priv->conn_attrs[count] = &class_device_attr_conn_##field; \
+ priv->conn_attrs[count] = &dev_attr_conn_##field; \
count++; \
} \
} while (0)
#define SETUP_HOST_RD_ATTR(field, param_flag) \
do { \
if (tt->host_param_mask & param_flag) { \
- priv->host_attrs[count] = &class_device_attr_host_##field; \
+ priv->host_attrs[count] = &dev_attr_host_##field; \
count++; \
} \
} while (0)
priv->iscsi_transport = tt;
priv->t.user_scan = iscsi_user_scan;
- priv->cdev.class = &iscsi_transport_class;
- snprintf(priv->cdev.class_id, BUS_ID_SIZE, "%s", tt->name);
- err = class_device_register(&priv->cdev);
+ priv->dev.class = &iscsi_transport_class;
+ snprintf(priv->dev.bus_id, BUS_ID_SIZE, "%s", tt->name);
+ err = device_register(&priv->dev);
if (err)
goto free_priv;
- err = sysfs_create_group(&priv->cdev.kobj, &iscsi_transport_group);
+ err = sysfs_create_group(&priv->dev.kobj, &iscsi_transport_group);
if (err)
- goto unregister_cdev;
+ goto unregister_dev;
/* host parameters */
priv->t.host_attrs.ac.attrs = &priv->host_attrs[0];
printk(KERN_NOTICE "iscsi: registered transport (%s)\n", tt->name);
return &priv->t;
-unregister_cdev:
- class_device_unregister(&priv->cdev);
+unregister_dev:
+ device_unregister(&priv->dev);
free_priv:
kfree(priv);
return NULL;
transport_container_unregister(&priv->session_cont);
transport_container_unregister(&priv->t.host_attrs);
- sysfs_remove_group(&priv->cdev.kobj, &iscsi_transport_group);
- class_device_unregister(&priv->cdev);
+ sysfs_remove_group(&priv->dev.kobj, &iscsi_transport_group);
+ device_unregister(&priv->dev);
mutex_unlock(&rx_queue_mutex);
return 0;
/*
* Hack to allow attributes of the same name in different objects.
*/
-#define SAS_CLASS_DEVICE_ATTR(_prefix,_name,_mode,_show,_store) \
- struct class_device_attribute class_device_attr_##_prefix##_##_name = \
+#define SAS_DEVICE_ATTR(_prefix,_name,_mode,_show,_store) \
+ struct device_attribute dev_attr_##_prefix##_##_name = \
__ATTR(_name,_mode,_show,_store)
*/
static int sas_host_setup(struct transport_container *tc, struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct Scsi_Host *shost = dev_to_shost(dev);
struct sas_host_attrs *sas_host = to_sas_host_attrs(shost);
}
static int sas_host_remove(struct transport_container *tc, struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct Scsi_Host *shost = dev_to_shost(dev);
#define sas_phy_show_simple(field, name, format_string, cast) \
static ssize_t \
-show_sas_phy_##name(struct class_device *cdev, char *buf) \
+show_sas_phy_##name(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct sas_phy *phy = transport_class_to_phy(cdev); \
+ struct sas_phy *phy = transport_class_to_phy(dev); \
\
return snprintf(buf, 20, format_string, cast phy->field); \
}
#define sas_phy_simple_attr(field, name, format_string, type) \
sas_phy_show_simple(field, name, format_string, (type)) \
-static CLASS_DEVICE_ATTR(name, S_IRUGO, show_sas_phy_##name, NULL)
+static DEVICE_ATTR(name, S_IRUGO, show_sas_phy_##name, NULL)
#define sas_phy_show_protocol(field, name) \
static ssize_t \
-show_sas_phy_##name(struct class_device *cdev, char *buf) \
+show_sas_phy_##name(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct sas_phy *phy = transport_class_to_phy(cdev); \
+ struct sas_phy *phy = transport_class_to_phy(dev); \
\
if (!phy->field) \
return snprintf(buf, 20, "none\n"); \
#define sas_phy_protocol_attr(field, name) \
sas_phy_show_protocol(field, name) \
-static CLASS_DEVICE_ATTR(name, S_IRUGO, show_sas_phy_##name, NULL)
+static DEVICE_ATTR(name, S_IRUGO, show_sas_phy_##name, NULL)
#define sas_phy_show_linkspeed(field) \
static ssize_t \
-show_sas_phy_##field(struct class_device *cdev, char *buf) \
+show_sas_phy_##field(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct sas_phy *phy = transport_class_to_phy(cdev); \
+ struct sas_phy *phy = transport_class_to_phy(dev); \
\
return get_sas_linkspeed_names(phy->field, buf); \
}
/* Fudge to tell if we're minimum or maximum */
#define sas_phy_store_linkspeed(field) \
static ssize_t \
-store_sas_phy_##field(struct class_device *cdev, const char *buf, \
- size_t count) \
+store_sas_phy_##field(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
- struct sas_phy *phy = transport_class_to_phy(cdev); \
+ struct sas_phy *phy = transport_class_to_phy(dev); \
struct Scsi_Host *shost = dev_to_shost(phy->dev.parent); \
struct sas_internal *i = to_sas_internal(shost->transportt); \
u32 value; \
#define sas_phy_linkspeed_rw_attr(field) \
sas_phy_show_linkspeed(field) \
sas_phy_store_linkspeed(field) \
-static CLASS_DEVICE_ATTR(field, S_IRUGO, show_sas_phy_##field, \
+static DEVICE_ATTR(field, S_IRUGO, show_sas_phy_##field, \
store_sas_phy_##field)
#define sas_phy_linkspeed_attr(field) \
sas_phy_show_linkspeed(field) \
-static CLASS_DEVICE_ATTR(field, S_IRUGO, show_sas_phy_##field, NULL)
+static DEVICE_ATTR(field, S_IRUGO, show_sas_phy_##field, NULL)
#define sas_phy_show_linkerror(field) \
static ssize_t \
-show_sas_phy_##field(struct class_device *cdev, char *buf) \
+show_sas_phy_##field(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct sas_phy *phy = transport_class_to_phy(cdev); \
+ struct sas_phy *phy = transport_class_to_phy(dev); \
struct Scsi_Host *shost = dev_to_shost(phy->dev.parent); \
struct sas_internal *i = to_sas_internal(shost->transportt); \
int error; \
#define sas_phy_linkerror_attr(field) \
sas_phy_show_linkerror(field) \
-static CLASS_DEVICE_ATTR(field, S_IRUGO, show_sas_phy_##field, NULL)
+static DEVICE_ATTR(field, S_IRUGO, show_sas_phy_##field, NULL)
static ssize_t
-show_sas_device_type(struct class_device *cdev, char *buf)
+show_sas_device_type(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct sas_phy *phy = transport_class_to_phy(cdev);
+ struct sas_phy *phy = transport_class_to_phy(dev);
if (!phy->identify.device_type)
return snprintf(buf, 20, "none\n");
return get_sas_device_type_names(phy->identify.device_type, buf);
}
-static CLASS_DEVICE_ATTR(device_type, S_IRUGO, show_sas_device_type, NULL);
+static DEVICE_ATTR(device_type, S_IRUGO, show_sas_device_type, NULL);
-static ssize_t do_sas_phy_enable(struct class_device *cdev,
+static ssize_t do_sas_phy_enable(struct device *dev,
size_t count, int enable)
{
- struct sas_phy *phy = transport_class_to_phy(cdev);
+ struct sas_phy *phy = transport_class_to_phy(dev);
struct Scsi_Host *shost = dev_to_shost(phy->dev.parent);
struct sas_internal *i = to_sas_internal(shost->transportt);
int error;
return count;
};
-static ssize_t store_sas_phy_enable(struct class_device *cdev,
- const char *buf, size_t count)
+static ssize_t
+store_sas_phy_enable(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
if (count < 1)
return -EINVAL;
switch (buf[0]) {
case '0':
- do_sas_phy_enable(cdev, count, 0);
+ do_sas_phy_enable(dev, count, 0);
break;
case '1':
- do_sas_phy_enable(cdev, count, 1);
+ do_sas_phy_enable(dev, count, 1);
break;
default:
return -EINVAL;
return count;
}
-static ssize_t show_sas_phy_enable(struct class_device *cdev, char *buf)
+static ssize_t
+show_sas_phy_enable(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct sas_phy *phy = transport_class_to_phy(cdev);
+ struct sas_phy *phy = transport_class_to_phy(dev);
return snprintf(buf, 20, "%d", phy->enabled);
}
-static CLASS_DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, show_sas_phy_enable,
+static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, show_sas_phy_enable,
store_sas_phy_enable);
-static ssize_t do_sas_phy_reset(struct class_device *cdev,
- size_t count, int hard_reset)
+static ssize_t
+do_sas_phy_reset(struct device *dev, size_t count, int hard_reset)
{
- struct sas_phy *phy = transport_class_to_phy(cdev);
+ struct sas_phy *phy = transport_class_to_phy(dev);
struct Scsi_Host *shost = dev_to_shost(phy->dev.parent);
struct sas_internal *i = to_sas_internal(shost->transportt);
int error;
return count;
};
-static ssize_t store_sas_link_reset(struct class_device *cdev,
- const char *buf, size_t count)
+static ssize_t
+store_sas_link_reset(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- return do_sas_phy_reset(cdev, count, 0);
+ return do_sas_phy_reset(dev, count, 0);
}
-static CLASS_DEVICE_ATTR(link_reset, S_IWUSR, NULL, store_sas_link_reset);
+static DEVICE_ATTR(link_reset, S_IWUSR, NULL, store_sas_link_reset);
-static ssize_t store_sas_hard_reset(struct class_device *cdev,
- const char *buf, size_t count)
+static ssize_t
+store_sas_hard_reset(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- return do_sas_phy_reset(cdev, count, 1);
+ return do_sas_phy_reset(dev, count, 1);
}
-static CLASS_DEVICE_ATTR(hard_reset, S_IWUSR, NULL, store_sas_hard_reset);
+static DEVICE_ATTR(hard_reset, S_IWUSR, NULL, store_sas_hard_reset);
sas_phy_protocol_attr(identify.initiator_port_protocols,
initiator_port_protocols);
*/
#define sas_port_show_simple(field, name, format_string, cast) \
static ssize_t \
-show_sas_port_##name(struct class_device *cdev, char *buf) \
+show_sas_port_##name(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct sas_port *port = transport_class_to_sas_port(cdev); \
+ struct sas_port *port = transport_class_to_sas_port(dev); \
\
return snprintf(buf, 20, format_string, cast port->field); \
}
#define sas_port_simple_attr(field, name, format_string, type) \
sas_port_show_simple(field, name, format_string, (type)) \
-static CLASS_DEVICE_ATTR(name, S_IRUGO, show_sas_port_##name, NULL)
+static DEVICE_ATTR(name, S_IRUGO, show_sas_port_##name, NULL)
sas_port_simple_attr(num_phys, num_phys, "%d\n", int);
#define sas_rphy_show_simple(field, name, format_string, cast) \
static ssize_t \
-show_sas_rphy_##name(struct class_device *cdev, char *buf) \
+show_sas_rphy_##name(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct sas_rphy *rphy = transport_class_to_rphy(cdev); \
+ struct sas_rphy *rphy = transport_class_to_rphy(dev); \
\
return snprintf(buf, 20, format_string, cast rphy->field); \
}
#define sas_rphy_simple_attr(field, name, format_string, type) \
sas_rphy_show_simple(field, name, format_string, (type)) \
-static SAS_CLASS_DEVICE_ATTR(rphy, name, S_IRUGO, \
+static SAS_DEVICE_ATTR(rphy, name, S_IRUGO, \
show_sas_rphy_##name, NULL)
#define sas_rphy_show_protocol(field, name) \
static ssize_t \
-show_sas_rphy_##name(struct class_device *cdev, char *buf) \
+show_sas_rphy_##name(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct sas_rphy *rphy = transport_class_to_rphy(cdev); \
+ struct sas_rphy *rphy = transport_class_to_rphy(dev); \
\
if (!rphy->field) \
return snprintf(buf, 20, "none\n"); \
#define sas_rphy_protocol_attr(field, name) \
sas_rphy_show_protocol(field, name) \
-static SAS_CLASS_DEVICE_ATTR(rphy, name, S_IRUGO, \
+static SAS_DEVICE_ATTR(rphy, name, S_IRUGO, \
show_sas_rphy_##name, NULL)
static ssize_t
-show_sas_rphy_device_type(struct class_device *cdev, char *buf)
+show_sas_rphy_device_type(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct sas_rphy *rphy = transport_class_to_rphy(cdev);
+ struct sas_rphy *rphy = transport_class_to_rphy(dev);
if (!rphy->identify.device_type)
return snprintf(buf, 20, "none\n");
rphy->identify.device_type, buf);
}
-static SAS_CLASS_DEVICE_ATTR(rphy, device_type, S_IRUGO,
+static SAS_DEVICE_ATTR(rphy, device_type, S_IRUGO,
show_sas_rphy_device_type, NULL);
static ssize_t
-show_sas_rphy_enclosure_identifier(struct class_device *cdev, char *buf)
+show_sas_rphy_enclosure_identifier(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct sas_rphy *rphy = transport_class_to_rphy(cdev);
+ struct sas_rphy *rphy = transport_class_to_rphy(dev);
struct sas_phy *phy = dev_to_phy(rphy->dev.parent);
struct Scsi_Host *shost = dev_to_shost(phy->dev.parent);
struct sas_internal *i = to_sas_internal(shost->transportt);
return sprintf(buf, "0x%llx\n", (unsigned long long)identifier);
}
-static SAS_CLASS_DEVICE_ATTR(rphy, enclosure_identifier, S_IRUGO,
+static SAS_DEVICE_ATTR(rphy, enclosure_identifier, S_IRUGO,
show_sas_rphy_enclosure_identifier, NULL);
static ssize_t
-show_sas_rphy_bay_identifier(struct class_device *cdev, char *buf)
+show_sas_rphy_bay_identifier(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct sas_rphy *rphy = transport_class_to_rphy(cdev);
+ struct sas_rphy *rphy = transport_class_to_rphy(dev);
struct sas_phy *phy = dev_to_phy(rphy->dev.parent);
struct Scsi_Host *shost = dev_to_shost(phy->dev.parent);
struct sas_internal *i = to_sas_internal(shost->transportt);
return sprintf(buf, "%d\n", val);
}
-static SAS_CLASS_DEVICE_ATTR(rphy, bay_identifier, S_IRUGO,
+static SAS_DEVICE_ATTR(rphy, bay_identifier, S_IRUGO,
show_sas_rphy_bay_identifier, NULL);
sas_rphy_protocol_attr(identify.initiator_port_protocols,
#define sas_end_dev_show_simple(field, name, format_string, cast) \
static ssize_t \
-show_sas_end_dev_##name(struct class_device *cdev, char *buf) \
+show_sas_end_dev_##name(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct sas_rphy *rphy = transport_class_to_rphy(cdev); \
+ struct sas_rphy *rphy = transport_class_to_rphy(dev); \
struct sas_end_device *rdev = rphy_to_end_device(rphy); \
\
return snprintf(buf, 20, format_string, cast rdev->field); \
#define sas_end_dev_simple_attr(field, name, format_string, type) \
sas_end_dev_show_simple(field, name, format_string, (type)) \
-static SAS_CLASS_DEVICE_ATTR(end_dev, name, S_IRUGO, \
+static SAS_DEVICE_ATTR(end_dev, name, S_IRUGO, \
show_sas_end_dev_##name, NULL)
sas_end_dev_simple_attr(ready_led_meaning, ready_led_meaning, "%d\n", int);
#define sas_expander_show_simple(field, name, format_string, cast) \
static ssize_t \
-show_sas_expander_##name(struct class_device *cdev, char *buf) \
+show_sas_expander_##name(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct sas_rphy *rphy = transport_class_to_rphy(cdev); \
+ struct sas_rphy *rphy = transport_class_to_rphy(dev); \
struct sas_expander_device *edev = rphy_to_expander_device(rphy); \
\
return snprintf(buf, 20, format_string, cast edev->field); \
#define sas_expander_simple_attr(field, name, format_string, type) \
sas_expander_show_simple(field, name, format_string, (type)) \
-static SAS_CLASS_DEVICE_ATTR(expander, name, S_IRUGO, \
+static SAS_DEVICE_ATTR(expander, name, S_IRUGO, \
show_sas_expander_##name, NULL)
sas_expander_simple_attr(vendor_id, vendor_id, "%s\n", char *);
*/
#define SETUP_TEMPLATE(attrb, field, perm, test) \
- i->private_##attrb[count] = class_device_attr_##field; \
+ i->private_##attrb[count] = dev_attr_##field; \
i->private_##attrb[count].attr.mode = perm; \
i->attrb[count] = &i->private_##attrb[count]; \
if (test) \
count++
#define SETUP_TEMPLATE_RW(attrb, field, perm, test, ro_test, ro_perm) \
- i->private_##attrb[count] = class_device_attr_##field; \
+ i->private_##attrb[count] = dev_attr_##field; \
i->private_##attrb[count].attr.mode = perm; \
if (ro_test) { \
i->private_##attrb[count].attr.mode = ro_perm; \
}
static int spi_host_setup(struct transport_container *tc, struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct Scsi_Host *shost = dev_to_shost(dev);
static int spi_host_configure(struct transport_container *tc,
struct device *dev,
- struct class_device *cdev);
+ struct device *cdev);
static DECLARE_TRANSPORT_CLASS(spi_host_class,
"spi_host",
static int spi_target_configure(struct transport_container *tc,
struct device *dev,
- struct class_device *cdev);
+ struct device *cdev);
static int spi_device_configure(struct transport_container *tc,
struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct scsi_device *sdev = to_scsi_device(dev);
struct scsi_target *starget = sdev->sdev_target;
static int spi_setup_transport_attrs(struct transport_container *tc,
struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct scsi_target *starget = to_scsi_target(dev);
#define spi_transport_show_simple(field, format_string) \
\
static ssize_t \
-show_spi_transport_##field(struct class_device *cdev, char *buf) \
+show_spi_transport_##field(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct scsi_target *starget = transport_class_to_starget(cdev); \
+ struct scsi_target *starget = transport_class_to_starget(dev); \
struct spi_transport_attrs *tp; \
\
tp = (struct spi_transport_attrs *)&starget->starget_data; \
#define spi_transport_store_simple(field, format_string) \
\
static ssize_t \
-store_spi_transport_##field(struct class_device *cdev, const char *buf, \
- size_t count) \
+store_spi_transport_##field(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
int val; \
- struct scsi_target *starget = transport_class_to_starget(cdev); \
+ struct scsi_target *starget = transport_class_to_starget(dev); \
struct spi_transport_attrs *tp; \
\
tp = (struct spi_transport_attrs *)&starget->starget_data; \
#define spi_transport_show_function(field, format_string) \
\
static ssize_t \
-show_spi_transport_##field(struct class_device *cdev, char *buf) \
+show_spi_transport_##field(struct device *dev, \
+ struct device_attribute *attr, char *buf) \
{ \
- struct scsi_target *starget = transport_class_to_starget(cdev); \
+ struct scsi_target *starget = transport_class_to_starget(dev); \
struct Scsi_Host *shost = dev_to_shost(starget->dev.parent); \
struct spi_transport_attrs *tp; \
struct spi_internal *i = to_spi_internal(shost->transportt); \
#define spi_transport_store_function(field, format_string) \
static ssize_t \
-store_spi_transport_##field(struct class_device *cdev, const char *buf, \
- size_t count) \
+store_spi_transport_##field(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
int val; \
- struct scsi_target *starget = transport_class_to_starget(cdev); \
+ struct scsi_target *starget = transport_class_to_starget(dev); \
struct Scsi_Host *shost = dev_to_shost(starget->dev.parent); \
struct spi_internal *i = to_spi_internal(shost->transportt); \
\
#define spi_transport_store_max(field, format_string) \
static ssize_t \
-store_spi_transport_##field(struct class_device *cdev, const char *buf, \
- size_t count) \
+store_spi_transport_##field(struct device *dev, \
+ struct device_attribute *attr, \
+ const char *buf, size_t count) \
{ \
int val; \
- struct scsi_target *starget = transport_class_to_starget(cdev); \
+ struct scsi_target *starget = transport_class_to_starget(dev); \
struct Scsi_Host *shost = dev_to_shost(starget->dev.parent); \
struct spi_internal *i = to_spi_internal(shost->transportt); \
struct spi_transport_attrs *tp \
#define spi_transport_rd_attr(field, format_string) \
spi_transport_show_function(field, format_string) \
spi_transport_store_function(field, format_string) \
-static CLASS_DEVICE_ATTR(field, S_IRUGO, \
- show_spi_transport_##field, \
- store_spi_transport_##field);
+static DEVICE_ATTR(field, S_IRUGO, \
+ show_spi_transport_##field, \
+ store_spi_transport_##field);
#define spi_transport_simple_attr(field, format_string) \
spi_transport_show_simple(field, format_string) \
spi_transport_store_simple(field, format_string) \
-static CLASS_DEVICE_ATTR(field, S_IRUGO, \
- show_spi_transport_##field, \
- store_spi_transport_##field);
+static DEVICE_ATTR(field, S_IRUGO, \
+ show_spi_transport_##field, \
+ store_spi_transport_##field);
#define spi_transport_max_attr(field, format_string) \
spi_transport_show_function(field, format_string) \
spi_transport_store_max(field, format_string) \
spi_transport_simple_attr(max_##field, format_string) \
-static CLASS_DEVICE_ATTR(field, S_IRUGO, \
- show_spi_transport_##field, \
- store_spi_transport_##field);
+static DEVICE_ATTR(field, S_IRUGO, \
+ show_spi_transport_##field, \
+ store_spi_transport_##field);
/* The Parallel SCSI Tranport Attributes: */
spi_transport_max_attr(offset, "%d\n");
}
static ssize_t
-store_spi_revalidate(struct class_device *cdev, const char *buf, size_t count)
+store_spi_revalidate(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct scsi_target *starget = transport_class_to_starget(cdev);
+ struct scsi_target *starget = transport_class_to_starget(dev);
device_for_each_child(&starget->dev, NULL, child_iter);
return count;
}
-static CLASS_DEVICE_ATTR(revalidate, S_IWUSR, NULL, store_spi_revalidate);
+static DEVICE_ATTR(revalidate, S_IWUSR, NULL, store_spi_revalidate);
/* Translate the period into ns according to the current spec
* for SDTR/PPR messages */
}
static ssize_t
-store_spi_transport_period_helper(struct class_device *cdev, const char *buf,
+store_spi_transport_period_helper(struct device *dev, const char *buf,
size_t count, int *periodp)
{
int j, picosec, period = -1;
}
static ssize_t
-show_spi_transport_period(struct class_device *cdev, char *buf)
+show_spi_transport_period(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
- struct scsi_target *starget = transport_class_to_starget(cdev);
+ struct scsi_target *starget = transport_class_to_starget(dev);
struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
struct spi_internal *i = to_spi_internal(shost->transportt);
struct spi_transport_attrs *tp =
}
static ssize_t
-store_spi_transport_period(struct class_device *cdev, const char *buf,
- size_t count)
+store_spi_transport_period(struct device *cdev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
struct scsi_target *starget = transport_class_to_starget(cdev);
struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
return retval;
}
-static CLASS_DEVICE_ATTR(period, S_IRUGO,
- show_spi_transport_period,
- store_spi_transport_period);
+static DEVICE_ATTR(period, S_IRUGO,
+ show_spi_transport_period,
+ store_spi_transport_period);
static ssize_t
-show_spi_transport_min_period(struct class_device *cdev, char *buf)
+show_spi_transport_min_period(struct device *cdev,
+ struct device_attribute *attr, char *buf)
{
struct scsi_target *starget = transport_class_to_starget(cdev);
struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
}
static ssize_t
-store_spi_transport_min_period(struct class_device *cdev, const char *buf,
- size_t count)
+store_spi_transport_min_period(struct device *cdev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
struct scsi_target *starget = transport_class_to_starget(cdev);
struct spi_transport_attrs *tp =
}
-static CLASS_DEVICE_ATTR(min_period, S_IRUGO,
- show_spi_transport_min_period,
- store_spi_transport_min_period);
+static DEVICE_ATTR(min_period, S_IRUGO,
+ show_spi_transport_min_period,
+ store_spi_transport_min_period);
-static ssize_t show_spi_host_signalling(struct class_device *cdev, char *buf)
+static ssize_t show_spi_host_signalling(struct device *cdev,
+ struct device_attribute *attr,
+ char *buf)
{
struct Scsi_Host *shost = transport_class_to_shost(cdev);
struct spi_internal *i = to_spi_internal(shost->transportt);
return sprintf(buf, "%s\n", spi_signal_to_string(spi_signalling(shost)));
}
-static ssize_t store_spi_host_signalling(struct class_device *cdev,
+static ssize_t store_spi_host_signalling(struct device *dev,
+ struct device_attribute *attr,
const char *buf, size_t count)
{
- struct Scsi_Host *shost = transport_class_to_shost(cdev);
+ struct Scsi_Host *shost = transport_class_to_shost(dev);
struct spi_internal *i = to_spi_internal(shost->transportt);
enum spi_signal_type type = spi_signal_to_value(buf);
return count;
}
-static CLASS_DEVICE_ATTR(signalling, S_IRUGO,
- show_spi_host_signalling,
- store_spi_host_signalling);
+static DEVICE_ATTR(signalling, S_IRUGO,
+ show_spi_host_signalling,
+ store_spi_host_signalling);
#define DV_SET(x, y) \
if(i->f->set_##x) \
spi_device_configure);
static struct attribute *host_attributes[] = {
- &class_device_attr_signalling.attr,
+ &dev_attr_signalling.attr,
NULL
};
static int spi_host_configure(struct transport_container *tc,
struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct kobject *kobj = &cdev->kobj;
struct Scsi_Host *shost = transport_class_to_shost(cdev);
struct spi_internal *si = to_spi_internal(shost->transportt);
- struct attribute *attr = &class_device_attr_signalling.attr;
+ struct attribute *attr = &dev_attr_signalling.attr;
int rc = 0;
if (si->f->set_signalling)
static int target_attribute_is_visible(struct kobject *kobj,
struct attribute *attr, int i)
{
- struct class_device *cdev =
- container_of(kobj, struct class_device, kobj);
+ struct device *cdev = container_of(kobj, struct device, kobj);
struct scsi_target *starget = transport_class_to_starget(cdev);
struct Scsi_Host *shost = transport_class_to_shost(cdev);
struct spi_internal *si = to_spi_internal(shost->transportt);
- if (attr == &class_device_attr_period.attr &&
+ if (attr == &dev_attr_period.attr &&
spi_support_sync(starget))
return TARGET_ATTRIBUTE_HELPER(period);
- else if (attr == &class_device_attr_min_period.attr &&
+ else if (attr == &dev_attr_min_period.attr &&
spi_support_sync(starget))
return TARGET_ATTRIBUTE_HELPER(period);
- else if (attr == &class_device_attr_offset.attr &&
+ else if (attr == &dev_attr_offset.attr &&
spi_support_sync(starget))
return TARGET_ATTRIBUTE_HELPER(offset);
- else if (attr == &class_device_attr_max_offset.attr &&
+ else if (attr == &dev_attr_max_offset.attr &&
spi_support_sync(starget))
return TARGET_ATTRIBUTE_HELPER(offset);
- else if (attr == &class_device_attr_width.attr &&
+ else if (attr == &dev_attr_width.attr &&
spi_support_wide(starget))
return TARGET_ATTRIBUTE_HELPER(width);
- else if (attr == &class_device_attr_max_width.attr &&
+ else if (attr == &dev_attr_max_width.attr &&
spi_support_wide(starget))
return TARGET_ATTRIBUTE_HELPER(width);
- else if (attr == &class_device_attr_iu.attr &&
+ else if (attr == &dev_attr_iu.attr &&
spi_support_ius(starget))
return TARGET_ATTRIBUTE_HELPER(iu);
- else if (attr == &class_device_attr_dt.attr &&
+ else if (attr == &dev_attr_dt.attr &&
spi_support_dt(starget))
return TARGET_ATTRIBUTE_HELPER(dt);
- else if (attr == &class_device_attr_qas.attr &&
+ else if (attr == &dev_attr_qas.attr &&
spi_support_qas(starget))
return TARGET_ATTRIBUTE_HELPER(qas);
- else if (attr == &class_device_attr_wr_flow.attr &&
+ else if (attr == &dev_attr_wr_flow.attr &&
spi_support_ius(starget))
return TARGET_ATTRIBUTE_HELPER(wr_flow);
- else if (attr == &class_device_attr_rd_strm.attr &&
+ else if (attr == &dev_attr_rd_strm.attr &&
spi_support_ius(starget))
return TARGET_ATTRIBUTE_HELPER(rd_strm);
- else if (attr == &class_device_attr_rti.attr &&
+ else if (attr == &dev_attr_rti.attr &&
spi_support_ius(starget))
return TARGET_ATTRIBUTE_HELPER(rti);
- else if (attr == &class_device_attr_pcomp_en.attr &&
+ else if (attr == &dev_attr_pcomp_en.attr &&
spi_support_ius(starget))
return TARGET_ATTRIBUTE_HELPER(pcomp_en);
- else if (attr == &class_device_attr_hold_mcs.attr &&
+ else if (attr == &dev_attr_hold_mcs.attr &&
spi_support_ius(starget))
return TARGET_ATTRIBUTE_HELPER(hold_mcs);
- else if (attr == &class_device_attr_revalidate.attr)
+ else if (attr == &dev_attr_revalidate.attr)
return 1;
return 0;
}
static struct attribute *target_attributes[] = {
- &class_device_attr_period.attr,
- &class_device_attr_min_period.attr,
- &class_device_attr_offset.attr,
- &class_device_attr_max_offset.attr,
- &class_device_attr_width.attr,
- &class_device_attr_max_width.attr,
- &class_device_attr_iu.attr,
- &class_device_attr_dt.attr,
- &class_device_attr_qas.attr,
- &class_device_attr_wr_flow.attr,
- &class_device_attr_rd_strm.attr,
- &class_device_attr_rti.attr,
- &class_device_attr_pcomp_en.attr,
- &class_device_attr_hold_mcs.attr,
- &class_device_attr_revalidate.attr,
+ &dev_attr_period.attr,
+ &dev_attr_min_period.attr,
+ &dev_attr_offset.attr,
+ &dev_attr_max_offset.attr,
+ &dev_attr_width.attr,
+ &dev_attr_max_width.attr,
+ &dev_attr_iu.attr,
+ &dev_attr_dt.attr,
+ &dev_attr_qas.attr,
+ &dev_attr_wr_flow.attr,
+ &dev_attr_rd_strm.attr,
+ &dev_attr_rti.attr,
+ &dev_attr_pcomp_en.attr,
+ &dev_attr_hold_mcs.attr,
+ &dev_attr_revalidate.attr,
NULL
};
static int spi_target_configure(struct transport_container *tc,
struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct kobject *kobj = &cdev->kobj;
int i;
* to ignore, sysfs also does a WARN_ON and dumps a trace,
* which is bad, so temporarily, skip attributes that are
* already visible (the revalidate one) */
- if (j && attr != &class_device_attr_revalidate.attr)
+ if (j && attr != &dev_attr_revalidate.attr)
rc = sysfs_add_file_to_group(kobj, attr,
target_attribute_group.name);
/* and make the attribute writeable if we have a set
struct scsi_transport_template t;
struct srp_function_template *f;
- struct class_device_attribute *host_attrs[SRP_HOST_ATTRS + 1];
+ struct device_attribute *host_attrs[SRP_HOST_ATTRS + 1];
- struct class_device_attribute *rport_attrs[SRP_RPORT_ATTRS + 1];
- struct class_device_attribute private_rport_attrs[SRP_RPORT_ATTRS];
+ struct device_attribute *rport_attrs[SRP_RPORT_ATTRS + 1];
+ struct device_attribute private_rport_attrs[SRP_RPORT_ATTRS];
struct transport_container rport_attr_cont;
};
#define to_srp_internal(tmpl) container_of(tmpl, struct srp_internal, t)
#define dev_to_rport(d) container_of(d, struct srp_rport, dev)
-#define transport_class_to_srp_rport(cdev) dev_to_rport((cdev)->dev)
+#define transport_class_to_srp_rport(dev) dev_to_rport((dev)->parent)
static int srp_host_setup(struct transport_container *tc, struct device *dev,
- struct class_device *cdev)
+ struct device *cdev)
{
struct Scsi_Host *shost = dev_to_shost(dev);
struct srp_host_attrs *srp_host = to_srp_host_attrs(shost);
NULL, NULL, NULL);
#define SETUP_TEMPLATE(attrb, field, perm, test, ro_test, ro_perm) \
- i->private_##attrb[count] = class_device_attr_##field; \
+ i->private_##attrb[count] = dev_attr_##field; \
i->private_##attrb[count].attr.mode = perm; \
if (ro_test) { \
i->private_##attrb[count].attr.mode = ro_perm; \
"%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x"
static ssize_t
-show_srp_rport_id(struct class_device *cdev, char *buf)
+show_srp_rport_id(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct srp_rport *rport = transport_class_to_srp_rport(cdev);
+ struct srp_rport *rport = transport_class_to_srp_rport(dev);
return sprintf(buf, SRP_PID_FMT "\n", SRP_PID(rport));
}
-static CLASS_DEVICE_ATTR(port_id, S_IRUGO, show_srp_rport_id, NULL);
+static DEVICE_ATTR(port_id, S_IRUGO, show_srp_rport_id, NULL);
static const struct {
u32 value;
};
static ssize_t
-show_srp_rport_roles(struct class_device *cdev, char *buf)
+show_srp_rport_roles(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct srp_rport *rport = transport_class_to_srp_rport(cdev);
+ struct srp_rport *rport = transport_class_to_srp_rport(dev);
int i;
char *name = NULL;
return sprintf(buf, "%s\n", name ? : "unknown");
}
-static CLASS_DEVICE_ATTR(roles, S_IRUGO, show_srp_rport_roles, NULL);
+static DEVICE_ATTR(roles, S_IRUGO, show_srp_rport_roles, NULL);
static void srp_rport_release(struct device *dev)
{
static void sd_rescan(struct device *);
static int sd_done(struct scsi_cmnd *);
static void sd_read_capacity(struct scsi_disk *sdkp, unsigned char *buffer);
-static void scsi_disk_release(struct class_device *cdev);
+static void scsi_disk_release(struct device *cdev);
static void sd_print_sense_hdr(struct scsi_disk *, struct scsi_sense_hdr *);
static void sd_print_result(struct scsi_disk *, int);
"write back, no read (daft)"
};
-static ssize_t sd_store_cache_type(struct class_device *cdev, const char *buf,
- size_t count)
+static ssize_t
+sd_store_cache_type(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
int i, ct = -1, rcd, wce, sp;
- struct scsi_disk *sdkp = to_scsi_disk(cdev);
+ struct scsi_disk *sdkp = to_scsi_disk(dev);
struct scsi_device *sdp = sdkp->device;
char buffer[64];
char *buffer_data;
return count;
}
-static ssize_t sd_store_manage_start_stop(struct class_device *cdev,
- const char *buf, size_t count)
+static ssize_t
+sd_store_manage_start_stop(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct scsi_disk *sdkp = to_scsi_disk(cdev);
+ struct scsi_disk *sdkp = to_scsi_disk(dev);
struct scsi_device *sdp = sdkp->device;
if (!capable(CAP_SYS_ADMIN))
return count;
}
-static ssize_t sd_store_allow_restart(struct class_device *cdev, const char *buf,
- size_t count)
+static ssize_t
+sd_store_allow_restart(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
{
- struct scsi_disk *sdkp = to_scsi_disk(cdev);
+ struct scsi_disk *sdkp = to_scsi_disk(dev);
struct scsi_device *sdp = sdkp->device;
if (!capable(CAP_SYS_ADMIN))
return count;
}
-static ssize_t sd_show_cache_type(struct class_device *cdev, char *buf)
+static ssize_t
+sd_show_cache_type(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct scsi_disk *sdkp = to_scsi_disk(cdev);
+ struct scsi_disk *sdkp = to_scsi_disk(dev);
int ct = sdkp->RCD + 2*sdkp->WCE;
return snprintf(buf, 40, "%s\n", sd_cache_types[ct]);
}
-static ssize_t sd_show_fua(struct class_device *cdev, char *buf)
+static ssize_t
+sd_show_fua(struct device *dev, struct device_attribute *attr, char *buf)
{
- struct scsi_disk *sdkp = to_scsi_disk(cdev);
+ struct scsi_disk *sdkp = to_scsi_disk(dev);
return snprintf(buf, 20, "%u\n", sdkp->DPOFUA);
}
-static ssize_t sd_show_manage_start_stop(struct class_device *cdev, char *buf)
+static ssize_t
+sd_show_manage_start_stop(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct scsi_disk *sdkp = to_scsi_disk(cdev);
+ struct scsi_disk *sdkp = to_scsi_disk(dev);
struct scsi_device *sdp = sdkp->device;
return snprintf(buf, 20, "%u\n", sdp->manage_start_stop);
}
-static ssize_t sd_show_allow_restart(struct class_device *cdev, char *buf)
+static ssize_t
+sd_show_allow_restart(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct scsi_disk *sdkp = to_scsi_disk(cdev);
+ struct scsi_disk *sdkp = to_scsi_disk(dev);
return snprintf(buf, 40, "%d\n", sdkp->device->allow_restart);
}
-static struct class_device_attribute sd_disk_attrs[] = {
+static struct device_attribute sd_disk_attrs[] = {
__ATTR(cache_type, S_IRUGO|S_IWUSR, sd_show_cache_type,
sd_store_cache_type),
__ATTR(FUA, S_IRUGO, sd_show_fua, NULL),
static struct class sd_disk_class = {
.name = "scsi_disk",
.owner = THIS_MODULE,
- .release = scsi_disk_release,
- .class_dev_attrs = sd_disk_attrs,
+ .dev_release = scsi_disk_release,
+ .dev_attrs = sd_disk_attrs,
};
static struct scsi_driver sd_template = {
if (disk->private_data) {
sdkp = scsi_disk(disk);
if (scsi_device_get(sdkp->device) == 0)
- class_device_get(&sdkp->cdev);
+ get_device(&sdkp->dev);
else
sdkp = NULL;
}
struct scsi_device *sdev = sdkp->device;
mutex_lock(&sd_ref_mutex);
- class_device_put(&sdkp->cdev);
+ put_device(&sdkp->dev);
scsi_device_put(sdev);
mutex_unlock(&sd_ref_mutex);
}
sdp->timeout = SD_MOD_TIMEOUT;
}
- class_device_initialize(&sdkp->cdev);
- sdkp->cdev.dev = &sdp->sdev_gendev;
- sdkp->cdev.class = &sd_disk_class;
- strncpy(sdkp->cdev.class_id, sdp->sdev_gendev.bus_id, BUS_ID_SIZE);
+ device_initialize(&sdkp->dev);
+ sdkp->dev.parent = &sdp->sdev_gendev;
+ sdkp->dev.class = &sd_disk_class;
+ strncpy(sdkp->dev.bus_id, sdp->sdev_gendev.bus_id, BUS_ID_SIZE);
- if (class_device_add(&sdkp->cdev))
+ if (device_add(&sdkp->dev))
goto out_put;
get_device(&sdp->sdev_gendev);
{
struct scsi_disk *sdkp = dev_get_drvdata(dev);
- class_device_del(&sdkp->cdev);
+ device_del(&sdkp->dev);
del_gendisk(sdkp->disk);
sd_shutdown(dev);
mutex_lock(&sd_ref_mutex);
dev_set_drvdata(dev, NULL);
- class_device_put(&sdkp->cdev);
+ put_device(&sdkp->dev);
mutex_unlock(&sd_ref_mutex);
return 0;
/**
* scsi_disk_release - Called to free the scsi_disk structure
- * @cdev: pointer to embedded class device
+ * @dev: pointer to embedded class device
*
* sd_ref_mutex must be held entering this routine. Because it is
* called on last put, you should always use the scsi_disk_get()
* scsi_disk_put() helpers which manipulate the semaphore directly
- * and never do a direct class_device_put().
+ * and never do a direct put_device.
**/
-static void scsi_disk_release(struct class_device *cdev)
+static void scsi_disk_release(struct device *dev)
{
- struct scsi_disk *sdkp = to_scsi_disk(cdev);
+ struct scsi_disk *sdkp = to_scsi_disk(dev);
struct gendisk *disk = sdkp->disk;
spin_lock(&sd_index_lock);
unsigned char *desc)
{
int i, j, count = 0, descriptor = ecomp->number;
- struct scsi_device *sdev = to_scsi_device(edev->cdev.dev);
+ struct scsi_device *sdev = to_scsi_device(edev->edev.parent);
struct ses_device *ses_dev = edev->scratch;
unsigned char *type_ptr = ses_dev->page1 + 12 + ses_dev->page1[11];
unsigned char *desc_ptr = ses_dev->page2 + 8;
struct enclosure_component *ecomp)
{
int i, j, count = 0, descriptor = ecomp->number;
- struct scsi_device *sdev = to_scsi_device(edev->cdev.dev);
+ struct scsi_device *sdev = to_scsi_device(edev->edev.parent);
struct ses_device *ses_dev = edev->scratch;
unsigned char *type_ptr = ses_dev->page1 + 12 + ses_dev->page1[11];
unsigned char *desc_ptr = ses_dev->page2 + 8;
struct ses_host_edev *sed = data;
struct scsi_device *sdev;
- if (!scsi_is_sdev_device(edev->cdev.dev))
+ if (!scsi_is_sdev_device(edev->edev.parent))
return 0;
- sdev = to_scsi_device(edev->cdev.dev);
+ sdev = to_scsi_device(edev->edev.parent);
if (sdev->host != sed->shost)
return 0;
#define INIT_ALLOC_SIZE 32
-static int ses_intf_add(struct class_device *cdev,
+static int ses_intf_add(struct device *cdev,
struct class_interface *intf)
{
- struct scsi_device *sdev = to_scsi_device(cdev->dev);
+ struct scsi_device *sdev = to_scsi_device(cdev->parent);
struct scsi_device *tmp_sdev;
unsigned char *buf = NULL, *hdr_buf, *type_ptr, *desc_ptr = NULL,
*addl_desc_ptr = NULL;
edev = enclosure_find(&sdev->host->shost_gendev);
if (edev) {
ses_match_to_enclosure(edev, sdev);
- class_device_put(&edev->cdev);
+ put_device(&edev->edev);
}
return -ENODEV;
}
if (!scomp)
goto err_free;
- edev = enclosure_register(cdev->dev, sdev->sdev_gendev.bus_id,
+ edev = enclosure_register(cdev->parent, sdev->sdev_gendev.bus_id,
components, &ses_enclosure_callbacks);
if (IS_ERR(edev)) {
err = PTR_ERR(edev);
return 0;
}
-static void ses_intf_remove(struct class_device *cdev,
+static void ses_intf_remove(struct device *cdev,
struct class_interface *intf)
{
- struct scsi_device *sdev = to_scsi_device(cdev->dev);
+ struct scsi_device *sdev = to_scsi_device(cdev->parent);
struct enclosure_device *edev;
struct ses_device *ses_dev;
if (!scsi_device_enclosure(sdev))
return;
- edev = enclosure_find(cdev->dev);
+ edev = enclosure_find(cdev->parent);
if (!edev)
return;
kfree(edev->component[0].scratch);
- class_device_put(&edev->cdev);
+ put_device(&edev->edev);
enclosure_unregister(edev);
}
static struct class_interface ses_interface = {
- .add = ses_intf_add,
- .remove = ses_intf_remove,
+ .add_dev = ses_intf_add,
+ .remove_dev = ses_intf_remove,
};
static struct scsi_driver ses_template = {
#define SG_SECTOR_SZ 512
#define SG_SECTOR_MSK (SG_SECTOR_SZ - 1)
-static int sg_add(struct class_device *, struct class_interface *);
-static void sg_remove(struct class_device *, struct class_interface *);
+static int sg_add(struct device *, struct class_interface *);
+static void sg_remove(struct device *, struct class_interface *);
static DEFINE_IDR(sg_index_idr);
static DEFINE_RWLOCK(sg_index_lock); /* Also used to lock
file descriptor list for device */
static struct class_interface sg_interface = {
- .add = sg_add,
- .remove = sg_remove,
+ .add_dev = sg_add,
+ .remove_dev = sg_remove,
};
typedef struct sg_scatter_hold { /* holding area for scsi scatter gather info */
}
static int
-sg_add(struct class_device *cl_dev, struct class_interface *cl_intf)
+sg_add(struct device *cl_dev, struct class_interface *cl_intf)
{
- struct scsi_device *scsidp = to_scsi_device(cl_dev->dev);
+ struct scsi_device *scsidp = to_scsi_device(cl_dev->parent);
struct gendisk *disk;
Sg_device *sdp = NULL;
struct cdev * cdev = NULL;
sdp->cdev = cdev;
if (sg_sysfs_valid) {
- struct class_device * sg_class_member;
+ struct device *sg_class_member;
- sg_class_member = class_device_create(sg_sysfs_class, NULL,
- MKDEV(SCSI_GENERIC_MAJOR, sdp->index),
- cl_dev->dev, "%s",
- disk->disk_name);
+ sg_class_member = device_create(sg_sysfs_class, cl_dev->parent,
+ MKDEV(SCSI_GENERIC_MAJOR,
+ sdp->index),
+ "%s", disk->disk_name);
if (IS_ERR(sg_class_member)) {
printk(KERN_ERR "sg_add: "
- "class_device_create failed\n");
+ "device_create failed\n");
error = PTR_ERR(sg_class_member);
goto cdev_add_err;
}
- class_set_devdata(sg_class_member, sdp);
+ dev_set_drvdata(sg_class_member, sdp);
error = sysfs_create_link(&scsidp->sdev_gendev.kobj,
&sg_class_member->kobj, "generic");
if (error)
"Attached scsi generic sg%d type %d\n", sdp->index,
scsidp->type);
- class_set_devdata(cl_dev, sdp);
+ dev_set_drvdata(cl_dev, sdp);
return 0;
}
static void
-sg_remove(struct class_device *cl_dev, struct class_interface *cl_intf)
+sg_remove(struct device *cl_dev, struct class_interface *cl_intf)
{
- struct scsi_device *scsidp = to_scsi_device(cl_dev->dev);
- Sg_device *sdp = class_get_devdata(cl_dev);
+ struct scsi_device *scsidp = to_scsi_device(cl_dev->parent);
+ Sg_device *sdp = dev_get_drvdata(cl_dev);
unsigned long iflags;
Sg_fd *sfp;
Sg_fd *tsfp;
write_unlock_irqrestore(&sg_index_lock, iflags);
sysfs_remove_link(&scsidp->sdev_gendev.kobj, "generic");
- class_device_destroy(sg_sysfs_class, MKDEV(SCSI_GENERIC_MAJOR, sdp->index));
+ device_destroy(sg_sysfs_class, MKDEV(SCSI_GENERIC_MAJOR, sdp->index));
cdev_del(sdp->cdev);
sdp->cdev = NULL;
put_disk(sdp->disk);
if (STm->cdevs[j]) {
if (cdev == STm->cdevs[j])
cdev = NULL;
- class_device_destroy(st_sysfs_class,
- MKDEV(SCSI_TAPE_MAJOR,
- TAPE_MINOR(i, mode, j)));
+ device_destroy(st_sysfs_class,
+ MKDEV(SCSI_TAPE_MAJOR,
+ TAPE_MINOR(i, mode, j)));
cdev_del(STm->cdevs[j]);
}
}
"tape");
for (mode = 0; mode < ST_NBR_MODES; ++mode) {
for (j=0; j < 2; j++) {
- class_device_destroy(st_sysfs_class,
- MKDEV(SCSI_TAPE_MAJOR,
- TAPE_MINOR(i, mode, j)));
+ device_destroy(st_sysfs_class,
+ MKDEV(SCSI_TAPE_MAJOR,
+ TAPE_MINOR(i, mode, j)));
cdev_del(tpnt->modes[mode].cdevs[j]);
tpnt->modes[mode].cdevs[j] = NULL;
}
/* The sysfs simple class interface */
-static ssize_t st_defined_show(struct class_device *class_dev, char *buf)
+static ssize_t
+st_defined_show(struct device *dev, struct device_attribute *attr, char *buf)
{
- struct st_modedef *STm = (struct st_modedef *)class_get_devdata(class_dev);
+ struct st_modedef *STm = (struct st_modedef *)dev_get_drvdata(dev);
ssize_t l = 0;
l = snprintf(buf, PAGE_SIZE, "%d\n", STm->defined);
return l;
}
-CLASS_DEVICE_ATTR(defined, S_IRUGO, st_defined_show, NULL);
+DEVICE_ATTR(defined, S_IRUGO, st_defined_show, NULL);
-static ssize_t st_defblk_show(struct class_device *class_dev, char *buf)
+static ssize_t
+st_defblk_show(struct device *dev, struct device_attribute *attr, char *buf)
{
- struct st_modedef *STm = (struct st_modedef *)class_get_devdata(class_dev);
+ struct st_modedef *STm = (struct st_modedef *)dev_get_drvdata(dev);
ssize_t l = 0;
l = snprintf(buf, PAGE_SIZE, "%d\n", STm->default_blksize);
return l;
}
-CLASS_DEVICE_ATTR(default_blksize, S_IRUGO, st_defblk_show, NULL);
+DEVICE_ATTR(default_blksize, S_IRUGO, st_defblk_show, NULL);
-static ssize_t st_defdensity_show(struct class_device *class_dev, char *buf)
+static ssize_t
+st_defdensity_show(struct device *dev, struct device_attribute *attr, char *buf)
{
- struct st_modedef *STm = (struct st_modedef *)class_get_devdata(class_dev);
+ struct st_modedef *STm = (struct st_modedef *)dev_get_drvdata(dev);
ssize_t l = 0;
char *fmt;
return l;
}
-CLASS_DEVICE_ATTR(default_density, S_IRUGO, st_defdensity_show, NULL);
+DEVICE_ATTR(default_density, S_IRUGO, st_defdensity_show, NULL);
-static ssize_t st_defcompression_show(struct class_device *class_dev, char *buf)
+static ssize_t
+st_defcompression_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
{
- struct st_modedef *STm = (struct st_modedef *)class_get_devdata(class_dev);
+ struct st_modedef *STm = (struct st_modedef *)dev_get_drvdata(dev);
ssize_t l = 0;
l = snprintf(buf, PAGE_SIZE, "%d\n", STm->default_compression - 1);
return l;
}
-CLASS_DEVICE_ATTR(default_compression, S_IRUGO, st_defcompression_show, NULL);
+DEVICE_ATTR(default_compression, S_IRUGO, st_defcompression_show, NULL);
-static ssize_t st_options_show(struct class_device *class_dev, char *buf)
+static ssize_t
+st_options_show(struct device *dev, struct device_attribute *attr, char *buf)
{
- struct st_modedef *STm = (struct st_modedef *)class_get_devdata(class_dev);
+ struct st_modedef *STm = (struct st_modedef *)dev_get_drvdata(dev);
struct scsi_tape *STp;
int i, j, options;
ssize_t l = 0;
return l;
}
-CLASS_DEVICE_ATTR(options, S_IRUGO, st_options_show, NULL);
+DEVICE_ATTR(options, S_IRUGO, st_options_show, NULL);
static int do_create_class_files(struct scsi_tape *STp, int dev_num, int mode)
{
int i, rew, error;
char name[10];
- struct class_device *st_class_member;
+ struct device *st_class_member;
for (rew=0; rew < 2; rew++) {
/* Make sure that the minor numbers corresponding to the four
snprintf(name, 10, "%s%s%s", rew ? "n" : "",
STp->disk->disk_name, st_formats[i]);
st_class_member =
- class_device_create(st_sysfs_class, NULL,
- MKDEV(SCSI_TAPE_MAJOR,
- TAPE_MINOR(dev_num, mode, rew)),
- &STp->device->sdev_gendev, "%s", name);
+ device_create(st_sysfs_class, &STp->device->sdev_gendev,
+ MKDEV(SCSI_TAPE_MAJOR,
+ TAPE_MINOR(dev_num, mode, rew)),
+ "%s", name);
if (IS_ERR(st_class_member)) {
- printk(KERN_WARNING "st%d: class_device_create failed\n",
+ printk(KERN_WARNING "st%d: device_create failed\n",
dev_num);
error = PTR_ERR(st_class_member);
goto out;
}
- class_set_devdata(st_class_member, &STp->modes[mode]);
+ dev_set_drvdata(st_class_member, &STp->modes[mode]);
- error = class_device_create_file(st_class_member,
- &class_device_attr_defined);
+ error = device_create_file(st_class_member,
+ &dev_attr_defined);
if (error) goto out;
- error = class_device_create_file(st_class_member,
- &class_device_attr_default_blksize);
+ error = device_create_file(st_class_member,
+ &dev_attr_default_blksize);
if (error) goto out;
- error = class_device_create_file(st_class_member,
- &class_device_attr_default_density);
+ error = device_create_file(st_class_member,
+ &dev_attr_default_density);
if (error) goto out;
- error = class_device_create_file(st_class_member,
- &class_device_attr_default_compression);
+ error = device_create_file(st_class_member,
+ &dev_attr_default_compression);
if (error) goto out;
- error = class_device_create_file(st_class_member,
- &class_device_attr_options);
+ error = device_create_file(st_class_member,
+ &dev_attr_options);
if (error) goto out;
if (mode == 0 && rew == 0) {
/* these are located in their respective files */
void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd);
+void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
+ struct device_node *np);
+void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram);
int cpm_uart_init_portdesc(void);
int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
void cpm_uart_freebuf(struct uart_cpm_port *pinfo);
if (!mem)
return -ENOMEM;
- pram = of_iomap(np, 1);
- if (!pram) {
- ret = -ENOMEM;
- goto out_mem;
- }
-
if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
pinfo->sccp = mem;
- pinfo->sccup = pram;
+ pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
} else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
pinfo->flags |= FLAG_SMC;
pinfo->smcp = mem;
- pinfo->smcup = pram;
+ pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
} else {
ret = -ENODEV;
- goto out_pram;
+ goto out_mem;
+ }
+
+ if (!pram) {
+ ret = -ENOMEM;
+ goto out_mem;
}
pinfo->tx_nrfifos = TX_NUM_FIFO;
return cpm_uart_request_port(&pinfo->port);
out_pram:
- iounmap(pram);
+ cpm_uart_unmap_pram(pinfo, pram);
out_mem:
iounmap(mem);
return ret;
#include <linux/serial_core.h>
#include <linux/kernel.h>
+#include <linux/of.h>
+
#include "cpm_uart.h"
/**************************************************************/
{
cpm_command(port->command, cmd);
}
+
+void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
+ struct device_node *np)
+{
+ return of_iomap(np, 1);
+}
+
+void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
+{
+ iounmap(pram);
+}
+
#else
void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/fs_pd.h>
+#ifdef CONFIG_PPC_CPM_NEW_BINDING
+#include <asm/prom.h>
+#endif
#include <linux/serial_core.h>
#include <linux/kernel.h>
{
cpm_command(port->command, cmd);
}
+
+void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
+ struct device_node *np)
+{
+ void __iomem *pram;
+ unsigned long offset;
+ struct resource res;
+ unsigned long len;
+
+ /* Don't remap parameter RAM if it has already been initialized
+ * during console setup.
+ */
+ if (IS_SMC(port) && port->smcup)
+ return port->smcup;
+ else if (!IS_SMC(port) && port->sccup)
+ return port->sccup;
+
+ if (of_address_to_resource(np, 1, &res))
+ return NULL;
+
+ len = 1 + res.end - res.start;
+ pram = ioremap(res.start, len);
+ if (!pram)
+ return NULL;
+
+ if (!IS_SMC(port))
+ return pram;
+
+ if (len != 2) {
+ printk(KERN_WARNING "cpm_uart[%d]: device tree references "
+ "SMC pram, using boot loader/wrapper pram mapping. "
+ "Please fix your device tree to reference the pram "
+ "base register instead.\n",
+ port->port.line);
+ return pram;
+ }
+
+ offset = cpm_dpalloc(PROFF_SMC_SIZE, 64);
+ out_be16(pram, offset);
+ iounmap(pram);
+ return cpm_muram_addr(offset);
+}
+
+void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
+{
+ if (!IS_SMC(port))
+ iounmap(pram);
+}
+
#else
void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{
#define SERIAL_IMX_MAJOR 204
#define MINOR_START 41
-#define NR_PORTS 2
-
-#define IMX_ISR_PASS_LIMIT 256
-
-/*
- * This is the size of our serial port register set.
- */
-#define UART_PORT_SIZE 0x100
-
/*
* This determines how often we check the modem status signals
* for any change. They generally aren't connected to an IRQ
struct tty_struct *tty = sport->port.info->tty;
unsigned long flags, temp;
- rx = readl(sport->port.membase + URXD0);
spin_lock_irqsave(&sport->port.lock,flags);
- do {
+ while (readl(sport->port.membase + USR2) & USR2_RDR) {
flg = TTY_NORMAL;
sport->port.icount.rx++;
+ rx = readl(sport->port.membase + URXD0);
+
temp = readl(sport->port.membase + USR2);
- if( temp & USR2_BRCD ) {
+ if (temp & USR2_BRCD) {
writel(temp | USR2_BRCD, sport->port.membase + USR2);
- if(uart_handle_break(&sport->port))
- goto ignore_char;
+ if (uart_handle_break(&sport->port))
+ continue;
}
if (uart_handle_sysrq_char
(&sport->port, (unsigned char)rx))
- goto ignore_char;
+ continue;
+
+ if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
+ if (rx & URXD_PRERR)
+ sport->port.icount.parity++;
+ else if (rx & URXD_FRMERR)
+ sport->port.icount.frame++;
+ if (rx & URXD_OVRRUN)
+ sport->port.icount.overrun++;
+
+ if (rx & sport->port.ignore_status_mask) {
+ if (++ignored > 100)
+ goto out;
+ continue;
+ }
+
+ rx &= sport->port.read_status_mask;
+
+ if (rx & URXD_PRERR)
+ flg = TTY_PARITY;
+ else if (rx & URXD_FRMERR)
+ flg = TTY_FRAME;
+ if (rx & URXD_OVRRUN)
+ flg = TTY_OVERRUN;
- if( rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) )
- goto handle_error;
+#ifdef SUPPORT_SYSRQ
+ sport->port.sysrq = 0;
+#endif
+ }
- error_return:
tty_insert_flip_char(tty, rx, flg);
-
- ignore_char:
- rx = readl(sport->port.membase + URXD0);
- } while(rx & URXD_CHARRDY);
+ }
out:
spin_unlock_irqrestore(&sport->port.lock,flags);
tty_flip_buffer_push(tty);
return IRQ_HANDLED;
-
-handle_error:
- if (rx & URXD_PRERR)
- sport->port.icount.parity++;
- else if (rx & URXD_FRMERR)
- sport->port.icount.frame++;
- if (rx & URXD_OVRRUN)
- sport->port.icount.overrun++;
-
- if (rx & sport->port.ignore_status_mask) {
- if (++ignored > 100)
- goto out;
- goto ignore_char;
- }
-
- rx &= sport->port.read_status_mask;
-
- if (rx & URXD_PRERR)
- flg = TTY_PARITY;
- else if (rx & URXD_FRMERR)
- flg = TTY_FRAME;
- if (rx & URXD_OVRRUN)
- flg = TTY_OVERRUN;
-
-#ifdef SUPPORT_SYSRQ
- sport->port.sysrq = 0;
-#endif
- goto error_return;
}
/*
writel(USR1_RTSD, sport->port.membase + USR1);
temp = readl(sport->port.membase + UCR1);
- temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
+ temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
writel(temp, sport->port.membase + UCR1);
temp = readl(sport->port.membase + UCR2);
*/
static void imx_release_port(struct uart_port *port)
{
- struct imx_port *sport = (struct imx_port *)port;
+ struct platform_device *pdev = to_platform_device(port->dev);
+ struct resource *mmres;
- release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(mmres->start, mmres->end - mmres->start + 1);
}
/*
*/
static int imx_request_port(struct uart_port *port)
{
- struct imx_port *sport = (struct imx_port *)port;
+ struct platform_device *pdev = to_platform_device(port->dev);
+ struct resource *mmres;
+ void *ret;
+
+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mmres)
+ return -ENODEV;
+
+ ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
+ "imx-uart");
- return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
- "imx-uart") != NULL ? 0 : -EBUSY;
+ return ret ? 0 : -EBUSY;
}
/*
.type = PORT_IMX,
.iotype = UPIO_MEM,
.membase = (void *)IMX_UART1_BASE,
- .mapbase = IMX_UART1_BASE, /* FIXME */
+ .mapbase = 0x00206000,
.irq = UART1_MINT_RX,
.uartclk = 16000000,
.fifosize = 32,
.type = PORT_IMX,
.iotype = UPIO_MEM,
.membase = (void *)IMX_UART2_BASE,
- .mapbase = IMX_UART2_BASE, /* FIXME */
+ .mapbase = 0x00207000,
.irq = UART2_MINT_RX,
.uartclk = 16000000,
.fifosize = 32,
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
-#include <asm/semaphore.h>
#include <asm/delay.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
| UPF_FIXED_PORT;
port->dev = &ofdev->dev;
- port->custom_divisor = *clk / (16 * (*spd));
+ /* If current-speed was set, then try not to change it. */
+ if (spd)
+ port->custom_divisor = *clk / (16 * (*spd));
return 0;
}
*/
tty_dev = tty_register_device(drv->tty_driver, port->line, port->dev);
if (likely(!IS_ERR(tty_dev))) {
- device_can_wakeup(tty_dev) = 1;
+ device_init_wakeup(tty_dev, 1);
device_set_wakeup_enable(tty_dev, 0);
} else
printk(KERN_ERR "Cannot register tty device on line %d\n",
}
sci_out(port, SCFCR, fcr_val);
}
-
#elif defined(CONFIG_CPU_SH3)
/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
sci_out(port, SCFCR, fcr_val);
}
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
+{
+ /* Nothing to do here.. */
+ sci_out(port, SCFCR, 0);
+}
#else
/* For SH7750 */
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
-/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
- *
- * linux/drivers/serial/sh-sci.h
- *
- * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
- * Copyright (C) 1999, 2000 Niibe Yutaka
- * Copyright (C) 2000 Greg Banks
- * Copyright (C) 2002, 2003 Paul Mundt
- * Modified to support multiple serial ports. Stuart Menefy (May 2000).
- * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
- * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
- * Removed SH7300 support (Jul 2007).
- * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
- */
#include <linux/serial_core.h>
#include <asm/io.h>
-
#include <asm/gpio.h>
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
# define SCSPTR0 SCPDR0
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+# define SCSPTR0 0xa4050160
+# define SCSPTR1 0xa405013e
+# define SCSPTR2 0xa4050160
+# define SCSPTR3 0xa405013e
+# define SCSPTR4 0xa4050128
+# define SCSPTR5 0xa4050128
+# define SCIF_ORER 0x0001 /* overrun error bit */
+# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
h8_sci_offset, h8_sci_size) \
CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+ #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
+ CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
+ #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
+ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#else
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
SCIF_FNS(SCxTDR, 0x20, 8)
SCIF_FNS(SCxRDR, 0x24, 8)
SCIF_FNS(SCLSR, 0x24, 16)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
+SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
+SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
+SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
+SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
+SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
+SCIF_FNS(SCTDSR, 0x0c, 8)
+SCIF_FNS(SCFER, 0x10, 16)
+SCIF_FNS(SCFCR, 0x18, 16)
+SCIF_FNS(SCFDR, 0x1c, 16)
+SCIF_FNS(SCLSR, 0x24, 16)
#else
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
/* name off sz off sz off sz off sz off sz*/
return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
return 1;
}
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+static inline int sci_rxd_in(struct uart_port *port)
+{
+ if (port->mapbase == 0xffe00000)
+ return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
+ if (port->mapbase == 0xffe10000)
+ return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
+ if (port->mapbase == 0xffe20000)
+ return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
+ if (port->mapbase == 0xa4e30000)
+ return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
+ if (port->mapbase == 0xa4e40000)
+ return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
+ if (port->mapbase == 0xa4e50000)
+ return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
+ return 1;
+}
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
static inline int sci_rxd_in(struct uart_port *port)
{
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
+#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(16*bps)-1)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
#elif defined(CONFIG_SUPERH64)
/* Get the UCC number (device ID) */
/* UCCs are numbered 1-7 */
- iprop = of_get_property(np, "device-id", NULL);
- if (!iprop || (*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
- dev_err(&ofdev->dev,
- "missing or invalid UCC specified in device tree\n");
+ iprop = of_get_property(np, "cell-index", NULL);
+ if (!iprop) {
+ iprop = of_get_property(np, "device-id", NULL);
+ if (!iprop) {
+ dev_err(&ofdev->dev, "UCC is unspecified in "
+ "device tree\n");
+ return -EINVAL;
+ }
+ }
+
+ if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
+ dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
kfree(qe_port);
return -ENODEV;
}
-menu "Userspace I/O"
- depends on !S390
-
-config UIO
+menuconfig UIO
tristate "Userspace I/O drivers"
+ depends on !S390
default n
help
Enable this to allow the userspace driver core code to be
If you don't know what to do here, say N.
+if UIO
+
config UIO_CIF
tristate "generic Hilscher CIF Card driver"
depends on UIO && PCI
To compile this driver as a module, choose M here: the module
will be called uio_cif.
-endmenu
+config UIO_SMX
+ tristate "SMX cryptengine UIO interface"
+ depends on UIO
+ default n
+ help
+ Userspace IO interface to the Cryptography engine found on the
+ Nias Digital SMX boards. These will be available from Q4 2008
+ from http://www.niasdigital.com. The userspace part of this
+ driver will be released under the GPL at the same time as the
+ hardware and will be able to be downloaded from the same site.
+
+ If you compile this as a module, it will be called uio_smx.
+
+endif
obj-$(CONFIG_UIO) += uio.o
obj-$(CONFIG_UIO_CIF) += uio_cif.o
+obj-$(CONFIG_UIO_SMX) += uio_smx.o
if (!idev)
return -ENODEV;
+ if (!try_module_get(idev->owner))
+ return -ENODEV;
+
listener = kmalloc(sizeof(*listener), GFP_KERNEL);
- if (!listener)
- return -ENOMEM;
+ if (!listener) {
+ ret = -ENOMEM;
+ goto err_alloc_listener;
+ }
listener->dev = idev;
listener->event_count = atomic_read(&idev->event);
filep->private_data = listener;
if (idev->info->open) {
- if (!try_module_get(idev->owner))
- return -ENODEV;
ret = idev->info->open(idev->info, inode);
- module_put(idev->owner);
+ if (ret)
+ goto err_infoopen;
}
- if (ret)
- kfree(listener);
+ return 0;
+
+err_infoopen:
+
+ kfree(listener);
+err_alloc_listener:
+
+ module_put(idev->owner);
return ret;
}
struct uio_listener *listener = filep->private_data;
struct uio_device *idev = listener->dev;
- if (idev->info->release) {
- if (!try_module_get(idev->owner))
- return -ENODEV;
+ if (idev->info->release)
ret = idev->info->release(idev->info, inode);
- module_put(idev->owner);
- }
+
+ module_put(idev->owner);
+
if (filep->f_flags & FASYNC)
ret = uio_fasync(-1, filep, 0);
kfree(listener);
return -EINVAL;
if (idev->info->mmap) {
- if (!try_module_get(idev->owner))
- return -ENODEV;
ret = idev->info->mmap(idev->info, vma);
- module_put(idev->owner);
return ret;
}
#include <asm/io.h>
-#ifndef PCI_DEVICE_ID_PLX_9030
-#define PCI_DEVICE_ID_PLX_9030 0x9030
-#endif
-
#define PLX9030_INTCSR 0x4C
#define INTSCR_INT1_ENABLE 0x01
#define INTSCR_INT1_STATUS 0x04
kfree (info);
}
-static struct pci_device_id hilscher_pci_ids[] = {
+static struct pci_device_id hilscher_pci_ids[] __devinitdata = {
{
.vendor = PCI_VENDOR_ID_PLX,
.device = PCI_DEVICE_ID_PLX_9030,
--- /dev/null
+/*
+ * UIO SMX Cryptengine driver.
+ *
+ * (C) 2008 Nias Digital P/L <bn@niasdigital.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/uio_driver.h>
+#include <linux/io.h>
+
+#define DRV_NAME "smx-ce"
+#define DRV_VERSION "0.03"
+
+#define SMX_CSR 0x00000000
+#define SMX_EnD 0x00000001
+#define SMX_RUN 0x00000002
+#define SMX_DRDY 0x00000004
+#define SMX_ERR 0x00000008
+
+static irqreturn_t smx_handler(int irq, struct uio_info *dev_info)
+{
+ void __iomem *csr = dev_info->mem[0].internal_addr + SMX_CSR;
+
+ u32 status = ioread32(csr);
+
+ if (!(status & SMX_DRDY))
+ return IRQ_NONE;
+
+ /* Disable interrupt */
+ iowrite32(status & ~SMX_DRDY, csr);
+ return IRQ_HANDLED;
+}
+
+static int __devinit smx_ce_probe(struct platform_device *dev)
+{
+
+ int ret = -ENODEV;
+ struct uio_info *info;
+ struct resource *regs;
+
+ info = kzalloc(sizeof(struct uio_info), GFP_KERNEL);
+ if (!info)
+ return -ENOMEM;
+
+ regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ if (!regs) {
+ dev_err(&dev->dev, "No memory resource specified\n");
+ goto out_free;
+ }
+
+ info->mem[0].addr = regs->start;
+ if (!info->mem[0].addr) {
+ dev_err(&dev->dev, "Invalid memory resource\n");
+ goto out_free;
+ }
+
+ info->mem[0].size = regs->end - regs->start + 1;
+ info->mem[0].internal_addr = ioremap(regs->start, info->mem[0].size);
+
+ if (!info->mem[0].internal_addr) {
+ dev_err(&dev->dev, "Can't remap memory address range\n");
+ goto out_free;
+ }
+
+ info->mem[0].memtype = UIO_MEM_PHYS;
+
+ info->name = "smx-ce";
+ info->version = "0.03";
+
+ info->irq = platform_get_irq(dev, 0);
+ if (info->irq < 0) {
+ ret = info->irq;
+ dev_err(&dev->dev, "No (or invalid) IRQ resource specified\n");
+ goto out_unmap;
+ }
+
+ info->irq_flags = IRQF_SHARED;
+ info->handler = smx_handler;
+
+ platform_set_drvdata(dev, info);
+
+ ret = uio_register_device(&dev->dev, info);
+
+ if (ret)
+ goto out_unmap;
+
+ return 0;
+
+out_unmap:
+ iounmap(info->mem[0].internal_addr);
+out_free:
+ kfree(info);
+
+ return ret;
+}
+
+static int __devexit smx_ce_remove(struct platform_device *dev)
+{
+ struct uio_info *info = platform_get_drvdata(dev);
+
+ uio_unregister_device(info);
+ platform_set_drvdata(dev, NULL);
+ iounmap(info->mem[0].internal_addr);
+
+ kfree(info);
+
+ return 0;
+}
+
+static struct platform_driver smx_ce_driver = {
+ .probe = smx_ce_probe,
+ .remove = __devexit_p(smx_ce_remove),
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init smx_ce_init_module(void)
+{
+ return platform_driver_register(&smx_ce_driver);
+}
+module_init(smx_ce_init_module);
+
+static void __exit smx_ce_exit_module(void)
+{
+ platform_driver_unregister(&smx_ce_driver);
+}
+module_exit(smx_ce_exit_module);
+
+MODULE_LICENSE("GPL v2");
+MODULE_VERSION(DRV_VERSION);
+MODULE_AUTHOR("Ben Nizette <bn@niasdigital.com>");
#ifndef _USBATM_H_
#define _USBATM_H_
-#include <asm/semaphore.h>
#include <linux/atm.h>
#include <linux/atmdev.h>
#include <linux/completion.h>
#include <linux/mutex.h>
#include <linux/freezer.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <asm/byteorder.h>
config USB_GADGET_ATMEL_USBA
boolean "Atmel USBA"
select USB_GADGET_DUALSPEED
- depends on AVR32
+ depends on AVR32 || ARCH_AT91CAP9
help
USBA is the integrated high-speed USB Device controller on
- the AT32AP700x processors from Atmel.
+ the AT32AP700x and AT91CAP9 processors from Atmel.
config USB_ATMEL_USBA
tristate
#include <linux/platform_device.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
+#include <linux/usb/atmel_usba_udc.h>
#include <linux/delay.h>
#include <asm/gpio.h>
static struct usba_udc the_udc;
+static struct usba_ep *usba_ep;
#ifdef CONFIG_USB_GADGET_DEBUG_FS
#include <linux/debugfs.h>
return 1;
}
-static void copy_to_fifo(void __iomem *fifo, const void *buf, int len)
+#if defined(CONFIG_AVR32)
+
+static void toggle_bias(int is_on)
{
- unsigned long tmp;
-
- DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
- for (; len > 0; len -= 4, buf += 4, fifo += 4) {
- tmp = *(unsigned long *)buf;
- if (len >= 4) {
- DBG(DBG_FIFO, " -> %08lx\n", tmp);
- __raw_writel(tmp, fifo);
- } else {
- do {
- DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
- __raw_writeb(tmp >> 24, fifo);
- fifo++;
- tmp <<= 8;
- } while (--len);
- break;
- }
- }
}
-static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
+#elif defined(CONFIG_ARCH_AT91)
+
+#include <asm/arch/at91_pmc.h>
+
+static void toggle_bias(int is_on)
{
- union {
- unsigned long *w;
- unsigned char *b;
- } p;
- unsigned long tmp;
-
- DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
- for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
- if (len >= 4) {
- tmp = __raw_readl(fifo);
- *p.w = tmp;
- DBG(DBG_FIFO, " -> %08lx\n", tmp);
- } else {
- do {
- tmp = __raw_readb(fifo);
- *p.b = tmp;
- DBG(DBG_FIFO, " -> %02lx\n", tmp);
- fifo++, p.b++;
- } while (--len);
- }
- }
+ unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
+
+ if (is_on)
+ at91_sys_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
+ else
+ at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
}
+#endif /* CONFIG_ARCH_AT91 */
+
static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
{
unsigned int transaction_len;
ep->ep.name, req, transaction_len,
req->last_transaction ? ", done" : "");
- copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
+ memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
req->req.actual += transaction_len;
}
bytecount = req->req.length - req->req.actual;
}
- copy_from_fifo(req->req.buf + req->req.actual,
+ memcpy_fromio(req->req.buf + req->req.actual,
ep->fifo, bytecount);
req->req.actual += bytecount;
.set_selfpowered = usba_udc_set_selfpowered,
};
-#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
-{ \
- .ep = { \
- .ops = &usba_ep_ops, \
- .name = nam, \
- .maxpacket = maxpkt, \
- }, \
- .udc = &the_udc, \
- .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
- .fifo_size = maxpkt, \
- .nr_banks = maxbk, \
- .index = idx, \
- .can_dma = dma, \
- .can_isoc = isoc, \
-}
-
-static struct usba_ep usba_ep[] = {
- EP("ep0", 0, 64, 1, 0, 0),
- EP("ep1in-bulk", 1, 512, 2, 1, 1),
- EP("ep2out-bulk", 2, 512, 2, 1, 1),
- EP("ep3in-int", 3, 64, 3, 1, 0),
- EP("ep4out-int", 4, 64, 3, 1, 0),
- EP("ep5in-iso", 5, 1024, 3, 1, 1),
- EP("ep6out-iso", 6, 1024, 3, 1, 1),
-};
-#undef EP
-
static struct usb_endpoint_descriptor usba_ep0_desc = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
static struct usba_udc the_udc = {
.gadget = {
.ops = &usba_udc_ops,
- .ep0 = &usba_ep[0].ep,
.ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
.is_dualspeed = 1,
.name = "atmel_usba_udc",
} else {
usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
usba_writel(udc, TST, USBA_TST_PKT_MODE);
- copy_to_fifo(ep->fifo, test_packet_buffer,
+ memcpy_toio(ep->fifo, test_packet_buffer,
sizeof(test_packet_buffer));
usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
dev_info(dev, "Entering Test_Packet mode...\n");
DBG(DBG_HW, "Packet length: %u\n", pkt_len);
if (pkt_len != sizeof(crq)) {
pr_warning("udc: Invalid packet length %u "
- "(expected %lu)\n", pkt_len, sizeof(crq));
+ "(expected %zu)\n", pkt_len, sizeof(crq));
set_protocol_stall(udc, ep);
return;
}
DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
- copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
+ memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
/* Free up one bank in the FIFO so that we can
* generate or receive a reply right away. */
DBG(DBG_INT, "irq, status=%#08x\n", status);
if (status & USBA_DET_SUSPEND) {
+ toggle_bias(0);
usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
DBG(DBG_BUS, "Suspend detected\n");
if (udc->gadget.speed != USB_SPEED_UNKNOWN
}
if (status & USBA_WAKE_UP) {
+ toggle_bias(1);
usba_writel(udc, INT_CLR, USBA_WAKE_UP);
DBG(DBG_BUS, "Wake Up CPU detected\n");
}
vbus = gpio_get_value(udc->vbus_pin);
if (vbus != udc->vbus_prev) {
if (vbus) {
- usba_writel(udc, CTRL, USBA_EN_USBA);
+ toggle_bias(1);
+ usba_writel(udc, CTRL, USBA_ENABLE_MASK);
usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
} else {
udc->gadget.speed = USB_SPEED_UNKNOWN;
reset_all_endpoints(udc);
- usba_writel(udc, CTRL, 0);
+ toggle_bias(0);
+ usba_writel(udc, CTRL, USBA_DISABLE_MASK);
spin_unlock(&udc->lock);
udc->driver->disconnect(&udc->gadget);
spin_lock(&udc->lock);
/* If Vbus is present, enable the controller and wait for reset */
spin_lock_irqsave(&udc->lock, flags);
if (vbus_is_present(udc) && udc->vbus_prev == 0) {
- usba_writel(udc, CTRL, USBA_EN_USBA);
+ toggle_bias(1);
+ usba_writel(udc, CTRL, USBA_ENABLE_MASK);
usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
}
spin_unlock_irqrestore(&udc->lock, flags);
spin_unlock_irqrestore(&udc->lock, flags);
/* This will also disable the DP pullup */
- usba_writel(udc, CTRL, 0);
+ toggle_bias(0);
+ usba_writel(udc, CTRL, USBA_DISABLE_MASK);
driver->unbind(&udc->gadget);
udc->gadget.dev.driver = NULL;
regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
- if (!regs || !fifo)
+ if (!regs || !fifo || !pdata)
return -ENXIO;
irq = platform_get_irq(pdev, 0);
/* Make sure we start from a clean slate */
clk_enable(pclk);
- usba_writel(udc, CTRL, 0);
+ toggle_bias(0);
+ usba_writel(udc, CTRL, USBA_DISABLE_MASK);
clk_disable(pclk);
+ usba_ep = kmalloc(sizeof(struct usba_ep) * pdata->num_ep,
+ GFP_KERNEL);
+ if (!usba_ep)
+ goto err_alloc_ep;
+
+ the_udc.gadget.ep0 = &usba_ep[0].ep;
+
INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
- for (i = 1; i < ARRAY_SIZE(usba_ep); i++) {
+ usba_ep[0].ep.ops = &usba_ep_ops;
+ usba_ep[0].ep.name = pdata->ep[0].name;
+ usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
+ usba_ep[0].udc = &the_udc;
+ INIT_LIST_HEAD(&usba_ep[0].queue);
+ usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
+ usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
+ usba_ep[0].index = pdata->ep[0].index;
+ usba_ep[0].can_dma = pdata->ep[0].can_dma;
+ usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
+
+ for (i = 1; i < pdata->num_ep; i++) {
struct usba_ep *ep = &usba_ep[i];
ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+ ep->ep.ops = &usba_ep_ops;
+ ep->ep.name = pdata->ep[i].name;
+ ep->ep.maxpacket = pdata->ep[i].fifo_size;
+ ep->udc = &the_udc;
+ INIT_LIST_HEAD(&ep->queue);
+ ep->fifo_size = pdata->ep[i].fifo_size;
+ ep->nr_banks = pdata->ep[i].nr_banks;
+ ep->index = pdata->ep[i].index;
+ ep->can_dma = pdata->ep[i].can_dma;
+ ep->can_isoc = pdata->ep[i].can_isoc;
list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
}
goto err_device_add;
}
- if (pdata && pdata->vbus_pin != GPIO_PIN_NONE) {
+ if (pdata->vbus_pin >= 0) {
if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
udc->vbus_pin = pdata->vbus_pin;
}
usba_init_debugfs(udc);
- for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
+ for (i = 1; i < pdata->num_ep; i++)
usba_ep_init_debugfs(udc, &usba_ep[i]);
return 0;
err_device_add:
free_irq(irq, udc);
err_request_irq:
+ kfree(usba_ep);
+err_alloc_ep:
iounmap(udc->fifo);
err_map_fifo:
iounmap(udc->regs);
{
struct usba_udc *udc;
int i;
+ struct usba_platform_data *pdata = pdev->dev.platform_data;
udc = platform_get_drvdata(pdev);
- for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
+ for (i = 1; i < pdata->num_ep; i++)
usba_ep_cleanup_debugfs(&usba_ep[i]);
usba_cleanup_debugfs(udc);
gpio_free(udc->vbus_pin);
free_irq(udc->irq, udc);
+ kfree(usba_ep);
iounmap(udc->fifo);
iounmap(udc->regs);
clk_put(udc->hclk);
#define USBA_EN_USBA (1 << 8)
#define USBA_DETACH (1 << 9)
#define USBA_REMOTE_WAKE_UP (1 << 10)
+#define USBA_PULLD_DIS (1 << 11)
+
+#if defined(CONFIG_AVR32)
+#define USBA_ENABLE_MASK USBA_EN_USBA
+#define USBA_DISABLE_MASK 0
+#elif defined(CONFIG_ARCH_AT91)
+#define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS)
+#define USBA_DISABLE_MASK USBA_DETACH
+#endif /* CONFIG_ARCH_AT91 */
/* Bitfields in FNUM */
#define USBA_MICRO_FRAME_NUM_OFFSET 0
#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
#endif
-#ifdef CONFIG_ARCH_ORION
+#ifdef CONFIG_PLAT_ORION
#include "ehci-orion.c"
#define PLATFORM_DRIVER ehci_orion_driver
#endif
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <asm/arch/orion.h>
+#include <linux/mbus.h>
+#include <asm/plat-orion/ehci-orion.h>
#define rdl(off) __raw_readl(hcd->regs + (off))
#define wrl(off, val) __raw_writel((val), hcd->regs + (off))
-#define USB_CAUSE 0x310
-#define USB_MASK 0x314
#define USB_CMD 0x140
#define USB_MODE 0x1a8
+#define USB_CAUSE 0x310
+#define USB_MASK 0x314
+#define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
+#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
#define USB_IPG 0x360
#define USB_PHY_PWR_CTRL 0x400
#define USB_PHY_TX_CTRL 0x420
.bus_resume = ehci_bus_resume,
};
+static void __init
+ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
+ struct mbus_dram_target_info *dram)
+{
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ wrl(USB_WINDOW_CTRL(i), 0);
+ wrl(USB_WINDOW_BASE(i), 0);
+ }
+
+ for (i = 0; i < dram->num_cs; i++) {
+ struct mbus_dram_window *cs = dram->cs + i;
+
+ wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) |
+ (cs->mbus_attr << 8) |
+ (dram->mbus_dram_target_id << 4) | 1);
+ wrl(USB_WINDOW_BASE(i), cs->base);
+ }
+}
+
static int __init ehci_orion_drv_probe(struct platform_device *pdev)
{
+ struct orion_ehci_data *pd = pdev->dev.platform_data;
struct resource *res;
struct usb_hcd *hcd;
struct ehci_hcd *ehci;
ehci->is_tdi_rh_tt = 1;
ehci->sbrn = 0x20;
+ /*
+ * (Re-)program MBUS remapping windows if we are asked to.
+ */
+ if (pd != NULL && pd->dram != NULL)
+ ehci_orion_conf_mbus_windows(hcd, pd->dram);
+
/*
* setup Orion USB controller
*/
#include <linux/timer.h>
#include <linux/workqueue.h>
#include <asm/atomic.h>
-#include <asm/semaphore.h>
#define APPLE_VENDOR_ID 0x05AC
#include <linux/serial.h>
#include <linux/ioctl.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <linux/usb.h>
#include <linux/usb/serial.h>
#include <linux/circ_buf.h>
#include <linux/mutex.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <linux/usb.h>
#include <linux/usb/serial.h>
#include <asm/irq.h>
#include <asm/div64.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/bitfield.h>
#include <asm/arch/pxafb.h>
#include <linux/init.h>
#include <linux/pnp.h>
#include <linux/fs.h>
+#include <linux/semaphore.h>
-#include <asm/semaphore.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <linux/fs.h>
#include <linux/sched.h>
#include <linux/idr.h>
-#include <asm/semaphore.h>
#include <net/9p/9p.h>
#include <net/9p/client.h>
config UDF_FS
tristate "UDF file system support"
+ select CRC_ITU_T
help
This is the new file system used on some CD-ROMs and DVDs. Say Y if
you intend to mount DVD discs or CDRW's written in packet mode, or
config BINFMT_AOUT
tristate "Kernel support for a.out and ECOFF binaries"
depends on ARCH_SUPPORTS_AOUT && \
- (X86_32 || ALPHA || ARM || M68K || SPARC32)
+ (X86_32 || ALPHA || ARM || M68K)
---help---
A.out (Assembler.OUTput) is a set of formats for libraries and
executables used in the earliest versions of UNIX. Linux used
struct bio_map_data {
struct bio_vec *iovecs;
- void __user *userptr;
+ int nr_sgvecs;
+ struct sg_iovec *sgvecs;
};
-static void bio_set_map_data(struct bio_map_data *bmd, struct bio *bio)
+static void bio_set_map_data(struct bio_map_data *bmd, struct bio *bio,
+ struct sg_iovec *iov, int iov_count)
{
memcpy(bmd->iovecs, bio->bi_io_vec, sizeof(struct bio_vec) * bio->bi_vcnt);
+ memcpy(bmd->sgvecs, iov, sizeof(struct sg_iovec) * iov_count);
+ bmd->nr_sgvecs = iov_count;
bio->bi_private = bmd;
}
static void bio_free_map_data(struct bio_map_data *bmd)
{
kfree(bmd->iovecs);
+ kfree(bmd->sgvecs);
kfree(bmd);
}
-static struct bio_map_data *bio_alloc_map_data(int nr_segs)
+static struct bio_map_data *bio_alloc_map_data(int nr_segs, int iov_count)
{
struct bio_map_data *bmd = kmalloc(sizeof(*bmd), GFP_KERNEL);
return NULL;
bmd->iovecs = kmalloc(sizeof(struct bio_vec) * nr_segs, GFP_KERNEL);
- if (bmd->iovecs)
+ if (!bmd->iovecs) {
+ kfree(bmd);
+ return NULL;
+ }
+
+ bmd->sgvecs = kmalloc(sizeof(struct sg_iovec) * iov_count, GFP_KERNEL);
+ if (bmd->sgvecs)
return bmd;
+ kfree(bmd->iovecs);
kfree(bmd);
return NULL;
}
+static int __bio_copy_iov(struct bio *bio, struct sg_iovec *iov, int iov_count,
+ int uncopy)
+{
+ int ret = 0, i;
+ struct bio_vec *bvec;
+ int iov_idx = 0;
+ unsigned int iov_off = 0;
+ int read = bio_data_dir(bio) == READ;
+
+ __bio_for_each_segment(bvec, bio, i, 0) {
+ char *bv_addr = page_address(bvec->bv_page);
+ unsigned int bv_len = bvec->bv_len;
+
+ while (bv_len && iov_idx < iov_count) {
+ unsigned int bytes;
+ char *iov_addr;
+
+ bytes = min_t(unsigned int,
+ iov[iov_idx].iov_len - iov_off, bv_len);
+ iov_addr = iov[iov_idx].iov_base + iov_off;
+
+ if (!ret) {
+ if (!read && !uncopy)
+ ret = copy_from_user(bv_addr, iov_addr,
+ bytes);
+ if (read && uncopy)
+ ret = copy_to_user(iov_addr, bv_addr,
+ bytes);
+
+ if (ret)
+ ret = -EFAULT;
+ }
+
+ bv_len -= bytes;
+ bv_addr += bytes;
+ iov_addr += bytes;
+ iov_off += bytes;
+
+ if (iov[iov_idx].iov_len == iov_off) {
+ iov_idx++;
+ iov_off = 0;
+ }
+ }
+
+ if (uncopy)
+ __free_page(bvec->bv_page);
+ }
+
+ return ret;
+}
+
/**
* bio_uncopy_user - finish previously mapped bio
* @bio: bio being terminated
int bio_uncopy_user(struct bio *bio)
{
struct bio_map_data *bmd = bio->bi_private;
- const int read = bio_data_dir(bio) == READ;
- struct bio_vec *bvec;
- int i, ret = 0;
+ int ret;
- __bio_for_each_segment(bvec, bio, i, 0) {
- char *addr = page_address(bvec->bv_page);
- unsigned int len = bmd->iovecs[i].bv_len;
+ ret = __bio_copy_iov(bio, bmd->sgvecs, bmd->nr_sgvecs, 1);
- if (read && !ret && copy_to_user(bmd->userptr, addr, len))
- ret = -EFAULT;
-
- __free_page(bvec->bv_page);
- bmd->userptr += len;
- }
bio_free_map_data(bmd);
bio_put(bio);
return ret;
}
/**
- * bio_copy_user - copy user data to bio
+ * bio_copy_user_iov - copy user data to bio
* @q: destination block queue
- * @uaddr: start of user address
- * @len: length in bytes
+ * @iov: the iovec.
+ * @iov_count: number of elements in the iovec
* @write_to_vm: bool indicating writing to pages or not
*
* Prepares and returns a bio for indirect user io, bouncing data
* to/from kernel pages as necessary. Must be paired with
* call bio_uncopy_user() on io completion.
*/
-struct bio *bio_copy_user(struct request_queue *q, unsigned long uaddr,
- unsigned int len, int write_to_vm)
+struct bio *bio_copy_user_iov(struct request_queue *q, struct sg_iovec *iov,
+ int iov_count, int write_to_vm)
{
- unsigned long end = (uaddr + len + PAGE_SIZE - 1) >> PAGE_SHIFT;
- unsigned long start = uaddr >> PAGE_SHIFT;
struct bio_map_data *bmd;
struct bio_vec *bvec;
struct page *page;
struct bio *bio;
int i, ret;
+ int nr_pages = 0;
+ unsigned int len = 0;
- bmd = bio_alloc_map_data(end - start);
+ for (i = 0; i < iov_count; i++) {
+ unsigned long uaddr;
+ unsigned long end;
+ unsigned long start;
+
+ uaddr = (unsigned long)iov[i].iov_base;
+ end = (uaddr + iov[i].iov_len + PAGE_SIZE - 1) >> PAGE_SHIFT;
+ start = uaddr >> PAGE_SHIFT;
+
+ nr_pages += end - start;
+ len += iov[i].iov_len;
+ }
+
+ bmd = bio_alloc_map_data(nr_pages, iov_count);
if (!bmd)
return ERR_PTR(-ENOMEM);
- bmd->userptr = (void __user *) uaddr;
-
ret = -ENOMEM;
- bio = bio_alloc(GFP_KERNEL, end - start);
+ bio = bio_alloc(GFP_KERNEL, nr_pages);
if (!bio)
goto out_bmd;
* success
*/
if (!write_to_vm) {
- char __user *p = (char __user *) uaddr;
-
- /*
- * for a write, copy in data to kernel pages
- */
- ret = -EFAULT;
- bio_for_each_segment(bvec, bio, i) {
- char *addr = page_address(bvec->bv_page);
-
- if (copy_from_user(addr, p, bvec->bv_len))
- goto cleanup;
- p += bvec->bv_len;
- }
+ ret = __bio_copy_iov(bio, iov, iov_count, 0);
+ if (ret)
+ goto cleanup;
}
- bio_set_map_data(bmd, bio);
+ bio_set_map_data(bmd, bio, iov, iov_count);
return bio;
cleanup:
bio_for_each_segment(bvec, bio, i)
return ERR_PTR(ret);
}
+/**
+ * bio_copy_user - copy user data to bio
+ * @q: destination block queue
+ * @uaddr: start of user address
+ * @len: length in bytes
+ * @write_to_vm: bool indicating writing to pages or not
+ *
+ * Prepares and returns a bio for indirect user io, bouncing data
+ * to/from kernel pages as necessary. Must be paired with
+ * call bio_uncopy_user() on io completion.
+ */
+struct bio *bio_copy_user(struct request_queue *q, unsigned long uaddr,
+ unsigned int len, int write_to_vm)
+{
+ struct sg_iovec iov;
+
+ iov.iov_base = (void __user *)uaddr;
+ iov.iov_len = len;
+
+ return bio_copy_user_iov(q, &iov, 1, write_to_vm);
+}
+
static struct bio *__bio_map_user_iov(struct request_queue *q,
struct block_device *bdev,
struct sg_iovec *iov, int iov_count,
#include <linux/buffer_head.h>
#include <linux/vfs.h>
#include <linux/mutex.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
midcomms.o \
netlink.o \
lowcomms.o \
+ plock.o \
rcom.o \
recover.o \
recoverd.o \
};
static ssize_t cluster_set(struct cluster *cl, unsigned int *cl_field,
- unsigned int *info_field, int check_zero,
+ int *info_field, int check_zero,
const char *buf, size_t len)
{
unsigned int x;
struct list_head list; /* space->members */
int nodeid;
int weight;
+ int new;
};
static struct configfs_group_operations clusters_ops = {
config_item_init_type_name(&nd->item, name, &node_type);
nd->nodeid = -1;
nd->weight = 1; /* default weight of 1 if none is set */
+ nd->new = 1; /* set to 0 once it's been read by dlm_nodeid_list() */
mutex_lock(&sp->members_lock);
list_add(&nd->list, &sp->members);
}
/* caller must free mem */
-int dlm_nodeid_list(char *lsname, int **ids_out)
+int dlm_nodeid_list(char *lsname, int **ids_out, int *ids_count_out,
+ int **new_out, int *new_count_out)
{
struct space *sp;
struct node *nd;
- int i = 0, rv = 0;
- int *ids;
+ int i = 0, rv = 0, ids_count = 0, new_count = 0;
+ int *ids, *new;
sp = get_space(lsname);
if (!sp)
mutex_lock(&sp->members_lock);
if (!sp->members_count) {
- rv = 0;
+ rv = -EINVAL;
+ printk(KERN_ERR "dlm: zero members_count\n");
goto out;
}
- ids = kcalloc(sp->members_count, sizeof(int), GFP_KERNEL);
+ ids_count = sp->members_count;
+
+ ids = kcalloc(ids_count, sizeof(int), GFP_KERNEL);
if (!ids) {
rv = -ENOMEM;
goto out;
}
- rv = sp->members_count;
- list_for_each_entry(nd, &sp->members, list)
+ list_for_each_entry(nd, &sp->members, list) {
ids[i++] = nd->nodeid;
+ if (nd->new)
+ new_count++;
+ }
+
+ if (ids_count != i)
+ printk(KERN_ERR "dlm: bad nodeid count %d %d\n", ids_count, i);
+
+ if (!new_count)
+ goto out_ids;
+
+ new = kcalloc(new_count, sizeof(int), GFP_KERNEL);
+ if (!new) {
+ kfree(ids);
+ rv = -ENOMEM;
+ goto out;
+ }
- if (rv != i)
- printk("bad nodeid count %d %d\n", rv, i);
+ i = 0;
+ list_for_each_entry(nd, &sp->members, list) {
+ if (nd->new) {
+ new[i++] = nd->nodeid;
+ nd->new = 0;
+ }
+ }
+ *new_count_out = new_count;
+ *new_out = new;
+ out_ids:
+ *ids_count_out = ids_count;
*ids_out = ids;
out:
mutex_unlock(&sp->members_lock);
int dlm_config_init(void);
void dlm_config_exit(void);
int dlm_node_weight(char *lsname, int nodeid);
-int dlm_nodeid_list(char *lsname, int **ids_out);
+int dlm_nodeid_list(char *lsname, int **ids_out, int *ids_count_out,
+ int **new_out, int *new_count_out);
int dlm_nodeid_to_addr(int nodeid, struct sockaddr_storage *addr);
int dlm_addr_to_nodeid(struct sockaddr_storage *addr, int *nodeid);
int dlm_our_nodeid(void);
#include <linux/jhash.h>
#include <linux/miscdevice.h>
#include <linux/mutex.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#include <linux/dlm.h>
#include "config.h"
-#define DLM_LOCKSPACE_LEN 64
-
/* Size of the temp buffer midcomms allocates on the stack.
We try to make this large enough so most messages fit.
FIXME: should sctp make this unnecessary? */
struct dlm_recover {
struct list_head list;
- int *nodeids;
+ int *nodeids; /* nodeids of all members */
int node_count;
+ int *new; /* nodeids of new members */
+ int new_count;
uint64_t seq;
};
int dlm_netlink_init(void);
void dlm_netlink_exit(void);
void dlm_timeout_warn(struct dlm_lkb *lkb);
+int dlm_plock_init(void);
+void dlm_plock_exit(void);
#ifdef CONFIG_DLM_DEBUG
int dlm_register_debugfs(void);
lkb->lkb_grmode, lkb->lkb_wait_type, lkb->lkb_ast_type);
}
-void dlm_print_rsb(struct dlm_rsb *r)
+static void dlm_print_rsb(struct dlm_rsb *r)
{
printk(KERN_ERR "rsb: nodeid %d flags %lx first %x rlc %d name %s\n",
r->res_nodeid, r->res_flags, r->res_first_lkid,
list_del_init(&lkb->lkb_rsb_lookup);
r->res_first_lkid = lkb->lkb_id;
_request_lock(r, lkb);
- } else
- r->res_nodeid = -1;
+ }
break;
default:
#ifndef __LOCK_DOT_H__
#define __LOCK_DOT_H__
-void dlm_print_rsb(struct dlm_rsb *r);
void dlm_dump_rsb(struct dlm_rsb *r);
void dlm_print_lkb(struct dlm_lkb *lkb);
void dlm_receive_message_saved(struct dlm_ls *ls, struct dlm_message *ms);
if (error)
goto out_user;
+ error = dlm_plock_init();
+ if (error)
+ goto out_netlink;
+
printk("DLM (built %s %s) installed\n", __DATE__, __TIME__);
return 0;
+ out_netlink:
+ dlm_netlink_exit();
out_user:
dlm_user_exit();
out_debug:
static void __exit exit_dlm(void)
{
+ dlm_plock_exit();
dlm_netlink_exit();
dlm_user_exit();
dlm_config_exit();
}
}
+ /* Add an entry to ls_nodes_gone for members that were removed and
+ then added again, so that previous state for these nodes will be
+ cleared during recovery. */
+
+ for (i = 0; i < rv->new_count; i++) {
+ if (!dlm_is_member(ls, rv->new[i]))
+ continue;
+ log_debug(ls, "new nodeid %d is a re-added member", rv->new[i]);
+
+ memb = kzalloc(sizeof(struct dlm_member), GFP_KERNEL);
+ if (!memb)
+ return -ENOMEM;
+ memb->nodeid = rv->new[i];
+ list_add_tail(&memb->list, &ls->ls_nodes_gone);
+ neg++;
+ }
+
/* add new members to ls_nodes */
for (i = 0; i < rv->node_count; i++) {
int dlm_ls_start(struct dlm_ls *ls)
{
struct dlm_recover *rv = NULL, *rv_old;
- int *ids = NULL;
- int error, count;
+ int *ids = NULL, *new = NULL;
+ int error, ids_count = 0, new_count = 0;
rv = kzalloc(sizeof(struct dlm_recover), GFP_KERNEL);
if (!rv)
return -ENOMEM;
- error = count = dlm_nodeid_list(ls->ls_name, &ids);
- if (error <= 0)
+ error = dlm_nodeid_list(ls->ls_name, &ids, &ids_count,
+ &new, &new_count);
+ if (error < 0)
goto fail;
spin_lock(&ls->ls_recover_lock);
}
rv->nodeids = ids;
- rv->node_count = count;
+ rv->node_count = ids_count;
+ rv->new = new;
+ rv->new_count = new_count;
rv->seq = ++ls->ls_recover_seq;
rv_old = ls->ls_recover_args;
ls->ls_recover_args = rv;
spin_unlock(&ls->ls_recover_lock);
if (rv_old) {
+ log_error(ls, "unused recovery %llx %d",
+ (unsigned long long)rv_old->seq, rv_old->node_count);
kfree(rv_old->nodeids);
+ kfree(rv_old->new);
kfree(rv_old);
}
fail:
kfree(rv);
kfree(ids);
+ kfree(new);
return error;
}
/*
- * Copyright (C) 2005 Red Hat, Inc. All rights reserved.
+ * Copyright (C) 2005-2008 Red Hat, Inc. All rights reserved.
*
* This copyrighted material is made available to anyone wishing to use,
* modify, copy, or redistribute it subject to the terms and conditions
* of the GNU General Public License version 2.
*/
+#include <linux/fs.h>
#include <linux/miscdevice.h>
-#include <linux/lock_dlm_plock.h>
#include <linux/poll.h>
+#include <linux/dlm.h>
+#include <linux/dlm_plock.h>
-#include "lock_dlm.h"
-
+#include "dlm_internal.h"
+#include "lockspace.h"
static spinlock_t ops_lock;
static struct list_head send_list;
struct plock_op {
struct list_head list;
int done;
- struct gdlm_plock_info info;
+ struct dlm_plock_info info;
};
struct plock_xop {
};
-static inline void set_version(struct gdlm_plock_info *info)
+static inline void set_version(struct dlm_plock_info *info)
{
- info->version[0] = GDLM_PLOCK_VERSION_MAJOR;
- info->version[1] = GDLM_PLOCK_VERSION_MINOR;
- info->version[2] = GDLM_PLOCK_VERSION_PATCH;
+ info->version[0] = DLM_PLOCK_VERSION_MAJOR;
+ info->version[1] = DLM_PLOCK_VERSION_MINOR;
+ info->version[2] = DLM_PLOCK_VERSION_PATCH;
}
-static int check_version(struct gdlm_plock_info *info)
+static int check_version(struct dlm_plock_info *info)
{
- if ((GDLM_PLOCK_VERSION_MAJOR != info->version[0]) ||
- (GDLM_PLOCK_VERSION_MINOR < info->version[1])) {
- log_error("plock device version mismatch: "
+ if ((DLM_PLOCK_VERSION_MAJOR != info->version[0]) ||
+ (DLM_PLOCK_VERSION_MINOR < info->version[1])) {
+ log_print("plock device version mismatch: "
"kernel (%u.%u.%u), user (%u.%u.%u)",
- GDLM_PLOCK_VERSION_MAJOR,
- GDLM_PLOCK_VERSION_MINOR,
- GDLM_PLOCK_VERSION_PATCH,
+ DLM_PLOCK_VERSION_MAJOR,
+ DLM_PLOCK_VERSION_MINOR,
+ DLM_PLOCK_VERSION_PATCH,
info->version[0],
info->version[1],
info->version[2]);
wake_up(&send_wq);
}
-int gdlm_plock(void *lockspace, struct lm_lockname *name,
- struct file *file, int cmd, struct file_lock *fl)
+int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file,
+ int cmd, struct file_lock *fl)
{
- struct gdlm_ls *ls = lockspace;
+ struct dlm_ls *ls;
struct plock_op *op;
struct plock_xop *xop;
int rv;
+ ls = dlm_find_lockspace_local(lockspace);
+ if (!ls)
+ return -EINVAL;
+
xop = kzalloc(sizeof(*xop), GFP_KERNEL);
- if (!xop)
- return -ENOMEM;
+ if (!xop) {
+ rv = -ENOMEM;
+ goto out;
+ }
op = &xop->xop;
- op->info.optype = GDLM_PLOCK_OP_LOCK;
+ op->info.optype = DLM_PLOCK_OP_LOCK;
op->info.pid = fl->fl_pid;
op->info.ex = (fl->fl_type == F_WRLCK);
op->info.wait = IS_SETLKW(cmd);
- op->info.fsid = ls->id;
- op->info.number = name->ln_number;
+ op->info.fsid = ls->ls_global_id;
+ op->info.number = number;
op->info.start = fl->fl_start;
op->info.end = fl->fl_end;
if (fl->fl_lmops && fl->fl_lmops->fl_grant) {
if (xop->callback == NULL)
wait_event(recv_wq, (op->done != 0));
- else
- return -EINPROGRESS;
+ else {
+ rv = -EINPROGRESS;
+ goto out;
+ }
spin_lock(&ops_lock);
if (!list_empty(&op->list)) {
- printk(KERN_INFO "plock op on list\n");
+ log_error(ls, "dlm_posix_lock: op on list %llx",
+ (unsigned long long)number);
list_del(&op->list);
}
spin_unlock(&ops_lock);
if (!rv) {
if (posix_lock_file_wait(file, fl) < 0)
- log_error("gdlm_plock: vfs lock error %x,%llx",
- name->ln_type,
- (unsigned long long)name->ln_number);
+ log_error(ls, "dlm_posix_lock: vfs lock error %llx",
+ (unsigned long long)number);
}
kfree(xop);
+out:
+ dlm_put_lockspace(ls);
return rv;
}
+EXPORT_SYMBOL_GPL(dlm_posix_lock);
/* Returns failure iff a succesful lock operation should be canceled */
-static int gdlm_plock_callback(struct plock_op *op)
+static int dlm_plock_callback(struct plock_op *op)
{
struct file *file;
struct file_lock *fl;
spin_lock(&ops_lock);
if (!list_empty(&op->list)) {
- printk(KERN_INFO "plock op on list\n");
+ log_print("dlm_plock_callback: op on list %llx",
+ (unsigned long long)op->info.number);
list_del(&op->list);
}
spin_unlock(&ops_lock);
* This can only happen in the case of kmalloc() failure.
* The filesystem's own lock is the authoritative lock,
* so a failure to get the lock locally is not a disaster.
- * As long as GFS cannot reliably cancel locks (especially
+ * As long as the fs cannot reliably cancel locks (especially
* in a low-memory situation), we're better off ignoring
* this failure than trying to recover.
*/
- log_error("gdlm_plock: vfs lock error file %p fl %p",
- file, fl);
+ log_print("dlm_plock_callback: vfs lock error %llx file %p fl %p",
+ (unsigned long long)op->info.number, file, fl);
}
rv = notify(flc, NULL, 0);
if (rv) {
/* XXX: We need to cancel the fs lock here: */
- printk("gfs2 lock granted after lock request failed;"
- " dangling lock!\n");
+ log_print("dlm_plock_callback: lock granted after lock request "
+ "failed; dangling lock!\n");
goto out;
}
return rv;
}
-int gdlm_punlock(void *lockspace, struct lm_lockname *name,
- struct file *file, struct file_lock *fl)
+int dlm_posix_unlock(dlm_lockspace_t *lockspace, u64 number, struct file *file,
+ struct file_lock *fl)
{
- struct gdlm_ls *ls = lockspace;
+ struct dlm_ls *ls;
struct plock_op *op;
int rv;
+ ls = dlm_find_lockspace_local(lockspace);
+ if (!ls)
+ return -EINVAL;
+
op = kzalloc(sizeof(*op), GFP_KERNEL);
- if (!op)
- return -ENOMEM;
+ if (!op) {
+ rv = -ENOMEM;
+ goto out;
+ }
if (posix_lock_file_wait(file, fl) < 0)
- log_error("gdlm_punlock: vfs unlock error %x,%llx",
- name->ln_type, (unsigned long long)name->ln_number);
+ log_error(ls, "dlm_posix_unlock: vfs unlock error %llx",
+ (unsigned long long)number);
- op->info.optype = GDLM_PLOCK_OP_UNLOCK;
+ op->info.optype = DLM_PLOCK_OP_UNLOCK;
op->info.pid = fl->fl_pid;
- op->info.fsid = ls->id;
- op->info.number = name->ln_number;
+ op->info.fsid = ls->ls_global_id;
+ op->info.number = number;
op->info.start = fl->fl_start;
op->info.end = fl->fl_end;
if (fl->fl_lmops && fl->fl_lmops->fl_grant)
spin_lock(&ops_lock);
if (!list_empty(&op->list)) {
- printk(KERN_INFO "punlock op on list\n");
+ log_error(ls, "dlm_posix_unlock: op on list %llx",
+ (unsigned long long)number);
list_del(&op->list);
}
spin_unlock(&ops_lock);
rv = 0;
kfree(op);
+out:
+ dlm_put_lockspace(ls);
return rv;
}
+EXPORT_SYMBOL_GPL(dlm_posix_unlock);
-int gdlm_plock_get(void *lockspace, struct lm_lockname *name,
- struct file *file, struct file_lock *fl)
+int dlm_posix_get(dlm_lockspace_t *lockspace, u64 number, struct file *file,
+ struct file_lock *fl)
{
- struct gdlm_ls *ls = lockspace;
+ struct dlm_ls *ls;
struct plock_op *op;
int rv;
+ ls = dlm_find_lockspace_local(lockspace);
+ if (!ls)
+ return -EINVAL;
+
op = kzalloc(sizeof(*op), GFP_KERNEL);
- if (!op)
- return -ENOMEM;
+ if (!op) {
+ rv = -ENOMEM;
+ goto out;
+ }
- op->info.optype = GDLM_PLOCK_OP_GET;
+ op->info.optype = DLM_PLOCK_OP_GET;
op->info.pid = fl->fl_pid;
op->info.ex = (fl->fl_type == F_WRLCK);
- op->info.fsid = ls->id;
- op->info.number = name->ln_number;
+ op->info.fsid = ls->ls_global_id;
+ op->info.number = number;
op->info.start = fl->fl_start;
op->info.end = fl->fl_end;
if (fl->fl_lmops && fl->fl_lmops->fl_grant)
spin_lock(&ops_lock);
if (!list_empty(&op->list)) {
- printk(KERN_INFO "plock_get op on list\n");
+ log_error(ls, "dlm_posix_get: op on list %llx",
+ (unsigned long long)number);
list_del(&op->list);
}
spin_unlock(&ops_lock);
}
kfree(op);
+out:
+ dlm_put_lockspace(ls);
return rv;
}
+EXPORT_SYMBOL_GPL(dlm_posix_get);
/* a read copies out one plock request from the send list */
static ssize_t dev_read(struct file *file, char __user *u, size_t count,
loff_t *ppos)
{
- struct gdlm_plock_info info;
+ struct dlm_plock_info info;
struct plock_op *op = NULL;
if (count < sizeof(info))
static ssize_t dev_write(struct file *file, const char __user *u, size_t count,
loff_t *ppos)
{
- struct gdlm_plock_info info;
+ struct dlm_plock_info info;
struct plock_op *op;
int found = 0;
struct plock_xop *xop;
xop = (struct plock_xop *)op;
if (xop->callback)
- count = gdlm_plock_callback(op);
+ count = dlm_plock_callback(op);
else
wake_up(&recv_wq);
} else
- printk(KERN_INFO "gdlm dev_write no op %x %llx\n", info.fsid,
- (unsigned long long)info.number);
+ log_print("dev_write no op %x %llx", info.fsid,
+ (unsigned long long)info.number);
return count;
}
static struct miscdevice plock_dev_misc = {
.minor = MISC_DYNAMIC_MINOR,
- .name = GDLM_PLOCK_MISC_NAME,
+ .name = DLM_PLOCK_MISC_NAME,
.fops = &dev_fops
};
-int gdlm_plock_init(void)
+int dlm_plock_init(void)
{
int rv;
rv = misc_register(&plock_dev_misc);
if (rv)
- printk(KERN_INFO "gdlm_plock_init: misc_register failed %d",
- rv);
+ log_print("dlm_plock_init: misc_register failed %d", rv);
return rv;
}
-void gdlm_plock_exit(void)
+void dlm_plock_exit(void)
{
if (misc_deregister(&plock_dev_misc) < 0)
- printk(KERN_INFO "gdlm_plock_exit: misc_deregister failed");
+ log_print("dlm_plock_exit: misc_deregister failed");
}
if (rv) {
ls_recover(ls, rv);
kfree(rv->nodeids);
+ kfree(rv->new);
kfree(rv);
}
}
* it has too few free inodes left (min_inodes) or
* it has too few free blocks left (min_blocks) or
* it's already running too large debt (max_debt).
- * Parent's group is prefered, if it doesn't satisfy these
+ * Parent's group is preferred, if it doesn't satisfy these
* conditions we search cyclically through the rest. If none
* of the groups look good we just look for a group with more
* free inodes than average (starting at parent's group).
* @inode: owner
* @ind: descriptor of indirect block.
*
- * This function returns the prefered place for block allocation.
+ * This function returns the preferred place for block allocation.
* It is used when heuristic for sequential allocation fails.
* Rules are:
* + if there is a block to the left of our position - allocate near it.
}
/**
- * ext2_find_goal - find a prefered place for allocation.
+ * ext2_find_goal - find a preferred place for allocation.
* @inode: owner
* @block: block we want
* @partial: pointer to the last triple within a chain
#include <linux/time.h>
#include <linux/sched.h>
#include <linux/compat.h>
+#include <linux/mount.h>
#include <linux/smp_lock.h>
#include <asm/current.h>
#include <asm/uaccess.h>
struct ext2_inode_info *ei = EXT2_I(inode);
unsigned int flags;
unsigned short rsv_window_size;
+ int ret;
ext2_debug ("cmd = %u, arg = %lu\n", cmd, arg);
case EXT2_IOC_SETFLAGS: {
unsigned int oldflags;
- if (IS_RDONLY(inode))
- return -EROFS;
+ ret = mnt_want_write(filp->f_path.mnt);
+ if (ret)
+ return ret;
- if (!is_owner_or_cap(inode))
- return -EACCES;
+ if (!is_owner_or_cap(inode)) {
+ ret = -EACCES;
+ goto setflags_out;
+ }
- if (get_user(flags, (int __user *) arg))
- return -EFAULT;
+ if (get_user(flags, (int __user *) arg)) {
+ ret = -EFAULT;
+ goto setflags_out;
+ }
if (!S_ISDIR(inode->i_mode))
flags &= ~EXT2_DIRSYNC_FL;
/* Is it quota file? Do not allow user to mess with it */
if (IS_NOQUOTA(inode)) {
mutex_unlock(&inode->i_mutex);
- return -EPERM;
+ ret = -EPERM;
+ goto setflags_out;
}
oldflags = ei->i_flags;
if ((flags ^ oldflags) & (EXT2_APPEND_FL | EXT2_IMMUTABLE_FL)) {
if (!capable(CAP_LINUX_IMMUTABLE)) {
mutex_unlock(&inode->i_mutex);
- return -EPERM;
+ ret = -EPERM;
+ goto setflags_out;
}
}
ext2_set_inode_flags(inode);
inode->i_ctime = CURRENT_TIME_SEC;
mark_inode_dirty(inode);
- return 0;
+setflags_out:
+ mnt_drop_write(filp->f_path.mnt);
+ return ret;
}
case EXT2_IOC_GETVERSION:
return put_user(inode->i_generation, (int __user *) arg);
case EXT2_IOC_SETVERSION:
if (!is_owner_or_cap(inode))
return -EPERM;
- if (IS_RDONLY(inode))
- return -EROFS;
- if (get_user(inode->i_generation, (int __user *) arg))
- return -EFAULT;
- inode->i_ctime = CURRENT_TIME_SEC;
- mark_inode_dirty(inode);
- return 0;
+ ret = mnt_want_write(filp->f_path.mnt);
+ if (ret)
+ return ret;
+ if (get_user(inode->i_generation, (int __user *) arg)) {
+ ret = -EFAULT;
+ } else {
+ inode->i_ctime = CURRENT_TIME_SEC;
+ mark_inode_dirty(inode);
+ }
+ mnt_drop_write(filp->f_path.mnt);
+ return ret;
case EXT2_IOC_GETRSVSZ:
if (test_opt(inode->i_sb, RESERVATION)
&& S_ISREG(inode->i_mode)
if (!test_opt(inode->i_sb, RESERVATION) ||!S_ISREG(inode->i_mode))
return -ENOTTY;
- if (IS_RDONLY(inode))
- return -EROFS;
-
- if ((current->fsuid != inode->i_uid) && !capable(CAP_FOWNER))
+ if (!is_owner_or_cap(inode))
return -EACCES;
if (get_user(rsv_window_size, (int __user *)arg))
return -EFAULT;
+ ret = mnt_want_write(filp->f_path.mnt);
+ if (ret)
+ return ret;
+
if (rsv_window_size > EXT2_MAX_RESERVE_BLOCKS)
rsv_window_size = EXT2_MAX_RESERVE_BLOCKS;
rsv->rsv_goal_size = rsv_window_size;
}
mutex_unlock(&ei->truncate_mutex);
+ mnt_drop_write(filp->f_path.mnt);
return 0;
}
default:
* it has too few free inodes left (min_inodes) or
* it has too few free blocks left (min_blocks) or
* it's already running too large debt (max_debt).
- * Parent's group is prefered, if it doesn't satisfy these
+ * Parent's group is preferred, if it doesn't satisfy these
* conditions we search cyclically through the rest. If none
* of the groups look good we just look for a group with more
* free inodes than average (starting at parent's group).
* @inode: owner
* @ind: descriptor of indirect block.
*
- * This function returns the prefered place for block allocation.
+ * This function returns the preferred place for block allocation.
* It is used when heuristic for sequential allocation fails.
* Rules are:
* + if there is a block to the left of our position - allocate near it.
}
/**
- * ext3_find_goal - find a prefered place for allocation.
+ * ext3_find_goal - find a preferred place for allocation.
* @inode: owner
* @block: block we want
* @partial: pointer to the last triple within a chain
*
- * Normally this function find the prefered place for block allocation,
+ * Normally this function find the preferred place for block allocation,
* returns it.
*/
#include <linux/capability.h>
#include <linux/ext3_fs.h>
#include <linux/ext3_jbd.h>
+#include <linux/mount.h>
#include <linux/time.h>
#include <linux/compat.h>
#include <linux/smp_lock.h>
unsigned int oldflags;
unsigned int jflag;
- if (IS_RDONLY(inode))
- return -EROFS;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
- if (!is_owner_or_cap(inode))
- return -EACCES;
+ if (!is_owner_or_cap(inode)) {
+ err = -EACCES;
+ goto flags_out;
+ }
- if (get_user(flags, (int __user *) arg))
- return -EFAULT;
+ if (get_user(flags, (int __user *) arg)) {
+ err = -EFAULT;
+ goto flags_out;
+ }
if (!S_ISDIR(inode->i_mode))
flags &= ~EXT3_DIRSYNC_FL;
/* Is it quota file? Do not allow user to mess with it */
if (IS_NOQUOTA(inode)) {
mutex_unlock(&inode->i_mutex);
- return -EPERM;
+ err = -EPERM;
+ goto flags_out;
}
oldflags = ei->i_flags;
if ((flags ^ oldflags) & (EXT3_APPEND_FL | EXT3_IMMUTABLE_FL)) {
if (!capable(CAP_LINUX_IMMUTABLE)) {
mutex_unlock(&inode->i_mutex);
- return -EPERM;
+ err = -EPERM;
+ goto flags_out;
}
}
if ((jflag ^ oldflags) & (EXT3_JOURNAL_DATA_FL)) {
if (!capable(CAP_SYS_RESOURCE)) {
mutex_unlock(&inode->i_mutex);
- return -EPERM;
+ err = -EPERM;
+ goto flags_out;
}
}
handle = ext3_journal_start(inode, 1);
if (IS_ERR(handle)) {
mutex_unlock(&inode->i_mutex);
- return PTR_ERR(handle);
+ err = PTR_ERR(handle);
+ goto flags_out;
}
if (IS_SYNC(inode))
handle->h_sync = 1;
if ((jflag ^ oldflags) & (EXT3_JOURNAL_DATA_FL))
err = ext3_change_inode_journal_flag(inode, jflag);
mutex_unlock(&inode->i_mutex);
+flags_out:
+ mnt_drop_write(filp->f_path.mnt);
return err;
}
case EXT3_IOC_GETVERSION:
if (!is_owner_or_cap(inode))
return -EPERM;
- if (IS_RDONLY(inode))
- return -EROFS;
- if (get_user(generation, (int __user *) arg))
- return -EFAULT;
-
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
+ if (get_user(generation, (int __user *) arg)) {
+ err = -EFAULT;
+ goto setversion_out;
+ }
handle = ext3_journal_start(inode, 1);
- if (IS_ERR(handle))
- return PTR_ERR(handle);
+ if (IS_ERR(handle)) {
+ err = PTR_ERR(handle);
+ goto setversion_out;
+ }
err = ext3_reserve_inode_write(handle, inode, &iloc);
if (err == 0) {
inode->i_ctime = CURRENT_TIME_SEC;
err = ext3_mark_iloc_dirty(handle, inode, &iloc);
}
ext3_journal_stop(handle);
+setversion_out:
+ mnt_drop_write(filp->f_path.mnt);
return err;
}
#ifdef CONFIG_JBD_DEBUG
}
return -ENOTTY;
case EXT3_IOC_SETRSVSZ: {
+ int err;
if (!test_opt(inode->i_sb, RESERVATION) ||!S_ISREG(inode->i_mode))
return -ENOTTY;
- if (IS_RDONLY(inode))
- return -EROFS;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
- if (!is_owner_or_cap(inode))
- return -EACCES;
+ if (!is_owner_or_cap(inode)) {
+ err = -EACCES;
+ goto setrsvsz_out;
+ }
- if (get_user(rsv_window_size, (int __user *)arg))
- return -EFAULT;
+ if (get_user(rsv_window_size, (int __user *)arg)) {
+ err = -EFAULT;
+ goto setrsvsz_out;
+ }
if (rsv_window_size > EXT3_MAX_RESERVE_BLOCKS)
rsv_window_size = EXT3_MAX_RESERVE_BLOCKS;
rsv->rsv_goal_size = rsv_window_size;
}
mutex_unlock(&ei->truncate_mutex);
- return 0;
+setrsvsz_out:
+ mnt_drop_write(filp->f_path.mnt);
+ return err;
}
case EXT3_IOC_GROUP_EXTEND: {
ext3_fsblk_t n_blocks_count;
if (!capable(CAP_SYS_RESOURCE))
return -EPERM;
- if (IS_RDONLY(inode))
- return -EROFS;
-
- if (get_user(n_blocks_count, (__u32 __user *)arg))
- return -EFAULT;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
+ if (get_user(n_blocks_count, (__u32 __user *)arg)) {
+ err = -EFAULT;
+ goto group_extend_out;
+ }
err = ext3_group_extend(sb, EXT3_SB(sb)->s_es, n_blocks_count);
journal_lock_updates(EXT3_SB(sb)->s_journal);
journal_flush(EXT3_SB(sb)->s_journal);
journal_unlock_updates(EXT3_SB(sb)->s_journal);
-
+group_extend_out:
+ mnt_drop_write(filp->f_path.mnt);
return err;
}
case EXT3_IOC_GROUP_ADD: {
if (!capable(CAP_SYS_RESOURCE))
return -EPERM;
- if (IS_RDONLY(inode))
- return -EROFS;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
if (copy_from_user(&input, (struct ext3_new_group_input __user *)arg,
- sizeof(input)))
- return -EFAULT;
+ sizeof(input))) {
+ err = -EFAULT;
+ goto group_add_out;
+ }
err = ext3_group_add(sb, &input);
journal_lock_updates(EXT3_SB(sb)->s_journal);
journal_flush(EXT3_SB(sb)->s_journal);
journal_unlock_updates(EXT3_SB(sb)->s_journal);
-
+group_add_out:
+ mnt_drop_write(filp->f_path.mnt);
return err;
}
* it has too few free inodes left (min_inodes) or
* it has too few free blocks left (min_blocks) or
* it's already running too large debt (max_debt).
- * Parent's group is prefered, if it doesn't satisfy these
+ * Parent's group is preferred, if it doesn't satisfy these
* conditions we search cyclically through the rest. If none
* of the groups look good we just look for a group with more
* free inodes than average (starting at parent's group).
* @inode: owner
* @ind: descriptor of indirect block.
*
- * This function returns the prefered place for block allocation.
+ * This function returns the preferred place for block allocation.
* It is used when heuristic for sequential allocation fails.
* Rules are:
* + if there is a block to the left of our position - allocate near it.
}
/**
- * ext4_find_goal - find a prefered place for allocation.
+ * ext4_find_goal - find a preferred place for allocation.
* @inode: owner
* @block: block we want
* @partial: pointer to the last triple within a chain
*
- * Normally this function find the prefered place for block allocation,
+ * Normally this function find the preferred place for block allocation,
* returns it.
*/
static ext4_fsblk_t ext4_find_goal(struct inode *inode, ext4_lblk_t block,
#include <linux/time.h>
#include <linux/compat.h>
#include <linux/smp_lock.h>
+#include <linux/mount.h>
#include <asm/uaccess.h>
int ext4_ioctl (struct inode * inode, struct file * filp, unsigned int cmd,
unsigned int oldflags;
unsigned int jflag;
- if (IS_RDONLY(inode))
- return -EROFS;
-
if (!is_owner_or_cap(inode))
return -EACCES;
if (get_user(flags, (int __user *) arg))
return -EFAULT;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
+
if (!S_ISDIR(inode->i_mode))
flags &= ~EXT4_DIRSYNC_FL;
+ err = -EPERM;
mutex_lock(&inode->i_mutex);
/* Is it quota file? Do not allow user to mess with it */
- if (IS_NOQUOTA(inode)) {
- mutex_unlock(&inode->i_mutex);
- return -EPERM;
- }
+ if (IS_NOQUOTA(inode))
+ goto flags_out;
+
oldflags = ei->i_flags;
/* The JOURNAL_DATA flag is modifiable only by root */
* This test looks nicer. Thanks to Pauline Middelink
*/
if ((flags ^ oldflags) & (EXT4_APPEND_FL | EXT4_IMMUTABLE_FL)) {
- if (!capable(CAP_LINUX_IMMUTABLE)) {
- mutex_unlock(&inode->i_mutex);
- return -EPERM;
- }
+ if (!capable(CAP_LINUX_IMMUTABLE))
+ goto flags_out;
}
/*
* the relevant capability.
*/
if ((jflag ^ oldflags) & (EXT4_JOURNAL_DATA_FL)) {
- if (!capable(CAP_SYS_RESOURCE)) {
- mutex_unlock(&inode->i_mutex);
- return -EPERM;
- }
+ if (!capable(CAP_SYS_RESOURCE))
+ goto flags_out;
}
-
handle = ext4_journal_start(inode, 1);
if (IS_ERR(handle)) {
- mutex_unlock(&inode->i_mutex);
- return PTR_ERR(handle);
+ err = PTR_ERR(handle);
+ goto flags_out;
}
if (IS_SYNC(inode))
handle->h_sync = 1;
err = ext4_mark_iloc_dirty(handle, inode, &iloc);
flags_err:
ext4_journal_stop(handle);
- if (err) {
- mutex_unlock(&inode->i_mutex);
- return err;
- }
+ if (err)
+ goto flags_out;
if ((jflag ^ oldflags) & (EXT4_JOURNAL_DATA_FL))
err = ext4_change_inode_journal_flag(inode, jflag);
+flags_out:
mutex_unlock(&inode->i_mutex);
+ mnt_drop_write(filp->f_path.mnt);
return err;
}
case EXT4_IOC_GETVERSION:
if (!is_owner_or_cap(inode))
return -EPERM;
- if (IS_RDONLY(inode))
- return -EROFS;
- if (get_user(generation, (int __user *) arg))
- return -EFAULT;
+
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
+ if (get_user(generation, (int __user *) arg)) {
+ err = -EFAULT;
+ goto setversion_out;
+ }
handle = ext4_journal_start(inode, 1);
- if (IS_ERR(handle))
- return PTR_ERR(handle);
+ if (IS_ERR(handle)) {
+ err = PTR_ERR(handle);
+ goto setversion_out;
+ }
err = ext4_reserve_inode_write(handle, inode, &iloc);
if (err == 0) {
inode->i_ctime = ext4_current_time(inode);
err = ext4_mark_iloc_dirty(handle, inode, &iloc);
}
ext4_journal_stop(handle);
+setversion_out:
+ mnt_drop_write(filp->f_path.mnt);
return err;
}
#ifdef CONFIG_JBD2_DEBUG
}
return -ENOTTY;
case EXT4_IOC_SETRSVSZ: {
+ int err;
if (!test_opt(inode->i_sb, RESERVATION) ||!S_ISREG(inode->i_mode))
return -ENOTTY;
- if (IS_RDONLY(inode))
- return -EROFS;
-
if (!is_owner_or_cap(inode))
return -EACCES;
if (get_user(rsv_window_size, (int __user *)arg))
return -EFAULT;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
+
if (rsv_window_size > EXT4_MAX_RESERVE_BLOCKS)
rsv_window_size = EXT4_MAX_RESERVE_BLOCKS;
rsv->rsv_goal_size = rsv_window_size;
}
up_write(&ei->i_data_sem);
+ mnt_drop_write(filp->f_path.mnt);
return 0;
}
case EXT4_IOC_GROUP_EXTEND: {
if (!capable(CAP_SYS_RESOURCE))
return -EPERM;
- if (IS_RDONLY(inode))
- return -EROFS;
-
if (get_user(n_blocks_count, (__u32 __user *)arg))
return -EFAULT;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
+
err = ext4_group_extend(sb, EXT4_SB(sb)->s_es, n_blocks_count);
jbd2_journal_lock_updates(EXT4_SB(sb)->s_journal);
jbd2_journal_flush(EXT4_SB(sb)->s_journal);
jbd2_journal_unlock_updates(EXT4_SB(sb)->s_journal);
+ mnt_drop_write(filp->f_path.mnt);
return err;
}
if (!capable(CAP_SYS_RESOURCE))
return -EPERM;
- if (IS_RDONLY(inode))
- return -EROFS;
-
if (copy_from_user(&input, (struct ext4_new_group_input __user *)arg,
sizeof(input)))
return -EFAULT;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
+
err = ext4_group_add(sb, &input);
jbd2_journal_lock_updates(EXT4_SB(sb)->s_journal);
jbd2_journal_flush(EXT4_SB(sb)->s_journal);
jbd2_journal_unlock_updates(EXT4_SB(sb)->s_journal);
+ mnt_drop_write(filp->f_path.mnt);
return err;
}
#include <linux/capability.h>
#include <linux/module.h>
+#include <linux/mount.h>
#include <linux/time.h>
#include <linux/msdos_fs.h>
#include <linux/smp_lock.h>
mutex_lock(&inode->i_mutex);
- if (IS_RDONLY(inode)) {
- err = -EROFS;
- goto up;
- }
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ goto up_no_drop_write;
/*
* ATTR_VOLUME and ATTR_DIR cannot be changed; this also
MSDOS_I(inode)->i_attrs = attr & ATTR_UNUSED;
mark_inode_dirty(inode);
- up:
+up:
+ mnt_drop_write(filp->f_path.mnt);
+up_no_drop_write:
mutex_unlock(&inode->i_mutex);
return err;
}
static inline void file_free(struct file *f)
{
percpu_counter_dec(&nr_files);
+ file_check_state(f);
call_rcu(&f->f_u.fu_rcuhead, file_free_rcu);
}
file->f_mapping = dentry->d_inode->i_mapping;
file->f_mode = mode;
file->f_op = fop;
+
+ /*
+ * These mounts don't really matter in practice
+ * for r/o bind mounts. They aren't userspace-
+ * visible. We do this for consistency, and so
+ * that we can do debugging checks at __fput()
+ */
+ if ((mode & FMODE_WRITE) && !special_file(dentry->d_inode->i_mode)) {
+ file_take_write(file);
+ error = mnt_want_write(mnt);
+ WARN_ON(error);
+ }
return error;
}
EXPORT_SYMBOL(init_file);
EXPORT_SYMBOL(fput);
+/**
+ * drop_file_write_access - give up ability to write to a file
+ * @file: the file to which we will stop writing
+ *
+ * This is a central place which will give up the ability
+ * to write to @file, along with access to write through
+ * its vfsmount.
+ */
+void drop_file_write_access(struct file *file)
+{
+ struct vfsmount *mnt = file->f_path.mnt;
+ struct dentry *dentry = file->f_path.dentry;
+ struct inode *inode = dentry->d_inode;
+
+ put_write_access(inode);
+
+ if (special_file(inode->i_mode))
+ return;
+ if (file_check_writeable(file) != 0)
+ return;
+ mnt_drop_write(mnt);
+ file_release_write(file);
+}
+EXPORT_SYMBOL_GPL(drop_file_write_access);
+
/* __fput is called from task context when aio completion releases the last
* last use of a struct file *. Do not use otherwise.
*/
if (unlikely(S_ISCHR(inode->i_mode) && inode->i_cdev != NULL))
cdev_put(inode->i_cdev);
fops_put(file->f_op);
- if (file->f_mode & FMODE_WRITE)
- put_write_access(inode);
put_pid(file->f_owner.pid);
file_kill(file);
+ if (file->f_mode & FMODE_WRITE)
+ drop_file_write_access(file);
file->f_path.dentry = NULL;
file->f_path.mnt = NULL;
file_free(file);
obj-$(CONFIG_GFS2_FS_LOCKING_DLM) += lock_dlm.o
-lock_dlm-y := lock.o main.o mount.o sysfs.o thread.o plock.o
+lock_dlm-y := lock.o main.o mount.o sysfs.o thread.o
#include <net/sock.h>
#include <linux/dlm.h>
+#include <linux/dlm_plock.h>
#include <linux/lm_interface.h>
/*
int gdlm_hold_lvb(void *, char **);
void gdlm_unhold_lvb(void *, char *);
-/* plock.c */
-
-int gdlm_plock_init(void);
-void gdlm_plock_exit(void);
-int gdlm_plock(void *, struct lm_lockname *, struct file *, int,
- struct file_lock *);
-int gdlm_plock_get(void *, struct lm_lockname *, struct file *,
- struct file_lock *);
-int gdlm_punlock(void *, struct lm_lockname *, struct file *,
- struct file_lock *);
-
/* mount.c */
extern const struct lm_lockops gdlm_ops;
return error;
}
- error = gdlm_plock_init();
- if (error) {
- gdlm_sysfs_exit();
- gfs2_unregister_lockproto(&gdlm_ops);
- return error;
- }
-
printk(KERN_INFO
"Lock_DLM (built %s %s) installed\n", __DATE__, __TIME__);
return 0;
static void __exit exit_lock_dlm(void)
{
- gdlm_plock_exit();
gdlm_sysfs_exit();
gfs2_unregister_lockproto(&gdlm_ops);
}
gdlm_kobject_release(ls);
}
+static int gdlm_plock(void *lockspace, struct lm_lockname *name,
+ struct file *file, int cmd, struct file_lock *fl)
+{
+ struct gdlm_ls *ls = lockspace;
+ return dlm_posix_lock(ls->dlm_lockspace, name->ln_number, file, cmd, fl);
+}
+
+static int gdlm_punlock(void *lockspace, struct lm_lockname *name,
+ struct file *file, struct file_lock *fl)
+{
+ struct gdlm_ls *ls = lockspace;
+ return dlm_posix_unlock(ls->dlm_lockspace, name->ln_number, file, fl);
+}
+
+static int gdlm_plock_get(void *lockspace, struct lm_lockname *name,
+ struct file *file, struct file_lock *fl)
+{
+ struct gdlm_ls *ls = lockspace;
+ return dlm_posix_get(ls->dlm_lockspace, name->ln_number, file, fl);
+}
+
const struct lm_lockops gdlm_ops = {
.lm_proto_name = "lock_dlm",
.lm_mount = gdlm_mount,
#include <linux/capability.h>
#include <linux/fs.h>
+#include <linux/mount.h>
#include <linux/sched.h>
#include <linux/xattr.h>
#include <asm/uaccess.h>
flags |= FS_NODUMP_FL; /* EXT2_NODUMP_FL */
return put_user(flags, (int __user *)arg);
case HFSPLUS_IOC_EXT2_SETFLAGS: {
- if (IS_RDONLY(inode))
- return -EROFS;
-
- if (!is_owner_or_cap(inode))
- return -EACCES;
-
- if (get_user(flags, (int __user *)arg))
- return -EFAULT;
-
+ int err = 0;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
+
+ if (!is_owner_or_cap(inode)) {
+ err = -EACCES;
+ goto setflags_out;
+ }
+ if (get_user(flags, (int __user *)arg)) {
+ err = -EFAULT;
+ goto setflags_out;
+ }
if (flags & (FS_IMMUTABLE_FL|FS_APPEND_FL) ||
HFSPLUS_I(inode).rootflags & (HFSPLUS_FLG_IMMUTABLE|HFSPLUS_FLG_APPEND)) {
- if (!capable(CAP_LINUX_IMMUTABLE))
- return -EPERM;
+ if (!capable(CAP_LINUX_IMMUTABLE)) {
+ err = -EPERM;
+ goto setflags_out;
+ }
}
/* don't silently ignore unsupported ext2 flags */
- if (flags & ~(FS_IMMUTABLE_FL|FS_APPEND_FL|FS_NODUMP_FL))
- return -EOPNOTSUPP;
-
+ if (flags & ~(FS_IMMUTABLE_FL|FS_APPEND_FL|FS_NODUMP_FL)) {
+ err = -EOPNOTSUPP;
+ goto setflags_out;
+ }
if (flags & FS_IMMUTABLE_FL) { /* EXT2_IMMUTABLE_FL */
inode->i_flags |= S_IMMUTABLE;
HFSPLUS_I(inode).rootflags |= HFSPLUS_FLG_IMMUTABLE;
inode->i_ctime = CURRENT_TIME_SEC;
mark_inode_dirty(inode);
- return 0;
+setflags_out:
+ mnt_drop_write(filp->f_path.mnt);
+ return err;
}
default:
return -ENOTTY;
struct inode *inode = dentry->d_inode;
struct timespec now;
- if (inode->i_flags & S_NOATIME)
+ if (mnt_want_write(mnt))
return;
+ if (inode->i_flags & S_NOATIME)
+ goto out;
if (IS_NOATIME(inode))
- return;
+ goto out;
if ((inode->i_sb->s_flags & MS_NODIRATIME) && S_ISDIR(inode->i_mode))
- return;
+ goto out;
- /*
- * We may have a NULL vfsmount when coming from NFSD
- */
- if (mnt) {
- if (mnt->mnt_flags & MNT_NOATIME)
- return;
- if ((mnt->mnt_flags & MNT_NODIRATIME) && S_ISDIR(inode->i_mode))
- return;
-
- if (mnt->mnt_flags & MNT_RELATIME) {
- /*
- * With relative atime, only update atime if the
- * previous atime is earlier than either the ctime or
- * mtime.
- */
- if (timespec_compare(&inode->i_mtime,
- &inode->i_atime) < 0 &&
- timespec_compare(&inode->i_ctime,
- &inode->i_atime) < 0)
- return;
- }
+ if (mnt->mnt_flags & MNT_NOATIME)
+ goto out;
+ if ((mnt->mnt_flags & MNT_NODIRATIME) && S_ISDIR(inode->i_mode))
+ goto out;
+ if (mnt->mnt_flags & MNT_RELATIME) {
+ /*
+ * With relative atime, only update atime if the previous
+ * atime is earlier than either the ctime or mtime.
+ */
+ if (timespec_compare(&inode->i_mtime, &inode->i_atime) < 0 &&
+ timespec_compare(&inode->i_ctime, &inode->i_atime) < 0)
+ goto out;
}
now = current_fs_time(inode->i_sb);
if (timespec_equal(&inode->i_atime, &now))
- return;
+ goto out;
inode->i_atime = now;
mark_inode_dirty_sync(inode);
+out:
+ mnt_drop_write(mnt);
}
EXPORT_SYMBOL(touch_atime);
struct inode *inode = file->f_path.dentry->d_inode;
struct timespec now;
int sync_it = 0;
+ int err;
if (IS_NOCMTIME(inode))
return;
- if (IS_RDONLY(inode))
+
+ err = mnt_want_write(file->f_path.mnt);
+ if (err)
return;
now = current_fs_time(inode->i_sb);
if (sync_it)
mark_inode_dirty_sync(inode);
+ mnt_drop_write(file->f_path.mnt);
}
EXPORT_SYMBOL(file_update_time);
* namespace.c
*/
extern int copy_mount_options(const void __user *, unsigned long *);
+
+extern void free_vfsmnt(struct vfsmount *);
+extern struct vfsmount *alloc_vfsmnt(const char *);
+extern struct vfsmount *__lookup_mnt(struct vfsmount *, struct dentry *, int);
+extern void mnt_set_mountpoint(struct vfsmount *, struct dentry *,
+ struct vfsmount *);
+extern void release_mounts(struct list_head *);
+extern void umount_tree(struct vfsmount *, int, struct list_head *);
+extern struct vfsmount *copy_tree(struct vfsmount *, struct dentry *, int);
+
+extern void __init mnt_init(void);
#include <linux/version.h>
#include <linux/rbtree.h>
#include <linux/posix_acl.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
struct jffs2_inode_info {
/* We need an internal mutex similar to inode->i_mutex.
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/completion.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include <linux/timer.h>
#include <linux/wait.h>
#include <linux/list.h>
#include <linux/fs.h>
#include <linux/ctype.h>
#include <linux/capability.h>
+#include <linux/mount.h>
#include <linux/time.h>
#include <linux/sched.h>
#include <asm/current.h>
return put_user(flags, (int __user *) arg);
case JFS_IOC_SETFLAGS: {
unsigned int oldflags;
+ int err;
- if (IS_RDONLY(inode))
- return -EROFS;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
- if (!is_owner_or_cap(inode))
- return -EACCES;
-
- if (get_user(flags, (int __user *) arg))
- return -EFAULT;
+ if (!is_owner_or_cap(inode)) {
+ err = -EACCES;
+ goto setflags_out;
+ }
+ if (get_user(flags, (int __user *) arg)) {
+ err = -EFAULT;
+ goto setflags_out;
+ }
flags = jfs_map_ext2(flags, 1);
if (!S_ISDIR(inode->i_mode))
flags &= ~JFS_DIRSYNC_FL;
/* Is it quota file? Do not allow user to mess with it */
- if (IS_NOQUOTA(inode))
- return -EPERM;
+ if (IS_NOQUOTA(inode)) {
+ err = -EPERM;
+ goto setflags_out;
+ }
/* Lock against other parallel changes of flags */
mutex_lock(&inode->i_mutex);
(JFS_APPEND_FL | JFS_IMMUTABLE_FL))) {
if (!capable(CAP_LINUX_IMMUTABLE)) {
mutex_unlock(&inode->i_mutex);
- return -EPERM;
+ err = -EPERM;
+ goto setflags_out;
}
}
mutex_unlock(&inode->i_mutex);
inode->i_ctime = CURRENT_TIME_SEC;
mark_inode_dirty(inode);
- return 0;
+setflags_out:
+ mnt_drop_write(filp->f_path.mnt);
+ return err;
}
default:
return -ENOTTY;
#include <linux/rcupdate.h>
#include <linux/pid_namespace.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
#define IS_POSIX(fl) (fl->fl_flags & FL_POSIX)
return -EACCES;
flag &= ~O_TRUNC;
- } else if (IS_RDONLY(inode) && (acc_mode & MAY_WRITE))
- return -EROFS;
+ }
error = vfs_permission(nd, acc_mode);
if (error)
return 0;
}
-static int open_namei_create(struct nameidata *nd, struct path *path,
+/*
+ * Be careful about ever adding any more callers of this
+ * function. Its flags must be in the namei format, not
+ * what get passed to sys_open().
+ */
+static int __open_namei_create(struct nameidata *nd, struct path *path,
int flag, int mode)
{
int error;
}
/*
- * open_namei()
+ * Note that while the flag value (low two bits) for sys_open means:
+ * 00 - read-only
+ * 01 - write-only
+ * 10 - read-write
+ * 11 - special
+ * it is changed into
+ * 00 - no permissions needed
+ * 01 - read-permission
+ * 10 - write-permission
+ * 11 - read-write
+ * for the internal routines (ie open_namei()/follow_link() etc)
+ * This is more logical, and also allows the 00 "no perm needed"
+ * to be used for symlinks (where the permissions are checked
+ * later).
*
- * namei for open - this is in fact almost the whole open-routine.
- *
- * Note that the low bits of "flag" aren't the same as in the open
- * system call - they are 00 - no permissions needed
- * 01 - read permission needed
- * 10 - write permission needed
- * 11 - read/write permissions needed
- * which is a lot more logical, and also allows the "no perm" needed
- * for symlinks (where the permissions are checked later).
- * SMP-safe
+*/
+static inline int open_to_namei_flags(int flag)
+{
+ if ((flag+1) & O_ACCMODE)
+ flag++;
+ return flag;
+}
+
+static int open_will_write_to_fs(int flag, struct inode *inode)
+{
+ /*
+ * We'll never write to the fs underlying
+ * a device file.
+ */
+ if (special_file(inode->i_mode))
+ return 0;
+ return (flag & O_TRUNC);
+}
+
+/*
+ * Note that the low bits of the passed in "open_flag"
+ * are not the same as in the local variable "flag". See
+ * open_to_namei_flags() for more details.
*/
-int open_namei(int dfd, const char *pathname, int flag,
- int mode, struct nameidata *nd)
+struct file *do_filp_open(int dfd, const char *pathname,
+ int open_flag, int mode)
{
+ struct file *filp;
+ struct nameidata nd;
int acc_mode, error;
struct path path;
struct dentry *dir;
int count = 0;
+ int will_write;
+ int flag = open_to_namei_flags(open_flag);
acc_mode = ACC_MODE(flag);
*/
if (!(flag & O_CREAT)) {
error = path_lookup_open(dfd, pathname, lookup_flags(flag),
- nd, flag);
+ &nd, flag);
if (error)
- return error;
+ return ERR_PTR(error);
goto ok;
}
/*
* Create - we need to know the parent.
*/
- error = path_lookup_create(dfd,pathname,LOOKUP_PARENT,nd,flag,mode);
+ error = path_lookup_create(dfd, pathname, LOOKUP_PARENT,
+ &nd, flag, mode);
if (error)
- return error;
+ return ERR_PTR(error);
/*
* We have the parent and last component. First of all, check
* will not do.
*/
error = -EISDIR;
- if (nd->last_type != LAST_NORM || nd->last.name[nd->last.len])
+ if (nd.last_type != LAST_NORM || nd.last.name[nd.last.len])
goto exit;
- dir = nd->path.dentry;
- nd->flags &= ~LOOKUP_PARENT;
+ dir = nd.path.dentry;
+ nd.flags &= ~LOOKUP_PARENT;
mutex_lock(&dir->d_inode->i_mutex);
- path.dentry = lookup_hash(nd);
- path.mnt = nd->path.mnt;
+ path.dentry = lookup_hash(&nd);
+ path.mnt = nd.path.mnt;
do_last:
error = PTR_ERR(path.dentry);
goto exit;
}
- if (IS_ERR(nd->intent.open.file)) {
- mutex_unlock(&dir->d_inode->i_mutex);
- error = PTR_ERR(nd->intent.open.file);
- goto exit_dput;
+ if (IS_ERR(nd.intent.open.file)) {
+ error = PTR_ERR(nd.intent.open.file);
+ goto exit_mutex_unlock;
}
/* Negative dentry, just create the file */
if (!path.dentry->d_inode) {
- error = open_namei_create(nd, &path, flag, mode);
+ /*
+ * This write is needed to ensure that a
+ * ro->rw transition does not occur between
+ * the time when the file is created and when
+ * a permanent write count is taken through
+ * the 'struct file' in nameidata_to_filp().
+ */
+ error = mnt_want_write(nd.path.mnt);
if (error)
+ goto exit_mutex_unlock;
+ error = __open_namei_create(&nd, &path, flag, mode);
+ if (error) {
+ mnt_drop_write(nd.path.mnt);
goto exit;
- return 0;
+ }
+ filp = nameidata_to_filp(&nd, open_flag);
+ mnt_drop_write(nd.path.mnt);
+ return filp;
}
/*
if (path.dentry->d_inode->i_op && path.dentry->d_inode->i_op->follow_link)
goto do_link;
- path_to_nameidata(&path, nd);
+ path_to_nameidata(&path, &nd);
error = -EISDIR;
if (path.dentry->d_inode && S_ISDIR(path.dentry->d_inode->i_mode))
goto exit;
ok:
- error = may_open(nd, acc_mode, flag);
- if (error)
+ /*
+ * Consider:
+ * 1. may_open() truncates a file
+ * 2. a rw->ro mount transition occurs
+ * 3. nameidata_to_filp() fails due to
+ * the ro mount.
+ * That would be inconsistent, and should
+ * be avoided. Taking this mnt write here
+ * ensures that (2) can not occur.
+ */
+ will_write = open_will_write_to_fs(flag, nd.path.dentry->d_inode);
+ if (will_write) {
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
+ goto exit;
+ }
+ error = may_open(&nd, acc_mode, flag);
+ if (error) {
+ if (will_write)
+ mnt_drop_write(nd.path.mnt);
goto exit;
- return 0;
+ }
+ filp = nameidata_to_filp(&nd, open_flag);
+ /*
+ * It is now safe to drop the mnt write
+ * because the filp has had a write taken
+ * on its behalf.
+ */
+ if (will_write)
+ mnt_drop_write(nd.path.mnt);
+ return filp;
+exit_mutex_unlock:
+ mutex_unlock(&dir->d_inode->i_mutex);
exit_dput:
- path_put_conditional(&path, nd);
+ path_put_conditional(&path, &nd);
exit:
- if (!IS_ERR(nd->intent.open.file))
- release_open_intent(nd);
- path_put(&nd->path);
- return error;
+ if (!IS_ERR(nd.intent.open.file))
+ release_open_intent(&nd);
+ path_put(&nd.path);
+ return ERR_PTR(error);
do_link:
error = -ELOOP;
* stored in nd->last.name and we will have to putname() it when we
* are done. Procfs-like symlinks just set LAST_BIND.
*/
- nd->flags |= LOOKUP_PARENT;
- error = security_inode_follow_link(path.dentry, nd);
+ nd.flags |= LOOKUP_PARENT;
+ error = security_inode_follow_link(path.dentry, &nd);
if (error)
goto exit_dput;
- error = __do_follow_link(&path, nd);
+ error = __do_follow_link(&path, &nd);
if (error) {
/* Does someone understand code flow here? Or it is only
* me so stupid? Anathema to whoever designed this non-sense
* with "intent.open".
*/
- release_open_intent(nd);
- return error;
+ release_open_intent(&nd);
+ return ERR_PTR(error);
}
- nd->flags &= ~LOOKUP_PARENT;
- if (nd->last_type == LAST_BIND)
+ nd.flags &= ~LOOKUP_PARENT;
+ if (nd.last_type == LAST_BIND)
goto ok;
error = -EISDIR;
- if (nd->last_type != LAST_NORM)
+ if (nd.last_type != LAST_NORM)
goto exit;
- if (nd->last.name[nd->last.len]) {
- __putname(nd->last.name);
+ if (nd.last.name[nd.last.len]) {
+ __putname(nd.last.name);
goto exit;
}
error = -ELOOP;
if (count++==32) {
- __putname(nd->last.name);
+ __putname(nd.last.name);
goto exit;
}
- dir = nd->path.dentry;
+ dir = nd.path.dentry;
mutex_lock(&dir->d_inode->i_mutex);
- path.dentry = lookup_hash(nd);
- path.mnt = nd->path.mnt;
- __putname(nd->last.name);
+ path.dentry = lookup_hash(&nd);
+ path.mnt = nd.path.mnt;
+ __putname(nd.last.name);
goto do_last;
}
+/**
+ * filp_open - open file and return file pointer
+ *
+ * @filename: path to open
+ * @flags: open flags as per the open(2) second argument
+ * @mode: mode for the new file if O_CREAT is set, else ignored
+ *
+ * This is the helper to open a file from kernelspace if you really
+ * have to. But in generally you should not do this, so please move
+ * along, nothing to see here..
+ */
+struct file *filp_open(const char *filename, int flags, int mode)
+{
+ return do_filp_open(AT_FDCWD, filename, flags, mode);
+}
+EXPORT_SYMBOL(filp_open);
+
/**
* lookup_create - lookup a dentry, creating it if it doesn't exist
* @nd: nameidata info
return error;
}
+static int may_mknod(mode_t mode)
+{
+ switch (mode & S_IFMT) {
+ case S_IFREG:
+ case S_IFCHR:
+ case S_IFBLK:
+ case S_IFIFO:
+ case S_IFSOCK:
+ case 0: /* zero mode translates to S_IFREG */
+ return 0;
+ case S_IFDIR:
+ return -EPERM;
+ default:
+ return -EINVAL;
+ }
+}
+
asmlinkage long sys_mknodat(int dfd, const char __user *filename, int mode,
unsigned dev)
{
if (error)
goto out;
dentry = lookup_create(&nd, 0);
- error = PTR_ERR(dentry);
-
+ if (IS_ERR(dentry)) {
+ error = PTR_ERR(dentry);
+ goto out_unlock;
+ }
if (!IS_POSIXACL(nd.path.dentry->d_inode))
mode &= ~current->fs->umask;
- if (!IS_ERR(dentry)) {
- switch (mode & S_IFMT) {
+ error = may_mknod(mode);
+ if (error)
+ goto out_dput;
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
+ goto out_dput;
+ switch (mode & S_IFMT) {
case 0: case S_IFREG:
error = vfs_create(nd.path.dentry->d_inode,dentry,mode,&nd);
break;
case S_IFIFO: case S_IFSOCK:
error = vfs_mknod(nd.path.dentry->d_inode,dentry,mode,0);
break;
- case S_IFDIR:
- error = -EPERM;
- break;
- default:
- error = -EINVAL;
- }
- dput(dentry);
}
+ mnt_drop_write(nd.path.mnt);
+out_dput:
+ dput(dentry);
+out_unlock:
mutex_unlock(&nd.path.dentry->d_inode->i_mutex);
path_put(&nd.path);
out:
if (!IS_POSIXACL(nd.path.dentry->d_inode))
mode &= ~current->fs->umask;
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
+ goto out_dput;
error = vfs_mkdir(nd.path.dentry->d_inode, dentry, mode);
+ mnt_drop_write(nd.path.mnt);
+out_dput:
dput(dentry);
out_unlock:
mutex_unlock(&nd.path.dentry->d_inode->i_mutex);
error = PTR_ERR(dentry);
if (IS_ERR(dentry))
goto exit2;
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
+ goto exit3;
error = vfs_rmdir(nd.path.dentry->d_inode, dentry);
+ mnt_drop_write(nd.path.mnt);
+exit3:
dput(dentry);
exit2:
mutex_unlock(&nd.path.dentry->d_inode->i_mutex);
inode = dentry->d_inode;
if (inode)
atomic_inc(&inode->i_count);
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
+ goto exit2;
error = vfs_unlink(nd.path.dentry->d_inode, dentry);
+ mnt_drop_write(nd.path.mnt);
exit2:
dput(dentry);
}
if (IS_ERR(dentry))
goto out_unlock;
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
+ goto out_dput;
error = vfs_symlink(nd.path.dentry->d_inode, dentry, from, S_IALLUGO);
+ mnt_drop_write(nd.path.mnt);
+out_dput:
dput(dentry);
out_unlock:
mutex_unlock(&nd.path.dentry->d_inode->i_mutex);
error = PTR_ERR(new_dentry);
if (IS_ERR(new_dentry))
goto out_unlock;
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
+ goto out_dput;
error = vfs_link(old_nd.path.dentry, nd.path.dentry->d_inode, new_dentry);
+ mnt_drop_write(nd.path.mnt);
+out_dput:
dput(new_dentry);
out_unlock:
mutex_unlock(&nd.path.dentry->d_inode->i_mutex);
if (new_dentry == trap)
goto exit5;
+ error = mnt_want_write(oldnd.path.mnt);
+ if (error)
+ goto exit5;
error = vfs_rename(old_dir->d_inode, old_dentry,
new_dir->d_inode, new_dentry);
+ mnt_drop_write(oldnd.path.mnt);
exit5:
dput(new_dentry);
exit4:
#include <linux/quotaops.h>
#include <linux/acct.h>
#include <linux/capability.h>
+#include <linux/cpumask.h>
#include <linux/module.h>
#include <linux/sysfs.h>
#include <linux/seq_file.h>
return tmp & (HASH_SIZE - 1);
}
+#define MNT_WRITER_UNDERFLOW_LIMIT -(1<<16)
+
struct vfsmount *alloc_vfsmnt(const char *name)
{
struct vfsmount *mnt = kmem_cache_zalloc(mnt_cache, GFP_KERNEL);
INIT_LIST_HEAD(&mnt->mnt_share);
INIT_LIST_HEAD(&mnt->mnt_slave_list);
INIT_LIST_HEAD(&mnt->mnt_slave);
+ atomic_set(&mnt->__mnt_writers, 0);
if (name) {
int size = strlen(name) + 1;
char *newname = kmalloc(size, GFP_KERNEL);
return mnt;
}
+/*
+ * Most r/o checks on a fs are for operations that take
+ * discrete amounts of time, like a write() or unlink().
+ * We must keep track of when those operations start
+ * (for permission checks) and when they end, so that
+ * we can determine when writes are able to occur to
+ * a filesystem.
+ */
+/*
+ * __mnt_is_readonly: check whether a mount is read-only
+ * @mnt: the mount to check for its write status
+ *
+ * This shouldn't be used directly ouside of the VFS.
+ * It does not guarantee that the filesystem will stay
+ * r/w, just that it is right *now*. This can not and
+ * should not be used in place of IS_RDONLY(inode).
+ * mnt_want/drop_write() will _keep_ the filesystem
+ * r/w.
+ */
+int __mnt_is_readonly(struct vfsmount *mnt)
+{
+ if (mnt->mnt_flags & MNT_READONLY)
+ return 1;
+ if (mnt->mnt_sb->s_flags & MS_RDONLY)
+ return 1;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(__mnt_is_readonly);
+
+struct mnt_writer {
+ /*
+ * If holding multiple instances of this lock, they
+ * must be ordered by cpu number.
+ */
+ spinlock_t lock;
+ struct lock_class_key lock_class; /* compiles out with !lockdep */
+ unsigned long count;
+ struct vfsmount *mnt;
+} ____cacheline_aligned_in_smp;
+static DEFINE_PER_CPU(struct mnt_writer, mnt_writers);
+
+static int __init init_mnt_writers(void)
+{
+ int cpu;
+ for_each_possible_cpu(cpu) {
+ struct mnt_writer *writer = &per_cpu(mnt_writers, cpu);
+ spin_lock_init(&writer->lock);
+ lockdep_set_class(&writer->lock, &writer->lock_class);
+ writer->count = 0;
+ }
+ return 0;
+}
+fs_initcall(init_mnt_writers);
+
+static void unlock_mnt_writers(void)
+{
+ int cpu;
+ struct mnt_writer *cpu_writer;
+
+ for_each_possible_cpu(cpu) {
+ cpu_writer = &per_cpu(mnt_writers, cpu);
+ spin_unlock(&cpu_writer->lock);
+ }
+}
+
+static inline void __clear_mnt_count(struct mnt_writer *cpu_writer)
+{
+ if (!cpu_writer->mnt)
+ return;
+ /*
+ * This is in case anyone ever leaves an invalid,
+ * old ->mnt and a count of 0.
+ */
+ if (!cpu_writer->count)
+ return;
+ atomic_add(cpu_writer->count, &cpu_writer->mnt->__mnt_writers);
+ cpu_writer->count = 0;
+}
+ /*
+ * must hold cpu_writer->lock
+ */
+static inline void use_cpu_writer_for_mount(struct mnt_writer *cpu_writer,
+ struct vfsmount *mnt)
+{
+ if (cpu_writer->mnt == mnt)
+ return;
+ __clear_mnt_count(cpu_writer);
+ cpu_writer->mnt = mnt;
+}
+
+/*
+ * Most r/o checks on a fs are for operations that take
+ * discrete amounts of time, like a write() or unlink().
+ * We must keep track of when those operations start
+ * (for permission checks) and when they end, so that
+ * we can determine when writes are able to occur to
+ * a filesystem.
+ */
+/**
+ * mnt_want_write - get write access to a mount
+ * @mnt: the mount on which to take a write
+ *
+ * This tells the low-level filesystem that a write is
+ * about to be performed to it, and makes sure that
+ * writes are allowed before returning success. When
+ * the write operation is finished, mnt_drop_write()
+ * must be called. This is effectively a refcount.
+ */
+int mnt_want_write(struct vfsmount *mnt)
+{
+ int ret = 0;
+ struct mnt_writer *cpu_writer;
+
+ cpu_writer = &get_cpu_var(mnt_writers);
+ spin_lock(&cpu_writer->lock);
+ if (__mnt_is_readonly(mnt)) {
+ ret = -EROFS;
+ goto out;
+ }
+ use_cpu_writer_for_mount(cpu_writer, mnt);
+ cpu_writer->count++;
+out:
+ spin_unlock(&cpu_writer->lock);
+ put_cpu_var(mnt_writers);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mnt_want_write);
+
+static void lock_mnt_writers(void)
+{
+ int cpu;
+ struct mnt_writer *cpu_writer;
+
+ for_each_possible_cpu(cpu) {
+ cpu_writer = &per_cpu(mnt_writers, cpu);
+ spin_lock(&cpu_writer->lock);
+ __clear_mnt_count(cpu_writer);
+ cpu_writer->mnt = NULL;
+ }
+}
+
+/*
+ * These per-cpu write counts are not guaranteed to have
+ * matched increments and decrements on any given cpu.
+ * A file open()ed for write on one cpu and close()d on
+ * another cpu will imbalance this count. Make sure it
+ * does not get too far out of whack.
+ */
+static void handle_write_count_underflow(struct vfsmount *mnt)
+{
+ if (atomic_read(&mnt->__mnt_writers) >=
+ MNT_WRITER_UNDERFLOW_LIMIT)
+ return;
+ /*
+ * It isn't necessary to hold all of the locks
+ * at the same time, but doing it this way makes
+ * us share a lot more code.
+ */
+ lock_mnt_writers();
+ /*
+ * vfsmount_lock is for mnt_flags.
+ */
+ spin_lock(&vfsmount_lock);
+ /*
+ * If coalescing the per-cpu writer counts did not
+ * get us back to a positive writer count, we have
+ * a bug.
+ */
+ if ((atomic_read(&mnt->__mnt_writers) < 0) &&
+ !(mnt->mnt_flags & MNT_IMBALANCED_WRITE_COUNT)) {
+ printk(KERN_DEBUG "leak detected on mount(%p) writers "
+ "count: %d\n",
+ mnt, atomic_read(&mnt->__mnt_writers));
+ WARN_ON(1);
+ /* use the flag to keep the dmesg spam down */
+ mnt->mnt_flags |= MNT_IMBALANCED_WRITE_COUNT;
+ }
+ spin_unlock(&vfsmount_lock);
+ unlock_mnt_writers();
+}
+
+/**
+ * mnt_drop_write - give up write access to a mount
+ * @mnt: the mount on which to give up write access
+ *
+ * Tells the low-level filesystem that we are done
+ * performing writes to it. Must be matched with
+ * mnt_want_write() call above.
+ */
+void mnt_drop_write(struct vfsmount *mnt)
+{
+ int must_check_underflow = 0;
+ struct mnt_writer *cpu_writer;
+
+ cpu_writer = &get_cpu_var(mnt_writers);
+ spin_lock(&cpu_writer->lock);
+
+ use_cpu_writer_for_mount(cpu_writer, mnt);
+ if (cpu_writer->count > 0) {
+ cpu_writer->count--;
+ } else {
+ must_check_underflow = 1;
+ atomic_dec(&mnt->__mnt_writers);
+ }
+
+ spin_unlock(&cpu_writer->lock);
+ /*
+ * Logically, we could call this each time,
+ * but the __mnt_writers cacheline tends to
+ * be cold, and makes this expensive.
+ */
+ if (must_check_underflow)
+ handle_write_count_underflow(mnt);
+ /*
+ * This could be done right after the spinlock
+ * is taken because the spinlock keeps us on
+ * the cpu, and disables preemption. However,
+ * putting it here bounds the amount that
+ * __mnt_writers can underflow. Without it,
+ * we could theoretically wrap __mnt_writers.
+ */
+ put_cpu_var(mnt_writers);
+}
+EXPORT_SYMBOL_GPL(mnt_drop_write);
+
+static int mnt_make_readonly(struct vfsmount *mnt)
+{
+ int ret = 0;
+
+ lock_mnt_writers();
+ /*
+ * With all the locks held, this value is stable
+ */
+ if (atomic_read(&mnt->__mnt_writers) > 0) {
+ ret = -EBUSY;
+ goto out;
+ }
+ /*
+ * nobody can do a successful mnt_want_write() with all
+ * of the counts in MNT_DENIED_WRITE and the locks held.
+ */
+ spin_lock(&vfsmount_lock);
+ if (!ret)
+ mnt->mnt_flags |= MNT_READONLY;
+ spin_unlock(&vfsmount_lock);
+out:
+ unlock_mnt_writers();
+ return ret;
+}
+
+static void __mnt_unmake_readonly(struct vfsmount *mnt)
+{
+ spin_lock(&vfsmount_lock);
+ mnt->mnt_flags &= ~MNT_READONLY;
+ spin_unlock(&vfsmount_lock);
+}
+
int simple_set_mnt(struct vfsmount *mnt, struct super_block *sb)
{
mnt->mnt_sb = sb;
static inline void __mntput(struct vfsmount *mnt)
{
+ int cpu;
struct super_block *sb = mnt->mnt_sb;
+ /*
+ * We don't have to hold all of the locks at the
+ * same time here because we know that we're the
+ * last reference to mnt and that no new writers
+ * can come in.
+ */
+ for_each_possible_cpu(cpu) {
+ struct mnt_writer *cpu_writer = &per_cpu(mnt_writers, cpu);
+ if (cpu_writer->mnt != mnt)
+ continue;
+ spin_lock(&cpu_writer->lock);
+ atomic_add(cpu_writer->count, &mnt->__mnt_writers);
+ cpu_writer->count = 0;
+ /*
+ * Might as well do this so that no one
+ * ever sees the pointer and expects
+ * it to be valid.
+ */
+ cpu_writer->mnt = NULL;
+ spin_unlock(&cpu_writer->lock);
+ }
+ /*
+ * This probably indicates that somebody messed
+ * up a mnt_want/drop_write() pair. If this
+ * happens, the filesystem was probably unable
+ * to make r/w->r/o transitions.
+ */
+ WARN_ON(atomic_read(&mnt->__mnt_writers));
dput(mnt->mnt_root);
free_vfsmnt(mnt);
deactivate_super(sb);
seq_putc(m, '.');
mangle(m, mnt->mnt_sb->s_subtype);
}
- seq_puts(m, mnt->mnt_sb->s_flags & MS_RDONLY ? " ro" : " rw");
+ seq_puts(m, __mnt_is_readonly(mnt) ? " ro" : " rw");
for (fs_infop = fs_info; fs_infop->flag; fs_infop++) {
if (mnt->mnt_sb->s_flags & fs_infop->flag)
seq_puts(m, fs_infop->str);
struct vfsmount *collect_mounts(struct vfsmount *mnt, struct dentry *dentry)
{
struct vfsmount *tree;
- down_read(&namespace_sem);
+ down_write(&namespace_sem);
tree = copy_tree(mnt, dentry, CL_COPY_ALL | CL_PRIVATE);
- up_read(&namespace_sem);
+ up_write(&namespace_sem);
return tree;
}
void drop_collected_mounts(struct vfsmount *mnt)
{
LIST_HEAD(umount_list);
- down_read(&namespace_sem);
+ down_write(&namespace_sem);
spin_lock(&vfsmount_lock);
umount_tree(mnt, 0, &umount_list);
spin_unlock(&vfsmount_lock);
- up_read(&namespace_sem);
+ up_write(&namespace_sem);
release_mounts(&umount_list);
}
return 0;
}
-static int graft_tree(struct vfsmount *mnt, struct nameidata *nd)
+static int graft_tree(struct vfsmount *mnt, struct path *path)
{
int err;
if (mnt->mnt_sb->s_flags & MS_NOUSER)
return -EINVAL;
- if (S_ISDIR(nd->path.dentry->d_inode->i_mode) !=
+ if (S_ISDIR(path->dentry->d_inode->i_mode) !=
S_ISDIR(mnt->mnt_root->d_inode->i_mode))
return -ENOTDIR;
err = -ENOENT;
- mutex_lock(&nd->path.dentry->d_inode->i_mutex);
- if (IS_DEADDIR(nd->path.dentry->d_inode))
+ mutex_lock(&path->dentry->d_inode->i_mutex);
+ if (IS_DEADDIR(path->dentry->d_inode))
goto out_unlock;
- err = security_sb_check_sb(mnt, nd);
+ err = security_sb_check_sb(mnt, path);
if (err)
goto out_unlock;
err = -ENOENT;
- if (IS_ROOT(nd->path.dentry) || !d_unhashed(nd->path.dentry))
- err = attach_recursive_mnt(mnt, &nd->path, NULL);
+ if (IS_ROOT(path->dentry) || !d_unhashed(path->dentry))
+ err = attach_recursive_mnt(mnt, path, NULL);
out_unlock:
- mutex_unlock(&nd->path.dentry->d_inode->i_mutex);
+ mutex_unlock(&path->dentry->d_inode->i_mutex);
if (!err)
- security_sb_post_addmount(mnt, nd);
+ security_sb_post_addmount(mnt, path);
return err;
}
if (!mnt)
goto out;
- err = graft_tree(mnt, nd);
+ err = graft_tree(mnt, &nd->path);
if (err) {
LIST_HEAD(umount_list);
spin_lock(&vfsmount_lock);
return err;
}
+static int change_mount_flags(struct vfsmount *mnt, int ms_flags)
+{
+ int error = 0;
+ int readonly_request = 0;
+
+ if (ms_flags & MS_RDONLY)
+ readonly_request = 1;
+ if (readonly_request == __mnt_is_readonly(mnt))
+ return 0;
+
+ if (readonly_request)
+ error = mnt_make_readonly(mnt);
+ else
+ __mnt_unmake_readonly(mnt);
+ return error;
+}
+
/*
* change filesystem flags. dir should be a physical root of filesystem.
* If you've mounted a non-root directory somewhere and want to do remount
return -EINVAL;
down_write(&sb->s_umount);
- err = do_remount_sb(sb, flags, data, 0);
+ if (flags & MS_BIND)
+ err = change_mount_flags(nd->path.mnt, flags);
+ else
+ err = do_remount_sb(sb, flags, data, 0);
if (!err)
nd->path.mnt->mnt_flags = mnt_flags;
up_write(&sb->s_umount);
goto unlock;
newmnt->mnt_flags = mnt_flags;
- if ((err = graft_tree(newmnt, nd)))
+ if ((err = graft_tree(newmnt, &nd->path)))
goto unlock;
if (fslist) /* add to the specified expiration list */
mnt_flags |= MNT_NODIRATIME;
if (flags & MS_RELATIME)
mnt_flags |= MNT_RELATIME;
+ if (flags & MS_RDONLY)
+ mnt_flags |= MNT_READONLY;
flags &= ~(MS_NOSUID | MS_NOEXEC | MS_NODEV | MS_ACTIVE |
MS_NOATIME | MS_NODIRATIME | MS_RELATIME| MS_KERNMOUNT);
if (retval)
return retval;
- retval = security_sb_mount(dev_name, &nd, type_page, flags, data_page);
+ retval = security_sb_mount(dev_name, &nd.path,
+ type_page, flags, data_page);
if (retval)
goto dput_out;
const char __user * put_old)
{
struct vfsmount *tmp;
- struct nameidata new_nd, old_nd, user_nd;
- struct path parent_path, root_parent;
+ struct nameidata new_nd, old_nd;
+ struct path parent_path, root_parent, root;
int error;
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
- lock_kernel();
-
error = __user_walk(new_root, LOOKUP_FOLLOW | LOOKUP_DIRECTORY,
&new_nd);
if (error)
if (error)
goto out1;
- error = security_sb_pivotroot(&old_nd, &new_nd);
+ error = security_sb_pivotroot(&old_nd.path, &new_nd.path);
if (error) {
path_put(&old_nd.path);
goto out1;
}
read_lock(¤t->fs->lock);
- user_nd.path = current->fs->root;
+ root = current->fs->root;
path_get(¤t->fs->root);
read_unlock(¤t->fs->lock);
down_write(&namespace_sem);
error = -EINVAL;
if (IS_MNT_SHARED(old_nd.path.mnt) ||
IS_MNT_SHARED(new_nd.path.mnt->mnt_parent) ||
- IS_MNT_SHARED(user_nd.path.mnt->mnt_parent))
+ IS_MNT_SHARED(root.mnt->mnt_parent))
goto out2;
- if (!check_mnt(user_nd.path.mnt))
+ if (!check_mnt(root.mnt))
goto out2;
error = -ENOENT;
if (IS_DEADDIR(new_nd.path.dentry->d_inode))
if (d_unhashed(old_nd.path.dentry) && !IS_ROOT(old_nd.path.dentry))
goto out2;
error = -EBUSY;
- if (new_nd.path.mnt == user_nd.path.mnt ||
- old_nd.path.mnt == user_nd.path.mnt)
+ if (new_nd.path.mnt == root.mnt ||
+ old_nd.path.mnt == root.mnt)
goto out2; /* loop, on the same file system */
error = -EINVAL;
- if (user_nd.path.mnt->mnt_root != user_nd.path.dentry)
+ if (root.mnt->mnt_root != root.dentry)
goto out2; /* not a mountpoint */
- if (user_nd.path.mnt->mnt_parent == user_nd.path.mnt)
+ if (root.mnt->mnt_parent == root.mnt)
goto out2; /* not attached */
if (new_nd.path.mnt->mnt_root != new_nd.path.dentry)
goto out2; /* not a mountpoint */
} else if (!is_subdir(old_nd.path.dentry, new_nd.path.dentry))
goto out3;
detach_mnt(new_nd.path.mnt, &parent_path);
- detach_mnt(user_nd.path.mnt, &root_parent);
+ detach_mnt(root.mnt, &root_parent);
/* mount old root on put_old */
- attach_mnt(user_nd.path.mnt, &old_nd.path);
+ attach_mnt(root.mnt, &old_nd.path);
/* mount new_root on / */
attach_mnt(new_nd.path.mnt, &root_parent);
touch_mnt_namespace(current->nsproxy->mnt_ns);
spin_unlock(&vfsmount_lock);
- chroot_fs_refs(&user_nd.path, &new_nd.path);
- security_sb_post_pivotroot(&user_nd, &new_nd);
+ chroot_fs_refs(&root, &new_nd.path);
+ security_sb_post_pivotroot(&root, &new_nd.path);
error = 0;
path_put(&root_parent);
path_put(&parent_path);
out2:
mutex_unlock(&old_nd.path.dentry->d_inode->i_mutex);
up_write(&namespace_sem);
- path_put(&user_nd.path);
+ path_put(&root);
path_put(&old_nd.path);
out1:
path_put(&new_nd.path);
out0:
- unlock_kernel();
return error;
out3:
spin_unlock(&vfsmount_lock);
#include <linux/ioctl.h>
#include <linux/time.h>
#include <linux/mm.h>
+#include <linux/mount.h>
#include <linux/highuid.h>
#include <linux/smp_lock.h>
#include <linux/vmalloc.h>
}
#endif /* CONFIG_NCPFS_NLS */
-int ncp_ioctl(struct inode *inode, struct file *filp,
+static int __ncp_ioctl(struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg)
{
struct ncp_server *server = NCP_SERVER(inode);
return -EINVAL;
}
+static int ncp_ioctl_need_write(unsigned int cmd)
+{
+ switch (cmd) {
+ case NCP_IOC_GET_FS_INFO:
+ case NCP_IOC_GET_FS_INFO_V2:
+ case NCP_IOC_NCPREQUEST:
+ case NCP_IOC_SETDENTRYTTL:
+ case NCP_IOC_SIGN_INIT:
+ case NCP_IOC_LOCKUNLOCK:
+ case NCP_IOC_SET_SIGN_WANTED:
+ return 1;
+ case NCP_IOC_GETOBJECTNAME:
+ case NCP_IOC_SETOBJECTNAME:
+ case NCP_IOC_GETPRIVATEDATA:
+ case NCP_IOC_SETPRIVATEDATA:
+ case NCP_IOC_SETCHARSETS:
+ case NCP_IOC_GETCHARSETS:
+ case NCP_IOC_CONN_LOGGED_IN:
+ case NCP_IOC_GETDENTRYTTL:
+ case NCP_IOC_GETMOUNTUID2:
+ case NCP_IOC_SIGN_WANTED:
+ case NCP_IOC_GETROOT:
+ case NCP_IOC_SETROOT:
+ return 0;
+ default:
+ /* unkown IOCTL command, assume write */
+ return 1;
+ }
+}
+
+int ncp_ioctl(struct inode *inode, struct file *filp,
+ unsigned int cmd, unsigned long arg)
+{
+ int ret;
+
+ if (ncp_ioctl_need_write(cmd)) {
+ /*
+ * inside the ioctl(), any failures which
+ * are because of file_permission() are
+ * -EACCESS, so it seems consistent to keep
+ * that here.
+ */
+ if (mnt_want_write(filp->f_path.mnt))
+ return -EACCES;
+ }
+ ret = __ncp_ioctl(inode, filp, cmd, arg);
+ if (ncp_ioctl_need_write(cmd))
+ mnt_drop_write(filp->f_path.mnt);
+ return ret;
+}
+
#ifdef CONFIG_COMPAT
long ncp_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
if (nd->flags & LOOKUP_DIRECTORY)
return 0;
/* Are we trying to write to a read only partition? */
- if (IS_RDONLY(dir) && (nd->intent.open.flags & (O_CREAT|O_TRUNC|FMODE_WRITE)))
+ if (__mnt_is_readonly(nd->path.mnt) &&
+ (nd->intent.open.flags & (O_CREAT|O_TRUNC|FMODE_WRITE)))
return 0;
return 1;
}
return status;
}
}
+ status = mnt_want_write(cstate->current_fh.fh_export->ex_path.mnt);
+ if (status)
+ return status;
status = nfs_ok;
if (setattr->sa_acl != NULL)
status = nfsd4_set_nfs4_acl(rqstp, &cstate->current_fh,
setattr->sa_acl);
if (status)
- return status;
+ goto out;
status = nfsd_setattr(rqstp, &cstate->current_fh, &setattr->sa_iattr,
0, (time_t)0);
+out:
+ mnt_drop_write(cstate->current_fh.fh_export->ex_path.mnt);
return status;
}
#include <linux/scatterlist.h>
#include <linux/crypto.h>
#include <linux/sched.h>
+#include <linux/mount.h>
#define NFSDDBG_FACILITY NFSDDBG_PROC
dprintk("NFSD: nfsd4_create_clid_dir: DIRECTORY EXISTS\n");
goto out_put;
}
+ status = mnt_want_write(rec_dir.path.mnt);
+ if (status)
+ goto out_put;
status = vfs_mkdir(rec_dir.path.dentry->d_inode, dentry, S_IRWXU);
+ mnt_drop_write(rec_dir.path.mnt);
out_put:
dput(dentry);
out_unlock:
if (!rec_dir_init || !clp->cl_firststate)
return;
+ status = mnt_want_write(rec_dir.path.mnt);
+ if (status)
+ goto out;
clp->cl_firststate = 0;
nfs4_save_user(&uid, &gid);
status = nfsd4_unlink_clid_dir(clp->cl_recdir, HEXDIR_LEN-1);
nfs4_reset_user(uid, gid);
if (status == 0)
nfsd4_sync_rec_dir();
+ mnt_drop_write(rec_dir.path.mnt);
+out:
if (status)
printk("NFSD: Failed to remove expired client state directory"
" %.*s\n", HEXDIR_LEN, clp->cl_recdir);
if (!rec_dir_init)
return;
+ status = mnt_want_write(rec_dir.path.mnt);
+ if (status)
+ goto out;
status = nfsd4_list_rec_dir(rec_dir.path.dentry, purge_old);
if (status == 0)
nfsd4_sync_rec_dir();
+ mnt_drop_write(rec_dir.path.mnt);
+out:
if (status)
printk("nfsd4: failed to purge old clients from recovery"
" directory %s\n", rec_dir.path.dentry->d_name.name);
- return;
}
static int
#include <linux/sunrpc/svc.h>
#include <linux/nfsd/nfsd.h>
#include <linux/nfsd/cache.h>
+#include <linux/file.h>
#include <linux/mount.h>
#include <linux/workqueue.h>
#include <linux/smp_lock.h>
nfs4_file_downgrade(struct file *filp, unsigned int share_access)
{
if (share_access & NFS4_SHARE_ACCESS_WRITE) {
- put_write_access(filp->f_path.dentry->d_inode);
+ drop_file_write_access(filp);
filp->f_mode = (filp->f_mode | FMODE_READ) & ~FMODE_WRITE;
}
}
err = 0;
switch (type) {
case S_IFREG:
+ host_err = mnt_want_write(fhp->fh_export->ex_path.mnt);
+ if (host_err)
+ goto out_nfserr;
host_err = vfs_create(dirp, dchild, iap->ia_mode, NULL);
break;
case S_IFDIR:
+ host_err = mnt_want_write(fhp->fh_export->ex_path.mnt);
+ if (host_err)
+ goto out_nfserr;
host_err = vfs_mkdir(dirp, dchild, iap->ia_mode);
break;
case S_IFCHR:
case S_IFBLK:
case S_IFIFO:
case S_IFSOCK:
+ host_err = mnt_want_write(fhp->fh_export->ex_path.mnt);
+ if (host_err)
+ goto out_nfserr;
host_err = vfs_mknod(dirp, dchild, iap->ia_mode, rdev);
break;
default:
printk("nfsd: bad file type %o in nfsd_create\n", type);
host_err = -EINVAL;
+ goto out_nfserr;
}
- if (host_err < 0)
+ if (host_err < 0) {
+ mnt_drop_write(fhp->fh_export->ex_path.mnt);
goto out_nfserr;
+ }
if (EX_ISSYNC(fhp->fh_export)) {
err = nfserrno(nfsd_sync_dir(dentry));
err2 = nfsd_create_setattr(rqstp, resfhp, iap);
if (err2)
err = err2;
+ mnt_drop_write(fhp->fh_export->ex_path.mnt);
/*
* Update the file handle to get the new inode info.
*/
v_atime = verifier[1]&0x7fffffff;
}
+ host_err = mnt_want_write(fhp->fh_export->ex_path.mnt);
+ if (host_err)
+ goto out_nfserr;
if (dchild->d_inode) {
err = 0;
case NFS3_CREATE_GUARDED:
err = nfserr_exist;
}
+ mnt_drop_write(fhp->fh_export->ex_path.mnt);
goto out;
}
host_err = vfs_create(dirp, dchild, iap->ia_mode, NULL);
- if (host_err < 0)
+ if (host_err < 0) {
+ mnt_drop_write(fhp->fh_export->ex_path.mnt);
goto out_nfserr;
+ }
if (created)
*created = 1;
if (err2)
err = err2;
+ mnt_drop_write(fhp->fh_export->ex_path.mnt);
/*
* Update the filehandle to get the new inode info.
*/
if (iap && (iap->ia_valid & ATTR_MODE))
mode = iap->ia_mode & S_IALLUGO;
+ host_err = mnt_want_write(fhp->fh_export->ex_path.mnt);
+ if (host_err)
+ goto out_nfserr;
+
if (unlikely(path[plen] != 0)) {
char *path_alloced = kmalloc(plen+1, GFP_KERNEL);
if (path_alloced == NULL)
err = nfserrno(host_err);
fh_unlock(fhp);
+ mnt_drop_write(fhp->fh_export->ex_path.mnt);
+
cerr = fh_compose(resfhp, fhp->fh_export, dnew, fhp);
dput(dnew);
if (err==0) err = cerr;
dold = tfhp->fh_dentry;
dest = dold->d_inode;
+ host_err = mnt_want_write(tfhp->fh_export->ex_path.mnt);
+ if (host_err) {
+ err = nfserrno(host_err);
+ goto out_dput;
+ }
host_err = vfs_link(dold, dirp, dnew);
if (!host_err) {
if (EX_ISSYNC(ffhp->fh_export)) {
else
err = nfserrno(host_err);
}
-
+ mnt_drop_write(tfhp->fh_export->ex_path.mnt);
+out_dput:
dput(dnew);
out_unlock:
fh_unlock(ffhp);
if (ndentry == trap)
goto out_dput_new;
-#ifdef MSNFS
- if ((ffhp->fh_export->ex_flags & NFSEXP_MSNFS) &&
+ if (svc_msnfs(ffhp) &&
((atomic_read(&odentry->d_count) > 1)
|| (atomic_read(&ndentry->d_count) > 1))) {
host_err = -EPERM;
- } else
-#endif
+ goto out_dput_new;
+ }
+
+ host_err = -EXDEV;
+ if (ffhp->fh_export->ex_path.mnt != tfhp->fh_export->ex_path.mnt)
+ goto out_dput_new;
+ host_err = mnt_want_write(ffhp->fh_export->ex_path.mnt);
+ if (host_err)
+ goto out_dput_new;
+
host_err = vfs_rename(fdir, odentry, tdir, ndentry);
if (!host_err && EX_ISSYNC(tfhp->fh_export)) {
host_err = nfsd_sync_dir(tdentry);
host_err = nfsd_sync_dir(fdentry);
}
+ mnt_drop_write(ffhp->fh_export->ex_path.mnt);
+
out_dput_new:
dput(ndentry);
out_dput_old:
if (!type)
type = rdentry->d_inode->i_mode & S_IFMT;
+ host_err = mnt_want_write(fhp->fh_export->ex_path.mnt);
+ if (host_err)
+ goto out_nfserr;
+
if (type != S_IFDIR) { /* It's UNLINK */
#ifdef MSNFS
if ((fhp->fh_export->ex_flags & NFSEXP_MSNFS) &&
dput(rdentry);
if (host_err)
- goto out_nfserr;
+ goto out_drop;
if (EX_ISSYNC(fhp->fh_export))
host_err = nfsd_sync_dir(dentry);
+out_drop:
+ mnt_drop_write(fhp->fh_export->ex_path.mnt);
out_nfserr:
err = nfserrno(host_err);
out:
inode->i_mode,
IS_IMMUTABLE(inode)? " immut" : "",
IS_APPEND(inode)? " append" : "",
- IS_RDONLY(inode)? " ro" : "");
+ __mnt_is_readonly(exp->ex_path.mnt)? " ro" : "");
dprintk(" owner %d/%d user %d/%d\n",
inode->i_uid, inode->i_gid, current->fsuid, current->fsgid);
#endif
*/
if (!(acc & MAY_LOCAL_ACCESS))
if (acc & (MAY_WRITE | MAY_SATTR | MAY_TRUNC)) {
- if (exp_rdonly(rqstp, exp) || IS_RDONLY(inode))
+ if (exp_rdonly(rqstp, exp) ||
+ __mnt_is_readonly(exp->ex_path.mnt))
return nfserr_rofs;
if (/* (acc & MAY_WRITE) && */ IS_IMMUTABLE(inode))
return nfserr_perm;
} else
size = 0;
+ error = mnt_want_write(fhp->fh_export->ex_path.mnt);
+ if (error)
+ goto getout;
if (size)
error = vfs_setxattr(fhp->fh_dentry, name, value, size, 0);
else {
error = 0;
}
}
+ mnt_drop_write(fhp->fh_export->ex_path.mnt);
getout:
kfree(value);
goto bail;
}
- status = -EROFS;
- if (IS_RDONLY(inode))
- goto bail_unlock;
-
status = -EACCES;
if (!is_owner_or_cap(inode))
goto bail_unlock;
if (get_user(flags, (int __user *) arg))
return -EFAULT;
- return ocfs2_set_inode_attr(inode, flags,
+ status = mnt_want_write(filp->f_path.mnt);
+ if (status)
+ return status;
+ status = ocfs2_set_inode_attr(inode, flags,
OCFS2_FL_MODIFIABLE);
+ mnt_drop_write(filp->f_path.mnt);
+ return status;
case OCFS2_IOC_RESVSP:
case OCFS2_IOC_RESVSP64:
case OCFS2_IOC_UNRESVSP:
if (!S_ISREG(inode->i_mode))
goto dput_and_out;
- error = vfs_permission(&nd, MAY_WRITE);
+ error = mnt_want_write(nd.path.mnt);
if (error)
goto dput_and_out;
- error = -EROFS;
- if (IS_RDONLY(inode))
- goto dput_and_out;
+ error = vfs_permission(&nd, MAY_WRITE);
+ if (error)
+ goto mnt_drop_write_and_out;
error = -EPERM;
if (IS_IMMUTABLE(inode) || IS_APPEND(inode))
- goto dput_and_out;
+ goto mnt_drop_write_and_out;
error = get_write_access(inode);
if (error)
- goto dput_and_out;
+ goto mnt_drop_write_and_out;
/*
* Make sure that there are no leases. get_write_access() protects
put_write_and_out:
put_write_access(inode);
+mnt_drop_write_and_out:
+ mnt_drop_write(nd.path.mnt);
dput_and_out:
path_put(&nd.path);
out:
if(res || !(mode & S_IWOTH) ||
special_file(nd.path.dentry->d_inode->i_mode))
goto out_path_release;
-
- if(IS_RDONLY(nd.path.dentry->d_inode))
+ /*
+ * This is a rare case where using __mnt_is_readonly()
+ * is OK without a mnt_want/drop_write() pair. Since
+ * no actual write to the fs is performed here, we do
+ * not need to telegraph to that to anyone.
+ *
+ * By doing this, we accept that this access is
+ * inherently racy and know that the fs may change
+ * state before we even see this result.
+ */
+ if (__mnt_is_readonly(nd.path.mnt))
res = -EROFS;
out_path_release:
audit_inode(NULL, dentry);
- err = -EROFS;
- if (IS_RDONLY(inode))
+ err = mnt_want_write(file->f_path.mnt);
+ if (err)
goto out_putf;
err = -EPERM;
if (IS_IMMUTABLE(inode) || IS_APPEND(inode))
- goto out_putf;
+ goto out_drop_write;
mutex_lock(&inode->i_mutex);
if (mode == (mode_t) -1)
mode = inode->i_mode;
err = notify_change(dentry, &newattrs);
mutex_unlock(&inode->i_mutex);
+out_drop_write:
+ mnt_drop_write(file->f_path.mnt);
out_putf:
fput(file);
out:
goto out;
inode = nd.path.dentry->d_inode;
- error = -EROFS;
- if (IS_RDONLY(inode))
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
goto dput_and_out;
error = -EPERM;
if (IS_IMMUTABLE(inode) || IS_APPEND(inode))
- goto dput_and_out;
+ goto out_drop_write;
mutex_lock(&inode->i_mutex);
if (mode == (mode_t) -1)
error = notify_change(nd.path.dentry, &newattrs);
mutex_unlock(&inode->i_mutex);
+out_drop_write:
+ mnt_drop_write(nd.path.mnt);
dput_and_out:
path_put(&nd.path);
out:
printk(KERN_ERR "chown_common: NULL inode\n");
goto out;
}
- error = -EROFS;
- if (IS_RDONLY(inode))
- goto out;
error = -EPERM;
if (IS_IMMUTABLE(inode) || IS_APPEND(inode))
goto out;
error = user_path_walk(filename, &nd);
if (error)
goto out;
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
+ goto out_release;
error = chown_common(nd.path.dentry, user, group);
+ mnt_drop_write(nd.path.mnt);
+out_release:
path_put(&nd.path);
out:
return error;
error = __user_walk_fd(dfd, filename, follow, &nd);
if (error)
goto out;
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
+ goto out_release;
error = chown_common(nd.path.dentry, user, group);
+ mnt_drop_write(nd.path.mnt);
+out_release:
path_put(&nd.path);
out:
return error;
error = user_path_walk_link(filename, &nd);
if (error)
goto out;
+ error = mnt_want_write(nd.path.mnt);
+ if (error)
+ goto out_release;
error = chown_common(nd.path.dentry, user, group);
+ mnt_drop_write(nd.path.mnt);
+out_release:
path_put(&nd.path);
out:
return error;
if (!file)
goto out;
+ error = mnt_want_write(file->f_path.mnt);
+ if (error)
+ goto out_fput;
dentry = file->f_path.dentry;
audit_inode(NULL, dentry);
error = chown_common(dentry, user, group);
+ mnt_drop_write(file->f_path.mnt);
+out_fput:
fput(file);
out:
return error;
}
+/*
+ * You have to be very careful that these write
+ * counts get cleaned up in error cases and
+ * upon __fput(). This should probably never
+ * be called outside of __dentry_open().
+ */
+static inline int __get_file_write_access(struct inode *inode,
+ struct vfsmount *mnt)
+{
+ int error;
+ error = get_write_access(inode);
+ if (error)
+ return error;
+ /*
+ * Do not take mount writer counts on
+ * special files since no writes to
+ * the mount itself will occur.
+ */
+ if (!special_file(inode->i_mode)) {
+ /*
+ * Balanced in __fput()
+ */
+ error = mnt_want_write(mnt);
+ if (error)
+ put_write_access(inode);
+ }
+ return error;
+}
+
static struct file *__dentry_open(struct dentry *dentry, struct vfsmount *mnt,
int flags, struct file *f,
int (*open)(struct inode *, struct file *))
FMODE_PREAD | FMODE_PWRITE;
inode = dentry->d_inode;
if (f->f_mode & FMODE_WRITE) {
- error = get_write_access(inode);
+ error = __get_file_write_access(inode, mnt);
if (error)
goto cleanup_file;
+ if (!special_file(inode->i_mode))
+ file_take_write(f);
}
f->f_mapping = inode->i_mapping;
cleanup_all:
fops_put(f->f_op);
- if (f->f_mode & FMODE_WRITE)
+ if (f->f_mode & FMODE_WRITE) {
put_write_access(inode);
+ if (!special_file(inode->i_mode)) {
+ /*
+ * We don't consider this a real
+ * mnt_want/drop_write() pair
+ * because it all happenend right
+ * here, so just reset the state.
+ */
+ file_reset_write(f);
+ mnt_drop_write(mnt);
+ }
+ }
file_kill(f);
f->f_path.dentry = NULL;
f->f_path.mnt = NULL;
return ERR_PTR(error);
}
-/*
- * Note that while the flag value (low two bits) for sys_open means:
- * 00 - read-only
- * 01 - write-only
- * 10 - read-write
- * 11 - special
- * it is changed into
- * 00 - no permissions needed
- * 01 - read-permission
- * 10 - write-permission
- * 11 - read-write
- * for the internal routines (ie open_namei()/follow_link() etc). 00 is
- * used by symlinks.
- */
-static struct file *do_filp_open(int dfd, const char *filename, int flags,
- int mode)
-{
- int namei_flags, error;
- struct nameidata nd;
-
- namei_flags = flags;
- if ((namei_flags+1) & O_ACCMODE)
- namei_flags++;
-
- error = open_namei(dfd, filename, namei_flags, mode, &nd);
- if (!error)
- return nameidata_to_filp(&nd, flags);
-
- return ERR_PTR(error);
-}
-
-struct file *filp_open(const char *filename, int flags, int mode)
-{
- return do_filp_open(AT_FDCWD, filename, flags, mode);
-}
-EXPORT_SYMBOL(filp_open);
-
/**
* lookup_instantiate_filp - instantiates the open intent filp
* @nd: pointer to nameidata
return 0;
if (IS_ERR(state)) /* I/O error reading the partition table */
return -EIO;
+
+ /* tell userspace that the media / partition table may have changed */
+ kobject_uevent(&disk->dev.kobj, KOBJ_CHANGE);
+
for (p = 1; p < state->limit; p++) {
sector_t size = state->parts[p].size;
sector_t from = state->parts[p].from;
return f;
err_dentry:
+ free_pipe_info(inode);
dput(dentry);
+ return ERR_PTR(err);
+
err_inode:
free_pipe_info(inode);
iput(inode);
#include <linux/mnt_namespace.h>
#include <linux/mount.h>
#include <linux/fs.h>
+#include "internal.h"
#include "pnode.h"
/* return the next shared peer mount of @p */
out:
spin_lock(&vfsmount_lock);
while (!list_empty(&tmp_list)) {
- child = list_entry(tmp_list.next, struct vfsmount, mnt_hash);
- list_del_init(&child->mnt_hash);
+ child = list_first_entry(&tmp_list, struct vfsmount, mnt_hash);
umount_tree(child, 0, &umount_list);
}
spin_unlock(&vfsmount_lock);
struct list_head *);
int propagate_umount(struct list_head *);
int propagate_mount_busy(struct vfsmount *, int);
+void mnt_release_group_id(struct vfsmount *);
#endif /* _LINUX_PNODE_H */
unsigned int fd, ino;
int retval;
struct files_struct * files;
- struct fdtable *fdt;
retval = -ENOENT;
if (!p)
if (!files)
goto out;
rcu_read_lock();
- fdt = files_fdtable(files);
for (fd = filp->f_pos-2;
- fd < fdt->max_fds;
+ fd < files_fdtable(files)->max_fds;
fd++, filp->f_pos++) {
char name[PROC_NUMBUF];
int len;
loff_t generic_file_llseek(struct file *file, loff_t offset, int origin)
{
- long long retval;
+ loff_t retval;
struct inode *inode = file->f_mapping->host;
mutex_lock(&inode->i_mutex);
loff_t remote_llseek(struct file *file, loff_t offset, int origin)
{
- long long retval;
+ loff_t retval;
lock_kernel();
switch (origin) {
loff_t default_llseek(struct file *file, loff_t offset, int origin)
{
- long long retval;
+ loff_t retval;
lock_kernel();
switch (origin) {
#include <linux/capability.h>
#include <linux/fs.h>
+#include <linux/mount.h>
#include <linux/reiserfs_fs.h>
#include <linux/time.h>
#include <asm/uaccess.h>
unsigned long arg)
{
unsigned int flags;
+ int err = 0;
switch (cmd) {
case REISERFS_IOC_UNPACK:
if (!reiserfs_attrs(inode->i_sb))
return -ENOTTY;
- if (IS_RDONLY(inode))
- return -EROFS;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
- if (!is_owner_or_cap(inode))
- return -EPERM;
-
- if (get_user(flags, (int __user *)arg))
- return -EFAULT;
-
- /* Is it quota file? Do not allow user to mess with it. */
- if (IS_NOQUOTA(inode))
- return -EPERM;
+ if (!is_owner_or_cap(inode)) {
+ err = -EPERM;
+ goto setflags_out;
+ }
+ if (get_user(flags, (int __user *)arg)) {
+ err = -EFAULT;
+ goto setflags_out;
+ }
+ /*
+ * Is it quota file? Do not allow user to mess with it
+ */
+ if (IS_NOQUOTA(inode)) {
+ err = -EPERM;
+ goto setflags_out;
+ }
if (((flags ^ REISERFS_I(inode)->
i_attrs) & (REISERFS_IMMUTABLE_FL |
REISERFS_APPEND_FL))
- && !capable(CAP_LINUX_IMMUTABLE))
- return -EPERM;
-
+ && !capable(CAP_LINUX_IMMUTABLE)) {
+ err = -EPERM;
+ goto setflags_out;
+ }
if ((flags & REISERFS_NOTAIL_FL) &&
S_ISREG(inode->i_mode)) {
int result;
result = reiserfs_unpack(inode, filp);
- if (result)
- return result;
+ if (result) {
+ err = result;
+ goto setflags_out;
+ }
}
sd_attrs_to_i_attrs(flags, inode);
REISERFS_I(inode)->i_attrs = flags;
inode->i_ctime = CURRENT_TIME_SEC;
mark_inode_dirty(inode);
- return 0;
+setflags_out:
+ mnt_drop_write(filp->f_path.mnt);
+ return err;
}
case REISERFS_IOC_GETVERSION:
return put_user(inode->i_generation, (int __user *)arg);
case REISERFS_IOC_SETVERSION:
if (!is_owner_or_cap(inode))
return -EPERM;
- if (IS_RDONLY(inode))
- return -EROFS;
- if (get_user(inode->i_generation, (int __user *)arg))
- return -EFAULT;
+ err = mnt_want_write(filp->f_path.mnt);
+ if (err)
+ return err;
+ if (get_user(inode->i_generation, (int __user *)arg)) {
+ err = -EFAULT;
+ goto setversion_out;
+ }
inode->i_ctime = CURRENT_TIME_SEC;
mark_inode_dirty(inode);
- return 0;
+setversion_out:
+ mnt_drop_write(filp->f_path.mnt);
+ return err;
default:
return -ENOTTY;
}
#include <asm/system.h>
#include <linux/time.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include <linux/vmalloc.h>
#include <linux/reiserfs_fs.h>
#include <net/checksum.h>
#include <linux/smp_lock.h>
#include <linux/stat.h>
-#include <asm/semaphore.h>
#define FL_READONLY 128
#define FL_DIR_SEM_HELD 256
wait = NULL;
if (retval || !*timeout || signal_pending(current))
break;
- if(table.error) {
+ if (table.error) {
retval = table.error;
break;
}
* into the buffer. In case of error ->start() and ->next() return
* ERR_PTR(error). In the end of sequence they return %NULL. ->show()
* returns 0 in case of success and negative number in case of error.
+ * Returning SEQ_SKIP means "discard this element and move on".
*/
int seq_open(struct file *file, const struct seq_operations *op)
{
if (!p || IS_ERR(p))
break;
err = m->op->show(m, p);
- if (err)
+ if (err < 0)
break;
+ if (unlikely(err))
+ m->count = 0;
if (m->count < m->size)
goto Fill;
m->op->stop(m, p);
break;
}
err = m->op->show(m, p);
- if (err || m->count == m->size) {
+ if (m->count == m->size || err) {
m->count = offs;
- break;
+ if (likely(err <= 0))
+ break;
}
pos = next;
}
if (IS_ERR(p))
break;
error = m->op->show(m, p);
- if (error)
+ if (error < 0)
break;
+ if (unlikely(error)) {
+ error = 0;
+ m->count = 0;
+ }
if (m->count == m->size)
goto Eoverflow;
if (pos + m->count > offset) {
loff_t seq_lseek(struct file *file, loff_t offset, int origin)
{
struct seq_file *m = (struct seq_file *)file->private_data;
- long long retval = -EINVAL;
+ loff_t retval = -EINVAL;
mutex_lock(&m->lock);
m->version = file->f_version;
#include <linux/idr.h>
#include <linux/kobject.h>
#include <linux/mutex.h>
+#include <linux/file.h>
#include <asm/uaccess.h>
+#include "internal.h"
LIST_HEAD(super_blocks);
{
struct file *f;
+retry:
file_list_lock();
list_for_each_entry(f, &sb->s_files, f_u.fu_list) {
- if (S_ISREG(f->f_path.dentry->d_inode->i_mode) && file_count(f))
- f->f_mode &= ~FMODE_WRITE;
+ struct vfsmount *mnt;
+ if (!S_ISREG(f->f_path.dentry->d_inode->i_mode))
+ continue;
+ if (!file_count(f))
+ continue;
+ if (!(f->f_mode & FMODE_WRITE))
+ continue;
+ f->f_mode &= ~FMODE_WRITE;
+ if (file_check_writeable(f) != 0)
+ continue;
+ file_release_write(f);
+ mnt = mntget(f->f_path.mnt);
+ file_list_unlock();
+ /*
+ * This can sleep, so we can't hold
+ * the file_list_lock() spinlock.
+ */
+ mnt_drop_write(mnt);
+ mntput(mnt);
+ goto retry;
}
file_list_unlock();
}
#include <linux/idr.h>
#include <linux/completion.h>
#include <linux/mutex.h>
+#include <linux/slab.h>
#include "sysfs.h"
DEFINE_MUTEX(sysfs_mutex);
#include <linux/module.h>
#include <linux/kobject.h>
#include <linux/kallsyms.h>
+#include <linux/slab.h>
#include <linux/namei.h>
#include <linux/poll.h>
#include <linux/list.h>
ssize_t retval = 0;
mutex_lock(&buffer->mutex);
- if (buffer->needs_read_fill) {
+ if (buffer->needs_read_fill || *ppos == 0) {
retval = fill_read_buffer(file->f_path.dentry,buffer);
if (retval)
goto out;
* return POLLERR|POLLPRI, and select will return the fd whether
* it is waiting for read, write, or exceptions.
* Once poll/select indicates that the value has changed, you
- * need to close and re-open the file, as simply seeking and reading
- * again will not get new data, or reset the state of 'poll'.
+ * need to close and re-open the file, or seek to 0 and read again.
* Reminder: this only works for attributes which actively support
* it, and it is not possible to test an attribute from userspace
* to see if it supports poll (Neither 'poll' nor 'select' return
udf-objs := balloc.o dir.o file.o ialloc.o inode.o lowlevel.o namei.o \
partition.o super.o truncate.o symlink.o fsync.o \
- crc.o directory.o misc.o udftime.o unicode.o
+ directory.o misc.o udftime.o unicode.o
return false;
lvid = (struct logicalVolIntegrityDesc *)sbi->s_lvid_bh->b_data;
- lvid->freeSpaceTable[partition] = cpu_to_le32(le32_to_cpu(
- lvid->freeSpaceTable[partition]) + cnt);
+ le32_add_cpu(&lvid->freeSpaceTable[partition], cnt);
return true;
}
sptr = oepos.bh->b_data + epos.offset;
aed = (struct allocExtDesc *)
oepos.bh->b_data;
- aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(
- aed->lengthAllocDescs) +
- adsize);
+ le32_add_cpu(&aed->lengthAllocDescs,
+ adsize);
} else {
sptr = iinfo->i_ext.i_data +
epos.offset;
mark_inode_dirty(table);
} else {
aed = (struct allocExtDesc *)epos.bh->b_data;
- aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(
- aed->lengthAllocDescs) + adsize);
+ le32_add_cpu(&aed->lengthAllocDescs, adsize);
udf_update_tag(epos.bh->b_data, epos.offset);
mark_buffer_dirty(epos.bh);
}
+++ /dev/null
-/*
- * crc.c
- *
- * PURPOSE
- * Routines to generate, calculate, and test a 16-bit CRC.
- *
- * DESCRIPTION
- * The CRC code was devised by Don P. Mitchell of AT&T Bell Laboratories
- * and Ned W. Rhodes of Software Systems Group. It has been published in
- * "Design and Validation of Computer Protocols", Prentice Hall,
- * Englewood Cliffs, NJ, 1991, Chapter 3, ISBN 0-13-539925-4.
- *
- * Copyright is held by AT&T.
- *
- * AT&T gives permission for the free use of the CRC source code.
- *
- * COPYRIGHT
- * This file is distributed under the terms of the GNU General Public
- * License (GPL). Copies of the GPL can be obtained from:
- * ftp://prep.ai.mit.edu/pub/gnu/GPL
- * Each contributing author retains all rights to their own work.
- */
-
-#include "udfdecl.h"
-
-static uint16_t crc_table[256] = {
- 0x0000U, 0x1021U, 0x2042U, 0x3063U, 0x4084U, 0x50a5U, 0x60c6U, 0x70e7U,
- 0x8108U, 0x9129U, 0xa14aU, 0xb16bU, 0xc18cU, 0xd1adU, 0xe1ceU, 0xf1efU,
- 0x1231U, 0x0210U, 0x3273U, 0x2252U, 0x52b5U, 0x4294U, 0x72f7U, 0x62d6U,
- 0x9339U, 0x8318U, 0xb37bU, 0xa35aU, 0xd3bdU, 0xc39cU, 0xf3ffU, 0xe3deU,
- 0x2462U, 0x3443U, 0x0420U, 0x1401U, 0x64e6U, 0x74c7U, 0x44a4U, 0x5485U,
- 0xa56aU, 0xb54bU, 0x8528U, 0x9509U, 0xe5eeU, 0xf5cfU, 0xc5acU, 0xd58dU,
- 0x3653U, 0x2672U, 0x1611U, 0x0630U, 0x76d7U, 0x66f6U, 0x5695U, 0x46b4U,
- 0xb75bU, 0xa77aU, 0x9719U, 0x8738U, 0xf7dfU, 0xe7feU, 0xd79dU, 0xc7bcU,
- 0x48c4U, 0x58e5U, 0x6886U, 0x78a7U, 0x0840U, 0x1861U, 0x2802U, 0x3823U,
- 0xc9ccU, 0xd9edU, 0xe98eU, 0xf9afU, 0x8948U, 0x9969U, 0xa90aU, 0xb92bU,
- 0x5af5U, 0x4ad4U, 0x7ab7U, 0x6a96U, 0x1a71U, 0x0a50U, 0x3a33U, 0x2a12U,
- 0xdbfdU, 0xcbdcU, 0xfbbfU, 0xeb9eU, 0x9b79U, 0x8b58U, 0xbb3bU, 0xab1aU,
- 0x6ca6U, 0x7c87U, 0x4ce4U, 0x5cc5U, 0x2c22U, 0x3c03U, 0x0c60U, 0x1c41U,
- 0xedaeU, 0xfd8fU, 0xcdecU, 0xddcdU, 0xad2aU, 0xbd0bU, 0x8d68U, 0x9d49U,
- 0x7e97U, 0x6eb6U, 0x5ed5U, 0x4ef4U, 0x3e13U, 0x2e32U, 0x1e51U, 0x0e70U,
- 0xff9fU, 0xefbeU, 0xdfddU, 0xcffcU, 0xbf1bU, 0xaf3aU, 0x9f59U, 0x8f78U,
- 0x9188U, 0x81a9U, 0xb1caU, 0xa1ebU, 0xd10cU, 0xc12dU, 0xf14eU, 0xe16fU,
- 0x1080U, 0x00a1U, 0x30c2U, 0x20e3U, 0x5004U, 0x4025U, 0x7046U, 0x6067U,
- 0x83b9U, 0x9398U, 0xa3fbU, 0xb3daU, 0xc33dU, 0xd31cU, 0xe37fU, 0xf35eU,
- 0x02b1U, 0x1290U, 0x22f3U, 0x32d2U, 0x4235U, 0x5214U, 0x6277U, 0x7256U,
- 0xb5eaU, 0xa5cbU, 0x95a8U, 0x8589U, 0xf56eU, 0xe54fU, 0xd52cU, 0xc50dU,
- 0x34e2U, 0x24c3U, 0x14a0U, 0x0481U, 0x7466U, 0x6447U, 0x5424U, 0x4405U,
- 0xa7dbU, 0xb7faU, 0x8799U, 0x97b8U, 0xe75fU, 0xf77eU, 0xc71dU, 0xd73cU,
- 0x26d3U, 0x36f2U, 0x0691U, 0x16b0U, 0x6657U, 0x7676U, 0x4615U, 0x5634U,
- 0xd94cU, 0xc96dU, 0xf90eU, 0xe92fU, 0x99c8U, 0x89e9U, 0xb98aU, 0xa9abU,
- 0x5844U, 0x4865U, 0x7806U, 0x6827U, 0x18c0U, 0x08e1U, 0x3882U, 0x28a3U,
- 0xcb7dU, 0xdb5cU, 0xeb3fU, 0xfb1eU, 0x8bf9U, 0x9bd8U, 0xabbbU, 0xbb9aU,
- 0x4a75U, 0x5a54U, 0x6a37U, 0x7a16U, 0x0af1U, 0x1ad0U, 0x2ab3U, 0x3a92U,
- 0xfd2eU, 0xed0fU, 0xdd6cU, 0xcd4dU, 0xbdaaU, 0xad8bU, 0x9de8U, 0x8dc9U,
- 0x7c26U, 0x6c07U, 0x5c64U, 0x4c45U, 0x3ca2U, 0x2c83U, 0x1ce0U, 0x0cc1U,
- 0xef1fU, 0xff3eU, 0xcf5dU, 0xdf7cU, 0xaf9bU, 0xbfbaU, 0x8fd9U, 0x9ff8U,
- 0x6e17U, 0x7e36U, 0x4e55U, 0x5e74U, 0x2e93U, 0x3eb2U, 0x0ed1U, 0x1ef0U
-};
-
-/*
- * udf_crc
- *
- * PURPOSE
- * Calculate a 16-bit CRC checksum using ITU-T V.41 polynomial.
- *
- * DESCRIPTION
- * The OSTA-UDF(tm) 1.50 standard states that using CRCs is mandatory.
- * The polynomial used is: x^16 + x^12 + x^15 + 1
- *
- * PRE-CONDITIONS
- * data Pointer to the data block.
- * size Size of the data block.
- *
- * POST-CONDITIONS
- * <return> CRC of the data block.
- *
- * HISTORY
- * July 21, 1997 - Andrew E. Mileski
- * Adapted from OSTA-UDF(tm) 1.50 standard.
- */
-uint16_t udf_crc(uint8_t *data, uint32_t size, uint16_t crc)
-{
- while (size--)
- crc = crc_table[(crc >> 8 ^ *(data++)) & 0xffU] ^ (crc << 8);
-
- return crc;
-}
-
-/****************************************************************************/
-#if defined(TEST)
-
-/*
- * PURPOSE
- * Test udf_crc()
- *
- * HISTORY
- * July 21, 1997 - Andrew E. Mileski
- * Adapted from OSTA-UDF(tm) 1.50 standard.
- */
-
-unsigned char bytes[] = { 0x70U, 0x6AU, 0x77U };
-
-int main(void)
-{
- unsigned short x;
-
- x = udf_crc(bytes, sizeof bytes);
- printf("udf_crc: calculated = %4.4x, correct = %4.4x\n", x, 0x3299U);
-
- return 0;
-}
-
-#endif /* defined(TEST) */
-
-/****************************************************************************/
-#if defined(GENERATE)
-
-/*
- * PURPOSE
- * Generate a table for fast 16-bit CRC calculations (any polynomial).
- *
- * DESCRIPTION
- * The ITU-T V.41 polynomial is 010041.
- *
- * HISTORY
- * July 21, 1997 - Andrew E. Mileski
- * Adapted from OSTA-UDF(tm) 1.50 standard.
- */
-
-#include <stdio.h>
-
-int main(int argc, char **argv)
-{
- unsigned long crc, poly;
- int n, i;
-
- /* Get the polynomial */
- sscanf(argv[1], "%lo", &poly);
- if (poly & 0xffff0000U) {
- fprintf(stderr, "polynomial is too large\en");
- exit(1);
- }
-
- printf("/* CRC 0%o */\n", poly);
-
- /* Create a table */
- printf("static unsigned short crc_table[256] = {\n");
- for (n = 0; n < 256; n++) {
- if (n % 8 == 0)
- printf("\t");
- crc = n << 8;
- for (i = 0; i < 8; i++) {
- if (crc & 0x8000U)
- crc = (crc << 1) ^ poly;
- else
- crc <<= 1;
- crc &= 0xFFFFU;
- }
- if (n == 255)
- printf("0x%04xU ", crc);
- else
- printf("0x%04xU, ", crc);
- if (n % 8 == 7)
- printf("\n");
- }
- printf("};\n");
-
- return 0;
-}
-
-#endif /* defined(GENERATE) */
static int do_udf_readdir(struct inode *dir, struct file *filp,
filldir_t filldir, void *dirent)
{
- struct udf_fileident_bh fibh;
+ struct udf_fileident_bh fibh = { .sbh = NULL, .ebh = NULL};
struct fileIdentDesc *fi = NULL;
struct fileIdentDesc cfi;
int block, iblock;
loff_t nf_pos = (filp->f_pos - 1) << 2;
int flen;
- char fname[UDF_NAME_LEN];
+ char *fname = NULL;
char *nameptr;
uint16_t liu;
uint8_t lfi;
kernel_lb_addr eloc;
uint32_t elen;
sector_t offset;
- int i, num;
+ int i, num, ret = 0;
unsigned int dt_type;
struct extent_position epos = { NULL, 0, {0, 0} };
struct udf_inode_info *iinfo;
if (nf_pos >= size)
- return 0;
+ goto out;
+
+ fname = kmalloc(UDF_NAME_LEN, GFP_NOFS);
+ if (!fname) {
+ ret = -ENOMEM;
+ goto out;
+ }
if (nf_pos == 0)
nf_pos = udf_ext0_offset(dir);
fibh.soffset = fibh.eoffset = nf_pos & (dir->i_sb->s_blocksize - 1);
iinfo = UDF_I(dir);
- if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
- fibh.sbh = fibh.ebh = NULL;
- } else if (inode_bmap(dir, nf_pos >> dir->i_sb->s_blocksize_bits,
- &epos, &eloc, &elen, &offset) == (EXT_RECORDED_ALLOCATED >> 30)) {
+ if (iinfo->i_alloc_type != ICBTAG_FLAG_AD_IN_ICB) {
+ if (inode_bmap(dir, nf_pos >> dir->i_sb->s_blocksize_bits,
+ &epos, &eloc, &elen, &offset)
+ != (EXT_RECORDED_ALLOCATED >> 30)) {
+ ret = -ENOENT;
+ goto out;
+ }
block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
if ((++offset << dir->i_sb->s_blocksize_bits) < elen) {
if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
}
if (!(fibh.sbh = fibh.ebh = udf_tread(dir->i_sb, block))) {
- brelse(epos.bh);
- return -EIO;
+ ret = -EIO;
+ goto out;
}
if (!(offset & ((16 >> (dir->i_sb->s_blocksize_bits - 9)) - 1))) {
brelse(bha[i]);
}
}
- } else {
- brelse(epos.bh);
- return -ENOENT;
}
while (nf_pos < size) {
fi = udf_fileident_read(dir, &nf_pos, &fibh, &cfi, &epos, &eloc,
&elen, &offset);
- if (!fi) {
- if (fibh.sbh != fibh.ebh)
- brelse(fibh.ebh);
- brelse(fibh.sbh);
- brelse(epos.bh);
- return 0;
- }
+ if (!fi)
+ goto out;
liu = le16_to_cpu(cfi.lengthOfImpUse);
lfi = cfi.lengthFileIdent;
dt_type = DT_UNKNOWN;
}
- if (flen) {
- if (filldir(dirent, fname, flen, filp->f_pos, iblock, dt_type) < 0) {
- if (fibh.sbh != fibh.ebh)
- brelse(fibh.ebh);
- brelse(fibh.sbh);
- brelse(epos.bh);
- return 0;
- }
- }
+ if (flen && filldir(dirent, fname, flen, filp->f_pos,
+ iblock, dt_type) < 0)
+ goto out;
} /* end while */
filp->f_pos = (nf_pos >> 2) + 1;
+out:
if (fibh.sbh != fibh.ebh)
brelse(fibh.ebh);
brelse(fibh.sbh);
brelse(epos.bh);
+ kfree(fname);
- return 0;
+ return ret;
}
-/*
- * udf_readdir
- *
- * PURPOSE
- * Read a directory entry.
- *
- * DESCRIPTION
- * Optional - sys_getdents() will return -ENOTDIR if this routine is not
- * available.
- *
- * Refer to sys_getdents() in fs/readdir.c
- * sys_getdents() -> .
- *
- * PRE-CONDITIONS
- * filp Pointer to directory file.
- * buf Pointer to directory entry buffer.
- * filldir Pointer to filldir function.
- *
- * POST-CONDITIONS
- * <return> >=0 on success.
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
- */
-
static int udf_readdir(struct file *filp, void *dirent, filldir_t filldir)
{
struct inode *dir = filp->f_path.dentry->d_inode;
uint8_t microseconds;
} __attribute__ ((packed)) timestamp;
-typedef struct {
- uint16_t typeAndTimezone;
- int16_t year;
- uint8_t month;
- uint8_t day;
- uint8_t hour;
- uint8_t minute;
- uint8_t second;
- uint8_t centiseconds;
- uint8_t hundredsOfMicroseconds;
- uint8_t microseconds;
-} __attribute__ ((packed)) kernel_timestamp;
-
/* Type and Time Zone (ECMA 167r3 1/7.3.1) */
#define TIMESTAMP_TYPE_MASK 0xF000
#define TIMESTAMP_TYPE_CUT 0x0000
#include "udfdecl.h"
#include <linux/fs.h>
-#include <linux/udf_fs.h>
#include <asm/uaccess.h>
#include <linux/kernel.h>
#include <linux/string.h> /* memset */
return retval;
}
-/*
- * udf_ioctl
- *
- * PURPOSE
- * Issue an ioctl.
- *
- * DESCRIPTION
- * Optional - sys_ioctl() will return -ENOTTY if this routine is not
- * available, and the ioctl cannot be handled without filesystem help.
- *
- * sys_ioctl() handles these ioctls that apply only to regular files:
- * FIBMAP [requires udf_block_map()], FIGETBSZ, FIONREAD
- * These ioctls are also handled by sys_ioctl():
- * FIOCLEX, FIONCLEX, FIONBIO, FIOASYNC
- * All other ioctls are passed to the filesystem.
- *
- * Refer to sys_ioctl() in fs/ioctl.c
- * sys_ioctl() -> .
- *
- * PRE-CONDITIONS
- * inode Pointer to inode that ioctl was issued on.
- * filp Pointer to file that ioctl was issued on.
- * cmd The ioctl command.
- * arg The ioctl argument [can be interpreted as a
- * user-space pointer if desired].
- *
- * POST-CONDITIONS
- * <return> Success (>=0) or an error code (<=0) that
- * sys_ioctl() will return.
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
- */
int udf_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
unsigned long arg)
{
return result;
}
-/*
- * udf_release_file
- *
- * PURPOSE
- * Called when all references to the file are closed
- *
- * DESCRIPTION
- * Discard prealloced blocks
- *
- * HISTORY
- *
- */
static int udf_release_file(struct inode *inode, struct file *filp)
{
if (filp->f_mode & FMODE_WRITE) {
#include "udfdecl.h"
#include <linux/fs.h>
#include <linux/quotaops.h>
-#include <linux/udf_fs.h>
#include <linux/sched.h>
#include <linux/slab.h>
struct logicalVolIntegrityDescImpUse *lvidiu =
udf_sb_lvidiu(sbi);
if (S_ISDIR(inode->i_mode))
- lvidiu->numDirs =
- cpu_to_le32(le32_to_cpu(lvidiu->numDirs) - 1);
+ le32_add_cpu(&lvidiu->numDirs, -1);
else
- lvidiu->numFiles =
- cpu_to_le32(le32_to_cpu(lvidiu->numFiles) - 1);
+ le32_add_cpu(&lvidiu->numFiles, -1);
mark_buffer_dirty(sbi->s_lvid_bh);
}
lvhd = (struct logicalVolHeaderDesc *)
(lvid->logicalVolContentsUse);
if (S_ISDIR(mode))
- lvidiu->numDirs =
- cpu_to_le32(le32_to_cpu(lvidiu->numDirs) + 1);
+ le32_add_cpu(&lvidiu->numDirs, 1);
else
- lvidiu->numFiles =
- cpu_to_le32(le32_to_cpu(lvidiu->numFiles) + 1);
+ le32_add_cpu(&lvidiu->numFiles, 1);
iinfo->i_unique = uniqueID = le64_to_cpu(lvhd->uniqueID);
if (!(++uniqueID & 0x00000000FFFFFFFFUL))
uniqueID += 16;
#include <linux/buffer_head.h>
#include <linux/writeback.h>
#include <linux/slab.h>
+#include <linux/crc-itu-t.h>
#include "udf_i.h"
#include "udf_sb.h"
struct extent_position *);
static int udf_get_block(struct inode *, sector_t, struct buffer_head *, int);
-/*
- * udf_delete_inode
- *
- * PURPOSE
- * Clean-up before the specified inode is destroyed.
- *
- * DESCRIPTION
- * This routine is called when the kernel destroys an inode structure
- * ie. when iput() finds i_count == 0.
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
- *
- * Called at the last iput() if i_nlink is zero.
- */
+
void udf_delete_inode(struct inode *inode)
{
truncate_inode_pages(&inode->i_data, 0);
lock_kernel();
- if (block < 0)
- goto abort_negative;
-
iinfo = UDF_I(inode);
if (block == iinfo->i_next_alloc_block + 1) {
iinfo->i_next_alloc_block++;
abort:
unlock_kernel();
return err;
-
-abort_negative:
- udf_warning(inode->i_sb, "udf_get_block", "block < 0");
- goto abort;
}
static struct buffer_head *udf_getblk(struct inode *inode, long block,
fe = (struct fileEntry *)bh->b_data;
if (fe->icbTag.strategyType == cpu_to_le16(4096)) {
- struct buffer_head *ibh = NULL, *nbh = NULL;
- struct indirectEntry *ie;
+ struct buffer_head *ibh;
ibh = udf_read_ptagged(inode->i_sb, iinfo->i_location, 1,
&ident);
- if (ident == TAG_IDENT_IE) {
- if (ibh) {
- kernel_lb_addr loc;
- ie = (struct indirectEntry *)ibh->b_data;
-
- loc = lelb_to_cpu(ie->indirectICB.extLocation);
-
- if (ie->indirectICB.extLength &&
- (nbh = udf_read_ptagged(inode->i_sb, loc, 0,
- &ident))) {
- if (ident == TAG_IDENT_FE ||
- ident == TAG_IDENT_EFE) {
- memcpy(&iinfo->i_location,
- &loc,
- sizeof(kernel_lb_addr));
- brelse(bh);
- brelse(ibh);
- brelse(nbh);
- __udf_read_inode(inode);
- return;
- } else {
- brelse(nbh);
- brelse(ibh);
- }
- } else {
+ if (ident == TAG_IDENT_IE && ibh) {
+ struct buffer_head *nbh = NULL;
+ kernel_lb_addr loc;
+ struct indirectEntry *ie;
+
+ ie = (struct indirectEntry *)ibh->b_data;
+ loc = lelb_to_cpu(ie->indirectICB.extLocation);
+
+ if (ie->indirectICB.extLength &&
+ (nbh = udf_read_ptagged(inode->i_sb, loc, 0,
+ &ident))) {
+ if (ident == TAG_IDENT_FE ||
+ ident == TAG_IDENT_EFE) {
+ memcpy(&iinfo->i_location,
+ &loc,
+ sizeof(kernel_lb_addr));
+ brelse(bh);
brelse(ibh);
+ brelse(nbh);
+ __udf_read_inode(inode);
+ return;
}
+ brelse(nbh);
}
- } else {
- brelse(ibh);
}
+ brelse(ibh);
} else if (fe->icbTag.strategyType != cpu_to_le16(4)) {
printk(KERN_ERR "udf: unsupported strategy type: %d\n",
le16_to_cpu(fe->icbTag.strategyType));
{
struct fileEntry *fe;
struct extendedFileEntry *efe;
- time_t convtime;
- long convtime_usec;
int offset;
struct udf_sb_info *sbi = UDF_SB(inode->i_sb);
struct udf_inode_info *iinfo = UDF_I(inode);
inode->i_blocks = le64_to_cpu(fe->logicalBlocksRecorded) <<
(inode->i_sb->s_blocksize_bits - 9);
- if (udf_stamp_to_time(&convtime, &convtime_usec,
- lets_to_cpu(fe->accessTime))) {
- inode->i_atime.tv_sec = convtime;
- inode->i_atime.tv_nsec = convtime_usec * 1000;
- } else {
+ if (!udf_disk_stamp_to_time(&inode->i_atime, fe->accessTime))
inode->i_atime = sbi->s_record_time;
- }
- if (udf_stamp_to_time(&convtime, &convtime_usec,
- lets_to_cpu(fe->modificationTime))) {
- inode->i_mtime.tv_sec = convtime;
- inode->i_mtime.tv_nsec = convtime_usec * 1000;
- } else {
+ if (!udf_disk_stamp_to_time(&inode->i_mtime,
+ fe->modificationTime))
inode->i_mtime = sbi->s_record_time;
- }
- if (udf_stamp_to_time(&convtime, &convtime_usec,
- lets_to_cpu(fe->attrTime))) {
- inode->i_ctime.tv_sec = convtime;
- inode->i_ctime.tv_nsec = convtime_usec * 1000;
- } else {
+ if (!udf_disk_stamp_to_time(&inode->i_ctime, fe->attrTime))
inode->i_ctime = sbi->s_record_time;
- }
iinfo->i_unique = le64_to_cpu(fe->uniqueID);
iinfo->i_lenEAttr = le32_to_cpu(fe->lengthExtendedAttr);
inode->i_blocks = le64_to_cpu(efe->logicalBlocksRecorded) <<
(inode->i_sb->s_blocksize_bits - 9);
- if (udf_stamp_to_time(&convtime, &convtime_usec,
- lets_to_cpu(efe->accessTime))) {
- inode->i_atime.tv_sec = convtime;
- inode->i_atime.tv_nsec = convtime_usec * 1000;
- } else {
+ if (!udf_disk_stamp_to_time(&inode->i_atime, efe->accessTime))
inode->i_atime = sbi->s_record_time;
- }
- if (udf_stamp_to_time(&convtime, &convtime_usec,
- lets_to_cpu(efe->modificationTime))) {
- inode->i_mtime.tv_sec = convtime;
- inode->i_mtime.tv_nsec = convtime_usec * 1000;
- } else {
+ if (!udf_disk_stamp_to_time(&inode->i_mtime,
+ efe->modificationTime))
inode->i_mtime = sbi->s_record_time;
- }
- if (udf_stamp_to_time(&convtime, &convtime_usec,
- lets_to_cpu(efe->createTime))) {
- iinfo->i_crtime.tv_sec = convtime;
- iinfo->i_crtime.tv_nsec = convtime_usec * 1000;
- } else {
+ if (!udf_disk_stamp_to_time(&iinfo->i_crtime, efe->createTime))
iinfo->i_crtime = sbi->s_record_time;
- }
- if (udf_stamp_to_time(&convtime, &convtime_usec,
- lets_to_cpu(efe->attrTime))) {
- inode->i_ctime.tv_sec = convtime;
- inode->i_ctime.tv_nsec = convtime_usec * 1000;
- } else {
+ if (!udf_disk_stamp_to_time(&inode->i_ctime, efe->attrTime))
inode->i_ctime = sbi->s_record_time;
- }
iinfo->i_unique = le64_to_cpu(efe->uniqueID);
iinfo->i_lenEAttr = le32_to_cpu(efe->lengthExtendedAttr);
case ICBTAG_FILE_TYPE_REALTIME:
case ICBTAG_FILE_TYPE_REGULAR:
case ICBTAG_FILE_TYPE_UNDEF:
+ case ICBTAG_FILE_TYPE_VAT20:
if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
inode->i_data.a_ops = &udf_adinicb_aops;
else
inode->i_op = &page_symlink_inode_operations;
inode->i_mode = S_IFLNK | S_IRWXUGO;
break;
+ case ICBTAG_FILE_TYPE_MAIN:
+ udf_debug("METADATA FILE-----\n");
+ break;
+ case ICBTAG_FILE_TYPE_MIRROR:
+ udf_debug("METADATA MIRROR FILE-----\n");
+ break;
+ case ICBTAG_FILE_TYPE_BITMAP:
+ udf_debug("METADATA BITMAP FILE-----\n");
+ break;
default:
printk(KERN_ERR "udf: udf_fill_inode(ino %ld) failed unknown "
"file type=%d\n", inode->i_ino,
return mode;
}
-/*
- * udf_write_inode
- *
- * PURPOSE
- * Write out the specified inode.
- *
- * DESCRIPTION
- * This routine is called whenever an inode is synced.
- * Currently this routine is just a placeholder.
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
- */
-
int udf_write_inode(struct inode *inode, int sync)
{
int ret;
uint32_t udfperms;
uint16_t icbflags;
uint16_t crclen;
- kernel_timestamp cpu_time;
int err = 0;
struct udf_sb_info *sbi = UDF_SB(inode->i_sb);
unsigned char blocksize_bits = inode->i_sb->s_blocksize_bits;
iinfo->i_location.
logicalBlockNum);
use->descTag.descCRCLength = cpu_to_le16(crclen);
- use->descTag.descCRC = cpu_to_le16(udf_crc((char *)use +
- sizeof(tag), crclen,
- 0));
+ use->descTag.descCRC = cpu_to_le16(crc_itu_t(0, (char *)use +
+ sizeof(tag),
+ crclen));
use->descTag.tagChecksum = udf_tag_checksum(&use->descTag);
mark_buffer_dirty(bh);
(inode->i_blocks + (1 << (blocksize_bits - 9)) - 1) >>
(blocksize_bits - 9));
- if (udf_time_to_stamp(&cpu_time, inode->i_atime))
- fe->accessTime = cpu_to_lets(cpu_time);
- if (udf_time_to_stamp(&cpu_time, inode->i_mtime))
- fe->modificationTime = cpu_to_lets(cpu_time);
- if (udf_time_to_stamp(&cpu_time, inode->i_ctime))
- fe->attrTime = cpu_to_lets(cpu_time);
+ udf_time_to_disk_stamp(&fe->accessTime, inode->i_atime);
+ udf_time_to_disk_stamp(&fe->modificationTime, inode->i_mtime);
+ udf_time_to_disk_stamp(&fe->attrTime, inode->i_ctime);
memset(&(fe->impIdent), 0, sizeof(regid));
strcpy(fe->impIdent.ident, UDF_ID_DEVELOPER);
fe->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
iinfo->i_crtime.tv_nsec > inode->i_ctime.tv_nsec))
iinfo->i_crtime = inode->i_ctime;
- if (udf_time_to_stamp(&cpu_time, inode->i_atime))
- efe->accessTime = cpu_to_lets(cpu_time);
- if (udf_time_to_stamp(&cpu_time, inode->i_mtime))
- efe->modificationTime = cpu_to_lets(cpu_time);
- if (udf_time_to_stamp(&cpu_time, iinfo->i_crtime))
- efe->createTime = cpu_to_lets(cpu_time);
- if (udf_time_to_stamp(&cpu_time, inode->i_ctime))
- efe->attrTime = cpu_to_lets(cpu_time);
+ udf_time_to_disk_stamp(&efe->accessTime, inode->i_atime);
+ udf_time_to_disk_stamp(&efe->modificationTime, inode->i_mtime);
+ udf_time_to_disk_stamp(&efe->createTime, iinfo->i_crtime);
+ udf_time_to_disk_stamp(&efe->attrTime, inode->i_ctime);
memset(&(efe->impIdent), 0, sizeof(regid));
strcpy(efe->impIdent.ident, UDF_ID_DEVELOPER);
crclen += iinfo->i_lenEAttr + iinfo->i_lenAlloc -
sizeof(tag);
fe->descTag.descCRCLength = cpu_to_le16(crclen);
- fe->descTag.descCRC = cpu_to_le16(udf_crc((char *)fe + sizeof(tag),
- crclen, 0));
+ fe->descTag.descCRC = cpu_to_le16(crc_itu_t(0, (char *)fe + sizeof(tag),
+ crclen));
fe->descTag.tagChecksum = udf_tag_checksum(&fe->descTag);
/* write the data blocks */
if (epos->bh) {
aed = (struct allocExtDesc *)epos->bh->b_data;
- aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(
- aed->lengthAllocDescs) + adsize);
+ le32_add_cpu(&aed->lengthAllocDescs, adsize);
} else {
iinfo->i_lenAlloc += adsize;
mark_inode_dirty(inode);
mark_inode_dirty(inode);
} else {
aed = (struct allocExtDesc *)epos->bh->b_data;
- aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) +
- adsize);
+ le32_add_cpu(&aed->lengthAllocDescs, adsize);
if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) ||
UDF_SB(inode->i_sb)->s_udfrev >= 0x0201)
udf_update_tag(epos->bh->b_data,
mark_inode_dirty(inode);
} else {
aed = (struct allocExtDesc *)oepos.bh->b_data;
- aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) -
- (2 * adsize));
+ le32_add_cpu(&aed->lengthAllocDescs, -(2 * adsize));
if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) ||
UDF_SB(inode->i_sb)->s_udfrev >= 0x0201)
udf_update_tag(oepos.bh->b_data,
mark_inode_dirty(inode);
} else {
aed = (struct allocExtDesc *)oepos.bh->b_data;
- aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) -
- adsize);
+ le32_add_cpu(&aed->lengthAllocDescs, -adsize);
if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) ||
UDF_SB(inode->i_sb)->s_udfrev >= 0x0201)
udf_update_tag(oepos.bh->b_data,
int8_t etype;
struct udf_inode_info *iinfo;
- if (block < 0) {
- printk(KERN_ERR "udf: inode_bmap: block < 0\n");
- return -1;
- }
-
iinfo = UDF_I(inode);
pos->offset = 0;
pos->block = iinfo->i_location;
#include <linux/cdrom.h>
#include <asm/uaccess.h>
-#include <linux/udf_fs.h>
#include "udf_sb.h"
unsigned int udf_get_last_session(struct super_block *sb)
#include <linux/fs.h>
#include <linux/string.h>
-#include <linux/udf_fs.h>
#include <linux/buffer_head.h>
+#include <linux/crc-itu-t.h>
#include "udf_i.h"
#include "udf_sb.h"
/* rewrite CRC + checksum of eahd */
crclen = sizeof(struct extendedAttrHeaderDesc) - sizeof(tag);
eahd->descTag.descCRCLength = cpu_to_le16(crclen);
- eahd->descTag.descCRC = cpu_to_le16(udf_crc((char *)eahd +
- sizeof(tag), crclen, 0));
+ eahd->descTag.descCRC = cpu_to_le16(crc_itu_t(0, (char *)eahd +
+ sizeof(tag), crclen));
eahd->descTag.tagChecksum = udf_tag_checksum(&eahd->descTag);
iinfo->i_lenEAttr += size;
return (struct genericFormat *)&ea[offset];
{
tag *tag_p;
struct buffer_head *bh = NULL;
- struct udf_sb_info *sbi = UDF_SB(sb);
/* Read the block */
if (block == 0xFFFFFFFF)
return NULL;
- bh = udf_tread(sb, block + sbi->s_session);
+ bh = udf_tread(sb, block);
if (!bh) {
udf_debug("block=%d, location=%d: read failed\n",
- block + sbi->s_session, location);
+ block, location);
return NULL;
}
if (location != le32_to_cpu(tag_p->tagLocation)) {
udf_debug("location mismatch block %u, tag %u != %u\n",
- block + sbi->s_session,
- le32_to_cpu(tag_p->tagLocation), location);
+ block, le32_to_cpu(tag_p->tagLocation), location);
goto error_out;
}
/* Verify the descriptor CRC */
if (le16_to_cpu(tag_p->descCRCLength) + sizeof(tag) > sb->s_blocksize ||
- le16_to_cpu(tag_p->descCRC) == udf_crc(bh->b_data + sizeof(tag),
- le16_to_cpu(tag_p->descCRCLength), 0))
+ le16_to_cpu(tag_p->descCRC) == crc_itu_t(0,
+ bh->b_data + sizeof(tag),
+ le16_to_cpu(tag_p->descCRCLength)))
return bh;
- udf_debug("Crc failure block %d: crc = %d, crclen = %d\n",
- block + sbi->s_session, le16_to_cpu(tag_p->descCRC),
- le16_to_cpu(tag_p->descCRCLength));
+ udf_debug("Crc failure block %d: crc = %d, crclen = %d\n", block,
+ le16_to_cpu(tag_p->descCRC), le16_to_cpu(tag_p->descCRCLength));
error_out:
brelse(bh);
length -= sizeof(tag);
tptr->descCRCLength = cpu_to_le16(length);
- tptr->descCRC = cpu_to_le16(udf_crc(data + sizeof(tag), length, 0));
+ tptr->descCRC = cpu_to_le16(crc_itu_t(0, data + sizeof(tag), length));
tptr->tagChecksum = udf_tag_checksum(tptr);
}
#include <linux/smp_lock.h>
#include <linux/buffer_head.h>
#include <linux/sched.h>
+#include <linux/crc-itu-t.h>
static inline int udf_match(int len1, const char *name1, int len2,
const char *name2)
memset(fibh->ebh->b_data, 0x00, padlen + offset);
}
- crc = udf_crc((uint8_t *)cfi + sizeof(tag),
- sizeof(struct fileIdentDesc) - sizeof(tag), 0);
+ crc = crc_itu_t(0, (uint8_t *)cfi + sizeof(tag),
+ sizeof(struct fileIdentDesc) - sizeof(tag));
if (fibh->sbh == fibh->ebh) {
- crc = udf_crc((uint8_t *)sfi->impUse,
+ crc = crc_itu_t(crc, (uint8_t *)sfi->impUse,
crclen + sizeof(tag) -
- sizeof(struct fileIdentDesc), crc);
+ sizeof(struct fileIdentDesc));
} else if (sizeof(struct fileIdentDesc) >= -fibh->soffset) {
- crc = udf_crc(fibh->ebh->b_data +
+ crc = crc_itu_t(crc, fibh->ebh->b_data +
sizeof(struct fileIdentDesc) +
fibh->soffset,
crclen + sizeof(tag) -
- sizeof(struct fileIdentDesc),
- crc);
+ sizeof(struct fileIdentDesc));
} else {
- crc = udf_crc((uint8_t *)sfi->impUse,
- -fibh->soffset - sizeof(struct fileIdentDesc),
- crc);
- crc = udf_crc(fibh->ebh->b_data, fibh->eoffset, crc);
+ crc = crc_itu_t(crc, (uint8_t *)sfi->impUse,
+ -fibh->soffset - sizeof(struct fileIdentDesc));
+ crc = crc_itu_t(crc, fibh->ebh->b_data, fibh->eoffset);
}
cfi->descTag.descCRC = cpu_to_le16(crc);
struct fileIdentDesc *fi = NULL;
loff_t f_pos;
int block, flen;
- char fname[UDF_NAME_LEN];
+ char *fname = NULL;
char *nameptr;
uint8_t lfi;
uint16_t liu;
size = udf_ext0_offset(dir) + dir->i_size;
f_pos = udf_ext0_offset(dir);
+ fibh->sbh = fibh->ebh = NULL;
fibh->soffset = fibh->eoffset = f_pos & (dir->i_sb->s_blocksize - 1);
- if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
- fibh->sbh = fibh->ebh = NULL;
- else if (inode_bmap(dir, f_pos >> dir->i_sb->s_blocksize_bits,
- &epos, &eloc, &elen, &offset) ==
- (EXT_RECORDED_ALLOCATED >> 30)) {
+ if (dinfo->i_alloc_type != ICBTAG_FLAG_AD_IN_ICB) {
+ if (inode_bmap(dir, f_pos >> dir->i_sb->s_blocksize_bits, &epos,
+ &eloc, &elen, &offset) != (EXT_RECORDED_ALLOCATED >> 30))
+ goto out_err;
block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
if ((++offset << dir->i_sb->s_blocksize_bits) < elen) {
if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
offset = 0;
fibh->sbh = fibh->ebh = udf_tread(dir->i_sb, block);
- if (!fibh->sbh) {
- brelse(epos.bh);
- return NULL;
- }
- } else {
- brelse(epos.bh);
- return NULL;
+ if (!fibh->sbh)
+ goto out_err;
}
+ fname = kmalloc(UDF_NAME_LEN, GFP_NOFS);
+ if (!fname)
+ goto out_err;
+
while (f_pos < size) {
fi = udf_fileident_read(dir, &f_pos, fibh, cfi, &epos, &eloc,
&elen, &offset);
- if (!fi) {
- if (fibh->sbh != fibh->ebh)
- brelse(fibh->ebh);
- brelse(fibh->sbh);
- brelse(epos.bh);
- return NULL;
- }
+ if (!fi)
+ goto out_err;
liu = le16_to_cpu(cfi->lengthOfImpUse);
lfi = cfi->lengthFileIdent;
flen = udf_get_filename(dir->i_sb, nameptr, fname, lfi);
if (flen && udf_match(flen, fname, dentry->d_name.len,
- dentry->d_name.name)) {
- brelse(epos.bh);
- return fi;
- }
+ dentry->d_name.name))
+ goto out_ok;
}
+out_err:
+ fi = NULL;
if (fibh->sbh != fibh->ebh)
brelse(fibh->ebh);
brelse(fibh->sbh);
+out_ok:
brelse(epos.bh);
+ kfree(fname);
- return NULL;
+ return fi;
}
-/*
- * udf_lookup
- *
- * PURPOSE
- * Look-up the inode for a given name.
- *
- * DESCRIPTION
- * Required - lookup_dentry() will return -ENOTDIR if this routine is not
- * available for a directory. The filesystem is useless if this routine is
- * not available for at least the filesystem's root directory.
- *
- * This routine is passed an incomplete dentry - it must be completed by
- * calling d_add(dentry, inode). If the name does not exist, then the
- * specified inode must be set to null. An error should only be returned
- * when the lookup fails for a reason other than the name not existing.
- * Note that the directory inode semaphore is held during the call.
- *
- * Refer to lookup_dentry() in fs/namei.c
- * lookup_dentry() -> lookup() -> real_lookup() -> .
- *
- * PRE-CONDITIONS
- * dir Pointer to inode of parent directory.
- * dentry Pointer to dentry to complete.
- * nd Pointer to lookup nameidata
- *
- * POST-CONDITIONS
- * <return> Zero on success.
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
- */
-
static struct dentry *udf_lookup(struct inode *dir, struct dentry *dentry,
struct nameidata *nd)
{
{
struct super_block *sb = dir->i_sb;
struct fileIdentDesc *fi = NULL;
- char name[UDF_NAME_LEN], fname[UDF_NAME_LEN];
+ char *name = NULL;
int namelen;
loff_t f_pos;
- int flen;
- char *nameptr;
loff_t size = udf_ext0_offset(dir) + dir->i_size;
int nfidlen;
uint8_t lfi;
struct extent_position epos = {};
struct udf_inode_info *dinfo;
+ fibh->sbh = fibh->ebh = NULL;
+ name = kmalloc(UDF_NAME_LEN, GFP_NOFS);
+ if (!name) {
+ *err = -ENOMEM;
+ goto out_err;
+ }
+
if (dentry) {
if (!dentry->d_name.len) {
*err = -EINVAL;
- return NULL;
+ goto out_err;
}
namelen = udf_put_filename(sb, dentry->d_name.name, name,
dentry->d_name.len);
if (!namelen) {
*err = -ENAMETOOLONG;
- return NULL;
+ goto out_err;
}
} else {
namelen = 0;
fibh->soffset = fibh->eoffset = f_pos & (dir->i_sb->s_blocksize - 1);
dinfo = UDF_I(dir);
- if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
- fibh->sbh = fibh->ebh = NULL;
- else if (inode_bmap(dir, f_pos >> dir->i_sb->s_blocksize_bits,
- &epos, &eloc, &elen, &offset) ==
- (EXT_RECORDED_ALLOCATED >> 30)) {
+ if (dinfo->i_alloc_type != ICBTAG_FLAG_AD_IN_ICB) {
+ if (inode_bmap(dir, f_pos >> dir->i_sb->s_blocksize_bits, &epos,
+ &eloc, &elen, &offset) != (EXT_RECORDED_ALLOCATED >> 30)) {
+ block = udf_get_lb_pblock(dir->i_sb,
+ dinfo->i_location, 0);
+ fibh->soffset = fibh->eoffset = sb->s_blocksize;
+ goto add;
+ }
block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
if ((++offset << dir->i_sb->s_blocksize_bits) < elen) {
if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
fibh->sbh = fibh->ebh = udf_tread(dir->i_sb, block);
if (!fibh->sbh) {
- brelse(epos.bh);
*err = -EIO;
- return NULL;
+ goto out_err;
}
block = dinfo->i_location.logicalBlockNum;
- } else {
- block = udf_get_lb_pblock(dir->i_sb, dinfo->i_location, 0);
- fibh->sbh = fibh->ebh = NULL;
- fibh->soffset = fibh->eoffset = sb->s_blocksize;
- goto add;
}
while (f_pos < size) {
&elen, &offset);
if (!fi) {
- if (fibh->sbh != fibh->ebh)
- brelse(fibh->ebh);
- brelse(fibh->sbh);
- brelse(epos.bh);
*err = -EIO;
- return NULL;
+ goto out_err;
}
liu = le16_to_cpu(cfi->lengthOfImpUse);
lfi = cfi->lengthFileIdent;
- if (fibh->sbh == fibh->ebh)
- nameptr = fi->fileIdent + liu;
- else {
- int poffset; /* Unpaded ending offset */
-
- poffset = fibh->soffset + sizeof(struct fileIdentDesc) +
- liu + lfi;
-
- if (poffset >= lfi)
- nameptr = (char *)(fibh->ebh->b_data +
- poffset - lfi);
- else {
- nameptr = fname;
- memcpy(nameptr, fi->fileIdent + liu,
- lfi - poffset);
- memcpy(nameptr + lfi - poffset,
- fibh->ebh->b_data, poffset);
- }
- }
-
if ((cfi->fileCharacteristics & FID_FILE_CHAR_DELETED) != 0) {
if (((sizeof(struct fileIdentDesc) +
liu + lfi + 3) & ~3) == nfidlen) {
- brelse(epos.bh);
cfi->descTag.tagSerialNum = cpu_to_le16(1);
cfi->fileVersionNum = cpu_to_le16(1);
cfi->fileCharacteristics = 0;
cfi->lengthOfImpUse = cpu_to_le16(0);
if (!udf_write_fi(dir, cfi, fi, fibh, NULL,
name))
- return fi;
+ goto out_ok;
else {
*err = -EIO;
- return NULL;
+ goto out_err;
}
}
}
-
- if (!lfi || !dentry)
- continue;
-
- flen = udf_get_filename(dir->i_sb, nameptr, fname, lfi);
- if (flen && udf_match(flen, fname, dentry->d_name.len,
- dentry->d_name.name)) {
- if (fibh->sbh != fibh->ebh)
- brelse(fibh->ebh);
- brelse(fibh->sbh);
- brelse(epos.bh);
- *err = -EEXIST;
- return NULL;
- }
}
add:
fibh->sbh = fibh->ebh =
udf_expand_dir_adinicb(dir, &block, err);
if (!fibh->sbh)
- return NULL;
+ goto out_err;
epos.block = dinfo->i_location;
epos.offset = udf_file_entry_alloc_offset(dir);
/* Load extent udf_expand_dir_adinicb() has created */
dir->i_sb->s_blocksize_bits);
fibh->ebh = udf_bread(dir,
f_pos >> dir->i_sb->s_blocksize_bits, 1, err);
- if (!fibh->ebh) {
- brelse(epos.bh);
- brelse(fibh->sbh);
- return NULL;
- }
+ if (!fibh->ebh)
+ goto out_err;
if (!fibh->soffset) {
if (udf_next_aext(dir, &epos, &eloc, &elen, 1) ==
cfi->lengthFileIdent = namelen;
cfi->lengthOfImpUse = cpu_to_le16(0);
if (!udf_write_fi(dir, cfi, fi, fibh, NULL, name)) {
- brelse(epos.bh);
dir->i_size += nfidlen;
if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
dinfo->i_lenAlloc += nfidlen;
mark_inode_dirty(dir);
- return fi;
+ goto out_ok;
} else {
- brelse(epos.bh);
- if (fibh->sbh != fibh->ebh)
- brelse(fibh->ebh);
- brelse(fibh->sbh);
*err = -EIO;
- return NULL;
+ goto out_err;
}
+
+out_err:
+ fi = NULL;
+ if (fibh->sbh != fibh->ebh)
+ brelse(fibh->ebh);
+ brelse(fibh->sbh);
+out_ok:
+ brelse(epos.bh);
+ kfree(name);
+ return fi;
}
static int udf_delete_entry(struct inode *inode, struct fileIdentDesc *fi,
char *ea;
int err;
int block;
- char name[UDF_NAME_LEN];
+ char *name = NULL;
int namelen;
struct buffer_head *bh;
struct udf_inode_info *iinfo;
if (!inode)
goto out;
+ name = kmalloc(UDF_NAME_LEN, GFP_NOFS);
+ if (!name) {
+ err = -ENOMEM;
+ goto out_no_entry;
+ }
+
iinfo = UDF_I(inode);
inode->i_mode = S_IFLNK | S_IRWXUGO;
inode->i_data.a_ops = &udf_symlink_aops;
err = 0;
out:
+ kfree(name);
unlock_kernel();
return err;
#include <linux/fs.h>
#include <linux/string.h>
-#include <linux/udf_fs.h>
#include <linux/slab.h>
#include <linux/buffer_head.h>
struct udf_sb_info *sbi = UDF_SB(sb);
struct udf_part_map *map;
struct udf_virtual_data *vdata;
- struct udf_inode_info *iinfo;
+ struct udf_inode_info *iinfo = UDF_I(sbi->s_vat_inode);
map = &sbi->s_partmaps[partition];
vdata = &map->s_type_specific.s_virtual;
- index = (sb->s_blocksize - vdata->s_start_offset) / sizeof(uint32_t);
if (block > vdata->s_num_entries) {
udf_debug("Trying to access block beyond end of VAT "
return 0xFFFFFFFF;
}
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
+ loc = le32_to_cpu(((__le32 *)(iinfo->i_ext.i_data +
+ vdata->s_start_offset))[block]);
+ goto translate;
+ }
+ index = (sb->s_blocksize - vdata->s_start_offset) / sizeof(uint32_t);
if (block >= index) {
block -= index;
newblock = 1 + (block / (sb->s_blocksize / sizeof(uint32_t)));
brelse(bh);
- iinfo = UDF_I(sbi->s_vat_inode);
+translate:
if (iinfo->i_location.partitionReferenceNum == partition) {
udf_debug("recursive call to udf_get_pblock!\n");
return 0xFFFFFFFF;
return 0;
}
+
+static uint32_t udf_try_read_meta(struct inode *inode, uint32_t block,
+ uint16_t partition, uint32_t offset)
+{
+ struct super_block *sb = inode->i_sb;
+ struct udf_part_map *map;
+ kernel_lb_addr eloc;
+ uint32_t elen;
+ sector_t ext_offset;
+ struct extent_position epos = {};
+ uint32_t phyblock;
+
+ if (inode_bmap(inode, block, &epos, &eloc, &elen, &ext_offset) !=
+ (EXT_RECORDED_ALLOCATED >> 30))
+ phyblock = 0xFFFFFFFF;
+ else {
+ map = &UDF_SB(sb)->s_partmaps[partition];
+ /* map to sparable/physical partition desc */
+ phyblock = udf_get_pblock(sb, eloc.logicalBlockNum,
+ map->s_partition_num, ext_offset + offset);
+ }
+
+ brelse(epos.bh);
+ return phyblock;
+}
+
+uint32_t udf_get_pblock_meta25(struct super_block *sb, uint32_t block,
+ uint16_t partition, uint32_t offset)
+{
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct udf_part_map *map;
+ struct udf_meta_data *mdata;
+ uint32_t retblk;
+ struct inode *inode;
+
+ udf_debug("READING from METADATA\n");
+
+ map = &sbi->s_partmaps[partition];
+ mdata = &map->s_type_specific.s_metadata;
+ inode = mdata->s_metadata_fe ? : mdata->s_mirror_fe;
+
+ /* We shouldn't mount such media... */
+ BUG_ON(!inode);
+ retblk = udf_try_read_meta(inode, block, partition, offset);
+ if (retblk == 0xFFFFFFFF) {
+ udf_warning(sb, __func__, "error reading from METADATA, "
+ "trying to read from MIRROR");
+ inode = mdata->s_mirror_fe;
+ if (!inode)
+ return 0xFFFFFFFF;
+ retblk = udf_try_read_meta(inode, block, partition, offset);
+ }
+
+ return retblk;
+}
#include <linux/errno.h>
#include <linux/mount.h>
#include <linux/seq_file.h>
+#include <linux/bitmap.h>
+#include <linux/crc-itu-t.h>
#include <asm/byteorder.h>
-#include <linux/udf_fs.h>
#include "udf_sb.h"
#include "udf_i.h"
static int udf_remount_fs(struct super_block *, int *, char *);
static int udf_check_valid(struct super_block *, int, int);
static int udf_vrs(struct super_block *sb, int silent);
-static int udf_load_partition(struct super_block *, kernel_lb_addr *);
-static int udf_load_logicalvol(struct super_block *, struct buffer_head *,
- kernel_lb_addr *);
static void udf_load_logicalvolint(struct super_block *, kernel_extent_ad);
static void udf_find_anchor(struct super_block *);
static int udf_find_fileset(struct super_block *, kernel_lb_addr *,
kernel_lb_addr *);
-static void udf_load_pvoldesc(struct super_block *, struct buffer_head *);
static void udf_load_fileset(struct super_block *, struct buffer_head *,
kernel_lb_addr *);
-static int udf_load_partdesc(struct super_block *, struct buffer_head *);
static void udf_open_lvid(struct super_block *);
static void udf_close_lvid(struct super_block *);
static unsigned int udf_count_free(struct super_block *);
static int udf_statfs(struct dentry *, struct kstatfs *);
static int udf_show_options(struct seq_file *, struct vfsmount *);
+static void udf_error(struct super_block *sb, const char *function,
+ const char *fmt, ...);
struct logicalVolIntegrityDescImpUse *udf_sb_lvidiu(struct udf_sb_info *sbi)
{
return 0;
}
-/*
- * udf_set_blocksize
- *
- * PURPOSE
- * Set the block size to be used in all transfers.
- *
- * DESCRIPTION
- * To allow room for a DMA transfer, it is best to guess big when unsure.
- * This routine picks 2048 bytes as the blocksize when guessing. This
- * should be adequate until devices with larger block sizes become common.
- *
- * Note that the Linux kernel can currently only deal with blocksizes of
- * 512, 1024, 2048, 4096, and 8192 bytes.
- *
- * PRE-CONDITIONS
- * sb Pointer to _locked_ superblock.
- *
- * POST-CONDITIONS
- * sb->s_blocksize Blocksize.
- * sb->s_blocksize_bits log2 of blocksize.
- * <return> 0 Blocksize is valid.
- * <return> 1 Blocksize is invalid.
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
- */
-static int udf_set_blocksize(struct super_block *sb, int bsize)
-{
- if (!sb_min_blocksize(sb, bsize)) {
- udf_debug("Bad block size (%d)\n", bsize);
- printk(KERN_ERR "udf: bad block size (%d)\n", bsize);
- return 0;
- }
-
- return sb->s_blocksize;
-}
-
static int udf_vrs(struct super_block *sb, int silent)
{
struct volStructDesc *vsd = NULL;
- int sector = 32768;
+ loff_t sector = 32768;
int sectorsize;
struct buffer_head *bh = NULL;
int iso9660 = 0;
sector += (sbi->s_session << sb->s_blocksize_bits);
udf_debug("Starting at sector %u (%ld byte sectors)\n",
- (sector >> sb->s_blocksize_bits), sb->s_blocksize);
+ (unsigned int)(sector >> sb->s_blocksize_bits),
+ sb->s_blocksize);
/* Process the sequence (if applicable) */
for (; !nsr02 && !nsr03; sector += sectorsize) {
/* Read a block */
}
/*
- * udf_find_anchor
- *
- * PURPOSE
- * Find an anchor volume descriptor.
- *
- * PRE-CONDITIONS
- * sb Pointer to _locked_ superblock.
- * lastblock Last block on media.
- *
- * POST-CONDITIONS
- * <return> 1 if not found, 0 if ok
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
+ * Check whether there is an anchor block in the given block
*/
-static void udf_find_anchor(struct super_block *sb)
+static int udf_check_anchor_block(struct super_block *sb, sector_t block,
+ bool varconv)
{
- int lastblock;
struct buffer_head *bh = NULL;
+ tag *t;
uint16_t ident;
uint32_t location;
- int i;
- struct udf_sb_info *sbi;
- sbi = UDF_SB(sb);
- lastblock = sbi->s_last_block;
+ if (varconv) {
+ if (udf_fixed_to_variable(block) >=
+ sb->s_bdev->bd_inode->i_size >> sb->s_blocksize_bits)
+ return 0;
+ bh = sb_bread(sb, udf_fixed_to_variable(block));
+ }
+ else
+ bh = sb_bread(sb, block);
- if (lastblock) {
- int varlastblock = udf_variable_to_fixed(lastblock);
- int last[] = { lastblock, lastblock - 2,
- lastblock - 150, lastblock - 152,
- varlastblock, varlastblock - 2,
- varlastblock - 150, varlastblock - 152 };
-
- lastblock = 0;
-
- /* Search for an anchor volume descriptor pointer */
-
- /* according to spec, anchor is in either:
- * block 256
- * lastblock-256
- * lastblock
- * however, if the disc isn't closed, it could be 512 */
-
- for (i = 0; !lastblock && i < ARRAY_SIZE(last); i++) {
- ident = location = 0;
- if (last[i] >= 0) {
- bh = sb_bread(sb, last[i]);
- if (bh) {
- tag *t = (tag *)bh->b_data;
- ident = le16_to_cpu(t->tagIdent);
- location = le32_to_cpu(t->tagLocation);
- brelse(bh);
- }
- }
+ if (!bh)
+ return 0;
- if (ident == TAG_IDENT_AVDP) {
- if (location == last[i] - sbi->s_session) {
- lastblock = last[i] - sbi->s_session;
- sbi->s_anchor[0] = lastblock;
- sbi->s_anchor[1] = lastblock - 256;
- } else if (location ==
- udf_variable_to_fixed(last[i]) -
- sbi->s_session) {
- UDF_SET_FLAG(sb, UDF_FLAG_VARCONV);
- lastblock =
- udf_variable_to_fixed(last[i]) -
- sbi->s_session;
- sbi->s_anchor[0] = lastblock;
- sbi->s_anchor[1] = lastblock - 256 -
- sbi->s_session;
- } else {
- udf_debug("Anchor found at block %d, "
- "location mismatch %d.\n",
- last[i], location);
- }
- } else if (ident == TAG_IDENT_FE ||
- ident == TAG_IDENT_EFE) {
- lastblock = last[i];
- sbi->s_anchor[3] = 512;
- } else {
- ident = location = 0;
- if (last[i] >= 256) {
- bh = sb_bread(sb, last[i] - 256);
- if (bh) {
- tag *t = (tag *)bh->b_data;
- ident = le16_to_cpu(
- t->tagIdent);
- location = le32_to_cpu(
- t->tagLocation);
- brelse(bh);
- }
- }
+ t = (tag *)bh->b_data;
+ ident = le16_to_cpu(t->tagIdent);
+ location = le32_to_cpu(t->tagLocation);
+ brelse(bh);
+ if (ident != TAG_IDENT_AVDP)
+ return 0;
+ return location == block;
+}
- if (ident == TAG_IDENT_AVDP &&
- location == last[i] - 256 -
- sbi->s_session) {
- lastblock = last[i];
- sbi->s_anchor[1] = last[i] - 256;
- } else {
- ident = location = 0;
- if (last[i] >= 312 + sbi->s_session) {
- bh = sb_bread(sb,
- last[i] - 312 -
- sbi->s_session);
- if (bh) {
- tag *t = (tag *)
- bh->b_data;
- ident = le16_to_cpu(
- t->tagIdent);
- location = le32_to_cpu(
- t->tagLocation);
- brelse(bh);
- }
- }
+/* Search for an anchor volume descriptor pointer */
+static sector_t udf_scan_anchors(struct super_block *sb, bool varconv,
+ sector_t lastblock)
+{
+ sector_t last[6];
+ int i;
+ struct udf_sb_info *sbi = UDF_SB(sb);
- if (ident == TAG_IDENT_AVDP &&
- location == udf_variable_to_fixed(last[i]) - 256) {
- UDF_SET_FLAG(sb,
- UDF_FLAG_VARCONV);
- lastblock = udf_variable_to_fixed(last[i]);
- sbi->s_anchor[1] = lastblock - 256;
- }
- }
- }
+ last[0] = lastblock;
+ last[1] = last[0] - 1;
+ last[2] = last[0] + 1;
+ last[3] = last[0] - 2;
+ last[4] = last[0] - 150;
+ last[5] = last[0] - 152;
+
+ /* according to spec, anchor is in either:
+ * block 256
+ * lastblock-256
+ * lastblock
+ * however, if the disc isn't closed, it could be 512 */
+
+ for (i = 0; i < ARRAY_SIZE(last); i++) {
+ if (last[i] < 0)
+ continue;
+ if (last[i] >= sb->s_bdev->bd_inode->i_size >>
+ sb->s_blocksize_bits)
+ continue;
+
+ if (udf_check_anchor_block(sb, last[i], varconv)) {
+ sbi->s_anchor[0] = last[i];
+ sbi->s_anchor[1] = last[i] - 256;
+ return last[i];
}
- }
- if (!lastblock) {
- /* We haven't found the lastblock. check 312 */
- bh = sb_bread(sb, 312 + sbi->s_session);
- if (bh) {
- tag *t = (tag *)bh->b_data;
- ident = le16_to_cpu(t->tagIdent);
- location = le32_to_cpu(t->tagLocation);
- brelse(bh);
+ if (last[i] < 256)
+ continue;
- if (ident == TAG_IDENT_AVDP && location == 256)
- UDF_SET_FLAG(sb, UDF_FLAG_VARCONV);
+ if (udf_check_anchor_block(sb, last[i] - 256, varconv)) {
+ sbi->s_anchor[1] = last[i] - 256;
+ return last[i];
}
}
+ if (udf_check_anchor_block(sb, sbi->s_session + 256, varconv)) {
+ sbi->s_anchor[0] = sbi->s_session + 256;
+ return last[0];
+ }
+ if (udf_check_anchor_block(sb, sbi->s_session + 512, varconv)) {
+ sbi->s_anchor[0] = sbi->s_session + 512;
+ return last[0];
+ }
+ return 0;
+}
+
+/*
+ * Find an anchor volume descriptor. The function expects sbi->s_lastblock to
+ * be the last block on the media.
+ *
+ * Return 1 if not found, 0 if ok
+ *
+ */
+static void udf_find_anchor(struct super_block *sb)
+{
+ sector_t lastblock;
+ struct buffer_head *bh = NULL;
+ uint16_t ident;
+ int i;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+
+ lastblock = udf_scan_anchors(sb, 0, sbi->s_last_block);
+ if (lastblock)
+ goto check_anchor;
+
+ /* No anchor found? Try VARCONV conversion of block numbers */
+ /* Firstly, we try to not convert number of the last block */
+ lastblock = udf_scan_anchors(sb, 1,
+ udf_variable_to_fixed(sbi->s_last_block));
+ if (lastblock) {
+ UDF_SET_FLAG(sb, UDF_FLAG_VARCONV);
+ goto check_anchor;
+ }
+
+ /* Secondly, we try with converted number of the last block */
+ lastblock = udf_scan_anchors(sb, 1, sbi->s_last_block);
+ if (lastblock)
+ UDF_SET_FLAG(sb, UDF_FLAG_VARCONV);
+
+check_anchor:
+ /*
+ * Check located anchors and the anchor block supplied via
+ * mount options
+ */
for (i = 0; i < ARRAY_SIZE(sbi->s_anchor); i++) {
- if (sbi->s_anchor[i]) {
- bh = udf_read_tagged(sb, sbi->s_anchor[i],
- sbi->s_anchor[i], &ident);
- if (!bh)
+ if (!sbi->s_anchor[i])
+ continue;
+ bh = udf_read_tagged(sb, sbi->s_anchor[i],
+ sbi->s_anchor[i], &ident);
+ if (!bh)
+ sbi->s_anchor[i] = 0;
+ else {
+ brelse(bh);
+ if (ident != TAG_IDENT_AVDP)
sbi->s_anchor[i] = 0;
- else {
- brelse(bh);
- if ((ident != TAG_IDENT_AVDP) &&
- (i || (ident != TAG_IDENT_FE &&
- ident != TAG_IDENT_EFE)))
- sbi->s_anchor[i] = 0;
- }
}
}
return 1;
}
-static void udf_load_pvoldesc(struct super_block *sb, struct buffer_head *bh)
+static int udf_load_pvoldesc(struct super_block *sb, sector_t block)
{
struct primaryVolDesc *pvoldesc;
- time_t recording;
- long recording_usec;
struct ustr instr;
struct ustr outstr;
+ struct buffer_head *bh;
+ uint16_t ident;
+
+ bh = udf_read_tagged(sb, block, block, &ident);
+ if (!bh)
+ return 1;
+ BUG_ON(ident != TAG_IDENT_PVD);
pvoldesc = (struct primaryVolDesc *)bh->b_data;
- if (udf_stamp_to_time(&recording, &recording_usec,
- lets_to_cpu(pvoldesc->recordingDateAndTime))) {
- kernel_timestamp ts;
- ts = lets_to_cpu(pvoldesc->recordingDateAndTime);
- udf_debug("recording time %ld/%ld, %04u/%02u/%02u"
+ if (udf_disk_stamp_to_time(&UDF_SB(sb)->s_record_time,
+ pvoldesc->recordingDateAndTime)) {
+#ifdef UDFFS_DEBUG
+ timestamp *ts = &pvoldesc->recordingDateAndTime;
+ udf_debug("recording time %04u/%02u/%02u"
" %02u:%02u (%x)\n",
- recording, recording_usec,
- ts.year, ts.month, ts.day, ts.hour,
- ts.minute, ts.typeAndTimezone);
- UDF_SB(sb)->s_record_time.tv_sec = recording;
- UDF_SB(sb)->s_record_time.tv_nsec = recording_usec * 1000;
+ le16_to_cpu(ts->year), ts->month, ts->day, ts->hour,
+ ts->minute, le16_to_cpu(ts->typeAndTimezone));
+#endif
}
if (!udf_build_ustr(&instr, pvoldesc->volIdent, 32))
if (!udf_build_ustr(&instr, pvoldesc->volSetIdent, 128))
if (udf_CS0toUTF8(&outstr, &instr))
udf_debug("volSetIdent[] = '%s'\n", outstr.u_name);
+
+ brelse(bh);
+ return 0;
+}
+
+static int udf_load_metadata_files(struct super_block *sb, int partition)
+{
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct udf_part_map *map;
+ struct udf_meta_data *mdata;
+ kernel_lb_addr addr;
+ int fe_error = 0;
+
+ map = &sbi->s_partmaps[partition];
+ mdata = &map->s_type_specific.s_metadata;
+
+ /* metadata address */
+ addr.logicalBlockNum = mdata->s_meta_file_loc;
+ addr.partitionReferenceNum = map->s_partition_num;
+
+ udf_debug("Metadata file location: block = %d part = %d\n",
+ addr.logicalBlockNum, addr.partitionReferenceNum);
+
+ mdata->s_metadata_fe = udf_iget(sb, addr);
+
+ if (mdata->s_metadata_fe == NULL) {
+ udf_warning(sb, __func__, "metadata inode efe not found, "
+ "will try mirror inode.");
+ fe_error = 1;
+ } else if (UDF_I(mdata->s_metadata_fe)->i_alloc_type !=
+ ICBTAG_FLAG_AD_SHORT) {
+ udf_warning(sb, __func__, "metadata inode efe does not have "
+ "short allocation descriptors!");
+ fe_error = 1;
+ iput(mdata->s_metadata_fe);
+ mdata->s_metadata_fe = NULL;
+ }
+
+ /* mirror file entry */
+ addr.logicalBlockNum = mdata->s_mirror_file_loc;
+ addr.partitionReferenceNum = map->s_partition_num;
+
+ udf_debug("Mirror metadata file location: block = %d part = %d\n",
+ addr.logicalBlockNum, addr.partitionReferenceNum);
+
+ mdata->s_mirror_fe = udf_iget(sb, addr);
+
+ if (mdata->s_mirror_fe == NULL) {
+ if (fe_error) {
+ udf_error(sb, __func__, "mirror inode efe not found "
+ "and metadata inode is missing too, exiting...");
+ goto error_exit;
+ } else
+ udf_warning(sb, __func__, "mirror inode efe not found,"
+ " but metadata inode is OK");
+ } else if (UDF_I(mdata->s_mirror_fe)->i_alloc_type !=
+ ICBTAG_FLAG_AD_SHORT) {
+ udf_warning(sb, __func__, "mirror inode efe does not have "
+ "short allocation descriptors!");
+ iput(mdata->s_mirror_fe);
+ mdata->s_mirror_fe = NULL;
+ if (fe_error)
+ goto error_exit;
+ }
+
+ /*
+ * bitmap file entry
+ * Note:
+ * Load only if bitmap file location differs from 0xFFFFFFFF (DCN-5102)
+ */
+ if (mdata->s_bitmap_file_loc != 0xFFFFFFFF) {
+ addr.logicalBlockNum = mdata->s_bitmap_file_loc;
+ addr.partitionReferenceNum = map->s_partition_num;
+
+ udf_debug("Bitmap file location: block = %d part = %d\n",
+ addr.logicalBlockNum, addr.partitionReferenceNum);
+
+ mdata->s_bitmap_fe = udf_iget(sb, addr);
+
+ if (mdata->s_bitmap_fe == NULL) {
+ if (sb->s_flags & MS_RDONLY)
+ udf_warning(sb, __func__, "bitmap inode efe "
+ "not found but it's ok since the disc"
+ " is mounted read-only");
+ else {
+ udf_error(sb, __func__, "bitmap inode efe not "
+ "found and attempted read-write mount");
+ goto error_exit;
+ }
+ }
+ }
+
+ udf_debug("udf_load_metadata_files Ok\n");
+
+ return 0;
+
+error_exit:
+ return 1;
}
static void udf_load_fileset(struct super_block *sb, struct buffer_head *bh,
int udf_compute_nr_groups(struct super_block *sb, u32 partition)
{
struct udf_part_map *map = &UDF_SB(sb)->s_partmaps[partition];
- return (map->s_partition_len +
- (sizeof(struct spaceBitmapDesc) << 3) +
- (sb->s_blocksize * 8) - 1) /
- (sb->s_blocksize * 8);
+ return DIV_ROUND_UP(map->s_partition_len +
+ (sizeof(struct spaceBitmapDesc) << 3),
+ sb->s_blocksize * 8);
}
static struct udf_bitmap *udf_sb_alloc_bitmap(struct super_block *sb, u32 index)
return bitmap;
}
-static int udf_load_partdesc(struct super_block *sb, struct buffer_head *bh)
+static int udf_fill_partdesc_info(struct super_block *sb,
+ struct partitionDesc *p, int p_index)
+{
+ struct udf_part_map *map;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct partitionHeaderDesc *phd;
+
+ map = &sbi->s_partmaps[p_index];
+
+ map->s_partition_len = le32_to_cpu(p->partitionLength); /* blocks */
+ map->s_partition_root = le32_to_cpu(p->partitionStartingLocation);
+
+ if (p->accessType == cpu_to_le32(PD_ACCESS_TYPE_READ_ONLY))
+ map->s_partition_flags |= UDF_PART_FLAG_READ_ONLY;
+ if (p->accessType == cpu_to_le32(PD_ACCESS_TYPE_WRITE_ONCE))
+ map->s_partition_flags |= UDF_PART_FLAG_WRITE_ONCE;
+ if (p->accessType == cpu_to_le32(PD_ACCESS_TYPE_REWRITABLE))
+ map->s_partition_flags |= UDF_PART_FLAG_REWRITABLE;
+ if (p->accessType == cpu_to_le32(PD_ACCESS_TYPE_OVERWRITABLE))
+ map->s_partition_flags |= UDF_PART_FLAG_OVERWRITABLE;
+
+ udf_debug("Partition (%d type %x) starts at physical %d, "
+ "block length %d\n", p_index,
+ map->s_partition_type, map->s_partition_root,
+ map->s_partition_len);
+
+ if (strcmp(p->partitionContents.ident, PD_PARTITION_CONTENTS_NSR02) &&
+ strcmp(p->partitionContents.ident, PD_PARTITION_CONTENTS_NSR03))
+ return 0;
+
+ phd = (struct partitionHeaderDesc *)p->partitionContentsUse;
+ if (phd->unallocSpaceTable.extLength) {
+ kernel_lb_addr loc = {
+ .logicalBlockNum = le32_to_cpu(
+ phd->unallocSpaceTable.extPosition),
+ .partitionReferenceNum = p_index,
+ };
+
+ map->s_uspace.s_table = udf_iget(sb, loc);
+ if (!map->s_uspace.s_table) {
+ udf_debug("cannot load unallocSpaceTable (part %d)\n",
+ p_index);
+ return 1;
+ }
+ map->s_partition_flags |= UDF_PART_FLAG_UNALLOC_TABLE;
+ udf_debug("unallocSpaceTable (part %d) @ %ld\n",
+ p_index, map->s_uspace.s_table->i_ino);
+ }
+
+ if (phd->unallocSpaceBitmap.extLength) {
+ struct udf_bitmap *bitmap = udf_sb_alloc_bitmap(sb, p_index);
+ if (!bitmap)
+ return 1;
+ map->s_uspace.s_bitmap = bitmap;
+ bitmap->s_extLength = le32_to_cpu(
+ phd->unallocSpaceBitmap.extLength);
+ bitmap->s_extPosition = le32_to_cpu(
+ phd->unallocSpaceBitmap.extPosition);
+ map->s_partition_flags |= UDF_PART_FLAG_UNALLOC_BITMAP;
+ udf_debug("unallocSpaceBitmap (part %d) @ %d\n", p_index,
+ bitmap->s_extPosition);
+ }
+
+ if (phd->partitionIntegrityTable.extLength)
+ udf_debug("partitionIntegrityTable (part %d)\n", p_index);
+
+ if (phd->freedSpaceTable.extLength) {
+ kernel_lb_addr loc = {
+ .logicalBlockNum = le32_to_cpu(
+ phd->freedSpaceTable.extPosition),
+ .partitionReferenceNum = p_index,
+ };
+
+ map->s_fspace.s_table = udf_iget(sb, loc);
+ if (!map->s_fspace.s_table) {
+ udf_debug("cannot load freedSpaceTable (part %d)\n",
+ p_index);
+ return 1;
+ }
+
+ map->s_partition_flags |= UDF_PART_FLAG_FREED_TABLE;
+ udf_debug("freedSpaceTable (part %d) @ %ld\n",
+ p_index, map->s_fspace.s_table->i_ino);
+ }
+
+ if (phd->freedSpaceBitmap.extLength) {
+ struct udf_bitmap *bitmap = udf_sb_alloc_bitmap(sb, p_index);
+ if (!bitmap)
+ return 1;
+ map->s_fspace.s_bitmap = bitmap;
+ bitmap->s_extLength = le32_to_cpu(
+ phd->freedSpaceBitmap.extLength);
+ bitmap->s_extPosition = le32_to_cpu(
+ phd->freedSpaceBitmap.extPosition);
+ map->s_partition_flags |= UDF_PART_FLAG_FREED_BITMAP;
+ udf_debug("freedSpaceBitmap (part %d) @ %d\n", p_index,
+ bitmap->s_extPosition);
+ }
+ return 0;
+}
+
+static int udf_load_vat(struct super_block *sb, int p_index, int type1_index)
+{
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct udf_part_map *map = &sbi->s_partmaps[p_index];
+ kernel_lb_addr ino;
+ struct buffer_head *bh = NULL;
+ struct udf_inode_info *vati;
+ uint32_t pos;
+ struct virtualAllocationTable20 *vat20;
+
+ /* VAT file entry is in the last recorded block */
+ ino.partitionReferenceNum = type1_index;
+ ino.logicalBlockNum = sbi->s_last_block - map->s_partition_root;
+ sbi->s_vat_inode = udf_iget(sb, ino);
+ if (!sbi->s_vat_inode)
+ return 1;
+
+ if (map->s_partition_type == UDF_VIRTUAL_MAP15) {
+ map->s_type_specific.s_virtual.s_start_offset = 0;
+ map->s_type_specific.s_virtual.s_num_entries =
+ (sbi->s_vat_inode->i_size - 36) >> 2;
+ } else if (map->s_partition_type == UDF_VIRTUAL_MAP20) {
+ vati = UDF_I(sbi->s_vat_inode);
+ if (vati->i_alloc_type != ICBTAG_FLAG_AD_IN_ICB) {
+ pos = udf_block_map(sbi->s_vat_inode, 0);
+ bh = sb_bread(sb, pos);
+ if (!bh)
+ return 1;
+ vat20 = (struct virtualAllocationTable20 *)bh->b_data;
+ } else {
+ vat20 = (struct virtualAllocationTable20 *)
+ vati->i_ext.i_data;
+ }
+
+ map->s_type_specific.s_virtual.s_start_offset =
+ le16_to_cpu(vat20->lengthHeader);
+ map->s_type_specific.s_virtual.s_num_entries =
+ (sbi->s_vat_inode->i_size -
+ map->s_type_specific.s_virtual.
+ s_start_offset) >> 2;
+ brelse(bh);
+ }
+ return 0;
+}
+
+static int udf_load_partdesc(struct super_block *sb, sector_t block)
{
+ struct buffer_head *bh;
struct partitionDesc *p;
- int i;
struct udf_part_map *map;
- struct udf_sb_info *sbi;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ int i, type1_idx;
+ uint16_t partitionNumber;
+ uint16_t ident;
+ int ret = 0;
+
+ bh = udf_read_tagged(sb, block, block, &ident);
+ if (!bh)
+ return 1;
+ if (ident != TAG_IDENT_PD)
+ goto out_bh;
p = (struct partitionDesc *)bh->b_data;
- sbi = UDF_SB(sb);
+ partitionNumber = le16_to_cpu(p->partitionNumber);
+ /* First scan for TYPE1, SPARABLE and METADATA partitions */
for (i = 0; i < sbi->s_partitions; i++) {
map = &sbi->s_partmaps[i];
udf_debug("Searching map: (%d == %d)\n",
- map->s_partition_num,
- le16_to_cpu(p->partitionNumber));
- if (map->s_partition_num ==
- le16_to_cpu(p->partitionNumber)) {
- map->s_partition_len =
- le32_to_cpu(p->partitionLength); /* blocks */
- map->s_partition_root =
- le32_to_cpu(p->partitionStartingLocation);
- if (p->accessType ==
- cpu_to_le32(PD_ACCESS_TYPE_READ_ONLY))
- map->s_partition_flags |=
- UDF_PART_FLAG_READ_ONLY;
- if (p->accessType ==
- cpu_to_le32(PD_ACCESS_TYPE_WRITE_ONCE))
- map->s_partition_flags |=
- UDF_PART_FLAG_WRITE_ONCE;
- if (p->accessType ==
- cpu_to_le32(PD_ACCESS_TYPE_REWRITABLE))
- map->s_partition_flags |=
- UDF_PART_FLAG_REWRITABLE;
- if (p->accessType ==
- cpu_to_le32(PD_ACCESS_TYPE_OVERWRITABLE))
- map->s_partition_flags |=
- UDF_PART_FLAG_OVERWRITABLE;
-
- if (!strcmp(p->partitionContents.ident,
- PD_PARTITION_CONTENTS_NSR02) ||
- !strcmp(p->partitionContents.ident,
- PD_PARTITION_CONTENTS_NSR03)) {
- struct partitionHeaderDesc *phd;
-
- phd = (struct partitionHeaderDesc *)
- (p->partitionContentsUse);
- if (phd->unallocSpaceTable.extLength) {
- kernel_lb_addr loc = {
- .logicalBlockNum = le32_to_cpu(phd->unallocSpaceTable.extPosition),
- .partitionReferenceNum = i,
- };
-
- map->s_uspace.s_table =
- udf_iget(sb, loc);
- if (!map->s_uspace.s_table) {
- udf_debug("cannot load unallocSpaceTable (part %d)\n", i);
- return 1;
- }
- map->s_partition_flags |=
- UDF_PART_FLAG_UNALLOC_TABLE;
- udf_debug("unallocSpaceTable (part %d) @ %ld\n",
- i, map->s_uspace.s_table->i_ino);
- }
- if (phd->unallocSpaceBitmap.extLength) {
- struct udf_bitmap *bitmap =
- udf_sb_alloc_bitmap(sb, i);
- map->s_uspace.s_bitmap = bitmap;
- if (bitmap != NULL) {
- bitmap->s_extLength =
- le32_to_cpu(phd->unallocSpaceBitmap.extLength);
- bitmap->s_extPosition =
- le32_to_cpu(phd->unallocSpaceBitmap.extPosition);
- map->s_partition_flags |= UDF_PART_FLAG_UNALLOC_BITMAP;
- udf_debug("unallocSpaceBitmap (part %d) @ %d\n",
- i, bitmap->s_extPosition);
- }
- }
- if (phd->partitionIntegrityTable.extLength)
- udf_debug("partitionIntegrityTable (part %d)\n", i);
- if (phd->freedSpaceTable.extLength) {
- kernel_lb_addr loc = {
- .logicalBlockNum = le32_to_cpu(phd->freedSpaceTable.extPosition),
- .partitionReferenceNum = i,
- };
-
- map->s_fspace.s_table =
- udf_iget(sb, loc);
- if (!map->s_fspace.s_table) {
- udf_debug("cannot load freedSpaceTable (part %d)\n", i);
- return 1;
- }
- map->s_partition_flags |=
- UDF_PART_FLAG_FREED_TABLE;
- udf_debug("freedSpaceTable (part %d) @ %ld\n",
- i, map->s_fspace.s_table->i_ino);
- }
- if (phd->freedSpaceBitmap.extLength) {
- struct udf_bitmap *bitmap =
- udf_sb_alloc_bitmap(sb, i);
- map->s_fspace.s_bitmap = bitmap;
- if (bitmap != NULL) {
- bitmap->s_extLength =
- le32_to_cpu(phd->freedSpaceBitmap.extLength);
- bitmap->s_extPosition =
- le32_to_cpu(phd->freedSpaceBitmap.extPosition);
- map->s_partition_flags |= UDF_PART_FLAG_FREED_BITMAP;
- udf_debug("freedSpaceBitmap (part %d) @ %d\n",
- i, bitmap->s_extPosition);
- }
- }
- }
+ map->s_partition_num, partitionNumber);
+ if (map->s_partition_num == partitionNumber &&
+ (map->s_partition_type == UDF_TYPE1_MAP15 ||
+ map->s_partition_type == UDF_SPARABLE_MAP15))
break;
- }
}
- if (i == sbi->s_partitions)
+
+ if (i >= sbi->s_partitions) {
udf_debug("Partition (%d) not found in partition map\n",
- le16_to_cpu(p->partitionNumber));
- else
- udf_debug("Partition (%d:%d type %x) starts at physical %d, "
- "block length %d\n",
- le16_to_cpu(p->partitionNumber), i,
- map->s_partition_type,
- map->s_partition_root,
- map->s_partition_len);
- return 0;
+ partitionNumber);
+ goto out_bh;
+ }
+
+ ret = udf_fill_partdesc_info(sb, p, i);
+
+ /*
+ * Now rescan for VIRTUAL or METADATA partitions when SPARABLE and
+ * PHYSICAL partitions are already set up
+ */
+ type1_idx = i;
+ for (i = 0; i < sbi->s_partitions; i++) {
+ map = &sbi->s_partmaps[i];
+
+ if (map->s_partition_num == partitionNumber &&
+ (map->s_partition_type == UDF_VIRTUAL_MAP15 ||
+ map->s_partition_type == UDF_VIRTUAL_MAP20 ||
+ map->s_partition_type == UDF_METADATA_MAP25))
+ break;
+ }
+
+ if (i >= sbi->s_partitions)
+ goto out_bh;
+
+ ret = udf_fill_partdesc_info(sb, p, i);
+ if (ret)
+ goto out_bh;
+
+ if (map->s_partition_type == UDF_METADATA_MAP25) {
+ ret = udf_load_metadata_files(sb, i);
+ if (ret) {
+ printk(KERN_ERR "UDF-fs: error loading MetaData "
+ "partition map %d\n", i);
+ goto out_bh;
+ }
+ } else {
+ ret = udf_load_vat(sb, i, type1_idx);
+ if (ret)
+ goto out_bh;
+ /*
+ * Mark filesystem read-only if we have a partition with
+ * virtual map since we don't handle writing to it (we
+ * overwrite blocks instead of relocating them).
+ */
+ sb->s_flags |= MS_RDONLY;
+ printk(KERN_NOTICE "UDF-fs: Filesystem marked read-only "
+ "because writing to pseudooverwrite partition is "
+ "not implemented.\n");
+ }
+out_bh:
+ /* In case loading failed, we handle cleanup in udf_fill_super */
+ brelse(bh);
+ return ret;
}
-static int udf_load_logicalvol(struct super_block *sb, struct buffer_head *bh,
+static int udf_load_logicalvol(struct super_block *sb, sector_t block,
kernel_lb_addr *fileset)
{
struct logicalVolDesc *lvd;
uint8_t type;
struct udf_sb_info *sbi = UDF_SB(sb);
struct genericPartitionMap *gpm;
+ uint16_t ident;
+ struct buffer_head *bh;
+ int ret = 0;
+ bh = udf_read_tagged(sb, block, block, &ident);
+ if (!bh)
+ return 1;
+ BUG_ON(ident != TAG_IDENT_LVD);
lvd = (struct logicalVolDesc *)bh->b_data;
i = udf_sb_alloc_partition_maps(sb, le32_to_cpu(lvd->numPartitionMaps));
- if (i != 0)
- return i;
+ if (i != 0) {
+ ret = i;
+ goto out_bh;
+ }
for (i = 0, offset = 0;
i < sbi->s_partitions && offset < le32_to_cpu(lvd->mapTableLength);
u16 suf =
le16_to_cpu(((__le16 *)upm2->partIdent.
identSuffix)[0]);
- if (suf == 0x0150) {
+ if (suf < 0x0200) {
map->s_partition_type =
UDF_VIRTUAL_MAP15;
map->s_partition_func =
udf_get_pblock_virt15;
- } else if (suf == 0x0200) {
+ } else {
map->s_partition_type =
UDF_VIRTUAL_MAP20;
map->s_partition_func =
UDF_ID_SPARABLE,
strlen(UDF_ID_SPARABLE))) {
uint32_t loc;
- uint16_t ident;
struct sparingTable *st;
struct sparablePartitionMap *spm =
(struct sparablePartitionMap *)gpm;
map->s_type_specific.s_sparing.
s_spar_map[j] = bh2;
- if (bh2 != NULL) {
- st = (struct sparingTable *)
- bh2->b_data;
- if (ident != 0 || strncmp(
- st->sparingIdent.ident,
- UDF_ID_SPARING,
- strlen(UDF_ID_SPARING))) {
- brelse(bh2);
- map->s_type_specific.
- s_sparing.
- s_spar_map[j] =
- NULL;
- }
+ if (bh2 == NULL)
+ continue;
+
+ st = (struct sparingTable *)bh2->b_data;
+ if (ident != 0 || strncmp(
+ st->sparingIdent.ident,
+ UDF_ID_SPARING,
+ strlen(UDF_ID_SPARING))) {
+ brelse(bh2);
+ map->s_type_specific.s_sparing.
+ s_spar_map[j] = NULL;
}
}
map->s_partition_func = udf_get_pblock_spar15;
+ } else if (!strncmp(upm2->partIdent.ident,
+ UDF_ID_METADATA,
+ strlen(UDF_ID_METADATA))) {
+ struct udf_meta_data *mdata =
+ &map->s_type_specific.s_metadata;
+ struct metadataPartitionMap *mdm =
+ (struct metadataPartitionMap *)
+ &(lvd->partitionMaps[offset]);
+ udf_debug("Parsing Logical vol part %d "
+ "type %d id=%s\n", i, type,
+ UDF_ID_METADATA);
+
+ map->s_partition_type = UDF_METADATA_MAP25;
+ map->s_partition_func = udf_get_pblock_meta25;
+
+ mdata->s_meta_file_loc =
+ le32_to_cpu(mdm->metadataFileLoc);
+ mdata->s_mirror_file_loc =
+ le32_to_cpu(mdm->metadataMirrorFileLoc);
+ mdata->s_bitmap_file_loc =
+ le32_to_cpu(mdm->metadataBitmapFileLoc);
+ mdata->s_alloc_unit_size =
+ le32_to_cpu(mdm->allocUnitSize);
+ mdata->s_align_unit_size =
+ le16_to_cpu(mdm->alignUnitSize);
+ mdata->s_dup_md_flag =
+ mdm->flags & 0x01;
+
+ udf_debug("Metadata Ident suffix=0x%x\n",
+ (le16_to_cpu(
+ ((__le16 *)
+ mdm->partIdent.identSuffix)[0])));
+ udf_debug("Metadata part num=%d\n",
+ le16_to_cpu(mdm->partitionNum));
+ udf_debug("Metadata part alloc unit size=%d\n",
+ le32_to_cpu(mdm->allocUnitSize));
+ udf_debug("Metadata file loc=%d\n",
+ le32_to_cpu(mdm->metadataFileLoc));
+ udf_debug("Mirror file loc=%d\n",
+ le32_to_cpu(mdm->metadataMirrorFileLoc));
+ udf_debug("Bitmap file loc=%d\n",
+ le32_to_cpu(mdm->metadataBitmapFileLoc));
+ udf_debug("Duplicate Flag: %d %d\n",
+ mdata->s_dup_md_flag, mdm->flags);
} else {
udf_debug("Unknown ident: %s\n",
upm2->partIdent.ident);
if (lvd->integritySeqExt.extLength)
udf_load_logicalvolint(sb, leea_to_cpu(lvd->integritySeqExt));
- return 0;
+out_bh:
+ brelse(bh);
+ return ret;
}
/*
* July 1, 1997 - Andrew E. Mileski
* Written, tested, and released.
*/
-static int udf_process_sequence(struct super_block *sb, long block,
+static noinline int udf_process_sequence(struct super_block *sb, long block,
long lastblock, kernel_lb_addr *fileset)
{
struct buffer_head *bh = NULL;
struct generic_desc *gd;
struct volDescPtr *vdp;
int done = 0;
- int i, j;
uint32_t vdsn;
uint16_t ident;
long next_s = 0, next_e = 0;
memset(vds, 0, sizeof(struct udf_vds_record) * VDS_POS_LENGTH);
- /* Read the main descriptor sequence */
+ /*
+ * Read the main descriptor sequence and find which descriptors
+ * are in it.
+ */
for (; (!done && block <= lastblock); block++) {
bh = udf_read_tagged(sb, block, block, &ident);
- if (!bh)
- break;
+ if (!bh) {
+ printk(KERN_ERR "udf: Block %Lu of volume descriptor "
+ "sequence is corrupted or we could not read "
+ "it.\n", (unsigned long long)block);
+ return 1;
+ }
/* Process each descriptor (ISO 13346 3/8.3-8.4) */
gd = (struct generic_desc *)bh->b_data;
}
brelse(bh);
}
- for (i = 0; i < VDS_POS_LENGTH; i++) {
- if (vds[i].block) {
- bh = udf_read_tagged(sb, vds[i].block, vds[i].block,
- &ident);
-
- if (i == VDS_POS_PRIMARY_VOL_DESC) {
- udf_load_pvoldesc(sb, bh);
- } else if (i == VDS_POS_LOGICAL_VOL_DESC) {
- if (udf_load_logicalvol(sb, bh, fileset)) {
- brelse(bh);
- return 1;
- }
- } else if (i == VDS_POS_PARTITION_DESC) {
- struct buffer_head *bh2 = NULL;
- if (udf_load_partdesc(sb, bh)) {
- brelse(bh);
- return 1;
- }
- for (j = vds[i].block + 1;
- j < vds[VDS_POS_TERMINATING_DESC].block;
- j++) {
- bh2 = udf_read_tagged(sb, j, j, &ident);
- gd = (struct generic_desc *)bh2->b_data;
- if (ident == TAG_IDENT_PD)
- if (udf_load_partdesc(sb,
- bh2)) {
- brelse(bh);
- brelse(bh2);
- return 1;
- }
- brelse(bh2);
- }
- }
- brelse(bh);
- }
+ /*
+ * Now read interesting descriptors again and process them
+ * in a suitable order
+ */
+ if (!vds[VDS_POS_PRIMARY_VOL_DESC].block) {
+ printk(KERN_ERR "udf: Primary Volume Descriptor not found!\n");
+ return 1;
+ }
+ if (udf_load_pvoldesc(sb, vds[VDS_POS_PRIMARY_VOL_DESC].block))
+ return 1;
+
+ if (vds[VDS_POS_LOGICAL_VOL_DESC].block && udf_load_logicalvol(sb,
+ vds[VDS_POS_LOGICAL_VOL_DESC].block, fileset))
+ return 1;
+
+ if (vds[VDS_POS_PARTITION_DESC].block) {
+ /*
+ * We rescan the whole descriptor sequence to find
+ * partition descriptor blocks and process them.
+ */
+ for (block = vds[VDS_POS_PARTITION_DESC].block;
+ block < vds[VDS_POS_TERMINATING_DESC].block;
+ block++)
+ if (udf_load_partdesc(sb, block))
+ return 1;
}
return 0;
static int udf_check_valid(struct super_block *sb, int novrs, int silent)
{
long block;
+ struct udf_sb_info *sbi = UDF_SB(sb);
if (novrs) {
udf_debug("Validity check skipped because of novrs option\n");
}
/* Check that it is NSR02 compliant */
/* Process any "CD-ROM Volume Descriptor Set" (ECMA 167 2/8.3.1) */
- else {
- block = udf_vrs(sb, silent);
- if (block == -1) {
- struct udf_sb_info *sbi = UDF_SB(sb);
- udf_debug("Failed to read byte 32768. Assuming open "
- "disc. Skipping validity check\n");
- if (!sbi->s_last_block)
- sbi->s_last_block = udf_get_last_block(sb);
- return 0;
- } else
- return !block;
- }
+ block = udf_vrs(sb, silent);
+ if (block == -1)
+ udf_debug("Failed to read byte 32768. Assuming open "
+ "disc. Skipping validity check\n");
+ if (block && !sbi->s_last_block)
+ sbi->s_last_block = udf_get_last_block(sb);
+ return !block;
}
-static int udf_load_partition(struct super_block *sb, kernel_lb_addr *fileset)
+static int udf_load_sequence(struct super_block *sb, kernel_lb_addr *fileset)
{
struct anchorVolDescPtr *anchor;
uint16_t ident;
struct buffer_head *bh;
long main_s, main_e, reserve_s, reserve_e;
- int i, j;
+ int i;
struct udf_sb_info *sbi;
if (!sb)
for (i = 0; i < ARRAY_SIZE(sbi->s_anchor); i++) {
if (!sbi->s_anchor[i])
continue;
+
bh = udf_read_tagged(sb, sbi->s_anchor[i], sbi->s_anchor[i],
&ident);
if (!bh)
}
udf_debug("Using anchor in block %d\n", sbi->s_anchor[i]);
- for (i = 0; i < sbi->s_partitions; i++) {
- kernel_lb_addr uninitialized_var(ino);
- struct udf_part_map *map = &sbi->s_partmaps[i];
- switch (map->s_partition_type) {
- case UDF_VIRTUAL_MAP15:
- case UDF_VIRTUAL_MAP20:
- if (!sbi->s_last_block) {
- sbi->s_last_block = udf_get_last_block(sb);
- udf_find_anchor(sb);
- }
-
- if (!sbi->s_last_block) {
- udf_debug("Unable to determine Lastblock (For "
- "Virtual Partition)\n");
- return 1;
- }
-
- for (j = 0; j < sbi->s_partitions; j++) {
- struct udf_part_map *map2 = &sbi->s_partmaps[j];
- if (j != i &&
- map->s_volumeseqnum ==
- map2->s_volumeseqnum &&
- map->s_partition_num ==
- map2->s_partition_num) {
- ino.partitionReferenceNum = j;
- ino.logicalBlockNum =
- sbi->s_last_block -
- map2->s_partition_root;
- break;
- }
- }
-
- if (j == sbi->s_partitions)
- return 1;
-
- sbi->s_vat_inode = udf_iget(sb, ino);
- if (!sbi->s_vat_inode)
- return 1;
-
- if (map->s_partition_type == UDF_VIRTUAL_MAP15) {
- map->s_type_specific.s_virtual.s_start_offset =
- udf_ext0_offset(sbi->s_vat_inode);
- map->s_type_specific.s_virtual.s_num_entries =
- (sbi->s_vat_inode->i_size - 36) >> 2;
- } else if (map->s_partition_type == UDF_VIRTUAL_MAP20) {
- uint32_t pos;
- struct virtualAllocationTable20 *vat20;
-
- pos = udf_block_map(sbi->s_vat_inode, 0);
- bh = sb_bread(sb, pos);
- if (!bh)
- return 1;
- vat20 = (struct virtualAllocationTable20 *)
- bh->b_data +
- udf_ext0_offset(sbi->s_vat_inode);
- map->s_type_specific.s_virtual.s_start_offset =
- le16_to_cpu(vat20->lengthHeader) +
- udf_ext0_offset(sbi->s_vat_inode);
- map->s_type_specific.s_virtual.s_num_entries =
- (sbi->s_vat_inode->i_size -
- map->s_type_specific.s_virtual.
- s_start_offset) >> 2;
- brelse(bh);
- }
- map->s_partition_root = udf_get_pblock(sb, 0, i, 0);
- map->s_partition_len =
- sbi->s_partmaps[ino.partitionReferenceNum].
- s_partition_len;
- }
- }
return 0;
}
{
struct udf_sb_info *sbi = UDF_SB(sb);
struct buffer_head *bh = sbi->s_lvid_bh;
- if (bh) {
- kernel_timestamp cpu_time;
- struct logicalVolIntegrityDesc *lvid =
- (struct logicalVolIntegrityDesc *)bh->b_data;
- struct logicalVolIntegrityDescImpUse *lvidiu =
- udf_sb_lvidiu(sbi);
+ struct logicalVolIntegrityDesc *lvid;
+ struct logicalVolIntegrityDescImpUse *lvidiu;
+ if (!bh)
+ return;
- lvidiu->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
- lvidiu->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
- if (udf_time_to_stamp(&cpu_time, CURRENT_TIME))
- lvid->recordingDateAndTime = cpu_to_lets(cpu_time);
- lvid->integrityType = LVID_INTEGRITY_TYPE_OPEN;
+ lvid = (struct logicalVolIntegrityDesc *)bh->b_data;
+ lvidiu = udf_sb_lvidiu(sbi);
- lvid->descTag.descCRC = cpu_to_le16(
- udf_crc((char *)lvid + sizeof(tag),
- le16_to_cpu(lvid->descTag.descCRCLength),
- 0));
+ lvidiu->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
+ lvidiu->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
+ udf_time_to_disk_stamp(&lvid->recordingDateAndTime,
+ CURRENT_TIME);
+ lvid->integrityType = LVID_INTEGRITY_TYPE_OPEN;
- lvid->descTag.tagChecksum = udf_tag_checksum(&lvid->descTag);
- mark_buffer_dirty(bh);
- }
+ lvid->descTag.descCRC = cpu_to_le16(
+ crc_itu_t(0, (char *)lvid + sizeof(tag),
+ le16_to_cpu(lvid->descTag.descCRCLength)));
+
+ lvid->descTag.tagChecksum = udf_tag_checksum(&lvid->descTag);
+ mark_buffer_dirty(bh);
}
static void udf_close_lvid(struct super_block *sb)
{
- kernel_timestamp cpu_time;
struct udf_sb_info *sbi = UDF_SB(sb);
struct buffer_head *bh = sbi->s_lvid_bh;
struct logicalVolIntegrityDesc *lvid;
+ struct logicalVolIntegrityDescImpUse *lvidiu;
if (!bh)
return;
lvid = (struct logicalVolIntegrityDesc *)bh->b_data;
- if (lvid->integrityType == LVID_INTEGRITY_TYPE_OPEN) {
- struct logicalVolIntegrityDescImpUse *lvidiu =
- udf_sb_lvidiu(sbi);
- lvidiu->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
- lvidiu->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
- if (udf_time_to_stamp(&cpu_time, CURRENT_TIME))
- lvid->recordingDateAndTime = cpu_to_lets(cpu_time);
- if (UDF_MAX_WRITE_VERSION > le16_to_cpu(lvidiu->maxUDFWriteRev))
- lvidiu->maxUDFWriteRev =
- cpu_to_le16(UDF_MAX_WRITE_VERSION);
- if (sbi->s_udfrev > le16_to_cpu(lvidiu->minUDFReadRev))
- lvidiu->minUDFReadRev = cpu_to_le16(sbi->s_udfrev);
- if (sbi->s_udfrev > le16_to_cpu(lvidiu->minUDFWriteRev))
- lvidiu->minUDFWriteRev = cpu_to_le16(sbi->s_udfrev);
- lvid->integrityType = cpu_to_le32(LVID_INTEGRITY_TYPE_CLOSE);
-
- lvid->descTag.descCRC = cpu_to_le16(
- udf_crc((char *)lvid + sizeof(tag),
- le16_to_cpu(lvid->descTag.descCRCLength),
- 0));
-
- lvid->descTag.tagChecksum = udf_tag_checksum(&lvid->descTag);
- mark_buffer_dirty(bh);
- }
+ if (lvid->integrityType != LVID_INTEGRITY_TYPE_OPEN)
+ return;
+
+ lvidiu = udf_sb_lvidiu(sbi);
+ lvidiu->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
+ lvidiu->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
+ udf_time_to_disk_stamp(&lvid->recordingDateAndTime, CURRENT_TIME);
+ if (UDF_MAX_WRITE_VERSION > le16_to_cpu(lvidiu->maxUDFWriteRev))
+ lvidiu->maxUDFWriteRev = cpu_to_le16(UDF_MAX_WRITE_VERSION);
+ if (sbi->s_udfrev > le16_to_cpu(lvidiu->minUDFReadRev))
+ lvidiu->minUDFReadRev = cpu_to_le16(sbi->s_udfrev);
+ if (sbi->s_udfrev > le16_to_cpu(lvidiu->minUDFWriteRev))
+ lvidiu->minUDFWriteRev = cpu_to_le16(sbi->s_udfrev);
+ lvid->integrityType = cpu_to_le32(LVID_INTEGRITY_TYPE_CLOSE);
+
+ lvid->descTag.descCRC = cpu_to_le16(
+ crc_itu_t(0, (char *)lvid + sizeof(tag),
+ le16_to_cpu(lvid->descTag.descCRCLength)));
+
+ lvid->descTag.tagChecksum = udf_tag_checksum(&lvid->descTag);
+ mark_buffer_dirty(bh);
}
static void udf_sb_free_bitmap(struct udf_bitmap *bitmap)
vfree(bitmap);
}
-/*
- * udf_read_super
- *
- * PURPOSE
- * Complete the specified super block.
- *
- * PRE-CONDITIONS
- * sb Pointer to superblock to complete - never NULL.
- * sb->s_dev Device to read suberblock from.
- * options Pointer to mount options.
- * silent Silent flag.
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
- */
+static void udf_free_partition(struct udf_part_map *map)
+{
+ int i;
+ struct udf_meta_data *mdata;
+
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_TABLE)
+ iput(map->s_uspace.s_table);
+ if (map->s_partition_flags & UDF_PART_FLAG_FREED_TABLE)
+ iput(map->s_fspace.s_table);
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP)
+ udf_sb_free_bitmap(map->s_uspace.s_bitmap);
+ if (map->s_partition_flags & UDF_PART_FLAG_FREED_BITMAP)
+ udf_sb_free_bitmap(map->s_fspace.s_bitmap);
+ if (map->s_partition_type == UDF_SPARABLE_MAP15)
+ for (i = 0; i < 4; i++)
+ brelse(map->s_type_specific.s_sparing.s_spar_map[i]);
+ else if (map->s_partition_type == UDF_METADATA_MAP25) {
+ mdata = &map->s_type_specific.s_metadata;
+ iput(mdata->s_metadata_fe);
+ mdata->s_metadata_fe = NULL;
+
+ iput(mdata->s_mirror_fe);
+ mdata->s_mirror_fe = NULL;
+
+ iput(mdata->s_bitmap_fe);
+ mdata->s_bitmap_fe = NULL;
+ }
+}
+
static int udf_fill_super(struct super_block *sb, void *options, int silent)
{
int i;
sbi->s_nls_map = uopt.nls_map;
/* Set the block size for all transfers */
- if (!udf_set_blocksize(sb, uopt.blocksize))
+ if (!sb_min_blocksize(sb, uopt.blocksize)) {
+ udf_debug("Bad block size (%d)\n", uopt.blocksize);
+ printk(KERN_ERR "udf: bad block size (%d)\n", uopt.blocksize);
goto error_out;
+ }
if (uopt.session == 0xFFFFFFFF)
sbi->s_session = udf_get_last_session(sb);
sbi->s_last_block = uopt.lastblock;
sbi->s_anchor[0] = sbi->s_anchor[1] = 0;
sbi->s_anchor[2] = uopt.anchor;
- sbi->s_anchor[3] = 256;
if (udf_check_valid(sb, uopt.novrs, silent)) {
/* read volume recognition sequences */
sb->s_magic = UDF_SUPER_MAGIC;
sb->s_time_gran = 1000;
- if (udf_load_partition(sb, &fileset)) {
+ if (udf_load_sequence(sb, &fileset)) {
printk(KERN_WARNING "UDF-fs: No partition found (1)\n");
goto error_out;
}
}
if (!silent) {
- kernel_timestamp ts;
- udf_time_to_stamp(&ts, sbi->s_record_time);
+ timestamp ts;
+ udf_time_to_disk_stamp(&ts, sbi->s_record_time);
udf_info("UDF: Mounting volume '%s', "
"timestamp %04u/%02u/%02u %02u:%02u (%x)\n",
- sbi->s_volume_ident, ts.year, ts.month, ts.day,
- ts.hour, ts.minute, ts.typeAndTimezone);
+ sbi->s_volume_ident, le16_to_cpu(ts.year), ts.month, ts.day,
+ ts.hour, ts.minute, le16_to_cpu(ts.typeAndTimezone));
}
if (!(sb->s_flags & MS_RDONLY))
udf_open_lvid(sb);
error_out:
if (sbi->s_vat_inode)
iput(sbi->s_vat_inode);
- if (sbi->s_partitions) {
- struct udf_part_map *map = &sbi->s_partmaps[sbi->s_partition];
- if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_TABLE)
- iput(map->s_uspace.s_table);
- if (map->s_partition_flags & UDF_PART_FLAG_FREED_TABLE)
- iput(map->s_fspace.s_table);
- if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP)
- udf_sb_free_bitmap(map->s_uspace.s_bitmap);
- if (map->s_partition_flags & UDF_PART_FLAG_FREED_BITMAP)
- udf_sb_free_bitmap(map->s_fspace.s_bitmap);
- if (map->s_partition_type == UDF_SPARABLE_MAP15)
- for (i = 0; i < 4; i++)
- brelse(map->s_type_specific.s_sparing.
- s_spar_map[i]);
- }
+ if (sbi->s_partitions)
+ for (i = 0; i < sbi->s_partitions; i++)
+ udf_free_partition(&sbi->s_partmaps[i]);
#ifdef CONFIG_UDF_NLS
if (UDF_QUERY_FLAG(sb, UDF_FLAG_NLS_MAP))
unload_nls(sbi->s_nls_map);
return -EINVAL;
}
-void udf_error(struct super_block *sb, const char *function,
- const char *fmt, ...)
+static void udf_error(struct super_block *sb, const char *function,
+ const char *fmt, ...)
{
va_list args;
sb->s_id, function, error_buf);
}
-/*
- * udf_put_super
- *
- * PURPOSE
- * Prepare for destruction of the superblock.
- *
- * DESCRIPTION
- * Called before the filesystem is unmounted.
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
- */
static void udf_put_super(struct super_block *sb)
{
int i;
sbi = UDF_SB(sb);
if (sbi->s_vat_inode)
iput(sbi->s_vat_inode);
- if (sbi->s_partitions) {
- struct udf_part_map *map = &sbi->s_partmaps[sbi->s_partition];
- if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_TABLE)
- iput(map->s_uspace.s_table);
- if (map->s_partition_flags & UDF_PART_FLAG_FREED_TABLE)
- iput(map->s_fspace.s_table);
- if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP)
- udf_sb_free_bitmap(map->s_uspace.s_bitmap);
- if (map->s_partition_flags & UDF_PART_FLAG_FREED_BITMAP)
- udf_sb_free_bitmap(map->s_fspace.s_bitmap);
- if (map->s_partition_type == UDF_SPARABLE_MAP15)
- for (i = 0; i < 4; i++)
- brelse(map->s_type_specific.s_sparing.
- s_spar_map[i]);
- }
+ if (sbi->s_partitions)
+ for (i = 0; i < sbi->s_partitions; i++)
+ udf_free_partition(&sbi->s_partmaps[i]);
#ifdef CONFIG_UDF_NLS
if (UDF_QUERY_FLAG(sb, UDF_FLAG_NLS_MAP))
unload_nls(sbi->s_nls_map);
sb->s_fs_info = NULL;
}
-/*
- * udf_stat_fs
- *
- * PURPOSE
- * Return info about the filesystem.
- *
- * DESCRIPTION
- * Called by sys_statfs()
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
- */
static int udf_statfs(struct dentry *dentry, struct kstatfs *buf)
{
struct super_block *sb = dentry->d_sb;
return 0;
}
-static unsigned char udf_bitmap_lookup[16] = {
- 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
-};
-
static unsigned int udf_count_free_bitmap(struct super_block *sb,
struct udf_bitmap *bitmap)
{
int block = 0, newblock;
kernel_lb_addr loc;
uint32_t bytes;
- uint8_t value;
uint8_t *ptr;
uint16_t ident;
struct spaceBitmapDesc *bm;
ptr = (uint8_t *)bh->b_data;
while (bytes > 0) {
- while ((bytes > 0) && (index < sb->s_blocksize)) {
- value = ptr[index];
- accum += udf_bitmap_lookup[value & 0x0f];
- accum += udf_bitmap_lookup[value >> 4];
- index++;
- bytes--;
- }
+ u32 cur_bytes = min_t(u32, bytes, sb->s_blocksize - index);
+ accum += bitmap_weight((const unsigned long *)(ptr + index),
+ cur_bytes * 8);
+ bytes -= cur_bytes;
if (bytes) {
brelse(bh);
newblock = udf_get_lb_pblock(sb, loc, ++block);
#include <asm/uaccess.h>
#include <linux/errno.h>
#include <linux/fs.h>
-#include <linux/udf_fs.h>
#include <linux/time.h>
#include <linux/mm.h>
#include <linux/stat.h>
#include "udfdecl.h"
#include <linux/fs.h>
#include <linux/mm.h>
-#include <linux/udf_fs.h>
#include <linux/buffer_head.h>
#include "udf_i.h"
brelse(epos.bh);
}
+static void udf_update_alloc_ext_desc(struct inode *inode,
+ struct extent_position *epos,
+ u32 lenalloc)
+{
+ struct super_block *sb = inode->i_sb;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+
+ struct allocExtDesc *aed = (struct allocExtDesc *) (epos->bh->b_data);
+ int len = sizeof(struct allocExtDesc);
+
+ aed->lengthAllocDescs = cpu_to_le32(lenalloc);
+ if (!UDF_QUERY_FLAG(sb, UDF_FLAG_STRICT) || sbi->s_udfrev >= 0x0201)
+ len += lenalloc;
+
+ udf_update_tag(epos->bh->b_data, len);
+ mark_buffer_dirty_inode(epos->bh, inode);
+}
+
void udf_truncate_extents(struct inode *inode)
{
struct extent_position epos;
uint32_t elen, nelen = 0, indirect_ext_len = 0, lenalloc;
int8_t etype;
struct super_block *sb = inode->i_sb;
- struct udf_sb_info *sbi = UDF_SB(sb);
sector_t first_block = inode->i_size >> sb->s_blocksize_bits, offset;
loff_t byte_offset;
int adsize;
if (indirect_ext_len) {
/* We managed to free all extents in the
* indirect extent - free it too */
- if (!epos.bh)
- BUG();
+ BUG_ON(!epos.bh);
udf_free_blocks(sb, inode, epos.block,
0, indirect_ext_len);
- } else {
- if (!epos.bh) {
- iinfo->i_lenAlloc =
- lenalloc;
- mark_inode_dirty(inode);
- } else {
- struct allocExtDesc *aed =
- (struct allocExtDesc *)
- (epos.bh->b_data);
- int len =
- sizeof(struct allocExtDesc);
-
- aed->lengthAllocDescs =
- cpu_to_le32(lenalloc);
- if (!UDF_QUERY_FLAG(sb,
- UDF_FLAG_STRICT) ||
- sbi->s_udfrev >= 0x0201)
- len += lenalloc;
-
- udf_update_tag(epos.bh->b_data,
- len);
- mark_buffer_dirty_inode(
- epos.bh, inode);
- }
- }
+ } else if (!epos.bh) {
+ iinfo->i_lenAlloc = lenalloc;
+ mark_inode_dirty(inode);
+ } else
+ udf_update_alloc_ext_desc(inode,
+ &epos, lenalloc);
brelse(epos.bh);
epos.offset = sizeof(struct allocExtDesc);
epos.block = eloc;
}
if (indirect_ext_len) {
- if (!epos.bh)
- BUG();
+ BUG_ON(!epos.bh);
udf_free_blocks(sb, inode, epos.block, 0,
indirect_ext_len);
- } else {
- if (!epos.bh) {
- iinfo->i_lenAlloc = lenalloc;
- mark_inode_dirty(inode);
- } else {
- struct allocExtDesc *aed =
- (struct allocExtDesc *)(epos.bh->b_data);
- aed->lengthAllocDescs = cpu_to_le32(lenalloc);
- if (!UDF_QUERY_FLAG(sb, UDF_FLAG_STRICT) ||
- sbi->s_udfrev >= 0x0201)
- udf_update_tag(epos.bh->b_data,
- lenalloc +
- sizeof(struct allocExtDesc));
- else
- udf_update_tag(epos.bh->b_data,
- sizeof(struct allocExtDesc));
- mark_buffer_dirty_inode(epos.bh, inode);
- }
- }
+ } else if (!epos.bh) {
+ iinfo->i_lenAlloc = lenalloc;
+ mark_inode_dirty(inode);
+ } else
+ udf_update_alloc_ext_desc(inode, &epos, lenalloc);
} else if (inode->i_size) {
if (byte_offset) {
kernel_long_ad extent;
-#ifndef __LINUX_UDF_I_H
-#define __LINUX_UDF_I_H
+#ifndef _UDF_I_H
+#define _UDF_I_H
+
+struct udf_inode_info {
+ struct timespec i_crtime;
+ /* Physical address of inode */
+ kernel_lb_addr i_location;
+ __u64 i_unique;
+ __u32 i_lenEAttr;
+ __u32 i_lenAlloc;
+ __u64 i_lenExtents;
+ __u32 i_next_alloc_block;
+ __u32 i_next_alloc_goal;
+ unsigned i_alloc_type : 3;
+ unsigned i_efe : 1; /* extendedFileEntry */
+ unsigned i_use : 1; /* unallocSpaceEntry */
+ unsigned i_strat4096 : 1;
+ unsigned reserved : 26;
+ union {
+ short_ad *i_sad;
+ long_ad *i_lad;
+ __u8 *i_data;
+ } i_ext;
+ struct inode vfs_inode;
+};
-#include <linux/udf_fs_i.h>
static inline struct udf_inode_info *UDF_I(struct inode *inode)
{
return list_entry(inode, struct udf_inode_info, vfs_inode);
}
-#endif /* !defined(_LINUX_UDF_I_H) */
+#endif /* _UDF_I_H) */
#ifndef __LINUX_UDF_SB_H
#define __LINUX_UDF_SB_H
+#include <linux/mutex.h>
+
/* Since UDF 2.01 is ISO 13346 based... */
#define UDF_SUPER_MAGIC 0x15013346
-#define UDF_MAX_READ_VERSION 0x0201
+#define UDF_MAX_READ_VERSION 0x0250
#define UDF_MAX_WRITE_VERSION 0x0201
#define UDF_FLAG_USE_EXTENDED_FE 0
#define UDF_PART_FLAG_REWRITABLE 0x0040
#define UDF_PART_FLAG_OVERWRITABLE 0x0080
+#define UDF_MAX_BLOCK_LOADED 8
+
+#define UDF_TYPE1_MAP15 0x1511U
+#define UDF_VIRTUAL_MAP15 0x1512U
+#define UDF_VIRTUAL_MAP20 0x2012U
+#define UDF_SPARABLE_MAP15 0x1522U
+#define UDF_METADATA_MAP25 0x2511U
+
+#pragma pack(1) /* XXX(hch): Why? This file just defines in-core structures */
+
+struct udf_meta_data {
+ __u32 s_meta_file_loc;
+ __u32 s_mirror_file_loc;
+ __u32 s_bitmap_file_loc;
+ __u32 s_alloc_unit_size;
+ __u16 s_align_unit_size;
+ __u8 s_dup_md_flag;
+ struct inode *s_metadata_fe;
+ struct inode *s_mirror_fe;
+ struct inode *s_bitmap_fe;
+};
+
+struct udf_sparing_data {
+ __u16 s_packet_len;
+ struct buffer_head *s_spar_map[4];
+};
+
+struct udf_virtual_data {
+ __u32 s_num_entries;
+ __u16 s_start_offset;
+};
+
+struct udf_bitmap {
+ __u32 s_extLength;
+ __u32 s_extPosition;
+ __u16 s_nr_groups;
+ struct buffer_head **s_block_bitmap;
+};
+
+struct udf_part_map {
+ union {
+ struct udf_bitmap *s_bitmap;
+ struct inode *s_table;
+ } s_uspace;
+ union {
+ struct udf_bitmap *s_bitmap;
+ struct inode *s_table;
+ } s_fspace;
+ __u32 s_partition_root;
+ __u32 s_partition_len;
+ __u16 s_partition_type;
+ __u16 s_partition_num;
+ union {
+ struct udf_sparing_data s_sparing;
+ struct udf_virtual_data s_virtual;
+ struct udf_meta_data s_metadata;
+ } s_type_specific;
+ __u32 (*s_partition_func)(struct super_block *, __u32, __u16, __u32);
+ __u16 s_volumeseqnum;
+ __u16 s_partition_flags;
+};
+
+#pragma pack()
+
+struct udf_sb_info {
+ struct udf_part_map *s_partmaps;
+ __u8 s_volume_ident[32];
+
+ /* Overall info */
+ __u16 s_partitions;
+ __u16 s_partition;
+
+ /* Sector headers */
+ __s32 s_session;
+ __u32 s_anchor[3];
+ __u32 s_last_block;
+
+ struct buffer_head *s_lvid_bh;
+
+ /* Default permissions */
+ mode_t s_umask;
+ gid_t s_gid;
+ uid_t s_uid;
+
+ /* Root Info */
+ struct timespec s_record_time;
+
+ /* Fileset Info */
+ __u16 s_serial_number;
+
+ /* highest UDF revision we have recorded to this media */
+ __u16 s_udfrev;
+
+ /* Miscellaneous flags */
+ __u32 s_flags;
+
+ /* Encoding info */
+ struct nls_table *s_nls_map;
+
+ /* VAT inode */
+ struct inode *s_vat_inode;
+
+ struct mutex s_alloc_mutex;
+};
+
static inline struct udf_sb_info *UDF_SB(struct super_block *sb)
{
return sb->s_fs_info;
#ifndef __UDF_DECL_H
#define __UDF_DECL_H
-#include <linux/udf_fs.h>
#include "ecma_167.h"
#include "osta_udf.h"
#include <linux/fs.h>
#include <linux/types.h>
-#include <linux/udf_fs_i.h>
-#include <linux/udf_fs_sb.h>
#include <linux/buffer_head.h>
+#include <linux/udf_fs_i.h>
+#include "udf_sb.h"
#include "udfend.h"
+#include "udf_i.h"
+
+#define UDF_PREALLOCATE
+#define UDF_DEFAULT_PREALLOC_BLOCKS 8
+
+#define UDFFS_DEBUG
+
+#ifdef UDFFS_DEBUG
+#define udf_debug(f, a...) \
+do { \
+ printk(KERN_DEBUG "UDF-fs DEBUG %s:%d:%s: ", \
+ __FILE__, __LINE__, __func__); \
+ printk(f, ##a); \
+} while (0)
+#else
+#define udf_debug(f, a...) /**/
+#endif
+
+#define udf_info(f, a...) \
+ printk(KERN_INFO "UDF-fs INFO " f, ##a);
+
#define udf_fixed_to_variable(x) ( ( ( (x) >> 5 ) * 39 ) + ( (x) & 0x0000001F ) )
#define udf_variable_to_fixed(x) ( ( ( (x) / 39 ) << 5 ) + ( (x) % 39 ) )
#define UDF_NAME_LEN 256
#define UDF_PATH_LEN 1023
-#define udf_file_entry_alloc_offset(inode)\
- (UDF_I(inode)->i_use ?\
- sizeof(struct unallocSpaceEntry) :\
- ((UDF_I(inode)->i_efe ?\
- sizeof(struct extendedFileEntry) :\
- sizeof(struct fileEntry)) + UDF_I(inode)->i_lenEAttr))
-
-#define udf_ext0_offset(inode)\
- (UDF_I(inode)->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB ?\
- udf_file_entry_alloc_offset(inode) : 0)
+static inline size_t udf_file_entry_alloc_offset(struct inode *inode)
+{
+ struct udf_inode_info *iinfo = UDF_I(inode);
+ if (iinfo->i_use)
+ return sizeof(struct unallocSpaceEntry);
+ else if (iinfo->i_efe)
+ return sizeof(struct extendedFileEntry) + iinfo->i_lenEAttr;
+ else
+ return sizeof(struct fileEntry) + iinfo->i_lenEAttr;
+}
+
+static inline size_t udf_ext0_offset(struct inode *inode)
+{
+ if (UDF_I(inode)->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
+ return udf_file_entry_alloc_offset(inode);
+ else
+ return 0;
+}
#define udf_get_lb_pblock(sb,loc,offset) udf_get_pblock((sb), (loc).logicalBlockNum, (loc).partitionReferenceNum, (offset))
};
/* super.c */
-extern void udf_error(struct super_block *, const char *, const char *, ...);
extern void udf_warning(struct super_block *, const char *, const char *, ...);
/* namei.c */
uint32_t);
extern uint32_t udf_get_pblock_spar15(struct super_block *, uint32_t, uint16_t,
uint32_t);
+extern uint32_t udf_get_pblock_meta25(struct super_block *, uint32_t, uint16_t,
+ uint32_t);
extern int udf_relocate_blocks(struct super_block *, long, long *);
/* unicode.c */
extern int udf_put_filename(struct super_block *, const uint8_t *, uint8_t *,
int);
extern int udf_build_ustr(struct ustr *, dstring *, int);
-extern int udf_CS0toUTF8(struct ustr *, struct ustr *);
+extern int udf_CS0toUTF8(struct ustr *, const struct ustr *);
/* ialloc.c */
extern void udf_free_inode(struct inode *);
extern long_ad *udf_get_filelongad(uint8_t *, int, uint32_t *, int);
extern short_ad *udf_get_fileshortad(uint8_t *, int, uint32_t *, int);
-/* crc.c */
-extern uint16_t udf_crc(uint8_t *, uint32_t, uint16_t);
-
/* udftime.c */
-extern time_t *udf_stamp_to_time(time_t *, long *, kernel_timestamp);
-extern kernel_timestamp *udf_time_to_stamp(kernel_timestamp *, struct timespec);
+extern struct timespec *udf_disk_stamp_to_time(struct timespec *dest,
+ timestamp src);
+extern timestamp *udf_time_to_disk_stamp(timestamp *dest, struct timespec src);
#endif /* __UDF_DECL_H */
return out;
}
-static inline kernel_timestamp lets_to_cpu(timestamp in)
-{
- kernel_timestamp out;
-
- memcpy(&out, &in, sizeof(timestamp));
- out.typeAndTimezone = le16_to_cpu(in.typeAndTimezone);
- out.year = le16_to_cpu(in.year);
-
- return out;
-}
-
static inline short_ad lesa_to_cpu(short_ad in)
{
short_ad out;
return out;
}
-static inline timestamp cpu_to_lets(kernel_timestamp in)
-{
- timestamp out;
-
- memcpy(&out, &in, sizeof(timestamp));
- out.typeAndTimezone = cpu_to_le16(in.typeAndTimezone);
- out.year = cpu_to_le16(in.year);
-
- return out;
-}
-
#endif /* __UDF_ENDIAN_H */
#define SECS_PER_HOUR (60 * 60)
#define SECS_PER_DAY (SECS_PER_HOUR * 24)
-time_t *udf_stamp_to_time(time_t *dest, long *dest_usec, kernel_timestamp src)
+struct timespec *udf_disk_stamp_to_time(struct timespec *dest, timestamp src)
{
int yday;
- uint8_t type = src.typeAndTimezone >> 12;
+ u16 typeAndTimezone = le16_to_cpu(src.typeAndTimezone);
+ u16 year = le16_to_cpu(src.year);
+ uint8_t type = typeAndTimezone >> 12;
int16_t offset;
if (type == 1) {
- offset = src.typeAndTimezone << 4;
+ offset = typeAndTimezone << 4;
/* sign extent offset */
offset = (offset >> 4);
if (offset == -2047) /* unspecified offset */
offset = 0;
- } else {
+ } else
offset = 0;
- }
- if ((src.year < EPOCH_YEAR) ||
- (src.year >= EPOCH_YEAR + MAX_YEAR_SECONDS)) {
- *dest = -1;
- *dest_usec = -1;
+ if ((year < EPOCH_YEAR) ||
+ (year >= EPOCH_YEAR + MAX_YEAR_SECONDS)) {
return NULL;
}
- *dest = year_seconds[src.year - EPOCH_YEAR];
- *dest -= offset * 60;
+ dest->tv_sec = year_seconds[year - EPOCH_YEAR];
+ dest->tv_sec -= offset * 60;
- yday = ((__mon_yday[__isleap(src.year)][src.month - 1]) + src.day - 1);
- *dest += (((yday * 24) + src.hour) * 60 + src.minute) * 60 + src.second;
- *dest_usec = src.centiseconds * 10000 +
- src.hundredsOfMicroseconds * 100 + src.microseconds;
+ yday = ((__mon_yday[__isleap(year)][src.month - 1]) + src.day - 1);
+ dest->tv_sec += (((yday * 24) + src.hour) * 60 + src.minute) * 60 + src.second;
+ dest->tv_nsec = 1000 * (src.centiseconds * 10000 +
+ src.hundredsOfMicroseconds * 100 + src.microseconds);
return dest;
}
-kernel_timestamp *udf_time_to_stamp(kernel_timestamp *dest, struct timespec ts)
+timestamp *udf_time_to_disk_stamp(timestamp *dest, struct timespec ts)
{
long int days, rem, y;
const unsigned short int *ip;
if (!dest)
return NULL;
- dest->typeAndTimezone = 0x1000 | (offset & 0x0FFF);
+ dest->typeAndTimezone = cpu_to_le16(0x1000 | (offset & 0x0FFF));
ts.tv_sec += offset * 60;
days = ts.tv_sec / SECS_PER_DAY;
- LEAPS_THRU_END_OF(y - 1));
y = yg;
}
- dest->year = y;
+ dest->year = cpu_to_le16(y);
ip = __mon_yday[__isleap(y)];
for (y = 11; days < (long int)ip[y]; --y)
continue;
#include <linux/kernel.h>
#include <linux/string.h> /* for memset */
#include <linux/nls.h>
-#include <linux/udf_fs.h>
+#include <linux/crc-itu-t.h>
#include "udf_sb.h"
{
int usesize;
- if ((!dest) || (!ptr) || (!size))
+ if (!dest || !ptr || !size)
return -1;
+ BUG_ON(size < 2);
- memset(dest, 0, sizeof(struct ustr));
- usesize = (size > UDF_NAME_LEN) ? UDF_NAME_LEN : size;
+ usesize = min_t(size_t, ptr[size - 1], sizeof(dest->u_name));
+ usesize = min(usesize, size - 2);
dest->u_cmpID = ptr[0];
- dest->u_len = ptr[size - 1];
- memcpy(dest->u_name, ptr + 1, usesize - 1);
+ dest->u_len = usesize;
+ memcpy(dest->u_name, ptr + 1, usesize);
+ memset(dest->u_name + usesize, 0, sizeof(dest->u_name) - usesize);
return 0;
}
* PURPOSE
* Convert OSTA Compressed Unicode to the UTF-8 equivalent.
*
- * DESCRIPTION
- * This routine is only called by udf_filldir().
- *
* PRE-CONDITIONS
* utf Pointer to UTF-8 output buffer.
* ocu Pointer to OSTA Compressed Unicode input buffer
* November 12, 1997 - Andrew E. Mileski
* Written, tested, and released.
*/
-int udf_CS0toUTF8(struct ustr *utf_o, struct ustr *ocu_i)
+int udf_CS0toUTF8(struct ustr *utf_o, const struct ustr *ocu_i)
{
- uint8_t *ocu;
- uint32_t c;
+ const uint8_t *ocu;
uint8_t cmp_id, ocu_len;
int i;
- ocu = ocu_i->u_name;
-
ocu_len = ocu_i->u_len;
- cmp_id = ocu_i->u_cmpID;
- utf_o->u_len = 0;
-
if (ocu_len == 0) {
memset(utf_o, 0, sizeof(struct ustr));
- utf_o->u_cmpID = 0;
- utf_o->u_len = 0;
return 0;
}
- if ((cmp_id != 8) && (cmp_id != 16)) {
+ cmp_id = ocu_i->u_cmpID;
+ if (cmp_id != 8 && cmp_id != 16) {
+ memset(utf_o, 0, sizeof(struct ustr));
printk(KERN_ERR "udf: unknown compression code (%d) stri=%s\n",
cmp_id, ocu_i->u_name);
return 0;
}
+ ocu = ocu_i->u_name;
+ utf_o->u_len = 0;
for (i = 0; (i < ocu_len) && (utf_o->u_len <= (UDF_NAME_LEN - 3));) {
/* Expand OSTA compressed Unicode to Unicode */
- c = ocu[i++];
+ uint32_t c = ocu[i++];
if (cmp_id == 16)
c = (c << 8) | ocu[i++];
/* Compress Unicode to UTF-8 */
- if (c < 0x80U) {
+ if (c < 0x80U)
utf_o->u_name[utf_o->u_len++] = (uint8_t)c;
- } else if (c < 0x800U) {
+ else if (c < 0x800U) {
utf_o->u_name[utf_o->u_len++] =
(uint8_t)(0xc0 | (c >> 6));
utf_o->u_name[utf_o->u_len++] =
}
static int udf_CS0toNLS(struct nls_table *nls, struct ustr *utf_o,
- struct ustr *ocu_i)
+ const struct ustr *ocu_i)
{
- uint8_t *ocu;
- uint32_t c;
+ const uint8_t *ocu;
uint8_t cmp_id, ocu_len;
int i;
- ocu = ocu_i->u_name;
ocu_len = ocu_i->u_len;
- cmp_id = ocu_i->u_cmpID;
- utf_o->u_len = 0;
-
if (ocu_len == 0) {
memset(utf_o, 0, sizeof(struct ustr));
- utf_o->u_cmpID = 0;
- utf_o->u_len = 0;
return 0;
}
- if ((cmp_id != 8) && (cmp_id != 16)) {
+ cmp_id = ocu_i->u_cmpID;
+ if (cmp_id != 8 && cmp_id != 16) {
+ memset(utf_o, 0, sizeof(struct ustr));
printk(KERN_ERR "udf: unknown compression code (%d) stri=%s\n",
cmp_id, ocu_i->u_name);
return 0;
}
+ ocu = ocu_i->u_name;
+ utf_o->u_len = 0;
for (i = 0; (i < ocu_len) && (utf_o->u_len <= (UDF_NAME_LEN - 3));) {
/* Expand OSTA compressed Unicode to Unicode */
- c = ocu[i++];
+ uint32_t c = ocu[i++];
if (cmp_id == 16)
c = (c << 8) | ocu[i++];
} else if (newIndex > 250)
newIndex = 250;
newName[newIndex++] = CRC_MARK;
- valueCRC = udf_crc(fidName, fidNameLen, 0);
+ valueCRC = crc_itu_t(0, fidName, fidNameLen);
newName[newIndex++] = hexChar[(valueCRC & 0xf000) >> 12];
newName[newIndex++] = hexChar[(valueCRC & 0x0f00) >> 8];
newName[newIndex++] = hexChar[(valueCRC & 0x00f0) >> 4];
#include <linux/file.h>
#include <linux/fs.h>
#include <linux/linkage.h>
+#include <linux/mount.h>
#include <linux/namei.h>
#include <linux/sched.h>
#include <linux/stat.h>
struct inode *inode;
struct iattr newattrs;
struct file *f = NULL;
+ struct vfsmount *mnt;
error = -EINVAL;
if (times && (!nsec_valid(times[0].tv_nsec) ||
if (!f)
goto out;
dentry = f->f_path.dentry;
+ mnt = f->f_path.mnt;
} else {
error = __user_walk_fd(dfd, filename, (flags & AT_SYMLINK_NOFOLLOW) ? 0 : LOOKUP_FOLLOW, &nd);
if (error)
goto out;
dentry = nd.path.dentry;
+ mnt = nd.path.mnt;
}
inode = dentry->d_inode;
- error = -EROFS;
- if (IS_RDONLY(inode))
+ error = mnt_want_write(mnt);
+ if (error)
goto dput_and_out;
/* Don't worry, the checks are done in inode_change_ok() */
if (times) {
error = -EPERM;
if (IS_APPEND(inode) || IS_IMMUTABLE(inode))
- goto dput_and_out;
+ goto mnt_drop_write_and_out;
if (times[0].tv_nsec == UTIME_OMIT)
newattrs.ia_valid &= ~ATTR_ATIME;
} else {
error = -EACCES;
if (IS_IMMUTABLE(inode))
- goto dput_and_out;
+ goto mnt_drop_write_and_out;
if (!is_owner_or_cap(inode)) {
if (f) {
if (!(f->f_mode & FMODE_WRITE))
- goto dput_and_out;
+ goto mnt_drop_write_and_out;
} else {
error = vfs_permission(&nd, MAY_WRITE);
if (error)
- goto dput_and_out;
+ goto mnt_drop_write_and_out;
}
}
}
mutex_lock(&inode->i_mutex);
error = notify_change(dentry, &newattrs);
mutex_unlock(&inode->i_mutex);
+mnt_drop_write_and_out:
+ mnt_drop_write(mnt);
dput_and_out:
if (f)
fput(f);
#include <linux/slab.h>
#include <linux/file.h>
#include <linux/xattr.h>
+#include <linux/mount.h>
#include <linux/namei.h>
#include <linux/security.h>
#include <linux/syscalls.h>
* filesystem or on an immutable / append-only inode.
*/
if (mask & MAY_WRITE) {
- if (IS_RDONLY(inode))
- return -EROFS;
if (IS_IMMUTABLE(inode) || IS_APPEND(inode))
return -EPERM;
}
error = user_path_walk(path, &nd);
if (error)
return error;
- error = setxattr(nd.path.dentry, name, value, size, flags);
+ error = mnt_want_write(nd.path.mnt);
+ if (!error) {
+ error = setxattr(nd.path.dentry, name, value, size, flags);
+ mnt_drop_write(nd.path.mnt);
+ }
path_put(&nd.path);
return error;
}
error = user_path_walk_link(path, &nd);
if (error)
return error;
- error = setxattr(nd.path.dentry, name, value, size, flags);
+ error = mnt_want_write(nd.path.mnt);
+ if (!error) {
+ error = setxattr(nd.path.dentry, name, value, size, flags);
+ mnt_drop_write(nd.path.mnt);
+ }
path_put(&nd.path);
return error;
}
return error;
dentry = f->f_path.dentry;
audit_inode(NULL, dentry);
- error = setxattr(dentry, name, value, size, flags);
+ error = mnt_want_write(f->f_path.mnt);
+ if (!error) {
+ error = setxattr(dentry, name, value, size, flags);
+ mnt_drop_write(f->f_path.mnt);
+ }
+out_fput:
fput(f);
return error;
}
error = user_path_walk(path, &nd);
if (error)
return error;
- error = removexattr(nd.path.dentry, name);
+ error = mnt_want_write(nd.path.mnt);
+ if (!error) {
+ error = removexattr(nd.path.dentry, name);
+ mnt_drop_write(nd.path.mnt);
+ }
path_put(&nd.path);
return error;
}
error = user_path_walk_link(path, &nd);
if (error)
return error;
- error = removexattr(nd.path.dentry, name);
+ error = mnt_want_write(nd.path.mnt);
+ if (!error) {
+ error = removexattr(nd.path.dentry, name);
+ mnt_drop_write(nd.path.mnt);
+ }
path_put(&nd.path);
return error;
}
return error;
dentry = f->f_path.dentry;
audit_inode(NULL, dentry);
- error = removexattr(dentry, name);
+ error = mnt_want_write(f->f_path.mnt);
+ if (!error) {
+ error = removexattr(dentry, name);
+ mnt_drop_write(f->f_path.mnt);
+ }
fput(f);
return error;
}
#include <linux/time.h>
#include <linux/wait.h>
+#include <linux/semaphore.h>
#include <asm/atomic.h>
-#include <asm/semaphore.h>
/*
* sema_t structure just maps to struct semaphore in Linux kernel.
char *kbuf;
int error = EFAULT;
- if (IS_RDONLY(inode))
- return -EROFS;
if (IS_IMMUTABLE(inode) || IS_APPEND(inode))
return EPERM;
if (len > XATTR_SIZE_MAX)
char *name,
__uint32_t flags)
{
- if (IS_RDONLY(inode))
- return -EROFS;
if (IS_IMMUTABLE(inode) || IS_APPEND(inode))
return EPERM;
return xfs_attr_remove(XFS_I(inode), name, flags);
xfs_attrmulti_by_handle(
xfs_mount_t *mp,
void __user *arg,
+ struct file *parfilp,
struct inode *parinode)
{
int error;
&ops[i].am_length, ops[i].am_flags);
break;
case ATTR_OP_SET:
+ ops[i].am_error = mnt_want_write(parfilp->f_path.mnt);
+ if (ops[i].am_error)
+ break;
ops[i].am_error = xfs_attrmulti_attr_set(inode,
attr_name, ops[i].am_attrvalue,
ops[i].am_length, ops[i].am_flags);
+ mnt_drop_write(parfilp->f_path.mnt);
break;
case ATTR_OP_REMOVE:
+ ops[i].am_error = mnt_want_write(parfilp->f_path.mnt);
+ if (ops[i].am_error)
+ break;
ops[i].am_error = xfs_attrmulti_attr_remove(inode,
attr_name, ops[i].am_flags);
+ mnt_drop_write(parfilp->f_path.mnt);
break;
default:
ops[i].am_error = EINVAL;
return xfs_attrlist_by_handle(mp, arg, inode);
case XFS_IOC_ATTRMULTI_BY_HANDLE:
- return xfs_attrmulti_by_handle(mp, arg, inode);
+ return xfs_attrmulti_by_handle(mp, arg, filp, inode);
case XFS_IOC_SWAPEXT: {
error = xfs_swapext((struct xfs_swapext __user *)arg);
*/
ASSERT((flags & XFS_ICHGTIME_ACC) == 0);
- /*
- * We're not supposed to change timestamps in readonly-mounted
- * filesystems. Throw it away if anyone asks us.
- */
- if (unlikely(IS_RDONLY(inode)))
- return;
-
if (flags & XFS_ICHGTIME_MOD) {
tvp = &inode->i_mtime;
ip->i_d.di_mtime.t_sec = (__int32_t)tvp->tv_sec;
#include "xfs_vnodeops.h"
#include <linux/capability.h>
+#include <linux/mount.h>
#include <linux/writeback.h>
if (new_size > xip->i_size)
xip->i_new_size = new_size;
- if (likely(!(ioflags & IO_INVIS))) {
+ /*
+ * We're not supposed to change timestamps in readonly-mounted
+ * filesystems. Throw it away if anyone asks us.
+ */
+ if (likely(!(ioflags & IO_INVIS) &&
+ !mnt_want_write(file->f_path.mnt))) {
file_update_time(file);
xfs_ichgtime_fast(xip, inode,
XFS_ICHGTIME_MOD | XFS_ICHGTIME_CHG);
+ mnt_drop_write(file->f_path.mnt);
}
/*
#define pcibus_to_cpumask(bus) (cpu_online_map)
-#else /* CONFIG_NUMA */
-# include <asm-generic/topology.h>
#endif /* !CONFIG_NUMA */
+# include <asm-generic/topology.h>
#endif /* _ASM_ALPHA_TOPOLOGY_H */
#ifndef AT91_ECC_H
#define AT91_ECC_H
-#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
+#define AT91_ECC_CR 0x00 /* Control register */
#define AT91_ECC_RST (1 << 0) /* Reset parity */
-#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
+#define AT91_ECC_MR 0x04 /* Mode register */
#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
#define AT91_ECC_PAGESIZE_528 (0)
#define AT91_ECC_PAGESIZE_1056 (1)
#define AT91_ECC_PAGESIZE_2112 (2)
#define AT91_ECC_PAGESIZE_4224 (3)
-#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
+#define AT91_ECC_SR 0x08 /* Status register */
#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
-#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
+#define AT91_ECC_PR 0x0c /* Parity register */
#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
-#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
+#define AT91_ECC_NPR 0x10 /* NParity register */
#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
#endif
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
-#define AT91_PMC_MDIV_1 (0 << 8)
-#define AT91_PMC_MDIV_2 (1 << 8)
-#define AT91_PMC_MDIV_3 (2 << 8)
-#define AT91_PMC_MDIV_4 (3 << 8)
+#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
+#define AT91RM9200_PMC_MDIV_2 (1 << 8)
+#define AT91RM9200_PMC_MDIV_3 (2 << 8)
+#define AT91RM9200_PMC_MDIV_4 (3 << 8)
+#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
+#define AT91SAM9_PMC_MDIV_2 (1 << 8)
+#define AT91SAM9_PMC_MDIV_4 (2 << 8)
+#define AT91SAM9_PMC_MDIV_6 (3 << 8)
+#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
+#define AT91_PMC_PDIV_1 (0 << 12)
+#define AT91_PMC_PDIV_2 (1 << 12)
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
#define AT91_SHDW_WKMODE0_LOW 2
#define AT91_SHDW_WKMODE0_ANYLEVEL 3
#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
+#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
+#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
#endif
--- /dev/null
+/*
+ * include/asm-arm/arch-at91/at91cap9_ddrsdr.h
+ *
+ * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
+ * Based on AT91CAP9 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91CAP9_DDRSDR_H
+#define AT91CAP9_DDRSDR_H
+
+#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */
+#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
+#define AT91_DDRSDRC_MODE_NORMAL 0
+#define AT91_DDRSDRC_MODE_NOP 1
+#define AT91_DDRSDRC_MODE_PRECHARGE 2
+#define AT91_DDRSDRC_MODE_LMR 3
+#define AT91_DDRSDRC_MODE_REFRESH 4
+#define AT91_DDRSDRC_MODE_EXT_LMR 5
+#define AT91_DDRSDRC_MODE_DEEP 6
+
+#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */
+#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
+
+#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */
+#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
+#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
+#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
+#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
+#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
+#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
+#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
+#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
+#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
+#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
+#define AT91_DDRSDRC_NR_11 (0 << 2)
+#define AT91_DDRSDRC_NR_12 (1 << 2)
+#define AT91_DDRSDRC_NR_13 (2 << 2)
+#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
+#define AT91_DDRSDRC_CAS_2 (2 << 4)
+#define AT91_DDRSDRC_CAS_3 (3 << 4)
+#define AT91_DDRSDRC_CAS_25 (6 << 4)
+#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
+#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
+
+#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */
+#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
+#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
+#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
+#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
+#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
+#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
+#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
+#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
+
+#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */
+#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
+#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
+#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
+#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
+
+#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */
+#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
+#define AT91_DDRSDRC_LPCB_DISABLE 0
+#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
+#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
+#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
+#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
+#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
+#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
+#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
+#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
+#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
+#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
+#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
+
+#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */
+#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
+#define AT91_DDRSDRC_MD_SDR 0
+#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
+#define AT91_DDRSDRC_MD_DDR 2
+#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
+
+#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */
+#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
+#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
+#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
+#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
+#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
+#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
+#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
+#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
+#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
+
+
+#endif
/*
- * include/asm-arm/arch-at91/at91sam926x_mc.h
+ * include/asm-arm/arch-at91/at91sam9_sdramc.h
*
- * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
+ * SDRAM Controllers (SDRAMC) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*/
-#ifndef AT91SAM926x_MC_H
-#define AT91SAM926x_MC_H
+#ifndef AT91SAM9_SDRAMC_H
+#define AT91SAM9_SDRAMC_H
/* SDRAM Controller (SDRAMC) registers */
#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
-#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
+#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
-/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
-#define AT91_SMC_NWESETUP_(x) ((x) << 0)
-#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
-#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
-#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
-#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
-#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
-#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
-
-#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
-#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
-#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
-#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
-#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
-#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
-#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-
-#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
-#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
-#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
-#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
-
-#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
-#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
-#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
-#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
-#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
-#define AT91_SMC_EXNWMODE_READY (3 << 4)
-#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
-#define AT91_SMC_BAT_SELECT (0 << 8)
-#define AT91_SMC_BAT_WRITE (1 << 8)
-#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
-#define AT91_SMC_DBW_8 (0 << 12)
-#define AT91_SMC_DBW_16 (1 << 12)
-#define AT91_SMC_DBW_32 (2 << 12)
-#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
-#define AT91_SMC_TDF_(x) ((x) << 16)
-#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
-#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
-#define AT91_SMC_PS (3 << 28) /* Page Size */
-#define AT91_SMC_PS_4 (0 << 28)
-#define AT91_SMC_PS_8 (1 << 28)
-#define AT91_SMC_PS_16 (2 << 28)
-#define AT91_SMC_PS_32 (3 << 28)
-
-#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
-
#endif
--- /dev/null
+/*
+ * include/asm-arm/arch-at91/at91sam9_smc.h
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9_SMC_H
+#define AT91SAM9_SMC_H
+
+#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
+#define AT91_SMC_NWESETUP_(x) ((x) << 0)
+#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
+#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
+#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
+#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
+#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
+#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
+
+#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
+#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
+#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
+#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
+#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
+#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
+#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+
+#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
+#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
+#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
+#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
+
+#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
+#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
+#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
+#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
+#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
+#define AT91_SMC_EXNWMODE_READY (3 << 4)
+#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
+#define AT91_SMC_BAT_SELECT (0 << 8)
+#define AT91_SMC_BAT_WRITE (1 << 8)
+#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
+#define AT91_SMC_DBW_8 (0 << 12)
+#define AT91_SMC_DBW_16 (1 << 12)
+#define AT91_SMC_DBW_32 (2 << 12)
+#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
+#define AT91_SMC_TDF_(x) ((x) << 16)
+#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
+#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
+#define AT91_SMC_PS (3 << 28) /* Page Size */
+#define AT91_SMC_PS_4 (0 << 28)
+#define AT91_SMC_PS_8 (1 << 28)
+#define AT91_SMC_PS_16 (2 << 28)
+#define AT91_SMC_PS_32 (3 << 28)
+
+#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
+#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#endif
+
+#endif
/* new generic GPIO API - see Documentation/gpio.txt */
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- if (gpio > EP93XX_GPIO_LINE_MAX)
- return -EINVAL;
- return 0;
-}
+#include <asm-generic/gpio.h>
-static inline void gpio_free(unsigned gpio)
-{
-}
-
-int gpio_direction_input(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
-void gpio_set_value(unsigned gpio, int value);
-
-#include <asm-generic/gpio.h> /* cansleep wrappers */
+#define gpio_get_value __gpio_get_value
+#define gpio_set_value __gpio_set_value
+#define gpio_cansleep __gpio_cansleep
/*
* Map GPIO A0..A7 (0..7) to irq 64..71,
* B0..B7 (7..15) to irq 72..79, and
* F0..F7 (16..24) to irq 80..87.
*/
-
static inline int gpio_to_irq(unsigned gpio)
{
if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ)
extern void __init ks8695_add_device_lan(void);
extern void __init ks8695_add_device_hpna(void);
+ /* LEDs */
+extern short ks8695_leds_cpu;
+extern short ks8695_leds_timer;
+extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
+
/* PCI */
#define KS8695_MODE_PCI 0
#define KS8695_MODE_MINIPCI 1
#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-/*!
- * @name PBC Controller parameters
- */
-/*! @{ */
-/*!
- * Base address of PBC controller
- */
+/* Base address of PBC controller */
#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
/* Offsets for the PBC Controller register */
-/*!
- * PBC Board status register offset
- */
+
+/* PBC Board status register offset */
#define PBC_BSTAT 0x000002
-/*!
- * PBC Board control register 1 set address.
- */
+
+/* PBC Board control register 1 set address */
#define PBC_BCTRL1_SET 0x000004
-/*!
- * PBC Board control register 1 clear address.
- */
+
+/* PBC Board control register 1 clear address */
#define PBC_BCTRL1_CLEAR 0x000006
-/*!
- * PBC Board control register 2 set address.
- */
+
+/* PBC Board control register 2 set address */
#define PBC_BCTRL2_SET 0x000008
-/*!
- * PBC Board control register 2 clear address.
- */
+
+/* PBC Board control register 2 clear address */
#define PBC_BCTRL2_CLEAR 0x00000A
-/*!
- * PBC Board control register 3 set address.
- */
+
+/* PBC Board control register 3 set address */
#define PBC_BCTRL3_SET 0x00000C
-/*!
- * PBC Board control register 3 clear address.
- */
+
+/* PBC Board control register 3 clear address */
#define PBC_BCTRL3_CLEAR 0x00000E
-/*!
- * PBC Board control register 4 set address.
- */
+
+/* PBC Board control register 4 set address */
#define PBC_BCTRL4_SET 0x000010
-/*!
- * PBC Board control register 4 clear address.
- */
+
+/* PBC Board control register 4 clear address */
#define PBC_BCTRL4_CLEAR 0x000012
-/*!
- * PBC Board status register 1.
- */
+
+/* PBC Board status register 1 */
#define PBC_BSTAT1 0x000014
-/*!
- * PBC Board interrupt status register.
- */
+
+/* PBC Board interrupt status register */
#define PBC_INTSTATUS 0x000016
-/*!
- * PBC Board interrupt current status register.
- */
+
+/* PBC Board interrupt current status register */
#define PBC_INTCURR_STATUS 0x000018
-/*!
- * PBC Interrupt mask register set address.
- */
+
+/* PBC Interrupt mask register set address */
#define PBC_INTMASK_SET 0x00001A
-/*!
- * PBC Interrupt mask register clear address.
- */
+
+/* PBC Interrupt mask register clear address */
#define PBC_INTMASK_CLEAR 0x00001C
-/*!
- * External UART A.
- */
+/* External UART A */
#define PBC_SC16C652_UARTA 0x010000
-/*!
- * External UART B.
- */
+
+/* External UART B */
#define PBC_SC16C652_UARTB 0x010010
-/*!
- * Ethernet Controller IO base address.
- */
+
+/* Ethernet Controller IO base address */
#define PBC_CS8900A_IOBASE 0x020000
-/*!
- * Ethernet Controller Memory base address.
- */
+
+/* Ethernet Controller Memory base address */
#define PBC_CS8900A_MEMBASE 0x021000
-/*!
- * Ethernet Controller DMA base address.
- */
+
+/* Ethernet Controller DMA base address */
#define PBC_CS8900A_DMABASE 0x022000
-/*!
- * External chip select 0.
- */
+
+/* External chip select 0 */
#define PBC_XCS0 0x040000
-/*!
- * LCD Display enable.
- */
+
+/* LCD Display enable */
#define PBC_LCD_EN_B 0x060000
-/*!
- * Code test debug enable.
- */
+
+/* Code test debug enable */
#define PBC_CODE_B 0x070000
-/*!
- * PSRAM memory select.
- */
+
+/* PSRAM memory select */
#define PBC_PSRAM_B 0x5000000
#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
#define MXC_MAX_EXP_IO_LINES 16
-#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
#ifndef __ASM_ARCH_MXC_DMA_H__
#define __ASM_ARCH_MXC_DMA_H__
-/*!
- * @file dma.h
- * @brief This file contains Unified DMA API for all MXC platforms.
- * The API is platform independent.
- *
- * @ingroup SDMA
- */
#endif
* published by the Free Software Foundation.
*/
-/*!
- * @file hardware.h
- * @brief This file contains the hardware definitions of the board.
- *
- * @ingroup System
- */
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#define __ASM_ARCH_MXC_HARDWARE_H__
#include <asm/sizes.h>
-#include <asm/arch/mx31.h>
+#ifdef CONFIG_ARCH_MX3
+# include <asm/arch/mx31.h>
+#endif
#include <asm/arch/mxc.h>
-#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
-
/*
* ---------------------------------------------------------------------------
* Board specific defines
* ---------------------------------------------------------------------------
*/
-#define MXC_EXP_IO_BASE (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES)
-
-#include <asm/arch/board-mx31ads.h>
-
-#ifndef MXC_MAX_EXP_IO_LINES
-#define MXC_MAX_EXP_IO_LINES 0
+#ifdef CONFIG_MACH_MX31ADS
+# include <asm/arch/board-mx31ads.h>
#endif
-#define MXC_MAX_VIRTUAL_INTS 16
-#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
-#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
-#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
-#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
-
-#define MXC_MAX_INTS (MXC_MAX_INT_LINES + \
- MXC_MAX_GPIO_LINES + \
- MXC_MAX_EXP_IO_LINES + \
- MXC_MAX_VIRTUAL_INTS)
-
-#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
+#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
* published by the Free Software Foundation.
*/
-/*!
- * @file io.h
- * @brief This file contains some memory mapping macros.
- * @note There is no real ISA or PCI buses. But have to define these macros
- * for some drivers to compile.
- *
- * @ingroup System
- */
-
#ifndef __ASM_ARCH_MXC_IO_H__
#define __ASM_ARCH_MXC_IO_H__
-/*! Allow IO space to be anywhere in the memory */
+/* Allow IO space to be anywhere in the memory */
#define IO_SPACE_LIMIT 0xffffffff
-/*!
- * io address mapping macro
- */
+/* io address mapping macro */
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#include <asm/hardware.h>
-/*!
- * @file irqs.h
- * @brief This file defines the number of normal interrupts and fast interrupts
- *
- * @ingroup Interrupt
- */
-
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
-/*!
- * Number of normal interrupts
- */
-#define NR_IRQS MXC_MAX_INTS
+/* Number of normal interrupts */
+#define NR_IRQS (MXC_MAX_INT_LINES + \
+ MXC_MAX_GPIO_LINES + \
+ MXC_MAX_VIRTUAL_INTS)
-/*!
- * Number of fast interrupts
- */
+/* Number of fast interrupts */
#define NR_FIQS MXC_MAX_INTS
-#endif /* __ASM_ARCH_MXC_IRQS_H__ */
+#endif /* __ASM_ARCH_MXC_IRQS_H__ */
#include <asm/hardware.h>
-/*!
- * @file memory.h
- * @brief This file contains macros needed by the Linux kernel and drivers.
- *
- * @ingroup Memory
- */
-
-/*!
+/*
* Virtual view <-> DMA view memory address translations
* This macro is used to translate the virtual address to an address
* suitable to be passed to set_dma_addr()
*/
#define __virt_to_bus(a) __virt_to_phys(a)
-/*!
+/*
* Used to convert an address for DMA operations to an address that the
* kernel can use.
*/
#define __bus_to_virt(a) __phys_to_virt(a)
-#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
+#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
#define MXC_MAX_INT_LINES 64
#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES
+#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
+#define MXC_MAX_VIRTUAL_INTS 16
/*!
* Number of GPIO port as defined in the IC Spec
#define PROD_SIGNATURE 0x1 /* For MX31 */
+/* silicon revisions specific to i.MX31 */
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_1 0x11
+#define CHIP_REV_1_2 0x12
+#define CHIP_REV_1_3 0x13
+#define CHIP_REV_2_0 0x20
+#define CHIP_REV_2_1 0x21
+#define CHIP_REV_2_2 0x22
+#define CHIP_REV_2_3 0x23
+#define CHIP_REV_3_0 0x30
+#define CHIP_REV_3_1 0x31
+#define CHIP_REV_3_2 0x32
+
#define SYSTEM_REV_MIN CHIP_REV_1_0
#define SYSTEM_REV_NUM 3
-#endif /* __ASM_ARCH_MXC_MX31_H__ */
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+
+/* this is a i.MX31 CPU */
+#define cpu_is_mx31() (1)
+
+extern unsigned int system_rev;
+
+static inline int mx31_revision(void)
+{
+ return system_rev;
+}
+#endif
+
+#endif /* __ASM_ARCH_MXC_MX31_H__ */
#error "Do not include directly."
#endif
+/* clean up all things that are not used */
+#ifndef CONFIG_ARCH_MX3
+# define cpu_is_mx31() (0)
+#endif
+
/*
*****************************************
* GPT Register definitions *
#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
-/*!
- * GPT Control register bit definitions
- */
+/* GPT Control register bit definitions */
#define GPTCR_FO3 (1 << 31)
#define GPTCR_FO2 (1 << 30)
#define GPTCR_FO1 (1 << 29)
#define IIM_PROD_REV_SH 3
#define IIM_PROD_REV_LEN 5
-#endif /* __ASM_ARCH_MXC_H__ */
+#endif /* __ASM_ARCH_MXC_H__ */
#ifndef __ASM_ARCH_MXC_SYSTEM_H__
#define __ASM_ARCH_MXC_SYSTEM_H__
-/*!
- * @file system.h
- * @brief This file contains idle and reset functions.
- *
- * @ingroup System
- */
-
-/*!
- * This function puts the CPU into idle mode. It is called by default_idle()
- * in process.c file.
- */
static inline void arch_idle(void)
{
cpu_do_idle();
}
-/*
- * This function resets the system. It is called by machine_restart().
- *
- * @param mode indicates different kinds of resets
- */
static inline void arch_reset(char mode)
{
cpu_reset(0);
}
-#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
+#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
#ifndef __ASM_ARCH_MXC_VMALLOC_H__
#define __ASM_ARCH_MXC_VMALLOC_H__
-/*!
- * @file vmalloc.h
- *
- * @brief This file contains platform specific macros for vmalloc.
- *
- * @ingroup System
- */
-
-/*!
- * vmalloc ending address
- */
+/* vmalloc ending address */
#define VMALLOC_END 0xF4000000
-#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
+#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
/*
* include/asm-arm/arch-ns9xxx/board.h
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
#include <asm/mach-types.h>
-#define board_is_a9m9750dev() (machine_is_cc9p9360dev())
+#define board_is_a9m9750dev() (0 \
+ || machine_is_cc9p9360dev() \
+ || machine_is_cc9p9750dev() \
+ )
-#define board_is_jscc9p9360() (machine_is_cc9p9360js())
+#define board_is_a9mvali() (0 \
+ || machine_is_cc9p9360val() \
+ || machine_is_cc9p9750val() \
+ )
+
+#define board_is_jscc9p9210() (0 \
+ || machine_is_cc9p9210js() \
+ )
+
+#define board_is_jscc9p9215() (0 \
+ || machine_is_cc9p9215js() \
+ )
+
+#define board_is_jscc9p9360() (0 \
+ || machine_is_cc9p9360js() \
+ )
+
+#define board_is_uncbas() (0 \
+ || machine_is_cc7ucamry() \
+ )
#endif /* ifndef __ASM_ARCH_BOARD_H */
+++ /dev/null
-/*
- * include/asm-arm/arch-ns9xxx/clock.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#include <asm/arch-ns9xxx/regs-sys.h>
-
-#define CRYSTAL 29491200 /* Hz */
-
-/* The HRM calls this value f_vco */
-static inline u32 ns9xxx_systemclock(void) __attribute__((const));
-static inline u32 ns9xxx_systemclock(void)
-{
- u32 pll = __raw_readl(SYS_PLL);
-
- /*
- * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in
- * time.c).
- *
- * The following values are given:
- * - TIMERCLOCKSELECT == 2^i for an i in {0 .. 6}
- * - CRYSTAL == 29491200 == 2^17 * 3^2 * 5^2
- * - ND in {0 .. 31}
- * - FS in {0 .. 3}
- *
- * Assuming the worst, we consider:
- * - TIMERCLOCKSELECT == 64
- * - ND == 0
- * - FS == 3
- *
- * So HZ should be a divisor of:
- * (CRYSTAL * (ND + 1) >> FS) / TIMERCLOCKSELECT
- * == (2^17 * 3^2 * 5^2 * 1 >> 3) / 64
- * == 2^8 * 3^2 * 5^2
- * == 57600
- *
- * Currently HZ is defined to be 100 for this platform.
- *
- * Fine.
- */
- return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
- >> REGGETIM(pll, SYS_PLL, FS);
-}
-
-static inline u32 ns9xxx_cpuclock(void) __attribute__((const));
-static inline u32 ns9xxx_cpuclock(void)
-{
- return ns9xxx_systemclock() / 2;
-}
-
-static inline u32 ns9xxx_ahbclock(void) __attribute__((const));
-static inline u32 ns9xxx_ahbclock(void)
-{
- return ns9xxx_systemclock() / 4;
-}
-
-static inline u32 ns9xxx_bbusclock(void) __attribute__((const));
-static inline u32 ns9xxx_bbusclock(void)
-{
- return ns9xxx_systemclock() / 8;
-}
-
-#endif /* ifndef __ASM_ARCH_CLOCK_H */
/*
* include/asm-arm/arch-ns9xxx/entry-macro.S
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* the Free Software Foundation.
*/
#include <asm/hardware.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/regs-sys-common.h>
.macro get_irqnr_preamble, base, tmp
+ ldr \base, =SYS_ISRADDR
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \base, =SYS_ISRADDR
ldr \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)]
cmp \irqstat, #0
ldrne \irqnr, [\base]
/*
* include/asm-arm/arch-ns9xxx/irqs.h
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
-#define IRQ_WATCHDOG 0
-#define IRQ_AHBBUSERR 1
-#define IRQ_BBUSAGG 2
+/* NetSilicon 9360 */
+#define IRQ_NS9XXX_WATCHDOG 0
+#define IRQ_NS9XXX_AHBBUSERR 1
+#define IRQ_NS9360_BBUSAGG 2
/* irq 3 is reserved for NS9360 */
-#define IRQ_ETHRX 4
-#define IRQ_ETHTX 5
-#define IRQ_ETHPHY 6
-#define IRQ_LCD 7
-#define IRQ_SERBRX 8
-#define IRQ_SERBTX 9
-#define IRQ_SERARX 10
-#define IRQ_SERATX 11
-#define IRQ_SERCRX 12
-#define IRQ_SERCTX 13
-#define IRQ_I2C 14
-#define IRQ_BBUSDMA 15
-#define IRQ_TIMER0 16
-#define IRQ_TIMER1 17
-#define IRQ_TIMER2 18
-#define IRQ_TIMER3 19
-#define IRQ_TIMER4 20
-#define IRQ_TIMER5 21
-#define IRQ_TIMER6 22
-#define IRQ_TIMER7 23
-#define IRQ_RTC 24
-#define IRQ_USBHOST 25
-#define IRQ_USBDEVICE 26
-#define IRQ_IEEE1284 27
-#define IRQ_EXT0 28
-#define IRQ_EXT1 29
-#define IRQ_EXT2 30
-#define IRQ_EXT3 31
+#define IRQ_NS9XXX_ETHRX 4
+#define IRQ_NS9XXX_ETHTX 5
+#define IRQ_NS9XXX_ETHPHY 6
+#define IRQ_NS9360_LCD 7
+#define IRQ_NS9360_SERBRX 8
+#define IRQ_NS9360_SERBTX 9
+#define IRQ_NS9360_SERARX 10
+#define IRQ_NS9360_SERATX 11
+#define IRQ_NS9360_SERCRX 12
+#define IRQ_NS9360_SERCTX 13
+#define IRQ_NS9360_I2C 14
+#define IRQ_NS9360_BBUSDMA 15
+#define IRQ_NS9360_TIMER0 16
+#define IRQ_NS9360_TIMER1 17
+#define IRQ_NS9360_TIMER2 18
+#define IRQ_NS9360_TIMER3 19
+#define IRQ_NS9360_TIMER4 20
+#define IRQ_NS9360_TIMER5 21
+#define IRQ_NS9360_TIMER6 22
+#define IRQ_NS9360_TIMER7 23
+#define IRQ_NS9360_RTC 24
+#define IRQ_NS9360_USBHOST 25
+#define IRQ_NS9360_USBDEVICE 26
+#define IRQ_NS9360_IEEE1284 27
+#define IRQ_NS9XXX_EXT0 28
+#define IRQ_NS9XXX_EXT1 29
+#define IRQ_NS9XXX_EXT2 30
+#define IRQ_NS9XXX_EXT3 31
#define BBUS_IRQ(irq) (32 + irq)
/*
* these Interrupts are specific for the a9m9750dev board.
* They are generated by an FPGA that interrupts the CPU on
- * IRQ_EXT2
+ * IRQ_NS9360_EXT2
*/
#define FPGA_IRQ(irq) (64 + irq)
--- /dev/null
+/*
+ * include/asm-arm/arch-ns9xxx/module.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MODULE_H
+#define __ASM_ARCH_MODULE_H
+
+#include <asm/mach-types.h>
+
+#define module_is_cc7ucamry() (0 \
+ || machine_is_cc7ucamry() \
+ )
+
+#define module_is_cc9c() (0 \
+ || machine_is_cc9c() \
+ )
+
+#define module_is_cc9p9210() (0 \
+ || machine_is_cc9p9210() \
+ || machine_is_cc9p9210js() \
+ )
+
+#define module_is_cc9p9215() (0 \
+ || machine_is_cc9p9215() \
+ || machine_is_cc9p9215js() \
+ )
+
+#define module_is_cc9p9360() (0 \
+ || machine_is_a9m9360() \
+ || machine_is_cc9p9360dev() \
+ || machine_is_cc9p9360js() \
+ || machine_is_cc9p9360val() \
+ )
+
+#define module_is_cc9p9750() (0 \
+ || machine_is_a9m9750() \
+ || machine_is_cc9p9750dev() \
+ || machine_is_cc9p9750js() \
+ || machine_is_cc9p9750val() \
+ )
+
+#define module_is_ccw9c() (0 \
+ || machine_is_ccw9c() \
+ )
+
+#define module_is_inc20otter() (0 \
+ || machine_is_inc20otter() \
+ )
+
+#define module_is_otter() (0 \
+ || machine_is_otter() \
+ )
+
+#endif /* ifndef __ASM_ARCH_MODULE_H */
--- /dev/null
+/*
+ * include/asm-arm/arch-ns9xxx/processor-ns9360.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_PROCESSORNS9360_H
+#define __ASM_ARCH_PROCESSORNS9360_H
+
+#include <linux/init.h>
+
+void ns9360_reset(char mode);
+
+unsigned long ns9360_systemclock(void) __attribute__((const));
+
+static inline unsigned long ns9360_cpuclock(void) __attribute__((const));
+static inline unsigned long ns9360_cpuclock(void)
+{
+ return ns9360_systemclock() / 2;
+}
+
+void __init ns9360_map_io(void);
+
+extern struct sys_timer ns9360_timer;
+
+int ns9360_gpio_configure(unsigned gpio, int inv, int func);
+
+#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */
/*
* include/asm-arm/arch-ns9xxx/processor.h
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
#ifndef __ASM_ARCH_PROCESSOR_H
#define __ASM_ARCH_PROCESSOR_H
-#include <asm/mach-types.h>
+#include <asm/arch-ns9xxx/module.h>
-#define processor_is_ns9360() (machine_is_cc9p9360dev() \
- || machine_is_cc9p9360js())
+#define processor_is_ns9210() (0 \
+ || module_is_cc7ucamry() \
+ || module_is_cc9p9210() \
+ || module_is_inc20otter() \
+ || module_is_otter() \
+ )
+
+#define processor_is_ns9215() (0 \
+ || module_is_cc9p9215() \
+ )
+
+#define processor_is_ns9360() (0 \
+ || module_is_cc9p9360() \
+ || module_is_cc9c() \
+ || module_is_ccw9c() \
+ )
+
+#define processor_is_ns9750() (0 \
+ || module_is_cc9p9750() \
+ )
+
+#define processor_is_ns921x() (0 \
+ || processor_is_ns9210() \
+ || processor_is_ns9215() \
+ )
#endif /* ifndef __ASM_ARCH_PROCESSOR_H */
--- /dev/null
+/*
+ * include/asm-arm/arch-ns9xxx/regs-sys-common.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_REGSSYSCOMMON_H
+#define __ASM_ARCH_REGSSYSCOMMON_H
+#include <asm/hardware.h>
+
+/* Interrupt Vector Address Register Level x */
+#define SYS_IVA(x) __REG2(0xa09000c4, (x))
+
+/* Interrupt Configuration registers */
+#define SYS_IC(x) __REG2(0xa0900144, (x))
+
+/* ISRADDR */
+#define SYS_ISRADDR __REG(0xa0900164)
+
+/* Interrupt Status Active */
+#define SYS_ISA __REG(0xa0900168)
+
+/* Interrupt Status Raw */
+#define SYS_ISR __REG(0xa090016c)
+
+#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */
/*
- * include/asm-arm/arch-ns9xxx/regs-sys.h
+ * include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
-#ifndef __ASM_ARCH_REGSSYS_H
-#define __ASM_ARCH_REGSSYS_H
+#ifndef __ASM_ARCH_REGSSYSNS9360_H
+#define __ASM_ARCH_REGSSYSNS9360_H
#include <asm/hardware.h>
/* Timer x Read register */
#define SYS_TR(x) __REG2(0xa0900084, (x))
-/* Interrupt Vector Address Register Level x */
-#define SYS_IVA(x) __REG2(0xa09000c4, (x))
-
-/* Interrupt Configuration registers */
-#define SYS_IC(x) __REG2(0xa0900144, (x))
-
-/* ISRADDR */
-#define SYS_ISRADDR __REG(0xa0900164)
-
-/* Interrupt Status Active */
-#define SYS_ISA __REG(0xa0900168)
-
-/* Interrupt Status Raw */
-#define SYS_ISR __REG(0xa090016c)
-
/* Timer Interrupt Status register */
#define SYS_TIS __REG(0xa0900170)
#define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0)
#define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1)
-#endif /* ifndef __ASM_ARCH_REGSSYS_H */
+#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */
/*
* include/asm-arm/arch-ns9xxx/system.h
*
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
#define __ASM_ARCH_SYSTEM_H
#include <asm/proc-fns.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
-#include <asm/mach-types.h>
+#include <asm/arch-ns9xxx/processor.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
static inline void arch_idle(void)
{
static inline void arch_reset(char mode)
{
- u32 reg;
-
- reg = __raw_readl(SYS_PLL) >> 16;
- REGSET(reg, SYS_PLL, SWC, YES);
- __raw_writel(reg, SYS_PLL);
+#ifdef CONFIG_PROCESSOR_NS9360
+ if (processor_is_ns9360())
+ ns9360_reset(mode);
+ else
+#endif
+ BUG();
BUG();
}
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
-static void putc(char c)
+#include <asm/io.h>
+
+#define __REG(x) ((void __iomem __force *)(x))
+
+static void putc_dummy(char c, void __iomem *base)
{
- volatile u8 *base = (volatile u8 *)0x40000000;
- int t = 0x10000;
+ /* nothing */
+}
+static void putc_ns9360(char c, void __iomem *base)
+{
+ static int t = 0x10000;
+ do {
+ if (t)
+ --t;
+
+ if (__raw_readl(base + 8) & (1 << 3)) {
+ __raw_writeb(c, base + 16);
+ t = 0x10000;
+ break;
+ }
+ } while (t);
+}
+
+static void putc_a9m9750dev(char c, void __iomem *base)
+{
+ static int t = 0x10000;
+ do {
+ if (t)
+ --t;
+
+ if (__raw_readb(base + 5) & (1 << 5)) {
+ __raw_writeb(c, base);
+ t = 0x10000;
+ break;
+ }
+ } while (t);
+
+}
+
+static void putc_ns921x(char c, void __iomem *base)
+{
+ static int t = 0x10000;
do {
- if (base[5] & 0x20) {
- base[0] = c;
+ if (t)
+ --t;
+
+ if (!(__raw_readl(base) & (1 << 11))) {
+ __raw_writeb(c, base + 0x0028);
+ t = 0x10000;
break;
}
- } while (--t);
+ } while (t);
}
-#define arch_decomp_setup()
+#define MSCS __REG(0xA0900184)
+
+#define NS9360_UARTA __REG(0x90200040)
+#define NS9360_UARTB __REG(0x90200000)
+#define NS9360_UARTC __REG(0x90300000)
+#define NS9360_UARTD __REG(0x90300040)
+
+#define NS9360_UART_ENABLED(base) \
+ (__raw_readl(NS9360_UARTA) & (1 << 31))
+
+#define A9M9750DEV_UARTA __REG(0x40000000)
+
+#define NS921XSYS_CLOCK __REG(0xa090017c)
+#define NS921X_UARTA __REG(0x90010000)
+#define NS921X_UARTB __REG(0x90018000)
+#define NS921X_UARTC __REG(0x90020000)
+#define NS921X_UARTD __REG(0x90028000)
+
+#define NS921X_UART_ENABLED(base) \
+ (__raw_readl((base) + 0x1000) & (1 << 29))
+
+static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
+{
+ if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
+ /* ns9360 or ns9750 */
+ if (NS9360_UART_ENABLED(NS9360_UARTA)) {
+ *putc = putc_ns9360;
+ *base = NS9360_UARTA;
+ return;
+ } else if (NS9360_UART_ENABLED(NS9360_UARTB)) {
+ *putc = putc_ns9360;
+ *base = NS9360_UARTB;
+ return;
+ } else if (NS9360_UART_ENABLED(NS9360_UARTC)) {
+ *putc = putc_ns9360;
+ *base = NS9360_UARTC;
+ return;
+ } else if (NS9360_UART_ENABLED(NS9360_UARTD)) {
+ *putc = putc_ns9360;
+ *base = NS9360_UARTD;
+ return;
+ } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) {
+ *putc = putc_a9m9750dev;
+ *base = A9M9750DEV_UARTA;
+ return;
+ }
+ } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) {
+ /* ns921x */
+ u32 clock = __raw_readl(NS921XSYS_CLOCK);
+
+ if ((clock & (1 << 1)) &&
+ NS921X_UART_ENABLED(NS921X_UARTA)) {
+ *putc = putc_ns921x;
+ *base = NS921X_UARTA;
+ return;
+ } else if ((clock & (1 << 2)) &&
+ NS921X_UART_ENABLED(NS921X_UARTB)) {
+ *putc = putc_ns921x;
+ *base = NS921X_UARTB;
+ return;
+ } else if ((clock & (1 << 3)) &&
+ NS921X_UART_ENABLED(NS921X_UARTC)) {
+ *putc = putc_ns921x;
+ *base = NS921X_UARTC;
+ return;
+ } else if ((clock & (1 << 4)) &&
+ NS921X_UART_ENABLED(NS921X_UARTD)) {
+ *putc = putc_ns921x;
+ *base = NS921X_UARTD;
+ return;
+ }
+ }
+
+ *putc = putc_dummy;
+}
+
+void (*myputc)(char, void __iomem *);
+void __iomem *base;
+
+static void putc(char c)
+{
+ myputc(c, base);
+}
+
+static void arch_decomp_setup(void)
+{
+ autodetect(&myputc, &base);
+}
#define arch_decomp_wdog()
static void flush(void)
/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
#define OMAP_OSK_ETHR_START 0x04800300
+/* TPS65010 has four GPIOs. nPG and LED2 can be treated like GPIOs with
+ * alternate pin configurations for hardware-controlled blinking.
+ */
+#define OSK_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
+# define OSK_TPS_GPIO_USB_PWR_EN (OSK_TPS_GPIO_BASE + 0)
+# define OSK_TPS_GPIO_LED_D3 (OSK_TPS_GPIO_BASE + 1)
+# define OSK_TPS_GPIO_LAN_RESET (OSK_TPS_GPIO_BASE + 2)
+# define OSK_TPS_GPIO_DSP_PWR_EN (OSK_TPS_GPIO_BASE + 3)
+# define OSK_TPS_GPIO_LED_D9 (OSK_TPS_GPIO_BASE + 4)
+# define OSK_TPS_GPIO_LED_D2 (OSK_TPS_GPIO_BASE + 5)
+
#endif /* __ASM_ARCH_OMAP_OSK_H */
#define __ARCH_ARM_OMAP_CLOCK_H
struct module;
+struct clk;
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+
+struct clksel_rate {
+ u8 div;
+ u32 val;
+ u8 flags;
+};
+
+struct clksel {
+ struct clk *parent;
+ const struct clksel_rate *rates;
+};
+
+struct dpll_data {
+ void __iomem *mult_div1_reg;
+ u32 mult_mask;
+ u32 div1_mask;
+# if defined(CONFIG_ARCH_OMAP3)
+ void __iomem *control_reg;
+ u32 enable_mask;
+ u8 auto_recal_bit;
+ u8 recal_en_bit;
+ u8 recal_st_bit;
+# endif
+};
+
+#endif
struct clk {
struct list_head node;
__u32 flags;
void __iomem *enable_reg;
__u8 enable_bit;
- __u8 rate_offset;
- __u8 src_offset;
__s8 usecount;
void (*recalc)(struct clk *);
int (*set_rate)(struct clk *, unsigned long);
void (*init)(struct clk *);
int (*enable)(struct clk *);
void (*disable)(struct clk *);
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+ u8 fixed_div;
+ void __iomem *clksel_reg;
+ u32 clksel_mask;
+ const struct clksel *clksel;
+ const struct dpll_data *dpll_data;
+#else
+ __u8 rate_offset;
+ __u8 src_offset;
+#endif
};
struct clk_functions {
extern int clk_register(struct clk *clk);
extern void clk_unregister(struct clk *clk);
extern void propagate_rate(struct clk *clk);
+extern void recalculate_root_clocks(void);
extern void followparent_recalc(struct clk * clk);
extern void clk_allow_idle(struct clk *clk);
extern void clk_deny_idle(struct clk *clk);
extern int clk_get_usecount(struct clk *clk);
+extern void clk_enable_init_clocks(void);
/* Clock flags */
#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
#define CLOCK_NO_IDLE_PARENT (1 << 8)
#define DELAYED_APP (1 << 9) /* Delay application of clock */
#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
-#define CM_MPU_SEL1 (1 << 11) /* Domain divider/source */
-#define CM_DSP_SEL1 (1 << 12)
-#define CM_GFX_SEL1 (1 << 13)
-#define CM_MODEM_SEL1 (1 << 14)
-#define CM_CORE_SEL1 (1 << 15) /* Sets divider for many */
-#define CM_CORE_SEL2 (1 << 16) /* sets parent for GPT */
-#define CM_WKUP_SEL1 (1 << 17)
-#define CM_PLL_SEL1 (1 << 18)
-#define CM_PLL_SEL2 (1 << 19)
-#define CM_SYSCLKOUT_SEL1 (1 << 20)
+#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
+#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
+/* bits 13-20 are currently free */
#define CLOCK_IN_OMAP310 (1 << 21)
#define CLOCK_IN_OMAP730 (1 << 22)
#define CLOCK_IN_OMAP1510 (1 << 23)
#define CLOCK_IN_OMAP16XX (1 << 24)
#define CLOCK_IN_OMAP242X (1 << 25)
#define CLOCK_IN_OMAP243X (1 << 26)
+#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
+#define PARENT_CONTROLS_CLOCK (1 << 28)
+#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
+#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
+
+/* Clksel_rate flags */
+#define DEFAULT_RATE (1 << 0)
+#define RATE_IN_242X (1 << 1)
+#define RATE_IN_243X (1 << 2)
+#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
+#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
+
+#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
+
+
+/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
+#define CORE_CLK_SRC_32K 0
+#define CORE_CLK_SRC_DPLL 1
+#define CORE_CLK_SRC_DPLL_X2 2
#endif
--- /dev/null
+#ifndef __ASM_ARCH_CONTROL_H
+#define __ASM_ARCH_CONTROL_H
+
+/*
+ * include/asm-arm/arch-omap/control.h
+ *
+ * OMAP2/3 System Control Module definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ */
+
+#include <asm/arch/io.h>
+
+#define OMAP242X_CTRL_REGADDR(reg) \
+ (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg) \
+ (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg) \
+ (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+
+/*
+ * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
+ * OMAP24XX and OMAP34XX.
+ */
+
+/* Control submodule offsets */
+
+#define OMAP2_CONTROL_INTERFACE 0x000
+#define OMAP2_CONTROL_PADCONFS 0x030
+#define OMAP2_CONTROL_GENERAL 0x270
+#define OMAP343X_CONTROL_MEM_WKUP 0x600
+#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
+#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
+
+/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
+
+#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
+
+/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
+#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
+#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
+#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
+#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
+#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
+#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
+#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
+#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
+#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
+#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
+#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
+#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
+
+/* 242x-only CONTROL_GENERAL register offsets */
+#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
+#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
+
+/* 243x-only CONTROL_GENERAL register offsets */
+/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
+#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
+#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
+#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
+
+/* 24xx-only CONTROL_GENERAL register offsets */
+#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
+#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
+#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
+#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
+#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
+#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
+#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074
+#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
+#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
+#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
+#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
+#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
+#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
+
+/* 34xx-only CONTROL_GENERAL register offsets */
+#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
+#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
+#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
+#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
+#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
+#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
+#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
+#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
+#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
+#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
+
+/*
+ * REVISIT: This list of registers is not comprehensive - there are more
+ * that should be added.
+ */
+
+/*
+ * Control module register bit defines - these should eventually go into
+ * their own regbits file. Some of these will be complicated, depending
+ * on the device type (general-purpose, emulator, test, secure, bad, other)
+ * and the security mode (secure, non-secure, don't care)
+ */
+/* CONTROL_DEVCONF0 bits */
+#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
+#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
+#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
+
+/* CONTROL_DEVCONF1 bits */
+#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
+#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
+#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
+
+/* CONTROL_STATUS bits */
+#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
+#define OMAP2_SYSBOOT_5_MASK (1 << 5)
+#define OMAP2_SYSBOOT_4_MASK (1 << 4)
+#define OMAP2_SYSBOOT_3_MASK (1 << 3)
+#define OMAP2_SYSBOOT_2_MASK (1 << 2)
+#define OMAP2_SYSBOOT_1_MASK (1 << 1)
+#define OMAP2_SYSBOOT_0_MASK (1 << 0)
+
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+extern void omap_ctrl_base_set(u32 base);
+extern u32 omap_ctrl_base_get(void);
+extern u8 omap_ctrl_readb(u16 offset);
+extern u16 omap_ctrl_readw(u16 offset);
+extern u32 omap_ctrl_readl(u16 offset);
+extern void omap_ctrl_writeb(u8 val, u16 offset);
+extern void omap_ctrl_writew(u16 val, u16 offset);
+extern void omap_ctrl_writel(u32 val, u16 offset);
+#else
+#define omap_ctrl_base_set(x) WARN_ON(1)
+#define omap_ctrl_base_get() 0
+#define omap_ctrl_readb(x) 0
+#define omap_ctrl_readw(x) 0
+#define omap_ctrl_readl(x) 0
+#define omap_ctrl_writeb(x, y) WARN_ON(1)
+#define omap_ctrl_writew(x, y) WARN_ON(1)
+#define omap_ctrl_writel(x, y) WARN_ON(1)
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_CONTROL_H */
+
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \base, =VA_IC_BASE
+ ldr \base, =OMAP2_VA_IC_BASE
ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
cmp \irqnr, #0x0
bne 2222f
/*-------------------------------------------------------------------------*/
-/* wrappers for "new style" GPIO calls. the old OMAP-specfic ones should
- * eventually be removed (along with this errno.h inclusion), and maybe
- * gpios should put MPUIOs last too.
+/* Wrappers for "new style" GPIO calls, using the new infrastructure
+ * which lets us plug in FPGA, I2C, and other implementations.
+ * *
+ * The original OMAP-specfic calls should eventually be removed.
*/
-#include <asm/errno.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- return omap_request_gpio(gpio);
-}
-
-static inline void gpio_free(unsigned gpio)
-{
- omap_free_gpio(gpio);
-}
-
-static inline int __gpio_set_direction(unsigned gpio, int is_input)
-{
- if (cpu_class_is_omap2()) {
- if (gpio > OMAP_MAX_GPIO_LINES)
- return -EINVAL;
- } else {
- if (gpio > (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */))
- return -EINVAL;
- }
- omap_set_gpio_direction(gpio, is_input);
- return 0;
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
- return __gpio_set_direction(gpio, 1);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
- omap_set_gpio_dataout(gpio, value);
- return __gpio_set_direction(gpio, 0);
-}
+#include <linux/errno.h>
+#include <asm-generic/gpio.h>
static inline int gpio_get_value(unsigned gpio)
{
- return omap_get_gpio_datain(gpio);
+ return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
- omap_set_gpio_dataout(gpio, value);
+ __gpio_set_value(gpio, value);
}
-#include <asm-generic/gpio.h> /* cansleep wrappers */
+static inline int gpio_cansleep(unsigned gpio)
+{
+ return __gpio_cansleep(gpio);
+}
static inline int gpio_to_irq(unsigned gpio)
{
- return OMAP_GPIO_IRQ(gpio);
+ if (gpio < (OMAP_MAX_GPIO_LINES + 16))
+ return OMAP_GPIO_IRQ(gpio);
+ return -EINVAL;
}
static inline int irq_to_gpio(unsigned irq)
#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
#define OMAP243X_GPMC_VIRT 0xFE000000
#define OMAP243X_GPMC_SIZE SZ_1M
+#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
+#define OMAP243X_SDRC_VIRT 0xFD000000
+#define OMAP243X_SDRC_SIZE SZ_1M
+#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
+#define OMAP243X_SMS_VIRT 0xFC000000
+#define OMAP243X_SMS_SIZE SZ_1M
+
#endif
#define IO_OFFSET 0x90000000
#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
/* DSP */
-#define DSP_MEM_24XX_PHYS OMAP24XX_DSP_MEM_BASE /* 0x58000000 */
+#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
#define DSP_MEM_24XX_VIRT 0xe0000000
#define DSP_MEM_24XX_SIZE 0x28000
-#define DSP_IPI_24XX_PHYS OMAP24XX_DSP_IPI_BASE /* 0x59000000 */
+#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
#define DSP_IPI_24XX_VIRT 0xe1000000
#define DSP_IPI_24XX_SIZE SZ_4K
-#define DSP_MMU_24XX_PHYS OMAP24XX_DSP_MMU_BASE /* 0x5a000000 */
+#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
#define DSP_MMU_24XX_VIRT 0xe2000000
#define DSP_MMU_24XX_SIZE SZ_4K
+#elif defined(CONFIG_ARCH_OMAP3)
+
+/* We map both L3 and L4 on OMAP3 */
+#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */
+#define L3_34XX_VIRT 0xf8000000
+#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
+
+#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */
+#define L4_34XX_VIRT 0xd8000000
+#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
+
+/*
+ * Need to look at the Size 4M for L4.
+ * VPOM3430 was not working for Int controller
+ */
+
+#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */
+#define L4_WK_34XX_VIRT 0xd8300000
+#define L4_WK_34XX_SIZE SZ_1M
+
+#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */
+#define L4_PER_34XX_VIRT 0xd9000000
+#define L4_PER_34XX_SIZE SZ_1M
+
+#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */
+#define L4_EMU_34XX_VIRT 0xe4000000
+#define L4_EMU_34XX_SIZE SZ_64M
+
+#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */
+#define OMAP34XX_GPMC_VIRT 0xFE000000
+#define OMAP34XX_GPMC_SIZE SZ_1M
+
+#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */
+#define OMAP343X_SMS_VIRT 0xFC000000
+#define OMAP343X_SMS_SIZE SZ_1M
+
+#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */
+#define OMAP343X_SDRC_VIRT 0xFD000000
+#define OMAP343X_SDRC_SIZE SZ_1M
+
+
+#define IO_OFFSET 0x90000000
+#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
+
+/* DSP */
+#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
+#define DSP_MEM_34XX_VIRT 0xe0000000
+#define DSP_MEM_34XX_SIZE 0x28000
+#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
+#define DSP_IPI_34XX_VIRT 0xe1000000
+#define DSP_IPI_34XX_SIZE SZ_4K
+#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
+#define DSP_MMU_34XX_VIRT 0xe2000000
+#define DSP_MMU_34XX_SIZE SZ_4K
+
#endif
#ifndef __ASSEMBLER__
#define OMAP_MMC_MAX_SLOTS 2
struct omap_mmc_platform_data {
+ struct omap_mmc_conf conf;
+
unsigned enabled:1;
/* number of slots on board */
unsigned nr_slots:2;
* Table of the Omap register configurations for the FUNC_MUX and
* PULL_DWN combinations.
*
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2003 - 2008 Nokia Corporation
*
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* - W8 = ball
* - 1610 = 1510 or 1610, none if common for both 1510 and 1610
* - MMC2_DAT0 = function
- *
- * Change log:
- * Added entry for the I2C interface. (02Feb 2004)
- * Copyright (C) 2004 Texas Instruments
- *
- * Added entry for the keypad and uwire CS1. (09Mar 2004)
- * Copyright (C) 2004 Texas Instruments
- *
*/
#ifndef __ASM_ARCH_MUX_H
AA8_242X_GPIO58,
Y20_24XX_GPIO60,
W4__24XX_GPIO74,
+ N15_24XX_GPIO85,
M15_24XX_GPIO92,
+ P20_24XX_GPIO93,
+ P18_24XX_GPIO95,
+ M18_24XX_GPIO96,
+ L14_24XX_GPIO97,
J15_24XX_GPIO99,
V14_24XX_GPIO117,
P14_24XX_GPIO125,
D3_242X_DMAREQ4,
E3_242X_DMAREQ5,
- P20_24XX_TSC_IRQ,
-
/* UART3 */
K15_24XX_UART3_TX,
K14_24XX_UART3_RX,
B3__24XX_KBR5,
AA4_24XX_KBC2,
B13_24XX_KBC6,
+
+ /* 2430 USB */
+ AD9_2430_USB0_PUEN,
+ Y11_2430_USB0_VP,
+ AD7_2430_USB0_VM,
+ AE7_2430_USB0_RCV,
+ AD4_2430_USB0_TXEN,
+ AF9_2430_USB0_SE0,
+ AE6_2430_USB0_DAT,
+ AD24_2430_USB1_SE0,
+ AB24_2430_USB1_RCV,
+ Y25_2430_USB1_TXEN,
+ AA26_2430_USB1_DAT,
+
+ /* 2430 HS-USB */
+ AD9_2430_USB0HS_DATA3,
+ Y11_2430_USB0HS_DATA4,
+ AD7_2430_USB0HS_DATA5,
+ AE7_2430_USB0HS_DATA6,
+ AD4_2430_USB0HS_DATA2,
+ AF9_2430_USB0HS_DATA0,
+ AE6_2430_USB0HS_DATA1,
+ AE8_2430_USB0HS_CLK,
+ AD8_2430_USB0HS_DIR,
+ AE5_2430_USB0HS_STP,
+ AE9_2430_USB0HS_NXT,
+ AC7_2430_USB0HS_DATA7,
+
+ /* 2430 McBSP */
+ AC10_2430_MCBSP2_FSX,
+ AD16_2430_MCBSP2_CLX,
+ AE13_2430_MCBSP2_DX,
+ AD13_2430_MCBSP2_DR,
+ AC10_2430_MCBSP2_FSX_OFF,
+ AD16_2430_MCBSP2_CLX_OFF,
+ AE13_2430_MCBSP2_DX_OFF,
+ AD13_2430_MCBSP2_DR_OFF,
+
+};
+
+struct omap_mux_cfg {
+ struct pin_config *pins;
+ unsigned long size;
+ int (*cfg_reg)(const struct pin_config *cfg);
};
#ifdef CONFIG_OMAP_MUX
/* setup pin muxing in Linux */
extern int omap1_mux_init(void);
extern int omap2_mux_init(void);
-extern int omap_mux_register(struct pin_config * pins, unsigned long size);
+extern int omap_mux_register(struct omap_mux_cfg *);
extern int omap_cfg_reg(unsigned long reg_cfg);
#else
/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
+/*
+ * include/asm-arm/arch-omap/omap24xx.h
+ *
+ * This file contains the processor specific definitions
+ * of the TI OMAP24XX.
+ *
+ * Copyright (C) 2007 Texas Instruments.
+ * Copyright (C) 2007 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
#ifndef __ASM_ARCH_OMAP24XX_H
#define __ASM_ARCH_OMAP24XX_H
/* interrupt controller */
#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
-#define VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
#define OMAP24XX_IVA_INTC_BASE 0x40000000
#define IRQ_SIR_IRQ 0x0040
-#ifdef CONFIG_ARCH_OMAP2420
-#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
-#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000)
-#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000)
-#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
-#endif
+#define OMAP2420_CTRL_BASE L4_24XX_BASE
+#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
+#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
+#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
+#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
+#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
+#define OMAP2420_SMS_BASE 0x68008000
-#ifdef CONFIG_ARCH_OMAP2430
-#define OMAP24XX_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
-#define OMAP24XX_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
-#define OMAP24XX_SDRC_BASE (0x6D000000)
-#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
+#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
+#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
+#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
+#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
+
+#define OMAP243X_SMS_BASE 0x6C000000
+#define OMAP243X_SDRC_BASE 0x6D000000
#define OMAP243X_GPMC_BASE 0x6E000000
-#endif
+#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
+#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
+#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
/* DSP SS */
-#define OMAP24XX_DSP_BASE 0x58000000
-#define OMAP24XX_DSP_MEM_BASE (OMAP24XX_DSP_BASE + 0x0)
-#define OMAP24XX_DSP_IPI_BASE (OMAP24XX_DSP_BASE + 0x1000000)
-#define OMAP24XX_DSP_MMU_BASE (OMAP24XX_DSP_BASE + 0x2000000)
+#define OMAP2420_DSP_BASE 0x58000000
+#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
+#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
+#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
+
+#define OMAP243X_DSP_BASE 0x5C000000
+#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
+#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
/* Mailbox */
#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
+/* Camera */
+#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
+
+/* Security */
+#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
+#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
+#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
+#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
+#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
+#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
+
+#if defined(CONFIG_ARCH_OMAP2420)
+
+#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE
+#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE
+#define OMAP2_CM_BASE OMAP2420_CM_BASE
+#define OMAP2_PRM_BASE OMAP2420_PRM_BASE
+#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
+
+#elif defined(CONFIG_ARCH_OMAP2430)
+
+#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE
+#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE
+#define OMAP2_CM_BASE OMAP2430_CM_BASE
+#define OMAP2_PRM_BASE OMAP2430_PRM_BASE
+#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
+
+#endif
+
#endif /* __ASM_ARCH_OMAP24XX_H */
--- /dev/null
+#ifndef ____ASM_ARCH_SDRC_H
+#define ____ASM_ARCH_SDRC_H
+
+/*
+ * OMAP2/3 SDRC/SMS register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/arch/io.h>
+
+/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
+
+#define SDRC_SYSCONFIG 0x010
+#define SDRC_DLLA_CTRL 0x060
+#define SDRC_DLLA_STATUS 0x064
+#define SDRC_DLLB_CTRL 0x068
+#define SDRC_DLLB_STATUS 0x06C
+#define SDRC_POWER 0x070
+#define SDRC_MR_0 0x084
+#define SDRC_RFR_CTRL_0 0x0a4
+
+/*
+ * These values represent the number of memory clock cycles between
+ * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
+ * rows per device, and include a subtraction of a 50 cycle window in the
+ * event that the autorefresh command is delayed due to other SDRC activity.
+ * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
+ * counter reaches 0.
+ *
+ * These represent optimal values for common parts, it won't work for all.
+ * As long as you scale down, most parameters are still work, they just
+ * become sub-optimal. The RFR value goes in the opposite direction. If you
+ * don't adjust it down as your clock period increases the refresh interval
+ * will not be met. Setting all parameters for complete worst case may work,
+ * but may cut memory performance by 2x. Due to errata the DLLs need to be
+ * unlocked and their value needs run time calibration. A dynamic call is
+ * need for that as no single right value exists acorss production samples.
+ *
+ * Only the FULL speed values are given. Current code is such that rate
+ * changes must be made at DPLLoutx2. The actual value adjustment for low
+ * frequency operation will be handled by omap_set_performance()
+ *
+ * By having the boot loader boot up in the fastest L4 speed available likely
+ * will result in something which you can switch between.
+ */
+#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
+#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
+#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
+#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
+#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
+
+
+/*
+ * SMS register access
+ */
+
+
+#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+
+/* SMS register offsets - read/write with sms_{read,write}_reg() */
+
+#define SMS_SYSCONFIG 0x010
+/* REVISIT: fill in other SMS registers here */
+
+#endif
# define CONF_USB_PWRDN_DP_R (1 << 1)
/* OMAP2 */
-#define CONTROL_DEVCONF_REG __REG32(L4_24XX_BASE + 0x0274)
# define USB_UNIDIR 0x0
# define USB_UNIDIR_TLL 0x1
# define USB_BIDIR 0x2
# define USB_BIDIR_TLL 0x3
-# define USBT0WRMODEI(x) ((x) << 22)
-# define USBT1WRMODEI(x) ((x) << 20)
-# define USBT2WRMODEI(x) ((x) << 18)
+# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
# define USBT2TLL5PI (1 << 17)
# define USB0PUENACTLOI (1 << 16)
# define USBSTANDBYCTRL (1 << 15)
+++ /dev/null
-/*
- * include/asm-arm/arch-orion/io.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include "orion.h"
-
-#define IO_SPACE_LIMIT 0xffffffff
-#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE
-
-static inline void __iomem *__io(unsigned long addr)
-{
- return (void __iomem *)addr;
-}
-
-#define __io(a) __io(a)
-#define __mem_pci(a) (a)
-
-#endif
+++ /dev/null
-/*
- * include/asm-arm/arch-orion/irqs.h
- *
- * IRQ definitions for Orion SoC
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IRQS_H__
-#define __ASM_ARCH_IRQS_H__
-
-#include "orion.h" /* need GPIO_MAX */
-
-/*
- * Orion Main Interrupt Controller
- */
-#define IRQ_ORION_BRIDGE 0
-#define IRQ_ORION_DOORBELL_H2C 1
-#define IRQ_ORION_DOORBELL_C2H 2
-#define IRQ_ORION_UART0 3
-#define IRQ_ORION_UART1 4
-#define IRQ_ORION_I2C 5
-#define IRQ_ORION_GPIO_0_7 6
-#define IRQ_ORION_GPIO_8_15 7
-#define IRQ_ORION_GPIO_16_23 8
-#define IRQ_ORION_GPIO_24_31 9
-#define IRQ_ORION_PCIE0_ERR 10
-#define IRQ_ORION_PCIE0_INT 11
-#define IRQ_ORION_USB1_CTRL 12
-#define IRQ_ORION_DEV_BUS_ERR 14
-#define IRQ_ORION_PCI_ERR 15
-#define IRQ_ORION_USB_BR_ERR 16
-#define IRQ_ORION_USB0_CTRL 17
-#define IRQ_ORION_ETH_RX 18
-#define IRQ_ORION_ETH_TX 19
-#define IRQ_ORION_ETH_MISC 20
-#define IRQ_ORION_ETH_SUM 21
-#define IRQ_ORION_ETH_ERR 22
-#define IRQ_ORION_IDMA_ERR 23
-#define IRQ_ORION_IDMA_0 24
-#define IRQ_ORION_IDMA_1 25
-#define IRQ_ORION_IDMA_2 26
-#define IRQ_ORION_IDMA_3 27
-#define IRQ_ORION_CESA 28
-#define IRQ_ORION_SATA 29
-#define IRQ_ORION_XOR0 30
-#define IRQ_ORION_XOR1 31
-
-/*
- * Orion General Purpose Pins
- */
-#define IRQ_ORION_GPIO_START 32
-#define NR_GPIO_IRQS GPIO_MAX
-
-#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
-
-#endif /* __ASM_ARCH_IRQS_H__ */
+++ /dev/null
-/*
- * include/asm-arm/arch-orion/orion.h
- *
- * Generic definitions of Orion SoC flavors:
- * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_ORION_H__
-#define __ASM_ARCH_ORION_H__
-
-/*****************************************************************************
- * Orion Address Map
- *
- * virt phys size
- * fdd00000 f1000000 1M on-chip peripheral registers
- * fde00000 f2000000 1M PCIe I/O space
- * fdf00000 f2100000 1M PCI I/O space
- * fe000000 f0000000 16M PCIe WA space (Orion-NAS only)
- ****************************************************************************/
-#define ORION_REGS_PHYS_BASE 0xf1000000
-#define ORION_REGS_VIRT_BASE 0xfdd00000
-#define ORION_REGS_SIZE SZ_1M
-
-#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
-#define ORION_PCIE_IO_VIRT_BASE 0xfde00000
-#define ORION_PCIE_IO_BUS_BASE 0x00000000
-#define ORION_PCIE_IO_SIZE SZ_1M
-
-#define ORION_PCI_IO_PHYS_BASE 0xf2100000
-#define ORION_PCI_IO_VIRT_BASE 0xfdf00000
-#define ORION_PCI_IO_BUS_BASE 0x00100000
-#define ORION_PCI_IO_SIZE SZ_1M
-
-/* Relevant only for Orion-NAS */
-#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
-#define ORION_PCIE_WA_VIRT_BASE 0xfe000000
-#define ORION_PCIE_WA_SIZE SZ_16M
-
-#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000
-#define ORION_PCIE_MEM_SIZE SZ_128M
-
-#define ORION_PCI_MEM_PHYS_BASE 0xe8000000
-#define ORION_PCI_MEM_SIZE SZ_128M
-
-/*******************************************************************************
- * Supported Devices & Revisions
- ******************************************************************************/
-/* Orion-1 (88F5181) */
-#define MV88F5181_DEV_ID 0x5181
-#define MV88F5181_REV_B1 3
-/* Orion-NAS (88F5182) */
-#define MV88F5182_DEV_ID 0x5182
-#define MV88F5182_REV_A2 2
-/* Orion-2 (88F5281) */
-#define MV88F5281_DEV_ID 0x5281
-#define MV88F5281_REV_D1 5
-#define MV88F5281_REV_D2 6
-
-/*******************************************************************************
- * Orion Registers Map
- ******************************************************************************/
-#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000)
-#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x))
-
-#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000)
-#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000)
-#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x))
-#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000)
-#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000)
-#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000)
-#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100)
-#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100)
-
-#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
-#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
-
-#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
-#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
-
-#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000)
-#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x))
-
-#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000)
-#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000)
-#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x))
-
-#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000)
-#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000)
-#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x))
-
-#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000)
-#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000)
-#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x))
-
-#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000)
-#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000)
-#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x))
-
-/*******************************************************************************
- * Device Bus Registers
- ******************************************************************************/
-#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000)
-#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004)
-#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050)
-#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008)
-#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010)
-#define GPIO_OUT ORION_DEV_BUS_REG(0x100)
-#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104)
-#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108)
-#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c)
-#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110)
-#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114)
-#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118)
-#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c)
-#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c)
-#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460)
-#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464)
-#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c)
-#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
-#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
-#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
-#define GPIO_MAX 32
-
-/***************************************************************************
- * Orion CPU Bridge Registers
- **************************************************************************/
-#define CPU_CONF ORION_BRIDGE_REG(0x100)
-#define CPU_CTRL ORION_BRIDGE_REG(0x104)
-#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108)
-#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c)
-#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
-#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
-#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
-#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
-#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
-#define TIMER_CTRL ORION_BRIDGE_REG(0x300)
-#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8))
-#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8))
-
-#ifndef __ASSEMBLY__
-
-/*******************************************************************************
- * Helpers to access Orion registers
- ******************************************************************************/
-#include <asm/types.h>
-#include <asm/io.h>
-
-#define orion_read(r) __raw_readl(r)
-#define orion_write(r, val) __raw_writel(val, r)
-
-/*
- * These are not preempt safe. Locks, if needed, must be taken care by caller.
- */
-#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask))
-#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask))
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARCH_ORION_H__ */
+++ /dev/null
-/*
- * include/asm-arm/arch-orion/timex.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define ORION_TCLK 166666667
-#define CLOCK_TICK_RATE ORION_TCLK
/*
- * linux/include/asm-arm/arch-orion/debug-macro.S
+ * include/asm-arm/arch-orion5x/debug-macro.S
*
* Debugging macro include header
*
* published by the Free Software Foundation.
*/
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
- ldreq \rx, =ORION_REGS_PHYS_BASE
- ldrne \rx, =ORION_REGS_VIRT_BASE
+ ldreq \rx, =ORION5X_REGS_PHYS_BASE
+ ldrne \rx, =ORION5X_REGS_VIRT_BASE
orr \rx, \rx, #0x00012000
.endm
/*
- * include/asm-arm/arch-orion/entry-macro.S
+ * include/asm-arm/arch-orion5x/entry-macro.S
*
* Low-level IRQ helper macros for Orion platforms
*
* warranty of any kind, whether express or implied.
*/
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
.macro disable_fiq
.endm
/*
- * include/asm-arm/arch-orion/gpio.h
+ * include/asm-arm/arch-orion5x/gpio.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
extern int gpio_direction_output(unsigned pin, int value);
extern int gpio_get_value(unsigned pin);
extern void gpio_set_value(unsigned pin, int value);
-extern void orion_gpio_set_blink(unsigned pin, int blink);
+extern void orion5x_gpio_set_blink(unsigned pin, int blink);
extern void gpio_display(void); /* debug */
static inline int gpio_to_irq(int pin)
{
- return pin + IRQ_ORION_GPIO_START;
+ return pin + IRQ_ORION5X_GPIO_START;
}
static inline int irq_to_gpio(int irq)
{
- return irq - IRQ_ORION_GPIO_START;
+ return irq - IRQ_ORION5X_GPIO_START;
}
#include <asm-generic/gpio.h> /* cansleep wrappers */
/*
- * include/asm-arm/arch-orion/hardware.h
+ * include/asm-arm/arch-orion5x/hardware.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#ifndef __ASM_ARCH_HARDWARE_H__
-#define __ASM_ARCH_HARDWARE_H__
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
-#include "orion.h"
+#include "orion5x.h"
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x01000000
-#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE
+#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE
#endif
--- /dev/null
+/*
+ * include/asm-arm/arch-orion5x/io.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "orion5x.h"
+
+#define IO_SPACE_LIMIT 0xffffffff
+#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE
+
+static inline void __iomem *
+__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
+{
+ void __iomem *retval;
+
+ if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE &&
+ paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) {
+ retval = (void __iomem *)ORION5X_REGS_VIRT_BASE +
+ (paddr - ORION5X_REGS_PHYS_BASE);
+ } else {
+ retval = __arm_ioremap(paddr, size, mtype);
+ }
+
+ return retval;
+}
+
+static inline void
+__arch_iounmap(void __iomem *addr)
+{
+ if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
+ addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
+ __iounmap(addr);
+}
+
+static inline void __iomem *__io(unsigned long addr)
+{
+ return (void __iomem *)addr;
+}
+
+#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
+#define __arch_iounmap(a) __arch_iounmap(a)
+#define __io(a) __io(a)
+#define __mem_pci(a) (a)
+
+
+/*****************************************************************************
+ * Helpers to access Orion registers
+ ****************************************************************************/
+#define orion5x_read(r) __raw_readl(r)
+#define orion5x_write(r, val) __raw_writel(val, r)
+
+/*
+ * These are not preempt-safe. Locks, if needed, must be taken
+ * care of by the caller.
+ */
+#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask))
+#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask))
+
+
+#endif
--- /dev/null
+/*
+ * include/asm-arm/arch-orion5x/irqs.h
+ *
+ * IRQ definitions for Orion SoC
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "orion5x.h" /* need GPIO_MAX */
+
+/*
+ * Orion Main Interrupt Controller
+ */
+#define IRQ_ORION5X_BRIDGE 0
+#define IRQ_ORION5X_DOORBELL_H2C 1
+#define IRQ_ORION5X_DOORBELL_C2H 2
+#define IRQ_ORION5X_UART0 3
+#define IRQ_ORION5X_UART1 4
+#define IRQ_ORION5X_I2C 5
+#define IRQ_ORION5X_GPIO_0_7 6
+#define IRQ_ORION5X_GPIO_8_15 7
+#define IRQ_ORION5X_GPIO_16_23 8
+#define IRQ_ORION5X_GPIO_24_31 9
+#define IRQ_ORION5X_PCIE0_ERR 10
+#define IRQ_ORION5X_PCIE0_INT 11
+#define IRQ_ORION5X_USB1_CTRL 12
+#define IRQ_ORION5X_DEV_BUS_ERR 14
+#define IRQ_ORION5X_PCI_ERR 15
+#define IRQ_ORION5X_USB_BR_ERR 16
+#define IRQ_ORION5X_USB0_CTRL 17
+#define IRQ_ORION5X_ETH_RX 18
+#define IRQ_ORION5X_ETH_TX 19
+#define IRQ_ORION5X_ETH_MISC 20
+#define IRQ_ORION5X_ETH_SUM 21
+#define IRQ_ORION5X_ETH_ERR 22
+#define IRQ_ORION5X_IDMA_ERR 23
+#define IRQ_ORION5X_IDMA_0 24
+#define IRQ_ORION5X_IDMA_1 25
+#define IRQ_ORION5X_IDMA_2 26
+#define IRQ_ORION5X_IDMA_3 27
+#define IRQ_ORION5X_CESA 28
+#define IRQ_ORION5X_SATA 29
+#define IRQ_ORION5X_XOR0 30
+#define IRQ_ORION5X_XOR1 31
+
+/*
+ * Orion General Purpose Pins
+ */
+#define IRQ_ORION5X_GPIO_START 32
+#define NR_GPIO_IRQS GPIO_MAX
+
+#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
/*
- * include/asm-arm/arch-orion/memory.h
+ * include/asm-arm/arch-orion5x/memory.h
*
* Marvell Orion memory definitions
*/
-#ifndef __ASM_ARCH_MMU_H
-#define __ASM_ARCH_MMU_H
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET UL(0x00000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
+
#endif
--- /dev/null
+/*
+ * include/asm-arm/arch-orion5x/orion5x.h
+ *
+ * Generic definitions of Orion SoC flavors:
+ * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_ORION5X_H
+#define __ASM_ARCH_ORION5X_H
+
+/*****************************************************************************
+ * Orion Address Maps
+ *
+ * phys
+ * e0000000 PCIe MEM space
+ * e8000000 PCI MEM space
+ * f0000000 PCIe WA space (Orion-1/Orion-NAS only)
+ * f1000000 on-chip peripheral registers
+ * f2000000 PCIe I/O space
+ * f2100000 PCI I/O space
+ * f4000000 device bus mappings (boot)
+ * fa000000 device bus mappings (cs0)
+ * fa800000 device bus mappings (cs2)
+ * fc000000 device bus mappings (cs0/cs1)
+ *
+ * virt phys size
+ * fdd00000 f1000000 1M on-chip peripheral registers
+ * fde00000 f2000000 1M PCIe I/O space
+ * fdf00000 f2100000 1M PCI I/O space
+ * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
+ ****************************************************************************/
+#define ORION5X_REGS_PHYS_BASE 0xf1000000
+#define ORION5X_REGS_VIRT_BASE 0xfdd00000
+#define ORION5X_REGS_SIZE SZ_1M
+
+#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
+#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000
+#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
+#define ORION5X_PCIE_IO_SIZE SZ_1M
+
+#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
+#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000
+#define ORION5X_PCI_IO_BUS_BASE 0x00100000
+#define ORION5X_PCI_IO_SIZE SZ_1M
+
+/* Relevant only for Orion-1/Orion-NAS */
+#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
+#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000
+#define ORION5X_PCIE_WA_SIZE SZ_16M
+
+#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
+#define ORION5X_PCIE_MEM_SIZE SZ_128M
+
+#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000
+#define ORION5X_PCI_MEM_SIZE SZ_128M
+
+/*******************************************************************************
+ * Supported Devices & Revisions
+ ******************************************************************************/
+/* Orion-1 (88F5181) */
+#define MV88F5181_DEV_ID 0x5181
+#define MV88F5181_REV_B1 3
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID 0x5182
+#define MV88F5182_REV_A2 2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID 0x5281
+#define MV88F5281_REV_D1 5
+#define MV88F5281_REV_D2 6
+
+/*******************************************************************************
+ * Orion Registers Map
+ ******************************************************************************/
+#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
+#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
+
+#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
+#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
+#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
+#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
+#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
+#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+
+#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
+#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
+#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
+
+#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
+
+#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x))
+
+#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
+#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x))
+
+#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
+#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x))
+
+#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
+#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x))
+
+#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
+#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x))
+
+/*******************************************************************************
+ * Device Bus Registers
+ ******************************************************************************/
+#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
+#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
+#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
+#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
+#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
+#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100)
+#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104)
+#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108)
+#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c)
+#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110)
+#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114)
+#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118)
+#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c)
+#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
+#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
+#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
+#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
+#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
+#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
+#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
+#define GPIO_MAX 32
+
+/***************************************************************************
+ * Orion CPU Bridge Registers
+ **************************************************************************/
+#define CPU_CONF ORION5X_BRIDGE_REG(0x100)
+#define CPU_CTRL ORION5X_BRIDGE_REG(0x104)
+#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108)
+#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c)
+#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C)
+#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110)
+#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
+#define BRIDGE_INT_TIMER0 0x0002
+#define BRIDGE_INT_TIMER1 0x0004
+#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
+#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)
+
+
+#endif
/*
- * include/asm-arm/arch-orion/system.h
+ * include/asm-arm/arch-orion5x/system.h
*
* Tzachi Perelstein <tzachi@marvell.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define __ASM_ARCH_SYSTEM_H
#include <asm/arch/hardware.h>
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
static inline void arch_idle(void)
{
/*
* Enable and issue soft reset
*/
- orion_setbits(CPU_RESET_MASK, (1 << 2));
- orion_setbits(CPU_SOFT_RESET, 1);
+ orion5x_setbits(CPU_RESET_MASK, (1 << 2));
+ orion5x_setbits(CPU_SOFT_RESET, 1);
}
+
#endif
--- /dev/null
+/*
+ * include/asm-arm/arch-orion5x/timex.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE (100 * HZ)
+
+#define ORION5X_TCLK 166666667
/*
- * include/asm-arm/arch-orion/uncompress.h
+ * include/asm-arm/arch-orion5x/uncompress.h
*
* Tzachi Perelstein <tzachi@marvell.com>
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
/*
- * include/asm-arm/arch-orion/vmalloc.h
+ * include/asm-arm/arch-orion5x/vmalloc.h
*/
#define VMALLOC_END 0xfd800000
--- /dev/null
+/*
+ camera.h - PXA camera driver header file
+
+ Copyright (C) 2003, Intel Corporation
+ Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __ASM_ARCH_CAMERA_H_
+#define __ASM_ARCH_CAMERA_H_
+
+#define PXA_CAMERA_MASTER 1
+#define PXA_CAMERA_DATAWIDTH_4 2
+#define PXA_CAMERA_DATAWIDTH_5 4
+#define PXA_CAMERA_DATAWIDTH_8 8
+#define PXA_CAMERA_DATAWIDTH_9 0x10
+#define PXA_CAMERA_DATAWIDTH_10 0x20
+#define PXA_CAMERA_PCLK_EN 0x40
+#define PXA_CAMERA_MCLK_EN 0x80
+#define PXA_CAMERA_PCP 0x100
+#define PXA_CAMERA_HSP 0x200
+#define PXA_CAMERA_VSP 0x400
+
+struct pxacamera_platform_data {
+ int (*init)(struct device *);
+ int (*power)(struct device *, int);
+ int (*reset)(struct device *, int);
+
+ unsigned long flags;
+ unsigned long mclk_10khz;
+};
+
+extern void pxa_set_camera_info(struct pxacamera_platform_data *);
+
+#endif /* __ASM_ARCH_CAMERA_H_ */
--- /dev/null
+/*
+ * linux/include/asm-arm/arch-pxa/gumstix.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* BTRESET - Reset line to Bluetooth module, active low signal. */
+#define GPIO_GUMSTIX_BTRESET 7
+#define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT)
+
+
+/*
+GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean
+interrupt signal for determining cable presence. On the original gumstix,
+this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F,
+this moves to GPIO17 and GPIO37. */
+
+/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
+has detected a cable insertion; driven low otherwise. */
+
+#ifdef CONFIG_ARCH_GUMSTIX_ORIG
+
+#define GPIO_GUMSTIX_USB_GPIOn 81
+#define GPIO_GUMSTIX_USB_GPIOx 83
+
+#else
+
+#define GPIO_GUMSTIX_USB_GPIOn 35
+#define GPIO_GUMSTIX_USB_GPIOx 41
+
+#endif
+
+/* usb state change */
+#define GUMSTIX_USB_INTR_IRQ IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn)
+
+#define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
+#define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
+#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN)
+
+/*
+ * SD/MMC definitions
+ */
+#define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */
+#define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */
+#define GUMSTIX_IRQ_GPIO_nSD_DETECT IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT)
+
+/*
+ * SMC Ethernet definitions
+ * ETH_RST provides a hardware reset line to the ethernet chip
+ * ETH is the IRQ line in from the ethernet chip to the PXA
+ */
+#define GPIO_GUMSTIX_ETH0_RST 80
+#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
+#define GPIO_GUMSTIX_ETH1_RST 52
+#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
+
+#define GPIO_GUMSTIX_ETH0 36
+#define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN)
+#define GUMSTIX_ETH0_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH0)
+#define GPIO_GUMSTIX_ETH1 27
+#define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN)
+#define GUMSTIX_ETH1_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH1)
+
+
+/* CF reset line */
+#define GPIO8_RESET 8
+
+/* CF slot 0 */
+#define GPIO4_nBVD1 4
+#define GPIO4_nSTSCHG GPIO4_nBVD1
+#define GPIO11_nCD 11
+#define GPIO26_PRDY_nBSY 26
+#define GUMSTIX_S0_nSTSCHG_IRQ IRQ_GPIO(GPIO4_nSTSCHG)
+#define GUMSTIX_S0_nCD_IRQ IRQ_GPIO(GPIO11_nCD)
+#define GUMSTIX_S0_PRDY_nBSY_IRQ IRQ_GPIO(GPIO26_PRDY_nBSY)
+
+/* CF slot 1 */
+#define GPIO18_nBVD1 18
+#define GPIO18_nSTSCHG GPIO18_nBVD1
+#define GPIO36_nCD 36
+#define GPIO27_PRDY_nBSY 27
+#define GUMSTIX_S1_nSTSCHG_IRQ IRQ_GPIO(GPIO18_nSTSCHG)
+#define GUMSTIX_S1_nCD_IRQ IRQ_GPIO(GPIO36_nCD)
+#define GUMSTIX_S1_PRDY_nBSY_IRQ IRQ_GPIO(GPIO27_PRDY_nBSY)
+
+/* CF GPIO line modes */
+#define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN)
+#define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT)
+#define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN)
+#define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN)
+#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN)
+#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN)
+#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN)
struct pxaficp_platform_data {
int transceiver_cap;
void (*transceiver_mode)(struct device *dev, int mode);
+ int (*startup)(struct device *dev);
+ void (*shutdown)(struct device *dev);
};
extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
#elif defined(CONFIG_ARCH_LUBBOCK) || \
defined(CONFIG_MACH_LOGICPD_PXA270) || \
defined(CONFIG_MACH_MAINSTONE) || \
- defined(CONFIG_MACH_PCM027)
+ defined(CONFIG_MACH_PCM027) || \
+ defined(CONFIG_MACH_MAGICIAN)
#define NR_IRQS (IRQ_BOARD_END)
#else
#define NR_IRQS (IRQ_BOARD_START)
#ifndef _MAGICIAN_H_
#define _MAGICIAN_H_
-#include <asm/arch/pxa-regs.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/pxa2xx-gpio.h>
/*
* PXA GPIOs
#define GPIO48_MAGICIAN_UNKNOWN 48
#define GPIO56_MAGICIAN_UNKNOWN 56
#define GPIO57_MAGICIAN_CAM_RESET 57
+#define GPIO75_MAGICIAN_SAMSUNG_POWER 75
#define GPIO83_MAGICIAN_nIR_EN 83
#define GPIO86_MAGICIAN_GSM_RESET 86
#define GPIO87_MAGICIAN_GSM_SELECT 87
#define GPIO48_MAGICIAN_UNKNOWN_MD (48 | GPIO_OUT)
#define GPIO56_MAGICIAN_UNKNOWN_MD (56 | GPIO_OUT)
#define GPIO57_MAGICIAN_CAM_RESET_MD (57 | GPIO_OUT)
+#define GPIO75_MAGICIAN_SAMSUNG_POWER_MD (75 | GPIO_OUT)
#define GPIO83_MAGICIAN_nIR_EN_MD (83 | GPIO_OUT)
#define GPIO86_MAGICIAN_GSM_RESET_MD (86 | GPIO_OUT)
#define GPIO87_MAGICIAN_GSM_SELECT_MD (87 | GPIO_OUT)
#define GPIO119_MAGICIAN_UNKNOWN_MD (119 | GPIO_OUT)
#define GPIO120_MAGICIAN_UNKNOWN_MD (120 | GPIO_OUT)
+/*
+ * CPLD IRQs
+ */
+
+#define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0)
+#define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1)
+#define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2)
+#define IRQ_MAGICIAN_AC (IRQ_BOARD_START + 3)
+
+/*
+ * CPLD EGPIOs
+ */
+
+#define MAGICIAN_EGPIO_BASE 0x80 /* GPIO_BOARD_START */
+#define MAGICIAN_EGPIO(reg,bit) \
+ (MAGICIAN_EGPIO_BASE + 8*reg + bit)
+
+/* output */
+
+#define EGPIO_MAGICIAN_TOPPOLY_POWER MAGICIAN_EGPIO(0, 2)
+#define EGPIO_MAGICIAN_LED_POWER MAGICIAN_EGPIO(0, 5)
+#define EGPIO_MAGICIAN_GSM_RESET MAGICIAN_EGPIO(0, 6)
+#define EGPIO_MAGICIAN_LCD_POWER MAGICIAN_EGPIO(0, 7)
+#define EGPIO_MAGICIAN_SPK_POWER MAGICIAN_EGPIO(1, 0)
+#define EGPIO_MAGICIAN_EP_POWER MAGICIAN_EGPIO(1, 1)
+#define EGPIO_MAGICIAN_IN_SEL0 MAGICIAN_EGPIO(1, 2)
+#define EGPIO_MAGICIAN_IN_SEL1 MAGICIAN_EGPIO(1, 3)
+#define EGPIO_MAGICIAN_MIC_POWER MAGICIAN_EGPIO(1, 4)
+#define EGPIO_MAGICIAN_CODEC_RESET MAGICIAN_EGPIO(1, 5)
+#define EGPIO_MAGICIAN_CODEC_POWER MAGICIAN_EGPIO(1, 6)
+#define EGPIO_MAGICIAN_BL_POWER MAGICIAN_EGPIO(1, 7)
+#define EGPIO_MAGICIAN_SD_POWER MAGICIAN_EGPIO(2, 0)
+#define EGPIO_MAGICIAN_CARKIT_MIC MAGICIAN_EGPIO(2, 1)
+#define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL MAGICIAN_EGPIO(2, 2)
+#define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3)
+#define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4)
+#define EGPIO_MAGICIAN_CHARGE_EN MAGICIAN_EGPIO(2, 5)
+#define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7)
+
+/* input */
+
+#define EGPIO_MAGICIAN_CABLE_STATE_AC MAGICIAN_EGPIO(4, 0)
+#define EGPIO_MAGICIAN_CABLE_STATE_USB MAGICIAN_EGPIO(4, 1)
+
+#define EGPIO_MAGICIAN_BOARD_ID0 MAGICIAN_EGPIO(5, 0)
+#define EGPIO_MAGICIAN_BOARD_ID1 MAGICIAN_EGPIO(5, 1)
+#define EGPIO_MAGICIAN_BOARD_ID2 MAGICIAN_EGPIO(5, 2)
+#define EGPIO_MAGICIAN_LCD_SELECT MAGICIAN_EGPIO(5, 3)
+#define EGPIO_MAGICIAN_nSD_READONLY MAGICIAN_EGPIO(5, 4)
+
+#define EGPIO_MAGICIAN_EP_INSERT MAGICIAN_EGPIO(6, 1)
+
#endif /* _MAGICIAN_H_ */
--- /dev/null
+#ifndef __ASM_ARCH_MFP_PXA25X_H
+#define __ASM_ARCH_MFP_PXA25X_H
+
+#include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa2xx.h>
+
+/* GPIO */
+#define GPIO2_GPIO MFP_CFG_IN(GPIO2, AF0)
+#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0)
+#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0)
+#define GPIO5_GPIO MFP_CFG_IN(GPIO5, AF0)
+#define GPIO6_GPIO MFP_CFG_IN(GPIO6, AF0)
+#define GPIO7_GPIO MFP_CFG_IN(GPIO7, AF0)
+#define GPIO8_GPIO MFP_CFG_IN(GPIO8, AF0)
+
+#define GPIO1_RST MFP_CFG_IN(GPIO1, AF1)
+
+/* Crystal and Clock Signals */
+#define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
+#define GPIO70_RTC_CLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
+#define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW)
+#define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
+#define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW)
+#define GPIO12_32KHz MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
+#define GPIO72_32kHz MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW)
+
+/* SDRAM and Static Memory I/O Signals */
+#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
+#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
+#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
+#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
+#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
+
+/* Miscellaneous I/O and DMA Signals */
+#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1)
+#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1)
+#define GPIO19_DREQ_1 MFP_CFG_IN(GPIO19, AF1)
+
+/* Alternate Bus Master Mode I/O Signals */
+#define GPIO13_MBGNT MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW)
+#define GPIO73_MBGNT MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW)
+#define GPIO14_MBREQ MFP_CFG_IN(GPIO14, AF1)
+#define GPIO66_MBREQ MFP_CFG_IN(GPIO66, AF1)
+
+/* PC CARD */
+#define GPIO52_nPCE_1 MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH)
+#define GPIO53_nPCE_2 MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH)
+#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
+#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
+#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
+#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
+#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
+#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1)
+#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1)
+#define GPIO54_nPSKTSEL MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
+
+/* FFUART */
+#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1)
+#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1)
+#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1)
+#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1)
+#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1)
+#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
+#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
+#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
+
+/* BTUART */
+#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1)
+#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1)
+#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+
+/* STUART */
+#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2)
+#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
+
+/* HWUART */
+#define GPIO42_HWUART_RXD MFP_CFG_IN(GPIO42, AF3)
+#define GPIO43_HWUART_TXD MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH)
+#define GPIO44_HWUART_CTS MFP_CFG_IN(GPIO44, AF3)
+#define GPIO45_HWUART_RTS MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH)
+#define GPIO48_HWUART_TXD MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH)
+#define GPIO49_HWUART_RXD MFP_CFG_IN(GPIO49, AF1)
+#define GPIO50_HWUART_CTS MFP_CFG_IN(GPIO50, AF1)
+#define GPIO51_HWUART_RTS MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH)
+
+/* FICP */
+#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1)
+#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
+
+/* PWM 0/1 */
+#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
+#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
+
+/* AC97 */
+#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1)
+#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1)
+#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
+#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
+#define GPIO32_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO32, AF1)
+
+/* I2S */
+#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2)
+#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
+#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2)
+#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
+#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
+#define GPIO32_I2S_SYSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
+
+/* SSP 1 */
+#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
+#define GPIO24_SSP1_SFRM MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW)
+#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
+#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1)
+#define GPIO27_SSP1_EXTCLK MFP_CFG_IN(GPIO27, AF1)
+
+/* SSP 2 - NSSP */
+#define GPIO81_SSP2_CLK_OUT MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
+#define GPIO81_SSP2_CLK_IN MFP_CFG_IN(GPIO81, AF1)
+#define GPIO82_SSP2_FRM_OUT MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW)
+#define GPIO82_SSP2_FRM_IN MFP_CFG_IN(GPIO82, AF1)
+#define GPIO83_SSP2_TXD MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW)
+#define GPIO83_SSP2_RXD MFP_CFG_IN(GPIO83, AF2)
+#define GPIO84_SSP2_TXD MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW)
+#define GPIO84_SSP2_RXD MFP_CFG_IN(GPIO84, AF2)
+
+/* MMC */
+#define GPIO6_MMC_CLK MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW)
+#define GPIO8_MMC_CS0 MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW)
+#define GPIO9_MMC_CS1 MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW)
+#define GPIO34_MMC_CS0 MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW)
+#define GPIO39_MMC_CS1 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
+#define GPIO53_MMC_CLK MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
+#define GPIO54_MMC_CLK MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW)
+#define GPIO69_MMC_CLK MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW)
+#define GPIO67_MMC_CS0 MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW)
+#define GPIO68_MMC_CS1 MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW)
+
+/* LCD */
+#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
+#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
+#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
+#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
+#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
+#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
+#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
+#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
+#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
+#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
+#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
+#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
+#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
+#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
+#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
+#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
+#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
+#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
+#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
+#define GPIO77_LCD_ACBIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
+
+#endif /* __ASM_ARCH_MFP_PXA25X_H */
--- /dev/null
+#ifndef __ASM_ARCH_MFP_PXA27X_H
+#define __ASM_ARCH_MFP_PXA27X_H
+
+/*
+ * NOTE: for those special-function bidirectional GPIOs, as described
+ * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input
+ * alternative is preserved, the direction is actually selected by the
+ * specific controller, and this should work in most cases.
+ */
+
+#include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa2xx.h>
+
+/* GPIO */
+#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0)
+#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0)
+#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF0)
+#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF0)
+#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF0)
+#define GPIO90_GPIO MFP_CFG_IN(GPIO90, AF0)
+#define GPIO91_GPIO MFP_CFG_IN(GPIO91, AF0)
+#define GPIO92_GPIO MFP_CFG_IN(GPIO92, AF0)
+#define GPIO93_GPIO MFP_CFG_IN(GPIO93, AF0)
+#define GPIO94_GPIO MFP_CFG_IN(GPIO94, AF0)
+#define GPIO95_GPIO MFP_CFG_IN(GPIO95, AF0)
+#define GPIO96_GPIO MFP_CFG_IN(GPIO96, AF0)
+#define GPIO97_GPIO MFP_CFG_IN(GPIO97, AF0)
+#define GPIO98_GPIO MFP_CFG_IN(GPIO98, AF0)
+#define GPIO99_GPIO MFP_CFG_IN(GPIO99, AF0)
+#define GPIO100_GPIO MFP_CFG_IN(GPIO100, AF0)
+#define GPIO101_GPIO MFP_CFG_IN(GPIO101, AF0)
+#define GPIO102_GPIO MFP_CFG_IN(GPIO102, AF0)
+#define GPIO103_GPIO MFP_CFG_IN(GPIO103, AF0)
+#define GPIO104_GPIO MFP_CFG_IN(GPIO104, AF0)
+#define GPIO105_GPIO MFP_CFG_IN(GPIO105, AF0)
+#define GPIO106_GPIO MFP_CFG_IN(GPIO106, AF0)
+#define GPIO107_GPIO MFP_CFG_IN(GPIO107, AF0)
+#define GPIO108_GPIO MFP_CFG_IN(GPIO108, AF0)
+#define GPIO109_GPIO MFP_CFG_IN(GPIO109, AF0)
+#define GPIO110_GPIO MFP_CFG_IN(GPIO110, AF0)
+#define GPIO111_GPIO MFP_CFG_IN(GPIO111, AF0)
+#define GPIO112_GPIO MFP_CFG_IN(GPIO112, AF0)
+#define GPIO113_GPIO MFP_CFG_IN(GPIO113, AF0)
+#define GPIO114_GPIO MFP_CFG_IN(GPIO114, AF0)
+#define GPIO115_GPIO MFP_CFG_IN(GPIO115, AF0)
+#define GPIO116_GPIO MFP_CFG_IN(GPIO116, AF0)
+#define GPIO117_GPIO MFP_CFG_IN(GPIO117, AF0)
+#define GPIO118_GPIO MFP_CFG_IN(GPIO118, AF0)
+#define GPIO119_GPIO MFP_CFG_IN(GPIO119, AF0)
+#define GPIO120_GPIO MFP_CFG_IN(GPIO120, AF0)
+
+/* Crystal and Clock Signals */
+#define GPIO9_HZ_CLK MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW)
+#define GPIO10_HZ_CLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
+#define GPIO11_48_MHz MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW)
+#define GPIO12_48_MHz MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW)
+#define GPIO13_CLK_EXT MFP_CFG_IN(GPIO13, AF1)
+
+/* OS Timer Signals */
+#define GPIO11_EXT_SYNC_0 MFP_CFG_IN(GPIO11, AF1)
+#define GPIO12_EXT_SYNC_1 MFP_CFG_IN(GPIO12, AF1)
+#define GPIO9_CHOUT_0 MFP_CFG_OUT(GPIO9, AF3, DRIVE_LOW)
+#define GPIO10_CHOUT_1 MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW)
+#define GPIO11_CHOUT_0 MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
+#define GPIO12_CHOUT_1 MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
+
+/* SDRAM and Static Memory I/O Signals */
+#define GPIO20_nSDCS_2 MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH)
+#define GPIO21_nSDCS_3 MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH)
+#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
+#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
+#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
+#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
+#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
+
+/* Miscellaneous I/O and DMA Signals */
+#define GPIO21_DVAL_0 MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH)
+#define GPIO116_DVAL_0 MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH)
+#define GPIO33_DVAL_1 MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH)
+#define GPIO96_DVAL_1 MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH)
+#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1)
+#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1)
+#define GPIO115_DREQ_0 MFP_CFG_IN(GPIO115, AF1)
+#define GPIO80_DREQ_1 MFP_CFG_IN(GPIO80, AF1)
+#define GPIO97_DREQ_1 MFP_CFG_IN(GPIO97, AF2)
+#define GPIO85_DREQ_2 MFP_CFG_IN(GPIO85, AF2)
+#define GPIO100_DREQ_2 MFP_CFG_IN(GPIO100, AF2)
+
+/* Alternate Bus Master Mode I/O Signals */
+#define GPIO20_MBREQ MFP_CFG_IN(GPIO20, AF2)
+#define GPIO80_MBREQ MFP_CFG_IN(GPIO80, AF2)
+#define GPIO96_MBREQ MFP_CFG_IN(GPIO96, AF2)
+#define GPIO115_MBREQ MFP_CFG_IN(GPIO115, AF3)
+#define GPIO21_MBGNT MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW)
+#define GPIO33_MBGNT MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW)
+#define GPIO97_MBGNT MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW)
+#define GPIO116_MBGNT MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW)
+
+/* PC CARD */
+#define GPIO15_nPCE_1 MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH)
+#define GPIO85_nPCE_1 MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH)
+#define GPIO86_nPCE_1 MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH)
+#define GPIO102_nPCE_1 MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH)
+#define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
+#define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH)
+#define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1)
+#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
+#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
+#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
+#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
+#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
+#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1)
+#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1)
+#define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH)
+
+/* I2C */
+#define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1)
+#define GPIO118_I2C_SDA MFP_CFG_IN(GPIO118, AF1)
+
+/* FFUART */
+#define GPIO9_FFUART_CTS MFP_CFG_IN(GPIO9, AF3)
+#define GPIO26_FFUART_CTS MFP_CFG_IN(GPIO26, AF3)
+#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1)
+#define GPIO100_FFUART_CTS MFP_CFG_IN(GPIO100, AF3)
+#define GPIO10_FFUART_DCD MFP_CFG_IN(GPIO10, AF1)
+#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1)
+#define GPIO33_FFUART_DSR MFP_CFG_IN(GPIO33, AF2)
+#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1)
+#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1)
+#define GPIO89_FFUART_RI MFP_CFG_IN(GPIO89, AF3)
+#define GPIO19_FFUART_RXD MFP_CFG_IN(GPIO19, AF3)
+#define GPIO33_FFUART_RXD MFP_CFG_IN(GPIO33, AF1)
+#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1)
+#define GPIO41_FFUART_RXD MFP_CFG_IN(GPIO41, AF1)
+#define GPIO53_FFUART_RXD MFP_CFG_IN(GPIO53, AF1)
+#define GPIO85_FFUART_RXD MFP_CFG_IN(GPIO85, AF1)
+#define GPIO96_FFUART_RXD MFP_CFG_IN(GPIO96, AF3)
+#define GPIO102_FFUART_RXD MFP_CFG_IN(GPIO102, AF3)
+#define GPIO16_FFUART_TXD MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH)
+#define GPIO37_FFUART_TXD MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH)
+#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
+#define GPIO83_FFUART_TXD MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH)
+#define GPIO99_FFUART_TXD MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH)
+#define GPIO27_FFUART_RTS MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH)
+#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
+#define GPIO83_FFUART_RTS MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH)
+#define GPIO98_FFUART_RTS MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH)
+#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
+#define GPIO82_FFUART_DTR MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH)
+
+/* BTUART */
+#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1)
+#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1)
+#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+
+/* STUART */
+#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2)
+#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
+
+/* FICP */
+#define GPIO42_FICP_RXD MFP_CFG_IN(GPIO42, AF2)
+#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1)
+#define GPIO43_FICP_TXD MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH)
+#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
+
+/* PWM 0/1/2/3 */
+#define GPIO11_PWM2_OUT MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW)
+#define GPIO12_PWM3_OUT MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW)
+#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
+#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
+#define GPIO38_PWM1_OUT MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW)
+#define GPIO46_PWM2_OUT MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW)
+#define GPIO47_PWM3_OUT MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW)
+#define GPIO79_PWM2_OUT MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW)
+#define GPIO80_PWM3_OUT MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW)
+#define GPIO115_PWM1_OUT MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW)
+
+/* AC97 */
+#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
+#define GPIO94_AC97_SYNC MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW)
+#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
+#define GPIO93_AC97_SDATA_OUT MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW)
+#define GPIO45_AC97_SYSCLK MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW)
+#define GPIO89_AC97_SYSCLK MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW)
+#define GPIO98_AC97_SYSCLK MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW)
+#define GPIO95_AC97_nRESET MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW)
+#define GPIO113_AC97_nRESET MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW)
+#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1)
+#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1)
+#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2)
+#define GPIO99_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO99, AF2)
+
+/* I2S */
+#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2)
+#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
+#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2)
+#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
+#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
+#define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW)
+
+/* SSP 1 */
+#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
+#define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3)
+#define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW)
+#define GPIO53_SSP1_SYSCLK MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW)
+#define GPIO24_SSP1_SFRM MFP_CFG_IN(GPIO24, AF2)
+#define GPIO28_SSP1_SFRM MFP_CFG_IN(GPIO28, AF3)
+#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
+#define GPIO57_SSP1_TXD MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW)
+#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1)
+#define GPIO27_SSP1_SCLKEN MFP_CFG_IN(GPIO27, AF2)
+
+/* SSP 2 */
+#define GPIO19_SSP2_SCLK MFP_CFG_IN(GPIO19, AF1)
+#define GPIO22_SSP2_SCLK MFP_CFG_IN(GPIO22, AF3)
+#define GPIO29_SSP2_SCLK MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW)
+#define GPIO36_SSP2_SCLK MFP_CFG_IN(GPIO36, AF2)
+#define GPIO50_SSP2_SCLK MFP_CFG_IN(GPIO50, AF3)
+#define GPIO22_SSP2_SYSCLK MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW)
+#define GPIO14_SSP2_SFRM MFP_CFG_IN(GPIO14, AF2)
+#define GPIO37_SSP2_SFRM MFP_CFG_IN(GPIO37, AF2)
+#define GPIO87_SSP2_SFRM MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW)
+#define GPIO88_SSP2_SFRM MFP_CFG_IN(GPIO88, AF3)
+#define GPIO13_SSP2_TXD MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW)
+#define GPIO38_SSP2_TXD MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW)
+#define GPIO87_SSP2_TXD MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW)
+#define GPIO89_SSP2_TXD MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW)
+#define GPIO11_SSP2_RXD MFP_CFG_IN(GPIO11, AF2)
+#define GPIO29_SSP2_RXD MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW)
+#define GPIO40_SSP2_RXD MFP_CFG_IN(GPIO40, AF1)
+#define GPIO86_SSP2_RXD MFP_CFG_IN(GPIO86, AF1)
+#define GPIO88_SSP2_RXD MFP_CFG_IN(GPIO88, AF2)
+#define GPIO22_SSP2_EXTCLK MFP_CFG_IN(GPIO22, AF1)
+#define GPIO27_SSP2_EXTCLK MFP_CFG_IN(GPIO27, AF1)
+#define GPIO22_SSP2_SCLKEN MFP_CFG_IN(GPIO22, AF2)
+#define GPIO23_SSP2_SCLKEN MFP_CFG_IN(GPIO23, AF2)
+
+/* SSP 3 */
+#define GPIO34_SSP3_SCLK MFP_CFG_IN(GPIO34, AF3)
+#define GPIO40_SSP3_SCLK MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW)
+#define GPIO52_SSP3_SCLK MFP_CFG_IN(GPIO52, AF2)
+#define GPIO84_SSP3_SCLK MFP_CFG_IN(GPIO84, AF1)
+#define GPIO45_SSP3_SYSCLK MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW)
+#define GPIO35_SSP3_SFRM MFP_CFG_IN(GPIO35, AF3)
+#define GPIO39_SSP3_SFRM MFP_CFG_IN(GPIO39, AF3)
+#define GPIO83_SSP3_SFRM MFP_CFG_IN(GPIO83, AF1)
+#define GPIO35_SSP3_TXD MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW)
+#define GPIO38_SSP3_TXD MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW)
+#define GPIO81_SSP3_TXD MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
+#define GPIO41_SSP3_RXD MFP_CFG_IN(GPIO41, AF3)
+#define GPIO82_SSP3_RXD MFP_CFG_IN(GPIO82, AF1)
+#define GPIO89_SSP3_RXD MFP_CFG_IN(GPIO89, AF1)
+
+/* MMC */
+#define GPIO32_MMC_CLK MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW)
+#define GPIO92_MMC_DAT_0 MFP_CFG_IN(GPIO92, AF1)
+#define GPIO109_MMC_DAT_1 MFP_CFG_IN(GPIO109, AF1)
+#define GPIO110_MMC_DAT_2 MFP_CFG_IN(GPIO110, AF1)
+#define GPIO111_MMC_DAT_3 MFP_CFG_IN(GPIO111, AF1)
+#define GPIO112_MMC_CMD MFP_CFG_IN(GPIO112, AF1)
+
+/* LCD */
+#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
+#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
+#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
+#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
+#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
+#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
+#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
+#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
+#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
+#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
+#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
+#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
+#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
+#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
+#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
+#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
+#define GPIO86_LCD_LDD_16 MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW)
+#define GPIO87_LCD_LDD_17 MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW)
+#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
+#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
+#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
+#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
+#define GPIO14_LCD_VSYNC MFP_CFG_IN(GPIO14, AF1)
+#define GPIO19_LCD_CS MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW)
+
+/* Keypad */
+#define GPIO93_KP_DKIN_0 MFP_CFG_IN(GPIO93, AF1)
+#define GPIO94_KP_DKIN_1 MFP_CFG_IN(GPIO94, AF1)
+#define GPIO95_KP_DKIN_2 MFP_CFG_IN(GPIO95, AF1)
+#define GPIO96_KP_DKIN_3 MFP_CFG_IN(GPIO96, AF1)
+#define GPIO97_KP_DKIN_4 MFP_CFG_IN(GPIO97, AF1)
+#define GPIO98_KP_DKIN_5 MFP_CFG_IN(GPIO98, AF1)
+#define GPIO99_KP_DKIN_6 MFP_CFG_IN(GPIO99, AF1)
+#define GPIO13_KP_KDIN_7 MFP_CFG_IN(GPIO13, AF2)
+#define GPIO100_KP_MKIN_0 MFP_CFG_IN(GPIO100, AF1)
+#define GPIO101_KP_MKIN_1 MFP_CFG_IN(GPIO101, AF1)
+#define GPIO102_KP_MKIN_2 MFP_CFG_IN(GPIO102, AF1)
+#define GPIO34_KP_MKIN_3 MFP_CFG_IN(GPIO34, AF2)
+#define GPIO37_KP_MKIN_3 MFP_CFG_IN(GPIO37, AF3)
+#define GPIO97_KP_MKIN_3 MFP_CFG_IN(GPIO97, AF3)
+#define GPIO98_KP_MKIN_4 MFP_CFG_IN(GPIO98, AF3)
+#define GPIO38_KP_MKIN_4 MFP_CFG_IN(GPIO38, AF2)
+#define GPIO39_KP_MKIN_4 MFP_CFG_IN(GPIO39, AF1)
+#define GPIO16_KP_MKIN_5 MFP_CFG_IN(GPIO16, AF1)
+#define GPIO90_KP_MKIN_5 MFP_CFG_IN(GPIO90, AF1)
+#define GPIO99_KP_MKIN_5 MFP_CFG_IN(GPIO99, AF3)
+#define GPIO17_KP_MKIN_6 MFP_CFG_IN(GPIO17, AF1)
+#define GPIO91_KP_MKIN_6 MFP_CFG_IN(GPIO91, AF1)
+#define GPIO95_KP_MKIN_6 MFP_CFG_IN(GPIO95, AF3)
+#define GPIO13_KP_MKIN_7 MFP_CFG_IN(GPIO13, AF3)
+#define GPIO36_KP_MKIN_7 MFP_CFG_IN(GPIO36, AF3)
+#define GPIO103_KP_MKOUT_0 MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH)
+#define GPIO104_KP_MKOUT_1 MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH)
+#define GPIO105_KP_MKOUT_2 MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH)
+#define GPIO106_KP_MKOUT_3 MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH)
+#define GPIO107_KP_MKOUT_4 MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH)
+#define GPIO108_KP_MKOUT_5 MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH)
+#define GPIO35_KP_MKOUT_6 MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH)
+#define GPIO22_KP_MKOUT_7 MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH)
+#define GPIO40_KP_MKOUT_6 MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH)
+#define GPIO41_KP_MKOUT_7 MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH)
+#define GPIO96_KP_MKOUT_6 MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH)
+
+/* USB P3 */
+#define GPIO10_USB_P3_5 MFP_CFG_IN(GPIO10, AF3)
+#define GPIO11_USB_P3_1 MFP_CFG_IN(GPIO11, AF3)
+#define GPIO30_USB_P3_2 MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
+#define GPIO31_USB_P3_6 MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
+#define GPIO56_USB_P3_4 MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
+#define GPIO86_USB_P3_5 MFP_CFG_IN(GPIO86, AF3)
+#define GPIO87_USB_P3_1 MFP_CFG_IN(GPIO87, AF3)
+#define GPIO90_USB_P3_5 MFP_CFG_IN(GPIO90, AF2)
+#define GPIO91_USB_P3_1 MFP_CFG_IN(GPIO91, AF2)
+#define GPIO113_USB_P3_3 MFP_CFG_IN(GPIO113, AF3)
+
+/* USB P2 */
+#define GPIO34_USB_P2_2 MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW)
+#define GPIO35_USB_P2_1 MFP_CFG_IN(GPIO35, AF2)
+#define GPIO36_USB_P2_4 MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW)
+#define GPIO37_USB_P2_8 MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW)
+#define GPIO38_USB_P2_3 MFP_CFG_IN(GPIO38, AF3)
+#define GPIO39_USB_P2_6 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
+#define GPIO40_USB_P2_5 MFP_CFG_IN(GPIO40, AF3)
+#define GPIO41_USB_P2_7 MFP_CFG_IN(GPIO41, AF2)
+#define GPIO53_USB_P2_3 MFP_CFG_IN(GPIO53, AF2)
+
+/* USB Host Port 1/2 */
+#define GPIO88_USBH1_PWR MFP_CFG_IN(GPIO88, AF1)
+#define GPIO89_USBH1_PEN MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW)
+#define GPIO119_USBH2_PWR MFP_CFG_IN(GPIO119, AF1)
+#define GPIO120_USBH2_PEN MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW)
+
+/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */
+#define GPIO115_CIF_DD_3 MFP_CFG_IN(GPIO115, AF2)
+#define GPIO116_CIF_DD_2 MFP_CFG_IN(GPIO116, AF1)
+#define GPIO12_CIF_DD_7 MFP_CFG_IN(GPIO12, AF2)
+#define GPIO17_CIF_DD_6 MFP_CFG_IN(GPIO17, AF2)
+#define GPIO23_CIF_MCLK MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW)
+#define GPIO24_CIF_FV MFP_CFG_IN(GPIO24, AF1)
+#define GPIO25_CIF_LV MFP_CFG_IN(GPIO25, AF1)
+#define GPIO26_CIF_PCLK MFP_CFG_IN(GPIO26, AF2)
+#define GPIO27_CIF_DD_0 MFP_CFG_IN(GPIO27, AF3)
+#define GPIO42_CIF_MCLK MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW)
+#define GPIO43_CIF_FV MFP_CFG_IN(GPIO43, AF3)
+#define GPIO44_CIF_LV MFP_CFG_IN(GPIO44, AF3)
+#define GPIO45_CIF_PCLK MFP_CFG_IN(GPIO45, AF3)
+#define GPIO47_CIF_DD_0 MFP_CFG_IN(GPIO47, AF1)
+#define GPIO48_CIF_DD_5 MFP_CFG_IN(GPIO48, AF1)
+#define GPIO50_CIF_DD_3 MFP_CFG_IN(GPIO50, AF1)
+#define GPIO51_CIF_DD_2 MFP_CFG_IN(GPIO51, AF1)
+#define GPIO52_CIF_DD_4 MFP_CFG_IN(GPIO52, AF1)
+#define GPIO53_CIF_MCLK MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW)
+#define GPIO54_CIF_PCLK MFP_CFG_IN(GPIO54, AF3)
+#define GPIO55_CIF_DD_1 MFP_CFG_IN(GPIO55, AF1)
+#define GPIO81_CIF_DD_0 MFP_CFG_IN(GPIO81, AF2)
+#define GPIO82_CIF_DD_5 MFP_CFG_IN(GPIO82, AF3)
+#define GPIO83_CIF_DD_4 MFP_CFG_IN(GPIO83, AF3)
+#define GPIO84_CIF_FV MFP_CFG_IN(GPIO84, AF3)
+#define GPIO85_CIF_LV MFP_CFG_IN(GPIO85, AF3)
+#define GPIO90_CIF_DD_4 MFP_CFG_IN(GPIO90, AF3)
+#define GPIO91_CIF_DD_5 MFP_CFG_IN(GPIO91, AF3)
+#define GPIO93_CIF_DD_6 MFP_CFG_IN(GPIO93, AF2)
+#define GPIO94_CIF_DD_5 MFP_CFG_IN(GPIO94, AF2)
+#define GPIO95_CIF_DD_4 MFP_CFG_IN(GPIO95, AF2)
+#define GPIO98_CIF_DD_0 MFP_CFG_IN(GPIO98, AF2)
+#define GPIO103_CIF_DD_3 MFP_CFG_IN(GPIO103, AF1)
+#define GPIO104_CIF_DD_2 MFP_CFG_IN(GPIO104, AF1)
+#define GPIO105_CIF_DD_1 MFP_CFG_IN(GPIO105, AF1)
+#define GPIO106_CIF_DD_9 MFP_CFG_IN(GPIO106, AF1)
+#define GPIO107_CIF_DD_8 MFP_CFG_IN(GPIO107, AF1)
+#define GPIO108_CIF_DD_7 MFP_CFG_IN(GPIO108, AF1)
+#define GPIO114_CIF_DD_1 MFP_CFG_IN(GPIO114, AF1)
+
+/* Universal Subscriber ID Interface */
+#define GPIO114_UVS0 MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW)
+#define GPIO115_nUVS1 MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW)
+#define GPIO116_nUVS2 MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW)
+#define GPIO14_UCLK MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW)
+#define GPIO91_UCLK MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW)
+#define GPIO19_nURST MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW)
+#define GPIO90_nURST MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW)
+#define GPIO116_UDET MFP_CFG_IN(GPIO116, AF3)
+#define GPIO114_UEN MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW)
+#define GPIO115_UEN MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW)
+
+/* Mobile Scalable Link (MSL) Interface */
+#define GPIO81_BB_OB_DAT_0 MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW)
+#define GPIO48_BB_OB_DAT_1 MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW)
+#define GPIO50_BB_OB_DAT_2 MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW)
+#define GPIO51_BB_OB_DAT_3 MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW)
+#define GPIO52_BB_OB_CLK MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW)
+#define GPIO53_BB_OB_STB MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
+#define GPIO54_BB_OB_WAIT MFP_CFG_IN(GPIO54, AF2)
+#define GPIO82_BB_IB_DAT_0 MFP_CFG_IN(GPIO82, AF2)
+#define GPIO55_BB_IB_DAT_1 MFP_CFG_IN(GPIO55, AF2)
+#define GPIO56_BB_IB_DAT_2 MFP_CFG_IN(GPIO56, AF2)
+#define GPIO57_BB_IB_DAT_3 MFP_CFG_IN(GPIO57, AF2)
+#define GPIO83_BB_IB_CLK MFP_CFG_IN(GPIO83, AF2)
+#define GPIO84_BB_IB_STB MFP_CFG_IN(GPIO84, AF2)
+#define GPIO85_BB_IB_WAIT MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW)
+
+/* Memory Stick Host Controller */
+#define GPIO92_MSBS MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW)
+#define GPIO109_MSSDIO MFP_CFG_IN(GPIO109, AF2)
+#define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2)
+#define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
+
+extern int keypad_set_wake(unsigned int on);
+#endif /* __ASM_ARCH_MFP_PXA27X_H */
--- /dev/null
+#ifndef __ASM_ARCH_MFP_PXA2XX_H
+#define __ASM_ARCH_MFP_PXA2XX_H
+
+#include <asm/arch/mfp.h>
+
+/*
+ * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
+ *
+ * MFP_PIN(x)
+ * MFP_AFx
+ * MFP_LPM_DRIVE_{LOW, HIGH}
+ * MFP_LPM_EDGE_x
+ *
+ * other MFP_x bit definitions will be ignored
+ *
+ * and adds the below two bits specifically for pxa2xx:
+ *
+ * bit 23 - Input/Output (PXA2xx specific)
+ * bit 24 - Wakeup Enable(PXA2xx specific)
+ */
+
+#define MFP_DIR_IN (0x0 << 23)
+#define MFP_DIR_OUT (0x1 << 23)
+#define MFP_DIR_MASK (0x1 << 23)
+#define MFP_DIR(x) (((x) >> 23) & 0x1)
+
+#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
+#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
+#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
+#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
+
+/* specifically for enabling wakeup on keypad GPIOs */
+#define WAKEUP_ON_LEVEL_HIGH (MFP_LPM_CAN_WAKEUP)
+
+#define MFP_CFG_IN(pin, af) \
+ ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
+ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN))
+
+/* NOTE: pins configured as output _must_ provide a low power state,
+ * and this state should help to minimize the power dissipation.
+ */
+#define MFP_CFG_OUT(pin, af, state) \
+ ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
+ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
+
+/* Common configurations for pxa25x and pxa27x
+ *
+ * Note: pins configured as GPIO are always initialized to input
+ * so not to cause any side effect
+ */
+#define GPIO0_GPIO MFP_CFG_IN(GPIO0, AF0)
+#define GPIO1_GPIO MFP_CFG_IN(GPIO1, AF0)
+#define GPIO9_GPIO MFP_CFG_IN(GPIO9, AF0)
+#define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0)
+#define GPIO11_GPIO MFP_CFG_IN(GPIO11, AF0)
+#define GPIO12_GPIO MFP_CFG_IN(GPIO12, AF0)
+#define GPIO13_GPIO MFP_CFG_IN(GPIO13, AF0)
+#define GPIO14_GPIO MFP_CFG_IN(GPIO14, AF0)
+#define GPIO15_GPIO MFP_CFG_IN(GPIO15, AF0)
+#define GPIO16_GPIO MFP_CFG_IN(GPIO16, AF0)
+#define GPIO17_GPIO MFP_CFG_IN(GPIO17, AF0)
+#define GPIO18_GPIO MFP_CFG_IN(GPIO18, AF0)
+#define GPIO19_GPIO MFP_CFG_IN(GPIO19, AF0)
+#define GPIO20_GPIO MFP_CFG_IN(GPIO20, AF0)
+#define GPIO21_GPIO MFP_CFG_IN(GPIO21, AF0)
+#define GPIO22_GPIO MFP_CFG_IN(GPIO22, AF0)
+#define GPIO23_GPIO MFP_CFG_IN(GPIO23, AF0)
+#define GPIO24_GPIO MFP_CFG_IN(GPIO24, AF0)
+#define GPIO25_GPIO MFP_CFG_IN(GPIO25, AF0)
+#define GPIO26_GPIO MFP_CFG_IN(GPIO26, AF0)
+#define GPIO27_GPIO MFP_CFG_IN(GPIO27, AF0)
+#define GPIO28_GPIO MFP_CFG_IN(GPIO28, AF0)
+#define GPIO29_GPIO MFP_CFG_IN(GPIO29, AF0)
+#define GPIO30_GPIO MFP_CFG_IN(GPIO30, AF0)
+#define GPIO31_GPIO MFP_CFG_IN(GPIO31, AF0)
+#define GPIO32_GPIO MFP_CFG_IN(GPIO32, AF0)
+#define GPIO33_GPIO MFP_CFG_IN(GPIO33, AF0)
+#define GPIO34_GPIO MFP_CFG_IN(GPIO34, AF0)
+#define GPIO35_GPIO MFP_CFG_IN(GPIO35, AF0)
+#define GPIO36_GPIO MFP_CFG_IN(GPIO36, AF0)
+#define GPIO37_GPIO MFP_CFG_IN(GPIO37, AF0)
+#define GPIO38_GPIO MFP_CFG_IN(GPIO38, AF0)
+#define GPIO39_GPIO MFP_CFG_IN(GPIO39, AF0)
+#define GPIO40_GPIO MFP_CFG_IN(GPIO40, AF0)
+#define GPIO41_GPIO MFP_CFG_IN(GPIO41, AF0)
+#define GPIO42_GPIO MFP_CFG_IN(GPIO42, AF0)
+#define GPIO43_GPIO MFP_CFG_IN(GPIO43, AF0)
+#define GPIO44_GPIO MFP_CFG_IN(GPIO44, AF0)
+#define GPIO45_GPIO MFP_CFG_IN(GPIO45, AF0)
+#define GPIO46_GPIO MFP_CFG_IN(GPIO46, AF0)
+#define GPIO47_GPIO MFP_CFG_IN(GPIO47, AF0)
+#define GPIO48_GPIO MFP_CFG_IN(GPIO48, AF0)
+#define GPIO49_GPIO MFP_CFG_IN(GPIO49, AF0)
+#define GPIO50_GPIO MFP_CFG_IN(GPIO50, AF0)
+#define GPIO51_GPIO MFP_CFG_IN(GPIO51, AF0)
+#define GPIO52_GPIO MFP_CFG_IN(GPIO52, AF0)
+#define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0)
+#define GPIO54_GPIO MFP_CFG_IN(GPIO54, AF0)
+#define GPIO55_GPIO MFP_CFG_IN(GPIO55, AF0)
+#define GPIO56_GPIO MFP_CFG_IN(GPIO56, AF0)
+#define GPIO57_GPIO MFP_CFG_IN(GPIO57, AF0)
+#define GPIO58_GPIO MFP_CFG_IN(GPIO58, AF0)
+#define GPIO59_GPIO MFP_CFG_IN(GPIO59, AF0)
+#define GPIO60_GPIO MFP_CFG_IN(GPIO60, AF0)
+#define GPIO61_GPIO MFP_CFG_IN(GPIO61, AF0)
+#define GPIO62_GPIO MFP_CFG_IN(GPIO62, AF0)
+#define GPIO63_GPIO MFP_CFG_IN(GPIO63, AF0)
+#define GPIO64_GPIO MFP_CFG_IN(GPIO64, AF0)
+#define GPIO65_GPIO MFP_CFG_IN(GPIO65, AF0)
+#define GPIO66_GPIO MFP_CFG_IN(GPIO66, AF0)
+#define GPIO67_GPIO MFP_CFG_IN(GPIO67, AF0)
+#define GPIO68_GPIO MFP_CFG_IN(GPIO68, AF0)
+#define GPIO69_GPIO MFP_CFG_IN(GPIO69, AF0)
+#define GPIO70_GPIO MFP_CFG_IN(GPIO70, AF0)
+#define GPIO71_GPIO MFP_CFG_IN(GPIO71, AF0)
+#define GPIO72_GPIO MFP_CFG_IN(GPIO72, AF0)
+#define GPIO73_GPIO MFP_CFG_IN(GPIO73, AF0)
+#define GPIO74_GPIO MFP_CFG_IN(GPIO74, AF0)
+#define GPIO75_GPIO MFP_CFG_IN(GPIO75, AF0)
+#define GPIO76_GPIO MFP_CFG_IN(GPIO76, AF0)
+#define GPIO77_GPIO MFP_CFG_IN(GPIO77, AF0)
+#define GPIO78_GPIO MFP_CFG_IN(GPIO78, AF0)
+#define GPIO79_GPIO MFP_CFG_IN(GPIO79, AF0)
+#define GPIO80_GPIO MFP_CFG_IN(GPIO80, AF0)
+#define GPIO81_GPIO MFP_CFG_IN(GPIO81, AF0)
+#define GPIO82_GPIO MFP_CFG_IN(GPIO82, AF0)
+#define GPIO83_GPIO MFP_CFG_IN(GPIO83, AF0)
+#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0)
+
+extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
+extern int gpio_set_wake(unsigned int gpio, unsigned int on);
+#endif /* __ASM_ARCH_MFP_PXA2XX_H */
#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
+#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
+#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
+#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
/*
* General Purpose I/O
/* Interrupt Controller */
-#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
-#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
-#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
-
#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
#endif
-
-/* GPIO alternate function assignments */
-
-#define GPIO1_RST 1 /* reset */
-#define GPIO6_MMCCLK 6 /* MMC Clock */
-#define GPIO7_48MHz 7 /* 48 MHz clock output */
-#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
-#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
-#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
-#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
-#define GPIO12_32KHz 12 /* 32 kHz out */
-#define GPIO13_MBGNT 13 /* memory controller grant */
-#define GPIO14_MBREQ 14 /* alternate bus master request */
-#define GPIO15_nCS_1 15 /* chip select 1 */
-#define GPIO16_PWM0 16 /* PWM0 output */
-#define GPIO17_PWM1 17 /* PWM1 output */
-#define GPIO18_RDY 18 /* Ext. Bus Ready */
-#define GPIO19_DREQ1 19 /* External DMA Request */
-#define GPIO20_DREQ0 20 /* External DMA Request */
-#define GPIO23_SCLK 23 /* SSP clock */
-#define GPIO24_SFRM 24 /* SSP Frame */
-#define GPIO25_STXD 25 /* SSP transmit */
-#define GPIO26_SRXD 26 /* SSP receive */
-#define GPIO27_SEXTCLK 27 /* SSP ext_clk */
-#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
-#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
-#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
-#define GPIO31_SYNC 31 /* AC97/I2S sync */
-#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
-#define GPIO32_SYSCLK 32 /* I2S System Clock */
-#define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */
-#define GPIO33_nCS_5 33 /* chip select 5 */
-#define GPIO34_FFRXD 34 /* FFUART receive */
-#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
-#define GPIO35_FFCTS 35 /* FFUART Clear to send */
-#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
-#define GPIO37_FFDSR 37 /* FFUART data set ready */
-#define GPIO38_FFRI 38 /* FFUART Ring Indicator */
-#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
-#define GPIO39_FFTXD 39 /* FFUART transmit data */
-#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
-#define GPIO41_FFRTS 41 /* FFUART request to send */
-#define GPIO42_BTRXD 42 /* BTUART receive data */
-#define GPIO42_HWRXD 42 /* HWUART receive data */
-#define GPIO43_BTTXD 43 /* BTUART transmit data */
-#define GPIO43_HWTXD 43 /* HWUART transmit data */
-#define GPIO44_BTCTS 44 /* BTUART clear to send */
-#define GPIO44_HWCTS 44 /* HWUART clear to send */
-#define GPIO45_BTRTS 45 /* BTUART request to send */
-#define GPIO45_HWRTS 45 /* HWUART request to send */
-#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
-#define GPIO46_ICPRXD 46 /* ICP receive data */
-#define GPIO46_STRXD 46 /* STD_UART receive data */
-#define GPIO47_ICPTXD 47 /* ICP transmit data */
-#define GPIO47_STTXD 47 /* STD_UART transmit data */
-#define GPIO48_nPOE 48 /* Output Enable for Card Space */
-#define GPIO49_nPWE 49 /* Write Enable for Card Space */
-#define GPIO50_nPIOR 50 /* I/O Read for Card Space */
-#define GPIO51_nPIOW 51 /* I/O Write for Card Space */
-#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
-#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
-#define GPIO53_MMCCLK 53 /* MMC Clock */
-#define GPIO54_MMCCLK 54 /* MMC Clock */
-#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
-#define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */
-#define GPIO55_nPREG 55 /* Card Address bit 26 */
-#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
-#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
-#define GPIO58_LDD_0 58 /* LCD data pin 0 */
-#define GPIO59_LDD_1 59 /* LCD data pin 1 */
-#define GPIO60_LDD_2 60 /* LCD data pin 2 */
-#define GPIO61_LDD_3 61 /* LCD data pin 3 */
-#define GPIO62_LDD_4 62 /* LCD data pin 4 */
-#define GPIO63_LDD_5 63 /* LCD data pin 5 */
-#define GPIO64_LDD_6 64 /* LCD data pin 6 */
-#define GPIO65_LDD_7 65 /* LCD data pin 7 */
-#define GPIO66_LDD_8 66 /* LCD data pin 8 */
-#define GPIO66_MBREQ 66 /* alternate bus master req */
-#define GPIO67_LDD_9 67 /* LCD data pin 9 */
-#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
-#define GPIO68_LDD_10 68 /* LCD data pin 10 */
-#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
-#define GPIO69_LDD_11 69 /* LCD data pin 11 */
-#define GPIO69_MMCCLK 69 /* MMC_CLK */
-#define GPIO70_LDD_12 70 /* LCD data pin 12 */
-#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
-#define GPIO71_LDD_13 71 /* LCD data pin 13 */
-#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
-#define GPIO72_LDD_14 72 /* LCD data pin 14 */
-#define GPIO72_32kHz 72 /* 32 kHz clock */
-#define GPIO73_LDD_15 73 /* LCD data pin 15 */
-#define GPIO73_MBGNT 73 /* Memory controller grant */
-#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
-#define GPIO75_LCD_LCLK 75 /* LCD line clock */
-#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
-#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
-#define GPIO78_nCS_2 78 /* chip select 2 */
-#define GPIO79_nCS_3 79 /* chip select 3 */
-#define GPIO80_nCS_4 80 /* chip select 4 */
-#define GPIO81_NSCLK 81 /* NSSP clock */
-#define GPIO82_NSFRM 82 /* NSSP Frame */
-#define GPIO83_NSTXD 83 /* NSSP transmit */
-#define GPIO84_NSRXD 84 /* NSSP receive */
-#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
-#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
-#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
-#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
-#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
-#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
-#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */
-#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */
-#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
-#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */
-#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
-
-/* GPIO alternate function mode & direction */
-
-#define GPIO_IN 0x000
-#define GPIO_OUT 0x080
-#define GPIO_ALT_FN_1_IN 0x100
-#define GPIO_ALT_FN_1_OUT 0x180
-#define GPIO_ALT_FN_2_IN 0x200
-#define GPIO_ALT_FN_2_OUT 0x280
-#define GPIO_ALT_FN_3_IN 0x300
-#define GPIO_ALT_FN_3_OUT 0x380
-#define GPIO_MD_MASK_NR 0x07f
-#define GPIO_MD_MASK_DIR 0x080
-#define GPIO_MD_MASK_FN 0x300
-#define GPIO_DFLT_LOW 0x400
-#define GPIO_DFLT_HIGH 0x800
-
-#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
-#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
-#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT)
-#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
-#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
-#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
-#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
-#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
-#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
-#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
-#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
-#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
-#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
-#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
-#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
-#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
-#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
-#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
-#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
-#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
-#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
-#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
-#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
-#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)
-#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
-#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
-#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
-#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
-#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
-#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
-#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
-#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT)
-#define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT)
-#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
-#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
-#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
-#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
-#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
-#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
-#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
-#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
-#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
-#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
-#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
-#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
-#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
-#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
-#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
-#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
-#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
-#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
-#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
-#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
-#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
-#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
-#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
-#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
-#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
-#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
-#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
-#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
-#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
-#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
-#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
-#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
-#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
-#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
-#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
-#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
-#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
-#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)
-#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
-#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
-#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
-#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
-#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
-#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
-#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
-#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
-#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
-#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
-#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
-#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
-#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
-#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
-#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
-#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
-#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
-#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
-#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
-#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
-#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
-#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
-#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
-#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
-#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
-#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
-#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
-#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
-#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
-#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
-#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
-#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
-#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
-#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
-#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT)
-#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
-#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT)
-#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN)
-#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT)
-#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN)
-#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)
-#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)
-#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)
-#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
-#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
-#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
-#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)
-#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
-#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
-#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)
-#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
-#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT)
-#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
-#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN)
-#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
-
/*
* Power Manager
*/
#ifdef CONFIG_PXA27x
-/*
- * Keypad
- */
-#define KPC __REG(0x41500000) /* Keypad Interface Control register */
-#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
-#define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
-#define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */
-#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
-#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
-#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
-#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
-#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
-#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
-
-#define KPC_AS (0x1 << 30) /* Automatic Scan bit */
-#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
-#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
-#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
-#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
-#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
-#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
-#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
-#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
-#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
-#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
-#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
-#define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
-#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
-#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
-#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */
-#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
-#define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */
-#define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */
-#define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */
-#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
-#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
-
-#define KPDK_DKP (0x1 << 31)
-#define KPDK_DK7 (0x1 << 7)
-#define KPDK_DK6 (0x1 << 6)
-#define KPDK_DK5 (0x1 << 5)
-#define KPDK_DK4 (0x1 << 4)
-#define KPDK_DK3 (0x1 << 3)
-#define KPDK_DK2 (0x1 << 2)
-#define KPDK_DK1 (0x1 << 1)
-#define KPDK_DK0 (0x1 << 0)
-
-#define KPREC_OF1 (0x1 << 31)
-#define kPREC_UF1 (0x1 << 30)
-#define KPREC_OF0 (0x1 << 15)
-#define KPREC_UF0 (0x1 << 14)
-
-#define KPMK_MKP (0x1 << 31)
-#define KPAS_SO (0x1 << 31)
-#define KPASMKPx_SO (0x1 << 31)
-
/* Camera Interface */
#define CICR0 __REG(0x50000000)
#define CICR1 __REG(0x50000004)
#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
#define CICR1_TBIT (1 << 31) /* Transparency bit */
-#define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */
+#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
#define CICR1_RGB_F (1 << 11) /* RGB format */
#define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val))
+extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
+
#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
--- /dev/null
+#ifndef __ASM_ARCH_PXA2XX_GPIO_H
+#define __ASM_ARCH_PXA2XX_GPIO_H
+
+/* GPIO alternate function assignments */
+
+#define GPIO1_RST 1 /* reset */
+#define GPIO6_MMCCLK 6 /* MMC Clock */
+#define GPIO7_48MHz 7 /* 48 MHz clock output */
+#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
+#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
+#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
+#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
+#define GPIO12_32KHz 12 /* 32 kHz out */
+#define GPIO12_CIF_DD_7 12 /* Camera data pin 7 */
+#define GPIO13_MBGNT 13 /* memory controller grant */
+#define GPIO14_MBREQ 14 /* alternate bus master request */
+#define GPIO15_nCS_1 15 /* chip select 1 */
+#define GPIO16_PWM0 16 /* PWM0 output */
+#define GPIO17_PWM1 17 /* PWM1 output */
+#define GPIO17_CIF_DD_6 17 /* Camera data pin 6 */
+#define GPIO18_RDY 18 /* Ext. Bus Ready */
+#define GPIO19_DREQ1 19 /* External DMA Request */
+#define GPIO20_DREQ0 20 /* External DMA Request */
+#define GPIO23_SCLK 23 /* SSP clock */
+#define GPIO23_CIF_MCLK 23 /* Camera Master Clock */
+#define GPIO24_SFRM 24 /* SSP Frame */
+#define GPIO24_CIF_FV 24 /* Camera frame start signal */
+#define GPIO25_STXD 25 /* SSP transmit */
+#define GPIO25_CIF_LV 25 /* Camera line start signal */
+#define GPIO26_SRXD 26 /* SSP receive */
+#define GPIO26_CIF_PCLK 26 /* Camera Pixel Clock */
+#define GPIO27_SEXTCLK 27 /* SSP ext_clk */
+#define GPIO27_CIF_DD_0 27 /* Camera data pin 0 */
+#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
+#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
+#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
+#define GPIO31_SYNC 31 /* AC97/I2S sync */
+#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
+#define GPIO32_SYSCLK 32 /* I2S System Clock */
+#define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */
+#define GPIO33_nCS_5 33 /* chip select 5 */
+#define GPIO34_FFRXD 34 /* FFUART receive */
+#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
+#define GPIO35_FFCTS 35 /* FFUART Clear to send */
+#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
+#define GPIO37_FFDSR 37 /* FFUART data set ready */
+#define GPIO38_FFRI 38 /* FFUART Ring Indicator */
+#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
+#define GPIO39_FFTXD 39 /* FFUART transmit data */
+#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
+#define GPIO41_FFRTS 41 /* FFUART request to send */
+#define GPIO42_BTRXD 42 /* BTUART receive data */
+#define GPIO42_HWRXD 42 /* HWUART receive data */
+#define GPIO42_CIF_MCLK 42 /* Camera Master Clock */
+#define GPIO43_BTTXD 43 /* BTUART transmit data */
+#define GPIO43_HWTXD 43 /* HWUART transmit data */
+#define GPIO43_CIF_FV 43 /* Camera frame start signal */
+#define GPIO44_BTCTS 44 /* BTUART clear to send */
+#define GPIO44_HWCTS 44 /* HWUART clear to send */
+#define GPIO44_CIF_LV 44 /* Camera line start signal */
+#define GPIO45_BTRTS 45 /* BTUART request to send */
+#define GPIO45_HWRTS 45 /* HWUART request to send */
+#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
+#define GPIO45_CIF_PCLK 45 /* Camera Pixel Clock */
+#define GPIO46_ICPRXD 46 /* ICP receive data */
+#define GPIO46_STRXD 46 /* STD_UART receive data */
+#define GPIO47_ICPTXD 47 /* ICP transmit data */
+#define GPIO47_STTXD 47 /* STD_UART transmit data */
+#define GPIO47_CIF_DD_0 47 /* Camera data pin 0 */
+#define GPIO48_nPOE 48 /* Output Enable for Card Space */
+#define GPIO48_CIF_DD_5 48 /* Camera data pin 5 */
+#define GPIO49_nPWE 49 /* Write Enable for Card Space */
+#define GPIO50_nPIOR 50 /* I/O Read for Card Space */
+#define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */
+#define GPIO51_nPIOW 51 /* I/O Write for Card Space */
+#define GPIO51_CIF_DD_2 51 /* Camera data pin 2 */
+#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
+#define GPIO52_CIF_DD_4 52 /* Camera data pin 4 */
+#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
+#define GPIO53_MMCCLK 53 /* MMC Clock */
+#define GPIO53_CIF_MCLK 53 /* Camera Master Clock */
+#define GPIO54_MMCCLK 54 /* MMC Clock */
+#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
+#define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */
+#define GPIO54_CIF_PCLK 54 /* Camera Pixel Clock */
+#define GPIO55_nPREG 55 /* Card Address bit 26 */
+#define GPIO55_CIF_DD_1 55 /* Camera data pin 1 */
+#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
+#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
+#define GPIO58_LDD_0 58 /* LCD data pin 0 */
+#define GPIO59_LDD_1 59 /* LCD data pin 1 */
+#define GPIO60_LDD_2 60 /* LCD data pin 2 */
+#define GPIO61_LDD_3 61 /* LCD data pin 3 */
+#define GPIO62_LDD_4 62 /* LCD data pin 4 */
+#define GPIO63_LDD_5 63 /* LCD data pin 5 */
+#define GPIO64_LDD_6 64 /* LCD data pin 6 */
+#define GPIO65_LDD_7 65 /* LCD data pin 7 */
+#define GPIO66_LDD_8 66 /* LCD data pin 8 */
+#define GPIO66_MBREQ 66 /* alternate bus master req */
+#define GPIO67_LDD_9 67 /* LCD data pin 9 */
+#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
+#define GPIO68_LDD_10 68 /* LCD data pin 10 */
+#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
+#define GPIO69_LDD_11 69 /* LCD data pin 11 */
+#define GPIO69_MMCCLK 69 /* MMC_CLK */
+#define GPIO70_LDD_12 70 /* LCD data pin 12 */
+#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
+#define GPIO71_LDD_13 71 /* LCD data pin 13 */
+#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
+#define GPIO72_LDD_14 72 /* LCD data pin 14 */
+#define GPIO72_32kHz 72 /* 32 kHz clock */
+#define GPIO73_LDD_15 73 /* LCD data pin 15 */
+#define GPIO73_MBGNT 73 /* Memory controller grant */
+#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
+#define GPIO75_LCD_LCLK 75 /* LCD line clock */
+#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
+#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
+#define GPIO78_nCS_2 78 /* chip select 2 */
+#define GPIO79_nCS_3 79 /* chip select 3 */
+#define GPIO80_nCS_4 80 /* chip select 4 */
+#define GPIO81_NSCLK 81 /* NSSP clock */
+#define GPIO81_CIF_DD_0 81 /* Camera data pin 0 */
+#define GPIO82_NSFRM 82 /* NSSP Frame */
+#define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */
+#define GPIO83_NSTXD 83 /* NSSP transmit */
+#define GPIO83_CIF_DD_4 83 /* Camera data pin 4 */
+#define GPIO84_NSRXD 84 /* NSSP receive */
+#define GPIO84_CIF_FV 84 /* Camera frame start signal */
+#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
+#define GPIO85_CIF_LV 85 /* Camera line start signal */
+#define GPIO90_CIF_DD_4 90 /* Camera data pin 4 */
+#define GPIO91_CIF_DD_5 91 /* Camera data pin 5 */
+#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
+#define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */
+#define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */
+#define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */
+#define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */
+#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
+#define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */
+#define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */
+#define GPIO105_CIF_DD_1 105 /* Camera data pin 1 */
+#define GPIO106_CIF_DD_9 106 /* Camera data pin 9 */
+#define GPIO107_CIF_DD_8 107 /* Camera data pin 8 */
+#define GPIO108_CIF_DD_7 108 /* Camera data pin 7 */
+#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
+#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
+#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
+#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */
+#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */
+#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
+#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */
+#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
+#define GPIO114_CIF_DD_1 114 /* Camera data pin 1 */
+#define GPIO115_CIF_DD_3 115 /* Camera data pin 3 */
+#define GPIO116_CIF_DD_2 116 /* Camera data pin 2 */
+
+/* GPIO alternate function mode & direction */
+
+#define GPIO_IN 0x000
+#define GPIO_OUT 0x080
+#define GPIO_ALT_FN_1_IN 0x100
+#define GPIO_ALT_FN_1_OUT 0x180
+#define GPIO_ALT_FN_2_IN 0x200
+#define GPIO_ALT_FN_2_OUT 0x280
+#define GPIO_ALT_FN_3_IN 0x300
+#define GPIO_ALT_FN_3_OUT 0x380
+#define GPIO_MD_MASK_NR 0x07f
+#define GPIO_MD_MASK_DIR 0x080
+#define GPIO_MD_MASK_FN 0x300
+#define GPIO_DFLT_LOW 0x400
+#define GPIO_DFLT_HIGH 0x800
+
+#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
+#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
+#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
+#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
+#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_CIF_DD_7_MD (12 | GPIO_ALT_FN_2_IN)
+#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
+#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
+#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
+#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_CIF_DD_6_MD (17 | GPIO_ALT_FN_2_IN)
+#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
+#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
+#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
+#define GPIO23_CIF_MCLK_MD (23 | GPIO_ALT_FN_1_OUT)
+#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
+#define GPIO24_CIF_FV_MD (24 | GPIO_ALT_FN_1_OUT)
+#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
+#define GPIO25_CIF_LV_MD (25 | GPIO_ALT_FN_1_OUT)
+#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
+#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
+#define GPIO26_CIF_PCLK_MD (26 | GPIO_ALT_FN_2_IN)
+#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
+#define GPIO27_CIF_DD_0_MD (27 | GPIO_ALT_FN_3_IN)
+#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
+#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)
+#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
+#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
+#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
+#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
+#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
+#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT)
+#define GPIO32_MMCCLK_MD (32 | GPIO_ALT_FN_2_OUT)
+#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
+#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
+#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
+#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
+#define GPIO35_KP_MKOUT6_MD (35 | GPIO_ALT_FN_2_OUT)
+#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
+#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
+#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
+#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
+#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
+#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT)
+#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
+#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
+#define GPIO42_CIF_MCLK_MD (42 | GPIO_ALT_FN_3_OUT)
+#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
+#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
+#define GPIO43_CIF_FV_MD (43 | GPIO_ALT_FN_3_OUT)
+#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
+#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
+#define GPIO44_CIF_LV_MD (44 | GPIO_ALT_FN_3_OUT)
+#define GPIO45_CIF_PCLK_MD (45 | GPIO_ALT_FN_3_IN)
+#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
+#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
+#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
+#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
+#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
+#define GPIO47_CIF_DD_0_MD (47 | GPIO_ALT_FN_1_IN)
+#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
+#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_CIF_DD_5_MD (48 | GPIO_ALT_FN_1_IN)
+#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
+#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
+#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
+#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
+#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
+#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
+#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
+#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
+#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
+#define GPIO52_CIF_DD_4_MD (52 | GPIO_ALT_FN_1_IN)
+#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
+#define GPIO53_CIF_MCLK_MD (53 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_CIF_PCLK_MD (54 | GPIO_ALT_FN_3_IN)
+#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
+#define GPIO55_CIF_DD_1_MD (55 | GPIO_ALT_FN_1_IN)
+#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
+#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
+#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
+#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
+#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
+#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
+#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
+#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
+#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
+#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
+#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
+#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
+#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
+#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
+#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
+#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
+#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
+#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
+#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
+#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
+#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
+#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
+#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
+#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
+#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
+#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
+#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
+#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nPCE_2_MD (78 | GPIO_ALT_FN_1_OUT)
+#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
+#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT)
+#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
+#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT)
+#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN)
+#define GPIO81_CIF_DD_0_MD (81 | GPIO_ALT_FN_2_IN)
+#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT)
+#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN)
+#define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN)
+#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)
+#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)
+#define GPIO83_CIF_DD_4_MD (83 | GPIO_ALT_FN_3_IN)
+#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)
+#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
+#define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN)
+#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
+#define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN)
+#define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT)
+#define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN)
+#define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN)
+#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
+#define GPIO93_CIF_DD_6_MD (93 | GPIO_ALT_FN_2_IN)
+#define GPIO94_CIF_DD_5_MD (94 | GPIO_ALT_FN_2_IN)
+#define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN)
+#define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN)
+#define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN)
+#define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN)
+#define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN)
+#define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN)
+#define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN)
+#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)
+#define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN)
+#define GPIO103_CIF_DD_3_MD (103 | GPIO_ALT_FN_1_IN)
+#define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT)
+#define GPIO104_CIF_DD_2_MD (104 | GPIO_ALT_FN_1_IN)
+#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
+#define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT)
+#define GPIO105_CIF_DD_1_MD (105 | GPIO_ALT_FN_1_IN)
+#define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT)
+#define GPIO106_CIF_DD_9_MD (106 | GPIO_ALT_FN_1_IN)
+#define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT)
+#define GPIO107_CIF_DD_8_MD (107 | GPIO_ALT_FN_1_IN)
+#define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT)
+#define GPIO108_CIF_DD_7_MD (108 | GPIO_ALT_FN_1_IN)
+#define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT)
+#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
+#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN)
+#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
+
+#endif /* __ASM_ARCH_PXA2XX_GPIO_H */
#ifndef __ASM_ARCH_PXA3XX_REGS_H
#define __ASM_ARCH_PXA3XX_REGS_H
+
+/*
+ * Oscillator Configuration Register (OSCC)
+ */
+#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */
+
+#define OSCC_PEN (1 << 11) /* 13MHz POUT */
+
+
/*
* Service Power Management Unit (MPMU)
*/
/*
* SCOOP2 internal GPIOs
*/
+#define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO
#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11
#define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12
-#define TOSA_SCOOP_IR_POWERDWN SCOOP_GPCR_PA13
-#define TOSA_SCOOP_SD_WP SCOOP_GPCR_PA14
-#define TOSA_SCOOP_PWR_ON SCOOP_GPCR_PA15
+#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2)
+#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3)
+#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4)
#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16
#define TOSA_SCOOP_BT_RESET SCOOP_GPCR_PA17
#define TOSA_SCOOP_BT_PWR_EN SCOOP_GPCR_PA18
/* GPIO Direction 1 : output mode / 0:input mode */
#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \
- TOSA_SCOOP_IR_POWERDWN | TOSA_SCOOP_PWR_ON | TOSA_SCOOP_AUD_PWR_ON |\
+ TOSA_SCOOP_AUD_PWR_ON |\
TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN )
/* GPIO out put level when init 1: Hi */
#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN )
/*
* SCOOP2 jacket GPIOs
*/
-#define TOSA_SCOOP_JC_BT_LED SCOOP_GPCR_PA11
-#define TOSA_SCOOP_JC_NOTE_LED SCOOP_GPCR_PA12
-#define TOSA_SCOOP_JC_CHRG_ERR_LED SCOOP_GPCR_PA13
-#define TOSA_SCOOP_JC_USB_PULLUP SCOOP_GPCR_PA14
+#define TOSA_SCOOP_JC_GPIO_BASE (NR_BUILTIN_GPIO + 12)
+#define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0)
+#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1)
+#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2)
+#define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3)
#define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15
#define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16
#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17
-#define TOSA_SCOOP_JC_WLAN_LED SCOOP_GPCR_PA18
+#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7)
#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19
/* GPIO Direction 1 : output mode / 0:input mode */
-#define TOSA_SCOOP_JC_IO_DIR ( TOSA_SCOOP_JC_BT_LED | TOSA_SCOOP_JC_NOTE_LED | \
- TOSA_SCOOP_JC_CHRG_ERR_LED | TOSA_SCOOP_JC_USB_PULLUP | \
+#define TOSA_SCOOP_JC_IO_DIR ( \
TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \
- TOSA_SCOOP_JC_WLAN_LED | TOSA_SCOOP_JC_CARD_LIMIT_SEL )
-/* GPIO out put level when init 1: Hi */
-#define TOSA_SCOOP_JC_IO_OUT ( 0 )
+ TOSA_SCOOP_JC_CARD_LIMIT_SEL )
/*
* Timing Generator
#define TG_PINICTL 0x06
#define TG_HPOSCTL 0x07
-/*
- * LED
- */
-#define TOSA_SCOOP_LED_BLUE TOSA_SCOOP_GPCR_PA11
-#define TOSA_SCOOP_LED_GREEN TOSA_SCOOP_GPCR_PA12
-#define TOSA_SCOOP_LED_ORANGE TOSA_SCOOP_GPCR_PA13
-#define TOSA_SCOOP_LED_WLAN TOSA_SCOOP_GPCR_PA18
-
-
/*
* PXA GPIOs
*/
#define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW)
-extern struct platform_device tosascoop_jc_device;
-extern struct platform_device tosascoop_device;
-
#define TOSA_KEY_SYNC KEY_102ND /* ??? */
-
#ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES
#define TOSA_KEY_RECORD KEY_YEN
#define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA
extern int gpio_backlight;
extern int gpio_eth_irq;
+extern int wm9713_irq;
+
extern int lcd_id;
extern int lcd_orientation;
/*
* RealView EB + ARM11MPCore peripheral addresses
*/
+#define REALVIEW_EB_UART0_BASE 0x10009000 /* UART 0 */
+#define REALVIEW_EB_UART1_BASE 0x1000A000 /* UART 1 */
+#define REALVIEW_EB_UART2_BASE 0x1000B000 /* UART 2 */
+#define REALVIEW_EB_UART3_BASE 0x1000C000 /* UART 3 */
+#define REALVIEW_EB_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
+#define REALVIEW_EB_WATCHDOG_BASE 0x10010000 /* watchdog interface */
+#define REALVIEW_EB_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
+#define REALVIEW_EB_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
+#define REALVIEW_EB_GPIO0_BASE 0x10013000 /* GPIO port 0 */
+#define REALVIEW_EB_RTC_BASE 0x10017000 /* Real Time Clock */
+#define REALVIEW_EB_CLCD_BASE 0x10020000 /* CLCD */
+#define REALVIEW_EB_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
+#define REALVIEW_EB_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
+#define REALVIEW_EB_SMC_BASE 0x10080000 /* Static memory controller */
+
+#define REALVIEW_EB_FLASH_BASE 0x40000000
+#define REALVIEW_EB_FLASH_SIZE SZ_64M
+#define REALVIEW_EB_ETH_BASE 0x4E000000 /* Ethernet */
+#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */
+
#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
--- /dev/null
+/*
+ * include/asm-arm/arch-realview/board-pb1176.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_BOARD_PB1176_H
+#define __ASM_ARCH_BOARD_PB1176_H
+
+#include <asm/arch/platform.h>
+
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */
+#define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */
+#define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */
+#define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
+#define REALVIEW_PB1176_FLASH_BASE 0x30000000
+#define REALVIEW_PB1176_FLASH_SIZE SZ_64M
+
+#define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */
+#define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */
+#define REALVIEW_PB1176_TIMER4_5_BASE 0x10106000 /* Timer 4 and 5 */
+#define REALVIEW_PB1176_WATCHDOG_BASE 0x10107000 /* watchdog interface */
+#define REALVIEW_PB1176_RTC_BASE 0x10108000 /* Real Time Clock */
+#define REALVIEW_PB1176_GPIO0_BASE 0x1010A000 /* GPIO port 0 */
+#define REALVIEW_PB1176_SSP_BASE 0x1010B000 /* Synchronous Serial Port */
+#define REALVIEW_PB1176_UART0_BASE 0x1010C000 /* UART 0 */
+#define REALVIEW_PB1176_UART1_BASE 0x1010D000 /* UART 1 */
+#define REALVIEW_PB1176_UART2_BASE 0x1010E000 /* UART 2 */
+#define REALVIEW_PB1176_UART3_BASE 0x1010F000 /* UART 3 */
+#define REALVIEW_PB1176_CLCD_BASE 0x10112000 /* CLCD */
+#define REALVIEW_PB1176_ETH_BASE 0x3A000000 /* Ethernet */
+#define REALVIEW_PB1176_USB_BASE 0x3B000000 /* USB */
+
+/*
+ * PCI regions
+ */
+#define REALVIEW_PB1176_PCI_BASE 0x60000000 /* PCI self config */
+#define REALVIEW_PB1176_PCI_CFG_BASE 0x61000000 /* PCI config */
+#define REALVIEW_PB1176_PCI_IO_BASE0 0x62000000 /* PCI IO region */
+#define REALVIEW_PB1176_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */
+#define REALVIEW_PB1176_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */
+#define REALVIEW_PB1176_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */
+
+#define REALVIEW_PB1176_PCI_BASE_SIZE 0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE 0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE 0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE 0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE 0x04000000 /* 64MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE 0x08000000 /* 128MB */
+
+#define REALVIEW_DC1176_GIC_CPU_BASE 0x10120000 /* GIC CPU interface, on devchip */
+#define REALVIEW_DC1176_GIC_DIST_BASE 0x10121000 /* GIC distributor, on devchip */
+#define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */
+#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */
+#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */
+
+/*
+ * Irqs
+ */
+#define IRQ_DC1176_GIC_START 32
+#define IRQ_PB1176_GIC_START 64
+
+/*
+ * ARM1176 DevChip interrupt sources (primary GIC)
+ */
+#define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */
+#define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */
+#define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */
+#define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */
+#define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */
+#define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */
+#define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */
+#define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11)
+#define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12)
+#define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13)
+#define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14)
+#define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */
+#define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */
+#define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */
+#define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */
+#define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */
+
+#define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */
+#define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */
+
+/*
+ * RealView PB1176 interrupt sources (secondary GIC)
+ */
+#define IRQ_PB1176_MMCI0A (IRQ_PB1176_GIC_START + 1) /* Multimedia Card 0A */
+#define IRQ_PB1176_MMCI0B (IRQ_PB1176_GIC_START + 2) /* Multimedia Card 0A */
+#define IRQ_PB1176_KMI0 (IRQ_PB1176_GIC_START + 3) /* Keyboard/Mouse port 0 */
+#define IRQ_PB1176_KMI1 (IRQ_PB1176_GIC_START + 4) /* Keyboard/Mouse port 1 */
+#define IRQ_PB1176_SCI (IRQ_PB1176_GIC_START + 5)
+#define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */
+#define IRQ_PB1176_CHARLCD (IRQ_PB1176_GIC_START + 7) /* Character LCD */
+#define IRQ_PB1176_GPIO1 (IRQ_PB1176_GIC_START + 8)
+#define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9)
+#define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */
+#define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */
+
+#define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16)
+
+#define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */
+
+#define IRQ_PB1176_TIMER0_1 (IRQ_PB1176_GIC_START + 22)
+#define IRQ_PB1176_TIMER2_3 (IRQ_PB1176_GIC_START + 23)
+#define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */
+#define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */
+
+#define IRQ_PB1176_GPIO0 -1
+#define IRQ_PB1176_SSP -1
+#define IRQ_PB1176_SCTL -1
+
+#define NR_GIC_PB1176 2
+
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PB1176
+ */
+#define NR_IRQS_PB1176 (IRQ_DC1176_GIC_START + 96)
+
+#if defined(CONFIG_MACH_REALVIEW_PB1176)
+
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176)
+#undef NR_IRQS
+#define NR_IRQS NR_IRQS_PB1176
+#endif
+
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR NR_GIC_PB1176
+#endif
+
+#endif /* CONFIG_MACH_REALVIEW_PB1176 */
+
+#endif /* __ASM_ARCH_BOARD_PB1176_H */
--- /dev/null
+/*
+ * include/asm-arm/arch-realview/board-pb11mp.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_BOARD_PB11MP_H
+#define __ASM_ARCH_BOARD_PB11MP_H
+
+#include <asm/arch/platform.h>
+
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_PB11MP_UART0_BASE 0x10009000 /* UART 0 */
+#define REALVIEW_PB11MP_UART1_BASE 0x1000A000 /* UART 1 */
+#define REALVIEW_PB11MP_UART2_BASE 0x1000B000 /* UART 2 */
+#define REALVIEW_PB11MP_UART3_BASE 0x1000C000 /* UART 3 */
+#define REALVIEW_PB11MP_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
+#define REALVIEW_PB11MP_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
+#define REALVIEW_PB11MP_WATCHDOG_BASE 0x10010000 /* watchdog interface */
+#define REALVIEW_PB11MP_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
+#define REALVIEW_PB11MP_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
+#define REALVIEW_PB11MP_GPIO0_BASE 0x10013000 /* GPIO port 0 */
+#define REALVIEW_PB11MP_RTC_BASE 0x10017000 /* Real Time Clock */
+#define REALVIEW_PB11MP_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
+#define REALVIEW_PB11MP_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
+#define REALVIEW_PB11MP_SCTL_BASE 0x1001A000 /* System Controller */
+#define REALVIEW_PB11MP_CLCD_BASE 0x10020000 /* CLCD */
+#define REALVIEW_PB11MP_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
+#define REALVIEW_PB11MP_DMC_BASE 0x100E0000 /* DMC configuration */
+#define REALVIEW_PB11MP_SMC_BASE 0x100E1000 /* SMC configuration */
+#define REALVIEW_PB11MP_CAN_BASE 0x100E2000 /* CAN bus */
+#define REALVIEW_PB11MP_CF_BASE 0x18000000 /* Compact flash */
+#define REALVIEW_PB11MP_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */
+#define REALVIEW_PB11MP_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */
+#define REALVIEW_PB11MP_FLASH0_BASE 0x40000000
+#define REALVIEW_PB11MP_FLASH0_SIZE SZ_64M
+#define REALVIEW_PB11MP_FLASH1_BASE 0x44000000
+#define REALVIEW_PB11MP_FLASH1_SIZE SZ_64M
+#define REALVIEW_PB11MP_ETH_BASE 0x4E000000 /* Ethernet */
+#define REALVIEW_PB11MP_USB_BASE 0x4F000000 /* USB */
+#define REALVIEW_PB11MP_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
+#define REALVIEW_PB11MP_LT_BASE 0xC0000000 /* Logic Tile expansion */
+#define REALVIEW_PB11MP_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
+#define REALVIEW_PB11MP_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
+
+#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74
+
+/*
+ * PB11MPCore PCI regions
+ */
+#define REALVIEW_PB11MP_PCI_BASE 0x90040000 /* PCI-X Unit base */
+#define REALVIEW_PB11MP_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
+#define REALVIEW_PB11MP_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
+
+#define REALVIEW_PB11MP_PCI_BASE_SIZE 0x10000 /* 16 Kb */
+#define REALVIEW_PB11MP_PCI_IO_SIZE 0x1000 /* 4 Kb */
+#define REALVIEW_PB11MP_PCI_MEM_SIZE 0x20000000 /* 512 MB */
+
+/*
+ * Testchip peripheral and fpga gic regions
+ */
+#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
+#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
+#define REALVIEW_TC11MP_TWD_BASE 0x1F000700
+#define REALVIEW_TC11MP_TWD_SIZE 0x00000100
+#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */
+#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */
+
+/*
+ * Irqs
+ */
+#define IRQ_TC11MP_GIC_START 32
+#define IRQ_PB11MP_GIC_START 64
+
+/*
+ * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
+ */
+#define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0)
+#define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1)
+#define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2)
+#define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3)
+#define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4)
+#define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5)
+#define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6)
+#define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7)
+#define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8)
+#define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9)
+#define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */
+#define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */
+#define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */
+#define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */
+#define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14)
+#define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15)
+
+#define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17)
+#define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18)
+#define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19)
+#define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20)
+#define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21)
+#define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22)
+#define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23)
+#define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24)
+#define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25)
+#define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26)
+#define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27)
+#define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28)
+
+#define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29)
+#define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30)
+#define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31)
+
+/*
+ * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
+ */
+#define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */
+#define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */
+#define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */
+#define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */
+#define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */
+#define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */
+#define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */
+ /* 9 reserved */
+#define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */
+#define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */
+#define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */
+#define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */
+#define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */
+#define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */
+#define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */
+#define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */
+#define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */
+#define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */
+#define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */
+#define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */
+#define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */
+#define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */
+#define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */
+#define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */
+#define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */
+#define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */
+#define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */
+#define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */
+#define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */
+#define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */
+
+#define IRQ_PB11MP_SMC -1
+#define IRQ_PB11MP_SCTL -1
+
+#define NR_GIC_PB11MP 2
+
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PB11MP
+ */
+#define NR_IRQS_PB11MP (IRQ_TC11MP_GIC_START + 96)
+
+#if defined(CONFIG_MACH_REALVIEW_PB11MP)
+
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
+#undef NR_IRQS
+#define NR_IRQS NR_IRQS_PB11MP
+#endif
+
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR NR_GIC_PB11MP
+#endif
+
+#endif /* CONFIG_MACH_REALVIEW_PB11MP */
+
+#endif /* __ASM_ARCH_BOARD_PB11MP_H */
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x10000000
- movne \rx, #0xf1000000 @ virtual base
+ movne \rx, #0xf0000000 @ virtual base
orr \rx, \rx, #0x00009000
.endm
#include <asm/sizes.h>
/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
+#define IO_ADDRESS(x) (((x) & 0x0fffffff) + 0xf0000000)
#define __io_address(n) __io(IO_ADDRESS(n))
#endif
#define __ASM_ARCH_IRQS_H
#include <asm/arch/board-eb.h>
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/board-pb1176.h>
#define IRQ_LOCALTIMER 29
#define IRQ_LOCALWDOG 30
#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
#define REALVIEW_SSRAM_SIZE SZ_2M
-#define REALVIEW_FLASH_BASE 0x40000000
-#define REALVIEW_FLASH_SIZE SZ_64M
-
/*
* SDRAM
*/
#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
/*
- * REALVIEW peripheral addresses
+ * RealView common peripheral addresses
*/
#define REALVIEW_SCTL_BASE 0x10001000 /* System controller */
#define REALVIEW_I2C_BASE 0x10002000 /* I2C control */
- /* Reserved 0x10003000 */
#define REALVIEW_AACI_BASE 0x10004000 /* Audio */
#define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */
#define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */
#define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */
#define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */
-#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */
-#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */
-#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */
-#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */
-#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
#define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */
- /* Reserved 0x1000F000 */
-#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */
-#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
-#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
-#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */
#define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */
#define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */
- /* Reserved 0x10016000 */
-#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */
#define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */
-#define REALVIEW_PCI_CORE_BASE 0x10019000 /* PCI configuration */
- /* Reserved 0x1001A000 - 0x1001FFFF */
-#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
-#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
-#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
-#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
- /* Reserved 0x10090000 - 0x100EFFFF */
-
-#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */
/* PCI space */
#define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */
#ifndef __ASMARM_ARCH_SCU_H
#define __ASMARM_ARCH_SCU_H
-#include <asm/arch/board-eb.h>
-
-#define SCU_BASE REALVIEW_EB11MP_SCU_BASE
+/*
+ * SCU registers
+ */
+#define SCU_CTRL 0x00
+#define SCU_CONFIG 0x04
+#define SCU_CPU_STATUS 0x08
+#define SCU_INVALIDATE 0x0c
+#define SCU_FPGA_REVISION 0x10
#endif
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <asm/hardware.h>
+#include <asm/mach-types.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/board-eb.h>
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/board-pb1176.h>
-#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
-#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
-#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
-#define AMBA_UART_FR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18))
+#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
+#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
+#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
+#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
+
+/*
+ * Return the UART base address
+ */
+static inline unsigned long get_uart_base(void)
+{
+ if (machine_is_realview_eb())
+ return REALVIEW_EB_UART0_BASE;
+ else if (machine_is_realview_pb11mp())
+ return REALVIEW_PB11MP_UART0_BASE;
+ else if (machine_is_realview_pb1176())
+ return REALVIEW_PB1176_UART0_BASE;
+ else
+ return 0;
+}
/*
* This does not append a newline
*/
static inline void putc(int c)
{
- while (AMBA_UART_FR & (1 << 5))
+ unsigned long base = get_uart_base();
+
+ while (AMBA_UART_FR(base) & (1 << 5))
barrier();
- AMBA_UART_DR = c;
+ AMBA_UART_DR(base) = c;
}
static inline void flush(void)
{
- while (AMBA_UART_FR & (1 << 3))
+ unsigned long base = get_uart_base();
+
+ while (AMBA_UART_FR(base) & (1 << 3))
barrier();
}
#define S3C2412_CLKDIVN_PDIVN (1<<2)
#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
-#define S3C2421_CLKDIVN_ARMDIVN (1<<3)
+#define S3C2412_CLKDIVN_ARMDIVN (1<<3)
#define S3C2412_CLKDIVN_DVSEN (1<<4)
#define S3C2412_CLKDIVN_HALFHCLK (1<<5)
#define S3C2412_CLKDIVN_USB48DIV (1<<6)
#define S3C2410_GPD14_INP (0x00 << 28)
#define S3C2410_GPD14_OUTP (0x01 << 28)
#define S3C2410_GPD14_VD22 (0x02 << 28)
+#define S3C2410_GPD14_nSS1 (0x03 << 28)
#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
#define S3C2410_GPD15_INP (0x00 << 30)
#define S3C2410_GPD15_OUTP (0x01 << 30)
#define S3C2410_GPD15_VD23 (0x02 << 30)
+#define S3C2410_GPD15_nSS0 (0x03 << 30)
#define S3C2410_GPD_PUPDIS(x) (1<<(x))
#define S3C2410_GPG2_INP (0x00 << 4)
#define S3C2410_GPG2_OUTP (0x01 << 4)
#define S3C2410_GPG2_EINT10 (0x02 << 4)
+#define S3C2410_GPG2_nSS0 (0x03 << 4)
#define S3C2400_GPG2_CDCLK (0x02 << 4)
#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
#define S3C2410_GPG3_INP (0x00 << 6)
#define S3C2410_GPG3_OUTP (0x01 << 6)
#define S3C2410_GPG3_EINT11 (0x02 << 6)
+#define S3C2410_GPG3_nSS1 (0x03 << 6)
#define S3C2400_GPG3_I2SSDO (0x02 << 6)
#define S3C2400_GPG3_I2SSDI (0x03 << 6)
--- /dev/null
+/* linux/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2412 memory register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_S3C2412_MEM
+#define __ASM_ARM_REGS_S3C2412_MEM
+
+#ifndef S3C2412_MEMREG
+#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
+#endif
+
+#define S3C2412_BANKCFG S3C2412_MEMREG(0x00)
+#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04)
+#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08)
+#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C)
+
+#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
+#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14)
+
+#endif /* __ASM_ARM_REGS_S3C2412_MEM */
--- /dev/null
+/* linux/include/asm-arm/arch-s3c2410/system-reset.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - System define for arch_reset() function
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+#include <asm/plat-s3c/regs-watchdog.h>
+#include <asm/arch/regs-clock.h>
+
+#include <linux/clk.h>
+#include <linux/err.h>
+
+extern void (*s3c24xx_reset_hook)(void);
+
+static void
+arch_reset(char mode)
+{
+ struct clk *wdtclk;
+
+ if (mode == 's') {
+ cpu_reset(0);
+ }
+
+ if (s3c24xx_reset_hook)
+ s3c24xx_reset_hook();
+
+ printk("arch_reset: attempting watchdog reset\n");
+
+ __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
+
+ wdtclk = clk_get(NULL, "watchdog");
+ if (!IS_ERR(wdtclk)) {
+ clk_enable(wdtclk);
+ } else
+ printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
+
+ /* put initial values into count and data */
+ __raw_writel(0x80, S3C2410_WTCNT);
+ __raw_writel(0x80, S3C2410_WTDAT);
+
+ /* set the watchdog to go and reset... */
+ __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
+ S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
+
+ /* wait for reset to assert... */
+ mdelay(500);
+
+ printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+
+ /* delay to allow the serial port to show the message */
+ mdelay(50);
+
+ /* we'll take a jump through zero as a poor second */
+ cpu_reset(0);
+}
#include <asm/arch/idle.h>
#include <asm/arch/reset.h>
-#include <asm/plat-s3c/regs-watchdog.h>
#include <asm/arch/regs-clock.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-
void (*s3c24xx_idle)(void);
void (*s3c24xx_reset_hook)(void);
s3c24xx_default_idle();
}
-static void
-arch_reset(char mode)
-{
- struct clk *wdtclk;
-
- if (mode == 's') {
- cpu_reset(0);
- }
-
- if (s3c24xx_reset_hook)
- s3c24xx_reset_hook();
-
- printk("arch_reset: attempting watchdog reset\n");
-
- __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
-
- wdtclk = clk_get(NULL, "watchdog");
- if (!IS_ERR(wdtclk)) {
- clk_enable(wdtclk);
- } else
- printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
-
- /* put initial values into count and data */
- __raw_writel(0x80, S3C2410_WTCNT);
- __raw_writel(0x80, S3C2410_WTDAT);
-
- /* set the watchdog to go and reset... */
- __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
- S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
-
- /* wait for reset to assert... */
- mdelay(500);
-
- printk(KERN_ERR "Watchdog reset failed to assert reset\n");
-
- /* delay to allow the serial port to show the message */
- mdelay(50);
-
- /* we'll take a jump through zero as a poor second */
- cpu_reset(0);
-}
+#include <asm/arch/system-reset.h>
#include <asm/hardware.h>
#include <asm/irq.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
- return;
-}
-
-extern int gpio_direction_input(unsigned gpio);
-extern int gpio_direction_output(unsigned gpio, int value);
-
+#include <asm-generic/gpio.h>
static inline int gpio_get_value(unsigned gpio)
{
- return GPLR & GPIO_GPIO(gpio);
+ if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
+ return GPLR & GPIO_GPIO(gpio);
+ else
+ return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
- if (value)
- GPSR = GPIO_GPIO(gpio);
+ if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
+ if (value)
+ GPSR = GPIO_GPIO(gpio);
+ else
+ GPCR = GPIO_GPIO(gpio);
else
- GPCR = GPIO_GPIO(gpio);
+ __gpio_set_value(gpio, value);
}
-#include <asm-generic/gpio.h> /* cansleep wrappers */
+#define gpio_cansleep __gpio_cansleep
static inline unsigned gpio_to_irq(unsigned gpio)
{
* get data abort address/flags
*/
void (*_data_abort)(unsigned long pc);
+ /*
+ * Retrieve prefetch fault address
+ */
+ unsigned long (*_prefetch_abort)(unsigned long lr);
/*
* Set up any processor specifics
*/
* v6_early - ARMv6 generic early abort handler
* v7_early - ARMv7 generic early abort handler
*/
-#undef CPU_ABORT_HANDLER
-#undef MULTI_ABORT
+#undef CPU_DABORT_HANDLER
+#undef MULTI_DABORT
#if defined(CONFIG_CPU_ARM610)
-# ifdef CPU_ABORT_HANDLER
-# define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+# define MULTI_DABORT 1
# else
-# define CPU_ABORT_HANDLER cpu_arm6_data_abort
+# define CPU_DABORT_HANDLER cpu_arm6_data_abort
# endif
#endif
#if defined(CONFIG_CPU_ARM710)
-# ifdef CPU_ABORT_HANDLER
-# define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+# define MULTI_DABORT 1
# else
-# define CPU_ABORT_HANDLER cpu_arm7_data_abort
+# define CPU_DABORT_HANDLER cpu_arm7_data_abort
# endif
#endif
#ifdef CONFIG_CPU_ABRT_LV4T
-# ifdef CPU_ABORT_HANDLER
-# define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+# define MULTI_DABORT 1
# else
-# define CPU_ABORT_HANDLER v4t_late_abort
+# define CPU_DABORT_HANDLER v4t_late_abort
# endif
#endif
#ifdef CONFIG_CPU_ABRT_EV4
-# ifdef CPU_ABORT_HANDLER
-# define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+# define MULTI_DABORT 1
# else
-# define CPU_ABORT_HANDLER v4_early_abort
+# define CPU_DABORT_HANDLER v4_early_abort
# endif
#endif
#ifdef CONFIG_CPU_ABRT_EV4T
-# ifdef CPU_ABORT_HANDLER
-# define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+# define MULTI_DABORT 1
# else
-# define CPU_ABORT_HANDLER v4t_early_abort
+# define CPU_DABORT_HANDLER v4t_early_abort
# endif
#endif
#ifdef CONFIG_CPU_ABRT_EV5TJ
-# ifdef CPU_ABORT_HANDLER
-# define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+# define MULTI_DABORT 1
# else
-# define CPU_ABORT_HANDLER v5tj_early_abort
+# define CPU_DABORT_HANDLER v5tj_early_abort
# endif
#endif
#ifdef CONFIG_CPU_ABRT_EV5T
-# ifdef CPU_ABORT_HANDLER
-# define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+# define MULTI_DABORT 1
# else
-# define CPU_ABORT_HANDLER v5t_early_abort
+# define CPU_DABORT_HANDLER v5t_early_abort
# endif
#endif
#ifdef CONFIG_CPU_ABRT_EV6
-# ifdef CPU_ABORT_HANDLER
-# define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+# define MULTI_DABORT 1
# else
-# define CPU_ABORT_HANDLER v6_early_abort
+# define CPU_DABORT_HANDLER v6_early_abort
# endif
#endif
#ifdef CONFIG_CPU_ABRT_EV7
-# ifdef CPU_ABORT_HANDLER
-# define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+# define MULTI_DABORT 1
# else
-# define CPU_ABORT_HANDLER v7_early_abort
+# define CPU_DABORT_HANDLER v7_early_abort
# endif
#endif
-#ifndef CPU_ABORT_HANDLER
+#ifndef CPU_DABORT_HANDLER
#error Unknown data abort handler type
#endif
+/*
+ * Prefetch abort handler. If the CPU has an IFAR use that, otherwise
+ * use the address of the aborted instruction
+ */
+#undef CPU_PABORT_HANDLER
+#undef MULTI_PABORT
+
+#ifdef CONFIG_CPU_PABRT_IFAR
+# ifdef CPU_PABORT_HANDLER
+# define MULTI_PABORT 1
+# else
+# define CPU_PABORT_HANDLER(reg, insn) mrc p15, 0, reg, cr6, cr0, 2
+# endif
+#endif
+
+#ifdef CONFIG_CPU_PABRT_NOIFAR
+# ifdef CPU_PABORT_HANDLER
+# define MULTI_PABORT 1
+# else
+# define CPU_PABORT_HANDLER(reg, insn) mov reg, insn
+# endif
+#endif
+
+#ifndef CPU_PABORT_HANDLER
+#error Unknown prefetch abort handler type
+#endif
+
#endif
+++ /dev/null
-#ifndef ASMARM_HARDWARE_ARM_SCU_H
-#define ASMARM_HARDWARE_ARM_SCU_H
-
-#include <asm/arch/scu.h>
-
-/*
- * SCU registers
- */
-#define SCU_CTRL 0x00
-#define SCU_CONFIG 0x04
-#define SCU_CPU_STATUS 0x08
-#define SCU_INVALIDATE 0x0c
-#define SCU_FPGA_REVISION 0x10
-
-#endif
static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
int *slots_per_op)
{
- const static int slot_count_table[] = { 0,
+ static const int slot_count_table[] = { 0,
1, 1, 1, 1, /* 01 - 04 */
2, 2, 2, 2, /* 05 - 08 */
4, 4, 4, 4, /* 09 - 12 */
/* translate the src_idx to a descriptor word index */
static inline int __desc_idx(int src_idx)
{
- const static int desc_idx_table[] = { 0, 0, 0, 0,
+ static const int desc_idx_table[] = { 0, 0, 0, 0,
0, 1, 2, 3,
5, 6, 7, 8,
9, 10, 11, 12,
extern int gpio_line_get(int line);
extern void gpio_line_set(int line, int value);
extern int init_atu;
+extern int iop3xx_get_init_atu(void);
#endif
#define IOP3XX_INIT_ATU_DISABLE -1
#define IOP3XX_INIT_ATU_ENABLE 1
-#ifdef CONFIG_IOP3XX_ATU
-#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
- IOP3XX_INIT_ATU_ENABLE : init_atu)
-#else
-#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
- IOP3XX_INIT_ATU_DISABLE : init_atu)
-#endif
-
/* Messaging Unit */
#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
unsigned short io_dir;
unsigned short suspend_clr;
unsigned short suspend_set;
+ int gpio_base;
};
/* Structure for linking scoop devices to PCMCIA sockets */
extern struct scoop_pcmcia_config *platform_scoop_config;
void reset_scoop(struct device *dev);
-unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
-unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit);
+unsigned short __deprecated set_scoop_gpio(struct device *dev, unsigned short bit);
+unsigned short __deprecated reset_scoop_gpio(struct device *dev, unsigned short bit);
unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);
#define HWCAP_JAVA 256
#define HWCAP_IWMMXT 512
#define HWCAP_CRUNCH 1024
+#define HWCAP_THUMBEE 2048
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
/*
extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
extern void iop3xx_pci_preinit(void);
+extern void iop3xx_pci_preinit_cond(void);
extern int dc21285_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
#ifndef CONFIG_DISCONTIGMEM
#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
+
+#ifndef CONFIG_SPARSEMEM
#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
+#endif
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
--- /dev/null
+/*
+ * include/asm-arm/plat-orion/ehci-orion.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_PLAT_ORION_EHCI_ORION_H
+#define __ASM_PLAT_ORION_EHCI_ORION_H
+
+#include <linux/mbus.h>
+
+struct orion_ehci_data {
+ struct mbus_dram_target_info *dram;
+};
+
+
+#endif
--- /dev/null
+/*
+ * include/asm-arm/plat-orion/irq.h
+ *
+ * Marvell Orion SoC IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_PLAT_ORION_IRQ_H
+#define __ASM_PLAT_ORION_IRQ_H
+
+void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
+
+
+#endif
/*
- * asm-arm/arch-orion/platform.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
+ * include/asm-arm/plat-orion/orion_nand.h
*
* This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
-#ifndef __ASM_ARCH_PLATFORM_H__
-#define __ASM_ARCH_PLATFORM_H__
+#ifndef __ASM_PLAT_ORION_ORION_NAND_H
+#define __ASM_PLAT_ORION_ORION_NAND_H
/*
* Device bus NAND private data
u8 width; /* buswidth */
};
+
#endif
--- /dev/null
+/*
+ * include/asm-arm/plat-orion/pcie.h
+ *
+ * Marvell Orion SoC PCIe handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_PLAT_ORION_PCIE_H
+#define __ASM_PLAT_ORION_PCIE_H
+
+u32 orion_pcie_dev_id(void __iomem *base);
+u32 orion_pcie_rev(void __iomem *base);
+int orion_pcie_link_up(void __iomem *base);
+int orion_pcie_get_local_bus_nr(void __iomem *base);
+void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
+void orion_pcie_setup(void __iomem *base,
+ struct mbus_dram_target_info *dram);
+int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val);
+int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val);
+int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val);
+int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 val);
+
+
+#endif
--- /dev/null
+/*
+ * include/asm-arm/plat-orion/time.h
+ *
+ * Marvell Orion SoC time handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_PLAT_ORION_TIME_H
+#define __ASM_PLAT_ORION_TIME_H
+
+void orion_time_init(unsigned int irq, unsigned int tclk);
+
+
+#endif
--- /dev/null
+#ifndef ASMARM_SPARSEMEM_H
+#define ASMARM_SPARSEMEM_H
+
+#include <asm/memory.h>
+
+#define MAX_PHYSADDR_BITS 32
+#define MAX_PHYSMEM_BITS 32
+#define SECTION_SIZE_BITS NODE_MEM_SIZE_BITS
+
+#endif
struct crunch_state crunchstate;
union fp_state fpstate __attribute__((aligned(8)));
union vfp_state vfpstate;
+#ifdef CONFIG_ARM_THUMBEE
+ unsigned long thumbee_state; /* ThumbEE Handler Base register */
+#endif
struct restart_block restart_block;
};
#define __NR_kexec_load (__NR_SYSCALL_BASE+347)
#define __NR_utimensat (__NR_SYSCALL_BASE+348)
#define __NR_signalfd (__NR_SYSCALL_BASE+349)
-#define __NR_timerfd (__NR_SYSCALL_BASE+350)
+#define __NR_timerfd_create (__NR_SYSCALL_BASE+350)
#define __NR_eventfd (__NR_SYSCALL_BASE+351)
#define __NR_fallocate (__NR_SYSCALL_BASE+352)
+#define __NR_timerfd_settime (__NR_SYSCALL_BASE+353)
+#define __NR_timerfd_gettime (__NR_SYSCALL_BASE+354)
/*
* The following SWIs are ARM private.
at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
unsigned long fbmem_start, unsigned long fbmem_len);
-struct usba_platform_data {
- int vbus_pin;
-};
+struct usba_platform_data;
struct platform_device *
at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
struct platform_device *
at32_add_device_ssc(unsigned int id, unsigned int flags);
-struct platform_device *at32_add_device_twi(unsigned int id);
+struct i2c_board_info;
+struct platform_device *at32_add_device_twi(unsigned int id,
+ struct i2c_board_info *b,
+ unsigned int n);
struct platform_device *at32_add_device_mci(unsigned int id);
struct platform_device *at32_add_device_ac97c(unsigned int id);
struct platform_device *at32_add_device_abdac(unsigned int id);
--- /dev/null
+/*
+ * AVR32 AP Power Management.
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_AVR32_ARCH_PM_H
+#define __ASM_AVR32_ARCH_PM_H
+
+/* Possible arguments to the "sleep" instruction */
+#define CPU_SLEEP_IDLE 0
+#define CPU_SLEEP_FROZEN 1
+#define CPU_SLEEP_STANDBY 2
+#define CPU_SLEEP_STOP 3
+#define CPU_SLEEP_STATIC 5
+
+#ifndef __ASSEMBLY__
+extern void cpu_enter_idle(void);
+
+extern bool disable_idle_sleep;
+
+static inline void cpu_disable_idle_sleep(void)
+{
+ disable_idle_sleep = true;
+}
+
+static inline void cpu_enable_idle_sleep(void)
+{
+ disable_idle_sleep = false;
+}
+
+static inline void cpu_idle_sleep(void)
+{
+ /*
+ * If we're using the COUNT and COMPARE registers for
+ * timekeeping, we can't use the IDLE state.
+ */
+ if (disable_idle_sleep)
+ cpu_relax();
+ else
+ cpu_enter_idle();
+}
+#endif
+
+#endif /* __ASM_AVR32_ARCH_PM_H */
+++ /dev/null
-/*
- * Copyright (C) 2007 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
-#define _ASM_AVR32_ARCH_AT32AP_TIME_H
-
-#include <linux/platform_device.h>
-
-extern struct irqaction timer_irqaction;
-extern struct platform_device at32_systc0_device;
-extern void local_timer_interrupt(int irq, void *dev_id);
-
-#define TIMER_BCR 0x000000c0
-#define TIMER_BCR_SYNC 0
-#define TIMER_BMR 0x000000c4
-#define TIMER_BMR_TC0XC0S 0
-#define TIMER_BMR_TC1XC1S 2
-#define TIMER_BMR_TC2XC2S 4
-#define TIMER_CCR 0x00000000
-#define TIMER_CCR_CLKDIS 1
-#define TIMER_CCR_CLKEN 0
-#define TIMER_CCR_SWTRG 2
-#define TIMER_CMR 0x00000004
-#define TIMER_CMR_ABETRG 10
-#define TIMER_CMR_ACPA 16
-#define TIMER_CMR_ACPC 18
-#define TIMER_CMR_AEEVT 20
-#define TIMER_CMR_ASWTRG 22
-#define TIMER_CMR_BCPB 24
-#define TIMER_CMR_BCPC 26
-#define TIMER_CMR_BEEVT 28
-#define TIMER_CMR_BSWTRG 30
-#define TIMER_CMR_BURST 4
-#define TIMER_CMR_CLKI 3
-#define TIMER_CMR_CPCDIS 7
-#define TIMER_CMR_CPCSTOP 6
-#define TIMER_CMR_CPCTRG 14
-#define TIMER_CMR_EEVT 10
-#define TIMER_CMR_EEVTEDG 8
-#define TIMER_CMR_ENETRG 12
-#define TIMER_CMR_ETRGEDG 8
-#define TIMER_CMR_LDBDIS 7
-#define TIMER_CMR_LDBSTOP 6
-#define TIMER_CMR_LDRA 16
-#define TIMER_CMR_LDRB 18
-#define TIMER_CMR_TCCLKS 0
-#define TIMER_CMR_WAVE 15
-#define TIMER_CMR_WAVSEL 13
-#define TIMER_CV 0x00000010
-#define TIMER_CV_CV 0
-#define TIMER_IDR 0x00000028
-#define TIMER_IDR_COVFS 0
-#define TIMER_IDR_CPAS 2
-#define TIMER_IDR_CPBS 3
-#define TIMER_IDR_CPCS 4
-#define TIMER_IDR_ETRGS 7
-#define TIMER_IDR_LDRAS 5
-#define TIMER_IDR_LDRBS 6
-#define TIMER_IDR_LOVRS 1
-#define TIMER_IER 0x00000024
-#define TIMER_IER_COVFS 0
-#define TIMER_IER_CPAS 2
-#define TIMER_IER_CPBS 3
-#define TIMER_IER_CPCS 4
-#define TIMER_IER_ETRGS 7
-#define TIMER_IER_LDRAS 5
-#define TIMER_IER_LDRBS 6
-#define TIMER_IER_LOVRS 1
-#define TIMER_IMR 0x0000002c
-#define TIMER_IMR_COVFS 0
-#define TIMER_IMR_CPAS 2
-#define TIMER_IMR_CPBS 3
-#define TIMER_IMR_CPCS 4
-#define TIMER_IMR_ETRGS 7
-#define TIMER_IMR_LDRAS 5
-#define TIMER_IMR_LDRBS 6
-#define TIMER_IMR_LOVRS 1
-#define TIMER_RA 0x00000014
-#define TIMER_RA_RA 0
-#define TIMER_RB 0x00000018
-#define TIMER_RB_RB 0
-#define TIMER_RC 0x0000001c
-#define TIMER_RC_RC 0
-#define TIMER_SR 0x00000020
-#define TIMER_SR_CLKSTA 16
-#define TIMER_SR_COVFS 0
-#define TIMER_SR_CPAS 2
-#define TIMER_SR_CPBS 3
-#define TIMER_SR_CPCS 4
-#define TIMER_SR_ETRGS 7
-#define TIMER_SR_LDRAS 5
-#define TIMER_SR_LDRBS 6
-#define TIMER_SR_LOVRS 1
-#define TIMER_SR_MTIOA 17
-#define TIMER_SR_MTIOB 18
-
-/* Bit manipulation macros */
-#define TIMER_BIT(name) (1 << TIMER_##name)
-#define TIMER_BF(name,value) ((value) << TIMER_##name)
-
-/* Register access macros */
-#define timer_read(port,instance,reg) \
- __raw_readl(port + (0x40 * instance) + TIMER_##reg)
-#define timer_write(port,instance,reg,value) \
- __raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
-
-#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
#include <asm/asm-offsets.h>
#include <asm/thread_info.h>
-#define mask_interrupts ssrf SR_GM_BIT
-#define mask_exceptions ssrf SR_EM_BIT
-#define unmask_interrupts csrf SR_GM_BIT
-#define unmask_exceptions csrf SR_EM_BIT
+#define mask_interrupts ssrf SYSREG_GM_OFFSET
+#define mask_exceptions ssrf SYSREG_EM_OFFSET
+#define unmask_interrupts csrf SYSREG_GM_OFFSET
+#define unmask_exceptions csrf SYSREG_EM_OFFSET
#ifdef CONFIG_FRAME_POINTER
.macro save_fp
+++ /dev/null
-#ifndef __ASM_AVR32_INTC_H
-#define __ASM_AVR32_INTC_H
-
-#include <linux/sysdev.h>
-#include <linux/interrupt.h>
-
-struct irq_controller;
-struct irqaction;
-struct pt_regs;
-
-struct platform_device;
-
-/* Information about the internal interrupt controller */
-struct intc_device {
- /* ioremapped address of configuration block */
- void __iomem *regs;
-
- /* the physical device */
- struct platform_device *pdev;
-
- /* Number of interrupt lines per group. */
- unsigned int irqs_per_group;
-
- /* The highest group ID + 1 */
- unsigned int nr_groups;
-
- /*
- * Bitfield indicating which groups are actually in use. The
- * size of the array is
- * ceil(group_max / (8 * sizeof(unsigned int))).
- */
- unsigned int group_mask[];
-};
-
-struct irq_controller_class {
- /*
- * A short name identifying this kind of controller.
- */
- const char *typename;
- /*
- * Handle the IRQ. Must do any necessary acking and masking.
- */
- irqreturn_t (*handle)(int irq, void *dev_id, struct pt_regs *regs);
- /*
- * Register a new IRQ handler.
- */
- int (*setup)(struct irq_controller *ctrl, unsigned int irq,
- struct irqaction *action);
- /*
- * Unregister a IRQ handler.
- */
- void (*free)(struct irq_controller *ctrl, unsigned int irq,
- void *dev_id);
- /*
- * Mask the IRQ in the interrupt controller.
- */
- void (*mask)(struct irq_controller *ctrl, unsigned int irq);
- /*
- * Unmask the IRQ in the interrupt controller.
- */
- void (*unmask)(struct irq_controller *ctrl, unsigned int irq);
- /*
- * Set the type of the IRQ. See below for possible types.
- * Return -EINVAL if a given type is not supported
- */
- int (*set_type)(struct irq_controller *ctrl, unsigned int irq,
- unsigned int type);
- /*
- * Return the IRQ type currently set
- */
- unsigned int (*get_type)(struct irq_controller *ctrl, unsigned int irq);
-};
-
-struct irq_controller {
- struct irq_controller_class *class;
- unsigned int irq_group;
- unsigned int first_irq;
- unsigned int nr_irqs;
- struct list_head list;
-};
-
-struct intc_group_desc {
- struct irq_controller *ctrl;
- irqreturn_t (*handle)(int, void *, struct pt_regs *);
- unsigned long flags;
- void *dev_id;
- const char *devname;
-};
-
-/*
- * The internal interrupt controller. Defined in board/part-specific
- * devices.c.
- * TODO: Should probably be defined per-cpu.
- */
-extern struct intc_device intc;
-
-extern int request_internal_irq(unsigned int irq,
- irqreturn_t (*handler)(int, void *, struct pt_regs *),
- unsigned long irqflags,
- const char *devname, void *dev_id);
-extern void free_internal_irq(unsigned int irq);
-
-/* Only used by time_init() */
-extern int setup_internal_irq(unsigned int irq, struct intc_group_desc *desc);
-
-/*
- * Set interrupt priority for a given group. `group' can be found by
- * using irq_to_group(irq). Priority can be from 0 (lowest) to 3
- * (highest). Higher-priority interrupts will preempt lower-priority
- * interrupts (unless interrupts are masked globally).
- *
- * This function does not check for conflicts within a group.
- */
-extern int intc_set_priority(unsigned int group,
- unsigned int priority);
-
-/*
- * Returns a bitmask of pending interrupts in a group.
- */
-extern unsigned long intc_get_pending(unsigned int group);
-
-/*
- * Register a new external interrupt controller. Returns the first
- * external IRQ number that is assigned to the new controller.
- */
-extern int intc_register_controller(struct irq_controller *ctrl);
-
-#endif /* __ASM_AVR32_INTC_H */
#ifndef __ASSEMBLER__
int nmi_enable(void);
void nmi_disable(void);
+
+/*
+ * Returns a bitmask of pending interrupts in a group.
+ */
+extern unsigned long intc_get_pending(unsigned int group);
#endif
#endif /* __ASM_AVR32_IOCTLS_H */
#ifndef __ASM_AVR32_PAGE_H
#define __ASM_AVR32_PAGE_H
+#include <linux/const.h>
+
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
-#ifdef __ASSEMBLY__
-#define PAGE_SIZE (1 << PAGE_SHIFT)
-#else
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
-#endif
+#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
#define PTE_MASK PAGE_MASK
--- /dev/null
+#ifndef _ASM_SERIAL_H
+#define _ASM_SERIAL_H
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD (1843200 / 16)
+
+#endif /* _ASM_SERIAL_H */
--- /dev/null
+#ifndef _ASM_XOR_H
+#define _ASM_XOR_H
+
+#include <asm-generic/xor.h>
+
+#endif
#include <linux/slab.h>
#include <asm/irq.h>
#include <asm/signal.h>
-#include <asm/semaphore.h>
#include <linux/kernel.h>
#include <asm/mach/dma.h>
do { var = (value); barrier(); } while (0)
#endif
-#define HARD_RESET_NOW() \
-do { \
- cli(); \
-} while(1)
-
extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2)));
extern void free_initmem(void);
#error NUMA not supported yet
-#else /* !CONFIG_NUMA */
+#endif /* CONFIG_NUMA */
#include <asm-generic/topology.h>
-#endif /* CONFIG_NUMA */
-
#endif /* _ASM_TOPOLOGY_H */
#ifndef _ASM_GENERIC_TOPOLOGY_H
#define _ASM_GENERIC_TOPOLOGY_H
+#ifndef CONFIG_NUMA
+
/* Other architectures wishing to use this simple topology API should fill
in the below functions as appropriate in their own <asm/topology.h> file. */
#ifndef cpu_to_node
)
#endif
+#endif /* CONFIG_NUMA */
+
+/* returns pointer to cpumask for specified node */
+#ifndef node_to_cpumask_ptr
+
+#define node_to_cpumask_ptr(v, node) \
+ cpumask_t _##v = node_to_cpumask(node), *v = &_##v
+
+#define node_to_cpumask_ptr_next(v, node) \
+ _##v = node_to_cpumask(node)
+#endif
+
#endif /* _ASM_GENERIC_TOPOLOGY_H */
struct ia64_mca_notify_die {
struct ia64_sal_os_state *sos;
int *monarch_cpu;
+ int *data;
};
DECLARE_PER_CPU(u64, ia64_mca_pal_base);
#define _ASM_IA64_SN_NODEPDA_H
-#include <asm/semaphore.h>
#include <asm/irq.h>
#include <asm/sn/arch.h>
#include <asm/sn/intr.h>
.cache_nice_tries = 2, \
.busy_idx = 3, \
.idle_idx = 2, \
- .newidle_idx = 0, /* unused */ \
+ .newidle_idx = 2, \
.wake_idx = 1, \
.forkexec_idx = 1, \
.flags = SD_LOAD_BALANCE \
#define smt_capable() (smp_num_siblings > 1)
#endif
+#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
+ CPU_MASK_ALL : \
+ node_to_cpumask(pcibus_to_node(bus)) \
+ )
+
#include <asm-generic/topology.h>
#endif /* _ASM_IA64_TOPOLOGY_H */
include include/asm-generic/Kbuild.asm
+header-y += a.out.h
header-y += auxvec.h
header-y += ioctls.h
header-y += mman.h
header-y += statfs.h
header-y += ps3fb.h
-unifdef-y += a.out.h
unifdef-y += asm-compat.h
unifdef-y += bootx.h
unifdef-y += byteorder.h
* 2 of the License, or (at your option) any later version.
*/
+#include <linux/lmb.h>
+
#include <asm/types.h>
#include <asm/page.h>
#include <asm/prom.h>
-#include <asm/lmb.h>
#include <asm/firmware.h>
struct mschunks_map {
asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
return 32 - lz;
}
+
+/*
+ * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
+ * instruction; for 32-bit we use the generic version, which does two
+ * 32-bit fls calls.
+ */
+#ifdef __powerpc64__
+static __inline__ int fls64(__u64 x)
+{
+ int lz;
+
+ asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
+ return 64 - lz;
+}
+#else
#include <asm-generic/bitops/fls64.h>
+#endif /* __powerpc64__ */
#include <asm-generic/bitops/hweight.h>
-
-#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
-unsigned long find_next_zero_bit(const unsigned long *addr,
- unsigned long size, unsigned long offset);
-/**
- * find_first_bit - find the first set bit in a memory region
- * @addr: The address to start the search at
- * @size: The maximum size to search
- *
- * Returns the bit-number of the first set bit, not the number of the byte
- * containing a bit.
- */
-#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
-unsigned long find_next_bit(const unsigned long *addr,
- unsigned long size, unsigned long offset);
+#include <asm-generic/bitops/find.h>
/* Little-endian versions */
#include <linux/compiler.h>
#include <linux/types.h>
+/* Opcodes common to CPM1 and CPM2
+*/
+#define CPM_CR_INIT_TRX ((ushort)0x0000)
+#define CPM_CR_INIT_RX ((ushort)0x0001)
+#define CPM_CR_INIT_TX ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE ((ushort)0x0003)
+#define CPM_CR_STOP_TX ((ushort)0x0004)
+#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
+#define CPM_CR_RESTART_TX ((ushort)0x0006)
+#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
+#define CPM_CR_SET_GADDR ((ushort)0x0008)
+#define CPM_CR_SET_TIMER ((ushort)0x0008)
+#define CPM_CR_STOP_IDMA ((ushort)0x000b)
+
/* Buffer descriptors used by many of the CPM protocols. */
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
#define CPM_CR_CHAN ((ushort)0x00f0)
#define CPM_CR_FLG ((ushort)0x0001)
-/* Some commands (there are more...later)
-*/
-#define CPM_CR_INIT_TRX ((ushort)0x0000)
-#define CPM_CR_INIT_RX ((ushort)0x0001)
-#define CPM_CR_INIT_TX ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE ((ushort)0x0003)
-#define CPM_CR_STOP_TX ((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
-#define CPM_CR_RESTART_TX ((ushort)0x0006)
-#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
-#define CPM_CR_SET_GADDR ((ushort)0x0008)
-#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR
-
/* Channel numbers.
*/
#define CPM_CR_CH_SCC1 ((ushort)0x0000)
#define CPM_CR_FCC_PAGE(x) (x + 0x04)
-/* Some opcodes (there are more...later)
+/* CPM2-specific opcodes (see cpm.h for common opcodes)
*/
-#define CPM_CR_INIT_TRX ((ushort)0x0000)
-#define CPM_CR_INIT_RX ((ushort)0x0001)
-#define CPM_CR_INIT_TX ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE ((ushort)0x0003)
-#define CPM_CR_STOP_TX ((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
-#define CPM_CR_RESTART_TX ((ushort)0x0006)
-#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_START_IDMA ((ushort)0x0009)
-#define CPM_CR_STOP_IDMA ((ushort)0x000b)
#define mk_cr_cmd(PG, SBC, MCN, OP) \
((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
res = CPU_MASK_NONE;
for (i = 0; i < NR_CPUS; i += threads_per_core) {
- cpus_shift_right(tmp, threads_core_mask, i);
+ cpus_shift_left(tmp, threads_core_mask, i);
if (cpus_intersects(threads, tmp))
cpu_set(i, res);
}
spin_unlock_irqrestore(&dcr_ind_lock, flags);
}
+static inline void __dcri_clrset(int base_addr, int base_data, int reg,
+ unsigned clr, unsigned set)
+{
+ unsigned long flags;
+ unsigned int val;
+
+ spin_lock_irqsave(&dcr_ind_lock, flags);
+ __mtdcr(base_addr, reg);
+ val = (__mfdcr(base_data) & ~clr) | set;
+ __mtdcr(base_data, val);
+ spin_unlock_irqrestore(&dcr_ind_lock, flags);
+}
+
#define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
DCRN_ ## base ## _CONFIG_DATA, \
reg)
DCRN_ ## base ## _CONFIG_DATA, \
reg, data)
+#define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \
+ DCRN_ ## base ## _CONFIG_DATA, \
+ reg, clr, set)
+
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_DCR_NATIVE_H */
#define SDR0_UART3 0x0123
#define SDR0_CUST0 0x4000
+/*
+ * All those DCR register addresses are offsets from the base address
+ * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
+ * excluded here and configured in the device tree.
+ */
+#define DCRN_SRAM0_SB0CR 0x00
+#define DCRN_SRAM0_SB1CR 0x01
+#define DCRN_SRAM0_SB2CR 0x02
+#define DCRN_SRAM0_SB3CR 0x03
+#define SRAM_SBCR_BU_MASK 0x00000180
+#define SRAM_SBCR_BS_64KB 0x00000800
+#define SRAM_SBCR_BU_RO 0x00000080
+#define SRAM_SBCR_BU_RW 0x00000180
+#define DCRN_SRAM0_BEAR 0x04
+#define DCRN_SRAM0_BESR0 0x05
+#define DCRN_SRAM0_BESR1 0x06
+#define DCRN_SRAM0_PMEG 0x07
+#define DCRN_SRAM0_CID 0x08
+#define DCRN_SRAM0_REVID 0x09
+#define DCRN_SRAM0_DPC 0x0a
+#define SRAM_DPC_ENABLE 0x80000000
+
+/*
+ * All those DCR register addresses are offsets from the base address
+ * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
+ * excluded here and configured in the device tree.
+ */
+#define DCRN_L2C0_CFG 0x00
+#define L2C_CFG_L2M 0x80000000
+#define L2C_CFG_ICU 0x40000000
+#define L2C_CFG_DCU 0x20000000
+#define L2C_CFG_DCW_MASK 0x1e000000
+#define L2C_CFG_TPC 0x01000000
+#define L2C_CFG_CPC 0x00800000
+#define L2C_CFG_FRAN 0x00200000
+#define L2C_CFG_SS_MASK 0x00180000
+#define L2C_CFG_SS_256 0x00000000
+#define L2C_CFG_CPIM 0x00040000
+#define L2C_CFG_TPIM 0x00020000
+#define L2C_CFG_LIM 0x00010000
+#define L2C_CFG_PMUX_MASK 0x00007000
+#define L2C_CFG_PMUX_SNP 0x00000000
+#define L2C_CFG_PMUX_IF 0x00001000
+#define L2C_CFG_PMUX_DF 0x00002000
+#define L2C_CFG_PMUX_DS 0x00003000
+#define L2C_CFG_PMIM 0x00000800
+#define L2C_CFG_TPEI 0x00000400
+#define L2C_CFG_CPEI 0x00000200
+#define L2C_CFG_NAM 0x00000100
+#define L2C_CFG_SMCM 0x00000080
+#define L2C_CFG_NBRM 0x00000040
+#define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */
+#define DCRN_L2C0_CMD 0x01
+#define L2C_CMD_CLR 0x80000000
+#define L2C_CMD_DIAG 0x40000000
+#define L2C_CMD_INV 0x20000000
+#define L2C_CMD_CCP 0x10000000
+#define L2C_CMD_CTE 0x08000000
+#define L2C_CMD_STRC 0x04000000
+#define L2C_CMD_STPC 0x02000000
+#define L2C_CMD_RPMC 0x01000000
+#define L2C_CMD_HCC 0x00800000
+#define DCRN_L2C0_ADDR 0x02
+#define DCRN_L2C0_DATA 0x03
+#define DCRN_L2C0_SR 0x04
+#define L2C_SR_CC 0x80000000
+#define L2C_SR_CPE 0x40000000
+#define L2C_SR_TPE 0x20000000
+#define L2C_SR_LRU 0x10000000
+#define L2C_SR_PCS 0x08000000
+#define DCRN_L2C0_REVID 0x05
+#define DCRN_L2C0_SNP0 0x06
+#define DCRN_L2C0_SNP1 0x07
+#define L2C_SNP_BA_MASK 0xffff0000
+#define L2C_SNP_SSR_MASK 0x0000f000
+#define L2C_SNP_SSR_32G 0x0000f000
+#define L2C_SNP_ESR 0x00000800
+
#endif /* __DCR_REGS_H__ */
BEGIN_FW_FTR_SECTION; \
stb r11,PACAHARDIRQEN(r13); \
END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
+ TRACE_DISABLE_INTS; \
BEGIN_FW_FTR_SECTION; \
mfmsr r10; \
ori r10,r10,MSR_EE; \
mtmsrd r10,1; \
END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-
#else
#define DISABLE_INTS \
li r11,0; \
stb r11,PACASOFTIRQEN(r13); \
- stb r11,PACAHARDIRQEN(r13)
-
+ stb r11,PACAHARDIRQEN(r13); \
+ TRACE_DISABLE_INTS
#endif /* CONFIG_PPC_ISERIES */
#define ENABLE_INTS \
--- /dev/null
+/* Freescale Local Bus Controller
+ *
+ * Copyright (c) 2006-2007 Freescale Semiconductor
+ *
+ * Authors: Nick Spence <nick.spence@freescale.com>,
+ * Scott Wood <scottwood@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_FSL_LBC_H
+#define __ASM_FSL_LBC_H
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+
+struct fsl_lbc_bank {
+ __be32 br; /**< Base Register */
+#define BR_BA 0xFFFF8000
+#define BR_BA_SHIFT 15
+#define BR_PS 0x00001800
+#define BR_PS_SHIFT 11
+#define BR_PS_8 0x00000800 /* Port Size 8 bit */
+#define BR_PS_16 0x00001000 /* Port Size 16 bit */
+#define BR_PS_32 0x00001800 /* Port Size 32 bit */
+#define BR_DECC 0x00000600
+#define BR_DECC_SHIFT 9
+#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
+#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
+#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
+#define BR_WP 0x00000100
+#define BR_WP_SHIFT 8
+#define BR_MSEL 0x000000E0
+#define BR_MSEL_SHIFT 5
+#define BR_MS_GPCM 0x00000000 /* GPCM */
+#define BR_MS_FCM 0x00000020 /* FCM */
+#define BR_MS_SDRAM 0x00000060 /* SDRAM */
+#define BR_MS_UPMA 0x00000080 /* UPMA */
+#define BR_MS_UPMB 0x000000A0 /* UPMB */
+#define BR_MS_UPMC 0x000000C0 /* UPMC */
+#define BR_V 0x00000001
+#define BR_V_SHIFT 0
+#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+
+ __be32 or; /**< Base Register */
+#define OR0 0x5004
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_FCM_AM 0xFFFF8000
+#define OR_FCM_AM_SHIFT 15
+#define OR_FCM_BCTLD 0x00001000
+#define OR_FCM_BCTLD_SHIFT 12
+#define OR_FCM_PGS 0x00000400
+#define OR_FCM_PGS_SHIFT 10
+#define OR_FCM_CSCT 0x00000200
+#define OR_FCM_CSCT_SHIFT 9
+#define OR_FCM_CST 0x00000100
+#define OR_FCM_CST_SHIFT 8
+#define OR_FCM_CHT 0x00000080
+#define OR_FCM_CHT_SHIFT 7
+#define OR_FCM_SCY 0x00000070
+#define OR_FCM_SCY_SHIFT 4
+#define OR_FCM_SCY_1 0x00000010
+#define OR_FCM_SCY_2 0x00000020
+#define OR_FCM_SCY_3 0x00000030
+#define OR_FCM_SCY_4 0x00000040
+#define OR_FCM_SCY_5 0x00000050
+#define OR_FCM_SCY_6 0x00000060
+#define OR_FCM_SCY_7 0x00000070
+#define OR_FCM_RST 0x00000008
+#define OR_FCM_RST_SHIFT 3
+#define OR_FCM_TRLX 0x00000004
+#define OR_FCM_TRLX_SHIFT 2
+#define OR_FCM_EHTR 0x00000002
+#define OR_FCM_EHTR_SHIFT 1
+};
+
+struct fsl_lbc_regs {
+ struct fsl_lbc_bank bank[8];
+ u8 res0[0x28];
+ __be32 mar; /**< UPM Address Register */
+ u8 res1[0x4];
+ __be32 mamr; /**< UPMA Mode Register */
+#define MxMR_OP_NO (0 << 28) /**< normal operation */
+#define MxMR_OP_WA (1 << 28) /**< write array */
+#define MxMR_OP_RA (2 << 28) /**< read array */
+#define MxMR_OP_RP (3 << 28) /**< run pattern */
+#define MxMR_MAD 0x3f /**< machine address */
+ __be32 mbmr; /**< UPMB Mode Register */
+ __be32 mcmr; /**< UPMC Mode Register */
+ u8 res2[0x8];
+ __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
+ __be32 mdr; /**< UPM Data Register */
+ u8 res3[0x4];
+ __be32 lsor; /**< Special Operation Initiation Register */
+ __be32 lsdmr; /**< SDRAM Mode Register */
+ u8 res4[0x8];
+ __be32 lurt; /**< UPM Refresh Timer */
+ __be32 lsrt; /**< SDRAM Refresh Timer */
+ u8 res5[0x8];
+ __be32 ltesr; /**< Transfer Error Status Register */
+#define LTESR_BM 0x80000000
+#define LTESR_FCT 0x40000000
+#define LTESR_PAR 0x20000000
+#define LTESR_WP 0x04000000
+#define LTESR_ATMW 0x00800000
+#define LTESR_ATMR 0x00400000
+#define LTESR_CS 0x00080000
+#define LTESR_CC 0x00000001
+#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+ __be32 ltedr; /**< Transfer Error Disable Register */
+ __be32 lteir; /**< Transfer Error Interrupt Register */
+ __be32 lteatr; /**< Transfer Error Attributes Register */
+ __be32 ltear; /**< Transfer Error Address Register */
+ u8 res6[0xC];
+ __be32 lbcr; /**< Configuration Register */
+#define LBCR_LDIS 0x80000000
+#define LBCR_LDIS_SHIFT 31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT 22
+#define LBCR_AHD 0x00200000
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT 17
+#define LBCR_EPAR 0x00010000
+#define LBCR_EPAR_SHIFT 16
+#define LBCR_BMT 0x0000FF00
+#define LBCR_BMT_SHIFT 8
+#define LBCR_INIT 0x00040000
+ __be32 lcrr; /**< Clock Ratio Register */
+#define LCRR_DBYP 0x80000000
+#define LCRR_DBYP_SHIFT 31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT 28
+#define LCRR_ECL 0x03000000
+#define LCRR_ECL_SHIFT 24
+#define LCRR_EADC 0x00030000
+#define LCRR_EADC_SHIFT 16
+#define LCRR_CLKDIV 0x0000000F
+#define LCRR_CLKDIV_SHIFT 0
+ u8 res7[0x8];
+ __be32 fmr; /**< Flash Mode Register */
+#define FMR_CWTO 0x0000F000
+#define FMR_CWTO_SHIFT 12
+#define FMR_BOOT 0x00000800
+#define FMR_ECCM 0x00000100
+#define FMR_AL 0x00000030
+#define FMR_AL_SHIFT 4
+#define FMR_OP 0x00000003
+#define FMR_OP_SHIFT 0
+ __be32 fir; /**< Flash Instruction Register */
+#define FIR_OP0 0xF0000000
+#define FIR_OP0_SHIFT 28
+#define FIR_OP1 0x0F000000
+#define FIR_OP1_SHIFT 24
+#define FIR_OP2 0x00F00000
+#define FIR_OP2_SHIFT 20
+#define FIR_OP3 0x000F0000
+#define FIR_OP3_SHIFT 16
+#define FIR_OP4 0x0000F000
+#define FIR_OP4_SHIFT 12
+#define FIR_OP5 0x00000F00
+#define FIR_OP5_SHIFT 8
+#define FIR_OP6 0x000000F0
+#define FIR_OP6_SHIFT 4
+#define FIR_OP7 0x0000000F
+#define FIR_OP7_SHIFT 0
+#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
+#define FIR_OP_CA 0x1 /* Issue current column address */
+#define FIR_OP_PA 0x2 /* Issue current block+page address */
+#define FIR_OP_UA 0x3 /* Issue user defined address */
+#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
+ __be32 fcr; /**< Flash Command Register */
+#define FCR_CMD0 0xFF000000
+#define FCR_CMD0_SHIFT 24
+#define FCR_CMD1 0x00FF0000
+#define FCR_CMD1_SHIFT 16
+#define FCR_CMD2 0x0000FF00
+#define FCR_CMD2_SHIFT 8
+#define FCR_CMD3 0x000000FF
+#define FCR_CMD3_SHIFT 0
+ __be32 fbar; /**< Flash Block Address Register */
+#define FBAR_BLK 0x00FFFFFF
+ __be32 fpar; /**< Flash Page Address Register */
+#define FPAR_SP_PI 0x00007C00
+#define FPAR_SP_PI_SHIFT 10
+#define FPAR_SP_MS 0x00000200
+#define FPAR_SP_CI 0x000001FF
+#define FPAR_SP_CI_SHIFT 0
+#define FPAR_LP_PI 0x0003F000
+#define FPAR_LP_PI_SHIFT 12
+#define FPAR_LP_MS 0x00000800
+#define FPAR_LP_CI 0x000007FF
+#define FPAR_LP_CI_SHIFT 0
+ __be32 fbcr; /**< Flash Byte Count Register */
+#define FBCR_BC 0x00000FFF
+ u8 res11[0x8];
+ u8 res8[0xF00];
+};
+
+extern struct fsl_lbc_regs __iomem *fsl_lbc_regs;
+extern spinlock_t fsl_lbc_lock;
+
+/*
+ * FSL UPM routines
+ */
+struct fsl_upm {
+ __be32 __iomem *mxmr;
+ int width;
+};
+
+extern int fsl_lbc_find(phys_addr_t addr_base);
+extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
+
+/**
+ * fsl_upm_start_pattern - start UPM patterns execution
+ * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
+ * @pat_offset: UPM pattern offset for the command to be executed
+ *
+ * This routine programmes UPM so the next memory access that hits an UPM
+ * will trigger pattern execution, starting at pat_offset.
+ */
+static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
+{
+ clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
+}
+
+/**
+ * fsl_upm_end_pattern - end UPM patterns execution
+ * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
+ *
+ * This routine reverts UPM to normal operation mode.
+ */
+static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
+{
+ clrbits32(upm->mxmr, MxMR_OP_RP);
+
+ while (in_be32(upm->mxmr) & MxMR_OP_RP)
+ cpu_relax();
+}
+
+/**
+ * fsl_upm_run_pattern - actually run an UPM pattern
+ * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
+ * @io_base: remapped pointer to where memory access should happen
+ * @mar: MAR register content during pattern execution
+ *
+ * This function triggers dummy write to the memory specified by the io_base,
+ * thus UPM pattern actually executed. Note that mar usage depends on the
+ * pre-programmed AMX bits in the UPM RAM.
+ */
+static inline int fsl_upm_run_pattern(struct fsl_upm *upm,
+ void __iomem *io_base, u32 mar)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&fsl_lbc_lock, flags);
+
+ out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width));
+
+ switch (upm->width) {
+ case 8:
+ out_8(io_base, 0x0);
+ break;
+ case 16:
+ out_be16(io_base, 0x0);
+ break;
+ case 32:
+ out_be32(io_base, 0x0);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ spin_unlock_irqrestore(&fsl_lbc_lock, flags);
+
+ return ret;
+}
+
+#endif /* __ASM_FSL_LBC_H */
--- /dev/null
+/*
+ * Generic GPIO API implementation for PowerPC.
+ *
+ * Copyright (c) 2007-2008 MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_POWERPC_GPIO_H
+#define __ASM_POWERPC_GPIO_H
+
+#include <linux/errno.h>
+#include <asm-generic/gpio.h>
+
+#ifdef CONFIG_HAVE_GPIO_LIB
+
+/*
+ * We don't (yet) implement inlined/rapid versions for on-chip gpios.
+ * Just call gpiolib.
+ */
+static inline int gpio_get_value(unsigned int gpio)
+{
+ return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+ __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+ return __gpio_cansleep(gpio);
+}
+
+/*
+ * Not implemented, yet.
+ */
+static inline int gpio_to_irq(unsigned int gpio)
+{
+ return -ENOSYS;
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+ return -EINVAL;
+}
+
+#endif /* CONFIG_HAVE_GPIO_LIB */
+
+#endif /* __ASM_POWERPC_GPIO_H */
return flags;
}
-static inline unsigned long local_irq_disable(void)
+static inline unsigned long raw_local_irq_disable(void)
{
unsigned long flags, zero;
return flags;
}
-extern void local_irq_restore(unsigned long);
+extern void raw_local_irq_restore(unsigned long);
extern void iseries_handle_interrupts(void);
-#define local_irq_enable() local_irq_restore(1)
-#define local_save_flags(flags) ((flags) = local_get_flags())
-#define local_irq_save(flags) ((flags) = local_irq_disable())
+#define raw_local_irq_enable() raw_local_irq_restore(1)
+#define raw_local_save_flags(flags) ((flags) = local_get_flags())
+#define raw_local_irq_save(flags) ((flags) = raw_local_irq_disable())
-#define irqs_disabled() (local_get_flags() == 0)
+#define raw_irqs_disabled() (local_get_flags() == 0)
+#define raw_irqs_disabled_flags(flags) ((flags) == 0)
#define __hard_irq_enable() __mtmsrd(mfmsr() | MSR_EE, 1)
#define __hard_irq_disable() __mtmsrd(mfmsr() & ~MSR_EE, 1)
#ifdef __KERNEL__
#include <linux/kernel.h>
+#include <asm/io.h>
#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
} __attribute__ ((packed));
-extern struct qe_immap *qe_immr;
+extern struct qe_immap __iomem *qe_immr;
extern phys_addr_t get_qe_base(void);
static inline unsigned long immrbar_virt_to_phys(void *address)
* include/asm-powerpc/irqflags.h
*
* IRQ flags handling
- *
- * This file gets included from lowlevel asm headers too, to provide
- * wrapped versions of the local_irq_*() APIs, based on the
- * raw_local_irq_*() macros from the lowlevel headers.
*/
#ifndef _ASM_IRQFLAGS_H
#define _ASM_IRQFLAGS_H
+#ifndef __ASSEMBLY__
/*
* Get definitions for raw_local_save_flags(x), etc.
*/
#include <asm-powerpc/hw_irq.h>
+#else
+#ifdef CONFIG_TRACE_IRQFLAGS
/*
- * Do the CPU's IRQ-state tracing from assembly code. We call a
- * C function, so save all the C-clobbered registers:
+ * Most of the CPU's IRQ-state tracing is done from assembly code; we
+ * have to call a C function so call a wrapper that saves all the
+ * C-clobbered registers.
*/
-#ifdef CONFIG_TRACE_IRQFLAGS
-
-#error No support on PowerPC yet for CONFIG_TRACE_IRQFLAGS
-
+#define TRACE_ENABLE_INTS bl .trace_hardirqs_on
+#define TRACE_DISABLE_INTS bl .trace_hardirqs_off
+#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip) \
+ cmpdi en, 0; \
+ bne 95f; \
+ stb en,PACASOFTIRQEN(r13); \
+ bl .trace_hardirqs_off; \
+ b skip; \
+95: bl .trace_hardirqs_on; \
+ li en,1;
+#define TRACE_AND_RESTORE_IRQ(en) \
+ TRACE_AND_RESTORE_IRQ_PARTIAL(en,96f); \
+96: stb en,PACASOFTIRQEN(r13)
#else
-# define TRACE_IRQS_ON
-# define TRACE_IRQS_OFF
+#define TRACE_ENABLE_INTS
+#define TRACE_DISABLE_INTS
+#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)
+#define TRACE_AND_RESTORE_IRQ(en) \
+ stb en,PACASOFTIRQEN(r13)
+#endif
#endif
#endif
--- /dev/null
+/*
+ * Copyright © 2008 Stephen Rothwell IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_ISERIES_ALPACA_H
+#define _ASM_POWERPC_ISERIES_ALPACA_H
+
+/*
+ * This is the part of the paca that the iSeries hypervisor
+ * needs to be statically initialised. Immediately after boot
+ * we switch to the normal Linux paca.
+ */
+struct alpaca {
+ struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
+ const void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
+};
+
+#endif /* _ASM_POWERPC_ISERIES_ALPACA_H */
+++ /dev/null
-/*
- * Copyright (C) 2001 Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H
-#define _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H
-
-/*
- * This control block contains the data that is shared between PLIC
- * and the OS
- */
-
-struct ItLpRegSave {
- u32 xDesc; // Eye catcher "LpRS" ebcdic 000-003
- u16 xSize; // Size of this class 004-005
- u8 xInUse; // Area is live 006-007
- u8 xRsvd1[9]; // Reserved 007-00F
-
- u8 xFixedRegSave[352]; // Fixed Register Save Area 010-16F
- u32 xCTRL; // Control Register 170-173
- u32 xDEC; // Decrementer 174-177
- u32 xFPSCR; // FP Status and Control Reg 178-17B
- u32 xPVR; // Processor Version Number 17C-17F
-
- u64 xMMCR0; // Monitor Mode Control Reg 0 180-187
- u32 xPMC1; // Perf Monitor Counter 1 188-18B
- u32 xPMC2; // Perf Monitor Counter 2 18C-18F
- u32 xPMC3; // Perf Monitor Counter 3 190-193
- u32 xPMC4; // Perf Monitor Counter 4 194-197
- u32 xPIR; // Processor ID Reg 198-19B
-
- u32 xMMCR1; // Monitor Mode Control Reg 1 19C-19F
- u32 xMMCRA; // Monitor Mode Control Reg A 1A0-1A3
- u32 xPMC5; // Perf Monitor Counter 5 1A4-1A7
- u32 xPMC6; // Perf Monitor Counter 6 1A8-1AB
- u32 xPMC7; // Perf Monitor Counter 7 1AC-1AF
- u32 xPMC8; // Perf Monitor Counter 8 1B0-1B3
- u32 xTSC; // Thread Switch Control 1B4-1B7
- u32 xTST; // Thread Switch Timeout 1B8-1BB
- u32 xRsvd; // Reserved 1BC-1BF
-
- u64 xACCR; // Address Compare Control Reg 1C0-1C7
- u64 xIMR; // Instruction Match Register 1C8-1CF
- u64 xSDR1; // Storage Description Reg 1 1D0-1D7
- u64 xSPRG0; // Special Purpose Reg General0 1D8-1DF
- u64 xSPRG1; // Special Purpose Reg General1 1E0-1E7
- u64 xSPRG2; // Special Purpose Reg General2 1E8-1EF
- u64 xSPRG3; // Special Purpose Reg General3 1F0-1F7
- u64 xTB; // Time Base Register 1F8-1FF
-
- u64 xFPR[32]; // Floating Point Registers 200-2FF
-
- u64 xMSR; // Machine State Register 300-307
- u64 xNIA; // Next Instruction Address 308-30F
-
- u64 xDABR; // Data Address Breakpoint Reg 310-317
- u64 xIABR; // Inst Address Breakpoint Reg 318-31F
-
- u64 xHID0; // HW Implementation Dependent0 320-327
-
- u64 xHID4; // HW Implementation Dependent4 328-32F
- u64 xSCOMd; // SCON Data Reg (SPRG4) 330-337
- u64 xSCOMc; // SCON Command Reg (SPRG5) 338-33F
- u64 xSDAR; // Sample Data Address Register 340-347
- u64 xSIAR; // Sample Inst Address Register 348-34F
-
- u8 xRsvd3[176]; // Reserved 350-3FF
-};
-
-extern struct ItLpRegSave iseries_reg_save[];
-
-#endif /* _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H */
#ifndef _ASM_POWERPC_LMB_H
#define _ASM_POWERPC_LMB_H
-#ifdef __KERNEL__
-/*
- * Definitions for talking to the Open Firmware PROM on
- * Power Macintosh computers.
- *
- * Copyright (C) 2001 Peter Bergner, IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
+#include <asm/udbg.h>
-#include <linux/init.h>
-#include <asm/prom.h>
+#define LMB_DBG(fmt...) udbg_printf(fmt)
-#define MAX_LMB_REGIONS 128
+#ifdef CONFIG_PPC32
+extern phys_addr_t lowmem_end_addr;
+#define LMB_REAL_LIMIT lowmem_end_addr
+#else
+#define LMB_REAL_LIMIT 0
+#endif
-struct lmb_property {
- unsigned long base;
- unsigned long size;
-};
-
-struct lmb_region {
- unsigned long cnt;
- unsigned long size;
- struct lmb_property region[MAX_LMB_REGIONS+1];
-};
-
-struct lmb {
- unsigned long debug;
- unsigned long rmo_size;
- struct lmb_region memory;
- struct lmb_region reserved;
-};
-
-extern struct lmb lmb;
-
-extern void __init lmb_init(void);
-extern void __init lmb_analyze(void);
-extern long __init lmb_add(unsigned long base, unsigned long size);
-extern long __init lmb_reserve(unsigned long base, unsigned long size);
-extern unsigned long __init lmb_alloc(unsigned long size, unsigned long align);
-extern unsigned long __init lmb_alloc_base(unsigned long size,
- unsigned long align, unsigned long max_addr);
-extern unsigned long __init __lmb_alloc_base(unsigned long size,
- unsigned long align, unsigned long max_addr);
-extern unsigned long __init lmb_phys_mem_size(void);
-extern unsigned long __init lmb_end_of_DRAM(void);
-extern void __init lmb_enforce_memory_limit(unsigned long memory_limit);
-extern int __init lmb_is_reserved(unsigned long addr);
-
-extern void lmb_dump_all(void);
-
-static inline unsigned long
-lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
-{
- return type->region[region_nr].size;
-}
-static inline unsigned long
-lmb_size_pages(struct lmb_region *type, unsigned long region_nr)
-{
- return lmb_size_bytes(type, region_nr) >> PAGE_SHIFT;
-}
-static inline unsigned long
-lmb_start_pfn(struct lmb_region *type, unsigned long region_nr)
-{
- return type->region[region_nr].base >> PAGE_SHIFT;
-}
-static inline unsigned long
-lmb_end_pfn(struct lmb_region *type, unsigned long region_nr)
-{
- return lmb_start_pfn(type, region_nr) +
- lmb_size_pages(type, region_nr);
-}
-
-#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_LMB_H */
unsigned long vflags,
int psize, int ssize);
long (*hpte_remove)(unsigned long hpte_group);
+ void (*hpte_removebolted)(unsigned long ea,
+ int psize, int ssize);
void (*flush_hash_range)(unsigned long number, int local);
/* special for kexec, to be called in real mode, linar mapping is
May be NULL. */
void (*init)(void);
- void (*setup_io_mappings)(void);
-
- void (*early_serial_map)(void);
void (*kgdb_map_scc)(void);
/*
#define __MACIO_ASIC_H__
#ifdef __KERNEL__
-#include <asm/of_device.h>
+#include <linux/of_device.h>
extern struct bus_type macio_bus_type;
#ifndef __ASSEMBLY__
-typedef unsigned long phys_addr_t;
-
typedef struct {
unsigned long id;
unsigned long vdso_base;
#ifndef __ASSEMBLY__
-typedef unsigned long long phys_addr_t;
-
typedef struct {
unsigned long id;
unsigned long vdso_base;
#define SPRN_M_TW 799
#ifndef __ASSEMBLY__
-typedef unsigned long phys_addr_t;
-
typedef struct {
unsigned long id;
unsigned long vdso_base;
#ifndef __ASSEMBLY__
-#ifndef CONFIG_PHYS_64BIT
-typedef unsigned long phys_addr_t;
-#else
-typedef unsigned long long phys_addr_t;
-#endif
-
typedef struct {
unsigned long id;
unsigned long vdso_base;
unsigned long vdso_base;
} mm_context_t;
-typedef unsigned long phys_addr_t;
-
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_MMU_HASH32_H_ */
VSID_MODULUS_256M)
#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
-/* Physical address used by some IO functions */
-typedef unsigned long phys_addr_t;
-
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
* Defines the layout of the paca.
*
* This structure is not directly accessed by firmware or the service
- * processor except for the first two pointers that point to the
- * lppaca area and the ItLpRegSave area for this CPU. The lppaca
- * object is currently contained within the PACA but it doesn't need
- * to be.
+ * processor.
*/
struct paca_struct {
/*
* avoid cacheline bouncing.
*/
- /*
- * MAGIC: These first two pointers can't be moved - they're
- * accessed by the firmware
- */
struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
-#ifdef CONFIG_PPC_ISERIES
- void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
-#endif /* CONFIG_PPC_ISERIES */
/*
* MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
#define PAGE_OFFSET ASM_CONST(CONFIG_KERNEL_START)
#define KERNELBASE (PAGE_OFFSET + PHYSICAL_START)
+#define LOAD_OFFSET PAGE_OFFSET
#ifdef CONFIG_FLATMEM
#define pfn_valid(pfn) ((pfn) < max_mapnr)
#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
-#define PPC_MEMSTART 0
-
#ifdef CONFIG_NOT_COHERENT_CACHE
#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
#endif
/*
- * Copyright (C) 2006 PA Semi, Inc
+ * Copyright (C) 2006-2008 PA Semi, Inc
*
* Hardware register layout and descriptor formats for the on-board
* DMA engine on PA Semi PWRficient. Used by ethernet, function and security
PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
+ PAS_DMA_COM_CFG = 0x114, /* Common config reg */
+ PAS_DMA_TXF_SFLG0 = 0x140, /* Set flags */
+ PAS_DMA_TXF_SFLG1 = 0x144, /* Set flags */
+ PAS_DMA_TXF_CFLG0 = 0x148, /* Set flags */
+ PAS_DMA_TXF_CFLG1 = 0x14c, /* Set flags */
};
#define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100
#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
+#define PAS_DMA_TXCHAN_CFG_TY_COPY 0x00000001 /* Type = copy only */
+#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = function */
+#define PAS_DMA_TXCHAN_CFG_TY_XOR 0x00000003 /* Type = xor only */
#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
#define PAS_DMA_TXCHAN_CFG_TATTR_S 2
#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
PAS_DMA_TXCHAN_CFG_TATTR_M)
-#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0
+#define PAS_DMA_TXCHAN_CFG_LPDQ 0x00000800
+#define PAS_DMA_TXCHAN_CFG_LPSQ 0x00000400
+#define PAS_DMA_TXCHAN_CFG_WT_M 0x000003c0
#define PAS_DMA_TXCHAN_CFG_WT_S 6
#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
PAS_DMA_TXCHAN_CFG_WT_M)
XCT_COPY_LLEN_M)
#define XCT_COPY_SE 0x0000000000000001ull
+/* Function descriptor fields */
+#define XCT_FUN_T 0x8000000000000000ull
+#define XCT_FUN_ST 0x4000000000000000ull
+#define XCT_FUN_RR_M 0x3000000000000000ull
+#define XCT_FUN_RR_NORES 0x0000000000000000ull
+#define XCT_FUN_RR_8BRES 0x1000000000000000ull
+#define XCT_FUN_RR_24BRES 0x2000000000000000ull
+#define XCT_FUN_RR_40BRES 0x3000000000000000ull
+#define XCT_FUN_I 0x0800000000000000ull
+#define XCT_FUN_O 0x0400000000000000ull
+#define XCT_FUN_E 0x0200000000000000ull
+#define XCT_FUN_FUN_M 0x01c0000000000000ull
+#define XCT_FUN_FUN_S 54
+#define XCT_FUN_FUN(x) ((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M)
+#define XCT_FUN_CRM_M 0x0038000000000000ull
+#define XCT_FUN_CRM_NOP 0x0000000000000000ull
+#define XCT_FUN_CRM_SIG 0x0008000000000000ull
+#define XCT_FUN_LLEN_M 0x0007ffff00000000ull
+#define XCT_FUN_LLEN_S 32
+#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M)
+#define XCT_FUN_SHL_M 0x00000000f8000000ull
+#define XCT_FUN_SHL_S 27
+#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M)
+#define XCT_FUN_CHL_M 0x0000000007c00000ull
+#define XCT_FUN_HSZ_M 0x00000000003c0000ull
+#define XCT_FUN_ALG_M 0x0000000000038000ull
+#define XCT_FUN_HP 0x0000000000004000ull
+#define XCT_FUN_BCM_M 0x0000000000003800ull
+#define XCT_FUN_BCP_M 0x0000000000000600ull
+#define XCT_FUN_SIG_M 0x00000000000001f0ull
+#define XCT_FUN_SIG_TCP4 0x0000000000000140ull
+#define XCT_FUN_SIG_TCP6 0x0000000000000150ull
+#define XCT_FUN_SIG_UDP4 0x0000000000000160ull
+#define XCT_FUN_SIG_UDP6 0x0000000000000170ull
+#define XCT_FUN_A 0x0000000000000008ull
+#define XCT_FUN_C 0x0000000000000004ull
+#define XCT_FUN_AL2 0x0000000000000002ull
+#define XCT_FUN_SE 0x0000000000000001ull
+
+/* Function descriptor 8byte result fields */
+#define XCT_FUNRES_8B_CS_M 0x0000ffff00000000ull
+#define XCT_FUNRES_8B_CS_S 32
+#define XCT_FUNRES_8B_CRC_M 0x00000000ffffffffull
+#define XCT_FUNRES_8B_CRC_S 0
+
/* Control descriptor fields */
#define CTRL_CMD_T 0x8000000000000000ull
#define CTRL_CMD_META_EVT 0x2000000000000000ull
#define CTRL_CMD_O 0x0400000000000000ull
-#define CTRL_CMD_REG_M 0x000000000000000full
+#define CTRL_CMD_ETYPE_M 0x0038000000000000ull
+#define CTRL_CMD_ETYPE_EXT 0x0000000000000000ull
+#define CTRL_CMD_ETYPE_WSET 0x0020000000000000ull
+#define CTRL_CMD_ETYPE_WCLR 0x0028000000000000ull
+#define CTRL_CMD_ETYPE_SET 0x0030000000000000ull
+#define CTRL_CMD_ETYPE_CLR 0x0038000000000000ull
+#define CTRL_CMD_REG_M 0x000000000000007full
#define CTRL_CMD_REG_S 0
#define CTRL_CMD_REG(x) ((((long)(x)) << CTRL_CMD_REG_S) & \
CTRL_CMD_REG_M)
extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
dma_addr_t *handle);
+/* Routines to allocate flags (events) for channel syncronization */
+extern int pasemi_dma_alloc_flag(void);
+extern void pasemi_dma_free_flag(int flag);
+extern void pasemi_dma_set_flag(int flag);
+extern void pasemi_dma_clear_flag(int flag);
+
+/* Routines to allocate function engines */
+extern int pasemi_dma_alloc_fun(void);
+extern void pasemi_dma_free_fun(int fun);
+
/* Initialize the library, must be called before any other functions */
extern int pasemi_dma_init(void);
#ifndef CONFIG_PPC64
-static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
+static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
return bus->sysdata;
}
extern int pcibios_remove_root_bus(struct pci_controller *phb);
-static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
+static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
struct device_node *busdn = bus->sysdata;
#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
#define FIRST_USER_ADDRESS 0
-#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
-#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
-
#define pte_ERROR(e) \
printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
(unsigned long long)pte_val(e))
#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
#define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
-#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
+#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
+ defined(CONFIG_KPROBES)
/* We want the debuggers to be able to set breakpoints anywhere, so
* don't write protect the kernel text */
#define _PAGE_RAM_TEXT _PAGE_RAM
#define pmd_page_vaddr(pmd) \
((unsigned long) (pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd) \
- (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
+ pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
#endif
/* to find an entry in a kernel page-table-directory */
--- /dev/null
+/*
+ * Hypervisor-assisted dump
+ *
+ * Linas Vepstas, Manish Ahuja 2008
+ * Copyright 2008 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _PPC64_PHYP_DUMP_H
+#define _PPC64_PHYP_DUMP_H
+
+#ifdef CONFIG_PHYP_DUMP
+
+/* The RMR region will be saved for later dumping
+ * whenever the kernel crashes. Set this to 256MB. */
+#define PHYP_DUMP_RMR_START 0x0
+#define PHYP_DUMP_RMR_END (1UL<<28)
+
+struct phyp_dump {
+ /* Memory that is reserved during very early boot. */
+ unsigned long init_reserve_start;
+ unsigned long init_reserve_size;
+ /* cmd line options during boot */
+ unsigned long reserve_bootvar;
+ unsigned long phyp_dump_at_boot;
+ /* Check status during boot if dump supported, active & present*/
+ unsigned long phyp_dump_configured;
+ unsigned long phyp_dump_is_active;
+ /* store cpu & hpte size */
+ unsigned long cpu_state_size;
+ unsigned long hpte_region_size;
+ /* previous scratch area values */
+ unsigned long reserved_scratch_addr;
+ unsigned long reserved_scratch_size;
+};
+
+extern struct phyp_dump *phyp_dump_info;
+
+int early_init_dt_scan_phyp_dump(unsigned long node,
+ const char *uname, int depth, void *data);
+
+#endif /* CONFIG_PHYP_DUMP */
+#endif /* _PPC64_PHYP_DUMP_H */
#ifdef __KERNEL__
-#include <asm/of_device.h>
-
#define PMI_TYPE_FREQ_CHANGE 0x01
#define PMI_READ_TYPE 0
#define PMI_READ_DATA0 1
--- /dev/null
+/*
+ * PPC4xx Prototypes and definitions
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_POWERPC_PPC4xx_H__
+#define __ASM_POWERPC_PPC4xx_H__
+
+extern void ppc4xx_reset_system(char *cmd);
+
+#endif /* __ASM_POWERPC_PPC4xx_H__ */
};
void ps3_sys_manager_register_ops(const struct ps3_sys_manager_ops *ops);
-void ps3_sys_manager_power_off(void);
-void ps3_sys_manager_restart(void);
+void __noreturn ps3_sys_manager_power_off(void);
+void __noreturn ps3_sys_manager_restart(void);
+void __noreturn ps3_sys_manager_halt(void);
+int ps3_sys_manager_get_wol(void);
+void ps3_sys_manager_set_wol(int state);
struct ps3_prealloc {
const char *name;
#define __ARCH_WANT_COMPAT_SYS_PTRACE
#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
+#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */
+#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265)
+#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \
+ STACK_FRAME_OVERHEAD + 288)
+#define STACK_FRAME_MARKER 12
/* Size of dummy stack frame allocated when calling signal handler. */
#define __SIGNAL_FRAMESIZE 128
#else /* __powerpc64__ */
#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
+#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */
+#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
+#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
+#define STACK_FRAME_MARKER 2
/* Size of stack frame allocated when calling signal handler. */
#define __SIGNAL_FRAMESIZE 64
/* QE internal API */
int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
enum qe_clock qe_clock_source(const char *source);
+unsigned int qe_get_brg_clk(void);
int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
int qe_get_snum(void);
void qe_put_snum(u8 snum);
int qe_muram_free(unsigned long offset);
unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
void qe_muram_dump(void);
-void *qe_muram_addr(unsigned long offset);
+
+static inline void __iomem *qe_muram_addr(unsigned long offset)
+{
+ return (void __iomem *)&qe_immr->muram[offset];
+}
+
+static inline unsigned long qe_muram_offset(void __iomem *addr)
+{
+ return addr - (void __iomem *)qe_immr->muram;
+}
/* Structure that defines QE firmware binary files.
*
#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
spinlock_t wait_lock;
struct list_head wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+ struct lockdep_map dep_map;
+#endif
};
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
+
#define __RWSEM_INITIALIZER(name) \
- { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
- LIST_HEAD_INIT((name).wait_list) }
+ { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
+ LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) }
#define DECLARE_RWSEM(name) \
struct rw_semaphore name = __RWSEM_INITIALIZER(name)
extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
-static inline void init_rwsem(struct rw_semaphore *sem)
-{
- sem->count = RWSEM_UNLOCKED_VALUE;
- spin_lock_init(&sem->wait_lock);
- INIT_LIST_HEAD(&sem->wait_list);
-}
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+ struct lock_class_key *key);
+
+#define init_rwsem(sem) \
+ do { \
+ static struct lock_class_key __key; \
+ \
+ __init_rwsem((sem), #sem, &__key); \
+ } while (0)
/*
* lock for reading
/*
* lock for writing
*/
-static inline void __down_write(struct rw_semaphore *sem)
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
{
int tmp;
rwsem_down_write_failed(sem);
}
+static inline void __down_write(struct rw_semaphore *sem)
+{
+ __down_write_nested(sem, 0);
+}
+
static inline int __down_write_trylock(struct rw_semaphore *sem)
{
int tmp;
#ifdef CONFIG_MEMORY_HOTPLUG
extern void create_section_mapping(unsigned long start, unsigned long end);
+extern int remove_section_mapping(unsigned long start, unsigned long end);
#ifdef CONFIG_NUMA
extern int hot_add_scn_to_nid(unsigned long scn_addr);
#else
*
* (the type definitions are in asm/spinlock_types.h)
*/
+#include <linux/irqflags.h>
#ifdef CONFIG_PPC64
#include <asm/paca.h>
#include <asm/hvcall.h>
#define __HAVE_ARCH_STRNCPY
#define __HAVE_ARCH_STRLEN
#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRNCMP
#define __HAVE_ARCH_STRCAT
#define __HAVE_ARCH_MEMSET
#define __HAVE_ARCH_MEMCPY
extern char * strncpy(char *,const char *, __kernel_size_t);
extern __kernel_size_t strlen(const char *);
extern int strcmp(const char *,const char *);
+extern int strncmp(const char *, const char *, __kernel_size_t);
extern char * strcat(char *, const char *);
extern void * memset(void *,int,__kernel_size_t);
extern void * memcpy(void *,const void *,__kernel_size_t);
#define _ASM_POWERPC_SYSTEM_H
#include <linux/kernel.h>
+#include <linux/irqflags.h>
#include <asm/hw_irq.h>
{
}
+#endif /* CONFIG_NUMA */
#include <asm-generic/topology.h>
-#endif /* CONFIG_NUMA */
-
#ifdef CONFIG_SMP
#include <asm/cputable.h>
#define smt_capable() (cpu_has_feature(CPU_FTR_SMT))
typedef __vector128 vector128;
+/* Physical address used by some IO functions */
+#if defined(CONFIG_PPC64) || defined(CONFIG_PHYS_64BIT)
+typedef u64 phys_addr_t;
+#else
+typedef u32 phys_addr_t;
+#endif
+
#ifdef __powerpc64__
typedef u64 dma_addr_t;
#else
#include <asm/mmu.h>
#include <asm/ocp_ids.h>
-#include <asm/semaphore.h>
#ifdef CONFIG_PPC_OCP
case CPU_SH7619:
*p++ = '2';
break;
- case CPU_SH7203 ... CPU_SH7263:
+ case CPU_SH7203 ... CPU_MXG:
*p++ = '2';
*p++ = 'a';
break;
#ifndef __ASM_CPU_SH4_FREQ_H
#define __ASM_CPU_SH4_FREQ_H
-#if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366)
+#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7723) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7366)
#define FRQCR 0xa4150000
#define VCLKCR 0xa4150004
#define SCLKACR 0xa4150008
#define SCLKBCR 0xa415000c
-#if defined(CONFIG_CPU_SUBTYPE_SH7722)
#define IrDACLKCR 0xa4150010
-#endif
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
#define FRQCR 0xffc80000
#ifndef __ASM_SH_CPU_SH4_RTC_H
#define __ASM_SH_CPU_SH4_RTC_H
+#ifdef CONFIG_CPU_SUBTYPE_SH7723
+#define rtc_reg_size sizeof(u16)
+#else
#define rtc_reg_size sizeof(u32)
+#endif
+
#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
--- /dev/null
+/*
+ * MMIO/IRQ and platform data for SH7760 I2C channels
+ */
+
+#ifndef _I2C_SH7760_H_
+#define _I2C_SH7760_H_
+
+#define SH7760_I2C_DEVNAME "sh7760-i2c"
+
+#define SH7760_I2C0_MMIO 0xFE140000
+#define SH7760_I2C0_MMIOEND 0xFE14003B
+#define SH7760_I2C0_IRQ 62
+
+#define SH7760_I2C1_MMIO 0xFE150000
+#define SH7760_I2C1_MMIOEND 0xFE15003B
+#define SH7760_I2C1_IRQ 63
+
+struct sh7760_i2c_platdata {
+ unsigned int speed_khz;
+};
+
+#endif
--- /dev/null
+#ifndef __ASM_SH_MIGOR_H
+#define __ASM_SH_MIGOR_H
+
+/*
+ * linux/include/asm-sh/migor.h
+ *
+ * Copyright (C) 2008 Renesas Solutions
+ *
+ * Portions Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* GPIO */
+#define MSTPCR0 0xa4150030
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+
+#define PORT_PACR 0xa4050100
+#define PORT_PDCR 0xa4050106
+#define PORT_PECR 0xa4050108
+#define PORT_PHCR 0xa405010e
+#define PORT_PJCR 0xa4050110
+#define PORT_PKCR 0xa4050112
+#define PORT_PLCR 0xa4050114
+#define PORT_PMCR 0xa4050116
+#define PORT_PRCR 0xa405011c
+#define PORT_PWCR 0xa4050146
+#define PORT_PXCR 0xa4050148
+#define PORT_PYCR 0xa405014a
+#define PORT_PZCR 0xa405014c
+#define PORT_PADR 0xa4050120
+#define PORT_PWDR 0xa4050166
+
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRC 0xa405015c
+
+#define PORT_MSELCRB 0xa4050182
+
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+
+#define PORT_PSELA 0xa405014e
+#define PORT_PSELB 0xa4050150
+#define PORT_PSELC 0xa4050152
+#define PORT_PSELD 0xa4050154
+
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRB 0xa405015a
+#define PORT_HIZCRC 0xa405015c
+
+#define BSC_CS6ABCR 0xfec1001c
+
+#endif /* __ASM_SH_MIGOR_H */
#define PCI_PROBE_BIOS 1
#define PCI_PROBE_CONF1 2
#define PCI_PROBE_CONF2 4
-#define PCI_NO_SORT 0x100
-#define PCI_BIOS_SORT 0x200
#define PCI_NO_CHECKS 0x400
#define PCI_ASSIGN_ROMS 0x1000
#define PCI_BIOS_IRQ_SCAN 0x2000
CPU_SH7619,
/* SH-2A types */
- CPU_SH7203, CPU_SH7206, CPU_SH7263,
+ CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
/* SH-3 types */
CPU_SH7705, CPU_SH7706, CPU_SH7707,
CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
/* SH-4A types */
- CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
+ CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
+ CPU_SH7723, CPU_SHX3,
/* SH4AL-DSP types */
CPU_SH7343, CPU_SH7722, CPU_SH7366,
#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
-#define PA_ICCR (PA_BCR+0x0600) /* Serial control */
-#define PA_SAR (PA_BCR+0x0602) /* Serial Slave control */
-#define PA_MDR (PA_BCR+0x0604) /* Serial Mode control */
-#define PA_ADR1 (PA_BCR+0x0606) /* Serial Address1 control */
-#define PA_DAR1 (PA_BCR+0x0646) /* Serial Data1 control */
+#define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */
+#define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */
+#define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */
+#define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
+#define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
#define PA_PMR (PA_BCR+0x0900) /* */
#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
-#define PA_ICCR (PA_BCR+0x0500) /* Serial control */
-#define PA_SAR (PA_BCR+0x0502) /* Serial Slave control */
-#define PA_MDR (PA_BCR+0x0504) /* Serial Mode control */
-#define PA_ADR1 (PA_BCR+0x0506) /* Serial Address1 control */
-#define PA_DAR1 (PA_BCR+0x0546) /* Serial Data1 control */
+#define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */
+#define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */
+#define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */
+#define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */
+#define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
#define PA_AX88796L 0xa5800400 /* AX88796L Area */
#define IRQ_TP (HL_FPGA_IRQ_BASE + 12)
#define IRQ_RTC (HL_FPGA_IRQ_BASE + 13)
#define IRQ_TH_ALERT (HL_FPGA_IRQ_BASE + 14)
+#define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15)
+#define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16)
unsigned char *highlander_init_irq_r7780mp(void);
unsigned char *highlander_init_irq_r7780rp(void);
--- /dev/null
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * Hitachi UL SolutionEngine 7721 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#ifndef __ASM_SH_SE7721_H
+#define __ASM_SH_SE7721_H
+#include <asm/addrspace.h>
+
+/* Box specific addresses. */
+#define SE_AREA0_WIDTH 2 /* Area0: 32bit */
+#define PA_ROM 0xa0000000 /* EPROM */
+#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
+#define PA_FROM 0xa1000000 /* Flash-ROM */
+#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
+#define PA_EXT1 0xa4000000
+#define PA_EXT1_SIZE 0x04000000
+#define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */
+#define PA_SDRAM_SIZE 0x04000000
+
+#define PA_EXT4 0xb0000000
+#define PA_EXT4_SIZE 0x04000000
+
+#define PA_PERIPHERAL 0xB8000000
+
+#define PA_PCIC PA_PERIPHERAL
+#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0)
+#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000)
+#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000)
+#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000)
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define PA_LED 0xB6800000 /* 8bit LED */
+#define PA_FPGA 0xB7000000 /* FPGA base address */
+
+#define MRSHPC_IRQ0 10
+
+#define FPGA_ILSR1 (PA_FPGA + 0x02)
+#define FPGA_ILSR2 (PA_FPGA + 0x03)
+#define FPGA_ILSR3 (PA_FPGA + 0x04)
+#define FPGA_ILSR4 (PA_FPGA + 0x05)
+#define FPGA_ILSR5 (PA_FPGA + 0x06)
+#define FPGA_ILSR6 (PA_FPGA + 0x07)
+#define FPGA_ILSR7 (PA_FPGA + 0x08)
+#define FPGA_ILSR8 (PA_FPGA + 0x09)
+
+void init_se7721_IRQ(void);
+
+#define __IO_PREFIX se7721
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_SE7721_H */
#define PORT_PSELA 0xA405014EUL
#define PORT_PYCR 0xA405014AUL
#define PORT_PZCR 0xA405014CUL
+#define PORT_HIZCRA 0xA4050158UL
+#define PORT_HIZCRC 0xA405015CUL
/* IRQ */
#define IRQ0_IRQ 32
--- /dev/null
+#ifndef __ASM_KEYSC_H__
+#define __ASM_KEYSC_H__
+
+#define SH_KEYSC_MAXKEYS 30
+
+struct sh_keysc_info {
+ enum { SH_KEYSC_MODE_1, SH_KEYSC_MODE_2, SH_KEYSC_MODE_3 } mode;
+ int scan_timing; /* 0 -> 7, see KYCR1, SCN[2:0] */
+ int delay;
+ int keycodes[SH_KEYSC_MAXKEYS];
+};
+
+#endif /* __ASM_KEYSC_H__ */
extern unsigned long cached_to_uncached;
+extern struct dentry *sh_debugfs_root;
+
/* XXX
* disable hlt during certain critical i/o operations
*/
.cache_nice_tries = 2, \
.busy_idx = 3, \
.idle_idx = 2, \
- .newidle_idx = 0, \
+ .newidle_idx = 2, \
.wake_idx = 1, \
.forkexec_idx = 1, \
.flags = SD_LOAD_BALANCE \
* If we don't have an MMU (or if its disabled) the only thing we really have
* to look out for is if the address resides somewhere outside of what
* available RAM we have.
- *
- * TODO: This check could probably also stand to be restricted somewhat more..
- * though it still does the Right Thing(tm) for the time being.
*/
static inline int __access_ok(unsigned long addr, unsigned long size)
{
- return ((addr >= memory_start) && ((addr + size) < memory_end));
+ return 1;
}
#else /* CONFIG_MMU */
#define __addr_ok(addr) \
header-y += bpp.h
header-y += jsflash.h
header-y += openpromio.h
-header-y += pconf.h
header-y += reg.h
header-y += traps.h
header-y += vfc_ioctls.h
+++ /dev/null
-/* a.out coredump register dumper
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_A_OUT_CORE_H
-#define _ASM_A_OUT_CORE_H
-
-#ifdef __KERNEL__
-
-#include <linux/user.h>
-
-/*
- * fill in the user structure for an a.out core dump
- */
-static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
-{
- unsigned long first_stack_page;
-
- dump->magic = SUNOS_CORE_MAGIC;
- dump->len = sizeof(struct user);
- dump->regs.psr = regs->psr;
- dump->regs.pc = regs->pc;
- dump->regs.npc = regs->npc;
- dump->regs.y = regs->y;
- /* fuck me plenty */
- memcpy(&dump->regs.regs[0], ®s->u_regs[1], (sizeof(unsigned long) * 15));
- dump->uexec = current->thread.core_exec;
- dump->u_tsize = (((unsigned long) current->mm->end_code) -
- ((unsigned long) current->mm->start_code)) & ~(PAGE_SIZE - 1);
- dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1)));
- dump->u_dsize -= dump->u_tsize;
- dump->u_dsize &= ~(PAGE_SIZE - 1);
- first_stack_page = (regs->u_regs[UREG_FP] & ~(PAGE_SIZE - 1));
- dump->u_ssize = (TASK_SIZE - first_stack_page) & ~(PAGE_SIZE - 1);
- memcpy(&dump->fpu.fpstatus.fregs.regs[0], ¤t->thread.float_regs[0], (sizeof(unsigned long) * 32));
- dump->fpu.fpstatus.fsr = current->thread.fsr;
- dump->fpu.fpstatus.flags = dump->fpu.fpstatus.extra = 0;
- dump->fpu.fpstatus.fpq_count = current->thread.fpqdepth;
- memcpy(&dump->fpu.fpstatus.fpq[0], ¤t->thread.fpqueue[0],
- ((sizeof(unsigned long) * 2) * 16));
- dump->sigcode = 0;
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_A_OUT_CORE_H */
+++ /dev/null
-#ifndef __SPARC_A_OUT_H__
-#define __SPARC_A_OUT_H__
-
-#define SPARC_PGSIZE 0x2000 /* Thanks to the sun4 architecture... */
-#define SEGMENT_SIZE SPARC_PGSIZE /* whee... */
-
-#ifndef __ASSEMBLY__
-
-struct exec {
- unsigned char a_dynamic:1; /* A __DYNAMIC is in this image */
- unsigned char a_toolversion:7;
- unsigned char a_machtype;
- unsigned short a_info;
- unsigned int a_text; /* length of text, in bytes */
- unsigned int a_data; /* length of data, in bytes */
- unsigned int a_bss; /* length of bss, in bytes */
- unsigned int a_syms; /* length of symbol table, in bytes */
- unsigned int a_entry; /* where program begins */
- unsigned int a_trsize;
- unsigned int a_drsize;
-};
-
-#endif /* !__ASSEMBLY__ */
-
-/* Where in the file does the text information begin? */
-#define N_TXTOFF(x) (N_MAGIC(x) == ZMAGIC ? 0 : sizeof (struct exec))
-
-/* Where do the Symbols start? */
-#define N_SYMOFF(x) (N_TXTOFF(x) + (x).a_text + \
- (x).a_data + (x).a_trsize + \
- (x).a_drsize)
-
-/* Where does text segment go in memory after being loaded? */
-#define N_TXTADDR(x) (unsigned long)(((N_MAGIC(x) == ZMAGIC) && \
- ((x).a_entry < SPARC_PGSIZE)) ? \
- 0 : SPARC_PGSIZE)
-
-/* And same for the data segment.. */
-#define N_DATADDR(x) (N_MAGIC(x)==OMAGIC ? \
- (N_TXTADDR(x) + (x).a_text) \
- : (unsigned long) (_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))
-
-#define N_TRSIZE(a) ((a).a_trsize)
-#define N_DRSIZE(a) ((a).a_drsize)
-#define N_SYMSIZE(a) ((a).a_syms)
-
-#ifndef __ASSEMBLY__
-
-/*
- * Sparc relocation types
- */
-enum reloc_type
-{
- RELOC_8,
- RELOC_16,
- RELOC_32, /* simplest relocs */
- RELOC_DISP8,
- RELOC_DISP16,
- RELOC_DISP32, /* Disp's (pc-rel) */
- RELOC_WDISP30,
- RELOC_WDISP22, /* SR word disp's */
- RELOC_HI22,
- RELOC_22, /* SR 22-bit relocs */
- RELOC_13,
- RELOC_LO10, /* SR 13&10-bit relocs */
- RELOC_SFA_BASE,
- RELOC_SFA_OFF13, /* SR S.F.A. relocs */
- RELOC_BASE10,
- RELOC_BASE13,
- RELOC_BASE22, /* base_relative pic */
- RELOC_PC10,
- RELOC_PC22, /* special pc-rel pic */
- RELOC_JMP_TBL, /* jmp_tbl_rel in pic */
- RELOC_SEGOFF16, /* ShLib offset-in-seg */
- RELOC_GLOB_DAT,
- RELOC_JMP_SLOT,
- RELOC_RELATIVE /* rtld relocs */
-};
-
-/*
- * Format of a relocation datum.
- */
-struct relocation_info /* used when header.a_machtype == M_SPARC */
-{
- unsigned int r_address; /* relocation addr */
- unsigned int r_index:24; /* segment index or symbol index */
- unsigned int r_extern:1; /* if F, r_index==SEG#; if T, SYM idx */
- unsigned int r_pad:2; /* <unused> */
- enum reloc_type r_type:5; /* type of relocation to perform */
- int r_addend; /* addend for relocation value */
-};
-
-#define N_RELOCATION_INFO_DECLARED 1
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* __SPARC_A_OUT_H__ */
/* Our low-level entry point in arch/sparc/kernel/entry.S */
extern int sparc_floppy_request_irq(int irq, unsigned long flags,
- irqreturn_t (*irq_handler)(int irq, void *));
+ irq_handler_t irq_handler);
static int sun_fd_request_irq(void)
{
b linux_sparc_syscall; \
rd %psr, %l0;
-/* Software trap for SunOS4.1.x system calls. */
-#define SUNOS_SYSCALL_TRAP \
- rd %psr, %l0; \
- sethi %hi(sunos_sys_table), %l7; \
- b linux_sparc_syscall; \
- or %l7, %lo(sunos_sys_table), %l7;
-
-#define SUNOS_NO_SYSCALL_TRAP \
- b sunos_syscall; \
- rd %psr, %l0; \
- nop; \
- nop;
-
-/* Software trap for Slowaris system calls. */
-#define SOLARIS_SYSCALL_TRAP \
- b solaris_syscall; \
- rd %psr, %l0; \
- nop; \
- nop;
-
-#define INDIRECT_SOLARIS_SYSCALL(x) \
- mov x, %g1; \
- b solaris_syscall; \
- rd %psr, %l0; \
- nop;
-
#define BREAKPOINT_TRAP \
b breakpoint_trap; \
rd %psr,%l0; \
nop; \
nop;
-/* Software trap for Sparc-netbsd system calls. */
-#define NETBSD_SYSCALL_TRAP \
- sethi %hi(sys_call_table), %l7; \
- or %l7, %lo(sys_call_table), %l7; \
- b bsd_syscall; \
- rd %psr, %l0;
-
/* The Get Condition Codes software trap for userland. */
#define GETCC_TRAP \
b getcc_trap_handler; mov %psr, %l0; nop; nop;
#define __TIOCSETX _IOW('t', 34, int) /* SunOS Specific */
#define __TIOCGETX _IOR('t', 35, int) /* SunOS Specific */
#define TIOCCONS _IO('t', 36)
-#define __TIOCSSIZE _IOW('t', 37, struct sunos_ttysize) /* SunOS Specific */
-#define __TIOCGSIZE _IOR('t', 38, struct sunos_ttysize) /* SunOS Specific */
#define TIOCGSOFTCAR _IOR('t', 100, int)
#define TIOCSSOFTCAR _IOW('t', 101, int)
#define __TIOCUCNTL _IOW('t', 102, int) /* SunOS Specific */
#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
#define MAP_NONBLOCK 0x10000 /* do not block on IO */
-/* XXX Need to add flags to SunOS's mctl, mlockall, and madvise system
- * XXX calls.
- */
-
-/* SunOS sys_mctl() stuff... */
-#define MC_SYNC 1 /* Sync pages in memory with storage (usu. a file) */
-#define MC_LOCK 2 /* Lock pages into core ram, do not allow swapping of them */
-#define MC_UNLOCK 3 /* Unlock pages locked via previous mctl() with MC_LOCK arg */
-#define MC_LOCKAS 5 /* Lock an entire address space of the calling process */
-#define MC_UNLOCKAS 6 /* Unlock entire address space of calling process */
-
-#define MADV_FREE 0x5 /* (Solaris) contents can be freed */
-
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
#define arch_mmap_check sparc_mmap_check
#ifndef __SPARC_NAMEI_H
#define __SPARC_NAMEI_H
-#define SPARC_BSD_EMUL "/usr/gnemul/sunos/"
-#define SPARC_SOL_EMUL "/usr/gnemul/solaris/"
-
-static inline char * __emul_prefix(void)
-{
- switch (current->personality) {
- case PER_SUNOS:
- return SPARC_BSD_EMUL;
- case PER_SVR4:
- return SPARC_SOL_EMUL;
- default:
- return NULL;
- }
-}
+#define __emul_prefix() NULL
#endif /* __SPARC_NAMEI_H */
+++ /dev/null
-/* $Id: pconf.h,v 1.3 1996/04/25 06:13:25 davem Exp $
- * pconf.h: pathconf() and fpathconf() defines for SunOS
- * system call compatibility.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_PCONF_H
-#define _SPARC_PCONF_H
-
-#include <linux/fs.h>
-#include <linux/limits.h>
-
-#define _PCONF_LINK 1 /* Max number of links to an object */
-#define _PCONF_CANON 2 /* TTY input buffer line size */
-#define _PCONF_INPUT 3 /* Biggest packet a tty can imbibe at once */
-#define _PCONF_NAME 4 /* Filename length max */
-#define _PCONF_PATH 5 /* Max size of a pathname */
-#define _PCONF_PIPE 6 /* Buffer size for a pipe */
-#define _PCONF_CHRESTRICT 7 /* Can only root chown files? */
-#define _PCONF_NOTRUNC 8 /* Are pathnames truncated if too big? */
-#define _PCONF_VDISABLE 9 /* Magic char to disable special tty chars */
-#define _PCONF_MAXPCONF 9
-
-#endif /* !(_SPARC_PCONF_H) */
*/
#define current_text_addr() ({ void *pc; __asm__("sethi %%hi(1f), %0; or %0, %%lo(1f), %0;\n1:" : "=r" (pc)); pc; })
-#include <linux/a.out.h>
-
#include <asm/psr.h>
#include <asm/ptrace.h>
#include <asm/head.h>
struct fpq fpqueue[16];
unsigned long flags;
mm_segment_t current_ds;
- struct exec core_exec; /* just what it says. */
int new_signal;
};
#define SO_SNDTIMEO 0x4000
#define SO_ACCEPTCONN 0x8000
-/* wha!??? */
-#define SO_DONTLINGER (~SO_LINGER) /* Older SunOS compat. hack */
-
#define SO_SNDBUF 0x1001
#define SO_RCVBUF 0x1002
#define SO_SNDBUFFORCE 0x100a
+++ /dev/null
-/* $Id: solerrno.h,v 1.5 1996/04/25 06:13:32 davem Exp $
- * solerrno.h: Solaris error return codes for compatibility.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC_SOLERRNO_H
-#define _SPARC_SOLERRNO_H
-
-#define SOL_EPERM 1 /* Required superuser access perms */
-#define SOL_ENOENT 2 /* File or directory does not exist */
-#define SOL_ESRCH 3 /* Process did not exist */
-#define SOL_EINTR 4 /* System call was interrupted */
-#define SOL_EIO 5 /* An i/o error occurred */
-#define SOL_ENXIO 6 /* Device or Address does not exist */
-#define SOL_E2BIG 7 /* Too many arguments were given */
-#define SOL_ENOEXEC 8 /* Header of executable was munged */
-#define SOL_EBADF 9 /* Bogus file number */
-#define SOL_ECHILD 10 /* No children of process exist */
-#define SOL_EAGAIN 11 /* beep beep, "try again later" */
-#define SOL_ENOMEM 12 /* No memory available */
-#define SOL_EACCES 13 /* Access not allowed */
-#define SOL_EFAULT 14 /* Address passed was invalid */
-#define SOL_ENOTBLK 15 /* blkdev op on non-block device */
-#define SOL_EBUSY 16 /* Mounted device was busy */
-#define SOL_EEXIST 17 /* File specified already exists */
-#define SOL_EXDEV 18 /* Link request across diff devices */
-#define SOL_ENODEV 19 /* Device does not exist on system */
-#define SOL_ENOTDIR 20 /* Dir operation on non-directory */
-#define SOL_EISDIR 21 /* File was of directory type */
-#define SOL_EINVAL 22 /* Argument passed was invalid */
-#define SOL_ENFILE 23 /* No more room in file table */
-#define SOL_EMFILE 24 /* Proc has too many files open */
-#define SOL_ENOTTY 25 /* Ioctl was invalid for req device */
-#define SOL_ETXTBSY 26 /* Text file in busy state */
-#define SOL_EFBIG 27 /* Too big of a file for operation */
-#define SOL_ENOSPC 28 /* Disk is full */
-#define SOL_ESPIPE 29 /* Seek attempted on non-seeking dev*/
-#define SOL_EROFS 30 /* Write attempted on read-only fs */
-#define SOL_EMLINK 31 /* Too many links in file search */
-#define SOL_EPIPE 32 /* Call a plumber */
-#define SOL_EDOM 33 /* Argument was out of fct domain */
-#define SOL_ERANGE 34 /* Could not represent math result */
-#define SOL_ENOMSG 35 /* Message of req type doesn't exist */
-#define SOL_EIDRM 36 /* Identifier has been removed */
-#define SOL_ECHRNG 37 /* Req channel number out of range */
-#define SOL_EL2NSYNC 38 /* Could not sync at run level 2 */
-#define SOL_EL3HLT 39 /* Halted at run level 3 */
-#define SOL_EL3RST 40 /* Reset at run level 3 */
-#define SOL_ELNRNG 41 /* Out of range link number */
-#define SOL_EUNATCH 42 /* Driver for protocol not attached */
-#define SOL_ENOCSI 43 /* CSI structure not around */
-#define SOL_EL2HLT 44 /* Halted at run level 2 */
-#define SOL_EDEADLK 45 /* Deadlock condition detected */
-#define SOL_ENOLCK 46 /* Record locks unavailable */
-#define SOL_ECANCELED 47 /* Cancellation of oper. happened */
-#define SOL_ENOTSUP 48 /* Attempt of unsupported operation */
-#define SOL_EDQUOT 49 /* Users disk quota exceeded */
-#define SOL_EBADE 50 /* Invalid exchange */
-#define SOL_EBADR 51 /* Request descriptor was invalid */
-#define SOL_EXFULL 52 /* Full exchange */
-#define SOL_ENOANO 53 /* ano does not exist */
-#define SOL_EBADRQC 54 /* Req code was invalid */
-#define SOL_EBADSLT 55 /* Bad slot number */
-#define SOL_EDEADLOCK 56 /* Deadlock in fs error */
-#define SOL_EBFONT 57 /* Font file format invalid */
-/* YOW, I LOVE SYSV STREAMS!!!! */
-#define SOL_ENOSTR 60 /* Stream-op on non-stream dev */
-#define SOL_ENODATA 61 /* No data avail at this time */
-#define SOL_ETIME 62 /* Expiration of time occurred */
-#define SOL_ENOSR 63 /* Streams resources exhausted */
-#define SOL_ENONET 64 /* No network connected */
-#define SOL_ENOPKG 65 /* Non-installed package */
-#define SOL_EREMOTE 66 /* Object was on remote machine */
-#define SOL_ENOLINK 67 /* Cut link */
-#define SOL_EADV 68 /* Error in advertise */
-#define SOL_ESRMNT 69 /* Some magic srmount problem */
-#define SOL_ECOMM 70 /* During send, comm error occurred */
-#define SOL_EPROTO 71 /* Protocol botch */
-#define SOL_EMULTIHOP 74 /* Multihop attempted */
-#define SOL_EBADMSG 77 /* Message was unreadable */
-#define SOL_ENAMETOOLONG 78 /* Too long of a path name */
-#define SOL_EOVERFLOW 79 /* Data type too small for datum */
-#define SOL_ENOTUNIQ 80 /* Logical name was not unique */
-#define SOL_EBADFD 81 /* Op cannot be performed on fd */
-#define SOL_EREMCHG 82 /* Remote address is now different */
-#define SOL_ELIBACC 83 /* Shared lib could not be accessed */
-#define SOL_ELIBBAD 84 /* ShLib is corrupted in some way */
-#define SOL_ELIBSCN 85 /* A.out ShLib problems */
-#define SOL_ELIBMAX 86 /* Exceeded ShLib linkage limit */
-#define SOL_ELIBEXEC 87 /* Execution of ShLib attempted */
-#define SOL_EILSEQ 88 /* Bad byte sequence found */
-#define SOL_ENOSYS 89 /* Invalid filesystem operation */
-#define SOL_ELOOP 90 /* Detected loop in symbolic links */
-#define SOL_ERESTART 91 /* System call is restartable */
-#define SOL_ESTRPIPE 92 /* Do not sleep in head of stream */
-#define SOL_ENOTEMPTY 93 /* Rmdir of non-empty directory */
-#define SOL_EUSERS 94 /* Over abundance of users for ufs */
-#define SOL_ENOTSOCK 95 /* Sock-op on non-sock */
-#define SOL_EDESTADDRREQ 96 /* No dest addr given, but needed */
-#define SOL_EMSGSIZE 97 /* Msg too big */
-#define SOL_EPROTOTYPE 98 /* Bad socket protocol */
-#define SOL_ENOPROTOOPT 99 /* Unavailable protocol */
-#define SOL_EPROTONOSUPPORT 120 /* Unsupported protocol */
-#define SOL_ESOCKTNOSUPPORT 121 /* Unsupported socket type */
-#define SOL_EOPNOTSUPP 122 /* Unsupported sock-op */
-#define SOL_EPFNOSUPPORT 123 /* Unsupported protocol family */
-#define SOL_EAFNOSUPPORT 124 /* Unsup addr family for protocol */
-#define SOL_EADDRINUSE 125 /* Req addr is already in use */
-#define SOL_EADDRNOTAVAIL 126 /* Req addr not available right now */
-#define SOL_ENETDOWN 127 /* Your subnet is on fire */
-#define SOL_ENETUNREACH 128 /* Someone playing with gateway and */
- /* did not tell you he was going to */
-#define SOL_ENETRESET 129 /* Buy less-buggy ethernet cards */
-#define SOL_ECONNABORTED 130 /* Aborted connection due to sw */
-#define SOL_ECONNRESET 131 /* Your peers reset your connection */
-#define SOL_ENOBUFS 132 /* No buffer space available */
-#define SOL_EISCONN 133 /* Connect on already connected */
- /* socket attempted */
-#define SOL_ENOTCONN 134 /* Comm on non-connected socket */
-#define SOL_ESHUTDOWN 143 /* Op attempted after sock-shutdown */
-#define SOL_ETOOMANYREFS 144 /* Reference limit exceeded */
-#define SOL_ETIMEDOUT 145 /* Timed out connection */
-#define SOL_ECONNREFUSED 146 /* Connection refused by remote host*/
-#define SOL_EHOSTDOWN 147 /* Remote host is up in flames */
-#define SOL_EHOSTUNREACH 148 /* Make a left at Easton Ave..... */
-#define SOL_EWOULDBLOCK EAGAIN /* Just an alias */
-#define SOL_EALREADY 149 /* Operation is already occurring */
-#define SOL_EINPROGRESS 150 /* Operation is happening now */
-#define SOL_ESTALE 151 /* Fungus growth on NFS file handle */
-
-#endif /* !(_SPARC_SOLERRNO_H) */
+++ /dev/null
-/* Solaris/SPARC constants and definitions --
- * (C) 1996 Miguel de Icaza
- *
- * This file is not meant to be included by user level applications
- * but the solaris syscall emulator
- */
-
-#ifndef _SPARC_SVR4_H
-#define _SPARC_SVR4_H
-
-/* Signals as used by svr4 */
-typedef struct { /* signal set type */
- ulong sigbits[4];
-} svr4_sigset_t;
-
-/* Values for siginfo.code */
-#define SVR4_SINOINFO 32767
-/* Siginfo, sucker expects bunch of information on those parameters */
-typedef union {
- char total_size [128];
- struct {
- int signo;
- int code;
- int error;
- union {
- } data;
- } siginfo;
-} svr4_siginfo_t;
-
-/* Context definition */
-
-/* Location of the user stored registers into a greg_t */
-enum {
- SVR4_PSR, SVR4_PC, SVR4_NPC, SVR4_Y,
- SVR4_G1, SVR4_G2, SVR4_G3, SVR4_G4,
- SVR4_G5, SVR4_G6, SVR4_G7, SVR4_O0,
- SVR4_O1, SVR4_O2, SVR4_O3, SVR4_O4,
- SVR4_O5, SVR4_O6, SVR4_O7
-};
-
-/* sizeof (regs) / sizeof (greg_t), defined in the ABI */
-#define SVR4_NREGS 19
-#define SVR4_MAXWIN 31
-
-typedef struct {
- uint rwin_lo[8];
- uint rwin_in[8];
-} svr4_rwindow_t;
-
-typedef struct {
- int count;
- int __user *winptr [SVR4_MAXWIN]; /* pointer to the windows */
- svr4_rwindow_t win[SVR4_MAXWIN]; /* the windows */
-} svr4_gwindows_t;
-
-typedef int svr4_gregset_t[SVR4_NREGS];
-
-typedef struct {
- double fpu_regs[32];
- void *fp_q;
- unsigned fp_fsr;
- u_char fp_nqel;
- u_char fp_nqsize;
- u_char inuse; /* if fpu is in use */
-} svr4_fregset_t;
-
-typedef struct {
- uint id; /* if this holds "xrs" string => ptr is valid */
- caddr_t ptr;
-} svr4_xrs_t;
-
-/* Machine dependent context */
-typedef struct {
- svr4_gregset_t greg; /* registers 0..19 (see top) */
- svr4_gwindows_t __user *gwin; /* may point to register windows */
- svr4_fregset_t freg; /* floating point registers */
- svr4_xrs_t xrs; /* mhm? */
- long pad[19];
-} svr4_mcontext_t;
-
-/* flags for stack_t.flags */
-enum svr4_stack_flags {
- SVR4_SS_ONSTACK,
- SVR4_SS_DISABLE,
-};
-
-/* signal stack exection place, unsupported */
-typedef struct svr4_stack_t {
- char __user *sp;
- int size;
- int flags;
-} svr4_stack_t;
-
-/* Context used by getcontext and setcontext */
-typedef struct svr4_ucontext_t {
- u_long flags; /* context flags, indicate what is loaded */
- struct svr4_ucontext *link;
- svr4_sigset_t sigmask;
- svr4_stack_t stack;
- svr4_mcontext_t mcontext;
- long pad[23];
-} svr4_ucontext_t;
-
-/* windows hold the windows as they were at signal time,
- * ucontext->mcontext holds a pointer to them.
- * addresses for uc and si are passed as parameters to svr4 signal
- * handler
- */
-
-/* This is the signal frame that is passed to the signal handler */
-typedef struct {
- svr4_gwindows_t gw; /* windows */
- svr4_ucontext_t uc; /* machine context */
- svr4_siginfo_t si; /* siginfo */
-} svr4_signal_frame_t;
-
-#define SVR4_SF_ALIGNED (((sizeof (svr4_signal_frame_t) + 7) & (~7)))
-
-#endif /* include control */
};
#endif /* __KERNEL__ */
-struct sunos_ttysize {
- int st_lines; /* Lines on the terminal */
- int st_columns; /* Columns on the terminal */
-};
-
struct winsize {
unsigned short ws_row;
unsigned short ws_col;
-/* $Id: user.h,v 1.5 1998/02/23 01:49:22 rth Exp $
- * asm-sparc/user.h: Core file definitions for the Sparc.
- *
- * Keep in sync with reg.h. Actually, we could get rid of this
- * one, since we won't a.out core dump that much anyways - miguel.
- * Copyright (C) 1995 (davem@caip.rutgers.edu)
- */
#ifndef _SPARC_USER_H
#define _SPARC_USER_H
-#include <asm/a.out.h>
-struct sunos_regs {
- unsigned long psr, pc, npc, y;
- unsigned long regs[15];
-};
-
-struct sunos_fpqueue {
- unsigned long *addr;
- unsigned long inst;
-};
-
-struct sunos_fp {
- union {
- unsigned long regs[32];
- double reg_dbls[16];
- } fregs;
- unsigned long fsr;
- unsigned long flags;
- unsigned long extra;
- unsigned long fpq_count;
- struct sunos_fpqueue fpq[16];
-};
-
-struct sunos_fpu {
- struct sunos_fp fpstatus;
-};
-
-/* The SunOS core file header layout. */
-struct user {
- unsigned long magic;
- unsigned long len;
- struct sunos_regs regs;
- struct exec uexec;
- int signal;
- size_t u_tsize; /* all of these in bytes! */
- size_t u_dsize;
- size_t u_ssize;
- char u_comm[17];
- struct sunos_fpu fpu;
- unsigned long sigcode; /* Special sigcontext subcode, if any */
-};
-
-#define NBPG 0x2000
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_DATA_START_ADDR (u.uexec.a_data)
-#define HOST_STACK_END_ADDR (- u.u_ssize * NBPG)
-#define SUNOS_CORE_MAGIC 0x080456
+/* Nothing to define. */
#endif /* !(_SPARC_USER_H) */
header-y += envctrl.h
header-y += openprom.h
header-y += openpromio.h
-header-y += pconf.h
header-y += psrcompat.h
header-y += pstate.h
header-y += reg.h
+++ /dev/null
-/* a.out coredump register dumper
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_A_OUT_CORE_H
-#define _ASM_A_OUT_CORE_H
-
-#ifdef __KERNEL__
-
-#include <linux/user.h>
-
-/*
- * fill in the user structure for an a.out core dump
- */
-static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
-{
- /* Only should be used for SunOS and ancient a.out
- * SparcLinux binaries... Not worth implementing.
- */
- memset(dump, 0, sizeof(struct user));
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_A_OUT_CORE_H */
+++ /dev/null
-#include <asm-sparc/a.out.h>
#define __TIOCSETX _IOW('t', 34, int) /* SunOS Specific */
#define __TIOCGETX _IOR('t', 35, int) /* SunOS Specific */
#define TIOCCONS _IO('t', 36)
-#define __TIOCSSIZE _IOW('t', 37, struct sunos_ttysize) /* SunOS Specific */
-#define __TIOCGSIZE _IOR('t', 38, struct sunos_ttysize) /* SunOS Specific */
#define TIOCGSOFTCAR _IOR('t', 100, int)
#define TIOCSSOFTCAR _IOW('t', 101, int)
#define __TIOCUCNTL _IOW('t', 102, int) /* SunOS Specific */
--- /dev/null
+#ifndef _SPARC64_LMB_H
+#define _SPARC64_LMB_H
+
+#include <asm/oplib.h>
+
+#define LMB_DBG(fmt...) prom_printf(fmt)
+
+#define LMB_REAL_LIMIT 0
+
+#endif /* !(_SPARC64_LMB_H) */
#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
#define MAP_NONBLOCK 0x10000 /* do not block on IO */
-/* XXX Need to add flags to SunOS's mctl, mlockall, and madvise system
- * XXX calls.
- */
-
-/* SunOS sys_mctl() stuff... */
-#define MC_SYNC 1 /* Sync pages in memory with storage (usu. a file) */
-#define MC_LOCK 2 /* Lock pages into core ram, do not allow swapping of them */
-#define MC_UNLOCK 3 /* Unlock pages locked via previous mctl() with MC_LOCK arg */
-#define MC_LOCKAS 5 /* Lock an entire address space of the calling process */
-#define MC_UNLOCKAS 6 /* Unlock entire address space of calling process */
-
-#define MADV_FREE 0x5 /* (Solaris) contents can be freed */
-
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
#define arch_mmap_check sparc64_mmap_check
#ifndef __SPARC64_NAMEI_H
#define __SPARC64_NAMEI_H
-#define SPARC_BSD_EMUL "/usr/gnemul/sunos/"
-#define SPARC_SOL_EMUL "/usr/gnemul/solaris/"
-
-static inline char * __emul_prefix(void)
-{
- switch (current->personality) {
- case PER_SUNOS:
- return SPARC_BSD_EMUL;
- case PER_SVR4:
- return SPARC_SOL_EMUL;
- default:
- return NULL;
- }
-}
+#define __emul_prefix() NULL
#endif /* __SPARC64_NAMEI_H */
+++ /dev/null
-/* $Id: pconf.h,v 1.1 1996/12/02 00:09:10 davem Exp $
- * pconf.h: pathconf() and fpathconf() defines for SunOS
- * system call compatibility.
- *
- * Copyright (C) 1995, 1996 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC64_PCONF_H
-#define _SPARC64_PCONF_H
-
-#include <linux/fs.h>
-#include <linux/limits.h>
-
-#define _PCONF_LINK 1 /* Max number of links to an object */
-#define _PCONF_CANON 2 /* TTY input buffer line size */
-#define _PCONF_INPUT 3 /* Biggest packet a tty can imbibe at once */
-#define _PCONF_NAME 4 /* Filename length max */
-#define _PCONF_PATH 5 /* Max size of a pathname */
-#define _PCONF_PIPE 6 /* Buffer size for a pipe */
-#define _PCONF_CHRESTRICT 7 /* Can only root chown files? */
-#define _PCONF_NOTRUNC 8 /* Are pathnames truncated if too big? */
-#define _PCONF_VDISABLE 9 /* Magic char to disable special tty chars */
-#define _PCONF_MAXPCONF 9
-
-#endif /* !(_SPARC64_PCONF_H) */
#define SO_SNDTIMEO 0x4000
#define SO_ACCEPTCONN 0x8000
-/* wha!??? */
-#define SO_DONTLINGER (~SO_LINGER) /* Older SunOS compat. hack */
-
#define SO_SNDBUF 0x1001
#define SO_RCVBUF 0x1002
#define SO_SNDBUFFORCE 0x100a
+++ /dev/null
-/* $Id: solerrno.h,v 1.1 1996/12/26 14:22:40 davem Exp $
- * solerrno.h: Solaris error return codes for compatibility.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _SPARC64_SOLERRNO_H
-#define _SPARC64_SOLERRNO_H
-
-#define SOL_EPERM 1 /* Required superuser access perms */
-#define SOL_ENOENT 2 /* File or directory does not exist */
-#define SOL_ESRCH 3 /* Process did not exist */
-#define SOL_EINTR 4 /* System call was interrupted */
-#define SOL_EIO 5 /* An i/o error occurred */
-#define SOL_ENXIO 6 /* Device or Address does not exist */
-#define SOL_E2BIG 7 /* Too many arguments were given */
-#define SOL_ENOEXEC 8 /* Header of executable was munged */
-#define SOL_EBADF 9 /* Bogus file number */
-#define SOL_ECHILD 10 /* No children of process exist */
-#define SOL_EAGAIN 11 /* beep beep, "try again later" */
-#define SOL_ENOMEM 12 /* No memory available */
-#define SOL_EACCES 13 /* Access not allowed */
-#define SOL_EFAULT 14 /* Address passed was invalid */
-#define SOL_ENOTBLK 15 /* blkdev op on non-block device */
-#define SOL_EBUSY 16 /* Mounted device was busy */
-#define SOL_EEXIST 17 /* File specified already exists */
-#define SOL_EXDEV 18 /* Link request across diff devices */
-#define SOL_ENODEV 19 /* Device does not exist on system */
-#define SOL_ENOTDIR 20 /* Dir operation on non-directory */
-#define SOL_EISDIR 21 /* File was of directory type */
-#define SOL_EINVAL 22 /* Argument passed was invalid */
-#define SOL_ENFILE 23 /* No more room in file table */
-#define SOL_EMFILE 24 /* Proc has too many files open */
-#define SOL_ENOTTY 25 /* Ioctl was invalid for req device */
-#define SOL_ETXTBSY 26 /* Text file in busy state */
-#define SOL_EFBIG 27 /* Too big of a file for operation */
-#define SOL_ENOSPC 28 /* Disk is full */
-#define SOL_ESPIPE 29 /* Seek attempted on non-seeking dev*/
-#define SOL_EROFS 30 /* Write attempted on read-only fs */
-#define SOL_EMLINK 31 /* Too many links in file search */
-#define SOL_EPIPE 32 /* Call a plumber */
-#define SOL_EDOM 33 /* Argument was out of fct domain */
-#define SOL_ERANGE 34 /* Could not represent math result */
-#define SOL_ENOMSG 35 /* Message of req type doesn't exist */
-#define SOL_EIDRM 36 /* Identifier has been removed */
-#define SOL_ECHRNG 37 /* Req channel number out of range */
-#define SOL_EL2NSYNC 38 /* Could not sync at run level 2 */
-#define SOL_EL3HLT 39 /* Halted at run level 3 */
-#define SOL_EL3RST 40 /* Reset at run level 3 */
-#define SOL_ELNRNG 41 /* Out of range link number */
-#define SOL_EUNATCH 42 /* Driver for protocol not attached */
-#define SOL_ENOCSI 43 /* CSI structure not around */
-#define SOL_EL2HLT 44 /* Halted at run level 2 */
-#define SOL_EDEADLK 45 /* Deadlock condition detected */
-#define SOL_ENOLCK 46 /* Record locks unavailable */
-#define SOL_ECANCELED 47 /* Cancellation of oper. happened */
-#define SOL_ENOTSUP 48 /* Attempt of unsupported operation */
-#define SOL_EDQUOT 49 /* Users disk quota exceeded */
-#define SOL_EBADE 50 /* Invalid exchange */
-#define SOL_EBADR 51 /* Request descriptor was invalid */
-#define SOL_EXFULL 52 /* Full exchange */
-#define SOL_ENOANO 53 /* ano does not exist */
-#define SOL_EBADRQC 54 /* Req code was invalid */
-#define SOL_EBADSLT 55 /* Bad slot number */
-#define SOL_EDEADLOCK 56 /* Deadlock in fs error */
-#define SOL_EBFONT 57 /* Font file format invalid */
-/* YOW, I LOVE SYSV STREAMS!!!! */
-#define SOL_ENOSTR 60 /* Stream-op on non-stream dev */
-#define SOL_ENODATA 61 /* No data avail at this time */
-#define SOL_ETIME 62 /* Expiration of time occurred */
-#define SOL_ENOSR 63 /* Streams resources exhausted */
-#define SOL_ENONET 64 /* No network connected */
-#define SOL_ENOPKG 65 /* Non-installed package */
-#define SOL_EREMOTE 66 /* Object was on remote machine */
-#define SOL_ENOLINK 67 /* Cut link */
-#define SOL_EADV 68 /* Error in advertise */
-#define SOL_ESRMNT 69 /* Some magic srmount problem */
-#define SOL_ECOMM 70 /* During send, comm error occurred */
-#define SOL_EPROTO 71 /* Protocol botch */
-#define SOL_EMULTIHOP 74 /* Multihop attempted */
-#define SOL_EBADMSG 77 /* Message was unreadable */
-#define SOL_ENAMETOOLONG 78 /* Too long of a path name */
-#define SOL_EOVERFLOW 79 /* Data type too small for datum */
-#define SOL_ENOTUNIQ 80 /* Logical name was not unique */
-#define SOL_EBADFD 81 /* Op cannot be performed on fd */
-#define SOL_EREMCHG 82 /* Remote address is now different */
-#define SOL_ELIBACC 83 /* Shared lib could not be accessed */
-#define SOL_ELIBBAD 84 /* ShLib is corrupted in some way */
-#define SOL_ELIBSCN 85 /* A.out ShLib problems */
-#define SOL_ELIBMAX 86 /* Exceeded ShLib linkage limit */
-#define SOL_ELIBEXEC 87 /* Execution of ShLib attempted */
-#define SOL_EILSEQ 88 /* Bad byte sequence found */
-#define SOL_ENOSYS 89 /* Invalid filesystem operation */
-#define SOL_ELOOP 90 /* Detected loop in symbolic links */
-#define SOL_ERESTART 91 /* System call is restartable */
-#define SOL_ESTRPIPE 92 /* Do not sleep in head of stream */
-#define SOL_ENOTEMPTY 93 /* Rmdir of non-empty directory */
-#define SOL_EUSERS 94 /* Over abundance of users for ufs */
-#define SOL_ENOTSOCK 95 /* Sock-op on non-sock */
-#define SOL_EDESTADDRREQ 96 /* No dest addr given, but needed */
-#define SOL_EMSGSIZE 97 /* Msg too big */
-#define SOL_EPROTOTYPE 98 /* Bad socket protocol */
-#define SOL_ENOPROTOOPT 99 /* Unavailable protocol */
-#define SOL_EPROTONOSUPPORT 120 /* Unsupported protocol */
-#define SOL_ESOCKTNOSUPPORT 121 /* Unsupported socket type */
-#define SOL_EOPNOTSUPP 122 /* Unsupported sock-op */
-#define SOL_EPFNOSUPPORT 123 /* Unsupported protocol family */
-#define SOL_EAFNOSUPPORT 124 /* Unsup addr family for protocol */
-#define SOL_EADDRINUSE 125 /* Req addr is already in use */
-#define SOL_EADDRNOTAVAIL 126 /* Req addr not available right now */
-#define SOL_ENETDOWN 127 /* Your subnet is on fire */
-#define SOL_ENETUNREACH 128 /* Someone playing with gateway and */
- /* did not tell you he was going to */
-#define SOL_ENETRESET 129 /* Buy less-buggy ethernet cards */
-#define SOL_ECONNABORTED 130 /* Aborted connection due to sw */
-#define SOL_ECONNRESET 131 /* Your peers reset your connection */
-#define SOL_ENOBUFS 132 /* No buffer space available */
-#define SOL_EISCONN 133 /* Connect on already connected */
- /* socket attempted */
-#define SOL_ENOTCONN 134 /* Comm on non-connected socket */
-#define SOL_ESHUTDOWN 143 /* Op attempted after sock-shutdown */
-#define SOL_ETOOMANYREFS 144 /* Reference limit exceeded */
-#define SOL_ETIMEDOUT 145 /* Timed out connection */
-#define SOL_ECONNREFUSED 146 /* Connection refused by remote host*/
-#define SOL_EHOSTDOWN 147 /* Remote host is up in flames */
-#define SOL_EHOSTUNREACH 148 /* Make a left at Easton Ave..... */
-#define SOL_EWOULDBLOCK EAGAIN /* Just an alias */
-#define SOL_EALREADY 149 /* Operation is already occurring */
-#define SOL_EINPROGRESS 150 /* Operation is happening now */
-#define SOL_ESTALE 151 /* Fungus growth on NFS file handle */
-
-#endif /* !(_SPARC64_SOLERRNO_H) */
+++ /dev/null
-/* Solaris/SPARC constants and definitions --
- * (C) 1996 Miguel de Icaza
- *
- * This file is not meant to be included by user level applications
- * but the solaris syscall emulator
- */
-
-#ifndef _SPARC64_SVR4_H
-#define _SPARC64_SVR4_H
-
-/* Signals as used by svr4 */
-typedef struct { /* signal set type */
- uint sigbits[4];
-} svr4_sigset_t;
-
-/* Values for siginfo.code */
-#define SVR4_SINOINFO 32767
-/* Siginfo, sucker expects bunch of information on those parameters */
-typedef union {
- char total_size [128];
- struct {
- int signo;
- int code;
- int error;
- union {
- } data;
- } siginfo;
-} svr4_siginfo_t;
-
-/* Context definition */
-
-/* Location of the user stored registers into a greg_t */
-enum {
- SVR4_PSR, SVR4_PC, SVR4_NPC, SVR4_Y,
- SVR4_G1, SVR4_G2, SVR4_G3, SVR4_G4,
- SVR4_G5, SVR4_G6, SVR4_G7, SVR4_O0,
- SVR4_O1, SVR4_O2, SVR4_O3, SVR4_O4,
- SVR4_O5, SVR4_O6, SVR4_O7
-};
-
-/* sizeof (regs) / sizeof (greg_t), defined in the ABI */
-#define SVR4_NREGS 19
-#define SVR4_MAXWIN 31
-
-typedef struct {
- u32 rwin_lo[8];
- u32 rwin_in[8];
-} svr4_rwindow_t;
-
-typedef struct {
- int count;
- u32 winptr [SVR4_MAXWIN]; /* pointer to the windows */
-
- svr4_rwindow_t win[SVR4_MAXWIN]; /* the windows */
-} svr4_gwindows_t;
-
-typedef int svr4_gregset_t[SVR4_NREGS];
-
-typedef struct {
- u64 fpu_regs[32];
- u32 fp_q;
- u32 fp_fsr;
- u_char fp_nqel;
- u_char fp_nqsize;
- u_char inuse; /* if fpu is in use */
-} svr4_fregset_t;
-
-typedef struct {
- u32 id; /* if this holds "xrs" string => ptr is valid */
- u32 ptr;
-} svr4_xrs_t;
-
-/* Machine dependent context */
-typedef struct {
- svr4_gregset_t greg; /* registers 0..19 (see top) */
- u32 gwin; /* may point to register windows */
- svr4_fregset_t freg; /* floating point registers */
- svr4_xrs_t xrs; /* mhm? */
- int pad[19];
-} svr4_mcontext_t;
-
-/* flags for stack_t.flags */
-enum svr4_stack_flags {
- SVR4_SS_ONSTACK,
- SVR4_SS_DISABLE,
-};
-
-/* signal stack execution place, unsupported */
-typedef struct svr4_stack_t {
- u32 sp;
- int size;
- int flags;
-} svr4_stack_t;
-
-/* Context used by getcontext and setcontext */
-typedef struct svr4_ucontext_t {
- u32 flags; /* context flags, indicate what is loaded */
- u32 link;
- svr4_sigset_t sigmask;
- svr4_stack_t stack;
- svr4_mcontext_t mcontext;
- int pad[23];
-} svr4_ucontext_t;
-
-/* windows hold the windows as they were at signal time,
- * ucontext->mcontext holds a pointer to them.
- * addresses for uc and si are passed as parameters to svr4 signal
- * handler
- */
-
-/* This is the signal frame that is passed to the signal handler */
-typedef struct {
- svr4_gwindows_t gw; /* windows */
- svr4_ucontext_t uc; /* machine context */
- svr4_siginfo_t si; /* siginfo */
-} svr4_signal_frame_t;
-
-#define SVR4_SF_ALIGNED (((sizeof (svr4_signal_frame_t) + 7) & (~7)))
-
-#endif /* include control */
};
#endif /* __KERNEL__ */
-struct sunos_ttysize {
- int st_lines; /* Lines on the terminal */
- int st_columns; /* Columns on the terminal */
-};
-
struct winsize {
unsigned short ws_row;
unsigned short ws_col;
or %l7, %lo(systbl), %l7; \
nop; nop;
-#define INDIRECT_SOLARIS_SYSCALL(num) \
- sethi %hi(109f), %g7; \
- ba,pt %xcc, etrap; \
-109: or %g7, %lo(109b), %g7; \
- ba,pt %xcc, tl0_solaris + 0xc; \
- mov num, %g1; \
- nop;nop;nop;
-
#define TRAP_UTRAP(handler,lvl) \
mov handler, %g3; \
ba,pt %xcc, utrap_trap; \
nop; \
nop;
-#ifdef CONFIG_SUNOS_EMUL
-#define SUNOS_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall32, sunos_sys_table)
-#else
-#define SUNOS_SYSCALL_TRAP TRAP(sunos_syscall)
-#endif
#ifdef CONFIG_COMPAT
#define LINUX_32BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall32, sys_call_table32)
#else
#define LINUX_64BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall, sys_call_table64)
#define GETCC_TRAP TRAP(getcc)
#define SETCC_TRAP TRAP(setcc)
-#ifdef CONFIG_SOLARIS_EMUL
-#define SOLARIS_SYSCALL_TRAP TRAP(solaris_sparc_syscall)
-#else
-#define SOLARIS_SYSCALL_TRAP TRAP(solaris_syscall)
-#endif
#define BREAKPOINT_TRAP TRAP(breakpoint_trap)
#ifdef CONFIG_TRACE_IRQFLAGS
#define NR_SYSCALLS 317
#ifdef __KERNEL__
-/* sysconf options, for SunOS compatibility */
-#define _SC_ARG_MAX 1
-#define _SC_CHILD_MAX 2
-#define _SC_CLK_TCK 3
-#define _SC_NGROUPS_MAX 4
-#define _SC_OPEN_MAX 5
-#define _SC_JOB_CONTROL 6
-#define _SC_SAVED_IDS 7
-#define _SC_VERSION 8
-
#define __ARCH_WANT_IPC_PARSE_VERSION
#define __ARCH_WANT_OLD_READDIR
#define __ARCH_WANT_STAT64
-/* $Id: user.h,v 1.1 1996/12/26 14:22:44 davem Exp $
- * asm-sparc64/user.h: Core file definitions for the Sparc.
- *
- * Keep in sync with reg.h. Actually, we could get rid of this
- * one, since we won't a.out core dump that much anyways - miguel.
- * Copyright (C) 1995 (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC64_USER_H
-#define _SPARC64_USER_H
-
-#include <linux/a.out.h>
-struct sunos_regs {
- unsigned int psr, pc, npc, y;
- unsigned int regs[15];
-};
-
-struct sunos_fpqueue {
- unsigned int *addr;
- unsigned int inst;
-};
-
-struct sunos_fp {
- union {
- unsigned int regs[32];
- double reg_dbls[16];
- } fregs;
- unsigned int fsr;
- unsigned int flags;
- unsigned int extra;
- unsigned int fpq_count;
- struct sunos_fpqueue fpq[16];
-};
-
-struct sunos_fpu {
- struct sunos_fp fpstatus;
-};
-
-/* The SunOS core file header layout. */
-struct user {
- unsigned int magic;
- unsigned int len;
- struct sunos_regs regs;
- struct exec uexec;
- int signal;
- size_t u_tsize; /* all of these in bytes! */
- size_t u_dsize;
- size_t u_ssize;
- char u_comm[17];
- struct sunos_fpu fpu;
- unsigned int sigcode; /* Special sigcontext subcode, if any */
-};
-
-#define NBPG PAGE_SIZE /* XXX 4096 maybe? */
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_DATA_START_ADDR (u.start_data)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-#define SUNOS_CORE_MAGIC 0x080456
-
-#endif /* !(_SPARC64_USER_H) */
+#include <asm-sparc/user.h>
+ (CONFIG_PHYSICAL_ALIGN - 1)) \
& ~(CONFIG_PHYSICAL_ALIGN - 1))
+#ifdef CONFIG_X86_64
+#define BOOT_HEAP_SIZE 0x7000
+#define BOOT_STACK_SIZE 0x4000
+#else
+#define BOOT_HEAP_SIZE 0x4000
+#define BOOT_STACK_SIZE 0x1000
+#endif
+
#endif /* _ASM_BOOT_H */
+#ifndef _ASM_DMA_MAPPING_H_
+#define _ASM_DMA_MAPPING_H_
+
+/*
+ * IOMMU interface. See Documentation/DMA-mapping.txt and DMA-API.txt for
+ * documentation.
+ */
+
+#include <linux/scatterlist.h>
+#include <asm/io.h>
+#include <asm/swiotlb.h>
+
+extern dma_addr_t bad_dma_address;
+extern int iommu_merge;
+extern struct device fallback_dev;
+extern int panic_on_overflow;
+extern int forbid_dac;
+extern int force_iommu;
+
+struct dma_mapping_ops {
+ int (*mapping_error)(dma_addr_t dma_addr);
+ void* (*alloc_coherent)(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t gfp);
+ void (*free_coherent)(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle);
+ dma_addr_t (*map_single)(struct device *hwdev, phys_addr_t ptr,
+ size_t size, int direction);
+ /* like map_single, but doesn't check the device mask */
+ dma_addr_t (*map_simple)(struct device *hwdev, phys_addr_t ptr,
+ size_t size, int direction);
+ void (*unmap_single)(struct device *dev, dma_addr_t addr,
+ size_t size, int direction);
+ void (*sync_single_for_cpu)(struct device *hwdev,
+ dma_addr_t dma_handle, size_t size,
+ int direction);
+ void (*sync_single_for_device)(struct device *hwdev,
+ dma_addr_t dma_handle, size_t size,
+ int direction);
+ void (*sync_single_range_for_cpu)(struct device *hwdev,
+ dma_addr_t dma_handle, unsigned long offset,
+ size_t size, int direction);
+ void (*sync_single_range_for_device)(struct device *hwdev,
+ dma_addr_t dma_handle, unsigned long offset,
+ size_t size, int direction);
+ void (*sync_sg_for_cpu)(struct device *hwdev,
+ struct scatterlist *sg, int nelems,
+ int direction);
+ void (*sync_sg_for_device)(struct device *hwdev,
+ struct scatterlist *sg, int nelems,
+ int direction);
+ int (*map_sg)(struct device *hwdev, struct scatterlist *sg,
+ int nents, int direction);
+ void (*unmap_sg)(struct device *hwdev,
+ struct scatterlist *sg, int nents,
+ int direction);
+ int (*dma_supported)(struct device *hwdev, u64 mask);
+ int is_phys;
+};
+
+extern const struct dma_mapping_ops *dma_ops;
+
+static inline int dma_mapping_error(dma_addr_t dma_addr)
+{
+ if (dma_ops->mapping_error)
+ return dma_ops->mapping_error(dma_addr);
+
+ return (dma_addr == bad_dma_address);
+}
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+
+void *dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag);
+
+void dma_free_coherent(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle);
+
+
+extern int dma_supported(struct device *hwdev, u64 mask);
+extern int dma_set_mask(struct device *dev, u64 mask);
+
+static inline dma_addr_t
+dma_map_single(struct device *hwdev, void *ptr, size_t size,
+ int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ return dma_ops->map_single(hwdev, virt_to_phys(ptr), size, direction);
+}
+
+static inline void
+dma_unmap_single(struct device *dev, dma_addr_t addr, size_t size,
+ int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ if (dma_ops->unmap_single)
+ dma_ops->unmap_single(dev, addr, size, direction);
+}
+
+static inline int
+dma_map_sg(struct device *hwdev, struct scatterlist *sg,
+ int nents, int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ return dma_ops->map_sg(hwdev, sg, nents, direction);
+}
+
+static inline void
+dma_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nents,
+ int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ if (dma_ops->unmap_sg)
+ dma_ops->unmap_sg(hwdev, sg, nents, direction);
+}
+
+static inline void
+dma_sync_single_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
+ size_t size, int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ if (dma_ops->sync_single_for_cpu)
+ dma_ops->sync_single_for_cpu(hwdev, dma_handle, size,
+ direction);
+ flush_write_buffers();
+}
+
+static inline void
+dma_sync_single_for_device(struct device *hwdev, dma_addr_t dma_handle,
+ size_t size, int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ if (dma_ops->sync_single_for_device)
+ dma_ops->sync_single_for_device(hwdev, dma_handle, size,
+ direction);
+ flush_write_buffers();
+}
+
+static inline void
+dma_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
+ unsigned long offset, size_t size, int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ if (dma_ops->sync_single_range_for_cpu)
+ dma_ops->sync_single_range_for_cpu(hwdev, dma_handle, offset,
+ size, direction);
+
+ flush_write_buffers();
+}
+
+static inline void
+dma_sync_single_range_for_device(struct device *hwdev, dma_addr_t dma_handle,
+ unsigned long offset, size_t size,
+ int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ if (dma_ops->sync_single_range_for_device)
+ dma_ops->sync_single_range_for_device(hwdev, dma_handle,
+ offset, size, direction);
+
+ flush_write_buffers();
+}
+
+static inline void
+dma_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
+ int nelems, int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ if (dma_ops->sync_sg_for_cpu)
+ dma_ops->sync_sg_for_cpu(hwdev, sg, nelems, direction);
+ flush_write_buffers();
+}
+
+static inline void
+dma_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
+ int nelems, int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ if (dma_ops->sync_sg_for_device)
+ dma_ops->sync_sg_for_device(hwdev, sg, nelems, direction);
+
+ flush_write_buffers();
+}
+
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+ size_t offset, size_t size,
+ int direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+ return dma_ops->map_single(dev, page_to_phys(page)+offset,
+ size, direction);
+}
+
+static inline void dma_unmap_page(struct device *dev, dma_addr_t addr,
+ size_t size, int direction)
+{
+ dma_unmap_single(dev, addr, size, direction);
+}
+
+static inline void
+dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+ enum dma_data_direction dir)
+{
+ flush_write_buffers();
+}
+
+static inline int dma_get_cache_alignment(void)
+{
+ /* no easy way to get cache size on all x86, so return the
+ * maximum possible, to be safe */
+ return boot_cpu_data.x86_clflush_size;
+}
+
+#define dma_is_consistent(d, h) (1)
+
#ifdef CONFIG_X86_32
-# include "dma-mapping_32.h"
-#else
-# include "dma-mapping_64.h"
+# define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
+struct dma_coherent_mem {
+ void *virt_base;
+ u32 device_base;
+ int size;
+ int flags;
+ unsigned long *bitmap;
+};
+
+extern int
+dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+ dma_addr_t device_addr, size_t size, int flags);
+
+extern void
+dma_release_declared_memory(struct device *dev);
+
+extern void *
+dma_mark_declared_memory_occupied(struct device *dev,
+ dma_addr_t device_addr, size_t size);
+#endif /* CONFIG_X86_32 */
#endif
+++ /dev/null
-#ifndef _ASM_I386_DMA_MAPPING_H
-#define _ASM_I386_DMA_MAPPING_H
-
-#include <linux/mm.h>
-#include <linux/scatterlist.h>
-
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <asm/bug.h>
-
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-
-void *dma_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t flag);
-
-void dma_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle);
-
-static inline dma_addr_t
-dma_map_single(struct device *dev, void *ptr, size_t size,
- enum dma_data_direction direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- WARN_ON(size == 0);
- flush_write_buffers();
- return virt_to_phys(ptr);
-}
-
-static inline void
-dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
- enum dma_data_direction direction)
-{
- BUG_ON(!valid_dma_direction(direction));
-}
-
-static inline int
-dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
- enum dma_data_direction direction)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(!valid_dma_direction(direction));
- WARN_ON(nents == 0 || sglist[0].length == 0);
-
- for_each_sg(sglist, sg, nents, i) {
- BUG_ON(!sg_page(sg));
-
- sg->dma_address = sg_phys(sg);
- }
-
- flush_write_buffers();
- return nents;
-}
-
-static inline dma_addr_t
-dma_map_page(struct device *dev, struct page *page, unsigned long offset,
- size_t size, enum dma_data_direction direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- return page_to_phys(page) + offset;
-}
-
-static inline void
-dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
- enum dma_data_direction direction)
-{
- BUG_ON(!valid_dma_direction(direction));
-}
-
-
-static inline void
-dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
- enum dma_data_direction direction)
-{
- BUG_ON(!valid_dma_direction(direction));
-}
-
-static inline void
-dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction)
-{
-}
-
-static inline void
-dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-static inline void
-dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
- unsigned long offset, size_t size,
- enum dma_data_direction direction)
-{
-}
-
-static inline void
-dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
- unsigned long offset, size_t size,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-static inline void
-dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
-{
-}
-
-static inline void
-dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-static inline int
-dma_mapping_error(dma_addr_t dma_addr)
-{
- return 0;
-}
-
-extern int forbid_dac;
-
-static inline int
-dma_supported(struct device *dev, u64 mask)
-{
- /*
- * we fall back to GFP_DMA when the mask isn't all 1s,
- * so we can't guarantee allocations that must be
- * within a tighter range than GFP_DMA..
- */
- if(mask < 0x00ffffff)
- return 0;
-
- /* Work around chipset bugs */
- if (forbid_dac > 0 && mask > 0xffffffffULL)
- return 0;
-
- return 1;
-}
-
-static inline int
-dma_set_mask(struct device *dev, u64 mask)
-{
- if(!dev->dma_mask || !dma_supported(dev, mask))
- return -EIO;
-
- *dev->dma_mask = mask;
-
- return 0;
-}
-
-static inline int
-dma_get_cache_alignment(void)
-{
- /* no easy way to get cache size on all x86, so return the
- * maximum possible, to be safe */
- return (1 << INTERNODE_CACHE_SHIFT);
-}
-
-#define dma_is_consistent(d, h) (1)
-
-static inline void
-dma_cache_sync(struct device *dev, void *vaddr, size_t size,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
-extern int
-dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
- dma_addr_t device_addr, size_t size, int flags);
-
-extern void
-dma_release_declared_memory(struct device *dev);
-
-extern void *
-dma_mark_declared_memory_occupied(struct device *dev,
- dma_addr_t device_addr, size_t size);
-
-#endif
+++ /dev/null
-#ifndef _X8664_DMA_MAPPING_H
-#define _X8664_DMA_MAPPING_H 1
-
-/*
- * IOMMU interface. See Documentation/DMA-mapping.txt and DMA-API.txt for
- * documentation.
- */
-
-#include <linux/scatterlist.h>
-#include <asm/io.h>
-#include <asm/swiotlb.h>
-
-struct dma_mapping_ops {
- int (*mapping_error)(dma_addr_t dma_addr);
- void* (*alloc_coherent)(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp);
- void (*free_coherent)(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle);
- dma_addr_t (*map_single)(struct device *hwdev, void *ptr,
- size_t size, int direction);
- /* like map_single, but doesn't check the device mask */
- dma_addr_t (*map_simple)(struct device *hwdev, char *ptr,
- size_t size, int direction);
- void (*unmap_single)(struct device *dev, dma_addr_t addr,
- size_t size, int direction);
- void (*sync_single_for_cpu)(struct device *hwdev,
- dma_addr_t dma_handle, size_t size,
- int direction);
- void (*sync_single_for_device)(struct device *hwdev,
- dma_addr_t dma_handle, size_t size,
- int direction);
- void (*sync_single_range_for_cpu)(struct device *hwdev,
- dma_addr_t dma_handle, unsigned long offset,
- size_t size, int direction);
- void (*sync_single_range_for_device)(struct device *hwdev,
- dma_addr_t dma_handle, unsigned long offset,
- size_t size, int direction);
- void (*sync_sg_for_cpu)(struct device *hwdev,
- struct scatterlist *sg, int nelems,
- int direction);
- void (*sync_sg_for_device)(struct device *hwdev,
- struct scatterlist *sg, int nelems,
- int direction);
- int (*map_sg)(struct device *hwdev, struct scatterlist *sg,
- int nents, int direction);
- void (*unmap_sg)(struct device *hwdev,
- struct scatterlist *sg, int nents,
- int direction);
- int (*dma_supported)(struct device *hwdev, u64 mask);
- int is_phys;
-};
-
-extern dma_addr_t bad_dma_address;
-extern const struct dma_mapping_ops* dma_ops;
-extern int iommu_merge;
-
-static inline int dma_mapping_error(dma_addr_t dma_addr)
-{
- if (dma_ops->mapping_error)
- return dma_ops->mapping_error(dma_addr);
-
- return (dma_addr == bad_dma_address);
-}
-
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-
-extern void *dma_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp);
-extern void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
- dma_addr_t dma_handle);
-
-static inline dma_addr_t
-dma_map_single(struct device *hwdev, void *ptr, size_t size,
- int direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- return dma_ops->map_single(hwdev, ptr, size, direction);
-}
-
-static inline void
-dma_unmap_single(struct device *dev, dma_addr_t addr,size_t size,
- int direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- dma_ops->unmap_single(dev, addr, size, direction);
-}
-
-#define dma_map_page(dev,page,offset,size,dir) \
- dma_map_single((dev), page_address(page)+(offset), (size), (dir))
-
-#define dma_unmap_page dma_unmap_single
-
-static inline void
-dma_sync_single_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
- size_t size, int direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- if (dma_ops->sync_single_for_cpu)
- dma_ops->sync_single_for_cpu(hwdev, dma_handle, size,
- direction);
- flush_write_buffers();
-}
-
-static inline void
-dma_sync_single_for_device(struct device *hwdev, dma_addr_t dma_handle,
- size_t size, int direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- if (dma_ops->sync_single_for_device)
- dma_ops->sync_single_for_device(hwdev, dma_handle, size,
- direction);
- flush_write_buffers();
-}
-
-static inline void
-dma_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
- unsigned long offset, size_t size, int direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- if (dma_ops->sync_single_range_for_cpu) {
- dma_ops->sync_single_range_for_cpu(hwdev, dma_handle, offset, size, direction);
- }
-
- flush_write_buffers();
-}
-
-static inline void
-dma_sync_single_range_for_device(struct device *hwdev, dma_addr_t dma_handle,
- unsigned long offset, size_t size, int direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- if (dma_ops->sync_single_range_for_device)
- dma_ops->sync_single_range_for_device(hwdev, dma_handle,
- offset, size, direction);
-
- flush_write_buffers();
-}
-
-static inline void
-dma_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
- int nelems, int direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- if (dma_ops->sync_sg_for_cpu)
- dma_ops->sync_sg_for_cpu(hwdev, sg, nelems, direction);
- flush_write_buffers();
-}
-
-static inline void
-dma_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
- int nelems, int direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- if (dma_ops->sync_sg_for_device) {
- dma_ops->sync_sg_for_device(hwdev, sg, nelems, direction);
- }
-
- flush_write_buffers();
-}
-
-static inline int
-dma_map_sg(struct device *hwdev, struct scatterlist *sg, int nents, int direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- return dma_ops->map_sg(hwdev, sg, nents, direction);
-}
-
-static inline void
-dma_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nents,
- int direction)
-{
- BUG_ON(!valid_dma_direction(direction));
- dma_ops->unmap_sg(hwdev, sg, nents, direction);
-}
-
-extern int dma_supported(struct device *hwdev, u64 mask);
-
-/* same for gart, swiotlb, and nommu */
-static inline int dma_get_cache_alignment(void)
-{
- return boot_cpu_data.x86_clflush_size;
-}
-
-#define dma_is_consistent(d, h) 1
-
-extern int dma_set_mask(struct device *dev, u64 mask);
-
-static inline void
-dma_cache_sync(struct device *dev, void *vaddr, size_t size,
- enum dma_data_direction dir)
-{
- flush_write_buffers();
-}
-
-extern struct device fallback_dev;
-extern int panic_on_overflow;
-
-#endif /* _X8664_DMA_MAPPING_H */
extern int e820_all_mapped(unsigned long start, unsigned long end,
unsigned type);
extern int e820_any_mapped(u64 start, u64 end, unsigned type);
-extern void find_max_pfn(void);
+extern void propagate_e820_map(void);
extern void register_bootmem_low_pages(unsigned long max_low_pfn);
extern void add_memory_region(unsigned long long start,
unsigned long long size, int type);
enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};
#define get_uv_system_type() UV_NONE
#define is_uv_system() 0
+#define uv_wakeup_secondary(a, b) 1
#endif
extern void fpu_init(void);
extern void mxcsr_feature_mask_init(void);
-extern void init_fpu(struct task_struct *child);
+extern int init_fpu(struct task_struct *child);
extern asmlinkage void math_state_restore(void);
+extern void init_thread_xstate(void);
extern user_regset_active_fn fpregs_active, xfpregs_active;
extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
/* Using "fxsaveq %0" would be the ideal choice, but is only supported
starting with gas 2.16. */
__asm__ __volatile__("fxsaveq %0"
- : "=m" (tsk->thread.i387.fxsave));
+ : "=m" (tsk->thread.xstate->fxsave));
#elif 0
/* Using, as a workaround, the properly prefixed form below isn't
accepted by any binutils version so far released, complaining that
the same type of prefix is used twice if an extended register is
needed for addressing (fix submitted to mainline 2005-11-21). */
__asm__ __volatile__("rex64/fxsave %0"
- : "=m" (tsk->thread.i387.fxsave));
+ : "=m" (tsk->thread.xstate->fxsave));
#else
/* This, however, we can work around by forcing the compiler to select
an addressing mode that doesn't require extended registers. */
- __asm__ __volatile__("rex64/fxsave %P2(%1)"
- : "=m" (tsk->thread.i387.fxsave)
- : "cdaSDb" (tsk),
- "i" (offsetof(__typeof__(*tsk),
- thread.i387.fxsave)));
+ __asm__ __volatile__("rex64/fxsave (%1)"
+ : "=m" (tsk->thread.xstate->fxsave)
+ : "cdaSDb" (&tsk->thread.xstate->fxsave));
#endif
- clear_fpu_state(&tsk->thread.i387.fxsave);
+ clear_fpu_state(&tsk->thread.xstate->fxsave);
task_thread_info(tsk)->status &= ~TS_USEDFPU;
}
int err = 0;
BUILD_BUG_ON(sizeof(struct user_i387_struct) !=
- sizeof(tsk->thread.i387.fxsave));
+ sizeof(tsk->thread.xstate->fxsave));
if ((unsigned long)buf % 16)
printk("save_i387: bad fpstate %p\n", buf);
task_thread_info(tsk)->status &= ~TS_USEDFPU;
stts();
} else {
- if (__copy_to_user(buf, &tsk->thread.i387.fxsave,
+ if (__copy_to_user(buf, &tsk->thread.xstate->fxsave,
sizeof(struct i387_fxsave_struct)))
return -1;
}
"nop ; frstor %1",
"fxrstor %1",
X86_FEATURE_FXSR,
- "m" ((tsk)->thread.i387.fxsave));
+ "m" (tsk->thread.xstate->fxsave));
}
/* We need a safe address that is cheap to find and that is already
"fxsave %[fx]\n"
"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
X86_FEATURE_FXSR,
- [fx] "m" (tsk->thread.i387.fxsave),
- [fsw] "m" (tsk->thread.i387.fxsave.swd) : "memory");
+ [fx] "m" (tsk->thread.xstate->fxsave),
+ [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
is pending. Clear the x87 state here by setting it to fixed
values. safe_address is a random variable that should be in L1 */
static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
{
if (cpu_has_fxsr) {
- return tsk->thread.i387.fxsave.cwd;
+ return tsk->thread.xstate->fxsave.cwd;
} else {
- return (unsigned short)tsk->thread.i387.fsave.cwd;
+ return (unsigned short)tsk->thread.xstate->fsave.cwd;
}
}
static inline unsigned short get_fpu_swd(struct task_struct *tsk)
{
if (cpu_has_fxsr) {
- return tsk->thread.i387.fxsave.swd;
+ return tsk->thread.xstate->fxsave.swd;
} else {
- return (unsigned short)tsk->thread.i387.fsave.swd;
+ return (unsigned short)tsk->thread.xstate->fsave.swd;
}
}
static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
{
if (cpu_has_xmm) {
- return tsk->thread.i387.fxsave.mxcsr;
+ return tsk->thread.xstate->fxsave.mxcsr;
} else {
return MXCSR_DEFAULT;
}
u64 end;
};
-extern int compute_hash_shift(struct bootnode *nodes, int numnodes);
+extern int compute_hash_shift(struct bootnode *nodes, int numblks,
+ int *nodeids);
#define ZONE_ALIGN (1UL << (MAX_ORDER+PAGE_SHIFT))
extern int (*pci_config_write)(int seg, int bus, int dev, int fn,
int reg, int len, u32 value);
+extern void dma32_reserve_bootmem(void);
extern void pci_iommu_alloc(void);
/* The PCI address space does equal the physical memory
u32 entry_eip;
};
-union i387_union {
+union thread_xstate {
struct i387_fsave_struct fsave;
struct i387_fxsave_struct fxsave;
struct i387_soft_struct soft;
#endif
extern void print_cpu_info(struct cpuinfo_x86 *);
+extern unsigned int xstate_size;
+extern void free_thread_xstate(struct task_struct *);
+extern struct kmem_cache *task_xstate_cachep;
extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
extern unsigned short num_cache_leaves;
unsigned long cr2;
unsigned long trap_no;
unsigned long error_code;
- /* Floating point info: */
- union i387_union i387 __attribute__((aligned(16)));;
+ /* floating point and extended processor state */
+ union thread_xstate *xstate;
#ifdef CONFIG_X86_32
/* Virtual 86 mode info */
struct vm86_struct __user *vm86_info;
#define KSTK_EIP(task) (task_pt_regs(task)->ip)
+/* Get/set a process' ability to use the timestamp counter instruction */
+#define GET_TSC_CTL(adr) get_tsc_mode((adr))
+#define SET_TSC_CTL(val) set_tsc_mode((val))
+
+extern int get_tsc_mode(unsigned long adr);
+extern int set_tsc_mode(unsigned int val);
+
#endif
unsigned int offset;
unsigned int length;
dma_addr_t dma_address;
-#ifdef CONFIG_X86_64
unsigned int dma_length;
-#endif
};
#define ARCH_HAS_SG_CHAIN
+#ifndef _ASM_X86_THREAD_INFO_H
#ifdef CONFIG_X86_32
# include "thread_info_32.h"
#else
# include "thread_info_64.h"
#endif
+
+#ifndef __ASSEMBLY__
+extern void arch_task_cache_init(void);
+extern void free_thread_info(struct thread_info *ti);
+extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
+#define arch_task_cache_init arch_task_cache_init
+#endif
+#endif /* _ASM_X86_THREAD_INFO_H */
__get_free_pages(GFP_KERNEL, get_order(THREAD_SIZE)))
#endif
-#define free_thread_info(info) free_pages((unsigned long)(info), get_order(THREAD_SIZE))
-
#else /* !__ASSEMBLY__ */
/* how to get the thread information struct from ASM */
#define alloc_thread_info(tsk) \
((struct thread_info *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER))
-#define free_thread_info(ti) free_pages((unsigned long) (ti), THREAD_ORDER)
-
#else /* !__ASSEMBLY__ */
/* how to get the thread information struct from ASM */
#define TIF_DEBUGCTLMSR 25 /* uses thread_struct.debugctlmsr */
#define TIF_DS_AREA_MSR 26 /* uses thread_struct.ds_area_msr */
#define TIF_BTS_TRACE_TS 27 /* record scheduling event timestamps */
+#define TIF_NOTSC 28 /* TSC is not accessible in userland */
#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
#define _TIF_DEBUGCTLMSR (1 << TIF_DEBUGCTLMSR)
#define _TIF_DS_AREA_MSR (1 << TIF_DS_AREA_MSR)
#define _TIF_BTS_TRACE_TS (1 << TIF_BTS_TRACE_TS)
+#define _TIF_NOTSC (1 << TIF_NOTSC)
/* work to do on interrupt/exception return */
#define _TIF_WORK_MASK \
/* flags to check in __switch_to() */
#define _TIF_WORK_CTXSW \
- (_TIF_IO_BITMAP|_TIF_DEBUGCTLMSR|_TIF_DS_AREA_MSR|_TIF_BTS_TRACE_TS)
+ (_TIF_IO_BITMAP|_TIF_DEBUGCTLMSR|_TIF_DS_AREA_MSR|_TIF_BTS_TRACE_TS|_TIF_NOTSC)
#define _TIF_WORK_CTXSW_PREV _TIF_WORK_CTXSW
#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW|_TIF_DEBUG)
#endif
return per_cpu(x86_cpu_to_node_map, cpu);
}
+
+#ifdef CONFIG_NUMA
+
+/* Returns a pointer to the cpumask of CPUs on Node 'node'. */
+#define node_to_cpumask_ptr(v, node) \
+ cpumask_t *v = &(node_to_cpumask_map[node])
+
+#define node_to_cpumask_ptr_next(v, node) \
+ v = &(node_to_cpumask_map[node])
+#endif
+
#endif /* CONFIG_X86_64 */
/*
# define SD_CACHE_NICE_TRIES 2
# define SD_IDLE_IDX 2
-# define SD_NEWIDLE_IDX 0
+# define SD_NEWIDLE_IDX 2
# define SD_FORKEXEC_IDX 1
#endif
/* sched_domains SD_NODE_INIT for NUMAQ machines */
#define SD_NODE_INIT (struct sched_domain) { \
- .span = CPU_MASK_NONE, \
- .parent = NULL, \
- .child = NULL, \
- .groups = NULL, \
.min_interval = 8, \
.max_interval = 32, \
.busy_factor = 32, \
| SD_WAKE_BALANCE, \
.last_balance = jiffies, \
.balance_interval = 1, \
- .nr_balance_failed = 0, \
}
#ifdef CONFIG_X86_64_ACPI_NUMA
#else /* CONFIG_NUMA */
-#include <asm-generic/topology.h>
-
#endif
+#include <asm-generic/topology.h>
+
extern cpumask_t cpu_coregroup_map(int cpu);
#ifdef ENABLE_TOPO_DEFINES
extern unsigned int tsc_khz;
extern void disable_TSC(void);
+extern void enable_TSC(void);
static inline cycles_t get_cycles(void)
{
#define AES_KEYSIZE_192 24
#define AES_KEYSIZE_256 32
#define AES_BLOCK_SIZE 16
+#define AES_MAX_KEYLENGTH (15 * 16)
+#define AES_MAX_KEYLENGTH_U32 (AES_MAX_KEYLENGTH / sizeof(u32))
struct crypto_aes_ctx {
u32 key_length;
- u32 key_enc[60];
- u32 key_dec[60];
+ u32 key_enc[AES_MAX_KEYLENGTH_U32];
+ u32 key_dec[AES_MAX_KEYLENGTH_U32];
};
extern u32 crypto_ft_tab[4][256];
int crypto_aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
unsigned int key_len);
+int crypto_aes_expand_key(struct crypto_aes_ctx *ctx, const u8 *in_key,
+ unsigned int key_len);
#endif
extern struct key *rxrpc_get_null_key(const char *);
-#endif /* _KEYS_USER_TYPE_H */
+#endif /* _KEYS_RXRPC_TYPE_H */
header-y += jffs2.h
header-y += keyctl.h
header-y += limits.h
-header-y += lock_dlm_plock.h
+header-y += dlm_plock.h
header-y += magic.h
header-y += major.h
header-y += matroxfb.h
header-y += tipc.h
header-y += tipc_config.h
header-y += toshiba.h
+header-y += udf_fs_i.h
header-y += ultrasound.h
header-y += un.h
header-y += utime.h
unifdef-y += hdlc.h
unifdef-y += hdreg.h
unifdef-y += hdsmart.h
+unifdef-y += hid.h
unifdef-y += hiddev.h
+unifdef-y += hidraw.h
unifdef-y += hpet.h
unifdef-y += i2c.h
unifdef-y += i2c-dev.h
unifdef-y += timex.h
unifdef-y += tty.h
unifdef-y += types.h
-unifdef-y += udf_fs_i.h
unifdef-y += udp.h
unifdef-y += uinput.h
unifdef-y += uio.h
extern int pci_find_aer_capability(struct pci_dev *dev);
extern int pci_disable_pcie_error_reporting(struct pci_dev *dev);
extern int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
-extern int pci_cleanup_aer_correct_error_status(struct pci_dev *dev);
#else
static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev)
{
{
return -EINVAL;
}
-static inline int pci_cleanup_aer_correct_error_status(struct pci_dev *dev)
-{
- return -EINVAL;
-}
#endif
#endif //_AER_H_
/*
* Marvell SATA private data
*/
+struct mbus_dram_target_info;
+
struct mv_sata_platform_data {
+ struct mbus_dram_target_info *dram;
int n_ports; /* number of sata ports */
};
--- /dev/null
+/*
+ * Timer/Counter Unit (TC) registers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef ATMEL_TC_H
+#define ATMEL_TC_H
+
+#include <linux/compiler.h>
+#include <linux/list.h>
+
+/*
+ * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
+ * three general-purpose 16-bit timers. These timers share one register bank.
+ * Depending on the SOC, each timer may have its own clock and IRQ, or those
+ * may be shared by the whole TC block.
+ *
+ * These TC blocks may have up to nine external pins: TCLK0..2 signals for
+ * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
+ * or triggering. Those pins need to be set up for use with the TC block,
+ * else they will be used as GPIOs or for a different controller.
+ *
+ * Although we expect each TC block to have a platform_device node, those
+ * nodes are not what drivers bind to. Instead, they ask for a specific
+ * TC block, by number ... which is a common approach on systems with many
+ * timers. Then they use clk_get() and platform_get_irq() to get clock and
+ * IRQ resources.
+ */
+
+struct clk;
+
+/**
+ * struct atmel_tc - information about a Timer/Counter Block
+ * @pdev: physical device
+ * @iomem: resource associated with the I/O register
+ * @regs: mapping through which the I/O registers can be accessed
+ * @irq: irq for each of the three channels
+ * @clk: internal clock source for each of the three channels
+ * @node: list node, for tclib internal use
+ *
+ * On some platforms, each TC channel has its own clocks and IRQs,
+ * while on others, all TC channels share the same clock and IRQ.
+ * Drivers should clk_enable() all the clocks they need even though
+ * all the entries in @clk may point to the same physical clock.
+ * Likewise, drivers should request irqs independently for each
+ * channel, but they must use IRQF_SHARED in case some of the entries
+ * in @irq are actually the same IRQ.
+ */
+struct atmel_tc {
+ struct platform_device *pdev;
+ struct resource *iomem;
+ void __iomem *regs;
+ int irq[3];
+ struct clk *clk[3];
+ struct list_head node;
+};
+
+extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
+extern void atmel_tc_free(struct atmel_tc *tc);
+
+/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
+extern const u8 atmel_tc_divisors[5];
+
+
+/*
+ * Two registers have block-wide controls. These are: configuring the three
+ * "external" clocks (or event sources) used by the timer channels; and
+ * synchronizing the timers by resetting them all at once.
+ *
+ * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
+ * signals. Or, it can mean "external to timer", using the TIOA output from
+ * one of the other two timers that's being run in waveform mode.
+ */
+
+#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
+#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
+
+#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
+#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
+#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
+#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
+#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
+#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
+#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
+#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
+#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
+#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
+#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
+#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
+#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
+#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
+#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
+#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
+
+
+/*
+ * Each TC block has three "channels", each with one counter and controls.
+ *
+ * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
+ * when it's not "external") is silicon-specific. AT91 platforms use one
+ * set of definitions; AVR32 platforms use a different set. Don't hard-wire
+ * such knowledge into your code, use the global "atmel_tc_divisors" ...
+ * where index N is the divisor for clock N+1, else zero to indicate it uses
+ * the 32 KiHz clock.
+ *
+ * The timers can be chained in various ways, and operated in "waveform"
+ * generation mode (including PWM) or "capture" mode (to time events). In
+ * both modes, behavior can be configured in many ways.
+ *
+ * Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
+ * PWM output, and TIOB as either another PWM or as a trigger. Capture mode
+ * uses them only as inputs.
+ */
+#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
+#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
+
+#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
+#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
+#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
+#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
+
+#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
+
+/* Both modes share some CMR bits */
+#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
+#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
+#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
+#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
+#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
+#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
+#define ATMEL_TC_XC0 (5 << 0)
+#define ATMEL_TC_XC1 (6 << 0)
+#define ATMEL_TC_XC2 (7 << 0)
+#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
+#define ATMEL_TC_BURST (3 << 4) /* clock gating */
+#define ATMEL_TC_GATE_NONE (0 << 4)
+#define ATMEL_TC_GATE_XC0 (1 << 4)
+#define ATMEL_TC_GATE_XC1 (2 << 4)
+#define ATMEL_TC_GATE_XC2 (3 << 4)
+#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
+
+/* CAPTURE mode CMR bits */
+#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
+#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
+#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
+#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
+#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
+#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
+#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
+#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
+#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
+#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
+#define ATMEL_TC_LDRA_NONE (0 << 16)
+#define ATMEL_TC_LDRA_RISING (1 << 16)
+#define ATMEL_TC_LDRA_FALLING (2 << 16)
+#define ATMEL_TC_LDRA_BOTH (3 << 16)
+#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
+#define ATMEL_TC_LDRB_NONE (0 << 18)
+#define ATMEL_TC_LDRB_RISING (1 << 18)
+#define ATMEL_TC_LDRB_FALLING (2 << 18)
+#define ATMEL_TC_LDRB_BOTH (3 << 18)
+
+/* WAVEFORM mode CMR bits */
+#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
+#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
+#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
+#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
+#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
+#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
+#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
+#define ATMEL_TC_EEVT (3 << 10) /* external event source */
+#define ATMEL_TC_EEVT_TIOB (0 << 10)
+#define ATMEL_TC_EEVT_XC0 (1 << 10)
+#define ATMEL_TC_EEVT_XC1 (2 << 10)
+#define ATMEL_TC_EEVT_XC2 (3 << 10)
+#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
+#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
+#define ATMEL_TC_WAVESEL_UP (0 << 13)
+#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
+#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
+#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
+#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
+#define ATMEL_TC_ACPA_NONE (0 << 16)
+#define ATMEL_TC_ACPA_SET (1 << 16)
+#define ATMEL_TC_ACPA_CLEAR (2 << 16)
+#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
+#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
+#define ATMEL_TC_ACPC_NONE (0 << 18)
+#define ATMEL_TC_ACPC_SET (1 << 18)
+#define ATMEL_TC_ACPC_CLEAR (2 << 18)
+#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
+#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
+#define ATMEL_TC_AEEVT_NONE (0 << 20)
+#define ATMEL_TC_AEEVT_SET (1 << 20)
+#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
+#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
+#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
+#define ATMEL_TC_ASWTRG_NONE (0 << 22)
+#define ATMEL_TC_ASWTRG_SET (1 << 22)
+#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
+#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
+#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
+#define ATMEL_TC_BCPB_NONE (0 << 24)
+#define ATMEL_TC_BCPB_SET (1 << 24)
+#define ATMEL_TC_BCPB_CLEAR (2 << 24)
+#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
+#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
+#define ATMEL_TC_BCPC_NONE (0 << 26)
+#define ATMEL_TC_BCPC_SET (1 << 26)
+#define ATMEL_TC_BCPC_CLEAR (2 << 26)
+#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
+#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
+#define ATMEL_TC_BEEVT_NONE (0 << 28)
+#define ATMEL_TC_BEEVT_SET (1 << 28)
+#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
+#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
+#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
+#define ATMEL_TC_BSWTRG_NONE (0 << 30)
+#define ATMEL_TC_BSWTRG_SET (1 << 30)
+#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
+#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
+
+#define ATMEL_TC_CV 0x10 /* counter Value */
+#define ATMEL_TC_RA 0x14 /* register A */
+#define ATMEL_TC_RB 0x18 /* register B */
+#define ATMEL_TC_RC 0x1c /* register C */
+
+#define ATMEL_TC_SR 0x20 /* status (read-only) */
+/* Status-only flags */
+#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
+#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
+#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
+
+#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
+#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
+#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
+
+/* Status and IRQ flags */
+#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
+#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
+#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
+#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
+#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
+#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
+#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
+#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
+
+#endif
/*
- * class_container.h - a generic container for all classes
+ * attribute_container.h - a generic container for all classes
*
* Copyright (c) 2005 - James Bottomley <James.Bottomley@steeleye.com>
*
struct klist containers;
struct class *class;
struct attribute_group *grp;
- struct class_device_attribute **attrs;
+ struct device_attribute **attrs;
int (*match)(struct attribute_container *, struct device *);
#define ATTRIBUTE_CONTAINER_NO_CLASSDEVS 0x01
unsigned long flags;
void attribute_container_create_device(struct device *dev,
int (*fn)(struct attribute_container *,
struct device *,
- struct class_device *));
+ struct device *));
void attribute_container_add_device(struct device *dev,
int (*fn)(struct attribute_container *,
struct device *,
- struct class_device *));
+ struct device *));
void attribute_container_remove_device(struct device *dev,
void (*fn)(struct attribute_container *,
struct device *,
- struct class_device *));
+ struct device *));
void attribute_container_device_trigger(struct device *dev,
int (*fn)(struct attribute_container *,
struct device *,
- struct class_device *));
+ struct device *));
void attribute_container_trigger(struct device *dev,
int (*fn)(struct attribute_container *,
struct device *));
-int attribute_container_add_attrs(struct class_device *classdev);
-int attribute_container_add_class_device(struct class_device *classdev);
+int attribute_container_add_attrs(struct device *classdev);
+int attribute_container_add_class_device(struct device *classdev);
int attribute_container_add_class_device_adapter(struct attribute_container *cont,
struct device *dev,
- struct class_device *classdev);
-void attribute_container_remove_attrs(struct class_device *classdev);
-void attribute_container_class_device_del(struct class_device *classdev);
-struct attribute_container *attribute_container_classdev_to_container(struct class_device *);
-struct class_device *attribute_container_find_class_device(struct attribute_container *, struct device *);
-struct class_device_attribute **attribute_container_classdev_to_attrs(const struct class_device *classdev);
+ struct device *classdev);
+void attribute_container_remove_attrs(struct device *classdev);
+void attribute_container_class_device_del(struct device *classdev);
+struct attribute_container *attribute_container_classdev_to_container(struct device *);
+struct device *attribute_container_find_class_device(struct attribute_container *, struct device *);
+struct device_attribute **attribute_container_classdev_to_attrs(const struct device *classdev);
#endif
extern void bio_set_pages_dirty(struct bio *bio);
extern void bio_check_pages_dirty(struct bio *bio);
extern struct bio *bio_copy_user(struct request_queue *, unsigned long, unsigned int, int);
+extern struct bio *bio_copy_user_iov(struct request_queue *, struct sg_iovec *,
+ int, int);
extern int bio_uncopy_user(struct bio *);
void zero_fill_bio(struct bio *bio);
extern int bitmap_scnprintf(char *buf, unsigned int len,
const unsigned long *src, int nbits);
+extern int bitmap_scnprintf_len(unsigned int len);
extern int __bitmap_parse(const char *buf, unsigned int buflen, int is_user,
unsigned long *dst, int nbits);
extern int bitmap_parse_user(const char __user *ubuf, unsigned int ulen,
__REQ_RW_SYNC, /* request is sync (O_DIRECT) */
__REQ_ALLOCED, /* request came from our alloc pool */
__REQ_RW_META, /* metadata io request */
+ __REQ_COPY_USER, /* contains copies of user pages */
__REQ_NR_BITS, /* stops here */
};
#define REQ_RW_SYNC (1 << __REQ_RW_SYNC)
#define REQ_ALLOCED (1 << __REQ_ALLOCED)
#define REQ_RW_META (1 << __REQ_RW_META)
+#define REQ_COPY_USER (1 << __REQ_COPY_USER)
#define BLK_MAX_CDB 16
* BLK_BOUNCE_ANY : don't bounce anything
* BLK_BOUNCE_ISA : bounce pages above ISA DMA boundary
*/
+
+#if BITS_PER_LONG == 32
#define BLK_BOUNCE_HIGH ((u64)blk_max_low_pfn << PAGE_SHIFT)
-#define BLK_BOUNCE_ANY ((u64)blk_max_pfn << PAGE_SHIFT)
+#else
+#define BLK_BOUNCE_HIGH -1ULL
+#endif
+#define BLK_BOUNCE_ANY (-1ULL)
#define BLK_BOUNCE_ISA (ISA_DMA_THRESHOLD)
/*
#if defined(CONFIG_BLK_DEV_BSG)
struct bsg_class_device {
- struct class_device *class_dev;
+ struct device *class_dev;
struct device *dev;
int minor;
struct request_queue *queue;
#ifdef __KERNEL__
#include <linux/fs.h> /* not really needed, later.. */
#include <linux/device.h>
+#include <linux/list.h>
struct packet_command
{
/* Uniform cdrom data structures for cdrom.c */
struct cdrom_device_info {
struct cdrom_device_ops *ops; /* link to device_ops */
- struct cdrom_device_info *next; /* next device_info for this major */
+ struct list_head list; /* linked list of all device_info */
struct gendisk *disk; /* matching block layer disk */
void *handle; /* driver-dependent data */
/* specifications */
extern int cdrom_media_changed(struct cdrom_device_info *);
extern int register_cdrom(struct cdrom_device_info *cdi);
-extern int unregister_cdrom(struct cdrom_device_info *cdi);
+extern void unregister_cdrom(struct cdrom_device_info *cdi);
typedef struct {
int data;
#include <linux/node.h>
#include <linux/compiler.h>
#include <linux/cpumask.h>
-#include <asm/semaphore.h>
#include <linux/mutex.h>
struct cpu {
#define next_cpu(n, src) ({ (void)(src); 1; })
#endif
+#ifdef CONFIG_HAVE_CPUMASK_OF_CPU_MAP
+extern cpumask_t *cpumask_of_cpu_map;
+#define cpumask_of_cpu(cpu) (cpumask_of_cpu_map[cpu])
+
+#else
#define cpumask_of_cpu(cpu) \
-({ \
+(*({ \
typeof(_unused_cpumask_arg_) m; \
if (sizeof(m) == sizeof(unsigned long)) { \
m.bits[0] = 1UL<<(cpu); \
cpus_clear(m); \
cpu_set((cpu), m); \
} \
- m; \
-})
+ &m; \
+}))
+#endif
#define CPU_MASK_LAST_WORD BITMAP_LAST_WORD_MASK(NR_CPUS)
[BITS_TO_LONGS(NR_CPUS)-1] = CPU_MASK_LAST_WORD \
} }
+#define CPU_MASK_ALL_PTR (&CPU_MASK_ALL)
+
#else
#define CPU_MASK_ALL \
[BITS_TO_LONGS(NR_CPUS)-1] = CPU_MASK_LAST_WORD \
} }
+/* cpu_mask_all is in init/main.c */
+extern cpumask_t cpu_mask_all;
+#define CPU_MASK_ALL_PTR (&cpu_mask_all)
+
#endif
#define CPU_MASK_NONE \
return bitmap_scnprintf(buf, len, srcp->bits, nbits);
}
+#define cpumask_scnprintf_len(len) \
+ __cpumask_scnprintf_len((len))
+static inline int __cpumask_scnprintf_len(int len)
+{
+ return bitmap_scnprintf_len(len);
+}
+
#define cpumask_parse_user(ubuf, ulen, dst) \
__cpumask_parse_user((ubuf), (ulen), &(dst), NR_CPUS)
static inline int __cpumask_parse_user(const char __user *buf, int len,
extern int cpuset_init_early(void);
extern int cpuset_init(void);
extern void cpuset_init_smp(void);
-extern cpumask_t cpuset_cpus_allowed(struct task_struct *p);
-extern cpumask_t cpuset_cpus_allowed_locked(struct task_struct *p);
+extern void cpuset_cpus_allowed(struct task_struct *p, cpumask_t *mask);
+extern void cpuset_cpus_allowed_locked(struct task_struct *p, cpumask_t *mask);
extern nodemask_t cpuset_mems_allowed(struct task_struct *p);
#define cpuset_current_mems_allowed (current->mems_allowed)
void cpuset_init_current_mems_allowed(void);
static inline int cpuset_init(void) { return 0; }
static inline void cpuset_init_smp(void) {}
-static inline cpumask_t cpuset_cpus_allowed(struct task_struct *p)
+static inline void cpuset_cpus_allowed(struct task_struct *p, cpumask_t *mask)
{
- return cpu_possible_map;
+ *mask = cpu_possible_map;
}
-static inline cpumask_t cpuset_cpus_allowed_locked(struct task_struct *p)
+static inline void cpuset_cpus_allowed_locked(struct task_struct *p,
+ cpumask_t *mask)
{
- return cpu_possible_map;
+ *mask = cpu_possible_map;
}
static inline nodemask_t cpuset_mems_allowed(struct task_struct *p)
/*
* Algorithm query interface.
*/
-#ifdef CONFIG_CRYPTO
int crypto_has_alg(const char *name, u32 type, u32 mask);
-#else
-static inline int crypto_has_alg(const char *name, u32 type, u32 mask)
-{
- return 0;
-}
-#endif
/*
* Transforms: user-instantiated objects which encapsulate algorithms
}
extern struct vfsmount *lookup_mnt(struct vfsmount *, struct dentry *);
-extern struct vfsmount *__lookup_mnt(struct vfsmount *, struct dentry *, int);
extern struct dentry *lookup_create(struct nameidata *nd, int is_dir);
extern int sysctl_vfs_cache_pressure;
#include <linux/types.h>
#include <linux/module.h>
#include <linux/pm.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include <asm/atomic.h>
#include <asm/device.h>
struct kobject kobj;
char bus_id[BUS_ID_SIZE]; /* position on parent bus */
struct device_type *type;
- unsigned is_registered:1;
unsigned uevent_suppress:1;
struct semaphore sem; /* semaphore to synchronize calls to
void (*release)(struct device *dev);
};
+/* Get the wakeup routines, which depend on struct device */
+#include <linux/pm_wakeup.h>
+
#ifdef CONFIG_NUMA
static inline int dev_to_node(struct device *dev)
{
static inline int device_is_registered(struct device *dev)
{
- return dev->is_registered;
+ return dev->kobj.state_in_sysfs;
}
void driver_init(void);
dev_t devt, const char *fmt, ...)
__attribute__((format(printf, 4, 5)));
extern void device_destroy(struct class *cls, dev_t devt);
-#ifdef CONFIG_PM_SLEEP
-extern void destroy_suspended_device(struct class *cls, dev_t devt);
-extern void device_pm_schedule_removal(struct device *);
-#else /* !CONFIG_PM_SLEEP */
-static inline void destroy_suspended_device(struct class *cls, dev_t devt)
-{
- device_destroy(cls, devt);
-}
-
-static inline void device_pm_schedule_removal(struct device *dev)
-{
- device_unregister(dev);
-}
-#endif /* !CONFIG_PM_SLEEP */
/*
* Platform "fixup" functions - allow the platform to have their say
#define dev_dbg(dev, format, arg...) \
dev_printk(KERN_DEBUG , dev , format , ## arg)
#else
-static inline int __attribute__ ((format (printf, 2, 3)))
-dev_dbg(struct device *dev, const char *fmt, ...)
-{
- return 0;
-}
+#define dev_dbg(dev, format, arg...) \
+ ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
#endif
#ifdef VERBOSE_DEBUG
#define dev_vdbg dev_dbg
#else
-static inline int __attribute__ ((format (printf, 2, 3)))
-dev_vdbg(struct device *dev, const char *fmt, ...)
-{
- return 0;
-}
+
+#define dev_vdbg(dev, format, arg...) \
+ ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
#endif
/* Create alias, so I can be autoloaded. */
/* Lock levels and flags are here */
#include <linux/dlmconstants.h>
-
-
-#define DLM_RESNAME_MAXLEN 64
-
+#include <linux/types.h>
typedef void dlm_lockspace_t;
struct dlm_lksb {
int sb_status;
- uint32_t sb_lkid;
+ __u32 sb_lkid;
char sb_flags;
char * sb_lvbptr;
};
*******************************************************************************
******************************************************************************/
+#ifndef _LINUX_DLM_DEVICE_H
+#define _LINUX_DLM_DEVICE_H
+
/* This is the device interface for dlm, most users will use a library
* interface.
*/
+#include <linux/dlm.h>
+#include <linux/types.h>
+
#define DLM_USER_LVB_LEN 32
/* Version of the device interface */
#define DLM_USER_PURGE 6
#define DLM_USER_DEADLOCK 7
-/* Arbitrary length restriction */
-#define MAX_LS_NAME_LEN 64
-
/* Lockspace flags */
#define DLM_USER_LSFLG_AUTOFREE 1
#define DLM_USER_LSFLG_FORCEFREE 2
+#endif
+
--- /dev/null
+/*
+ * Copyright (C) 2005-2008 Red Hat, Inc. All rights reserved.
+ *
+ * This copyrighted material is made available to anyone wishing to use,
+ * modify, copy, or redistribute it subject to the terms and conditions
+ * of the GNU General Public License v.2.
+ */
+
+#ifndef __DLM_PLOCK_DOT_H__
+#define __DLM_PLOCK_DOT_H__
+
+#define DLM_PLOCK_MISC_NAME "dlm_plock"
+
+#define DLM_PLOCK_VERSION_MAJOR 1
+#define DLM_PLOCK_VERSION_MINOR 1
+#define DLM_PLOCK_VERSION_PATCH 0
+
+enum {
+ DLM_PLOCK_OP_LOCK = 1,
+ DLM_PLOCK_OP_UNLOCK,
+ DLM_PLOCK_OP_GET,
+};
+
+struct dlm_plock_info {
+ __u32 version[3];
+ __u8 optype;
+ __u8 ex;
+ __u8 wait;
+ __u8 pad;
+ __u32 pid;
+ __s32 nodeid;
+ __s32 rv;
+ __u32 fsid;
+ __u64 number;
+ __u64 start;
+ __u64 end;
+ __u64 owner;
+};
+
+#ifdef __KERNEL__
+int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file,
+ int cmd, struct file_lock *fl);
+int dlm_posix_unlock(dlm_lockspace_t *lockspace, u64 number, struct file *file,
+ struct file_lock *fl);
+int dlm_posix_get(dlm_lockspace_t *lockspace, u64 number, struct file *file,
+ struct file_lock *fl);
+#endif /* __KERNEL__ */
+
+#endif
+
* Constants used by DLM interface.
*/
+#define DLM_LOCKSPACE_LEN 64
+#define DLM_RESNAME_MAXLEN 64
+
+
/*
* Lock Modes
*/
* @last_used: last cookie value handed out
*
* dma_async_is_complete() is used in dma_async_memcpy_complete()
- * the test logic is seperated for lightweight testing of multiple cookies
+ * the test logic is separated for lightweight testing of multiple cookies
*/
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
dma_cookie_t last_complete, dma_cookie_t last_used)
#include <linux/proc_fs.h>
#include <linux/rtc.h>
#include <linux/ioport.h>
+#include <linux/pfn.h>
#include <asm/page.h>
#include <asm/system.h>
u16 length;
} __attribute ((packed));
+static inline void memrange_efi_to_native(u64 *addr, u64 *npages)
+{
+ *npages = PFN_UP(*addr + (*npages<<EFI_PAGE_SHIFT)) - PFN_DOWN(*addr);
+ *addr &= PAGE_MASK;
+}
+
#endif /* _LINUX_EFI_H */
struct enclosure_component {
void *scratch;
- struct class_device cdev;
+ struct device cdev;
+ struct device *dev;
enum enclosure_component_type type;
int number;
int fault;
struct enclosure_device {
void *scratch;
struct list_head node;
- struct class_device cdev;
+ struct device edev;
struct enclosure_component_callbacks *cb;
int components;
struct enclosure_component component[0];
};
static inline struct enclosure_device *
-to_enclosure_device(struct class_device *dev)
+to_enclosure_device(struct device *dev)
{
- return container_of(dev, struct enclosure_device, cdev);
+ return container_of(dev, struct enclosure_device, edev);
}
static inline struct enclosure_component *
-to_enclosure_component(struct class_device *dev)
+to_enclosure_component(struct device *dev)
{
return container_of(dev, struct enclosure_component, cdev);
}
extern void __fput(struct file *);
extern void fput(struct file *);
+extern void drop_file_write_access(struct file *file);
struct file_operations;
struct vfsmount;
#include <linux/pid.h>
#include <linux/mutex.h>
#include <linux/capability.h>
+#include <linux/semaphore.h>
#include <asm/atomic.h>
-#include <asm/semaphore.h>
#include <asm/byteorder.h>
struct export_operations;
extern void __init inode_init(void);
extern void __init inode_init_early(void);
-extern void __init mnt_init(void);
extern void __init files_init(unsigned long);
struct buffer_head;
index < ra->start + ra->size);
}
+#define FILE_MNT_WRITE_TAKEN 1
+#define FILE_MNT_WRITE_RELEASED 2
+
struct file {
/*
* fu_list becomes invalid after file_free is called and queued via
spinlock_t f_ep_lock;
#endif /* #ifdef CONFIG_EPOLL */
struct address_space *f_mapping;
+#ifdef CONFIG_DEBUG_WRITECOUNT
+ unsigned long f_mnt_write_state;
+#endif
};
extern spinlock_t files_lock;
#define file_list_lock() spin_lock(&files_lock);
#define get_file(x) atomic_inc(&(x)->f_count)
#define file_count(x) atomic_read(&(x)->f_count)
+#ifdef CONFIG_DEBUG_WRITECOUNT
+static inline void file_take_write(struct file *f)
+{
+ WARN_ON(f->f_mnt_write_state != 0);
+ f->f_mnt_write_state = FILE_MNT_WRITE_TAKEN;
+}
+static inline void file_release_write(struct file *f)
+{
+ f->f_mnt_write_state |= FILE_MNT_WRITE_RELEASED;
+}
+static inline void file_reset_write(struct file *f)
+{
+ f->f_mnt_write_state = 0;
+}
+static inline void file_check_state(struct file *f)
+{
+ /*
+ * At this point, either both or neither of these bits
+ * should be set.
+ */
+ WARN_ON(f->f_mnt_write_state == FILE_MNT_WRITE_TAKEN);
+ WARN_ON(f->f_mnt_write_state == FILE_MNT_WRITE_RELEASED);
+}
+static inline int file_check_writeable(struct file *f)
+{
+ if (f->f_mnt_write_state == FILE_MNT_WRITE_TAKEN)
+ return 0;
+ printk(KERN_WARNING "writeable file with no "
+ "mnt_want_write()\n");
+ WARN_ON(1);
+ return -EINVAL;
+}
+#else /* !CONFIG_DEBUG_WRITECOUNT */
+static inline void file_take_write(struct file *filp) {}
+static inline void file_release_write(struct file *filp) {}
+static inline void file_reset_write(struct file *filp) {}
+static inline void file_check_state(struct file *filp) {}
+static inline int file_check_writeable(struct file *filp)
+{
+ return 0;
+}
+#endif /* CONFIG_DEBUG_WRITECOUNT */
+
#define MAX_NON_LFS ((1UL<<31) - 1)
/* Page cache limit. The filesystems should put that into their s_maxbytes
#define kern_mount(type) kern_mount_data(type, NULL)
extern int may_umount_tree(struct vfsmount *);
extern int may_umount(struct vfsmount *);
-extern void umount_tree(struct vfsmount *, int, struct list_head *);
-extern void release_mounts(struct list_head *);
extern long do_mount(char *, char *, char *, unsigned long, void *);
-extern struct vfsmount *copy_tree(struct vfsmount *, struct dentry *, int);
-extern void mnt_set_mountpoint(struct vfsmount *, struct dentry *,
- struct vfsmount *);
extern struct vfsmount *collect_mounts(struct vfsmount *, struct dentry *);
extern void drop_collected_mounts(struct vfsmount *);
extern struct file *create_write_pipe(void);
extern void free_write_pipe(struct file *);
-extern int open_namei(int dfd, const char *, int, int, struct nameidata *);
+extern struct file *do_filp_open(int dfd, const char *pathname,
+ int open_flag, int mode);
extern int may_open(struct nameidata *, int, int);
extern int kernel_read(struct file *, unsigned long, char *, unsigned long);
#define HID_QUIRK_2WHEEL_MOUSE_HACK_B8 0x02000000
#define HID_QUIRK_HWHEEL_WHEEL_INVERT 0x04000000
#define HID_QUIRK_MICROSOFT_KEYS 0x08000000
+#define HID_QUIRK_FULLSPEED_INTERVAL 0x10000000
/*
* Separate quirks for runtime report descriptor fixup
#define HID_QUIRK_RDESC_MACBOOK_JIS 0x00000010
#define HID_QUIRK_RDESC_BUTTON_CONSUMER 0x00000020
#define HID_QUIRK_RDESC_SAMSUNG_REMOTE 0x00000040
+#define HID_QUIRK_RDESC_MICROSOFT_RECV_1028 0x00000080
+#define HID_QUIRK_RDESC_SUNPLUS_WDESKTOP 0x00000100
/*
* This is the global environment of the parser. This information is
* This is the local environment. It is persistent up the next main-item.
*/
-#define HID_MAX_USAGES 8192
+#define HID_MAX_USAGES 12288
#define HID_DEFAULT_NUM_COLLECTIONS 16
struct hid_local {
#define HID_RESET_PENDING 4
#define HID_SUSPENDED 5
#define HID_CLEAR_HALT 6
+#define HID_DISCONNECTED 7
struct hid_input {
struct list_head list;
void *hidraw;
int minor; /* Hiddev minor number */
- wait_queue_head_t wait; /* For sleeping */
-
int open; /* is the device open by anyone? */
char name[128]; /* Device name */
char phys[64]; /* Device physical location */
int hidinput_mapping_quirks(struct hid_usage *, struct input_dev *, unsigned long **, int *);
int hidinput_event_quirks(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);
int hidinput_apple_event(struct hid_device *, struct input_dev *, struct hid_usage *, __s32);
-void hid_input_field(struct hid_device *hid, struct hid_field *field, __u8 *data, int interrupt);
void hid_output_report(struct hid_report *report, __u8 *data);
void hid_free_device(struct hid_device *device);
struct hid_device *hid_parse_report(__u8 *start, unsigned size);
/* HID quirks API */
u32 usbhid_lookup_quirk(const u16 idVendor, const u16 idProduct);
-int usbhid_modify_dquirk(const u16 idVendor, const u16 idProduct, const u32 quirks);
int usbhid_quirks_init(char **quirks_param);
void usbhid_quirks_exit(void);
void usbhid_fixup_report_descriptor(const u16, const u16, char *, unsigned, char **);
int hid_ff_init(struct hid_device *hid);
int hid_lgff_init(struct hid_device *hid);
+int hid_lg2ff_init(struct hid_device *hid);
int hid_plff_init(struct hid_device *hid);
int hid_tmff_init(struct hid_device *hid);
int hid_zpff_init(struct hid_device *hid);
#define dbg_hid_line(format, arg...) if (hid_debug) \
printk(format, ## arg)
#else
-#define dbg_hid(format, arg...) do {} while (0)
+static inline int __attribute__((format(printf, 1, 2)))
+dbg_hid(const char *fmt, ...)
+{
+ return 0;
+}
#define dbg_hid_line dbg_hid
#endif
*/
#include <linux/hid.h>
+#include <linux/types.h>
struct hidraw_report_descriptor {
__u32 size;
#include <linux/hil.h>
#include <linux/time.h>
#include <linux/interrupt.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include <linux/serio.h>
#include <linux/list.h>
/** Register a new Hardware Random Number Generator driver. */
extern int hwrng_register(struct hwrng *rng);
/** Unregister a Hardware Random Number Generator driver. */
-extern void __hwrng_unregister(struct hwrng *rng, bool suspended);
-static inline void hwrng_unregister(struct hwrng *rng)
-{
- __hwrng_unregister(rng, false);
-}
-static inline void hwrng_unregister_suspended(struct hwrng *rng)
-{
- __hwrng_unregister(rng, true);
-}
+extern void hwrng_unregister(struct hwrng *rng);
#endif /* __KERNEL__ */
#endif /* LINUX_HWRANDOM_H_ */
#ifndef _LINUX_I2C_ALGO_PCA_H
#define _LINUX_I2C_ALGO_PCA_H
+/* Clock speeds for the bus */
+#define I2C_PCA_CON_330kHz 0x00
+#define I2C_PCA_CON_288kHz 0x01
+#define I2C_PCA_CON_217kHz 0x02
+#define I2C_PCA_CON_146kHz 0x03
+#define I2C_PCA_CON_88kHz 0x04
+#define I2C_PCA_CON_59kHz 0x05
+#define I2C_PCA_CON_44kHz 0x06
+#define I2C_PCA_CON_36kHz 0x07
+
+/* PCA9564 registers */
+#define I2C_PCA_STA 0x00 /* STATUS Read Only */
+#define I2C_PCA_TO 0x00 /* TIMEOUT Write Only */
+#define I2C_PCA_DAT 0x01 /* DATA Read/Write */
+#define I2C_PCA_ADR 0x02 /* OWN ADR Read/Write */
+#define I2C_PCA_CON 0x03 /* CONTROL Read/Write */
+
+#define I2C_PCA_CON_AA 0x80 /* Assert Acknowledge */
+#define I2C_PCA_CON_ENSIO 0x40 /* Enable */
+#define I2C_PCA_CON_STA 0x20 /* Start */
+#define I2C_PCA_CON_STO 0x10 /* Stop */
+#define I2C_PCA_CON_SI 0x08 /* Serial Interrupt */
+#define I2C_PCA_CON_CR 0x07 /* Clock Rate (MASK) */
+
struct i2c_algo_pca_data {
- int (*get_own) (struct i2c_algo_pca_data *adap); /* Obtain own address */
- int (*get_clock) (struct i2c_algo_pca_data *adap);
- void (*write_byte) (struct i2c_algo_pca_data *adap, int reg, int val);
- int (*read_byte) (struct i2c_algo_pca_data *adap, int reg);
- int (*wait_for_interrupt) (struct i2c_algo_pca_data *adap);
+ void *data; /* private low level data */
+ void (*write_byte) (void *data, int reg, int val);
+ int (*read_byte) (void *data, int reg);
+ int (*wait_for_completion) (void *data);
+ void (*reset_chip) (void *data);
+ /* i2c_clock values are defined in linux/i2c-algo-pca.h */
+ unsigned int i2c_clock;
};
int i2c_pca_add_bus(struct i2c_adapter *);
+int i2c_pca_add_numbered_bus(struct i2c_adapter *);
#endif /* _LINUX_I2C_ALGO_PCA_H */
--- /dev/null
+#ifndef I2C_PCA9564_PLATFORM_H
+#define I2C_PCA9564_PLATFORM_H
+
+struct i2c_pca9564_pf_platform_data {
+ int gpio; /* pin to reset chip. driver will work when
+ * not supplied (negative value), but it
+ * cannot exit some error conditions then */
+ int i2c_clock_speed; /* values are defined in linux/i2c-algo-pca.h */
+ int timeout; /* timeout = this value * 10us */
+};
+
+#endif /* I2C_PCA9564_PLATFORM_H */
*/
extern int tps65013_set_low_pwr(unsigned mode);
+
+struct i2c_client;
+
+/**
+ * struct tps65010_board - packages GPIO and LED lines
+ * @base: the GPIO number to assign to GPIO-1
+ * @outmask: bit (N-1) is set to allow GPIO-N to be used as an
+ * (open drain) output
+ * @setup: optional callback issued once the GPIOs are valid
+ * @teardown: optional callback issued before the GPIOs are invalidated
+ * @context: optional parameter passed to setup() and teardown()
+ *
+ * Board data may be used to package the GPIO (and LED) lines for use
+ * in by the generic GPIO and LED frameworks. The first four GPIOs
+ * starting at gpio_base are GPIO1..GPIO4. The next two are LED1/nPG
+ * and LED2 (with hardware blinking capability, not currently exposed).
+ *
+ * The @setup callback may be used with the kind of board-specific glue
+ * which hands the (now-valid) GPIOs to other drivers, or which puts
+ * devices in their initial states using these GPIOs.
+ */
+struct tps65010_board {
+ int base;
+ unsigned outmask;
+
+ int (*setup)(struct i2c_client *client, void *context);
+ int (*teardown)(struct i2c_client *client, void *context);
+ void *context;
+};
+
#endif /* __LINUX_I2C_TPS65010_H */
#include <linux/mempool.h>
#include <linux/mutex.h>
#include <linux/scatterlist.h>
+#include <linux/semaphore.h> /* Needed for MUTEX init macros */
#include <asm/io.h>
-#include <asm/semaphore.h> /* Needed for MUTEX init macros */
/* message queue empty */
#define I2O_QUEUE_EMPTY 0xffffffff
#include <asm/byteorder.h>
#include <asm/system.h>
#include <asm/io.h>
-#include <asm/semaphore.h>
#include <asm/mutex.h>
#if defined(CONFIG_CRIS) || defined(CONFIG_FRV)
#include <linux/if_ether.h>
#include <linux/if.h>
#include <linux/netdevice.h>
-#include <asm/semaphore.h>
#include <linux/ppp_channel.h>
#endif /* __KERNEL__ */
#include <linux/if_pppol2tp.h>
.cpus_allowed = CPU_MASK_ALL, \
.mm = NULL, \
.active_mm = &init_mm, \
+ .se = { \
+ .group_node = LIST_HEAD_INIT(tsk.se.group_node), \
+ }, \
.rt = { \
.run_list = LIST_HEAD_INIT(tsk.rt.run_list), \
.time_slice = HZ, \
#define IORESOURCE_CACHEABLE 0x00004000
#define IORESOURCE_RANGELENGTH 0x00008000
#define IORESOURCE_SHADOWABLE 0x00010000
-#define IORESOURCE_BUS_HAS_VGA 0x00080000
+
+#define IORESOURCE_SIZEALIGN 0x00020000 /* size indicates alignment */
+#define IORESOURCE_STARTALIGN 0x00040000 /* start field is alignment */
#define IORESOURCE_DISABLED 0x10000000
#define IORESOURCE_UNSET 0x20000000
void *alignf_data);
int adjust_resource(struct resource *res, resource_size_t start,
resource_size_t size);
+resource_size_t resource_alignment(struct resource *res);
/* Convenience shorthand with allocation */
#define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name))
#define irqs_disabled() \
({ \
- unsigned long flags; \
+ unsigned long _flags; \
\
- raw_local_save_flags(flags); \
- raw_irqs_disabled_flags(flags); \
+ raw_local_save_flags(_flags); \
+ raw_irqs_disabled_flags(_flags); \
})
#define irqs_disabled_flags(flags) raw_irqs_disabled_flags(flags)
--- /dev/null
+/*
+ * Copyright 2007 Red Hat, Inc.
+ * by Peter Jones <pjones@redhat.com>
+ * Copyright 2007 IBM, Inc.
+ * by Konrad Rzeszutek <konradr@linux.vnet.ibm.com>
+ * Copyright 2008
+ * by Konrad Rzeszutek <ketuzsezr@darnok.org>
+ *
+ * This code exposes the iSCSI Boot Format Table to userland via sysfs.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2.0 as published by
+ * the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ISCSI_IBFT_H
+#define ISCSI_IBFT_H
+
+struct ibft_table_header {
+ char signature[4];
+ u32 length;
+ u8 revision;
+ u8 checksum;
+ char oem_id[6];
+ char oem_table_id[8];
+ char reserved[24];
+} __attribute__((__packed__));
+
+/*
+ * Logical location of iSCSI Boot Format Table.
+ * If the value is NULL there is no iBFT on the machine.
+ */
+extern struct ibft_table_header *ibft_addr;
+
+/*
+ * Routine used to find and reserve the iSCSI Boot Format Table. The
+ * mapped address is set in the ibft_addr variable.
+ */
+#ifdef CONFIG_ISCSI_IBFT_FIND
+extern void __init reserve_ibft_region(void);
+#else
+static inline void reserve_ibft_region(void) { }
+#endif
+
+#endif /* ISCSI_IBFT_H */
#include <linux/timer.h>
#include <linux/lockdep.h>
-#include <asm/semaphore.h>
-
#define journal_oom_retry 1
/*
#include <linux/bit_spinlock.h>
#include <linux/mutex.h>
#include <linux/timer.h>
-
-#include <asm/semaphore.h>
#endif
#define journal_oom_retry 1
#elif HZ >= 6144 && HZ < 12288
# define SHIFT_HZ 13
#else
-# error You lose.
+# error Invalid value of HZ.
#endif
/* LATCH is used in the interval timer and ftape setup. */
((__s64)(a) - (__s64)(b) >= 0))
#define time_before_eq64(a,b) time_after_eq64(b,a)
+/*
+ * These four macros compare jiffies and 'a' for convenience.
+ */
+
+/* time_is_before_jiffies(a) return true if a is before jiffies */
+#define time_is_before_jiffies(a) time_after(jiffies, a)
+
+/* time_is_after_jiffies(a) return true if a is after jiffies */
+#define time_is_after_jiffies(a) time_before(jiffies, a)
+
+/* time_is_before_eq_jiffies(a) return true if a is before or equal to jiffies*/
+#define time_is_before_eq_jiffies(a) time_after_eq(jiffies, a)
+
+/* time_is_after_eq_jiffies(a) return true if a is after or equal to jiffies*/
+#define time_is_after_eq_jiffies(a) time_before_eq(jiffies, a)
+
/*
* Have the 32 bit jiffies value wrap 5 minutes after boot
* so jiffies wrap bugs show up earlier.
#define pr_debug(fmt, arg...) \
printk(KERN_DEBUG fmt, ##arg)
#else
-static inline int __attribute__ ((format (printf, 1, 2))) pr_debug(const char * fmt, ...)
-{
- return 0;
-}
+#define pr_debug(fmt, arg...) \
+ ({ if (0) printk(KERN_DEBUG fmt, ##arg); 0; })
#endif
/*
#include <linux/list.h>
#include <linux/skbuff.h>
#include <linux/workqueue.h>
-#include <asm/semaphore.h>
#define KCI_CONTRUP 0 /* arg: struct capi_profile */
#define KCI_CONTRDOWN 1 /* arg: NULL */
/* Get the real (wall-) time in timespec format: */
#define ktime_get_real_ts(ts) getnstimeofday(ts)
+static inline ktime_t ns_to_ktime(u64 ns)
+{
+ static const ktime_t ktime_zero = { .tv64 = 0 };
+ return ktime_add_ns(ktime_zero, ns);
+}
+
#endif
extern int led_classdev_register(struct device *parent,
struct led_classdev *led_cdev);
-extern void __led_classdev_unregister(struct led_classdev *led_cdev, bool sus);
-static inline void led_classdev_unregister(struct led_classdev *lcd)
-{
- __led_classdev_unregister(lcd, false);
-}
-static inline void led_classdev_unregister_suspended(struct led_classdev *lcd)
-{
- __led_classdev_unregister(lcd, true);
-}
+extern void led_classdev_unregister(struct led_classdev *lcd);
extern void led_classdev_suspend(struct led_classdev *led_cdev);
extern void led_classdev_resume(struct led_classdev *led_cdev);
MAX_PERFORMANCE,
MEDIUM_POWER,
};
-extern struct class_device_attribute class_device_attr_link_power_management_policy;
+extern struct device_attribute dev_attr_link_power_management_policy;
#ifdef CONFIG_ATA_SFF
struct ata_ioports {
* as long as the traversal is guarded by rcu_read_lock().
*/
#define list_for_each_rcu(pos, head) \
- for (pos = (head)->next; \
- prefetch(rcu_dereference(pos)->next), pos != (head); \
- pos = pos->next)
+ for (pos = rcu_dereference((head)->next); \
+ prefetch(pos->next), pos != (head); \
+ pos = rcu_dereference(pos->next))
#define __list_for_each_rcu(pos, head) \
- for (pos = (head)->next; \
- rcu_dereference(pos) != (head); \
- pos = pos->next)
-
-/**
- * list_for_each_safe_rcu
- * @pos: the &struct list_head to use as a loop cursor.
- * @n: another &struct list_head to use as temporary storage
- * @head: the head for your list.
- *
- * Iterate over an rcu-protected list, safe against removal of list entry.
- *
- * This list-traversal primitive may safely run concurrently with
- * the _rcu list-mutation primitives such as list_add_rcu()
- * as long as the traversal is guarded by rcu_read_lock().
- */
-#define list_for_each_safe_rcu(pos, n, head) \
- for (pos = (head)->next; \
- n = rcu_dereference(pos)->next, pos != (head); \
- pos = n)
+ for (pos = rcu_dereference((head)->next); \
+ pos != (head); \
+ pos = rcu_dereference(pos->next))
/**
* list_for_each_entry_rcu - iterate over rcu list of given type
* as long as the traversal is guarded by rcu_read_lock().
*/
#define list_for_each_entry_rcu(pos, head, member) \
- for (pos = list_entry((head)->next, typeof(*pos), member); \
- prefetch(rcu_dereference(pos)->member.next), \
- &pos->member != (head); \
- pos = list_entry(pos->member.next, typeof(*pos), member))
+ for (pos = list_entry(rcu_dereference((head)->next), typeof(*pos), member); \
+ prefetch(pos->member.next), &pos->member != (head); \
+ pos = list_entry(rcu_dereference(pos->member.next), typeof(*pos), member))
/**
* as long as the traversal is guarded by rcu_read_lock().
*/
#define list_for_each_continue_rcu(pos, head) \
- for ((pos) = (pos)->next; \
- prefetch(rcu_dereference((pos))->next), (pos) != (head); \
- (pos) = (pos)->next)
+ for ((pos) = rcu_dereference((pos)->next); \
+ prefetch((pos)->next), (pos) != (head); \
+ (pos) = rcu_dereference((pos)->next))
/*
* Double linked lists with a single pointer list head.
* as long as the traversal is guarded by rcu_read_lock().
*/
#define hlist_for_each_entry_rcu(tpos, pos, head, member) \
- for (pos = (head)->first; \
- rcu_dereference(pos) && ({ prefetch(pos->next); 1;}) && \
+ for (pos = rcu_dereference((head)->first); \
+ pos && ({ prefetch(pos->next); 1;}) && \
({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
- pos = pos->next)
+ pos = rcu_dereference(pos->next))
#else
#warning "don't include kernel headers in userspace"
--- /dev/null
+#ifndef _LINUX_LMB_H
+#define _LINUX_LMB_H
+#ifdef __KERNEL__
+
+/*
+ * Logical memory blocks.
+ *
+ * Copyright (C) 2001 Peter Bergner, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+
+#define MAX_LMB_REGIONS 128
+
+struct lmb_property {
+ u64 base;
+ u64 size;
+};
+
+struct lmb_region {
+ unsigned long cnt;
+ u64 size;
+ struct lmb_property region[MAX_LMB_REGIONS+1];
+};
+
+struct lmb {
+ unsigned long debug;
+ u64 rmo_size;
+ struct lmb_region memory;
+ struct lmb_region reserved;
+};
+
+extern struct lmb lmb;
+
+extern void __init lmb_init(void);
+extern void __init lmb_analyze(void);
+extern long __init lmb_add(u64 base, u64 size);
+extern long __init lmb_reserve(u64 base, u64 size);
+extern u64 __init lmb_alloc_nid(u64 size, u64 align, int nid,
+ u64 (*nid_range)(u64, u64, int *));
+extern u64 __init lmb_alloc(u64 size, u64 align);
+extern u64 __init lmb_alloc_base(u64 size,
+ u64, u64 max_addr);
+extern u64 __init __lmb_alloc_base(u64 size,
+ u64 align, u64 max_addr);
+extern u64 __init lmb_phys_mem_size(void);
+extern u64 __init lmb_end_of_DRAM(void);
+extern void __init lmb_enforce_memory_limit(u64 memory_limit);
+extern int __init lmb_is_reserved(u64 addr);
+
+extern void lmb_dump_all(void);
+
+static inline u64
+lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
+{
+ return type->region[region_nr].size;
+}
+static inline u64
+lmb_size_pages(struct lmb_region *type, unsigned long region_nr)
+{
+ return lmb_size_bytes(type, region_nr) >> PAGE_SHIFT;
+}
+static inline u64
+lmb_start_pfn(struct lmb_region *type, unsigned long region_nr)
+{
+ return type->region[region_nr].base >> PAGE_SHIFT;
+}
+static inline u64
+lmb_end_pfn(struct lmb_region *type, unsigned long region_nr)
+{
+ return lmb_start_pfn(type, region_nr) +
+ lmb_size_pages(type, region_nr);
+}
+
+#include <asm/lmb.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* _LINUX_LMB_H */
+++ /dev/null
-/*
- * Copyright (C) 2005 Red Hat, Inc. All rights reserved.
- *
- * This copyrighted material is made available to anyone wishing to use,
- * modify, copy, or redistribute it subject to the terms and conditions
- * of the GNU General Public License v.2.
- */
-
-#ifndef __LOCK_DLM_PLOCK_DOT_H__
-#define __LOCK_DLM_PLOCK_DOT_H__
-
-#define GDLM_PLOCK_MISC_NAME "lock_dlm_plock"
-
-#define GDLM_PLOCK_VERSION_MAJOR 1
-#define GDLM_PLOCK_VERSION_MINOR 1
-#define GDLM_PLOCK_VERSION_PATCH 0
-
-enum {
- GDLM_PLOCK_OP_LOCK = 1,
- GDLM_PLOCK_OP_UNLOCK,
- GDLM_PLOCK_OP_GET,
-};
-
-struct gdlm_plock_info {
- __u32 version[3];
- __u8 optype;
- __u8 ex;
- __u8 wait;
- __u8 pad;
- __u32 pid;
- __s32 nodeid;
- __s32 rv;
- __u32 fsid;
- __u64 number;
- __u64 start;
- __u64 end;
- __u64 owner;
-};
-
-#endif
-
--- /dev/null
+/*
+ * Marvell MBUS common definitions.
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __LINUX_MBUS_H
+#define __LINUX_MBUS_H
+
+struct mbus_dram_target_info
+{
+ /*
+ * The 4-bit MBUS target ID of the DRAM controller.
+ */
+ u8 mbus_dram_target_id;
+
+ /*
+ * The base address, size, and MBUS attribute ID for each
+ * of the possible DRAM chip selects. Peripherals are
+ * required to support at least 4 decode windows.
+ */
+ int num_cs;
+ struct mbus_dram_window {
+ u8 cs_index;
+ u8 mbus_attr;
+ u32 base;
+ u32 size;
+ } cs[4];
+};
+
+
+#endif
#include <linux/sysdev.h>
#include <linux/node.h>
#include <linux/compiler.h>
-
-#include <asm/semaphore.h>
+#include <linux/mutex.h>
struct memory_block {
unsigned long phys_index;
* created long after the critical areas during
* initialization.
*/
- struct semaphore state_sem;
+ struct mutex state_mutex;
int phys_device; /* to which fru does this belong? */
void *hw; /* optional pointer to fw/hw data */
int (*phys_callback)(struct memory_block *);
#define MEMSTICK_CAP_PAR8 4
struct work_struct media_checker;
- struct class_device cdev;
+ struct device dev;
struct memstick_dev *card;
unsigned int retries;
--- /dev/null
+/*
+ * HTC simple EGPIO irq and gpio extender
+ */
+
+#ifndef __HTC_EGPIO_H__
+#define __HTC_EGPIO_H__
+
+#include <linux/gpio.h>
+
+/* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */
+#define HTC_EGPIO_OUTPUT (~0)
+#define HTC_EGPIO_INPUT 0
+
+/**
+ * struct htc_egpio_chip - descriptor to create gpio_chip for register range
+ * @reg_start: index of first register
+ * @gpio_base: gpio number of first pin in this register range
+ * @num_gpios: number of gpios in this register range, max BITS_PER_LONG
+ * (number of registers = DIV_ROUND_UP(num_gpios, reg_width))
+ * @direction: bitfield, '0' = input, '1' = output,
+ */
+struct htc_egpio_chip {
+ int reg_start;
+ int gpio_base;
+ int num_gpios;
+ unsigned long direction;
+ unsigned long initial_values;
+};
+
+/**
+ * struct htc_egpio_platform_data - description provided by the arch
+ * @irq_base: beginning of available IRQs (eg, IRQ_BOARD_START)
+ * @num_irqs: number of irqs
+ * @reg_width: number of bits per register, either 8 or 16 bit
+ * @bus_width: alignment of the registers, either 16 or 32 bit
+ * @invert_acks: set if chip requires writing '0' to ack an irq, instead of '1'
+ * @ack_register: location of the irq/ack register
+ * @chip: pointer to array of htc_egpio_chip descriptors
+ * @num_chips: number of egpio chip descriptors
+ */
+struct htc_egpio_platform_data {
+ int bus_width;
+ int reg_width;
+
+ int irq_base;
+ int num_irqs;
+ int invert_acks;
+ int ack_register;
+
+ struct htc_egpio_chip *chip;
+ int num_chips;
+};
+
+/* Determine the wakeup irq, to be called during early resume */
+extern int htc_egpio_get_wakeup_irq(struct device *dev);
+
+#endif
--- /dev/null
+/*
+ * HTC PASIC3 driver - LEDs and DS1WM
+ *
+ * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ *
+ */
+
+#ifndef __PASIC3_H
+#define __PASIC3_H
+
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+
+extern void pasic3_write_register(struct device *dev, u32 reg, u8 val);
+extern u8 pasic3_read_register(struct device *dev, u32 reg);
+
+/*
+ * mask for registers 0x20,0x21,0x22
+ */
+#define PASIC3_MASK_LED0 0x04
+#define PASIC3_MASK_LED1 0x08
+#define PASIC3_MASK_LED2 0x40
+
+/*
+ * bits in register 0x06
+ */
+#define PASIC3_BIT2_LED0 0x08
+#define PASIC3_BIT2_LED1 0x10
+#define PASIC3_BIT2_LED2 0x20
+
+struct pasic3_led {
+ struct led_classdev led;
+ unsigned int hw_num;
+ unsigned int bit2;
+ unsigned int mask;
+ struct pasic3_leds_machinfo *pdata;
+};
+
+struct pasic3_leds_machinfo {
+ unsigned int num_leds;
+ unsigned int power_gpio;
+ struct pasic3_led *leds;
+};
+
+struct pasic3_platform_data {
+ struct pasic3_leds_machinfo *led_pdata;
+ unsigned int bus_shift;
+ unsigned int clock_rate;
+};
+
+#endif
};
extern int misc_register(struct miscdevice * misc);
-extern int __misc_deregister(struct miscdevice *misc, bool suspended);
-static inline int misc_deregister(struct miscdevice *misc)
-{
- return __misc_deregister(misc, false);
-}
-static inline int misc_deregister_suspended(struct miscdevice *misc)
-{
- return __misc_deregister(misc, true);
-}
+extern int misc_deregister(struct miscdevice *misc);
#define MODULE_ALIAS_MISCDEV(minor) \
MODULE_ALIAS("char-major-" __stringify(MISC_MAJOR) \
extern struct pglist_data contig_page_data;
#define NODE_DATA(nid) (&contig_page_data)
#define NODE_MEM_MAP(nid) mem_map
-#define MAX_NODES_SHIFT 1
#else /* CONFIG_NEED_MULTIPLE_NODES */
#include <linux/types.h>
#include <linux/list.h>
+#include <linux/nodemask.h>
#include <linux/spinlock.h>
#include <asm/atomic.h>
#define MNT_NOATIME 0x08
#define MNT_NODIRATIME 0x10
#define MNT_RELATIME 0x20
+#define MNT_READONLY 0x40 /* does the user want this to be r/o? */
#define MNT_SHRINKABLE 0x100
+#define MNT_IMBALANCED_WRITE_COUNT 0x200 /* just for debugging */
#define MNT_SHARED 0x1000 /* if the vfsmount is a shared mount */
#define MNT_UNBINDABLE 0x2000 /* if the vfsmount is a unbindable mount */
int mnt_expiry_mark; /* true if marked for expiry */
int mnt_pinned;
int mnt_ghosts;
+ /*
+ * This value is not stable unless all of the mnt_writers[] spinlocks
+ * are held, and all mnt_writer[]s on this mount have 0 as their ->count
+ */
+ atomic_t __mnt_writers;
};
static inline struct vfsmount *mntget(struct vfsmount *mnt)
return mnt;
}
+extern int mnt_want_write(struct vfsmount *mnt);
+extern void mnt_drop_write(struct vfsmount *mnt);
extern void mntput_no_expire(struct vfsmount *mnt);
extern void mnt_pin(struct vfsmount *mnt);
extern void mnt_unpin(struct vfsmount *mnt);
+extern int __mnt_is_readonly(struct vfsmount *mnt);
static inline void mntput(struct vfsmount *mnt)
{
}
}
-extern void free_vfsmnt(struct vfsmount *mnt);
-extern struct vfsmount *alloc_vfsmnt(const char *name);
extern struct vfsmount *do_kern_mount(const char *fstype, int flags,
const char *name, void *data);
int *lenp);
extern int of_device_is_compatible(const struct device_node *device,
const char *);
+extern int of_device_is_available(const struct device_node *device);
extern const void *of_get_property(const struct device_node *node,
const char *name,
int *lenp);
--- /dev/null
+/*
+ * OF helpers for the GPIO API
+ *
+ * Copyright (c) 2007-2008 MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_OF_GPIO_H
+#define __LINUX_OF_GPIO_H
+
+#include <linux/errno.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_OF_GPIO
+
+/*
+ * Generic OF GPIO chip
+ */
+struct of_gpio_chip {
+ struct gpio_chip gc;
+ int gpio_cells;
+ int (*xlate)(struct of_gpio_chip *of_gc, struct device_node *np,
+ const void *gpio_spec);
+};
+
+static inline struct of_gpio_chip *to_of_gpio_chip(struct gpio_chip *gc)
+{
+ return container_of(gc, struct of_gpio_chip, gc);
+}
+
+/*
+ * OF GPIO chip for memory mapped banks
+ */
+struct of_mm_gpio_chip {
+ struct of_gpio_chip of_gc;
+ void (*save_regs)(struct of_mm_gpio_chip *mm_gc);
+ void __iomem *regs;
+};
+
+static inline struct of_mm_gpio_chip *to_of_mm_gpio_chip(struct gpio_chip *gc)
+{
+ struct of_gpio_chip *of_gc = to_of_gpio_chip(gc);
+
+ return container_of(of_gc, struct of_mm_gpio_chip, of_gc);
+}
+
+extern int of_get_gpio(struct device_node *np, int index);
+extern int of_mm_gpiochip_add(struct device_node *np,
+ struct of_mm_gpio_chip *mm_gc);
+extern int of_gpio_simple_xlate(struct of_gpio_chip *of_gc,
+ struct device_node *np,
+ const void *gpio_spec);
+#else
+
+/* Drivers may not strictly depend on the GPIO support, so let them link. */
+static inline int of_get_gpio(struct device_node *np, int index)
+{
+ return -ENOSYS;
+}
+
+#endif /* CONFIG_OF_GPIO */
+
+#endif /* __LINUX_OF_GPIO_H */
--- /dev/null
+/*
+ * Generic I2C API implementation for PowerPC.
+ *
+ * Copyright (c) 2008 Jochen Friedrich <jochen@scram.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_OF_I2C_H
+#define __LINUX_OF_I2C_H
+
+#include <linux/i2c.h>
+
+#ifdef CONFIG_OF_I2C
+
+void of_register_i2c_devices(struct i2c_adapter *adap,
+ struct device_node *adap_node);
+
+#endif /* CONFIG_OF_I2C */
+
+#endif /* __LINUX_OF_I2C_H */
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/irqreturn.h>
+#include <linux/semaphore.h>
#include <asm/system.h>
#include <asm/ptrace.h>
-#include <asm/semaphore.h>
/* Define this later. */
struct parport;
--- /dev/null
+/*
+ * aspm.h
+ *
+ * PCI Express ASPM defines and function prototypes
+ *
+ * Copyright (C) 2007 Intel Corp.
+ * Zhang Yanmin (yanmin.zhang@intel.com)
+ * Shaohua Li (shaohua.li@intel.com)
+ *
+ * For more information, please consult the following manuals (look at
+ * http://www.pcisig.com/ for how to get them):
+ *
+ * PCI Express Specification
+ */
+
+#ifndef LINUX_ASPM_H
+#define LINUX_ASPM_H
+
+#include <linux/pci.h>
+
+#define PCIE_LINK_STATE_L0S 1
+#define PCIE_LINK_STATE_L1 2
+#define PCIE_LINK_STATE_CLKPM 4
+
+#ifdef CONFIG_PCIEASPM
+extern void pcie_aspm_init_link_state(struct pci_dev *pdev);
+extern void pcie_aspm_exit_link_state(struct pci_dev *pdev);
+extern void pcie_aspm_pm_state_change(struct pci_dev *pdev);
+extern void pci_disable_link_state(struct pci_dev *pdev, int state);
+#else
+static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
+{
+}
+static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev)
+{
+}
+static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev)
+{
+}
+static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
+{
+}
+#endif
+
+#ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
+extern void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
+extern void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
+#else
+static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
+{
+}
+static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
+{
+}
+#endif
+#endif /* LINUX_ASPM_H */
/* Include the pci register defines */
#include <linux/pci_regs.h>
+struct pci_vpd;
+
/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
u32 data[0];
};
+struct pcie_link_state;
/*
* The pci_dev structure is used to describe PCI devices.
*/
struct pci_dev {
- struct list_head global_list; /* node in list of all PCI devices */
struct list_head bus_list; /* node in per-bus list */
struct pci_bus *bus; /* bus this device is on */
struct pci_bus *subordinate; /* bus this device bridges to */
this is D0-D3, D0 being fully functional,
and D3 being off. */
+#ifdef CONFIG_PCIEASPM
+ struct pcie_link_state *link_state; /* ASPM link state. */
+#endif
+
pci_channel_state_t error_state; /* current connectivity state */
struct device dev; /* Generic device interface */
unsigned int transparent:1; /* Transparent PCI bridge */
unsigned int multifunction:1;/* Part of multi-function device */
/* keep track of device state */
+ unsigned int is_added:1;
unsigned int is_busmaster:1; /* device is busmaster */
unsigned int no_msi:1; /* device may not use msi */
unsigned int no_d1d2:1; /* only allow d0 or d3 */
#ifdef CONFIG_PCI_MSI
struct list_head msi_list;
#endif
+ struct pci_vpd *vpd;
};
extern struct pci_dev *alloc_pci_dev(void);
-#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
/* Do NOT directly access these two variables, unless you are arch specific pci
* code, or pci core code. */
extern struct list_head pci_root_buses; /* list of all known PCI buses */
-extern struct list_head pci_devices; /* list of all devices */
/* Some device drivers need know if pci is initiated */
extern int no_pci_devices(void);
struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
struct pci_dev *from);
-struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
- struct pci_dev *from);
-
struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
unsigned int ss_vendor, unsigned int ss_device,
- struct pci_dev *from);
+ const struct pci_dev *from);
struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
int pci_dev_present(const struct pci_device_id *ids);
-const struct pci_device_id *pci_find_present(const struct pci_device_id *ids);
int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
int where, u8 *val);
int pcie_set_readrq(struct pci_dev *dev, int rq);
void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
int __must_check pci_assign_resource(struct pci_dev *dev, int i);
-int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
int pci_select_bars(struct pci_dev *dev, unsigned long flags);
/* ROM control related routines */
void pci_assign_unassigned_resources(void);
void pdev_enable_device(struct pci_dev *);
void pdev_sort_resources(struct pci_dev *, struct resource_list *);
+int pci_enable_resources(struct pci_dev *, int mask);
void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
int (*)(struct pci_dev *, u8, u8));
#define HAVE_PCI_REQ_REGIONS 2
return NULL;
}
-static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
- unsigned int device,
- struct pci_dev *from)
-{
- return NULL;
-}
-
static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
unsigned int device,
unsigned int ss_vendor,
unsigned int ss_device,
- struct pci_dev *from)
+ const struct pci_dev *from)
{
return NULL;
}
#define pci_dev_present(ids) (0)
#define no_pci_devices() (1)
-#define pci_find_present(ids) (NULL)
#define pci_dev_put(dev) do { } while (0)
static inline void pci_set_master(struct pci_dev *dev)
#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
+#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
+#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
+#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
+#define PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */
#define PCI_EXP_LNKCTL 16 /* Link Control */
+#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */
+#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */
#define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
#define PCI_EXP_LNKSTA 18 /* Link Status */
+#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */
+#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCTL 24 /* Slot Control */
#define PCI_EXP_SLTSTA 26 /* Slot Status */
struct dev_pm_info {
pm_message_t power_state;
unsigned can_wakeup:1;
-#ifdef CONFIG_PM_SLEEP
unsigned should_wakeup:1;
+ bool sleeping:1; /* Owned by the PM core */
+#ifdef CONFIG_PM_SLEEP
struct list_head entry;
#endif
};
extern int device_suspend(pm_message_t state);
extern int device_prepare_suspend(pm_message_t state);
-#define device_set_wakeup_enable(dev,val) \
- ((dev)->power.should_wakeup = !!(val))
-#define device_may_wakeup(dev) \
- (device_can_wakeup(dev) && (dev)->power.should_wakeup)
-
extern void __suspend_report_result(const char *function, void *fn, int ret);
#define suspend_report_result(fn, ret) \
__suspend_report_result(__FUNCTION__, fn, ret); \
} while (0)
-/*
- * Platform hook to activate device wakeup capability, if that's not already
- * handled by enable_irq_wake() etc.
- * Returns zero on success, else negative errno
- */
-extern int (*platform_enable_wakeup)(struct device *dev, int is_on);
-
-static inline int call_platform_enable_wakeup(struct device *dev, int is_on)
-{
- if (platform_enable_wakeup)
- return (*platform_enable_wakeup)(dev, is_on);
- return 0;
-}
-
#else /* !CONFIG_PM_SLEEP */
static inline int device_suspend(pm_message_t state)
return 0;
}
-#define device_set_wakeup_enable(dev,val) do{}while(0)
-#define device_may_wakeup(dev) (0)
-
-#define suspend_report_result(fn, ret) do { } while (0)
-
-static inline int call_platform_enable_wakeup(struct device *dev, int is_on)
-{
- return 0;
-}
+#define suspend_report_result(fn, ret) do {} while (0)
#endif /* !CONFIG_PM_SLEEP */
-/* changes to device_may_wakeup take effect on the next pm state change.
- * by default, devices should wakeup if they can.
- */
-#define device_can_wakeup(dev) \
- ((dev)->power.can_wakeup)
-#define device_init_wakeup(dev,val) \
- do { \
- device_can_wakeup(dev) = !!(val); \
- device_set_wakeup_enable(dev,val); \
- } while(0)
-
/*
* Global Power Management flags
* Used to keep APM and ACPI from both being active
--- /dev/null
+/*
+ * pm_wakeup.h - Power management wakeup interface
+ *
+ * Copyright (C) 2008 Alan Stern
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _LINUX_PM_WAKEUP_H
+#define _LINUX_PM_WAKEUP_H
+
+#ifndef _DEVICE_H_
+# error "please don't include this file directly"
+#endif
+
+#ifdef CONFIG_PM
+
+/* changes to device_may_wakeup take effect on the next pm state change.
+ * by default, devices should wakeup if they can.
+ */
+static inline void device_init_wakeup(struct device *dev, int val)
+{
+ dev->power.can_wakeup = dev->power.should_wakeup = !!val;
+}
+
+static inline int device_can_wakeup(struct device *dev)
+{
+ return dev->power.can_wakeup;
+}
+
+static inline void device_set_wakeup_enable(struct device *dev, int val)
+{
+ dev->power.should_wakeup = !!val;
+}
+
+static inline int device_may_wakeup(struct device *dev)
+{
+ return dev->power.can_wakeup & dev->power.should_wakeup;
+}
+
+/*
+ * Platform hook to activate device wakeup capability, if that's not already
+ * handled by enable_irq_wake() etc.
+ * Returns zero on success, else negative errno
+ */
+extern int (*platform_enable_wakeup)(struct device *dev, int is_on);
+
+static inline int call_platform_enable_wakeup(struct device *dev, int is_on)
+{
+ if (platform_enable_wakeup)
+ return (*platform_enable_wakeup)(dev, is_on);
+ return 0;
+}
+
+#else /* !CONFIG_PM */
+
+/* For some reason the next two routines work even without CONFIG_PM */
+static inline void device_init_wakeup(struct device *dev, int val)
+{
+ dev->power.can_wakeup = !!val;
+}
+
+static inline int device_can_wakeup(struct device *dev)
+{
+ return dev->power.can_wakeup;
+}
+
+#define device_set_wakeup_enable(dev, val) do {} while (0)
+#define device_may_wakeup(dev) 0
+
+static inline int call_platform_enable_wakeup(struct device *dev, int is_on)
+{
+ return 0;
+}
+
+#endif /* !CONFIG_PM */
+
+#endif /* _LINUX_PM_WAKEUP_H */
#define PR_CAPBSET_READ 23
#define PR_CAPBSET_DROP 24
+/* Get/set the process' ability to use the timestamp counter instruction */
+#define PR_GET_TSC 25
+#define PR_SET_TSC 26
+# define PR_TSC_ENABLE 1 /* allow the use of the timestamp counter */
+# define PR_TSC_SIGSEGV 2 /* throw a SIGSEGV instead of reading the TSC */
+
#endif /* _LINUX_PRCTL_H */
#define _MD_H
#include <linux/blkdev.h>
-#include <asm/semaphore.h>
#include <linux/major.h>
#include <linux/ioctl.h>
#include <linux/types.h>
#define DEFINE_RAID_ATTRIBUTE(type, attr) \
static inline void \
raid_set_##attr(struct raid_template *r, struct device *dev, type value) { \
- struct class_device *cdev = \
+ struct device *device = \
attribute_container_find_class_device(&r->raid_attrs.ac, dev);\
struct raid_data *rd; \
- BUG_ON(!cdev); \
- rd = class_get_devdata(cdev); \
+ BUG_ON(!device); \
+ rd = dev_get_drvdata(device); \
rd->attr = value; \
} \
static inline type \
raid_get_##attr(struct raid_template *r, struct device *dev) { \
- struct class_device *cdev = \
+ struct device *device = \
attribute_container_find_class_device(&r->raid_attrs.ac, dev);\
struct raid_data *rd; \
- BUG_ON(!cdev); \
- rd = class_get_devdata(cdev); \
+ BUG_ON(!device); \
+ rd = dev_get_drvdata(device); \
return rd->attr; \
}
#include <linux/mm_types.h>
#include <asm/system.h>
-#include <asm/semaphore.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/cputime.h>
#define SD_POWERSAVINGS_BALANCE 256 /* Balance for power savings */
#define SD_SHARE_PKG_RESOURCES 512 /* Domain members share cpu pkg resources */
#define SD_SERIALIZE 1024 /* Only a single load balancing instance */
+#define SD_WAKE_IDLE_FAR 2048 /* Gain latency sacrificing cache hit */
#define BALANCE_FOR_MC_POWER \
(sched_smt_power_savings ? SD_POWERSAVINGS_BALANCE : 0)
u32 reciprocal_cpu_power;
};
+enum sched_domain_level {
+ SD_LV_NONE = 0,
+ SD_LV_SIBLING,
+ SD_LV_MC,
+ SD_LV_CPU,
+ SD_LV_NODE,
+ SD_LV_ALLNODES,
+ SD_LV_MAX
+};
+
+struct sched_domain_attr {
+ int relax_domain_level;
+};
+
+#define SD_ATTR_INIT (struct sched_domain_attr) { \
+ .relax_domain_level = -1, \
+}
+
struct sched_domain {
/* These fields must be setup */
struct sched_domain *parent; /* top domain must be null terminated */
struct sched_domain *child; /* bottom domain must be null terminated */
struct sched_group *groups; /* the balancing groups of the domain */
cpumask_t span; /* span of all CPUs in this domain */
+ int first_cpu; /* cache of the first cpu in this domain */
unsigned long min_interval; /* Minimum balance interval ms */
unsigned long max_interval; /* Maximum balance interval ms */
unsigned int busy_factor; /* less balancing by factor if busy */
unsigned int wake_idx;
unsigned int forkexec_idx;
int flags; /* See SD_* */
+ enum sched_domain_level level;
/* Runtime fields. */
unsigned long last_balance; /* init to jiffies. units in jiffies */
#endif
};
-extern void partition_sched_domains(int ndoms_new, cpumask_t *doms_new);
+extern void partition_sched_domains(int ndoms_new, cpumask_t *doms_new,
+ struct sched_domain_attr *dattr_new);
extern int arch_reinit_sched_domains(void);
#endif /* CONFIG_SMP */
void (*set_curr_task) (struct rq *rq);
void (*task_tick) (struct rq *rq, struct task_struct *p, int queued);
void (*task_new) (struct rq *rq, struct task_struct *p);
- void (*set_cpus_allowed)(struct task_struct *p, cpumask_t *newmask);
+ void (*set_cpus_allowed)(struct task_struct *p,
+ const cpumask_t *newmask);
void (*join_domain)(struct rq *rq);
void (*leave_domain)(struct rq *rq);
struct sched_entity {
struct load_weight load; /* for load-balancing */
struct rb_node run_node;
+ struct list_head group_node;
unsigned int on_rq;
u64 exec_start;
unsigned long timeout;
int nr_cpus_allowed;
+ struct sched_rt_entity *back;
#ifdef CONFIG_RT_GROUP_SCHED
struct sched_rt_entity *parent;
/* rq on which this entity is (to be) queued: */
#define used_math() tsk_used_math(current)
#ifdef CONFIG_SMP
-extern int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask);
+extern int set_cpus_allowed_ptr(struct task_struct *p,
+ const cpumask_t *new_mask);
#else
-static inline int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask)
+static inline int set_cpus_allowed_ptr(struct task_struct *p,
+ const cpumask_t *new_mask)
{
- if (!cpu_isset(0, new_mask))
+ if (!cpu_isset(0, *new_mask))
return -EINVAL;
return 0;
}
#endif
+static inline int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask)
+{
+ return set_cpus_allowed_ptr(p, &new_mask);
+}
extern unsigned long long sched_clock(void);
extern unsigned int sysctl_sched_latency;
extern unsigned int sysctl_sched_min_granularity;
extern unsigned int sysctl_sched_wakeup_granularity;
-extern unsigned int sysctl_sched_batch_wakeup_granularity;
extern unsigned int sysctl_sched_child_runs_first;
extern unsigned int sysctl_sched_features;
extern unsigned int sysctl_sched_migration_cost;
extern unsigned int sysctl_sched_rt_period;
extern int sysctl_sched_rt_runtime;
+int sched_rt_handler(struct ctl_table *table, int write,
+ struct file *filp, void __user *buffer, size_t *lenp,
+ loff_t *ppos);
+
extern unsigned int sysctl_sched_compat_yield;
#ifdef CONFIG_RT_MUTEXES
}
#endif
-extern long sched_setaffinity(pid_t pid, cpumask_t new_mask);
+extern long sched_setaffinity(pid_t pid, const cpumask_t *new_mask);
extern long sched_getaffinity(pid_t pid, cpumask_t *mask);
extern int sched_mc_power_savings, sched_smt_power_savings;
#ifdef CONFIG_GROUP_SCHED
extern struct task_group init_task_group;
+#ifdef CONFIG_USER_SCHED
+extern struct task_group root_task_group;
+#endif
-extern struct task_group *sched_create_group(void);
+extern struct task_group *sched_create_group(struct task_group *parent);
extern void sched_destroy_group(struct task_group *tg);
extern void sched_move_task(struct task_struct *tsk);
#ifdef CONFIG_FAIR_GROUP_SCHED
extern int sched_group_set_rt_runtime(struct task_group *tg,
long rt_runtime_us);
extern long sched_group_rt_runtime(struct task_group *tg);
+extern int sched_group_set_rt_period(struct task_group *tg,
+ long rt_period_us);
+extern long sched_group_rt_period(struct task_group *tg);
#endif
#endif
* loopback/bind mount (@flags & MS_BIND), @dev_name identifies the
* pathname of the object being mounted.
* @dev_name contains the name for object being mounted.
- * @nd contains the nameidata structure for mount point object.
+ * @path contains the path for mount point object.
* @type contains the filesystem type.
* @flags contains the mount flags.
* @data contains the filesystem-specific data.
* Check permission before the device with superblock @mnt->sb is mounted
* on the mount point named by @nd.
* @mnt contains the vfsmount for device being mounted.
- * @nd contains the nameidata object for the mount point.
+ * @path contains the path for the mount point.
* Return 0 if permission is granted.
* @sb_umount:
* Check permission before the @mnt file system is unmounted.
* This hook is called any time a mount is successfully grafetd to
* the tree.
* @mnt contains the mounted filesystem.
- * @mountpoint_nd contains the nameidata structure for the mount point.
+ * @mountpoint contains the path for the mount point.
* @sb_pivotroot:
* Check permission before pivoting the root filesystem.
- * @old_nd contains the nameidata structure for the new location of the current root (put_old).
- * @new_nd contains the nameidata structure for the new root (new_root).
+ * @old_path contains the path for the new location of the current root (put_old).
+ * @new_path contains the path for the new root (new_root).
* Return 0 if permission is granted.
* @sb_post_pivotroot:
* Update module state after a successful pivot.
- * @old_nd contains the nameidata structure for the old root.
- * @new_nd contains the nameidata structure for the new root.
+ * @old_path contains the path for the old root.
+ * @new_path contains the path for the new root.
* @sb_get_mnt_opts:
* Get the security relevant mount options used for a superblock
* @sb the superblock to get security mount options from
int (*sb_copy_data)(char *orig, char *copy);
int (*sb_kern_mount) (struct super_block *sb, void *data);
int (*sb_statfs) (struct dentry *dentry);
- int (*sb_mount) (char *dev_name, struct nameidata * nd,
+ int (*sb_mount) (char *dev_name, struct path *path,
char *type, unsigned long flags, void *data);
- int (*sb_check_sb) (struct vfsmount * mnt, struct nameidata * nd);
+ int (*sb_check_sb) (struct vfsmount * mnt, struct path *path);
int (*sb_umount) (struct vfsmount * mnt, int flags);
void (*sb_umount_close) (struct vfsmount * mnt);
void (*sb_umount_busy) (struct vfsmount * mnt);
void (*sb_post_remount) (struct vfsmount * mnt,
unsigned long flags, void *data);
void (*sb_post_addmount) (struct vfsmount * mnt,
- struct nameidata * mountpoint_nd);
- int (*sb_pivotroot) (struct nameidata * old_nd,
- struct nameidata * new_nd);
- void (*sb_post_pivotroot) (struct nameidata * old_nd,
- struct nameidata * new_nd);
+ struct path *mountpoint);
+ int (*sb_pivotroot) (struct path *old_path,
+ struct path *new_path);
+ void (*sb_post_pivotroot) (struct path *old_path,
+ struct path *new_path);
int (*sb_get_mnt_opts) (const struct super_block *sb,
struct security_mnt_opts *opts);
int (*sb_set_mnt_opts) (struct super_block *sb,
int security_sb_copy_data(char *orig, char *copy);
int security_sb_kern_mount(struct super_block *sb, void *data);
int security_sb_statfs(struct dentry *dentry);
-int security_sb_mount(char *dev_name, struct nameidata *nd,
+int security_sb_mount(char *dev_name, struct path *path,
char *type, unsigned long flags, void *data);
-int security_sb_check_sb(struct vfsmount *mnt, struct nameidata *nd);
+int security_sb_check_sb(struct vfsmount *mnt, struct path *path);
int security_sb_umount(struct vfsmount *mnt, int flags);
void security_sb_umount_close(struct vfsmount *mnt);
void security_sb_umount_busy(struct vfsmount *mnt);
void security_sb_post_remount(struct vfsmount *mnt, unsigned long flags, void *data);
-void security_sb_post_addmount(struct vfsmount *mnt, struct nameidata *mountpoint_nd);
-int security_sb_pivotroot(struct nameidata *old_nd, struct nameidata *new_nd);
-void security_sb_post_pivotroot(struct nameidata *old_nd, struct nameidata *new_nd);
+void security_sb_post_addmount(struct vfsmount *mnt, struct path *mountpoint);
+int security_sb_pivotroot(struct path *old_path, struct path *new_path);
+void security_sb_post_pivotroot(struct path *old_path, struct path *new_path);
int security_sb_get_mnt_opts(const struct super_block *sb,
struct security_mnt_opts *opts);
int security_sb_set_mnt_opts(struct super_block *sb, struct security_mnt_opts *opts);
return 0;
}
-static inline int security_sb_mount (char *dev_name, struct nameidata *nd,
+static inline int security_sb_mount (char *dev_name, struct path *path,
char *type, unsigned long flags,
void *data)
{
}
static inline int security_sb_check_sb (struct vfsmount *mnt,
- struct nameidata *nd)
+ struct path *path)
{
return 0;
}
{ }
static inline void security_sb_post_addmount (struct vfsmount *mnt,
- struct nameidata *mountpoint_nd)
+ struct path *mountpoint)
{ }
-static inline int security_sb_pivotroot (struct nameidata *old_nd,
- struct nameidata *new_nd)
+static inline int security_sb_pivotroot (struct path *old_path,
+ struct path *new_path)
{
return 0;
}
-static inline void security_sb_post_pivotroot (struct nameidata *old_nd,
- struct nameidata *new_nd)
+static inline void security_sb_post_pivotroot (struct path *old_path,
+ struct path *new_path)
{ }
static inline int security_sb_get_mnt_opts(const struct super_block *sb,
struct security_mnt_opts *opts)
int (*show) (struct seq_file *m, void *v);
};
+#define SEQ_SKIP 1
+
int seq_open(struct file *, const struct seq_operations *);
ssize_t seq_read(struct file *, char __user *, size_t, loff_t *);
loff_t seq_lseek(struct file *, loff_t, int);
#include <linux/capability.h>
#include <linux/list.h>
#include <linux/sem.h>
-#include <asm/semaphore.h>
#include <asm/siginfo.h>
#include <asm/signal.h>
#include <linux/quota.h>
ssize_t (*store)(struct sysdev_class *, const char *, size_t);
};
-#define SYSDEV_CLASS_ATTR(_name,_mode,_show,_store) \
-struct sysdev_class_attribute attr_##_name = { \
+#define _SYSDEV_CLASS_ATTR(_name,_mode,_show,_store) \
+{ \
.attr = {.name = __stringify(_name), .mode = _mode }, \
.show = _show, \
.store = _store, \
-};
+}
+
+#define SYSDEV_CLASS_ATTR(_name,_mode,_show,_store) \
+ struct sysdev_class_attribute attr_##_name = \
+ _SYSDEV_CLASS_ATTR(_name,_mode,_show,_store)
extern int sysdev_class_register(struct sysdev_class *);
};
-#define _SYSDEV_ATTR(_name,_mode,_show,_store) \
+#define _SYSDEV_ATTR(_name, _mode, _show, _store) \
{ \
.attr = { .name = __stringify(_name), .mode = _mode }, \
.show = _show, \
.store = _store, \
}
-#define SYSDEV_ATTR(_name,_mode,_show,_store) \
-struct sysdev_attribute attr_##_name = _SYSDEV_ATTR(_name,_mode,_show,_store);
+#define SYSDEV_ATTR(_name, _mode, _show, _store) \
+ struct sysdev_attribute attr_##_name = \
+ _SYSDEV_ATTR(_name, _mode, _show, _store);
extern int sysdev_create_file(struct sys_device *, struct sysdev_attribute *);
extern void sysdev_remove_file(struct sys_device *, struct sysdev_attribute *);
static inline void sysfs_remove_dir(struct kobject *kobj)
{
- ;
}
static inline int sysfs_rename_dir(struct kobject *kobj, const char *new_name)
static inline void sysfs_remove_file(struct kobject *kobj,
const struct attribute *attr)
{
- ;
}
static inline int sysfs_create_bin_file(struct kobject *kobj,
return 0;
}
-static inline int sysfs_remove_bin_file(struct kobject *kobj,
- struct bin_attribute *attr)
+static inline void sysfs_remove_bin_file(struct kobject *kobj,
+ struct bin_attribute *attr)
{
- return 0;
}
static inline int sysfs_create_link(struct kobject *kobj,
static inline void sysfs_remove_link(struct kobject *kobj, const char *name)
{
- ;
}
static inline int sysfs_create_group(struct kobject *kobj,
static inline void sysfs_remove_group(struct kobject *kobj,
const struct attribute_group *grp)
{
- ;
}
static inline int sysfs_add_file_to_group(struct kobject *kobj,
#endif
#ifndef nr_cpus_node
-#define nr_cpus_node(node) \
- ({ \
- cpumask_t __tmp__; \
- __tmp__ = node_to_cpumask(node); \
- cpus_weight(__tmp__); \
+#define nr_cpus_node(node) \
+ ({ \
+ node_to_cpumask_ptr(__tmp__, node); \
+ cpus_weight(*__tmp__); \
})
#endif
-#define for_each_node_with_cpus(node) \
- for_each_online_node(node) \
+#define for_each_node_with_cpus(node) \
+ for_each_online_node(node) \
if (nr_cpus_node(node))
void arch_update_cpu_topology(void);
* by defining their own arch-specific initializer in include/asm/topology.h.
* A definition there will automagically override these default initializers
* and allow arch-specific performance tuning of sched_domains.
+ * (Only non-zero and non-null fields need be specified.)
*/
+
#ifdef CONFIG_SCHED_SMT
/* MCD - Do we really need this? It is always on if CONFIG_SCHED_SMT is,
* so can't we drop this in favor of CONFIG_SCHED_SMT?
/* Common values for SMT siblings */
#ifndef SD_SIBLING_INIT
#define SD_SIBLING_INIT (struct sched_domain) { \
- .span = CPU_MASK_NONE, \
- .parent = NULL, \
- .child = NULL, \
- .groups = NULL, \
.min_interval = 1, \
.max_interval = 2, \
.busy_factor = 64, \
.imbalance_pct = 110, \
- .cache_nice_tries = 0, \
- .busy_idx = 0, \
- .idle_idx = 0, \
- .newidle_idx = 0, \
- .wake_idx = 0, \
- .forkexec_idx = 0, \
.flags = SD_LOAD_BALANCE \
| SD_BALANCE_NEWIDLE \
| SD_BALANCE_FORK \
| SD_SHARE_CPUPOWER, \
.last_balance = jiffies, \
.balance_interval = 1, \
- .nr_balance_failed = 0, \
}
#endif
#endif /* CONFIG_SCHED_SMT */
/* Common values for MC siblings. for now mostly derived from SD_CPU_INIT */
#ifndef SD_MC_INIT
#define SD_MC_INIT (struct sched_domain) { \
- .span = CPU_MASK_NONE, \
- .parent = NULL, \
- .child = NULL, \
- .groups = NULL, \
.min_interval = 1, \
.max_interval = 4, \
.busy_factor = 64, \
.imbalance_pct = 125, \
.cache_nice_tries = 1, \
.busy_idx = 2, \
- .idle_idx = 0, \
- .newidle_idx = 0, \
.wake_idx = 1, \
.forkexec_idx = 1, \
.flags = SD_LOAD_BALANCE \
| BALANCE_FOR_MC_POWER, \
.last_balance = jiffies, \
.balance_interval = 1, \
- .nr_balance_failed = 0, \
}
#endif
#endif /* CONFIG_SCHED_MC */
/* Common values for CPUs */
#ifndef SD_CPU_INIT
#define SD_CPU_INIT (struct sched_domain) { \
- .span = CPU_MASK_NONE, \
- .parent = NULL, \
- .child = NULL, \
- .groups = NULL, \
.min_interval = 1, \
.max_interval = 4, \
.busy_factor = 64, \
| BALANCE_FOR_PKG_POWER,\
.last_balance = jiffies, \
.balance_interval = 1, \
- .nr_balance_failed = 0, \
}
#endif
/* sched_domains SD_ALLNODES_INIT for NUMA machines */
#define SD_ALLNODES_INIT (struct sched_domain) { \
- .span = CPU_MASK_NONE, \
- .parent = NULL, \
- .child = NULL, \
- .groups = NULL, \
.min_interval = 64, \
.max_interval = 64*num_online_cpus(), \
.busy_factor = 128, \
.cache_nice_tries = 1, \
.busy_idx = 3, \
.idle_idx = 3, \
- .newidle_idx = 0, /* unused */ \
- .wake_idx = 0, /* unused */ \
- .forkexec_idx = 0, /* unused */ \
.flags = SD_LOAD_BALANCE \
| SD_SERIALIZE, \
.last_balance = jiffies, \
.balance_interval = 64, \
- .nr_balance_failed = 0, \
}
#ifdef CONFIG_NUMA
struct transport_class {
struct class class;
int (*setup)(struct transport_container *, struct device *,
- struct class_device *);
+ struct device *);
int (*configure)(struct transport_container *, struct device *,
- struct class_device *);
+ struct device *);
int (*remove)(struct transport_container *, struct device *,
- struct class_device *);
+ struct device *);
};
#define DECLARE_TRANSPORT_CLASS(cls, nm, su, rm, cfg) \
+++ /dev/null
-/*
- * udf_fs.h
- *
- * PURPOSE
- * Included by fs/filesystems.c
- *
- * DESCRIPTION
- * OSTA-UDF(tm) = Optical Storage Technology Association
- * Universal Disk Format.
- *
- * This code is based on version 2.50 of the UDF specification,
- * and revision 3 of the ECMA 167 standard [equivalent to ISO 13346].
- * http://www.osta.org/ * http://www.ecma.ch/
- * http://www.iso.org/
- *
- * COPYRIGHT
- * This file is distributed under the terms of the GNU General Public
- * License (GPL). Copies of the GPL can be obtained from:
- * ftp://prep.ai.mit.edu/pub/gnu/GPL
- * Each contributing author retains all rights to their own work.
- *
- * (C) 1999-2004 Ben Fennema
- * (C) 1999-2000 Stelias Computing Inc
- *
- * HISTORY
- *
- */
-
-#ifndef _UDF_FS_H
-#define _UDF_FS_H 1
-
-#define UDF_PREALLOCATE
-#define UDF_DEFAULT_PREALLOC_BLOCKS 8
-
-#undef UDFFS_DEBUG
-
-#ifdef UDFFS_DEBUG
-#define udf_debug(f, a...) \
- do { \
- printk (KERN_DEBUG "UDF-fs DEBUG %s:%d:%s: ", \
- __FILE__, __LINE__, __FUNCTION__); \
- printk (f, ##a); \
- } while (0)
-#else
-#define udf_debug(f, a...) /**/
-#endif
-
-#define udf_info(f, a...) \
- printk (KERN_INFO "UDF-fs INFO " f, ##a);
-
-#endif /* _UDF_FS_H */
* ftp://prep.ai.mit.edu/pub/gnu/GPL
* Each contributing author retains all rights to their own work.
*/
-
#ifndef _UDF_FS_I_H
#define _UDF_FS_I_H 1
-#ifdef __KERNEL__
-
-struct udf_inode_info
-{
- struct timespec i_crtime;
- /* Physical address of inode */
- kernel_lb_addr i_location;
- __u64 i_unique;
- __u32 i_lenEAttr;
- __u32 i_lenAlloc;
- __u64 i_lenExtents;
- __u32 i_next_alloc_block;
- __u32 i_next_alloc_goal;
- unsigned i_alloc_type : 3;
- unsigned i_efe : 1;
- unsigned i_use : 1;
- unsigned i_strat4096 : 1;
- unsigned reserved : 26;
- union
- {
- short_ad *i_sad;
- long_ad *i_lad;
- __u8 *i_data;
- } i_ext;
- struct inode vfs_inode;
-};
-
-#endif
-
/* exported IOCTLs, we have 'l', 0x40-0x7f */
-
#define UDF_GETEASIZE _IOR('l', 0x40, int)
#define UDF_GETEABLOCK _IOR('l', 0x41, void *)
#define UDF_GETVOLIDENT _IOR('l', 0x42, void *)
+++ /dev/null
-/*
- * udf_fs_sb.h
- *
- * This include file is for the Linux kernel/module.
- *
- * COPYRIGHT
- * This file is distributed under the terms of the GNU General Public
- * License (GPL). Copies of the GPL can be obtained from:
- * ftp://prep.ai.mit.edu/pub/gnu/GPL
- * Each contributing author retains all rights to their own work.
- */
-
-#ifndef _UDF_FS_SB_H
-#define _UDF_FS_SB_H 1
-
-#include <linux/mutex.h>
-
-#pragma pack(1)
-
-#define UDF_MAX_BLOCK_LOADED 8
-
-#define UDF_TYPE1_MAP15 0x1511U
-#define UDF_VIRTUAL_MAP15 0x1512U
-#define UDF_VIRTUAL_MAP20 0x2012U
-#define UDF_SPARABLE_MAP15 0x1522U
-
-struct udf_sparing_data
-{
- __u16 s_packet_len;
- struct buffer_head *s_spar_map[4];
-};
-
-struct udf_virtual_data
-{
- __u32 s_num_entries;
- __u16 s_start_offset;
-};
-
-struct udf_bitmap
-{
- __u32 s_extLength;
- __u32 s_extPosition;
- __u16 s_nr_groups;
- struct buffer_head **s_block_bitmap;
-};
-
-struct udf_part_map
-{
- union
- {
- struct udf_bitmap *s_bitmap;
- struct inode *s_table;
- } s_uspace;
- union
- {
- struct udf_bitmap *s_bitmap;
- struct inode *s_table;
- } s_fspace;
- __u32 s_partition_root;
- __u32 s_partition_len;
- __u16 s_partition_type;
- __u16 s_partition_num;
- union
- {
- struct udf_sparing_data s_sparing;
- struct udf_virtual_data s_virtual;
- } s_type_specific;
- __u32 (*s_partition_func)(struct super_block *, __u32, __u16, __u32);
- __u16 s_volumeseqnum;
- __u16 s_partition_flags;
-};
-
-#pragma pack()
-
-struct udf_sb_info
-{
- struct udf_part_map *s_partmaps;
- __u8 s_volume_ident[32];
-
- /* Overall info */
- __u16 s_partitions;
- __u16 s_partition;
-
- /* Sector headers */
- __s32 s_session;
- __u32 s_anchor[4];
- __u32 s_last_block;
-
- struct buffer_head *s_lvid_bh;
-
- /* Default permissions */
- mode_t s_umask;
- gid_t s_gid;
- uid_t s_uid;
-
- /* Root Info */
- struct timespec s_record_time;
-
- /* Fileset Info */
- __u16 s_serial_number;
-
- /* highest UDF revision we have recorded to this media */
- __u16 s_udfrev;
-
- /* Miscellaneous flags */
- __u32 s_flags;
-
- /* Encoding info */
- struct nls_table *s_nls_map;
-
- /* VAT inode */
- struct inode *s_vat_inode;
-
- struct mutex s_alloc_mutex;
-};
-
-#endif /* _UDF_FS_SB_H */
--- /dev/null
+/*
+ * Platform data definitions for Atmel USBA gadget driver.
+ */
+#ifndef __LINUX_USB_USBA_H
+#define __LINUX_USB_USBA_H
+
+struct usba_ep_data {
+ char *name;
+ int index;
+ int fifo_size;
+ int nr_banks;
+ int can_dma;
+ int can_isoc;
+};
+
+struct usba_platform_data {
+ int vbus_pin;
+ int num_ep;
+ struct usba_ep_data ep[0];
+};
+
+#endif /* __LINUX_USB_USBA_H */
struct ib_dma_mapping_ops *dma_ops;
struct module *owner;
- struct class_device class_dev;
+ struct device dev;
struct kobject *ports_parent;
struct list_head port_list;
#include <scsi/sas.h>
#include <linux/libata.h>
#include <linux/list.h>
-#include <asm/semaphore.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_transport_sas.h>
int timeout;
- struct device sdev_gendev;
- struct class_device sdev_classdev;
+ struct device sdev_gendev,
+ sdev_dev;
struct execute_work ew; /* used to get process context on put */
#define to_scsi_device(d) \
container_of(d, struct scsi_device, sdev_gendev)
#define class_to_sdev(d) \
- container_of(d, struct scsi_device, sdev_classdev)
+ container_of(d, struct scsi_device, sdev_dev)
#define transport_class_to_sdev(class_dev) \
- to_scsi_device(class_dev->dev)
+ to_scsi_device(class_dev->parent)
#define sdev_printk(prefix, sdev, fmt, a...) \
dev_printk(prefix, &(sdev)->sdev_gendev, fmt, ##a)
return to_scsi_target(sdev->sdev_gendev.parent);
}
#define transport_class_to_starget(class_dev) \
- to_scsi_target(class_dev->dev)
+ to_scsi_target(class_dev->parent)
#define starget_printk(prefix, starget, fmt, a...) \
dev_printk(prefix, &(starget)->dev, fmt, ##a)
/*
* Pointer to the sysfs class properties for this host, NULL terminated.
*/
- struct class_device_attribute **shost_attrs;
+ struct device_attribute **shost_attrs;
/*
* Pointer to the SCSI device properties for this host, NULL terminated.
enum scsi_host_state shost_state;
/* ldm bits */
- struct device shost_gendev;
- struct class_device shost_classdev;
+ struct device shost_gendev, shost_dev;
/*
* List of hosts per template.
};
#define class_to_shost(d) \
- container_of(d, struct Scsi_Host, shost_classdev)
+ container_of(d, struct Scsi_Host, shost_dev)
#define shost_printk(prefix, shost, fmt, a...) \
dev_printk(prefix, &(shost)->shost_gendev, fmt, ##a)
};
#define transport_class_to_shost(tc) \
- dev_to_shost((tc)->dev)
+ dev_to_shost((tc)->parent)
/* Private area maintenance. The driver requested allocations come
/* Macro for use in defining Virtual Port attributes */
-#define FC_VPORT_ATTR(_name,_mode,_show,_store) \
-struct class_device_attribute class_device_attr_vport_##_name = \
+#define FC_VPORT_ATTR(_name,_mode,_show,_store) \
+struct device_attribute dev_attr_vport_##_name = \
__ATTR(_name,_mode,_show,_store)
#define dev_to_vport(d) \
container_of(d, struct fc_vport, dev)
-#define transport_class_to_vport(classdev) \
- dev_to_vport(classdev->dev)
+#define transport_class_to_vport(dev) \
+ dev_to_vport(dev->parent)
#define vport_to_shost(v) \
(v->shost)
#define vport_to_shost_channel(v) \
/* Macro for use in defining Remote Port attributes */
#define FC_RPORT_ATTR(_name,_mode,_show,_store) \
-struct class_device_attribute class_device_attr_rport_##_name = \
+struct device_attribute dev_attr_rport_##_name = \
__ATTR(_name,_mode,_show,_store)
#define dev_to_rport(d) \
container_of(d, struct fc_rport, dev)
-#define transport_class_to_rport(classdev) \
- dev_to_rport(classdev->dev)
+#define transport_class_to_rport(dev) \
+ dev_to_rport(dev->parent)
#define rport_to_shost(r) \
dev_to_shost(r->dev.parent)
#define dev_to_phy(d) \
container_of((d), struct sas_phy, dev)
-#define transport_class_to_phy(cdev) \
- dev_to_phy((cdev)->dev)
+#define transport_class_to_phy(dev) \
+ dev_to_phy((dev)->parent)
#define phy_to_shost(phy) \
dev_to_shost((phy)->dev.parent)
#define dev_to_rphy(d) \
container_of((d), struct sas_rphy, dev)
-#define transport_class_to_rphy(cdev) \
- dev_to_rphy((cdev)->dev)
+#define transport_class_to_rphy(dev) \
+ dev_to_rphy((dev)->parent)
#define rphy_to_shost(rphy) \
dev_to_shost((rphy)->dev.parent)
#define target_to_rphy(targ) \
#define dev_to_sas_port(d) \
container_of((d), struct sas_port, dev)
-#define transport_class_to_sas_port(cdev) \
- dev_to_sas_port((cdev)->dev)
+#define transport_class_to_sas_port(dev) \
+ dev_to_sas_port((dev)->parent)
struct sas_phy_linkrates {
enum sas_linkrate maximum_linkrate;
struct scsi_disk {
struct scsi_driver *driver; /* always &sd_template */
struct scsi_device *device;
- struct class_device cdev;
+ struct device dev;
struct gendisk *disk;
unsigned int openers; /* protected by BKL for now, yuck */
sector_t capacity; /* size in 512-byte sectors */
unsigned RCD : 1; /* state of disk RCD bit, unused */
unsigned DPOFUA : 1; /* state of disk DPOFUA bit */
};
-#define to_scsi_disk(obj) container_of(obj,struct scsi_disk,cdev)
+#define to_scsi_disk(obj) container_of(obj,struct scsi_disk,dev)
#define sd_printk(prefix, sdsk, fmt, a...) \
(sdsk)->disk ? \
depends on EXPERIMENTAL
depends on GROUP_SCHED
default n
+ help
+ This feature lets you explicitly allocate real CPU bandwidth
+ to users or control groups (depending on the "Basis for grouping tasks"
+ setting below. If enabled, it will also make it impossible to
+ schedule realtime tasks for non-root users until you allocate
+ realtime bandwidth for them.
+ See Documentation/sched-rt-group.txt for more information.
choice
depends on GROUP_SCHED
#endif
static inline void setup_per_cpu_areas(void) { }
+static inline void setup_nr_cpu_ids(void) { }
static inline void smp_prepare_cpus(unsigned int maxcpus) { }
#else
+#if NR_CPUS > BITS_PER_LONG
+cpumask_t cpu_mask_all __read_mostly = CPU_MASK_ALL;
+EXPORT_SYMBOL(cpu_mask_all);
+#endif
+
+/* Setup number of possible processor ids */
+int nr_cpu_ids __read_mostly = NR_CPUS;
+EXPORT_SYMBOL(nr_cpu_ids);
+
+/* An arch may set nr_cpu_ids earlier if needed, so this would be redundant */
+static void __init setup_nr_cpu_ids(void)
+{
+ int cpu, highest_cpu = 0;
+
+ for_each_possible_cpu(cpu)
+ highest_cpu = cpu;
+
+ nr_cpu_ids = highest_cpu + 1;
+}
+
#ifndef CONFIG_HAVE_SETUP_PER_CPU_AREA
unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
setup_command_line(command_line);
unwind_setup();
setup_per_cpu_areas();
+ setup_nr_cpu_ids();
smp_prepare_boot_cpu(); /* arch-specific boot-cpu hooks */
/*
/*
* init can run on any cpu.
*/
- set_cpus_allowed(current, CPU_MASK_ALL);
+ set_cpus_allowed_ptr(current, CPU_MASK_ALL_PTR);
/*
* Tell the world that we're going to be the grim
* reaper of innocent orphaned children.
int oflag, mode_t mode, struct mq_attr __user *u_attr)
{
struct mq_attr attr;
+ struct file *result;
int ret;
if (u_attr) {
}
mode &= ~current->fs->umask;
+ ret = mnt_want_write(mqueue_mnt);
+ if (ret)
+ goto out;
ret = vfs_create(dir->d_inode, dentry, mode, NULL);
dentry->d_fsdata = NULL;
if (ret)
- goto out;
-
- return dentry_open(dentry, mqueue_mnt, oflag);
-
+ goto out_drop_write;
+
+ result = dentry_open(dentry, mqueue_mnt, oflag);
+ /*
+ * dentry_open() took a persistent mnt_want_write(),
+ * so we can now drop this one.
+ */
+ mnt_drop_write(mqueue_mnt);
+ return result;
+
+out_drop_write:
+ mnt_drop_write(mqueue_mnt);
out:
dput(dentry);
mntput(mqueue_mnt);
inode = dentry->d_inode;
if (inode)
atomic_inc(&inode->i_count);
-
+ err = mnt_want_write(mqueue_mnt);
+ if (err)
+ goto out_err;
err = vfs_unlink(dentry->d_parent->d_inode, dentry);
+ mnt_drop_write(mqueue_mnt);
out_err:
dput(dentry);
if (retval)
return retval;
- return sched_setaffinity(pid, new_mask);
+ return sched_setaffinity(pid, &new_mask);
}
asmlinkage long compat_sys_sched_getaffinity(compat_pid_t pid, unsigned int len,
/* Ensure that we are not runnable on dying cpu */
old_allowed = current->cpus_allowed;
- tmp = CPU_MASK_ALL;
+ cpus_setall(tmp);
cpu_clear(cpu, tmp);
- set_cpus_allowed(current, tmp);
+ set_cpus_allowed_ptr(current, &tmp);
p = __stop_machine_run(take_cpu_down, &tcd_param, cpu);
out_thread:
err = kthread_stop(p);
out_allowed:
- set_cpus_allowed(current, old_allowed);
+ set_cpus_allowed_ptr(current, &old_allowed);
out_release:
cpu_hotplug_done();
return err;
/* partition number for rebuild_sched_domains() */
int pn;
+ /* for custom sched domain */
+ int relax_domain_level;
+
/* used for walking a cpuset heirarchy */
struct list_head stack_list;
};
return cpus_intersects(a->cpus_allowed, b->cpus_allowed);
}
+static void
+update_domain_attr(struct sched_domain_attr *dattr, struct cpuset *c)
+{
+ if (!dattr)
+ return;
+ if (dattr->relax_domain_level < c->relax_domain_level)
+ dattr->relax_domain_level = c->relax_domain_level;
+ return;
+}
+
/*
* rebuild_sched_domains()
*
int csn; /* how many cpuset ptrs in csa so far */
int i, j, k; /* indices for partition finding loops */
cpumask_t *doms; /* resulting partition; i.e. sched domains */
+ struct sched_domain_attr *dattr; /* attributes for custom domains */
int ndoms; /* number of sched domains in result */
int nslot; /* next empty doms[] cpumask_t slot */
q = NULL;
csa = NULL;
doms = NULL;
+ dattr = NULL;
/* Special case for the 99% of systems with one, full, sched domain */
if (is_sched_load_balance(&top_cpuset)) {
doms = kmalloc(sizeof(cpumask_t), GFP_KERNEL);
if (!doms)
goto rebuild;
+ dattr = kmalloc(sizeof(struct sched_domain_attr), GFP_KERNEL);
+ if (dattr) {
+ *dattr = SD_ATTR_INIT;
+ update_domain_attr(dattr, &top_cpuset);
+ }
*doms = top_cpuset.cpus_allowed;
goto rebuild;
}
doms = kmalloc(ndoms * sizeof(cpumask_t), GFP_KERNEL);
if (!doms)
goto rebuild;
+ dattr = kmalloc(ndoms * sizeof(struct sched_domain_attr), GFP_KERNEL);
for (nslot = 0, i = 0; i < csn; i++) {
struct cpuset *a = csa[i];
}
cpus_clear(*dp);
+ if (dattr)
+ *(dattr + nslot) = SD_ATTR_INIT;
for (j = i; j < csn; j++) {
struct cpuset *b = csa[j];
if (apn == b->pn) {
cpus_or(*dp, *dp, b->cpus_allowed);
b->pn = -1;
+ update_domain_attr(dattr, b);
}
}
nslot++;
rebuild:
/* Have scheduler rebuild sched domains */
get_online_cpus();
- partition_sched_domains(ndoms, doms);
+ partition_sched_domains(ndoms, doms, dattr);
put_online_cpus();
done:
kfifo_free(q);
kfree(csa);
/* Don't kfree(doms) -- partition_sched_domains() does that. */
+ /* Don't kfree(dattr) -- partition_sched_domains() does that. */
}
static inline int started_after_time(struct task_struct *t1,
*/
void cpuset_change_cpumask(struct task_struct *tsk, struct cgroup_scanner *scan)
{
- set_cpus_allowed(tsk, (cgroup_cs(scan->cg))->cpus_allowed);
+ set_cpus_allowed_ptr(tsk, &((cgroup_cs(scan->cg))->cpus_allowed));
}
/**
return 0;
}
+static int update_relax_domain_level(struct cpuset *cs, char *buf)
+{
+ int val = simple_strtol(buf, NULL, 10);
+
+ if (val < 0)
+ val = -1;
+
+ if (val != cs->relax_domain_level) {
+ cs->relax_domain_level = val;
+ rebuild_sched_domains();
+ }
+
+ return 0;
+}
+
/*
* update_flag - read a 0 or a 1 in a file and update associated flag
* bit: the bit to update (CS_CPU_EXCLUSIVE, CS_MEM_EXCLUSIVE,
mutex_lock(&callback_mutex);
guarantee_online_cpus(cs, &cpus);
- set_cpus_allowed(tsk, cpus);
+ set_cpus_allowed_ptr(tsk, &cpus);
mutex_unlock(&callback_mutex);
from = oldcs->mems_allowed;
FILE_CPU_EXCLUSIVE,
FILE_MEM_EXCLUSIVE,
FILE_SCHED_LOAD_BALANCE,
+ FILE_SCHED_RELAX_DOMAIN_LEVEL,
FILE_MEMORY_PRESSURE_ENABLED,
FILE_MEMORY_PRESSURE,
FILE_SPREAD_PAGE,
case FILE_SCHED_LOAD_BALANCE:
retval = update_flag(CS_SCHED_LOAD_BALANCE, cs, buffer);
break;
+ case FILE_SCHED_RELAX_DOMAIN_LEVEL:
+ retval = update_relax_domain_level(cs, buffer);
+ break;
case FILE_MEMORY_MIGRATE:
retval = update_flag(CS_MEMORY_MIGRATE, cs, buffer);
break;
case FILE_SCHED_LOAD_BALANCE:
*s++ = is_sched_load_balance(cs) ? '1' : '0';
break;
+ case FILE_SCHED_RELAX_DOMAIN_LEVEL:
+ s += sprintf(s, "%d", cs->relax_domain_level);
+ break;
case FILE_MEMORY_MIGRATE:
*s++ = is_memory_migrate(cs) ? '1' : '0';
break;
.private = FILE_SCHED_LOAD_BALANCE,
};
+static struct cftype cft_sched_relax_domain_level = {
+ .name = "sched_relax_domain_level",
+ .read = cpuset_common_file_read,
+ .write = cpuset_common_file_write,
+ .private = FILE_SCHED_RELAX_DOMAIN_LEVEL,
+};
+
static struct cftype cft_memory_migrate = {
.name = "memory_migrate",
.read = cpuset_common_file_read,
return err;
if ((err = cgroup_add_file(cont, ss, &cft_sched_load_balance)) < 0)
return err;
+ if ((err = cgroup_add_file(cont, ss,
+ &cft_sched_relax_domain_level)) < 0)
+ return err;
if ((err = cgroup_add_file(cont, ss, &cft_memory_pressure)) < 0)
return err;
if ((err = cgroup_add_file(cont, ss, &cft_spread_page)) < 0)
if (is_spread_slab(parent))
set_bit(CS_SPREAD_SLAB, &cs->flags);
set_bit(CS_SCHED_LOAD_BALANCE, &cs->flags);
- cs->cpus_allowed = CPU_MASK_NONE;
- cs->mems_allowed = NODE_MASK_NONE;
+ cpus_clear(cs->cpus_allowed);
+ nodes_clear(cs->mems_allowed);
cs->mems_generation = cpuset_mems_generation++;
fmeter_init(&cs->fmeter);
+ cs->relax_domain_level = -1;
cs->parent = parent;
number_of_cpusets++;
{
int err = 0;
- top_cpuset.cpus_allowed = CPU_MASK_ALL;
- top_cpuset.mems_allowed = NODE_MASK_ALL;
+ cpus_setall(top_cpuset.cpus_allowed);
+ nodes_setall(top_cpuset.mems_allowed);
fmeter_init(&top_cpuset.fmeter);
top_cpuset.mems_generation = cpuset_mems_generation++;
set_bit(CS_SCHED_LOAD_BALANCE, &top_cpuset.flags);
+ top_cpuset.relax_domain_level = -1;
err = register_filesystem(&cpuset_fs_type);
if (err < 0)
* cpuset_cpus_allowed - return cpus_allowed mask from a tasks cpuset.
* @tsk: pointer to task_struct from which to obtain cpuset->cpus_allowed.
+ * @pmask: pointer to cpumask_t variable to receive cpus_allowed set.
*
* Description: Returns the cpumask_t cpus_allowed of the cpuset
* attached to the specified @tsk. Guaranteed to return some non-empty
* tasks cpuset.
**/
-cpumask_t cpuset_cpus_allowed(struct task_struct *tsk)
+void cpuset_cpus_allowed(struct task_struct *tsk, cpumask_t *pmask)
{
- cpumask_t mask;
-
mutex_lock(&callback_mutex);
- mask = cpuset_cpus_allowed_locked(tsk);
+ cpuset_cpus_allowed_locked(tsk, pmask);
mutex_unlock(&callback_mutex);
-
- return mask;
}
/**
* cpuset_cpus_allowed_locked - return cpus_allowed mask from a tasks cpuset.
* Must be called with callback_mutex held.
**/
-cpumask_t cpuset_cpus_allowed_locked(struct task_struct *tsk)
+void cpuset_cpus_allowed_locked(struct task_struct *tsk, cpumask_t *pmask)
{
- cpumask_t mask;
-
task_lock(tsk);
- guarantee_online_cpus(task_cs(tsk), &mask);
+ guarantee_online_cpus(task_cs(tsk), pmask);
task_unlock(tsk);
-
- return mask;
}
void cpuset_init_current_mems_allowed(void)
{
- current->mems_allowed = NODE_MASK_ALL;
+ nodes_setall(current->mems_allowed);
}
/**
m->count += cpumask_scnprintf(m->buf + m->count, m->size - m->count,
task->cpus_allowed);
seq_printf(m, "\n");
+ seq_printf(m, "Cpus_allowed_list:\t");
+ m->count += cpulist_scnprintf(m->buf + m->count, m->size - m->count,
+ task->cpus_allowed);
+ seq_printf(m, "\n");
seq_printf(m, "Mems_allowed:\t");
m->count += nodemask_scnprintf(m->buf + m->count, m->size - m->count,
task->mems_allowed);
seq_printf(m, "\n");
+ seq_printf(m, "Mems_allowed_list:\t");
+ m->count += nodelist_scnprintf(m->buf + m->count, m->size - m->count,
+ task->mems_allowed);
+ seq_printf(m, "\n");
}
}
EXPORT_SYMBOL(reset_files_struct);
-static void __exit_files(struct task_struct *tsk)
+void exit_files(struct task_struct *tsk)
{
struct files_struct * files = tsk->files;
}
}
-void exit_files(struct task_struct *tsk)
-{
- __exit_files(tsk);
-}
-
-static void __put_fs_struct(struct fs_struct *fs)
+void put_fs_struct(struct fs_struct *fs)
{
/* No need to hold fs->lock if we are killing it */
if (atomic_dec_and_test(&fs->count)) {
}
}
-void put_fs_struct(struct fs_struct *fs)
-{
- __put_fs_struct(fs);
-}
-
-static void __exit_fs(struct task_struct *tsk)
+void exit_fs(struct task_struct *tsk)
{
struct fs_struct * fs = tsk->fs;
task_lock(tsk);
tsk->fs = NULL;
task_unlock(tsk);
- __put_fs_struct(fs);
+ put_fs_struct(fs);
}
}
-void exit_fs(struct task_struct *tsk)
-{
- __exit_fs(tsk);
-}
-
EXPORT_SYMBOL_GPL(exit_fs);
/*
if (group_dead)
acct_process();
exit_sem(tsk);
- __exit_files(tsk);
- __exit_fs(tsk);
+ exit_files(tsk);
+ exit_fs(tsk);
check_stack_usage();
exit_thread();
cgroup_exit(tsk, 1);
free_task(tsk);
}
+/*
+ * macro override instead of weak attribute alias, to workaround
+ * gcc 4.1.0 and 4.1.1 bugs with weak attribute and empty functions.
+ */
+#ifndef arch_task_cache_init
+#define arch_task_cache_init()
+#endif
+
void __init fork_init(unsigned long mempages)
{
#ifndef __HAVE_ARCH_TASK_STRUCT_ALLOCATOR
ARCH_MIN_TASKALIGN, SLAB_PANIC, NULL);
#endif
+ /* do the arch specific task caches init */
+ arch_task_cache_init();
+
/*
* The default maximum number of threads is set to a safe
* value: the thread structures can take up at most half
init_task.signal->rlim[RLIMIT_NPROC];
}
+int __attribute__((weak)) arch_dup_task_struct(struct task_struct *dst,
+ struct task_struct *src)
+{
+ *dst = *src;
+ return 0;
+}
+
static struct task_struct *dup_task_struct(struct task_struct *orig)
{
struct task_struct *tsk;
return NULL;
}
- *tsk = *orig;
+ err = arch_dup_task_struct(tsk, orig);
+ if (err)
+ goto out;
+
tsk->stack = ti;
err = prop_local_init_single(&tsk->dirties);
- if (err) {
- free_thread_info(ti);
- free_task_struct(tsk);
- return NULL;
- }
+ if (err)
+ goto out;
setup_thread_stack(tsk, orig);
#endif
tsk->splice_pipe = NULL;
return tsk;
+
+out:
+ free_thread_info(ti);
+ free_task_struct(tsk);
+ return NULL;
}
#ifdef CONFIG_MMU
/*
* Called from hardirq context every jiffy
*/
-static inline void run_hrtimer_queue(struct hrtimer_cpu_base *cpu_base,
- int index)
+void hrtimer_run_queues(void)
{
struct rb_node *node;
- struct hrtimer_clock_base *base = &cpu_base->clock_base[index];
+ struct hrtimer_cpu_base *cpu_base = &__get_cpu_var(hrtimer_bases);
+ struct hrtimer_clock_base *base;
+ int index, gettime = 1;
- if (!base->first)
+ if (hrtimer_hres_active())
return;
- if (base->get_softirq_time)
- base->softirq_time = base->get_softirq_time();
-
- spin_lock(&cpu_base->lock);
+ for (index = 0; index < HRTIMER_MAX_CLOCK_BASES; index++) {
+ base = &cpu_base->clock_base[index];
- while ((node = base->first)) {
- struct hrtimer *timer;
-
- timer = rb_entry(node, struct hrtimer, node);
- if (base->softirq_time.tv64 <= timer->expires.tv64)
- break;
-
- if (timer->cb_mode == HRTIMER_CB_SOFTIRQ) {
- __remove_hrtimer(timer, base, HRTIMER_STATE_PENDING, 0);
- list_add_tail(&timer->cb_entry,
- &base->cpu_base->cb_pending);
+ if (!base->first)
continue;
+
+ if (base->get_softirq_time)
+ base->softirq_time = base->get_softirq_time();
+ else if (gettime) {
+ hrtimer_get_softirq_time(cpu_base);
+ gettime = 0;
}
- __run_hrtimer(timer);
- }
- spin_unlock(&cpu_base->lock);
-}
+ spin_lock(&cpu_base->lock);
-void hrtimer_run_queues(void)
-{
- struct hrtimer_cpu_base *cpu_base = &__get_cpu_var(hrtimer_bases);
- int i;
+ while ((node = base->first)) {
+ struct hrtimer *timer;
- if (hrtimer_hres_active())
- return;
+ timer = rb_entry(node, struct hrtimer, node);
+ if (base->softirq_time.tv64 <= timer->expires.tv64)
+ break;
- hrtimer_get_softirq_time(cpu_base);
+ if (timer->cb_mode == HRTIMER_CB_SOFTIRQ) {
+ __remove_hrtimer(timer, base,
+ HRTIMER_STATE_PENDING, 0);
+ list_add_tail(&timer->cb_entry,
+ &base->cpu_base->cb_pending);
+ continue;
+ }
- for (i = 0; i < HRTIMER_MAX_CLOCK_BASES; i++)
- run_hrtimer_queue(cpu_base, i);
+ __run_hrtimer(timer);
+ }
+ spin_unlock(&cpu_base->lock);
+ }
}
/*
desc->irq_count = 0;
desc->irqs_unhandled = 0;
#ifdef CONFIG_SMP
- desc->affinity = CPU_MASK_ALL;
+ cpus_setall(desc->affinity);
#endif
spin_unlock_irqrestore(&desc->lock, flags);
}
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/system.h>
-#include <asm/semaphore.h>
#include <asm/sections.h>
/* Per cpu memory for storing cpu states in case of system crash. */
}
/* We can run anywhere, unlike our parent keventd(). */
- set_cpus_allowed(current, CPU_MASK_ALL);
+ set_cpus_allowed_ptr(current, CPU_MASK_ALL_PTR);
/*
* Our parent is keventd, which runs with elevated scheduling priority.
#include <linux/file.h>
#include <linux/module.h>
#include <linux/mutex.h>
-#include <asm/semaphore.h>
#define KTHREAD_NICE_LEVEL (-5)
wait_task_inactive(k);
set_task_cpu(k, cpu);
k->cpus_allowed = cpumask_of_cpu(cpu);
+ k->rt.nr_cpus_allowed = 1;
}
EXPORT_SYMBOL(kthread_bind);
return;
for (i = 0; i < MAXLR; i++) {
- int q;
- int same = 1;
+ int q, same = 1;
+
/* Nothing stored: */
if (!latency_record[i].backtrace[0]) {
if (firstnonnull > i)
continue;
}
for (q = 0 ; q < LT_BACKTRACEDEPTH ; q++) {
- if (latency_record[i].backtrace[q] !=
- lat->backtrace[q])
+ unsigned long record = lat->backtrace[q];
+
+ if (latency_record[i].backtrace[q] != record) {
same = 0;
- if (same && lat->backtrace[q] == 0)
break;
- if (same && lat->backtrace[q] == ULONG_MAX)
+ }
+
+ /* 0 and ULONG_MAX entries mean end of backtrace: */
+ if (record == 0 || record == ULONG_MAX)
break;
}
if (same) {
for (i = 0; i < LT_SAVECOUNT ; i++) {
struct latency_record *mylat;
int same = 1;
+
mylat = &tsk->latency_record[i];
for (q = 0 ; q < LT_BACKTRACEDEPTH ; q++) {
- if (mylat->backtrace[q] !=
- lat.backtrace[q])
+ unsigned long record = lat.backtrace[q];
+
+ if (mylat->backtrace[q] != record) {
same = 0;
- if (same && lat.backtrace[q] == 0)
break;
- if (same && lat.backtrace[q] == ULONG_MAX)
+ }
+
+ /* 0 and ULONG_MAX entries mean end of backtrace: */
+ if (record == 0 || record == ULONG_MAX)
break;
}
if (same) {
#include <linux/mutex.h>
#include <linux/unwind.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <asm/cacheflush.h>
#include <linux/license.h>
#include <asm/sections.h>
static void wait_for_zero_refcount(struct module *mod)
{
- /* Since we might sleep for some time, drop the semaphore first */
+ /* Since we might sleep for some time, release the mutex first */
mutex_unlock(&module_mutex);
for (;;) {
DEBUGP("Looking at refcount...\n");
#include <linux/mutex.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
#include <linux/list.h>
#include <linux/init.h>
#include <linux/compiler.h>
#include <linux/highmem.h>
#include <linux/mutex.h>
#include <asm/sections.h>
-#include <asm/semaphore.h>
#include <asm/irq_regs.h>
#include <asm/ptrace.h>
return (data & ~PTRACE_O_MASK) ? -EINVAL : 0;
}
-static int ptrace_getsiginfo(struct task_struct *child, siginfo_t __user * data)
+static int ptrace_getsiginfo(struct task_struct *child, siginfo_t *info)
{
- siginfo_t lastinfo;
int error = -ESRCH;
read_lock(&tasklist_lock);
error = -EINVAL;
spin_lock_irq(&child->sighand->siglock);
if (likely(child->last_siginfo != NULL)) {
- lastinfo = *child->last_siginfo;
+ *info = *child->last_siginfo;
error = 0;
}
spin_unlock_irq(&child->sighand->siglock);
}
read_unlock(&tasklist_lock);
- if (!error)
- return copy_siginfo_to_user(data, &lastinfo);
return error;
}
-static int ptrace_setsiginfo(struct task_struct *child, siginfo_t __user * data)
+static int ptrace_setsiginfo(struct task_struct *child, const siginfo_t *info)
{
- siginfo_t newinfo;
int error = -ESRCH;
- if (copy_from_user(&newinfo, data, sizeof (siginfo_t)))
- return -EFAULT;
-
read_lock(&tasklist_lock);
if (likely(child->sighand != NULL)) {
error = -EINVAL;
spin_lock_irq(&child->sighand->siglock);
if (likely(child->last_siginfo != NULL)) {
- *child->last_siginfo = newinfo;
+ *child->last_siginfo = *info;
error = 0;
}
spin_unlock_irq(&child->sighand->siglock);
long addr, long data)
{
int ret = -EIO;
+ siginfo_t siginfo;
switch (request) {
case PTRACE_PEEKTEXT:
case PTRACE_GETEVENTMSG:
ret = put_user(child->ptrace_message, (unsigned long __user *) data);
break;
+
case PTRACE_GETSIGINFO:
- ret = ptrace_getsiginfo(child, (siginfo_t __user *) data);
+ ret = ptrace_getsiginfo(child, &siginfo);
+ if (!ret)
+ ret = copy_siginfo_to_user((siginfo_t __user *) data,
+ &siginfo);
break;
+
case PTRACE_SETSIGINFO:
- ret = ptrace_setsiginfo(child, (siginfo_t __user *) data);
+ if (copy_from_user(&siginfo, (siginfo_t __user *) data,
+ sizeof siginfo))
+ ret = -EFAULT;
+ else
+ ret = ptrace_setsiginfo(child, &siginfo);
break;
+
case PTRACE_DETACH: /* detach a process that was attached. */
ret = ptrace_detach(child, data);
break;
{
compat_ulong_t __user *datap = compat_ptr(data);
compat_ulong_t word;
+ siginfo_t siginfo;
int ret;
switch (request) {
ret = put_user((compat_ulong_t) child->ptrace_message, datap);
break;
+ case PTRACE_GETSIGINFO:
+ ret = ptrace_getsiginfo(child, &siginfo);
+ if (!ret)
+ ret = copy_siginfo_to_user32(
+ (struct compat_siginfo __user *) datap,
+ &siginfo);
+ break;
+
+ case PTRACE_SETSIGINFO:
+ memset(&siginfo, 0, sizeof siginfo);
+ if (copy_siginfo_from_user32(
+ &siginfo, (struct compat_siginfo __user *) datap))
+ ret = -EFAULT;
+ else
+ ret = ptrace_setsiginfo(child, &siginfo);
+ break;
+
default:
ret = ptrace_request(child, request, addr, data);
}
if (sched_getaffinity(0, &oldmask) < 0)
oldmask = cpu_possible_map;
for_each_online_cpu(cpu) {
- sched_setaffinity(0, cpumask_of_cpu(cpu));
+ sched_setaffinity(0, &cpumask_of_cpu(cpu));
schedule();
}
- sched_setaffinity(0, oldmask);
+ sched_setaffinity(0, &oldmask);
}
EXPORT_SYMBOL_GPL(__synchronize_sched);
*/
static void rcu_torture_shuffle_tasks(void)
{
- cpumask_t tmp_mask = CPU_MASK_ALL;
+ cpumask_t tmp_mask;
int i;
+ cpus_setall(tmp_mask);
get_online_cpus();
/* No point in shuffling if there is only one online CPU (ex: UP) */
if (rcu_idle_cpu != -1)
cpu_clear(rcu_idle_cpu, tmp_mask);
- set_cpus_allowed(current, tmp_mask);
+ set_cpus_allowed_ptr(current, &tmp_mask);
if (reader_tasks) {
for (i = 0; i < nrealreaders; i++)
if (reader_tasks[i])
- set_cpus_allowed(reader_tasks[i], tmp_mask);
+ set_cpus_allowed_ptr(reader_tasks[i],
+ &tmp_mask);
}
if (fakewriter_tasks) {
for (i = 0; i < nfakewriters; i++)
if (fakewriter_tasks[i])
- set_cpus_allowed(fakewriter_tasks[i], tmp_mask);
+ set_cpus_allowed_ptr(fakewriter_tasks[i],
+ &tmp_mask);
}
if (writer_task)
- set_cpus_allowed(writer_task, tmp_mask);
+ set_cpus_allowed_ptr(writer_task, &tmp_mask);
if (stats_task)
- set_cpus_allowed(stats_task, tmp_mask);
+ set_cpus_allowed_ptr(stats_task, &tmp_mask);
if (rcu_idle_cpu == -1)
rcu_idle_cpu = num_online_cpus() - 1;
EXPORT_SYMBOL(adjust_resource);
+/**
+ * resource_alignment - calculate resource's alignment
+ * @res: resource pointer
+ *
+ * Returns alignment on success, 0 (invalid alignment) on failure.
+ */
+resource_size_t resource_alignment(struct resource *res)
+{
+ switch (res->flags & (IORESOURCE_SIZEALIGN | IORESOURCE_STARTALIGN)) {
+ case IORESOURCE_SIZEALIGN:
+ return res->end - res->start + 1;
+ case IORESOURCE_STARTALIGN:
+ return res->start;
+ default:
+ return 0;
+ }
+}
+
/*
* This is compatibility stuff for IO resources.
*
#include <linux/unistd.h>
#include <linux/pagemap.h>
#include <linux/hrtimer.h>
+#include <linux/tick.h>
+#include <linux/bootmem.h>
+#include <linux/debugfs.h>
+#include <linux/ctype.h>
#include <asm/tlb.h>
#include <asm/irq_regs.h>
*/
#define DEF_TIMESLICE (100 * HZ / 1000)
+/*
+ * single value that denotes runtime == period, ie unlimited time.
+ */
+#define RUNTIME_INF ((u64)~0ULL)
+
#ifdef CONFIG_SMP
/*
* Divide a load by a sched group cpu_power : (load / sg->__cpu_power)
struct list_head queue[MAX_RT_PRIO];
};
+struct rt_bandwidth {
+ /* nests inside the rq lock: */
+ spinlock_t rt_runtime_lock;
+ ktime_t rt_period;
+ u64 rt_runtime;
+ struct hrtimer rt_period_timer;
+};
+
+static struct rt_bandwidth def_rt_bandwidth;
+
+static int do_sched_rt_period_timer(struct rt_bandwidth *rt_b, int overrun);
+
+static enum hrtimer_restart sched_rt_period_timer(struct hrtimer *timer)
+{
+ struct rt_bandwidth *rt_b =
+ container_of(timer, struct rt_bandwidth, rt_period_timer);
+ ktime_t now;
+ int overrun;
+ int idle = 0;
+
+ for (;;) {
+ now = hrtimer_cb_get_time(timer);
+ overrun = hrtimer_forward(timer, now, rt_b->rt_period);
+
+ if (!overrun)
+ break;
+
+ idle = do_sched_rt_period_timer(rt_b, overrun);
+ }
+
+ return idle ? HRTIMER_NORESTART : HRTIMER_RESTART;
+}
+
+static
+void init_rt_bandwidth(struct rt_bandwidth *rt_b, u64 period, u64 runtime)
+{
+ rt_b->rt_period = ns_to_ktime(period);
+ rt_b->rt_runtime = runtime;
+
+ spin_lock_init(&rt_b->rt_runtime_lock);
+
+ hrtimer_init(&rt_b->rt_period_timer,
+ CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ rt_b->rt_period_timer.function = sched_rt_period_timer;
+ rt_b->rt_period_timer.cb_mode = HRTIMER_CB_IRQSAFE_NO_SOFTIRQ;
+}
+
+static void start_rt_bandwidth(struct rt_bandwidth *rt_b)
+{
+ ktime_t now;
+
+ if (rt_b->rt_runtime == RUNTIME_INF)
+ return;
+
+ if (hrtimer_active(&rt_b->rt_period_timer))
+ return;
+
+ spin_lock(&rt_b->rt_runtime_lock);
+ for (;;) {
+ if (hrtimer_active(&rt_b->rt_period_timer))
+ break;
+
+ now = hrtimer_cb_get_time(&rt_b->rt_period_timer);
+ hrtimer_forward(&rt_b->rt_period_timer, now, rt_b->rt_period);
+ hrtimer_start(&rt_b->rt_period_timer,
+ rt_b->rt_period_timer.expires,
+ HRTIMER_MODE_ABS);
+ }
+ spin_unlock(&rt_b->rt_runtime_lock);
+}
+
+#ifdef CONFIG_RT_GROUP_SCHED
+static void destroy_rt_bandwidth(struct rt_bandwidth *rt_b)
+{
+ hrtimer_cancel(&rt_b->rt_period_timer);
+}
+#endif
+
#ifdef CONFIG_GROUP_SCHED
#include <linux/cgroup.h>
struct sched_rt_entity **rt_se;
struct rt_rq **rt_rq;
- u64 rt_runtime;
+ struct rt_bandwidth rt_bandwidth;
#endif
struct rcu_head rcu;
struct list_head list;
+
+ struct task_group *parent;
+ struct list_head siblings;
+ struct list_head children;
};
+#ifdef CONFIG_USER_SCHED
+
+/*
+ * Root task group.
+ * Every UID task group (including init_task_group aka UID-0) will
+ * be a child to this group.
+ */
+struct task_group root_task_group;
+
#ifdef CONFIG_FAIR_GROUP_SCHED
/* Default task group's sched entity on each cpu */
static DEFINE_PER_CPU(struct sched_entity, init_sched_entity);
/* Default task group's cfs_rq on each cpu */
static DEFINE_PER_CPU(struct cfs_rq, init_cfs_rq) ____cacheline_aligned_in_smp;
-
-static struct sched_entity *init_sched_entity_p[NR_CPUS];
-static struct cfs_rq *init_cfs_rq_p[NR_CPUS];
#endif
#ifdef CONFIG_RT_GROUP_SCHED
static DEFINE_PER_CPU(struct sched_rt_entity, init_sched_rt_entity);
static DEFINE_PER_CPU(struct rt_rq, init_rt_rq) ____cacheline_aligned_in_smp;
-
-static struct sched_rt_entity *init_sched_rt_entity_p[NR_CPUS];
-static struct rt_rq *init_rt_rq_p[NR_CPUS];
+#endif
+#else
+#define root_task_group init_task_group
#endif
/* task_group_lock serializes add/remove of task groups and also changes to
# define INIT_TASK_GROUP_LOAD NICE_0_LOAD
#endif
+#define MIN_SHARES 2
+
static int init_task_group_load = INIT_TASK_GROUP_LOAD;
#endif
/* Default task group.
* Every task in system belong to this group at bootup.
*/
-struct task_group init_task_group = {
-#ifdef CONFIG_FAIR_GROUP_SCHED
- .se = init_sched_entity_p,
- .cfs_rq = init_cfs_rq_p,
-#endif
-
-#ifdef CONFIG_RT_GROUP_SCHED
- .rt_se = init_sched_rt_entity_p,
- .rt_rq = init_rt_rq_p,
-#endif
-};
+struct task_group init_task_group;
/* return group to which a task belongs */
static inline struct task_group *task_group(struct task_struct *p)
struct rb_root tasks_timeline;
struct rb_node *rb_leftmost;
- struct rb_node *rb_load_balance_curr;
- /* 'curr' points to currently running entity on this cfs_rq.
+
+ struct list_head tasks;
+ struct list_head *balance_iterator;
+
+ /*
+ * 'curr' points to currently running entity on this cfs_rq.
* It is set to NULL otherwise (i.e when none are currently running).
*/
struct sched_entity *curr, *next;
*/
struct list_head leaf_cfs_rq_list;
struct task_group *tg; /* group that "owns" this runqueue */
+
+#ifdef CONFIG_SMP
+ unsigned long task_weight;
+ unsigned long shares;
+ /*
+ * We need space to build a sched_domain wide view of the full task
+ * group tree, in order to avoid depending on dynamic memory allocation
+ * during the load balancing we place this in the per cpu task group
+ * hierarchy. This limits the load balancing to one instance per cpu,
+ * but more should not be needed anyway.
+ */
+ struct aggregate_struct {
+ /*
+ * load = weight(cpus) * f(tg)
+ *
+ * Where f(tg) is the recursive weight fraction assigned to
+ * this group.
+ */
+ unsigned long load;
+
+ /*
+ * part of the group weight distributed to this span.
+ */
+ unsigned long shares;
+
+ /*
+ * The sum of all runqueue weights within this span.
+ */
+ unsigned long rq_weight;
+
+ /*
+ * Weight contributed by tasks; this is the part we can
+ * influence by moving tasks around.
+ */
+ unsigned long task_weight;
+ } aggregate;
+#endif
#endif
};
#endif
int rt_throttled;
u64 rt_time;
+ u64 rt_runtime;
+ /* Nests inside the rq lock: */
+ spinlock_t rt_runtime_lock;
#ifdef CONFIG_RT_GROUP_SCHED
unsigned long rt_nr_boosted;
unsigned long cpu_load[CPU_LOAD_IDX_MAX];
unsigned char idle_at_tick;
#ifdef CONFIG_NO_HZ
+ unsigned long last_tick_seen;
unsigned char in_nohz_recently;
#endif
/* capture load from *all* tasks on this cpu: */
struct cfs_rq cfs;
struct rt_rq rt;
- u64 rt_period_expire;
- int rt_throttled;
#ifdef CONFIG_FAIR_GROUP_SCHED
/* list of leaf cfs_rq on this cpu: */
#endif
}
+#ifdef CONFIG_NO_HZ
+static inline bool nohz_on(int cpu)
+{
+ return tick_get_tick_sched(cpu)->nohz_mode != NOHZ_MODE_INACTIVE;
+}
+
+static inline u64 max_skipped_ticks(struct rq *rq)
+{
+ return nohz_on(cpu_of(rq)) ? jiffies - rq->last_tick_seen + 2 : 1;
+}
+
+static inline void update_last_tick_seen(struct rq *rq)
+{
+ rq->last_tick_seen = jiffies;
+}
+#else
+static inline u64 max_skipped_ticks(struct rq *rq)
+{
+ return 1;
+}
+
+static inline void update_last_tick_seen(struct rq *rq)
+{
+}
+#endif
+
/*
* Update the per-runqueue clock, as finegrained as the platform can give
* us, but without assuming monotonicity, etc.:
/*
* Catch too large forward jumps too:
*/
- if (unlikely(clock + delta > rq->tick_timestamp + TICK_NSEC)) {
- if (clock < rq->tick_timestamp + TICK_NSEC)
- clock = rq->tick_timestamp + TICK_NSEC;
+ u64 max_jump = max_skipped_ticks(rq) * TICK_NSEC;
+ u64 max_time = rq->tick_timestamp + max_jump;
+
+ if (unlikely(clock + delta > max_time)) {
+ if (clock < max_time)
+ clock = max_time;
else
clock++;
rq->clock_overflows++;
#define task_rq(p) cpu_rq(task_cpu(p))
#define cpu_curr(cpu) (cpu_rq(cpu)->curr)
-unsigned long rt_needs_cpu(int cpu)
-{
- struct rq *rq = cpu_rq(cpu);
- u64 delta;
-
- if (!rq->rt_throttled)
- return 0;
-
- if (rq->clock > rq->rt_period_expire)
- return 1;
-
- delta = rq->rt_period_expire - rq->clock;
- do_div(delta, NSEC_PER_SEC / HZ);
-
- return (unsigned long)delta;
-}
-
/*
* Tunables that become constants when CONFIG_SCHED_DEBUG is off:
*/
/*
* Debugging: various feature bits
*/
+
+#define SCHED_FEAT(name, enabled) \
+ __SCHED_FEAT_##name ,
+
enum {
- SCHED_FEAT_NEW_FAIR_SLEEPERS = 1,
- SCHED_FEAT_WAKEUP_PREEMPT = 2,
- SCHED_FEAT_START_DEBIT = 4,
- SCHED_FEAT_HRTICK = 8,
- SCHED_FEAT_DOUBLE_TICK = 16,
+#include "sched_features.h"
};
+#undef SCHED_FEAT
+
+#define SCHED_FEAT(name, enabled) \
+ (1UL << __SCHED_FEAT_##name) * enabled |
+
const_debug unsigned int sysctl_sched_features =
- SCHED_FEAT_NEW_FAIR_SLEEPERS * 1 |
- SCHED_FEAT_WAKEUP_PREEMPT * 1 |
- SCHED_FEAT_START_DEBIT * 1 |
- SCHED_FEAT_HRTICK * 1 |
- SCHED_FEAT_DOUBLE_TICK * 0;
+#include "sched_features.h"
+ 0;
+
+#undef SCHED_FEAT
+
+#ifdef CONFIG_SCHED_DEBUG
+#define SCHED_FEAT(name, enabled) \
+ #name ,
-#define sched_feat(x) (sysctl_sched_features & SCHED_FEAT_##x)
+__read_mostly char *sched_feat_names[] = {
+#include "sched_features.h"
+ NULL
+};
+
+#undef SCHED_FEAT
+
+int sched_feat_open(struct inode *inode, struct file *filp)
+{
+ filp->private_data = inode->i_private;
+ return 0;
+}
+
+static ssize_t
+sched_feat_read(struct file *filp, char __user *ubuf,
+ size_t cnt, loff_t *ppos)
+{
+ char *buf;
+ int r = 0;
+ int len = 0;
+ int i;
+
+ for (i = 0; sched_feat_names[i]; i++) {
+ len += strlen(sched_feat_names[i]);
+ len += 4;
+ }
+
+ buf = kmalloc(len + 2, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ for (i = 0; sched_feat_names[i]; i++) {
+ if (sysctl_sched_features & (1UL << i))
+ r += sprintf(buf + r, "%s ", sched_feat_names[i]);
+ else
+ r += sprintf(buf + r, "NO_%s ", sched_feat_names[i]);
+ }
+
+ r += sprintf(buf + r, "\n");
+ WARN_ON(r >= len + 2);
+
+ r = simple_read_from_buffer(ubuf, cnt, ppos, buf, r);
+
+ kfree(buf);
+
+ return r;
+}
+
+static ssize_t
+sched_feat_write(struct file *filp, const char __user *ubuf,
+ size_t cnt, loff_t *ppos)
+{
+ char buf[64];
+ char *cmp = buf;
+ int neg = 0;
+ int i;
+
+ if (cnt > 63)
+ cnt = 63;
+
+ if (copy_from_user(&buf, ubuf, cnt))
+ return -EFAULT;
+
+ buf[cnt] = 0;
+
+ if (strncmp(buf, "NO_", 3) == 0) {
+ neg = 1;
+ cmp += 3;
+ }
+
+ for (i = 0; sched_feat_names[i]; i++) {
+ int len = strlen(sched_feat_names[i]);
+
+ if (strncmp(cmp, sched_feat_names[i], len) == 0) {
+ if (neg)
+ sysctl_sched_features &= ~(1UL << i);
+ else
+ sysctl_sched_features |= (1UL << i);
+ break;
+ }
+ }
+
+ if (!sched_feat_names[i])
+ return -EINVAL;
+
+ filp->f_pos += cnt;
+
+ return cnt;
+}
+
+static struct file_operations sched_feat_fops = {
+ .open = sched_feat_open,
+ .read = sched_feat_read,
+ .write = sched_feat_write,
+};
+
+static __init int sched_init_debug(void)
+{
+ debugfs_create_file("sched_features", 0644, NULL, NULL,
+ &sched_feat_fops);
+
+ return 0;
+}
+late_initcall(sched_init_debug);
+
+#endif
+
+#define sched_feat(x) (sysctl_sched_features & (1UL << __SCHED_FEAT_##x))
/*
* Number of tasks to iterate in a single balance run.
*/
int sysctl_sched_rt_runtime = 950000;
-/*
- * single value that denotes runtime == period, ie unlimited time.
- */
-#define RUNTIME_INF ((u64)~0ULL)
+static inline u64 global_rt_period(void)
+{
+ return (u64)sysctl_sched_rt_period * NSEC_PER_USEC;
+}
+
+static inline u64 global_rt_runtime(void)
+{
+ if (sysctl_sched_rt_period < 0)
+ return RUNTIME_INF;
+
+ return (u64)sysctl_sched_rt_runtime * NSEC_PER_USEC;
+}
+
+static const unsigned long long time_sync_thresh = 100000;
+
+static DEFINE_PER_CPU(unsigned long long, time_offset);
+static DEFINE_PER_CPU(unsigned long long, prev_cpu_time);
/*
- * For kernel-internal use: high-speed (but slightly incorrect) per-cpu
- * clock constructed from sched_clock():
+ * Global lock which we take every now and then to synchronize
+ * the CPUs time. This method is not warp-safe, but it's good
+ * enough to synchronize slowly diverging time sources and thus
+ * it's good enough for tracing:
*/
-unsigned long long cpu_clock(int cpu)
+static DEFINE_SPINLOCK(time_sync_lock);
+static unsigned long long prev_global_time;
+
+static unsigned long long __sync_cpu_clock(cycles_t time, int cpu)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&time_sync_lock, flags);
+
+ if (time < prev_global_time) {
+ per_cpu(time_offset, cpu) += prev_global_time - time;
+ time = prev_global_time;
+ } else {
+ prev_global_time = time;
+ }
+
+ spin_unlock_irqrestore(&time_sync_lock, flags);
+
+ return time;
+}
+
+static unsigned long long __cpu_clock(int cpu)
{
unsigned long long now;
unsigned long flags;
return now;
}
+
+/*
+ * For kernel-internal use: high-speed (but slightly incorrect) per-cpu
+ * clock constructed from sched_clock():
+ */
+unsigned long long cpu_clock(int cpu)
+{
+ unsigned long long prev_cpu_time, time, delta_time;
+
+ prev_cpu_time = per_cpu(prev_cpu_time, cpu);
+ time = __cpu_clock(cpu) + per_cpu(time_offset, cpu);
+ delta_time = time-prev_cpu_time;
+
+ if (unlikely(delta_time > time_sync_thresh))
+ time = __sync_cpu_clock(time, cpu);
+
+ return time;
+}
EXPORT_SYMBOL_GPL(cpu_clock);
#ifndef prepare_arch_switch
*/
#define SRR(x, y) (((x) + (1UL << ((y) - 1))) >> (y))
+/*
+ * delta *= weight / lw
+ */
static unsigned long
calc_delta_mine(unsigned long delta_exec, unsigned long weight,
struct load_weight *lw)
return (unsigned long)min(tmp, (u64)(unsigned long)LONG_MAX);
}
-static inline unsigned long
-calc_delta_fair(unsigned long delta_exec, struct load_weight *lw)
-{
- return calc_delta_mine(delta_exec, NICE_0_LOAD, lw);
-}
-
static inline void update_load_add(struct load_weight *lw, unsigned long inc)
{
lw->weight += inc;
static inline void cpuacct_charge(struct task_struct *tsk, u64 cputime) {}
#endif
+static inline void inc_cpu_load(struct rq *rq, unsigned long load)
+{
+ update_load_add(&rq->load, load);
+}
+
+static inline void dec_cpu_load(struct rq *rq, unsigned long load)
+{
+ update_load_sub(&rq->load, load);
+}
+
#ifdef CONFIG_SMP
static unsigned long source_load(int cpu, int type);
static unsigned long target_load(int cpu, int type);
static unsigned long cpu_avg_load_per_task(int cpu);
static int task_hot(struct task_struct *p, u64 now, struct sched_domain *sd);
+
+#ifdef CONFIG_FAIR_GROUP_SCHED
+
+/*
+ * Group load balancing.
+ *
+ * We calculate a few balance domain wide aggregate numbers; load and weight.
+ * Given the pictures below, and assuming each item has equal weight:
+ *
+ * root 1 - thread
+ * / | \ A - group
+ * A 1 B
+ * /|\ / \
+ * C 2 D 3 4
+ * | |
+ * 5 6
+ *
+ * load:
+ * A and B get 1/3-rd of the total load. C and D get 1/3-rd of A's 1/3-rd,
+ * which equals 1/9-th of the total load.
+ *
+ * shares:
+ * The weight of this group on the selected cpus.
+ *
+ * rq_weight:
+ * Direct sum of all the cpu's their rq weight, e.g. A would get 3 while
+ * B would get 2.
+ *
+ * task_weight:
+ * Part of the rq_weight contributed by tasks; all groups except B would
+ * get 1, B gets 2.
+ */
+
+static inline struct aggregate_struct *
+aggregate(struct task_group *tg, struct sched_domain *sd)
+{
+ return &tg->cfs_rq[sd->first_cpu]->aggregate;
+}
+
+typedef void (*aggregate_func)(struct task_group *, struct sched_domain *);
+
+/*
+ * Iterate the full tree, calling @down when first entering a node and @up when
+ * leaving it for the final time.
+ */
+static
+void aggregate_walk_tree(aggregate_func down, aggregate_func up,
+ struct sched_domain *sd)
+{
+ struct task_group *parent, *child;
+
+ rcu_read_lock();
+ parent = &root_task_group;
+down:
+ (*down)(parent, sd);
+ list_for_each_entry_rcu(child, &parent->children, siblings) {
+ parent = child;
+ goto down;
+
+up:
+ continue;
+ }
+ (*up)(parent, sd);
+
+ child = parent;
+ parent = parent->parent;
+ if (parent)
+ goto up;
+ rcu_read_unlock();
+}
+
+/*
+ * Calculate the aggregate runqueue weight.
+ */
+static
+void aggregate_group_weight(struct task_group *tg, struct sched_domain *sd)
+{
+ unsigned long rq_weight = 0;
+ unsigned long task_weight = 0;
+ int i;
+
+ for_each_cpu_mask(i, sd->span) {
+ rq_weight += tg->cfs_rq[i]->load.weight;
+ task_weight += tg->cfs_rq[i]->task_weight;
+ }
+
+ aggregate(tg, sd)->rq_weight = rq_weight;
+ aggregate(tg, sd)->task_weight = task_weight;
+}
+
+/*
+ * Redistribute tg->shares amongst all tg->cfs_rq[]s.
+ */
+static void __aggregate_redistribute_shares(struct task_group *tg)
+{
+ int i, max_cpu = smp_processor_id();
+ unsigned long rq_weight = 0;
+ unsigned long shares, max_shares = 0, shares_rem = tg->shares;
+
+ for_each_possible_cpu(i)
+ rq_weight += tg->cfs_rq[i]->load.weight;
+
+ for_each_possible_cpu(i) {
+ /*
+ * divide shares proportional to the rq_weights.
+ */
+ shares = tg->shares * tg->cfs_rq[i]->load.weight;
+ shares /= rq_weight + 1;
+
+ tg->cfs_rq[i]->shares = shares;
+
+ if (shares > max_shares) {
+ max_shares = shares;
+ max_cpu = i;
+ }
+ shares_rem -= shares;
+ }
+
+ /*
+ * Ensure it all adds up to tg->shares; we can loose a few
+ * due to rounding down when computing the per-cpu shares.
+ */
+ if (shares_rem)
+ tg->cfs_rq[max_cpu]->shares += shares_rem;
+}
+
+/*
+ * Compute the weight of this group on the given cpus.
+ */
+static
+void aggregate_group_shares(struct task_group *tg, struct sched_domain *sd)
+{
+ unsigned long shares = 0;
+ int i;
+
+again:
+ for_each_cpu_mask(i, sd->span)
+ shares += tg->cfs_rq[i]->shares;
+
+ /*
+ * When the span doesn't have any shares assigned, but does have
+ * tasks to run do a machine wide rebalance (should be rare).
+ */
+ if (unlikely(!shares && aggregate(tg, sd)->rq_weight)) {
+ __aggregate_redistribute_shares(tg);
+ goto again;
+ }
+
+ aggregate(tg, sd)->shares = shares;
+}
+
+/*
+ * Compute the load fraction assigned to this group, relies on the aggregate
+ * weight and this group's parent's load, i.e. top-down.
+ */
+static
+void aggregate_group_load(struct task_group *tg, struct sched_domain *sd)
+{
+ unsigned long load;
+
+ if (!tg->parent) {
+ int i;
+
+ load = 0;
+ for_each_cpu_mask(i, sd->span)
+ load += cpu_rq(i)->load.weight;
+
+ } else {
+ load = aggregate(tg->parent, sd)->load;
+
+ /*
+ * shares is our weight in the parent's rq so
+ * shares/parent->rq_weight gives our fraction of the load
+ */
+ load *= aggregate(tg, sd)->shares;
+ load /= aggregate(tg->parent, sd)->rq_weight + 1;
+ }
+
+ aggregate(tg, sd)->load = load;
+}
+
+static void __set_se_shares(struct sched_entity *se, unsigned long shares);
+
+/*
+ * Calculate and set the cpu's group shares.
+ */
+static void
+__update_group_shares_cpu(struct task_group *tg, struct sched_domain *sd,
+ int tcpu)
+{
+ int boost = 0;
+ unsigned long shares;
+ unsigned long rq_weight;
+
+ if (!tg->se[tcpu])
+ return;
+
+ rq_weight = tg->cfs_rq[tcpu]->load.weight;
+
+ /*
+ * If there are currently no tasks on the cpu pretend there is one of
+ * average load so that when a new task gets to run here it will not
+ * get delayed by group starvation.
+ */
+ if (!rq_weight) {
+ boost = 1;
+ rq_weight = NICE_0_LOAD;
+ }
+
+ /*
+ * \Sum shares * rq_weight
+ * shares = -----------------------
+ * \Sum rq_weight
+ *
+ */
+ shares = aggregate(tg, sd)->shares * rq_weight;
+ shares /= aggregate(tg, sd)->rq_weight + 1;
+
+ /*
+ * record the actual number of shares, not the boosted amount.
+ */
+ tg->cfs_rq[tcpu]->shares = boost ? 0 : shares;
+
+ if (shares < MIN_SHARES)
+ shares = MIN_SHARES;
+
+ __set_se_shares(tg->se[tcpu], shares);
+}
+
+/*
+ * Re-adjust the weights on the cpu the task came from and on the cpu the
+ * task went to.
+ */
+static void
+__move_group_shares(struct task_group *tg, struct sched_domain *sd,
+ int scpu, int dcpu)
+{
+ unsigned long shares;
+
+ shares = tg->cfs_rq[scpu]->shares + tg->cfs_rq[dcpu]->shares;
+
+ __update_group_shares_cpu(tg, sd, scpu);
+ __update_group_shares_cpu(tg, sd, dcpu);
+
+ /*
+ * ensure we never loose shares due to rounding errors in the
+ * above redistribution.
+ */
+ shares -= tg->cfs_rq[scpu]->shares + tg->cfs_rq[dcpu]->shares;
+ if (shares)
+ tg->cfs_rq[dcpu]->shares += shares;
+}
+
+/*
+ * Because changing a group's shares changes the weight of the super-group
+ * we need to walk up the tree and change all shares until we hit the root.
+ */
+static void
+move_group_shares(struct task_group *tg, struct sched_domain *sd,
+ int scpu, int dcpu)
+{
+ while (tg) {
+ __move_group_shares(tg, sd, scpu, dcpu);
+ tg = tg->parent;
+ }
+}
+
+static
+void aggregate_group_set_shares(struct task_group *tg, struct sched_domain *sd)
+{
+ unsigned long shares = aggregate(tg, sd)->shares;
+ int i;
+
+ for_each_cpu_mask(i, sd->span) {
+ struct rq *rq = cpu_rq(i);
+ unsigned long flags;
+
+ spin_lock_irqsave(&rq->lock, flags);
+ __update_group_shares_cpu(tg, sd, i);
+ spin_unlock_irqrestore(&rq->lock, flags);
+ }
+
+ aggregate_group_shares(tg, sd);
+
+ /*
+ * ensure we never loose shares due to rounding errors in the
+ * above redistribution.
+ */
+ shares -= aggregate(tg, sd)->shares;
+ if (shares) {
+ tg->cfs_rq[sd->first_cpu]->shares += shares;
+ aggregate(tg, sd)->shares += shares;
+ }
+}
+
+/*
+ * Calculate the accumulative weight and recursive load of each task group
+ * while walking down the tree.
+ */
+static
+void aggregate_get_down(struct task_group *tg, struct sched_domain *sd)
+{
+ aggregate_group_weight(tg, sd);
+ aggregate_group_shares(tg, sd);
+ aggregate_group_load(tg, sd);
+}
+
+/*
+ * Rebalance the cpu shares while walking back up the tree.
+ */
+static
+void aggregate_get_up(struct task_group *tg, struct sched_domain *sd)
+{
+ aggregate_group_set_shares(tg, sd);
+}
+
+static DEFINE_PER_CPU(spinlock_t, aggregate_lock);
+
+static void __init init_aggregate(void)
+{
+ int i;
+
+ for_each_possible_cpu(i)
+ spin_lock_init(&per_cpu(aggregate_lock, i));
+}
+
+static int get_aggregate(struct sched_domain *sd)
+{
+ if (!spin_trylock(&per_cpu(aggregate_lock, sd->first_cpu)))
+ return 0;
+
+ aggregate_walk_tree(aggregate_get_down, aggregate_get_up, sd);
+ return 1;
+}
+
+static void put_aggregate(struct sched_domain *sd)
+{
+ spin_unlock(&per_cpu(aggregate_lock, sd->first_cpu));
+}
+
+static void cfs_rq_set_shares(struct cfs_rq *cfs_rq, unsigned long shares)
+{
+ cfs_rq->shares = shares;
+}
+
+#else
+
+static inline void init_aggregate(void)
+{
+}
+
+static inline int get_aggregate(struct sched_domain *sd)
+{
+ return 0;
+}
+
+static inline void put_aggregate(struct sched_domain *sd)
+{
+}
+#endif
+
+#else /* CONFIG_SMP */
+
+#ifdef CONFIG_FAIR_GROUP_SCHED
+static void cfs_rq_set_shares(struct cfs_rq *cfs_rq, unsigned long shares)
+{
+}
+#endif
+
#endif /* CONFIG_SMP */
#include "sched_stats.h"
#define sched_class_highest (&rt_sched_class)
-static inline void inc_load(struct rq *rq, const struct task_struct *p)
-{
- update_load_add(&rq->load, p->se.load.weight);
-}
-
-static inline void dec_load(struct rq *rq, const struct task_struct *p)
-{
- update_load_sub(&rq->load, p->se.load.weight);
-}
-
-static void inc_nr_running(struct task_struct *p, struct rq *rq)
+static void inc_nr_running(struct rq *rq)
{
rq->nr_running++;
- inc_load(rq, p);
}
-static void dec_nr_running(struct task_struct *p, struct rq *rq)
+static void dec_nr_running(struct rq *rq)
{
rq->nr_running--;
- dec_load(rq, p);
}
static void set_load_weight(struct task_struct *p)
rq->nr_uninterruptible--;
enqueue_task(rq, p, wakeup);
- inc_nr_running(p, rq);
+ inc_nr_running(rq);
}
/*
rq->nr_uninterruptible++;
dequeue_task(rq, p, sleep);
- dec_nr_running(p, rq);
+ dec_nr_running(rq);
}
/**
/*
* Buddy candidates are cache hot:
*/
- if (&p->se == cfs_rq_of(&p->se)->next)
+ if (sched_feat(CACHE_HOT_BUDDY) && (&p->se == cfs_rq_of(&p->se)->next))
return 1;
if (p->sched_class != &fair_sched_class)
* find_idlest_cpu - find the idlest cpu among the cpus in group.
*/
static int
-find_idlest_cpu(struct sched_group *group, struct task_struct *p, int this_cpu)
+find_idlest_cpu(struct sched_group *group, struct task_struct *p, int this_cpu,
+ cpumask_t *tmp)
{
- cpumask_t tmp;
unsigned long load, min_load = ULONG_MAX;
int idlest = -1;
int i;
/* Traverse only the allowed CPUs */
- cpus_and(tmp, group->cpumask, p->cpus_allowed);
+ cpus_and(*tmp, group->cpumask, p->cpus_allowed);
- for_each_cpu_mask(i, tmp) {
+ for_each_cpu_mask(i, *tmp) {
load = weighted_cpuload(i);
if (load < min_load || (load == min_load && i == this_cpu)) {
}
while (sd) {
- cpumask_t span;
+ cpumask_t span, tmpmask;
struct sched_group *group;
int new_cpu, weight;
continue;
}
- new_cpu = find_idlest_cpu(group, t, cpu);
+ new_cpu = find_idlest_cpu(group, t, cpu, &tmpmask);
if (new_cpu == -1 || new_cpu == cpu) {
/* Now try balancing at a lower domain level of cpu */
sd = sd->child;
long old_state;
struct rq *rq;
+ if (!sched_feat(SYNC_WAKEUPS))
+ sync = 0;
+
smp_wmb();
rq = task_rq_lock(p, &flags);
old_state = p->state;
INIT_LIST_HEAD(&p->rt.run_list);
p->se.on_rq = 0;
+ INIT_LIST_HEAD(&p->se.group_node);
#ifdef CONFIG_PREEMPT_NOTIFIERS
INIT_HLIST_HEAD(&p->preempt_notifiers);
* management (if any):
*/
p->sched_class->task_new(rq, p);
- inc_nr_running(p, rq);
+ inc_nr_running(rq);
}
check_preempt_curr(rq, p);
#ifdef CONFIG_SMP
static struct sched_group *
find_busiest_group(struct sched_domain *sd, int this_cpu,
unsigned long *imbalance, enum cpu_idle_type idle,
- int *sd_idle, cpumask_t *cpus, int *balance)
+ int *sd_idle, const cpumask_t *cpus, int *balance)
{
struct sched_group *busiest = NULL, *this = NULL, *group = sd->groups;
unsigned long max_load, avg_load, total_load, this_load, total_pwr;
*/
static struct rq *
find_busiest_queue(struct sched_group *group, enum cpu_idle_type idle,
- unsigned long imbalance, cpumask_t *cpus)
+ unsigned long imbalance, const cpumask_t *cpus)
{
struct rq *busiest = NULL, *rq;
unsigned long max_load = 0;
*/
static int load_balance(int this_cpu, struct rq *this_rq,
struct sched_domain *sd, enum cpu_idle_type idle,
- int *balance)
+ int *balance, cpumask_t *cpus)
{
int ld_moved, all_pinned = 0, active_balance = 0, sd_idle = 0;
struct sched_group *group;
unsigned long imbalance;
struct rq *busiest;
- cpumask_t cpus = CPU_MASK_ALL;
unsigned long flags;
+ int unlock_aggregate;
+
+ cpus_setall(*cpus);
+
+ unlock_aggregate = get_aggregate(sd);
/*
* When power savings policy is enabled for the parent domain, idle
redo:
group = find_busiest_group(sd, this_cpu, &imbalance, idle, &sd_idle,
- &cpus, balance);
+ cpus, balance);
if (*balance == 0)
goto out_balanced;
goto out_balanced;
}
- busiest = find_busiest_queue(group, idle, imbalance, &cpus);
+ busiest = find_busiest_queue(group, idle, imbalance, cpus);
if (!busiest) {
schedstat_inc(sd, lb_nobusyq[idle]);
goto out_balanced;
/* All tasks on this runqueue were pinned by CPU affinity */
if (unlikely(all_pinned)) {
- cpu_clear(cpu_of(busiest), cpus);
- if (!cpus_empty(cpus))
+ cpu_clear(cpu_of(busiest), *cpus);
+ if (!cpus_empty(*cpus))
goto redo;
goto out_balanced;
}
if (!ld_moved && !sd_idle && sd->flags & SD_SHARE_CPUPOWER &&
!test_sd_parent(sd, SD_POWERSAVINGS_BALANCE))
- return -1;
- return ld_moved;
+ ld_moved = -1;
+
+ goto out;
out_balanced:
schedstat_inc(sd, lb_balanced[idle]);
if (!sd_idle && sd->flags & SD_SHARE_CPUPOWER &&
!test_sd_parent(sd, SD_POWERSAVINGS_BALANCE))
- return -1;
- return 0;
+ ld_moved = -1;
+ else
+ ld_moved = 0;
+out:
+ if (unlock_aggregate)
+ put_aggregate(sd);
+ return ld_moved;
}
/*
* this_rq is locked.
*/
static int
-load_balance_newidle(int this_cpu, struct rq *this_rq, struct sched_domain *sd)
+load_balance_newidle(int this_cpu, struct rq *this_rq, struct sched_domain *sd,
+ cpumask_t *cpus)
{
struct sched_group *group;
struct rq *busiest = NULL;
int ld_moved = 0;
int sd_idle = 0;
int all_pinned = 0;
- cpumask_t cpus = CPU_MASK_ALL;
+
+ cpus_setall(*cpus);
/*
* When power savings policy is enabled for the parent domain, idle
schedstat_inc(sd, lb_count[CPU_NEWLY_IDLE]);
redo:
group = find_busiest_group(sd, this_cpu, &imbalance, CPU_NEWLY_IDLE,
- &sd_idle, &cpus, NULL);
+ &sd_idle, cpus, NULL);
if (!group) {
schedstat_inc(sd, lb_nobusyg[CPU_NEWLY_IDLE]);
goto out_balanced;
}
- busiest = find_busiest_queue(group, CPU_NEWLY_IDLE, imbalance,
- &cpus);
+ busiest = find_busiest_queue(group, CPU_NEWLY_IDLE, imbalance, cpus);
if (!busiest) {
schedstat_inc(sd, lb_nobusyq[CPU_NEWLY_IDLE]);
goto out_balanced;
spin_unlock(&busiest->lock);
if (unlikely(all_pinned)) {
- cpu_clear(cpu_of(busiest), cpus);
- if (!cpus_empty(cpus))
+ cpu_clear(cpu_of(busiest), *cpus);
+ if (!cpus_empty(*cpus))
goto redo;
}
}
struct sched_domain *sd;
int pulled_task = -1;
unsigned long next_balance = jiffies + HZ;
+ cpumask_t tmpmask;
for_each_domain(this_cpu, sd) {
unsigned long interval;
if (sd->flags & SD_BALANCE_NEWIDLE)
/* If we've pulled tasks over stop searching: */
- pulled_task = load_balance_newidle(this_cpu,
- this_rq, sd);
+ pulled_task = load_balance_newidle(this_cpu, this_rq,
+ sd, &tmpmask);
interval = msecs_to_jiffies(sd->balance_interval);
if (time_after(next_balance, sd->last_balance + interval))
/* Earliest time when we have to do rebalance again */
unsigned long next_balance = jiffies + 60*HZ;
int update_next_balance = 0;
+ cpumask_t tmp;
for_each_domain(cpu, sd) {
if (!(sd->flags & SD_LOAD_BALANCE))
}
if (time_after_eq(jiffies, sd->last_balance + interval)) {
- if (load_balance(cpu, rq, sd, idle, &balance)) {
+ if (load_balance(cpu, rq, sd, idle, &balance, &tmp)) {
/*
* We've pulled tasks over so either we're no
* longer idle, or one of our SMT siblings is
*/
int ilb = first_cpu(nohz.cpu_mask);
- if (ilb != NR_CPUS)
+ if (ilb < nr_cpu_ids)
resched_cpu(ilb);
}
}
rq->clock_underflows++;
}
rq->tick_timestamp = rq->clock;
+ update_last_tick_seen(rq);
update_cpu_load(rq);
curr->sched_class->task_tick(rq, curr, 0);
- update_sched_rt_period(rq);
spin_unlock(&rq->lock);
#ifdef CONFIG_SMP
goto out_unlock;
}
on_rq = p->se.on_rq;
- if (on_rq) {
+ if (on_rq)
dequeue_task(rq, p, 0);
- dec_load(rq, p);
- }
p->static_prio = NICE_TO_PRIO(nice);
set_load_weight(p);
if (on_rq) {
enqueue_task(rq, p, 0);
- inc_load(rq, p);
/*
* If the task increased its priority or is running and
* lowered its priority, then reschedule its CPU:
* Do not allow realtime tasks into groups that have no runtime
* assigned.
*/
- if (rt_policy(policy) && task_group(p)->rt_runtime == 0)
+ if (rt_policy(policy) && task_group(p)->rt_bandwidth.rt_runtime == 0)
return -EPERM;
#endif
return retval;
}
-long sched_setaffinity(pid_t pid, cpumask_t new_mask)
+long sched_setaffinity(pid_t pid, const cpumask_t *in_mask)
{
cpumask_t cpus_allowed;
+ cpumask_t new_mask = *in_mask;
struct task_struct *p;
int retval;
if (retval)
goto out_unlock;
- cpus_allowed = cpuset_cpus_allowed(p);
+ cpuset_cpus_allowed(p, &cpus_allowed);
cpus_and(new_mask, new_mask, cpus_allowed);
again:
- retval = set_cpus_allowed(p, new_mask);
+ retval = set_cpus_allowed_ptr(p, &new_mask);
if (!retval) {
- cpus_allowed = cpuset_cpus_allowed(p);
+ cpuset_cpus_allowed(p, &cpus_allowed);
if (!cpus_subset(new_mask, cpus_allowed)) {
/*
* We must have raced with a concurrent cpuset
if (retval)
return retval;
- return sched_setaffinity(pid, new_mask);
+ return sched_setaffinity(pid, &new_mask);
}
/*
sysctl_sched_latency = limit;
sysctl_sched_wakeup_granularity *= factor;
- sysctl_sched_batch_wakeup_granularity *= factor;
}
#ifdef CONFIG_SMP
* task must not exit() & deallocate itself prematurely. The
* call is not atomic; no spinlocks may be held.
*/
-int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask)
+int set_cpus_allowed_ptr(struct task_struct *p, const cpumask_t *new_mask)
{
struct migration_req req;
unsigned long flags;
int ret = 0;
rq = task_rq_lock(p, &flags);
- if (!cpus_intersects(new_mask, cpu_online_map)) {
+ if (!cpus_intersects(*new_mask, cpu_online_map)) {
ret = -EINVAL;
goto out;
}
if (p->sched_class->set_cpus_allowed)
- p->sched_class->set_cpus_allowed(p, &new_mask);
+ p->sched_class->set_cpus_allowed(p, new_mask);
else {
- p->cpus_allowed = new_mask;
- p->rt.nr_cpus_allowed = cpus_weight(new_mask);
+ p->cpus_allowed = *new_mask;
+ p->rt.nr_cpus_allowed = cpus_weight(*new_mask);
}
/* Can the task run on the task's current CPU? If so, we're done */
- if (cpu_isset(task_cpu(p), new_mask))
+ if (cpu_isset(task_cpu(p), *new_mask))
goto out;
- if (migrate_task(p, any_online_cpu(new_mask), &req)) {
+ if (migrate_task(p, any_online_cpu(*new_mask), &req)) {
/* Need help from migration thread: drop lock and wait. */
task_rq_unlock(rq, &flags);
wake_up_process(rq->migration_thread);
return ret;
}
-EXPORT_SYMBOL_GPL(set_cpus_allowed);
+EXPORT_SYMBOL_GPL(set_cpus_allowed_ptr);
/*
* Move (not current) task off this cpu, onto dest cpu. We're doing
dest_cpu = any_online_cpu(mask);
/* On any allowed CPU? */
- if (dest_cpu == NR_CPUS)
+ if (dest_cpu >= nr_cpu_ids)
dest_cpu = any_online_cpu(p->cpus_allowed);
/* No more Mr. Nice Guy. */
- if (dest_cpu == NR_CPUS) {
- cpumask_t cpus_allowed = cpuset_cpus_allowed_locked(p);
+ if (dest_cpu >= nr_cpu_ids) {
+ cpumask_t cpus_allowed;
+
+ cpuset_cpus_allowed_locked(p, &cpus_allowed);
/*
* Try to stay on the same cpuset, where the
* current cpuset may be a subset of all cpus.
*/
static void migrate_nr_uninterruptible(struct rq *rq_src)
{
- struct rq *rq_dest = cpu_rq(any_online_cpu(CPU_MASK_ALL));
+ struct rq *rq_dest = cpu_rq(any_online_cpu(*CPU_MASK_ALL_PTR));
unsigned long flags;
local_irq_save(flags);
#ifdef CONFIG_SMP
-/* Number of possible processor ids */
-int nr_cpu_ids __read_mostly = NR_CPUS;
-EXPORT_SYMBOL(nr_cpu_ids);
-
#ifdef CONFIG_SCHED_DEBUG
-static int sched_domain_debug_one(struct sched_domain *sd, int cpu, int level)
+static int sched_domain_debug_one(struct sched_domain *sd, int cpu, int level,
+ cpumask_t *groupmask)
{
struct sched_group *group = sd->groups;
- cpumask_t groupmask;
- char str[NR_CPUS];
+ char str[256];
- cpumask_scnprintf(str, NR_CPUS, sd->span);
- cpus_clear(groupmask);
+ cpulist_scnprintf(str, sizeof(str), sd->span);
+ cpus_clear(*groupmask);
printk(KERN_DEBUG "%*s domain %d: ", level, "", level);
break;
}
- if (cpus_intersects(groupmask, group->cpumask)) {
+ if (cpus_intersects(*groupmask, group->cpumask)) {
printk(KERN_CONT "\n");
printk(KERN_ERR "ERROR: repeated CPUs\n");
break;
}
- cpus_or(groupmask, groupmask, group->cpumask);
+ cpus_or(*groupmask, *groupmask, group->cpumask);
- cpumask_scnprintf(str, NR_CPUS, group->cpumask);
+ cpulist_scnprintf(str, sizeof(str), group->cpumask);
printk(KERN_CONT " %s", str);
group = group->next;
} while (group != sd->groups);
printk(KERN_CONT "\n");
- if (!cpus_equal(sd->span, groupmask))
+ if (!cpus_equal(sd->span, *groupmask))
printk(KERN_ERR "ERROR: groups don't span domain->span\n");
- if (sd->parent && !cpus_subset(groupmask, sd->parent->span))
+ if (sd->parent && !cpus_subset(*groupmask, sd->parent->span))
printk(KERN_ERR "ERROR: parent span is not a superset "
"of domain->span\n");
return 0;
static void sched_domain_debug(struct sched_domain *sd, int cpu)
{
+ cpumask_t *groupmask;
int level = 0;
if (!sd) {
printk(KERN_DEBUG "CPU%d attaching sched-domain:\n", cpu);
+ groupmask = kmalloc(sizeof(cpumask_t), GFP_KERNEL);
+ if (!groupmask) {
+ printk(KERN_DEBUG "Cannot load-balance (out of memory)\n");
+ return;
+ }
+
for (;;) {
- if (sched_domain_debug_one(sd, cpu, level))
+ if (sched_domain_debug_one(sd, cpu, level, groupmask))
break;
level++;
sd = sd->parent;
if (!sd)
break;
}
+ kfree(groupmask);
}
#else
# define sched_domain_debug(sd, cpu) do { } while (0)
* and ->cpu_power to 0.
*/
static void
-init_sched_build_groups(cpumask_t span, const cpumask_t *cpu_map,
+init_sched_build_groups(const cpumask_t *span, const cpumask_t *cpu_map,
int (*group_fn)(int cpu, const cpumask_t *cpu_map,
- struct sched_group **sg))
+ struct sched_group **sg,
+ cpumask_t *tmpmask),
+ cpumask_t *covered, cpumask_t *tmpmask)
{
struct sched_group *first = NULL, *last = NULL;
- cpumask_t covered = CPU_MASK_NONE;
int i;
- for_each_cpu_mask(i, span) {
+ cpus_clear(*covered);
+
+ for_each_cpu_mask(i, *span) {
struct sched_group *sg;
- int group = group_fn(i, cpu_map, &sg);
+ int group = group_fn(i, cpu_map, &sg, tmpmask);
int j;
- if (cpu_isset(i, covered))
+ if (cpu_isset(i, *covered))
continue;
- sg->cpumask = CPU_MASK_NONE;
+ cpus_clear(sg->cpumask);
sg->__cpu_power = 0;
- for_each_cpu_mask(j, span) {
- if (group_fn(j, cpu_map, NULL) != group)
+ for_each_cpu_mask(j, *span) {
+ if (group_fn(j, cpu_map, NULL, tmpmask) != group)
continue;
- cpu_set(j, covered);
+ cpu_set(j, *covered);
cpu_set(j, sg->cpumask);
}
if (!first)
*
* Should use nodemask_t.
*/
-static int find_next_best_node(int node, unsigned long *used_nodes)
+static int find_next_best_node(int node, nodemask_t *used_nodes)
{
int i, n, val, min_val, best_node = 0;
continue;
/* Skip already used nodes */
- if (test_bit(n, used_nodes))
+ if (node_isset(n, *used_nodes))
continue;
/* Simple min distance search */
}
}
- set_bit(best_node, used_nodes);
+ node_set(best_node, *used_nodes);
return best_node;
}
/**
* sched_domain_node_span - get a cpumask for a node's sched_domain
* @node: node whose cpumask we're constructing
- * @size: number of nodes to include in this span
+ * @span: resulting cpumask
*
* Given a node, construct a good cpumask for its sched_domain to span. It
* should be one that prevents unnecessary balancing, but also spreads tasks
* out optimally.
*/
-static cpumask_t sched_domain_node_span(int node)
+static void sched_domain_node_span(int node, cpumask_t *span)
{
- DECLARE_BITMAP(used_nodes, MAX_NUMNODES);
- cpumask_t span, nodemask;
+ nodemask_t used_nodes;
+ node_to_cpumask_ptr(nodemask, node);
int i;
- cpus_clear(span);
- bitmap_zero(used_nodes, MAX_NUMNODES);
+ cpus_clear(*span);
+ nodes_clear(used_nodes);
- nodemask = node_to_cpumask(node);
- cpus_or(span, span, nodemask);
- set_bit(node, used_nodes);
+ cpus_or(*span, *span, *nodemask);
+ node_set(node, used_nodes);
for (i = 1; i < SD_NODES_PER_DOMAIN; i++) {
- int next_node = find_next_best_node(node, used_nodes);
+ int next_node = find_next_best_node(node, &used_nodes);
- nodemask = node_to_cpumask(next_node);
- cpus_or(span, span, nodemask);
+ node_to_cpumask_ptr_next(nodemask, next_node);
+ cpus_or(*span, *span, *nodemask);
}
-
- return span;
}
#endif
static DEFINE_PER_CPU(struct sched_group, sched_group_cpus);
static int
-cpu_to_cpu_group(int cpu, const cpumask_t *cpu_map, struct sched_group **sg)
+cpu_to_cpu_group(int cpu, const cpumask_t *cpu_map, struct sched_group **sg,
+ cpumask_t *unused)
{
if (sg)
*sg = &per_cpu(sched_group_cpus, cpu);
#if defined(CONFIG_SCHED_MC) && defined(CONFIG_SCHED_SMT)
static int
-cpu_to_core_group(int cpu, const cpumask_t *cpu_map, struct sched_group **sg)
+cpu_to_core_group(int cpu, const cpumask_t *cpu_map, struct sched_group **sg,
+ cpumask_t *mask)
{
int group;
- cpumask_t mask = per_cpu(cpu_sibling_map, cpu);
- cpus_and(mask, mask, *cpu_map);
- group = first_cpu(mask);
+
+ *mask = per_cpu(cpu_sibling_map, cpu);
+ cpus_and(*mask, *mask, *cpu_map);
+ group = first_cpu(*mask);
if (sg)
*sg = &per_cpu(sched_group_core, group);
return group;
}
#elif defined(CONFIG_SCHED_MC)
static int
-cpu_to_core_group(int cpu, const cpumask_t *cpu_map, struct sched_group **sg)
+cpu_to_core_group(int cpu, const cpumask_t *cpu_map, struct sched_group **sg,
+ cpumask_t *unused)
{
if (sg)
*sg = &per_cpu(sched_group_core, cpu);
static DEFINE_PER_CPU(struct sched_group, sched_group_phys);
static int
-cpu_to_phys_group(int cpu, const cpumask_t *cpu_map, struct sched_group **sg)
+cpu_to_phys_group(int cpu, const cpumask_t *cpu_map, struct sched_group **sg,
+ cpumask_t *mask)
{
int group;
#ifdef CONFIG_SCHED_MC
- cpumask_t mask = cpu_coregroup_map(cpu);
- cpus_and(mask, mask, *cpu_map);
- group = first_cpu(mask);
+ *mask = cpu_coregroup_map(cpu);
+ cpus_and(*mask, *mask, *cpu_map);
+ group = first_cpu(*mask);
#elif defined(CONFIG_SCHED_SMT)
- cpumask_t mask = per_cpu(cpu_sibling_map, cpu);
- cpus_and(mask, mask, *cpu_map);
- group = first_cpu(mask);
+ *mask = per_cpu(cpu_sibling_map, cpu);
+ cpus_and(*mask, *mask, *cpu_map);
+ group = first_cpu(*mask);
#else
group = cpu;
#endif
* gets dynamically allocated.
*/
static DEFINE_PER_CPU(struct sched_domain, node_domains);
-static struct sched_group **sched_group_nodes_bycpu[NR_CPUS];
+static struct sched_group ***sched_group_nodes_bycpu;
static DEFINE_PER_CPU(struct sched_domain, allnodes_domains);
static DEFINE_PER_CPU(struct sched_group, sched_group_allnodes);
static int cpu_to_allnodes_group(int cpu, const cpumask_t *cpu_map,
- struct sched_group **sg)
+ struct sched_group **sg, cpumask_t *nodemask)
{
- cpumask_t nodemask = node_to_cpumask(cpu_to_node(cpu));
int group;
- cpus_and(nodemask, nodemask, *cpu_map);
- group = first_cpu(nodemask);
+ *nodemask = node_to_cpumask(cpu_to_node(cpu));
+ cpus_and(*nodemask, *nodemask, *cpu_map);
+ group = first_cpu(*nodemask);
if (sg)
*sg = &per_cpu(sched_group_allnodes, group);
#ifdef CONFIG_NUMA
/* Free memory allocated for various sched_group structures */
-static void free_sched_groups(const cpumask_t *cpu_map)
+static void free_sched_groups(const cpumask_t *cpu_map, cpumask_t *nodemask)
{
int cpu, i;
continue;
for (i = 0; i < MAX_NUMNODES; i++) {
- cpumask_t nodemask = node_to_cpumask(i);
struct sched_group *oldsg, *sg = sched_group_nodes[i];
- cpus_and(nodemask, nodemask, *cpu_map);
- if (cpus_empty(nodemask))
+ *nodemask = node_to_cpumask(i);
+ cpus_and(*nodemask, *nodemask, *cpu_map);
+ if (cpus_empty(*nodemask))
continue;
if (sg == NULL)
}
}
#else
-static void free_sched_groups(const cpumask_t *cpu_map)
+static void free_sched_groups(const cpumask_t *cpu_map, cpumask_t *nodemask)
{
}
#endif
return;
}
- /*
- * add cpu_power of each child group to this groups cpu_power
- */
- group = child->groups;
- do {
- sg_inc_cpu_power(sd->groups, group->__cpu_power);
- group = group->next;
- } while (group != child->groups);
+ /*
+ * add cpu_power of each child group to this groups cpu_power
+ */
+ group = child->groups;
+ do {
+ sg_inc_cpu_power(sd->groups, group->__cpu_power);
+ group = group->next;
+ } while (group != child->groups);
+}
+
+/*
+ * Initializers for schedule domains
+ * Non-inlined to reduce accumulated stack pressure in build_sched_domains()
+ */
+
+#define SD_INIT(sd, type) sd_init_##type(sd)
+#define SD_INIT_FUNC(type) \
+static noinline void sd_init_##type(struct sched_domain *sd) \
+{ \
+ memset(sd, 0, sizeof(*sd)); \
+ *sd = SD_##type##_INIT; \
+ sd->level = SD_LV_##type; \
+}
+
+SD_INIT_FUNC(CPU)
+#ifdef CONFIG_NUMA
+ SD_INIT_FUNC(ALLNODES)
+ SD_INIT_FUNC(NODE)
+#endif
+#ifdef CONFIG_SCHED_SMT
+ SD_INIT_FUNC(SIBLING)
+#endif
+#ifdef CONFIG_SCHED_MC
+ SD_INIT_FUNC(MC)
+#endif
+
+/*
+ * To minimize stack usage kmalloc room for cpumasks and share the
+ * space as the usage in build_sched_domains() dictates. Used only
+ * if the amount of space is significant.
+ */
+struct allmasks {
+ cpumask_t tmpmask; /* make this one first */
+ union {
+ cpumask_t nodemask;
+ cpumask_t this_sibling_map;
+ cpumask_t this_core_map;
+ };
+ cpumask_t send_covered;
+
+#ifdef CONFIG_NUMA
+ cpumask_t domainspan;
+ cpumask_t covered;
+ cpumask_t notcovered;
+#endif
+};
+
+#if NR_CPUS > 128
+#define SCHED_CPUMASK_ALLOC 1
+#define SCHED_CPUMASK_FREE(v) kfree(v)
+#define SCHED_CPUMASK_DECLARE(v) struct allmasks *v
+#else
+#define SCHED_CPUMASK_ALLOC 0
+#define SCHED_CPUMASK_FREE(v)
+#define SCHED_CPUMASK_DECLARE(v) struct allmasks _v, *v = &_v
+#endif
+
+#define SCHED_CPUMASK_VAR(v, a) cpumask_t *v = (cpumask_t *) \
+ ((unsigned long)(a) + offsetof(struct allmasks, v))
+
+static int default_relax_domain_level = -1;
+
+static int __init setup_relax_domain_level(char *str)
+{
+ default_relax_domain_level = simple_strtoul(str, NULL, 0);
+ return 1;
+}
+__setup("relax_domain_level=", setup_relax_domain_level);
+
+static void set_domain_attribute(struct sched_domain *sd,
+ struct sched_domain_attr *attr)
+{
+ int request;
+
+ if (!attr || attr->relax_domain_level < 0) {
+ if (default_relax_domain_level < 0)
+ return;
+ else
+ request = default_relax_domain_level;
+ } else
+ request = attr->relax_domain_level;
+ if (request < sd->level) {
+ /* turn off idle balance on this domain */
+ sd->flags &= ~(SD_WAKE_IDLE|SD_BALANCE_NEWIDLE);
+ } else {
+ /* turn on idle balance on this domain */
+ sd->flags |= (SD_WAKE_IDLE_FAR|SD_BALANCE_NEWIDLE);
+ }
}
/*
* Build sched domains for a given set of cpus and attach the sched domains
* to the individual cpus
*/
-static int build_sched_domains(const cpumask_t *cpu_map)
+static int __build_sched_domains(const cpumask_t *cpu_map,
+ struct sched_domain_attr *attr)
{
int i;
struct root_domain *rd;
+ SCHED_CPUMASK_DECLARE(allmasks);
+ cpumask_t *tmpmask;
#ifdef CONFIG_NUMA
struct sched_group **sched_group_nodes = NULL;
int sd_allnodes = 0;
printk(KERN_WARNING "Can not alloc sched group node list\n");
return -ENOMEM;
}
- sched_group_nodes_bycpu[first_cpu(*cpu_map)] = sched_group_nodes;
#endif
rd = alloc_rootdomain();
if (!rd) {
printk(KERN_WARNING "Cannot alloc root domain\n");
+#ifdef CONFIG_NUMA
+ kfree(sched_group_nodes);
+#endif
+ return -ENOMEM;
+ }
+
+#if SCHED_CPUMASK_ALLOC
+ /* get space for all scratch cpumask variables */
+ allmasks = kmalloc(sizeof(*allmasks), GFP_KERNEL);
+ if (!allmasks) {
+ printk(KERN_WARNING "Cannot alloc cpumask array\n");
+ kfree(rd);
+#ifdef CONFIG_NUMA
+ kfree(sched_group_nodes);
+#endif
return -ENOMEM;
}
+#endif
+ tmpmask = (cpumask_t *)allmasks;
+
+
+#ifdef CONFIG_NUMA
+ sched_group_nodes_bycpu[first_cpu(*cpu_map)] = sched_group_nodes;
+#endif
/*
* Set up domains for cpus specified by the cpu_map.
*/
for_each_cpu_mask(i, *cpu_map) {
struct sched_domain *sd = NULL, *p;
- cpumask_t nodemask = node_to_cpumask(cpu_to_node(i));
+ SCHED_CPUMASK_VAR(nodemask, allmasks);
- cpus_and(nodemask, nodemask, *cpu_map);
+ *nodemask = node_to_cpumask(cpu_to_node(i));
+ cpus_and(*nodemask, *nodemask, *cpu_map);
#ifdef CONFIG_NUMA
if (cpus_weight(*cpu_map) >
- SD_NODES_PER_DOMAIN*cpus_weight(nodemask)) {
+ SD_NODES_PER_DOMAIN*cpus_weight(*nodemask)) {
sd = &per_cpu(allnodes_domains, i);
- *sd = SD_ALLNODES_INIT;
+ SD_INIT(sd, ALLNODES);
+ set_domain_attribute(sd, attr);
sd->span = *cpu_map;
- cpu_to_allnodes_group(i, cpu_map, &sd->groups);
+ sd->first_cpu = first_cpu(sd->span);
+ cpu_to_allnodes_group(i, cpu_map, &sd->groups, tmpmask);
p = sd;
sd_allnodes = 1;
} else
p = NULL;
sd = &per_cpu(node_domains, i);
- *sd = SD_NODE_INIT;
- sd->span = sched_domain_node_span(cpu_to_node(i));
+ SD_INIT(sd, NODE);
+ set_domain_attribute(sd, attr);
+ sched_domain_node_span(cpu_to_node(i), &sd->span);
+ sd->first_cpu = first_cpu(sd->span);
sd->parent = p;
if (p)
p->child = sd;
p = sd;
sd = &per_cpu(phys_domains, i);
- *sd = SD_CPU_INIT;
- sd->span = nodemask;
+ SD_INIT(sd, CPU);
+ set_domain_attribute(sd, attr);
+ sd->span = *nodemask;
+ sd->first_cpu = first_cpu(sd->span);
sd->parent = p;
if (p)
p->child = sd;
- cpu_to_phys_group(i, cpu_map, &sd->groups);
+ cpu_to_phys_group(i, cpu_map, &sd->groups, tmpmask);
#ifdef CONFIG_SCHED_MC
p = sd;
sd = &per_cpu(core_domains, i);
- *sd = SD_MC_INIT;
+ SD_INIT(sd, MC);
+ set_domain_attribute(sd, attr);
sd->span = cpu_coregroup_map(i);
+ sd->first_cpu = first_cpu(sd->span);
cpus_and(sd->span, sd->span, *cpu_map);
sd->parent = p;
p->child = sd;
- cpu_to_core_group(i, cpu_map, &sd->groups);
+ cpu_to_core_group(i, cpu_map, &sd->groups, tmpmask);
#endif
#ifdef CONFIG_SCHED_SMT
p = sd;
sd = &per_cpu(cpu_domains, i);
- *sd = SD_SIBLING_INIT;
+ SD_INIT(sd, SIBLING);
+ set_domain_attribute(sd, attr);
sd->span = per_cpu(cpu_sibling_map, i);
+ sd->first_cpu = first_cpu(sd->span);
cpus_and(sd->span, sd->span, *cpu_map);
sd->parent = p;
p->child = sd;
- cpu_to_cpu_group(i, cpu_map, &sd->groups);
+ cpu_to_cpu_group(i, cpu_map, &sd->groups, tmpmask);
#endif
}
#ifdef CONFIG_SCHED_SMT
/* Set up CPU (sibling) groups */
for_each_cpu_mask(i, *cpu_map) {
- cpumask_t this_sibling_map = per_cpu(cpu_sibling_map, i);
- cpus_and(this_sibling_map, this_sibling_map, *cpu_map);
- if (i != first_cpu(this_sibling_map))
+ SCHED_CPUMASK_VAR(this_sibling_map, allmasks);
+ SCHED_CPUMASK_VAR(send_covered, allmasks);
+
+ *this_sibling_map = per_cpu(cpu_sibling_map, i);
+ cpus_and(*this_sibling_map, *this_sibling_map, *cpu_map);
+ if (i != first_cpu(*this_sibling_map))
continue;
init_sched_build_groups(this_sibling_map, cpu_map,
- &cpu_to_cpu_group);
+ &cpu_to_cpu_group,
+ send_covered, tmpmask);
}
#endif
#ifdef CONFIG_SCHED_MC
/* Set up multi-core groups */
for_each_cpu_mask(i, *cpu_map) {
- cpumask_t this_core_map = cpu_coregroup_map(i);
- cpus_and(this_core_map, this_core_map, *cpu_map);
- if (i != first_cpu(this_core_map))
+ SCHED_CPUMASK_VAR(this_core_map, allmasks);
+ SCHED_CPUMASK_VAR(send_covered, allmasks);
+
+ *this_core_map = cpu_coregroup_map(i);
+ cpus_and(*this_core_map, *this_core_map, *cpu_map);
+ if (i != first_cpu(*this_core_map))
continue;
+
init_sched_build_groups(this_core_map, cpu_map,
- &cpu_to_core_group);
+ &cpu_to_core_group,
+ send_covered, tmpmask);
}
#endif
/* Set up physical groups */
for (i = 0; i < MAX_NUMNODES; i++) {
- cpumask_t nodemask = node_to_cpumask(i);
+ SCHED_CPUMASK_VAR(nodemask, allmasks);
+ SCHED_CPUMASK_VAR(send_covered, allmasks);
- cpus_and(nodemask, nodemask, *cpu_map);
- if (cpus_empty(nodemask))
+ *nodemask = node_to_cpumask(i);
+ cpus_and(*nodemask, *nodemask, *cpu_map);
+ if (cpus_empty(*nodemask))
continue;
- init_sched_build_groups(nodemask, cpu_map, &cpu_to_phys_group);
+ init_sched_build_groups(nodemask, cpu_map,
+ &cpu_to_phys_group,
+ send_covered, tmpmask);
}
#ifdef CONFIG_NUMA
/* Set up node groups */
- if (sd_allnodes)
- init_sched_build_groups(*cpu_map, cpu_map,
- &cpu_to_allnodes_group);
+ if (sd_allnodes) {
+ SCHED_CPUMASK_VAR(send_covered, allmasks);
+
+ init_sched_build_groups(cpu_map, cpu_map,
+ &cpu_to_allnodes_group,
+ send_covered, tmpmask);
+ }
for (i = 0; i < MAX_NUMNODES; i++) {
/* Set up node groups */
struct sched_group *sg, *prev;
- cpumask_t nodemask = node_to_cpumask(i);
- cpumask_t domainspan;
- cpumask_t covered = CPU_MASK_NONE;
+ SCHED_CPUMASK_VAR(nodemask, allmasks);
+ SCHED_CPUMASK_VAR(domainspan, allmasks);
+ SCHED_CPUMASK_VAR(covered, allmasks);
int j;
- cpus_and(nodemask, nodemask, *cpu_map);
- if (cpus_empty(nodemask)) {
+ *nodemask = node_to_cpumask(i);
+ cpus_clear(*covered);
+
+ cpus_and(*nodemask, *nodemask, *cpu_map);
+ if (cpus_empty(*nodemask)) {
sched_group_nodes[i] = NULL;
continue;
}
- domainspan = sched_domain_node_span(i);
- cpus_and(domainspan, domainspan, *cpu_map);
+ sched_domain_node_span(i, domainspan);
+ cpus_and(*domainspan, *domainspan, *cpu_map);
sg = kmalloc_node(sizeof(struct sched_group), GFP_KERNEL, i);
if (!sg) {
goto error;
}
sched_group_nodes[i] = sg;
- for_each_cpu_mask(j, nodemask) {
+ for_each_cpu_mask(j, *nodemask) {
struct sched_domain *sd;
sd = &per_cpu(node_domains, j);
sd->groups = sg;
}
sg->__cpu_power = 0;
- sg->cpumask = nodemask;
+ sg->cpumask = *nodemask;
sg->next = sg;
- cpus_or(covered, covered, nodemask);
+ cpus_or(*covered, *covered, *nodemask);
prev = sg;
for (j = 0; j < MAX_NUMNODES; j++) {
- cpumask_t tmp, notcovered;
+ SCHED_CPUMASK_VAR(notcovered, allmasks);
int n = (i + j) % MAX_NUMNODES;
+ node_to_cpumask_ptr(pnodemask, n);
- cpus_complement(notcovered, covered);
- cpus_and(tmp, notcovered, *cpu_map);
- cpus_and(tmp, tmp, domainspan);
- if (cpus_empty(tmp))
+ cpus_complement(*notcovered, *covered);
+ cpus_and(*tmpmask, *notcovered, *cpu_map);
+ cpus_and(*tmpmask, *tmpmask, *domainspan);
+ if (cpus_empty(*tmpmask))
break;
- nodemask = node_to_cpumask(n);
- cpus_and(tmp, tmp, nodemask);
- if (cpus_empty(tmp))
+ cpus_and(*tmpmask, *tmpmask, *pnodemask);
+ if (cpus_empty(*tmpmask))
continue;
sg = kmalloc_node(sizeof(struct sched_group),
goto error;
}
sg->__cpu_power = 0;
- sg->cpumask = tmp;
+ sg->cpumask = *tmpmask;
sg->next = prev->next;
- cpus_or(covered, covered, tmp);
+ cpus_or(*covered, *covered, *tmpmask);
prev->next = sg;
prev = sg;
}
if (sd_allnodes) {
struct sched_group *sg;
- cpu_to_allnodes_group(first_cpu(*cpu_map), cpu_map, &sg);
+ cpu_to_allnodes_group(first_cpu(*cpu_map), cpu_map, &sg,
+ tmpmask);
init_numa_sched_groups_power(sg);
}
#endif
cpu_attach_domain(sd, rd, i);
}
+ SCHED_CPUMASK_FREE((void *)allmasks);
return 0;
#ifdef CONFIG_NUMA
error:
- free_sched_groups(cpu_map);
+ free_sched_groups(cpu_map, tmpmask);
+ SCHED_CPUMASK_FREE((void *)allmasks);
return -ENOMEM;
#endif
}
+static int build_sched_domains(const cpumask_t *cpu_map)
+{
+ return __build_sched_domains(cpu_map, NULL);
+}
+
static cpumask_t *doms_cur; /* current sched domains */
static int ndoms_cur; /* number of sched domains in 'doms_cur' */
+static struct sched_domain_attr *dattr_cur; /* attribues of custom domains
+ in 'doms_cur' */
/*
* Special case: If a kmalloc of a doms_cur partition (array of
if (!doms_cur)
doms_cur = &fallback_doms;
cpus_andnot(*doms_cur, *cpu_map, cpu_isolated_map);
+ dattr_cur = NULL;
err = build_sched_domains(doms_cur);
register_sched_domain_sysctl();
return err;
}
-static void arch_destroy_sched_domains(const cpumask_t *cpu_map)
+static void arch_destroy_sched_domains(const cpumask_t *cpu_map,
+ cpumask_t *tmpmask)
{
- free_sched_groups(cpu_map);
+ free_sched_groups(cpu_map, tmpmask);
}
/*
*/
static void detach_destroy_domains(const cpumask_t *cpu_map)
{
+ cpumask_t tmpmask;
int i;
unregister_sched_domain_sysctl();
for_each_cpu_mask(i, *cpu_map)
cpu_attach_domain(NULL, &def_root_domain, i);
synchronize_sched();
- arch_destroy_sched_domains(cpu_map);
+ arch_destroy_sched_domains(cpu_map, &tmpmask);
+}
+
+/* handle null as "default" */
+static int dattrs_equal(struct sched_domain_attr *cur, int idx_cur,
+ struct sched_domain_attr *new, int idx_new)
+{
+ struct sched_domain_attr tmp;
+
+ /* fast path */
+ if (!new && !cur)
+ return 1;
+
+ tmp = SD_ATTR_INIT;
+ return !memcmp(cur ? (cur + idx_cur) : &tmp,
+ new ? (new + idx_new) : &tmp,
+ sizeof(struct sched_domain_attr));
}
/*
*
* Call with hotplug lock held
*/
-void partition_sched_domains(int ndoms_new, cpumask_t *doms_new)
+void partition_sched_domains(int ndoms_new, cpumask_t *doms_new,
+ struct sched_domain_attr *dattr_new)
{
int i, j;
ndoms_new = 1;
doms_new = &fallback_doms;
cpus_andnot(doms_new[0], cpu_online_map, cpu_isolated_map);
+ dattr_new = NULL;
}
/* Destroy deleted domains */
for (i = 0; i < ndoms_cur; i++) {
for (j = 0; j < ndoms_new; j++) {
- if (cpus_equal(doms_cur[i], doms_new[j]))
+ if (cpus_equal(doms_cur[i], doms_new[j])
+ && dattrs_equal(dattr_cur, i, dattr_new, j))
goto match1;
}
/* no match - a current sched domain not in new doms_new[] */
/* Build new domains */
for (i = 0; i < ndoms_new; i++) {
for (j = 0; j < ndoms_cur; j++) {
- if (cpus_equal(doms_new[i], doms_cur[j]))
+ if (cpus_equal(doms_new[i], doms_cur[j])
+ && dattrs_equal(dattr_new, i, dattr_cur, j))
goto match2;
}
/* no match - add a new doms_new */
- build_sched_domains(doms_new + i);
+ __build_sched_domains(doms_new + i,
+ dattr_new ? dattr_new + i : NULL);
match2:
;
}
/* Remember the new sched domains */
if (doms_cur != &fallback_doms)
kfree(doms_cur);
+ kfree(dattr_cur); /* kfree(NULL) is safe */
doms_cur = doms_new;
+ dattr_cur = dattr_new;
ndoms_cur = ndoms_new;
register_sched_domain_sysctl();
{
cpumask_t non_isolated_cpus;
+#if defined(CONFIG_NUMA)
+ sched_group_nodes_bycpu = kzalloc(nr_cpu_ids * sizeof(void **),
+ GFP_KERNEL);
+ BUG_ON(sched_group_nodes_bycpu == NULL);
+#endif
get_online_cpus();
arch_init_sched_domains(&cpu_online_map);
cpus_andnot(non_isolated_cpus, cpu_possible_map, cpu_isolated_map);
hotcpu_notifier(update_sched_domains, 0);
/* Move init over to a non-isolated CPU */
- if (set_cpus_allowed(current, non_isolated_cpus) < 0)
+ if (set_cpus_allowed_ptr(current, &non_isolated_cpus) < 0)
BUG();
sched_init_granularity();
}
#else
void __init sched_init_smp(void)
{
+#if defined(CONFIG_NUMA)
+ sched_group_nodes_bycpu = kzalloc(nr_cpu_ids * sizeof(void **),
+ GFP_KERNEL);
+ BUG_ON(sched_group_nodes_bycpu == NULL);
+#endif
sched_init_granularity();
}
#endif /* CONFIG_SMP */
static void init_cfs_rq(struct cfs_rq *cfs_rq, struct rq *rq)
{
cfs_rq->tasks_timeline = RB_ROOT;
+ INIT_LIST_HEAD(&cfs_rq->tasks);
#ifdef CONFIG_FAIR_GROUP_SCHED
cfs_rq->rq = rq;
#endif
rt_rq->rt_time = 0;
rt_rq->rt_throttled = 0;
+ rt_rq->rt_runtime = 0;
+ spin_lock_init(&rt_rq->rt_runtime_lock);
#ifdef CONFIG_RT_GROUP_SCHED
rt_rq->rt_nr_boosted = 0;
}
#ifdef CONFIG_FAIR_GROUP_SCHED
-static void init_tg_cfs_entry(struct rq *rq, struct task_group *tg,
- struct cfs_rq *cfs_rq, struct sched_entity *se,
- int cpu, int add)
+static void init_tg_cfs_entry(struct task_group *tg, struct cfs_rq *cfs_rq,
+ struct sched_entity *se, int cpu, int add,
+ struct sched_entity *parent)
{
+ struct rq *rq = cpu_rq(cpu);
tg->cfs_rq[cpu] = cfs_rq;
init_cfs_rq(cfs_rq, rq);
cfs_rq->tg = tg;
list_add(&cfs_rq->leaf_cfs_rq_list, &rq->leaf_cfs_rq_list);
tg->se[cpu] = se;
- se->cfs_rq = &rq->cfs;
+ /* se could be NULL for init_task_group */
+ if (!se)
+ return;
+
+ if (!parent)
+ se->cfs_rq = &rq->cfs;
+ else
+ se->cfs_rq = parent->my_q;
+
se->my_q = cfs_rq;
se->load.weight = tg->shares;
se->load.inv_weight = div64_64(1ULL<<32, se->load.weight);
- se->parent = NULL;
+ se->parent = parent;
}
#endif
#ifdef CONFIG_RT_GROUP_SCHED
-static void init_tg_rt_entry(struct rq *rq, struct task_group *tg,
- struct rt_rq *rt_rq, struct sched_rt_entity *rt_se,
- int cpu, int add)
+static void init_tg_rt_entry(struct task_group *tg, struct rt_rq *rt_rq,
+ struct sched_rt_entity *rt_se, int cpu, int add,
+ struct sched_rt_entity *parent)
{
+ struct rq *rq = cpu_rq(cpu);
+
tg->rt_rq[cpu] = rt_rq;
init_rt_rq(rt_rq, rq);
rt_rq->tg = tg;
rt_rq->rt_se = rt_se;
+ rt_rq->rt_runtime = tg->rt_bandwidth.rt_runtime;
if (add)
list_add(&rt_rq->leaf_rt_rq_list, &rq->leaf_rt_rq_list);
tg->rt_se[cpu] = rt_se;
+ if (!rt_se)
+ return;
+
+ if (!parent)
+ rt_se->rt_rq = &rq->rt;
+ else
+ rt_se->rt_rq = parent->my_q;
+
rt_se->rt_rq = &rq->rt;
rt_se->my_q = rt_rq;
- rt_se->parent = NULL;
+ rt_se->parent = parent;
INIT_LIST_HEAD(&rt_se->run_list);
}
#endif
void __init sched_init(void)
{
- int highest_cpu = 0;
int i, j;
+ unsigned long alloc_size = 0, ptr;
+
+#ifdef CONFIG_FAIR_GROUP_SCHED
+ alloc_size += 2 * nr_cpu_ids * sizeof(void **);
+#endif
+#ifdef CONFIG_RT_GROUP_SCHED
+ alloc_size += 2 * nr_cpu_ids * sizeof(void **);
+#endif
+#ifdef CONFIG_USER_SCHED
+ alloc_size *= 2;
+#endif
+ /*
+ * As sched_init() is called before page_alloc is setup,
+ * we use alloc_bootmem().
+ */
+ if (alloc_size) {
+ ptr = (unsigned long)alloc_bootmem_low(alloc_size);
+
+#ifdef CONFIG_FAIR_GROUP_SCHED
+ init_task_group.se = (struct sched_entity **)ptr;
+ ptr += nr_cpu_ids * sizeof(void **);
+
+ init_task_group.cfs_rq = (struct cfs_rq **)ptr;
+ ptr += nr_cpu_ids * sizeof(void **);
+
+#ifdef CONFIG_USER_SCHED
+ root_task_group.se = (struct sched_entity **)ptr;
+ ptr += nr_cpu_ids * sizeof(void **);
+
+ root_task_group.cfs_rq = (struct cfs_rq **)ptr;
+ ptr += nr_cpu_ids * sizeof(void **);
+#endif
+#endif
+#ifdef CONFIG_RT_GROUP_SCHED
+ init_task_group.rt_se = (struct sched_rt_entity **)ptr;
+ ptr += nr_cpu_ids * sizeof(void **);
+
+ init_task_group.rt_rq = (struct rt_rq **)ptr;
+ ptr += nr_cpu_ids * sizeof(void **);
+
+#ifdef CONFIG_USER_SCHED
+ root_task_group.rt_se = (struct sched_rt_entity **)ptr;
+ ptr += nr_cpu_ids * sizeof(void **);
+
+ root_task_group.rt_rq = (struct rt_rq **)ptr;
+ ptr += nr_cpu_ids * sizeof(void **);
+#endif
+#endif
+ }
#ifdef CONFIG_SMP
+ init_aggregate();
init_defrootdomain();
#endif
+ init_rt_bandwidth(&def_rt_bandwidth,
+ global_rt_period(), global_rt_runtime());
+
+#ifdef CONFIG_RT_GROUP_SCHED
+ init_rt_bandwidth(&init_task_group.rt_bandwidth,
+ global_rt_period(), global_rt_runtime());
+#ifdef CONFIG_USER_SCHED
+ init_rt_bandwidth(&root_task_group.rt_bandwidth,
+ global_rt_period(), RUNTIME_INF);
+#endif
+#endif
+
#ifdef CONFIG_GROUP_SCHED
list_add(&init_task_group.list, &task_groups);
+ INIT_LIST_HEAD(&init_task_group.children);
+
+#ifdef CONFIG_USER_SCHED
+ INIT_LIST_HEAD(&root_task_group.children);
+ init_task_group.parent = &root_task_group;
+ list_add(&init_task_group.siblings, &root_task_group.children);
+#endif
#endif
for_each_possible_cpu(i) {
lockdep_set_class(&rq->lock, &rq->rq_lock_key);
rq->nr_running = 0;
rq->clock = 1;
+ update_last_tick_seen(rq);
init_cfs_rq(&rq->cfs, rq);
init_rt_rq(&rq->rt, rq);
#ifdef CONFIG_FAIR_GROUP_SCHED
init_task_group.shares = init_task_group_load;
INIT_LIST_HEAD(&rq->leaf_cfs_rq_list);
- init_tg_cfs_entry(rq, &init_task_group,
+#ifdef CONFIG_CGROUP_SCHED
+ /*
+ * How much cpu bandwidth does init_task_group get?
+ *
+ * In case of task-groups formed thr' the cgroup filesystem, it
+ * gets 100% of the cpu resources in the system. This overall
+ * system cpu resource is divided among the tasks of
+ * init_task_group and its child task-groups in a fair manner,
+ * based on each entity's (task or task-group's) weight
+ * (se->load.weight).
+ *
+ * In other words, if init_task_group has 10 tasks of weight
+ * 1024) and two child groups A0 and A1 (of weight 1024 each),
+ * then A0's share of the cpu resource is:
+ *
+ * A0's bandwidth = 1024 / (10*1024 + 1024 + 1024) = 8.33%
+ *
+ * We achieve this by letting init_task_group's tasks sit
+ * directly in rq->cfs (i.e init_task_group->se[] = NULL).
+ */
+ init_tg_cfs_entry(&init_task_group, &rq->cfs, NULL, i, 1, NULL);
+#elif defined CONFIG_USER_SCHED
+ root_task_group.shares = NICE_0_LOAD;
+ init_tg_cfs_entry(&root_task_group, &rq->cfs, NULL, i, 0, NULL);
+ /*
+ * In case of task-groups formed thr' the user id of tasks,
+ * init_task_group represents tasks belonging to root user.
+ * Hence it forms a sibling of all subsequent groups formed.
+ * In this case, init_task_group gets only a fraction of overall
+ * system cpu resource, based on the weight assigned to root
+ * user's cpu share (INIT_TASK_GROUP_LOAD). This is accomplished
+ * by letting tasks of init_task_group sit in a separate cfs_rq
+ * (init_cfs_rq) and having one entity represent this group of
+ * tasks in rq->cfs (i.e init_task_group->se[] != NULL).
+ */
+ init_tg_cfs_entry(&init_task_group,
&per_cpu(init_cfs_rq, i),
- &per_cpu(init_sched_entity, i), i, 1);
+ &per_cpu(init_sched_entity, i), i, 1,
+ root_task_group.se[i]);
#endif
+#endif /* CONFIG_FAIR_GROUP_SCHED */
+
+ rq->rt.rt_runtime = def_rt_bandwidth.rt_runtime;
#ifdef CONFIG_RT_GROUP_SCHED
- init_task_group.rt_runtime =
- sysctl_sched_rt_runtime * NSEC_PER_USEC;
INIT_LIST_HEAD(&rq->leaf_rt_rq_list);
- init_tg_rt_entry(rq, &init_task_group,
+#ifdef CONFIG_CGROUP_SCHED
+ init_tg_rt_entry(&init_task_group, &rq->rt, NULL, i, 1, NULL);
+#elif defined CONFIG_USER_SCHED
+ init_tg_rt_entry(&root_task_group, &rq->rt, NULL, i, 0, NULL);
+ init_tg_rt_entry(&init_task_group,
&per_cpu(init_rt_rq, i),
- &per_cpu(init_sched_rt_entity, i), i, 1);
+ &per_cpu(init_sched_rt_entity, i), i, 1,
+ root_task_group.rt_se[i]);
+#endif
#endif
- rq->rt_period_expire = 0;
- rq->rt_throttled = 0;
for (j = 0; j < CPU_LOAD_IDX_MAX; j++)
rq->cpu_load[j] = 0;
#endif
init_rq_hrtick(rq);
atomic_set(&rq->nr_iowait, 0);
- highest_cpu = i;
}
set_load_weight(&init_task);
#endif
#ifdef CONFIG_SMP
- nr_cpu_ids = highest_cpu + 1;
open_softirq(SCHED_SOFTIRQ, run_rebalance_domains, NULL);
#endif
#endif
-#ifdef CONFIG_GROUP_SCHED
-
#ifdef CONFIG_FAIR_GROUP_SCHED
static void free_fair_sched_group(struct task_group *tg)
{
kfree(tg->se);
}
-static int alloc_fair_sched_group(struct task_group *tg)
+static
+int alloc_fair_sched_group(struct task_group *tg, struct task_group *parent)
{
struct cfs_rq *cfs_rq;
- struct sched_entity *se;
+ struct sched_entity *se, *parent_se;
struct rq *rq;
int i;
- tg->cfs_rq = kzalloc(sizeof(cfs_rq) * NR_CPUS, GFP_KERNEL);
+ tg->cfs_rq = kzalloc(sizeof(cfs_rq) * nr_cpu_ids, GFP_KERNEL);
if (!tg->cfs_rq)
goto err;
- tg->se = kzalloc(sizeof(se) * NR_CPUS, GFP_KERNEL);
+ tg->se = kzalloc(sizeof(se) * nr_cpu_ids, GFP_KERNEL);
if (!tg->se)
goto err;
if (!se)
goto err;
- init_tg_cfs_entry(rq, tg, cfs_rq, se, i, 0);
+ parent_se = parent ? parent->se[i] : NULL;
+ init_tg_cfs_entry(tg, cfs_rq, se, i, 0, parent_se);
}
return 1;
{
}
-static inline int alloc_fair_sched_group(struct task_group *tg)
+static inline
+int alloc_fair_sched_group(struct task_group *tg, struct task_group *parent)
{
return 1;
}
{
int i;
+ destroy_rt_bandwidth(&tg->rt_bandwidth);
+
for_each_possible_cpu(i) {
if (tg->rt_rq)
kfree(tg->rt_rq[i]);
kfree(tg->rt_se);
}
-static int alloc_rt_sched_group(struct task_group *tg)
+static
+int alloc_rt_sched_group(struct task_group *tg, struct task_group *parent)
{
struct rt_rq *rt_rq;
- struct sched_rt_entity *rt_se;
+ struct sched_rt_entity *rt_se, *parent_se;
struct rq *rq;
int i;
- tg->rt_rq = kzalloc(sizeof(rt_rq) * NR_CPUS, GFP_KERNEL);
+ tg->rt_rq = kzalloc(sizeof(rt_rq) * nr_cpu_ids, GFP_KERNEL);
if (!tg->rt_rq)
goto err;
- tg->rt_se = kzalloc(sizeof(rt_se) * NR_CPUS, GFP_KERNEL);
+ tg->rt_se = kzalloc(sizeof(rt_se) * nr_cpu_ids, GFP_KERNEL);
if (!tg->rt_se)
goto err;
- tg->rt_runtime = 0;
+ init_rt_bandwidth(&tg->rt_bandwidth,
+ ktime_to_ns(def_rt_bandwidth.rt_period), 0);
for_each_possible_cpu(i) {
rq = cpu_rq(i);
if (!rt_se)
goto err;
- init_tg_rt_entry(rq, tg, rt_rq, rt_se, i, 0);
+ parent_se = parent ? parent->rt_se[i] : NULL;
+ init_tg_rt_entry(tg, rt_rq, rt_se, i, 0, parent_se);
}
return 1;
{
}
-static inline int alloc_rt_sched_group(struct task_group *tg)
+static inline
+int alloc_rt_sched_group(struct task_group *tg, struct task_group *parent)
{
return 1;
}
}
#endif
+#ifdef CONFIG_GROUP_SCHED
static void free_sched_group(struct task_group *tg)
{
free_fair_sched_group(tg);
}
/* allocate runqueue etc for a new task group */
-struct task_group *sched_create_group(void)
+struct task_group *sched_create_group(struct task_group *parent)
{
struct task_group *tg;
unsigned long flags;
if (!tg)
return ERR_PTR(-ENOMEM);
- if (!alloc_fair_sched_group(tg))
+ if (!alloc_fair_sched_group(tg, parent))
goto err;
- if (!alloc_rt_sched_group(tg))
+ if (!alloc_rt_sched_group(tg, parent))
goto err;
spin_lock_irqsave(&task_group_lock, flags);
register_rt_sched_group(tg, i);
}
list_add_rcu(&tg->list, &task_groups);
+
+ WARN_ON(!parent); /* root should already exist */
+
+ tg->parent = parent;
+ list_add_rcu(&tg->siblings, &parent->children);
+ INIT_LIST_HEAD(&tg->children);
spin_unlock_irqrestore(&task_group_lock, flags);
return tg;
unregister_rt_sched_group(tg, i);
}
list_del_rcu(&tg->list);
+ list_del_rcu(&tg->siblings);
spin_unlock_irqrestore(&task_group_lock, flags);
/* wait for possible concurrent references to cfs_rqs complete */
task_rq_unlock(rq, &flags);
}
+#endif
#ifdef CONFIG_FAIR_GROUP_SCHED
-static void set_se_shares(struct sched_entity *se, unsigned long shares)
+static void __set_se_shares(struct sched_entity *se, unsigned long shares)
{
struct cfs_rq *cfs_rq = se->cfs_rq;
- struct rq *rq = cfs_rq->rq;
int on_rq;
- spin_lock_irq(&rq->lock);
-
on_rq = se->on_rq;
if (on_rq)
dequeue_entity(cfs_rq, se, 0);
if (on_rq)
enqueue_entity(cfs_rq, se, 0);
+}
- spin_unlock_irq(&rq->lock);
+static void set_se_shares(struct sched_entity *se, unsigned long shares)
+{
+ struct cfs_rq *cfs_rq = se->cfs_rq;
+ struct rq *rq = cfs_rq->rq;
+ unsigned long flags;
+
+ spin_lock_irqsave(&rq->lock, flags);
+ __set_se_shares(se, shares);
+ spin_unlock_irqrestore(&rq->lock, flags);
}
static DEFINE_MUTEX(shares_mutex);
int i;
unsigned long flags;
+ /*
+ * We can't change the weight of the root cgroup.
+ */
+ if (!tg->se[0])
+ return -EINVAL;
+
/*
* A weight of 0 or 1 can cause arithmetics problems.
* (The default weight is 1024 - so there's no practical
* limitation from this.)
*/
- if (shares < 2)
- shares = 2;
+ if (shares < MIN_SHARES)
+ shares = MIN_SHARES;
mutex_lock(&shares_mutex);
if (tg->shares == shares)
spin_lock_irqsave(&task_group_lock, flags);
for_each_possible_cpu(i)
unregister_fair_sched_group(tg, i);
+ list_del_rcu(&tg->siblings);
spin_unlock_irqrestore(&task_group_lock, flags);
/* wait for any ongoing reference to this group to finish */
* w/o tripping rebalance_share or load_balance_fair.
*/
tg->shares = shares;
- for_each_possible_cpu(i)
- set_se_shares(tg->se[i], shares);
+ for_each_possible_cpu(i) {
+ /*
+ * force a rebalance
+ */
+ cfs_rq_set_shares(tg->cfs_rq[i], 0);
+ set_se_shares(tg->se[i], shares/nr_cpu_ids);
+ }
/*
* Enable load balance activity on this group, by inserting it back on
spin_lock_irqsave(&task_group_lock, flags);
for_each_possible_cpu(i)
register_fair_sched_group(tg, i);
+ list_add_rcu(&tg->siblings, &tg->parent->children);
spin_unlock_irqrestore(&task_group_lock, flags);
done:
mutex_unlock(&shares_mutex);
return div64_64(runtime << 16, period);
}
+#ifdef CONFIG_CGROUP_SCHED
+static int __rt_schedulable(struct task_group *tg, u64 period, u64 runtime)
+{
+ struct task_group *tgi, *parent = tg->parent;
+ unsigned long total = 0;
+
+ if (!parent) {
+ if (global_rt_period() < period)
+ return 0;
+
+ return to_ratio(period, runtime) <
+ to_ratio(global_rt_period(), global_rt_runtime());
+ }
+
+ if (ktime_to_ns(parent->rt_bandwidth.rt_period) < period)
+ return 0;
+
+ rcu_read_lock();
+ list_for_each_entry_rcu(tgi, &parent->children, siblings) {
+ if (tgi == tg)
+ continue;
+
+ total += to_ratio(ktime_to_ns(tgi->rt_bandwidth.rt_period),
+ tgi->rt_bandwidth.rt_runtime);
+ }
+ rcu_read_unlock();
+
+ return total + to_ratio(period, runtime) <
+ to_ratio(ktime_to_ns(parent->rt_bandwidth.rt_period),
+ parent->rt_bandwidth.rt_runtime);
+}
+#elif defined CONFIG_USER_SCHED
static int __rt_schedulable(struct task_group *tg, u64 period, u64 runtime)
{
struct task_group *tgi;
unsigned long total = 0;
unsigned long global_ratio =
- to_ratio(sysctl_sched_rt_period,
- sysctl_sched_rt_runtime < 0 ?
- RUNTIME_INF : sysctl_sched_rt_runtime);
+ to_ratio(global_rt_period(), global_rt_runtime());
rcu_read_lock();
list_for_each_entry_rcu(tgi, &task_groups, list) {
if (tgi == tg)
continue;
- total += to_ratio(period, tgi->rt_runtime);
+ total += to_ratio(ktime_to_ns(tgi->rt_bandwidth.rt_period),
+ tgi->rt_bandwidth.rt_runtime);
}
rcu_read_unlock();
return total + to_ratio(period, runtime) < global_ratio;
}
+#endif
/* Must be called with tasklist_lock held */
static inline int tg_has_rt_tasks(struct task_group *tg)
return 0;
}
-int sched_group_set_rt_runtime(struct task_group *tg, long rt_runtime_us)
+static int tg_set_bandwidth(struct task_group *tg,
+ u64 rt_period, u64 rt_runtime)
{
- u64 rt_runtime, rt_period;
- int err = 0;
-
- rt_period = (u64)sysctl_sched_rt_period * NSEC_PER_USEC;
- rt_runtime = (u64)rt_runtime_us * NSEC_PER_USEC;
- if (rt_runtime_us == -1)
- rt_runtime = RUNTIME_INF;
+ int i, err = 0;
mutex_lock(&rt_constraints_mutex);
read_lock(&tasklist_lock);
- if (rt_runtime_us == 0 && tg_has_rt_tasks(tg)) {
+ if (rt_runtime == 0 && tg_has_rt_tasks(tg)) {
err = -EBUSY;
goto unlock;
}
err = -EINVAL;
goto unlock;
}
- tg->rt_runtime = rt_runtime;
+
+ spin_lock_irq(&tg->rt_bandwidth.rt_runtime_lock);
+ tg->rt_bandwidth.rt_period = ns_to_ktime(rt_period);
+ tg->rt_bandwidth.rt_runtime = rt_runtime;
+
+ for_each_possible_cpu(i) {
+ struct rt_rq *rt_rq = tg->rt_rq[i];
+
+ spin_lock(&rt_rq->rt_runtime_lock);
+ rt_rq->rt_runtime = rt_runtime;
+ spin_unlock(&rt_rq->rt_runtime_lock);
+ }
+ spin_unlock_irq(&tg->rt_bandwidth.rt_runtime_lock);
unlock:
read_unlock(&tasklist_lock);
mutex_unlock(&rt_constraints_mutex);
return err;
}
+int sched_group_set_rt_runtime(struct task_group *tg, long rt_runtime_us)
+{
+ u64 rt_runtime, rt_period;
+
+ rt_period = ktime_to_ns(tg->rt_bandwidth.rt_period);
+ rt_runtime = (u64)rt_runtime_us * NSEC_PER_USEC;
+ if (rt_runtime_us < 0)
+ rt_runtime = RUNTIME_INF;
+
+ return tg_set_bandwidth(tg, rt_period, rt_runtime);
+}
+
long sched_group_rt_runtime(struct task_group *tg)
{
u64 rt_runtime_us;
- if (tg->rt_runtime == RUNTIME_INF)
+ if (tg->rt_bandwidth.rt_runtime == RUNTIME_INF)
return -1;
- rt_runtime_us = tg->rt_runtime;
+ rt_runtime_us = tg->rt_bandwidth.rt_runtime;
do_div(rt_runtime_us, NSEC_PER_USEC);
return rt_runtime_us;
}
+
+int sched_group_set_rt_period(struct task_group *tg, long rt_period_us)
+{
+ u64 rt_runtime, rt_period;
+
+ rt_period = (u64)rt_period_us * NSEC_PER_USEC;
+ rt_runtime = tg->rt_bandwidth.rt_runtime;
+
+ return tg_set_bandwidth(tg, rt_period, rt_runtime);
+}
+
+long sched_group_rt_period(struct task_group *tg)
+{
+ u64 rt_period_us;
+
+ rt_period_us = ktime_to_ns(tg->rt_bandwidth.rt_period);
+ do_div(rt_period_us, NSEC_PER_USEC);
+ return rt_period_us;
+}
+
+static int sched_rt_global_constraints(void)
+{
+ int ret = 0;
+
+ mutex_lock(&rt_constraints_mutex);
+ if (!__rt_schedulable(NULL, 1, 0))
+ ret = -EINVAL;
+ mutex_unlock(&rt_constraints_mutex);
+
+ return ret;
+}
+#else
+static int sched_rt_global_constraints(void)
+{
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(&def_rt_bandwidth.rt_runtime_lock, flags);
+ for_each_possible_cpu(i) {
+ struct rt_rq *rt_rq = &cpu_rq(i)->rt;
+
+ spin_lock(&rt_rq->rt_runtime_lock);
+ rt_rq->rt_runtime = global_rt_runtime();
+ spin_unlock(&rt_rq->rt_runtime_lock);
+ }
+ spin_unlock_irqrestore(&def_rt_bandwidth.rt_runtime_lock, flags);
+
+ return 0;
+}
#endif
-#endif /* CONFIG_GROUP_SCHED */
+
+int sched_rt_handler(struct ctl_table *table, int write,
+ struct file *filp, void __user *buffer, size_t *lenp,
+ loff_t *ppos)
+{
+ int ret;
+ int old_period, old_runtime;
+ static DEFINE_MUTEX(mutex);
+
+ mutex_lock(&mutex);
+ old_period = sysctl_sched_rt_period;
+ old_runtime = sysctl_sched_rt_runtime;
+
+ ret = proc_dointvec(table, write, filp, buffer, lenp, ppos);
+
+ if (!ret && write) {
+ ret = sched_rt_global_constraints();
+ if (ret) {
+ sysctl_sched_rt_period = old_period;
+ sysctl_sched_rt_runtime = old_runtime;
+ } else {
+ def_rt_bandwidth.rt_runtime = global_rt_runtime();
+ def_rt_bandwidth.rt_period =
+ ns_to_ktime(global_rt_period());
+ }
+ }
+ mutex_unlock(&mutex);
+
+ return ret;
+}
#ifdef CONFIG_CGROUP_SCHED
static struct cgroup_subsys_state *
cpu_cgroup_create(struct cgroup_subsys *ss, struct cgroup *cgrp)
{
- struct task_group *tg;
+ struct task_group *tg, *parent;
if (!cgrp->parent) {
/* This is early initialization for the top cgroup */
return &init_task_group.css;
}
- /* we support only 1-level deep hierarchical scheduler atm */
- if (cgrp->parent->parent)
- return ERR_PTR(-EINVAL);
-
- tg = sched_create_group();
+ parent = cgroup_tg(cgrp->parent);
+ tg = sched_create_group(parent);
if (IS_ERR(tg))
return ERR_PTR(-ENOMEM);
{
#ifdef CONFIG_RT_GROUP_SCHED
/* Don't accept realtime tasks when there is no way for them to run */
- if (rt_task(tsk) && cgroup_tg(cgrp)->rt_runtime == 0)
+ if (rt_task(tsk) && cgroup_tg(cgrp)->rt_bandwidth.rt_runtime == 0)
return -EINVAL;
#else
/* We don't support RT-tasks being in separate groups */
#endif
#ifdef CONFIG_RT_GROUP_SCHED
-static int cpu_rt_runtime_write(struct cgroup *cgrp, struct cftype *cft,
+static ssize_t cpu_rt_runtime_write(struct cgroup *cgrp, struct cftype *cft,
struct file *file,
const char __user *userbuf,
size_t nbytes, loff_t *unused_ppos)
return simple_read_from_buffer(buf, nbytes, ppos, tmp, len);
}
+
+static int cpu_rt_period_write_uint(struct cgroup *cgrp, struct cftype *cftype,
+ u64 rt_period_us)
+{
+ return sched_group_set_rt_period(cgroup_tg(cgrp), rt_period_us);
+}
+
+static u64 cpu_rt_period_read_uint(struct cgroup *cgrp, struct cftype *cft)
+{
+ return sched_group_rt_period(cgroup_tg(cgrp));
+}
#endif
static struct cftype cpu_files[] = {
.read = cpu_rt_runtime_read,
.write = cpu_rt_runtime_write,
},
+ {
+ .name = "rt_period_us",
+ .read_uint = cpu_rt_period_read_uint,
+ .write_uint = cpu_rt_period_write_uint,
+ },
#endif
};
struct cgroup_subsys cpuacct_subsys;
/* return cpu accounting group corresponding to this container */
-static inline struct cpuacct *cgroup_ca(struct cgroup *cont)
+static inline struct cpuacct *cgroup_ca(struct cgroup *cgrp)
{
- return container_of(cgroup_subsys_state(cont, cpuacct_subsys_id),
+ return container_of(cgroup_subsys_state(cgrp, cpuacct_subsys_id),
struct cpuacct, css);
}
/* create a new cpu accounting group */
static struct cgroup_subsys_state *cpuacct_create(
- struct cgroup_subsys *ss, struct cgroup *cont)
+ struct cgroup_subsys *ss, struct cgroup *cgrp)
{
struct cpuacct *ca = kzalloc(sizeof(*ca), GFP_KERNEL);
/* destroy an existing cpu accounting group */
static void
-cpuacct_destroy(struct cgroup_subsys *ss, struct cgroup *cont)
+cpuacct_destroy(struct cgroup_subsys *ss, struct cgroup *cgrp)
{
- struct cpuacct *ca = cgroup_ca(cont);
+ struct cpuacct *ca = cgroup_ca(cgrp);
free_percpu(ca->cpuusage);
kfree(ca);
}
/* return total cpu usage (in nanoseconds) of a group */
-static u64 cpuusage_read(struct cgroup *cont, struct cftype *cft)
+static u64 cpuusage_read(struct cgroup *cgrp, struct cftype *cft)
{
- struct cpuacct *ca = cgroup_ca(cont);
+ struct cpuacct *ca = cgroup_ca(cgrp);
u64 totalcpuusage = 0;
int i;
return totalcpuusage;
}
+static int cpuusage_write(struct cgroup *cgrp, struct cftype *cftype,
+ u64 reset)
+{
+ struct cpuacct *ca = cgroup_ca(cgrp);
+ int err = 0;
+ int i;
+
+ if (reset) {
+ err = -EINVAL;
+ goto out;
+ }
+
+ for_each_possible_cpu(i) {
+ u64 *cpuusage = percpu_ptr(ca->cpuusage, i);
+
+ spin_lock_irq(&cpu_rq(i)->lock);
+ *cpuusage = 0;
+ spin_unlock_irq(&cpu_rq(i)->lock);
+ }
+out:
+ return err;
+}
+
static struct cftype files[] = {
{
.name = "usage",
.read_uint = cpuusage_read,
+ .write_uint = cpuusage_write,
},
};
-static int cpuacct_populate(struct cgroup_subsys *ss, struct cgroup *cont)
+static int cpuacct_populate(struct cgroup_subsys *ss, struct cgroup *cgrp)
{
- return cgroup_add_files(cont, ss, files, ARRAY_SIZE(files));
+ return cgroup_add_files(cgrp, ss, files, ARRAY_SIZE(files));
}
/*
(long long)(p->nvcsw + p->nivcsw),
p->prio);
#ifdef CONFIG_SCHEDSTATS
- SEQ_printf(m, "%9Ld.%06ld %9Ld.%06ld %9Ld.%06ld\n",
+ SEQ_printf(m, "%9Ld.%06ld %9Ld.%06ld %9Ld.%06ld",
SPLIT_NS(p->se.vruntime),
SPLIT_NS(p->se.sum_exec_runtime),
SPLIT_NS(p->se.sum_sleep_runtime));
#else
- SEQ_printf(m, "%15Ld %15Ld %15Ld.%06ld %15Ld.%06ld %15Ld.%06ld\n",
+ SEQ_printf(m, "%15Ld %15Ld %15Ld.%06ld %15Ld.%06ld %15Ld.%06ld",
0LL, 0LL, 0LL, 0L, 0LL, 0L, 0LL, 0L);
#endif
+
+#ifdef CONFIG_CGROUP_SCHED
+ {
+ char path[64];
+
+ cgroup_path(task_group(p)->css.cgroup, path, sizeof(path));
+ SEQ_printf(m, " %s", path);
+ }
+#endif
+ SEQ_printf(m, "\n");
}
static void print_rq(struct seq_file *m, struct rq *rq, int rq_cpu)
struct sched_entity *last;
unsigned long flags;
- SEQ_printf(m, "\ncfs_rq\n");
+#if !defined(CONFIG_CGROUP_SCHED) || !defined(CONFIG_USER_SCHED)
+ SEQ_printf(m, "\ncfs_rq[%d]:\n", cpu);
+#else
+ char path[128] = "";
+ struct cgroup *cgroup = NULL;
+ struct task_group *tg = cfs_rq->tg;
+
+ if (tg)
+ cgroup = tg->css.cgroup;
+
+ if (cgroup)
+ cgroup_path(cgroup, path, sizeof(path));
+
+ SEQ_printf(m, "\ncfs_rq[%d]:%s\n", cpu, path);
+#endif
SEQ_printf(m, " .%-30s: %Ld.%06ld\n", "exec_clock",
SPLIT_NS(cfs_rq->exec_clock));
#endif
SEQ_printf(m, " .%-30s: %ld\n", "nr_spread_over",
cfs_rq->nr_spread_over);
+#ifdef CONFIG_FAIR_GROUP_SCHED
+#ifdef CONFIG_SMP
+ SEQ_printf(m, " .%-30s: %lu\n", "shares", cfs_rq->shares);
+#endif
+#endif
}
static void print_cpu(struct seq_file *m, int cpu)
PN(sysctl_sched_latency);
PN(sysctl_sched_min_granularity);
PN(sysctl_sched_wakeup_granularity);
- PN(sysctl_sched_batch_wakeup_granularity);
PN(sysctl_sched_child_runs_first);
P(sysctl_sched_features);
#undef PN
*/
unsigned int __read_mostly sysctl_sched_compat_yield;
-/*
- * SCHED_BATCH wake-up granularity.
- * (default: 10 msec * (1 + ilog(ncpus)), units: nanoseconds)
- *
- * This option delays the preemption effects of decoupled workloads
- * and reduces their over-scheduling. Synchronous workloads will still
- * have immediate wakeup/sleep latencies.
- */
-unsigned int sysctl_sched_batch_wakeup_granularity = 10000000UL;
-
/*
* SCHED_OTHER wake-up granularity.
- * (default: 5 msec * (1 + ilog(ncpus)), units: nanoseconds)
+ * (default: 10 msec * (1 + ilog(ncpus)), units: nanoseconds)
*
* This option delays the preemption effects of decoupled workloads
* and reduces their over-scheduling. Synchronous workloads will still
* have immediate wakeup/sleep latencies.
*/
-unsigned int sysctl_sched_wakeup_granularity = 5000000UL;
+unsigned int sysctl_sched_wakeup_granularity = 10000000UL;
const_debug unsigned int sysctl_sched_migration_cost = 500000UL;
* CFS operations on generic schedulable entities:
*/
+static inline struct task_struct *task_of(struct sched_entity *se)
+{
+ return container_of(se, struct task_struct, se);
+}
+
#ifdef CONFIG_FAIR_GROUP_SCHED
/* cpu runqueue to which this cfs_rq is attached */
/* An entity is a task if it doesn't "own" a runqueue */
#define entity_is_task(se) (!se->my_q)
+/* Walk up scheduling entities hierarchy */
+#define for_each_sched_entity(se) \
+ for (; se; se = se->parent)
+
+static inline struct cfs_rq *task_cfs_rq(struct task_struct *p)
+{
+ return p->se.cfs_rq;
+}
+
+/* runqueue on which this entity is (to be) queued */
+static inline struct cfs_rq *cfs_rq_of(struct sched_entity *se)
+{
+ return se->cfs_rq;
+}
+
+/* runqueue "owned" by this group */
+static inline struct cfs_rq *group_cfs_rq(struct sched_entity *grp)
+{
+ return grp->my_q;
+}
+
+/* Given a group's cfs_rq on one cpu, return its corresponding cfs_rq on
+ * another cpu ('this_cpu')
+ */
+static inline struct cfs_rq *cpu_cfs_rq(struct cfs_rq *cfs_rq, int this_cpu)
+{
+ return cfs_rq->tg->cfs_rq[this_cpu];
+}
+
+/* Iterate thr' all leaf cfs_rq's on a runqueue */
+#define for_each_leaf_cfs_rq(rq, cfs_rq) \
+ list_for_each_entry_rcu(cfs_rq, &rq->leaf_cfs_rq_list, leaf_cfs_rq_list)
+
+/* Do the two (enqueued) entities belong to the same group ? */
+static inline int
+is_same_group(struct sched_entity *se, struct sched_entity *pse)
+{
+ if (se->cfs_rq == pse->cfs_rq)
+ return 1;
+
+ return 0;
+}
+
+static inline struct sched_entity *parent_entity(struct sched_entity *se)
+{
+ return se->parent;
+}
+
#else /* CONFIG_FAIR_GROUP_SCHED */
static inline struct rq *rq_of(struct cfs_rq *cfs_rq)
#define entity_is_task(se) 1
-#endif /* CONFIG_FAIR_GROUP_SCHED */
+#define for_each_sched_entity(se) \
+ for (; se; se = NULL)
-static inline struct task_struct *task_of(struct sched_entity *se)
+static inline struct cfs_rq *task_cfs_rq(struct task_struct *p)
{
- return container_of(se, struct task_struct, se);
+ return &task_rq(p)->cfs;
+}
+
+static inline struct cfs_rq *cfs_rq_of(struct sched_entity *se)
+{
+ struct task_struct *p = task_of(se);
+ struct rq *rq = task_rq(p);
+
+ return &rq->cfs;
+}
+
+/* runqueue "owned" by this group */
+static inline struct cfs_rq *group_cfs_rq(struct sched_entity *grp)
+{
+ return NULL;
+}
+
+static inline struct cfs_rq *cpu_cfs_rq(struct cfs_rq *cfs_rq, int this_cpu)
+{
+ return &cpu_rq(this_cpu)->cfs;
+}
+
+#define for_each_leaf_cfs_rq(rq, cfs_rq) \
+ for (cfs_rq = &rq->cfs; cfs_rq; cfs_rq = NULL)
+
+static inline int
+is_same_group(struct sched_entity *se, struct sched_entity *pse)
+{
+ return 1;
+}
+
+static inline struct sched_entity *parent_entity(struct sched_entity *se)
+{
+ return NULL;
}
+#endif /* CONFIG_FAIR_GROUP_SCHED */
+
/**************************************************************
* Scheduling class tree data structure manipulation methods:
}
#endif
+/*
+ * delta *= w / rw
+ */
+static inline unsigned long
+calc_delta_weight(unsigned long delta, struct sched_entity *se)
+{
+ for_each_sched_entity(se) {
+ delta = calc_delta_mine(delta,
+ se->load.weight, &cfs_rq_of(se)->load);
+ }
+
+ return delta;
+}
+
+/*
+ * delta *= rw / w
+ */
+static inline unsigned long
+calc_delta_fair(unsigned long delta, struct sched_entity *se)
+{
+ for_each_sched_entity(se) {
+ delta = calc_delta_mine(delta,
+ cfs_rq_of(se)->load.weight, &se->load);
+ }
+
+ return delta;
+}
+
/*
* The idea is to set a period in which each task runs once.
*
*/
static u64 sched_slice(struct cfs_rq *cfs_rq, struct sched_entity *se)
{
- return calc_delta_mine(__sched_period(cfs_rq->nr_running),
- se->load.weight, &cfs_rq->load);
+ return calc_delta_weight(__sched_period(cfs_rq->nr_running), se);
}
/*
- * We calculate the vruntime slice.
+ * We calculate the vruntime slice of a to be inserted task
*
- * vs = s/w = p/rw
+ * vs = s*rw/w = p
*/
-static u64 __sched_vslice(unsigned long rq_weight, unsigned long nr_running)
+static u64 sched_vslice_add(struct cfs_rq *cfs_rq, struct sched_entity *se)
{
- u64 vslice = __sched_period(nr_running);
+ unsigned long nr_running = cfs_rq->nr_running;
- vslice *= NICE_0_LOAD;
- do_div(vslice, rq_weight);
+ if (!se->on_rq)
+ nr_running++;
- return vslice;
+ return __sched_period(nr_running);
}
-static u64 sched_vslice_add(struct cfs_rq *cfs_rq, struct sched_entity *se)
+/*
+ * The goal of calc_delta_asym() is to be asymmetrically around NICE_0_LOAD, in
+ * that it favours >=0 over <0.
+ *
+ * -20 |
+ * |
+ * 0 --------+-------
+ * .'
+ * 19 .'
+ *
+ */
+static unsigned long
+calc_delta_asym(unsigned long delta, struct sched_entity *se)
{
- return __sched_vslice(cfs_rq->load.weight + se->load.weight,
- cfs_rq->nr_running + 1);
+ struct load_weight lw = {
+ .weight = NICE_0_LOAD,
+ .inv_weight = 1UL << (WMULT_SHIFT-NICE_0_SHIFT)
+ };
+
+ for_each_sched_entity(se) {
+ struct load_weight *se_lw = &se->load;
+
+ if (se->load.weight < NICE_0_LOAD)
+ se_lw = &lw;
+
+ delta = calc_delta_mine(delta,
+ cfs_rq_of(se)->load.weight, se_lw);
+ }
+
+ return delta;
}
/*
curr->sum_exec_runtime += delta_exec;
schedstat_add(cfs_rq, exec_clock, delta_exec);
- delta_exec_weighted = delta_exec;
- if (unlikely(curr->load.weight != NICE_0_LOAD)) {
- delta_exec_weighted = calc_delta_fair(delta_exec_weighted,
- &curr->load);
- }
+ delta_exec_weighted = calc_delta_fair(delta_exec, curr);
curr->vruntime += delta_exec_weighted;
}
* Scheduling class queueing methods:
*/
+#if defined CONFIG_SMP && defined CONFIG_FAIR_GROUP_SCHED
+static void
+add_cfs_task_weight(struct cfs_rq *cfs_rq, unsigned long weight)
+{
+ cfs_rq->task_weight += weight;
+}
+#else
+static inline void
+add_cfs_task_weight(struct cfs_rq *cfs_rq, unsigned long weight)
+{
+}
+#endif
+
static void
account_entity_enqueue(struct cfs_rq *cfs_rq, struct sched_entity *se)
{
update_load_add(&cfs_rq->load, se->load.weight);
+ if (!parent_entity(se))
+ inc_cpu_load(rq_of(cfs_rq), se->load.weight);
+ if (entity_is_task(se))
+ add_cfs_task_weight(cfs_rq, se->load.weight);
cfs_rq->nr_running++;
se->on_rq = 1;
+ list_add(&se->group_node, &cfs_rq->tasks);
}
static void
account_entity_dequeue(struct cfs_rq *cfs_rq, struct sched_entity *se)
{
update_load_sub(&cfs_rq->load, se->load.weight);
+ if (!parent_entity(se))
+ dec_cpu_load(rq_of(cfs_rq), se->load.weight);
+ if (entity_is_task(se))
+ add_cfs_task_weight(cfs_rq, -se->load.weight);
cfs_rq->nr_running--;
se->on_rq = 0;
+ list_del_init(&se->group_node);
}
static void enqueue_sleeper(struct cfs_rq *cfs_rq, struct sched_entity *se)
if (!initial) {
/* sleeps upto a single latency don't count. */
- if (sched_feat(NEW_FAIR_SLEEPERS))
- vruntime -= sysctl_sched_latency;
+ if (sched_feat(NEW_FAIR_SLEEPERS)) {
+ if (sched_feat(NORMALIZED_SLEEPER))
+ vruntime -= calc_delta_weight(sysctl_sched_latency, se);
+ else
+ vruntime -= sysctl_sched_latency;
+ }
/* ensure we never gain time by being placed backwards. */
vruntime = max_vruntime(se->vruntime, vruntime);
se->prev_sum_exec_runtime = se->sum_exec_runtime;
}
+static int
+wakeup_preempt_entity(struct sched_entity *curr, struct sched_entity *se);
+
static struct sched_entity *
pick_next(struct cfs_rq *cfs_rq, struct sched_entity *se)
{
- s64 diff, gran;
-
if (!cfs_rq->next)
return se;
- diff = cfs_rq->next->vruntime - se->vruntime;
- if (diff < 0)
- return se;
-
- gran = calc_delta_fair(sysctl_sched_wakeup_granularity, &cfs_rq->load);
- if (diff > gran)
+ if (wakeup_preempt_entity(cfs_rq->next, se) != 0)
return se;
return cfs_rq->next;
* CFS operations on tasks:
*/
-#ifdef CONFIG_FAIR_GROUP_SCHED
-
-/* Walk up scheduling entities hierarchy */
-#define for_each_sched_entity(se) \
- for (; se; se = se->parent)
-
-static inline struct cfs_rq *task_cfs_rq(struct task_struct *p)
-{
- return p->se.cfs_rq;
-}
-
-/* runqueue on which this entity is (to be) queued */
-static inline struct cfs_rq *cfs_rq_of(struct sched_entity *se)
-{
- return se->cfs_rq;
-}
-
-/* runqueue "owned" by this group */
-static inline struct cfs_rq *group_cfs_rq(struct sched_entity *grp)
-{
- return grp->my_q;
-}
-
-/* Given a group's cfs_rq on one cpu, return its corresponding cfs_rq on
- * another cpu ('this_cpu')
- */
-static inline struct cfs_rq *cpu_cfs_rq(struct cfs_rq *cfs_rq, int this_cpu)
-{
- return cfs_rq->tg->cfs_rq[this_cpu];
-}
-
-/* Iterate thr' all leaf cfs_rq's on a runqueue */
-#define for_each_leaf_cfs_rq(rq, cfs_rq) \
- list_for_each_entry_rcu(cfs_rq, &rq->leaf_cfs_rq_list, leaf_cfs_rq_list)
-
-/* Do the two (enqueued) entities belong to the same group ? */
-static inline int
-is_same_group(struct sched_entity *se, struct sched_entity *pse)
-{
- if (se->cfs_rq == pse->cfs_rq)
- return 1;
-
- return 0;
-}
-
-static inline struct sched_entity *parent_entity(struct sched_entity *se)
-{
- return se->parent;
-}
-
-#else /* CONFIG_FAIR_GROUP_SCHED */
-
-#define for_each_sched_entity(se) \
- for (; se; se = NULL)
-
-static inline struct cfs_rq *task_cfs_rq(struct task_struct *p)
-{
- return &task_rq(p)->cfs;
-}
-
-static inline struct cfs_rq *cfs_rq_of(struct sched_entity *se)
-{
- struct task_struct *p = task_of(se);
- struct rq *rq = task_rq(p);
-
- return &rq->cfs;
-}
-
-/* runqueue "owned" by this group */
-static inline struct cfs_rq *group_cfs_rq(struct sched_entity *grp)
-{
- return NULL;
-}
-
-static inline struct cfs_rq *cpu_cfs_rq(struct cfs_rq *cfs_rq, int this_cpu)
-{
- return &cpu_rq(this_cpu)->cfs;
-}
-
-#define for_each_leaf_cfs_rq(rq, cfs_rq) \
- for (cfs_rq = &rq->cfs; cfs_rq; cfs_rq = NULL)
-
-static inline int
-is_same_group(struct sched_entity *se, struct sched_entity *pse)
-{
- return 1;
-}
-
-static inline struct sched_entity *parent_entity(struct sched_entity *se)
-{
- return NULL;
-}
-
-#endif /* CONFIG_FAIR_GROUP_SCHED */
-
#ifdef CONFIG_SCHED_HRTICK
static void hrtick_start_fair(struct rq *rq, struct task_struct *p)
{
/*
* Already in the rightmost position?
*/
- if (unlikely(rightmost->vruntime < se->vruntime))
+ if (unlikely(!rightmost || rightmost->vruntime < se->vruntime))
return;
/*
return cpu;
for_each_domain(cpu, sd) {
- if (sd->flags & SD_WAKE_IDLE) {
+ if ((sd->flags & SD_WAKE_IDLE)
+ || ((sd->flags & SD_WAKE_IDLE_FAR)
+ && !task_hot(p, task_rq(p)->clock, sd))) {
cpus_and(tmp, sd->span, p->cpus_allowed);
for_each_cpu_mask(i, tmp) {
if (idle_cpu(i)) {
}
#endif /* CONFIG_SMP */
+static unsigned long wakeup_gran(struct sched_entity *se)
+{
+ unsigned long gran = sysctl_sched_wakeup_granularity;
+
+ /*
+ * More easily preempt - nice tasks, while not making it harder for
+ * + nice tasks.
+ */
+ gran = calc_delta_asym(sysctl_sched_wakeup_granularity, se);
+
+ return gran;
+}
+
+/*
+ * Should 'se' preempt 'curr'.
+ *
+ * |s1
+ * |s2
+ * |s3
+ * g
+ * |<--->|c
+ *
+ * w(c, s1) = -1
+ * w(c, s2) = 0
+ * w(c, s3) = 1
+ *
+ */
+static int
+wakeup_preempt_entity(struct sched_entity *curr, struct sched_entity *se)
+{
+ s64 gran, vdiff = curr->vruntime - se->vruntime;
+
+ if (vdiff < 0)
+ return -1;
+
+ gran = wakeup_gran(curr);
+ if (vdiff > gran)
+ return 1;
+
+ return 0;
+}
+
+/* return depth at which a sched entity is present in the hierarchy */
+static inline int depth_se(struct sched_entity *se)
+{
+ int depth = 0;
+
+ for_each_sched_entity(se)
+ depth++;
+
+ return depth;
+}
/*
* Preempt the current task with a newly woken task if needed:
struct task_struct *curr = rq->curr;
struct cfs_rq *cfs_rq = task_cfs_rq(curr);
struct sched_entity *se = &curr->se, *pse = &p->se;
- unsigned long gran;
+ int se_depth, pse_depth;
if (unlikely(rt_prio(p->prio))) {
update_rq_clock(rq);
if (!sched_feat(WAKEUP_PREEMPT))
return;
- while (!is_same_group(se, pse)) {
+ /*
+ * preemption test can be made between sibling entities who are in the
+ * same cfs_rq i.e who have a common parent. Walk up the hierarchy of
+ * both tasks until we find their ancestors who are siblings of common
+ * parent.
+ */
+
+ /* First walk up until both entities are at same depth */
+ se_depth = depth_se(se);
+ pse_depth = depth_se(pse);
+
+ while (se_depth > pse_depth) {
+ se_depth--;
se = parent_entity(se);
+ }
+
+ while (pse_depth > se_depth) {
+ pse_depth--;
pse = parent_entity(pse);
}
- gran = sysctl_sched_wakeup_granularity;
- /*
- * More easily preempt - nice tasks, while not making
- * it harder for + nice tasks.
- */
- if (unlikely(se->load.weight > NICE_0_LOAD))
- gran = calc_delta_fair(gran, &se->load);
+ while (!is_same_group(se, pse)) {
+ se = parent_entity(se);
+ pse = parent_entity(pse);
+ }
- if (pse->vruntime + gran < se->vruntime)
+ if (wakeup_preempt_entity(se, pse) == 1)
resched_task(curr);
}
* the current task:
*/
static struct task_struct *
-__load_balance_iterator(struct cfs_rq *cfs_rq, struct rb_node *curr)
+__load_balance_iterator(struct cfs_rq *cfs_rq, struct list_head *next)
{
- struct task_struct *p;
+ struct task_struct *p = NULL;
+ struct sched_entity *se;
+
+ if (next == &cfs_rq->tasks)
+ return NULL;
+
+ /* Skip over entities that are not tasks */
+ do {
+ se = list_entry(next, struct sched_entity, group_node);
+ next = next->next;
+ } while (next != &cfs_rq->tasks && !entity_is_task(se));
- if (!curr)
+ if (next == &cfs_rq->tasks)
return NULL;
- p = rb_entry(curr, struct task_struct, se.run_node);
- cfs_rq->rb_load_balance_curr = rb_next(curr);
+ cfs_rq->balance_iterator = next;
+
+ if (entity_is_task(se))
+ p = task_of(se);
return p;
}
{
struct cfs_rq *cfs_rq = arg;
- return __load_balance_iterator(cfs_rq, first_fair(cfs_rq));
+ return __load_balance_iterator(cfs_rq, cfs_rq->tasks.next);
}
static struct task_struct *load_balance_next_fair(void *arg)
{
struct cfs_rq *cfs_rq = arg;
- return __load_balance_iterator(cfs_rq, cfs_rq->rb_load_balance_curr);
+ return __load_balance_iterator(cfs_rq, cfs_rq->balance_iterator);
}
-#ifdef CONFIG_FAIR_GROUP_SCHED
-static int cfs_rq_best_prio(struct cfs_rq *cfs_rq)
+static unsigned long
+__load_balance_fair(struct rq *this_rq, int this_cpu, struct rq *busiest,
+ unsigned long max_load_move, struct sched_domain *sd,
+ enum cpu_idle_type idle, int *all_pinned, int *this_best_prio,
+ struct cfs_rq *cfs_rq)
{
- struct sched_entity *curr;
- struct task_struct *p;
-
- if (!cfs_rq->nr_running || !first_fair(cfs_rq))
- return MAX_PRIO;
-
- curr = cfs_rq->curr;
- if (!curr)
- curr = __pick_next_entity(cfs_rq);
+ struct rq_iterator cfs_rq_iterator;
- p = task_of(curr);
+ cfs_rq_iterator.start = load_balance_start_fair;
+ cfs_rq_iterator.next = load_balance_next_fair;
+ cfs_rq_iterator.arg = cfs_rq;
- return p->prio;
+ return balance_tasks(this_rq, this_cpu, busiest,
+ max_load_move, sd, idle, all_pinned,
+ this_best_prio, &cfs_rq_iterator);
}
-#endif
+#ifdef CONFIG_FAIR_GROUP_SCHED
static unsigned long
load_balance_fair(struct rq *this_rq, int this_cpu, struct rq *busiest,
unsigned long max_load_move,
struct sched_domain *sd, enum cpu_idle_type idle,
int *all_pinned, int *this_best_prio)
{
- struct cfs_rq *busy_cfs_rq;
long rem_load_move = max_load_move;
- struct rq_iterator cfs_rq_iterator;
-
- cfs_rq_iterator.start = load_balance_start_fair;
- cfs_rq_iterator.next = load_balance_next_fair;
+ int busiest_cpu = cpu_of(busiest);
+ struct task_group *tg;
- for_each_leaf_cfs_rq(busiest, busy_cfs_rq) {
-#ifdef CONFIG_FAIR_GROUP_SCHED
- struct cfs_rq *this_cfs_rq;
+ rcu_read_lock();
+ list_for_each_entry(tg, &task_groups, list) {
long imbalance;
- unsigned long maxload;
+ unsigned long this_weight, busiest_weight;
+ long rem_load, max_load, moved_load;
+
+ /*
+ * empty group
+ */
+ if (!aggregate(tg, sd)->task_weight)
+ continue;
+
+ rem_load = rem_load_move * aggregate(tg, sd)->rq_weight;
+ rem_load /= aggregate(tg, sd)->load + 1;
+
+ this_weight = tg->cfs_rq[this_cpu]->task_weight;
+ busiest_weight = tg->cfs_rq[busiest_cpu]->task_weight;
+
+ imbalance = (busiest_weight - this_weight) / 2;
- this_cfs_rq = cpu_cfs_rq(busy_cfs_rq, this_cpu);
+ if (imbalance < 0)
+ imbalance = busiest_weight;
- imbalance = busy_cfs_rq->load.weight - this_cfs_rq->load.weight;
- /* Don't pull if this_cfs_rq has more load than busy_cfs_rq */
- if (imbalance <= 0)
+ max_load = max(rem_load, imbalance);
+ moved_load = __load_balance_fair(this_rq, this_cpu, busiest,
+ max_load, sd, idle, all_pinned, this_best_prio,
+ tg->cfs_rq[busiest_cpu]);
+
+ if (!moved_load)
continue;
- /* Don't pull more than imbalance/2 */
- imbalance /= 2;
- maxload = min(rem_load_move, imbalance);
+ move_group_shares(tg, sd, busiest_cpu, this_cpu);
- *this_best_prio = cfs_rq_best_prio(this_cfs_rq);
-#else
-# define maxload rem_load_move
-#endif
- /*
- * pass busy_cfs_rq argument into
- * load_balance_[start|next]_fair iterators
- */
- cfs_rq_iterator.arg = busy_cfs_rq;
- rem_load_move -= balance_tasks(this_rq, this_cpu, busiest,
- maxload, sd, idle, all_pinned,
- this_best_prio,
- &cfs_rq_iterator);
+ moved_load *= aggregate(tg, sd)->load;
+ moved_load /= aggregate(tg, sd)->rq_weight + 1;
- if (rem_load_move <= 0)
+ rem_load_move -= moved_load;
+ if (rem_load_move < 0)
break;
}
+ rcu_read_unlock();
return max_load_move - rem_load_move;
}
+#else
+static unsigned long
+load_balance_fair(struct rq *this_rq, int this_cpu, struct rq *busiest,
+ unsigned long max_load_move,
+ struct sched_domain *sd, enum cpu_idle_type idle,
+ int *all_pinned, int *this_best_prio)
+{
+ return __load_balance_fair(this_rq, this_cpu, busiest,
+ max_load_move, sd, idle, all_pinned,
+ this_best_prio, &busiest->cfs);
+}
+#endif
static int
move_one_task_fair(struct rq *this_rq, int this_cpu, struct rq *busiest,
};
#ifdef CONFIG_SCHED_DEBUG
+static void
+print_cfs_rq_tasks(struct seq_file *m, struct cfs_rq *cfs_rq, int depth)
+{
+ struct sched_entity *se;
+
+ if (!cfs_rq)
+ return;
+
+ list_for_each_entry_rcu(se, &cfs_rq->tasks, group_node) {
+ int i;
+
+ for (i = depth; i; i--)
+ seq_puts(m, " ");
+
+ seq_printf(m, "%lu %s %lu\n",
+ se->load.weight,
+ entity_is_task(se) ? "T" : "G",
+ calc_delta_weight(SCHED_LOAD_SCALE, se)
+ );
+ if (!entity_is_task(se))
+ print_cfs_rq_tasks(m, group_cfs_rq(se), depth + 1);
+ }
+}
+
static void print_cfs_stats(struct seq_file *m, int cpu)
{
struct cfs_rq *cfs_rq;
-#ifdef CONFIG_FAIR_GROUP_SCHED
- print_cfs_rq(m, cpu, &cpu_rq(cpu)->cfs);
-#endif
rcu_read_lock();
for_each_leaf_cfs_rq(cpu_rq(cpu), cfs_rq)
print_cfs_rq(m, cpu, cfs_rq);
+
+ seq_printf(m, "\nWeight tree:\n");
+ print_cfs_rq_tasks(m, &cpu_rq(cpu)->cfs, 1);
rcu_read_unlock();
}
#endif
--- /dev/null
+SCHED_FEAT(NEW_FAIR_SLEEPERS, 1)
+SCHED_FEAT(WAKEUP_PREEMPT, 1)
+SCHED_FEAT(START_DEBIT, 1)
+SCHED_FEAT(AFFINE_WAKEUPS, 1)
+SCHED_FEAT(CACHE_HOT_BUDDY, 1)
+SCHED_FEAT(SYNC_WAKEUPS, 1)
+SCHED_FEAT(HRTICK, 1)
+SCHED_FEAT(DOUBLE_TICK, 0)
+SCHED_FEAT(NORMALIZED_SLEEPER, 1)
+SCHED_FEAT(DEADLINE, 1)
if (!rt_rq->tg)
return RUNTIME_INF;
- return rt_rq->tg->rt_runtime;
+ return rt_rq->rt_runtime;
+}
+
+static inline u64 sched_rt_period(struct rt_rq *rt_rq)
+{
+ return ktime_to_ns(rt_rq->tg->rt_bandwidth.rt_period);
}
#define for_each_leaf_rt_rq(rt_rq, rq) \
return p->prio != p->normal_prio;
}
+#ifdef CONFIG_SMP
+static inline cpumask_t sched_rt_period_mask(void)
+{
+ return cpu_rq(smp_processor_id())->rd->span;
+}
+#else
+static inline cpumask_t sched_rt_period_mask(void)
+{
+ return cpu_online_map;
+}
+#endif
+
+static inline
+struct rt_rq *sched_rt_period_rt_rq(struct rt_bandwidth *rt_b, int cpu)
+{
+ return container_of(rt_b, struct task_group, rt_bandwidth)->rt_rq[cpu];
+}
+
+static inline struct rt_bandwidth *sched_rt_bandwidth(struct rt_rq *rt_rq)
+{
+ return &rt_rq->tg->rt_bandwidth;
+}
+
#else
static inline u64 sched_rt_runtime(struct rt_rq *rt_rq)
{
- if (sysctl_sched_rt_runtime == -1)
- return RUNTIME_INF;
+ return rt_rq->rt_runtime;
+}
- return (u64)sysctl_sched_rt_runtime * NSEC_PER_USEC;
+static inline u64 sched_rt_period(struct rt_rq *rt_rq)
+{
+ return ktime_to_ns(def_rt_bandwidth.rt_period);
}
#define for_each_leaf_rt_rq(rt_rq, rq) \
{
return rt_rq->rt_throttled;
}
+
+static inline cpumask_t sched_rt_period_mask(void)
+{
+ return cpu_online_map;
+}
+
+static inline
+struct rt_rq *sched_rt_period_rt_rq(struct rt_bandwidth *rt_b, int cpu)
+{
+ return &cpu_rq(cpu)->rt;
+}
+
+static inline struct rt_bandwidth *sched_rt_bandwidth(struct rt_rq *rt_rq)
+{
+ return &def_rt_bandwidth;
+}
+
+#endif
+
+static int do_sched_rt_period_timer(struct rt_bandwidth *rt_b, int overrun)
+{
+ int i, idle = 1;
+ cpumask_t span;
+
+ if (rt_b->rt_runtime == RUNTIME_INF)
+ return 1;
+
+ span = sched_rt_period_mask();
+ for_each_cpu_mask(i, span) {
+ int enqueue = 0;
+ struct rt_rq *rt_rq = sched_rt_period_rt_rq(rt_b, i);
+ struct rq *rq = rq_of_rt_rq(rt_rq);
+
+ spin_lock(&rq->lock);
+ if (rt_rq->rt_time) {
+ u64 runtime;
+
+ spin_lock(&rt_rq->rt_runtime_lock);
+ runtime = rt_rq->rt_runtime;
+ rt_rq->rt_time -= min(rt_rq->rt_time, overrun*runtime);
+ if (rt_rq->rt_throttled && rt_rq->rt_time < runtime) {
+ rt_rq->rt_throttled = 0;
+ enqueue = 1;
+ }
+ if (rt_rq->rt_time || rt_rq->rt_nr_running)
+ idle = 0;
+ spin_unlock(&rt_rq->rt_runtime_lock);
+ }
+
+ if (enqueue)
+ sched_rt_rq_enqueue(rt_rq);
+ spin_unlock(&rq->lock);
+ }
+
+ return idle;
+}
+
+#ifdef CONFIG_SMP
+static int balance_runtime(struct rt_rq *rt_rq)
+{
+ struct rt_bandwidth *rt_b = sched_rt_bandwidth(rt_rq);
+ struct root_domain *rd = cpu_rq(smp_processor_id())->rd;
+ int i, weight, more = 0;
+ u64 rt_period;
+
+ weight = cpus_weight(rd->span);
+
+ spin_lock(&rt_b->rt_runtime_lock);
+ rt_period = ktime_to_ns(rt_b->rt_period);
+ for_each_cpu_mask(i, rd->span) {
+ struct rt_rq *iter = sched_rt_period_rt_rq(rt_b, i);
+ s64 diff;
+
+ if (iter == rt_rq)
+ continue;
+
+ spin_lock(&iter->rt_runtime_lock);
+ diff = iter->rt_runtime - iter->rt_time;
+ if (diff > 0) {
+ do_div(diff, weight);
+ if (rt_rq->rt_runtime + diff > rt_period)
+ diff = rt_period - rt_rq->rt_runtime;
+ iter->rt_runtime -= diff;
+ rt_rq->rt_runtime += diff;
+ more = 1;
+ if (rt_rq->rt_runtime == rt_period) {
+ spin_unlock(&iter->rt_runtime_lock);
+ break;
+ }
+ }
+ spin_unlock(&iter->rt_runtime_lock);
+ }
+ spin_unlock(&rt_b->rt_runtime_lock);
+
+ return more;
+}
#endif
static inline int rt_se_prio(struct sched_rt_entity *rt_se)
if (rt_rq->rt_throttled)
return rt_rq_throttled(rt_rq);
+ if (sched_rt_runtime(rt_rq) >= sched_rt_period(rt_rq))
+ return 0;
+
+#ifdef CONFIG_SMP
if (rt_rq->rt_time > runtime) {
- struct rq *rq = rq_of_rt_rq(rt_rq);
+ int more;
- rq->rt_throttled = 1;
- rt_rq->rt_throttled = 1;
+ spin_unlock(&rt_rq->rt_runtime_lock);
+ more = balance_runtime(rt_rq);
+ spin_lock(&rt_rq->rt_runtime_lock);
+ if (more)
+ runtime = sched_rt_runtime(rt_rq);
+ }
+#endif
+
+ if (rt_rq->rt_time > runtime) {
+ rt_rq->rt_throttled = 1;
if (rt_rq_throttled(rt_rq)) {
sched_rt_rq_dequeue(rt_rq);
return 1;
return 0;
}
-static void update_sched_rt_period(struct rq *rq)
-{
- struct rt_rq *rt_rq;
- u64 period;
-
- while (rq->clock > rq->rt_period_expire) {
- period = (u64)sysctl_sched_rt_period * NSEC_PER_USEC;
- rq->rt_period_expire += period;
-
- for_each_leaf_rt_rq(rt_rq, rq) {
- u64 runtime = sched_rt_runtime(rt_rq);
-
- rt_rq->rt_time -= min(rt_rq->rt_time, runtime);
- if (rt_rq->rt_throttled && rt_rq->rt_time < runtime) {
- rt_rq->rt_throttled = 0;
- sched_rt_rq_enqueue(rt_rq);
- }
- }
-
- rq->rt_throttled = 0;
- }
-}
-
/*
* Update the current task's runtime statistics. Skip current tasks that
* are not in our scheduling class.
curr->se.exec_start = rq->clock;
cpuacct_charge(curr, delta_exec);
- rt_rq->rt_time += delta_exec;
- if (sched_rt_runtime_exceeded(rt_rq))
- resched_task(curr);
+ for_each_sched_rt_entity(rt_se) {
+ rt_rq = rt_rq_of_se(rt_se);
+
+ spin_lock(&rt_rq->rt_runtime_lock);
+ rt_rq->rt_time += delta_exec;
+ if (sched_rt_runtime_exceeded(rt_rq))
+ resched_task(curr);
+ spin_unlock(&rt_rq->rt_runtime_lock);
+ }
}
static inline
#ifdef CONFIG_RT_GROUP_SCHED
if (rt_se_boosted(rt_se))
rt_rq->rt_nr_boosted++;
+
+ if (rt_rq->tg)
+ start_rt_bandwidth(&rt_rq->tg->rt_bandwidth);
+#else
+ start_rt_bandwidth(&def_rt_bandwidth);
#endif
}
/*
* Because the prio of an upper entry depends on the lower
* entries, we must remove entries top - down.
- *
- * XXX: O(1/2 h^2) because we can only walk up, not down the chain.
- * doesn't matter much for now, as h=2 for GROUP_SCHED.
*/
static void dequeue_rt_stack(struct task_struct *p)
{
- struct sched_rt_entity *rt_se, *top_se;
+ struct sched_rt_entity *rt_se, *back = NULL;
- /*
- * dequeue all, top - down.
- */
- do {
- rt_se = &p->rt;
- top_se = NULL;
- for_each_sched_rt_entity(rt_se) {
- if (on_rt_rq(rt_se))
- top_se = rt_se;
- }
- if (top_se)
- dequeue_rt_entity(top_se);
- } while (top_se);
+ rt_se = &p->rt;
+ for_each_sched_rt_entity(rt_se) {
+ rt_se->back = back;
+ back = rt_se;
+ }
+
+ for (rt_se = back; rt_se; rt_se = rt_se->back) {
+ if (on_rt_rq(rt_se))
+ dequeue_rt_entity(rt_se);
+ }
}
/*
*/
for_each_sched_rt_entity(rt_se)
enqueue_rt_entity(rt_se);
+
+ inc_cpu_load(rq, p->se.load.weight);
}
static void dequeue_task_rt(struct rq *rq, struct task_struct *p, int sleep)
if (rt_rq && rt_rq->rt_nr_running)
enqueue_rt_entity(rt_se);
}
+
+ dec_cpu_load(rq, p->se.load.weight);
}
/*
return 0;
}
-static void set_cpus_allowed_rt(struct task_struct *p, cpumask_t *new_mask)
+static void set_cpus_allowed_rt(struct task_struct *p,
+ const cpumask_t *new_mask)
{
int weight = cpus_weight(*new_mask);
static int show_schedstat(struct seq_file *seq, void *v)
{
int cpu;
+ int mask_len = NR_CPUS/32 * 9;
+ char *mask_str = kmalloc(mask_len, GFP_KERNEL);
+
+ if (mask_str == NULL)
+ return -ENOMEM;
seq_printf(seq, "version %d\n", SCHEDSTAT_VERSION);
seq_printf(seq, "timestamp %lu\n", jiffies);
preempt_disable();
for_each_domain(cpu, sd) {
enum cpu_idle_type itype;
- char mask_str[NR_CPUS];
- cpumask_scnprintf(mask_str, NR_CPUS, sd->span);
+ cpumask_scnprintf(mask_str, mask_len, sd->span);
seq_printf(seq, "domain%d %s", dcount++, mask_str);
for (itype = CPU_IDLE; itype < CPU_MAX_IDLE_TYPES;
itype++) {
unsigned long flags;
spin_lock_irqsave(&t->sighand->siglock, flags);
- clear_tsk_thread_flag(t,TIF_SIGPENDING);
+ clear_tsk_thread_flag(t, TIF_SIGPENDING);
flush_sigqueue(&t->pending);
flush_sigqueue(&t->signal->shared_pending);
spin_unlock_irqrestore(&t->sighand->siglock, flags);
}
if (signr &&
((info->si_code & __SI_MASK) == __SI_TIMER) &&
- info->si_sys_private){
+ info->si_sys_private) {
/*
* Release the siglock to ensure proper locking order
* of timer locks outside of siglocks. Note, we leave
/* Tasklets */
struct tasklet_head
{
- struct tasklet_struct *list;
+ struct tasklet_struct *head;
+ struct tasklet_struct **tail;
};
/* Some compilers disobey section attribute on statics when not
unsigned long flags;
local_irq_save(flags);
- t->next = __get_cpu_var(tasklet_vec).list;
- __get_cpu_var(tasklet_vec).list = t;
+ t->next = NULL;
+ *__get_cpu_var(tasklet_vec).tail = t;
+ __get_cpu_var(tasklet_vec).tail = &(t->next);
raise_softirq_irqoff(TASKLET_SOFTIRQ);
local_irq_restore(flags);
}
unsigned long flags;
local_irq_save(flags);
- t->next = __get_cpu_var(tasklet_hi_vec).list;
- __get_cpu_var(tasklet_hi_vec).list = t;
+ t->next = NULL;
+ *__get_cpu_var(tasklet_hi_vec).tail = t;
+ __get_cpu_var(tasklet_hi_vec).tail = &(t->next);
raise_softirq_irqoff(HI_SOFTIRQ);
local_irq_restore(flags);
}
struct tasklet_struct *list;
local_irq_disable();
- list = __get_cpu_var(tasklet_vec).list;
- __get_cpu_var(tasklet_vec).list = NULL;
+ list = __get_cpu_var(tasklet_vec).head;
+ __get_cpu_var(tasklet_vec).head = NULL;
+ __get_cpu_var(tasklet_vec).tail = &__get_cpu_var(tasklet_vec).head;
local_irq_enable();
while (list) {
}
local_irq_disable();
- t->next = __get_cpu_var(tasklet_vec).list;
- __get_cpu_var(tasklet_vec).list = t;
+ t->next = NULL;
+ *__get_cpu_var(tasklet_vec).tail = t;
+ __get_cpu_var(tasklet_vec).tail = &(t->next);
__raise_softirq_irqoff(TASKLET_SOFTIRQ);
local_irq_enable();
}
struct tasklet_struct *list;
local_irq_disable();
- list = __get_cpu_var(tasklet_hi_vec).list;
- __get_cpu_var(tasklet_hi_vec).list = NULL;
+ list = __get_cpu_var(tasklet_hi_vec).head;
+ __get_cpu_var(tasklet_hi_vec).head = NULL;
+ __get_cpu_var(tasklet_hi_vec).tail = &__get_cpu_var(tasklet_hi_vec).head;
local_irq_enable();
while (list) {
}
local_irq_disable();
- t->next = __get_cpu_var(tasklet_hi_vec).list;
- __get_cpu_var(tasklet_hi_vec).list = t;
+ t->next = NULL;
+ *__get_cpu_var(tasklet_hi_vec).tail = t;
+ __get_cpu_var(tasklet_hi_vec).tail = &(t->next);
__raise_softirq_irqoff(HI_SOFTIRQ);
local_irq_enable();
}
void __init softirq_init(void)
{
+ int cpu;
+
+ for_each_possible_cpu(cpu) {
+ per_cpu(tasklet_vec, cpu).tail =
+ &per_cpu(tasklet_vec, cpu).head;
+ per_cpu(tasklet_hi_vec, cpu).tail =
+ &per_cpu(tasklet_hi_vec, cpu).head;
+ }
+
open_softirq(TASKLET_SOFTIRQ, tasklet_action, NULL);
open_softirq(HI_SOFTIRQ, tasklet_hi_action, NULL);
}
return;
/* CPU is dead, so no lock needed. */
- for (i = &per_cpu(tasklet_vec, cpu).list; *i; i = &(*i)->next) {
+ for (i = &per_cpu(tasklet_vec, cpu).head; *i; i = &(*i)->next) {
if (*i == t) {
*i = t->next;
+ /* If this was the tail element, move the tail ptr */
+ if (*i == NULL)
+ per_cpu(tasklet_vec, cpu).tail = i;
return;
}
}
static void takeover_tasklets(unsigned int cpu)
{
- struct tasklet_struct **i;
-
/* CPU is dead, so no lock needed. */
local_irq_disable();
/* Find end, append list for that CPU. */
- for (i = &__get_cpu_var(tasklet_vec).list; *i; i = &(*i)->next);
- *i = per_cpu(tasklet_vec, cpu).list;
- per_cpu(tasklet_vec, cpu).list = NULL;
+ *__get_cpu_var(tasklet_vec).tail = per_cpu(tasklet_vec, cpu).head;
+ __get_cpu_var(tasklet_vec).tail = per_cpu(tasklet_vec, cpu).tail;
+ per_cpu(tasklet_vec, cpu).head = NULL;
+ per_cpu(tasklet_vec, cpu).tail = &per_cpu(tasklet_vec, cpu).head;
raise_softirq_irqoff(TASKLET_SOFTIRQ);
- for (i = &__get_cpu_var(tasklet_hi_vec).list; *i; i = &(*i)->next);
- *i = per_cpu(tasklet_hi_vec, cpu).list;
- per_cpu(tasklet_hi_vec, cpu).list = NULL;
+ *__get_cpu_var(tasklet_hi_vec).tail = per_cpu(tasklet_hi_vec, cpu).head;
+ __get_cpu_var(tasklet_hi_vec).tail = per_cpu(tasklet_hi_vec, cpu).tail;
+ per_cpu(tasklet_hi_vec, cpu).head = NULL;
+ per_cpu(tasklet_hi_vec, cpu).tail = &per_cpu(tasklet_hi_vec, cpu).head;
raise_softirq_irqoff(HI_SOFTIRQ);
local_irq_enable();
#include <linux/interrupt.h>
#include <asm/atomic.h>
-#include <asm/semaphore.h>
#include <asm/uaccess.h>
/* Since we effect priority and affinity (both of which are visible
int irqs_disabled = 0;
int prepared = 0;
- set_cpus_allowed(current, cpumask_of_cpu((int)(long)cpu));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu((int)(long)cpu));
/* Ack: we are alive */
smp_mb(); /* Theoretically the ack = 0 might not be on this CPU yet. */
preempt_enable_no_resched();
}
-struct stop_machine_data
-{
+struct stop_machine_data {
int (*fn)(void *);
void *data;
struct completion done;
#ifndef SET_ENDIAN
# define SET_ENDIAN(a,b) (-EINVAL)
#endif
+#ifndef GET_TSC_CTL
+# define GET_TSC_CTL(a) (-EINVAL)
+#endif
+#ifndef SET_TSC_CTL
+# define SET_TSC_CTL(a) (-EINVAL)
+#endif
/*
* this is where the system-wide overflow UID and GID are defined, for
#else
return -EINVAL;
#endif
-
+ case PR_GET_TSC:
+ error = GET_TSC_CTL(arg2);
+ break;
+ case PR_SET_TSC:
+ error = SET_TSC_CTL(arg2);
+ break;
default:
error = -EINVAL;
break;
.extra1 = &min_wakeup_granularity_ns,
.extra2 = &max_wakeup_granularity_ns,
},
- {
- .ctl_name = CTL_UNNUMBERED,
- .procname = "sched_batch_wakeup_granularity_ns",
- .data = &sysctl_sched_batch_wakeup_granularity,
- .maxlen = sizeof(unsigned int),
- .mode = 0644,
- .proc_handler = &proc_dointvec_minmax,
- .strategy = &sysctl_intvec,
- .extra1 = &min_wakeup_granularity_ns,
- .extra2 = &max_wakeup_granularity_ns,
- },
{
.ctl_name = CTL_UNNUMBERED,
.procname = "sched_child_runs_first",
.data = &sysctl_sched_rt_period,
.maxlen = sizeof(unsigned int),
.mode = 0644,
- .proc_handler = &proc_dointvec,
+ .proc_handler = &sched_rt_handler,
},
{
.ctl_name = CTL_UNNUMBERED,
.data = &sysctl_sched_rt_runtime,
.maxlen = sizeof(int),
.mode = 0644,
- .proc_handler = &proc_dointvec,
+ .proc_handler = &sched_rt_handler,
},
{
.ctl_name = CTL_UNNUMBERED,
void tick_broadcast_on_off(unsigned long reason, int *oncpu)
{
if (!cpu_isset(*oncpu, cpu_online_map))
- printk(KERN_ERR "tick-braodcast: ignoring broadcast for "
+ printk(KERN_ERR "tick-broadcast: ignoring broadcast for "
"offline CPU #%d\n", *oncpu);
else
smp_call_function_single(*oncpu, tick_do_broadcast_on_off,
void tick_nohz_stop_sched_tick(void)
{
unsigned long seq, last_jiffies, next_jiffies, delta_jiffies, flags;
- unsigned long rt_jiffies;
struct tick_sched *ts;
ktime_t last_update, expires, now;
struct clock_event_device *dev = __get_cpu_var(tick_cpu_device).evtdev;
next_jiffies = get_next_timer_interrupt(last_jiffies);
delta_jiffies = next_jiffies - last_jiffies;
- rt_jiffies = rt_needs_cpu(cpu);
- if (rt_jiffies && rt_jiffies < delta_jiffies)
- delta_jiffies = rt_jiffies;
-
if (rcu_needs_cpu(cpu))
delta_jiffies = 1;
/*
if (clock == new)
return;
+ new->cycle_last = 0;
now = clocksource_read(new);
nsec = __get_nsec_offset();
timespec_add_ns(&xtime, nsec);
timespec_add_ns(&xtime, timekeeping_suspend_nsecs);
update_xtime_cache(0);
/* re-base the last cycle value */
+ clock->cycle_last = 0;
clock->cycle_last = clocksource_read(clock);
clock->error = 0;
timekeeping_suspended = 0;
{
int rc = 0;
- up->tg = sched_create_group();
+ up->tg = sched_create_group(&root_task_group);
if (IS_ERR(up->tg))
rc = -ENOMEM;
static struct kobj_attribute cpu_rt_runtime_attr =
__ATTR(cpu_rt_runtime, 0644, cpu_rt_runtime_show, cpu_rt_runtime_store);
+
+static ssize_t cpu_rt_period_show(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ char *buf)
+{
+ struct user_struct *up = container_of(kobj, struct user_struct, kobj);
+
+ return sprintf(buf, "%lu\n", sched_group_rt_period(up->tg));
+}
+
+static ssize_t cpu_rt_period_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct user_struct *up = container_of(kobj, struct user_struct, kobj);
+ unsigned long rt_period;
+ int rc;
+
+ sscanf(buf, "%lu", &rt_period);
+
+ rc = sched_group_set_rt_period(up->tg, rt_period);
+
+ return (rc ? rc : size);
+}
+
+static struct kobj_attribute cpu_rt_period_attr =
+ __ATTR(cpu_rt_period, 0644, cpu_rt_period_show, cpu_rt_period_store);
#endif
/* default attributes per uid directory */
#endif
#ifdef CONFIG_RT_GROUP_SCHED
&cpu_rt_runtime_attr.attr,
+ &cpu_rt_period_attr.attr,
#endif
NULL
};
config CHECK_SIGNATURE
bool
+config HAVE_LMB
+ boolean
+
endmenu
If unsure, say N.
+config DEBUG_WRITECOUNT
+ bool "Debug filesystem writers count"
+ depends on DEBUG_KERNEL
+ help
+ Enable this to catch wrong use of the writers count in struct
+ vfsmount. This will increase the size of each file struct by
+ 32 bits.
+
+ If unsure, say N.
+
config DEBUG_LIST
bool "Debug linked list manipulation"
depends on DEBUG_KERNEL
lib-$(CONFIG_GENERIC_BUG) += bug.o
+obj-$(CONFIG_HAVE_LMB) += lmb.o
+
hostprogs-y := gen_crc32table
clean-files := crc32table.h
}
EXPORT_SYMBOL(bitmap_scnprintf);
+/**
+ * bitmap_scnprintf_len - return buffer length needed to convert
+ * bitmap to an ASCII hex string.
+ * @len: number of bits to be converted
+ */
+int bitmap_scnprintf_len(unsigned int len)
+{
+ /* we need 9 chars per word for 32 bit words (8 hexdigits + sep/null) */
+ int bitslen = ALIGN(len, CHUNKSZ);
+ int wordlen = CHUNKSZ / 4;
+ int buflen = (bitslen / wordlen) * (wordlen + 1) * sizeof(char);
+
+ return buflen;
+}
+EXPORT_SYMBOL(bitmap_scnprintf_len);
+
/**
* __bitmap_parse - convert an ASCII hex string into a bitmap.
* @buf: pointer to buffer containing string.
#include <linux/smp_lock.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
/*
* The 'big kernel semaphore'
return error;
}
-static inline struct kobject *to_kobj(struct list_head *entry)
-{
- return container_of(entry, struct kobject, entry);
-}
-
static int get_kobj_path_length(struct kobject *kobj)
{
int length = 1;
*/
void kobject_put(struct kobject *kobj)
{
- if (kobj)
+ if (kobj) {
+ if (!kobj->state_initialized) {
+ printk(KERN_WARNING "kobject: '%s' (%p): is not "
+ "initialized, yet kobject_put() is being "
+ "called.\n", kobject_name(kobj), kobj);
+ WARN_ON(1);
+ }
kref_put(&kobj->kref, kobject_release);
+ }
}
static void dynamic_kobj_release(struct kobject *kobj)
*/
struct kobject *kset_find_obj(struct kset *kset, const char *name)
{
- struct list_head *entry;
+ struct kobject *k;
struct kobject *ret = NULL;
spin_lock(&kset->list_lock);
- list_for_each(entry, &kset->list) {
- struct kobject *k = to_kobj(entry);
+ list_for_each_entry(k, &kset->list, entry) {
if (kobject_name(k) && !strcmp(kobject_name(k), name)) {
ret = kobject_get(k);
break;
--- /dev/null
+/*
+ * Procedures for maintaining information about logical memory blocks.
+ *
+ * Peter Bergner, IBM Corp. June 2001.
+ * Copyright (C) 2001 Peter Bergner.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/lmb.h>
+
+#define LMB_ALLOC_ANYWHERE 0
+
+struct lmb lmb;
+
+void lmb_dump_all(void)
+{
+#ifdef DEBUG
+ unsigned long i;
+
+ pr_debug("lmb_dump_all:\n");
+ pr_debug(" memory.cnt = 0x%lx\n", lmb.memory.cnt);
+ pr_debug(" memory.size = 0x%llx\n",
+ (unsigned long long)lmb.memory.size);
+ for (i=0; i < lmb.memory.cnt ;i++) {
+ pr_debug(" memory.region[0x%x].base = 0x%llx\n",
+ i, (unsigned long long)lmb.memory.region[i].base);
+ pr_debug(" .size = 0x%llx\n",
+ (unsigned long long)lmb.memory.region[i].size);
+ }
+
+ pr_debug(" reserved.cnt = 0x%lx\n", lmb.reserved.cnt);
+ pr_debug(" reserved.size = 0x%lx\n", lmb.reserved.size);
+ for (i=0; i < lmb.reserved.cnt ;i++) {
+ pr_debug(" reserved.region[0x%x].base = 0x%llx\n",
+ i, (unsigned long long)lmb.reserved.region[i].base);
+ pr_debug(" .size = 0x%llx\n",
+ (unsigned long long)lmb.reserved.region[i].size);
+ }
+#endif /* DEBUG */
+}
+
+static unsigned long __init lmb_addrs_overlap(u64 base1, u64 size1,
+ u64 base2, u64 size2)
+{
+ return ((base1 < (base2 + size2)) && (base2 < (base1 + size1)));
+}
+
+static long __init lmb_addrs_adjacent(u64 base1, u64 size1,
+ u64 base2, u64 size2)
+{
+ if (base2 == base1 + size1)
+ return 1;
+ else if (base1 == base2 + size2)
+ return -1;
+
+ return 0;
+}
+
+static long __init lmb_regions_adjacent(struct lmb_region *rgn,
+ unsigned long r1, unsigned long r2)
+{
+ u64 base1 = rgn->region[r1].base;
+ u64 size1 = rgn->region[r1].size;
+ u64 base2 = rgn->region[r2].base;
+ u64 size2 = rgn->region[r2].size;
+
+ return lmb_addrs_adjacent(base1, size1, base2, size2);
+}
+
+static void __init lmb_remove_region(struct lmb_region *rgn, unsigned long r)
+{
+ unsigned long i;
+
+ for (i = r; i < rgn->cnt - 1; i++) {
+ rgn->region[i].base = rgn->region[i + 1].base;
+ rgn->region[i].size = rgn->region[i + 1].size;
+ }
+ rgn->cnt--;
+}
+
+/* Assumption: base addr of region 1 < base addr of region 2 */
+static void __init lmb_coalesce_regions(struct lmb_region *rgn,
+ unsigned long r1, unsigned long r2)
+{
+ rgn->region[r1].size += rgn->region[r2].size;
+ lmb_remove_region(rgn, r2);
+}
+
+void __init lmb_init(void)
+{
+ /* Create a dummy zero size LMB which will get coalesced away later.
+ * This simplifies the lmb_add() code below...
+ */
+ lmb.memory.region[0].base = 0;
+ lmb.memory.region[0].size = 0;
+ lmb.memory.cnt = 1;
+
+ /* Ditto. */
+ lmb.reserved.region[0].base = 0;
+ lmb.reserved.region[0].size = 0;
+ lmb.reserved.cnt = 1;
+}
+
+void __init lmb_analyze(void)
+{
+ int i;
+
+ lmb.memory.size = 0;
+
+ for (i = 0; i < lmb.memory.cnt; i++)
+ lmb.memory.size += lmb.memory.region[i].size;
+}
+
+static long __init lmb_add_region(struct lmb_region *rgn, u64 base, u64 size)
+{
+ unsigned long coalesced = 0;
+ long adjacent, i;
+
+ if ((rgn->cnt == 1) && (rgn->region[0].size == 0)) {
+ rgn->region[0].base = base;
+ rgn->region[0].size = size;
+ return 0;
+ }
+
+ /* First try and coalesce this LMB with another. */
+ for (i = 0; i < rgn->cnt; i++) {
+ u64 rgnbase = rgn->region[i].base;
+ u64 rgnsize = rgn->region[i].size;
+
+ if ((rgnbase == base) && (rgnsize == size))
+ /* Already have this region, so we're done */
+ return 0;
+
+ adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize);
+ if (adjacent > 0) {
+ rgn->region[i].base -= size;
+ rgn->region[i].size += size;
+ coalesced++;
+ break;
+ } else if (adjacent < 0) {
+ rgn->region[i].size += size;
+ coalesced++;
+ break;
+ }
+ }
+
+ if ((i < rgn->cnt - 1) && lmb_regions_adjacent(rgn, i, i+1)) {
+ lmb_coalesce_regions(rgn, i, i+1);
+ coalesced++;
+ }
+
+ if (coalesced)
+ return coalesced;
+ if (rgn->cnt >= MAX_LMB_REGIONS)
+ return -1;
+
+ /* Couldn't coalesce the LMB, so add it to the sorted table. */
+ for (i = rgn->cnt - 1; i >= 0; i--) {
+ if (base < rgn->region[i].base) {
+ rgn->region[i+1].base = rgn->region[i].base;
+ rgn->region[i+1].size = rgn->region[i].size;
+ } else {
+ rgn->region[i+1].base = base;
+ rgn->region[i+1].size = size;
+ break;
+ }
+ }
+
+ if (base < rgn->region[0].base) {
+ rgn->region[0].base = base;
+ rgn->region[0].size = size;
+ }
+ rgn->cnt++;
+
+ return 0;
+}
+
+long __init lmb_add(u64 base, u64 size)
+{
+ struct lmb_region *_rgn = &lmb.memory;
+
+ /* On pSeries LPAR systems, the first LMB is our RMO region. */
+ if (base == 0)
+ lmb.rmo_size = size;
+
+ return lmb_add_region(_rgn, base, size);
+
+}
+
+long __init lmb_reserve(u64 base, u64 size)
+{
+ struct lmb_region *_rgn = &lmb.reserved;
+
+ BUG_ON(0 == size);
+
+ return lmb_add_region(_rgn, base, size);
+}
+
+long __init lmb_overlaps_region(struct lmb_region *rgn, u64 base, u64 size)
+{
+ unsigned long i;
+
+ for (i = 0; i < rgn->cnt; i++) {
+ u64 rgnbase = rgn->region[i].base;
+ u64 rgnsize = rgn->region[i].size;
+ if (lmb_addrs_overlap(base, size, rgnbase, rgnsize))
+ break;
+ }
+
+ return (i < rgn->cnt) ? i : -1;
+}
+
+static u64 lmb_align_down(u64 addr, u64 size)
+{
+ return addr & ~(size - 1);
+}
+
+static u64 lmb_align_up(u64 addr, u64 size)
+{
+ return (addr + (size - 1)) & ~(size - 1);
+}
+
+static u64 __init lmb_alloc_nid_unreserved(u64 start, u64 end,
+ u64 size, u64 align)
+{
+ u64 base, res_base;
+ long j;
+
+ base = lmb_align_down((end - size), align);
+ while (start <= base) {
+ j = lmb_overlaps_region(&lmb.reserved, base, size);
+ if (j < 0) {
+ /* this area isn't reserved, take it */
+ if (lmb_add_region(&lmb.reserved, base,
+ lmb_align_up(size, align)) < 0)
+ base = ~(u64)0;
+ return base;
+ }
+ res_base = lmb.reserved.region[j].base;
+ if (res_base < size)
+ break;
+ base = lmb_align_down(res_base - size, align);
+ }
+
+ return ~(u64)0;
+}
+
+static u64 __init lmb_alloc_nid_region(struct lmb_property *mp,
+ u64 (*nid_range)(u64, u64, int *),
+ u64 size, u64 align, int nid)
+{
+ u64 start, end;
+
+ start = mp->base;
+ end = start + mp->size;
+
+ start = lmb_align_up(start, align);
+ while (start < end) {
+ u64 this_end;
+ int this_nid;
+
+ this_end = nid_range(start, end, &this_nid);
+ if (this_nid == nid) {
+ u64 ret = lmb_alloc_nid_unreserved(start, this_end,
+ size, align);
+ if (ret != ~(u64)0)
+ return ret;
+ }
+ start = this_end;
+ }
+
+ return ~(u64)0;
+}
+
+u64 __init lmb_alloc_nid(u64 size, u64 align, int nid,
+ u64 (*nid_range)(u64 start, u64 end, int *nid))
+{
+ struct lmb_region *mem = &lmb.memory;
+ int i;
+
+ for (i = 0; i < mem->cnt; i++) {
+ u64 ret = lmb_alloc_nid_region(&mem->region[i],
+ nid_range,
+ size, align, nid);
+ if (ret != ~(u64)0)
+ return ret;
+ }
+
+ return lmb_alloc(size, align);
+}
+
+u64 __init lmb_alloc(u64 size, u64 align)
+{
+ return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE);
+}
+
+u64 __init lmb_alloc_base(u64 size, u64 align, u64 max_addr)
+{
+ u64 alloc;
+
+ alloc = __lmb_alloc_base(size, align, max_addr);
+
+ if (alloc == 0)
+ panic("ERROR: Failed to allocate 0x%llx bytes below 0x%llx.\n",
+ (unsigned long long) size, (unsigned long long) max_addr);
+
+ return alloc;
+}
+
+u64 __init __lmb_alloc_base(u64 size, u64 align, u64 max_addr)
+{
+ long i, j;
+ u64 base = 0;
+ u64 res_base;
+
+ BUG_ON(0 == size);
+
+ /* On some platforms, make sure we allocate lowmem */
+ /* Note that LMB_REAL_LIMIT may be LMB_ALLOC_ANYWHERE */
+ if (max_addr == LMB_ALLOC_ANYWHERE)
+ max_addr = LMB_REAL_LIMIT;
+
+ for (i = lmb.memory.cnt - 1; i >= 0; i--) {
+ u64 lmbbase = lmb.memory.region[i].base;
+ u64 lmbsize = lmb.memory.region[i].size;
+
+ if (lmbsize < size)
+ continue;
+ if (max_addr == LMB_ALLOC_ANYWHERE)
+ base = lmb_align_down(lmbbase + lmbsize - size, align);
+ else if (lmbbase < max_addr) {
+ base = min(lmbbase + lmbsize, max_addr);
+ base = lmb_align_down(base - size, align);
+ } else
+ continue;
+
+ while (base && lmbbase <= base) {
+ j = lmb_overlaps_region(&lmb.reserved, base, size);
+ if (j < 0) {
+ /* this area isn't reserved, take it */
+ if (lmb_add_region(&lmb.reserved, base,
+ size) < 0)
+ return 0;
+ return base;
+ }
+ res_base = lmb.reserved.region[j].base;
+ if (res_base < size)
+ break;
+ base = lmb_align_down(res_base - size, align);
+ }
+ }
+ return 0;
+}
+
+/* You must call lmb_analyze() before this. */
+u64 __init lmb_phys_mem_size(void)
+{
+ return lmb.memory.size;
+}
+
+u64 __init lmb_end_of_DRAM(void)
+{
+ int idx = lmb.memory.cnt - 1;
+
+ return (lmb.memory.region[idx].base + lmb.memory.region[idx].size);
+}
+
+/* You must call lmb_analyze() after this. */
+void __init lmb_enforce_memory_limit(u64 memory_limit)
+{
+ unsigned long i;
+ u64 limit;
+ struct lmb_property *p;
+
+ if (!memory_limit)
+ return;
+
+ /* Truncate the lmb regions to satisfy the memory limit. */
+ limit = memory_limit;
+ for (i = 0; i < lmb.memory.cnt; i++) {
+ if (limit > lmb.memory.region[i].size) {
+ limit -= lmb.memory.region[i].size;
+ continue;
+ }
+
+ lmb.memory.region[i].size = limit;
+ lmb.memory.cnt = i + 1;
+ break;
+ }
+
+ if (lmb.memory.region[0].size < lmb.rmo_size)
+ lmb.rmo_size = lmb.memory.region[0].size;
+
+ /* And truncate any reserves above the limit also. */
+ for (i = 0; i < lmb.reserved.cnt; i++) {
+ p = &lmb.reserved.region[i];
+
+ if (p->base > memory_limit)
+ p->size = 0;
+ else if ((p->base + p->size) > memory_limit)
+ p->size = memory_limit - p->base;
+
+ if (p->size == 0) {
+ lmb_remove_region(&lmb.reserved, i);
+ i--;
+ }
+ }
+}
+
+int __init lmb_is_reserved(u64 addr)
+{
+ int i;
+
+ for (i = 0; i < lmb.reserved.cnt; i++) {
+ u64 upper = lmb.reserved.region[i].base +
+ lmb.reserved.region[i].size - 1;
+ if ((addr >= lmb.reserved.region[i].base) && (addr <= upper))
+ return 1;
+ }
+ return 0;
+}
#include <linux/rslib.h>
#include <linux/slab.h>
#include <linux/mutex.h>
-#include <asm/semaphore.h>
/* This list holds all currently allocated rs control structures */
static LIST_HEAD (rslist);
int __percpu_populate_mask(void *__pdata, size_t size, gfp_t gfp,
cpumask_t *mask)
{
- cpumask_t populated = CPU_MASK_NONE;
+ cpumask_t populated;
int cpu;
+ cpus_clear(populated);
for_each_cpu_mask(cpu, *mask)
if (unlikely(!percpu_populate(__pdata, size, gfp, cpu))) {
__percpu_depopulate_mask(__pdata, &populated);
/*
* This doesn't need a lock to do pfn_to_page().
* The section can't be removed here because of the
- * memory_block->state_sem.
+ * memory_block->state_mutex.
*/
zone = page_zone(pfn_to_page(pfn));
pgdat_resize_lock(zone->zone_pgdat, &flags);
int n, val;
int min_val = INT_MAX;
int best_node = -1;
+ node_to_cpumask_ptr(tmp, 0);
/* Use the local node if we haven't already */
if (!node_isset(node, *used_node_mask)) {
}
for_each_node_state(n, N_HIGH_MEMORY) {
- cpumask_t tmp;
/* Don't want a node to appear more than once */
if (node_isset(n, *used_node_mask))
val += (n < node);
/* Give preference to headless and unused nodes */
- tmp = node_to_cpumask(n);
- if (!cpus_empty(tmp))
+ node_to_cpumask_ptr_next(tmp, n);
+ if (!cpus_empty(*tmp))
val += PENALTY_FOR_NODE_WITH_CPUS;
/* Slight preference for less loaded node */
#include <linux/gfp.h>
#include <linux/init.h>
#include <linux/module.h>
-#include <linux/fs.h> // Needed by writeback.h
-#include <linux/writeback.h> // Prototypes pdflush_operation()
+#include <linux/fs.h> /* Needed by writeback.h */
+#include <linux/writeback.h> /* Prototypes pdflush_operation() */
#include <linux/kthread.h>
#include <linux/cpuset.h>
#include <linux/freezer.h>
* This is needed as pdflush's are dynamically created and destroyed.
* The boottime pdflush's are easily placed w/o these 2 lines.
*/
- cpus_allowed = cpuset_cpus_allowed(current);
- set_cpus_allowed(current, cpus_allowed);
+ cpuset_cpus_allowed(current, &cpus_allowed);
+ set_cpus_allowed_ptr(current, &cpus_allowed);
return __pdflush(&my_work);
}
struct kmem_cache *cachep;
struct kmem_list3 *l3 = NULL;
int node = cpu_to_node(cpu);
+ node_to_cpumask_ptr(mask, node);
list_for_each_entry(cachep, &cache_chain, next) {
struct array_cache *nc;
struct array_cache *shared;
struct array_cache **alien;
- cpumask_t mask;
- mask = node_to_cpumask(node);
/* cpu is dead; no one can alloc from it. */
nc = cachep->array[cpu];
cachep->array[cpu] = NULL;
if (nc)
free_block(cachep, nc->entry, nc->avail, node);
- if (!cpus_empty(mask)) {
+ if (!cpus_empty(*mask)) {
spin_unlock_irq(&l3->list_lock);
goto free_array_cache;
}
struct reclaim_state reclaim_state = {
.reclaimed_slab = 0,
};
- cpumask_t cpumask;
+ node_to_cpumask_ptr(cpumask, pgdat->node_id);
- cpumask = node_to_cpumask(pgdat->node_id);
- if (!cpus_empty(cpumask))
- set_cpus_allowed(tsk, cpumask);
+ if (!cpus_empty(*cpumask))
+ set_cpus_allowed_ptr(tsk, cpumask);
current->reclaim_state = &reclaim_state;
/*
static int __devinit cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
- pg_data_t *pgdat;
- cpumask_t mask;
int nid;
if (action == CPU_ONLINE || action == CPU_ONLINE_FROZEN) {
for_each_node_state(nid, N_HIGH_MEMORY) {
- pgdat = NODE_DATA(nid);
- mask = node_to_cpumask(pgdat->node_id);
- if (any_online_cpu(mask) != NR_CPUS)
+ pg_data_t *pgdat = NODE_DATA(nid);
+ node_to_cpumask_ptr(mask, pgdat->node_id);
+
+ if (any_online_cpu(*mask) < nr_cpu_ids)
/* One of our CPUs online: restore mask */
- set_cpus_allowed(pgdat->kswapd, mask);
+ set_cpus_allowed_ptr(pgdat->kswapd, mask);
}
}
return NOTIFY_OK;
#include <linux/mutex.h>
#include <net/flow.h>
#include <asm/atomic.h>
-#include <asm/semaphore.h>
#include <linux/security.h>
struct flow_cache_entry {
* Options without arguments
*/
-#ifdef SO_DONTLINGER /* Compatibility item... */
- if (optname == SO_DONTLINGER) {
- lock_sock(sk);
- sock_reset_flag(sk, SOCK_LINGER);
- release_sock(sk);
- return 0;
- }
-#endif
-
if (optname == SO_BINDTODEVICE)
return sock_bindtodevice(sk, optval, optlen);
* @family: protocol family
* @priority: for allocation (%GFP_KERNEL, %GFP_ATOMIC, etc)
* @prot: struct proto associated with this new sock instance
- * @zero_it: if we should zero the newly allocated sock
*/
struct sock *sk_alloc(struct net *net, int family, gfp_t priority,
struct proto *prot)
#include <net/xfrm.h>
#include <asm/ioctls.h>
-#include <asm/semaphore.h>
#include <linux/spinlock.h>
#include <linux/timer.h>
#include <linux/delay.h>
* - Adaptive compression.
*/
#include <linux/module.h>
-#include <asm/semaphore.h>
#include <linux/crypto.h>
#include <linux/err.h>
#include <linux/pfkeyv2.h>
#include <net/ip.h>
#include <net/xfrm.h>
#include <net/ipcomp.h>
-#include <asm/semaphore.h>
#include <linux/crypto.h>
#include <linux/err.h>
#include <linux/pfkeyv2.h>
svc_pool_map_set_cpumask(unsigned int pidx, cpumask_t *oldmask)
{
struct svc_pool_map *m = &svc_pool_map;
- unsigned int node; /* or cpu */
/*
* The caller checks for sv_nrpools > 1, which
default:
return 0;
case SVC_POOL_PERCPU:
- node = m->pool_to[pidx];
+ {
+ unsigned int cpu = m->pool_to[pidx];
+
*oldmask = current->cpus_allowed;
- set_cpus_allowed(current, cpumask_of_cpu(node));
+ set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
return 1;
+ }
case SVC_POOL_PERNODE:
- node = m->pool_to[pidx];
+ {
+ unsigned int node = m->pool_to[pidx];
+ node_to_cpumask_ptr(nodecpumask, node);
+
*oldmask = current->cpus_allowed;
- set_cpus_allowed(current, node_to_cpumask(node));
+ set_cpus_allowed_ptr(current, nodecpumask);
return 1;
}
+ }
}
/*
*/
mode = S_IFSOCK |
(SOCK_INODE(sock)->i_mode & ~current->fs->umask);
+ err = mnt_want_write(nd.path.mnt);
+ if (err)
+ goto out_mknod_dput;
err = vfs_mknod(nd.path.dentry->d_inode, dentry, mode, 0);
+ mnt_drop_write(nd.path.mnt);
if (err)
goto out_mknod_dput;
mutex_unlock(&nd.path.dentry->d_inode->i_mutex);
#include <linux/init.h>
#include <linux/device.h>
#include <linux/string.h>
-
-#include "linux/firmware.h"
+#include <linux/firmware.h>
static struct device ghost_device = {
.bus_id = "ghost0",
static void sample_probe_default(void)
{
/* uses the default method to get the firmware */
- const struct firmware *fw_entry;
- printk(KERN_INFO "firmware_sample_driver: a ghost device got inserted :)\n");
+ const struct firmware *fw_entry;
+ int retval;
+
+ printk(KERN_INFO "firmware_sample_driver: "
+ "a ghost device got inserted :)\n");
- if(request_firmware(&fw_entry, "sample_driver_fw", &ghost_device)!=0)
- {
+ retval = request_firmware(&fw_entry, "sample_driver_fw", &ghost_device);
+ if (retval) {
printk(KERN_ERR
"firmware_sample_driver: Firmware not available\n");
return;
}
-
+
sample_firmware_load(fw_entry->data, fw_entry->size);
release_firmware(fw_entry);
/* finish setting up the device */
}
+
static void sample_probe_specific(void)
{
+ int retval;
/* Uses some specific hotplug support to get the firmware from
* userspace directly into the hardware, or via some sysfs file */
/* NOTE: This currently doesn't work */
- printk(KERN_INFO "firmware_sample_driver: a ghost device got inserted :)\n");
+ printk(KERN_INFO "firmware_sample_driver: "
+ "a ghost device got inserted :)\n");
- if(request_firmware(NULL, "sample_driver_fw", &ghost_device)!=0)
- {
+ retval = request_firmware(NULL, "sample_driver_fw", &ghost_device);
+ if (retval) {
printk(KERN_ERR
"firmware_sample_driver: Firmware load failed\n");
return;
}
-
+
/* request_firmware blocks until userspace finished, so at
* this point the firmware should be already in the device */
/* finish setting up the device */
}
+
static void sample_probe_async_cont(const struct firmware *fw, void *context)
{
- if(!fw){
+ if (!fw) {
printk(KERN_ERR
"firmware_sample_driver: firmware load failed\n");
return;
(char *)context);
sample_firmware_load(fw->data, fw->size);
}
+
static void sample_probe_async(void)
{
/* Let's say that I can't sleep */
int error;
- error = request_firmware_nowait (THIS_MODULE, FW_ACTION_NOHOTPLUG,
- "sample_driver_fw", &ghost_device,
- "my device pointer",
- sample_probe_async_cont);
- if(error){
- printk(KERN_ERR
- "firmware_sample_driver:"
+ error = request_firmware_nowait(THIS_MODULE, FW_ACTION_NOHOTPLUG,
+ "sample_driver_fw", &ghost_device,
+ "my device pointer",
+ sample_probe_async_cont);
+ if (error)
+ printk(KERN_ERR "firmware_sample_driver:"
" request_firmware_nowait failed\n");
- }
}
static int sample_init(void)
sample_probe_async();
return 0;
}
+
static void __exit sample_exit(void)
{
}
-module_init (sample_init);
-module_exit (sample_exit);
+module_init(sample_init);
+module_exit(sample_exit);
MODULE_LICENSE("GPL");
static inline struct class_device *to_class_dev(struct kobject *obj)
{
- return container_of(obj,struct class_device,kobj);
+ return container_of(obj, struct class_device, kobj);
}
+
static inline
struct class_device_attribute *to_class_dev_attr(struct attribute *_attr)
{
- return container_of(_attr,struct class_device_attribute,attr);
+ return container_of(_attr, struct class_device_attribute, attr);
}
-int sysfs_create_bin_file(struct kobject * kobj, struct bin_attribute * attr);
-int sysfs_remove_bin_file(struct kobject * kobj, struct bin_attribute * attr);
-
struct firmware_priv {
char fw_id[FIRMWARE_NAME_MAX];
s32 loading:2;
u32 abort:1;
};
-extern struct class firmware_class;
-
static ssize_t firmware_loading_show(struct class_device *class_dev, char *buf)
{
struct firmware_priv *fw_priv = class_get_devdata(class_dev);
return sprintf(buf, "%d\n", fw_priv->loading);
}
+
static ssize_t firmware_loading_store(struct class_device *class_dev,
const char *buf, size_t count)
{
int prev_loading = fw_priv->loading;
fw_priv->loading = simple_strtol(buf, NULL, 10);
-
- switch(fw_priv->loading){
+
+ switch (fw_priv->loading) {
case -1:
/* abort load an panic */
break;
/* setup load */
break;
case 0:
- if(prev_loading==1){
+ if (prev_loading == 1) {
/* finish load and get the device back to working
* state */
}
class_dev->class = &firmware_class,
class_set_devdata(class_dev, fw_priv);
retval = class_device_register(class_dev);
- if (retval){
+ if (retval) {
printk(KERN_ERR "%s: class_device_register failed\n",
- __FUNCTION__);
+ __func__);
goto error_free_fw_priv;
}
retval = sysfs_create_bin_file(&class_dev->kobj, &firmware_attr_data);
- if (retval){
+ if (retval) {
printk(KERN_ERR "%s: sysfs_create_bin_file failed\n",
- __FUNCTION__);
+ __func__);
goto error_unreg_class_dev;
}
retval = class_device_create_file(class_dev,
&class_device_attr_loading);
- if (retval){
+ if (retval) {
printk(KERN_ERR "%s: class_device_create_file failed\n",
- __FUNCTION__);
+ __func__);
goto error_remove_data;
}
goto out;
-
+
error_remove_data:
sysfs_remove_bin_file(&class_dev->kobj, &firmware_attr_data);
error_unreg_class_dev:
device_initialize(&my_device);
class_dev = kmalloc(sizeof(struct class_device), GFP_KERNEL);
- if(!class_dev)
+ if (!class_dev)
return -ENOMEM;
error = fw_setup_class_device(class_dev, "my_firmware_image",
&my_device);
- if(error){
+ if (error) {
kfree(class_dev);
return error;
}
- return 0;
+ return 0;
}
static void __exit firmware_sample_exit(void)
kfree(fw_priv);
kfree(class_dev);
}
+
module_init(firmware_sample_init);
module_exit(firmware_sample_exit);
-
return 1;
}
-/* looks like: "pnp:cCdD..." */
-static int do_pnp_card_entry(const char *filename,
- struct pnp_card_device_id *id, char *alias)
+/* looks like: "pnp:dD" for every device of the card */
+static void do_pnp_card_entries(void *symval, unsigned long size,
+ struct module *mod)
{
- int i;
+ const unsigned long id_size = sizeof(struct pnp_card_device_id);
+ const unsigned int count = (size / id_size)-1;
+ const struct pnp_card_device_id *cards = symval;
+ unsigned int i;
- sprintf(alias, "pnp:c%s", id->id);
- for (i = 0; i < PNP_MAX_DEVICES; i++) {
- if (! *id->devs[i].id)
- break;
- sprintf(alias + strlen(alias), "d%s", id->devs[i].id);
+ device_id_check(mod->name, "pnp", size, id_size, symval);
+
+ for (i = 0; i < count; i++) {
+ unsigned int j;
+ const struct pnp_card_device_id *card = &cards[i];
+
+ for (j = 0; j < PNP_MAX_DEVICES; j++) {
+ const char *id = (char *)card->devs[j].id;
+ int i2, j2;
+ int dup = 0;
+
+ if (!id[0])
+ break;
+
+ /* find duplicate, already added value */
+ for (i2 = 0; i2 < i && !dup; i2++) {
+ const struct pnp_card_device_id *card2 = &cards[i2];
+
+ for (j2 = 0; j2 < PNP_MAX_DEVICES; j2++) {
+ const char *id2 = (char *)card2->devs[j2].id;
+
+ if (!id2[0])
+ break;
+
+ if (!strcmp(id, id2)) {
+ dup = 1;
+ break;
+ }
+ }
+ }
+
+ /* add an individual alias for every device entry */
+ if (!dup)
+ buf_printf(&mod->dev_table_buf,
+ "MODULE_ALIAS(\"pnp:d%s*\");\n", id);
+ }
}
- return 1;
}
/* Looks like: pcmcia:mNcNfNfnNpfnNvaNvbNvcNvdN. */
sizeof(struct pnp_device_id), "pnp",
do_pnp_entry, mod);
else if (sym_is(symname, "__mod_pnp_card_device_table"))
- do_table(symval, sym->st_size,
- sizeof(struct pnp_card_device_id), "pnp_card",
- do_pnp_card_entry, mod);
+ do_pnp_card_entries(symval, sym->st_size, mod);
else if (sym_is(symname, "__mod_pcmcia_device_table"))
do_table(symval, sym->st_size,
sizeof(struct pcmcia_device_id), "pcmcia",
return 0;
}
-static int dummy_sb_mount (char *dev_name, struct nameidata *nd, char *type,
+static int dummy_sb_mount (char *dev_name, struct path *path, char *type,
unsigned long flags, void *data)
{
return 0;
}
-static int dummy_sb_check_sb (struct vfsmount *mnt, struct nameidata *nd)
+static int dummy_sb_check_sb (struct vfsmount *mnt, struct path *path)
{
return 0;
}
}
-static void dummy_sb_post_addmount (struct vfsmount *mnt, struct nameidata *nd)
+static void dummy_sb_post_addmount (struct vfsmount *mnt, struct path *path)
{
return;
}
-static int dummy_sb_pivotroot (struct nameidata *old_nd, struct nameidata *new_nd)
+static int dummy_sb_pivotroot (struct path *old_path, struct path *new_path)
{
return 0;
}
-static void dummy_sb_post_pivotroot (struct nameidata *old_nd, struct nameidata *new_nd)
+static void dummy_sb_post_pivotroot (struct path *old_path, struct path *new_path)
{
return;
}
return security_ops->sb_statfs(dentry);
}
-int security_sb_mount(char *dev_name, struct nameidata *nd,
+int security_sb_mount(char *dev_name, struct path *path,
char *type, unsigned long flags, void *data)
{
- return security_ops->sb_mount(dev_name, nd, type, flags, data);
+ return security_ops->sb_mount(dev_name, path, type, flags, data);
}
-int security_sb_check_sb(struct vfsmount *mnt, struct nameidata *nd)
+int security_sb_check_sb(struct vfsmount *mnt, struct path *path)
{
- return security_ops->sb_check_sb(mnt, nd);
+ return security_ops->sb_check_sb(mnt, path);
}
int security_sb_umount(struct vfsmount *mnt, int flags)
security_ops->sb_post_remount(mnt, flags, data);
}
-void security_sb_post_addmount(struct vfsmount *mnt, struct nameidata *mountpoint_nd)
+void security_sb_post_addmount(struct vfsmount *mnt, struct path *mountpoint)
{
- security_ops->sb_post_addmount(mnt, mountpoint_nd);
+ security_ops->sb_post_addmount(mnt, mountpoint);
}
-int security_sb_pivotroot(struct nameidata *old_nd, struct nameidata *new_nd)
+int security_sb_pivotroot(struct path *old_path, struct path *new_path)
{
- return security_ops->sb_pivotroot(old_nd, new_nd);
+ return security_ops->sb_pivotroot(old_path, new_path);
}
-void security_sb_post_pivotroot(struct nameidata *old_nd, struct nameidata *new_nd)
+void security_sb_post_pivotroot(struct path *old_path, struct path *new_path)
{
- security_ops->sb_post_pivotroot(old_nd, new_nd);
+ security_ops->sb_post_pivotroot(old_path, new_path);
}
int security_sb_get_mnt_opts(const struct super_block *sb,
* Implementation of the kernel access vector cache (AVC).
*
* Authors: Stephen Smalley, <sds@epoch.ncsc.mil>
- * James Morris <jmorris@redhat.com>
+ * James Morris <jmorris@redhat.com>
*
* Update: KaiGai, Kohei <kaigai@ak.jp.nec.com>
- * Replaced the avc_lock spinlock by RCU.
+ * Replaced the avc_lock spinlock by RCU.
*
* Copyright (C) 2003 Red Hat, Inc., James Morris <jmorris@redhat.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2,
- * as published by the Free Software Foundation.
+ * as published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/stddef.h>
#undef S_
};
-#define TB_(s) static const char * s [] = {
+#define TB_(s) static const char *s[] = {
#define TE_(s) };
#define S_(s) s,
#include "common_perm_to_string.h"
#define AVC_CACHE_RECLAIM 16
#ifdef CONFIG_SECURITY_SELINUX_AVC_STATS
-#define avc_cache_stats_incr(field) \
+#define avc_cache_stats_incr(field) \
do { \
per_cpu(avc_cache_stats, get_cpu()).field++; \
put_cpu(); \
struct avc_node {
struct avc_entry ae;
struct list_head list;
- struct rcu_head rhead;
+ struct rcu_head rhead;
};
struct avc_cache {
struct avc_callback_node {
int (*callback) (u32 event, u32 ssid, u32 tsid,
- u16 tclass, u32 perms,
- u32 *out_retained);
+ u16 tclass, u32 perms,
+ u32 *out_retained);
u32 events;
u32 ssid;
u32 tsid;
char *scontext;
u32 scontext_len;
- rc = security_sid_to_context(ssid, &scontext, &scontext_len);
+ rc = security_sid_to_context(ssid, &scontext, &scontext_len);
if (rc)
audit_log_format(ab, "ssid=%d", ssid);
else {
int hvalue, try, ecx;
unsigned long flags;
- for (try = 0, ecx = 0; try < AVC_CACHE_SLOTS; try++ ) {
+ for (try = 0, ecx = 0; try < AVC_CACHE_SLOTS; try++) {
hvalue = atomic_inc_return(&avc_cache.lru_hint) & (AVC_CACHE_SLOTS - 1);
if (!spin_trylock_irqsave(&avc_cache.slots_lock[hvalue], flags))
continue;
+ rcu_read_lock();
list_for_each_entry(node, &avc_cache.slots[hvalue], list) {
if (atomic_dec_and_test(&node->ae.used)) {
/* Recently Unused */
avc_cache_stats_incr(reclaims);
ecx++;
if (ecx >= AVC_CACHE_RECLAIM) {
+ rcu_read_unlock();
spin_unlock_irqrestore(&avc_cache.slots_lock[hvalue], flags);
goto out;
}
}
}
+ rcu_read_unlock();
spin_unlock_irqrestore(&avc_cache.slots_lock[hvalue], flags);
}
out:
spin_lock_irqsave(¬if_lock, flag);
if (is_insert) {
if (seqno < avc_cache.latest_notif) {
- printk(KERN_WARNING "avc: seqno %d < latest_notif %d\n",
+ printk(KERN_WARNING "SELinux: avc: seqno %d < latest_notif %d\n",
seqno, avc_cache.latest_notif);
ret = -EAGAIN;
}
if (pos->ae.ssid == ssid &&
pos->ae.tsid == tsid &&
pos->ae.tclass == tclass) {
- avc_node_replace(node, pos);
+ avc_node_replace(node, pos);
goto found;
}
}
* before calling the auditing code.
*/
void avc_audit(u32 ssid, u32 tsid,
- u16 tclass, u32 requested,
- struct av_decision *avd, int result, struct avc_audit_data *a)
+ u16 tclass, u32 requested,
+ struct av_decision *avd, int result, struct avc_audit_data *a)
{
struct task_struct *tsk = current;
struct inode *inode = NULL;
return;
} else if (result) {
audited = denied = requested;
- } else {
+ } else {
audited = requested;
if (!(audited & avd->auditallow))
return;
if (!ab)
return; /* audit_panic has been called */
audit_log_format(ab, "avc: %s ", denied ? "denied" : "granted");
- avc_dump_av(ab, tclass,audited);
+ avc_dump_av(ab, tclass, audited);
audit_log_format(ab, " for ");
if (a && a->tsk)
tsk = a->tsk;
break;
}
}
-
+
switch (a->u.net.family) {
case AF_INET:
avc_print_ipv4_addr(ab, a->u.net.v4info.saddr,
* -%ENOMEM if insufficient memory exists to add the callback.
*/
int avc_add_callback(int (*callback)(u32 event, u32 ssid, u32 tsid,
- u16 tclass, u32 perms,
- u32 *out_retained),
- u32 events, u32 ssid, u32 tsid,
- u16 tclass, u32 perms)
+ u16 tclass, u32 perms,
+ u32 *out_retained),
+ u32 events, u32 ssid, u32 tsid,
+ u16 tclass, u32 perms)
{
struct avc_callback_node *c;
int rc = 0;
hvalue = avc_hash(ssid, tsid, tclass);
spin_lock_irqsave(&avc_cache.slots_lock[hvalue], flag);
- list_for_each_entry(pos, &avc_cache.slots[hvalue], list){
- if ( ssid==pos->ae.ssid &&
- tsid==pos->ae.tsid &&
- tclass==pos->ae.tclass ){
+ list_for_each_entry(pos, &avc_cache.slots[hvalue], list) {
+ if (ssid == pos->ae.ssid &&
+ tsid == pos->ae.tsid &&
+ tclass == pos->ae.tclass){
orig = pos;
break;
}
for (i = 0; i < AVC_CACHE_SLOTS; i++) {
spin_lock_irqsave(&avc_cache.slots_lock[i], flag);
+ /*
+ * With preemptable RCU, the outer spinlock does not
+ * prevent RCU grace periods from ending.
+ */
+ rcu_read_lock();
list_for_each_entry(node, &avc_cache.slots[i], list)
avc_node_delete(node);
+ rcu_read_unlock();
spin_unlock_irqrestore(&avc_cache.slots_lock[i], flag);
}
for (c = avc_callbacks; c; c = c->next) {
if (c->events & AVC_CALLBACK_RESET) {
tmprc = c->callback(AVC_CALLBACK_RESET,
- 0, 0, 0, 0, NULL);
+ 0, 0, 0, 0, NULL);
/* save the first error encountered for the return
value and continue processing the callbacks */
if (!rc)
node = avc_lookup(ssid, tsid, tclass, requested);
if (!node) {
rcu_read_unlock();
- rc = security_compute_av(ssid,tsid,tclass,requested,&entry.avd);
+ rc = security_compute_av(ssid, tsid, tclass, requested, &entry.avd);
if (rc)
goto out;
rcu_read_lock();
- node = avc_insert(ssid,tsid,tclass,&entry);
+ node = avc_insert(ssid, tsid, tclass, &entry);
}
p_ae = node ? &node->ae : &entry;
* another -errno upon other errors.
*/
int avc_has_perm(u32 ssid, u32 tsid, u16 tclass,
- u32 requested, struct avc_audit_data *auditdata)
+ u32 requested, struct avc_audit_data *auditdata)
{
struct av_decision avd;
int rc;
* This file contains the SELinux hook function implementations.
*
* Authors: Stephen Smalley, <sds@epoch.ncsc.mil>
- * Chris Vance, <cvance@nai.com>
- * Wayne Salamon, <wsalamon@nai.com>
- * James Morris <jmorris@redhat.com>
+ * Chris Vance, <cvance@nai.com>
+ * Wayne Salamon, <wsalamon@nai.com>
+ * James Morris <jmorris@redhat.com>
*
* Copyright (C) 2001,2002 Networks Associates Technology, Inc.
* Copyright (C) 2003 Red Hat, Inc., James Morris <jmorris@redhat.com>
* Copyright (C) 2004-2005 Trusted Computer Solutions, Inc.
- * <dgoeddel@trustedcs.com>
+ * <dgoeddel@trustedcs.com>
* Copyright (C) 2006, 2007 Hewlett-Packard Development Company, L.P.
- *
Paul Moore <paul.moore@hp.com>
+ * Paul Moore <paul.moore@hp.com>
* Copyright (C) 2007 Hitachi Software Engineering Co., Ltd.
- * Yuichi Nakamura <ynakam@hitachisoft.jp>
+ * Yuichi Nakamura <ynakam@hitachisoft.jp>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2,
- * as published by the Free Software Foundation.
+ * as published by the Free Software Foundation.
*/
#include <linux/init.h>
atomic_t selinux_secmark_refcount = ATOMIC_INIT(0);
#ifdef CONFIG_SECURITY_SELINUX_DEVELOP
-int selinux_enforcing = 0;
+int selinux_enforcing;
static int __init enforcing_setup(char *str)
{
- selinux_enforcing = simple_strtol(str,NULL,0);
+ selinux_enforcing = simple_strtol(str, NULL, 0);
return 1;
}
__setup("enforcing=", enforcing_setup);
#endif
/* Original (dummy) security module. */
-static struct security_operations *original_ops = NULL;
+static struct security_operations *original_ops;
/* Minimal support for a secondary security module,
just to allow the use of the dummy or capability modules.
The owlsm module can alternatively be used as a secondary
module as long as CONFIG_OWLSM_FD is not enabled. */
-static struct security_operations *secondary_ops = NULL;
+static struct security_operations *secondary_ops;
/* Lists of inode and superblock security structures initialized
before the policy was loaded. */
goto out;
}
rc = -EINVAL;
- printk(KERN_WARNING "Unable to set superblock options before "
- "the security server is initialized\n");
+ printk(KERN_WARNING "SELinux: Unable to set superblock options "
+ "before the security server is initialized\n");
goto out;
}
int set_context = (oldsbsec->flags & CONTEXT_MNT);
int set_rootcontext = (oldsbsec->flags & ROOTCONTEXT_MNT);
- /* we can't error, we can't save the info, this shouldn't get called
- * this early in the boot process. */
- BUG_ON(!ss_initialized);
+ /*
+ * if the parent was able to be mounted it clearly had no special lsm
+ * mount options. thus we can safely put this sb on the list and deal
+ * with it later
+ */
+ if (!ss_initialized) {
+ spin_lock(&sb_security_lock);
+ if (list_empty(&newsbsec->list))
+ list_add(&newsbsec->list, &superblock_security_head);
+ spin_unlock(&sb_security_lock);
+ return;
+ }
/* how can we clone if the old one wasn't set up?? */
BUG_ON(!oldsbsec->initialized);
int buflen, rc;
char *buffer, *path, *end;
- buffer = (char*)__get_free_page(GFP_KERNEL);
+ buffer = (char *)__get_free_page(GFP_KERNEL);
if (!buffer)
return -ENOMEM;
dentry = d_find_alias(inode);
}
if (!dentry) {
- printk(KERN_WARNING "%s: no dentry for dev=%s "
+ printk(KERN_WARNING "SELinux: %s: no dentry for dev=%s "
"ino=%ld\n", __func__, inode->i_sb->s_id,
inode->i_ino);
goto out_unlock;
dput(dentry);
if (rc < 0) {
if (rc != -ENODATA) {
- printk(KERN_WARNING "%s: getxattr returned "
+ printk(KERN_WARNING "SELinux: %s: getxattr returned "
"%d for dev=%s ino=%ld\n", __func__,
-rc, inode->i_sb->s_id, inode->i_ino);
kfree(context);
sbsec->def_sid,
GFP_NOFS);
if (rc) {
- printk(KERN_WARNING "%s: context_to_sid(%s) "
+ printk(KERN_WARNING "SELinux: %s: context_to_sid(%s) "
"returned %d for dev=%s ino=%ld\n",
__func__, context, -rc,
inode->i_sb->s_id, inode->i_ino);
tsec = tsk->security;
- AVC_AUDIT_DATA_INIT(&ad,CAP);
+ AVC_AUDIT_DATA_INIT(&ad, CAP);
ad.tsk = tsk;
ad.u.cap = cap;
struct inode_security_struct *isec;
struct avc_audit_data ad;
- if (unlikely (IS_PRIVATE (inode)))
+ if (unlikely(IS_PRIVATE(inode)))
return 0;
tsec = tsk->security;
{
struct inode *inode = dentry->d_inode;
struct avc_audit_data ad;
- AVC_AUDIT_DATA_INIT(&ad,FS);
+ AVC_AUDIT_DATA_INIT(&ad, FS);
ad.u.fs.path.mnt = mnt;
ad.u.fs.path.dentry = dentry;
return inode_has_perm(tsk, inode, av, &ad);
return avc_has_perm(tsec->sid, ksid, SECCLASS_KEY, KEY__CREATE, NULL);
}
-#define MAY_LINK 0
-#define MAY_UNLINK 1
-#define MAY_RMDIR 2
+#define MAY_LINK 0
+#define MAY_UNLINK 1
+#define MAY_RMDIR 2
/* Check whether a task can link, unlink, or rmdir a file/directory. */
static int may_link(struct inode *dir,
av = DIR__RMDIR;
break;
default:
- printk(KERN_WARNING "may_link: unrecognized kind %d\n", kind);
+ printk(KERN_WARNING "SELinux: %s: unrecognized kind %d\n",
+ __func__, kind);
return 0;
}
else if (S_ISDIR(mode))
av |= DIR__OPEN;
else
- printk(KERN_ERR "SELinux: WARNING: inside open_file_to_av "
- "with unknown mode:%x\n", mode);
+ printk(KERN_ERR "SELinux: WARNING: inside %s with "
+ "unknown mode:%x\n", __func__, mode);
}
return av;
}
{
int rc;
- rc = secondary_ops->ptrace(parent,child);
+ rc = secondary_ops->ptrace(parent, child);
if (rc)
return rc;
}
static int selinux_capget(struct task_struct *target, kernel_cap_t *effective,
- kernel_cap_t *inheritable, kernel_cap_t *permitted)
+ kernel_cap_t *inheritable, kernel_cap_t *permitted)
{
int error;
}
static int selinux_capset_check(struct task_struct *target, kernel_cap_t *effective,
- kernel_cap_t *inheritable, kernel_cap_t *permitted)
+ kernel_cap_t *inheritable, kernel_cap_t *permitted)
{
int error;
}
static void selinux_capset_set(struct task_struct *target, kernel_cap_t *effective,
- kernel_cap_t *inheritable, kernel_cap_t *permitted)
+ kernel_cap_t *inheritable, kernel_cap_t *permitted)
{
secondary_ops->capset_set(target, effective, inheritable, permitted);
}
if (rc)
return rc;
- return task_has_capability(tsk,cap);
+ return task_has_capability(tsk, cap);
}
static int selinux_sysctl_get_sid(ctl_table *table, u16 tclass, u32 *sid)
char *buffer, *path, *end;
rc = -ENOMEM;
- buffer = (char*)__get_free_page(GFP_KERNEL);
+ buffer = (char *)__get_free_page(GFP_KERNEL);
if (!buffer)
goto out;
/* The op values are "defined" in sysctl.c, thereby creating
* a bad coupling between this module and sysctl.c */
- if(op == 001) {
+ if (op == 001) {
error = avc_has_perm(tsec->sid, tsid,
SECCLASS_DIR, DIR__SEARCH, NULL);
} else {
if (av)
error = avc_has_perm(tsec->sid, tsid,
SECCLASS_FILE, av, NULL);
- }
+ }
return error;
}
return 0;
switch (cmds) {
- case Q_SYNC:
- case Q_QUOTAON:
- case Q_QUOTAOFF:
- case Q_SETINFO:
- case Q_SETQUOTA:
- rc = superblock_has_perm(current,
- sb,
- FILESYSTEM__QUOTAMOD, NULL);
- break;
- case Q_GETFMT:
- case Q_GETINFO:
- case Q_GETQUOTA:
- rc = superblock_has_perm(current,
- sb,
- FILESYSTEM__QUOTAGET, NULL);
- break;
- default:
- rc = 0; /* let the kernel handle invalid cmds */
- break;
+ case Q_SYNC:
+ case Q_QUOTAON:
+ case Q_QUOTAOFF:
+ case Q_SETINFO:
+ case Q_SETQUOTA:
+ rc = superblock_has_perm(current, sb, FILESYSTEM__QUOTAMOD,
+ NULL);
+ break;
+ case Q_GETFMT:
+ case Q_GETINFO:
+ case Q_GETQUOTA:
+ rc = superblock_has_perm(current, sb, FILESYSTEM__QUOTAGET,
+ NULL);
+ break;
+ default:
+ rc = 0; /* let the kernel handle invalid cmds */
+ break;
}
return rc;
}
return rc;
switch (type) {
- case 3: /* Read last kernel messages */
- case 10: /* Return size of the log buffer */
- rc = task_has_system(current, SYSTEM__SYSLOG_READ);
- break;
- case 6: /* Disable logging to console */
- case 7: /* Enable logging to console */
- case 8: /* Set level of messages printed to console */
- rc = task_has_system(current, SYSTEM__SYSLOG_CONSOLE);
- break;
- case 0: /* Close log */
- case 1: /* Open log */
- case 2: /* Read from log */
- case 4: /* Read/clear last kernel messages */
- case 5: /* Clear ring buffer */
- default:
- rc = task_has_system(current, SYSTEM__SYSLOG_MOD);
- break;
+ case 3: /* Read last kernel messages */
+ case 10: /* Return size of the log buffer */
+ rc = task_has_system(current, SYSTEM__SYSLOG_READ);
+ break;
+ case 6: /* Disable logging to console */
+ case 7: /* Enable logging to console */
+ case 8: /* Set level of messages printed to console */
+ rc = task_has_system(current, SYSTEM__SYSLOG_CONSOLE);
+ break;
+ case 0: /* Close log */
+ case 1: /* Open log */
+ case 2: /* Read from log */
+ case 4: /* Read/clear last kernel messages */
+ case 5: /* Clear ring buffer */
+ default:
+ rc = task_has_system(current, SYSTEM__SYSLOG_MOD);
+ break;
}
return rc;
}
} else {
/* Check for a default transition on this program. */
rc = security_transition_sid(tsec->sid, isec->sid,
- SECCLASS_PROCESS, &newsid);
+ SECCLASS_PROCESS, &newsid);
if (rc)
return rc;
}
if (bprm->file->f_path.mnt->mnt_flags & MNT_NOSUID)
newsid = tsec->sid;
- if (tsec->sid == newsid) {
+ if (tsec->sid == newsid) {
rc = avc_has_perm(tsec->sid, isec->sid,
SECCLASS_FILE, FILE__EXECUTE_NO_TRANS, &ad);
if (rc)
return 0;
}
-static int selinux_bprm_check_security (struct linux_binprm *bprm)
+static int selinux_bprm_check_security(struct linux_binprm *bprm)
{
return secondary_ops->bprm_check_security(bprm);
}
-static int selinux_bprm_secureexec (struct linux_binprm *bprm)
+static int selinux_bprm_secureexec(struct linux_binprm *bprm)
{
struct task_security_struct *tsec = current->security;
int atsecure = 0;
extern struct dentry *selinux_null;
/* Derived from fs/exec.c:flush_old_files. */
-static inline void flush_unauthorized_files(struct files_struct * files)
+static inline void flush_unauthorized_files(struct files_struct *files)
{
struct avc_audit_data ad;
struct file *file, *devnull = NULL;
/* Revalidate access to inherited open files. */
- AVC_AUDIT_DATA_INIT(&ad,FS);
+ AVC_AUDIT_DATA_INIT(&ad, FS);
spin_lock(&files->file_lock);
for (;;) {
if (!set)
continue;
spin_unlock(&files->file_lock);
- for ( ; set ; i++,set >>= 1) {
+ for ( ; set ; i++, set >>= 1) {
if (set & 1) {
file = fget(i);
if (!file)
for (i = 0; i < RLIM_NLIMITS; i++) {
rlim = current->signal->rlim + i;
initrlim = init_task.signal->rlim+i;
- rlim->rlim_cur = min(rlim->rlim_max,initrlim->rlim_cur);
+ rlim->rlim_cur = min(rlim->rlim_max, initrlim->rlim_cur);
}
if (current->signal->rlim[RLIMIT_CPU].rlim_cur != RLIM_INFINITY) {
/*
*to += len;
}
-static inline void take_selinux_option(char **to, char *from, int *first,
- int len)
+static inline void take_selinux_option(char **to, char *from, int *first,
+ int len)
{
int current_size = 0;
if (!*first) {
**to = '|';
*to += 1;
- }
- else
+ } else
*first = 0;
while (current_size < len) {
if (rc)
return rc;
- AVC_AUDIT_DATA_INIT(&ad,FS);
+ AVC_AUDIT_DATA_INIT(&ad, FS);
ad.u.fs.path.dentry = sb->s_root;
return superblock_has_perm(current, sb, FILESYSTEM__MOUNT, &ad);
}
{
struct avc_audit_data ad;
- AVC_AUDIT_DATA_INIT(&ad,FS);
+ AVC_AUDIT_DATA_INIT(&ad, FS);
ad.u.fs.path.dentry = dentry->d_sb->s_root;
return superblock_has_perm(current, dentry->d_sb, FILESYSTEM__GETATTR, &ad);
}
-static int selinux_mount(char * dev_name,
- struct nameidata *nd,
- char * type,
- unsigned long flags,
- void * data)
+static int selinux_mount(char *dev_name,
+ struct path *path,
+ char *type,
+ unsigned long flags,
+ void *data)
{
int rc;
- rc = secondary_ops->sb_mount(dev_name, nd, type, flags, data);
+ rc = secondary_ops->sb_mount(dev_name, path, type, flags, data);
if (rc)
return rc;
if (flags & MS_REMOUNT)
- return superblock_has_perm(current, nd->path.mnt->mnt_sb,
- FILESYSTEM__REMOUNT, NULL);
+ return superblock_has_perm(current, path->mnt->mnt_sb,
+ FILESYSTEM__REMOUNT, NULL);
else
- return dentry_has_perm(current, nd->path.mnt, nd->path.dentry,
- FILE__MOUNTON);
+ return dentry_has_perm(current, path->mnt, path->dentry,
+ FILE__MOUNTON);
}
static int selinux_umount(struct vfsmount *mnt, int flags)
if (rc)
return rc;
- return superblock_has_perm(current,mnt->mnt_sb,
- FILESYSTEM__UNMOUNT,NULL);
+ return superblock_has_perm(current, mnt->mnt_sb,
+ FILESYSTEM__UNMOUNT, NULL);
}
/* inode security operations */
{
int rc;
- rc = secondary_ops->inode_link(old_dentry,dir,new_dentry);
+ rc = secondary_ops->inode_link(old_dentry, dir, new_dentry);
if (rc)
return rc;
return may_link(dir, old_dentry, MAY_LINK);
}
static int selinux_inode_rename(struct inode *old_inode, struct dentry *old_dentry,
- struct inode *new_inode, struct dentry *new_dentry)
+ struct inode *new_inode, struct dentry *new_dentry)
{
return may_rename(old_inode, old_dentry, new_inode, new_dentry);
}
{
int rc;
- rc = secondary_ops->inode_follow_link(dentry,nameidata);
+ rc = secondary_ops->inode_follow_link(dentry, nameidata);
if (rc)
return rc;
return dentry_has_perm(current, NULL, dentry, FILE__READ);
if (!is_owner_or_cap(inode))
return -EPERM;
- AVC_AUDIT_DATA_INIT(&ad,FS);
+ AVC_AUDIT_DATA_INIT(&ad, FS);
ad.u.fs.path.dentry = dentry;
rc = avc_has_perm(tsec->sid, isec->sid, isec->sclass,
return rc;
rc = security_validate_transition(isec->sid, newsid, tsec->sid,
- isec->sclass);
+ isec->sclass);
if (rc)
return rc;
}
static void selinux_inode_post_setxattr(struct dentry *dentry, char *name,
- void *value, size_t size, int flags)
+ void *value, size_t size, int flags)
{
struct inode *inode = dentry->d_inode;
struct inode_security_struct *isec = inode->i_security;
return;
}
-static int selinux_inode_getxattr (struct dentry *dentry, char *name)
+static int selinux_inode_getxattr(struct dentry *dentry, char *name)
{
return dentry_has_perm(current, NULL, dentry, FILE__GETATTR);
}
-static int selinux_inode_listxattr (struct dentry *dentry)
+static int selinux_inode_listxattr(struct dentry *dentry)
{
return dentry_has_perm(current, NULL, dentry, FILE__GETATTR);
}
-static int selinux_inode_removexattr (struct dentry *dentry, char *name)
+static int selinux_inode_removexattr(struct dentry *dentry, char *name)
{
if (strcmp(name, XATTR_NAME_SELINUX))
return selinux_inode_setotherxattr(dentry, name);
}
static int selinux_inode_setsecurity(struct inode *inode, const char *name,
- const void *value, size_t size, int flags)
+ const void *value, size_t size, int flags)
{
struct inode_security_struct *isec = inode->i_security;
u32 newsid;
if (!value || !size)
return -EACCES;
- rc = security_context_to_sid((void*)value, size, &newsid);
+ rc = security_context_to_sid((void *)value, size, &newsid);
if (rc)
return rc;
int error = 0;
switch (cmd) {
- case FIONREAD:
- /* fall through */
- case FIBMAP:
- /* fall through */
- case FIGETBSZ:
- /* fall through */
- case EXT2_IOC_GETFLAGS:
- /* fall through */
- case EXT2_IOC_GETVERSION:
- error = file_has_perm(current, file, FILE__GETATTR);
- break;
-
- case EXT2_IOC_SETFLAGS:
- /* fall through */
- case EXT2_IOC_SETVERSION:
- error = file_has_perm(current, file, FILE__SETATTR);
- break;
+ case FIONREAD:
+ /* fall through */
+ case FIBMAP:
+ /* fall through */
+ case FIGETBSZ:
+ /* fall through */
+ case EXT2_IOC_GETFLAGS:
+ /* fall through */
+ case EXT2_IOC_GETVERSION:
+ error = file_has_perm(current, file, FILE__GETATTR);
+ break;
- /* sys_ioctl() checks */
- case FIONBIO:
- /* fall through */
- case FIOASYNC:
- error = file_has_perm(current, file, 0);
- break;
+ case EXT2_IOC_SETFLAGS:
+ /* fall through */
+ case EXT2_IOC_SETVERSION:
+ error = file_has_perm(current, file, FILE__SETATTR);
+ break;
- case KDSKBENT:
- case KDSKBSENT:
- error = task_has_capability(current,CAP_SYS_TTY_CONFIG);
- break;
+ /* sys_ioctl() checks */
+ case FIONBIO:
+ /* fall through */
+ case FIOASYNC:
+ error = file_has_perm(current, file, 0);
+ break;
- /* default case assumes that the command will go
- * to the file's ioctl() function.
- */
- default:
- error = file_has_perm(current, file, FILE__IOCTL);
+ case KDSKBENT:
+ case KDSKBSENT:
+ error = task_has_capability(current, CAP_SYS_TTY_CONFIG);
+ break;
+ /* default case assumes that the command will go
+ * to the file's ioctl() function.
+ */
+ default:
+ error = file_has_perm(current, file, FILE__IOCTL);
}
return error;
}
unsigned long addr, unsigned long addr_only)
{
int rc = 0;
- u32 sid = ((struct task_security_struct*)(current->security))->sid;
+ u32 sid = ((struct task_security_struct *)(current->security))->sid;
if (addr < mmap_min_addr)
rc = avc_has_perm(sid, sid, SECCLASS_MEMPROTECT,
int err = 0;
switch (cmd) {
- case F_SETFL:
- if (!file->f_path.dentry || !file->f_path.dentry->d_inode) {
- err = -EINVAL;
- break;
- }
+ case F_SETFL:
+ if (!file->f_path.dentry || !file->f_path.dentry->d_inode) {
+ err = -EINVAL;
+ break;
+ }
- if ((file->f_flags & O_APPEND) && !(arg & O_APPEND)) {
- err = file_has_perm(current, file,FILE__WRITE);
- break;
- }
- /* fall through */
- case F_SETOWN:
- case F_SETSIG:
- case F_GETFL:
- case F_GETOWN:
- case F_GETSIG:
- /* Just check FD__USE permission */
- err = file_has_perm(current, file, 0);
+ if ((file->f_flags & O_APPEND) && !(arg & O_APPEND)) {
+ err = file_has_perm(current, file, FILE__WRITE);
break;
- case F_GETLK:
- case F_SETLK:
- case F_SETLKW:
+ }
+ /* fall through */
+ case F_SETOWN:
+ case F_SETSIG:
+ case F_GETFL:
+ case F_GETOWN:
+ case F_GETSIG:
+ /* Just check FD__USE permission */
+ err = file_has_perm(current, file, 0);
+ break;
+ case F_GETLK:
+ case F_SETLK:
+ case F_SETLKW:
#if BITS_PER_LONG == 32
- case F_GETLK64:
- case F_SETLK64:
- case F_SETLKW64:
+ case F_GETLK64:
+ case F_SETLK64:
+ case F_SETLKW64:
#endif
- if (!file->f_path.dentry || !file->f_path.dentry->d_inode) {
- err = -EINVAL;
- break;
- }
- err = file_has_perm(current, file, FILE__LOCK);
+ if (!file->f_path.dentry || !file->f_path.dentry->d_inode) {
+ err = -EINVAL;
break;
+ }
+ err = file_has_perm(current, file, FILE__LOCK);
+ break;
}
return err;
static int selinux_file_send_sigiotask(struct task_struct *tsk,
struct fown_struct *fown, int signum)
{
- struct file *file;
+ struct file *file;
u32 perm;
struct task_security_struct *tsec;
struct file_security_struct *fsec;
/* struct fown_struct is never outside the context of a struct file */
- file = container_of(fown, struct file, f_owner);
+ file = container_of(fown, struct file, f_owner);
tsec = tsk->security;
fsec = file->f_security;
static int selinux_task_post_setuid(uid_t id0, uid_t id1, uid_t id2, int flags)
{
- return secondary_ops->task_post_setuid(id0,id1,id2,flags);
+ return secondary_ops->task_post_setuid(id0, id1, id2, flags);
}
static int selinux_task_setgid(gid_t id0, gid_t id1, gid_t id2, int flags)
if (rc)
return rc;
- return task_has_perm(current,p, PROCESS__SETSCHED);
+ return task_has_perm(current, p, PROCESS__SETSCHED);
}
static int selinux_task_setioprio(struct task_struct *p, int ioprio)
static void selinux_task_reparent_to_init(struct task_struct *p)
{
- struct task_security_struct *tsec;
+ struct task_security_struct *tsec;
secondary_ops->task_reparent_to_init(p);
*proto = ih->protocol;
switch (ih->protocol) {
- case IPPROTO_TCP: {
- struct tcphdr _tcph, *th;
+ case IPPROTO_TCP: {
+ struct tcphdr _tcph, *th;
- if (ntohs(ih->frag_off) & IP_OFFSET)
- break;
+ if (ntohs(ih->frag_off) & IP_OFFSET)
+ break;
offset += ihlen;
th = skb_header_pointer(skb, offset, sizeof(_tcph), &_tcph);
ad->u.net.sport = th->source;
ad->u.net.dport = th->dest;
break;
- }
-
- case IPPROTO_UDP: {
- struct udphdr _udph, *uh;
-
- if (ntohs(ih->frag_off) & IP_OFFSET)
- break;
-
+ }
+
+ case IPPROTO_UDP: {
+ struct udphdr _udph, *uh;
+
+ if (ntohs(ih->frag_off) & IP_OFFSET)
+ break;
+
offset += ihlen;
- uh = skb_header_pointer(skb, offset, sizeof(_udph), &_udph);
+ uh = skb_header_pointer(skb, offset, sizeof(_udph), &_udph);
if (uh == NULL)
- break;
+ break;
- ad->u.net.sport = uh->source;
- ad->u.net.dport = uh->dest;
- break;
- }
+ ad->u.net.sport = uh->source;
+ ad->u.net.dport = uh->dest;
+ break;
+ }
case IPPROTO_DCCP: {
struct dccp_hdr _dccph, *dh;
ad->u.net.sport = dh->dccph_sport;
ad->u.net.dport = dh->dccph_dport;
break;
- }
+ }
- default:
- break;
- }
+ default:
+ break;
+ }
out:
return ret;
}
switch (nexthdr) {
case IPPROTO_TCP: {
- struct tcphdr _tcph, *th;
+ struct tcphdr _tcph, *th;
th = skb_header_pointer(skb, offset, sizeof(_tcph), &_tcph);
if (th == NULL)
ad->u.net.sport = dh->dccph_sport;
ad->u.net.dport = dh->dccph_dport;
break;
- }
+ }
/* includes fragments */
default:
if (isec->sid == SECINITSID_KERNEL)
goto out;
- AVC_AUDIT_DATA_INIT(&ad,NET);
+ AVC_AUDIT_DATA_INIT(&ad, NET);
ad.u.net.sk = sock->sk;
err = avc_has_perm(tsec->sid, isec->sid, isec->sclass, perms, &ad);
snum, &sid);
if (err)
goto out;
- AVC_AUDIT_DATA_INIT(&ad,NET);
+ AVC_AUDIT_DATA_INIT(&ad, NET);
ad.u.net.sport = htons(snum);
ad.u.net.family = family;
err = avc_has_perm(isec->sid, sid,
goto out;
}
}
-
- switch(isec->sclass) {
+
+ switch (isec->sclass) {
case SECCLASS_TCP_SOCKET:
node_perm = TCP_SOCKET__NODE_BIND;
break;
-
+
case SECCLASS_UDP_SOCKET:
node_perm = UDP_SOCKET__NODE_BIND;
break;
node_perm = RAWIP_SOCKET__NODE_BIND;
break;
}
-
+
err = sel_netnode_sid(addrp, family, &sid);
if (err)
goto out;
-
- AVC_AUDIT_DATA_INIT(&ad,NET);
+
+ AVC_AUDIT_DATA_INIT(&ad, NET);
ad.u.net.sport = htons(snum);
ad.u.net.family = family;
ipv6_addr_copy(&ad.u.net.v6info.saddr, &addr6->sin6_addr);
err = avc_has_perm(isec->sid, sid,
- isec->sclass, node_perm, &ad);
+ isec->sclass, node_perm, &ad);
if (err)
goto out;
}
perm = (isec->sclass == SECCLASS_TCP_SOCKET) ?
TCP_SOCKET__NAME_CONNECT : DCCP_SOCKET__NAME_CONNECT;
- AVC_AUDIT_DATA_INIT(&ad,NET);
+ AVC_AUDIT_DATA_INIT(&ad, NET);
ad.u.net.dport = htons(snum);
ad.u.net.family = sk->sk_family;
err = avc_has_perm(isec->sid, sid, isec->sclass, perm, &ad);
}
static int selinux_socket_sendmsg(struct socket *sock, struct msghdr *msg,
- int size)
+ int size)
{
int rc;
return socket_has_perm(current, sock, SOCKET__GETATTR);
}
-static int selinux_socket_setsockopt(struct socket *sock,int level,int optname)
+static int selinux_socket_setsockopt(struct socket *sock, int level, int optname)
{
int err;
isec = SOCK_INODE(sock)->i_security;
other_isec = SOCK_INODE(other)->i_security;
- AVC_AUDIT_DATA_INIT(&ad,NET);
+ AVC_AUDIT_DATA_INIT(&ad, NET);
ad.u.net.sk = other->sk;
err = avc_has_perm(isec->sid, other_isec->sid,
/* connecting socket */
ssec = sock->sk->sk_security;
ssec->peer_sid = other_isec->sid;
-
+
/* server child socket */
ssec = newsk->sk_security;
ssec->peer_sid = isec->sid;
isec = SOCK_INODE(sock)->i_security;
other_isec = SOCK_INODE(other)->i_security;
- AVC_AUDIT_DATA_INIT(&ad,NET);
+ AVC_AUDIT_DATA_INIT(&ad, NET);
ad.u.net.sk = other->sk;
err = avc_has_perm(isec->sid, other_isec->sid,
err = avc_has_perm(sk_sid, if_sid, SECCLASS_NETIF, netif_perm, ad);
if (err)
return err;
-
+
err = sel_netnode_sid(addrp, family, &node_sid);
if (err)
return err;
err = -EFAULT;
kfree(scontext);
-out:
+out:
return err;
}
}
}
-static void selinux_sock_graft(struct sock* sk, struct socket *parent)
+static void selinux_sock_graft(struct sock *sk, struct socket *parent)
{
struct inode_security_struct *isec = SOCK_INODE(parent)->i_security;
struct sk_security_struct *sksec = sk->sk_security;
struct nlmsghdr *nlh;
struct socket *sock = sk->sk_socket;
struct inode_security_struct *isec = SOCK_INODE(sock)->i_security;
-
+
if (skb->len < NLMSG_SPACE(0)) {
err = -EINVAL;
goto out;
}
nlh = nlmsg_hdr(skb);
-
+
err = selinux_nlmsg_lookup(isec->sclass, nlh->nlmsg_type, &perm);
if (err) {
if (err == -EINVAL) {
return err;
err = avc_has_perm(sk_sid, if_sid, SECCLASS_NETIF, netif_perm, ad);
return err;
-
+
err = sel_netnode_sid(addrp, family, &node_sid);
if (err)
return err;
ad.u.cap = capability;
return avc_has_perm(NETLINK_CB(skb).sid, NETLINK_CB(skb).sid,
- SECCLASS_CAPABILITY, CAP_TO_MASK(capability), &ad);
+ SECCLASS_CAPABILITY, CAP_TO_MASK(capability), &ad);
}
static int ipc_alloc_security(struct task_struct *task,
isec = msq->q_perm.security;
AVC_AUDIT_DATA_INIT(&ad, IPC);
- ad.u.ipc_id = msq->q_perm.key;
+ ad.u.ipc_id = msq->q_perm.key;
rc = avc_has_perm(tsec->sid, isec->sid, SECCLASS_MSGQ,
MSGQ__CREATE, &ad);
int err;
int perms;
- switch(cmd) {
+ switch (cmd) {
case IPC_INFO:
case MSG_INFO:
/* No specific object, just general system-wide information. */
msec = msg->security;
AVC_AUDIT_DATA_INIT(&ad, IPC);
- ad.u.ipc_id = msq->q_perm.key;
+ ad.u.ipc_id = msq->q_perm.key;
rc = avc_has_perm(tsec->sid, isec->sid,
SECCLASS_MSGQ, MSGQ__READ, &ad);
isec = shp->shm_perm.security;
AVC_AUDIT_DATA_INIT(&ad, IPC);
- ad.u.ipc_id = shp->shm_perm.key;
+ ad.u.ipc_id = shp->shm_perm.key;
rc = avc_has_perm(tsec->sid, isec->sid, SECCLASS_SHM,
SHM__CREATE, &ad);
int perms;
int err;
- switch(cmd) {
+ switch (cmd) {
case IPC_INFO:
case SHM_INFO:
/* No specific object, just general system-wide information. */
isec = sma->sem_perm.security;
AVC_AUDIT_DATA_INIT(&ad, IPC);
- ad.u.ipc_id = sma->sem_perm.key;
+ ad.u.ipc_id = sma->sem_perm.key;
rc = avc_has_perm(tsec->sid, isec->sid, SECCLASS_SEM,
SEM__CREATE, &ad);
int err;
u32 perms;
- switch(cmd) {
+ switch (cmd) {
case IPC_INFO:
case SEM_INFO:
/* No specific object, just general system-wide information. */
}
/* module stacking operations */
-static int selinux_register_security (const char *name, struct security_operations *ops)
+static int selinux_register_security(const char *name, struct security_operations *ops)
{
if (secondary_ops != original_ops) {
printk(KERN_ERR "%s: There is already a secondary security "
"module registered.\n", __func__);
return -EINVAL;
- }
+ }
secondary_ops = ops;
return 0;
}
-static void selinux_d_instantiate (struct dentry *dentry, struct inode *inode)
+static void selinux_d_instantiate(struct dentry *dentry, struct inode *inode)
{
if (inode)
inode_doinit_with_dentry(inode, dentry);
}
while_each_thread(g, t);
read_unlock(&tasklist_lock);
- }
+ }
/* Check permissions for the transition. */
error = avc_has_perm(tsec->sid, sid, SECCLASS_PROCESS,
- PROCESS__DYNTRANSITION, NULL);
+ PROCESS__DYNTRANSITION, NULL);
if (error)
return error;
tsec->sid = sid;
task_unlock(p);
}
- }
- else
+ } else
return -EINVAL;
return size;
.vm_enough_memory = selinux_vm_enough_memory,
.netlink_send = selinux_netlink_send,
- .netlink_recv = selinux_netlink_recv,
+ .netlink_recv = selinux_netlink_recv,
.bprm_alloc_security = selinux_bprm_alloc_security,
.bprm_free_security = selinux_bprm_free_security,
.sb_alloc_security = selinux_sb_alloc_security,
.sb_free_security = selinux_sb_free_security,
.sb_copy_data = selinux_sb_copy_data,
- .sb_kern_mount = selinux_sb_kern_mount,
+ .sb_kern_mount = selinux_sb_kern_mount,
.sb_statfs = selinux_sb_statfs,
.sb_mount = selinux_mount,
.sb_umount = selinux_umount,
.sb_get_mnt_opts = selinux_get_mnt_opts,
.sb_set_mnt_opts = selinux_set_mnt_opts,
- .sb_clone_mnt_opts = selinux_sb_clone_mnt_opts,
+ .sb_clone_mnt_opts = selinux_sb_clone_mnt_opts,
.sb_parse_opts_str = selinux_parse_opts_str,
.inode_getxattr = selinux_inode_getxattr,
.inode_listxattr = selinux_inode_listxattr,
.inode_removexattr = selinux_inode_removexattr,
- .inode_getsecurity = selinux_inode_getsecurity,
- .inode_setsecurity = selinux_inode_setsecurity,
- .inode_listsecurity = selinux_inode_listsecurity,
+ .inode_getsecurity = selinux_inode_getsecurity,
+ .inode_setsecurity = selinux_inode_setsecurity,
+ .inode_listsecurity = selinux_inode_listsecurity,
.inode_need_killpriv = selinux_inode_need_killpriv,
.inode_killpriv = selinux_inode_killpriv,
.inode_getsecid = selinux_inode_getsecid,
.file_send_sigiotask = selinux_file_send_sigiotask,
.file_receive = selinux_file_receive,
- .dentry_open = selinux_dentry_open,
+ .dentry_open = selinux_dentry_open,
.task_create = selinux_task_create,
.task_alloc_security = selinux_task_alloc_security,
.task_setgid = selinux_task_setgid,
.task_setpgid = selinux_task_setpgid,
.task_getpgid = selinux_task_getpgid,
- .task_getsid = selinux_task_getsid,
+ .task_getsid = selinux_task_getsid,
.task_getsecid = selinux_task_getsecid,
.task_setgroups = selinux_task_setgroups,
.task_setnice = selinux_task_setnice,
.task_wait = selinux_task_wait,
.task_prctl = selinux_task_prctl,
.task_reparent_to_init = selinux_task_reparent_to_init,
- .task_to_inode = selinux_task_to_inode,
+ .task_to_inode = selinux_task_to_inode,
.ipc_permission = selinux_ipc_permission,
.ipc_getsecid = selinux_ipc_getsecid,
.shm_shmctl = selinux_shm_shmctl,
.shm_shmat = selinux_shm_shmat,
- .sem_alloc_security = selinux_sem_alloc_security,
- .sem_free_security = selinux_sem_free_security,
+ .sem_alloc_security = selinux_sem_alloc_security,
+ .sem_free_security = selinux_sem_free_security,
.sem_associate = selinux_sem_associate,
.sem_semctl = selinux_sem_semctl,
.sem_semop = selinux_sem_semop,
.register_security = selinux_register_security,
- .d_instantiate = selinux_d_instantiate,
+ .d_instantiate = selinux_d_instantiate,
- .getprocattr = selinux_getprocattr,
- .setprocattr = selinux_setprocattr,
+ .getprocattr = selinux_getprocattr,
+ .setprocattr = selinux_setprocattr,
.secid_to_secctx = selinux_secid_to_secctx,
.secctx_to_secid = selinux_secctx_to_secid,
.release_secctx = selinux_release_secctx,
- .unix_stream_connect = selinux_socket_unix_stream_connect,
+ .unix_stream_connect = selinux_socket_unix_stream_connect,
.unix_may_send = selinux_socket_unix_may_send,
.socket_create = selinux_socket_create,
.sk_alloc_security = selinux_sk_alloc_security,
.sk_free_security = selinux_sk_free_security,
.sk_clone_security = selinux_sk_clone_security,
- .sk_getsecid = selinux_sk_getsecid,
+ .sk_getsecid = selinux_sk_getsecid,
.sock_graft = selinux_sock_graft,
.inet_conn_request = selinux_inet_conn_request,
.inet_csk_clone = selinux_inet_csk_clone,
.xfrm_state_alloc_security = selinux_xfrm_state_alloc,
.xfrm_state_free_security = selinux_xfrm_state_free,
.xfrm_state_delete_security = selinux_xfrm_state_delete,
- .xfrm_policy_lookup = selinux_xfrm_policy_lookup,
+ .xfrm_policy_lookup = selinux_xfrm_policy_lookup,
.xfrm_state_pol_flow_match = selinux_xfrm_state_pol_flow_match,
.xfrm_decode_session = selinux_xfrm_decode_session,
#endif
#ifdef CONFIG_KEYS
- .key_alloc = selinux_key_alloc,
- .key_free = selinux_key_free,
- .key_permission = selinux_key_permission,
+ .key_alloc = selinux_key_alloc,
+ .key_free = selinux_key_free,
+ .key_permission = selinux_key_permission,
#endif
#ifdef CONFIG_AUDIT
original_ops = secondary_ops = security_ops;
if (!secondary_ops)
- panic ("SELinux: No initial security operations\n");
- if (register_security (&selinux_ops))
+ panic("SELinux: No initial security operations\n");
+ if (register_security(&selinux_ops))
panic("SELinux: Unable to register with kernel.\n");
- if (selinux_enforcing) {
+ if (selinux_enforcing)
printk(KERN_DEBUG "SELinux: Starting in enforcing mode\n");
- } else {
+ else
printk(KERN_DEBUG "SELinux: Starting in permissive mode\n");
- }
#ifdef CONFIG_KEYS
/* Add security information to initial keyrings */
if (!list_empty(&superblock_security_head)) {
struct superblock_security_struct *sbsec =
list_entry(superblock_security_head.next,
- struct superblock_security_struct,
- list);
+ struct superblock_security_struct,
+ list);
struct super_block *sb = sbsec->sb;
sb->s_count++;
spin_unlock(&sb_security_lock);
#endif /* CONFIG_NETFILTER */
#ifdef CONFIG_SECURITY_SELINUX_DISABLE
+static int selinux_disabled;
+
int selinux_disable(void)
{
extern void exit_sel_fs(void);
- static int selinux_disabled = 0;
if (ss_initialized) {
/* Not permitted after initial policy load. */
*
* Copyright (C) 2003 Red Hat, Inc., James Morris <jmorris@redhat.com>
* Copyright (C) 2007 Hewlett-Packard Development Company, L.P.
- *
Paul Moore <paul.moore@hp.com>
+ * Paul Moore <paul.moore@hp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2,
#define SEL_NETIF_HASH_SIZE 64
#define SEL_NETIF_HASH_MAX 1024
-struct sel_netif
-{
+struct sel_netif {
struct list_head list;
struct netif_security_struct nsec;
struct rcu_head rcu_head;
static int sel_netif_insert(struct sel_netif *netif)
{
int idx;
-
+
if (sel_netif_total >= SEL_NETIF_HASH_MAX)
return -ENOSPC;
-
+
idx = sel_netif_hashfn(netif->nsec.ifindex);
list_add_rcu(&netif->list, &sel_netif_hash[idx]);
sel_netif_total++;
{
struct sel_netif *netif;
+ rcu_read_lock();
spin_lock_bh(&sel_netif_lock);
netif = sel_netif_find(ifindex);
if (netif)
sel_netif_destroy(netif);
spin_unlock_bh(&sel_netif_lock);
+ rcu_read_unlock();
}
/**
}
static int sel_netif_avc_callback(u32 event, u32 ssid, u32 tsid,
- u16 class, u32 perms, u32 *retained)
+ u16 class, u32 perms, u32 *retained)
{
if (event == AVC_CALLBACK_RESET) {
sel_netif_flush();
}
static int sel_netif_netdev_notifier_handler(struct notifier_block *this,
- unsigned long event, void *ptr)
+ unsigned long event, void *ptr)
{
struct net_device *dev = ptr;
static __init int sel_netif_init(void)
{
int i, err;
-
+
if (!selinux_enabled)
return 0;
INIT_LIST_HEAD(&sel_netif_hash[i]);
register_netdevice_notifier(&sel_netif_netdev_notifier);
-
+
err = avc_add_callback(sel_netif_avc_callback, AVC_CALLBACK_RESET,
- SECSID_NULL, SECSID_NULL, SECCLASS_NULL, 0);
+ SECSID_NULL, SECSID_NULL, SECCLASS_NULL, 0);
if (err)
panic("avc_add_callback() failed, error %d\n", err);
void selinux_netlbl_sk_security_reset(struct sk_security_struct *ssec,
int family)
{
- if (family == PF_INET)
+ if (family == PF_INET)
ssec->nlbl_state = NLBL_REQUIRE;
else
ssec->nlbl_state = NLBL_UNSET;
static int selnl_msglen(int msgtype)
{
int ret = 0;
-
+
switch (msgtype) {
case SELNL_MSG_SETENFORCE:
ret = sizeof(struct selnl_msg_setenforce);
break;
-
+
case SELNL_MSG_POLICYLOAD:
ret = sizeof(struct selnl_msg_policyload);
break;
-
+
default:
BUG();
}
switch (msgtype) {
case SELNL_MSG_SETENFORCE: {
struct selnl_msg_setenforce *msg = NLMSG_DATA(nlh);
-
+
memset(msg, 0, len);
msg->val = *((int *)data);
break;
}
-
+
case SELNL_MSG_POLICYLOAD: {
struct selnl_msg_policyload *msg = NLMSG_DATA(nlh);
-
+
memset(msg, 0, len);
msg->seqno = *((u32 *)data);
break;
sk_buff_data_t tmp;
struct sk_buff *skb;
struct nlmsghdr *nlh;
-
+
len = selnl_msglen(msgtype);
-
+
skb = alloc_skb(NLMSG_SPACE(len), GFP_USER);
if (!skb)
goto oom;
netlink_broadcast(selnl, skb, 0, SELNLGRP_AVC, GFP_USER);
out:
return;
-
+
nlmsg_failure:
kfree_skb(skb);
oom:
SELNLGRP_MAX, NULL, NULL, THIS_MODULE);
if (selnl == NULL)
panic("SELinux: Cannot create netlink socket.");
- netlink_set_nonroot(NETLINK_SELINUX, NL_NONROOT_RECV);
+ netlink_set_nonroot(NETLINK_SELINUX, NL_NONROOT_RECV);
return 0;
}
INIT_LIST_HEAD(&sel_netnode_hash[iter]);
ret = avc_add_callback(sel_netnode_avc_callback, AVC_CALLBACK_RESET,
- SECSID_NULL, SECSID_NULL, SECCLASS_NULL, 0);
+ SECSID_NULL, SECSID_NULL, SECCLASS_NULL, 0);
if (ret != 0)
panic("avc_add_callback() failed, error %d\n", ret);
#include "flask.h"
#include "av_permissions.h"
-struct nlmsg_perm
-{
+struct nlmsg_perm {
u16 nlmsg_type;
u32 perm;
};
if ((nlmsg_type >= AUDIT_FIRST_USER_MSG &&
nlmsg_type <= AUDIT_LAST_USER_MSG) ||
(nlmsg_type >= AUDIT_FIRST_USER_MSG2 &&
- nlmsg_type <= AUDIT_LAST_USER_MSG2)) {
+ nlmsg_type <= AUDIT_LAST_USER_MSG2)) {
*perm = NETLINK_AUDIT_SOCKET__NLMSG_RELAY;
} else {
err = nlmsg_perm(nlmsg_type, perm, nlmsg_audit_perms,
/* Updated: Karl MacMillan <kmacmillan@tresys.com>
*
- * Added conditional policy language extensions
+ * Added conditional policy language extensions
*
* Updated: Hewlett-Packard <paul.moore@hp.com>
*
- * Added support for the policy capability bitmap
+ * Added support for the policy capability bitmap
*
* Copyright (C) 2007 Hewlett-Packard Development Company, L.P.
* Copyright (C) 2003 - 2004 Tresys Technology, LLC
* Copyright (C) 2004 Red Hat, Inc., James Morris <jmorris@redhat.com>
* This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
+ * it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 2.
*/
#include <linux/percpu.h>
#include <linux/audit.h>
#include <asm/uaccess.h>
-#include <asm/semaphore.h>
/* selinuxfs pseudo filesystem for exporting the security policy API.
Based on the proc code and the fs/nfsd/nfsctl.c code. */
static int __init checkreqprot_setup(char *str)
{
- selinux_checkreqprot = simple_strtoul(str,NULL,0) ? 1 : 0;
+ selinux_checkreqprot = simple_strtoul(str, NULL, 0) ? 1 : 0;
return 1;
}
__setup("checkreqprot=", checkreqprot_setup);
static int __init selinux_compat_net_setup(char *str)
{
- selinux_compat_net = simple_strtoul(str,NULL,0) ? 1 : 0;
+ selinux_compat_net = simple_strtoul(str, NULL, 0) ? 1 : 0;
return 1;
}
__setup("selinux_compat_net=", selinux_compat_net_setup);
static DEFINE_MUTEX(sel_mutex);
/* global data for booleans */
-static struct dentry *bool_dir = NULL;
-static int bool_num = 0;
+static struct dentry *bool_dir;
+static int bool_num;
static char **bool_pending_names;
-static int *bool_pending_values = NULL;
+static int *bool_pending_values;
/* global data for classes */
-static struct dentry *class_dir = NULL;
+static struct dentry *class_dir;
static unsigned long last_class_ino;
/* global data for policy capabilities */
-static struct dentry *policycap_dir = NULL;
+static struct dentry *policycap_dir;
extern void selnl_notify_setenforce(int val);
}
#ifdef CONFIG_SECURITY_SELINUX_DEVELOP
-static ssize_t sel_write_enforce(struct file * file, const char __user * buf,
+static ssize_t sel_write_enforce(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
/* No partial writes. */
return -EINVAL;
}
- page = (char*)get_zeroed_page(GFP_KERNEL);
+ page = (char *)get_zeroed_page(GFP_KERNEL);
if (!page)
return -ENOMEM;
length = -EFAULT;
};
#ifdef CONFIG_SECURITY_SELINUX_DISABLE
-static ssize_t sel_write_disable(struct file * file, const char __user * buf,
+static ssize_t sel_write_disable(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
/* No partial writes. */
return -EINVAL;
}
- page = (char*)get_zeroed_page(GFP_KERNEL);
+ page = (char *)get_zeroed_page(GFP_KERNEL);
if (!page)
return -ENOMEM;
length = -EFAULT;
};
static ssize_t sel_read_policyvers(struct file *filp, char __user *buf,
- size_t count, loff_t *ppos)
+ size_t count, loff_t *ppos)
{
char tmpbuf[TMPBUFLEN];
ssize_t length;
.read = sel_read_mls,
};
-static ssize_t sel_write_load(struct file * file, const char __user * buf,
+static ssize_t sel_write_load(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
.write = sel_write_load,
};
-static ssize_t sel_write_context(struct file * file, char *buf, size_t size)
+static ssize_t sel_write_context(struct file *file, char *buf, size_t size)
{
char *canon;
u32 sid, len;
return length;
if (len > SIMPLE_TRANSACTION_LIMIT) {
- printk(KERN_ERR "%s: context size (%u) exceeds payload "
- "max\n", __func__, len);
+ printk(KERN_ERR "SELinux: %s: context size (%u) exceeds "
+ "payload max\n", __func__, len);
length = -ERANGE;
goto out;
}
return simple_read_from_buffer(buf, count, ppos, tmpbuf, length);
}
-static ssize_t sel_write_checkreqprot(struct file * file, const char __user * buf,
+static ssize_t sel_write_checkreqprot(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
char *page;
/* No partial writes. */
return -EINVAL;
}
- page = (char*)get_zeroed_page(GFP_KERNEL);
+ page = (char *)get_zeroed_page(GFP_KERNEL);
if (!page)
return -ENOMEM;
length = -EFAULT;
return simple_read_from_buffer(buf, count, ppos, tmpbuf, length);
}
-static ssize_t sel_write_compat_net(struct file * file, const char __user * buf,
+static ssize_t sel_write_compat_net(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
char *page;
/* No partial writes. */
return -EINVAL;
}
- page = (char*)get_zeroed_page(GFP_KERNEL);
+ page = (char *)get_zeroed_page(GFP_KERNEL);
if (!page)
return -ENOMEM;
length = -EFAULT;
/*
* Remaining nodes use transaction based IO methods like nfsd/nfsctl.c
*/
-static ssize_t sel_write_access(struct file * file, char *buf, size_t size);
-static ssize_t sel_write_create(struct file * file, char *buf, size_t size);
-static ssize_t sel_write_relabel(struct file * file, char *buf, size_t size);
-static ssize_t sel_write_user(struct file * file, char *buf, size_t size);
-static ssize_t sel_write_member(struct file * file, char *buf, size_t size);
+static ssize_t sel_write_access(struct file *file, char *buf, size_t size);
+static ssize_t sel_write_create(struct file *file, char *buf, size_t size);
+static ssize_t sel_write_relabel(struct file *file, char *buf, size_t size);
+static ssize_t sel_write_user(struct file *file, char *buf, size_t size);
+static ssize_t sel_write_member(struct file *file, char *buf, size_t size);
static ssize_t (*write_op[])(struct file *, char *, size_t) = {
[SEL_ACCESS] = sel_write_access,
static ssize_t selinux_transaction_write(struct file *file, const char __user *buf, size_t size, loff_t *pos)
{
- ino_t ino = file->f_path.dentry->d_inode->i_ino;
+ ino_t ino = file->f_path.dentry->d_inode->i_ino;
char *data;
ssize_t rv;
if (IS_ERR(data))
return PTR_ERR(data);
- rv = write_op[ino](file, data, size);
- if (rv>0) {
+ rv = write_op[ino](file, data, size);
+ if (rv > 0) {
simple_transaction_set(file, rv);
rv = size;
}
* and the length returned. Otherwise return 0 or and -error.
*/
-static ssize_t sel_write_access(struct file * file, char *buf, size_t size)
+static ssize_t sel_write_access(struct file *file, char *buf, size_t size)
{
char *scon, *tcon;
u32 ssid, tsid;
return length;
}
-static ssize_t sel_write_create(struct file * file, char *buf, size_t size)
+static ssize_t sel_write_create(struct file *file, char *buf, size_t size)
{
char *scon, *tcon;
u32 ssid, tsid, newsid;
goto out2;
if (len > SIMPLE_TRANSACTION_LIMIT) {
- printk(KERN_ERR "%s: context size (%u) exceeds payload "
- "max\n", __func__, len);
+ printk(KERN_ERR "SELinux: %s: context size (%u) exceeds "
+ "payload max\n", __func__, len);
length = -ERANGE;
goto out3;
}
return length;
}
-static ssize_t sel_write_relabel(struct file * file, char *buf, size_t size)
+static ssize_t sel_write_relabel(struct file *file, char *buf, size_t size)
{
char *scon, *tcon;
u32 ssid, tsid, newsid;
return length;
}
-static ssize_t sel_write_user(struct file * file, char *buf, size_t size)
+static ssize_t sel_write_user(struct file *file, char *buf, size_t size)
{
char *con, *user, *ptr;
u32 sid, *sids;
return length;
}
-static ssize_t sel_write_member(struct file * file, char *buf, size_t size)
+static ssize_t sel_write_member(struct file *file, char *buf, size_t size)
{
char *scon, *tcon;
u32 ssid, tsid, newsid;
goto out2;
if (len > SIMPLE_TRANSACTION_LIMIT) {
- printk(KERN_ERR "%s: context size (%u) exceeds payload "
- "max\n", __func__, len);
+ printk(KERN_ERR "SELinux: %s: context size (%u) exceeds "
+ "payload max\n", __func__, len);
length = -ERANGE;
goto out3;
}
ret = -EINVAL;
goto out;
}
- if (!(page = (char*)get_zeroed_page(GFP_KERNEL))) {
+ page = (char *)get_zeroed_page(GFP_KERNEL);
+ if (!page) {
ret = -ENOMEM;
goto out;
}
length = -EINVAL;
goto out;
}
- page = (char*)get_zeroed_page(GFP_KERNEL);
+ page = (char *)get_zeroed_page(GFP_KERNEL);
if (!page) {
length = -ENOMEM;
goto out;
}
static const struct file_operations sel_bool_ops = {
- .read = sel_read_bool,
- .write = sel_write_bool,
+ .read = sel_read_bool,
+ .write = sel_write_bool,
};
static ssize_t sel_commit_bools_write(struct file *filep,
/* No partial writes. */
goto out;
}
- page = (char*)get_zeroed_page(GFP_KERNEL);
+ page = (char *)get_zeroed_page(GFP_KERNEL);
if (!page) {
length = -ENOMEM;
goto out;
if (sscanf(page, "%d", &new_value) != 1)
goto out;
- if (new_value && bool_pending_values) {
+ if (new_value && bool_pending_values)
security_set_bools(bool_num, bool_pending_values);
- }
length = count;
}
static const struct file_operations sel_commit_bools_ops = {
- .write = sel_commit_bools_write,
+ .write = sel_commit_bools_write,
};
static void sel_remove_entries(struct dentry *de)
sel_remove_entries(dir);
- if (!(page = (char*)get_zeroed_page(GFP_KERNEL)))
+ page = (char *)get_zeroed_page(GFP_KERNEL);
+ if (!page)
return -ENOMEM;
ret = security_get_bools(&num, &names, &values);
ret = -ENAMETOOLONG;
goto err;
}
- isec = (struct inode_security_struct*)inode->i_security;
- if ((ret = security_genfs_sid("selinuxfs", page, SECCLASS_FILE, &sid)))
+ isec = (struct inode_security_struct *)inode->i_security;
+ ret = security_genfs_sid("selinuxfs", page, SECCLASS_FILE, &sid);
+ if (ret)
goto err;
isec->sid = sid;
isec->initialized = 1;
#define NULL_FILE_NAME "null"
-struct dentry *selinux_null = NULL;
+struct dentry *selinux_null;
static ssize_t sel_read_avc_cache_threshold(struct file *filp, char __user *buf,
size_t count, loff_t *ppos)
return simple_read_from_buffer(buf, count, ppos, tmpbuf, length);
}
-static ssize_t sel_write_avc_cache_threshold(struct file * file,
- const char __user * buf,
+static ssize_t sel_write_avc_cache_threshold(struct file *file,
+ const char __user *buf,
size_t count, loff_t *ppos)
{
goto out;
}
- page = (char*)get_zeroed_page(GFP_KERNEL);
+ page = (char *)get_zeroed_page(GFP_KERNEL);
if (!page) {
ret = -ENOMEM;
goto out;
return ret;
}
-static ssize_t sel_read_initcon(struct file * file, char __user *buf,
+static ssize_t sel_read_initcon(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
struct inode *inode;
return (ino & SEL_INO_MASK) % (SEL_VEC_MAX + 1);
}
-static ssize_t sel_read_class(struct file * file, char __user *buf,
+static ssize_t sel_read_class(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
ssize_t rc, len;
.read = sel_read_class,
};
-static ssize_t sel_read_perm(struct file * file, char __user *buf,
+static ssize_t sel_read_perm(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
ssize_t rc, len;
goto out;
}
- len = snprintf(page, PAGE_SIZE,"%d", sel_ino_to_perm(ino));
+ len = snprintf(page, PAGE_SIZE, "%d", sel_ino_to_perm(ino));
rc = simple_read_from_buffer(buf, count, ppos, page, len);
free_page((unsigned long)page);
out:
return ret;
}
-static int sel_fill_super(struct super_block * sb, void * data, int silent)
+static int sel_fill_super(struct super_block *sb, void *data, int silent)
{
int ret;
struct dentry *dentry;
goto err;
}
inode->i_ino = ++sel_last_ino;
- isec = (struct inode_security_struct*)inode->i_security;
+ isec = (struct inode_security_struct *)inode->i_security;
isec->sid = SECINITSID_DEVNULL;
isec->sclass = SECCLASS_CHR_FILE;
isec->initialized = 1;
out:
return ret;
err:
- printk(KERN_ERR "%s: failed while creating inodes\n", __func__);
+ printk(KERN_ERR "SELinux: %s: failed while creating inodes\n",
+ __func__);
goto out;
}
/* Updated: Frank Mayer <mayerf@tresys.com> and Karl MacMillan <kmacmillan@tresys.com>
*
- * Added conditional policy language extensions
+ * Added conditional policy language extensions
*
* Copyright (C) 2003 Tresys Technology, LLC
* This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
+ * it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 2.
*
* Updated: Yuichi Nakamura <ynakam@hitachisoft.jp>
- * Tuned number of hash slots for avtab to reduce memory usage
+ * Tuned number of hash slots for avtab to reduce memory usage
*/
#include <linux/kernel.h>
static struct avtab_node*
avtab_insert_node(struct avtab *h, int hvalue,
- struct avtab_node * prev, struct avtab_node * cur,
+ struct avtab_node *prev, struct avtab_node *cur,
struct avtab_key *key, struct avtab_datum *datum)
{
- struct avtab_node * newnode;
+ struct avtab_node *newnode;
newnode = kmem_cache_zalloc(avtab_node_cachep, GFP_KERNEL);
if (newnode == NULL)
return NULL;
}
newnode = avtab_insert_node(h, hvalue, prev, cur, key, datum);
- if(!newnode)
+ if (!newnode)
return -ENOMEM;
return 0;
* It also returns a pointer to the node inserted.
*/
struct avtab_node *
-avtab_insert_nonunique(struct avtab * h, struct avtab_key * key, struct avtab_datum * datum)
+avtab_insert_nonunique(struct avtab *h, struct avtab_key *key, struct avtab_datum *datum)
{
int hvalue;
struct avtab_node *prev, *cur, *newnode;
}
}
- printk(KERN_DEBUG "%s: %d entries and %d/%d buckets used, longest "
- "chain length %d sum of chain length^2 %Lu\n",
+ printk(KERN_DEBUG "SELinux: %s: %d entries and %d/%d buckets used, "
+ "longest chain length %d sum of chain length^2 %Lu\n",
tag, h->nel, slots_used, h->nslot, max_chain_len,
chain2_len_sum);
}
};
int avtab_read_item(struct avtab *a, void *fp, struct policydb *pol,
- int (*insertf)(struct avtab *a, struct avtab_key *k,
+ int (*insertf)(struct avtab *a, struct avtab_key *k,
struct avtab_datum *d, void *p),
void *p)
{
val = le32_to_cpu(buf32[items++]);
key.source_type = (u16)val;
if (key.source_type != val) {
- printk("SELinux: avtab: truncated source type\n");
+ printk(KERN_ERR "SELinux: avtab: truncated source type\n");
return -1;
}
val = le32_to_cpu(buf32[items++]);
key.target_type = (u16)val;
if (key.target_type != val) {
- printk("SELinux: avtab: truncated target type\n");
+ printk(KERN_ERR "SELinux: avtab: truncated target type\n");
return -1;
}
val = le32_to_cpu(buf32[items++]);
key.target_class = (u16)val;
if (key.target_class != val) {
- printk("SELinux: avtab: truncated target class\n");
+ printk(KERN_ERR "SELinux: avtab: truncated target class\n");
return -1;
}
enabled = (val & AVTAB_ENABLED_OLD) ? AVTAB_ENABLED : 0;
if (!(val & (AVTAB_AV | AVTAB_TYPE))) {
- printk("SELinux: avtab: null entry\n");
+ printk(KERN_ERR "SELinux: avtab: null entry\n");
return -1;
}
if ((val & AVTAB_AV) &&
(val & AVTAB_TYPE)) {
- printk("SELinux: avtab: entry has both access vectors and types\n");
+ printk(KERN_ERR "SELinux: avtab: entry has both access vectors and types\n");
return -1;
}
key.specified = spec_order[i] | enabled;
datum.data = le32_to_cpu(buf32[items++]);
rc = insertf(a, &key, &datum, p);
- if (rc) return rc;
+ if (rc)
+ return rc;
}
}
if (items != items2) {
- printk("SELinux: avtab: entry only had %d items, expected %d\n", items2, items);
+ printk(KERN_ERR "SELinux: avtab: entry only had %d items, expected %d\n", items2, items);
return -1;
}
return 0;
rc = next_entry(buf16, fp, sizeof(u16)*4);
if (rc < 0) {
- printk("SELinux: avtab: truncated entry\n");
+ printk(KERN_ERR "SELinux: avtab: truncated entry\n");
return -1;
}
if (!policydb_type_isvalid(pol, key.source_type) ||
!policydb_type_isvalid(pol, key.target_type) ||
!policydb_class_isvalid(pol, key.target_class)) {
- printk(KERN_WARNING "SELinux: avtab: invalid type or class\n");
+ printk(KERN_ERR "SELinux: avtab: invalid type or class\n");
return -1;
}
set++;
}
if (!set || set > 1) {
- printk(KERN_WARNING
- "SELinux: avtab: more than one specifier\n");
+ printk(KERN_ERR "SELinux: avtab: more than one specifier\n");
return -1;
}
rc = next_entry(buf32, fp, sizeof(u32));
if (rc < 0) {
- printk("SELinux: avtab: truncated entry\n");
+ printk(KERN_ERR "SELinux: avtab: truncated entry\n");
return -1;
}
datum.data = le32_to_cpu(*buf32);
if ((key.specified & AVTAB_TYPE) &&
!policydb_type_isvalid(pol, datum.data)) {
- printk(KERN_WARNING "SELinux: avtab: invalid type\n");
+ printk(KERN_ERR "SELinux: avtab: invalid type\n");
return -1;
}
return insertf(a, &key, &datum, p);
void avtab_cache_destroy(void)
{
- kmem_cache_destroy (avtab_node_cachep);
+ kmem_cache_destroy(avtab_node_cachep);
}
/* Authors: Karl MacMillan <kmacmillan@tresys.com>
- * Frank Mayer <mayerf@tresys.com>
+ * Frank Mayer <mayerf@tresys.com>
*
* Copyright (C) 2003 - 2004 Tresys Technology, LLC
* This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
+ * it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 2.
*/
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/spinlock.h>
-#include <asm/semaphore.h>
#include <linux/slab.h>
#include "security.h"
int evaluate_cond_node(struct policydb *p, struct cond_node *node)
{
int new_state;
- struct cond_av_list* cur;
+ struct cond_av_list *cur;
new_state = cond_evaluate_expr(p, node->expr);
if (new_state != node->cur_state) {
printk(KERN_ERR "SELinux: expression result was undefined - disabling all rules.\n");
/* turn the rules on or off */
for (cur = node->true_list; cur != NULL; cur = cur->next) {
- if (new_state <= 0) {
+ if (new_state <= 0)
cur->node->key.specified &= ~AVTAB_ENABLED;
- } else {
+ else
cur->node->key.specified |= AVTAB_ENABLED;
- }
}
for (cur = node->false_list; cur != NULL; cur = cur->next) {
/* -1 or 1 */
- if (new_state) {
+ if (new_state)
cur->node->key.specified &= ~AVTAB_ENABLED;
- } else {
+ else
cur->node->key.specified |= AVTAB_ENABLED;
- }
}
}
return 0;
int cond_init_bool_indexes(struct policydb *p)
{
kfree(p->bool_val_to_struct);
- p->bool_val_to_struct = (struct cond_bool_datum**)
- kmalloc(p->p_bools.nprim * sizeof(struct cond_bool_datum*), GFP_KERNEL);
+ p->bool_val_to_struct = (struct cond_bool_datum **)
+ kmalloc(p->p_bools.nprim * sizeof(struct cond_bool_datum *), GFP_KERNEL);
if (!p->bool_val_to_struct)
return -1;
return 0;
return -EINVAL;
p->p_bool_val_to_name[booldatum->value - 1] = key;
- p->bool_val_to_struct[booldatum->value -1] = booldatum;
+ p->bool_val_to_struct[booldatum->value - 1] = booldatum;
return 0;
}
return -1;
}
-struct cond_insertf_data
-{
+struct cond_insertf_data {
struct policydb *p;
struct cond_av_list *other;
struct cond_av_list *head;
*/
if (k->specified & AVTAB_TYPE) {
if (avtab_search(&p->te_avtab, k)) {
- printk("SELinux: type rule already exists outside of a conditional.");
+ printk(KERN_ERR "SELinux: type rule already exists outside of a conditional.\n");
goto err;
}
/*
node_ptr = avtab_search_node(&p->te_cond_avtab, k);
if (node_ptr) {
if (avtab_search_node_next(node_ptr, k->specified)) {
- printk("SELinux: too many conflicting type rules.");
+ printk(KERN_ERR "SELinux: too many conflicting type rules.\n");
goto err;
}
found = 0;
}
}
if (!found) {
- printk("SELinux: conflicting type rules.\n");
+ printk(KERN_ERR "SELinux: conflicting type rules.\n");
goto err;
}
}
} else {
if (avtab_search(&p->te_cond_avtab, k)) {
- printk("SELinux: conflicting type rules when adding type rule for true.\n");
+ printk(KERN_ERR "SELinux: conflicting type rules when adding type rule for true.\n");
goto err;
}
}
node_ptr = avtab_insert_nonunique(&p->te_cond_avtab, k, d);
if (!node_ptr) {
- printk("SELinux: could not insert rule.");
+ printk(KERN_ERR "SELinux: could not insert rule.\n");
goto err;
}
return -1;
len = le32_to_cpu(buf[0]);
- if (len == 0) {
+ if (len == 0)
return 0;
- }
data.p = p;
data.other = other;
static int expr_isvalid(struct policydb *p, struct cond_expr *expr)
{
if (expr->expr_type <= 0 || expr->expr_type > COND_LAST) {
- printk("SELinux: conditional expressions uses unknown operator.\n");
+ printk(KERN_ERR "SELinux: conditional expressions uses unknown operator.\n");
return 0;
}
if (expr->bool > p->p_bools.nprim) {
- printk("SELinux: conditional expressions uses unknown bool.\n");
+ printk(KERN_ERR "SELinux: conditional expressions uses unknown bool.\n");
return 0;
}
return 1;
/* expr */
len = le32_to_cpu(buf[0]);
- for (i = 0; i < len; i++ ) {
+ for (i = 0; i < len; i++) {
rc = next_entry(buf, fp, sizeof(u32) * 2);
if (rc < 0)
goto err;
expr = kzalloc(sizeof(struct cond_expr), GFP_KERNEL);
- if (!expr) {
+ if (!expr)
goto err;
- }
expr->expr_type = le32_to_cpu(buf[0]);
expr->bool = le32_to_cpu(buf[1]);
goto err;
}
- if (i == 0) {
+ if (i == 0)
node->expr = expr;
- } else {
+ else
last->next = expr;
- }
last = expr;
}
if (cond_read_node(p, node, fp) != 0)
goto err;
- if (i == 0) {
+ if (i == 0)
p->cond_list = node;
- } else {
+ else
last->next = node;
- }
last = node;
}
return 0;
{
struct avtab_node *node;
- if(!ctab || !key || !avd)
+ if (!ctab || !key || !avd)
return;
- for(node = avtab_search_node(ctab, key); node != NULL;
+ for (node = avtab_search_node(ctab, key); node != NULL;
node = avtab_search_node_next(node, key->specified)) {
- if ( (u16) (AVTAB_ALLOWED|AVTAB_ENABLED) ==
- (node->key.specified & (AVTAB_ALLOWED|AVTAB_ENABLED)))
+ if ((u16)(AVTAB_ALLOWED|AVTAB_ENABLED) ==
+ (node->key.specified & (AVTAB_ALLOWED|AVTAB_ENABLED)))
avd->allowed |= node->datum.data;
- if ( (u16) (AVTAB_AUDITDENY|AVTAB_ENABLED) ==
- (node->key.specified & (AVTAB_AUDITDENY|AVTAB_ENABLED)))
+ if ((u16)(AVTAB_AUDITDENY|AVTAB_ENABLED) ==
+ (node->key.specified & (AVTAB_AUDITDENY|AVTAB_ENABLED)))
/* Since a '0' in an auditdeny mask represents a
* permission we do NOT want to audit (dontaudit), we use
* the '&' operand to ensure that all '0's in the mask
* are retained (much unlike the allow and auditallow cases).
*/
avd->auditdeny &= node->datum.data;
- if ( (u16) (AVTAB_AUDITALLOW|AVTAB_ENABLED) ==
- (node->key.specified & (AVTAB_AUDITALLOW|AVTAB_ENABLED)))
+ if ((u16)(AVTAB_AUDITALLOW|AVTAB_ENABLED) ==
+ (node->key.specified & (AVTAB_AUDITALLOW|AVTAB_ENABLED)))
avd->auditallow |= node->datum.data;
}
return;
}
/* round down */
tmp->startbit = startbit - (startbit % EBITMAP_SIZE);
- if (n) {
+ if (n)
n->next = tmp;
- } else {
+ else
e->node = tmp;
- }
n = tmp;
} else if (startbit <= n->startbit) {
printk(KERN_ERR "SELinux: ebitmap: start bit %d"
#include "hashtab.h"
struct hashtab *hashtab_create(u32 (*hash_value)(struct hashtab *h, const void *key),
- int (*keycmp)(struct hashtab *h, const void *key1, const void *key2),
- u32 size)
+ int (*keycmp)(struct hashtab *h, const void *key1, const void *key2),
+ u32 size)
{
struct hashtab *p;
u32 i;
* Return the length in bytes for the MLS fields of the
* security context string representation of `context'.
*/
-int mls_compute_context_len(struct context * context)
+int mls_compute_context_len(struct context *context)
{
int i, l, len, head, prev;
char *nm;
* Update `*scontext' to point to the end of the MLS fields.
*/
void mls_sid_to_context(struct context *context,
- char **scontext)
+ char **scontext)
{
char *scontextp, *nm;
int i, l, head, prev;
if (l == 0) {
if (mls_level_eq(&context->range.level[0],
- &context->range.level[1]))
+ &context->range.level[1]))
break;
else
*scontextp++ = '-';
*p++ = 0;
/* Separate into range if exists */
- if ((rngptr = strchr(scontextp, '.')) != NULL) {
+ rngptr = strchr(scontextp, '.');
+ if (rngptr != NULL) {
/* Remove '.' */
*rngptr++ = 0;
}
catdatum = hashtab_search(policydb.p_cats.table,
- scontextp);
+ scontextp);
if (!catdatum) {
rc = -EINVAL;
goto out;
}
rc = ebitmap_set_bit(&context->range.level[l].cat,
- catdatum->value - 1, 1);
+ catdatum->value - 1, 1);
if (rc)
goto out;
rc = -ENOMEM;
} else {
rc = mls_context_to_sid(':', &tmpstr, context,
- NULL, SECSID_NULL);
+ NULL, SECSID_NULL);
kfree(freestr);
}
* Copies the MLS range `range' into `context'.
*/
static inline int mls_range_set(struct context *context,
- struct mls_range *range)
+ struct mls_range *range)
{
int l, rc = 0;
}
int mls_setup_user_range(struct context *fromcon, struct user_datum *user,
- struct context *usercon)
+ struct context *usercon)
{
if (selinux_mls_enabled) {
struct mls_level *fromcon_sen = &(fromcon->range.level[0]);
that of the user's default clearance (but
only if the "fromcon" clearance dominates
the user's computed sensitivity level) */
- if (mls_level_dom(user_clr, fromcon_clr)) {
+ if (mls_level_dom(user_clr, fromcon_clr))
*usercon_clr = *fromcon_clr;
- } else if (mls_level_dom(fromcon_clr, user_clr)) {
+ else if (mls_level_dom(fromcon_clr, user_clr))
*usercon_clr = *user_clr;
- } else
+ else
return -EINVAL;
}
rtr->target_class == tclass) {
/* Set the range from the rule */
return mls_range_set(newcontext,
- &rtr->target_range);
+ &rtr->target_range);
}
}
/* Fallthrough */
*
* Updated: Frank Mayer <mayerf@tresys.com> and Karl MacMillan <kmacmillan@tresys.com>
*
- * Added conditional policy language extensions
+ * Added conditional policy language extensions
*
* Updated: Hewlett-Packard <paul.moore@hp.com>
*
* Copyright (C) 2004-2005 Trusted Computer Solutions, Inc.
* Copyright (C) 2003 - 2004 Tresys Technology, LLC
* This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
+ * it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 2.
*/
};
#endif
-int selinux_mls_enabled = 0;
+int selinux_mls_enabled;
static unsigned int symtab_sizes[SYM_NUM] = {
2,
/* These need to be updated if SYM_NUM or OCON_NUM changes */
static struct policydb_compat_info policydb_compat[] = {
{
- .version = POLICYDB_VERSION_BASE,
- .sym_num = SYM_NUM - 3,
- .ocon_num = OCON_NUM - 1,
+ .version = POLICYDB_VERSION_BASE,
+ .sym_num = SYM_NUM - 3,
+ .ocon_num = OCON_NUM - 1,
},
{
- .version = POLICYDB_VERSION_BOOL,
- .sym_num = SYM_NUM - 2,
- .ocon_num = OCON_NUM - 1,
+ .version = POLICYDB_VERSION_BOOL,
+ .sym_num = SYM_NUM - 2,
+ .ocon_num = OCON_NUM - 1,
},
{
- .version = POLICYDB_VERSION_IPV6,
- .sym_num = SYM_NUM - 2,
- .ocon_num = OCON_NUM,
+ .version = POLICYDB_VERSION_IPV6,
+ .sym_num = SYM_NUM - 2,
+ .ocon_num = OCON_NUM,
},
{
- .version = POLICYDB_VERSION_NLCLASS,
- .sym_num = SYM_NUM - 2,
- .ocon_num = OCON_NUM,
+ .version = POLICYDB_VERSION_NLCLASS,
+ .sym_num = SYM_NUM - 2,
+ .ocon_num = OCON_NUM,
},
{
- .version = POLICYDB_VERSION_MLS,
- .sym_num = SYM_NUM,
- .ocon_num = OCON_NUM,
+ .version = POLICYDB_VERSION_MLS,
+ .sym_num = SYM_NUM,
+ .ocon_num = OCON_NUM,
},
{
- .version = POLICYDB_VERSION_AVTAB,
- .sym_num = SYM_NUM,
- .ocon_num = OCON_NUM,
+ .version = POLICYDB_VERSION_AVTAB,
+ .sym_num = SYM_NUM,
+ .ocon_num = OCON_NUM,
},
{
- .version = POLICYDB_VERSION_RANGETRANS,
- .sym_num = SYM_NUM,
- .ocon_num = OCON_NUM,
+ .version = POLICYDB_VERSION_RANGETRANS,
+ .sym_num = SYM_NUM,
+ .ocon_num = OCON_NUM,
},
{
.version = POLICYDB_VERSION_POLCAP,
rc = -EINVAL;
goto out_free_role;
}
- key = kmalloc(strlen(OBJECT_R)+1,GFP_KERNEL);
+ key = kmalloc(strlen(OBJECT_R)+1, GFP_KERNEL);
if (!key) {
rc = -ENOMEM;
goto out_free_role;
struct hashtab_info info;
hashtab_stat(h, &info);
- printk(KERN_DEBUG "%s: %d entries and %d/%d buckets used, "
+ printk(KERN_DEBUG "SELinux: %s: %d entries and %d/%d buckets used, "
"longest chain length %d\n", symtab_name[i], h->nel,
info.slots_used, h->size, info.max_chain_len);
}
p->role_val_to_struct =
kmalloc(p->p_roles.nprim * sizeof(*(p->role_val_to_struct)),
- GFP_KERNEL);
+ GFP_KERNEL);
if (!p->role_val_to_struct) {
rc = -ENOMEM;
goto out;
p->user_val_to_struct =
kmalloc(p->p_users.nprim * sizeof(*(p->user_val_to_struct)),
- GFP_KERNEL);
+ GFP_KERNEL);
if (!p->user_val_to_struct) {
rc = -ENOMEM;
goto out;
while (c) {
ctmp = c;
c = c->next;
- ocontext_destroy(ctmp,i);
+ ocontext_destroy(ctmp, i);
}
p->ocontexts[i] = NULL;
}
while (c) {
ctmp = c;
c = c->next;
- ocontext_destroy(ctmp,OCON_FSUSE);
+ ocontext_destroy(ctmp, OCON_FSUSE);
}
gtmp = g;
g = g->next;
}
kfree(ltr);
- for (ra = p->role_allow; ra; ra = ra -> next) {
+ for (ra = p->role_allow; ra; ra = ra->next) {
cond_resched();
kfree(lra);
lra = ra;
}
kfree(lra);
- for (rt = p->range_tr; rt; rt = rt -> next) {
+ for (rt = p->range_tr; rt; rt = rt->next) {
cond_resched();
if (lrt) {
ebitmap_destroy(&lrt->target_range.level[0].cat);
len = le32_to_cpu(buf[0]);
perdatum->value = le32_to_cpu(buf[1]);
- key = kmalloc(len + 1,GFP_KERNEL);
+ key = kmalloc(len + 1, GFP_KERNEL);
if (!key) {
rc = -ENOMEM;
goto bad;
comdatum->permissions.nprim = le32_to_cpu(buf[2]);
nel = le32_to_cpu(buf[3]);
- key = kmalloc(len + 1,GFP_KERNEL);
+ key = kmalloc(len + 1, GFP_KERNEL);
if (!key) {
rc = -ENOMEM;
goto bad;
}
static int read_cons_helper(struct constraint_node **nodep, int ncons,
- int allowxtarget, void *fp)
+ int allowxtarget, void *fp)
{
struct constraint_node *c, *lc;
struct constraint_expr *e, *le;
if (!c)
return -ENOMEM;
- if (lc) {
+ if (lc)
lc->next = c;
- } else {
+ else
*nodep = c;
- }
rc = next_entry(buf, fp, (sizeof(u32) * 2));
if (rc < 0)
if (!e)
return -ENOMEM;
- if (le) {
+ if (le)
le->next = e;
- } else {
+ else
c->expr = e;
- }
rc = next_entry(buf, fp, (sizeof(u32) * 3));
if (rc < 0)
ncons = le32_to_cpu(buf[5]);
- key = kmalloc(len + 1,GFP_KERNEL);
+ key = kmalloc(len + 1, GFP_KERNEL);
if (!key) {
rc = -ENOMEM;
goto bad;
key[len] = 0;
if (len2) {
- cladatum->comkey = kmalloc(len2 + 1,GFP_KERNEL);
+ cladatum->comkey = kmalloc(len2 + 1, GFP_KERNEL);
if (!cladatum->comkey) {
rc = -ENOMEM;
goto bad;
len = le32_to_cpu(buf[0]);
role->value = le32_to_cpu(buf[1]);
- key = kmalloc(len + 1,GFP_KERNEL);
+ key = kmalloc(len + 1, GFP_KERNEL);
if (!key) {
rc = -ENOMEM;
goto bad;
if (strcmp(key, OBJECT_R) == 0) {
if (role->value != OBJECT_R_VAL) {
- printk(KERN_ERR "Role %s has wrong value %d\n",
+ printk(KERN_ERR "SELinux: Role %s has wrong value %d\n",
OBJECT_R, role->value);
rc = -EINVAL;
goto bad;
__le32 buf[3];
u32 len;
- typdatum = kzalloc(sizeof(*typdatum),GFP_KERNEL);
+ typdatum = kzalloc(sizeof(*typdatum), GFP_KERNEL);
if (!typdatum) {
rc = -ENOMEM;
return rc;
typdatum->value = le32_to_cpu(buf[1]);
typdatum->primary = le32_to_cpu(buf[2]);
- key = kmalloc(len + 1,GFP_KERNEL);
+ key = kmalloc(len + 1, GFP_KERNEL);
if (!key) {
rc = -ENOMEM;
goto bad;
len = le32_to_cpu(buf[0]);
usrdatum->value = le32_to_cpu(buf[1]);
- key = kmalloc(len + 1,GFP_KERNEL);
+ key = kmalloc(len + 1, GFP_KERNEL);
if (!key) {
rc = -ENOMEM;
goto bad;
len = le32_to_cpu(buf[0]);
levdatum->isalias = le32_to_cpu(buf[1]);
- key = kmalloc(len + 1,GFP_ATOMIC);
+ key = kmalloc(len + 1, GFP_ATOMIC);
if (!key) {
rc = -ENOMEM;
goto bad;
catdatum->value = le32_to_cpu(buf[1]);
catdatum->isalias = le32_to_cpu(buf[2]);
- key = kmalloc(len + 1,GFP_ATOMIC);
+ key = kmalloc(len + 1, GFP_ATOMIC);
if (!key) {
rc = -ENOMEM;
goto bad;
goto out;
/* Read the magic number and string length. */
- rc = next_entry(buf, fp, sizeof(u32)* 2);
+ rc = next_entry(buf, fp, sizeof(u32) * 2);
if (rc < 0)
goto bad;
len, strlen(POLICYDB_STRING));
goto bad;
}
- policydb_str = kmalloc(len + 1,GFP_KERNEL);
+ policydb_str = kmalloc(len + 1, GFP_KERNEL);
if (!policydb_str) {
printk(KERN_ERR "SELinux: unable to allocate memory for policydb "
"string of length %d\n", len);
if (p->policyvers < POLICYDB_VERSION_MIN ||
p->policyvers > POLICYDB_VERSION_MAX) {
printk(KERN_ERR "SELinux: policydb version %d does not match "
- "my version range %d-%d\n",
- le32_to_cpu(buf[0]), POLICYDB_VERSION_MIN, POLICYDB_VERSION_MAX);
- goto bad;
+ "my version range %d-%d\n",
+ le32_to_cpu(buf[0]), POLICYDB_VERSION_MIN, POLICYDB_VERSION_MAX);
+ goto bad;
}
if ((le32_to_cpu(buf[1]) & POLICYDB_CONFIG_MLS)) {
if (ss_initialized && !selinux_mls_enabled) {
- printk(KERN_ERR "Cannot switch between non-MLS and MLS "
- "policies\n");
+ printk(KERN_ERR "SELinux: Cannot switch between non-MLS"
+ " and MLS policies\n");
goto bad;
}
selinux_mls_enabled = 1;
config |= POLICYDB_CONFIG_MLS;
if (p->policyvers < POLICYDB_VERSION_MLS) {
- printk(KERN_ERR "security policydb version %d (MLS) "
- "not backwards compatible\n", p->policyvers);
+ printk(KERN_ERR "SELinux: security policydb version %d "
+ "(MLS) not backwards compatible\n",
+ p->policyvers);
goto bad;
}
} else {
if (ss_initialized && selinux_mls_enabled) {
- printk(KERN_ERR "Cannot switch between MLS and non-MLS "
- "policies\n");
+ printk(KERN_ERR "SELinux: Cannot switch between MLS and"
+ " non-MLS policies\n");
goto bad;
}
}
rc = -ENOMEM;
goto bad;
}
- if (ltr) {
+ if (ltr)
ltr->next = tr;
- } else {
+ else
p->role_tr = tr;
- }
rc = next_entry(buf, fp, sizeof(u32)*3);
if (rc < 0)
goto bad;
rc = -ENOMEM;
goto bad;
}
- if (lra) {
+ if (lra)
lra->next = ra;
- } else {
+ else
p->role_allow = ra;
- }
rc = next_entry(buf, fp, sizeof(u32)*2);
if (rc < 0)
goto bad;
rc = -ENOMEM;
goto bad;
}
- if (l) {
+ if (l)
l->next = c;
- } else {
+ else
p->ocontexts[i] = c;
- }
l = c;
rc = -EINVAL;
switch (i) {
if (rc < 0)
goto bad;
len = le32_to_cpu(buf[0]);
- c->u.name = kmalloc(len + 1,GFP_KERNEL);
+ c->u.name = kmalloc(len + 1, GFP_KERNEL);
if (!c->u.name) {
rc = -ENOMEM;
goto bad;
goto bad;
break;
case OCON_NODE:
- rc = next_entry(buf, fp, sizeof(u32)* 2);
+ rc = next_entry(buf, fp, sizeof(u32) * 2);
if (rc < 0)
goto bad;
c->u.node.addr = le32_to_cpu(buf[0]);
if (c->v.behavior > SECURITY_FS_USE_NONE)
goto bad;
len = le32_to_cpu(buf[1]);
- c->u.name = kmalloc(len + 1,GFP_KERNEL);
+ c->u.name = kmalloc(len + 1, GFP_KERNEL);
if (!c->u.name) {
rc = -ENOMEM;
goto bad;
goto bad;
}
- newgenfs->fstype = kmalloc(len + 1,GFP_KERNEL);
+ newgenfs->fstype = kmalloc(len + 1, GFP_KERNEL);
if (!newgenfs->fstype) {
rc = -ENOMEM;
kfree(newgenfs);
goto bad;
}
- newc->u.name = kmalloc(len + 1,GFP_KERNEL);
+ newc->u.name = kmalloc(len + 1, GFP_KERNEL);
if (!newc->u.name) {
rc = -ENOMEM;
goto bad_newc;
out:
return rc;
bad_newc:
- ocontext_destroy(newc,OCON_FSUSE);
+ ocontext_destroy(newc, OCON_FSUSE);
bad:
if (!rc)
rc = -EINVAL;
* Implementation of the security services.
*
* Authors : Stephen Smalley, <sds@epoch.ncsc.mil>
- * James Morris <jmorris@redhat.com>
+ * James Morris <jmorris@redhat.com>
*
* Updated: Trusted Computer Solutions, Inc. <dgoeddel@trustedcs.com>
*
*
* Updated: Frank Mayer <mayerf@tresys.com> and Karl MacMillan <kmacmillan@tresys.com>
*
- * Added conditional policy language extensions
+ * Added conditional policy language extensions
*
* Updated: Hewlett-Packard <paul.moore@hp.com>
*
* Copyright (C) 2003 - 2004, 2006 Tresys Technology, LLC
* Copyright (C) 2003 Red Hat, Inc., James Morris <jmorris@redhat.com>
* This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
+ * it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 2.
*/
#include <linux/kernel.h>
static struct sidtab sidtab;
struct policydb policydb;
-int ss_initialized = 0;
+int ss_initialized;
/*
* The largest sequence number that has been used when
* The sequence number only changes when a policy change
* occurs.
*/
-static u32 latest_granting = 0;
+static u32 latest_granting;
/* Forward declaration. */
static int context_struct_to_string(struct context *context, char **scontext,
val1 - 1);
continue;
case CEXPR_INCOMP:
- s[++sp] = ( !ebitmap_get_bit(&r1->dominates,
- val2 - 1) &&
- !ebitmap_get_bit(&r2->dominates,
- val1 - 1) );
+ s[++sp] = (!ebitmap_get_bit(&r1->dominates,
+ val2 - 1) &&
+ !ebitmap_get_bit(&r2->dominates,
+ val1 - 1));
continue;
default:
break;
}
if (!ra)
avd->allowed = (avd->allowed) & ~(PROCESS__TRANSITION |
- PROCESS__DYNTRANSITION);
+ PROCESS__DYNTRANSITION);
}
return 0;
inval_class:
- printk(KERN_ERR "%s: unrecognized class %d\n", __func__, tclass);
+ printk(KERN_ERR "SELinux: %s: unrecognized class %d\n", __func__,
+ tclass);
return -EINVAL;
}
}
static int security_validtrans_handle_fail(struct context *ocontext,
- struct context *ncontext,
- struct context *tcontext,
- u16 tclass)
+ struct context *ncontext,
+ struct context *tcontext,
+ u16 tclass)
{
char *o = NULL, *n = NULL, *t = NULL;
u32 olen, nlen, tlen;
if (context_struct_to_string(tcontext, &t, &tlen) < 0)
goto out;
audit_log(current->audit_context, GFP_ATOMIC, AUDIT_SELINUX_ERR,
- "security_validate_transition: denied for"
- " oldcontext=%s newcontext=%s taskcontext=%s tclass=%s",
- o, n, t, policydb.p_class_val_to_name[tclass-1]);
+ "security_validate_transition: denied for"
+ " oldcontext=%s newcontext=%s taskcontext=%s tclass=%s",
+ o, n, t, policydb.p_class_val_to_name[tclass-1]);
out:
kfree(o);
kfree(n);
}
int security_validate_transition(u32 oldsid, u32 newsid, u32 tasksid,
- u16 tclass)
+ u16 tclass)
{
struct context *ocontext;
struct context *ncontext;
tclass = SECCLASS_NETLINK_SOCKET;
if (!tclass || tclass > policydb.p_classes.nprim) {
- printk(KERN_ERR "security_validate_transition: "
- "unrecognized class %d\n", tclass);
+ printk(KERN_ERR "SELinux: %s: unrecognized class %d\n",
+ __func__, tclass);
rc = -EINVAL;
goto out;
}
ocontext = sidtab_search(&sidtab, oldsid);
if (!ocontext) {
- printk(KERN_ERR "security_validate_transition: "
- " unrecognized SID %d\n", oldsid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, oldsid);
rc = -EINVAL;
goto out;
}
ncontext = sidtab_search(&sidtab, newsid);
if (!ncontext) {
- printk(KERN_ERR "security_validate_transition: "
- " unrecognized SID %d\n", newsid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, newsid);
rc = -EINVAL;
goto out;
}
tcontext = sidtab_search(&sidtab, tasksid);
if (!tcontext) {
- printk(KERN_ERR "security_validate_transition: "
- " unrecognized SID %d\n", tasksid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, tasksid);
rc = -EINVAL;
goto out;
}
constraint = tclass_datum->validatetrans;
while (constraint) {
if (!constraint_expr_eval(ocontext, ncontext, tcontext,
- constraint->expr)) {
+ constraint->expr)) {
rc = security_validtrans_handle_fail(ocontext, ncontext,
- tcontext, tclass);
+ tcontext, tclass);
goto out;
}
constraint = constraint->next;
scontext = sidtab_search(&sidtab, ssid);
if (!scontext) {
- printk(KERN_ERR "security_compute_av: unrecognized SID %d\n",
- ssid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, ssid);
rc = -EINVAL;
goto out;
}
tcontext = sidtab_search(&sidtab, tsid);
if (!tcontext) {
- printk(KERN_ERR "security_compute_av: unrecognized SID %d\n",
- tsid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, tsid);
rc = -EINVAL;
goto out;
}
/* Allocate space for the context; caller must free this space. */
scontextp = kmalloc(*scontext_len, GFP_ATOMIC);
- if (!scontextp) {
+ if (!scontextp)
return -ENOMEM;
- }
*scontext = scontextp;
/*
policydb.p_role_val_to_name[context->role - 1],
policydb.p_type_val_to_name[context->type - 1]);
scontextp += strlen(policydb.p_user_val_to_name[context->user - 1]) +
- 1 + strlen(policydb.p_role_val_to_name[context->role - 1]) +
- 1 + strlen(policydb.p_type_val_to_name[context->type - 1]);
+ 1 + strlen(policydb.p_role_val_to_name[context->role - 1]) +
+ 1 + strlen(policydb.p_type_val_to_name[context->type - 1]);
mls_sid_to_context(context, &scontextp);
char *scontextp;
*scontext_len = strlen(initial_sid_to_string[sid]) + 1;
- scontextp = kmalloc(*scontext_len,GFP_ATOMIC);
+ scontextp = kmalloc(*scontext_len, GFP_ATOMIC);
if (!scontextp) {
rc = -ENOMEM;
goto out;
*scontext = scontextp;
goto out;
}
- printk(KERN_ERR "security_sid_to_context: called before initial "
- "load_policy on unknown SID %d\n", sid);
+ printk(KERN_ERR "SELinux: %s: called before initial "
+ "load_policy on unknown SID %d\n", __func__, sid);
rc = -EINVAL;
goto out;
}
POLICY_RDLOCK;
context = sidtab_search(&sidtab, sid);
if (!context) {
- printk(KERN_ERR "security_sid_to_context: unrecognized SID "
- "%d\n", sid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, sid);
rc = -EINVAL;
goto out_unlock;
}
scontext = sidtab_search(&sidtab, ssid);
if (!scontext) {
- printk(KERN_ERR "security_compute_sid: unrecognized SID %d\n",
- ssid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, ssid);
rc = -EINVAL;
goto out_unlock;
}
tcontext = sidtab_search(&sidtab, tsid);
if (!tcontext) {
- printk(KERN_ERR "security_compute_sid: unrecognized SID %d\n",
- tsid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, tsid);
rc = -EINVAL;
goto out_unlock;
}
avdatum = avtab_search(&policydb.te_avtab, &avkey);
/* If no permanent rule, also check for enabled conditional rules */
- if(!avdatum) {
+ if (!avdatum) {
node = avtab_search_node(&policydb.te_cond_avtab, &avkey);
for (; node != NULL; node = avtab_search_node_next(node, specified)) {
if (node->key.specified & AVTAB_ENABLED) {
/* Convert the user. */
usrdatum = hashtab_search(args->newp->p_users.table,
- args->oldp->p_user_val_to_name[c->user - 1]);
- if (!usrdatum) {
+ args->oldp->p_user_val_to_name[c->user - 1]);
+ if (!usrdatum)
goto bad;
- }
c->user = usrdatum->value;
/* Convert the role. */
role = hashtab_search(args->newp->p_roles.table,
- args->oldp->p_role_val_to_name[c->role - 1]);
- if (!role) {
+ args->oldp->p_role_val_to_name[c->role - 1]);
+ if (!role)
goto bad;
- }
c->role = role->value;
/* Convert the type. */
typdatum = hashtab_search(args->newp->p_types.table,
- args->oldp->p_type_val_to_name[c->type - 1]);
- if (!typdatum) {
+ args->oldp->p_type_val_to_name[c->type - 1]);
+ if (!typdatum)
goto bad;
- }
c->type = typdatum->value;
rc = mls_convert_context(args->oldp, args->newp, c);
{
int i, fail = 0;
- for(i = 0; i < 4; i++)
- if(addr[i] != (input[i] & mask[i])) {
+ for (i = 0; i < 4; i++)
+ if (addr[i] != (input[i] & mask[i])) {
fail = 1;
break;
}
*/
int security_get_user_sids(u32 fromsid,
- char *username,
+ char *username,
u32 **sids,
u32 *nel)
{
* transition SIDs or task SIDs.
*/
int security_genfs_sid(const char *fstype,
- char *path,
+ char *path,
u16 sclass,
u32 *sid)
{
goto out;
}
- *names = kcalloc(*len, sizeof(char*), GFP_ATOMIC);
+ *names = kcalloc(*len, sizeof(char *), GFP_ATOMIC);
if (!*names)
goto err;
size_t name_len;
(*values)[i] = policydb.bool_val_to_struct[i]->state;
name_len = strlen(policydb.p_bool_val_to_name[i]) + 1;
- (*names)[i] = kmalloc(sizeof(char) * name_len, GFP_ATOMIC);
+ (*names)[i] = kmalloc(sizeof(char) * name_len, GFP_ATOMIC);
if (!(*names)[i])
goto err;
strncpy((*names)[i], policydb.p_bool_val_to_name[i], name_len);
audit_get_loginuid(current),
audit_get_sessionid(current));
}
- if (values[i]) {
+ if (values[i])
policydb.bool_val_to_struct[i]->state = 1;
- } else {
+ else
policydb.bool_val_to_struct[i]->state = 0;
- }
}
for (cur = policydb.cond_list; cur != NULL; cur = cur->next) {
POLICY_RDLOCK;
context1 = sidtab_search(&sidtab, sid);
if (!context1) {
- printk(KERN_ERR "security_sid_mls_copy: unrecognized SID "
- "%d\n", sid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, sid);
rc = -EINVAL;
goto out_unlock;
}
context2 = sidtab_search(&sidtab, mls_sid);
if (!context2) {
- printk(KERN_ERR "security_sid_mls_copy: unrecognized SID "
- "%d\n", mls_sid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, mls_sid);
rc = -EINVAL;
goto out_unlock;
}
nlbl_ctx = sidtab_search(&sidtab, nlbl_sid);
if (!nlbl_ctx) {
- printk(KERN_ERR
- "security_sid_mls_cmp: unrecognized SID %d\n",
- nlbl_sid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, nlbl_sid);
rc = -EINVAL;
goto out_slowpath;
}
xfrm_ctx = sidtab_search(&sidtab, xfrm_sid);
if (!xfrm_ctx) {
- printk(KERN_ERR
- "security_sid_mls_cmp: unrecognized SID %d\n",
- xfrm_sid);
+ printk(KERN_ERR "SELinux: %s: unrecognized SID %d\n",
+ __func__, xfrm_sid);
rc = -EINVAL;
goto out_slowpath;
}
match = hashtab_search(policydb.p_classes.table, class);
if (!match) {
- printk(KERN_ERR "%s: unrecognized class %s\n",
+ printk(KERN_ERR "SELinux: %s: unrecognized class %s\n",
__func__, class);
rc = -EINVAL;
goto out;
if (!rule) {
audit_log(actx, GFP_ATOMIC, AUDIT_SELINUX_ERR,
- "selinux_audit_rule_match: missing rule\n");
+ "selinux_audit_rule_match: missing rule\n");
return -ENOENT;
}
if (rule->au_seqno < latest_granting) {
audit_log(actx, GFP_ATOMIC, AUDIT_SELINUX_ERR,
- "selinux_audit_rule_match: stale rule\n");
+ "selinux_audit_rule_match: stale rule\n");
match = -ESTALE;
goto out;
}
ctxt = sidtab_search(&sidtab, sid);
if (!ctxt) {
audit_log(actx, GFP_ATOMIC, AUDIT_SELINUX_ERR,
- "selinux_audit_rule_match: unrecognized SID %d\n",
- sid);
+ "selinux_audit_rule_match: unrecognized SID %d\n",
+ sid);
match = -ENOENT;
goto out;
}
case AUDIT_OBJ_LEV_LOW:
case AUDIT_OBJ_LEV_HIGH:
level = ((field == AUDIT_SUBJ_SEN ||
- field == AUDIT_OBJ_LEV_LOW) ?
- &ctxt->range.level[0] : &ctxt->range.level[1]);
+ field == AUDIT_OBJ_LEV_LOW) ?
+ &ctxt->range.level[0] : &ctxt->range.level[1]);
switch (op) {
case AUDIT_EQUAL:
match = mls_level_eq(&rule->au_ctxt.range.level[0],
- level);
+ level);
break;
case AUDIT_NOT_EQUAL:
match = !mls_level_eq(&rule->au_ctxt.range.level[0],
- level);
+ level);
break;
case AUDIT_LESS_THAN:
match = (mls_level_dom(&rule->au_ctxt.range.level[0],
- level) &&
- !mls_level_eq(&rule->au_ctxt.range.level[0],
- level));
+ level) &&
+ !mls_level_eq(&rule->au_ctxt.range.level[0],
+ level));
break;
case AUDIT_LESS_THAN_OR_EQUAL:
match = mls_level_dom(&rule->au_ctxt.range.level[0],
- level);
+ level);
break;
case AUDIT_GREATER_THAN:
match = (mls_level_dom(level,
- &rule->au_ctxt.range.level[0]) &&
- !mls_level_eq(level,
- &rule->au_ctxt.range.level[0]));
+ &rule->au_ctxt.range.level[0]) &&
+ !mls_level_eq(level,
+ &rule->au_ctxt.range.level[0]));
break;
case AUDIT_GREATER_THAN_OR_EQUAL:
match = mls_level_dom(level,
- &rule->au_ctxt.range.level[0]);
+ &rule->au_ctxt.range.level[0]);
break;
}
}
int err;
err = avc_add_callback(aurule_avc_callback, AVC_CALLBACK_RESET,
- SECSID_NULL, SECSID_NULL, SECCLASS_NULL, 0);
+ SECSID_NULL, SECSID_NULL, SECCLASS_NULL, 0);
if (err)
panic("avc_add_callback() failed, error %d\n", err);
while (cur != NULL) {
ret = apply(cur->sid, &cur->context, args);
if (ret) {
- if (last) {
+ if (last)
last->next = cur->next;
- } else {
+ else
s->htable[i] = cur->next;
- }
-
temp = cur;
cur = cur->next;
context_destroy(&temp->context);
#include <net/xfrm.h>
#include <net/checksum.h>
#include <net/udp.h>
-#include <asm/semaphore.h>
#include <asm/atomic.h>
#include "avc.h"
if (!ckall)
break;
- }
- else if (*sid != ctx->ctx_sid)
+ } else if (*sid != ctx->ctx_sid)
return -EINVAL;
}
}
*/
void selinux_xfrm_policy_free(struct xfrm_sec_ctx *ctx)
{
- if (ctx)
- kfree(ctx);
+ kfree(ctx);
}
/*
void selinux_xfrm_state_free(struct xfrm_state *x)
{
struct xfrm_sec_ctx *ctx = x->security;
- if (ctx)
- kfree(ctx);
+ kfree(ctx);
}
/*
* Returns 0 if current can write the floor of the filesystem
* being mounted on, an error code otherwise.
*/
-static int smack_sb_mount(char *dev_name, struct nameidata *nd,
+static int smack_sb_mount(char *dev_name, struct path *path,
char *type, unsigned long flags, void *data)
{
- struct superblock_smack *sbp = nd->path.mnt->mnt_sb->s_security;
+ struct superblock_smack *sbp = path->mnt->mnt_sb->s_security;
return smk_curacc(sbp->smk_floor, MAY_WRITE);
}
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
+#include <linux/clk.h>
#include <linux/delay.h>
#include <sound/core.h>
#include <linux/mutex.h>
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/audio.h>
#include "pxa2xx-pcm.h"
static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;
+static struct clk *ac97_clk;
+#ifdef CONFIG_PXA27x
+static struct clk *ac97conf_clk;
+#endif
/*
* Beware PXA27x bugs:
gsr_bits = 0;
#ifdef CONFIG_PXA27x
/* PXA27x Developers Manual section 13.5.2.2.1 */
- pxa_set_cken(CKEN_AC97CONF, 1);
+ clk_enable(ac97conf_clk);
udelay(5);
- pxa_set_cken(CKEN_AC97CONF, 0);
+ clk_disable(ac97conf_clk);
GCR = GCR_COLD_RST;
udelay(50);
#else
if (platform_ops && platform_ops->suspend)
platform_ops->suspend(platform_ops->priv);
GCR |= GCR_ACLINK_OFF;
- pxa_set_cken(CKEN_AC97, 0);
+ clk_disable(ac97_clk);
return 0;
}
{
pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
- pxa_set_cken(CKEN_AC97, 1);
+ clk_enable(ac97_clk);
if (platform_ops && platform_ops->resume)
platform_ops->resume(platform_ops->priv);
snd_ac97_resume(pxa2xx_ac97_ac97);
#ifdef CONFIG_PXA27x
/* Use GPIO 113 as AC97 Reset on Bulverde */
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
+ ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
+ if (IS_ERR(ac97conf_clk)) {
+ ret = PTR_ERR(ac97conf_clk);
+ ac97conf_clk = NULL;
+ goto err;
+ }
#endif
- pxa_set_cken(CKEN_AC97, 1);
+
+ ac97_clk = clk_get(&dev->dev, "AC97CLK");
+ if (IS_ERR(ac97_clk)) {
+ ret = PTR_ERR(ac97_clk);
+ ac97_clk = NULL;
+ goto err;
+ }
+ clk_enable(ac97_clk);
ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
if (ret)
err:
if (card)
snd_card_free(card);
- if (CKEN & (1 << CKEN_AC97)) {
+ if (ac97_clk) {
GCR |= GCR_ACLINK_OFF;
free_irq(IRQ_AC97, NULL);
- pxa_set_cken(CKEN_AC97, 0);
+ clk_disable(ac97_clk);
+ clk_put(ac97_clk);
+ ac97_clk = NULL;
+ }
+#ifdef CONFIG_PXA27x
+ if (ac97conf_clk) {
+ clk_put(ac97conf_clk);
+ ac97conf_clk = NULL;
}
+#endif
return ret;
}
platform_set_drvdata(dev, NULL);
GCR |= GCR_ACLINK_OFF;
free_irq(IRQ_AC97, NULL);
- pxa_set_cken(CKEN_AC97, 0);
+ clk_disable(ac97_clk);
+ clk_put(ac97_clk);
+ ac97_clk = NULL;
+#ifdef CONFIG_PXA27x
+ clk_put(ac97conf_clk);
+ ac97conf_clk = NULL;
+#endif
}
return 0;
u16 status;
u16 rdy;
int count;
- const static u16 codec_ready[3] = {
+ static const u16 codec_ready[3] = {
SIS_AC97_STATUS_CODEC_READY,
SIS_AC97_STATUS_CODEC2_READY,
SIS_AC97_STATUS_CODEC3_READY,
static void sis_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
unsigned short val)
{
- const static u32 cmd[3] = {
+ static const u32 cmd[3] = {
SIS_AC97_CMD_CODEC_WRITE,
SIS_AC97_CMD_CODEC2_WRITE,
SIS_AC97_CMD_CODEC3_WRITE,
static unsigned short sis_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
- const static u32 cmd[3] = {
+ static const u32 cmd[3] = {
SIS_AC97_CMD_CODEC_READ,
SIS_AC97_CMD_CODEC2_READ,
SIS_AC97_CMD_CODEC3_READ,
/*
* ALSA defs
*/
-const static struct snd_pcm_hardware snd_ps3_pcm_hw = {
+static const struct snd_pcm_hardware snd_ps3_pcm_hw = {
.info = (SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_NONINTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID),
#include <sound/soc.h>
#include <sound/soc-dapm.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pio.h>
+#include <asm/hardware.h>
#include <asm/arch/gpio.h>
#include "../codecs/wm8731.h"
#define DBG(x...)
#endif
-#define AT91_PIO_TF1 (1 << (AT91_PIN_PB6 - PIN_BASE) % 32)
-#define AT91_PIO_TK1 (1 << (AT91_PIN_PB7 - PIN_BASE) % 32)
-#define AT91_PIO_TD1 (1 << (AT91_PIN_PB8 - PIN_BASE) % 32)
-#define AT91_PIO_RD1 (1 << (AT91_PIN_PB9 - PIN_BASE) % 32)
-#define AT91_PIO_RK1 (1 << (AT91_PIN_PB10 - PIN_BASE) % 32)
-#define AT91_PIO_RF1 (1 << (AT91_PIN_PB11 - PIN_BASE) % 32)
-
static struct clk *pck1_clk;
static struct clk *pllb_clk;
static int __init eti_b1_init(void)
{
int ret;
- u32 ssc_pio_lines;
struct at91_ssc_periph *ssc = eti_b1_dai.cpu_dai->private_data;
if (!request_mem_region(AT91RM9200_BASE_SSC1, SZ_16K, "soc-audio")) {
goto fail_io_unmap;
}
- ssc_pio_lines = AT91_PIO_TF1 | AT91_PIO_TK1 | AT91_PIO_TD1
- | AT91_PIO_RD1 /* | AT91_PIO_RK1 */ | AT91_PIO_RF1;
-
- /* Reset all PIO registers and assign lines to peripheral A */
- at91_sys_write(AT91_PIOB + PIO_PDR, ssc_pio_lines);
- at91_sys_write(AT91_PIOB + PIO_ODR, ssc_pio_lines);
- at91_sys_write(AT91_PIOB + PIO_IFDR, ssc_pio_lines);
- at91_sys_write(AT91_PIOB + PIO_CODR, ssc_pio_lines);
- at91_sys_write(AT91_PIOB + PIO_IDR, ssc_pio_lines);
- at91_sys_write(AT91_PIOB + PIO_MDDR, ssc_pio_lines);
- at91_sys_write(AT91_PIOB + PIO_PUDR, ssc_pio_lines);
- at91_sys_write(AT91_PIOB + PIO_ASR, ssc_pio_lines);
- at91_sys_write(AT91_PIOB + PIO_OWDR, ssc_pio_lines);
+ at91_set_A_periph(AT91_PIN_PB6, 0); /* TF1 */
+ at91_set_A_periph(AT91_PIN_PB7, 0); /* TK1 */
+ at91_set_A_periph(AT91_PIN_PB8, 0); /* TD1 */
+ at91_set_A_periph(AT91_PIN_PB9, 0); /* RD1 */
+/* at91_set_A_periph(AT91_PIN_PB10, 0);*/ /* RK1 */
+ at91_set_A_periph(AT91_PIN_PB11, 0); /* RF1 */
/*
* Set PCK1 parent to PLLB and its rate to 12 Mhz.
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
+#include <linux/clk.h>
#include <linux/delay.h>
#include <sound/core.h>
#include <linux/mutex.h>
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/audio.h>
#include "pxa2xx-pcm.h"
static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;
+static struct clk *ac97_clk;
+#ifdef CONFIG_PXA27x
+static struct clk *ac97conf_clk;
+#endif
/*
* Beware PXA27x bugs:
gsr_bits = 0;
#ifdef CONFIG_PXA27x
/* PXA27x Developers Manual section 13.5.2.2.1 */
- pxa_set_cken(CKEN_AC97CONF, 1);
+ clk_enable(ac97conf_clk);
udelay(5);
- pxa_set_cken(CKEN_AC97CONF, 0);
+ clk_disable(ac97conf_clk);
GCR = GCR_COLD_RST;
udelay(50);
#else
struct snd_soc_cpu_dai *dai)
{
GCR |= GCR_ACLINK_OFF;
- pxa_set_cken(CKEN_AC97, 0);
+ clk_disable(ac97_clk);
return 0;
}
/* Use GPIO 113 as AC97 Reset on Bulverde */
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
#endif
- pxa_set_cken(CKEN_AC97, 1);
+ clk_enable(ac97_clk);
return 0;
}
#ifdef CONFIG_PXA27x
/* Use GPIO 113 as AC97 Reset on Bulverde */
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
+
+ ac97conf_clk = clk_get(&pdev->dev, "AC97CONFCLK");
+ if (IS_ERR(ac97conf_clk)) {
+ ret = PTR_ERR(ac97conf_clk);
+ ac97conf_clk = NULL;
+ goto err_irq;
+ }
#endif
- pxa_set_cken(CKEN_AC97, 1);
+ ac97_clk = clk_get(&pdev->dev, "AC97CLK");
+ if (IS_ERR(ac97_clk)) {
+ ret = PTR_ERR(ac97_clk);
+ ac97_clk = NULL;
+ goto err_irq;
+ }
+ clk_enable(ac97_clk);
return 0;
- err:
- if (CKEN & (1 << CKEN_AC97)) {
- GCR |= GCR_ACLINK_OFF;
- free_irq(IRQ_AC97, NULL);
- pxa_set_cken(CKEN_AC97, 0);
+ err_irq:
+ GCR |= GCR_ACLINK_OFF;
+#ifdef CONFIG_PXA27x
+ if (ac97conf_clk) {
+ clk_put(ac97conf_clk);
+ ac97conf_clk = NULL;
}
+#endif
+ free_irq(IRQ_AC97, NULL);
+ err:
return ret;
}
{
GCR |= GCR_ACLINK_OFF;
free_irq(IRQ_AC97, NULL);
- pxa_set_cken(CKEN_AC97, 0);
+#ifdef CONFIG_PXA27x
+ clk_put(ac97conf_clk);
+ ac97conf_clk = NULL;
+#endif
+ clk_disable(ac97_clk);
+ clk_put(ac97_clk);
+ ac97_clk = NULL;
}
static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream,
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/audio.h>
#include "pxa2xx-pcm.h"
git.samba.org / sfrench / cifs-2.6.git / commitdiff