net: mscc: ocelot: add wave programming registers definitions
authorYangbo Lu <yangbo.lu@nxp.com>
Mon, 20 Apr 2020 02:46:48 +0000 (10:46 +0800)
committerDavid S. Miller <davem@davemloft.net>
Tue, 21 Apr 2020 22:38:33 +0000 (15:38 -0700)
Add wave programming registers definitions for Ocelot platforms.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/dsa/ocelot/felix_vsc9959.c
drivers/net/ethernet/mscc/ocelot_regs.c
include/soc/mscc/ocelot.h
include/soc/mscc/ocelot_ptp.h

index b4078f3c5c383d1b3f9a5bbb31d6992ff1657a08..4fe707ef54b8390fc61fb1eace23ff65d635c85c 100644 (file)
@@ -313,6 +313,8 @@ static const u32 vsc9959_ptp_regmap[] = {
        REG(PTP_PIN_TOD_SEC_MSB,           0x000004),
        REG(PTP_PIN_TOD_SEC_LSB,           0x000008),
        REG(PTP_PIN_TOD_NSEC,              0x00000c),
+       REG(PTP_PIN_WF_HIGH_PERIOD,        0x000014),
+       REG(PTP_PIN_WF_LOW_PERIOD,         0x000018),
        REG(PTP_CFG_MISC,                  0x0000a0),
        REG(PTP_CLK_CFG_ADJ_CFG,           0x0000a4),
        REG(PTP_CLK_CFG_ADJ_FREQ,          0x0000a8),
index b88b5899b22736fdc44f4dc7da04453282012d95..ed4dd01a41adc9ff5f99a6b07be79aa138550431 100644 (file)
@@ -239,6 +239,8 @@ static const u32 ocelot_ptp_regmap[] = {
        REG(PTP_PIN_TOD_SEC_MSB,           0x000004),
        REG(PTP_PIN_TOD_SEC_LSB,           0x000008),
        REG(PTP_PIN_TOD_NSEC,              0x00000c),
+       REG(PTP_PIN_WF_HIGH_PERIOD,        0x000014),
+       REG(PTP_PIN_WF_LOW_PERIOD,         0x000018),
        REG(PTP_CFG_MISC,                  0x0000a0),
        REG(PTP_CLK_CFG_ADJ_CFG,           0x0000a4),
        REG(PTP_CLK_CFG_ADJ_FREQ,          0x0000a8),
index 7d44d3508869da675341b7633104fdbae41d4776..31193ad3a545f2684510c6c8bbcc026428d758bb 100644 (file)
@@ -385,6 +385,8 @@ enum ocelot_reg {
        PTP_PIN_TOD_SEC_MSB,
        PTP_PIN_TOD_SEC_LSB,
        PTP_PIN_TOD_NSEC,
+       PTP_PIN_WF_HIGH_PERIOD,
+       PTP_PIN_WF_LOW_PERIOD,
        PTP_CFG_MISC,
        PTP_CLK_CFG_ADJ_CFG,
        PTP_CLK_CFG_ADJ_FREQ,
index f01b0ce4e4cbebbe862198617187eb95ffc43174..aae1570eecb17510434fcef545bc80cf5a4776fe 100644 (file)
@@ -17,6 +17,8 @@
 #define PTP_PIN_TOD_SEC_MSB_RSZ                PTP_PIN_CFG_RSZ
 #define PTP_PIN_TOD_SEC_LSB_RSZ                PTP_PIN_CFG_RSZ
 #define PTP_PIN_TOD_NSEC_RSZ           PTP_PIN_CFG_RSZ
+#define PTP_PIN_WF_HIGH_PERIOD_RSZ     PTP_PIN_CFG_RSZ
+#define PTP_PIN_WF_LOW_PERIOD_RSZ      PTP_PIN_CFG_RSZ
 
 #define PTP_PIN_CFG_DOM                        BIT(0)
 #define PTP_PIN_CFG_SYNC               BIT(2)