net/mlx5: Use the correct IPsec capability function for FPGA ops
authorRaed Salem <raeds@mellanox.com>
Wed, 23 Oct 2019 13:03:12 +0000 (16:03 +0300)
committerSaeed Mahameed <saeedm@mellanox.com>
Mon, 20 Apr 2020 21:20:19 +0000 (14:20 -0700)
Currently the IPsec acceleration capability function is also used
at IPsec fpga capable device code.

This could cause a future bug as the acceleration layer is agnostic
to the device implementing its API.

Fix by using the IPsec FPGA capability function instead of acceleration
layer capability function in case of FPGA IPsec only related operations.

Downstream patches will add support for Connect-X IPsec, this can avoid
a future bug.

Signed-off-by: Raed Salem <raeds@mellanox.com>
Reviewed-by: Boris Pismenny <borisp@mellanox.com>
Reviewed-by: Huy Nguyen <huyn@mellanox.com>
Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c
drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.h
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c

index b794888fa3ba66f51e5cfd09a7b53fbe97f32a28..c8736b6b41728e0ed7986e5332a7a04c024ce99c 100644 (file)
@@ -602,7 +602,7 @@ static bool mlx5_is_fpga_ipsec_rule(struct mlx5_core_dev *dev,
                                    const u32 *match_c,
                                    const u32 *match_v)
 {
-       u32 ipsec_dev_caps = mlx5_accel_ipsec_device_caps(dev);
+       u32 ipsec_dev_caps = mlx5_fpga_ipsec_device_caps(dev);
        bool ipv6_flow;
 
        ipv6_flow = mlx5_fs_is_outer_ipv6_flow(dev, match_c, match_v);
index 382985e65b488c03c8885a1982ef63c00c5f83ad..d01b1fc8e11b77ffbf0185446d0d82eed845ef68 100644 (file)
@@ -37,6 +37,7 @@
 #include "accel/ipsec.h"
 #include "fs_cmd.h"
 
+#ifdef CONFIG_MLX5_FPGA_IPSEC
 u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev);
 unsigned int mlx5_fpga_ipsec_counters_count(struct mlx5_core_dev *mdev);
 int mlx5_fpga_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
@@ -63,5 +64,17 @@ int mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
 
 const struct mlx5_flow_cmds *
 mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type);
+#else
+static inline u32 mlx5_fpga_ipsec_device_caps(struct mlx5_core_dev *mdev)
+{
+       return 0;
+}
 
-#endif /* __MLX5_FPGA_SADB_H__ */
+static inline const struct mlx5_flow_cmds *
+mlx5_fs_cmd_get_default_ipsec_fpga_cmds(enum fs_flow_table_type type)
+{
+       return mlx5_fs_cmd_get_default(type);
+}
+
+#endif /* CONFIG_MLX5_FPGA_IPSEC */
+#endif /* __MLX5_FPGA_IPSEC_H__ */
index d5defe09339a8a4e406027062b0e64f855f4acd2..2da45e9b9b6d019d99b51de27b8381a8f4b179a4 100644 (file)
@@ -2359,7 +2359,7 @@ static struct mlx5_flow_root_namespace
        struct mlx5_flow_root_namespace *root_ns;
        struct mlx5_flow_namespace *ns;
 
-       if (mlx5_accel_ipsec_device_caps(steering->dev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
+       if (mlx5_fpga_ipsec_device_caps(steering->dev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
            (table_type == FS_FT_NIC_RX || table_type == FS_FT_NIC_TX))
                cmds = mlx5_fs_cmd_get_default_ipsec_fpga_cmds(table_type);
 
@@ -2943,7 +2943,8 @@ int mlx5_init_fs(struct mlx5_core_dev *dev)
                        goto err;
        }
 
-       if (MLX5_IPSEC_DEV(dev) || MLX5_CAP_FLOWTABLE_NIC_TX(dev, ft_support)) {
+       if (mlx5_fpga_ipsec_device_caps(steering->dev) & MLX5_ACCEL_IPSEC_CAP_DEVICE ||
+           MLX5_CAP_FLOWTABLE_NIC_TX(dev, ft_support)) {
                err = init_egress_root_ns(steering);
                if (err)
                        goto err;