return sun_fdc->data_82072;
case 7: /* FD_DIR */
return sun_read_dir();
- };
+ }
panic("sun_82072_fd_inb: How did I get here?");
}
case 4: /* FD_STATUS */
sun_fdc->status_82072 = value;
break;
- };
+ }
return;
}
return sun_fdc->data_82077;
case 7: /* FD_DIR */
return sun_read_dir();
- };
+ }
panic("sun_82077_fd_inb: How did I get here?");
}
case 3: /* FD_TDR */
sun_fdc->tapectl_82077 = value;
break;
- };
+ }
return;
}
case 7: /* FD_DIR */
/* XXX: Is DCL on 0x80 in sun4m? */
return sbus_readb(&sun_fdc->dir_82077);
- };
+ }
panic("sun_82072_fd_inb: How did I get here?");
}
case 4: /* FD_STATUS */
sbus_writeb(value, &sun_fdc->status_82077);
break;
- };
+ }
return;
}
switch (size) {
case 4:
return xchg_u32(ptr, x);
- };
+ }
__xchg_called_with_bad_pointer();
return x;
}
return xchg32(ptr, x);
case 8:
return xchg64(ptr, x);
- };
+ }
__xchg_called_with_bad_pointer();
return x;
}
default:
return -EINVAL;
- };
+ }
return 0;
}
break;
default:
panic("Can't set AUXIO register on this machine.");
- };
+ }
spin_unlock_irqrestore(&auxio_lock, flags);
}
EXPORT_SYMBOL(set_auxio);
case 0x0:
bp->interleave = 16;
break;
- };
+ }
/* UK[10] is reserved, and UK[11] is not set for the SDRAM
* bank size definition.
me->name,
(int) (ELF_R_TYPE(rel[i].r_info) & 0xff));
return -ENOEXEC;
- };
+ }
}
return 0;
}
case 4:
*value = ret & 0xffffffff;
break;
- };
+ }
return PCIBIOS_SUCCESSFUL;
default:
break;
- };
+ }
}
if (!saw_io || !saw_mem) {
default:
type_string = "ECC Error";
break;
- };
+ }
printk("%s: IOMMU Error, type[%s]\n",
pbm->name, type_string);
default:
type_string = "ECC Error";
break;
- };
+ }
printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
"sz(%dK) vpg(%08lx)]\n",
pbm->name, i, type_string,
default:
chipset_name = "SCHIZO";
break;
- };
+ }
/* For SCHIZO, three OBP regs:
* 1) PBM controller regs
case 3:
iclr = reg_base + SYSIO_ICLR_SLOT3;
break;
- };
+ }
iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
}
default:
type_str = "ECC Error";
break;
- };
+ }
printk(KERN_ERR "%s: IOMMU Error, type[%s]\n",
pbm->name, type_str);
default:
return;
- };
+ }
val = upa_readq(cfg_reg);
if (val & (1UL << 14UL)) {
case 3:
iclr = reg_base + SYSIO_ICLR_SLOT3;
break;
- };
+ }
iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
}
default:
printk("UNKNOWN!\n");
break;
- };
+ }
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
default:
prom_printf("Unknown cpu type, halting.\n");
prom_halt();
- };
+ }
*(unsigned int *) (addr + 0) = insns[0];
wmb();
printk("UNKNOWN!\n");
BUG();
break;
- };
+ }
}
void cpu_panic(void)
printk("UNKNOWN!\n");
BUG();
break;
- };
+ }
}
/* Set this up early so that things like the scheduler can init
printk("UNKNOWN!\n");
BUG();
break;
- };
+ }
if (!ret) {
cpumask_set_cpu(cpu, &smp_commenced_mask);
default:
return -ENOSYS;
- };
+ }
return -ENOSYS;
}
default:
err = -ENOSYS;
goto out;
- };
+ }
}
if (call <= MSGCTL) {
switch (call) {
default:
err = -ENOSYS;
goto out;
- };
+ }
}
if (call <= SHMCTL) {
switch (call) {
default:
err = -ENOSYS;
goto out;
- };
+ }
} else {
err = -ENOSYS;
}
case CLOCK_EVT_MODE_UNUSED:
WARN_ON(1);
break;
- };
+ }
}
static struct clock_event_device sparc64_clockevent = {
return "warning resumable";
default:
return "unknown";
- };
+ }
}
static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
default:
BUG();
break;
- };
+ }
}
return __do_int_store(dst_addr, size, src_val, asi);
}
case ASI_SNFL:
asi &= ~0x08;
break;
- };
+ }
switch (dir) {
case load:
reg_addr = fetch_reg_addr(((insn>>25)&0x1f), regs);
default:
BUG();
break;
- };
+ }
*reg_addr = val_in;
}
break;
default:
BUG();
- };
+ }
}
static unsigned long index_to_divisor(unsigned int index)
default:
BUG();
- };
+ }
}
static unsigned long estar_to_divisor(unsigned long estar)
break;
default:
BUG();
- };
+ }
return ret;
}
break;
default:
BUG();
- };
+ }
return ret;
}
default:
BUG();
- };
+ }
reg = read_safari_cfg();
default:
return handshake_failure(vio);
- };
+ }
}
static int process_attr(struct vio_driver_state *vio, void *pkt)
left = edge32_tab_l[(rs1 >> 2) & 0x1].left;
right = edge32_tab_l[(rs2 >> 2) & 0x1].right;
break;
- };
+ }
if ((rs1 & ~0x7UL) == (rs2 & ~0x7UL))
rd_val = right & left;
tstate = regs->tstate & ~(TSTATE_XCC | TSTATE_ICC);
regs->tstate = tstate | (ccr << 32UL);
}
- };
+ }
}
static void array(struct pt_regs *regs, unsigned int insn, unsigned int opf)
case ARRAY32_OPF:
rd_val <<= 2;
- };
+ }
store_reg(regs, rd_val, RD(insn));
}
*fpd_regaddr(f, RD(insn)) = rd_val;
break;
}
- };
+ }
}
static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf)
*fpd_regaddr(f, RD(insn)) = rd_val;
break;
}
- };
+ }
}
static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf)
rd_val |= 1 << i;
}
break;
- };
+ }
maybe_flush_windows(0, 0, RD(insn), 0);
store_reg(regs, rd_val, RD(insn));
case BSHUFFLE_OPF:
bshuffle(regs, insn);
break;
- };
+ }
regs->tpc = regs->tnpc;
regs->tnpc += 4;
default:
break;
- };
+ }
memset(®s, 0, sizeof (regs));
regs.pc = pc;
prom_printf("paging_init: sparc_cpu_model = %d\n", sparc_cpu_model);
prom_printf("paging_init: Halting...\n");
prom_halt();
- };
+ }
/* Initialize the protection map with non-constant, MMU dependent values. */
protection_map[0] = PAGE_NONE;
ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
break;
- };
+ }
ktsb_descr[0].assoc = 1;
ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
return _PAGE_SZ512K_4V;
case 4 * 1024 * 1024:
return _PAGE_SZ4MB_4V;
- };
+ }
} else {
switch (sz) {
case 8 * 1024:
return _PAGE_SZ512K_4U;
case 4 * 1024 * 1024:
return _PAGE_SZ4MB_4U;
- };
+ }
}
}
default:
srmmu_modtype = Swift_ok;
break;
- };
+ }
BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
/* Some other Cypress revision, assume a 605. */
init_cypress_605(mod_rev);
break;
- };
+ }
return;
}
prom_printf("probe_vac: Didn't expect vac-linesize of %d, halting\n",
sun4c_vacinfo.linesize);
prom_halt();
- };
+ }
sun4c_flush_all();
sun4c_enable_vac();
prom_printf("Unhandled number of segmaps: %d\n",
num_segmaps);
prom_halt();
- };
+ }
switch (num_contexts) {
case 8:
/* Default, nothing to do. */
prom_printf("Unhandled number of contexts: %d\n",
num_contexts);
prom_halt();
- };
+ }
if (sun4c_vacinfo.do_hwflushes != 0) {
PATCH_INSN(vac_hwflush_patch1_on, vac_hwflush_patch1);
prom_printf("Impossible VAC linesize %d, halting...\n",
sun4c_vacinfo.linesize);
prom_halt();
- };
+ }
}
}
printk(KERN_ERR "TSB[%s:%d]: Impossible TSB size %lu, killing process.\n",
current->comm, current->pid, tsb_bytes);
do_exit(SIGSEGV);
- };
+ }
tte |= pte_sz_bits(page_sz);
if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
#endif
default:
BUG();
- };
+ }
hp->assoc = 1;
hp->num_ttes = tsb_bytes / 16;
hp->ctx_idx = 0;
#endif
default:
BUG();
- };
+ }
hp->tsb_base = tsb_paddr;
hp->resv = 0;
}
break;
default:
break;
- };
+ }
restore_current();
spin_unlock_irqrestore(&prom_lock, flags);
return i; /* Ugh, we could spin forever on unsupported proms ;( */
romvec->pv_romvers);
prom_halt();
break;
- };
+ }
prom_rev = romvec->pv_plugin_revision;
prom_prev = romvec->pv_printrev;
case PROM_V3:
ret = (*(romvec->v3_cpustart))(cpunode, (int) ctable_reg, ctx, pc);
break;
- };
+ }
restore_current();
spin_unlock_irqrestore(&prom_lock, flags);
git.samba.org / sfrench / cifs-2.6.git / commitdiff