[ARM] mmp: enable L2 in mmp2

Enable Tauros2 L2 in mmp2. Tauros2 L2 is shared in Marvell ARM cores.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>

diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 03f76cfc941cfca53f7e930bc1ded964e9585c29..db8936370b6beb38f02c8f6765a698b22b838443 100644 (file)
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -246,6 +246,8 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_TAUROS2=y
 CONFIG_ARM_L1_CACHE_SHIFT=5
 # CONFIG_ARM_ERRATA_411920 is not set
 CONFIG_COMMON_CLKDEV=y

diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index cca39929110fbc1dfe051f8e4ac21b92bb44ceec..e236ec0c54f6fa32be3b83741db2e1376c6f70a6 100644 (file)
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -15,6 +15,8 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
+#include <asm/hardware/cache-tauros2.h>
+
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
 #include <mach/regs-apmu.h>
@@ -99,6 +101,9 @@ static struct clk_lookup mmp2_clkregs[] = {
 static int __init mmp2_init(void)
 {
        if (cpu_is_mmp2()) {
+#ifdef CONFIG_CACHE_TAUROS2
+               tauros2_init();
+#endif
                mfp_init_base(MFPR_VIRT_BASE);
                mfp_init_addr(mmp2_addr_map);
                clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 5bd7c89a604515273212ea304a02353ab9af5c39..698912602387fe66720457432698df51d703444f 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -769,7 +769,7 @@ config CACHE_L2X0
 
 config CACHE_TAUROS2
        bool "Enable the Tauros2 L2 cache controller"
-       depends on ARCH_DOVE
+       depends on (ARCH_DOVE || ARCH_MMP)
        default y
        select OUTER_CACHE
        help