drm/amdgpu: add VCN2.0 decode ib test

Add internal register offset for registers involving in ib tests

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 5dbd975bac09545b6e5083250ca1d9fa06f5d5d0..1d575e2e701be30b928e26a8250773dbc54d81c8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -349,14 +349,14 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 
        ib = &job->ibs[0];
        addr = amdgpu_bo_gpu_offset(bo);
-       ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);
+       ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
        ib->ptr[1] = addr;
-       ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);
+       ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
        ib->ptr[3] = addr >> 32;
-       ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);
+       ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
        ib->ptr[5] = 0;
        for (i = 6; i < 16; i += 2) {
-               ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);
+               ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
                ib->ptr[i+1] = 0;
        }
        ib->length_dw = 16;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index b80fc139eb7b4bfac577e8dbd51da25a0b470164..b14655a0e1dbeb775932f53e518c398837eee9d7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -25,7 +25,7 @@
 #define __AMDGPU_VCN_H__
 
 #define AMDGPU_VCN_STACK_SIZE          (128*1024)
-#define AMDGPU_VCN_CONTEXT_SIZE        (512*1024)
+#define AMDGPU_VCN_CONTEXT_SIZE        (512*1024)
 
 #define AMDGPU_VCN_FIRMWARE_OFFSET     256
 #define AMDGPU_VCN_MAX_ENC_RINGS       3
@@ -88,6 +88,10 @@ struct dpg_pause_state {
 };
 
 struct amdgpu_vcn_reg{
+       unsigned        data0;
+       unsigned        data1;
+       unsigned        cmd;
+       unsigned        nop;
        unsigned        scratch9;
 };
 

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index bab900653a0bda3aed4a3c24e5b96304d9a9fd88..2a2c40cf32c87694dea0902360f827b84f5d8426 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -130,6 +130,14 @@ static int vcn_v1_0_sw_init(void *handle)
 
        adev->vcn.internal.scratch9 = adev->vcn.external.scratch9 =
                SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
+       adev->vcn.internal.data0 = adev->vcn.external.data0 =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
+       adev->vcn.internal.data1 = adev->vcn.external.data1 =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
+       adev->vcn.internal.cmd = adev->vcn.external.cmd =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
+       adev->vcn.internal.nop = adev->vcn.external.nop =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
 
        for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
                ring = &adev->vcn.ring_enc[i];