MIPS: Add cases for CPU_I6400

Add a CPU_I6400 case to various switch statements, doing the same thing
as for CPU_P5600.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10635/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index d41e8e2848253146bd12ceed71794ea51bd488b5..abee2bfd10dc1dce791ae5691417303d58b08ce6 100644 (file)
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -77,6 +77,10 @@ static inline int __pure __get_cpu_type(const int cpu_type)
         */
 #endif
 
+#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
+       case CPU_I6400:
+#endif
+
 #ifdef CONFIG_SYS_HAS_CPU_R3000
        case CPU_R2000:
        case CPU_R3000:

diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index e4f62b7875d24b068ee44000b1ad7f8b7b5a38d4..ab1478d5a4db1b247caa94527925da0d005adf10 100644 (file)
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -196,6 +196,7 @@ void __init check_wait(void)
        case CPU_INTERAPTIV:
        case CPU_M5150:
        case CPU_QEMU_GENERIC:
+       case CPU_I6400:
                cpu_wait = r4k_wait;
                if (read_c0_config7() & MIPS_CONF7_WII)
                        cpu_wait = r4k_wait_irqoff;

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index cc1b6fadf08989a8048a6dc304a9f58f1c29228e..d7b8dd43147a44e7a400efc4b5e2019e015f82b9 100644 (file)
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1556,6 +1556,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
 #endif
                break;
        case CPU_P5600:
+       case CPU_I6400:
                /* 8-bit event numbers */
                raw_id = config & 0x1ff;
                base_id = raw_id & 0xff;
@@ -1717,6 +1718,11 @@ init_hw_perf_events(void)
                mipspmu.general_event_map = &mipsxxcore_event_map2;
                mipspmu.cache_event_map = &mipsxxcore_cache_map2;
                break;
+       case CPU_I6400:
+               mipspmu.name = "mips/I6400";
+               mipspmu.general_event_map = &mipsxxcore_event_map2;
+               mipspmu.cache_event_map = &mipsxxcore_cache_map2;
+               break;
        case CPU_1004K:
                mipspmu.name = "mips/1004K";
                mipspmu.general_event_map = &mipsxxcore_event_map;

diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 06147179a175b7ea5d8c02a502e4b20653dd8b3d..f63a289977cc5f34d5ee52daf61f1065153166a1 100644 (file)
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -267,6 +267,7 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
 
        /* CPUs which do not require the workaround */
        case CPU_P5600:
+       case CPU_I6400:
                return 0;
 
        default:
@@ -671,6 +672,7 @@ static int __init cps_pm_init(void)
        case CPU_PROAPTIV:
        case CPU_M5150:
        case CPU_P5600:
+       case CPU_I6400:
                stype_intervention = 0x2;
                stype_memory = 0x3;
                stype_ordering = 0x10;

diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index d1168d7c31e8ef37c51568b93cf676e9a6c3ef81..8489c88f9932310b7732e1ec396ca2fb2000078c 100644 (file)
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -209,6 +209,7 @@ void spram_config(void)
        case CPU_PROAPTIV:
        case CPU_P5600:
        case CPU_QEMU_GENERIC:
+       case CPU_I6400:
                config0 = read_c0_config();
                /* FIXME: addresses are Malta specific */
                if (config0 & (1<<24)) {

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 8ea28e6ab37dead56439dc37871b6b18e8ec02d5..01da120d75c44a352b7b8ea58bf954a0a56add58 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1651,6 +1651,7 @@ static inline void parity_protection_init(void)
        case CPU_PROAPTIV:
        case CPU_P5600:
        case CPU_QEMU_GENERIC:
+       case CPU_I6400:
                {
 #define ERRCTL_PE      0x80000000
 #define ERRCTL_L2P     0x00800000

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fbea4432f3f23fe3d44d278f48d28fd78797d580..5d3a25e1cfaea62cf7859f3408e3d101f9bf4060 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1276,6 +1276,7 @@ static void probe_pcache(void)
        case CPU_PROAPTIV:
        case CPU_M5150:
        case CPU_QEMU_GENERIC:
+       case CPU_I6400:
                if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
                    (c->icache.waysize > PAGE_SIZE))
                        c->icache.flags |= MIPS_CACHE_ALIASES;

diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 81f58958cf081bf8f307f47c1dd4a3a93e82c5cd..3c9ec3ddca845dccac627dcf13fec4a7b62ee272 100644 (file)
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -91,6 +91,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
        case CPU_INTERAPTIV:
        case CPU_PROAPTIV:
        case CPU_P5600:
+       case CPU_I6400:
        case CPU_M5150:
        case CPU_LOONGSON1:
        case CPU_SB1:

diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 6a6e2cc55b8926975fb17f9f54649a0a634018c5..8f988a61b7a850526e623733a969b405f7755fce 100644 (file)
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -392,6 +392,10 @@ static int __init mipsxx_init(void)
                op_model_mipsxx_ops.cpu_type = "mips/P5600";
                break;
 
+       case CPU_I6400:
+               op_model_mipsxx_ops.cpu_type = "mips/I6400";
+               break;
+
        case CPU_M5150:
                op_model_mipsxx_ops.cpu_type = "mips/M5150";
                break;