clk: rockchip: fix rk3188 USB HSIC PHY clock divider

The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11).

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index c24986970815d8cd84f5b7fe42900675e720f1bd..22dccc6cd6648611397ff8b232ff8d37c8c6f5e9 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -664,7 +664,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
                        RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
                        RK2928_CLKGATE_CON(3), 6, GFLAGS),
        DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
-                       RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),
+                       RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
 
        MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
                        RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),