2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/clk-provider.h>
25 #define BRRx_MASK(x) (0x3FF & x)
27 static struct rsnd_mod_ops adg_ops = {
32 struct clk *clk[CLKMAX];
33 struct clk *clkout[CLKOUTMAX];
34 struct clk_onecell_data onecell;
41 int rbga_rate_for_441khz; /* RBGA */
42 int rbgb_rate_for_48khz; /* RBGB */
45 #define LRCLK_ASYNC (1 << 0)
46 #define AUDIO_OUT_48 (1 << 1)
47 #define adg_mode_flags(adg) (adg->flags)
49 #define for_each_rsnd_clk(pos, adg, i) \
52 ((pos) = adg->clk[i]); \
54 #define for_each_rsnd_clkout(pos, adg, i) \
57 ((pos) = adg->clkout[i]); \
59 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
61 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
68 for (i = 3; i >= 0; i--) {
70 if (0 == (div % ratio))
71 return (u32)((i << 8) | ((div / ratio) - 1));
77 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
79 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io);
80 int id = rsnd_mod_id(ssi_mod);
83 if (rsnd_ssi_is_pin_sharing(io)) {
98 return (0x6 + ws) << 8;
101 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
102 struct rsnd_dai_stream *io,
103 unsigned int target_rate,
104 unsigned int *target_val,
105 unsigned int *target_en)
107 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
108 struct device *dev = rsnd_priv_to_dev(priv);
109 int idx, sel, div, step;
110 unsigned int val, en;
111 unsigned int min, diff;
112 unsigned int sel_rate[] = {
113 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
114 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
115 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
116 adg->rbga_rate_for_441khz, /* 0011: RBGA */
117 adg->rbgb_rate_for_48khz, /* 0100: RBGB */
123 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
130 for (div = 2; div <= 98304; div += step) {
131 diff = abs(target_rate - sel_rate[sel] / div);
133 val = (sel << 8) | idx;
135 en = 1 << (sel + 1); /* fixme */
139 * step of 0_0000 / 0_0001 / 0_1101
142 if ((idx > 2) && (idx % 2))
153 dev_err(dev, "no Input clock\n");
162 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
163 struct rsnd_dai_stream *io,
164 unsigned int in_rate,
165 unsigned int out_rate,
166 u32 *in, u32 *out, u32 *en)
168 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
169 unsigned int target_rate;
175 /* default = SSI WS */
177 _out = rsnd_adg_ssi_ws_timing_gen2(io);
182 if (runtime->rate != in_rate) {
183 target_rate = out_rate;
185 } else if (runtime->rate != out_rate) {
186 target_rate = in_rate;
191 __rsnd_adg_get_timesel_ratio(priv, io,
203 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
204 struct rsnd_dai_stream *io)
206 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod);
207 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
208 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
209 int id = rsnd_mod_id(cmd_mod);
210 int shift = (id % 2) ? 16 : 0;
213 rsnd_adg_get_timesel_ratio(priv, io,
214 rsnd_src_get_in_rate(priv, io),
215 rsnd_src_get_out_rate(priv, io),
219 mask = 0xffff << shift;
221 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
226 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
227 struct rsnd_dai_stream *io,
228 unsigned int in_rate,
229 unsigned int out_rate)
231 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
232 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
233 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
236 int id = rsnd_mod_id(src_mod);
237 int shift = (id % 2) ? 16 : 0;
239 rsnd_mod_confirm_src(src_mod);
241 rsnd_adg_get_timesel_ratio(priv, io,
247 mask = 0xffff << shift;
251 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
252 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
255 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
256 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
259 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
260 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
263 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
264 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
267 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
268 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
273 rsnd_mod_bset(adg_mod, DIV_EN, en, en);
278 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
280 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
281 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
282 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
283 int id = rsnd_mod_id(ssi_mod);
284 int shift = (id % 4) * 8;
285 u32 mask = 0xFF << shift;
287 rsnd_mod_confirm_ssi(ssi_mod);
292 * SSI 8 is not connected to ADG.
293 * it works with SSI 7
300 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
303 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
306 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
311 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate)
313 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
314 struct device *dev = rsnd_priv_to_dev(priv);
324 dev_dbg(dev, "request clock = %d\n", rate);
327 * find suitable clock from
328 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
330 for_each_rsnd_clk(clk, adg, i) {
331 if (rate == clk_get_rate(clk))
336 * find divided clock from BRGA/BRGB
338 if (rate == adg->rbga_rate_for_441khz)
341 if (rate == adg->rbgb_rate_for_48khz)
347 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod)
349 rsnd_adg_set_ssi_clk(ssi_mod, 0);
354 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
356 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
357 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
358 struct device *dev = rsnd_priv_to_dev(priv);
359 struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
363 data = rsnd_adg_clk_query(priv, rate);
367 rsnd_adg_set_ssi_clk(ssi_mod, data);
369 if (adg_mode_flags(adg) & LRCLK_ASYNC) {
370 if (adg_mode_flags(adg) & AUDIO_OUT_48)
373 if (0 == (rate % 8000))
377 rsnd_mod_bset(adg_mod, BRGCKR, 0x80FF0000, adg->ckr | ckr);
378 rsnd_mod_write(adg_mod, BRRA, adg->rbga);
379 rsnd_mod_write(adg_mod, BRRB, adg->rbgb);
381 dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
382 rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
388 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable)
390 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
391 struct device *dev = rsnd_priv_to_dev(priv);
395 for_each_rsnd_clk(clk, adg, i) {
398 ret = clk_prepare_enable(clk);
400 clk_disable_unprepare(clk);
403 dev_warn(dev, "can't use clk %d\n", i);
407 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
408 struct rsnd_adg *adg)
410 struct device *dev = rsnd_priv_to_dev(priv);
412 static const char * const clk_name[] = {
420 for (i = 0; i < CLKMAX; i++) {
421 clk = devm_clk_get(dev, clk_name[i]);
422 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
425 for_each_rsnd_clk(clk, adg, i)
426 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
429 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
430 struct rsnd_adg *adg)
433 struct device *dev = rsnd_priv_to_dev(priv);
434 struct device_node *np = dev->of_node;
435 struct property *prop;
436 u32 ckr, rbgx, rbga, rbgb;
439 u32 req_rate[REQ_SIZE] = {};
441 unsigned long req_48kHz_rate, req_441kHz_rate;
443 const char *parent_clk_name = NULL;
444 static const char * const clkout_name[] = {
445 [CLKOUT] = "audio_clkout",
446 [CLKOUT1] = "audio_clkout1",
447 [CLKOUT2] = "audio_clkout2",
448 [CLKOUT3] = "audio_clkout3",
458 rbga = 2; /* default 1/6 */
459 rbgb = 2; /* default 1/6 */
462 * ADG supports BRRA/BRRB output only
463 * this means all clkout0/1/2/3 will be same rate
465 prop = of_find_property(np, "clock-frequency", NULL);
467 goto rsnd_adg_get_clkout_end;
469 req_size = prop->length / sizeof(u32);
471 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
474 for (i = 0; i < req_size; i++) {
475 if (0 == (req_rate[i] % 44100))
476 req_441kHz_rate = req_rate[i];
477 if (0 == (req_rate[i] % 48000))
478 req_48kHz_rate = req_rate[i];
481 if (req_rate[0] % 48000 == 0)
482 adg->flags = AUDIO_OUT_48;
484 if (of_get_property(np, "clkout-lr-asynchronous", NULL))
485 adg->flags = LRCLK_ASYNC;
488 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
489 * have 44.1kHz or 48kHz base clocks for now.
491 * SSI itself can divide parent clock by 1/1 - 1/16
493 * rsnd_adg_ssi_clk_try_start()
494 * rsnd_ssi_master_clk_start()
496 adg->rbga_rate_for_441khz = 0;
497 adg->rbgb_rate_for_48khz = 0;
498 for_each_rsnd_clk(clk, adg, i) {
499 rate = clk_get_rate(clk);
501 if (0 == rate) /* not used */
505 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
508 div = rate / req_441kHz_rate;
509 rbgx = rsnd_adg_calculate_rbgx(div);
510 if (BRRx_MASK(rbgx) == rbgx) {
512 adg->rbga_rate_for_441khz = rate / div;
513 ckr |= brg_table[i] << 20;
514 if (req_441kHz_rate &&
515 !(adg_mode_flags(adg) & AUDIO_OUT_48))
516 parent_clk_name = __clk_get_name(clk);
521 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
524 div = rate / req_48kHz_rate;
525 rbgx = rsnd_adg_calculate_rbgx(div);
526 if (BRRx_MASK(rbgx) == rbgx) {
528 adg->rbgb_rate_for_48khz = rate / div;
529 ckr |= brg_table[i] << 16;
530 if (req_48kHz_rate &&
531 (adg_mode_flags(adg) & AUDIO_OUT_48))
532 parent_clk_name = __clk_get_name(clk);
538 * ADG supports BRRA/BRRB output only.
539 * this means all clkout0/1/2/3 will be * same rate
542 of_property_read_u32(np, "#clock-cells", &count);
547 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
548 parent_clk_name, 0, req_rate[0]);
550 adg->clkout[CLKOUT] = clk;
551 of_clk_add_provider(np, of_clk_src_simple_get, clk);
558 for (i = 0; i < CLKOUTMAX; i++) {
559 clk = clk_register_fixed_rate(dev, clkout_name[i],
563 adg->clkout[i] = clk;
565 adg->onecell.clks = adg->clkout;
566 adg->onecell.clk_num = CLKOUTMAX;
567 of_clk_add_provider(np, of_clk_src_onecell_get,
571 rsnd_adg_get_clkout_end:
576 for_each_rsnd_clkout(clk, adg, i)
577 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
578 dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
582 int rsnd_adg_probe(struct rsnd_priv *priv)
584 struct rsnd_adg *adg;
585 struct device *dev = rsnd_priv_to_dev(priv);
588 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
590 dev_err(dev, "ADG allocate failed\n");
594 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops,
599 rsnd_adg_get_clkin(priv, adg);
600 rsnd_adg_get_clkout(priv, adg);
604 rsnd_adg_clk_enable(priv);
609 void rsnd_adg_remove(struct rsnd_priv *priv)
611 struct device *dev = rsnd_priv_to_dev(priv);
612 struct device_node *np = dev->of_node;
614 of_clk_del_provider(np);
616 rsnd_adg_clk_disable(priv);