sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009-12 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/gcd.h>
  20 #include <linux/i2c.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/slab.h>
  25 #include <sound/core.h>
  26 #include <sound/jack.h>
  27 #include <sound/pcm.h>
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <sound/initval.h>
  31 #include <sound/tlv.h>
  32 #include <trace/events/asoc.h>
  33
  34 #include <linux/mfd/wm8994/core.h>
  35 #include <linux/mfd/wm8994/registers.h>
  36 #include <linux/mfd/wm8994/pdata.h>
  37 #include <linux/mfd/wm8994/gpio.h>
  38
  39 #include "wm8994.h"
  40 #include "wm_hubs.h"
  41
  42 #define WM1811_JACKDET_MODE_NONE  0x0000
  43 #define WM1811_JACKDET_MODE_JACK  0x0100
  44 #define WM1811_JACKDET_MODE_MIC   0x0080
  45 #define WM1811_JACKDET_MODE_AUDIO 0x0180
  46
  47 #define WM8994_NUM_DRC 3
  48 #define WM8994_NUM_EQ  3
  49
  50 static struct {
  51         unsigned int reg;
  52         unsigned int mask;
  53 } wm8994_vu_bits[] = {
  54         { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  55         { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  56         { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  57         { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  58         { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
  59         { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
  60         { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  61         { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  62         { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  63         { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  64
  65         { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
  66         { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
  67         { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
  68         { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
  69         { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
  70         { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
  71         { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
  72         { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
  73         { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
  74         { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  75         { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
  76         { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  77         { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
  78         { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
  79         { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
  80         { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
  81 };
  82
  83 static int wm8994_drc_base[] = {
  84         WM8994_AIF1_DRC1_1,
  85         WM8994_AIF1_DRC2_1,
  86         WM8994_AIF2_DRC_1,
  87 };
  88
  89 static int wm8994_retune_mobile_base[] = {
  90         WM8994_AIF1_DAC1_EQ_GAINS_1,
  91         WM8994_AIF1_DAC2_EQ_GAINS_1,
  92         WM8994_AIF2_EQ_GAINS_1,
  93 };
  94
  95 static const struct wm8958_micd_rate micdet_rates[] = {
  96         { 32768,       true,  1, 4 },
  97         { 32768,       false, 1, 1 },
  98         { 44100 * 256, true,  7, 10 },
  99         { 44100 * 256, false, 7, 10 },
 100 };
 101
 102 static const struct wm8958_micd_rate jackdet_rates[] = {
 103         { 32768,       true,  0, 1 },
 104         { 32768,       false, 0, 1 },
 105         { 44100 * 256, true,  10, 10 },
 106         { 44100 * 256, false, 7, 8 },
 107 };
 108
 109 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
 110 {
 111         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 112         struct wm8994 *control = wm8994->wm8994;
 113         int best, i, sysclk, val;
 114         bool idle;
 115         const struct wm8958_micd_rate *rates;
 116         int num_rates;
 117
 118         idle = !wm8994->jack_mic;
 119
 120         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
 121         if (sysclk & WM8994_SYSCLK_SRC)
 122                 sysclk = wm8994->aifclk[1];
 123         else
 124                 sysclk = wm8994->aifclk[0];
 125
 126         if (control->pdata.micd_rates) {
 127                 rates = control->pdata.micd_rates;
 128                 num_rates = control->pdata.num_micd_rates;
 129         } else if (wm8994->jackdet) {
 130                 rates = jackdet_rates;
 131                 num_rates = ARRAY_SIZE(jackdet_rates);
 132         } else {
 133                 rates = micdet_rates;
 134                 num_rates = ARRAY_SIZE(micdet_rates);
 135         }
 136
 137         best = 0;
 138         for (i = 0; i < num_rates; i++) {
 139                 if (rates[i].idle != idle)
 140                         continue;
 141                 if (abs(rates[i].sysclk - sysclk) <
 142                     abs(rates[best].sysclk - sysclk))
 143                         best = i;
 144                 else if (rates[best].idle != idle)
 145                         best = i;
 146         }
 147
 148         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
 149                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
 150
 151         dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
 152                 rates[best].start, rates[best].rate, sysclk,
 153                 idle ? "idle" : "active");
 154
 155         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
 156                             WM8958_MICD_BIAS_STARTTIME_MASK |
 157                             WM8958_MICD_RATE_MASK, val);
 158 }
 159
 160 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 161 {
 162         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 163         int rate;
 164         int reg1 = 0;
 165         int offset;
 166
 167         if (aif)
 168                 offset = 4;
 169         else
 170                 offset = 0;
 171
 172         switch (wm8994->sysclk[aif]) {
 173         case WM8994_SYSCLK_MCLK1:
 174                 rate = wm8994->mclk[0];
 175                 break;
 176
 177         case WM8994_SYSCLK_MCLK2:
 178                 reg1 |= 0x8;
 179                 rate = wm8994->mclk[1];
 180                 break;
 181
 182         case WM8994_SYSCLK_FLL1:
 183                 reg1 |= 0x10;
 184                 rate = wm8994->fll[0].out;
 185                 break;
 186
 187         case WM8994_SYSCLK_FLL2:
 188                 reg1 |= 0x18;
 189                 rate = wm8994->fll[1].out;
 190                 break;
 191
 192         default:
 193                 return -EINVAL;
 194         }
 195
 196         if (rate >= 13500000) {
 197                 rate /= 2;
 198                 reg1 |= WM8994_AIF1CLK_DIV;
 199
 200                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 201                         aif + 1, rate);
 202         }
 203
 204         wm8994->aifclk[aif] = rate;
 205
 206         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 207                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 208                             reg1);
 209
 210         return 0;
 211 }
 212
 213 static int configure_clock(struct snd_soc_codec *codec)
 214 {
 215         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 216         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 217         int change, new;
 218
 219         /* Bring up the AIF clocks first */
 220         configure_aif_clock(codec, 0);
 221         configure_aif_clock(codec, 1);
 222
 223         /* Then switch CLK_SYS over to the higher of them; a change
 224          * can only happen as a result of a clocking change which can
 225          * only be made outside of DAPM so we can safely redo the
 226          * clocking.
 227          */
 228
 229         /* If they're equal it doesn't matter which is used */
 230         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
 231                 wm8958_micd_set_rate(codec);
 232                 return 0;
 233         }
 234
 235         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 236                 new = WM8994_SYSCLK_SRC;
 237         else
 238                 new = 0;
 239
 240         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 241                                      WM8994_SYSCLK_SRC, new);
 242         if (change)
 243                 snd_soc_dapm_sync(dapm);
 244
 245         wm8958_micd_set_rate(codec);
 246
 247         return 0;
 248 }
 249
 250 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 251                          struct snd_soc_dapm_widget *sink)
 252 {
 253         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
 254         int reg = snd_soc_read(codec, WM8994_CLOCKING_1);
 255         const char *clk;
 256
 257         /* Check what we're currently using for CLK_SYS */
 258         if (reg & WM8994_SYSCLK_SRC)
 259                 clk = "AIF2CLK";
 260         else
 261                 clk = "AIF1CLK";
 262
 263         return strcmp(source->name, clk) == 0;
 264 }
 265
 266 static const char *sidetone_hpf_text[] = {
 267         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 268 };
 269
 270 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
 271                             WM8994_SIDETONE, 7, sidetone_hpf_text);
 272
 273 static const char *adc_hpf_text[] = {
 274         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 275 };
 276
 277 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
 278                             WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
 279
 280 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
 281                             WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
 282
 283 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
 284                             WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
 285
 286 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 287 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 288 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 289 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 290 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 291 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 292 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 293
 294 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 295         SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
 296                 snd_soc_get_volsw, wm8994_put_drc_sw)
 297
 298 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 299                              struct snd_ctl_elem_value *ucontrol)
 300 {
 301         struct soc_mixer_control *mc =
 302                 (struct soc_mixer_control *)kcontrol->private_value;
 303         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 304         int mask, ret;
 305
 306         /* Can't enable both ADC and DAC paths simultaneously */
 307         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 308                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 309                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 310         else
 311                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 312
 313         ret = snd_soc_read(codec, mc->reg);
 314         if (ret < 0)
 315                 return ret;
 316         if (ret & mask)
 317                 return -EINVAL;
 318
 319         return snd_soc_put_volsw(kcontrol, ucontrol);
 320 }
 321
 322 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 323 {
 324         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 325         struct wm8994 *control = wm8994->wm8994;
 326         struct wm8994_pdata *pdata = &control->pdata;
 327         int base = wm8994_drc_base[drc];
 328         int cfg = wm8994->drc_cfg[drc];
 329         int save, i;
 330
 331         /* Save any enables; the configuration should clear them. */
 332         save = snd_soc_read(codec, base);
 333         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 334                 WM8994_AIF1ADC1R_DRC_ENA;
 335
 336         for (i = 0; i < WM8994_DRC_REGS; i++)
 337                 snd_soc_update_bits(codec, base + i, 0xffff,
 338                                     pdata->drc_cfgs[cfg].regs[i]);
 339
 340         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 341                              WM8994_AIF1ADC1L_DRC_ENA |
 342                              WM8994_AIF1ADC1R_DRC_ENA, save);
 343 }
 344
 345 /* Icky as hell but saves code duplication */
 346 static int wm8994_get_drc(const char *name)
 347 {
 348         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 349                 return 0;
 350         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 351                 return 1;
 352         if (strcmp(name, "AIF2DRC Mode") == 0)
 353                 return 2;
 354         return -EINVAL;
 355 }
 356
 357 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 358                                struct snd_ctl_elem_value *ucontrol)
 359 {
 360         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 361         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 362         struct wm8994 *control = wm8994->wm8994;
 363         struct wm8994_pdata *pdata = &control->pdata;
 364         int drc = wm8994_get_drc(kcontrol->id.name);
 365         int value = ucontrol->value.enumerated.item[0];
 366
 367         if (drc < 0)
 368                 return drc;
 369
 370         if (value >= pdata->num_drc_cfgs)
 371                 return -EINVAL;
 372
 373         wm8994->drc_cfg[drc] = value;
 374
 375         wm8994_set_drc(codec, drc);
 376
 377         return 0;
 378 }
 379
 380 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 381                                struct snd_ctl_elem_value *ucontrol)
 382 {
 383         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 384         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 385         int drc = wm8994_get_drc(kcontrol->id.name);
 386
 387         if (drc < 0)
 388                 return drc;
 389         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 390
 391         return 0;
 392 }
 393
 394 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 395 {
 396         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 397         struct wm8994 *control = wm8994->wm8994;
 398         struct wm8994_pdata *pdata = &control->pdata;
 399         int base = wm8994_retune_mobile_base[block];
 400         int iface, best, best_val, save, i, cfg;
 401
 402         if (!pdata || !wm8994->num_retune_mobile_texts)
 403                 return;
 404
 405         switch (block) {
 406         case 0:
 407         case 1:
 408                 iface = 0;
 409                 break;
 410         case 2:
 411                 iface = 1;
 412                 break;
 413         default:
 414                 return;
 415         }
 416
 417         /* Find the version of the currently selected configuration
 418          * with the nearest sample rate. */
 419         cfg = wm8994->retune_mobile_cfg[block];
 420         best = 0;
 421         best_val = INT_MAX;
 422         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 423                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 424                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 425                     abs(pdata->retune_mobile_cfgs[i].rate
 426                         - wm8994->dac_rates[iface]) < best_val) {
 427                         best = i;
 428                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 429                                        - wm8994->dac_rates[iface]);
 430                 }
 431         }
 432
 433         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 434                 block,
 435                 pdata->retune_mobile_cfgs[best].name,
 436                 pdata->retune_mobile_cfgs[best].rate,
 437                 wm8994->dac_rates[iface]);
 438
 439         /* The EQ will be disabled while reconfiguring it, remember the
 440          * current configuration.
 441          */
 442         save = snd_soc_read(codec, base);
 443         save &= WM8994_AIF1DAC1_EQ_ENA;
 444
 445         for (i = 0; i < WM8994_EQ_REGS; i++)
 446                 snd_soc_update_bits(codec, base + i, 0xffff,
 447                                 pdata->retune_mobile_cfgs[best].regs[i]);
 448
 449         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 450 }
 451
 452 /* Icky as hell but saves code duplication */
 453 static int wm8994_get_retune_mobile_block(const char *name)
 454 {
 455         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 456                 return 0;
 457         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 458                 return 1;
 459         if (strcmp(name, "AIF2 EQ Mode") == 0)
 460                 return 2;
 461         return -EINVAL;
 462 }
 463
 464 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 465                                          struct snd_ctl_elem_value *ucontrol)
 466 {
 467         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 468         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 469         struct wm8994 *control = wm8994->wm8994;
 470         struct wm8994_pdata *pdata = &control->pdata;
 471         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 472         int value = ucontrol->value.enumerated.item[0];
 473
 474         if (block < 0)
 475                 return block;
 476
 477         if (value >= pdata->num_retune_mobile_cfgs)
 478                 return -EINVAL;
 479
 480         wm8994->retune_mobile_cfg[block] = value;
 481
 482         wm8994_set_retune_mobile(codec, block);
 483
 484         return 0;
 485 }
 486
 487 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 488                                          struct snd_ctl_elem_value *ucontrol)
 489 {
 490         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 491         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 492         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 493
 494         if (block < 0)
 495                 return block;
 496
 497         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 498
 499         return 0;
 500 }
 501
 502 static const char *aif_chan_src_text[] = {
 503         "Left", "Right"
 504 };
 505
 506 static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
 507                             WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
 508
 509 static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
 510                             WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
 511
 512 static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
 513                             WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
 514
 515 static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
 516                             WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
 517
 518 static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
 519                             WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
 520
 521 static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
 522                             WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
 523
 524 static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
 525                             WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
 526
 527 static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
 528                             WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
 529
 530 static const char *osr_text[] = {
 531         "Low Power", "High Performance",
 532 };
 533
 534 static SOC_ENUM_SINGLE_DECL(dac_osr,
 535                             WM8994_OVERSAMPLING, 0, osr_text);
 536
 537 static SOC_ENUM_SINGLE_DECL(adc_osr,
 538                             WM8994_OVERSAMPLING, 1, osr_text);
 539
 540 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 541 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 542                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 543                  1, 119, 0, digital_tlv),
 544 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 545                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 546                  1, 119, 0, digital_tlv),
 547 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 548                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 549                  1, 119, 0, digital_tlv),
 550
 551 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 552 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 553 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 554 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 555
 556 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 557 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 558 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 559 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 560
 561 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 562                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 563 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 564                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 565 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 566                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 567
 568 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 569 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 570
 571 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 572 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 573 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 574
 575 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 576 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 577 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 578
 579 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 580 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 581 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 582
 583 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 584 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 585 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 586
 587 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 588                5, 12, 0, st_tlv),
 589 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 590                0, 12, 0, st_tlv),
 591 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 592                5, 12, 0, st_tlv),
 593 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 594                0, 12, 0, st_tlv),
 595 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 596 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 597
 598 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 599 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 600
 601 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 602 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 603
 604 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 605 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 606
 607 SOC_ENUM("ADC OSR", adc_osr),
 608 SOC_ENUM("DAC OSR", dac_osr),
 609
 610 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 611                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 612 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 613              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 614
 615 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 616                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 617 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 618              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 619
 620 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 621                6, 1, 1, wm_hubs_spkmix_tlv),
 622 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 623                2, 1, 1, wm_hubs_spkmix_tlv),
 624
 625 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 626                6, 1, 1, wm_hubs_spkmix_tlv),
 627 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 628                2, 1, 1, wm_hubs_spkmix_tlv),
 629
 630 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 631                10, 15, 0, wm8994_3d_tlv),
 632 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 633            8, 1, 0),
 634 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 635                10, 15, 0, wm8994_3d_tlv),
 636 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 637            8, 1, 0),
 638 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 639                10, 15, 0, wm8994_3d_tlv),
 640 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 641            8, 1, 0),
 642 };
 643
 644 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 645 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 646                eq_tlv),
 647 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 648                eq_tlv),
 649 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 650                eq_tlv),
 651 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 652                eq_tlv),
 653 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 654                eq_tlv),
 655
 656 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 657                eq_tlv),
 658 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 659                eq_tlv),
 660 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 661                eq_tlv),
 662 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 663                eq_tlv),
 664 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 665                eq_tlv),
 666
 667 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 668                eq_tlv),
 669 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 670                eq_tlv),
 671 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 672                eq_tlv),
 673 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 674                eq_tlv),
 675 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 676                eq_tlv),
 677 };
 678
 679 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
 680 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
 681                    WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 682                    WM8994_AIF1ADC1R_DRC_ENA),
 683 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
 684                    WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
 685                    WM8994_AIF1ADC2R_DRC_ENA),
 686 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
 687                    WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
 688                    WM8994_AIF2ADCR_DRC_ENA),
 689 };
 690
 691 static const char *wm8958_ng_text[] = {
 692         "30ms", "125ms", "250ms", "500ms",
 693 };
 694
 695 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
 696                             WM8958_AIF1_DAC1_NOISE_GATE,
 697                             WM8958_AIF1DAC1_NG_THR_SHIFT,
 698                             wm8958_ng_text);
 699
 700 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
 701                             WM8958_AIF1_DAC2_NOISE_GATE,
 702                             WM8958_AIF1DAC2_NG_THR_SHIFT,
 703                             wm8958_ng_text);
 704
 705 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
 706                             WM8958_AIF2_DAC_NOISE_GATE,
 707                             WM8958_AIF2DAC_NG_THR_SHIFT,
 708                             wm8958_ng_text);
 709
 710 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 711 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 712
 713 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 714            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 715 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 716 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 717                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 718                7, 1, ng_tlv),
 719
 720 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 721            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 722 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 723 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 724                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 725                7, 1, ng_tlv),
 726
 727 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 728            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 729 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 730 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 731                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 732                7, 1, ng_tlv),
 733 };
 734
 735 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 736 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 737                mixin_boost_tlv),
 738 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 739                mixin_boost_tlv),
 740 };
 741
 742 /* We run all mode setting through a function to enforce audio mode */
 743 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
 744 {
 745         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 746
 747         if (!wm8994->jackdet || !wm8994->micdet[0].jack)
 748                 return;
 749
 750         if (wm8994->active_refcount)
 751                 mode = WM1811_JACKDET_MODE_AUDIO;
 752
 753         if (mode == wm8994->jackdet_mode)
 754                 return;
 755
 756         wm8994->jackdet_mode = mode;
 757
 758         /* Always use audio mode to detect while the system is active */
 759         if (mode != WM1811_JACKDET_MODE_NONE)
 760                 mode = WM1811_JACKDET_MODE_AUDIO;
 761
 762         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 763                             WM1811_JACKDET_MODE_MASK, mode);
 764 }
 765
 766 static void active_reference(struct snd_soc_codec *codec)
 767 {
 768         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 769
 770         mutex_lock(&wm8994->accdet_lock);
 771
 772         wm8994->active_refcount++;
 773
 774         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
 775                 wm8994->active_refcount);
 776
 777         /* If we're using jack detection go into audio mode */
 778         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
 779
 780         mutex_unlock(&wm8994->accdet_lock);
 781 }
 782
 783 static void active_dereference(struct snd_soc_codec *codec)
 784 {
 785         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 786         u16 mode;
 787
 788         mutex_lock(&wm8994->accdet_lock);
 789
 790         wm8994->active_refcount--;
 791
 792         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
 793                 wm8994->active_refcount);
 794
 795         if (wm8994->active_refcount == 0) {
 796                 /* Go into appropriate detection only mode */
 797                 if (wm8994->jack_mic || wm8994->mic_detecting)
 798                         mode = WM1811_JACKDET_MODE_MIC;
 799                 else
 800                         mode = WM1811_JACKDET_MODE_JACK;
 801
 802                 wm1811_jackdet_set_mode(codec, mode);
 803         }
 804
 805         mutex_unlock(&wm8994->accdet_lock);
 806 }
 807
 808 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 809                          struct snd_kcontrol *kcontrol, int event)
 810 {
 811         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 812         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 813
 814         switch (event) {
 815         case SND_SOC_DAPM_PRE_PMU:
 816                 return configure_clock(codec);
 817
 818         case SND_SOC_DAPM_POST_PMU:
 819                 /*
 820                  * JACKDET won't run until we start the clock and it
 821                  * only reports deltas, make sure we notify the state
 822                  * up the stack on startup.  Use a *very* generous
 823                  * timeout for paranoia, there's no urgency and we
 824                  * don't want false reports.
 825                  */
 826                 if (wm8994->jackdet && !wm8994->clk_has_run) {
 827                         queue_delayed_work(system_power_efficient_wq,
 828                                            &wm8994->jackdet_bootstrap,
 829                                            msecs_to_jiffies(1000));
 830                         wm8994->clk_has_run = true;
 831                 }
 832                 break;
 833
 834         case SND_SOC_DAPM_POST_PMD:
 835                 configure_clock(codec);
 836                 break;
 837         }
 838
 839         return 0;
 840 }
 841
 842 static void vmid_reference(struct snd_soc_codec *codec)
 843 {
 844         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 845
 846         pm_runtime_get_sync(codec->dev);
 847
 848         wm8994->vmid_refcount++;
 849
 850         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 851                 wm8994->vmid_refcount);
 852
 853         if (wm8994->vmid_refcount == 1) {
 854                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 855                                     WM8994_LINEOUT1_DISCH |
 856                                     WM8994_LINEOUT2_DISCH, 0);
 857
 858                 wm_hubs_vmid_ena(codec);
 859
 860                 switch (wm8994->vmid_mode) {
 861                 default:
 862                         WARN_ON(NULL == "Invalid VMID mode");
 863                         /* fall through */
 864                 case WM8994_VMID_NORMAL:
 865                         /* Startup bias, VMID ramp & buffer */
 866                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 867                                             WM8994_BIAS_SRC |
 868                                             WM8994_VMID_DISCH |
 869                                             WM8994_STARTUP_BIAS_ENA |
 870                                             WM8994_VMID_BUF_ENA |
 871                                             WM8994_VMID_RAMP_MASK,
 872                                             WM8994_BIAS_SRC |
 873                                             WM8994_STARTUP_BIAS_ENA |
 874                                             WM8994_VMID_BUF_ENA |
 875                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
 876
 877                         /* Main bias enable, VMID=2x40k */
 878                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 879                                             WM8994_BIAS_ENA |
 880                                             WM8994_VMID_SEL_MASK,
 881                                             WM8994_BIAS_ENA | 0x2);
 882
 883                         msleep(300);
 884
 885                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 886                                             WM8994_VMID_RAMP_MASK |
 887                                             WM8994_BIAS_SRC,
 888                                             0);
 889                         break;
 890
 891                 case WM8994_VMID_FORCE:
 892                         /* Startup bias, slow VMID ramp & buffer */
 893                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 894                                             WM8994_BIAS_SRC |
 895                                             WM8994_VMID_DISCH |
 896                                             WM8994_STARTUP_BIAS_ENA |
 897                                             WM8994_VMID_BUF_ENA |
 898                                             WM8994_VMID_RAMP_MASK,
 899                                             WM8994_BIAS_SRC |
 900                                             WM8994_STARTUP_BIAS_ENA |
 901                                             WM8994_VMID_BUF_ENA |
 902                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
 903
 904                         /* Main bias enable, VMID=2x40k */
 905                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 906                                             WM8994_BIAS_ENA |
 907                                             WM8994_VMID_SEL_MASK,
 908                                             WM8994_BIAS_ENA | 0x2);
 909
 910                         msleep(400);
 911
 912                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 913                                             WM8994_VMID_RAMP_MASK |
 914                                             WM8994_BIAS_SRC,
 915                                             0);
 916                         break;
 917                 }
 918         }
 919 }
 920
 921 static void vmid_dereference(struct snd_soc_codec *codec)
 922 {
 923         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 924
 925         wm8994->vmid_refcount--;
 926
 927         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 928                 wm8994->vmid_refcount);
 929
 930         if (wm8994->vmid_refcount == 0) {
 931                 if (wm8994->hubs.lineout1_se)
 932                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 933                                             WM8994_LINEOUT1N_ENA |
 934                                             WM8994_LINEOUT1P_ENA,
 935                                             WM8994_LINEOUT1N_ENA |
 936                                             WM8994_LINEOUT1P_ENA);
 937
 938                 if (wm8994->hubs.lineout2_se)
 939                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 940                                             WM8994_LINEOUT2N_ENA |
 941                                             WM8994_LINEOUT2P_ENA,
 942                                             WM8994_LINEOUT2N_ENA |
 943                                             WM8994_LINEOUT2P_ENA);
 944
 945                 /* Start discharging VMID */
 946                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 947                                     WM8994_BIAS_SRC |
 948                                     WM8994_VMID_DISCH,
 949                                     WM8994_BIAS_SRC |
 950                                     WM8994_VMID_DISCH);
 951
 952                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 953                                     WM8994_VMID_SEL_MASK, 0);
 954
 955                 msleep(400);
 956
 957                 /* Active discharge */
 958                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 959                                     WM8994_LINEOUT1_DISCH |
 960                                     WM8994_LINEOUT2_DISCH,
 961                                     WM8994_LINEOUT1_DISCH |
 962                                     WM8994_LINEOUT2_DISCH);
 963
 964                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 965                                     WM8994_LINEOUT1N_ENA |
 966                                     WM8994_LINEOUT1P_ENA |
 967                                     WM8994_LINEOUT2N_ENA |
 968                                     WM8994_LINEOUT2P_ENA, 0);
 969
 970                 /* Switch off startup biases */
 971                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 972                                     WM8994_BIAS_SRC |
 973                                     WM8994_STARTUP_BIAS_ENA |
 974                                     WM8994_VMID_BUF_ENA |
 975                                     WM8994_VMID_RAMP_MASK, 0);
 976
 977                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 978                                     WM8994_VMID_SEL_MASK, 0);
 979         }
 980
 981         pm_runtime_put(codec->dev);
 982 }
 983
 984 static int vmid_event(struct snd_soc_dapm_widget *w,
 985                       struct snd_kcontrol *kcontrol, int event)
 986 {
 987         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 988
 989         switch (event) {
 990         case SND_SOC_DAPM_PRE_PMU:
 991                 vmid_reference(codec);
 992                 break;
 993
 994         case SND_SOC_DAPM_POST_PMD:
 995                 vmid_dereference(codec);
 996                 break;
 997         }
 998
 999         return 0;
1000 }
1001
1002 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
1003 {
1004         int source = 0;  /* GCC flow analysis can't track enable */
1005         int reg, reg_r;
1006
1007         /* We also need the same AIF source for L/R and only one path */
1008         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1009         switch (reg) {
1010         case WM8994_AIF2DACL_TO_DAC1L:
1011                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1012                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1013                 break;
1014         case WM8994_AIF1DAC2L_TO_DAC1L:
1015                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1016                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1017                 break;
1018         case WM8994_AIF1DAC1L_TO_DAC1L:
1019                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1020                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1021                 break;
1022         default:
1023                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1024                 return false;
1025         }
1026
1027         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1028         if (reg_r != reg) {
1029                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1030                 return false;
1031         }
1032
1033         /* Set the source up */
1034         snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1035                             WM8994_CP_DYN_SRC_SEL_MASK, source);
1036
1037         return true;
1038 }
1039
1040 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1041                       struct snd_kcontrol *kcontrol, int event)
1042 {
1043         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1044         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1045         struct wm8994 *control = wm8994->wm8994;
1046         int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1047         int i;
1048         int dac;
1049         int adc;
1050         int val;
1051
1052         switch (control->type) {
1053         case WM8994:
1054         case WM8958:
1055                 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1056                 break;
1057         default:
1058                 break;
1059         }
1060
1061         switch (event) {
1062         case SND_SOC_DAPM_PRE_PMU:
1063                 /* Don't enable timeslot 2 if not in use */
1064                 if (wm8994->channels[0] <= 2)
1065                         mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1066
1067                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1068                 if ((val & WM8994_AIF1ADCL_SRC) &&
1069                     (val & WM8994_AIF1ADCR_SRC))
1070                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1071                 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1072                          !(val & WM8994_AIF1ADCR_SRC))
1073                         adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1074                 else
1075                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1076                                 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1077
1078                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1079                 if ((val & WM8994_AIF1DACL_SRC) &&
1080                     (val & WM8994_AIF1DACR_SRC))
1081                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1082                 else if (!(val & WM8994_AIF1DACL_SRC) &&
1083                          !(val & WM8994_AIF1DACR_SRC))
1084                         dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1085                 else
1086                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1087                                 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1088
1089                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1090                                     mask, adc);
1091                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1092                                     mask, dac);
1093                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1094                                     WM8994_AIF1DSPCLK_ENA |
1095                                     WM8994_SYSDSPCLK_ENA,
1096                                     WM8994_AIF1DSPCLK_ENA |
1097                                     WM8994_SYSDSPCLK_ENA);
1098                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1099                                     WM8994_AIF1ADC1R_ENA |
1100                                     WM8994_AIF1ADC1L_ENA |
1101                                     WM8994_AIF1ADC2R_ENA |
1102                                     WM8994_AIF1ADC2L_ENA);
1103                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1104                                     WM8994_AIF1DAC1R_ENA |
1105                                     WM8994_AIF1DAC1L_ENA |
1106                                     WM8994_AIF1DAC2R_ENA |
1107                                     WM8994_AIF1DAC2L_ENA);
1108                 break;
1109
1110         case SND_SOC_DAPM_POST_PMU:
1111                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1112                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1113                                       snd_soc_read(codec,
1114                                                    wm8994_vu_bits[i].reg));
1115                 break;
1116
1117         case SND_SOC_DAPM_PRE_PMD:
1118         case SND_SOC_DAPM_POST_PMD:
1119                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1120                                     mask, 0);
1121                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1122                                     mask, 0);
1123
1124                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1125                 if (val & WM8994_AIF2DSPCLK_ENA)
1126                         val = WM8994_SYSDSPCLK_ENA;
1127                 else
1128                         val = 0;
1129                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1130                                     WM8994_SYSDSPCLK_ENA |
1131                                     WM8994_AIF1DSPCLK_ENA, val);
1132                 break;
1133         }
1134
1135         return 0;
1136 }
1137
1138 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1139                       struct snd_kcontrol *kcontrol, int event)
1140 {
1141         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1142         int i;
1143         int dac;
1144         int adc;
1145         int val;
1146
1147         switch (event) {
1148         case SND_SOC_DAPM_PRE_PMU:
1149                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1150                 if ((val & WM8994_AIF2ADCL_SRC) &&
1151                     (val & WM8994_AIF2ADCR_SRC))
1152                         adc = WM8994_AIF2ADCR_ENA;
1153                 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1154                          !(val & WM8994_AIF2ADCR_SRC))
1155                         adc = WM8994_AIF2ADCL_ENA;
1156                 else
1157                         adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1158
1159
1160                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1161                 if ((val & WM8994_AIF2DACL_SRC) &&
1162                     (val & WM8994_AIF2DACR_SRC))
1163                         dac = WM8994_AIF2DACR_ENA;
1164                 else if (!(val & WM8994_AIF2DACL_SRC) &&
1165                          !(val & WM8994_AIF2DACR_SRC))
1166                         dac = WM8994_AIF2DACL_ENA;
1167                 else
1168                         dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1169
1170                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1171                                     WM8994_AIF2ADCL_ENA |
1172                                     WM8994_AIF2ADCR_ENA, adc);
1173                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1174                                     WM8994_AIF2DACL_ENA |
1175                                     WM8994_AIF2DACR_ENA, dac);
1176                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1177                                     WM8994_AIF2DSPCLK_ENA |
1178                                     WM8994_SYSDSPCLK_ENA,
1179                                     WM8994_AIF2DSPCLK_ENA |
1180                                     WM8994_SYSDSPCLK_ENA);
1181                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1182                                     WM8994_AIF2ADCL_ENA |
1183                                     WM8994_AIF2ADCR_ENA,
1184                                     WM8994_AIF2ADCL_ENA |
1185                                     WM8994_AIF2ADCR_ENA);
1186                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1187                                     WM8994_AIF2DACL_ENA |
1188                                     WM8994_AIF2DACR_ENA,
1189                                     WM8994_AIF2DACL_ENA |
1190                                     WM8994_AIF2DACR_ENA);
1191                 break;
1192
1193         case SND_SOC_DAPM_POST_PMU:
1194                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1195                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1196                                       snd_soc_read(codec,
1197                                                    wm8994_vu_bits[i].reg));
1198                 break;
1199
1200         case SND_SOC_DAPM_PRE_PMD:
1201         case SND_SOC_DAPM_POST_PMD:
1202                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1203                                     WM8994_AIF2DACL_ENA |
1204                                     WM8994_AIF2DACR_ENA, 0);
1205                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1206                                     WM8994_AIF2ADCL_ENA |
1207                                     WM8994_AIF2ADCR_ENA, 0);
1208
1209                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1210                 if (val & WM8994_AIF1DSPCLK_ENA)
1211                         val = WM8994_SYSDSPCLK_ENA;
1212                 else
1213                         val = 0;
1214                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1215                                     WM8994_SYSDSPCLK_ENA |
1216                                     WM8994_AIF2DSPCLK_ENA, val);
1217                 break;
1218         }
1219
1220         return 0;
1221 }
1222
1223 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1224                            struct snd_kcontrol *kcontrol, int event)
1225 {
1226         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1227         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1228
1229         switch (event) {
1230         case SND_SOC_DAPM_PRE_PMU:
1231                 wm8994->aif1clk_enable = 1;
1232                 break;
1233         case SND_SOC_DAPM_POST_PMD:
1234                 wm8994->aif1clk_disable = 1;
1235                 break;
1236         }
1237
1238         return 0;
1239 }
1240
1241 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1242                            struct snd_kcontrol *kcontrol, int event)
1243 {
1244         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1245         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1246
1247         switch (event) {
1248         case SND_SOC_DAPM_PRE_PMU:
1249                 wm8994->aif2clk_enable = 1;
1250                 break;
1251         case SND_SOC_DAPM_POST_PMD:
1252                 wm8994->aif2clk_disable = 1;
1253                 break;
1254         }
1255
1256         return 0;
1257 }
1258
1259 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1260                           struct snd_kcontrol *kcontrol, int event)
1261 {
1262         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1263         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1264
1265         switch (event) {
1266         case SND_SOC_DAPM_PRE_PMU:
1267                 if (wm8994->aif1clk_enable) {
1268                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1269                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1270                                             WM8994_AIF1CLK_ENA_MASK,
1271                                             WM8994_AIF1CLK_ENA);
1272                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1273                         wm8994->aif1clk_enable = 0;
1274                 }
1275                 if (wm8994->aif2clk_enable) {
1276                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1277                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1278                                             WM8994_AIF2CLK_ENA_MASK,
1279                                             WM8994_AIF2CLK_ENA);
1280                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1281                         wm8994->aif2clk_enable = 0;
1282                 }
1283                 break;
1284         }
1285
1286         /* We may also have postponed startup of DSP, handle that. */
1287         wm8958_aif_ev(w, kcontrol, event);
1288
1289         return 0;
1290 }
1291
1292 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1293                            struct snd_kcontrol *kcontrol, int event)
1294 {
1295         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1296         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1297
1298         switch (event) {
1299         case SND_SOC_DAPM_POST_PMD:
1300                 if (wm8994->aif1clk_disable) {
1301                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1302                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1303                                             WM8994_AIF1CLK_ENA_MASK, 0);
1304                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1305                         wm8994->aif1clk_disable = 0;
1306                 }
1307                 if (wm8994->aif2clk_disable) {
1308                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1309                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1310                                             WM8994_AIF2CLK_ENA_MASK, 0);
1311                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1312                         wm8994->aif2clk_disable = 0;
1313                 }
1314                 break;
1315         }
1316
1317         return 0;
1318 }
1319
1320 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1321                       struct snd_kcontrol *kcontrol, int event)
1322 {
1323         late_enable_ev(w, kcontrol, event);
1324         return 0;
1325 }
1326
1327 static int micbias_ev(struct snd_soc_dapm_widget *w,
1328                       struct snd_kcontrol *kcontrol, int event)
1329 {
1330         late_enable_ev(w, kcontrol, event);
1331         return 0;
1332 }
1333
1334 static int dac_ev(struct snd_soc_dapm_widget *w,
1335                   struct snd_kcontrol *kcontrol, int event)
1336 {
1337         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1338         unsigned int mask = 1 << w->shift;
1339
1340         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1341                             mask, mask);
1342         return 0;
1343 }
1344
1345 static const char *adc_mux_text[] = {
1346         "ADC",
1347         "DMIC",
1348 };
1349
1350 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1351
1352 static const struct snd_kcontrol_new adcl_mux =
1353         SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1354
1355 static const struct snd_kcontrol_new adcr_mux =
1356         SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1357
1358 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1359 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1360 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1361 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1362 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1363 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1364 };
1365
1366 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1367 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1368 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1369 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1370 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1371 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1372 };
1373
1374 /* Debugging; dump chip status after DAPM transitions */
1375 static int post_ev(struct snd_soc_dapm_widget *w,
1376             struct snd_kcontrol *kcontrol, int event)
1377 {
1378         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1379         dev_dbg(codec->dev, "SRC status: %x\n",
1380                 snd_soc_read(codec,
1381                              WM8994_RATE_STATUS));
1382         return 0;
1383 }
1384
1385 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1386 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1387                 1, 1, 0),
1388 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1389                 0, 1, 0),
1390 };
1391
1392 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1393 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1394                 1, 1, 0),
1395 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1396                 0, 1, 0),
1397 };
1398
1399 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1400 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1401                 1, 1, 0),
1402 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1403                 0, 1, 0),
1404 };
1405
1406 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1407 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1408                 1, 1, 0),
1409 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1410                 0, 1, 0),
1411 };
1412
1413 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1414 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1415                 5, 1, 0),
1416 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1417                 4, 1, 0),
1418 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1419                 2, 1, 0),
1420 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1421                 1, 1, 0),
1422 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1423                 0, 1, 0),
1424 };
1425
1426 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1427 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1428                 5, 1, 0),
1429 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1430                 4, 1, 0),
1431 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1432                 2, 1, 0),
1433 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1434                 1, 1, 0),
1435 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1436                 0, 1, 0),
1437 };
1438
1439 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1440         SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1441                 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1442
1443 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1444                               struct snd_ctl_elem_value *ucontrol)
1445 {
1446         struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
1447         int ret;
1448
1449         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1450
1451         wm_hubs_update_class_w(codec);
1452
1453         return ret;
1454 }
1455
1456 static const struct snd_kcontrol_new dac1l_mix[] = {
1457 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1458                       5, 1, 0),
1459 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1460                       4, 1, 0),
1461 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1462                       2, 1, 0),
1463 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1464                       1, 1, 0),
1465 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1466                       0, 1, 0),
1467 };
1468
1469 static const struct snd_kcontrol_new dac1r_mix[] = {
1470 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1471                       5, 1, 0),
1472 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1473                       4, 1, 0),
1474 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1475                       2, 1, 0),
1476 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1477                       1, 1, 0),
1478 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1479                       0, 1, 0),
1480 };
1481
1482 static const char *sidetone_text[] = {
1483         "ADC/DMIC1", "DMIC2",
1484 };
1485
1486 static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1487                             WM8994_SIDETONE, 0, sidetone_text);
1488
1489 static const struct snd_kcontrol_new sidetone1_mux =
1490         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1491
1492 static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1493                             WM8994_SIDETONE, 1, sidetone_text);
1494
1495 static const struct snd_kcontrol_new sidetone2_mux =
1496         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1497
1498 static const char *aif1dac_text[] = {
1499         "AIF1DACDAT", "AIF3DACDAT",
1500 };
1501
1502 static const char *loopback_text[] = {
1503         "None", "ADCDAT",
1504 };
1505
1506 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1507                             WM8994_AIF1_CONTROL_2,
1508                             WM8994_AIF1_LOOPBACK_SHIFT,
1509                             loopback_text);
1510
1511 static const struct snd_kcontrol_new aif1_loopback =
1512         SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1513
1514 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1515                             WM8994_AIF2_CONTROL_2,
1516                             WM8994_AIF2_LOOPBACK_SHIFT,
1517                             loopback_text);
1518
1519 static const struct snd_kcontrol_new aif2_loopback =
1520         SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1521
1522 static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1523                             WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1524
1525 static const struct snd_kcontrol_new aif1dac_mux =
1526         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1527
1528 static const char *aif2dac_text[] = {
1529         "AIF2DACDAT", "AIF3DACDAT",
1530 };
1531
1532 static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1533                             WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1534
1535 static const struct snd_kcontrol_new aif2dac_mux =
1536         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1537
1538 static const char *aif2adc_text[] = {
1539         "AIF2ADCDAT", "AIF3DACDAT",
1540 };
1541
1542 static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1543                             WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1544
1545 static const struct snd_kcontrol_new aif2adc_mux =
1546         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1547
1548 static const char *aif3adc_text[] = {
1549         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1550 };
1551
1552 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1553                             WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1554
1555 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1556         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1557
1558 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1559                             WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1560
1561 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1562         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1563
1564 static const char *mono_pcm_out_text[] = {
1565         "None", "AIF2ADCL", "AIF2ADCR",
1566 };
1567
1568 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1569                             WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1570
1571 static const struct snd_kcontrol_new mono_pcm_out_mux =
1572         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1573
1574 static const char *aif2dac_src_text[] = {
1575         "AIF2", "AIF3",
1576 };
1577
1578 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1579 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1580                             WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1581
1582 static const struct snd_kcontrol_new aif2dacl_src_mux =
1583         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1584
1585 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1586                             WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1587
1588 static const struct snd_kcontrol_new aif2dacr_src_mux =
1589         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1590
1591 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1592 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1593         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1594 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1595         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1596
1597 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1598         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1599 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1600         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1601 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1602         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1603 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1604         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1605 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1606         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1607
1608 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1609                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1610                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1611 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1612                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1613                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1614 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1615                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1616 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1617                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1618
1619 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1620 };
1621
1622 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1623 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1624                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1625                     SND_SOC_DAPM_PRE_PMD),
1626 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1627                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1628                     SND_SOC_DAPM_PRE_PMD),
1629 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1630 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1631                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1632 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1633                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1634 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1635 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1636 };
1637
1638 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1639 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1640         dac_ev, SND_SOC_DAPM_PRE_PMU),
1641 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1642         dac_ev, SND_SOC_DAPM_PRE_PMU),
1643 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1644         dac_ev, SND_SOC_DAPM_PRE_PMU),
1645 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1646         dac_ev, SND_SOC_DAPM_PRE_PMU),
1647 };
1648
1649 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1650 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1651 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1652 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1653 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1654 };
1655
1656 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1657 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1658                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1659 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1660                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1661 };
1662
1663 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1664 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1665 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1666 };
1667
1668 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1669 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1670 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1671 SND_SOC_DAPM_INPUT("Clock"),
1672
1673 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1674                       SND_SOC_DAPM_PRE_PMU),
1675 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1676                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1677
1678 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1679                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1680                     SND_SOC_DAPM_PRE_PMD),
1681
1682 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1683 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1684 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1685
1686 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1687                      0, SND_SOC_NOPM, 9, 0),
1688 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1689                      0, SND_SOC_NOPM, 8, 0),
1690 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1691                       SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1692                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1693 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1694                       SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1695                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1696
1697 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1698                      0, SND_SOC_NOPM, 11, 0),
1699 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1700                      0, SND_SOC_NOPM, 10, 0),
1701 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1702                       SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1703                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1704 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1705                       SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1706                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1707
1708 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1709                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1710 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1711                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1712
1713 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1714                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1715 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1716                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1717
1718 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1719                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1720 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1721                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1722
1723 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1724 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1725
1726 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1727                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1728 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1729                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1730
1731 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1732                      SND_SOC_NOPM, 13, 0),
1733 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1734                      SND_SOC_NOPM, 12, 0),
1735 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1736                       SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1737                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1738 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1739                       SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1740                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1741
1742 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1743 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1744 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1745 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1746
1747 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1748 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1749 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1750
1751 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1752 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1753
1754 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1755
1756 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1757 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1758 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1759 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1760
1761 /* Power is done with the muxes since the ADC power also controls the
1762  * downsampling chain, the chip will automatically manage the analogue
1763  * specific portions.
1764  */
1765 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1766 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1767
1768 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1769 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1770
1771 SND_SOC_DAPM_POST("Debug log", post_ev),
1772 };
1773
1774 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1775 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1776 };
1777
1778 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1779 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1780 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1781 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1782 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1783 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1784 };
1785
1786 static const struct snd_soc_dapm_route intercon[] = {
1787         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1788         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1789
1790         { "DSP1CLK", NULL, "CLK_SYS" },
1791         { "DSP2CLK", NULL, "CLK_SYS" },
1792         { "DSPINTCLK", NULL, "CLK_SYS" },
1793
1794         { "AIF1ADC1L", NULL, "AIF1CLK" },
1795         { "AIF1ADC1L", NULL, "DSP1CLK" },
1796         { "AIF1ADC1R", NULL, "AIF1CLK" },
1797         { "AIF1ADC1R", NULL, "DSP1CLK" },
1798         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1799
1800         { "AIF1DAC1L", NULL, "AIF1CLK" },
1801         { "AIF1DAC1L", NULL, "DSP1CLK" },
1802         { "AIF1DAC1R", NULL, "AIF1CLK" },
1803         { "AIF1DAC1R", NULL, "DSP1CLK" },
1804         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1805
1806         { "AIF1ADC2L", NULL, "AIF1CLK" },
1807         { "AIF1ADC2L", NULL, "DSP1CLK" },
1808         { "AIF1ADC2R", NULL, "AIF1CLK" },
1809         { "AIF1ADC2R", NULL, "DSP1CLK" },
1810         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1811
1812         { "AIF1DAC2L", NULL, "AIF1CLK" },
1813         { "AIF1DAC2L", NULL, "DSP1CLK" },
1814         { "AIF1DAC2R", NULL, "AIF1CLK" },
1815         { "AIF1DAC2R", NULL, "DSP1CLK" },
1816         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1817
1818         { "AIF2ADCL", NULL, "AIF2CLK" },
1819         { "AIF2ADCL", NULL, "DSP2CLK" },
1820         { "AIF2ADCR", NULL, "AIF2CLK" },
1821         { "AIF2ADCR", NULL, "DSP2CLK" },
1822         { "AIF2ADCR", NULL, "DSPINTCLK" },
1823
1824         { "AIF2DACL", NULL, "AIF2CLK" },
1825         { "AIF2DACL", NULL, "DSP2CLK" },
1826         { "AIF2DACR", NULL, "AIF2CLK" },
1827         { "AIF2DACR", NULL, "DSP2CLK" },
1828         { "AIF2DACR", NULL, "DSPINTCLK" },
1829
1830         { "DMIC1L", NULL, "DMIC1DAT" },
1831         { "DMIC1L", NULL, "CLK_SYS" },
1832         { "DMIC1R", NULL, "DMIC1DAT" },
1833         { "DMIC1R", NULL, "CLK_SYS" },
1834         { "DMIC2L", NULL, "DMIC2DAT" },
1835         { "DMIC2L", NULL, "CLK_SYS" },
1836         { "DMIC2R", NULL, "DMIC2DAT" },
1837         { "DMIC2R", NULL, "CLK_SYS" },
1838
1839         { "ADCL", NULL, "AIF1CLK" },
1840         { "ADCL", NULL, "DSP1CLK" },
1841         { "ADCL", NULL, "DSPINTCLK" },
1842
1843         { "ADCR", NULL, "AIF1CLK" },
1844         { "ADCR", NULL, "DSP1CLK" },
1845         { "ADCR", NULL, "DSPINTCLK" },
1846
1847         { "ADCL Mux", "ADC", "ADCL" },
1848         { "ADCL Mux", "DMIC", "DMIC1L" },
1849         { "ADCR Mux", "ADC", "ADCR" },
1850         { "ADCR Mux", "DMIC", "DMIC1R" },
1851
1852         { "DAC1L", NULL, "AIF1CLK" },
1853         { "DAC1L", NULL, "DSP1CLK" },
1854         { "DAC1L", NULL, "DSPINTCLK" },
1855
1856         { "DAC1R", NULL, "AIF1CLK" },
1857         { "DAC1R", NULL, "DSP1CLK" },
1858         { "DAC1R", NULL, "DSPINTCLK" },
1859
1860         { "DAC2L", NULL, "AIF2CLK" },
1861         { "DAC2L", NULL, "DSP2CLK" },
1862         { "DAC2L", NULL, "DSPINTCLK" },
1863
1864         { "DAC2R", NULL, "AIF2DACR" },
1865         { "DAC2R", NULL, "AIF2CLK" },
1866         { "DAC2R", NULL, "DSP2CLK" },
1867         { "DAC2R", NULL, "DSPINTCLK" },
1868
1869         { "TOCLK", NULL, "CLK_SYS" },
1870
1871         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1872         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1873         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1874
1875         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1876         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1877         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1878
1879         /* AIF1 outputs */
1880         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1881         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1882         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1883
1884         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1885         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1886         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1887
1888         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1889         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1890         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1891
1892         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1893         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1894         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1895
1896         /* Pin level routing for AIF3 */
1897         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1898         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1899         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1900         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1901
1902         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1903         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1904         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1905         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1906         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1907         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1908         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1909
1910         /* DAC1 inputs */
1911         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1912         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1913         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1914         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1915         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1916
1917         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1918         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1919         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1920         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1921         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1922
1923         /* DAC2/AIF2 outputs  */
1924         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1925         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1926         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1927         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1928         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1929         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1930
1931         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1932         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1933         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1934         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1935         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1936         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1937
1938         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1939         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1940         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1941         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1942
1943         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1944
1945         /* AIF3 output */
1946         { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" },
1947         { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" },
1948         { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" },
1949         { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" },
1950         { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1951         { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1952         { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" },
1953         { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" },
1954
1955         { "AIF3ADCDAT", NULL, "AIF3ADC Mux" },
1956
1957         /* Loopback */
1958         { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1959         { "AIF1 Loopback", "None", "AIF1DACDAT" },
1960         { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1961         { "AIF2 Loopback", "None", "AIF2DACDAT" },
1962
1963         /* Sidetone */
1964         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1965         { "Left Sidetone", "DMIC2", "DMIC2L" },
1966         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1967         { "Right Sidetone", "DMIC2", "DMIC2R" },
1968
1969         /* Output stages */
1970         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1971         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1972
1973         { "SPKL", "DAC1 Switch", "DAC1L" },
1974         { "SPKL", "DAC2 Switch", "DAC2L" },
1975
1976         { "SPKR", "DAC1 Switch", "DAC1R" },
1977         { "SPKR", "DAC2 Switch", "DAC2R" },
1978
1979         { "Left Headphone Mux", "DAC", "DAC1L" },
1980         { "Right Headphone Mux", "DAC", "DAC1R" },
1981 };
1982
1983 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1984         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1985         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1986         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1987         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1988         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1989         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1990         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1991         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1992 };
1993
1994 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1995         { "DAC1L", NULL, "DAC1L Mixer" },
1996         { "DAC1R", NULL, "DAC1R Mixer" },
1997         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1998         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1999 };
2000
2001 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
2002         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
2003         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
2004         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2005         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2006         { "MICBIAS1", NULL, "CLK_SYS" },
2007         { "MICBIAS1", NULL, "MICBIAS Supply" },
2008         { "MICBIAS2", NULL, "CLK_SYS" },
2009         { "MICBIAS2", NULL, "MICBIAS Supply" },
2010 };
2011
2012 static const struct snd_soc_dapm_route wm8994_intercon[] = {
2013         { "AIF2DACL", NULL, "AIF2DAC Mux" },
2014         { "AIF2DACR", NULL, "AIF2DAC Mux" },
2015         { "MICBIAS1", NULL, "VMID" },
2016         { "MICBIAS2", NULL, "VMID" },
2017 };
2018
2019 static const struct snd_soc_dapm_route wm8958_intercon[] = {
2020         { "AIF2DACL", NULL, "AIF2DACL Mux" },
2021         { "AIF2DACR", NULL, "AIF2DACR Mux" },
2022
2023         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2024         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2025         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2026         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2027
2028         { "AIF3DACDAT", NULL, "AIF3" },
2029         { "AIF3ADCDAT", NULL, "AIF3" },
2030
2031         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2032         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2033
2034         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2035 };
2036
2037 /* The size in bits of the FLL divide multiplied by 10
2038  * to allow rounding later */
2039 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2040
2041 struct fll_div {
2042         u16 outdiv;
2043         u16 n;
2044         u16 k;
2045         u16 lambda;
2046         u16 clk_ref_div;
2047         u16 fll_fratio;
2048 };
2049
2050 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2051                                  int freq_in, int freq_out)
2052 {
2053         u64 Kpart;
2054         unsigned int K, Ndiv, Nmod, gcd_fll;
2055
2056         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2057
2058         /* Scale the input frequency down to <= 13.5MHz */
2059         fll->clk_ref_div = 0;
2060         while (freq_in > 13500000) {
2061                 fll->clk_ref_div++;
2062                 freq_in /= 2;
2063
2064                 if (fll->clk_ref_div > 3)
2065                         return -EINVAL;
2066         }
2067         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2068
2069         /* Scale the output to give 90MHz<=Fvco<=100MHz */
2070         fll->outdiv = 3;
2071         while (freq_out * (fll->outdiv + 1) < 90000000) {
2072                 fll->outdiv++;
2073                 if (fll->outdiv > 63)
2074                         return -EINVAL;
2075         }
2076         freq_out *= fll->outdiv + 1;
2077         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2078
2079         if (freq_in > 1000000) {
2080                 fll->fll_fratio = 0;
2081         } else if (freq_in > 256000) {
2082                 fll->fll_fratio = 1;
2083                 freq_in *= 2;
2084         } else if (freq_in > 128000) {
2085                 fll->fll_fratio = 2;
2086                 freq_in *= 4;
2087         } else if (freq_in > 64000) {
2088                 fll->fll_fratio = 3;
2089                 freq_in *= 8;
2090         } else {
2091                 fll->fll_fratio = 4;
2092                 freq_in *= 16;
2093         }
2094         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2095
2096         /* Now, calculate N.K */
2097         Ndiv = freq_out / freq_in;
2098
2099         fll->n = Ndiv;
2100         Nmod = freq_out % freq_in;
2101         pr_debug("Nmod=%d\n", Nmod);
2102
2103         switch (control->type) {
2104         case WM8994:
2105                 /* Calculate fractional part - scale up so we can round. */
2106                 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2107
2108                 do_div(Kpart, freq_in);
2109
2110                 K = Kpart & 0xFFFFFFFF;
2111
2112                 if ((K % 10) >= 5)
2113                         K += 5;
2114
2115                 /* Move down to proper range now rounding is done */
2116                 fll->k = K / 10;
2117                 fll->lambda = 0;
2118
2119                 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2120                 break;
2121
2122         default:
2123                 gcd_fll = gcd(freq_out, freq_in);
2124
2125                 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2126                 fll->lambda = freq_in / gcd_fll;
2127
2128         }
2129
2130         return 0;
2131 }
2132
2133 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2134                           unsigned int freq_in, unsigned int freq_out)
2135 {
2136         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2137         struct wm8994 *control = wm8994->wm8994;
2138         int reg_offset, ret;
2139         struct fll_div fll;
2140         u16 reg, clk1, aif_reg, aif_src;
2141         unsigned long timeout;
2142         bool was_enabled;
2143
2144         switch (id) {
2145         case WM8994_FLL1:
2146                 reg_offset = 0;
2147                 id = 0;
2148                 aif_src = 0x10;
2149                 break;
2150         case WM8994_FLL2:
2151                 reg_offset = 0x20;
2152                 id = 1;
2153                 aif_src = 0x18;
2154                 break;
2155         default:
2156                 return -EINVAL;
2157         }
2158
2159         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2160         was_enabled = reg & WM8994_FLL1_ENA;
2161
2162         switch (src) {
2163         case 0:
2164                 /* Allow no source specification when stopping */
2165                 if (freq_out)
2166                         return -EINVAL;
2167                 src = wm8994->fll[id].src;
2168                 break;
2169         case WM8994_FLL_SRC_MCLK1:
2170         case WM8994_FLL_SRC_MCLK2:
2171         case WM8994_FLL_SRC_LRCLK:
2172         case WM8994_FLL_SRC_BCLK:
2173                 break;
2174         case WM8994_FLL_SRC_INTERNAL:
2175                 freq_in = 12000000;
2176                 freq_out = 12000000;
2177                 break;
2178         default:
2179                 return -EINVAL;
2180         }
2181
2182         /* Are we changing anything? */
2183         if (wm8994->fll[id].src == src &&
2184             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2185                 return 0;
2186
2187         /* If we're stopping the FLL redo the old config - no
2188          * registers will actually be written but we avoid GCC flow
2189          * analysis bugs spewing warnings.
2190          */
2191         if (freq_out)
2192                 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2193         else
2194                 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2195                                             wm8994->fll[id].out);
2196         if (ret < 0)
2197                 return ret;
2198
2199         /* Make sure that we're not providing SYSCLK right now */
2200         clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2201         if (clk1 & WM8994_SYSCLK_SRC)
2202                 aif_reg = WM8994_AIF2_CLOCKING_1;
2203         else
2204                 aif_reg = WM8994_AIF1_CLOCKING_1;
2205         reg = snd_soc_read(codec, aif_reg);
2206
2207         if ((reg & WM8994_AIF1CLK_ENA) &&
2208             (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2209                 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2210                         id + 1);
2211                 return -EBUSY;
2212         }
2213
2214         /* We always need to disable the FLL while reconfiguring */
2215         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2216                             WM8994_FLL1_ENA, 0);
2217
2218         if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2219             freq_in == freq_out && freq_out) {
2220                 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2221                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2222                                     WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2223                 goto out;
2224         }
2225
2226         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2227                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2228         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2229                             WM8994_FLL1_OUTDIV_MASK |
2230                             WM8994_FLL1_FRATIO_MASK, reg);
2231
2232         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2233                             WM8994_FLL1_K_MASK, fll.k);
2234
2235         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2236                             WM8994_FLL1_N_MASK,
2237                             fll.n << WM8994_FLL1_N_SHIFT);
2238
2239         if (fll.lambda) {
2240                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2241                                     WM8958_FLL1_LAMBDA_MASK,
2242                                     fll.lambda);
2243                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2244                                     WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2245         } else {
2246                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2247                                     WM8958_FLL1_EFS_ENA, 0);
2248         }
2249
2250         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2251                             WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2252                             WM8994_FLL1_REFCLK_DIV_MASK |
2253                             WM8994_FLL1_REFCLK_SRC_MASK,
2254                             ((src == WM8994_FLL_SRC_INTERNAL)
2255                              << WM8994_FLL1_FRC_NCO_SHIFT) |
2256                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2257                             (src - 1));
2258
2259         /* Clear any pending completion from a previous failure */
2260         try_wait_for_completion(&wm8994->fll_locked[id]);
2261
2262         /* Enable (with fractional mode if required) */
2263         if (freq_out) {
2264                 /* Enable VMID if we need it */
2265                 if (!was_enabled) {
2266                         active_reference(codec);
2267
2268                         switch (control->type) {
2269                         case WM8994:
2270                                 vmid_reference(codec);
2271                                 break;
2272                         case WM8958:
2273                                 if (control->revision < 1)
2274                                         vmid_reference(codec);
2275                                 break;
2276                         default:
2277                                 break;
2278                         }
2279                 }
2280
2281                 reg = WM8994_FLL1_ENA;
2282
2283                 if (fll.k)
2284                         reg |= WM8994_FLL1_FRAC;
2285                 if (src == WM8994_FLL_SRC_INTERNAL)
2286                         reg |= WM8994_FLL1_OSC_ENA;
2287
2288                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2289                                     WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2290                                     WM8994_FLL1_FRAC, reg);
2291
2292                 if (wm8994->fll_locked_irq) {
2293                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2294                                                               msecs_to_jiffies(10));
2295                         if (timeout == 0)
2296                                 dev_warn(codec->dev,
2297                                          "Timed out waiting for FLL lock\n");
2298                 } else {
2299                         msleep(5);
2300                 }
2301         } else {
2302                 if (was_enabled) {
2303                         switch (control->type) {
2304                         case WM8994:
2305                                 vmid_dereference(codec);
2306                                 break;
2307                         case WM8958:
2308                                 if (control->revision < 1)
2309                                         vmid_dereference(codec);
2310                                 break;
2311                         default:
2312                                 break;
2313                         }
2314
2315                         active_dereference(codec);
2316                 }
2317         }
2318
2319 out:
2320         wm8994->fll[id].in = freq_in;
2321         wm8994->fll[id].out = freq_out;
2322         wm8994->fll[id].src = src;
2323
2324         configure_clock(codec);
2325
2326         /*
2327          * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2328          * for detection.
2329          */
2330         if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2331                 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2332
2333                 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2334                         & WM8994_AIF1CLK_RATE_MASK;
2335                 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2336                         & WM8994_AIF1CLK_RATE_MASK;
2337
2338                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2339                                     WM8994_AIF1CLK_RATE_MASK, 0x1);
2340                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2341                                     WM8994_AIF2CLK_RATE_MASK, 0x1);
2342         } else if (wm8994->aifdiv[0]) {
2343                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2344                                     WM8994_AIF1CLK_RATE_MASK,
2345                                     wm8994->aifdiv[0]);
2346                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2347                                     WM8994_AIF2CLK_RATE_MASK,
2348                                     wm8994->aifdiv[1]);
2349
2350                 wm8994->aifdiv[0] = 0;
2351                 wm8994->aifdiv[1] = 0;
2352         }
2353
2354         return 0;
2355 }
2356
2357 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2358 {
2359         struct completion *completion = data;
2360
2361         complete(completion);
2362
2363         return IRQ_HANDLED;
2364 }
2365
2366 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2367
2368 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2369                           unsigned int freq_in, unsigned int freq_out)
2370 {
2371         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2372 }
2373
2374 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2375                 int clk_id, unsigned int freq, int dir)
2376 {
2377         struct snd_soc_codec *codec = dai->codec;
2378         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2379         int i;
2380
2381         switch (dai->id) {
2382         case 1:
2383         case 2:
2384                 break;
2385
2386         default:
2387                 /* AIF3 shares clocking with AIF1/2 */
2388                 return -EINVAL;
2389         }
2390
2391         switch (clk_id) {
2392         case WM8994_SYSCLK_MCLK1:
2393                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2394                 wm8994->mclk[0] = freq;
2395                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2396                         dai->id, freq);
2397                 break;
2398
2399         case WM8994_SYSCLK_MCLK2:
2400                 /* TODO: Set GPIO AF */
2401                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2402                 wm8994->mclk[1] = freq;
2403                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2404                         dai->id, freq);
2405                 break;
2406
2407         case WM8994_SYSCLK_FLL1:
2408                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2409                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2410                 break;
2411
2412         case WM8994_SYSCLK_FLL2:
2413                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2414                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2415                 break;
2416
2417         case WM8994_SYSCLK_OPCLK:
2418                 /* Special case - a division (times 10) is given and
2419                  * no effect on main clocking.
2420                  */
2421                 if (freq) {
2422                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2423                                 if (opclk_divs[i] == freq)
2424                                         break;
2425                         if (i == ARRAY_SIZE(opclk_divs))
2426                                 return -EINVAL;
2427                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2428                                             WM8994_OPCLK_DIV_MASK, i);
2429                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2430                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2431                 } else {
2432                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2433                                             WM8994_OPCLK_ENA, 0);
2434                 }
2435
2436         default:
2437                 return -EINVAL;
2438         }
2439
2440         configure_clock(codec);
2441
2442         /*
2443          * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2444          * for detection.
2445          */
2446         if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2447                 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2448
2449                 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2450                         & WM8994_AIF1CLK_RATE_MASK;
2451                 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2452                         & WM8994_AIF1CLK_RATE_MASK;
2453
2454                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2455                                     WM8994_AIF1CLK_RATE_MASK, 0x1);
2456                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2457                                     WM8994_AIF2CLK_RATE_MASK, 0x1);
2458         } else if (wm8994->aifdiv[0]) {
2459                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2460                                     WM8994_AIF1CLK_RATE_MASK,
2461                                     wm8994->aifdiv[0]);
2462                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2463                                     WM8994_AIF2CLK_RATE_MASK,
2464                                     wm8994->aifdiv[1]);
2465
2466                 wm8994->aifdiv[0] = 0;
2467                 wm8994->aifdiv[1] = 0;
2468         }
2469
2470         return 0;
2471 }
2472
2473 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2474                                  enum snd_soc_bias_level level)
2475 {
2476         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2477         struct wm8994 *control = wm8994->wm8994;
2478
2479         wm_hubs_set_bias_level(codec, level);
2480
2481         switch (level) {
2482         case SND_SOC_BIAS_ON:
2483                 break;
2484
2485         case SND_SOC_BIAS_PREPARE:
2486                 /* MICBIAS into regulating mode */
2487                 switch (control->type) {
2488                 case WM8958:
2489                 case WM1811:
2490                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2491                                             WM8958_MICB1_MODE, 0);
2492                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2493                                             WM8958_MICB2_MODE, 0);
2494                         break;
2495                 default:
2496                         break;
2497                 }
2498
2499                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY)
2500                         active_reference(codec);
2501                 break;
2502
2503         case SND_SOC_BIAS_STANDBY:
2504                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
2505                         switch (control->type) {
2506                         case WM8958:
2507                                 if (control->revision == 0) {
2508                                         /* Optimise performance for rev A */
2509                                         snd_soc_update_bits(codec,
2510                                                             WM8958_CHARGE_PUMP_2,
2511                                                             WM8958_CP_DISCH,
2512                                                             WM8958_CP_DISCH);
2513                                 }
2514                                 break;
2515
2516                         default:
2517                                 break;
2518                         }
2519
2520                         /* Discharge LINEOUT1 & 2 */
2521                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2522                                             WM8994_LINEOUT1_DISCH |
2523                                             WM8994_LINEOUT2_DISCH,
2524                                             WM8994_LINEOUT1_DISCH |
2525                                             WM8994_LINEOUT2_DISCH);
2526                 }
2527
2528                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE)
2529                         active_dereference(codec);
2530
2531                 /* MICBIAS into bypass mode on newer devices */
2532                 switch (control->type) {
2533                 case WM8958:
2534                 case WM1811:
2535                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2536                                             WM8958_MICB1_MODE,
2537                                             WM8958_MICB1_MODE);
2538                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2539                                             WM8958_MICB2_MODE,
2540                                             WM8958_MICB2_MODE);
2541                         break;
2542                 default:
2543                         break;
2544                 }
2545                 break;
2546
2547         case SND_SOC_BIAS_OFF:
2548                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY)
2549                         wm8994->cur_fw = NULL;
2550                 break;
2551         }
2552
2553         return 0;
2554 }
2555
2556 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2557 {
2558         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2559         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2560
2561         switch (mode) {
2562         case WM8994_VMID_NORMAL:
2563                 snd_soc_dapm_mutex_lock(dapm);
2564
2565                 if (wm8994->hubs.lineout1_se) {
2566                         snd_soc_dapm_disable_pin_unlocked(dapm,
2567                                                           "LINEOUT1N Driver");
2568                         snd_soc_dapm_disable_pin_unlocked(dapm,
2569                                                           "LINEOUT1P Driver");
2570                 }
2571                 if (wm8994->hubs.lineout2_se) {
2572                         snd_soc_dapm_disable_pin_unlocked(dapm,
2573                                                           "LINEOUT2N Driver");
2574                         snd_soc_dapm_disable_pin_unlocked(dapm,
2575                                                           "LINEOUT2P Driver");
2576                 }
2577
2578                 /* Do the sync with the old mode to allow it to clean up */
2579                 snd_soc_dapm_sync_unlocked(dapm);
2580                 wm8994->vmid_mode = mode;
2581
2582                 snd_soc_dapm_mutex_unlock(dapm);
2583                 break;
2584
2585         case WM8994_VMID_FORCE:
2586                 snd_soc_dapm_mutex_lock(dapm);
2587
2588                 if (wm8994->hubs.lineout1_se) {
2589                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2590                                                                "LINEOUT1N Driver");
2591                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2592                                                                "LINEOUT1P Driver");
2593                 }
2594                 if (wm8994->hubs.lineout2_se) {
2595                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2596                                                                "LINEOUT2N Driver");
2597                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2598                                                                "LINEOUT2P Driver");
2599                 }
2600
2601                 wm8994->vmid_mode = mode;
2602                 snd_soc_dapm_sync_unlocked(dapm);
2603
2604                 snd_soc_dapm_mutex_unlock(dapm);
2605                 break;
2606
2607         default:
2608                 return -EINVAL;
2609         }
2610
2611         return 0;
2612 }
2613
2614 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2615 {
2616         struct snd_soc_codec *codec = dai->codec;
2617         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2618         struct wm8994 *control = wm8994->wm8994;
2619         int ms_reg;
2620         int aif1_reg;
2621         int dac_reg;
2622         int adc_reg;
2623         int ms = 0;
2624         int aif1 = 0;
2625         int lrclk = 0;
2626
2627         switch (dai->id) {
2628         case 1:
2629                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2630                 aif1_reg = WM8994_AIF1_CONTROL_1;
2631                 dac_reg = WM8994_AIF1DAC_LRCLK;
2632                 adc_reg = WM8994_AIF1ADC_LRCLK;
2633                 break;
2634         case 2:
2635                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2636                 aif1_reg = WM8994_AIF2_CONTROL_1;
2637                 dac_reg = WM8994_AIF1DAC_LRCLK;
2638                 adc_reg = WM8994_AIF1ADC_LRCLK;
2639                 break;
2640         default:
2641                 return -EINVAL;
2642         }
2643
2644         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2645         case SND_SOC_DAIFMT_CBS_CFS:
2646                 break;
2647         case SND_SOC_DAIFMT_CBM_CFM:
2648                 ms = WM8994_AIF1_MSTR;
2649                 break;
2650         default:
2651                 return -EINVAL;
2652         }
2653
2654         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2655         case SND_SOC_DAIFMT_DSP_B:
2656                 aif1 |= WM8994_AIF1_LRCLK_INV;
2657                 lrclk |= WM8958_AIF1_LRCLK_INV;
2658                 /* fall through */
2659         case SND_SOC_DAIFMT_DSP_A:
2660                 aif1 |= 0x18;
2661                 break;
2662         case SND_SOC_DAIFMT_I2S:
2663                 aif1 |= 0x10;
2664                 break;
2665         case SND_SOC_DAIFMT_RIGHT_J:
2666                 break;
2667         case SND_SOC_DAIFMT_LEFT_J:
2668                 aif1 |= 0x8;
2669                 break;
2670         default:
2671                 return -EINVAL;
2672         }
2673
2674         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2675         case SND_SOC_DAIFMT_DSP_A:
2676         case SND_SOC_DAIFMT_DSP_B:
2677                 /* frame inversion not valid for DSP modes */
2678                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2679                 case SND_SOC_DAIFMT_NB_NF:
2680                         break;
2681                 case SND_SOC_DAIFMT_IB_NF:
2682                         aif1 |= WM8994_AIF1_BCLK_INV;
2683                         break;
2684                 default:
2685                         return -EINVAL;
2686                 }
2687                 break;
2688
2689         case SND_SOC_DAIFMT_I2S:
2690         case SND_SOC_DAIFMT_RIGHT_J:
2691         case SND_SOC_DAIFMT_LEFT_J:
2692                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2693                 case SND_SOC_DAIFMT_NB_NF:
2694                         break;
2695                 case SND_SOC_DAIFMT_IB_IF:
2696                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2697                         lrclk |= WM8958_AIF1_LRCLK_INV;
2698                         break;
2699                 case SND_SOC_DAIFMT_IB_NF:
2700                         aif1 |= WM8994_AIF1_BCLK_INV;
2701                         break;
2702                 case SND_SOC_DAIFMT_NB_IF:
2703                         aif1 |= WM8994_AIF1_LRCLK_INV;
2704                         lrclk |= WM8958_AIF1_LRCLK_INV;
2705                         break;
2706                 default:
2707                         return -EINVAL;
2708                 }
2709                 break;
2710         default:
2711                 return -EINVAL;
2712         }
2713
2714         /* The AIF2 format configuration needs to be mirrored to AIF3
2715          * on WM8958 if it's in use so just do it all the time. */
2716         switch (control->type) {
2717         case WM1811:
2718         case WM8958:
2719                 if (dai->id == 2)
2720                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2721                                             WM8994_AIF1_LRCLK_INV |
2722                                             WM8958_AIF3_FMT_MASK, aif1);
2723                 break;
2724
2725         default:
2726                 break;
2727         }
2728
2729         snd_soc_update_bits(codec, aif1_reg,
2730                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2731                             WM8994_AIF1_FMT_MASK,
2732                             aif1);
2733         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2734                             ms);
2735         snd_soc_update_bits(codec, dac_reg,
2736                             WM8958_AIF1_LRCLK_INV, lrclk);
2737         snd_soc_update_bits(codec, adc_reg,
2738                             WM8958_AIF1_LRCLK_INV, lrclk);
2739
2740         return 0;
2741 }
2742
2743 static struct {
2744         int val, rate;
2745 } srs[] = {
2746         { 0,   8000 },
2747         { 1,  11025 },
2748         { 2,  12000 },
2749         { 3,  16000 },
2750         { 4,  22050 },
2751         { 5,  24000 },
2752         { 6,  32000 },
2753         { 7,  44100 },
2754         { 8,  48000 },
2755         { 9,  88200 },
2756         { 10, 96000 },
2757 };
2758
2759 static int fs_ratios[] = {
2760         64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
2761 };
2762
2763 static int bclk_divs[] = {
2764         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2765         640, 880, 960, 1280, 1760, 1920
2766 };
2767
2768 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2769                             struct snd_pcm_hw_params *params,
2770                             struct snd_soc_dai *dai)
2771 {
2772         struct snd_soc_codec *codec = dai->codec;
2773         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2774         struct wm8994 *control = wm8994->wm8994;
2775         struct wm8994_pdata *pdata = &control->pdata;
2776         int aif1_reg;
2777         int aif2_reg;
2778         int bclk_reg;
2779         int lrclk_reg;
2780         int rate_reg;
2781         int aif1 = 0;
2782         int aif2 = 0;
2783         int bclk = 0;
2784         int lrclk = 0;
2785         int rate_val = 0;
2786         int id = dai->id - 1;
2787
2788         int i, cur_val, best_val, bclk_rate, best;
2789
2790         switch (dai->id) {
2791         case 1:
2792                 aif1_reg = WM8994_AIF1_CONTROL_1;
2793                 aif2_reg = WM8994_AIF1_CONTROL_2;
2794                 bclk_reg = WM8994_AIF1_BCLK;
2795                 rate_reg = WM8994_AIF1_RATE;
2796                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2797                     wm8994->lrclk_shared[0]) {
2798                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2799                 } else {
2800                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2801                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2802                 }
2803                 break;
2804         case 2:
2805                 aif1_reg = WM8994_AIF2_CONTROL_1;
2806                 aif2_reg = WM8994_AIF2_CONTROL_2;
2807                 bclk_reg = WM8994_AIF2_BCLK;
2808                 rate_reg = WM8994_AIF2_RATE;
2809                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2810                     wm8994->lrclk_shared[1]) {
2811                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2812                 } else {
2813                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2814                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2815                 }
2816                 break;
2817         default:
2818                 return -EINVAL;
2819         }
2820
2821         bclk_rate = params_rate(params);
2822         switch (params_width(params)) {
2823         case 16:
2824                 bclk_rate *= 16;
2825                 break;
2826         case 20:
2827                 bclk_rate *= 20;
2828                 aif1 |= 0x20;
2829                 break;
2830         case 24:
2831                 bclk_rate *= 24;
2832                 aif1 |= 0x40;
2833                 break;
2834         case 32:
2835                 bclk_rate *= 32;
2836                 aif1 |= 0x60;
2837                 break;
2838         default:
2839                 return -EINVAL;
2840         }
2841
2842         wm8994->channels[id] = params_channels(params);
2843         if (pdata->max_channels_clocked[id] &&
2844             wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2845                 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2846                         pdata->max_channels_clocked[id], wm8994->channels[id]);
2847                 wm8994->channels[id] = pdata->max_channels_clocked[id];
2848         }
2849
2850         switch (wm8994->channels[id]) {
2851         case 1:
2852         case 2:
2853                 bclk_rate *= 2;
2854                 break;
2855         default:
2856                 bclk_rate *= 4;
2857                 break;
2858         }
2859
2860         /* Try to find an appropriate sample rate; look for an exact match. */
2861         for (i = 0; i < ARRAY_SIZE(srs); i++)
2862                 if (srs[i].rate == params_rate(params))
2863                         break;
2864         if (i == ARRAY_SIZE(srs))
2865                 return -EINVAL;
2866         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2867
2868         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2869         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2870                 dai->id, wm8994->aifclk[id], bclk_rate);
2871
2872         if (wm8994->channels[id] == 1 &&
2873             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2874                 aif2 |= WM8994_AIF1_MONO;
2875
2876         if (wm8994->aifclk[id] == 0) {
2877                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2878                 return -EINVAL;
2879         }
2880
2881         /* AIFCLK/fs ratio; look for a close match in either direction */
2882         best = 0;
2883         best_val = abs((fs_ratios[0] * params_rate(params))
2884                        - wm8994->aifclk[id]);
2885         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2886                 cur_val = abs((fs_ratios[i] * params_rate(params))
2887                               - wm8994->aifclk[id]);
2888                 if (cur_val >= best_val)
2889                         continue;
2890                 best = i;
2891                 best_val = cur_val;
2892         }
2893         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2894                 dai->id, fs_ratios[best]);
2895         rate_val |= best;
2896
2897         /* We may not get quite the right frequency if using
2898          * approximate clocks so look for the closest match that is
2899          * higher than the target (we need to ensure that there enough
2900          * BCLKs to clock out the samples).
2901          */
2902         best = 0;
2903         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2904                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2905                 if (cur_val < 0) /* BCLK table is sorted */
2906                         break;
2907                 best = i;
2908         }
2909         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2910         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2911                 bclk_divs[best], bclk_rate);
2912         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2913
2914         lrclk = bclk_rate / params_rate(params);
2915         if (!lrclk) {
2916                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2917                         bclk_rate);
2918                 return -EINVAL;
2919         }
2920         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2921                 lrclk, bclk_rate / lrclk);
2922
2923         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2924         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2925         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2926         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2927                             lrclk);
2928         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2929                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2930
2931         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2932                 switch (dai->id) {
2933                 case 1:
2934                         wm8994->dac_rates[0] = params_rate(params);
2935                         wm8994_set_retune_mobile(codec, 0);
2936                         wm8994_set_retune_mobile(codec, 1);
2937                         break;
2938                 case 2:
2939                         wm8994->dac_rates[1] = params_rate(params);
2940                         wm8994_set_retune_mobile(codec, 2);
2941                         break;
2942                 }
2943         }
2944
2945         return 0;
2946 }
2947
2948 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2949                                  struct snd_pcm_hw_params *params,
2950                                  struct snd_soc_dai *dai)
2951 {
2952         struct snd_soc_codec *codec = dai->codec;
2953         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2954         struct wm8994 *control = wm8994->wm8994;
2955         int aif1_reg;
2956         int aif1 = 0;
2957
2958         switch (dai->id) {
2959         case 3:
2960                 switch (control->type) {
2961                 case WM1811:
2962                 case WM8958:
2963                         aif1_reg = WM8958_AIF3_CONTROL_1;
2964                         break;
2965                 default:
2966                         return 0;
2967                 }
2968                 break;
2969         default:
2970                 return 0;
2971         }
2972
2973         switch (params_width(params)) {
2974         case 16:
2975                 break;
2976         case 20:
2977                 aif1 |= 0x20;
2978                 break;
2979         case 24:
2980                 aif1 |= 0x40;
2981                 break;
2982         case 32:
2983                 aif1 |= 0x60;
2984                 break;
2985         default:
2986                 return -EINVAL;
2987         }
2988
2989         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2990 }
2991
2992 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2993 {
2994         struct snd_soc_codec *codec = codec_dai->codec;
2995         int mute_reg;
2996         int reg;
2997
2998         switch (codec_dai->id) {
2999         case 1:
3000                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
3001                 break;
3002         case 2:
3003                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3004                 break;
3005         default:
3006                 return -EINVAL;
3007         }
3008
3009         if (mute)
3010                 reg = WM8994_AIF1DAC1_MUTE;
3011         else
3012                 reg = 0;
3013
3014         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3015
3016         return 0;
3017 }
3018
3019 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3020 {
3021         struct snd_soc_codec *codec = codec_dai->codec;
3022         int reg, val, mask;
3023
3024         switch (codec_dai->id) {
3025         case 1:
3026                 reg = WM8994_AIF1_MASTER_SLAVE;
3027                 mask = WM8994_AIF1_TRI;
3028                 break;
3029         case 2:
3030                 reg = WM8994_AIF2_MASTER_SLAVE;
3031                 mask = WM8994_AIF2_TRI;
3032                 break;
3033         default:
3034                 return -EINVAL;
3035         }
3036
3037         if (tristate)
3038                 val = mask;
3039         else
3040                 val = 0;
3041
3042         return snd_soc_update_bits(codec, reg, mask, val);
3043 }
3044
3045 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3046 {
3047         struct snd_soc_codec *codec = dai->codec;
3048
3049         /* Disable the pulls on the AIF if we're using it to save power. */
3050         snd_soc_update_bits(codec, WM8994_GPIO_3,
3051                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
3052         snd_soc_update_bits(codec, WM8994_GPIO_4,
3053                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
3054         snd_soc_update_bits(codec, WM8994_GPIO_5,
3055                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
3056
3057         return 0;
3058 }
3059
3060 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3061
3062 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3063                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3064
3065 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3066         .set_sysclk     = wm8994_set_dai_sysclk,
3067         .set_fmt        = wm8994_set_dai_fmt,
3068         .hw_params      = wm8994_hw_params,
3069         .digital_mute   = wm8994_aif_mute,
3070         .set_pll        = wm8994_set_fll,
3071         .set_tristate   = wm8994_set_tristate,
3072 };
3073
3074 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3075         .set_sysclk     = wm8994_set_dai_sysclk,
3076         .set_fmt        = wm8994_set_dai_fmt,
3077         .hw_params      = wm8994_hw_params,
3078         .digital_mute   = wm8994_aif_mute,
3079         .set_pll        = wm8994_set_fll,
3080         .set_tristate   = wm8994_set_tristate,
3081 };
3082
3083 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3084         .hw_params      = wm8994_aif3_hw_params,
3085 };
3086
3087 static struct snd_soc_dai_driver wm8994_dai[] = {
3088         {
3089                 .name = "wm8994-aif1",
3090                 .id = 1,
3091                 .playback = {
3092                         .stream_name = "AIF1 Playback",
3093                         .channels_min = 1,
3094                         .channels_max = 2,
3095                         .rates = WM8994_RATES,
3096                         .formats = WM8994_FORMATS,
3097                         .sig_bits = 24,
3098                 },
3099                 .capture = {
3100                         .stream_name = "AIF1 Capture",
3101                         .channels_min = 1,
3102                         .channels_max = 2,
3103                         .rates = WM8994_RATES,
3104                         .formats = WM8994_FORMATS,
3105                         .sig_bits = 24,
3106                  },
3107                 .ops = &wm8994_aif1_dai_ops,
3108         },
3109         {
3110                 .name = "wm8994-aif2",
3111                 .id = 2,
3112                 .playback = {
3113                         .stream_name = "AIF2 Playback",
3114                         .channels_min = 1,
3115                         .channels_max = 2,
3116                         .rates = WM8994_RATES,
3117                         .formats = WM8994_FORMATS,
3118                         .sig_bits = 24,
3119                 },
3120                 .capture = {
3121                         .stream_name = "AIF2 Capture",
3122                         .channels_min = 1,
3123                         .channels_max = 2,
3124                         .rates = WM8994_RATES,
3125                         .formats = WM8994_FORMATS,
3126                         .sig_bits = 24,
3127                 },
3128                 .probe = wm8994_aif2_probe,
3129                 .ops = &wm8994_aif2_dai_ops,
3130         },
3131         {
3132                 .name = "wm8994-aif3",
3133                 .id = 3,
3134                 .playback = {
3135                         .stream_name = "AIF3 Playback",
3136                         .channels_min = 1,
3137                         .channels_max = 2,
3138                         .rates = WM8994_RATES,
3139                         .formats = WM8994_FORMATS,
3140                         .sig_bits = 24,
3141                 },
3142                 .capture = {
3143                         .stream_name = "AIF3 Capture",
3144                         .channels_min = 1,
3145                         .channels_max = 2,
3146                         .rates = WM8994_RATES,
3147                         .formats = WM8994_FORMATS,
3148                         .sig_bits = 24,
3149                  },
3150                 .ops = &wm8994_aif3_dai_ops,
3151         }
3152 };
3153
3154 #ifdef CONFIG_PM
3155 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3156 {
3157         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3158         int i, ret;
3159
3160         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3161                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3162                        sizeof(struct wm8994_fll_config));
3163                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3164                 if (ret < 0)
3165                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3166                                  i + 1, ret);
3167         }
3168
3169         snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
3170
3171         return 0;
3172 }
3173
3174 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3175 {
3176         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3177         int i, ret;
3178
3179         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3180                 if (!wm8994->fll_suspend[i].out)
3181                         continue;
3182
3183                 ret = _wm8994_set_fll(codec, i + 1,
3184                                      wm8994->fll_suspend[i].src,
3185                                      wm8994->fll_suspend[i].in,
3186                                      wm8994->fll_suspend[i].out);
3187                 if (ret < 0)
3188                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3189                                  i + 1, ret);
3190         }
3191
3192         return 0;
3193 }
3194 #else
3195 #define wm8994_codec_suspend NULL
3196 #define wm8994_codec_resume NULL
3197 #endif
3198
3199 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3200 {
3201         struct snd_soc_codec *codec = wm8994->hubs.codec;
3202         struct wm8994 *control = wm8994->wm8994;
3203         struct wm8994_pdata *pdata = &control->pdata;
3204         struct snd_kcontrol_new controls[] = {
3205                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3206                              wm8994->retune_mobile_enum,
3207                              wm8994_get_retune_mobile_enum,
3208                              wm8994_put_retune_mobile_enum),
3209                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3210                              wm8994->retune_mobile_enum,
3211                              wm8994_get_retune_mobile_enum,
3212                              wm8994_put_retune_mobile_enum),
3213                 SOC_ENUM_EXT("AIF2 EQ Mode",
3214                              wm8994->retune_mobile_enum,
3215                              wm8994_get_retune_mobile_enum,
3216                              wm8994_put_retune_mobile_enum),
3217         };
3218         int ret, i, j;
3219         const char **t;
3220
3221         /* We need an array of texts for the enum API but the number
3222          * of texts is likely to be less than the number of
3223          * configurations due to the sample rate dependency of the
3224          * configurations. */
3225         wm8994->num_retune_mobile_texts = 0;
3226         wm8994->retune_mobile_texts = NULL;
3227         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3228                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3229                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
3230                                    wm8994->retune_mobile_texts[j]) == 0)
3231                                 break;
3232                 }
3233
3234                 if (j != wm8994->num_retune_mobile_texts)
3235                         continue;
3236
3237                 /* Expand the array... */
3238                 t = krealloc(wm8994->retune_mobile_texts,
3239                              sizeof(char *) *
3240                              (wm8994->num_retune_mobile_texts + 1),
3241                              GFP_KERNEL);
3242                 if (t == NULL)
3243                         continue;
3244
3245                 /* ...store the new entry... */
3246                 t[wm8994->num_retune_mobile_texts] =
3247                         pdata->retune_mobile_cfgs[i].name;
3248
3249                 /* ...and remember the new version. */
3250                 wm8994->num_retune_mobile_texts++;
3251                 wm8994->retune_mobile_texts = t;
3252         }
3253
3254         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3255                 wm8994->num_retune_mobile_texts);
3256
3257         wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3258         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3259
3260         ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3261                                    ARRAY_SIZE(controls));
3262         if (ret != 0)
3263                 dev_err(wm8994->hubs.codec->dev,
3264                         "Failed to add ReTune Mobile controls: %d\n", ret);
3265 }
3266
3267 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3268 {
3269         struct snd_soc_codec *codec = wm8994->hubs.codec;
3270         struct wm8994 *control = wm8994->wm8994;
3271         struct wm8994_pdata *pdata = &control->pdata;
3272         int ret, i;
3273
3274         if (!pdata)
3275                 return;
3276
3277         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3278                                       pdata->lineout2_diff,
3279                                       pdata->lineout1fb,
3280                                       pdata->lineout2fb,
3281                                       pdata->jd_scthr,
3282                                       pdata->jd_thr,
3283                                       pdata->micb1_delay,
3284                                       pdata->micb2_delay,
3285                                       pdata->micbias1_lvl,
3286                                       pdata->micbias2_lvl);
3287
3288         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3289
3290         if (pdata->num_drc_cfgs) {
3291                 struct snd_kcontrol_new controls[] = {
3292                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3293                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3294                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3295                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3296                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3297                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3298                 };
3299
3300                 /* We need an array of texts for the enum API */
3301                 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3302                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3303                 if (!wm8994->drc_texts)
3304                         return;
3305
3306                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3307                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3308
3309                 wm8994->drc_enum.items = pdata->num_drc_cfgs;
3310                 wm8994->drc_enum.texts = wm8994->drc_texts;
3311
3312                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3313                                            ARRAY_SIZE(controls));
3314                 for (i = 0; i < WM8994_NUM_DRC; i++)
3315                         wm8994_set_drc(codec, i);
3316         } else {
3317                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3318                                                  wm8994_drc_controls,
3319                                                  ARRAY_SIZE(wm8994_drc_controls));
3320         }
3321
3322         if (ret != 0)
3323                 dev_err(wm8994->hubs.codec->dev,
3324                         "Failed to add DRC mode controls: %d\n", ret);
3325
3326
3327         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3328                 pdata->num_retune_mobile_cfgs);
3329
3330         if (pdata->num_retune_mobile_cfgs)
3331                 wm8994_handle_retune_mobile_pdata(wm8994);
3332         else
3333                 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3334                                      ARRAY_SIZE(wm8994_eq_controls));
3335
3336         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3337                 if (pdata->micbias[i]) {
3338                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3339                                 pdata->micbias[i] & 0xffff);
3340                 }
3341         }
3342 }
3343
3344 /**
3345  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3346  *
3347  * @codec:   WM8994 codec
3348  * @jack:    jack to report detection events on
3349  * @micbias: microphone bias to detect on
3350  *
3351  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3352  * being used to bring out signals to the processor then only platform
3353  * data configuration is needed for WM8994 and processor GPIOs should
3354  * be configured using snd_soc_jack_add_gpios() instead.
3355  *
3356  * Configuration of detection levels is available via the micbias1_lvl
3357  * and micbias2_lvl platform data members.
3358  */
3359 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3360                       int micbias)
3361 {
3362         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3363         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3364         struct wm8994_micdet *micdet;
3365         struct wm8994 *control = wm8994->wm8994;
3366         int reg, ret;
3367
3368         if (control->type != WM8994) {
3369                 dev_warn(codec->dev, "Not a WM8994\n");
3370                 return -EINVAL;
3371         }
3372
3373         switch (micbias) {
3374         case 1:
3375                 micdet = &wm8994->micdet[0];
3376                 if (jack)
3377                         ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
3378                 else
3379                         ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
3380                 break;
3381         case 2:
3382                 micdet = &wm8994->micdet[1];
3383                 if (jack)
3384                         ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
3385                 else
3386                         ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
3387                 break;
3388         default:
3389                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3390                 return -EINVAL;
3391         }
3392
3393         if (ret != 0)
3394                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3395                          micbias, ret);
3396
3397         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3398                 micbias, jack);
3399
3400         /* Store the configuration */
3401         micdet->jack = jack;
3402         micdet->detecting = true;
3403
3404         /* If either of the jacks is set up then enable detection */
3405         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3406                 reg = WM8994_MICD_ENA;
3407         else
3408                 reg = 0;
3409
3410         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3411
3412         /* enable MICDET and MICSHRT deboune */
3413         snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3414                             WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3415                             WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3416                             WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3417
3418         snd_soc_dapm_sync(dapm);
3419
3420         return 0;
3421 }
3422 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3423
3424 static void wm8994_mic_work(struct work_struct *work)
3425 {
3426         struct wm8994_priv *priv = container_of(work,
3427                                                 struct wm8994_priv,
3428                                                 mic_work.work);
3429         struct regmap *regmap = priv->wm8994->regmap;
3430         struct device *dev = priv->wm8994->dev;
3431         unsigned int reg;
3432         int ret;
3433         int report;
3434
3435         pm_runtime_get_sync(dev);
3436
3437         ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3438         if (ret < 0) {
3439                 dev_err(dev, "Failed to read microphone status: %d\n",
3440                         ret);
3441                 pm_runtime_put(dev);
3442                 return;
3443         }
3444
3445         dev_dbg(dev, "Microphone status: %x\n", reg);
3446
3447         report = 0;
3448         if (reg & WM8994_MIC1_DET_STS) {
3449                 if (priv->micdet[0].detecting)
3450                         report = SND_JACK_HEADSET;
3451         }
3452         if (reg & WM8994_MIC1_SHRT_STS) {
3453                 if (priv->micdet[0].detecting)
3454                         report = SND_JACK_HEADPHONE;
3455                 else
3456                         report |= SND_JACK_BTN_0;
3457         }
3458         if (report)
3459                 priv->micdet[0].detecting = false;
3460         else
3461                 priv->micdet[0].detecting = true;
3462
3463         snd_soc_jack_report(priv->micdet[0].jack, report,
3464                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3465
3466         report = 0;
3467         if (reg & WM8994_MIC2_DET_STS) {
3468                 if (priv->micdet[1].detecting)
3469                         report = SND_JACK_HEADSET;
3470         }
3471         if (reg & WM8994_MIC2_SHRT_STS) {
3472                 if (priv->micdet[1].detecting)
3473                         report = SND_JACK_HEADPHONE;
3474                 else
3475                         report |= SND_JACK_BTN_0;
3476         }
3477         if (report)
3478                 priv->micdet[1].detecting = false;
3479         else
3480                 priv->micdet[1].detecting = true;
3481
3482         snd_soc_jack_report(priv->micdet[1].jack, report,
3483                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3484
3485         pm_runtime_put(dev);
3486 }
3487
3488 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3489 {
3490         struct wm8994_priv *priv = data;
3491         struct snd_soc_codec *codec = priv->hubs.codec;
3492
3493 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3494         trace_snd_soc_jack_irq(dev_name(codec->dev));
3495 #endif
3496
3497         pm_wakeup_event(codec->dev, 300);
3498
3499         queue_delayed_work(system_power_efficient_wq,
3500                            &priv->mic_work, msecs_to_jiffies(250));
3501
3502         return IRQ_HANDLED;
3503 }
3504
3505 /* Should be called with accdet_lock held */
3506 static void wm1811_micd_stop(struct snd_soc_codec *codec)
3507 {
3508         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3509         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3510
3511         if (!wm8994->jackdet)
3512                 return;
3513
3514         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3515
3516         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3517
3518         if (wm8994->wm8994->pdata.jd_ext_cap)
3519                 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
3520 }
3521
3522 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3523 {
3524         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3525         int report;
3526
3527         report = 0;
3528         if (status & 0x4)
3529                 report |= SND_JACK_BTN_0;
3530
3531         if (status & 0x8)
3532                 report |= SND_JACK_BTN_1;
3533
3534         if (status & 0x10)
3535                 report |= SND_JACK_BTN_2;
3536
3537         if (status & 0x20)
3538                 report |= SND_JACK_BTN_3;
3539
3540         if (status & 0x40)
3541                 report |= SND_JACK_BTN_4;
3542
3543         if (status & 0x80)
3544                 report |= SND_JACK_BTN_5;
3545
3546         snd_soc_jack_report(wm8994->micdet[0].jack, report,
3547                             wm8994->btn_mask);
3548 }
3549
3550 static void wm8958_open_circuit_work(struct work_struct *work)
3551 {
3552         struct wm8994_priv *wm8994 = container_of(work,
3553                                                   struct wm8994_priv,
3554                                                   open_circuit_work.work);
3555         struct device *dev = wm8994->wm8994->dev;
3556
3557         mutex_lock(&wm8994->accdet_lock);
3558
3559         wm1811_micd_stop(wm8994->hubs.codec);
3560
3561         dev_dbg(dev, "Reporting open circuit\n");
3562
3563         wm8994->jack_mic = false;
3564         wm8994->mic_detecting = true;
3565
3566         wm8958_micd_set_rate(wm8994->hubs.codec);
3567
3568         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3569                             wm8994->btn_mask |
3570                             SND_JACK_HEADSET);
3571
3572         mutex_unlock(&wm8994->accdet_lock);
3573 }
3574
3575 static void wm8958_mic_id(void *data, u16 status)
3576 {
3577         struct snd_soc_codec *codec = data;
3578         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3579
3580         /* Either nothing present or just starting detection */
3581         if (!(status & WM8958_MICD_STS)) {
3582                 /* If nothing present then clear our statuses */
3583                 dev_dbg(codec->dev, "Detected open circuit\n");
3584
3585                 queue_delayed_work(system_power_efficient_wq,
3586                                    &wm8994->open_circuit_work,
3587                                    msecs_to_jiffies(2500));
3588                 return;
3589         }
3590
3591         /* If the measurement is showing a high impedence we've got a
3592          * microphone.
3593          */
3594         if (status & 0x600) {
3595                 dev_dbg(codec->dev, "Detected microphone\n");
3596
3597                 wm8994->mic_detecting = false;
3598                 wm8994->jack_mic = true;
3599
3600                 wm8958_micd_set_rate(codec);
3601
3602                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3603                                     SND_JACK_HEADSET);
3604         }
3605
3606
3607         if (status & 0xfc) {
3608                 dev_dbg(codec->dev, "Detected headphone\n");
3609                 wm8994->mic_detecting = false;
3610
3611                 wm8958_micd_set_rate(codec);
3612
3613                 /* If we have jackdet that will detect removal */
3614                 wm1811_micd_stop(codec);
3615
3616                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3617                                     SND_JACK_HEADSET);
3618         }
3619 }
3620
3621 /* Deferred mic detection to allow for extra settling time */
3622 static void wm1811_mic_work(struct work_struct *work)
3623 {
3624         struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3625                                                   mic_work.work);
3626         struct wm8994 *control = wm8994->wm8994;
3627         struct snd_soc_codec *codec = wm8994->hubs.codec;
3628         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3629
3630         pm_runtime_get_sync(codec->dev);
3631
3632         /* If required for an external cap force MICBIAS on */
3633         if (control->pdata.jd_ext_cap) {
3634                 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
3635                 snd_soc_dapm_sync(dapm);
3636         }
3637
3638         mutex_lock(&wm8994->accdet_lock);
3639
3640         dev_dbg(codec->dev, "Starting mic detection\n");
3641
3642         /* Use a user-supplied callback if we have one */
3643         if (wm8994->micd_cb) {
3644                 wm8994->micd_cb(wm8994->micd_cb_data);
3645         } else {
3646                 /*
3647                  * Start off measument of microphone impedence to find out
3648                  * what's actually there.
3649                  */
3650                 wm8994->mic_detecting = true;
3651                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3652
3653                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3654                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3655         }
3656
3657         mutex_unlock(&wm8994->accdet_lock);
3658
3659         pm_runtime_put(codec->dev);
3660 }
3661
3662 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3663 {
3664         struct wm8994_priv *wm8994 = data;
3665         struct wm8994 *control = wm8994->wm8994;
3666         struct snd_soc_codec *codec = wm8994->hubs.codec;
3667         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3668         int reg, delay;
3669         bool present;
3670
3671         pm_runtime_get_sync(codec->dev);
3672
3673         cancel_delayed_work_sync(&wm8994->mic_complete_work);
3674
3675         mutex_lock(&wm8994->accdet_lock);
3676
3677         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3678         if (reg < 0) {
3679                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3680                 mutex_unlock(&wm8994->accdet_lock);
3681                 pm_runtime_put(codec->dev);
3682                 return IRQ_NONE;
3683         }
3684
3685         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3686
3687         present = reg & WM1811_JACKDET_LVL;
3688
3689         if (present) {
3690                 dev_dbg(codec->dev, "Jack detected\n");
3691
3692                 wm8958_micd_set_rate(codec);
3693
3694                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3695                                     WM8958_MICB2_DISCH, 0);
3696
3697                 /* Disable debounce while inserted */
3698                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3699                                     WM1811_JACKDET_DB, 0);
3700
3701                 delay = control->pdata.micdet_delay;
3702                 queue_delayed_work(system_power_efficient_wq,
3703                                    &wm8994->mic_work,
3704                                    msecs_to_jiffies(delay));
3705         } else {
3706                 dev_dbg(codec->dev, "Jack not detected\n");
3707
3708                 cancel_delayed_work_sync(&wm8994->mic_work);
3709
3710                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3711                                     WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3712
3713                 /* Enable debounce while removed */
3714                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3715                                     WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3716
3717                 wm8994->mic_detecting = false;
3718                 wm8994->jack_mic = false;
3719                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3720                                     WM8958_MICD_ENA, 0);
3721                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3722         }
3723
3724         mutex_unlock(&wm8994->accdet_lock);
3725
3726         /* Turn off MICBIAS if it was on for an external cap */
3727         if (control->pdata.jd_ext_cap && !present)
3728                 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
3729
3730         if (present)
3731                 snd_soc_jack_report(wm8994->micdet[0].jack,
3732                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3733         else
3734                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3735                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3736                                     wm8994->btn_mask);
3737
3738         /* Since we only report deltas force an update, ensures we
3739          * avoid bootstrapping issues with the core. */
3740         snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3741
3742         pm_runtime_put(codec->dev);
3743         return IRQ_HANDLED;
3744 }
3745
3746 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3747 {
3748         struct wm8994_priv *wm8994 = container_of(work,
3749                                                 struct wm8994_priv,
3750                                                 jackdet_bootstrap.work);
3751         wm1811_jackdet_irq(0, wm8994);
3752 }
3753
3754 /**
3755  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3756  *
3757  * @codec:   WM8958 codec
3758  * @jack:    jack to report detection events on
3759  *
3760  * Enable microphone detection functionality for the WM8958.  By
3761  * default simple detection which supports the detection of up to 6
3762  * buttons plus video and microphone functionality is supported.
3763  *
3764  * The WM8958 has an advanced jack detection facility which is able to
3765  * support complex accessory detection, especially when used in
3766  * conjunction with external circuitry.  In order to provide maximum
3767  * flexiblity a callback is provided which allows a completely custom
3768  * detection algorithm.
3769  */
3770 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3771                       wm1811_micdet_cb det_cb, void *det_cb_data,
3772                       wm1811_mic_id_cb id_cb, void *id_cb_data)
3773 {
3774         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3775         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3776         struct wm8994 *control = wm8994->wm8994;
3777         u16 micd_lvl_sel;
3778
3779         switch (control->type) {
3780         case WM1811:
3781         case WM8958:
3782                 break;
3783         default:
3784                 return -EINVAL;
3785         }
3786
3787         if (jack) {
3788                 snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS");
3789                 snd_soc_dapm_sync(dapm);
3790
3791                 wm8994->micdet[0].jack = jack;
3792
3793                 if (det_cb) {
3794                         wm8994->micd_cb = det_cb;
3795                         wm8994->micd_cb_data = det_cb_data;
3796                 } else {
3797                         wm8994->mic_detecting = true;
3798                         wm8994->jack_mic = false;
3799                 }
3800
3801                 if (id_cb) {
3802                         wm8994->mic_id_cb = id_cb;
3803                         wm8994->mic_id_cb_data = id_cb_data;
3804                 } else {
3805                         wm8994->mic_id_cb = wm8958_mic_id;
3806                         wm8994->mic_id_cb_data = codec;
3807                 }
3808
3809                 wm8958_micd_set_rate(codec);
3810
3811                 /* Detect microphones and short circuits by default */
3812                 if (control->pdata.micd_lvl_sel)
3813                         micd_lvl_sel = control->pdata.micd_lvl_sel;
3814                 else
3815                         micd_lvl_sel = 0x41;
3816
3817                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3818                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3819                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3820
3821                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3822                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3823
3824                 WARN_ON(snd_soc_codec_get_bias_level(codec) > SND_SOC_BIAS_STANDBY);
3825
3826                 /*
3827                  * If we can use jack detection start off with that,
3828                  * otherwise jump straight to microphone detection.
3829                  */
3830                 if (wm8994->jackdet) {
3831                         /* Disable debounce for the initial detect */
3832                         snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3833                                             WM1811_JACKDET_DB, 0);
3834
3835                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
3836                                             WM8958_MICB2_DISCH,
3837                                             WM8958_MICB2_DISCH);
3838                         snd_soc_update_bits(codec, WM8994_LDO_1,
3839                                             WM8994_LDO1_DISCH, 0);
3840                         wm1811_jackdet_set_mode(codec,
3841                                                 WM1811_JACKDET_MODE_JACK);
3842                 } else {
3843                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3844                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3845                 }
3846
3847         } else {
3848                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3849                                     WM8958_MICD_ENA, 0);
3850                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3851                 snd_soc_dapm_disable_pin(dapm, "CLK_SYS");
3852                 snd_soc_dapm_sync(dapm);
3853         }
3854
3855         return 0;
3856 }
3857 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3858
3859 static void wm8958_mic_work(struct work_struct *work)
3860 {
3861         struct wm8994_priv *wm8994 = container_of(work,
3862                                                   struct wm8994_priv,
3863                                                   mic_complete_work.work);
3864         struct snd_soc_codec *codec = wm8994->hubs.codec;
3865
3866         pm_runtime_get_sync(codec->dev);
3867
3868         mutex_lock(&wm8994->accdet_lock);
3869
3870         wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3871
3872         mutex_unlock(&wm8994->accdet_lock);
3873
3874         pm_runtime_put(codec->dev);
3875 }
3876
3877 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3878 {
3879         struct wm8994_priv *wm8994 = data;
3880         struct snd_soc_codec *codec = wm8994->hubs.codec;
3881         int reg, count, ret, id_delay;
3882
3883         /*
3884          * Jack detection may have detected a removal simulataneously
3885          * with an update of the MICDET status; if so it will have
3886          * stopped detection and we can ignore this interrupt.
3887          */
3888         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3889                 return IRQ_HANDLED;
3890
3891         cancel_delayed_work_sync(&wm8994->mic_complete_work);
3892         cancel_delayed_work_sync(&wm8994->open_circuit_work);
3893
3894         pm_runtime_get_sync(codec->dev);
3895
3896         /* We may occasionally read a detection without an impedence
3897          * range being provided - if that happens loop again.
3898          */
3899         count = 10;
3900         do {
3901                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3902                 if (reg < 0) {
3903                         dev_err(codec->dev,
3904                                 "Failed to read mic detect status: %d\n",
3905                                 reg);
3906                         pm_runtime_put(codec->dev);
3907                         return IRQ_NONE;
3908                 }
3909
3910                 if (!(reg & WM8958_MICD_VALID)) {
3911                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3912                         goto out;
3913                 }
3914
3915                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3916                         break;
3917
3918                 msleep(1);
3919         } while (count--);
3920
3921         if (count == 0)
3922                 dev_warn(codec->dev, "No impedance range reported for jack\n");
3923
3924 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3925         trace_snd_soc_jack_irq(dev_name(codec->dev));
3926 #endif
3927
3928         /* Avoid a transient report when the accessory is being removed */
3929         if (wm8994->jackdet) {
3930                 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3931                 if (ret < 0) {
3932                         dev_err(codec->dev, "Failed to read jack status: %d\n",
3933                                 ret);
3934                 } else if (!(ret & WM1811_JACKDET_LVL)) {
3935                         dev_dbg(codec->dev, "Ignoring removed jack\n");
3936                         goto out;
3937                 }
3938         } else if (!(reg & WM8958_MICD_STS)) {
3939                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3940                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3941                                     wm8994->btn_mask);
3942                 wm8994->mic_detecting = true;
3943                 goto out;
3944         }
3945
3946         wm8994->mic_status = reg;
3947         id_delay = wm8994->wm8994->pdata.mic_id_delay;
3948
3949         if (wm8994->mic_detecting)
3950                 queue_delayed_work(system_power_efficient_wq,
3951                                    &wm8994->mic_complete_work,
3952                                    msecs_to_jiffies(id_delay));
3953         else
3954                 wm8958_button_det(codec, reg);
3955
3956 out:
3957         pm_runtime_put(codec->dev);
3958         return IRQ_HANDLED;
3959 }
3960
3961 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3962 {
3963         struct snd_soc_codec *codec = data;
3964
3965         dev_err(codec->dev, "FIFO error\n");
3966
3967         return IRQ_HANDLED;
3968 }
3969
3970 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3971 {
3972         struct snd_soc_codec *codec = data;
3973
3974         dev_err(codec->dev, "Thermal warning\n");
3975
3976         return IRQ_HANDLED;
3977 }
3978
3979 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3980 {
3981         struct snd_soc_codec *codec = data;
3982
3983         dev_crit(codec->dev, "Thermal shutdown\n");
3984
3985         return IRQ_HANDLED;
3986 }
3987
3988 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3989 {
3990         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3991         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3992         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3993         unsigned int reg;
3994         int ret, i;
3995
3996         snd_soc_codec_init_regmap(codec, control->regmap);
3997
3998         wm8994->hubs.codec = codec;
3999
4000         mutex_init(&wm8994->accdet_lock);
4001         INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
4002                           wm1811_jackdet_bootstrap);
4003         INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4004                           wm8958_open_circuit_work);
4005
4006         switch (control->type) {
4007         case WM8994:
4008                 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4009                 break;
4010         case WM1811:
4011                 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4012                 break;
4013         default:
4014                 break;
4015         }
4016
4017         INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4018
4019         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4020                 init_completion(&wm8994->fll_locked[i]);
4021
4022         wm8994->micdet_irq = control->pdata.micdet_irq;
4023
4024         /* By default use idle_bias_off, will override for WM8994 */
4025         dapm->idle_bias_off = 1;
4026
4027         /* Set revision-specific configuration */
4028         switch (control->type) {
4029         case WM8994:
4030                 /* Single ended line outputs should have VMID on. */
4031                 if (!control->pdata.lineout1_diff ||
4032                     !control->pdata.lineout2_diff)
4033                         dapm->idle_bias_off = 0;
4034
4035                 switch (control->revision) {
4036                 case 2:
4037                 case 3:
4038                         wm8994->hubs.dcs_codes_l = -5;
4039                         wm8994->hubs.dcs_codes_r = -5;
4040                         wm8994->hubs.hp_startup_mode = 1;
4041                         wm8994->hubs.dcs_readback_mode = 1;
4042                         wm8994->hubs.series_startup = 1;
4043                         break;
4044                 default:
4045                         wm8994->hubs.dcs_readback_mode = 2;
4046                         break;
4047                 }
4048                 break;
4049
4050         case WM8958:
4051                 wm8994->hubs.dcs_readback_mode = 1;
4052                 wm8994->hubs.hp_startup_mode = 1;
4053
4054                 switch (control->revision) {
4055                 case 0:
4056                         break;
4057                 default:
4058                         wm8994->fll_byp = true;
4059                         break;
4060                 }
4061                 break;
4062
4063         case WM1811:
4064                 wm8994->hubs.dcs_readback_mode = 2;
4065                 wm8994->hubs.no_series_update = 1;
4066                 wm8994->hubs.hp_startup_mode = 1;
4067                 wm8994->hubs.no_cache_dac_hp_direct = true;
4068                 wm8994->fll_byp = true;
4069
4070                 wm8994->hubs.dcs_codes_l = -9;
4071                 wm8994->hubs.dcs_codes_r = -7;
4072
4073                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4074                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4075                 break;
4076
4077         default:
4078                 break;
4079         }
4080
4081         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4082                            wm8994_fifo_error, "FIFO error", codec);
4083         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4084                            wm8994_temp_warn, "Thermal warning", codec);
4085         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4086                            wm8994_temp_shut, "Thermal shutdown", codec);
4087
4088         switch (control->type) {
4089         case WM8994:
4090                 if (wm8994->micdet_irq)
4091                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4092                                                    wm8994_mic_irq,
4093                                                    IRQF_TRIGGER_RISING |
4094                                                    IRQF_ONESHOT,
4095                                                    "Mic1 detect",
4096                                                    wm8994);
4097                  else
4098                         ret = wm8994_request_irq(wm8994->wm8994,
4099                                         WM8994_IRQ_MIC1_DET,
4100                                         wm8994_mic_irq, "Mic 1 detect",
4101                                         wm8994);
4102
4103                 if (ret != 0)
4104                         dev_warn(codec->dev,
4105                                  "Failed to request Mic1 detect IRQ: %d\n",
4106                                  ret);
4107
4108
4109                 ret = wm8994_request_irq(wm8994->wm8994,
4110                                          WM8994_IRQ_MIC1_SHRT,
4111                                          wm8994_mic_irq, "Mic 1 short",
4112                                          wm8994);
4113                 if (ret != 0)
4114                         dev_warn(codec->dev,
4115                                  "Failed to request Mic1 short IRQ: %d\n",
4116                                  ret);
4117
4118                 ret = wm8994_request_irq(wm8994->wm8994,
4119                                          WM8994_IRQ_MIC2_DET,
4120                                          wm8994_mic_irq, "Mic 2 detect",
4121                                          wm8994);
4122                 if (ret != 0)
4123                         dev_warn(codec->dev,
4124                                  "Failed to request Mic2 detect IRQ: %d\n",
4125                                  ret);
4126
4127                 ret = wm8994_request_irq(wm8994->wm8994,
4128                                          WM8994_IRQ_MIC2_SHRT,
4129                                          wm8994_mic_irq, "Mic 2 short",
4130                                          wm8994);
4131                 if (ret != 0)
4132                         dev_warn(codec->dev,
4133                                  "Failed to request Mic2 short IRQ: %d\n",
4134                                  ret);
4135                 break;
4136
4137         case WM8958:
4138         case WM1811:
4139                 if (wm8994->micdet_irq) {
4140                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4141                                                    wm8958_mic_irq,
4142                                                    IRQF_TRIGGER_RISING |
4143                                                    IRQF_ONESHOT,
4144                                                    "Mic detect",
4145                                                    wm8994);
4146                         if (ret != 0)
4147                                 dev_warn(codec->dev,
4148                                          "Failed to request Mic detect IRQ: %d\n",
4149                                          ret);
4150                 } else {
4151                         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4152                                            wm8958_mic_irq, "Mic detect",
4153                                            wm8994);
4154                 }
4155         }
4156
4157         switch (control->type) {
4158         case WM1811:
4159                 if (control->cust_id > 1 || control->revision > 1) {
4160                         ret = wm8994_request_irq(wm8994->wm8994,
4161                                                  WM8994_IRQ_GPIO(6),
4162                                                  wm1811_jackdet_irq, "JACKDET",
4163                                                  wm8994);
4164                         if (ret == 0)
4165                                 wm8994->jackdet = true;
4166                 }
4167                 break;
4168         default:
4169                 break;
4170         }
4171
4172         wm8994->fll_locked_irq = true;
4173         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4174                 ret = wm8994_request_irq(wm8994->wm8994,
4175                                          WM8994_IRQ_FLL1_LOCK + i,
4176                                          wm8994_fll_locked_irq, "FLL lock",
4177                                          &wm8994->fll_locked[i]);
4178                 if (ret != 0)
4179                         wm8994->fll_locked_irq = false;
4180         }
4181
4182         /* Make sure we can read from the GPIOs if they're inputs */
4183         pm_runtime_get_sync(codec->dev);
4184
4185         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
4186          * configured on init - if a system wants to do this dynamically
4187          * at runtime we can deal with that then.
4188          */
4189         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
4190         if (ret < 0) {
4191                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4192                 goto err_irq;
4193         }
4194         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4195                 wm8994->lrclk_shared[0] = 1;
4196                 wm8994_dai[0].symmetric_rates = 1;
4197         } else {
4198                 wm8994->lrclk_shared[0] = 0;
4199         }
4200
4201         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4202         if (ret < 0) {
4203                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4204                 goto err_irq;
4205         }
4206         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4207                 wm8994->lrclk_shared[1] = 1;
4208                 wm8994_dai[1].symmetric_rates = 1;
4209         } else {
4210                 wm8994->lrclk_shared[1] = 0;
4211         }
4212
4213         pm_runtime_put(codec->dev);
4214
4215         /* Latch volume update bits */
4216         for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4217                 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4218                                     wm8994_vu_bits[i].mask,
4219                                     wm8994_vu_bits[i].mask);
4220
4221         /* Set the low bit of the 3D stereo depth so TLV matches */
4222         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4223                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4224                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4225         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4226                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4227                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4228         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4229                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4230                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4231
4232         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4233          * use this; it only affects behaviour on idle TDM clock
4234          * cycles. */
4235         switch (control->type) {
4236         case WM8994:
4237         case WM8958:
4238                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4239                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4240                 break;
4241         default:
4242                 break;
4243         }
4244
4245         /* Put MICBIAS into bypass mode by default on newer devices */
4246         switch (control->type) {
4247         case WM8958:
4248         case WM1811:
4249                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4250                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4251                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4252                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4253                 break;
4254         default:
4255                 break;
4256         }
4257
4258         wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4259         wm_hubs_update_class_w(codec);
4260
4261         wm8994_handle_pdata(wm8994);
4262
4263         wm_hubs_add_analogue_controls(codec);
4264         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4265                              ARRAY_SIZE(wm8994_snd_controls));
4266         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4267                                   ARRAY_SIZE(wm8994_dapm_widgets));
4268
4269         switch (control->type) {
4270         case WM8994:
4271                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4272                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
4273                 if (control->revision < 4) {
4274                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4275                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4276                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4277                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4278                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4279                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4280                 } else {
4281                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4282                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4283                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4284                                                   ARRAY_SIZE(wm8994_adc_widgets));
4285                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4286                                                   ARRAY_SIZE(wm8994_dac_widgets));
4287                 }
4288                 break;
4289         case WM8958:
4290                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4291                                      ARRAY_SIZE(wm8958_snd_controls));
4292                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4293                                           ARRAY_SIZE(wm8958_dapm_widgets));
4294                 if (control->revision < 1) {
4295                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4296                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4297                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4298                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4299                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4300                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4301                 } else {
4302                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4303                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4304                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4305                                                   ARRAY_SIZE(wm8994_adc_widgets));
4306                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4307                                                   ARRAY_SIZE(wm8994_dac_widgets));
4308                 }
4309                 break;
4310
4311         case WM1811:
4312                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4313                                      ARRAY_SIZE(wm8958_snd_controls));
4314                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4315                                           ARRAY_SIZE(wm8958_dapm_widgets));
4316                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4317                                           ARRAY_SIZE(wm8994_lateclk_widgets));
4318                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4319                                           ARRAY_SIZE(wm8994_adc_widgets));
4320                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4321                                           ARRAY_SIZE(wm8994_dac_widgets));
4322                 break;
4323         }
4324
4325         wm_hubs_add_analogue_routes(codec, 0, 0);
4326         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4327                                  wm_hubs_dcs_done, "DC servo done",
4328                                  &wm8994->hubs);
4329         if (ret == 0)
4330                 wm8994->hubs.dcs_done_irq = true;
4331         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4332
4333         switch (control->type) {
4334         case WM8994:
4335                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4336                                         ARRAY_SIZE(wm8994_intercon));
4337
4338                 if (control->revision < 4) {
4339                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4340                                                 ARRAY_SIZE(wm8994_revd_intercon));
4341                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4342                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4343                 } else {
4344                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4345                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4346                 }
4347                 break;
4348         case WM8958:
4349                 if (control->revision < 1) {
4350                         snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4351                                                 ARRAY_SIZE(wm8994_intercon));
4352                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4353                                                 ARRAY_SIZE(wm8994_revd_intercon));
4354                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4355                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4356                 } else {
4357                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4358                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4359                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4360                                                 ARRAY_SIZE(wm8958_intercon));
4361                 }
4362
4363                 wm8958_dsp2_init(codec);
4364                 break;
4365         case WM1811:
4366                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4367                                         ARRAY_SIZE(wm8994_lateclk_intercon));
4368                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4369                                         ARRAY_SIZE(wm8958_intercon));
4370                 break;
4371         }
4372
4373         return 0;
4374
4375 err_irq:
4376         if (wm8994->jackdet)
4377                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4378         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4379         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4380         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4381         if (wm8994->micdet_irq)
4382                 free_irq(wm8994->micdet_irq, wm8994);
4383         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4384                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4385                                 &wm8994->fll_locked[i]);
4386         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4387                         &wm8994->hubs);
4388         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4389         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4390         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4391
4392         return ret;
4393 }
4394
4395 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4396 {
4397         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4398         struct wm8994 *control = wm8994->wm8994;
4399         int i;
4400
4401         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4402                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4403                                 &wm8994->fll_locked[i]);
4404
4405         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4406                         &wm8994->hubs);
4407         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4408         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4409         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4410
4411         if (wm8994->jackdet)
4412                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4413
4414         switch (control->type) {
4415         case WM8994:
4416                 if (wm8994->micdet_irq)
4417                         free_irq(wm8994->micdet_irq, wm8994);
4418                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4419                                 wm8994);
4420                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4421                                 wm8994);
4422                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4423                                 wm8994);
4424                 break;
4425
4426         case WM1811:
4427         case WM8958:
4428                 if (wm8994->micdet_irq)
4429                         free_irq(wm8994->micdet_irq, wm8994);
4430                 break;
4431         }
4432         release_firmware(wm8994->mbc);
4433         release_firmware(wm8994->mbc_vss);
4434         release_firmware(wm8994->enh_eq);
4435         kfree(wm8994->retune_mobile_texts);
4436         return 0;
4437 }
4438
4439 static const struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4440         .probe =        wm8994_codec_probe,
4441         .remove =       wm8994_codec_remove,
4442         .suspend =      wm8994_codec_suspend,
4443         .resume =       wm8994_codec_resume,
4444         .set_bias_level = wm8994_set_bias_level,
4445 };
4446
4447 static int wm8994_probe(struct platform_device *pdev)
4448 {
4449         struct wm8994_priv *wm8994;
4450
4451         wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4452                               GFP_KERNEL);
4453         if (wm8994 == NULL)
4454                 return -ENOMEM;
4455         platform_set_drvdata(pdev, wm8994);
4456
4457         mutex_init(&wm8994->fw_lock);
4458
4459         wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4460
4461         pm_runtime_enable(&pdev->dev);
4462         pm_runtime_idle(&pdev->dev);
4463
4464         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4465                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
4466 }
4467
4468 static int wm8994_remove(struct platform_device *pdev)
4469 {
4470         snd_soc_unregister_codec(&pdev->dev);
4471         pm_runtime_disable(&pdev->dev);
4472
4473         return 0;
4474 }
4475
4476 #ifdef CONFIG_PM_SLEEP
4477 static int wm8994_suspend(struct device *dev)
4478 {
4479         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4480
4481         /* Drop down to power saving mode when system is suspended */
4482         if (wm8994->jackdet && !wm8994->active_refcount)
4483                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4484                                    WM1811_JACKDET_MODE_MASK,
4485                                    wm8994->jackdet_mode);
4486
4487         return 0;
4488 }
4489
4490 static int wm8994_resume(struct device *dev)
4491 {
4492         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4493
4494         if (wm8994->jackdet && wm8994->jackdet_mode)
4495                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4496                                    WM1811_JACKDET_MODE_MASK,
4497                                    WM1811_JACKDET_MODE_AUDIO);
4498
4499         return 0;
4500 }
4501 #endif
4502
4503 static const struct dev_pm_ops wm8994_pm_ops = {
4504         SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4505 };
4506
4507 static struct platform_driver wm8994_codec_driver = {
4508         .driver = {
4509                 .name = "wm8994-codec",
4510                 .pm = &wm8994_pm_ops,
4511         },
4512         .probe = wm8994_probe,
4513         .remove = wm8994_remove,
4514 };
4515
4516 module_platform_driver(wm8994_codec_driver);
4517
4518 MODULE_DESCRIPTION("ASoC WM8994 driver");
4519 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4520 MODULE_LICENSE("GPL");
4521 MODULE_ALIAS("platform:wm8994-codec");