sound/soc/codecs/wm8350.c

   1 /*
   2  * wm8350.c -- WM8350 ALSA SoC audio driver
   3  *
   4  * Copyright (C) 2007-12 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/slab.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/mfd/wm8350/audio.h>
  21 #include <linux/mfd/wm8350/core.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <trace/events/asoc.h>
  30
  31 #include "wm8350.h"
  32
  33 #define WM8350_OUTn_0dB 0x39
  34
  35 #define WM8350_RAMP_NONE        0
  36 #define WM8350_RAMP_UP          1
  37 #define WM8350_RAMP_DOWN        2
  38
  39 /* We only include the analogue supplies here; the digital supplies
  40  * need to be available well before this driver can be probed.
  41  */
  42 static const char *supply_names[] = {
  43         "AVDD",
  44         "HPVDD",
  45 };
  46
  47 struct wm8350_output {
  48         u16 active;
  49         u16 left_vol;
  50         u16 right_vol;
  51         u16 ramp;
  52         u16 mute;
  53 };
  54
  55 struct wm8350_jack_data {
  56         struct snd_soc_jack *jack;
  57         struct delayed_work work;
  58         int report;
  59         int short_report;
  60 };
  61
  62 struct wm8350_data {
  63         struct wm8350 *wm8350;
  64         struct wm8350_output out1;
  65         struct wm8350_output out2;
  66         struct wm8350_jack_data hpl;
  67         struct wm8350_jack_data hpr;
  68         struct wm8350_jack_data mic;
  69         struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  70         int fll_freq_out;
  71         int fll_freq_in;
  72 };
  73
  74 /*
  75  * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
  76  */
  77 static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec)
  78 {
  79         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
  80         struct wm8350_output *out1 = &wm8350_data->out1;
  81         struct wm8350 *wm8350 = wm8350_data->wm8350;
  82         int left_complete = 0, right_complete = 0;
  83         u16 reg, val;
  84
  85         /* left channel */
  86         reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
  87         val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  88
  89         if (out1->ramp == WM8350_RAMP_UP) {
  90                 /* ramp step up */
  91                 if (val < out1->left_vol) {
  92                         val++;
  93                         reg &= ~WM8350_OUT1L_VOL_MASK;
  94                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
  95                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
  96                 } else
  97                         left_complete = 1;
  98         } else if (out1->ramp == WM8350_RAMP_DOWN) {
  99                 /* ramp step down */
 100                 if (val > 0) {
 101                         val--;
 102                         reg &= ~WM8350_OUT1L_VOL_MASK;
 103                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
 104                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 105                 } else
 106                         left_complete = 1;
 107         } else
 108                 return 1;
 109
 110         /* right channel */
 111         reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
 112         val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 113         if (out1->ramp == WM8350_RAMP_UP) {
 114                 /* ramp step up */
 115                 if (val < out1->right_vol) {
 116                         val++;
 117                         reg &= ~WM8350_OUT1R_VOL_MASK;
 118                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 119                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 120                 } else
 121                         right_complete = 1;
 122         } else if (out1->ramp == WM8350_RAMP_DOWN) {
 123                 /* ramp step down */
 124                 if (val > 0) {
 125                         val--;
 126                         reg &= ~WM8350_OUT1R_VOL_MASK;
 127                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 128                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 129                 } else
 130                         right_complete = 1;
 131         }
 132
 133         /* only hit the update bit if either volume has changed this step */
 134         if (!left_complete || !right_complete)
 135                 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
 136
 137         return left_complete & right_complete;
 138 }
 139
 140 /*
 141  * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
 142  */
 143 static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
 144 {
 145         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 146         struct wm8350_output *out2 = &wm8350_data->out2;
 147         struct wm8350 *wm8350 = wm8350_data->wm8350;
 148         int left_complete = 0, right_complete = 0;
 149         u16 reg, val;
 150
 151         /* left channel */
 152         reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
 153         val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
 154         if (out2->ramp == WM8350_RAMP_UP) {
 155                 /* ramp step up */
 156                 if (val < out2->left_vol) {
 157                         val++;
 158                         reg &= ~WM8350_OUT2L_VOL_MASK;
 159                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 160                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 161                 } else
 162                         left_complete = 1;
 163         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 164                 /* ramp step down */
 165                 if (val > 0) {
 166                         val--;
 167                         reg &= ~WM8350_OUT2L_VOL_MASK;
 168                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 169                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 170                 } else
 171                         left_complete = 1;
 172         } else
 173                 return 1;
 174
 175         /* right channel */
 176         reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
 177         val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 178         if (out2->ramp == WM8350_RAMP_UP) {
 179                 /* ramp step up */
 180                 if (val < out2->right_vol) {
 181                         val++;
 182                         reg &= ~WM8350_OUT2R_VOL_MASK;
 183                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 184                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 185                 } else
 186                         right_complete = 1;
 187         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 188                 /* ramp step down */
 189                 if (val > 0) {
 190                         val--;
 191                         reg &= ~WM8350_OUT2R_VOL_MASK;
 192                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 193                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 194                 } else
 195                         right_complete = 1;
 196         }
 197
 198         /* only hit the update bit if either volume has changed this step */
 199         if (!left_complete || !right_complete)
 200                 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
 201
 202         return left_complete & right_complete;
 203 }
 204
 205 /*
 206  * This work ramps both output PGAs at stream start/stop time to
 207  * minimise pop associated with DAPM power switching.
 208  * It's best to enable Zero Cross when ramping occurs to minimise any
 209  * zipper noises.
 210  */
 211 static void wm8350_pga_work(struct work_struct *work)
 212 {
 213         struct snd_soc_dapm_context *dapm =
 214             container_of(work, struct snd_soc_dapm_context, delayed_work.work);
 215         struct snd_soc_codec *codec = dapm->codec;
 216         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 217         struct wm8350_output *out1 = &wm8350_data->out1,
 218             *out2 = &wm8350_data->out2;
 219         int i, out1_complete, out2_complete;
 220
 221         /* do we need to ramp at all ? */
 222         if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
 223                 return;
 224
 225         /* PGA volumes have 6 bits of resolution to ramp */
 226         for (i = 0; i <= 63; i++) {
 227                 out1_complete = 1, out2_complete = 1;
 228                 if (out1->ramp != WM8350_RAMP_NONE)
 229                         out1_complete = wm8350_out1_ramp_step(codec);
 230                 if (out2->ramp != WM8350_RAMP_NONE)
 231                         out2_complete = wm8350_out2_ramp_step(codec);
 232
 233                 /* ramp finished ? */
 234                 if (out1_complete && out2_complete)
 235                         break;
 236
 237                 /* we need to delay longer on the up ramp */
 238                 if (out1->ramp == WM8350_RAMP_UP ||
 239                     out2->ramp == WM8350_RAMP_UP) {
 240                         /* delay is longer over 0dB as increases are larger */
 241                         if (i >= WM8350_OUTn_0dB)
 242                                 schedule_timeout_interruptible(msecs_to_jiffies
 243                                                                (2));
 244                         else
 245                                 schedule_timeout_interruptible(msecs_to_jiffies
 246                                                                (1));
 247                 } else
 248                         udelay(50);     /* doesn't matter if we delay longer */
 249         }
 250
 251         out1->ramp = WM8350_RAMP_NONE;
 252         out2->ramp = WM8350_RAMP_NONE;
 253 }
 254
 255 /*
 256  * WM8350 Controls
 257  */
 258
 259 static int pga_event(struct snd_soc_dapm_widget *w,
 260                      struct snd_kcontrol *kcontrol, int event)
 261 {
 262         struct snd_soc_codec *codec = w->codec;
 263         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 264         struct wm8350_output *out;
 265
 266         switch (w->shift) {
 267         case 0:
 268         case 1:
 269                 out = &wm8350_data->out1;
 270                 break;
 271         case 2:
 272         case 3:
 273                 out = &wm8350_data->out2;
 274                 break;
 275
 276         default:
 277                 WARN(1, "Invalid shift %d\n", w->shift);
 278                 return -1;
 279         }
 280
 281         switch (event) {
 282         case SND_SOC_DAPM_POST_PMU:
 283                 out->ramp = WM8350_RAMP_UP;
 284                 out->active = 1;
 285
 286                 schedule_delayed_work(&codec->dapm.delayed_work,
 287                                       msecs_to_jiffies(1));
 288                 break;
 289
 290         case SND_SOC_DAPM_PRE_PMD:
 291                 out->ramp = WM8350_RAMP_DOWN;
 292                 out->active = 0;
 293
 294                 schedule_delayed_work(&codec->dapm.delayed_work,
 295                                       msecs_to_jiffies(1));
 296                 break;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
 303                                   struct snd_ctl_elem_value *ucontrol)
 304 {
 305         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 306         struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
 307         struct wm8350_output *out = NULL;
 308         struct soc_mixer_control *mc =
 309                 (struct soc_mixer_control *)kcontrol->private_value;
 310         int ret;
 311         unsigned int reg = mc->reg;
 312         u16 val;
 313
 314         /* For OUT1 and OUT2 we shadow the values and only actually write
 315          * them out when active in order to ensure the amplifier comes on
 316          * as quietly as possible. */
 317         switch (reg) {
 318         case WM8350_LOUT1_VOLUME:
 319                 out = &wm8350_priv->out1;
 320                 break;
 321         case WM8350_LOUT2_VOLUME:
 322                 out = &wm8350_priv->out2;
 323                 break;
 324         default:
 325                 break;
 326         }
 327
 328         if (out) {
 329                 out->left_vol = ucontrol->value.integer.value[0];
 330                 out->right_vol = ucontrol->value.integer.value[1];
 331                 if (!out->active)
 332                         return 1;
 333         }
 334
 335         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 336         if (ret < 0)
 337                 return ret;
 338
 339         /* now hit the volume update bits (always bit 8) */
 340         val = snd_soc_read(codec, reg);
 341         snd_soc_write(codec, reg, val | WM8350_OUT1_VU);
 342         return 1;
 343 }
 344
 345 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
 346                                struct snd_ctl_elem_value *ucontrol)
 347 {
 348         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 349         struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
 350         struct wm8350_output *out1 = &wm8350_priv->out1;
 351         struct wm8350_output *out2 = &wm8350_priv->out2;
 352         struct soc_mixer_control *mc =
 353                 (struct soc_mixer_control *)kcontrol->private_value;
 354         unsigned int reg = mc->reg;
 355
 356         /* If these are cached registers use the cache */
 357         switch (reg) {
 358         case WM8350_LOUT1_VOLUME:
 359                 ucontrol->value.integer.value[0] = out1->left_vol;
 360                 ucontrol->value.integer.value[1] = out1->right_vol;
 361                 return 0;
 362
 363         case WM8350_LOUT2_VOLUME:
 364                 ucontrol->value.integer.value[0] = out2->left_vol;
 365                 ucontrol->value.integer.value[1] = out2->right_vol;
 366                 return 0;
 367
 368         default:
 369                 break;
 370         }
 371
 372         return snd_soc_get_volsw(kcontrol, ucontrol);
 373 }
 374
 375 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
 376 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
 377 static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
 378 static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
 379 static const char *wm8350_adcfilter[] = { "None", "High Pass" };
 380 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
 381 static const char *wm8350_lr[] = { "Left", "Right" };
 382
 383 static const struct soc_enum wm8350_enum[] = {
 384         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
 385         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
 386         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
 387         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
 388         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
 389         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
 390         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
 391         SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
 392 };
 393
 394 static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
 395 static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
 396 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
 397 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
 398 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
 399
 400 static const unsigned int capture_sd_tlv[] = {
 401         TLV_DB_RANGE_HEAD(2),
 402         0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
 403         13, 15, TLV_DB_SCALE_ITEM(0, 0, 0),
 404 };
 405
 406 static const struct snd_kcontrol_new wm8350_snd_controls[] = {
 407         SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
 408         SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
 409         SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
 410                                 WM8350_DAC_DIGITAL_VOLUME_L,
 411                                 WM8350_DAC_DIGITAL_VOLUME_R,
 412                                 0, 255, 0, wm8350_get_volsw_2r,
 413                                 wm8350_put_volsw_2r_vu, dac_pcm_tlv),
 414         SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
 415         SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
 416         SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
 417         SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
 418         SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
 419         SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
 420                                 WM8350_ADC_DIGITAL_VOLUME_L,
 421                                 WM8350_ADC_DIGITAL_VOLUME_R,
 422                                 0, 255, 0, wm8350_get_volsw_2r,
 423                                 wm8350_put_volsw_2r_vu, adc_pcm_tlv),
 424         SOC_DOUBLE_TLV("Capture Sidetone Volume",
 425                        WM8350_ADC_DIVIDER,
 426                        8, 4, 15, 1, capture_sd_tlv),
 427         SOC_DOUBLE_R_EXT_TLV("Capture Volume",
 428                                 WM8350_LEFT_INPUT_VOLUME,
 429                                 WM8350_RIGHT_INPUT_VOLUME,
 430                                 2, 63, 0, wm8350_get_volsw_2r,
 431                                 wm8350_put_volsw_2r_vu, pre_amp_tlv),
 432         SOC_DOUBLE_R("Capture ZC Switch",
 433                      WM8350_LEFT_INPUT_VOLUME,
 434                      WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
 435         SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
 436                        WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
 437         SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
 438                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 439                        5, 7, 0, out_mix_tlv),
 440         SOC_SINGLE_TLV("Left Input Bypass Volume",
 441                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 442                        9, 7, 0, out_mix_tlv),
 443         SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
 444                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 445                        1, 7, 0, out_mix_tlv),
 446         SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
 447                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 448                        5, 7, 0, out_mix_tlv),
 449         SOC_SINGLE_TLV("Right Input Bypass Volume",
 450                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 451                        13, 7, 0, out_mix_tlv),
 452         SOC_SINGLE("Left Input Mixer +20dB Switch",
 453                    WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
 454         SOC_SINGLE("Right Input Mixer +20dB Switch",
 455                    WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
 456         SOC_SINGLE_TLV("Out4 Capture Volume",
 457                        WM8350_INPUT_MIXER_VOLUME,
 458                        1, 7, 0, out_mix_tlv),
 459         SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
 460                                 WM8350_LOUT1_VOLUME,
 461                                 WM8350_ROUT1_VOLUME,
 462                                 2, 63, 0, wm8350_get_volsw_2r,
 463                                 wm8350_put_volsw_2r_vu, out_pga_tlv),
 464         SOC_DOUBLE_R("Out1 Playback ZC Switch",
 465                      WM8350_LOUT1_VOLUME,
 466                      WM8350_ROUT1_VOLUME, 13, 1, 0),
 467         SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
 468                                 WM8350_LOUT2_VOLUME,
 469                                 WM8350_ROUT2_VOLUME,
 470                                 2, 63, 0, wm8350_get_volsw_2r,
 471                                 wm8350_put_volsw_2r_vu, out_pga_tlv),
 472         SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
 473                      WM8350_ROUT2_VOLUME, 13, 1, 0),
 474         SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
 475         SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
 476                        5, 7, 0, out_mix_tlv),
 477
 478         SOC_DOUBLE_R("Out1 Playback Switch",
 479                      WM8350_LOUT1_VOLUME,
 480                      WM8350_ROUT1_VOLUME,
 481                      14, 1, 1),
 482         SOC_DOUBLE_R("Out2 Playback Switch",
 483                      WM8350_LOUT2_VOLUME,
 484                      WM8350_ROUT2_VOLUME,
 485                      14, 1, 1),
 486 };
 487
 488 /*
 489  * DAPM Controls
 490  */
 491
 492 /* Left Playback Mixer */
 493 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
 494         SOC_DAPM_SINGLE("Playback Switch",
 495                         WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
 496         SOC_DAPM_SINGLE("Left Bypass Switch",
 497                         WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
 498         SOC_DAPM_SINGLE("Right Playback Switch",
 499                         WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
 500         SOC_DAPM_SINGLE("Left Sidetone Switch",
 501                         WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
 502         SOC_DAPM_SINGLE("Right Sidetone Switch",
 503                         WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
 504 };
 505
 506 /* Right Playback Mixer */
 507 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
 508         SOC_DAPM_SINGLE("Playback Switch",
 509                         WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
 510         SOC_DAPM_SINGLE("Right Bypass Switch",
 511                         WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
 512         SOC_DAPM_SINGLE("Left Playback Switch",
 513                         WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
 514         SOC_DAPM_SINGLE("Left Sidetone Switch",
 515                         WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
 516         SOC_DAPM_SINGLE("Right Sidetone Switch",
 517                         WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
 518 };
 519
 520 /* Out4 Mixer */
 521 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
 522         SOC_DAPM_SINGLE("Right Playback Switch",
 523                         WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
 524         SOC_DAPM_SINGLE("Left Playback Switch",
 525                         WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
 526         SOC_DAPM_SINGLE("Right Capture Switch",
 527                         WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
 528         SOC_DAPM_SINGLE("Out3 Playback Switch",
 529                         WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
 530         SOC_DAPM_SINGLE("Right Mixer Switch",
 531                         WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
 532         SOC_DAPM_SINGLE("Left Mixer Switch",
 533                         WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
 534 };
 535
 536 /* Out3 Mixer */
 537 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
 538         SOC_DAPM_SINGLE("Left Playback Switch",
 539                         WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
 540         SOC_DAPM_SINGLE("Left Capture Switch",
 541                         WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
 542         SOC_DAPM_SINGLE("Out4 Playback Switch",
 543                         WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
 544         SOC_DAPM_SINGLE("Left Mixer Switch",
 545                         WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
 546 };
 547
 548 /* Left Input Mixer */
 549 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
 550         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 551                             WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
 552         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 553                             WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
 554         SOC_DAPM_SINGLE("PGA Capture Switch",
 555                         WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
 556 };
 557
 558 /* Right Input Mixer */
 559 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
 560         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 561                             WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
 562         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 563                             WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
 564         SOC_DAPM_SINGLE("PGA Capture Switch",
 565                         WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
 566 };
 567
 568 /* Left Mic Mixer */
 569 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
 570         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
 571         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
 572         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
 573 };
 574
 575 /* Right Mic Mixer */
 576 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
 577         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
 578         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
 579         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
 580 };
 581
 582 /* Beep Switch */
 583 static const struct snd_kcontrol_new wm8350_beep_switch_controls =
 584 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
 585
 586 /* Out4 Capture Mux */
 587 static const struct snd_kcontrol_new wm8350_out4_capture_controls =
 588 SOC_DAPM_ENUM("Route", wm8350_enum[7]);
 589
 590 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
 591
 592         SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
 593         SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
 594         SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
 595                            0, pga_event,
 596                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 597         SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
 598                            pga_event,
 599                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 600         SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
 601                            0, pga_event,
 602                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 603         SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
 604                            pga_event,
 605                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 606
 607         SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
 608                            7, 0, &wm8350_right_capt_mixer_controls[0],
 609                            ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
 610
 611         SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
 612                            6, 0, &wm8350_left_capt_mixer_controls[0],
 613                            ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
 614
 615         SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
 616                            &wm8350_out4_mixer_controls[0],
 617                            ARRAY_SIZE(wm8350_out4_mixer_controls)),
 618
 619         SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
 620                            &wm8350_out3_mixer_controls[0],
 621                            ARRAY_SIZE(wm8350_out3_mixer_controls)),
 622
 623         SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
 624                            &wm8350_right_play_mixer_controls[0],
 625                            ARRAY_SIZE(wm8350_right_play_mixer_controls)),
 626
 627         SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
 628                            &wm8350_left_play_mixer_controls[0],
 629                            ARRAY_SIZE(wm8350_left_play_mixer_controls)),
 630
 631         SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
 632                            &wm8350_left_mic_mixer_controls[0],
 633                            ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
 634
 635         SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
 636                            &wm8350_right_mic_mixer_controls[0],
 637                            ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
 638
 639         /* virtual mixer for Beep and Out2R */
 640         SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
 641
 642         SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
 643                             &wm8350_beep_switch_controls),
 644
 645         SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
 646                          WM8350_POWER_MGMT_4, 3, 0),
 647         SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
 648                          WM8350_POWER_MGMT_4, 2, 0),
 649         SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
 650                          WM8350_POWER_MGMT_4, 5, 0),
 651         SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
 652                          WM8350_POWER_MGMT_4, 4, 0),
 653
 654         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
 655
 656         SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
 657                          &wm8350_out4_capture_controls),
 658
 659         SND_SOC_DAPM_OUTPUT("OUT1R"),
 660         SND_SOC_DAPM_OUTPUT("OUT1L"),
 661         SND_SOC_DAPM_OUTPUT("OUT2R"),
 662         SND_SOC_DAPM_OUTPUT("OUT2L"),
 663         SND_SOC_DAPM_OUTPUT("OUT3"),
 664         SND_SOC_DAPM_OUTPUT("OUT4"),
 665
 666         SND_SOC_DAPM_INPUT("IN1RN"),
 667         SND_SOC_DAPM_INPUT("IN1RP"),
 668         SND_SOC_DAPM_INPUT("IN2R"),
 669         SND_SOC_DAPM_INPUT("IN1LP"),
 670         SND_SOC_DAPM_INPUT("IN1LN"),
 671         SND_SOC_DAPM_INPUT("IN2L"),
 672         SND_SOC_DAPM_INPUT("IN3R"),
 673         SND_SOC_DAPM_INPUT("IN3L"),
 674 };
 675
 676 static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {
 677
 678         /* left playback mixer */
 679         {"Left Playback Mixer", "Playback Switch", "Left DAC"},
 680         {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
 681         {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
 682         {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 683         {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 684
 685         /* right playback mixer */
 686         {"Right Playback Mixer", "Playback Switch", "Right DAC"},
 687         {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
 688         {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
 689         {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 690         {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 691
 692         /* out4 playback mixer */
 693         {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
 694         {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
 695         {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
 696         {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
 697         {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
 698         {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 699         {"OUT4", NULL, "Out4 Mixer"},
 700
 701         /* out3 playback mixer */
 702         {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
 703         {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
 704         {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 705         {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
 706         {"OUT3", NULL, "Out3 Mixer"},
 707
 708         /* out2 */
 709         {"Right Out2 PGA", NULL, "Right Playback Mixer"},
 710         {"Left Out2 PGA", NULL, "Left Playback Mixer"},
 711         {"OUT2L", NULL, "Left Out2 PGA"},
 712         {"OUT2R", NULL, "Right Out2 PGA"},
 713
 714         /* out1 */
 715         {"Right Out1 PGA", NULL, "Right Playback Mixer"},
 716         {"Left Out1 PGA", NULL, "Left Playback Mixer"},
 717         {"OUT1L", NULL, "Left Out1 PGA"},
 718         {"OUT1R", NULL, "Right Out1 PGA"},
 719
 720         /* ADCs */
 721         {"Left ADC", NULL, "Left Capture Mixer"},
 722         {"Right ADC", NULL, "Right Capture Mixer"},
 723
 724         /* Left capture mixer */
 725         {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
 726         {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
 727         {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
 728         {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
 729
 730         /* Right capture mixer */
 731         {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
 732         {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
 733         {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
 734         {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
 735
 736         /* L3 Inputs */
 737         {"IN3L PGA", NULL, "IN3L"},
 738         {"IN3R PGA", NULL, "IN3R"},
 739
 740         /* Left Mic mixer */
 741         {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
 742         {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
 743         {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
 744
 745         /* Right Mic mixer */
 746         {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
 747         {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
 748         {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
 749
 750         /* out 4 capture */
 751         {"Out4 Capture Channel", NULL, "Out4 Mixer"},
 752
 753         /* Beep */
 754         {"Beep", NULL, "IN3R PGA"},
 755 };
 756
 757 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 758                                  int clk_id, unsigned int freq, int dir)
 759 {
 760         struct snd_soc_codec *codec = codec_dai->codec;
 761         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 762         struct wm8350 *wm8350 = wm8350_data->wm8350;
 763         u16 fll_4;
 764
 765         switch (clk_id) {
 766         case WM8350_MCLK_SEL_MCLK:
 767                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 768                                   WM8350_MCLK_SEL);
 769                 break;
 770         case WM8350_MCLK_SEL_PLL_MCLK:
 771         case WM8350_MCLK_SEL_PLL_DAC:
 772         case WM8350_MCLK_SEL_PLL_ADC:
 773         case WM8350_MCLK_SEL_PLL_32K:
 774                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 775                                 WM8350_MCLK_SEL);
 776                 fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) &
 777                     ~WM8350_FLL_CLK_SRC_MASK;
 778                 snd_soc_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
 779                 break;
 780         }
 781
 782         /* MCLK direction */
 783         if (dir == SND_SOC_CLOCK_OUT)
 784                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 785                                 WM8350_MCLK_DIR);
 786         else
 787                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 788                                   WM8350_MCLK_DIR);
 789
 790         return 0;
 791 }
 792
 793 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
 794 {
 795         struct snd_soc_codec *codec = codec_dai->codec;
 796         u16 val;
 797
 798         switch (div_id) {
 799         case WM8350_ADC_CLKDIV:
 800                 val = snd_soc_read(codec, WM8350_ADC_DIVIDER) &
 801                     ~WM8350_ADC_CLKDIV_MASK;
 802                 snd_soc_write(codec, WM8350_ADC_DIVIDER, val | div);
 803                 break;
 804         case WM8350_DAC_CLKDIV:
 805                 val = snd_soc_read(codec, WM8350_DAC_CLOCK_CONTROL) &
 806                     ~WM8350_DAC_CLKDIV_MASK;
 807                 snd_soc_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
 808                 break;
 809         case WM8350_BCLK_CLKDIV:
 810                 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
 811                     ~WM8350_BCLK_DIV_MASK;
 812                 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 813                 break;
 814         case WM8350_OPCLK_CLKDIV:
 815                 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
 816                     ~WM8350_OPCLK_DIV_MASK;
 817                 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 818                 break;
 819         case WM8350_SYS_CLKDIV:
 820                 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
 821                     ~WM8350_MCLK_DIV_MASK;
 822                 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 823                 break;
 824         case WM8350_DACLR_CLKDIV:
 825                 val = snd_soc_read(codec, WM8350_DAC_LR_RATE) &
 826                     ~WM8350_DACLRC_RATE_MASK;
 827                 snd_soc_write(codec, WM8350_DAC_LR_RATE, val | div);
 828                 break;
 829         case WM8350_ADCLR_CLKDIV:
 830                 val = snd_soc_read(codec, WM8350_ADC_LR_RATE) &
 831                     ~WM8350_ADCLRC_RATE_MASK;
 832                 snd_soc_write(codec, WM8350_ADC_LR_RATE, val | div);
 833                 break;
 834         default:
 835                 return -EINVAL;
 836         }
 837
 838         return 0;
 839 }
 840
 841 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 842 {
 843         struct snd_soc_codec *codec = codec_dai->codec;
 844         u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) &
 845             ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
 846         u16 master = snd_soc_read(codec, WM8350_AI_DAC_CONTROL) &
 847             ~WM8350_BCLK_MSTR;
 848         u16 dac_lrc = snd_soc_read(codec, WM8350_DAC_LR_RATE) &
 849             ~WM8350_DACLRC_ENA;
 850         u16 adc_lrc = snd_soc_read(codec, WM8350_ADC_LR_RATE) &
 851             ~WM8350_ADCLRC_ENA;
 852
 853         /* set master/slave audio interface */
 854         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 855         case SND_SOC_DAIFMT_CBM_CFM:
 856                 master |= WM8350_BCLK_MSTR;
 857                 dac_lrc |= WM8350_DACLRC_ENA;
 858                 adc_lrc |= WM8350_ADCLRC_ENA;
 859                 break;
 860         case SND_SOC_DAIFMT_CBS_CFS:
 861                 break;
 862         default:
 863                 return -EINVAL;
 864         }
 865
 866         /* interface format */
 867         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 868         case SND_SOC_DAIFMT_I2S:
 869                 iface |= 0x2 << 8;
 870                 break;
 871         case SND_SOC_DAIFMT_RIGHT_J:
 872                 break;
 873         case SND_SOC_DAIFMT_LEFT_J:
 874                 iface |= 0x1 << 8;
 875                 break;
 876         case SND_SOC_DAIFMT_DSP_A:
 877                 iface |= 0x3 << 8;
 878                 break;
 879         case SND_SOC_DAIFMT_DSP_B:
 880                 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
 881                 break;
 882         default:
 883                 return -EINVAL;
 884         }
 885
 886         /* clock inversion */
 887         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 888         case SND_SOC_DAIFMT_NB_NF:
 889                 break;
 890         case SND_SOC_DAIFMT_IB_IF:
 891                 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
 892                 break;
 893         case SND_SOC_DAIFMT_IB_NF:
 894                 iface |= WM8350_AIF_BCLK_INV;
 895                 break;
 896         case SND_SOC_DAIFMT_NB_IF:
 897                 iface |= WM8350_AIF_LRCLK_INV;
 898                 break;
 899         default:
 900                 return -EINVAL;
 901         }
 902
 903         snd_soc_write(codec, WM8350_AI_FORMATING, iface);
 904         snd_soc_write(codec, WM8350_AI_DAC_CONTROL, master);
 905         snd_soc_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
 906         snd_soc_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
 907         return 0;
 908 }
 909
 910 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
 911                                 struct snd_pcm_hw_params *params,
 912                                 struct snd_soc_dai *codec_dai)
 913 {
 914         struct snd_soc_codec *codec = codec_dai->codec;
 915         struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 916         struct wm8350 *wm8350 = wm8350_data->wm8350;
 917         u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) &
 918             ~WM8350_AIF_WL_MASK;
 919
 920         /* bit size */
 921         switch (params_width(params)) {
 922         case 16:
 923                 break;
 924         case 20:
 925                 iface |= 0x1 << 10;
 926                 break;
 927         case 24:
 928                 iface |= 0x2 << 10;
 929                 break;
 930         case 32:
 931                 iface |= 0x3 << 10;
 932                 break;
 933         }
 934
 935         snd_soc_write(codec, WM8350_AI_FORMATING, iface);
 936
 937         /* The sloping stopband filter is recommended for use with
 938          * lower sample rates to improve performance.
 939          */
 940         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 941                 if (params_rate(params) < 24000)
 942                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
 943                                         WM8350_DAC_SB_FILT);
 944                 else
 945                         wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
 946                                           WM8350_DAC_SB_FILT);
 947         }
 948
 949         return 0;
 950 }
 951
 952 static int wm8350_mute(struct snd_soc_dai *dai, int mute)
 953 {
 954         struct snd_soc_codec *codec = dai->codec;
 955         unsigned int val;
 956
 957         if (mute)
 958                 val = WM8350_DAC_MUTE_ENA;
 959         else
 960                 val = 0;
 961
 962         snd_soc_update_bits(codec, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);
 963
 964         return 0;
 965 }
 966
 967 /* FLL divisors */
 968 struct _fll_div {
 969         int div;                /* FLL_OUTDIV */
 970         int n;
 971         int k;
 972         int ratio;              /* FLL_FRATIO */
 973 };
 974
 975 /* The size in bits of the fll divide multiplied by 10
 976  * to allow rounding later */
 977 #define FIXED_FLL_SIZE ((1 << 16) * 10)
 978
 979 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
 980                               unsigned int output)
 981 {
 982         u64 Kpart;
 983         unsigned int t1, t2, K, Nmod;
 984
 985         if (output >= 2815250 && output <= 3125000)
 986                 fll_div->div = 0x4;
 987         else if (output >= 5625000 && output <= 6250000)
 988                 fll_div->div = 0x3;
 989         else if (output >= 11250000 && output <= 12500000)
 990                 fll_div->div = 0x2;
 991         else if (output >= 22500000 && output <= 25000000)
 992                 fll_div->div = 0x1;
 993         else {
 994                 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
 995                 return -EINVAL;
 996         }
 997
 998         if (input > 48000)
 999                 fll_div->ratio = 1;
1000         else
1001                 fll_div->ratio = 8;
1002
1003         t1 = output * (1 << (fll_div->div + 1));
1004         t2 = input * fll_div->ratio;
1005
1006         fll_div->n = t1 / t2;
1007         Nmod = t1 % t2;
1008
1009         if (Nmod) {
1010                 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1011                 do_div(Kpart, t2);
1012                 K = Kpart & 0xFFFFFFFF;
1013
1014                 /* Check if we need to round */
1015                 if ((K % 10) >= 5)
1016                         K += 5;
1017
1018                 /* Move down to proper range now rounding is done */
1019                 K /= 10;
1020                 fll_div->k = K;
1021         } else
1022                 fll_div->k = 0;
1023
1024         return 0;
1025 }
1026
1027 static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1028                           int pll_id, int source, unsigned int freq_in,
1029                           unsigned int freq_out)
1030 {
1031         struct snd_soc_codec *codec = codec_dai->codec;
1032         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1033         struct wm8350 *wm8350 = priv->wm8350;
1034         struct _fll_div fll_div;
1035         int ret = 0;
1036         u16 fll_1, fll_4;
1037
1038         if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1039                 return 0;
1040
1041         /* power down FLL - we need to do this for reconfiguration */
1042         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1043                           WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1044
1045         if (freq_out == 0 || freq_in == 0)
1046                 return ret;
1047
1048         ret = fll_factors(&fll_div, freq_in, freq_out);
1049         if (ret < 0)
1050                 return ret;
1051         dev_dbg(wm8350->dev,
1052                 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
1053                 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1054                 fll_div.ratio);
1055
1056         /* set up N.K & dividers */
1057         fll_1 = snd_soc_read(codec, WM8350_FLL_CONTROL_1) &
1058             ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1059         snd_soc_write(codec, WM8350_FLL_CONTROL_1,
1060                            fll_1 | (fll_div.div << 8) | 0x50);
1061         snd_soc_write(codec, WM8350_FLL_CONTROL_2,
1062                            (fll_div.ratio << 11) | (fll_div.
1063                                                     n & WM8350_FLL_N_MASK));
1064         snd_soc_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1065         fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) &
1066             ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1067         snd_soc_write(codec, WM8350_FLL_CONTROL_4,
1068                            fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1069                            (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1070
1071         /* power FLL on */
1072         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1073         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1074
1075         priv->fll_freq_out = freq_out;
1076         priv->fll_freq_in = freq_in;
1077
1078         return 0;
1079 }
1080
1081 static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1082                                  enum snd_soc_bias_level level)
1083 {
1084         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1085         struct wm8350 *wm8350 = priv->wm8350;
1086         struct wm8350_audio_platform_data *platform =
1087                 wm8350->codec.platform_data;
1088         u16 pm1;
1089         int ret;
1090
1091         switch (level) {
1092         case SND_SOC_BIAS_ON:
1093                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1094                     ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1095                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1096                                  pm1 | WM8350_VMID_50K |
1097                                  platform->codec_current_on << 14);
1098                 break;
1099
1100         case SND_SOC_BIAS_PREPARE:
1101                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1102                 pm1 &= ~WM8350_VMID_MASK;
1103                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1104                                  pm1 | WM8350_VMID_50K);
1105                 break;
1106
1107         case SND_SOC_BIAS_STANDBY:
1108                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1109                         ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1110                                                     priv->supplies);
1111                         if (ret != 0)
1112                                 return ret;
1113
1114                         /* Enable the system clock */
1115                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1116                                         WM8350_SYSCLK_ENA);
1117
1118                         /* mute DAC & outputs */
1119                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1120                                         WM8350_DAC_MUTE_ENA);
1121
1122                         /* discharge cap memory */
1123                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1124                                          platform->dis_out1 |
1125                                          (platform->dis_out2 << 2) |
1126                                          (platform->dis_out3 << 4) |
1127                                          (platform->dis_out4 << 6));
1128
1129                         /* wait for discharge */
1130                         schedule_timeout_interruptible(msecs_to_jiffies
1131                                                        (platform->
1132                                                         cap_discharge_msecs));
1133
1134                         /* enable antipop */
1135                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1136                                          (platform->vmid_s_curve << 8));
1137
1138                         /* ramp up vmid */
1139                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1140                                          (platform->
1141                                           codec_current_charge << 14) |
1142                                          WM8350_VMID_5K | WM8350_VMIDEN |
1143                                          WM8350_VBUFEN);
1144
1145                         /* wait for vmid */
1146                         schedule_timeout_interruptible(msecs_to_jiffies
1147                                                        (platform->
1148                                                         vmid_charge_msecs));
1149
1150                         /* turn on vmid 300k  */
1151                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1152                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1153                         pm1 |= WM8350_VMID_300K |
1154                                 (platform->codec_current_standby << 14);
1155                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1156                                          pm1);
1157
1158
1159                         /* enable analogue bias */
1160                         pm1 |= WM8350_BIASEN;
1161                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1162
1163                         /* disable antipop */
1164                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1165
1166                 } else {
1167                         /* turn on vmid 300k and reduce current */
1168                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1169                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1170                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1171                                          pm1 | WM8350_VMID_300K |
1172                                          (platform->
1173                                           codec_current_standby << 14));
1174
1175                 }
1176                 break;
1177
1178         case SND_SOC_BIAS_OFF:
1179
1180                 /* mute DAC & enable outputs */
1181                 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1182
1183                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1184                                 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1185                                 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1186
1187                 /* enable anti pop S curve */
1188                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1189                                  (platform->vmid_s_curve << 8));
1190
1191                 /* turn off vmid  */
1192                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1193                     ~WM8350_VMIDEN;
1194                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1195
1196                 /* wait */
1197                 schedule_timeout_interruptible(msecs_to_jiffies
1198                                                (platform->
1199                                                 vmid_discharge_msecs));
1200
1201                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1202                                  (platform->vmid_s_curve << 8) |
1203                                  platform->dis_out1 |
1204                                  (platform->dis_out2 << 2) |
1205                                  (platform->dis_out3 << 4) |
1206                                  (platform->dis_out4 << 6));
1207
1208                 /* turn off VBuf and drain */
1209                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1210                     ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1211                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1212                                  pm1 | WM8350_OUTPUT_DRAIN_EN);
1213
1214                 /* wait */
1215                 schedule_timeout_interruptible(msecs_to_jiffies
1216                                                (platform->drain_msecs));
1217
1218                 pm1 &= ~WM8350_BIASEN;
1219                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1220
1221                 /* disable anti-pop */
1222                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1223
1224                 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1225                                   WM8350_OUT1L_ENA);
1226                 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1227                                   WM8350_OUT1R_ENA);
1228                 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1229                                   WM8350_OUT2L_ENA);
1230                 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1231                                   WM8350_OUT2R_ENA);
1232
1233                 /* disable clock gen */
1234                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1235                                   WM8350_SYSCLK_ENA);
1236
1237                 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1238                                        priv->supplies);
1239                 break;
1240         }
1241         codec->dapm.bias_level = level;
1242         return 0;
1243 }
1244
1245 static int wm8350_suspend(struct snd_soc_codec *codec)
1246 {
1247         wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1248         return 0;
1249 }
1250
1251 static int wm8350_resume(struct snd_soc_codec *codec)
1252 {
1253         wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1254
1255         return 0;
1256 }
1257
1258 static void wm8350_hp_work(struct wm8350_data *priv,
1259                            struct wm8350_jack_data *jack,
1260                            u16 mask)
1261 {
1262         struct wm8350 *wm8350 = priv->wm8350;
1263         u16 reg;
1264         int report;
1265
1266         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1267         if (reg & mask)
1268                 report = jack->report;
1269         else
1270                 report = 0;
1271
1272         snd_soc_jack_report(jack->jack, report, jack->report);
1273
1274 }
1275
1276 static void wm8350_hpl_work(struct work_struct *work)
1277 {
1278         struct wm8350_data *priv =
1279             container_of(work, struct wm8350_data, hpl.work.work);
1280
1281         wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1282 }
1283
1284 static void wm8350_hpr_work(struct work_struct *work)
1285 {
1286         struct wm8350_data *priv =
1287             container_of(work, struct wm8350_data, hpr.work.work);
1288
1289         wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1290 }
1291
1292 static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)
1293 {
1294         struct wm8350_data *priv = data;
1295         struct wm8350 *wm8350 = priv->wm8350;
1296
1297 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1298         trace_snd_soc_jack_irq("WM8350 HPL");
1299 #endif
1300
1301         if (device_may_wakeup(wm8350->dev))
1302                 pm_wakeup_event(wm8350->dev, 250);
1303
1304         queue_delayed_work(system_power_efficient_wq,
1305                            &priv->hpl.work, msecs_to_jiffies(200));
1306
1307         return IRQ_HANDLED;
1308 }
1309
1310 static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)
1311 {
1312         struct wm8350_data *priv = data;
1313         struct wm8350 *wm8350 = priv->wm8350;
1314
1315 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1316         trace_snd_soc_jack_irq("WM8350 HPR");
1317 #endif
1318
1319         if (device_may_wakeup(wm8350->dev))
1320                 pm_wakeup_event(wm8350->dev, 250);
1321
1322         queue_delayed_work(system_power_efficient_wq,
1323                            &priv->hpr.work, msecs_to_jiffies(200));
1324
1325         return IRQ_HANDLED;
1326 }
1327
1328 /**
1329  * wm8350_hp_jack_detect - Enable headphone jack detection.
1330  *
1331  * @codec:  WM8350 codec
1332  * @which:  left or right jack detect signal
1333  * @jack:   jack to report detection events on
1334  * @report: value to report
1335  *
1336  * Enables the headphone jack detection of the WM8350.  If no report
1337  * is specified then detection is disabled.
1338  */
1339 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1340                           struct snd_soc_jack *jack, int report)
1341 {
1342         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1343         struct wm8350 *wm8350 = priv->wm8350;
1344         int ena;
1345
1346         switch (which) {
1347         case WM8350_JDL:
1348                 priv->hpl.jack = jack;
1349                 priv->hpl.report = report;
1350                 ena = WM8350_JDL_ENA;
1351                 break;
1352
1353         case WM8350_JDR:
1354                 priv->hpr.jack = jack;
1355                 priv->hpr.report = report;
1356                 ena = WM8350_JDR_ENA;
1357                 break;
1358
1359         default:
1360                 return -EINVAL;
1361         }
1362
1363         if (report) {
1364                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1365                 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1366         } else {
1367                 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1368         }
1369
1370         /* Sync status */
1371         switch (which) {
1372         case WM8350_JDL:
1373                 wm8350_hpl_jack_handler(0, priv);
1374                 break;
1375         case WM8350_JDR:
1376                 wm8350_hpr_jack_handler(0, priv);
1377                 break;
1378         }
1379
1380         return 0;
1381 }
1382 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1383
1384 static irqreturn_t wm8350_mic_handler(int irq, void *data)
1385 {
1386         struct wm8350_data *priv = data;
1387         struct wm8350 *wm8350 = priv->wm8350;
1388         u16 reg;
1389         int report = 0;
1390
1391 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1392         trace_snd_soc_jack_irq("WM8350 mic");
1393 #endif
1394
1395         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1396         if (reg & WM8350_JACK_MICSCD_LVL)
1397                 report |= priv->mic.short_report;
1398         if (reg & WM8350_JACK_MICSD_LVL)
1399                 report |= priv->mic.report;
1400
1401         snd_soc_jack_report(priv->mic.jack, report,
1402                             priv->mic.report | priv->mic.short_report);
1403
1404         return IRQ_HANDLED;
1405 }
1406
1407 /**
1408  * wm8350_mic_jack_detect - Enable microphone jack detection.
1409  *
1410  * @codec:         WM8350 codec
1411  * @jack:          jack to report detection events on
1412  * @detect_report: value to report when presence detected
1413  * @short_report:  value to report when microphone short detected
1414  *
1415  * Enables the microphone jack detection of the WM8350.  If both reports
1416  * are specified as zero then detection is disabled.
1417  */
1418 int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
1419                            struct snd_soc_jack *jack,
1420                            int detect_report, int short_report)
1421 {
1422         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1423         struct wm8350 *wm8350 = priv->wm8350;
1424
1425         priv->mic.jack = jack;
1426         priv->mic.report = detect_report;
1427         priv->mic.short_report = short_report;
1428
1429         if (detect_report || short_report) {
1430                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1431                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1432                                 WM8350_MIC_DET_ENA);
1433         } else {
1434                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1435                                   WM8350_MIC_DET_ENA);
1436         }
1437
1438         return 0;
1439 }
1440 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1441
1442 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1443
1444 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1445                         SNDRV_PCM_FMTBIT_S20_3LE |\
1446                         SNDRV_PCM_FMTBIT_S24_LE)
1447
1448 static const struct snd_soc_dai_ops wm8350_dai_ops = {
1449          .hw_params     = wm8350_pcm_hw_params,
1450          .digital_mute  = wm8350_mute,
1451          .set_fmt       = wm8350_set_dai_fmt,
1452          .set_sysclk    = wm8350_set_dai_sysclk,
1453          .set_pll       = wm8350_set_fll,
1454          .set_clkdiv    = wm8350_set_clkdiv,
1455 };
1456
1457 static struct snd_soc_dai_driver wm8350_dai = {
1458         .name = "wm8350-hifi",
1459         .playback = {
1460                 .stream_name = "Playback",
1461                 .channels_min = 1,
1462                 .channels_max = 2,
1463                 .rates = WM8350_RATES,
1464                 .formats = WM8350_FORMATS,
1465         },
1466         .capture = {
1467                  .stream_name = "Capture",
1468                  .channels_min = 1,
1469                  .channels_max = 2,
1470                  .rates = WM8350_RATES,
1471                  .formats = WM8350_FORMATS,
1472          },
1473         .ops = &wm8350_dai_ops,
1474 };
1475
1476 static  int wm8350_codec_probe(struct snd_soc_codec *codec)
1477 {
1478         struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1479         struct wm8350_data *priv;
1480         struct wm8350_output *out1;
1481         struct wm8350_output *out2;
1482         int ret, i;
1483
1484         if (wm8350->codec.platform_data == NULL) {
1485                 dev_err(codec->dev, "No audio platform data supplied\n");
1486                 return -EINVAL;
1487         }
1488
1489         priv = devm_kzalloc(codec->dev, sizeof(struct wm8350_data),
1490                             GFP_KERNEL);
1491         if (priv == NULL)
1492                 return -ENOMEM;
1493         snd_soc_codec_set_drvdata(codec, priv);
1494
1495         priv->wm8350 = wm8350;
1496
1497         for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1498                 priv->supplies[i].supply = supply_names[i];
1499
1500         ret = devm_regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1501                                  priv->supplies);
1502         if (ret != 0)
1503                 return ret;
1504
1505         /* Put the codec into reset if it wasn't already */
1506         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1507
1508         INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work);
1509         INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1510         INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
1511
1512         /* Enable the codec */
1513         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1514
1515         /* Enable robust clocking mode in ADC */
1516         snd_soc_write(codec, WM8350_SECURITY, 0xa7);
1517         snd_soc_write(codec, 0xde, 0x13);
1518         snd_soc_write(codec, WM8350_SECURITY, 0);
1519
1520         /* read OUT1 & OUT2 volumes */
1521         out1 = &priv->out1;
1522         out2 = &priv->out2;
1523         out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1524                           WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1525         out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1526                            WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1527         out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1528                           WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1529         out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1530                            WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1531         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1532         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1533         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1534         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1535
1536         /* Latch VU bits & mute */
1537         wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1538                         WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1539         wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1540                         WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1541         wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1542                         WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1543         wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1544                         WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1545
1546         /* Make sure AIF tristating is disabled by default */
1547         wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
1548
1549         /* Make sure we've got a sane companding setup too */
1550         wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
1551                           WM8350_DAC_COMP | WM8350_LOOPBACK);
1552
1553         /* Make sure jack detect is disabled to start off with */
1554         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1555                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1556
1557         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1558                             wm8350_hpl_jack_handler, 0, "Left jack detect",
1559                             priv);
1560         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1561                             wm8350_hpr_jack_handler, 0, "Right jack detect",
1562                             priv);
1563         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1564                             wm8350_mic_handler, 0, "Microphone short", priv);
1565         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1566                             wm8350_mic_handler, 0, "Microphone detect", priv);
1567
1568
1569         wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1570
1571         return 0;
1572 }
1573
1574 static int  wm8350_codec_remove(struct snd_soc_codec *codec)
1575 {
1576         struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1577         struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1578
1579         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1580                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1581         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1582
1583         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1584         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
1585         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1586         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
1587
1588         priv->hpl.jack = NULL;
1589         priv->hpr.jack = NULL;
1590         priv->mic.jack = NULL;
1591
1592         cancel_delayed_work_sync(&priv->hpl.work);
1593         cancel_delayed_work_sync(&priv->hpr.work);
1594
1595         /* if there was any work waiting then we run it now and
1596          * wait for its completion */
1597         flush_delayed_work(&codec->dapm.delayed_work);
1598
1599         wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1600
1601         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1602
1603         return 0;
1604 }
1605
1606 static struct regmap *wm8350_get_regmap(struct device *dev)
1607 {
1608         struct wm8350 *wm8350 = dev_get_platdata(dev);
1609
1610         return wm8350->regmap;
1611 }
1612
1613 static struct snd_soc_codec_driver soc_codec_dev_wm8350 = {
1614         .probe =        wm8350_codec_probe,
1615         .remove =       wm8350_codec_remove,
1616         .suspend =      wm8350_suspend,
1617         .resume =       wm8350_resume,
1618         .get_regmap =   wm8350_get_regmap,
1619         .set_bias_level = wm8350_set_bias_level,
1620
1621         .controls = wm8350_snd_controls,
1622         .num_controls = ARRAY_SIZE(wm8350_snd_controls),
1623         .dapm_widgets = wm8350_dapm_widgets,
1624         .num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets),
1625         .dapm_routes = wm8350_dapm_routes,
1626         .num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes),
1627 };
1628
1629 static int wm8350_probe(struct platform_device *pdev)
1630 {
1631         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350,
1632                         &wm8350_dai, 1);
1633 }
1634
1635 static int wm8350_remove(struct platform_device *pdev)
1636 {
1637         snd_soc_unregister_codec(&pdev->dev);
1638         return 0;
1639 }
1640
1641 static struct platform_driver wm8350_codec_driver = {
1642         .driver = {
1643                    .name = "wm8350-codec",
1644                    .owner = THIS_MODULE,
1645                    },
1646         .probe = wm8350_probe,
1647         .remove = wm8350_remove,
1648 };
1649
1650 module_platform_driver(wm8350_codec_driver);
1651
1652 MODULE_DESCRIPTION("ASoC WM8350 driver");
1653 MODULE_AUTHOR("Liam Girdwood");
1654 MODULE_LICENSE("GPL");
1655 MODULE_ALIAS("platform:wm8350-codec");