2 * wm2200.c -- WM2200 ALSA SoC Audio driver
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/firmware.h>
19 #include <linux/gcd.h>
20 #include <linux/gpio.h>
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/regulator/fixed.h>
25 #include <linux/slab.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/jack.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <sound/wm2200.h>
39 #define WM2200_DSP_CONTROL_1 0x00
40 #define WM2200_DSP_CONTROL_2 0x02
41 #define WM2200_DSP_CONTROL_3 0x03
42 #define WM2200_DSP_CONTROL_4 0x04
43 #define WM2200_DSP_CONTROL_5 0x06
44 #define WM2200_DSP_CONTROL_6 0x07
45 #define WM2200_DSP_CONTROL_7 0x08
46 #define WM2200_DSP_CONTROL_8 0x09
47 #define WM2200_DSP_CONTROL_9 0x0A
48 #define WM2200_DSP_CONTROL_10 0x0B
49 #define WM2200_DSP_CONTROL_11 0x0C
50 #define WM2200_DSP_CONTROL_12 0x0D
51 #define WM2200_DSP_CONTROL_13 0x0F
52 #define WM2200_DSP_CONTROL_14 0x10
53 #define WM2200_DSP_CONTROL_15 0x11
54 #define WM2200_DSP_CONTROL_16 0x12
55 #define WM2200_DSP_CONTROL_17 0x13
56 #define WM2200_DSP_CONTROL_18 0x14
57 #define WM2200_DSP_CONTROL_19 0x16
58 #define WM2200_DSP_CONTROL_20 0x17
59 #define WM2200_DSP_CONTROL_21 0x18
60 #define WM2200_DSP_CONTROL_22 0x1A
61 #define WM2200_DSP_CONTROL_23 0x1B
62 #define WM2200_DSP_CONTROL_24 0x1C
63 #define WM2200_DSP_CONTROL_25 0x1E
64 #define WM2200_DSP_CONTROL_26 0x20
65 #define WM2200_DSP_CONTROL_27 0x21
66 #define WM2200_DSP_CONTROL_28 0x22
67 #define WM2200_DSP_CONTROL_29 0x23
68 #define WM2200_DSP_CONTROL_30 0x24
69 #define WM2200_DSP_CONTROL_31 0x26
71 /* The code assumes DCVDD is generated internally */
72 #define WM2200_NUM_CORE_SUPPLIES 2
73 static const char *wm2200_core_supply_names[WM2200_NUM_CORE_SUPPLIES] = {
82 struct completion lock;
85 /* codec private data */
87 struct wm_adsp dsp[2];
88 struct regmap *regmap;
90 struct snd_soc_codec *codec;
91 struct wm2200_pdata pdata;
92 struct regulator_bulk_data core_supplies[WM2200_NUM_CORE_SUPPLIES];
94 struct completion fll_lock;
103 #define WM2200_DSP_RANGE_BASE (WM2200_MAX_REGISTER + 1)
104 #define WM2200_DSP_SPACING 12288
106 #define WM2200_DSP1_DM_BASE (WM2200_DSP_RANGE_BASE + (0 * WM2200_DSP_SPACING))
107 #define WM2200_DSP1_PM_BASE (WM2200_DSP_RANGE_BASE + (1 * WM2200_DSP_SPACING))
108 #define WM2200_DSP1_ZM_BASE (WM2200_DSP_RANGE_BASE + (2 * WM2200_DSP_SPACING))
109 #define WM2200_DSP2_DM_BASE (WM2200_DSP_RANGE_BASE + (3 * WM2200_DSP_SPACING))
110 #define WM2200_DSP2_PM_BASE (WM2200_DSP_RANGE_BASE + (4 * WM2200_DSP_SPACING))
111 #define WM2200_DSP2_ZM_BASE (WM2200_DSP_RANGE_BASE + (5 * WM2200_DSP_SPACING))
113 static const struct regmap_range_cfg wm2200_ranges[] = {
114 { .name = "DSP1DM", .range_min = WM2200_DSP1_DM_BASE,
115 .range_max = WM2200_DSP1_DM_BASE + 12287,
116 .selector_reg = WM2200_DSP1_CONTROL_3,
117 .selector_mask = WM2200_DSP1_PAGE_BASE_DM_0_MASK,
118 .selector_shift = WM2200_DSP1_PAGE_BASE_DM_0_SHIFT,
119 .window_start = WM2200_DSP1_DM_0, .window_len = 2048, },
121 { .name = "DSP1PM", .range_min = WM2200_DSP1_PM_BASE,
122 .range_max = WM2200_DSP1_PM_BASE + 12287,
123 .selector_reg = WM2200_DSP1_CONTROL_2,
124 .selector_mask = WM2200_DSP1_PAGE_BASE_PM_0_MASK,
125 .selector_shift = WM2200_DSP1_PAGE_BASE_PM_0_SHIFT,
126 .window_start = WM2200_DSP1_PM_0, .window_len = 768, },
128 { .name = "DSP1ZM", .range_min = WM2200_DSP1_ZM_BASE,
129 .range_max = WM2200_DSP1_ZM_BASE + 2047,
130 .selector_reg = WM2200_DSP1_CONTROL_4,
131 .selector_mask = WM2200_DSP1_PAGE_BASE_ZM_0_MASK,
132 .selector_shift = WM2200_DSP1_PAGE_BASE_ZM_0_SHIFT,
133 .window_start = WM2200_DSP1_ZM_0, .window_len = 1024, },
135 { .name = "DSP2DM", .range_min = WM2200_DSP2_DM_BASE,
136 .range_max = WM2200_DSP2_DM_BASE + 4095,
137 .selector_reg = WM2200_DSP2_CONTROL_3,
138 .selector_mask = WM2200_DSP2_PAGE_BASE_DM_0_MASK,
139 .selector_shift = WM2200_DSP2_PAGE_BASE_DM_0_SHIFT,
140 .window_start = WM2200_DSP2_DM_0, .window_len = 2048, },
142 { .name = "DSP2PM", .range_min = WM2200_DSP2_PM_BASE,
143 .range_max = WM2200_DSP2_PM_BASE + 11287,
144 .selector_reg = WM2200_DSP2_CONTROL_2,
145 .selector_mask = WM2200_DSP2_PAGE_BASE_PM_0_MASK,
146 .selector_shift = WM2200_DSP2_PAGE_BASE_PM_0_SHIFT,
147 .window_start = WM2200_DSP2_PM_0, .window_len = 768, },
149 { .name = "DSP2ZM", .range_min = WM2200_DSP2_ZM_BASE,
150 .range_max = WM2200_DSP2_ZM_BASE + 2047,
151 .selector_reg = WM2200_DSP2_CONTROL_4,
152 .selector_mask = WM2200_DSP2_PAGE_BASE_ZM_0_MASK,
153 .selector_shift = WM2200_DSP2_PAGE_BASE_ZM_0_SHIFT,
154 .window_start = WM2200_DSP2_ZM_0, .window_len = 1024, },
157 static const struct wm_adsp_region wm2200_dsp1_regions[] = {
158 { .type = WMFW_ADSP1_PM, .base = WM2200_DSP1_PM_BASE },
159 { .type = WMFW_ADSP1_DM, .base = WM2200_DSP1_DM_BASE },
160 { .type = WMFW_ADSP1_ZM, .base = WM2200_DSP1_ZM_BASE },
163 static const struct wm_adsp_region wm2200_dsp2_regions[] = {
164 { .type = WMFW_ADSP1_PM, .base = WM2200_DSP2_PM_BASE },
165 { .type = WMFW_ADSP1_DM, .base = WM2200_DSP2_DM_BASE },
166 { .type = WMFW_ADSP1_ZM, .base = WM2200_DSP2_ZM_BASE },
169 static const struct reg_default wm2200_reg_defaults[] = {
170 { 0x000B, 0x0000 }, /* R11 - Tone Generator 1 */
171 { 0x0102, 0x0000 }, /* R258 - Clocking 3 */
172 { 0x0103, 0x0011 }, /* R259 - Clocking 4 */
173 { 0x0111, 0x0000 }, /* R273 - FLL Control 1 */
174 { 0x0112, 0x0000 }, /* R274 - FLL Control 2 */
175 { 0x0113, 0x0000 }, /* R275 - FLL Control 3 */
176 { 0x0114, 0x0000 }, /* R276 - FLL Control 4 */
177 { 0x0116, 0x0177 }, /* R278 - FLL Control 6 */
178 { 0x0117, 0x0004 }, /* R279 - FLL Control 7 */
179 { 0x0119, 0x0000 }, /* R281 - FLL EFS 1 */
180 { 0x011A, 0x0002 }, /* R282 - FLL EFS 2 */
181 { 0x0200, 0x0000 }, /* R512 - Mic Charge Pump 1 */
182 { 0x0201, 0x03FF }, /* R513 - Mic Charge Pump 2 */
183 { 0x0202, 0x9BDE }, /* R514 - DM Charge Pump 1 */
184 { 0x020C, 0x0000 }, /* R524 - Mic Bias Ctrl 1 */
185 { 0x020D, 0x0000 }, /* R525 - Mic Bias Ctrl 2 */
186 { 0x020F, 0x0000 }, /* R527 - Ear Piece Ctrl 1 */
187 { 0x0210, 0x0000 }, /* R528 - Ear Piece Ctrl 2 */
188 { 0x0301, 0x0000 }, /* R769 - Input Enables */
189 { 0x0302, 0x2240 }, /* R770 - IN1L Control */
190 { 0x0303, 0x0040 }, /* R771 - IN1R Control */
191 { 0x0304, 0x2240 }, /* R772 - IN2L Control */
192 { 0x0305, 0x0040 }, /* R773 - IN2R Control */
193 { 0x0306, 0x2240 }, /* R774 - IN3L Control */
194 { 0x0307, 0x0040 }, /* R775 - IN3R Control */
195 { 0x030A, 0x0000 }, /* R778 - RXANC_SRC */
196 { 0x030B, 0x0022 }, /* R779 - Input Volume Ramp */
197 { 0x030C, 0x0180 }, /* R780 - ADC Digital Volume 1L */
198 { 0x030D, 0x0180 }, /* R781 - ADC Digital Volume 1R */
199 { 0x030E, 0x0180 }, /* R782 - ADC Digital Volume 2L */
200 { 0x030F, 0x0180 }, /* R783 - ADC Digital Volume 2R */
201 { 0x0310, 0x0180 }, /* R784 - ADC Digital Volume 3L */
202 { 0x0311, 0x0180 }, /* R785 - ADC Digital Volume 3R */
203 { 0x0400, 0x0000 }, /* R1024 - Output Enables */
204 { 0x0401, 0x0000 }, /* R1025 - DAC Volume Limit 1L */
205 { 0x0402, 0x0000 }, /* R1026 - DAC Volume Limit 1R */
206 { 0x0403, 0x0000 }, /* R1027 - DAC Volume Limit 2L */
207 { 0x0404, 0x0000 }, /* R1028 - DAC Volume Limit 2R */
208 { 0x0409, 0x0000 }, /* R1033 - DAC AEC Control 1 */
209 { 0x040A, 0x0022 }, /* R1034 - Output Volume Ramp */
210 { 0x040B, 0x0180 }, /* R1035 - DAC Digital Volume 1L */
211 { 0x040C, 0x0180 }, /* R1036 - DAC Digital Volume 1R */
212 { 0x040D, 0x0180 }, /* R1037 - DAC Digital Volume 2L */
213 { 0x040E, 0x0180 }, /* R1038 - DAC Digital Volume 2R */
214 { 0x0417, 0x0069 }, /* R1047 - PDM 1 */
215 { 0x0418, 0x0000 }, /* R1048 - PDM 2 */
216 { 0x0500, 0x0000 }, /* R1280 - Audio IF 1_1 */
217 { 0x0501, 0x0008 }, /* R1281 - Audio IF 1_2 */
218 { 0x0502, 0x0000 }, /* R1282 - Audio IF 1_3 */
219 { 0x0503, 0x0000 }, /* R1283 - Audio IF 1_4 */
220 { 0x0504, 0x0000 }, /* R1284 - Audio IF 1_5 */
221 { 0x0505, 0x0001 }, /* R1285 - Audio IF 1_6 */
222 { 0x0506, 0x0001 }, /* R1286 - Audio IF 1_7 */
223 { 0x0507, 0x0000 }, /* R1287 - Audio IF 1_8 */
224 { 0x0508, 0x0000 }, /* R1288 - Audio IF 1_9 */
225 { 0x0509, 0x0000 }, /* R1289 - Audio IF 1_10 */
226 { 0x050A, 0x0000 }, /* R1290 - Audio IF 1_11 */
227 { 0x050B, 0x0000 }, /* R1291 - Audio IF 1_12 */
228 { 0x050C, 0x0000 }, /* R1292 - Audio IF 1_13 */
229 { 0x050D, 0x0000 }, /* R1293 - Audio IF 1_14 */
230 { 0x050E, 0x0000 }, /* R1294 - Audio IF 1_15 */
231 { 0x050F, 0x0000 }, /* R1295 - Audio IF 1_16 */
232 { 0x0510, 0x0000 }, /* R1296 - Audio IF 1_17 */
233 { 0x0511, 0x0000 }, /* R1297 - Audio IF 1_18 */
234 { 0x0512, 0x0000 }, /* R1298 - Audio IF 1_19 */
235 { 0x0513, 0x0000 }, /* R1299 - Audio IF 1_20 */
236 { 0x0514, 0x0000 }, /* R1300 - Audio IF 1_21 */
237 { 0x0515, 0x0001 }, /* R1301 - Audio IF 1_22 */
238 { 0x0600, 0x0000 }, /* R1536 - OUT1LMIX Input 1 Source */
239 { 0x0601, 0x0080 }, /* R1537 - OUT1LMIX Input 1 Volume */
240 { 0x0602, 0x0000 }, /* R1538 - OUT1LMIX Input 2 Source */
241 { 0x0603, 0x0080 }, /* R1539 - OUT1LMIX Input 2 Volume */
242 { 0x0604, 0x0000 }, /* R1540 - OUT1LMIX Input 3 Source */
243 { 0x0605, 0x0080 }, /* R1541 - OUT1LMIX Input 3 Volume */
244 { 0x0606, 0x0000 }, /* R1542 - OUT1LMIX Input 4 Source */
245 { 0x0607, 0x0080 }, /* R1543 - OUT1LMIX Input 4 Volume */
246 { 0x0608, 0x0000 }, /* R1544 - OUT1RMIX Input 1 Source */
247 { 0x0609, 0x0080 }, /* R1545 - OUT1RMIX Input 1 Volume */
248 { 0x060A, 0x0000 }, /* R1546 - OUT1RMIX Input 2 Source */
249 { 0x060B, 0x0080 }, /* R1547 - OUT1RMIX Input 2 Volume */
250 { 0x060C, 0x0000 }, /* R1548 - OUT1RMIX Input 3 Source */
251 { 0x060D, 0x0080 }, /* R1549 - OUT1RMIX Input 3 Volume */
252 { 0x060E, 0x0000 }, /* R1550 - OUT1RMIX Input 4 Source */
253 { 0x060F, 0x0080 }, /* R1551 - OUT1RMIX Input 4 Volume */
254 { 0x0610, 0x0000 }, /* R1552 - OUT2LMIX Input 1 Source */
255 { 0x0611, 0x0080 }, /* R1553 - OUT2LMIX Input 1 Volume */
256 { 0x0612, 0x0000 }, /* R1554 - OUT2LMIX Input 2 Source */
257 { 0x0613, 0x0080 }, /* R1555 - OUT2LMIX Input 2 Volume */
258 { 0x0614, 0x0000 }, /* R1556 - OUT2LMIX Input 3 Source */
259 { 0x0615, 0x0080 }, /* R1557 - OUT2LMIX Input 3 Volume */
260 { 0x0616, 0x0000 }, /* R1558 - OUT2LMIX Input 4 Source */
261 { 0x0617, 0x0080 }, /* R1559 - OUT2LMIX Input 4 Volume */
262 { 0x0618, 0x0000 }, /* R1560 - OUT2RMIX Input 1 Source */
263 { 0x0619, 0x0080 }, /* R1561 - OUT2RMIX Input 1 Volume */
264 { 0x061A, 0x0000 }, /* R1562 - OUT2RMIX Input 2 Source */
265 { 0x061B, 0x0080 }, /* R1563 - OUT2RMIX Input 2 Volume */
266 { 0x061C, 0x0000 }, /* R1564 - OUT2RMIX Input 3 Source */
267 { 0x061D, 0x0080 }, /* R1565 - OUT2RMIX Input 3 Volume */
268 { 0x061E, 0x0000 }, /* R1566 - OUT2RMIX Input 4 Source */
269 { 0x061F, 0x0080 }, /* R1567 - OUT2RMIX Input 4 Volume */
270 { 0x0620, 0x0000 }, /* R1568 - AIF1TX1MIX Input 1 Source */
271 { 0x0621, 0x0080 }, /* R1569 - AIF1TX1MIX Input 1 Volume */
272 { 0x0622, 0x0000 }, /* R1570 - AIF1TX1MIX Input 2 Source */
273 { 0x0623, 0x0080 }, /* R1571 - AIF1TX1MIX Input 2 Volume */
274 { 0x0624, 0x0000 }, /* R1572 - AIF1TX1MIX Input 3 Source */
275 { 0x0625, 0x0080 }, /* R1573 - AIF1TX1MIX Input 3 Volume */
276 { 0x0626, 0x0000 }, /* R1574 - AIF1TX1MIX Input 4 Source */
277 { 0x0627, 0x0080 }, /* R1575 - AIF1TX1MIX Input 4 Volume */
278 { 0x0628, 0x0000 }, /* R1576 - AIF1TX2MIX Input 1 Source */
279 { 0x0629, 0x0080 }, /* R1577 - AIF1TX2MIX Input 1 Volume */
280 { 0x062A, 0x0000 }, /* R1578 - AIF1TX2MIX Input 2 Source */
281 { 0x062B, 0x0080 }, /* R1579 - AIF1TX2MIX Input 2 Volume */
282 { 0x062C, 0x0000 }, /* R1580 - AIF1TX2MIX Input 3 Source */
283 { 0x062D, 0x0080 }, /* R1581 - AIF1TX2MIX Input 3 Volume */
284 { 0x062E, 0x0000 }, /* R1582 - AIF1TX2MIX Input 4 Source */
285 { 0x062F, 0x0080 }, /* R1583 - AIF1TX2MIX Input 4 Volume */
286 { 0x0630, 0x0000 }, /* R1584 - AIF1TX3MIX Input 1 Source */
287 { 0x0631, 0x0080 }, /* R1585 - AIF1TX3MIX Input 1 Volume */
288 { 0x0632, 0x0000 }, /* R1586 - AIF1TX3MIX Input 2 Source */
289 { 0x0633, 0x0080 }, /* R1587 - AIF1TX3MIX Input 2 Volume */
290 { 0x0634, 0x0000 }, /* R1588 - AIF1TX3MIX Input 3 Source */
291 { 0x0635, 0x0080 }, /* R1589 - AIF1TX3MIX Input 3 Volume */
292 { 0x0636, 0x0000 }, /* R1590 - AIF1TX3MIX Input 4 Source */
293 { 0x0637, 0x0080 }, /* R1591 - AIF1TX3MIX Input 4 Volume */
294 { 0x0638, 0x0000 }, /* R1592 - AIF1TX4MIX Input 1 Source */
295 { 0x0639, 0x0080 }, /* R1593 - AIF1TX4MIX Input 1 Volume */
296 { 0x063A, 0x0000 }, /* R1594 - AIF1TX4MIX Input 2 Source */
297 { 0x063B, 0x0080 }, /* R1595 - AIF1TX4MIX Input 2 Volume */
298 { 0x063C, 0x0000 }, /* R1596 - AIF1TX4MIX Input 3 Source */
299 { 0x063D, 0x0080 }, /* R1597 - AIF1TX4MIX Input 3 Volume */
300 { 0x063E, 0x0000 }, /* R1598 - AIF1TX4MIX Input 4 Source */
301 { 0x063F, 0x0080 }, /* R1599 - AIF1TX4MIX Input 4 Volume */
302 { 0x0640, 0x0000 }, /* R1600 - AIF1TX5MIX Input 1 Source */
303 { 0x0641, 0x0080 }, /* R1601 - AIF1TX5MIX Input 1 Volume */
304 { 0x0642, 0x0000 }, /* R1602 - AIF1TX5MIX Input 2 Source */
305 { 0x0643, 0x0080 }, /* R1603 - AIF1TX5MIX Input 2 Volume */
306 { 0x0644, 0x0000 }, /* R1604 - AIF1TX5MIX Input 3 Source */
307 { 0x0645, 0x0080 }, /* R1605 - AIF1TX5MIX Input 3 Volume */
308 { 0x0646, 0x0000 }, /* R1606 - AIF1TX5MIX Input 4 Source */
309 { 0x0647, 0x0080 }, /* R1607 - AIF1TX5MIX Input 4 Volume */
310 { 0x0648, 0x0000 }, /* R1608 - AIF1TX6MIX Input 1 Source */
311 { 0x0649, 0x0080 }, /* R1609 - AIF1TX6MIX Input 1 Volume */
312 { 0x064A, 0x0000 }, /* R1610 - AIF1TX6MIX Input 2 Source */
313 { 0x064B, 0x0080 }, /* R1611 - AIF1TX6MIX Input 2 Volume */
314 { 0x064C, 0x0000 }, /* R1612 - AIF1TX6MIX Input 3 Source */
315 { 0x064D, 0x0080 }, /* R1613 - AIF1TX6MIX Input 3 Volume */
316 { 0x064E, 0x0000 }, /* R1614 - AIF1TX6MIX Input 4 Source */
317 { 0x064F, 0x0080 }, /* R1615 - AIF1TX6MIX Input 4 Volume */
318 { 0x0650, 0x0000 }, /* R1616 - EQLMIX Input 1 Source */
319 { 0x0651, 0x0080 }, /* R1617 - EQLMIX Input 1 Volume */
320 { 0x0652, 0x0000 }, /* R1618 - EQLMIX Input 2 Source */
321 { 0x0653, 0x0080 }, /* R1619 - EQLMIX Input 2 Volume */
322 { 0x0654, 0x0000 }, /* R1620 - EQLMIX Input 3 Source */
323 { 0x0655, 0x0080 }, /* R1621 - EQLMIX Input 3 Volume */
324 { 0x0656, 0x0000 }, /* R1622 - EQLMIX Input 4 Source */
325 { 0x0657, 0x0080 }, /* R1623 - EQLMIX Input 4 Volume */
326 { 0x0658, 0x0000 }, /* R1624 - EQRMIX Input 1 Source */
327 { 0x0659, 0x0080 }, /* R1625 - EQRMIX Input 1 Volume */
328 { 0x065A, 0x0000 }, /* R1626 - EQRMIX Input 2 Source */
329 { 0x065B, 0x0080 }, /* R1627 - EQRMIX Input 2 Volume */
330 { 0x065C, 0x0000 }, /* R1628 - EQRMIX Input 3 Source */
331 { 0x065D, 0x0080 }, /* R1629 - EQRMIX Input 3 Volume */
332 { 0x065E, 0x0000 }, /* R1630 - EQRMIX Input 4 Source */
333 { 0x065F, 0x0080 }, /* R1631 - EQRMIX Input 4 Volume */
334 { 0x0660, 0x0000 }, /* R1632 - LHPF1MIX Input 1 Source */
335 { 0x0661, 0x0080 }, /* R1633 - LHPF1MIX Input 1 Volume */
336 { 0x0662, 0x0000 }, /* R1634 - LHPF1MIX Input 2 Source */
337 { 0x0663, 0x0080 }, /* R1635 - LHPF1MIX Input 2 Volume */
338 { 0x0664, 0x0000 }, /* R1636 - LHPF1MIX Input 3 Source */
339 { 0x0665, 0x0080 }, /* R1637 - LHPF1MIX Input 3 Volume */
340 { 0x0666, 0x0000 }, /* R1638 - LHPF1MIX Input 4 Source */
341 { 0x0667, 0x0080 }, /* R1639 - LHPF1MIX Input 4 Volume */
342 { 0x0668, 0x0000 }, /* R1640 - LHPF2MIX Input 1 Source */
343 { 0x0669, 0x0080 }, /* R1641 - LHPF2MIX Input 1 Volume */
344 { 0x066A, 0x0000 }, /* R1642 - LHPF2MIX Input 2 Source */
345 { 0x066B, 0x0080 }, /* R1643 - LHPF2MIX Input 2 Volume */
346 { 0x066C, 0x0000 }, /* R1644 - LHPF2MIX Input 3 Source */
347 { 0x066D, 0x0080 }, /* R1645 - LHPF2MIX Input 3 Volume */
348 { 0x066E, 0x0000 }, /* R1646 - LHPF2MIX Input 4 Source */
349 { 0x066F, 0x0080 }, /* R1647 - LHPF2MIX Input 4 Volume */
350 { 0x0670, 0x0000 }, /* R1648 - DSP1LMIX Input 1 Source */
351 { 0x0671, 0x0080 }, /* R1649 - DSP1LMIX Input 1 Volume */
352 { 0x0672, 0x0000 }, /* R1650 - DSP1LMIX Input 2 Source */
353 { 0x0673, 0x0080 }, /* R1651 - DSP1LMIX Input 2 Volume */
354 { 0x0674, 0x0000 }, /* R1652 - DSP1LMIX Input 3 Source */
355 { 0x0675, 0x0080 }, /* R1653 - DSP1LMIX Input 3 Volume */
356 { 0x0676, 0x0000 }, /* R1654 - DSP1LMIX Input 4 Source */
357 { 0x0677, 0x0080 }, /* R1655 - DSP1LMIX Input 4 Volume */
358 { 0x0678, 0x0000 }, /* R1656 - DSP1RMIX Input 1 Source */
359 { 0x0679, 0x0080 }, /* R1657 - DSP1RMIX Input 1 Volume */
360 { 0x067A, 0x0000 }, /* R1658 - DSP1RMIX Input 2 Source */
361 { 0x067B, 0x0080 }, /* R1659 - DSP1RMIX Input 2 Volume */
362 { 0x067C, 0x0000 }, /* R1660 - DSP1RMIX Input 3 Source */
363 { 0x067D, 0x0080 }, /* R1661 - DSP1RMIX Input 3 Volume */
364 { 0x067E, 0x0000 }, /* R1662 - DSP1RMIX Input 4 Source */
365 { 0x067F, 0x0080 }, /* R1663 - DSP1RMIX Input 4 Volume */
366 { 0x0680, 0x0000 }, /* R1664 - DSP1AUX1MIX Input 1 Source */
367 { 0x0681, 0x0000 }, /* R1665 - DSP1AUX2MIX Input 1 Source */
368 { 0x0682, 0x0000 }, /* R1666 - DSP1AUX3MIX Input 1 Source */
369 { 0x0683, 0x0000 }, /* R1667 - DSP1AUX4MIX Input 1 Source */
370 { 0x0684, 0x0000 }, /* R1668 - DSP1AUX5MIX Input 1 Source */
371 { 0x0685, 0x0000 }, /* R1669 - DSP1AUX6MIX Input 1 Source */
372 { 0x0686, 0x0000 }, /* R1670 - DSP2LMIX Input 1 Source */
373 { 0x0687, 0x0080 }, /* R1671 - DSP2LMIX Input 1 Volume */
374 { 0x0688, 0x0000 }, /* R1672 - DSP2LMIX Input 2 Source */
375 { 0x0689, 0x0080 }, /* R1673 - DSP2LMIX Input 2 Volume */
376 { 0x068A, 0x0000 }, /* R1674 - DSP2LMIX Input 3 Source */
377 { 0x068B, 0x0080 }, /* R1675 - DSP2LMIX Input 3 Volume */
378 { 0x068C, 0x0000 }, /* R1676 - DSP2LMIX Input 4 Source */
379 { 0x068D, 0x0080 }, /* R1677 - DSP2LMIX Input 4 Volume */
380 { 0x068E, 0x0000 }, /* R1678 - DSP2RMIX Input 1 Source */
381 { 0x068F, 0x0080 }, /* R1679 - DSP2RMIX Input 1 Volume */
382 { 0x0690, 0x0000 }, /* R1680 - DSP2RMIX Input 2 Source */
383 { 0x0691, 0x0080 }, /* R1681 - DSP2RMIX Input 2 Volume */
384 { 0x0692, 0x0000 }, /* R1682 - DSP2RMIX Input 3 Source */
385 { 0x0693, 0x0080 }, /* R1683 - DSP2RMIX Input 3 Volume */
386 { 0x0694, 0x0000 }, /* R1684 - DSP2RMIX Input 4 Source */
387 { 0x0695, 0x0080 }, /* R1685 - DSP2RMIX Input 4 Volume */
388 { 0x0696, 0x0000 }, /* R1686 - DSP2AUX1MIX Input 1 Source */
389 { 0x0697, 0x0000 }, /* R1687 - DSP2AUX2MIX Input 1 Source */
390 { 0x0698, 0x0000 }, /* R1688 - DSP2AUX3MIX Input 1 Source */
391 { 0x0699, 0x0000 }, /* R1689 - DSP2AUX4MIX Input 1 Source */
392 { 0x069A, 0x0000 }, /* R1690 - DSP2AUX5MIX Input 1 Source */
393 { 0x069B, 0x0000 }, /* R1691 - DSP2AUX6MIX Input 1 Source */
394 { 0x0700, 0xA101 }, /* R1792 - GPIO CTRL 1 */
395 { 0x0701, 0xA101 }, /* R1793 - GPIO CTRL 2 */
396 { 0x0702, 0xA101 }, /* R1794 - GPIO CTRL 3 */
397 { 0x0703, 0xA101 }, /* R1795 - GPIO CTRL 4 */
398 { 0x0709, 0x0000 }, /* R1801 - Misc Pad Ctrl 1 */
399 { 0x0801, 0x00FF }, /* R2049 - Interrupt Status 1 Mask */
400 { 0x0804, 0xFFFF }, /* R2052 - Interrupt Status 2 Mask */
401 { 0x0808, 0x0000 }, /* R2056 - Interrupt Control */
402 { 0x0900, 0x0000 }, /* R2304 - EQL_1 */
403 { 0x0901, 0x0000 }, /* R2305 - EQL_2 */
404 { 0x0902, 0x0000 }, /* R2306 - EQL_3 */
405 { 0x0903, 0x0000 }, /* R2307 - EQL_4 */
406 { 0x0904, 0x0000 }, /* R2308 - EQL_5 */
407 { 0x0905, 0x0000 }, /* R2309 - EQL_6 */
408 { 0x0906, 0x0000 }, /* R2310 - EQL_7 */
409 { 0x0907, 0x0000 }, /* R2311 - EQL_8 */
410 { 0x0908, 0x0000 }, /* R2312 - EQL_9 */
411 { 0x0909, 0x0000 }, /* R2313 - EQL_10 */
412 { 0x090A, 0x0000 }, /* R2314 - EQL_11 */
413 { 0x090B, 0x0000 }, /* R2315 - EQL_12 */
414 { 0x090C, 0x0000 }, /* R2316 - EQL_13 */
415 { 0x090D, 0x0000 }, /* R2317 - EQL_14 */
416 { 0x090E, 0x0000 }, /* R2318 - EQL_15 */
417 { 0x090F, 0x0000 }, /* R2319 - EQL_16 */
418 { 0x0910, 0x0000 }, /* R2320 - EQL_17 */
419 { 0x0911, 0x0000 }, /* R2321 - EQL_18 */
420 { 0x0912, 0x0000 }, /* R2322 - EQL_19 */
421 { 0x0913, 0x0000 }, /* R2323 - EQL_20 */
422 { 0x0916, 0x0000 }, /* R2326 - EQR_1 */
423 { 0x0917, 0x0000 }, /* R2327 - EQR_2 */
424 { 0x0918, 0x0000 }, /* R2328 - EQR_3 */
425 { 0x0919, 0x0000 }, /* R2329 - EQR_4 */
426 { 0x091A, 0x0000 }, /* R2330 - EQR_5 */
427 { 0x091B, 0x0000 }, /* R2331 - EQR_6 */
428 { 0x091C, 0x0000 }, /* R2332 - EQR_7 */
429 { 0x091D, 0x0000 }, /* R2333 - EQR_8 */
430 { 0x091E, 0x0000 }, /* R2334 - EQR_9 */
431 { 0x091F, 0x0000 }, /* R2335 - EQR_10 */
432 { 0x0920, 0x0000 }, /* R2336 - EQR_11 */
433 { 0x0921, 0x0000 }, /* R2337 - EQR_12 */
434 { 0x0922, 0x0000 }, /* R2338 - EQR_13 */
435 { 0x0923, 0x0000 }, /* R2339 - EQR_14 */
436 { 0x0924, 0x0000 }, /* R2340 - EQR_15 */
437 { 0x0925, 0x0000 }, /* R2341 - EQR_16 */
438 { 0x0926, 0x0000 }, /* R2342 - EQR_17 */
439 { 0x0927, 0x0000 }, /* R2343 - EQR_18 */
440 { 0x0928, 0x0000 }, /* R2344 - EQR_19 */
441 { 0x0929, 0x0000 }, /* R2345 - EQR_20 */
442 { 0x093E, 0x0000 }, /* R2366 - HPLPF1_1 */
443 { 0x093F, 0x0000 }, /* R2367 - HPLPF1_2 */
444 { 0x0942, 0x0000 }, /* R2370 - HPLPF2_1 */
445 { 0x0943, 0x0000 }, /* R2371 - HPLPF2_2 */
446 { 0x0A00, 0x0000 }, /* R2560 - DSP1 Control 1 */
447 { 0x0A02, 0x0000 }, /* R2562 - DSP1 Control 2 */
448 { 0x0A03, 0x0000 }, /* R2563 - DSP1 Control 3 */
449 { 0x0A04, 0x0000 }, /* R2564 - DSP1 Control 4 */
450 { 0x0A06, 0x0000 }, /* R2566 - DSP1 Control 5 */
451 { 0x0A07, 0x0000 }, /* R2567 - DSP1 Control 6 */
452 { 0x0A08, 0x0000 }, /* R2568 - DSP1 Control 7 */
453 { 0x0A09, 0x0000 }, /* R2569 - DSP1 Control 8 */
454 { 0x0A0A, 0x0000 }, /* R2570 - DSP1 Control 9 */
455 { 0x0A0B, 0x0000 }, /* R2571 - DSP1 Control 10 */
456 { 0x0A0C, 0x0000 }, /* R2572 - DSP1 Control 11 */
457 { 0x0A0D, 0x0000 }, /* R2573 - DSP1 Control 12 */
458 { 0x0A0F, 0x0000 }, /* R2575 - DSP1 Control 13 */
459 { 0x0A10, 0x0000 }, /* R2576 - DSP1 Control 14 */
460 { 0x0A11, 0x0000 }, /* R2577 - DSP1 Control 15 */
461 { 0x0A12, 0x0000 }, /* R2578 - DSP1 Control 16 */
462 { 0x0A13, 0x0000 }, /* R2579 - DSP1 Control 17 */
463 { 0x0A14, 0x0000 }, /* R2580 - DSP1 Control 18 */
464 { 0x0A16, 0x0000 }, /* R2582 - DSP1 Control 19 */
465 { 0x0A17, 0x0000 }, /* R2583 - DSP1 Control 20 */
466 { 0x0A18, 0x0000 }, /* R2584 - DSP1 Control 21 */
467 { 0x0A1A, 0x1800 }, /* R2586 - DSP1 Control 22 */
468 { 0x0A1B, 0x1000 }, /* R2587 - DSP1 Control 23 */
469 { 0x0A1C, 0x0400 }, /* R2588 - DSP1 Control 24 */
470 { 0x0A1E, 0x0000 }, /* R2590 - DSP1 Control 25 */
471 { 0x0A20, 0x0000 }, /* R2592 - DSP1 Control 26 */
472 { 0x0A21, 0x0000 }, /* R2593 - DSP1 Control 27 */
473 { 0x0A22, 0x0000 }, /* R2594 - DSP1 Control 28 */
474 { 0x0A23, 0x0000 }, /* R2595 - DSP1 Control 29 */
475 { 0x0A24, 0x0000 }, /* R2596 - DSP1 Control 30 */
476 { 0x0A26, 0x0000 }, /* R2598 - DSP1 Control 31 */
477 { 0x0B00, 0x0000 }, /* R2816 - DSP2 Control 1 */
478 { 0x0B02, 0x0000 }, /* R2818 - DSP2 Control 2 */
479 { 0x0B03, 0x0000 }, /* R2819 - DSP2 Control 3 */
480 { 0x0B04, 0x0000 }, /* R2820 - DSP2 Control 4 */
481 { 0x0B06, 0x0000 }, /* R2822 - DSP2 Control 5 */
482 { 0x0B07, 0x0000 }, /* R2823 - DSP2 Control 6 */
483 { 0x0B08, 0x0000 }, /* R2824 - DSP2 Control 7 */
484 { 0x0B09, 0x0000 }, /* R2825 - DSP2 Control 8 */
485 { 0x0B0A, 0x0000 }, /* R2826 - DSP2 Control 9 */
486 { 0x0B0B, 0x0000 }, /* R2827 - DSP2 Control 10 */
487 { 0x0B0C, 0x0000 }, /* R2828 - DSP2 Control 11 */
488 { 0x0B0D, 0x0000 }, /* R2829 - DSP2 Control 12 */
489 { 0x0B0F, 0x0000 }, /* R2831 - DSP2 Control 13 */
490 { 0x0B10, 0x0000 }, /* R2832 - DSP2 Control 14 */
491 { 0x0B11, 0x0000 }, /* R2833 - DSP2 Control 15 */
492 { 0x0B12, 0x0000 }, /* R2834 - DSP2 Control 16 */
493 { 0x0B13, 0x0000 }, /* R2835 - DSP2 Control 17 */
494 { 0x0B14, 0x0000 }, /* R2836 - DSP2 Control 18 */
495 { 0x0B16, 0x0000 }, /* R2838 - DSP2 Control 19 */
496 { 0x0B17, 0x0000 }, /* R2839 - DSP2 Control 20 */
497 { 0x0B18, 0x0000 }, /* R2840 - DSP2 Control 21 */
498 { 0x0B1A, 0x0800 }, /* R2842 - DSP2 Control 22 */
499 { 0x0B1B, 0x1000 }, /* R2843 - DSP2 Control 23 */
500 { 0x0B1C, 0x0400 }, /* R2844 - DSP2 Control 24 */
501 { 0x0B1E, 0x0000 }, /* R2846 - DSP2 Control 25 */
502 { 0x0B20, 0x0000 }, /* R2848 - DSP2 Control 26 */
503 { 0x0B21, 0x0000 }, /* R2849 - DSP2 Control 27 */
504 { 0x0B22, 0x0000 }, /* R2850 - DSP2 Control 28 */
505 { 0x0B23, 0x0000 }, /* R2851 - DSP2 Control 29 */
506 { 0x0B24, 0x0000 }, /* R2852 - DSP2 Control 30 */
507 { 0x0B26, 0x0000 }, /* R2854 - DSP2 Control 31 */
510 static bool wm2200_volatile_register(struct device *dev, unsigned int reg)
514 for (i = 0; i < ARRAY_SIZE(wm2200_ranges); i++)
515 if ((reg >= wm2200_ranges[i].window_start &&
516 reg <= wm2200_ranges[i].window_start +
517 wm2200_ranges[i].window_len) ||
518 (reg >= wm2200_ranges[i].range_min &&
519 reg <= wm2200_ranges[i].range_max))
523 case WM2200_SOFTWARE_RESET:
524 case WM2200_DEVICE_REVISION:
525 case WM2200_ADPS1_IRQ0:
526 case WM2200_ADPS1_IRQ1:
527 case WM2200_INTERRUPT_STATUS_1:
528 case WM2200_INTERRUPT_STATUS_2:
529 case WM2200_INTERRUPT_RAW_STATUS_2:
536 static bool wm2200_readable_register(struct device *dev, unsigned int reg)
540 for (i = 0; i < ARRAY_SIZE(wm2200_ranges); i++)
541 if ((reg >= wm2200_ranges[i].window_start &&
542 reg <= wm2200_ranges[i].window_start +
543 wm2200_ranges[i].window_len) ||
544 (reg >= wm2200_ranges[i].range_min &&
545 reg <= wm2200_ranges[i].range_max))
549 case WM2200_SOFTWARE_RESET:
550 case WM2200_DEVICE_REVISION:
551 case WM2200_TONE_GENERATOR_1:
552 case WM2200_CLOCKING_3:
553 case WM2200_CLOCKING_4:
554 case WM2200_FLL_CONTROL_1:
555 case WM2200_FLL_CONTROL_2:
556 case WM2200_FLL_CONTROL_3:
557 case WM2200_FLL_CONTROL_4:
558 case WM2200_FLL_CONTROL_6:
559 case WM2200_FLL_CONTROL_7:
560 case WM2200_FLL_EFS_1:
561 case WM2200_FLL_EFS_2:
562 case WM2200_MIC_CHARGE_PUMP_1:
563 case WM2200_MIC_CHARGE_PUMP_2:
564 case WM2200_DM_CHARGE_PUMP_1:
565 case WM2200_MIC_BIAS_CTRL_1:
566 case WM2200_MIC_BIAS_CTRL_2:
567 case WM2200_EAR_PIECE_CTRL_1:
568 case WM2200_EAR_PIECE_CTRL_2:
569 case WM2200_INPUT_ENABLES:
570 case WM2200_IN1L_CONTROL:
571 case WM2200_IN1R_CONTROL:
572 case WM2200_IN2L_CONTROL:
573 case WM2200_IN2R_CONTROL:
574 case WM2200_IN3L_CONTROL:
575 case WM2200_IN3R_CONTROL:
576 case WM2200_RXANC_SRC:
577 case WM2200_INPUT_VOLUME_RAMP:
578 case WM2200_ADC_DIGITAL_VOLUME_1L:
579 case WM2200_ADC_DIGITAL_VOLUME_1R:
580 case WM2200_ADC_DIGITAL_VOLUME_2L:
581 case WM2200_ADC_DIGITAL_VOLUME_2R:
582 case WM2200_ADC_DIGITAL_VOLUME_3L:
583 case WM2200_ADC_DIGITAL_VOLUME_3R:
584 case WM2200_OUTPUT_ENABLES:
585 case WM2200_DAC_VOLUME_LIMIT_1L:
586 case WM2200_DAC_VOLUME_LIMIT_1R:
587 case WM2200_DAC_VOLUME_LIMIT_2L:
588 case WM2200_DAC_VOLUME_LIMIT_2R:
589 case WM2200_DAC_AEC_CONTROL_1:
590 case WM2200_OUTPUT_VOLUME_RAMP:
591 case WM2200_DAC_DIGITAL_VOLUME_1L:
592 case WM2200_DAC_DIGITAL_VOLUME_1R:
593 case WM2200_DAC_DIGITAL_VOLUME_2L:
594 case WM2200_DAC_DIGITAL_VOLUME_2R:
597 case WM2200_AUDIO_IF_1_1:
598 case WM2200_AUDIO_IF_1_2:
599 case WM2200_AUDIO_IF_1_3:
600 case WM2200_AUDIO_IF_1_4:
601 case WM2200_AUDIO_IF_1_5:
602 case WM2200_AUDIO_IF_1_6:
603 case WM2200_AUDIO_IF_1_7:
604 case WM2200_AUDIO_IF_1_8:
605 case WM2200_AUDIO_IF_1_9:
606 case WM2200_AUDIO_IF_1_10:
607 case WM2200_AUDIO_IF_1_11:
608 case WM2200_AUDIO_IF_1_12:
609 case WM2200_AUDIO_IF_1_13:
610 case WM2200_AUDIO_IF_1_14:
611 case WM2200_AUDIO_IF_1_15:
612 case WM2200_AUDIO_IF_1_16:
613 case WM2200_AUDIO_IF_1_17:
614 case WM2200_AUDIO_IF_1_18:
615 case WM2200_AUDIO_IF_1_19:
616 case WM2200_AUDIO_IF_1_20:
617 case WM2200_AUDIO_IF_1_21:
618 case WM2200_AUDIO_IF_1_22:
619 case WM2200_OUT1LMIX_INPUT_1_SOURCE:
620 case WM2200_OUT1LMIX_INPUT_1_VOLUME:
621 case WM2200_OUT1LMIX_INPUT_2_SOURCE:
622 case WM2200_OUT1LMIX_INPUT_2_VOLUME:
623 case WM2200_OUT1LMIX_INPUT_3_SOURCE:
624 case WM2200_OUT1LMIX_INPUT_3_VOLUME:
625 case WM2200_OUT1LMIX_INPUT_4_SOURCE:
626 case WM2200_OUT1LMIX_INPUT_4_VOLUME:
627 case WM2200_OUT1RMIX_INPUT_1_SOURCE:
628 case WM2200_OUT1RMIX_INPUT_1_VOLUME:
629 case WM2200_OUT1RMIX_INPUT_2_SOURCE:
630 case WM2200_OUT1RMIX_INPUT_2_VOLUME:
631 case WM2200_OUT1RMIX_INPUT_3_SOURCE:
632 case WM2200_OUT1RMIX_INPUT_3_VOLUME:
633 case WM2200_OUT1RMIX_INPUT_4_SOURCE:
634 case WM2200_OUT1RMIX_INPUT_4_VOLUME:
635 case WM2200_OUT2LMIX_INPUT_1_SOURCE:
636 case WM2200_OUT2LMIX_INPUT_1_VOLUME:
637 case WM2200_OUT2LMIX_INPUT_2_SOURCE:
638 case WM2200_OUT2LMIX_INPUT_2_VOLUME:
639 case WM2200_OUT2LMIX_INPUT_3_SOURCE:
640 case WM2200_OUT2LMIX_INPUT_3_VOLUME:
641 case WM2200_OUT2LMIX_INPUT_4_SOURCE:
642 case WM2200_OUT2LMIX_INPUT_4_VOLUME:
643 case WM2200_OUT2RMIX_INPUT_1_SOURCE:
644 case WM2200_OUT2RMIX_INPUT_1_VOLUME:
645 case WM2200_OUT2RMIX_INPUT_2_SOURCE:
646 case WM2200_OUT2RMIX_INPUT_2_VOLUME:
647 case WM2200_OUT2RMIX_INPUT_3_SOURCE:
648 case WM2200_OUT2RMIX_INPUT_3_VOLUME:
649 case WM2200_OUT2RMIX_INPUT_4_SOURCE:
650 case WM2200_OUT2RMIX_INPUT_4_VOLUME:
651 case WM2200_AIF1TX1MIX_INPUT_1_SOURCE:
652 case WM2200_AIF1TX1MIX_INPUT_1_VOLUME:
653 case WM2200_AIF1TX1MIX_INPUT_2_SOURCE:
654 case WM2200_AIF1TX1MIX_INPUT_2_VOLUME:
655 case WM2200_AIF1TX1MIX_INPUT_3_SOURCE:
656 case WM2200_AIF1TX1MIX_INPUT_3_VOLUME:
657 case WM2200_AIF1TX1MIX_INPUT_4_SOURCE:
658 case WM2200_AIF1TX1MIX_INPUT_4_VOLUME:
659 case WM2200_AIF1TX2MIX_INPUT_1_SOURCE:
660 case WM2200_AIF1TX2MIX_INPUT_1_VOLUME:
661 case WM2200_AIF1TX2MIX_INPUT_2_SOURCE:
662 case WM2200_AIF1TX2MIX_INPUT_2_VOLUME:
663 case WM2200_AIF1TX2MIX_INPUT_3_SOURCE:
664 case WM2200_AIF1TX2MIX_INPUT_3_VOLUME:
665 case WM2200_AIF1TX2MIX_INPUT_4_SOURCE:
666 case WM2200_AIF1TX2MIX_INPUT_4_VOLUME:
667 case WM2200_AIF1TX3MIX_INPUT_1_SOURCE:
668 case WM2200_AIF1TX3MIX_INPUT_1_VOLUME:
669 case WM2200_AIF1TX3MIX_INPUT_2_SOURCE:
670 case WM2200_AIF1TX3MIX_INPUT_2_VOLUME:
671 case WM2200_AIF1TX3MIX_INPUT_3_SOURCE:
672 case WM2200_AIF1TX3MIX_INPUT_3_VOLUME:
673 case WM2200_AIF1TX3MIX_INPUT_4_SOURCE:
674 case WM2200_AIF1TX3MIX_INPUT_4_VOLUME:
675 case WM2200_AIF1TX4MIX_INPUT_1_SOURCE:
676 case WM2200_AIF1TX4MIX_INPUT_1_VOLUME:
677 case WM2200_AIF1TX4MIX_INPUT_2_SOURCE:
678 case WM2200_AIF1TX4MIX_INPUT_2_VOLUME:
679 case WM2200_AIF1TX4MIX_INPUT_3_SOURCE:
680 case WM2200_AIF1TX4MIX_INPUT_3_VOLUME:
681 case WM2200_AIF1TX4MIX_INPUT_4_SOURCE:
682 case WM2200_AIF1TX4MIX_INPUT_4_VOLUME:
683 case WM2200_AIF1TX5MIX_INPUT_1_SOURCE:
684 case WM2200_AIF1TX5MIX_INPUT_1_VOLUME:
685 case WM2200_AIF1TX5MIX_INPUT_2_SOURCE:
686 case WM2200_AIF1TX5MIX_INPUT_2_VOLUME:
687 case WM2200_AIF1TX5MIX_INPUT_3_SOURCE:
688 case WM2200_AIF1TX5MIX_INPUT_3_VOLUME:
689 case WM2200_AIF1TX5MIX_INPUT_4_SOURCE:
690 case WM2200_AIF1TX5MIX_INPUT_4_VOLUME:
691 case WM2200_AIF1TX6MIX_INPUT_1_SOURCE:
692 case WM2200_AIF1TX6MIX_INPUT_1_VOLUME:
693 case WM2200_AIF1TX6MIX_INPUT_2_SOURCE:
694 case WM2200_AIF1TX6MIX_INPUT_2_VOLUME:
695 case WM2200_AIF1TX6MIX_INPUT_3_SOURCE:
696 case WM2200_AIF1TX6MIX_INPUT_3_VOLUME:
697 case WM2200_AIF1TX6MIX_INPUT_4_SOURCE:
698 case WM2200_AIF1TX6MIX_INPUT_4_VOLUME:
699 case WM2200_EQLMIX_INPUT_1_SOURCE:
700 case WM2200_EQLMIX_INPUT_1_VOLUME:
701 case WM2200_EQLMIX_INPUT_2_SOURCE:
702 case WM2200_EQLMIX_INPUT_2_VOLUME:
703 case WM2200_EQLMIX_INPUT_3_SOURCE:
704 case WM2200_EQLMIX_INPUT_3_VOLUME:
705 case WM2200_EQLMIX_INPUT_4_SOURCE:
706 case WM2200_EQLMIX_INPUT_4_VOLUME:
707 case WM2200_EQRMIX_INPUT_1_SOURCE:
708 case WM2200_EQRMIX_INPUT_1_VOLUME:
709 case WM2200_EQRMIX_INPUT_2_SOURCE:
710 case WM2200_EQRMIX_INPUT_2_VOLUME:
711 case WM2200_EQRMIX_INPUT_3_SOURCE:
712 case WM2200_EQRMIX_INPUT_3_VOLUME:
713 case WM2200_EQRMIX_INPUT_4_SOURCE:
714 case WM2200_EQRMIX_INPUT_4_VOLUME:
715 case WM2200_LHPF1MIX_INPUT_1_SOURCE:
716 case WM2200_LHPF1MIX_INPUT_1_VOLUME:
717 case WM2200_LHPF1MIX_INPUT_2_SOURCE:
718 case WM2200_LHPF1MIX_INPUT_2_VOLUME:
719 case WM2200_LHPF1MIX_INPUT_3_SOURCE:
720 case WM2200_LHPF1MIX_INPUT_3_VOLUME:
721 case WM2200_LHPF1MIX_INPUT_4_SOURCE:
722 case WM2200_LHPF1MIX_INPUT_4_VOLUME:
723 case WM2200_LHPF2MIX_INPUT_1_SOURCE:
724 case WM2200_LHPF2MIX_INPUT_1_VOLUME:
725 case WM2200_LHPF2MIX_INPUT_2_SOURCE:
726 case WM2200_LHPF2MIX_INPUT_2_VOLUME:
727 case WM2200_LHPF2MIX_INPUT_3_SOURCE:
728 case WM2200_LHPF2MIX_INPUT_3_VOLUME:
729 case WM2200_LHPF2MIX_INPUT_4_SOURCE:
730 case WM2200_LHPF2MIX_INPUT_4_VOLUME:
731 case WM2200_DSP1LMIX_INPUT_1_SOURCE:
732 case WM2200_DSP1LMIX_INPUT_1_VOLUME:
733 case WM2200_DSP1LMIX_INPUT_2_SOURCE:
734 case WM2200_DSP1LMIX_INPUT_2_VOLUME:
735 case WM2200_DSP1LMIX_INPUT_3_SOURCE:
736 case WM2200_DSP1LMIX_INPUT_3_VOLUME:
737 case WM2200_DSP1LMIX_INPUT_4_SOURCE:
738 case WM2200_DSP1LMIX_INPUT_4_VOLUME:
739 case WM2200_DSP1RMIX_INPUT_1_SOURCE:
740 case WM2200_DSP1RMIX_INPUT_1_VOLUME:
741 case WM2200_DSP1RMIX_INPUT_2_SOURCE:
742 case WM2200_DSP1RMIX_INPUT_2_VOLUME:
743 case WM2200_DSP1RMIX_INPUT_3_SOURCE:
744 case WM2200_DSP1RMIX_INPUT_3_VOLUME:
745 case WM2200_DSP1RMIX_INPUT_4_SOURCE:
746 case WM2200_DSP1RMIX_INPUT_4_VOLUME:
747 case WM2200_DSP1AUX1MIX_INPUT_1_SOURCE:
748 case WM2200_DSP1AUX2MIX_INPUT_1_SOURCE:
749 case WM2200_DSP1AUX3MIX_INPUT_1_SOURCE:
750 case WM2200_DSP1AUX4MIX_INPUT_1_SOURCE:
751 case WM2200_DSP1AUX5MIX_INPUT_1_SOURCE:
752 case WM2200_DSP1AUX6MIX_INPUT_1_SOURCE:
753 case WM2200_DSP2LMIX_INPUT_1_SOURCE:
754 case WM2200_DSP2LMIX_INPUT_1_VOLUME:
755 case WM2200_DSP2LMIX_INPUT_2_SOURCE:
756 case WM2200_DSP2LMIX_INPUT_2_VOLUME:
757 case WM2200_DSP2LMIX_INPUT_3_SOURCE:
758 case WM2200_DSP2LMIX_INPUT_3_VOLUME:
759 case WM2200_DSP2LMIX_INPUT_4_SOURCE:
760 case WM2200_DSP2LMIX_INPUT_4_VOLUME:
761 case WM2200_DSP2RMIX_INPUT_1_SOURCE:
762 case WM2200_DSP2RMIX_INPUT_1_VOLUME:
763 case WM2200_DSP2RMIX_INPUT_2_SOURCE:
764 case WM2200_DSP2RMIX_INPUT_2_VOLUME:
765 case WM2200_DSP2RMIX_INPUT_3_SOURCE:
766 case WM2200_DSP2RMIX_INPUT_3_VOLUME:
767 case WM2200_DSP2RMIX_INPUT_4_SOURCE:
768 case WM2200_DSP2RMIX_INPUT_4_VOLUME:
769 case WM2200_DSP2AUX1MIX_INPUT_1_SOURCE:
770 case WM2200_DSP2AUX2MIX_INPUT_1_SOURCE:
771 case WM2200_DSP2AUX3MIX_INPUT_1_SOURCE:
772 case WM2200_DSP2AUX4MIX_INPUT_1_SOURCE:
773 case WM2200_DSP2AUX5MIX_INPUT_1_SOURCE:
774 case WM2200_DSP2AUX6MIX_INPUT_1_SOURCE:
775 case WM2200_GPIO_CTRL_1:
776 case WM2200_GPIO_CTRL_2:
777 case WM2200_GPIO_CTRL_3:
778 case WM2200_GPIO_CTRL_4:
779 case WM2200_ADPS1_IRQ0:
780 case WM2200_ADPS1_IRQ1:
781 case WM2200_MISC_PAD_CTRL_1:
782 case WM2200_INTERRUPT_STATUS_1:
783 case WM2200_INTERRUPT_STATUS_1_MASK:
784 case WM2200_INTERRUPT_STATUS_2:
785 case WM2200_INTERRUPT_RAW_STATUS_2:
786 case WM2200_INTERRUPT_STATUS_2_MASK:
787 case WM2200_INTERRUPT_CONTROL:
828 case WM2200_HPLPF1_1:
829 case WM2200_HPLPF1_2:
830 case WM2200_HPLPF2_1:
831 case WM2200_HPLPF2_2:
832 case WM2200_DSP1_CONTROL_1:
833 case WM2200_DSP1_CONTROL_2:
834 case WM2200_DSP1_CONTROL_3:
835 case WM2200_DSP1_CONTROL_4:
836 case WM2200_DSP1_CONTROL_5:
837 case WM2200_DSP1_CONTROL_6:
838 case WM2200_DSP1_CONTROL_7:
839 case WM2200_DSP1_CONTROL_8:
840 case WM2200_DSP1_CONTROL_9:
841 case WM2200_DSP1_CONTROL_10:
842 case WM2200_DSP1_CONTROL_11:
843 case WM2200_DSP1_CONTROL_12:
844 case WM2200_DSP1_CONTROL_13:
845 case WM2200_DSP1_CONTROL_14:
846 case WM2200_DSP1_CONTROL_15:
847 case WM2200_DSP1_CONTROL_16:
848 case WM2200_DSP1_CONTROL_17:
849 case WM2200_DSP1_CONTROL_18:
850 case WM2200_DSP1_CONTROL_19:
851 case WM2200_DSP1_CONTROL_20:
852 case WM2200_DSP1_CONTROL_21:
853 case WM2200_DSP1_CONTROL_22:
854 case WM2200_DSP1_CONTROL_23:
855 case WM2200_DSP1_CONTROL_24:
856 case WM2200_DSP1_CONTROL_25:
857 case WM2200_DSP1_CONTROL_26:
858 case WM2200_DSP1_CONTROL_27:
859 case WM2200_DSP1_CONTROL_28:
860 case WM2200_DSP1_CONTROL_29:
861 case WM2200_DSP1_CONTROL_30:
862 case WM2200_DSP1_CONTROL_31:
863 case WM2200_DSP2_CONTROL_1:
864 case WM2200_DSP2_CONTROL_2:
865 case WM2200_DSP2_CONTROL_3:
866 case WM2200_DSP2_CONTROL_4:
867 case WM2200_DSP2_CONTROL_5:
868 case WM2200_DSP2_CONTROL_6:
869 case WM2200_DSP2_CONTROL_7:
870 case WM2200_DSP2_CONTROL_8:
871 case WM2200_DSP2_CONTROL_9:
872 case WM2200_DSP2_CONTROL_10:
873 case WM2200_DSP2_CONTROL_11:
874 case WM2200_DSP2_CONTROL_12:
875 case WM2200_DSP2_CONTROL_13:
876 case WM2200_DSP2_CONTROL_14:
877 case WM2200_DSP2_CONTROL_15:
878 case WM2200_DSP2_CONTROL_16:
879 case WM2200_DSP2_CONTROL_17:
880 case WM2200_DSP2_CONTROL_18:
881 case WM2200_DSP2_CONTROL_19:
882 case WM2200_DSP2_CONTROL_20:
883 case WM2200_DSP2_CONTROL_21:
884 case WM2200_DSP2_CONTROL_22:
885 case WM2200_DSP2_CONTROL_23:
886 case WM2200_DSP2_CONTROL_24:
887 case WM2200_DSP2_CONTROL_25:
888 case WM2200_DSP2_CONTROL_26:
889 case WM2200_DSP2_CONTROL_27:
890 case WM2200_DSP2_CONTROL_28:
891 case WM2200_DSP2_CONTROL_29:
892 case WM2200_DSP2_CONTROL_30:
893 case WM2200_DSP2_CONTROL_31:
900 static const struct reg_sequence wm2200_reva_patch[] = {
985 static int wm2200_reset(struct wm2200_priv *wm2200)
987 if (wm2200->pdata.reset) {
988 gpio_set_value_cansleep(wm2200->pdata.reset, 0);
989 gpio_set_value_cansleep(wm2200->pdata.reset, 1);
993 return regmap_write(wm2200->regmap, WM2200_SOFTWARE_RESET,
998 static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
999 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
1000 static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
1002 static const char * const wm2200_mixer_texts[] = {
1036 static unsigned int wm2200_mixer_values[] = {
1070 #define WM2200_MIXER_CONTROLS(name, base) \
1071 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
1072 WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
1073 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
1074 WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
1075 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
1076 WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
1077 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
1078 WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
1080 #define WM2200_MUX_ENUM_DECL(name, reg) \
1081 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
1082 wm2200_mixer_texts, wm2200_mixer_values)
1084 #define WM2200_MUX_CTL_DECL(name) \
1085 const struct snd_kcontrol_new name##_mux = \
1086 SOC_DAPM_ENUM("Route", name##_enum)
1088 #define WM2200_MIXER_ENUMS(name, base_reg) \
1089 static WM2200_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
1090 static WM2200_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
1091 static WM2200_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
1092 static WM2200_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
1093 static WM2200_MUX_CTL_DECL(name##_in1); \
1094 static WM2200_MUX_CTL_DECL(name##_in2); \
1095 static WM2200_MUX_CTL_DECL(name##_in3); \
1096 static WM2200_MUX_CTL_DECL(name##_in4)
1098 #define WM2200_DSP_ENUMS(name, base_reg) \
1099 static WM2200_MUX_ENUM_DECL(name##_aux1_enum, base_reg); \
1100 static WM2200_MUX_ENUM_DECL(name##_aux2_enum, base_reg + 1); \
1101 static WM2200_MUX_ENUM_DECL(name##_aux3_enum, base_reg + 2); \
1102 static WM2200_MUX_ENUM_DECL(name##_aux4_enum, base_reg + 3); \
1103 static WM2200_MUX_ENUM_DECL(name##_aux5_enum, base_reg + 4); \
1104 static WM2200_MUX_ENUM_DECL(name##_aux6_enum, base_reg + 5); \
1105 static WM2200_MUX_CTL_DECL(name##_aux1); \
1106 static WM2200_MUX_CTL_DECL(name##_aux2); \
1107 static WM2200_MUX_CTL_DECL(name##_aux3); \
1108 static WM2200_MUX_CTL_DECL(name##_aux4); \
1109 static WM2200_MUX_CTL_DECL(name##_aux5); \
1110 static WM2200_MUX_CTL_DECL(name##_aux6);
1112 static const char *wm2200_rxanc_input_sel_texts[] = {
1113 "None", "IN1", "IN2", "IN3",
1116 static SOC_ENUM_SINGLE_DECL(wm2200_rxanc_input_sel,
1118 WM2200_IN_RXANC_SEL_SHIFT,
1119 wm2200_rxanc_input_sel_texts);
1121 static const struct snd_kcontrol_new wm2200_snd_controls[] = {
1122 SOC_SINGLE("IN1 High Performance Switch", WM2200_IN1L_CONTROL,
1123 WM2200_IN1_OSR_SHIFT, 1, 0),
1124 SOC_SINGLE("IN2 High Performance Switch", WM2200_IN2L_CONTROL,
1125 WM2200_IN2_OSR_SHIFT, 1, 0),
1126 SOC_SINGLE("IN3 High Performance Switch", WM2200_IN3L_CONTROL,
1127 WM2200_IN3_OSR_SHIFT, 1, 0),
1129 SOC_DOUBLE_R_TLV("IN1 Volume", WM2200_IN1L_CONTROL, WM2200_IN1R_CONTROL,
1130 WM2200_IN1L_PGA_VOL_SHIFT, 0x5f, 0, in_tlv),
1131 SOC_DOUBLE_R_TLV("IN2 Volume", WM2200_IN2L_CONTROL, WM2200_IN2R_CONTROL,
1132 WM2200_IN2L_PGA_VOL_SHIFT, 0x5f, 0, in_tlv),
1133 SOC_DOUBLE_R_TLV("IN3 Volume", WM2200_IN3L_CONTROL, WM2200_IN3R_CONTROL,
1134 WM2200_IN3L_PGA_VOL_SHIFT, 0x5f, 0, in_tlv),
1136 SOC_DOUBLE_R("IN1 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L,
1137 WM2200_ADC_DIGITAL_VOLUME_1R, WM2200_IN1L_MUTE_SHIFT, 1, 1),
1138 SOC_DOUBLE_R("IN2 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_2L,
1139 WM2200_ADC_DIGITAL_VOLUME_2R, WM2200_IN2L_MUTE_SHIFT, 1, 1),
1140 SOC_DOUBLE_R("IN3 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_3L,
1141 WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_MUTE_SHIFT, 1, 1),
1143 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_1L,
1144 WM2200_ADC_DIGITAL_VOLUME_1R, WM2200_IN1L_DIG_VOL_SHIFT,
1145 0xbf, 0, digital_tlv),
1146 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_2L,
1147 WM2200_ADC_DIGITAL_VOLUME_2R, WM2200_IN2L_DIG_VOL_SHIFT,
1148 0xbf, 0, digital_tlv),
1149 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_3L,
1150 WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_DIG_VOL_SHIFT,
1151 0xbf, 0, digital_tlv),
1153 SND_SOC_BYTES_MASK("EQL Coefficients", WM2200_EQL_1, 20, WM2200_EQL_ENA),
1154 SND_SOC_BYTES_MASK("EQR Coefficients", WM2200_EQR_1, 20, WM2200_EQR_ENA),
1156 SND_SOC_BYTES("LHPF1 Coefficeints", WM2200_HPLPF1_2, 1),
1157 SND_SOC_BYTES("LHPF2 Coefficeints", WM2200_HPLPF2_2, 1),
1159 SOC_SINGLE("OUT1 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_1L,
1160 WM2200_OUT1_OSR_SHIFT, 1, 0),
1161 SOC_SINGLE("OUT2 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_2L,
1162 WM2200_OUT2_OSR_SHIFT, 1, 0),
1164 SOC_DOUBLE_R("OUT1 Digital Switch", WM2200_DAC_DIGITAL_VOLUME_1L,
1165 WM2200_DAC_DIGITAL_VOLUME_1R, WM2200_OUT1L_MUTE_SHIFT, 1, 1),
1166 SOC_DOUBLE_R_TLV("OUT1 Digital Volume", WM2200_DAC_DIGITAL_VOLUME_1L,
1167 WM2200_DAC_DIGITAL_VOLUME_1R, WM2200_OUT1L_VOL_SHIFT, 0x9f, 0,
1169 SOC_DOUBLE_R_TLV("OUT1 Volume", WM2200_DAC_VOLUME_LIMIT_1L,
1170 WM2200_DAC_VOLUME_LIMIT_1R, WM2200_OUT1L_PGA_VOL_SHIFT,
1173 SOC_DOUBLE_R("OUT2 Digital Switch", WM2200_DAC_DIGITAL_VOLUME_2L,
1174 WM2200_DAC_DIGITAL_VOLUME_2R, WM2200_OUT2L_MUTE_SHIFT, 1, 1),
1175 SOC_DOUBLE_R_TLV("OUT2 Digital Volume", WM2200_DAC_DIGITAL_VOLUME_2L,
1176 WM2200_DAC_DIGITAL_VOLUME_2R, WM2200_OUT2L_VOL_SHIFT, 0x9f, 0,
1178 SOC_DOUBLE("OUT2 Switch", WM2200_PDM_1, WM2200_SPK1L_MUTE_SHIFT,
1179 WM2200_SPK1R_MUTE_SHIFT, 1, 1),
1180 SOC_ENUM("RxANC Src", wm2200_rxanc_input_sel),
1183 WM2200_MIXER_ENUMS(OUT1L, WM2200_OUT1LMIX_INPUT_1_SOURCE);
1184 WM2200_MIXER_ENUMS(OUT1R, WM2200_OUT1RMIX_INPUT_1_SOURCE);
1185 WM2200_MIXER_ENUMS(OUT2L, WM2200_OUT2LMIX_INPUT_1_SOURCE);
1186 WM2200_MIXER_ENUMS(OUT2R, WM2200_OUT2RMIX_INPUT_1_SOURCE);
1188 WM2200_MIXER_ENUMS(AIF1TX1, WM2200_AIF1TX1MIX_INPUT_1_SOURCE);
1189 WM2200_MIXER_ENUMS(AIF1TX2, WM2200_AIF1TX2MIX_INPUT_1_SOURCE);
1190 WM2200_MIXER_ENUMS(AIF1TX3, WM2200_AIF1TX3MIX_INPUT_1_SOURCE);
1191 WM2200_MIXER_ENUMS(AIF1TX4, WM2200_AIF1TX4MIX_INPUT_1_SOURCE);
1192 WM2200_MIXER_ENUMS(AIF1TX5, WM2200_AIF1TX5MIX_INPUT_1_SOURCE);
1193 WM2200_MIXER_ENUMS(AIF1TX6, WM2200_AIF1TX6MIX_INPUT_1_SOURCE);
1195 WM2200_MIXER_ENUMS(EQL, WM2200_EQLMIX_INPUT_1_SOURCE);
1196 WM2200_MIXER_ENUMS(EQR, WM2200_EQRMIX_INPUT_1_SOURCE);
1198 WM2200_MIXER_ENUMS(DSP1L, WM2200_DSP1LMIX_INPUT_1_SOURCE);
1199 WM2200_MIXER_ENUMS(DSP1R, WM2200_DSP1RMIX_INPUT_1_SOURCE);
1200 WM2200_MIXER_ENUMS(DSP2L, WM2200_DSP2LMIX_INPUT_1_SOURCE);
1201 WM2200_MIXER_ENUMS(DSP2R, WM2200_DSP2RMIX_INPUT_1_SOURCE);
1203 WM2200_DSP_ENUMS(DSP1, WM2200_DSP1AUX1MIX_INPUT_1_SOURCE);
1204 WM2200_DSP_ENUMS(DSP2, WM2200_DSP2AUX1MIX_INPUT_1_SOURCE);
1206 WM2200_MIXER_ENUMS(LHPF1, WM2200_LHPF1MIX_INPUT_1_SOURCE);
1207 WM2200_MIXER_ENUMS(LHPF2, WM2200_LHPF2MIX_INPUT_1_SOURCE);
1209 #define WM2200_MUX(name, ctrl) \
1210 SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
1212 #define WM2200_MIXER_WIDGETS(name, name_str) \
1213 WM2200_MUX(name_str " Input 1", &name##_in1_mux), \
1214 WM2200_MUX(name_str " Input 2", &name##_in2_mux), \
1215 WM2200_MUX(name_str " Input 3", &name##_in3_mux), \
1216 WM2200_MUX(name_str " Input 4", &name##_in4_mux), \
1217 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
1219 #define WM2200_DSP_WIDGETS(name, name_str) \
1220 WM2200_MIXER_WIDGETS(name##L, name_str "L"), \
1221 WM2200_MIXER_WIDGETS(name##R, name_str "R"), \
1222 WM2200_MUX(name_str " Aux 1", &name##_aux1_mux), \
1223 WM2200_MUX(name_str " Aux 2", &name##_aux2_mux), \
1224 WM2200_MUX(name_str " Aux 3", &name##_aux3_mux), \
1225 WM2200_MUX(name_str " Aux 4", &name##_aux4_mux), \
1226 WM2200_MUX(name_str " Aux 5", &name##_aux5_mux), \
1227 WM2200_MUX(name_str " Aux 6", &name##_aux6_mux)
1229 #define WM2200_MIXER_INPUT_ROUTES(name) \
1230 { name, "Tone Generator", "Tone Generator" }, \
1231 { name, "AEC Loopback", "AEC Loopback" }, \
1232 { name, "IN1L", "IN1L PGA" }, \
1233 { name, "IN1R", "IN1R PGA" }, \
1234 { name, "IN2L", "IN2L PGA" }, \
1235 { name, "IN2R", "IN2R PGA" }, \
1236 { name, "IN3L", "IN3L PGA" }, \
1237 { name, "IN3R", "IN3R PGA" }, \
1238 { name, "DSP1.1", "DSP1" }, \
1239 { name, "DSP1.2", "DSP1" }, \
1240 { name, "DSP1.3", "DSP1" }, \
1241 { name, "DSP1.4", "DSP1" }, \
1242 { name, "DSP1.5", "DSP1" }, \
1243 { name, "DSP1.6", "DSP1" }, \
1244 { name, "DSP2.1", "DSP2" }, \
1245 { name, "DSP2.2", "DSP2" }, \
1246 { name, "DSP2.3", "DSP2" }, \
1247 { name, "DSP2.4", "DSP2" }, \
1248 { name, "DSP2.5", "DSP2" }, \
1249 { name, "DSP2.6", "DSP2" }, \
1250 { name, "AIF1RX1", "AIF1RX1" }, \
1251 { name, "AIF1RX2", "AIF1RX2" }, \
1252 { name, "AIF1RX3", "AIF1RX3" }, \
1253 { name, "AIF1RX4", "AIF1RX4" }, \
1254 { name, "AIF1RX5", "AIF1RX5" }, \
1255 { name, "AIF1RX6", "AIF1RX6" }, \
1256 { name, "EQL", "EQL" }, \
1257 { name, "EQR", "EQR" }, \
1258 { name, "LHPF1", "LHPF1" }, \
1259 { name, "LHPF2", "LHPF2" }
1261 #define WM2200_MIXER_ROUTES(widget, name) \
1262 { widget, NULL, name " Mixer" }, \
1263 { name " Mixer", NULL, name " Input 1" }, \
1264 { name " Mixer", NULL, name " Input 2" }, \
1265 { name " Mixer", NULL, name " Input 3" }, \
1266 { name " Mixer", NULL, name " Input 4" }, \
1267 WM2200_MIXER_INPUT_ROUTES(name " Input 1"), \
1268 WM2200_MIXER_INPUT_ROUTES(name " Input 2"), \
1269 WM2200_MIXER_INPUT_ROUTES(name " Input 3"), \
1270 WM2200_MIXER_INPUT_ROUTES(name " Input 4")
1272 #define WM2200_DSP_AUX_ROUTES(name) \
1273 { name, NULL, name " Aux 1" }, \
1274 { name, NULL, name " Aux 2" }, \
1275 { name, NULL, name " Aux 3" }, \
1276 { name, NULL, name " Aux 4" }, \
1277 { name, NULL, name " Aux 5" }, \
1278 { name, NULL, name " Aux 6" }, \
1279 WM2200_MIXER_INPUT_ROUTES(name " Aux 1"), \
1280 WM2200_MIXER_INPUT_ROUTES(name " Aux 2"), \
1281 WM2200_MIXER_INPUT_ROUTES(name " Aux 3"), \
1282 WM2200_MIXER_INPUT_ROUTES(name " Aux 4"), \
1283 WM2200_MIXER_INPUT_ROUTES(name " Aux 5"), \
1284 WM2200_MIXER_INPUT_ROUTES(name " Aux 6")
1286 static const char *wm2200_aec_loopback_texts[] = {
1287 "OUT1L", "OUT1R", "OUT2L", "OUT2R",
1290 static SOC_ENUM_SINGLE_DECL(wm2200_aec_loopback,
1291 WM2200_DAC_AEC_CONTROL_1,
1292 WM2200_AEC_LOOPBACK_SRC_SHIFT,
1293 wm2200_aec_loopback_texts);
1295 static const struct snd_kcontrol_new wm2200_aec_loopback_mux =
1296 SOC_DAPM_ENUM("AEC Loopback", wm2200_aec_loopback);
1298 static const struct snd_soc_dapm_widget wm2200_dapm_widgets[] = {
1299 SND_SOC_DAPM_SUPPLY("SYSCLK", WM2200_CLOCKING_3, WM2200_SYSCLK_ENA_SHIFT, 0,
1301 SND_SOC_DAPM_SUPPLY("CP1", WM2200_DM_CHARGE_PUMP_1, WM2200_CPDM_ENA_SHIFT, 0,
1303 SND_SOC_DAPM_SUPPLY("CP2", WM2200_MIC_CHARGE_PUMP_1, WM2200_CPMIC_ENA_SHIFT, 0,
1305 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM2200_MIC_BIAS_CTRL_1, WM2200_MICB1_ENA_SHIFT,
1307 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM2200_MIC_BIAS_CTRL_2, WM2200_MICB2_ENA_SHIFT,
1309 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
1310 SND_SOC_DAPM_REGULATOR_SUPPLY("AVDD", 20, 0),
1312 SND_SOC_DAPM_INPUT("IN1L"),
1313 SND_SOC_DAPM_INPUT("IN1R"),
1314 SND_SOC_DAPM_INPUT("IN2L"),
1315 SND_SOC_DAPM_INPUT("IN2R"),
1316 SND_SOC_DAPM_INPUT("IN3L"),
1317 SND_SOC_DAPM_INPUT("IN3R"),
1319 SND_SOC_DAPM_SIGGEN("TONE"),
1320 SND_SOC_DAPM_PGA("Tone Generator", WM2200_TONE_GENERATOR_1,
1321 WM2200_TONE_ENA_SHIFT, 0, NULL, 0),
1323 SND_SOC_DAPM_PGA("IN1L PGA", WM2200_INPUT_ENABLES, WM2200_IN1L_ENA_SHIFT, 0,
1325 SND_SOC_DAPM_PGA("IN1R PGA", WM2200_INPUT_ENABLES, WM2200_IN1R_ENA_SHIFT, 0,
1327 SND_SOC_DAPM_PGA("IN2L PGA", WM2200_INPUT_ENABLES, WM2200_IN2L_ENA_SHIFT, 0,
1329 SND_SOC_DAPM_PGA("IN2R PGA", WM2200_INPUT_ENABLES, WM2200_IN2R_ENA_SHIFT, 0,
1331 SND_SOC_DAPM_PGA("IN3L PGA", WM2200_INPUT_ENABLES, WM2200_IN3L_ENA_SHIFT, 0,
1333 SND_SOC_DAPM_PGA("IN3R PGA", WM2200_INPUT_ENABLES, WM2200_IN3R_ENA_SHIFT, 0,
1336 SND_SOC_DAPM_AIF_IN("AIF1RX1", "Playback", 0,
1337 WM2200_AUDIO_IF_1_22, WM2200_AIF1RX1_ENA_SHIFT, 0),
1338 SND_SOC_DAPM_AIF_IN("AIF1RX2", "Playback", 1,
1339 WM2200_AUDIO_IF_1_22, WM2200_AIF1RX2_ENA_SHIFT, 0),
1340 SND_SOC_DAPM_AIF_IN("AIF1RX3", "Playback", 2,
1341 WM2200_AUDIO_IF_1_22, WM2200_AIF1RX3_ENA_SHIFT, 0),
1342 SND_SOC_DAPM_AIF_IN("AIF1RX4", "Playback", 3,
1343 WM2200_AUDIO_IF_1_22, WM2200_AIF1RX4_ENA_SHIFT, 0),
1344 SND_SOC_DAPM_AIF_IN("AIF1RX5", "Playback", 4,
1345 WM2200_AUDIO_IF_1_22, WM2200_AIF1RX5_ENA_SHIFT, 0),
1346 SND_SOC_DAPM_AIF_IN("AIF1RX6", "Playback", 5,
1347 WM2200_AUDIO_IF_1_22, WM2200_AIF1RX6_ENA_SHIFT, 0),
1349 SND_SOC_DAPM_PGA("EQL", WM2200_EQL_1, WM2200_EQL_ENA_SHIFT, 0, NULL, 0),
1350 SND_SOC_DAPM_PGA("EQR", WM2200_EQR_1, WM2200_EQR_ENA_SHIFT, 0, NULL, 0),
1352 SND_SOC_DAPM_PGA("LHPF1", WM2200_HPLPF1_1, WM2200_LHPF1_ENA_SHIFT, 0,
1354 SND_SOC_DAPM_PGA("LHPF2", WM2200_HPLPF2_1, WM2200_LHPF2_ENA_SHIFT, 0,
1357 WM_ADSP1("DSP1", 0),
1358 WM_ADSP1("DSP2", 1),
1360 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "Capture", 0,
1361 WM2200_AUDIO_IF_1_22, WM2200_AIF1TX1_ENA_SHIFT, 0),
1362 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "Capture", 1,
1363 WM2200_AUDIO_IF_1_22, WM2200_AIF1TX2_ENA_SHIFT, 0),
1364 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "Capture", 2,
1365 WM2200_AUDIO_IF_1_22, WM2200_AIF1TX3_ENA_SHIFT, 0),
1366 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "Capture", 3,
1367 WM2200_AUDIO_IF_1_22, WM2200_AIF1TX4_ENA_SHIFT, 0),
1368 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "Capture", 4,
1369 WM2200_AUDIO_IF_1_22, WM2200_AIF1TX5_ENA_SHIFT, 0),
1370 SND_SOC_DAPM_AIF_OUT("AIF1TX6", "Capture", 5,
1371 WM2200_AUDIO_IF_1_22, WM2200_AIF1TX6_ENA_SHIFT, 0),
1373 SND_SOC_DAPM_MUX("AEC Loopback", WM2200_DAC_AEC_CONTROL_1,
1374 WM2200_AEC_LOOPBACK_ENA_SHIFT, 0, &wm2200_aec_loopback_mux),
1376 SND_SOC_DAPM_PGA_S("OUT1L", 0, WM2200_OUTPUT_ENABLES,
1377 WM2200_OUT1L_ENA_SHIFT, 0, NULL, 0),
1378 SND_SOC_DAPM_PGA_S("OUT1R", 0, WM2200_OUTPUT_ENABLES,
1379 WM2200_OUT1R_ENA_SHIFT, 0, NULL, 0),
1381 SND_SOC_DAPM_PGA_S("EPD_LP", 1, WM2200_EAR_PIECE_CTRL_1,
1382 WM2200_EPD_LP_ENA_SHIFT, 0, NULL, 0),
1383 SND_SOC_DAPM_PGA_S("EPD_OUTP_LP", 1, WM2200_EAR_PIECE_CTRL_1,
1384 WM2200_EPD_OUTP_LP_ENA_SHIFT, 0, NULL, 0),
1385 SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_LP", 1, WM2200_EAR_PIECE_CTRL_1,
1386 WM2200_EPD_RMV_SHRT_LP_SHIFT, 0, NULL, 0),
1388 SND_SOC_DAPM_PGA_S("EPD_LN", 1, WM2200_EAR_PIECE_CTRL_1,
1389 WM2200_EPD_LN_ENA_SHIFT, 0, NULL, 0),
1390 SND_SOC_DAPM_PGA_S("EPD_OUTP_LN", 1, WM2200_EAR_PIECE_CTRL_1,
1391 WM2200_EPD_OUTP_LN_ENA_SHIFT, 0, NULL, 0),
1392 SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_LN", 1, WM2200_EAR_PIECE_CTRL_1,
1393 WM2200_EPD_RMV_SHRT_LN_SHIFT, 0, NULL, 0),
1395 SND_SOC_DAPM_PGA_S("EPD_RP", 1, WM2200_EAR_PIECE_CTRL_2,
1396 WM2200_EPD_RP_ENA_SHIFT, 0, NULL, 0),
1397 SND_SOC_DAPM_PGA_S("EPD_OUTP_RP", 1, WM2200_EAR_PIECE_CTRL_2,
1398 WM2200_EPD_OUTP_RP_ENA_SHIFT, 0, NULL, 0),
1399 SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_RP", 1, WM2200_EAR_PIECE_CTRL_2,
1400 WM2200_EPD_RMV_SHRT_RP_SHIFT, 0, NULL, 0),
1402 SND_SOC_DAPM_PGA_S("EPD_RN", 1, WM2200_EAR_PIECE_CTRL_2,
1403 WM2200_EPD_RN_ENA_SHIFT, 0, NULL, 0),
1404 SND_SOC_DAPM_PGA_S("EPD_OUTP_RN", 1, WM2200_EAR_PIECE_CTRL_2,
1405 WM2200_EPD_OUTP_RN_ENA_SHIFT, 0, NULL, 0),
1406 SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_RN", 1, WM2200_EAR_PIECE_CTRL_2,
1407 WM2200_EPD_RMV_SHRT_RN_SHIFT, 0, NULL, 0),
1409 SND_SOC_DAPM_PGA("OUT2L", WM2200_OUTPUT_ENABLES, WM2200_OUT2L_ENA_SHIFT,
1411 SND_SOC_DAPM_PGA("OUT2R", WM2200_OUTPUT_ENABLES, WM2200_OUT2R_ENA_SHIFT,
1414 SND_SOC_DAPM_OUTPUT("EPOUTLN"),
1415 SND_SOC_DAPM_OUTPUT("EPOUTLP"),
1416 SND_SOC_DAPM_OUTPUT("EPOUTRN"),
1417 SND_SOC_DAPM_OUTPUT("EPOUTRP"),
1418 SND_SOC_DAPM_OUTPUT("SPK"),
1420 WM2200_MIXER_WIDGETS(EQL, "EQL"),
1421 WM2200_MIXER_WIDGETS(EQR, "EQR"),
1423 WM2200_MIXER_WIDGETS(LHPF1, "LHPF1"),
1424 WM2200_MIXER_WIDGETS(LHPF2, "LHPF2"),
1426 WM2200_DSP_WIDGETS(DSP1, "DSP1"),
1427 WM2200_DSP_WIDGETS(DSP2, "DSP2"),
1429 WM2200_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1430 WM2200_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1431 WM2200_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1432 WM2200_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1433 WM2200_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1434 WM2200_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1436 WM2200_MIXER_WIDGETS(OUT1L, "OUT1L"),
1437 WM2200_MIXER_WIDGETS(OUT1R, "OUT1R"),
1438 WM2200_MIXER_WIDGETS(OUT2L, "OUT2L"),
1439 WM2200_MIXER_WIDGETS(OUT2R, "OUT2R"),
1442 static const struct snd_soc_dapm_route wm2200_dapm_routes[] = {
1443 /* Everything needs SYSCLK but only hook up things on the edge
1445 { "IN1L", NULL, "SYSCLK" },
1446 { "IN1R", NULL, "SYSCLK" },
1447 { "IN2L", NULL, "SYSCLK" },
1448 { "IN2R", NULL, "SYSCLK" },
1449 { "IN3L", NULL, "SYSCLK" },
1450 { "IN3R", NULL, "SYSCLK" },
1451 { "OUT1L", NULL, "SYSCLK" },
1452 { "OUT1R", NULL, "SYSCLK" },
1453 { "OUT2L", NULL, "SYSCLK" },
1454 { "OUT2R", NULL, "SYSCLK" },
1455 { "AIF1RX1", NULL, "SYSCLK" },
1456 { "AIF1RX2", NULL, "SYSCLK" },
1457 { "AIF1RX3", NULL, "SYSCLK" },
1458 { "AIF1RX4", NULL, "SYSCLK" },
1459 { "AIF1RX5", NULL, "SYSCLK" },
1460 { "AIF1RX6", NULL, "SYSCLK" },
1461 { "AIF1TX1", NULL, "SYSCLK" },
1462 { "AIF1TX2", NULL, "SYSCLK" },
1463 { "AIF1TX3", NULL, "SYSCLK" },
1464 { "AIF1TX4", NULL, "SYSCLK" },
1465 { "AIF1TX5", NULL, "SYSCLK" },
1466 { "AIF1TX6", NULL, "SYSCLK" },
1468 { "IN1L", NULL, "AVDD" },
1469 { "IN1R", NULL, "AVDD" },
1470 { "IN2L", NULL, "AVDD" },
1471 { "IN2R", NULL, "AVDD" },
1472 { "IN3L", NULL, "AVDD" },
1473 { "IN3R", NULL, "AVDD" },
1474 { "OUT1L", NULL, "AVDD" },
1475 { "OUT1R", NULL, "AVDD" },
1477 { "IN1L PGA", NULL, "IN1L" },
1478 { "IN1R PGA", NULL, "IN1R" },
1479 { "IN2L PGA", NULL, "IN2L" },
1480 { "IN2R PGA", NULL, "IN2R" },
1481 { "IN3L PGA", NULL, "IN3L" },
1482 { "IN3R PGA", NULL, "IN3R" },
1484 { "Tone Generator", NULL, "TONE" },
1486 { "CP2", NULL, "CPVDD" },
1487 { "MICBIAS1", NULL, "CP2" },
1488 { "MICBIAS2", NULL, "CP2" },
1490 { "CP1", NULL, "CPVDD" },
1491 { "EPD_LN", NULL, "CP1" },
1492 { "EPD_LP", NULL, "CP1" },
1493 { "EPD_RN", NULL, "CP1" },
1494 { "EPD_RP", NULL, "CP1" },
1496 { "EPD_LP", NULL, "OUT1L" },
1497 { "EPD_OUTP_LP", NULL, "EPD_LP" },
1498 { "EPD_RMV_SHRT_LP", NULL, "EPD_OUTP_LP" },
1499 { "EPOUTLP", NULL, "EPD_RMV_SHRT_LP" },
1501 { "EPD_LN", NULL, "OUT1L" },
1502 { "EPD_OUTP_LN", NULL, "EPD_LN" },
1503 { "EPD_RMV_SHRT_LN", NULL, "EPD_OUTP_LN" },
1504 { "EPOUTLN", NULL, "EPD_RMV_SHRT_LN" },
1506 { "EPD_RP", NULL, "OUT1R" },
1507 { "EPD_OUTP_RP", NULL, "EPD_RP" },
1508 { "EPD_RMV_SHRT_RP", NULL, "EPD_OUTP_RP" },
1509 { "EPOUTRP", NULL, "EPD_RMV_SHRT_RP" },
1511 { "EPD_RN", NULL, "OUT1R" },
1512 { "EPD_OUTP_RN", NULL, "EPD_RN" },
1513 { "EPD_RMV_SHRT_RN", NULL, "EPD_OUTP_RN" },
1514 { "EPOUTRN", NULL, "EPD_RMV_SHRT_RN" },
1516 { "SPK", NULL, "OUT2L" },
1517 { "SPK", NULL, "OUT2R" },
1519 { "AEC Loopback", "OUT1L", "OUT1L" },
1520 { "AEC Loopback", "OUT1R", "OUT1R" },
1521 { "AEC Loopback", "OUT2L", "OUT2L" },
1522 { "AEC Loopback", "OUT2R", "OUT2R" },
1524 WM2200_MIXER_ROUTES("DSP1", "DSP1L"),
1525 WM2200_MIXER_ROUTES("DSP1", "DSP1R"),
1526 WM2200_MIXER_ROUTES("DSP2", "DSP2L"),
1527 WM2200_MIXER_ROUTES("DSP2", "DSP2R"),
1529 WM2200_DSP_AUX_ROUTES("DSP1"),
1530 WM2200_DSP_AUX_ROUTES("DSP2"),
1532 WM2200_MIXER_ROUTES("OUT1L", "OUT1L"),
1533 WM2200_MIXER_ROUTES("OUT1R", "OUT1R"),
1534 WM2200_MIXER_ROUTES("OUT2L", "OUT2L"),
1535 WM2200_MIXER_ROUTES("OUT2R", "OUT2R"),
1537 WM2200_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1538 WM2200_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1539 WM2200_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1540 WM2200_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1541 WM2200_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1542 WM2200_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1544 WM2200_MIXER_ROUTES("EQL", "EQL"),
1545 WM2200_MIXER_ROUTES("EQR", "EQR"),
1547 WM2200_MIXER_ROUTES("LHPF1", "LHPF1"),
1548 WM2200_MIXER_ROUTES("LHPF2", "LHPF2"),
1551 static int wm2200_probe(struct snd_soc_codec *codec)
1553 struct wm2200_priv *wm2200 = dev_get_drvdata(codec->dev);
1556 wm2200->codec = codec;
1558 ret = snd_soc_add_codec_controls(codec, wm_adsp_fw_controls, 2);
1565 static int wm2200_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1567 struct snd_soc_codec *codec = dai->codec;
1568 int lrclk, bclk, fmt_val;
1573 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1574 case SND_SOC_DAIFMT_DSP_A:
1577 case SND_SOC_DAIFMT_I2S:
1581 dev_err(codec->dev, "Unsupported DAI format %d\n",
1582 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1586 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1587 case SND_SOC_DAIFMT_CBS_CFS:
1589 case SND_SOC_DAIFMT_CBS_CFM:
1590 lrclk |= WM2200_AIF1TX_LRCLK_MSTR;
1592 case SND_SOC_DAIFMT_CBM_CFS:
1593 bclk |= WM2200_AIF1_BCLK_MSTR;
1595 case SND_SOC_DAIFMT_CBM_CFM:
1596 lrclk |= WM2200_AIF1TX_LRCLK_MSTR;
1597 bclk |= WM2200_AIF1_BCLK_MSTR;
1600 dev_err(codec->dev, "Unsupported master mode %d\n",
1601 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1605 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1606 case SND_SOC_DAIFMT_NB_NF:
1608 case SND_SOC_DAIFMT_IB_IF:
1609 bclk |= WM2200_AIF1_BCLK_INV;
1610 lrclk |= WM2200_AIF1TX_LRCLK_INV;
1612 case SND_SOC_DAIFMT_IB_NF:
1613 bclk |= WM2200_AIF1_BCLK_INV;
1615 case SND_SOC_DAIFMT_NB_IF:
1616 lrclk |= WM2200_AIF1TX_LRCLK_INV;
1622 snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_1, WM2200_AIF1_BCLK_MSTR |
1623 WM2200_AIF1_BCLK_INV, bclk);
1624 snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_2,
1625 WM2200_AIF1TX_LRCLK_MSTR | WM2200_AIF1TX_LRCLK_INV,
1627 snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_3,
1628 WM2200_AIF1TX_LRCLK_MSTR | WM2200_AIF1TX_LRCLK_INV,
1630 snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_5,
1631 WM2200_AIF1_FMT_MASK, fmt_val);
1636 static int wm2200_sr_code[] = {
1663 #define WM2200_NUM_BCLK_RATES 12
1665 static int wm2200_bclk_rates_dat[WM2200_NUM_BCLK_RATES] = {
1680 static int wm2200_bclk_rates_cd[WM2200_NUM_BCLK_RATES] = {
1695 static int wm2200_hw_params(struct snd_pcm_substream *substream,
1696 struct snd_pcm_hw_params *params,
1697 struct snd_soc_dai *dai)
1699 struct snd_soc_codec *codec = dai->codec;
1700 struct wm2200_priv *wm2200 = snd_soc_codec_get_drvdata(codec);
1701 int i, bclk, lrclk, wl, fl, sr_code;
1704 /* Data sizes if not using TDM */
1705 wl = params_width(params);
1708 fl = snd_soc_params_to_frame_size(params);
1712 dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1715 /* Target BCLK rate */
1716 bclk = snd_soc_params_to_bclk(params);
1720 if (!wm2200->sysclk) {
1721 dev_err(codec->dev, "SYSCLK has no rate set\n");
1725 for (i = 0; i < ARRAY_SIZE(wm2200_sr_code); i++)
1726 if (wm2200_sr_code[i] == params_rate(params))
1728 if (i == ARRAY_SIZE(wm2200_sr_code)) {
1729 dev_err(codec->dev, "Unsupported sample rate: %dHz\n",
1730 params_rate(params));
1735 dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz SYSCLK\n",
1736 bclk, wm2200->sysclk);
1738 if (wm2200->sysclk % 4000)
1739 bclk_rates = wm2200_bclk_rates_cd;
1741 bclk_rates = wm2200_bclk_rates_dat;
1743 for (i = 0; i < WM2200_NUM_BCLK_RATES; i++)
1744 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1746 if (i == WM2200_NUM_BCLK_RATES) {
1748 "No valid BCLK for %dHz found from %dHz SYSCLK\n",
1749 bclk, wm2200->sysclk);
1754 dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1755 snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_1,
1756 WM2200_AIF1_BCLK_DIV_MASK, bclk);
1758 lrclk = bclk_rates[bclk] / params_rate(params);
1759 dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1760 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1761 dai->symmetric_rates)
1762 snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_7,
1763 WM2200_AIF1RX_BCPF_MASK, lrclk);
1765 snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_6,
1766 WM2200_AIF1TX_BCPF_MASK, lrclk);
1768 i = (wl << WM2200_AIF1TX_WL_SHIFT) | wl;
1769 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1770 snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_9,
1771 WM2200_AIF1RX_WL_MASK |
1772 WM2200_AIF1RX_SLOT_LEN_MASK, i);
1774 snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_8,
1775 WM2200_AIF1TX_WL_MASK |
1776 WM2200_AIF1TX_SLOT_LEN_MASK, i);
1778 snd_soc_update_bits(codec, WM2200_CLOCKING_4,
1779 WM2200_SAMPLE_RATE_1_MASK, sr_code);
1784 static const struct snd_soc_dai_ops wm2200_dai_ops = {
1785 .set_fmt = wm2200_set_fmt,
1786 .hw_params = wm2200_hw_params,
1789 static int wm2200_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1790 int source, unsigned int freq, int dir)
1792 struct wm2200_priv *wm2200 = snd_soc_codec_get_drvdata(codec);
1796 case WM2200_CLK_SYSCLK:
1800 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1805 case WM2200_CLKSRC_MCLK1:
1806 case WM2200_CLKSRC_MCLK2:
1807 case WM2200_CLKSRC_FLL:
1808 case WM2200_CLKSRC_BCLK1:
1811 dev_err(codec->dev, "Invalid source %d\n", source);
1821 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1825 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1829 snd_soc_update_bits(codec, WM2200_CLOCKING_3, WM2200_SYSCLK_FREQ_MASK |
1830 WM2200_SYSCLK_SRC_MASK,
1831 fval << WM2200_SYSCLK_FREQ_SHIFT | source);
1833 wm2200->sysclk = freq;
1853 { 0, 64000, 4, 16 },
1854 { 64000, 128000, 3, 8 },
1855 { 128000, 256000, 2, 4 },
1856 { 256000, 1000000, 1, 2 },
1857 { 1000000, 13500000, 0, 1 },
1860 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1863 unsigned int target;
1865 unsigned int fratio, gcd_fll;
1868 /* Fref must be <=13.5MHz */
1870 fll_div->fll_refclk_div = 0;
1871 while ((Fref / div) > 13500000) {
1873 fll_div->fll_refclk_div++;
1876 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1882 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1884 /* Apply the division for our remaining calculations */
1887 /* Fvco should be 90-100MHz; don't check the upper bound */
1889 while (Fout * div < 90000000) {
1892 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1897 target = Fout * div;
1898 fll_div->fll_outdiv = div - 1;
1900 pr_debug("FLL Fvco=%dHz\n", target);
1902 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1903 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1904 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1905 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1906 fratio = fll_fratios[i].ratio;
1910 if (i == ARRAY_SIZE(fll_fratios)) {
1911 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1915 fll_div->n = target / (fratio * Fref);
1917 if (target % Fref == 0) {
1919 fll_div->lambda = 0;
1921 gcd_fll = gcd(target, fratio * Fref);
1923 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1925 fll_div->lambda = (fratio * Fref) / gcd_fll;
1928 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1929 fll_div->n, fll_div->theta, fll_div->lambda);
1930 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1931 fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1932 fll_div->fll_refclk_div);
1937 static int wm2200_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1938 unsigned int Fref, unsigned int Fout)
1940 struct i2c_client *i2c = to_i2c_client(codec->dev);
1941 struct wm2200_priv *wm2200 = snd_soc_codec_get_drvdata(codec);
1942 struct _fll_div factors;
1943 int ret, i, timeout;
1944 unsigned long time_left;
1947 dev_dbg(codec->dev, "FLL disabled");
1949 if (wm2200->fll_fout)
1950 pm_runtime_put(codec->dev);
1952 wm2200->fll_fout = 0;
1953 snd_soc_update_bits(codec, WM2200_FLL_CONTROL_1,
1959 case WM2200_FLL_SRC_MCLK1:
1960 case WM2200_FLL_SRC_MCLK2:
1961 case WM2200_FLL_SRC_BCLK:
1964 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1968 ret = fll_factors(&factors, Fref, Fout);
1972 /* Disable the FLL while we reconfigure */
1973 snd_soc_update_bits(codec, WM2200_FLL_CONTROL_1, WM2200_FLL_ENA, 0);
1975 snd_soc_update_bits(codec, WM2200_FLL_CONTROL_2,
1976 WM2200_FLL_OUTDIV_MASK | WM2200_FLL_FRATIO_MASK,
1977 (factors.fll_outdiv << WM2200_FLL_OUTDIV_SHIFT) |
1978 factors.fll_fratio);
1979 if (factors.theta) {
1980 snd_soc_update_bits(codec, WM2200_FLL_CONTROL_3,
1981 WM2200_FLL_FRACN_ENA,
1982 WM2200_FLL_FRACN_ENA);
1983 snd_soc_update_bits(codec, WM2200_FLL_EFS_2,
1985 WM2200_FLL_EFS_ENA);
1987 snd_soc_update_bits(codec, WM2200_FLL_CONTROL_3,
1988 WM2200_FLL_FRACN_ENA, 0);
1989 snd_soc_update_bits(codec, WM2200_FLL_EFS_2,
1990 WM2200_FLL_EFS_ENA, 0);
1993 snd_soc_update_bits(codec, WM2200_FLL_CONTROL_4, WM2200_FLL_THETA_MASK,
1995 snd_soc_update_bits(codec, WM2200_FLL_CONTROL_6, WM2200_FLL_N_MASK,
1997 snd_soc_update_bits(codec, WM2200_FLL_CONTROL_7,
1998 WM2200_FLL_CLK_REF_DIV_MASK |
1999 WM2200_FLL_CLK_REF_SRC_MASK,
2000 (factors.fll_refclk_div
2001 << WM2200_FLL_CLK_REF_DIV_SHIFT) | source);
2002 snd_soc_update_bits(codec, WM2200_FLL_EFS_1,
2003 WM2200_FLL_LAMBDA_MASK, factors.lambda);
2005 /* Clear any pending completions */
2006 try_wait_for_completion(&wm2200->fll_lock);
2008 pm_runtime_get_sync(codec->dev);
2010 snd_soc_update_bits(codec, WM2200_FLL_CONTROL_1,
2011 WM2200_FLL_ENA, WM2200_FLL_ENA);
2018 snd_soc_update_bits(codec, WM2200_CLOCKING_3, WM2200_SYSCLK_ENA,
2021 /* Poll for the lock; will use the interrupt to exit quickly */
2022 for (i = 0; i < timeout; i++) {
2024 time_left = wait_for_completion_timeout(
2026 msecs_to_jiffies(25));
2033 ret = snd_soc_read(codec,
2034 WM2200_INTERRUPT_RAW_STATUS_2);
2037 "Failed to read FLL status: %d\n",
2041 if (ret & WM2200_FLL_LOCK_STS)
2045 dev_err(codec->dev, "FLL lock timed out\n");
2046 pm_runtime_put(codec->dev);
2050 wm2200->fll_src = source;
2051 wm2200->fll_fref = Fref;
2052 wm2200->fll_fout = Fout;
2054 dev_dbg(codec->dev, "FLL running %dHz->%dHz\n", Fref, Fout);
2059 static int wm2200_dai_probe(struct snd_soc_dai *dai)
2061 struct snd_soc_codec *codec = dai->codec;
2062 unsigned int val = 0;
2065 ret = snd_soc_read(codec, WM2200_GPIO_CTRL_1);
2067 if ((ret & WM2200_GP1_FN_MASK) != 0) {
2068 dai->symmetric_rates = true;
2069 val = WM2200_AIF1TX_LRCLK_SRC;
2072 dev_err(codec->dev, "Failed to read GPIO 1 config: %d\n", ret);
2075 snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_2,
2076 WM2200_AIF1TX_LRCLK_SRC, val);
2081 #define WM2200_RATES SNDRV_PCM_RATE_8000_48000
2083 #define WM2200_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2084 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2086 static struct snd_soc_dai_driver wm2200_dai = {
2088 .probe = wm2200_dai_probe,
2090 .stream_name = "Playback",
2093 .rates = WM2200_RATES,
2094 .formats = WM2200_FORMATS,
2097 .stream_name = "Capture",
2100 .rates = WM2200_RATES,
2101 .formats = WM2200_FORMATS,
2103 .ops = &wm2200_dai_ops,
2106 static const struct snd_soc_codec_driver soc_codec_wm2200 = {
2107 .probe = wm2200_probe,
2109 .idle_bias_off = true,
2110 .ignore_pmdown_time = true,
2111 .set_sysclk = wm2200_set_sysclk,
2112 .set_pll = wm2200_set_fll,
2114 .component_driver = {
2115 .controls = wm2200_snd_controls,
2116 .num_controls = ARRAY_SIZE(wm2200_snd_controls),
2117 .dapm_widgets = wm2200_dapm_widgets,
2118 .num_dapm_widgets = ARRAY_SIZE(wm2200_dapm_widgets),
2119 .dapm_routes = wm2200_dapm_routes,
2120 .num_dapm_routes = ARRAY_SIZE(wm2200_dapm_routes),
2124 static irqreturn_t wm2200_irq(int irq, void *data)
2126 struct wm2200_priv *wm2200 = data;
2127 unsigned int val, mask;
2130 ret = regmap_read(wm2200->regmap, WM2200_INTERRUPT_STATUS_2, &val);
2132 dev_err(wm2200->dev, "Failed to read IRQ status: %d\n", ret);
2136 ret = regmap_read(wm2200->regmap, WM2200_INTERRUPT_STATUS_2_MASK,
2139 dev_warn(wm2200->dev, "Failed to read IRQ mask: %d\n", ret);
2145 if (val & WM2200_FLL_LOCK_EINT) {
2146 dev_dbg(wm2200->dev, "FLL locked\n");
2147 complete(&wm2200->fll_lock);
2151 regmap_write(wm2200->regmap, WM2200_INTERRUPT_STATUS_2, val);
2159 static const struct regmap_config wm2200_regmap = {
2163 .max_register = WM2200_MAX_REGISTER + (ARRAY_SIZE(wm2200_ranges) *
2164 WM2200_DSP_SPACING),
2165 .reg_defaults = wm2200_reg_defaults,
2166 .num_reg_defaults = ARRAY_SIZE(wm2200_reg_defaults),
2167 .volatile_reg = wm2200_volatile_register,
2168 .readable_reg = wm2200_readable_register,
2169 .cache_type = REGCACHE_RBTREE,
2170 .ranges = wm2200_ranges,
2171 .num_ranges = ARRAY_SIZE(wm2200_ranges),
2174 static const unsigned int wm2200_dig_vu[] = {
2175 WM2200_DAC_DIGITAL_VOLUME_1L,
2176 WM2200_DAC_DIGITAL_VOLUME_1R,
2177 WM2200_DAC_DIGITAL_VOLUME_2L,
2178 WM2200_DAC_DIGITAL_VOLUME_2R,
2179 WM2200_ADC_DIGITAL_VOLUME_1L,
2180 WM2200_ADC_DIGITAL_VOLUME_1R,
2181 WM2200_ADC_DIGITAL_VOLUME_2L,
2182 WM2200_ADC_DIGITAL_VOLUME_2R,
2183 WM2200_ADC_DIGITAL_VOLUME_3L,
2184 WM2200_ADC_DIGITAL_VOLUME_3R,
2187 static const unsigned int wm2200_mic_ctrl_reg[] = {
2188 WM2200_IN1L_CONTROL,
2189 WM2200_IN2L_CONTROL,
2190 WM2200_IN3L_CONTROL,
2193 static int wm2200_i2c_probe(struct i2c_client *i2c,
2194 const struct i2c_device_id *id)
2196 struct wm2200_pdata *pdata = dev_get_platdata(&i2c->dev);
2197 struct wm2200_priv *wm2200;
2202 wm2200 = devm_kzalloc(&i2c->dev, sizeof(struct wm2200_priv),
2207 wm2200->dev = &i2c->dev;
2208 init_completion(&wm2200->fll_lock);
2210 wm2200->regmap = devm_regmap_init_i2c(i2c, &wm2200_regmap);
2211 if (IS_ERR(wm2200->regmap)) {
2212 ret = PTR_ERR(wm2200->regmap);
2213 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2218 for (i = 0; i < 2; i++) {
2219 wm2200->dsp[i].type = WMFW_ADSP1;
2220 wm2200->dsp[i].part = "wm2200";
2221 wm2200->dsp[i].num = i + 1;
2222 wm2200->dsp[i].dev = &i2c->dev;
2223 wm2200->dsp[i].regmap = wm2200->regmap;
2224 wm2200->dsp[i].sysclk_reg = WM2200_CLOCKING_3;
2225 wm2200->dsp[i].sysclk_mask = WM2200_SYSCLK_FREQ_MASK;
2226 wm2200->dsp[i].sysclk_shift = WM2200_SYSCLK_FREQ_SHIFT;
2229 wm2200->dsp[0].base = WM2200_DSP1_CONTROL_1;
2230 wm2200->dsp[0].mem = wm2200_dsp1_regions;
2231 wm2200->dsp[0].num_mems = ARRAY_SIZE(wm2200_dsp1_regions);
2233 wm2200->dsp[1].base = WM2200_DSP2_CONTROL_1;
2234 wm2200->dsp[1].mem = wm2200_dsp2_regions;
2235 wm2200->dsp[1].num_mems = ARRAY_SIZE(wm2200_dsp2_regions);
2237 for (i = 0; i < ARRAY_SIZE(wm2200->dsp); i++)
2238 wm_adsp1_init(&wm2200->dsp[i]);
2241 wm2200->pdata = *pdata;
2243 i2c_set_clientdata(i2c, wm2200);
2245 for (i = 0; i < ARRAY_SIZE(wm2200->core_supplies); i++)
2246 wm2200->core_supplies[i].supply = wm2200_core_supply_names[i];
2248 ret = devm_regulator_bulk_get(&i2c->dev,
2249 ARRAY_SIZE(wm2200->core_supplies),
2250 wm2200->core_supplies);
2252 dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2257 ret = regulator_bulk_enable(ARRAY_SIZE(wm2200->core_supplies),
2258 wm2200->core_supplies);
2260 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2265 if (wm2200->pdata.ldo_ena) {
2266 ret = devm_gpio_request_one(&i2c->dev, wm2200->pdata.ldo_ena,
2267 GPIOF_OUT_INIT_HIGH,
2270 dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2271 wm2200->pdata.ldo_ena, ret);
2277 if (wm2200->pdata.reset) {
2278 ret = devm_gpio_request_one(&i2c->dev, wm2200->pdata.reset,
2279 GPIOF_OUT_INIT_HIGH,
2282 dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2283 wm2200->pdata.reset, ret);
2288 ret = regmap_read(wm2200->regmap, WM2200_SOFTWARE_RESET, ®);
2290 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2298 dev_err(&i2c->dev, "Device is not a WM2200, ID is %x\n", reg);
2303 ret = regmap_read(wm2200->regmap, WM2200_DEVICE_REVISION, ®);
2305 dev_err(&i2c->dev, "Failed to read revision register\n");
2309 wm2200->rev = reg & WM2200_DEVICE_REVISION_MASK;
2311 dev_info(&i2c->dev, "revision %c\n", wm2200->rev + 'A');
2313 switch (wm2200->rev) {
2316 ret = regmap_register_patch(wm2200->regmap, wm2200_reva_patch,
2317 ARRAY_SIZE(wm2200_reva_patch));
2319 dev_err(&i2c->dev, "Failed to register patch: %d\n",
2327 ret = wm2200_reset(wm2200);
2329 dev_err(&i2c->dev, "Failed to issue reset\n");
2333 for (i = 0; i < ARRAY_SIZE(wm2200->pdata.gpio_defaults); i++) {
2334 if (!wm2200->pdata.gpio_defaults[i])
2337 regmap_write(wm2200->regmap, WM2200_GPIO_CTRL_1 + i,
2338 wm2200->pdata.gpio_defaults[i]);
2341 for (i = 0; i < ARRAY_SIZE(wm2200_dig_vu); i++)
2342 regmap_update_bits(wm2200->regmap, wm2200_dig_vu[i],
2343 WM2200_OUT_VU, WM2200_OUT_VU);
2345 /* Assign slots 1-6 to channels 1-6 for both TX and RX */
2346 for (i = 0; i < 6; i++) {
2347 regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_10 + i, i);
2348 regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_16 + i, i);
2351 for (i = 0; i < WM2200_MAX_MICBIAS; i++) {
2352 if (!wm2200->pdata.micbias[i].mb_lvl &&
2353 !wm2200->pdata.micbias[i].bypass)
2356 /* Apply default for bypass mode */
2357 if (!wm2200->pdata.micbias[i].mb_lvl)
2358 wm2200->pdata.micbias[i].mb_lvl
2359 = WM2200_MBIAS_LVL_1V5;
2361 val = (wm2200->pdata.micbias[i].mb_lvl -1)
2362 << WM2200_MICB1_LVL_SHIFT;
2364 if (wm2200->pdata.micbias[i].discharge)
2365 val |= WM2200_MICB1_DISCH;
2367 if (wm2200->pdata.micbias[i].fast_start)
2368 val |= WM2200_MICB1_RATE;
2370 if (wm2200->pdata.micbias[i].bypass)
2371 val |= WM2200_MICB1_MODE;
2373 regmap_update_bits(wm2200->regmap,
2374 WM2200_MIC_BIAS_CTRL_1 + i,
2375 WM2200_MICB1_LVL_MASK |
2376 WM2200_MICB1_DISCH |
2378 WM2200_MICB1_RATE, val);
2381 for (i = 0; i < ARRAY_SIZE(wm2200->pdata.in_mode); i++) {
2382 regmap_update_bits(wm2200->regmap, wm2200_mic_ctrl_reg[i],
2383 WM2200_IN1_MODE_MASK |
2384 WM2200_IN1_DMIC_SUP_MASK,
2385 (wm2200->pdata.in_mode[i] <<
2386 WM2200_IN1_MODE_SHIFT) |
2387 (wm2200->pdata.dmic_sup[i] <<
2388 WM2200_IN1_DMIC_SUP_SHIFT));
2392 ret = request_threaded_irq(i2c->irq, NULL, wm2200_irq,
2393 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2396 regmap_update_bits(wm2200->regmap,
2397 WM2200_INTERRUPT_STATUS_2_MASK,
2398 WM2200_FLL_LOCK_EINT, 0);
2400 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2404 pm_runtime_set_active(&i2c->dev);
2405 pm_runtime_enable(&i2c->dev);
2406 pm_request_idle(&i2c->dev);
2408 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_wm2200,
2411 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
2412 goto err_pm_runtime;
2418 pm_runtime_disable(&i2c->dev);
2420 if (wm2200->pdata.reset)
2421 gpio_set_value_cansleep(wm2200->pdata.reset, 0);
2423 if (wm2200->pdata.ldo_ena)
2424 gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 0);
2426 regulator_bulk_disable(ARRAY_SIZE(wm2200->core_supplies),
2427 wm2200->core_supplies);
2431 static int wm2200_i2c_remove(struct i2c_client *i2c)
2433 struct wm2200_priv *wm2200 = i2c_get_clientdata(i2c);
2435 snd_soc_unregister_codec(&i2c->dev);
2437 free_irq(i2c->irq, wm2200);
2438 if (wm2200->pdata.reset)
2439 gpio_set_value_cansleep(wm2200->pdata.reset, 0);
2440 if (wm2200->pdata.ldo_ena)
2441 gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 0);
2447 static int wm2200_runtime_suspend(struct device *dev)
2449 struct wm2200_priv *wm2200 = dev_get_drvdata(dev);
2451 regcache_cache_only(wm2200->regmap, true);
2452 regcache_mark_dirty(wm2200->regmap);
2453 if (wm2200->pdata.ldo_ena)
2454 gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 0);
2455 regulator_bulk_disable(ARRAY_SIZE(wm2200->core_supplies),
2456 wm2200->core_supplies);
2461 static int wm2200_runtime_resume(struct device *dev)
2463 struct wm2200_priv *wm2200 = dev_get_drvdata(dev);
2466 ret = regulator_bulk_enable(ARRAY_SIZE(wm2200->core_supplies),
2467 wm2200->core_supplies);
2469 dev_err(dev, "Failed to enable supplies: %d\n",
2474 if (wm2200->pdata.ldo_ena) {
2475 gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 1);
2479 regcache_cache_only(wm2200->regmap, false);
2480 regcache_sync(wm2200->regmap);
2486 static const struct dev_pm_ops wm2200_pm = {
2487 SET_RUNTIME_PM_OPS(wm2200_runtime_suspend, wm2200_runtime_resume,
2491 static const struct i2c_device_id wm2200_i2c_id[] = {
2495 MODULE_DEVICE_TABLE(i2c, wm2200_i2c_id);
2497 static struct i2c_driver wm2200_i2c_driver = {
2502 .probe = wm2200_i2c_probe,
2503 .remove = wm2200_i2c_remove,
2504 .id_table = wm2200_i2c_id,
2507 module_i2c_driver(wm2200_i2c_driver);
2509 MODULE_DESCRIPTION("ASoC WM2200 driver");
2510 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2511 MODULE_LICENSE("GPL");
git.samba.org / sfrench / cifs-2.6.git / blob