2 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/acpi.h>
21 #include <linux/gpio.h>
22 #include <linux/of_gpio.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/mutex.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/jack.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <sound/rt5665.h>
38 #define RT5665_NUM_SUPPLIES 3
40 static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
47 struct snd_soc_codec *codec;
48 struct rt5665_platform_data pdata;
49 struct regmap *regmap;
50 struct gpio_desc *gpiod_ldo1_en;
51 struct gpio_desc *gpiod_reset;
52 struct snd_soc_jack *hs_jack;
53 struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
54 struct delayed_work jack_detect_work;
55 struct delayed_work calibrate_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
61 int lrck[RT5665_AIFS];
62 int bclk[RT5665_AIFS];
63 int master[RT5665_AIFS];
71 int irq_work_delay_time;
72 unsigned int sar_adc_value;
75 static const struct reg_default rt5665_reg[] = {
466 static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
470 case RT5665_EJD_CTRL_2:
471 case RT5665_GPIO_STA:
472 case RT5665_INT_ST_1:
473 case RT5665_IL_CMD_1:
474 case RT5665_4BTN_IL_CMD_1:
475 case RT5665_PSV_IL_CMD_1:
476 case RT5665_AJD1_CTRL:
477 case RT5665_JD_CTRL_3:
478 case RT5665_STO_NG2_CTRL_1:
479 case RT5665_SAR_IL_CMD_4:
480 case RT5665_DEVICE_ID:
481 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
482 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
483 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
484 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
491 static bool rt5665_readable_register(struct device *dev, unsigned int reg)
495 case RT5665_VENDOR_ID:
496 case RT5665_VENDOR_ID_1:
497 case RT5665_DEVICE_ID:
499 case RT5665_HP_CTRL_1:
500 case RT5665_HP_CTRL_2:
501 case RT5665_MONO_OUT:
502 case RT5665_HPL_GAIN:
503 case RT5665_HPR_GAIN:
504 case RT5665_MONO_GAIN:
505 case RT5665_CAL_BST_CTRL:
506 case RT5665_CBJ_BST_CTRL:
509 case RT5665_INL1_INR1_VOL:
510 case RT5665_EJD_CTRL_1:
511 case RT5665_EJD_CTRL_2:
512 case RT5665_EJD_CTRL_3:
513 case RT5665_EJD_CTRL_4:
514 case RT5665_EJD_CTRL_5:
515 case RT5665_EJD_CTRL_6:
516 case RT5665_EJD_CTRL_7:
517 case RT5665_DAC2_CTRL:
518 case RT5665_DAC2_DIG_VOL:
519 case RT5665_DAC1_DIG_VOL:
520 case RT5665_DAC3_DIG_VOL:
521 case RT5665_DAC3_CTRL:
522 case RT5665_STO1_ADC_DIG_VOL:
523 case RT5665_MONO_ADC_DIG_VOL:
524 case RT5665_STO2_ADC_DIG_VOL:
525 case RT5665_STO1_ADC_BOOST:
526 case RT5665_MONO_ADC_BOOST:
527 case RT5665_STO2_ADC_BOOST:
528 case RT5665_HP_IMP_GAIN_1:
529 case RT5665_HP_IMP_GAIN_2:
530 case RT5665_STO1_ADC_MIXER:
531 case RT5665_MONO_ADC_MIXER:
532 case RT5665_STO2_ADC_MIXER:
533 case RT5665_AD_DA_MIXER:
534 case RT5665_STO1_DAC_MIXER:
535 case RT5665_MONO_DAC_MIXER:
536 case RT5665_STO2_DAC_MIXER:
537 case RT5665_A_DAC1_MUX:
538 case RT5665_A_DAC2_MUX:
539 case RT5665_DIG_INF2_DATA:
540 case RT5665_DIG_INF3_DATA:
541 case RT5665_PDM_OUT_CTRL:
542 case RT5665_PDM_DATA_CTRL_1:
543 case RT5665_PDM_DATA_CTRL_2:
544 case RT5665_PDM_DATA_CTRL_3:
545 case RT5665_PDM_DATA_CTRL_4:
546 case RT5665_REC1_GAIN:
547 case RT5665_REC1_L1_MIXER:
548 case RT5665_REC1_L2_MIXER:
549 case RT5665_REC1_R1_MIXER:
550 case RT5665_REC1_R2_MIXER:
551 case RT5665_REC2_GAIN:
552 case RT5665_REC2_L1_MIXER:
553 case RT5665_REC2_L2_MIXER:
554 case RT5665_REC2_R1_MIXER:
555 case RT5665_REC2_R2_MIXER:
557 case RT5665_ALC_BACK_GAIN:
558 case RT5665_MONOMIX_GAIN:
559 case RT5665_MONOMIX_IN_GAIN:
560 case RT5665_OUT_L_GAIN:
561 case RT5665_OUT_L_MIXER:
562 case RT5665_OUT_R_GAIN:
563 case RT5665_OUT_R_MIXER:
564 case RT5665_LOUT_MIXER:
565 case RT5665_PWR_DIG_1:
566 case RT5665_PWR_DIG_2:
567 case RT5665_PWR_ANLG_1:
568 case RT5665_PWR_ANLG_2:
569 case RT5665_PWR_ANLG_3:
570 case RT5665_PWR_MIXER:
573 case RT5665_HPF_CTRL1:
574 case RT5665_DMIC_CTRL_1:
575 case RT5665_DMIC_CTRL_2:
576 case RT5665_I2S1_SDP:
577 case RT5665_I2S2_SDP:
578 case RT5665_I2S3_SDP:
579 case RT5665_ADDA_CLK_1:
580 case RT5665_ADDA_CLK_2:
581 case RT5665_I2S1_F_DIV_CTRL_1:
582 case RT5665_I2S1_F_DIV_CTRL_2:
583 case RT5665_TDM_CTRL_1:
584 case RT5665_TDM_CTRL_2:
585 case RT5665_TDM_CTRL_3:
586 case RT5665_TDM_CTRL_4:
587 case RT5665_TDM_CTRL_5:
588 case RT5665_TDM_CTRL_6:
589 case RT5665_TDM_CTRL_7:
590 case RT5665_TDM_CTRL_8:
592 case RT5665_PLL_CTRL_1:
593 case RT5665_PLL_CTRL_2:
606 case RT5665_HP_CHARGE_PUMP_1:
607 case RT5665_HP_CHARGE_PUMP_2:
608 case RT5665_MICBIAS_1:
609 case RT5665_MICBIAS_2:
613 case RT5665_RC_CLK_CTRL:
614 case RT5665_I2S_M_CLK_CTRL_1:
615 case RT5665_I2S2_F_DIV_CTRL_1:
616 case RT5665_I2S2_F_DIV_CTRL_2:
617 case RT5665_I2S3_F_DIV_CTRL_1:
618 case RT5665_I2S3_F_DIV_CTRL_2:
619 case RT5665_EQ_CTRL_1:
620 case RT5665_EQ_CTRL_2:
621 case RT5665_IRQ_CTRL_1:
622 case RT5665_IRQ_CTRL_2:
623 case RT5665_IRQ_CTRL_3:
624 case RT5665_IRQ_CTRL_4:
625 case RT5665_IRQ_CTRL_5:
626 case RT5665_IRQ_CTRL_6:
627 case RT5665_INT_ST_1:
628 case RT5665_GPIO_CTRL_1:
629 case RT5665_GPIO_CTRL_2:
630 case RT5665_GPIO_CTRL_3:
631 case RT5665_GPIO_CTRL_4:
632 case RT5665_GPIO_STA:
633 case RT5665_HP_AMP_DET_CTRL_1:
634 case RT5665_HP_AMP_DET_CTRL_2:
635 case RT5665_MID_HP_AMP_DET:
636 case RT5665_LOW_HP_AMP_DET:
637 case RT5665_SV_ZCD_1:
638 case RT5665_SV_ZCD_2:
639 case RT5665_IL_CMD_1:
640 case RT5665_IL_CMD_2:
641 case RT5665_IL_CMD_3:
642 case RT5665_IL_CMD_4:
643 case RT5665_4BTN_IL_CMD_1:
644 case RT5665_4BTN_IL_CMD_2:
645 case RT5665_4BTN_IL_CMD_3:
646 case RT5665_PSV_IL_CMD_1:
647 case RT5665_ADC_STO1_HP_CTRL_1:
648 case RT5665_ADC_STO1_HP_CTRL_2:
649 case RT5665_ADC_MONO_HP_CTRL_1:
650 case RT5665_ADC_MONO_HP_CTRL_2:
651 case RT5665_ADC_STO2_HP_CTRL_1:
652 case RT5665_ADC_STO2_HP_CTRL_2:
653 case RT5665_AJD1_CTRL:
656 case RT5665_JD_CTRL_1:
657 case RT5665_JD_CTRL_2:
658 case RT5665_JD_CTRL_3:
659 case RT5665_DIG_MISC:
662 case RT5665_DAC_ADC_DIG_VOL1:
663 case RT5665_DAC_ADC_DIG_VOL2:
664 case RT5665_BIAS_CUR_CTRL_1:
665 case RT5665_BIAS_CUR_CTRL_2:
666 case RT5665_BIAS_CUR_CTRL_3:
667 case RT5665_BIAS_CUR_CTRL_4:
668 case RT5665_BIAS_CUR_CTRL_5:
669 case RT5665_BIAS_CUR_CTRL_6:
670 case RT5665_BIAS_CUR_CTRL_7:
671 case RT5665_BIAS_CUR_CTRL_8:
672 case RT5665_BIAS_CUR_CTRL_9:
673 case RT5665_BIAS_CUR_CTRL_10:
674 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
675 case RT5665_CHARGE_PUMP_1:
676 case RT5665_DIG_IN_CTRL_1:
677 case RT5665_DIG_IN_CTRL_2:
678 case RT5665_PAD_DRIVING_CTRL:
679 case RT5665_SOFT_RAMP_DEPOP:
681 case RT5665_CHOP_DAC:
682 case RT5665_CHOP_ADC:
683 case RT5665_CALIB_ADC_CTRL:
684 case RT5665_VOL_TEST:
685 case RT5665_TEST_MODE_CTRL_1:
686 case RT5665_TEST_MODE_CTRL_2:
687 case RT5665_TEST_MODE_CTRL_3:
688 case RT5665_TEST_MODE_CTRL_4:
689 case RT5665_BASSBACK_CTRL:
690 case RT5665_STO_NG2_CTRL_1:
691 case RT5665_STO_NG2_CTRL_2:
692 case RT5665_STO_NG2_CTRL_3:
693 case RT5665_STO_NG2_CTRL_4:
694 case RT5665_STO_NG2_CTRL_5:
695 case RT5665_STO_NG2_CTRL_6:
696 case RT5665_STO_NG2_CTRL_7:
697 case RT5665_STO_NG2_CTRL_8:
698 case RT5665_MONO_NG2_CTRL_1:
699 case RT5665_MONO_NG2_CTRL_2:
700 case RT5665_MONO_NG2_CTRL_3:
701 case RT5665_MONO_NG2_CTRL_4:
702 case RT5665_MONO_NG2_CTRL_5:
703 case RT5665_MONO_NG2_CTRL_6:
704 case RT5665_STO1_DAC_SIL_DET:
705 case RT5665_MONOL_DAC_SIL_DET:
706 case RT5665_MONOR_DAC_SIL_DET:
707 case RT5665_STO2_DAC_SIL_DET:
708 case RT5665_SIL_PSV_CTRL1:
709 case RT5665_SIL_PSV_CTRL2:
710 case RT5665_SIL_PSV_CTRL3:
711 case RT5665_SIL_PSV_CTRL4:
712 case RT5665_SIL_PSV_CTRL5:
713 case RT5665_SIL_PSV_CTRL6:
714 case RT5665_MONO_AMP_CALIB_CTRL_1:
715 case RT5665_MONO_AMP_CALIB_CTRL_2:
716 case RT5665_MONO_AMP_CALIB_CTRL_3:
717 case RT5665_MONO_AMP_CALIB_CTRL_4:
718 case RT5665_MONO_AMP_CALIB_CTRL_5:
719 case RT5665_MONO_AMP_CALIB_CTRL_6:
720 case RT5665_MONO_AMP_CALIB_CTRL_7:
721 case RT5665_MONO_AMP_CALIB_STA1:
722 case RT5665_MONO_AMP_CALIB_STA2:
723 case RT5665_MONO_AMP_CALIB_STA3:
724 case RT5665_MONO_AMP_CALIB_STA4:
725 case RT5665_MONO_AMP_CALIB_STA6:
726 case RT5665_HP_IMP_SENS_CTRL_01:
727 case RT5665_HP_IMP_SENS_CTRL_02:
728 case RT5665_HP_IMP_SENS_CTRL_03:
729 case RT5665_HP_IMP_SENS_CTRL_04:
730 case RT5665_HP_IMP_SENS_CTRL_05:
731 case RT5665_HP_IMP_SENS_CTRL_06:
732 case RT5665_HP_IMP_SENS_CTRL_07:
733 case RT5665_HP_IMP_SENS_CTRL_08:
734 case RT5665_HP_IMP_SENS_CTRL_09:
735 case RT5665_HP_IMP_SENS_CTRL_10:
736 case RT5665_HP_IMP_SENS_CTRL_11:
737 case RT5665_HP_IMP_SENS_CTRL_12:
738 case RT5665_HP_IMP_SENS_CTRL_13:
739 case RT5665_HP_IMP_SENS_CTRL_14:
740 case RT5665_HP_IMP_SENS_CTRL_15:
741 case RT5665_HP_IMP_SENS_CTRL_16:
742 case RT5665_HP_IMP_SENS_CTRL_17:
743 case RT5665_HP_IMP_SENS_CTRL_18:
744 case RT5665_HP_IMP_SENS_CTRL_19:
745 case RT5665_HP_IMP_SENS_CTRL_20:
746 case RT5665_HP_IMP_SENS_CTRL_21:
747 case RT5665_HP_IMP_SENS_CTRL_22:
748 case RT5665_HP_IMP_SENS_CTRL_23:
749 case RT5665_HP_IMP_SENS_CTRL_24:
750 case RT5665_HP_IMP_SENS_CTRL_25:
751 case RT5665_HP_IMP_SENS_CTRL_26:
752 case RT5665_HP_IMP_SENS_CTRL_27:
753 case RT5665_HP_IMP_SENS_CTRL_28:
754 case RT5665_HP_IMP_SENS_CTRL_29:
755 case RT5665_HP_IMP_SENS_CTRL_30:
756 case RT5665_HP_IMP_SENS_CTRL_31:
757 case RT5665_HP_IMP_SENS_CTRL_32:
758 case RT5665_HP_IMP_SENS_CTRL_33:
759 case RT5665_HP_IMP_SENS_CTRL_34:
760 case RT5665_HP_LOGIC_CTRL_1:
761 case RT5665_HP_LOGIC_CTRL_2:
762 case RT5665_HP_LOGIC_CTRL_3:
763 case RT5665_HP_CALIB_CTRL_1:
764 case RT5665_HP_CALIB_CTRL_2:
765 case RT5665_HP_CALIB_CTRL_3:
766 case RT5665_HP_CALIB_CTRL_4:
767 case RT5665_HP_CALIB_CTRL_5:
768 case RT5665_HP_CALIB_CTRL_6:
769 case RT5665_HP_CALIB_CTRL_7:
770 case RT5665_HP_CALIB_CTRL_9:
771 case RT5665_HP_CALIB_CTRL_10:
772 case RT5665_HP_CALIB_CTRL_11:
773 case RT5665_HP_CALIB_STA_1:
774 case RT5665_HP_CALIB_STA_2:
775 case RT5665_HP_CALIB_STA_3:
776 case RT5665_HP_CALIB_STA_4:
777 case RT5665_HP_CALIB_STA_5:
778 case RT5665_HP_CALIB_STA_6:
779 case RT5665_HP_CALIB_STA_7:
780 case RT5665_HP_CALIB_STA_8:
781 case RT5665_HP_CALIB_STA_9:
782 case RT5665_HP_CALIB_STA_10:
783 case RT5665_HP_CALIB_STA_11:
784 case RT5665_PGM_TAB_CTRL1:
785 case RT5665_PGM_TAB_CTRL2:
786 case RT5665_PGM_TAB_CTRL3:
787 case RT5665_PGM_TAB_CTRL4:
788 case RT5665_PGM_TAB_CTRL5:
789 case RT5665_PGM_TAB_CTRL6:
790 case RT5665_PGM_TAB_CTRL7:
791 case RT5665_PGM_TAB_CTRL8:
792 case RT5665_PGM_TAB_CTRL9:
793 case RT5665_SAR_IL_CMD_1:
794 case RT5665_SAR_IL_CMD_2:
795 case RT5665_SAR_IL_CMD_3:
796 case RT5665_SAR_IL_CMD_4:
797 case RT5665_SAR_IL_CMD_5:
798 case RT5665_SAR_IL_CMD_6:
799 case RT5665_SAR_IL_CMD_7:
800 case RT5665_SAR_IL_CMD_8:
801 case RT5665_SAR_IL_CMD_9:
802 case RT5665_SAR_IL_CMD_10:
803 case RT5665_SAR_IL_CMD_11:
804 case RT5665_SAR_IL_CMD_12:
805 case RT5665_DRC1_CTRL_0:
806 case RT5665_DRC1_CTRL_1:
807 case RT5665_DRC1_CTRL_2:
808 case RT5665_DRC1_CTRL_3:
809 case RT5665_DRC1_CTRL_4:
810 case RT5665_DRC1_CTRL_5:
811 case RT5665_DRC1_CTRL_6:
812 case RT5665_DRC1_HARD_LMT_CTRL_1:
813 case RT5665_DRC1_HARD_LMT_CTRL_2:
814 case RT5665_DRC1_PRIV_1:
815 case RT5665_DRC1_PRIV_2:
816 case RT5665_DRC1_PRIV_3:
817 case RT5665_DRC1_PRIV_4:
818 case RT5665_DRC1_PRIV_5:
819 case RT5665_DRC1_PRIV_6:
820 case RT5665_DRC1_PRIV_7:
821 case RT5665_DRC1_PRIV_8:
822 case RT5665_ALC_PGA_CTRL_1:
823 case RT5665_ALC_PGA_CTRL_2:
824 case RT5665_ALC_PGA_CTRL_3:
825 case RT5665_ALC_PGA_CTRL_4:
826 case RT5665_ALC_PGA_CTRL_5:
827 case RT5665_ALC_PGA_CTRL_6:
828 case RT5665_ALC_PGA_CTRL_7:
829 case RT5665_ALC_PGA_CTRL_8:
830 case RT5665_ALC_PGA_STA_1:
831 case RT5665_ALC_PGA_STA_2:
832 case RT5665_ALC_PGA_STA_3:
833 case RT5665_EQ_AUTO_RCV_CTRL1:
834 case RT5665_EQ_AUTO_RCV_CTRL2:
835 case RT5665_EQ_AUTO_RCV_CTRL3:
836 case RT5665_EQ_AUTO_RCV_CTRL4:
837 case RT5665_EQ_AUTO_RCV_CTRL5:
838 case RT5665_EQ_AUTO_RCV_CTRL6:
839 case RT5665_EQ_AUTO_RCV_CTRL7:
840 case RT5665_EQ_AUTO_RCV_CTRL8:
841 case RT5665_EQ_AUTO_RCV_CTRL9:
842 case RT5665_EQ_AUTO_RCV_CTRL10:
843 case RT5665_EQ_AUTO_RCV_CTRL11:
844 case RT5665_EQ_AUTO_RCV_CTRL12:
845 case RT5665_EQ_AUTO_RCV_CTRL13:
846 case RT5665_ADC_L_EQ_LPF1_A1:
847 case RT5665_R_EQ_LPF1_A1:
848 case RT5665_L_EQ_LPF1_H0:
849 case RT5665_R_EQ_LPF1_H0:
850 case RT5665_L_EQ_BPF1_A1:
851 case RT5665_R_EQ_BPF1_A1:
852 case RT5665_L_EQ_BPF1_A2:
853 case RT5665_R_EQ_BPF1_A2:
854 case RT5665_L_EQ_BPF1_H0:
855 case RT5665_R_EQ_BPF1_H0:
856 case RT5665_L_EQ_BPF2_A1:
857 case RT5665_R_EQ_BPF2_A1:
858 case RT5665_L_EQ_BPF2_A2:
859 case RT5665_R_EQ_BPF2_A2:
860 case RT5665_L_EQ_BPF2_H0:
861 case RT5665_R_EQ_BPF2_H0:
862 case RT5665_L_EQ_BPF3_A1:
863 case RT5665_R_EQ_BPF3_A1:
864 case RT5665_L_EQ_BPF3_A2:
865 case RT5665_R_EQ_BPF3_A2:
866 case RT5665_L_EQ_BPF3_H0:
867 case RT5665_R_EQ_BPF3_H0:
868 case RT5665_L_EQ_BPF4_A1:
869 case RT5665_R_EQ_BPF4_A1:
870 case RT5665_L_EQ_BPF4_A2:
871 case RT5665_R_EQ_BPF4_A2:
872 case RT5665_L_EQ_BPF4_H0:
873 case RT5665_R_EQ_BPF4_H0:
874 case RT5665_L_EQ_HPF1_A1:
875 case RT5665_R_EQ_HPF1_A1:
876 case RT5665_L_EQ_HPF1_H0:
877 case RT5665_R_EQ_HPF1_H0:
878 case RT5665_L_EQ_PRE_VOL:
879 case RT5665_R_EQ_PRE_VOL:
880 case RT5665_L_EQ_POST_VOL:
881 case RT5665_R_EQ_POST_VOL:
882 case RT5665_SCAN_MODE_CTRL:
883 case RT5665_I2C_MODE:
890 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
891 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
892 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
893 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
894 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
895 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
896 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
897 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
899 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
900 static const DECLARE_TLV_DB_RANGE(bst_tlv,
901 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
902 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
903 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
904 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
905 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
906 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
907 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
910 /* Interface data select */
911 static const char * const rt5665_data_select[] = {
912 "L/R", "R/L", "L/L", "R/R"
915 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
916 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
918 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
919 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
921 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
922 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
924 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
925 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
927 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
928 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
930 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
931 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
933 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
934 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
936 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
937 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
939 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
940 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
942 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
943 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
945 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
946 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
948 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
949 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
951 static const SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
952 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
954 static const SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
955 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
957 static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
958 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
960 static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
961 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
963 static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
964 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
966 static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
967 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
969 static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
970 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
972 static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
973 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
975 static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
976 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
978 static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
979 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
981 static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
982 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
984 static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
985 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
987 static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
988 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
990 static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
991 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
993 static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
994 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
996 static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
997 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
999 static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1002 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1003 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1005 if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1006 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1007 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1008 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1009 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1015 static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1016 struct snd_ctl_elem_value *ucontrol)
1018 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1019 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1021 if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1022 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1023 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1024 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1025 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1032 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1033 * @codec: SoC audio codec device.
1034 * @filter_mask: mask of filters.
1035 * @clk_src: clock source
1037 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1038 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1039 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1040 * ASRC function will track i2s clock and generate a corresponding system clock
1041 * for codec. This function provides an API to select the clock source for a
1042 * set of filters specified by the mask. And the codec driver will turn on ASRC
1043 * for these filters if ASRC is selected as their clock source.
1045 int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1046 unsigned int filter_mask, unsigned int clk_src)
1048 unsigned int asrc2_mask = 0;
1049 unsigned int asrc2_value = 0;
1050 unsigned int asrc3_mask = 0;
1051 unsigned int asrc3_value = 0;
1054 case RT5665_CLK_SEL_SYS:
1055 case RT5665_CLK_SEL_I2S1_ASRC:
1056 case RT5665_CLK_SEL_I2S2_ASRC:
1057 case RT5665_CLK_SEL_I2S3_ASRC:
1058 case RT5665_CLK_SEL_SYS2:
1059 case RT5665_CLK_SEL_SYS3:
1060 case RT5665_CLK_SEL_SYS4:
1067 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1068 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1069 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1070 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1073 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1074 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1075 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1076 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1079 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1080 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1081 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1082 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1085 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1086 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1087 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1088 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1091 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1092 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1093 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1094 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1097 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1098 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1099 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1100 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1103 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1104 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1105 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1106 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1109 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1110 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1111 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1112 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1116 snd_soc_update_bits(codec, RT5665_ASRC_2,
1117 asrc2_mask, asrc2_value);
1120 snd_soc_update_bits(codec, RT5665_ASRC_3,
1121 asrc3_mask, asrc3_value);
1125 EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1127 static int rt5665_button_detect(struct snd_soc_codec *codec)
1131 val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
1132 btn_type = val & 0xfff0;
1133 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
1138 static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
1142 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x0003);
1143 snd_soc_update_bits(codec, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
1144 snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
1145 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1146 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1147 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1148 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1149 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1151 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1152 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1153 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1154 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1155 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1156 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1161 * rt5665_headset_detect - Detect headset.
1162 * @codec: SoC audio codec device.
1163 * @jack_insert: Jack insert or not.
1165 * Detect whether is headset or not when jack inserted.
1167 * Returns detect status.
1169 static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1171 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1172 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1173 unsigned int sar_hs_type, val;
1176 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1177 snd_soc_dapm_sync(dapm);
1179 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1182 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1184 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1187 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1189 usleep_range(10000, 15000);
1190 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1195 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1197 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1198 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1200 rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
1201 RT5665_SAR_IL_CMD_4) & 0x7ff;
1203 sar_hs_type = rt5665->pdata.sar_hs_type ?
1204 rt5665->pdata.sar_hs_type : 729;
1206 if (rt5665->sar_adc_value > sar_hs_type) {
1207 rt5665->jack_type = SND_JACK_HEADSET;
1208 rt5665_enable_push_button_irq(codec, true);
1210 rt5665->jack_type = SND_JACK_HEADPHONE;
1211 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1213 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1215 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1216 snd_soc_dapm_sync(dapm);
1219 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1220 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1221 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1222 snd_soc_dapm_sync(dapm);
1223 if (rt5665->jack_type == SND_JACK_HEADSET)
1224 rt5665_enable_push_button_irq(codec, false);
1225 rt5665->jack_type = 0;
1228 dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
1229 return rt5665->jack_type;
1232 static irqreturn_t rt5665_irq(int irq, void *data)
1234 struct rt5665_priv *rt5665 = data;
1236 mod_delayed_work(system_power_efficient_wq,
1237 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1242 static void rt5665_jd_check_handler(struct work_struct *work)
1244 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
1245 jd_check_work.work);
1247 if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
1249 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1251 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1253 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1254 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1256 schedule_delayed_work(&rt5665->jd_check_work, 500);
1260 int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1261 struct snd_soc_jack *hs_jack)
1263 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1265 switch (rt5665->pdata.jd_src) {
1267 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1268 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1269 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1271 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1272 RT5665_PWR_JD1, RT5665_PWR_JD1);
1273 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1276 case RT5665_JD_NULL:
1280 dev_warn(codec->dev, "Wrong JD source\n");
1284 rt5665->hs_jack = hs_jack;
1288 EXPORT_SYMBOL_GPL(rt5665_set_jack_detect);
1290 static void rt5665_jack_detect_handler(struct work_struct *work)
1292 struct rt5665_priv *rt5665 =
1293 container_of(work, struct rt5665_priv, jack_detect_work.work);
1296 while (!rt5665->codec) {
1297 pr_debug("%s codec = null\n", __func__);
1298 usleep_range(10000, 15000);
1301 while (!rt5665->codec->component.card->instantiated) {
1302 pr_debug("%s\n", __func__);
1303 usleep_range(10000, 15000);
1306 mutex_lock(&rt5665->calibrate_mutex);
1308 val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
1311 if (rt5665->jack_type == 0) {
1312 /* jack was out, report jack type */
1314 rt5665_headset_detect(rt5665->codec, 1);
1316 /* jack is already in, report button event */
1317 rt5665->jack_type = SND_JACK_HEADSET;
1318 btn_type = rt5665_button_detect(rt5665->codec);
1320 * rt5665 can report three kinds of button behavior,
1321 * one click, double click and hold. However,
1322 * currently we will report button pressed/released
1323 * event. So all the three button behaviors are
1324 * treated as button pressed.
1330 rt5665->jack_type |= SND_JACK_BTN_0;
1335 rt5665->jack_type |= SND_JACK_BTN_1;
1340 rt5665->jack_type |= SND_JACK_BTN_2;
1345 rt5665->jack_type |= SND_JACK_BTN_3;
1347 case 0x0000: /* unpressed */
1351 dev_err(rt5665->codec->dev,
1352 "Unexpected button code 0x%04x\n",
1359 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1362 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1364 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1365 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1367 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1368 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1369 schedule_delayed_work(&rt5665->jd_check_work, 0);
1371 cancel_delayed_work_sync(&rt5665->jd_check_work);
1373 mutex_unlock(&rt5665->calibrate_mutex);
1376 static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1377 /* Headphone Output Volume */
1378 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1379 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1380 rt5665_hp_vol_put, hp_vol_tlv),
1382 /* Mono Output Volume */
1383 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1384 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1385 rt5665_mono_vol_put, mono_vol_tlv),
1388 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1389 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1391 /* DAC Digital Volume */
1392 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1393 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1394 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1395 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1396 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1397 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1399 /* IN1/IN2/IN3/IN4 Volume */
1400 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1401 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1402 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1403 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1404 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1405 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1406 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1407 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1408 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1409 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1411 /* INL/INR Volume Control */
1412 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1413 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1415 /* ADC Digital Volume Control */
1416 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1417 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1418 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1419 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1420 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1421 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1422 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1423 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1424 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1425 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1426 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1427 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1429 /* ADC Boost Volume Control */
1430 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1431 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1434 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1435 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1438 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1439 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1444 * set_dmic_clk - Set parameter of dmic.
1447 * @kcontrol: The kcontrol of this widget.
1450 * Choose dmic clock between 1MHz and 3MHz.
1451 * It is better for clock to approximate 3MHz.
1453 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1454 struct snd_kcontrol *kcontrol, int event)
1456 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1457 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1458 int pd, idx = -EINVAL;
1460 pd = rl6231_get_pre_div(rt5665->regmap,
1461 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1462 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1465 dev_err(codec->dev, "Failed to set DMIC clock\n");
1467 snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
1468 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1473 static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1474 struct snd_kcontrol *kcontrol, int event)
1476 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1479 case SND_SOC_DAPM_PRE_PMU:
1480 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1481 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1482 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1484 case SND_SOC_DAPM_POST_PMD:
1485 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1486 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1487 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1496 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1497 struct snd_soc_dapm_widget *sink)
1500 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1502 val = snd_soc_read(codec, RT5665_GLB_CLK);
1503 val &= RT5665_SCLK_SRC_MASK;
1504 if (val == RT5665_SCLK_SRC_PLL1)
1510 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1511 struct snd_soc_dapm_widget *sink)
1513 unsigned int reg, shift, val;
1514 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1517 case RT5665_ADC_MONO_R_ASRC_SFT:
1518 reg = RT5665_ASRC_3;
1519 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1521 case RT5665_ADC_MONO_L_ASRC_SFT:
1522 reg = RT5665_ASRC_3;
1523 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1525 case RT5665_ADC_STO1_ASRC_SFT:
1526 reg = RT5665_ASRC_3;
1527 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1529 case RT5665_ADC_STO2_ASRC_SFT:
1530 reg = RT5665_ASRC_3;
1531 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1533 case RT5665_DAC_MONO_R_ASRC_SFT:
1534 reg = RT5665_ASRC_2;
1535 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1537 case RT5665_DAC_MONO_L_ASRC_SFT:
1538 reg = RT5665_ASRC_2;
1539 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1541 case RT5665_DAC_STO1_ASRC_SFT:
1542 reg = RT5665_ASRC_2;
1543 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1545 case RT5665_DAC_STO2_ASRC_SFT:
1546 reg = RT5665_ASRC_2;
1547 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1553 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1555 case RT5665_CLK_SEL_I2S1_ASRC:
1556 case RT5665_CLK_SEL_I2S2_ASRC:
1557 case RT5665_CLK_SEL_I2S3_ASRC:
1558 /* I2S_Pre_Div1 should be 1 in asrc mode */
1559 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
1560 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1569 static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1570 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1571 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1572 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1573 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1576 static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1577 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1578 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1579 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1580 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1583 static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1584 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1585 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1586 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1587 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1590 static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1591 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1592 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1593 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1594 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1597 static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1598 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1599 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1600 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1601 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1604 static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1605 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1606 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1607 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1608 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1611 static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1612 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1613 RT5665_M_ADCMIX_L_SFT, 1, 1),
1614 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1615 RT5665_M_DAC1_L_SFT, 1, 1),
1618 static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1619 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1620 RT5665_M_ADCMIX_R_SFT, 1, 1),
1621 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1622 RT5665_M_DAC1_R_SFT, 1, 1),
1625 static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1626 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1627 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1628 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1629 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1630 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1631 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1632 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1633 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1636 static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1637 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1638 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1639 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1640 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1641 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1642 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1643 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1644 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1647 static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1648 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1649 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1650 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1651 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1652 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1653 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1656 static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1657 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1658 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1659 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1660 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1661 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1662 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1665 static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1666 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1667 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1668 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1669 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1670 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1671 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1672 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1673 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1676 static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1677 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1678 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1679 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1680 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1681 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1682 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1683 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1684 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1687 /* Analog Input Mixer */
1688 static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1689 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1690 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1691 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1692 RT5665_M_INL_RM1_L_SFT, 1, 1),
1693 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1694 RT5665_M_INR_RM1_L_SFT, 1, 1),
1695 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1696 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1697 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1698 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1699 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1700 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1701 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1702 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1705 static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1706 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1707 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1708 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1709 RT5665_M_INR_RM1_R_SFT, 1, 1),
1710 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1711 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1712 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1713 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1714 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1715 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1716 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1717 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1720 static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1721 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1722 RT5665_M_INL_RM2_L_SFT, 1, 1),
1723 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1724 RT5665_M_INR_RM2_L_SFT, 1, 1),
1725 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1726 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1727 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1728 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1729 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1730 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1731 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1732 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1733 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1734 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1737 static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1738 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1739 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1740 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1741 RT5665_M_INL_RM2_R_SFT, 1, 1),
1742 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1743 RT5665_M_INR_RM2_R_SFT, 1, 1),
1744 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1745 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1746 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1747 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1748 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1749 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1750 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1751 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1754 static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1755 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1756 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1757 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1758 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1759 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1760 RT5665_M_BST1_MM_SFT, 1, 1),
1761 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1762 RT5665_M_BST2_MM_SFT, 1, 1),
1763 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1764 RT5665_M_BST3_MM_SFT, 1, 1),
1767 static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1768 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1769 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1770 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1771 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1772 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1773 RT5665_M_BST1_OM_L_SFT, 1, 1),
1774 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1775 RT5665_M_BST2_OM_L_SFT, 1, 1),
1776 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1777 RT5665_M_BST3_OM_L_SFT, 1, 1),
1780 static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1781 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1782 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1783 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1784 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1785 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1786 RT5665_M_BST2_OM_R_SFT, 1, 1),
1787 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1788 RT5665_M_BST3_OM_R_SFT, 1, 1),
1789 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1790 RT5665_M_BST4_OM_R_SFT, 1, 1),
1793 static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1794 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1795 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1796 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1797 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1800 static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1801 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1802 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1803 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1804 RT5665_M_OV_L_LM_SFT, 1, 1),
1807 static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1808 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1809 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1810 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1811 RT5665_M_OV_R_LM_SFT, 1, 1),
1815 /*MX-17 [6:4], MX-17 [2:0]*/
1816 static const char * const rt5665_dac2_src[] = {
1817 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1820 static const SOC_ENUM_SINGLE_DECL(
1821 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1822 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1824 static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1825 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1827 static const SOC_ENUM_SINGLE_DECL(
1828 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1829 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1831 static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1832 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1835 /*MX-1B [6:4], MX-1B [2:0]*/
1836 static const char * const rt5665_dac3_src[] = {
1837 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1840 static const SOC_ENUM_SINGLE_DECL(
1841 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1842 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1844 static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1845 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1847 static const SOC_ENUM_SINGLE_DECL(
1848 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1849 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1851 static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1852 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1854 /* STO1 ADC1 Source */
1855 /* MX-26 [13] [5] */
1856 static const char * const rt5665_sto1_adc1_src[] = {
1860 static const SOC_ENUM_SINGLE_DECL(
1861 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1862 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1864 static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1865 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1867 static const SOC_ENUM_SINGLE_DECL(
1868 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1869 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1871 static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1872 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1874 /* STO1 ADC Source */
1875 /* MX-26 [11:10] [3:2] */
1876 static const char * const rt5665_sto1_adc_src[] = {
1877 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1880 static const SOC_ENUM_SINGLE_DECL(
1881 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1882 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1884 static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1885 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1887 static const SOC_ENUM_SINGLE_DECL(
1888 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1889 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1891 static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1892 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1894 /* STO1 ADC2 Source */
1895 /* MX-26 [12] [4] */
1896 static const char * const rt5665_sto1_adc2_src[] = {
1900 static const SOC_ENUM_SINGLE_DECL(
1901 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1902 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1904 static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1905 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1907 static const SOC_ENUM_SINGLE_DECL(
1908 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1909 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1911 static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1912 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1914 /* STO1 DMIC Source */
1916 static const char * const rt5665_sto1_dmic_src[] = {
1920 static const SOC_ENUM_SINGLE_DECL(
1921 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1922 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1924 static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1925 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1928 static const char * const rt5665_sto1_dd_l_src[] = {
1929 "STO2 DAC", "MONO DAC"
1932 static const SOC_ENUM_SINGLE_DECL(
1933 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1934 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1936 static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1937 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1940 static const char * const rt5665_sto1_dd_r_src[] = {
1941 "STO2 DAC", "MONO DAC", "AEC REF"
1944 static const SOC_ENUM_SINGLE_DECL(
1945 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1946 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1948 static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1949 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1951 /* MONO ADC L2 Source */
1953 static const char * const rt5665_mono_adc_l2_src[] = {
1957 static const SOC_ENUM_SINGLE_DECL(
1958 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1959 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1961 static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1962 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1965 /* MONO ADC L1 Source */
1967 static const char * const rt5665_mono_adc_l1_src[] = {
1971 static const SOC_ENUM_SINGLE_DECL(
1972 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1973 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1975 static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1976 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1979 static const char * const rt5665_mono_dd_src[] = {
1980 "STO2 DAC", "MONO DAC"
1983 static const SOC_ENUM_SINGLE_DECL(
1984 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
1985 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
1987 static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
1988 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
1990 static const SOC_ENUM_SINGLE_DECL(
1991 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
1992 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
1994 static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
1995 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
1997 /* MONO ADC L Source, MONO ADC R Source*/
1998 /* MX-27 [11:10], MX-27 [3:2] */
1999 static const char * const rt5665_mono_adc_src[] = {
2000 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2003 static const SOC_ENUM_SINGLE_DECL(
2004 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2005 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2007 static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2008 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2010 static const SOC_ENUM_SINGLE_DECL(
2011 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2012 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2014 static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2015 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2017 /* MONO DMIC L Source */
2019 static const char * const rt5665_mono_dmic_l_src[] = {
2020 "DMIC1 L", "DMIC2 L"
2023 static const SOC_ENUM_SINGLE_DECL(
2024 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2025 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2027 static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2028 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2030 /* MONO ADC R2 Source */
2032 static const char * const rt5665_mono_adc_r2_src[] = {
2036 static const SOC_ENUM_SINGLE_DECL(
2037 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2038 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2040 static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2041 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2043 /* MONO ADC R1 Source */
2045 static const char * const rt5665_mono_adc_r1_src[] = {
2049 static const SOC_ENUM_SINGLE_DECL(
2050 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2051 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2053 static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2054 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2056 /* MONO DMIC R Source */
2058 static const char * const rt5665_mono_dmic_r_src[] = {
2059 "DMIC1 R", "DMIC2 R"
2062 static const SOC_ENUM_SINGLE_DECL(
2063 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2064 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2066 static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2067 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2070 /* STO2 ADC1 Source */
2071 /* MX-28 [13] [5] */
2072 static const char * const rt5665_sto2_adc1_src[] = {
2076 static const SOC_ENUM_SINGLE_DECL(
2077 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2078 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2080 static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2081 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2083 static const SOC_ENUM_SINGLE_DECL(
2084 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2085 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2087 static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2088 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2090 /* STO2 ADC Source */
2091 /* MX-28 [11:10] [3:2] */
2092 static const char * const rt5665_sto2_adc_src[] = {
2093 "ADC1 L", "ADC1 R", "ADC2 L"
2096 static const SOC_ENUM_SINGLE_DECL(
2097 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2098 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2100 static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2101 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2103 static const SOC_ENUM_SINGLE_DECL(
2104 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2105 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2107 static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2108 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2110 /* STO2 ADC2 Source */
2111 /* MX-28 [12] [4] */
2112 static const char * const rt5665_sto2_adc2_src[] = {
2116 static const SOC_ENUM_SINGLE_DECL(
2117 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2118 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2120 static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2121 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2123 static const SOC_ENUM_SINGLE_DECL(
2124 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2125 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2127 static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2128 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2130 /* STO2 DMIC Source */
2132 static const char * const rt5665_sto2_dmic_src[] = {
2136 static const SOC_ENUM_SINGLE_DECL(
2137 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2138 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2140 static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2141 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2144 static const char * const rt5665_sto2_dd_l_src[] = {
2145 "STO2 DAC", "MONO DAC"
2148 static const SOC_ENUM_SINGLE_DECL(
2149 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2150 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2152 static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2153 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2156 static const char * const rt5665_sto2_dd_r_src[] = {
2157 "STO2 DAC", "MONO DAC"
2160 static const SOC_ENUM_SINGLE_DECL(
2161 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2162 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2164 static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2165 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2167 /* DAC R1 Source, DAC L1 Source*/
2168 /* MX-29 [11:10], MX-29 [9:8]*/
2169 static const char * const rt5665_dac1_src[] = {
2170 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2173 static const SOC_ENUM_SINGLE_DECL(
2174 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2175 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2177 static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2178 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2180 static const SOC_ENUM_SINGLE_DECL(
2181 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2182 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2184 static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2185 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2187 /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2188 /* MX-2D [13:12], MX-2D [9:8]*/
2189 static const char * const rt5665_dig_dac_mix_src[] = {
2190 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2193 static const SOC_ENUM_SINGLE_DECL(
2194 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2195 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2197 static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2198 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2200 static const SOC_ENUM_SINGLE_DECL(
2201 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2202 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2204 static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2205 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2207 /* Analog DAC L1 Source, Analog DAC R1 Source*/
2208 /* MX-2D [5:4], MX-2D [1:0]*/
2209 static const char * const rt5665_alg_dac1_src[] = {
2210 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2213 static const SOC_ENUM_SINGLE_DECL(
2214 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2215 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2217 static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2218 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2220 static const SOC_ENUM_SINGLE_DECL(
2221 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2222 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2224 static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2225 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2227 /* Analog DAC LR Source, Analog DAC R2 Source*/
2228 /* MX-2E [5:4], MX-2E [0]*/
2229 static const char * const rt5665_alg_dac2_src[] = {
2230 "Mono DAC Mixer", "DAC2"
2233 static const SOC_ENUM_SINGLE_DECL(
2234 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2235 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2237 static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2238 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2240 static const SOC_ENUM_SINGLE_DECL(
2241 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2242 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2244 static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2245 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2247 /* Interface2 ADC Data Input*/
2249 static const char * const rt5665_if2_1_adc_in_src[] = {
2250 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2251 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2254 static const SOC_ENUM_SINGLE_DECL(
2255 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2256 RT5665_IF3_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2258 static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2259 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2262 static const char * const rt5665_if2_2_adc_in_src[] = {
2263 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2264 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2267 static const SOC_ENUM_SINGLE_DECL(
2268 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2269 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2271 static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2272 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2274 /* Interface3 ADC Data Input*/
2276 static const char * const rt5665_if3_adc_in_src[] = {
2277 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2278 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2281 static const SOC_ENUM_SINGLE_DECL(
2282 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2283 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2285 static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2286 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2289 /* MX-31 [11:10] [9:8] */
2290 static const char * const rt5665_pdm_src[] = {
2291 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2294 static const SOC_ENUM_SINGLE_DECL(
2295 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2296 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2298 static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2299 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2301 static const SOC_ENUM_SINGLE_DECL(
2302 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2303 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2305 static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2306 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2309 /* I2S1 TDM ADCDAT Source */
2311 static const char * const rt5665_if1_1_adc1_data_src[] = {
2312 "STO1 ADC", "IF2_1 DAC",
2315 static const SOC_ENUM_SINGLE_DECL(
2316 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2317 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2319 static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2320 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2323 static const char * const rt5665_if1_1_adc2_data_src[] = {
2324 "STO2 ADC", "IF2_2 DAC",
2327 static const SOC_ENUM_SINGLE_DECL(
2328 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2329 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2331 static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2332 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2335 static const char * const rt5665_if1_1_adc3_data_src[] = {
2336 "MONO ADC", "IF3 DAC",
2339 static const SOC_ENUM_SINGLE_DECL(
2340 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2341 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2343 static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2344 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2347 static const char * const rt5665_if1_2_adc1_data_src[] = {
2348 "STO1 ADC", "IF1 DAC",
2351 static const SOC_ENUM_SINGLE_DECL(
2352 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2353 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2355 static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2356 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2359 static const char * const rt5665_if1_2_adc2_data_src[] = {
2360 "STO2 ADC", "IF2_1 DAC",
2363 static const SOC_ENUM_SINGLE_DECL(
2364 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2365 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2367 static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2368 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2371 static const char * const rt5665_if1_2_adc3_data_src[] = {
2372 "MONO ADC", "IF2_2 DAC",
2375 static const SOC_ENUM_SINGLE_DECL(
2376 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2377 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2379 static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2380 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2383 static const char * const rt5665_if1_2_adc4_data_src[] = {
2387 static const SOC_ENUM_SINGLE_DECL(
2388 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2389 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2391 static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2392 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2394 /* MX-7a[4:0] MX-7b[4:0] */
2395 static const char * const rt5665_tdm_adc_data_src[] = {
2396 "1234", "1243", "1324", "1342", "1432", "1423",
2397 "2134", "2143", "2314", "2341", "2431", "2413",
2398 "3124", "3142", "3214", "3241", "3412", "3421",
2399 "4123", "4132", "4213", "4231", "4312", "4321"
2402 static const SOC_ENUM_SINGLE_DECL(
2403 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2404 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2406 static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2407 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2409 static const SOC_ENUM_SINGLE_DECL(
2410 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2411 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2413 static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2414 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2416 /* Out Volume Switch */
2417 static const struct snd_kcontrol_new monovol_switch =
2418 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2420 static const struct snd_kcontrol_new outvol_l_switch =
2421 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2423 static const struct snd_kcontrol_new outvol_r_switch =
2424 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2427 static const struct snd_kcontrol_new mono_switch =
2428 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2430 static const struct snd_kcontrol_new hpo_switch =
2431 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2432 RT5665_VOL_L_SFT, 1, 0);
2434 static const struct snd_kcontrol_new lout_l_switch =
2435 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2437 static const struct snd_kcontrol_new lout_r_switch =
2438 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2440 static const struct snd_kcontrol_new pdm_l_switch =
2441 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2442 RT5665_M_PDM1_L_SFT, 1, 1);
2444 static const struct snd_kcontrol_new pdm_r_switch =
2445 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2446 RT5665_M_PDM1_R_SFT, 1, 1);
2448 static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2449 struct snd_kcontrol *kcontrol, int event)
2451 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2454 case SND_SOC_DAPM_PRE_PMU:
2455 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2456 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2457 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2459 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
2460 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
2463 case SND_SOC_DAPM_POST_PMD:
2464 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
2465 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
2466 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2468 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2469 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2480 static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2481 struct snd_kcontrol *kcontrol, int event)
2483 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2486 case SND_SOC_DAPM_PRE_PMU:
2487 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2488 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2489 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2492 case SND_SOC_DAPM_POST_PMD:
2493 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2494 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2495 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2506 static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2507 struct snd_kcontrol *kcontrol, int event)
2509 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2512 case SND_SOC_DAPM_POST_PMU:
2513 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2514 RT5665_PUMP_EN, RT5665_PUMP_EN);
2517 case SND_SOC_DAPM_PRE_PMD:
2518 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2530 static int set_dmic_power(struct snd_soc_dapm_widget *w,
2531 struct snd_kcontrol *kcontrol, int event)
2534 case SND_SOC_DAPM_POST_PMU:
2535 /*Add delay to avoid pop noise*/
2546 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2547 struct snd_kcontrol *kcontrol, int event)
2549 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2552 case SND_SOC_DAPM_PRE_PMU:
2554 case RT5665_PWR_VREF1_BIT:
2555 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2559 case RT5665_PWR_VREF2_BIT:
2560 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2564 case RT5665_PWR_VREF3_BIT:
2565 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2574 case SND_SOC_DAPM_POST_PMU:
2575 usleep_range(15000, 20000);
2577 case RT5665_PWR_VREF1_BIT:
2578 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2579 RT5665_PWR_FV1, RT5665_PWR_FV1);
2582 case RT5665_PWR_VREF2_BIT:
2583 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2584 RT5665_PWR_FV2, RT5665_PWR_FV2);
2587 case RT5665_PWR_VREF3_BIT:
2588 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2589 RT5665_PWR_FV3, RT5665_PWR_FV3);
2605 static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2606 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2608 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2610 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2611 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2612 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2613 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2614 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2615 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2616 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2617 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2620 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2621 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2622 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2623 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2624 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2625 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2626 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2627 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2628 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2629 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2630 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2631 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2632 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2633 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2634 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2635 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2636 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2637 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2638 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2639 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2640 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2641 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2642 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2643 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2644 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2645 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2646 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2647 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2650 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2652 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2654 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2658 SND_SOC_DAPM_INPUT("DMIC L1"),
2659 SND_SOC_DAPM_INPUT("DMIC R1"),
2660 SND_SOC_DAPM_INPUT("DMIC L2"),
2661 SND_SOC_DAPM_INPUT("DMIC R2"),
2663 SND_SOC_DAPM_INPUT("IN1P"),
2664 SND_SOC_DAPM_INPUT("IN1N"),
2665 SND_SOC_DAPM_INPUT("IN2P"),
2666 SND_SOC_DAPM_INPUT("IN2N"),
2667 SND_SOC_DAPM_INPUT("IN3P"),
2668 SND_SOC_DAPM_INPUT("IN3N"),
2669 SND_SOC_DAPM_INPUT("IN4P"),
2670 SND_SOC_DAPM_INPUT("IN4N"),
2672 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2673 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2675 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2676 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2677 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2678 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2679 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2680 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2683 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2685 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2687 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2689 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2691 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2693 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2694 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2695 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2696 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2697 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2698 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2699 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2700 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2701 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2702 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2703 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2704 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2705 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2706 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2707 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2708 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2709 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2710 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2714 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2716 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2720 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2721 ARRAY_SIZE(rt5665_rec1_l_mix)),
2722 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2723 ARRAY_SIZE(rt5665_rec1_r_mix)),
2724 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2725 ARRAY_SIZE(rt5665_rec2_l_mix)),
2726 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2727 ARRAY_SIZE(rt5665_rec2_r_mix)),
2728 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2729 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2730 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2731 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2732 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2733 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2734 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2735 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2738 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2739 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2740 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2741 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2743 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2744 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2745 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2746 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2747 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2748 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2749 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2750 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2751 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2752 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2753 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2754 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2757 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2758 &rt5665_sto1_dmic_mux),
2759 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2760 &rt5665_sto1_dmic_mux),
2761 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2762 &rt5665_sto1_adc1l_mux),
2763 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2764 &rt5665_sto1_adc1r_mux),
2765 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2766 &rt5665_sto1_adc2l_mux),
2767 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2768 &rt5665_sto1_adc2r_mux),
2769 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2770 &rt5665_sto1_adcl_mux),
2771 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2772 &rt5665_sto1_adcr_mux),
2773 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2774 &rt5665_sto1_dd_l_mux),
2775 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2776 &rt5665_sto1_dd_r_mux),
2777 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2778 &rt5665_mono_adc_l2_mux),
2779 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2780 &rt5665_mono_adc_r2_mux),
2781 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2782 &rt5665_mono_adc_l1_mux),
2783 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2784 &rt5665_mono_adc_r1_mux),
2785 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2786 &rt5665_mono_dmic_l_mux),
2787 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2788 &rt5665_mono_dmic_r_mux),
2789 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2790 &rt5665_mono_adc_l_mux),
2791 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2792 &rt5665_mono_adc_r_mux),
2793 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2794 &rt5665_mono_dd_l_mux),
2795 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2796 &rt5665_mono_dd_r_mux),
2797 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2798 &rt5665_sto2_dmic_mux),
2799 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2800 &rt5665_sto2_dmic_mux),
2801 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2802 &rt5665_sto2_adc1l_mux),
2803 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2804 &rt5665_sto2_adc1r_mux),
2805 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2806 &rt5665_sto2_adc2l_mux),
2807 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2808 &rt5665_sto2_adc2r_mux),
2809 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2810 &rt5665_sto2_adcl_mux),
2811 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2812 &rt5665_sto2_adcr_mux),
2813 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2814 &rt5665_sto2_dd_l_mux),
2815 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2816 &rt5665_sto2_dd_r_mux),
2818 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2819 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2820 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2821 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2822 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2823 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2824 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2825 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2826 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2827 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2828 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2829 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2830 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2831 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2832 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2833 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2834 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2835 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2836 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2837 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2838 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2839 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2840 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2841 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2842 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2843 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2846 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 /* Digital Interface */
2851 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2853 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2855 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
2857 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
2859 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
2861 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2878 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 /* Digital Interface Select */
2886 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2887 &rt5665_if1_1_adc1_mux),
2888 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2889 &rt5665_if1_1_adc2_mux),
2890 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2891 &rt5665_if1_1_adc3_mux),
2892 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2893 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2894 &rt5665_if1_2_adc1_mux),
2895 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2896 &rt5665_if1_2_adc2_mux),
2897 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2898 &rt5665_if1_2_adc3_mux),
2899 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2900 &rt5665_if1_2_adc4_mux),
2901 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2902 &rt5665_tdm1_adc_mux),
2903 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2904 &rt5665_tdm1_adc_mux),
2905 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2906 &rt5665_tdm1_adc_mux),
2907 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2908 &rt5665_tdm1_adc_mux),
2909 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2910 &rt5665_tdm2_adc_mux),
2911 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2912 &rt5665_tdm2_adc_mux),
2913 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2914 &rt5665_tdm2_adc_mux),
2915 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2916 &rt5665_tdm2_adc_mux),
2917 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2918 &rt5665_if2_1_adc_in_mux),
2919 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2920 &rt5665_if2_2_adc_in_mux),
2921 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2922 &rt5665_if3_adc_in_mux),
2923 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2924 &rt5665_if1_1_01_adc_swap_mux),
2925 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2926 &rt5665_if1_1_01_adc_swap_mux),
2927 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2928 &rt5665_if1_1_23_adc_swap_mux),
2929 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2930 &rt5665_if1_1_23_adc_swap_mux),
2931 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2932 &rt5665_if1_1_45_adc_swap_mux),
2933 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2934 &rt5665_if1_1_45_adc_swap_mux),
2935 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2936 &rt5665_if1_1_67_adc_swap_mux),
2937 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2938 &rt5665_if1_1_67_adc_swap_mux),
2939 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2940 &rt5665_if1_2_01_adc_swap_mux),
2941 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2942 &rt5665_if1_2_01_adc_swap_mux),
2943 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2944 &rt5665_if1_2_23_adc_swap_mux),
2945 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2946 &rt5665_if1_2_23_adc_swap_mux),
2947 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2948 &rt5665_if1_2_45_adc_swap_mux),
2949 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2950 &rt5665_if1_2_45_adc_swap_mux),
2951 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2952 &rt5665_if1_2_67_adc_swap_mux),
2953 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2954 &rt5665_if1_2_67_adc_swap_mux),
2955 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2956 &rt5665_if2_1_dac_swap_mux),
2957 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2958 &rt5665_if2_1_adc_swap_mux),
2959 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5665_if2_2_dac_swap_mux),
2961 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5665_if2_2_adc_swap_mux),
2963 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5665_if3_dac_swap_mux),
2965 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5665_if3_adc_swap_mux),
2968 /* Audio Interface */
2969 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
2970 0, SND_SOC_NOPM, 0, 0),
2971 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
2972 1, SND_SOC_NOPM, 0, 0),
2973 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
2974 2, SND_SOC_NOPM, 0, 0),
2975 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
2976 3, SND_SOC_NOPM, 0, 0),
2977 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
2978 4, SND_SOC_NOPM, 0, 0),
2979 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
2980 5, SND_SOC_NOPM, 0, 0),
2981 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
2982 6, SND_SOC_NOPM, 0, 0),
2983 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
2984 7, SND_SOC_NOPM, 0, 0),
2985 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
2986 0, SND_SOC_NOPM, 0, 0),
2987 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
2988 1, SND_SOC_NOPM, 0, 0),
2989 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
2990 2, SND_SOC_NOPM, 0, 0),
2991 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
2992 3, SND_SOC_NOPM, 0, 0),
2993 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
2994 4, SND_SOC_NOPM, 0, 0),
2995 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
2996 5, SND_SOC_NOPM, 0, 0),
2997 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
2998 6, SND_SOC_NOPM, 0, 0),
2999 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
3000 7, SND_SOC_NOPM, 0, 0),
3001 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3002 0, SND_SOC_NOPM, 0, 0),
3003 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3004 0, SND_SOC_NOPM, 0, 0),
3005 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3006 0, SND_SOC_NOPM, 0, 0),
3007 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3008 0, SND_SOC_NOPM, 0, 0),
3009 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3010 0, SND_SOC_NOPM, 0, 0),
3011 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3012 0, SND_SOC_NOPM, 0, 0),
3013 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3014 0, SND_SOC_NOPM, 0, 0),
3017 /* DAC mixer before sound effect */
3018 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3019 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3020 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3021 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3023 /* DAC channel Mux */
3024 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3025 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3026 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3027 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3028 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3029 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3031 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3032 &rt5665_alg_dac_l1_mux),
3033 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3034 &rt5665_alg_dac_r1_mux),
3035 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3036 &rt5665_alg_dac_l2_mux),
3037 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3038 &rt5665_alg_dac_r2_mux),
3041 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3042 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3043 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3044 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3045 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3046 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3047 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3048 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3049 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3050 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3051 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3052 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3053 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3054 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3055 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3056 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3057 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3058 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3059 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3060 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3061 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3062 &rt5665_dig_dac_mixl_mux),
3063 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3064 &rt5665_dig_dac_mixr_mux),
3067 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3068 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3070 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3071 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3072 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3073 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3074 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3075 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3076 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3078 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3079 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3080 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3081 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3084 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3085 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3086 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3087 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3088 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3089 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3092 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3094 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3096 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3100 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3101 ARRAY_SIZE(rt5665_mono_mix)),
3102 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3103 ARRAY_SIZE(rt5665_lout_l_mix)),
3104 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3105 ARRAY_SIZE(rt5665_lout_r_mix)),
3106 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3107 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3108 SND_SOC_DAPM_PRE_PMU),
3109 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3110 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3111 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3112 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3113 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3114 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3116 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3117 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3118 SND_SOC_DAPM_POST_PMD),
3120 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3122 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3124 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3126 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3128 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3130 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3134 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3135 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3136 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3137 0, 1, &rt5665_pdm_l_mux),
3138 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3139 0, 1, &rt5665_pdm_r_mux),
3142 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3144 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3146 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3148 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3150 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3154 SND_SOC_DAPM_OUTPUT("HPOL"),
3155 SND_SOC_DAPM_OUTPUT("HPOR"),
3156 SND_SOC_DAPM_OUTPUT("LOUTL"),
3157 SND_SOC_DAPM_OUTPUT("LOUTR"),
3158 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3159 SND_SOC_DAPM_OUTPUT("PDML"),
3160 SND_SOC_DAPM_OUTPUT("PDMR"),
3163 static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3165 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3166 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3167 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3168 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3169 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3170 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3171 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3172 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3175 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3176 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3177 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3178 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3179 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3180 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3181 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3182 {"I2S1 ASRC", NULL, "CLKDET"},
3183 {"I2S2 ASRC", NULL, "CLKDET"},
3184 {"I2S3 ASRC", NULL, "CLKDET"},
3187 {"Mic Det Power", NULL, "Vref2"},
3188 {"MICBIAS1", NULL, "Vref1"},
3189 {"MICBIAS1", NULL, "Vref2"},
3190 {"MICBIAS2", NULL, "Vref1"},
3191 {"MICBIAS2", NULL, "Vref2"},
3192 {"MICBIAS3", NULL, "Vref1"},
3193 {"MICBIAS3", NULL, "Vref2"},
3195 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3196 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3197 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3198 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3199 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3200 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3202 {"I2S1_1", NULL, "I2S1 ASRC"},
3203 {"I2S1_2", NULL, "I2S1 ASRC"},
3204 {"I2S2_1", NULL, "I2S2 ASRC"},
3205 {"I2S2_2", NULL, "I2S2 ASRC"},
3206 {"I2S3", NULL, "I2S3 ASRC"},
3208 {"CLKDET SYS", NULL, "CLKDET"},
3209 {"CLKDET HP", NULL, "CLKDET"},
3210 {"CLKDET MONO", NULL, "CLKDET"},
3211 {"CLKDET LOUT", NULL, "CLKDET"},
3213 {"IN1P", NULL, "LDO2"},
3214 {"IN2P", NULL, "LDO2"},
3215 {"IN3P", NULL, "LDO2"},
3216 {"IN4P", NULL, "LDO2"},
3218 {"DMIC1", NULL, "DMIC L1"},
3219 {"DMIC1", NULL, "DMIC R1"},
3220 {"DMIC2", NULL, "DMIC L2"},
3221 {"DMIC2", NULL, "DMIC R2"},
3223 {"BST1", NULL, "IN1P"},
3224 {"BST1", NULL, "IN1N"},
3225 {"BST1", NULL, "BST1 Power"},
3226 {"BST1", NULL, "BST1P Power"},
3227 {"BST2", NULL, "IN2P"},
3228 {"BST2", NULL, "IN2N"},
3229 {"BST2", NULL, "BST2 Power"},
3230 {"BST2", NULL, "BST2P Power"},
3231 {"BST3", NULL, "IN3P"},
3232 {"BST3", NULL, "IN3N"},
3233 {"BST3", NULL, "BST3 Power"},
3234 {"BST3", NULL, "BST3P Power"},
3235 {"BST4", NULL, "IN4P"},
3236 {"BST4", NULL, "IN4N"},
3237 {"BST4", NULL, "BST4 Power"},
3238 {"BST4", NULL, "BST4P Power"},
3239 {"BST1 CBJ", NULL, "IN1P"},
3240 {"BST1 CBJ", NULL, "IN1N"},
3241 {"BST1 CBJ", NULL, "CBJ Power"},
3242 {"CBJ Power", NULL, "Vref2"},
3244 {"INL VOL", NULL, "IN3P"},
3245 {"INR VOL", NULL, "IN3N"},
3247 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3248 {"RECMIX1L", "INL Switch", "INL VOL"},
3249 {"RECMIX1L", "INR Switch", "INR VOL"},
3250 {"RECMIX1L", "BST4 Switch", "BST4"},
3251 {"RECMIX1L", "BST3 Switch", "BST3"},
3252 {"RECMIX1L", "BST2 Switch", "BST2"},
3253 {"RECMIX1L", "BST1 Switch", "BST1"},
3254 {"RECMIX1L", NULL, "RECMIX1L Power"},
3256 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3257 {"RECMIX1R", "INR Switch", "INR VOL"},
3258 {"RECMIX1R", "BST4 Switch", "BST4"},
3259 {"RECMIX1R", "BST3 Switch", "BST3"},
3260 {"RECMIX1R", "BST2 Switch", "BST2"},
3261 {"RECMIX1R", "BST1 Switch", "BST1"},
3262 {"RECMIX1R", NULL, "RECMIX1R Power"},
3264 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3265 {"RECMIX2L", "INL Switch", "INL VOL"},
3266 {"RECMIX2L", "INR Switch", "INR VOL"},
3267 {"RECMIX2L", "BST4 Switch", "BST4"},
3268 {"RECMIX2L", "BST3 Switch", "BST3"},
3269 {"RECMIX2L", "BST2 Switch", "BST2"},
3270 {"RECMIX2L", "BST1 Switch", "BST1"},
3271 {"RECMIX2L", NULL, "RECMIX2L Power"},
3273 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3274 {"RECMIX2R", "INL Switch", "INL VOL"},
3275 {"RECMIX2R", "INR Switch", "INR VOL"},
3276 {"RECMIX2R", "BST4 Switch", "BST4"},
3277 {"RECMIX2R", "BST3 Switch", "BST3"},
3278 {"RECMIX2R", "BST2 Switch", "BST2"},
3279 {"RECMIX2R", "BST1 Switch", "BST1"},
3280 {"RECMIX2R", NULL, "RECMIX2R Power"},
3282 {"ADC1 L", NULL, "RECMIX1L"},
3283 {"ADC1 L", NULL, "ADC1 L Power"},
3284 {"ADC1 L", NULL, "ADC1 clock"},
3285 {"ADC1 R", NULL, "RECMIX1R"},
3286 {"ADC1 R", NULL, "ADC1 R Power"},
3287 {"ADC1 R", NULL, "ADC1 clock"},
3289 {"ADC2 L", NULL, "RECMIX2L"},
3290 {"ADC2 L", NULL, "ADC2 L Power"},
3291 {"ADC2 L", NULL, "ADC2 clock"},
3292 {"ADC2 R", NULL, "RECMIX2R"},
3293 {"ADC2 R", NULL, "ADC2 R Power"},
3294 {"ADC2 R", NULL, "ADC2 clock"},
3296 {"DMIC L1", NULL, "DMIC CLK"},
3297 {"DMIC L1", NULL, "DMIC1 Power"},
3298 {"DMIC R1", NULL, "DMIC CLK"},
3299 {"DMIC R1", NULL, "DMIC1 Power"},
3300 {"DMIC L2", NULL, "DMIC CLK"},
3301 {"DMIC L2", NULL, "DMIC2 Power"},
3302 {"DMIC R2", NULL, "DMIC CLK"},
3303 {"DMIC R2", NULL, "DMIC2 Power"},
3305 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3306 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3308 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3309 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3311 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3312 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3314 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3315 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3317 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3318 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3320 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3321 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3323 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3324 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3325 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3326 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3327 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3328 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3329 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3330 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3332 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3333 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3335 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3336 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3338 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3339 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3340 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3341 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3343 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3344 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3345 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3346 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3348 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3349 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3350 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3351 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3353 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3354 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3355 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3356 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3358 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3359 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3361 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3362 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3364 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3365 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3366 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3367 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3369 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3370 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3371 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3372 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3374 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3375 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3376 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3377 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3378 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3379 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3381 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3382 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3384 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3385 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3387 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3388 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3389 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3390 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3392 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3393 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3394 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3395 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3397 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3398 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3399 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3401 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3402 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3403 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3405 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3406 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3407 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3409 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3410 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3411 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3413 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3414 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3415 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3417 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3418 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3419 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3421 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3422 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3423 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3424 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3425 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3426 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3428 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3429 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3430 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3431 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3432 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3433 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3434 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3436 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3437 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3438 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3439 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3440 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3441 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3442 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3443 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3445 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3446 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3447 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3448 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3449 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3450 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3451 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3452 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3453 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3454 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3455 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3456 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3457 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3458 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3459 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3460 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3461 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3462 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3463 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3464 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3465 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3466 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3467 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3468 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3469 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3471 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3472 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3473 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3474 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3475 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3476 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3477 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3478 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3479 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3480 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3481 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3482 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3483 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3484 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3485 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3486 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3487 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3488 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3489 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3490 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3491 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3492 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3493 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3494 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3495 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3497 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3498 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3499 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3500 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3501 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3502 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3503 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3504 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3505 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3506 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3507 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3508 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3509 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3510 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3511 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3512 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3513 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3514 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3515 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3516 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3517 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3518 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3519 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3520 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3521 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3523 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3524 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3525 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3526 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3527 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3528 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3529 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3530 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3531 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3532 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3533 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3534 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3535 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3536 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3537 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3538 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3539 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3540 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3541 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3542 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3543 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3544 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3545 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3546 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3547 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3550 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3551 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3552 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3553 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3554 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3555 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3556 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3557 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3558 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3559 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3560 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3561 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3562 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3563 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3564 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3565 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3566 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3567 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3568 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3569 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3570 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3571 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3572 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3573 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3574 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3576 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3577 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3578 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3579 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3580 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3581 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3582 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3583 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3584 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3585 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3586 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3587 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3588 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3589 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3590 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3591 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3592 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3593 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3594 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3595 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3596 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3597 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3598 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3599 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3600 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3602 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3603 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3604 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3605 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3606 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3607 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3608 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3609 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3610 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3611 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3612 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3613 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3614 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3615 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3616 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3617 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3618 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3619 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3620 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3621 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3622 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3623 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3624 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3625 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3626 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3628 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3629 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3630 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3631 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3632 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3633 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3634 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3635 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3636 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3637 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3638 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3639 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3640 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3641 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3642 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3643 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3644 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3645 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3646 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3647 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3648 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3649 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3650 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3651 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3652 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3654 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3655 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3656 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3657 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3658 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3659 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3660 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3661 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3662 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3663 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3664 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3665 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3666 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3667 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3668 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3669 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3670 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3671 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3672 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3673 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3674 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3675 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3676 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3677 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3678 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3679 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3680 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3681 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3682 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3683 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3684 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3685 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3687 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3688 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3689 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3690 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3691 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3692 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3693 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3694 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3695 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3696 {"IF2_1 ADC", NULL, "I2S2_1"},
3698 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3699 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3700 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3701 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3702 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3703 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3704 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3705 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3706 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3707 {"IF2_2 ADC", NULL, "I2S2_2"},
3709 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3710 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3711 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3712 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3713 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3714 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3715 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3716 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3717 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3718 {"IF3 ADC", NULL, "I2S3"},
3720 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3721 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3722 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3723 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3724 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3725 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3726 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3727 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3728 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3729 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3730 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3731 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3732 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3733 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3734 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3735 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3736 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3737 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3738 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3739 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3740 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3741 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3742 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3743 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3744 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3745 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3746 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3747 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3748 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3749 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3750 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3752 {"IF1 DAC1", NULL, "AIF1RX"},
3753 {"IF1 DAC2", NULL, "AIF1RX"},
3754 {"IF1 DAC3", NULL, "AIF1RX"},
3755 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3756 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3757 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3758 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3759 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3760 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3761 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3762 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3763 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3764 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3765 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3766 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3767 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3768 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3769 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3771 {"IF1 DAC1", NULL, "I2S1_1"},
3772 {"IF1 DAC2", NULL, "I2S1_1"},
3773 {"IF1 DAC3", NULL, "I2S1_1"},
3774 {"IF2_1 DAC", NULL, "I2S2_1"},
3775 {"IF2_2 DAC", NULL, "I2S2_2"},
3776 {"IF3 DAC", NULL, "I2S3"},
3778 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3779 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3780 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3781 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3782 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3783 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3784 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3785 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3786 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3787 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3788 {"IF3 DAC L", NULL, "IF3 DAC"},
3789 {"IF3 DAC R", NULL, "IF3 DAC"},
3791 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3792 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3793 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3794 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3795 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3797 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3798 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3799 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3800 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3801 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3803 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3804 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3805 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3806 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3808 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3809 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3811 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3812 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3813 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3814 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3815 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3816 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3818 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3819 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3820 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3821 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3822 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3823 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3825 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3826 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3827 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3828 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3829 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3830 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3832 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3833 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3834 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3835 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3836 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3837 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3839 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3840 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3841 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3842 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3844 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3845 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3846 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3847 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3849 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3850 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3851 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3853 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3854 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3855 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3857 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3858 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3859 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3860 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3861 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3862 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3863 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3864 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3866 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3867 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3868 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3869 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3870 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3871 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3873 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3874 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3875 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3876 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3877 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3878 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3880 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3881 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3882 {"DAC L2 Source", NULL, "DAC L2 Power"},
3883 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3884 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3885 {"DAC R2 Source", NULL, "DAC R2 Power"},
3887 {"DAC L1", NULL, "DAC L1 Source"},
3888 {"DAC R1", NULL, "DAC R1 Source"},
3889 {"DAC L2", NULL, "DAC L2 Source"},
3890 {"DAC R2", NULL, "DAC R2 Source"},
3892 {"DAC L1", NULL, "DAC 1 Clock"},
3893 {"DAC R1", NULL, "DAC 1 Clock"},
3894 {"DAC L2", NULL, "DAC 2 Clock"},
3895 {"DAC R2", NULL, "DAC 2 Clock"},
3897 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3898 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3899 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3900 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3901 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3903 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3904 {"OUT MIXL", "INL Switch", "INL VOL"},
3905 {"OUT MIXL", "BST1 Switch", "BST1"},
3906 {"OUT MIXL", "BST2 Switch", "BST2"},
3907 {"OUT MIXL", "BST3 Switch", "BST3"},
3908 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3909 {"OUT MIXR", "INR Switch", "INR VOL"},
3910 {"OUT MIXR", "BST2 Switch", "BST2"},
3911 {"OUT MIXR", "BST3 Switch", "BST3"},
3912 {"OUT MIXR", "BST4 Switch", "BST4"},
3914 {"MONOVOL", "Switch", "MONOVOL MIX"},
3915 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3916 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3917 {"Mono Amp", NULL, "Mono MIX"},
3918 {"Mono Amp", NULL, "Vref2"},
3919 {"Mono Amp", NULL, "Vref3"},
3920 {"Mono Amp", NULL, "CLKDET SYS"},
3921 {"Mono Amp", NULL, "CLKDET MONO"},
3922 {"Mono Playback", "Switch", "Mono Amp"},
3923 {"MONOOUT", NULL, "Mono Playback"},
3925 {"HP Amp", NULL, "DAC L1"},
3926 {"HP Amp", NULL, "DAC R1"},
3927 {"HP Amp", NULL, "Charge Pump"},
3928 {"HP Amp", NULL, "CLKDET SYS"},
3929 {"HP Amp", NULL, "CLKDET HP"},
3930 {"HP Amp", NULL, "CBJ Power"},
3931 {"HP Amp", NULL, "Vref2"},
3932 {"HPO Playback", "Switch", "HP Amp"},
3933 {"HPOL", NULL, "HPO Playback"},
3934 {"HPOR", NULL, "HPO Playback"},
3936 {"OUTVOL L", "Switch", "OUT MIXL"},
3937 {"OUTVOL R", "Switch", "OUT MIXR"},
3938 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
3939 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
3940 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
3941 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
3942 {"LOUT Amp", NULL, "LOUT L MIX"},
3943 {"LOUT Amp", NULL, "LOUT R MIX"},
3944 {"LOUT Amp", NULL, "Vref1"},
3945 {"LOUT Amp", NULL, "Vref2"},
3946 {"LOUT Amp", NULL, "CLKDET SYS"},
3947 {"LOUT Amp", NULL, "CLKDET LOUT"},
3948 {"LOUT L Playback", "Switch", "LOUT Amp"},
3949 {"LOUT R Playback", "Switch", "LOUT Amp"},
3950 {"LOUTL", NULL, "LOUT L Playback"},
3951 {"LOUTR", NULL, "LOUT R Playback"},
3953 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
3954 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
3955 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
3956 {"PDM L Mux", NULL, "PDM Power"},
3957 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
3958 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
3959 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
3960 {"PDM R Mux", NULL, "PDM Power"},
3961 {"PDM L Playback", "Switch", "PDM L Mux"},
3962 {"PDM R Playback", "Switch", "PDM R Mux"},
3963 {"PDML", NULL, "PDM L Playback"},
3964 {"PDMR", NULL, "PDM R Playback"},
3967 static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3968 unsigned int rx_mask, int slots, int slot_width)
3970 struct snd_soc_codec *codec = dai->codec;
3971 unsigned int val = 0;
3973 if (rx_mask || tx_mask)
3974 val |= RT5665_I2S1_MODE_TDM;
3978 val |= RT5665_TDM_IN_CH_4;
3979 val |= RT5665_TDM_OUT_CH_4;
3982 val |= RT5665_TDM_IN_CH_6;
3983 val |= RT5665_TDM_OUT_CH_6;
3986 val |= RT5665_TDM_IN_CH_8;
3987 val |= RT5665_TDM_OUT_CH_8;
3995 switch (slot_width) {
3997 val |= RT5665_TDM_IN_LEN_20;
3998 val |= RT5665_TDM_OUT_LEN_20;
4001 val |= RT5665_TDM_IN_LEN_24;
4002 val |= RT5665_TDM_OUT_LEN_24;
4005 val |= RT5665_TDM_IN_LEN_32;
4006 val |= RT5665_TDM_OUT_LEN_32;
4014 snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
4015 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4016 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4017 RT5665_TDM_OUT_LEN_MASK, val);
4023 static int rt5665_hw_params(struct snd_pcm_substream *substream,
4024 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4026 struct snd_soc_codec *codec = dai->codec;
4027 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4028 unsigned int val_len = 0, val_clk, mask_clk, val_bits = 0x0100;
4029 int pre_div, frame_size;
4031 rt5665->lrck[dai->id] = params_rate(params);
4032 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4034 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
4035 rt5665->lrck[dai->id], dai->id);
4038 frame_size = snd_soc_params_to_frame_size(params);
4039 if (frame_size < 0) {
4040 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4044 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4045 rt5665->lrck[dai->id], pre_div, dai->id);
4047 switch (params_width(params)) {
4052 val_len |= RT5665_I2S_DL_20;
4056 val_len |= RT5665_I2S_DL_24;
4060 val_len |= RT5665_I2S_DL_8;
4069 if (params_channels(params) > 2)
4070 rt5665_set_tdm_slot(dai, 0xf, 0xf,
4071 params_channels(params), params_width(params));
4072 mask_clk = RT5665_I2S_PD1_MASK;
4073 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4074 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4075 RT5665_I2S_DL_MASK, val_len);
4079 mask_clk = RT5665_I2S_PD2_MASK;
4080 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4081 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4082 RT5665_I2S_DL_MASK, val_len);
4085 mask_clk = RT5665_I2S_PD3_MASK;
4086 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4087 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4088 RT5665_I2S_DL_MASK, val_len);
4091 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4095 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1, mask_clk, val_clk);
4096 snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4098 switch (rt5665->lrck[dai->id]) {
4100 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4101 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4102 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4105 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4106 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4107 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4110 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4111 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4112 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4119 static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4121 struct snd_soc_codec *codec = dai->codec;
4122 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4123 unsigned int reg_val = 0;
4125 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4126 case SND_SOC_DAIFMT_CBM_CFM:
4127 rt5665->master[dai->id] = 1;
4129 case SND_SOC_DAIFMT_CBS_CFS:
4130 reg_val |= RT5665_I2S_MS_S;
4131 rt5665->master[dai->id] = 0;
4137 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4138 case SND_SOC_DAIFMT_NB_NF:
4140 case SND_SOC_DAIFMT_IB_NF:
4141 reg_val |= RT5665_I2S_BP_INV;
4147 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4148 case SND_SOC_DAIFMT_I2S:
4150 case SND_SOC_DAIFMT_LEFT_J:
4151 reg_val |= RT5665_I2S_DF_LEFT;
4153 case SND_SOC_DAIFMT_DSP_A:
4154 reg_val |= RT5665_I2S_DF_PCM_A;
4156 case SND_SOC_DAIFMT_DSP_B:
4157 reg_val |= RT5665_I2S_DF_PCM_B;
4166 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4167 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4168 RT5665_I2S_DF_MASK, reg_val);
4172 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4173 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4174 RT5665_I2S_DF_MASK, reg_val);
4177 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4178 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4179 RT5665_I2S_DF_MASK, reg_val);
4182 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4188 static int rt5665_set_dai_sysclk(struct snd_soc_dai *dai,
4189 int clk_id, unsigned int freq, int dir)
4191 struct snd_soc_codec *codec = dai->codec;
4192 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4193 unsigned int reg_val = 0;
4195 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4199 case RT5665_SCLK_S_MCLK:
4200 reg_val |= RT5665_SCLK_SRC_MCLK;
4202 case RT5665_SCLK_S_PLL1:
4203 reg_val |= RT5665_SCLK_SRC_PLL1;
4205 case RT5665_SCLK_S_RCCLK:
4206 reg_val |= RT5665_SCLK_SRC_RCCLK;
4209 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4212 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4213 RT5665_SCLK_SRC_MASK, reg_val);
4214 rt5665->sysclk = freq;
4215 rt5665->sysclk_src = clk_id;
4217 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4222 static int rt5665_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int Source,
4223 unsigned int freq_in, unsigned int freq_out)
4225 struct snd_soc_codec *codec = dai->codec;
4226 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4227 struct rl6231_pll_code pll_code;
4230 if (Source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4231 freq_out == rt5665->pll_out)
4234 if (!freq_in || !freq_out) {
4235 dev_dbg(codec->dev, "PLL disabled\n");
4238 rt5665->pll_out = 0;
4239 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4240 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4245 case RT5665_PLL1_S_MCLK:
4246 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4247 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4249 case RT5665_PLL1_S_BCLK1:
4250 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4251 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4253 case RT5665_PLL1_S_BCLK2:
4254 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4255 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4257 case RT5665_PLL1_S_BCLK3:
4258 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4259 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4262 dev_err(codec->dev, "Unknown PLL Source %d\n", Source);
4266 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4268 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4272 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
4273 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4274 pll_code.n_code, pll_code.k_code);
4276 snd_soc_write(codec, RT5665_PLL_CTRL_1,
4277 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4278 snd_soc_write(codec, RT5665_PLL_CTRL_2,
4279 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4280 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4282 rt5665->pll_in = freq_in;
4283 rt5665->pll_out = freq_out;
4284 rt5665->pll_src = Source;
4289 static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4291 struct snd_soc_codec *codec = dai->codec;
4292 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4294 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
4296 rt5665->bclk[dai->id] = ratio;
4302 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4303 RT5665_I2S_BCLK_MS2_MASK,
4304 RT5665_I2S_BCLK_MS2_64);
4307 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4308 RT5665_I2S_BCLK_MS3_MASK,
4309 RT5665_I2S_BCLK_MS3_64);
4317 static int rt5665_set_bias_level(struct snd_soc_codec *codec,
4318 enum snd_soc_bias_level level)
4320 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4323 case SND_SOC_BIAS_PREPARE:
4324 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4325 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4328 case SND_SOC_BIAS_STANDBY:
4329 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4330 RT5665_PWR_LDO, RT5665_PWR_LDO);
4331 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4332 RT5665_PWR_MB, RT5665_PWR_MB);
4333 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4334 RT5665_DIG_GATE_CTRL, 0);
4336 case SND_SOC_BIAS_OFF:
4337 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4339 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4350 static int rt5665_probe(struct snd_soc_codec *codec)
4352 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4354 rt5665->codec = codec;
4356 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4361 static int rt5665_remove(struct snd_soc_codec *codec)
4363 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4365 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4371 static int rt5665_suspend(struct snd_soc_codec *codec)
4373 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4375 regcache_cache_only(rt5665->regmap, true);
4376 regcache_mark_dirty(rt5665->regmap);
4380 static int rt5665_resume(struct snd_soc_codec *codec)
4382 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4384 regcache_cache_only(rt5665->regmap, false);
4385 regcache_sync(rt5665->regmap);
4390 #define rt5665_suspend NULL
4391 #define rt5665_resume NULL
4394 #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4395 #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4396 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4398 static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4399 .hw_params = rt5665_hw_params,
4400 .set_fmt = rt5665_set_dai_fmt,
4401 .set_sysclk = rt5665_set_dai_sysclk,
4402 .set_tdm_slot = rt5665_set_tdm_slot,
4403 .set_pll = rt5665_set_dai_pll,
4404 .set_bclk_ratio = rt5665_set_bclk_ratio,
4407 static struct snd_soc_dai_driver rt5665_dai[] = {
4409 .name = "rt5665-aif1_1",
4410 .id = RT5665_AIF1_1,
4412 .stream_name = "AIF1 Playback",
4415 .rates = RT5665_STEREO_RATES,
4416 .formats = RT5665_FORMATS,
4419 .stream_name = "AIF1_1 Capture",
4422 .rates = RT5665_STEREO_RATES,
4423 .formats = RT5665_FORMATS,
4425 .ops = &rt5665_aif_dai_ops,
4428 .name = "rt5665-aif1_2",
4429 .id = RT5665_AIF1_2,
4431 .stream_name = "AIF1_2 Capture",
4434 .rates = RT5665_STEREO_RATES,
4435 .formats = RT5665_FORMATS,
4437 .ops = &rt5665_aif_dai_ops,
4440 .name = "rt5665-aif2_1",
4441 .id = RT5665_AIF2_1,
4443 .stream_name = "AIF2_1 Playback",
4446 .rates = RT5665_STEREO_RATES,
4447 .formats = RT5665_FORMATS,
4450 .stream_name = "AIF2_1 Capture",
4453 .rates = RT5665_STEREO_RATES,
4454 .formats = RT5665_FORMATS,
4456 .ops = &rt5665_aif_dai_ops,
4459 .name = "rt5665-aif2_2",
4460 .id = RT5665_AIF2_2,
4462 .stream_name = "AIF2_2 Playback",
4465 .rates = RT5665_STEREO_RATES,
4466 .formats = RT5665_FORMATS,
4469 .stream_name = "AIF2_2 Capture",
4472 .rates = RT5665_STEREO_RATES,
4473 .formats = RT5665_FORMATS,
4475 .ops = &rt5665_aif_dai_ops,
4478 .name = "rt5665-aif3",
4481 .stream_name = "AIF3 Playback",
4484 .rates = RT5665_STEREO_RATES,
4485 .formats = RT5665_FORMATS,
4488 .stream_name = "AIF3 Capture",
4491 .rates = RT5665_STEREO_RATES,
4492 .formats = RT5665_FORMATS,
4494 .ops = &rt5665_aif_dai_ops,
4498 static struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
4499 .probe = rt5665_probe,
4500 .remove = rt5665_remove,
4501 .suspend = rt5665_suspend,
4502 .resume = rt5665_resume,
4503 .set_bias_level = rt5665_set_bias_level,
4504 .idle_bias_off = true,
4505 .component_driver = {
4506 .controls = rt5665_snd_controls,
4507 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4508 .dapm_widgets = rt5665_dapm_widgets,
4509 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4510 .dapm_routes = rt5665_dapm_routes,
4511 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4516 static const struct regmap_config rt5665_regmap = {
4519 .max_register = 0x0400,
4520 .volatile_reg = rt5665_volatile_register,
4521 .readable_reg = rt5665_readable_register,
4522 .cache_type = REGCACHE_RBTREE,
4523 .reg_defaults = rt5665_reg,
4524 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4525 .use_single_rw = true,
4528 static const struct i2c_device_id rt5665_i2c_id[] = {
4532 MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4534 static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4536 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4537 "realtek,in1-differential");
4538 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4539 "realtek,in2-differential");
4540 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4541 "realtek,in3-differential");
4542 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4543 "realtek,in4-differential");
4545 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4546 &rt5665->pdata.dmic1_data_pin);
4547 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4548 &rt5665->pdata.dmic2_data_pin);
4549 of_property_read_u32(dev->of_node, "realtek,jd-src",
4550 &rt5665->pdata.jd_src);
4552 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4553 "realtek,ldo1-en-gpios", 0);
4558 static void rt5665_calibrate(struct rt5665_priv *rt5665)
4562 mutex_lock(&rt5665->calibrate_mutex);
4564 regcache_cache_bypass(rt5665->regmap, true);
4566 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4567 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4568 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4569 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4570 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4571 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4572 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4573 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4574 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4575 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4576 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4577 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4578 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4579 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4580 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4581 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4582 usleep_range(15000, 20000);
4583 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4584 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4586 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4589 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4591 usleep_range(10000, 10005);
4596 pr_err("HP Calibration Failure\n");
4597 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4598 regcache_cache_bypass(rt5665->regmap, false);
4605 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4608 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4610 usleep_range(10000, 10005);
4615 pr_err("MONO Calibration Failure\n");
4616 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4617 regcache_cache_bypass(rt5665->regmap, false);
4624 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4625 regcache_cache_bypass(rt5665->regmap, false);
4627 regcache_mark_dirty(rt5665->regmap);
4628 regcache_sync(rt5665->regmap);
4630 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4631 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4634 mutex_unlock(&rt5665->calibrate_mutex);
4637 static void rt5665_calibrate_handler(struct work_struct *work)
4639 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4640 calibrate_work.work);
4642 while (!rt5665->codec->component.card->instantiated) {
4643 pr_debug("%s\n", __func__);
4644 usleep_range(10000, 15000);
4647 rt5665_calibrate(rt5665);
4650 static int rt5665_i2c_probe(struct i2c_client *i2c,
4651 const struct i2c_device_id *id)
4653 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4654 struct rt5665_priv *rt5665;
4658 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4664 i2c_set_clientdata(i2c, rt5665);
4667 rt5665->pdata = *pdata;
4669 rt5665_parse_dt(rt5665, &i2c->dev);
4671 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4672 rt5665->supplies[i].supply = rt5665_supply_names[i];
4674 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4677 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4681 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4684 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4688 if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
4689 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
4690 GPIOF_OUT_INIT_HIGH, "rt5665"))
4691 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
4694 /* Sleep for 300 ms miniumum */
4695 usleep_range(300000, 350000);
4697 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4698 if (IS_ERR(rt5665->regmap)) {
4699 ret = PTR_ERR(rt5665->regmap);
4700 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4705 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4706 if (val != DEVICE_ID) {
4708 "Device with ID register %x is not rt5665\n", val);
4712 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4715 rt5665->id = CODEC_5666;
4718 rt5665->id = CODEC_5668;
4722 rt5665->id = CODEC_5665;
4726 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4728 /* line in diff mode*/
4729 if (rt5665->pdata.in1_diff)
4730 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4731 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4732 if (rt5665->pdata.in2_diff)
4733 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4734 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4735 if (rt5665->pdata.in3_diff)
4736 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4737 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4738 if (rt5665->pdata.in4_diff)
4739 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4740 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4743 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4744 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4745 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4746 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4747 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4748 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4749 switch (rt5665->pdata.dmic1_data_pin) {
4750 case RT5665_DMIC1_DATA_IN2N:
4751 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4752 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4755 case RT5665_DMIC1_DATA_GPIO4:
4756 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4757 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4758 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4759 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4763 dev_dbg(&i2c->dev, "no DMIC1\n");
4767 switch (rt5665->pdata.dmic2_data_pin) {
4768 case RT5665_DMIC2_DATA_IN2P:
4769 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4770 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4773 case RT5665_DMIC2_DATA_GPIO5:
4774 regmap_update_bits(rt5665->regmap,
4776 RT5665_DMIC_2_DP_MASK,
4777 RT5665_DMIC_2_DP_GPIO5);
4778 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4779 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4783 dev_dbg(&i2c->dev, "no DMIC2\n");
4789 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4790 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4791 0xf000 | RT5665_VREF_POW_MASK, 0xd000 | RT5665_VREF_POW_REG);
4792 /* Work around for pow_pump */
4793 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4794 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4796 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4797 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4799 /* Set GPIO4,8 as input for combo jack */
4800 if (rt5665->id == CODEC_5666) {
4801 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4802 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4803 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4804 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4807 /* Enhance performance*/
4808 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4809 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
4810 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
4812 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4813 rt5665_jack_detect_handler);
4814 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4815 rt5665_calibrate_handler);
4816 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4817 rt5665_jd_check_handler);
4819 mutex_init(&rt5665->calibrate_mutex);
4822 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4823 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4824 | IRQF_ONESHOT, "rt5665", rt5665);
4826 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4830 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
4831 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4834 static int rt5665_i2c_remove(struct i2c_client *i2c)
4836 snd_soc_unregister_codec(&i2c->dev);
4841 static void rt5665_i2c_shutdown(struct i2c_client *client)
4843 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4845 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4849 static const struct of_device_id rt5665_of_match[] = {
4850 {.compatible = "realtek,rt5665"},
4851 {.compatible = "realtek,rt5666"},
4852 {.compatible = "realtek,rt5668"},
4855 MODULE_DEVICE_TABLE(of, rt5665_of_match);
4859 static struct acpi_device_id rt5665_acpi_match[] = {
4865 MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4868 struct i2c_driver rt5665_i2c_driver = {
4871 .of_match_table = of_match_ptr(rt5665_of_match),
4872 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4874 .probe = rt5665_i2c_probe,
4875 .remove = rt5665_i2c_remove,
4876 .shutdown = rt5665_i2c_shutdown,
4877 .id_table = rt5665_i2c_id,
4879 module_i2c_driver(rt5665_i2c_driver);
4881 MODULE_DESCRIPTION("ASoC RT5665 driver");
4882 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4883 MODULE_LICENSE("GPL v2");
git.samba.org / sfrench / cifs-2.6.git / blob