sound/soc/codecs/inno_rk3036.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Driver of Inno Codec for rk3036 by Rockchip Inc.
   4  *
   5  * Author: Zheng ShunQian<zhengsq@rock-chips.com>
   6  */
   7
   8 #ifndef _INNO_RK3036_CODEC_H
   9 #define _INNO_RK3036_CODEC_H
  10
  11 /* codec registers */
  12 #define INNO_R00        0x00
  13 #define INNO_R01        0x0c
  14 #define INNO_R02        0x10
  15 #define INNO_R03        0x14
  16 #define INNO_R04        0x88
  17 #define INNO_R05        0x8c
  18 #define INNO_R06        0x90
  19 #define INNO_R07        0x94
  20 #define INNO_R08        0x98
  21 #define INNO_R09        0x9c
  22 #define INNO_R10        0xa0
  23
  24 /* register bit filed */
  25 #define INNO_R00_CSR_RESET              (0x0 << 0) /*codec system reset*/
  26 #define INNO_R00_CSR_WORK               (0x1 << 0)
  27 #define INNO_R00_CDCR_RESET             (0x0 << 1) /*codec digital core reset*/
  28 #define INNO_R00_CDCR_WORK              (0x1 << 1)
  29 #define INNO_R00_PRB_DISABLE            (0x0 << 6) /*power reset bypass*/
  30 #define INNO_R00_PRB_ENABLE             (0x1 << 6)
  31
  32 #define INNO_R01_I2SMODE_MSK            (0x1 << 4)
  33 #define INNO_R01_I2SMODE_SLAVE          (0x0 << 4)
  34 #define INNO_R01_I2SMODE_MASTER         (0x1 << 4)
  35 #define INNO_R01_PINDIR_MSK             (0x1 << 5)
  36 #define INNO_R01_PINDIR_IN_SLAVE        (0x0 << 5) /*direction of pin*/
  37 #define INNO_R01_PINDIR_OUT_MASTER      (0x1 << 5)
  38
  39 #define INNO_R02_LRS_MSK                (0x1 << 2)
  40 #define INNO_R02_LRS_NORMAL             (0x0 << 2) /*DAC Left Right Swap*/
  41 #define INNO_R02_LRS_SWAP               (0x1 << 2)
  42 #define INNO_R02_DACM_MSK               (0x3 << 3)
  43 #define INNO_R02_DACM_PCM               (0x3 << 3) /*DAC Mode*/
  44 #define INNO_R02_DACM_I2S               (0x2 << 3)
  45 #define INNO_R02_DACM_LJM               (0x1 << 3)
  46 #define INNO_R02_DACM_RJM               (0x0 << 3)
  47 #define INNO_R02_VWL_MSK                (0x3 << 5)
  48 #define INNO_R02_VWL_32BIT              (0x3 << 5) /*1/2Frame Valid Word Len*/
  49 #define INNO_R02_VWL_24BIT              (0x2 << 5)
  50 #define INNO_R02_VWL_20BIT              (0x1 << 5)
  51 #define INNO_R02_VWL_16BIT              (0x0 << 5)
  52 #define INNO_R02_LRCP_MSK               (0x1 << 7)
  53 #define INNO_R02_LRCP_NORMAL            (0x0 << 7) /*Left Right Polarity*/
  54 #define INNO_R02_LRCP_REVERSAL          (0x1 << 7)
  55
  56 #define INNO_R03_BCP_MSK                (0x1 << 0)
  57 #define INNO_R03_BCP_NORMAL             (0x0 << 0) /*DAC bit clock polarity*/
  58 #define INNO_R03_BCP_REVERSAL           (0x1 << 0)
  59 #define INNO_R03_DACR_MSK               (0x1 << 1)
  60 #define INNO_R03_DACR_RESET             (0x0 << 1) /*DAC Reset*/
  61 #define INNO_R03_DACR_WORK              (0x1 << 1)
  62 #define INNO_R03_FWL_MSK                (0x3 << 2)
  63 #define INNO_R03_FWL_32BIT              (0x3 << 2) /*1/2Frame Word Length*/
  64 #define INNO_R03_FWL_24BIT              (0x2 << 2)
  65 #define INNO_R03_FWL_20BIT              (0x1 << 2)
  66 #define INNO_R03_FWL_16BIT              (0x0 << 2)
  67
  68 #define INNO_R04_DACR_SW_SHIFT          0
  69 #define INNO_R04_DACL_SW_SHIFT          1
  70 #define INNO_R04_DACR_CLK_SHIFT         2
  71 #define INNO_R04_DACL_CLK_SHIFT         3
  72 #define INNO_R04_DACR_VREF_SHIFT        4
  73 #define INNO_R04_DACL_VREF_SHIFT        5
  74
  75 #define INNO_R05_HPR_EN_SHIFT           0
  76 #define INNO_R05_HPL_EN_SHIFT           1
  77 #define INNO_R05_HPR_WORK_SHIFT         2
  78 #define INNO_R05_HPL_WORK_SHIFT         3
  79
  80 #define INNO_R06_VOUTR_CZ_SHIFT         0
  81 #define INNO_R06_VOUTL_CZ_SHIFT         1
  82 #define INNO_R06_DACR_HILO_VREF_SHIFT   2
  83 #define INNO_R06_DACL_HILO_VREF_SHIFT   3
  84 #define INNO_R06_DAC_EN_SHIFT           5
  85
  86 #define INNO_R06_DAC_PRECHARGE          (0x0 << 4) /*PreCharge control for DAC*/
  87 #define INNO_R06_DAC_DISCHARGE          (0x1 << 4)
  88
  89 #define INNO_HP_GAIN_SHIFT              0
  90 /* Gain of output, 1.5db step: -39db(0x0) ~ 0db(0x1a) ~ 6db(0x1f) */
  91 #define INNO_HP_GAIN_0DB                0x1a
  92 #define INNO_HP_GAIN_N39DB              0x0
  93
  94 #define INNO_R09_HP_ANTIPOP_MSK         0x3
  95 #define INNO_R09_HP_ANTIPOP_OFF         0x1
  96 #define INNO_R09_HP_ANTIPOP_ON          0x2
  97 #define INNO_R09_HPR_ANITPOP_SHIFT      0
  98 #define INNO_R09_HPL_ANITPOP_SHIFT      2
  99 #define INNO_R09_HPR_MUTE_SHIFT         4
 100 #define INNO_R09_HPL_MUTE_SHIFT         5
 101 #define INNO_R09_DACR_SWITCH_SHIFT      6
 102 #define INNO_R09_DACL_SWITCH_SHIFT      7
 103
 104 #define INNO_R10_CHARGE_SEL_CUR_400I_YES        (0x0 << 0)
 105 #define INNO_R10_CHARGE_SEL_CUR_400I_NO         (0x1 << 0)
 106 #define INNO_R10_CHARGE_SEL_CUR_260I_YES        (0x0 << 1)
 107 #define INNO_R10_CHARGE_SEL_CUR_260I_NO         (0x1 << 1)
 108 #define INNO_R10_CHARGE_SEL_CUR_130I_YES        (0x0 << 2)
 109 #define INNO_R10_CHARGE_SEL_CUR_130I_NO         (0x1 << 2)
 110 #define INNO_R10_CHARGE_SEL_CUR_100I_YES        (0x0 << 3)
 111 #define INNO_R10_CHARGE_SEL_CUR_100I_NO         (0x1 << 3)
 112 #define INNO_R10_CHARGE_SEL_CUR_050I_YES        (0x0 << 4)
 113 #define INNO_R10_CHARGE_SEL_CUR_050I_NO         (0x1 << 4)
 114 #define INNO_R10_CHARGE_SEL_CUR_027I_YES        (0x0 << 5)
 115 #define INNO_R10_CHARGE_SEL_CUR_027I_NO         (0x1 << 5)
 116
 117 #define INNO_R10_MAX_CUR (INNO_R10_CHARGE_SEL_CUR_400I_YES | \
 118                           INNO_R10_CHARGE_SEL_CUR_260I_YES | \
 119                           INNO_R10_CHARGE_SEL_CUR_130I_YES | \
 120                           INNO_R10_CHARGE_SEL_CUR_100I_YES | \
 121                           INNO_R10_CHARGE_SEL_CUR_050I_YES | \
 122                           INNO_R10_CHARGE_SEL_CUR_027I_YES)
 123
 124 #endif