1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include "include/acp_2_2_d.h"
6 #include "include/acp_2_2_sh_mask.h"
8 #define ACP_PAGE_SIZE_4K_ENABLE 0x02
10 #define ACP_PLAYBACK_PTE_OFFSET 10
11 #define ACP_CAPTURE_PTE_OFFSET 0
13 #define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4
14 #define ACP_ONION_CNTL_DEFAULT 0x00000FB4
16 #define ACP_PHYSICAL_BASE 0x14000
18 /* Playback SRAM address (as a destination in dma descriptor) */
19 #define ACP_SHARED_RAM_BANK_1_ADDRESS 0x4002000
21 /* Capture SRAM address (as a source in dma descriptor) */
22 #define ACP_SHARED_RAM_BANK_5_ADDRESS 0x400A000
23 #define ACP_SHARED_RAM_BANK_3_ADDRESS 0x4006000
25 #define ACP_DMA_RESET_TIME 10000
26 #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
27 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
28 #define ACP_DMA_COMPLETE_TIME_OUT_VALUE 0x000000FF
30 #define ACP_SRAM_BASE_ADDRESS 0x4000000
31 #define ACP_DAGB_GRP_SRAM_BASE_ADDRESS 0x4001000
32 #define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET 0x1000
33 #define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 0x00000000
34 #define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS 0x01800000
36 #define TO_ACP_I2S_1 0x2
37 #define TO_ACP_I2S_2 0x4
38 #define FROM_ACP_I2S_1 0xa
39 #define FROM_ACP_I2S_2 0xb
41 #define ACP_TILE_ON_MASK 0x03
42 #define ACP_TILE_OFF_MASK 0x02
43 #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
44 #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
46 #define ACP_TILE_P1_MASK 0x3e
47 #define ACP_TILE_P2_MASK 0x3d
48 #define ACP_TILE_DSP0_MASK 0x3b
49 #define ACP_TILE_DSP1_MASK 0x37
51 #define ACP_TILE_DSP2_MASK 0x2f
52 /* Playback DMA channels */
53 #define SYSRAM_TO_ACP_CH_NUM 12
54 #define ACP_TO_I2S_DMA_CH_NUM 13
56 /* Capture DMA channels */
57 #define ACP_TO_SYSRAM_CH_NUM 14
58 #define I2S_TO_ACP_DMA_CH_NUM 15
60 #define NUM_DSCRS_PER_CHANNEL 2
62 #define PLAYBACK_START_DMA_DESCR_CH12 0
63 #define PLAYBACK_END_DMA_DESCR_CH12 1
64 #define PLAYBACK_START_DMA_DESCR_CH13 2
65 #define PLAYBACK_END_DMA_DESCR_CH13 3
67 #define CAPTURE_START_DMA_DESCR_CH14 4
68 #define CAPTURE_END_DMA_DESCR_CH14 5
69 #define CAPTURE_START_DMA_DESCR_CH15 6
70 #define CAPTURE_END_DMA_DESCR_CH15 7
72 #define mmACP_I2S_16BIT_RESOLUTION_EN 0x5209
73 #define ACP_I2S_MIC_16BIT_RESOLUTION_EN 0x01
74 #define ACP_I2S_SP_16BIT_RESOLUTION_EN 0x02
75 enum acp_dma_priority_level {
76 /* 0x0 Specifies the DMA channel is given normal priority */
77 ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0,
78 /* 0x1 Specifies the DMA channel is given high priority */
79 ACP_DMA_PRIORITY_LEVEL_HIGH = 0x1,
80 ACP_DMA_PRIORITY_LEVEL_FORCESIZE = 0xFF
83 struct audio_substream_data {
90 u64 capturebytescount;
91 void __iomem *acp_mmio;
94 struct audio_drv_data {
95 struct snd_pcm_substream *play_stream;
96 struct snd_pcm_substream *capture_stream;
97 void __iomem *acp_mmio;
101 union acp_dma_count {
118 ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION = 0x0,
119 ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC = 0x1,
120 ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM = 0x8,
121 ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM = 0x9,
122 ACP_DMA_ATTRIBUTES_FORCE_SIZE = 0xF
125 typedef struct acp_dma_dscr_transfer {
126 /* Specifies the source memory location for the DMA data transfer. */
128 /* Specifies the destination memory location to where the data will
132 /* Specifies the number of bytes need to be transferred
133 * from source to destination memory.Transfer direction & IOC enable
136 /* Reserved for future use */
138 } acp_dma_dscr_transfer_t;
140 #endif /*__ACP_HW_H */