2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
11 * Modified 2009-04-13 for proper metering by Florian Faber
14 * Modified 2009-04-14 for native float support by Florian Faber
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
42 /* ************* Register Documentation *******************************************************
44 * Work in progress! Documentation is based on the code in this file.
46 * --------- HDSPM_controlRegister ---------
47 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
48 * :||||.||||:||||.||||:||||.||||:||||.||||:
49 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
50 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
51 * :||||.||||:||||.||||:||||.||||:||||.||||:
52 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
53 * : . : . : . : x . : HDSPM_AudioInterruptEnable \_ setting both bits
54 * : . : . : . : . x: HDSPM_Start / enables audio IO
55 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave
56 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency
57 * : . : . : . : . : 0:64, 1:128, 2:256, 3:512,
58 * : . : . : . : . : 4:1024, 5:2048, 6:4096, 7:8192
59 * :x . : . : . x:xx . : HDSPM_FrequencyMask
60 * : . : . : . :10 . : HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=??
61 * : . : . : . x: . : <MADI> HDSPM_DoubleSpeed
62 * :x . : . : . : . : <MADI> HDSPM_QuadSpeed
63 * : . 3 : . 10: 2 . : . : HDSPM_SyncRefMask :
64 * : . : . x: . : . : HDSPM_SyncRef0
65 * : . : . x : . : . : HDSPM_SyncRef1
66 * : . : . : x . : . : <AES32> HDSPM_SyncRef2
67 * : . x : . : . : . : <AES32> HDSPM_SyncRef3
68 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn
69 * : . 3 : . 10: 2 . : . : <AES32> 0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn?
70 * : . x : . : . : . : <MADIe> HDSPe_FLOAT_FORMAT
71 * : . : . : x . : . : <MADI> HDSPM_InputSelect0 : 0=optical,1=coax
72 * : . : . :x . : . : <MADI> HDSPM_InputSelect1
73 * : . : .x : . : . : <MADI> HDSPM_clr_tms
74 * : . : . : . x : . : <MADI> HDSPM_TX_64ch
75 * : . : . : . x : . : <AES32> HDSPM_Emphasis
76 * : . : . : .x : . : <MADI> HDSPM_AutoInp
77 * : . : . x : . : . : <MADI> HDSPM_SMUX
78 * : . : .x : . : . : <MADI> HDSPM_clr_tms
79 * : . : x. : . : . : <MADI> HDSPM_taxi_reset
80 * : . x: . : . : . : <MADI> HDSPM_LineOut
81 * : . x: . : . : . : <AES32> ??????????????????
82 * : . : x. : . : . : <AES32> HDSPM_WCK48
83 * : . : . : .x : . : <AES32> HDSPM_Dolby
84 * : . : x . : . : . : HDSPM_Midi0InterruptEnable
85 * : . :x . : . : . : HDSPM_Midi1InterruptEnable
86 * : . : x . : . : . : HDSPM_Midi2InterruptEnable
87 * : . x : . : . : . : <MADI> HDSPM_Midi3InterruptEnable
88 * : . x : . : . : . : <AES32> HDSPM_DS_DoubleWire
89 * : .x : . : . : . : <AES32> HDSPM_QS_DoubleWire
90 * : x. : . : . : . : <AES32> HDSPM_QS_QuadWire
91 * : . : . : . x : . : <AES32> HDSPM_Professional
92 * : x . : . : . : . : HDSPM_wclk_sel
94 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
95 * :||||.||||:||||.||||:||||.||||:||||.||||:
96 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
97 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
98 * :||||.||||:||||.||||:||||.||||:||||.||||:
99 * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit
105 * ------------ HDSPM_WR_SETTINGS ----------
106 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
107 * :1098.7654:3210.9876:5432.1098:7654.3210:
108 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
109 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
110 * :||||.||||:||||.||||:||||.||||:||||.||||:
111 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
112 * : . : . : . : . x: HDSPM_c0Master 1: Master, 0: Slave
113 * : . : . : . : . x : HDSPM_c0_SyncRef0
114 * : . : . : . : . x : HDSPM_c0_SyncRef1
115 * : . : . : . : .x : HDSPM_c0_SyncRef2
116 * : . : . : . : x. : HDSPM_c0_SyncRef3
117 * : . : . : . : 3.210 : HDSPM_c0_SyncRefMask:
118 * : . : . : . : . : RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4,
119 * : . : . : . : . : 9:TCO, 10:SyncIn
120 * : . : . : . : . : AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT,
121 * : . : . : . : . : 9:TCO, 10:SyncIn
124 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
125 * :1098.7654:3210.9876:5432.1098:7654.3210:
126 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
127 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
128 * :||||.||||:||||.||||:||||.||||:||||.||||:
129 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
132 #include <linux/init.h>
133 #include <linux/delay.h>
134 #include <linux/interrupt.h>
135 #include <linux/module.h>
136 #include <linux/slab.h>
137 #include <linux/pci.h>
138 #include <linux/math64.h>
141 #include <sound/core.h>
142 #include <sound/control.h>
143 #include <sound/pcm.h>
144 #include <sound/pcm_params.h>
145 #include <sound/info.h>
146 #include <sound/asoundef.h>
147 #include <sound/rawmidi.h>
148 #include <sound/hwdep.h>
149 #include <sound/initval.h>
151 #include <sound/hdspm.h>
153 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
154 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
155 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
157 module_param_array(index, int, NULL, 0444);
158 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
160 module_param_array(id, charp, NULL, 0444);
161 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
163 module_param_array(enable, bool, NULL, 0444);
164 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
169 "Winfried Ritsch <ritsch_AT_iem.at>, "
170 "Paul Davis <paul@linuxaudiosystems.com>, "
171 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
172 "Remy Bruno <remy.bruno@trinnov.com>, "
173 "Florian Faber <faberman@linuxproaudio.org>, "
174 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
176 MODULE_DESCRIPTION("RME HDSPM");
177 MODULE_LICENSE("GPL");
178 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
180 /* --- Write registers. ---
181 These are defined as byte-offsets from the iobase value. */
183 #define HDSPM_WR_SETTINGS 0
184 #define HDSPM_outputBufferAddress 32
185 #define HDSPM_inputBufferAddress 36
186 #define HDSPM_controlRegister 64
187 #define HDSPM_interruptConfirmation 96
188 #define HDSPM_control2Reg 256 /* not in specs ???????? */
189 #define HDSPM_freqReg 256 /* for setting arbitrary clock values (DDS feature) */
190 #define HDSPM_midiDataOut0 352 /* just believe in old code */
191 #define HDSPM_midiDataOut1 356
192 #define HDSPM_eeprom_wr 384 /* for AES32 */
194 /* DMA enable for 64 channels, only Bit 0 is relevant */
195 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
196 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
198 /* 16 page addresses for each of the 64 channels DMA buffer in and out
199 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
200 #define HDSPM_pageAddressBufferOut 8192
201 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
203 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
205 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
207 /* --- Read registers. ---
208 These are defined as byte-offsets from the iobase value */
209 #define HDSPM_statusRegister 0
210 /*#define HDSPM_statusRegister2 96 */
211 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
212 * offset 192, for AES32 *and* MADI
213 * => need to check that offset 192 is working on MADI */
214 #define HDSPM_statusRegister2 192
215 #define HDSPM_timecodeRegister 128
218 #define HDSPM_RD_STATUS_0 0
219 #define HDSPM_RD_STATUS_1 64
220 #define HDSPM_RD_STATUS_2 128
221 #define HDSPM_RD_STATUS_3 192
223 #define HDSPM_RD_TCO 256
224 #define HDSPM_RD_PLL_FREQ 512
225 #define HDSPM_WR_TCO 128
227 #define HDSPM_TCO1_TCO_lock 0x00000001
228 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
229 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
230 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
231 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
232 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
233 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
235 #define HDSPM_TCO1_set_TC 0x00000100
236 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
237 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
238 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
240 #define HDSPM_TCO2_TC_run 0x00010000
241 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
242 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
243 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
244 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
245 #define HDSPM_TCO2_set_jam_sync 0x00200000
246 #define HDSPM_TCO2_set_flywheel 0x00400000
248 #define HDSPM_TCO2_set_01_4 0x01000000
249 #define HDSPM_TCO2_set_pull_down 0x02000000
250 #define HDSPM_TCO2_set_pull_up 0x04000000
251 #define HDSPM_TCO2_set_freq 0x08000000
252 #define HDSPM_TCO2_set_term_75R 0x10000000
253 #define HDSPM_TCO2_set_input_LSB 0x20000000
254 #define HDSPM_TCO2_set_input_MSB 0x40000000
255 #define HDSPM_TCO2_set_freq_from_app 0x80000000
258 #define HDSPM_midiDataOut0 352
259 #define HDSPM_midiDataOut1 356
260 #define HDSPM_midiDataOut2 368
262 #define HDSPM_midiDataIn0 360
263 #define HDSPM_midiDataIn1 364
264 #define HDSPM_midiDataIn2 372
265 #define HDSPM_midiDataIn3 376
267 /* status is data bytes in MIDI-FIFO (0-128) */
268 #define HDSPM_midiStatusOut0 384
269 #define HDSPM_midiStatusOut1 388
270 #define HDSPM_midiStatusOut2 400
272 #define HDSPM_midiStatusIn0 392
273 #define HDSPM_midiStatusIn1 396
274 #define HDSPM_midiStatusIn2 404
275 #define HDSPM_midiStatusIn3 408
278 /* the meters are regular i/o-mapped registers, but offset
279 considerably from the rest. the peak registers are reset
280 when read; the least-significant 4 bits are full-scale counters;
281 the actual peak value is in the most-significant 24 bits.
284 #define HDSPM_MADI_INPUT_PEAK 4096
285 #define HDSPM_MADI_PLAYBACK_PEAK 4352
286 #define HDSPM_MADI_OUTPUT_PEAK 4608
288 #define HDSPM_MADI_INPUT_RMS_L 6144
289 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
290 #define HDSPM_MADI_OUTPUT_RMS_L 6656
292 #define HDSPM_MADI_INPUT_RMS_H 7168
293 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
294 #define HDSPM_MADI_OUTPUT_RMS_H 7680
296 /* --- Control Register bits --------- */
297 #define HDSPM_Start (1<<0) /* start engine */
299 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
300 #define HDSPM_Latency1 (1<<2) /* where n is defined */
301 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
303 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
304 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
305 register [RayDAT, AIO] */
307 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
309 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
310 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
311 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
312 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
314 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
315 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
316 56channelMODE=0 */ /* MADI ONLY*/
317 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
319 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
320 0=off, 1=on */ /* MADI ONLY */
321 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
323 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
326 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
328 #define HDSPM_SyncRef2 (1<<13)
329 #define HDSPM_SyncRef3 (1<<25)
331 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
332 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
333 AES additional bits in
334 lower 5 Audiodatabits ??? */
335 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
336 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
338 #define HDSPM_Midi0InterruptEnable 0x0400000
339 #define HDSPM_Midi1InterruptEnable 0x0800000
340 #define HDSPM_Midi2InterruptEnable 0x0200000
341 #define HDSPM_Midi3InterruptEnable 0x4000000
343 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
344 #define HDSPe_FLOAT_FORMAT 0x2000000
346 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
347 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
348 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
350 #define HDSPM_wclk_sel (1<<30)
352 /* additional control register bits for AIO*/
353 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */
354 #define HDSPM_c0_Input0 0x1000
355 #define HDSPM_c0_Input1 0x2000
356 #define HDSPM_c0_Spdif_Opt 0x4000
357 #define HDSPM_c0_Pro 0x8000
358 #define HDSPM_c0_clr_tms 0x10000
359 #define HDSPM_c0_AEB1 0x20000
360 #define HDSPM_c0_AEB2 0x40000
361 #define HDSPM_c0_LineOut 0x80000
362 #define HDSPM_c0_AD_GAIN0 0x100000
363 #define HDSPM_c0_AD_GAIN1 0x200000
364 #define HDSPM_c0_DA_GAIN0 0x400000
365 #define HDSPM_c0_DA_GAIN1 0x800000
366 #define HDSPM_c0_PH_GAIN0 0x1000000
367 #define HDSPM_c0_PH_GAIN1 0x2000000
368 #define HDSPM_c0_Sym6db 0x4000000
371 /* --- bit helper defines */
372 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
373 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
374 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
375 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
376 #define HDSPM_InputOptical 0
377 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
378 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
379 HDSPM_SyncRef2|HDSPM_SyncRef3)
381 #define HDSPM_c0_SyncRef0 0x2
382 #define HDSPM_c0_SyncRef1 0x4
383 #define HDSPM_c0_SyncRef2 0x8
384 #define HDSPM_c0_SyncRef3 0x10
385 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
386 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
388 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
389 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
390 #define HDSPM_SYNC_FROM_TCO 2
391 #define HDSPM_SYNC_FROM_SYNC_IN 3
393 #define HDSPM_Frequency32KHz HDSPM_Frequency0
394 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
395 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
396 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
397 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
398 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
400 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
401 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
402 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
406 /* Synccheck Status */
407 #define HDSPM_SYNC_CHECK_NO_LOCK 0
408 #define HDSPM_SYNC_CHECK_LOCK 1
409 #define HDSPM_SYNC_CHECK_SYNC 2
411 /* AutoSync References - used by "autosync_ref" control switch */
412 #define HDSPM_AUTOSYNC_FROM_WORD 0
413 #define HDSPM_AUTOSYNC_FROM_MADI 1
414 #define HDSPM_AUTOSYNC_FROM_TCO 2
415 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
416 #define HDSPM_AUTOSYNC_FROM_NONE 4
418 /* Possible sources of MADI input */
419 #define HDSPM_OPTICAL 0 /* optical */
420 #define HDSPM_COAXIAL 1 /* BNC */
422 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
423 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
425 #define hdspm_encode_in(x) (((x)&0x3)<<14)
426 #define hdspm_decode_in(x) (((x)>>14)&0x3)
428 /* --- control2 register bits --- */
429 #define HDSPM_TMS (1<<0)
430 #define HDSPM_TCK (1<<1)
431 #define HDSPM_TDI (1<<2)
432 #define HDSPM_JTAG (1<<3)
433 #define HDSPM_PWDN (1<<4)
434 #define HDSPM_PROGRAM (1<<5)
435 #define HDSPM_CONFIG_MODE_0 (1<<6)
436 #define HDSPM_CONFIG_MODE_1 (1<<7)
437 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
438 #define HDSPM_BIGENDIAN_MODE (1<<9)
439 #define HDSPM_RD_MULTIPLE (1<<10)
441 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
442 that do not conflict with specific bits for AES32 seem to be valid also
445 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
446 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
447 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
451 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
452 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
454 #define HDSPM_tcoLockMadi 0x00000020 /* Optional TCO locked status for HDSPe MADI*/
455 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
457 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
458 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
460 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
461 /* since 64byte accurate, last 6 bits are not used */
465 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
467 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
468 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
469 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
470 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
472 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
475 #define HDSPM_tco_detect 0x08000000
476 #define HDSPM_tcoLockAes 0x20000000 /* Optional TCO locked status for HDSPe AES */
478 #define HDSPM_s2_tco_detect 0x00000040
479 #define HDSPM_s2_AEBO_D 0x00000080
480 #define HDSPM_s2_AEBI_D 0x00000100
483 #define HDSPM_midi0IRQPending 0x40000000
484 #define HDSPM_midi1IRQPending 0x80000000
485 #define HDSPM_midi2IRQPending 0x20000000
486 #define HDSPM_midi2IRQPendingAES 0x00000020
487 #define HDSPM_midi3IRQPending 0x00200000
489 /* --- status bit helpers */
490 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
491 HDSPM_madiFreq2|HDSPM_madiFreq3)
492 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
493 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
494 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
495 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
496 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
497 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
498 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
499 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
500 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
502 /* Status2 Register bits */ /* MADI ONLY */
504 #define HDSPM_version0 (1<<0) /* not really defined but I guess */
505 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
506 #define HDSPM_version2 (1<<2)
508 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
509 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
511 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
512 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
513 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */
514 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */
516 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
517 #define HDSPM_SyncRef1 0x20000
519 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
520 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
521 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
523 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
525 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
527 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
528 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
529 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
530 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
531 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
532 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
533 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
534 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
535 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3)
537 #define HDSPM_status1_F_0 0x0400000
538 #define HDSPM_status1_F_1 0x0800000
539 #define HDSPM_status1_F_2 0x1000000
540 #define HDSPM_status1_F_3 0x2000000
541 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
544 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
546 #define HDSPM_SelSyncRef_WORD 0
547 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
548 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
549 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
550 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
554 For AES32, bits for status, status2 and timecode are different
557 #define HDSPM_AES32_wcLock 0x0200000
558 #define HDSPM_AES32_wcSync 0x0100000
559 #define HDSPM_AES32_wcFreq_bit 22
560 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
562 #define HDSPM_AES32_syncref_bit 16
563 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
565 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
566 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
567 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
568 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
569 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
570 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
571 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
572 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
573 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
574 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
575 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
576 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
579 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
580 #define HDSPM_LockAES 0x80
581 #define HDSPM_LockAES1 0x80
582 #define HDSPM_LockAES2 0x40
583 #define HDSPM_LockAES3 0x20
584 #define HDSPM_LockAES4 0x10
585 #define HDSPM_LockAES5 0x8
586 #define HDSPM_LockAES6 0x4
587 #define HDSPM_LockAES7 0x2
588 #define HDSPM_LockAES8 0x1
591 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
603 NB: Timecode register doesn't seem to work on AES32 card revision 230
607 #define UNITY_GAIN 32768 /* = 65536/2 */
608 #define MINUS_INFINITY_GAIN 0
610 /* Number of channels for different Speed Modes */
611 #define MADI_SS_CHANNELS 64
612 #define MADI_DS_CHANNELS 32
613 #define MADI_QS_CHANNELS 16
615 #define RAYDAT_SS_CHANNELS 36
616 #define RAYDAT_DS_CHANNELS 20
617 #define RAYDAT_QS_CHANNELS 12
619 #define AIO_IN_SS_CHANNELS 14
620 #define AIO_IN_DS_CHANNELS 10
621 #define AIO_IN_QS_CHANNELS 8
622 #define AIO_OUT_SS_CHANNELS 16
623 #define AIO_OUT_DS_CHANNELS 12
624 #define AIO_OUT_QS_CHANNELS 10
626 #define AES32_CHANNELS 16
628 /* the size of a substream (1 mono data stream) */
629 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
630 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
632 /* the size of the area we need to allocate for DMA transfers. the
633 size is the same regardless of the number of channels, and
634 also the latency to use.
635 for one direction !!!
637 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
638 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
640 #define HDSPM_RAYDAT_REV 211
641 #define HDSPM_AIO_REV 212
642 #define HDSPM_MADIFACE_REV 213
644 /* speed factor modes */
645 #define HDSPM_SPEED_SINGLE 0
646 #define HDSPM_SPEED_DOUBLE 1
647 #define HDSPM_SPEED_QUAD 2
649 /* names for speed modes */
650 static char *hdspm_speed_names[] = { "single", "double", "quad" };
652 static const char *const texts_autosync_aes_tco[] = { "Word Clock",
653 "AES1", "AES2", "AES3", "AES4",
654 "AES5", "AES6", "AES7", "AES8",
657 static const char *const texts_autosync_aes[] = { "Word Clock",
658 "AES1", "AES2", "AES3", "AES4",
659 "AES5", "AES6", "AES7", "AES8",
662 static const char *const texts_autosync_madi_tco[] = { "Word Clock",
663 "MADI", "TCO", "Sync In" };
664 static const char *const texts_autosync_madi[] = { "Word Clock",
667 static const char *const texts_autosync_raydat_tco[] = {
669 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
670 "AES", "SPDIF", "TCO", "Sync In"
672 static const char *const texts_autosync_raydat[] = {
674 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
675 "AES", "SPDIF", "Sync In"
677 static const char *const texts_autosync_aio_tco[] = {
679 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
681 static const char *const texts_autosync_aio[] = { "Word Clock",
682 "ADAT", "AES", "SPDIF", "Sync In" };
684 static const char *const texts_freq[] = {
697 static char *texts_ports_madi[] = {
698 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
699 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
700 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
701 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
702 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
703 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
704 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
705 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
706 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
707 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
708 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
712 static char *texts_ports_raydat_ss[] = {
713 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
714 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
715 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
716 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
717 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
718 "ADAT4.7", "ADAT4.8",
723 static char *texts_ports_raydat_ds[] = {
724 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
725 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
726 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
727 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
732 static char *texts_ports_raydat_qs[] = {
733 "ADAT1.1", "ADAT1.2",
734 "ADAT2.1", "ADAT2.2",
735 "ADAT3.1", "ADAT3.2",
736 "ADAT4.1", "ADAT4.2",
742 static char *texts_ports_aio_in_ss[] = {
743 "Analogue.L", "Analogue.R",
745 "SPDIF.L", "SPDIF.R",
746 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
748 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
751 static char *texts_ports_aio_out_ss[] = {
752 "Analogue.L", "Analogue.R",
754 "SPDIF.L", "SPDIF.R",
755 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
757 "Phone.L", "Phone.R",
758 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
761 static char *texts_ports_aio_in_ds[] = {
762 "Analogue.L", "Analogue.R",
764 "SPDIF.L", "SPDIF.R",
765 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
766 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
769 static char *texts_ports_aio_out_ds[] = {
770 "Analogue.L", "Analogue.R",
772 "SPDIF.L", "SPDIF.R",
773 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
774 "Phone.L", "Phone.R",
775 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
778 static char *texts_ports_aio_in_qs[] = {
779 "Analogue.L", "Analogue.R",
781 "SPDIF.L", "SPDIF.R",
782 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
783 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
786 static char *texts_ports_aio_out_qs[] = {
787 "Analogue.L", "Analogue.R",
789 "SPDIF.L", "SPDIF.R",
790 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
791 "Phone.L", "Phone.R",
792 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
795 static char *texts_ports_aes32[] = {
796 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
797 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
801 /* These tables map the ALSA channels 1..N to the channels that we
802 need to use in order to find the relevant channel buffer. RME
803 refers to this kind of mapping as between "the ADAT channel and
804 the DMA channel." We index it using the logical audio channel,
805 and the value is the DMA channel (i.e. channel buffer number)
806 where the data for that channel can be read/written from/to.
809 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
810 0, 1, 2, 3, 4, 5, 6, 7,
811 8, 9, 10, 11, 12, 13, 14, 15,
812 16, 17, 18, 19, 20, 21, 22, 23,
813 24, 25, 26, 27, 28, 29, 30, 31,
814 32, 33, 34, 35, 36, 37, 38, 39,
815 40, 41, 42, 43, 44, 45, 46, 47,
816 48, 49, 50, 51, 52, 53, 54, 55,
817 56, 57, 58, 59, 60, 61, 62, 63
820 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
821 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
822 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
823 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
824 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
833 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
834 4, 5, 6, 7, /* ADAT 1 */
835 8, 9, 10, 11, /* ADAT 2 */
836 12, 13, 14, 15, /* ADAT 3 */
837 16, 17, 18, 19, /* ADAT 4 */
841 -1, -1, -1, -1, -1, -1, -1, -1,
842 -1, -1, -1, -1, -1, -1, -1, -1,
843 -1, -1, -1, -1, -1, -1, -1, -1,
844 -1, -1, -1, -1, -1, -1, -1, -1,
845 -1, -1, -1, -1, -1, -1, -1, -1,
848 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
856 -1, -1, -1, -1, -1, -1, -1, -1,
857 -1, -1, -1, -1, -1, -1, -1, -1,
858 -1, -1, -1, -1, -1, -1, -1, -1,
859 -1, -1, -1, -1, -1, -1, -1, -1,
860 -1, -1, -1, -1, -1, -1, -1, -1,
861 -1, -1, -1, -1, -1, -1, -1, -1,
864 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
867 10, 11, /* spdif in */
868 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
869 2, 3, 4, 5, /* AEB */
870 -1, -1, -1, -1, -1, -1,
871 -1, -1, -1, -1, -1, -1, -1, -1,
872 -1, -1, -1, -1, -1, -1, -1, -1,
873 -1, -1, -1, -1, -1, -1, -1, -1,
874 -1, -1, -1, -1, -1, -1, -1, -1,
875 -1, -1, -1, -1, -1, -1, -1, -1,
878 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
881 10, 11, /* spdif out */
882 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
883 6, 7, /* phone out */
884 2, 3, 4, 5, /* AEB */
886 -1, -1, -1, -1, -1, -1, -1, -1,
887 -1, -1, -1, -1, -1, -1, -1, -1,
888 -1, -1, -1, -1, -1, -1, -1, -1,
889 -1, -1, -1, -1, -1, -1, -1, -1,
890 -1, -1, -1, -1, -1, -1, -1, -1,
893 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
896 10, 11, /* spdif in */
897 12, 14, 16, 18, /* adat in */
898 2, 3, 4, 5, /* AEB */
900 -1, -1, -1, -1, -1, -1, -1, -1,
901 -1, -1, -1, -1, -1, -1, -1, -1,
902 -1, -1, -1, -1, -1, -1, -1, -1,
903 -1, -1, -1, -1, -1, -1, -1, -1,
904 -1, -1, -1, -1, -1, -1, -1, -1,
905 -1, -1, -1, -1, -1, -1, -1, -1
908 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
911 10, 11, /* spdif out */
912 12, 14, 16, 18, /* adat out */
913 6, 7, /* phone out */
914 2, 3, 4, 5, /* AEB */
915 -1, -1, -1, -1, -1, -1, -1, -1,
916 -1, -1, -1, -1, -1, -1, -1, -1,
917 -1, -1, -1, -1, -1, -1, -1, -1,
918 -1, -1, -1, -1, -1, -1, -1, -1,
919 -1, -1, -1, -1, -1, -1, -1, -1,
920 -1, -1, -1, -1, -1, -1, -1, -1
923 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
926 10, 11, /* spdif in */
927 12, 16, /* adat in */
928 2, 3, 4, 5, /* AEB */
930 -1, -1, -1, -1, -1, -1, -1, -1,
931 -1, -1, -1, -1, -1, -1, -1, -1,
932 -1, -1, -1, -1, -1, -1, -1, -1,
933 -1, -1, -1, -1, -1, -1, -1, -1,
934 -1, -1, -1, -1, -1, -1, -1, -1,
935 -1, -1, -1, -1, -1, -1, -1, -1
938 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
941 10, 11, /* spdif out */
942 12, 16, /* adat out */
943 6, 7, /* phone out */
944 2, 3, 4, 5, /* AEB */
946 -1, -1, -1, -1, -1, -1, -1, -1,
947 -1, -1, -1, -1, -1, -1, -1, -1,
948 -1, -1, -1, -1, -1, -1, -1, -1,
949 -1, -1, -1, -1, -1, -1, -1, -1,
950 -1, -1, -1, -1, -1, -1, -1, -1,
951 -1, -1, -1, -1, -1, -1, -1, -1
954 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
955 0, 1, 2, 3, 4, 5, 6, 7,
956 8, 9, 10, 11, 12, 13, 14, 15,
957 -1, -1, -1, -1, -1, -1, -1, -1,
958 -1, -1, -1, -1, -1, -1, -1, -1,
959 -1, -1, -1, -1, -1, -1, -1, -1,
960 -1, -1, -1, -1, -1, -1, -1, -1,
961 -1, -1, -1, -1, -1, -1, -1, -1,
962 -1, -1, -1, -1, -1, -1, -1, -1
968 struct snd_rawmidi *rmidi;
969 struct snd_rawmidi_substream *input;
970 struct snd_rawmidi_substream *output;
971 char istimer; /* timer in use */
972 struct timer_list timer;
984 int input; /* 0: LTC, 1:Video, 2: WC*/
985 int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */
986 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */
987 int samplerate; /* 0=44.1, 1=48, 2= freq from app */
988 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/
989 int term; /* 0 = off, 1 = on */
994 /* only one playback and/or capture stream */
995 struct snd_pcm_substream *capture_substream;
996 struct snd_pcm_substream *playback_substream;
998 char *card_name; /* for procinfo */
999 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
1003 int monitor_outs; /* set up monitoring outs init flag */
1005 u32 control_register; /* cached value */
1006 u32 control2_register; /* cached value */
1007 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */
1009 struct hdspm_midi midi[4];
1010 struct tasklet_struct midi_tasklet;
1012 size_t period_bytes;
1013 unsigned char ss_in_channels;
1014 unsigned char ds_in_channels;
1015 unsigned char qs_in_channels;
1016 unsigned char ss_out_channels;
1017 unsigned char ds_out_channels;
1018 unsigned char qs_out_channels;
1020 unsigned char max_channels_in;
1021 unsigned char max_channels_out;
1023 signed char *channel_map_in;
1024 signed char *channel_map_out;
1026 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
1027 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
1029 char **port_names_in;
1030 char **port_names_out;
1032 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
1033 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
1035 unsigned char *playback_buffer; /* suitably aligned address */
1036 unsigned char *capture_buffer; /* suitably aligned address */
1038 pid_t capture_pid; /* process id which uses capture */
1039 pid_t playback_pid; /* process id which uses capture */
1040 int running; /* running status */
1042 int last_external_sample_rate; /* samplerate mystic ... */
1043 int last_internal_sample_rate;
1044 int system_sample_rate;
1046 int dev; /* Hardware vars... */
1049 void __iomem *iobase;
1051 int irq_count; /* for debug */
1054 struct snd_card *card; /* one card */
1055 struct snd_pcm *pcm; /* has one pcm */
1056 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
1057 struct pci_dev *pci; /* and an pci info */
1060 /* fast alsa mixer */
1061 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
1062 /* but input to much, so not used */
1063 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
1064 /* full mixer accessible over mixer ioctl or hwdep-device */
1065 struct hdspm_mixer *mixer;
1067 struct hdspm_tco *tco; /* NULL if no TCO detected */
1069 const char *const *texts_autosync;
1070 int texts_autosync_items;
1072 cycles_t last_interrupt;
1074 unsigned int serial;
1076 struct hdspm_peak_rms peak_rms;
1080 static const struct pci_device_id snd_hdspm_ids[] = {
1082 .vendor = PCI_VENDOR_ID_XILINX,
1083 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
1084 .subvendor = PCI_ANY_ID,
1085 .subdevice = PCI_ANY_ID,
1092 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1095 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1096 struct hdspm *hdspm);
1097 static int snd_hdspm_create_pcm(struct snd_card *card,
1098 struct hdspm *hdspm);
1100 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1101 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1102 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1103 static int hdspm_autosync_ref(struct hdspm *hdspm);
1104 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1105 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1106 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1107 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1108 struct snd_pcm_substream *substream,
1109 unsigned int reg, int channels);
1111 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1112 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1113 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1114 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1116 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1117 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1118 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1122 static inline int HDSPM_bit2freq(int n)
1124 static const int bit2freq_tab[] = {
1125 0, 32000, 44100, 48000, 64000, 88200,
1126 96000, 128000, 176400, 192000 };
1129 return bit2freq_tab[n];
1132 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1134 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1138 /* Write/read to/from HDSPM with Adresses in Bytes
1139 not words but only 32Bit writes are allowed */
1141 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1144 writel(val, hdspm->iobase + reg);
1147 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1149 return readl(hdspm->iobase + reg);
1152 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1153 mixer is write only on hardware so we have to cache him for read
1154 each fader is a u32, but uses only the first 16 bit */
1156 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1159 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1162 return hdspm->mixer->ch[chan].in[in];
1165 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1168 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1170 return hdspm->mixer->ch[chan].pb[pb];
1173 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1174 unsigned int in, unsigned short data)
1176 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1180 HDSPM_MADI_mixerBase +
1181 ((in + 128 * chan) * sizeof(u32)),
1182 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1186 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1187 unsigned int pb, unsigned short data)
1189 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1193 HDSPM_MADI_mixerBase +
1194 ((64 + pb + 128 * chan) * sizeof(u32)),
1195 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1200 /* enable DMA for specific channels, now available for DSP-MADI */
1201 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1203 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1206 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1208 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1211 /* check if same process is writing and reading */
1212 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1214 unsigned long flags;
1217 spin_lock_irqsave(&hdspm->lock, flags);
1218 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1219 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1222 spin_unlock_irqrestore(&hdspm->lock, flags);
1226 /* round arbitary sample rates to commonly known rates */
1227 static int hdspm_round_frequency(int rate)
1237 /* QS and DS rates normally can not be detected
1238 * automatically by the card. Only exception is MADI
1239 * in 96k frame mode.
1241 * So if we read SS values (32 .. 48k), check for
1242 * user-provided DS/QS bits in the control register
1243 * and multiply the base frequency accordingly.
1245 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1247 if (rate <= 48000) {
1248 if (hdspm->control_register & HDSPM_QuadSpeed)
1250 else if (hdspm->control_register &
1257 /* check for external sample rate, returns the sample rate in Hz*/
1258 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1260 unsigned int status, status2;
1261 int syncref, rate = 0, rate_bits;
1263 switch (hdspm->io_type) {
1265 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1266 status = hdspm_read(hdspm, HDSPM_statusRegister);
1268 syncref = hdspm_autosync_ref(hdspm);
1270 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1271 /* Check WC sync and get sample rate */
1272 if (hdspm_wc_sync_check(hdspm))
1273 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1276 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1277 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1278 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1279 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1280 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1281 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1282 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1283 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1284 /* Check AES sync and get sample rate */
1285 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1286 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1287 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1291 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1292 /* Check TCO sync and get sample rate */
1293 if (hdspm_tco_sync_check(hdspm))
1294 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1298 } /* end switch(syncref) */
1302 status = hdspm_read(hdspm, HDSPM_statusRegister);
1304 if (!(status & HDSPM_madiLock)) {
1305 rate = 0; /* no lock */
1307 switch (status & (HDSPM_status1_freqMask)) {
1308 case HDSPM_status1_F_0*1:
1309 rate = 32000; break;
1310 case HDSPM_status1_F_0*2:
1311 rate = 44100; break;
1312 case HDSPM_status1_F_0*3:
1313 rate = 48000; break;
1314 case HDSPM_status1_F_0*4:
1315 rate = 64000; break;
1316 case HDSPM_status1_F_0*5:
1317 rate = 88200; break;
1318 case HDSPM_status1_F_0*6:
1319 rate = 96000; break;
1320 case HDSPM_status1_F_0*7:
1321 rate = 128000; break;
1322 case HDSPM_status1_F_0*8:
1323 rate = 176400; break;
1324 case HDSPM_status1_F_0*9:
1325 rate = 192000; break;
1336 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1337 status = hdspm_read(hdspm, HDSPM_statusRegister);
1340 /* if wordclock has synced freq and wordclock is valid */
1341 if ((status2 & HDSPM_wcLock) != 0 &&
1342 (status2 & HDSPM_SelSyncRef0) == 0) {
1344 rate_bits = status2 & HDSPM_wcFreqMask;
1347 switch (rate_bits) {
1348 case HDSPM_wcFreq32:
1351 case HDSPM_wcFreq44_1:
1354 case HDSPM_wcFreq48:
1357 case HDSPM_wcFreq64:
1360 case HDSPM_wcFreq88_2:
1363 case HDSPM_wcFreq96:
1366 case HDSPM_wcFreq128:
1369 case HDSPM_wcFreq176_4:
1372 case HDSPM_wcFreq192:
1381 /* if rate detected and Syncref is Word than have it,
1382 * word has priority to MADI
1385 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1386 return hdspm_rate_multiplier(hdspm, rate);
1388 /* maybe a madi input (which is taken if sel sync is madi) */
1389 if (status & HDSPM_madiLock) {
1390 rate_bits = status & HDSPM_madiFreqMask;
1392 switch (rate_bits) {
1393 case HDSPM_madiFreq32:
1396 case HDSPM_madiFreq44_1:
1399 case HDSPM_madiFreq48:
1402 case HDSPM_madiFreq64:
1405 case HDSPM_madiFreq88_2:
1408 case HDSPM_madiFreq96:
1411 case HDSPM_madiFreq128:
1414 case HDSPM_madiFreq176_4:
1417 case HDSPM_madiFreq192:
1425 } /* endif HDSPM_madiLock */
1427 /* check sample rate from TCO or SYNC_IN */
1429 bool is_valid_input = 0;
1432 syncref = hdspm_autosync_ref(hdspm);
1433 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1435 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1436 hdspm_tco_sync_check(hdspm));
1437 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1439 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1440 hdspm_sync_in_sync_check(hdspm));
1443 if (is_valid_input && has_sync) {
1444 rate = hdspm_round_frequency(
1445 hdspm_get_pll_freq(hdspm));
1449 rate = hdspm_rate_multiplier(hdspm, rate);
1457 /* return latency in samples per period */
1458 static int hdspm_get_latency(struct hdspm *hdspm)
1462 n = hdspm_decode_latency(hdspm->control_register);
1464 /* Special case for new RME cards with 32 samples period size.
1465 * The three latency bits in the control register
1466 * (HDSP_LatencyMask) encode latency values of 64 samples as
1467 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1468 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1469 * it corresponds to 32 samples.
1471 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1474 return 1 << (n + 6);
1477 /* Latency function */
1478 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1480 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1484 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1488 position = hdspm_read(hdspm, HDSPM_statusRegister);
1490 switch (hdspm->io_type) {
1493 position &= HDSPM_BufferPositionMask;
1494 position /= 4; /* Bytes per sample */
1497 position = (position & HDSPM_BufferID) ?
1498 (hdspm->period_bytes / 4) : 0;
1505 static inline void hdspm_start_audio(struct hdspm * s)
1507 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1508 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1511 static inline void hdspm_stop_audio(struct hdspm * s)
1513 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1514 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1517 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1518 static void hdspm_silence_playback(struct hdspm *hdspm)
1521 int n = hdspm->period_bytes;
1522 void *buf = hdspm->playback_buffer;
1527 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1529 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1533 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1537 spin_lock_irq(&s->lock);
1540 /* Special case for new RME cards like RayDAT/AIO which
1541 * support period sizes of 32 samples. Since latency is
1542 * encoded in the three bits of HDSP_LatencyMask, we can only
1543 * have values from 0 .. 7. While 0 still means 64 samples and
1544 * 6 represents 4096 samples on all cards, 7 represents 8192
1545 * on older cards and 32 samples on new cards.
1547 * In other words, period size in samples is calculated by
1548 * 2^(n+6) with n ranging from 0 .. 7.
1560 s->control_register &= ~HDSPM_LatencyMask;
1561 s->control_register |= hdspm_encode_latency(n);
1563 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1565 hdspm_compute_period_size(s);
1567 spin_unlock_irq(&s->lock);
1572 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1579 switch (hdspm->io_type) {
1582 freq_const = 110069313433624ULL;
1586 freq_const = 104857600000000ULL;
1589 freq_const = 131072000000000ULL;
1596 return div_u64(freq_const, period);
1600 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1606 else if (rate >= 56000)
1609 switch (hdspm->io_type) {
1611 n = 131072000000000ULL; /* 125 MHz */
1615 n = 110069313433624ULL; /* 105 MHz */
1619 n = 104857600000000ULL; /* 100 MHz */
1626 n = div_u64(n, rate);
1627 /* n should be less than 2^32 for being written to FREQ register */
1628 snd_BUG_ON(n >> 32);
1629 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1632 /* dummy set rate lets see what happens */
1633 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1638 int current_speed, target_speed;
1640 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1641 it (e.g. during module initialization).
1644 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1647 if (called_internally) {
1649 /* request from ctl or card initialization
1650 just make a warning an remember setting
1651 for future master mode switching */
1653 dev_warn(hdspm->card->dev,
1654 "Warning: device is not running as a clock master.\n");
1658 /* hw_param request while in AutoSync mode */
1660 hdspm_external_sample_rate(hdspm);
1662 if (hdspm_autosync_ref(hdspm) ==
1663 HDSPM_AUTOSYNC_FROM_NONE) {
1665 dev_warn(hdspm->card->dev,
1666 "Detected no Externel Sync\n");
1669 } else if (rate != external_freq) {
1671 dev_warn(hdspm->card->dev,
1672 "Warning: No AutoSync source for requested rate\n");
1678 current_rate = hdspm->system_sample_rate;
1680 /* Changing between Singe, Double and Quad speed is not
1681 allowed if any substreams are open. This is because such a change
1682 causes a shift in the location of the DMA buffers and a reduction
1683 in the number of available buffers.
1685 Note that a similar but essentially insoluble problem exists for
1686 externally-driven rate changes. All we can do is to flag rate
1687 changes in the read/write routines.
1690 if (current_rate <= 48000)
1691 current_speed = HDSPM_SPEED_SINGLE;
1692 else if (current_rate <= 96000)
1693 current_speed = HDSPM_SPEED_DOUBLE;
1695 current_speed = HDSPM_SPEED_QUAD;
1698 target_speed = HDSPM_SPEED_SINGLE;
1699 else if (rate <= 96000)
1700 target_speed = HDSPM_SPEED_DOUBLE;
1702 target_speed = HDSPM_SPEED_QUAD;
1706 rate_bits = HDSPM_Frequency32KHz;
1709 rate_bits = HDSPM_Frequency44_1KHz;
1712 rate_bits = HDSPM_Frequency48KHz;
1715 rate_bits = HDSPM_Frequency64KHz;
1718 rate_bits = HDSPM_Frequency88_2KHz;
1721 rate_bits = HDSPM_Frequency96KHz;
1724 rate_bits = HDSPM_Frequency128KHz;
1727 rate_bits = HDSPM_Frequency176_4KHz;
1730 rate_bits = HDSPM_Frequency192KHz;
1736 if (current_speed != target_speed
1737 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1738 dev_err(hdspm->card->dev,
1739 "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n",
1740 hdspm_speed_names[current_speed],
1741 hdspm_speed_names[target_speed],
1742 hdspm->capture_pid, hdspm->playback_pid);
1746 hdspm->control_register &= ~HDSPM_FrequencyMask;
1747 hdspm->control_register |= rate_bits;
1748 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1750 /* For AES32, need to set DDS value in FREQ register
1751 For MADI, also apparently */
1752 hdspm_set_dds_value(hdspm, rate);
1754 if (AES32 == hdspm->io_type && rate != current_rate)
1755 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1757 hdspm->system_sample_rate = rate;
1759 if (rate <= 48000) {
1760 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1761 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1762 hdspm->max_channels_in = hdspm->ss_in_channels;
1763 hdspm->max_channels_out = hdspm->ss_out_channels;
1764 hdspm->port_names_in = hdspm->port_names_in_ss;
1765 hdspm->port_names_out = hdspm->port_names_out_ss;
1766 } else if (rate <= 96000) {
1767 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1768 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1769 hdspm->max_channels_in = hdspm->ds_in_channels;
1770 hdspm->max_channels_out = hdspm->ds_out_channels;
1771 hdspm->port_names_in = hdspm->port_names_in_ds;
1772 hdspm->port_names_out = hdspm->port_names_out_ds;
1774 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1775 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1776 hdspm->max_channels_in = hdspm->qs_in_channels;
1777 hdspm->max_channels_out = hdspm->qs_out_channels;
1778 hdspm->port_names_in = hdspm->port_names_in_qs;
1779 hdspm->port_names_out = hdspm->port_names_out_qs;
1788 /* mainly for init to 0 on load */
1789 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1794 if (sgain > UNITY_GAIN)
1801 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1802 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1803 hdspm_write_in_gain(hdspm, i, j, gain);
1804 hdspm_write_pb_gain(hdspm, i, j, gain);
1808 /*----------------------------------------------------------------------------
1810 ----------------------------------------------------------------------------*/
1812 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1815 /* the hardware already does the relevant bit-mask with 0xff */
1816 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1819 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1822 /* the hardware already does the relevant bit-mask with 0xff */
1823 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1826 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1828 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1831 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1833 int fifo_bytes_used;
1835 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1837 if (fifo_bytes_used < 128)
1838 return 128 - fifo_bytes_used;
1843 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1845 while (snd_hdspm_midi_input_available (hdspm, id))
1846 snd_hdspm_midi_read_byte (hdspm, id);
1849 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1851 unsigned long flags;
1855 unsigned char buf[128];
1857 /* Output is not interrupt driven */
1859 spin_lock_irqsave (&hmidi->lock, flags);
1860 if (hmidi->output &&
1861 !snd_rawmidi_transmit_empty (hmidi->output)) {
1862 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1864 if (n_pending > 0) {
1865 if (n_pending > (int)sizeof (buf))
1866 n_pending = sizeof (buf);
1868 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1871 for (i = 0; i < to_write; ++i)
1872 snd_hdspm_midi_write_byte (hmidi->hdspm,
1878 spin_unlock_irqrestore (&hmidi->lock, flags);
1882 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1884 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1887 unsigned long flags;
1891 spin_lock_irqsave (&hmidi->lock, flags);
1892 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1893 if (n_pending > 0) {
1895 if (n_pending > (int)sizeof (buf))
1896 n_pending = sizeof (buf);
1897 for (i = 0; i < n_pending; ++i)
1898 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1901 snd_rawmidi_receive (hmidi->input, buf,
1904 /* flush the MIDI input FIFO */
1906 snd_hdspm_midi_read_byte (hmidi->hdspm,
1911 spin_unlock_irqrestore(&hmidi->lock, flags);
1913 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1914 hmidi->hdspm->control_register |= hmidi->ie;
1915 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1916 hmidi->hdspm->control_register);
1917 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1919 return snd_hdspm_midi_output_write (hmidi);
1923 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1925 struct hdspm *hdspm;
1926 struct hdspm_midi *hmidi;
1927 unsigned long flags;
1929 hmidi = substream->rmidi->private_data;
1930 hdspm = hmidi->hdspm;
1932 spin_lock_irqsave (&hdspm->lock, flags);
1934 if (!(hdspm->control_register & hmidi->ie)) {
1935 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1936 hdspm->control_register |= hmidi->ie;
1939 hdspm->control_register &= ~hmidi->ie;
1942 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1943 spin_unlock_irqrestore (&hdspm->lock, flags);
1946 static void snd_hdspm_midi_output_timer(unsigned long data)
1948 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1949 unsigned long flags;
1951 snd_hdspm_midi_output_write(hmidi);
1952 spin_lock_irqsave (&hmidi->lock, flags);
1954 /* this does not bump hmidi->istimer, because the
1955 kernel automatically removed the timer when it
1956 expired, and we are now adding it back, thus
1957 leaving istimer wherever it was set before.
1960 if (hmidi->istimer) {
1961 hmidi->timer.expires = 1 + jiffies;
1962 add_timer(&hmidi->timer);
1965 spin_unlock_irqrestore (&hmidi->lock, flags);
1969 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1971 struct hdspm_midi *hmidi;
1972 unsigned long flags;
1974 hmidi = substream->rmidi->private_data;
1975 spin_lock_irqsave (&hmidi->lock, flags);
1977 if (!hmidi->istimer) {
1978 init_timer(&hmidi->timer);
1979 hmidi->timer.function = snd_hdspm_midi_output_timer;
1980 hmidi->timer.data = (unsigned long) hmidi;
1981 hmidi->timer.expires = 1 + jiffies;
1982 add_timer(&hmidi->timer);
1986 if (hmidi->istimer && --hmidi->istimer <= 0)
1987 del_timer (&hmidi->timer);
1989 spin_unlock_irqrestore (&hmidi->lock, flags);
1991 snd_hdspm_midi_output_write(hmidi);
1994 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1996 struct hdspm_midi *hmidi;
1998 hmidi = substream->rmidi->private_data;
1999 spin_lock_irq (&hmidi->lock);
2000 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
2001 hmidi->input = substream;
2002 spin_unlock_irq (&hmidi->lock);
2007 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
2009 struct hdspm_midi *hmidi;
2011 hmidi = substream->rmidi->private_data;
2012 spin_lock_irq (&hmidi->lock);
2013 hmidi->output = substream;
2014 spin_unlock_irq (&hmidi->lock);
2019 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
2021 struct hdspm_midi *hmidi;
2023 snd_hdspm_midi_input_trigger (substream, 0);
2025 hmidi = substream->rmidi->private_data;
2026 spin_lock_irq (&hmidi->lock);
2027 hmidi->input = NULL;
2028 spin_unlock_irq (&hmidi->lock);
2033 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
2035 struct hdspm_midi *hmidi;
2037 snd_hdspm_midi_output_trigger (substream, 0);
2039 hmidi = substream->rmidi->private_data;
2040 spin_lock_irq (&hmidi->lock);
2041 hmidi->output = NULL;
2042 spin_unlock_irq (&hmidi->lock);
2047 static struct snd_rawmidi_ops snd_hdspm_midi_output =
2049 .open = snd_hdspm_midi_output_open,
2050 .close = snd_hdspm_midi_output_close,
2051 .trigger = snd_hdspm_midi_output_trigger,
2054 static struct snd_rawmidi_ops snd_hdspm_midi_input =
2056 .open = snd_hdspm_midi_input_open,
2057 .close = snd_hdspm_midi_input_close,
2058 .trigger = snd_hdspm_midi_input_trigger,
2061 static int snd_hdspm_create_midi(struct snd_card *card,
2062 struct hdspm *hdspm, int id)
2067 hdspm->midi[id].id = id;
2068 hdspm->midi[id].hdspm = hdspm;
2069 spin_lock_init (&hdspm->midi[id].lock);
2072 if (MADIface == hdspm->io_type) {
2073 /* MIDI-over-MADI on HDSPe MADIface */
2074 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2075 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2076 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2077 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2078 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2079 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2081 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2082 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2083 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2084 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2085 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2086 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2088 } else if (1 == id) {
2089 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2090 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2091 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2092 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2093 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2094 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2095 } else if ((2 == id) && (MADI == hdspm->io_type)) {
2096 /* MIDI-over-MADI on HDSPe MADI */
2097 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2098 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2099 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2100 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2101 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2102 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2103 } else if (2 == id) {
2104 /* TCO MTC, read only */
2105 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2106 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2107 hdspm->midi[2].dataOut = -1;
2108 hdspm->midi[2].statusOut = -1;
2109 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2110 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2111 } else if (3 == id) {
2112 /* TCO MTC on HDSPe MADI */
2113 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2114 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2115 hdspm->midi[3].dataOut = -1;
2116 hdspm->midi[3].statusOut = -1;
2117 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2118 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2121 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2122 (MADIface == hdspm->io_type)))) {
2123 if ((id == 0) && (MADIface == hdspm->io_type)) {
2124 sprintf(buf, "%s MIDIoverMADI", card->shortname);
2125 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2126 sprintf(buf, "%s MIDIoverMADI", card->shortname);
2128 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
2130 err = snd_rawmidi_new(card, buf, id, 1, 1,
2131 &hdspm->midi[id].rmidi);
2135 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
2137 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2139 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2140 SNDRV_RAWMIDI_STREAM_OUTPUT,
2141 &snd_hdspm_midi_output);
2142 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2143 SNDRV_RAWMIDI_STREAM_INPUT,
2144 &snd_hdspm_midi_input);
2146 hdspm->midi[id].rmidi->info_flags |=
2147 SNDRV_RAWMIDI_INFO_OUTPUT |
2148 SNDRV_RAWMIDI_INFO_INPUT |
2149 SNDRV_RAWMIDI_INFO_DUPLEX;
2151 /* TCO MTC, read only */
2152 sprintf(buf, "%s MTC %d", card->shortname, id+1);
2153 err = snd_rawmidi_new(card, buf, id, 1, 1,
2154 &hdspm->midi[id].rmidi);
2158 sprintf(hdspm->midi[id].rmidi->name,
2159 "%s MTC %d", card->id, id+1);
2160 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2162 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2163 SNDRV_RAWMIDI_STREAM_INPUT,
2164 &snd_hdspm_midi_input);
2166 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2173 static void hdspm_midi_tasklet(unsigned long arg)
2175 struct hdspm *hdspm = (struct hdspm *)arg;
2178 while (i < hdspm->midiPorts) {
2179 if (hdspm->midi[i].pending)
2180 snd_hdspm_midi_input_read(&hdspm->midi[i]);
2187 /*-----------------------------------------------------------------------------
2189 ----------------------------------------------------------------------------*/
2191 /* get the system sample rate which is set */
2194 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2196 unsigned int period, rate;
2198 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2199 rate = hdspm_calc_dds_value(hdspm, period);
2205 * Calculate the real sample rate from the
2206 * current DDS value.
2208 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2212 rate = hdspm_get_pll_freq(hdspm);
2214 if (rate > 207000) {
2215 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2216 if (0 == hdspm_system_clock_mode(hdspm)) {
2217 /* master mode, return internal sample rate */
2218 rate = hdspm->system_sample_rate;
2220 /* slave mode, return external sample rate */
2221 rate = hdspm_external_sample_rate(hdspm);
2229 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2230 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2233 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2234 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2235 .info = snd_hdspm_info_system_sample_rate, \
2236 .put = snd_hdspm_put_system_sample_rate, \
2237 .get = snd_hdspm_get_system_sample_rate \
2240 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2241 struct snd_ctl_elem_info *uinfo)
2243 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2245 uinfo->value.integer.min = 27000;
2246 uinfo->value.integer.max = 207000;
2247 uinfo->value.integer.step = 1;
2252 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2253 struct snd_ctl_elem_value *
2256 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2258 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2262 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2263 struct snd_ctl_elem_value *
2266 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2268 hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2274 * Returns the WordClock sample rate class for the given card.
2276 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2280 switch (hdspm->io_type) {
2283 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2284 return (status >> 16) & 0xF;
2287 status = hdspm_read(hdspm, HDSPM_statusRegister);
2288 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2299 * Returns the TCO sample rate class for the given card.
2301 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2306 switch (hdspm->io_type) {
2309 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2310 return (status >> 20) & 0xF;
2313 status = hdspm_read(hdspm, HDSPM_statusRegister);
2314 return (status >> 1) & 0xF;
2325 * Returns the SYNC_IN sample rate class for the given card.
2327 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2332 switch (hdspm->io_type) {
2335 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2336 return (status >> 12) & 0xF;
2347 * Returns the AES sample rate class for the given card.
2349 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2353 switch (hdspm->io_type) {
2355 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2356 return (timecode >> (4*index)) & 0xF;
2365 * Returns the sample rate class for input source <idx> for
2366 * 'new style' cards like the AIO and RayDAT.
2368 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2370 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2372 return (status >> (idx*4)) & 0xF;
2375 #define ENUMERATED_CTL_INFO(info, texts) \
2376 snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts)
2379 /* Helper function to query the external sample rate and return the
2380 * corresponding enum to be returned to userspace.
2382 static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2384 int rate = hdspm_external_sample_rate(hdspm);
2385 int i, selected_rate = 0;
2386 for (i = 1; i < 10; i++)
2387 if (HDSPM_bit2freq(i) == rate) {
2391 return selected_rate;
2395 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2396 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2398 .private_value = xindex, \
2399 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2400 .info = snd_hdspm_info_autosync_sample_rate, \
2401 .get = snd_hdspm_get_autosync_sample_rate \
2405 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2406 struct snd_ctl_elem_info *uinfo)
2408 ENUMERATED_CTL_INFO(uinfo, texts_freq);
2413 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2414 struct snd_ctl_elem_value *
2417 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2419 switch (hdspm->io_type) {
2421 switch (kcontrol->private_value) {
2423 ucontrol->value.enumerated.item[0] =
2424 hdspm_get_wc_sample_rate(hdspm);
2427 ucontrol->value.enumerated.item[0] =
2428 hdspm_get_tco_sample_rate(hdspm);
2431 ucontrol->value.enumerated.item[0] =
2432 hdspm_get_sync_in_sample_rate(hdspm);
2435 ucontrol->value.enumerated.item[0] =
2436 hdspm_get_s1_sample_rate(hdspm,
2437 kcontrol->private_value-1);
2442 switch (kcontrol->private_value) {
2444 ucontrol->value.enumerated.item[0] =
2445 hdspm_get_wc_sample_rate(hdspm);
2448 ucontrol->value.enumerated.item[0] =
2449 hdspm_get_tco_sample_rate(hdspm);
2451 case 5: /* SYNC_IN */
2452 ucontrol->value.enumerated.item[0] =
2453 hdspm_get_sync_in_sample_rate(hdspm);
2456 ucontrol->value.enumerated.item[0] =
2457 hdspm_get_s1_sample_rate(hdspm,
2458 kcontrol->private_value-1);
2464 switch (kcontrol->private_value) {
2466 ucontrol->value.enumerated.item[0] =
2467 hdspm_get_wc_sample_rate(hdspm);
2470 ucontrol->value.enumerated.item[0] =
2471 hdspm_get_tco_sample_rate(hdspm);
2473 case 10: /* SYNC_IN */
2474 ucontrol->value.enumerated.item[0] =
2475 hdspm_get_sync_in_sample_rate(hdspm);
2477 case 11: /* External Rate */
2478 ucontrol->value.enumerated.item[0] =
2479 hdspm_external_rate_to_enum(hdspm);
2481 default: /* AES1 to AES8 */
2482 ucontrol->value.enumerated.item[0] =
2483 hdspm_get_aes_sample_rate(hdspm,
2484 kcontrol->private_value -
2485 HDSPM_AES32_AUTOSYNC_FROM_AES1);
2492 ucontrol->value.enumerated.item[0] =
2493 hdspm_external_rate_to_enum(hdspm);
2503 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2504 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2507 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2508 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2509 .info = snd_hdspm_info_system_clock_mode, \
2510 .get = snd_hdspm_get_system_clock_mode, \
2511 .put = snd_hdspm_put_system_clock_mode, \
2516 * Returns the system clock mode for the given card.
2517 * @returns 0 - master, 1 - slave
2519 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2521 switch (hdspm->io_type) {
2524 if (hdspm->settings_register & HDSPM_c0Master)
2529 if (hdspm->control_register & HDSPM_ClockModeMaster)
2538 * Sets the system clock mode.
2539 * @param mode 0 - master, 1 - slave
2541 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2543 hdspm_set_toggle_setting(hdspm,
2544 (hdspm_is_raydat_or_aio(hdspm)) ?
2545 HDSPM_c0Master : HDSPM_ClockModeMaster,
2550 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2551 struct snd_ctl_elem_info *uinfo)
2553 static const char *const texts[] = { "Master", "AutoSync" };
2554 ENUMERATED_CTL_INFO(uinfo, texts);
2558 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2559 struct snd_ctl_elem_value *ucontrol)
2561 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2563 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2567 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2568 struct snd_ctl_elem_value *ucontrol)
2570 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2573 if (!snd_hdspm_use_is_exclusive(hdspm))
2576 val = ucontrol->value.enumerated.item[0];
2582 hdspm_set_system_clock_mode(hdspm, val);
2588 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2589 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2592 .info = snd_hdspm_info_clock_source, \
2593 .get = snd_hdspm_get_clock_source, \
2594 .put = snd_hdspm_put_clock_source \
2598 static int hdspm_clock_source(struct hdspm * hdspm)
2600 switch (hdspm->system_sample_rate) {
2601 case 32000: return 0;
2602 case 44100: return 1;
2603 case 48000: return 2;
2604 case 64000: return 3;
2605 case 88200: return 4;
2606 case 96000: return 5;
2607 case 128000: return 6;
2608 case 176400: return 7;
2609 case 192000: return 8;
2615 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2620 rate = 32000; break;
2622 rate = 44100; break;
2624 rate = 48000; break;
2626 rate = 64000; break;
2628 rate = 88200; break;
2630 rate = 96000; break;
2632 rate = 128000; break;
2634 rate = 176400; break;
2636 rate = 192000; break;
2640 hdspm_set_rate(hdspm, rate, 1);
2644 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2645 struct snd_ctl_elem_info *uinfo)
2647 return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1);
2650 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2651 struct snd_ctl_elem_value *ucontrol)
2653 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2655 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2659 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2660 struct snd_ctl_elem_value *ucontrol)
2662 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2666 if (!snd_hdspm_use_is_exclusive(hdspm))
2668 val = ucontrol->value.enumerated.item[0];
2673 spin_lock_irq(&hdspm->lock);
2674 if (val != hdspm_clock_source(hdspm))
2675 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2678 spin_unlock_irq(&hdspm->lock);
2683 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2684 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2687 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2688 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2689 .info = snd_hdspm_info_pref_sync_ref, \
2690 .get = snd_hdspm_get_pref_sync_ref, \
2691 .put = snd_hdspm_put_pref_sync_ref \
2696 * Returns the current preferred sync reference setting.
2697 * The semantics of the return value are depending on the
2698 * card, please see the comments for clarification.
2700 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2702 switch (hdspm->io_type) {
2704 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2705 case 0: return 0; /* WC */
2706 case HDSPM_SyncRef0: return 1; /* AES 1 */
2707 case HDSPM_SyncRef1: return 2; /* AES 2 */
2708 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2709 case HDSPM_SyncRef2: return 4; /* AES 4 */
2710 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2711 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2712 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2713 return 7; /* AES 7 */
2714 case HDSPM_SyncRef3: return 8; /* AES 8 */
2715 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2722 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2723 case 0: return 0; /* WC */
2724 case HDSPM_SyncRef0: return 1; /* MADI */
2725 case HDSPM_SyncRef1: return 2; /* TCO */
2726 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2727 return 3; /* SYNC_IN */
2730 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2731 case 0: return 0; /* WC */
2732 case HDSPM_SyncRef0: return 1; /* MADI */
2733 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2734 return 2; /* SYNC_IN */
2741 switch ((hdspm->settings_register &
2742 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2743 case 0: return 0; /* WC */
2744 case 3: return 1; /* ADAT 1 */
2745 case 4: return 2; /* ADAT 2 */
2746 case 5: return 3; /* ADAT 3 */
2747 case 6: return 4; /* ADAT 4 */
2748 case 1: return 5; /* AES */
2749 case 2: return 6; /* SPDIF */
2750 case 9: return 7; /* TCO */
2751 case 10: return 8; /* SYNC_IN */
2754 switch ((hdspm->settings_register &
2755 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2756 case 0: return 0; /* WC */
2757 case 3: return 1; /* ADAT 1 */
2758 case 4: return 2; /* ADAT 2 */
2759 case 5: return 3; /* ADAT 3 */
2760 case 6: return 4; /* ADAT 4 */
2761 case 1: return 5; /* AES */
2762 case 2: return 6; /* SPDIF */
2763 case 10: return 7; /* SYNC_IN */
2771 switch ((hdspm->settings_register &
2772 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2773 case 0: return 0; /* WC */
2774 case 3: return 1; /* ADAT */
2775 case 1: return 2; /* AES */
2776 case 2: return 3; /* SPDIF */
2777 case 9: return 4; /* TCO */
2778 case 10: return 5; /* SYNC_IN */
2781 switch ((hdspm->settings_register &
2782 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2783 case 0: return 0; /* WC */
2784 case 3: return 1; /* ADAT */
2785 case 1: return 2; /* AES */
2786 case 2: return 3; /* SPDIF */
2787 case 10: return 4; /* SYNC_IN */
2799 * Set the preferred sync reference to <pref>. The semantics
2800 * of <pref> are depending on the card type, see the comments
2801 * for clarification.
2803 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2807 switch (hdspm->io_type) {
2809 hdspm->control_register &= ~HDSPM_SyncRefMask;
2814 hdspm->control_register |= HDSPM_SyncRef0;
2817 hdspm->control_register |= HDSPM_SyncRef1;
2820 hdspm->control_register |=
2821 HDSPM_SyncRef1+HDSPM_SyncRef0;
2824 hdspm->control_register |= HDSPM_SyncRef2;
2827 hdspm->control_register |=
2828 HDSPM_SyncRef2+HDSPM_SyncRef0;
2831 hdspm->control_register |=
2832 HDSPM_SyncRef2+HDSPM_SyncRef1;
2835 hdspm->control_register |=
2836 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2839 hdspm->control_register |= HDSPM_SyncRef3;
2842 hdspm->control_register |=
2843 HDSPM_SyncRef3+HDSPM_SyncRef0;
2853 hdspm->control_register &= ~HDSPM_SyncRefMask;
2859 hdspm->control_register |= HDSPM_SyncRef0;
2862 hdspm->control_register |= HDSPM_SyncRef1;
2864 case 3: /* SYNC_IN */
2865 hdspm->control_register |=
2866 HDSPM_SyncRef0+HDSPM_SyncRef1;
2876 hdspm->control_register |= HDSPM_SyncRef0;
2878 case 2: /* SYNC_IN */
2879 hdspm->control_register |=
2880 HDSPM_SyncRef0+HDSPM_SyncRef1;
2892 case 0: p = 0; break; /* WC */
2893 case 1: p = 3; break; /* ADAT 1 */
2894 case 2: p = 4; break; /* ADAT 2 */
2895 case 3: p = 5; break; /* ADAT 3 */
2896 case 4: p = 6; break; /* ADAT 4 */
2897 case 5: p = 1; break; /* AES */
2898 case 6: p = 2; break; /* SPDIF */
2899 case 7: p = 9; break; /* TCO */
2900 case 8: p = 10; break; /* SYNC_IN */
2905 case 0: p = 0; break; /* WC */
2906 case 1: p = 3; break; /* ADAT 1 */
2907 case 2: p = 4; break; /* ADAT 2 */
2908 case 3: p = 5; break; /* ADAT 3 */
2909 case 4: p = 6; break; /* ADAT 4 */
2910 case 5: p = 1; break; /* AES */
2911 case 6: p = 2; break; /* SPDIF */
2912 case 7: p = 10; break; /* SYNC_IN */
2921 case 0: p = 0; break; /* WC */
2922 case 1: p = 3; break; /* ADAT */
2923 case 2: p = 1; break; /* AES */
2924 case 3: p = 2; break; /* SPDIF */
2925 case 4: p = 9; break; /* TCO */
2926 case 5: p = 10; break; /* SYNC_IN */
2931 case 0: p = 0; break; /* WC */
2932 case 1: p = 3; break; /* ADAT */
2933 case 2: p = 1; break; /* AES */
2934 case 3: p = 2; break; /* SPDIF */
2935 case 4: p = 10; break; /* SYNC_IN */
2942 switch (hdspm->io_type) {
2945 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2946 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2947 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2953 hdspm_write(hdspm, HDSPM_controlRegister,
2954 hdspm->control_register);
2961 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2962 struct snd_ctl_elem_info *uinfo)
2964 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2966 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2971 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2972 struct snd_ctl_elem_value *ucontrol)
2974 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2975 int psf = hdspm_pref_sync_ref(hdspm);
2978 ucontrol->value.enumerated.item[0] = psf;
2985 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2986 struct snd_ctl_elem_value *ucontrol)
2988 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2989 int val, change = 0;
2991 if (!snd_hdspm_use_is_exclusive(hdspm))
2994 val = ucontrol->value.enumerated.item[0];
2998 else if (val >= hdspm->texts_autosync_items)
2999 val = hdspm->texts_autosync_items-1;
3001 spin_lock_irq(&hdspm->lock);
3002 if (val != hdspm_pref_sync_ref(hdspm))
3003 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
3005 spin_unlock_irq(&hdspm->lock);
3010 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
3011 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3014 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
3015 .info = snd_hdspm_info_autosync_ref, \
3016 .get = snd_hdspm_get_autosync_ref, \
3019 static int hdspm_autosync_ref(struct hdspm *hdspm)
3021 /* This looks at the autosync selected sync reference */
3022 if (AES32 == hdspm->io_type) {
3024 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
3025 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
3026 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) &&
3027 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) {
3030 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
3032 } else if (MADI == hdspm->io_type) {
3034 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3035 switch (status2 & HDSPM_SelSyncRefMask) {
3036 case HDSPM_SelSyncRef_WORD:
3037 return HDSPM_AUTOSYNC_FROM_WORD;
3038 case HDSPM_SelSyncRef_MADI:
3039 return HDSPM_AUTOSYNC_FROM_MADI;
3040 case HDSPM_SelSyncRef_TCO:
3041 return HDSPM_AUTOSYNC_FROM_TCO;
3042 case HDSPM_SelSyncRef_SyncIn:
3043 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
3044 case HDSPM_SelSyncRef_NVALID:
3045 return HDSPM_AUTOSYNC_FROM_NONE;
3047 return HDSPM_AUTOSYNC_FROM_NONE;
3055 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
3056 struct snd_ctl_elem_info *uinfo)
3058 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3060 if (AES32 == hdspm->io_type) {
3061 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3",
3062 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
3064 ENUMERATED_CTL_INFO(uinfo, texts);
3065 } else if (MADI == hdspm->io_type) {
3066 static const char *const texts[] = {"Word Clock", "MADI", "TCO",
3067 "Sync In", "None" };
3069 ENUMERATED_CTL_INFO(uinfo, texts);
3074 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3075 struct snd_ctl_elem_value *ucontrol)
3077 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3079 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3085 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3086 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3088 .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3089 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3090 .info = snd_hdspm_info_tco_video_input_format, \
3091 .get = snd_hdspm_get_tco_video_input_format, \
3094 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3095 struct snd_ctl_elem_info *uinfo)
3097 static const char *const texts[] = {"No video", "NTSC", "PAL"};
3098 ENUMERATED_CTL_INFO(uinfo, texts);
3102 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3103 struct snd_ctl_elem_value *ucontrol)
3108 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3109 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3110 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3111 HDSPM_TCO1_Video_Input_Format_PAL)) {
3112 case HDSPM_TCO1_Video_Input_Format_NTSC:
3116 case HDSPM_TCO1_Video_Input_Format_PAL:
3125 ucontrol->value.enumerated.item[0] = ret;
3131 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3132 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3134 .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3135 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3136 .info = snd_hdspm_info_tco_ltc_frames, \
3137 .get = snd_hdspm_get_tco_ltc_frames, \
3140 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3141 struct snd_ctl_elem_info *uinfo)
3143 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3145 ENUMERATED_CTL_INFO(uinfo, texts);
3149 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3154 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3155 if (status & HDSPM_TCO1_LTC_Input_valid) {
3156 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3157 HDSPM_TCO1_LTC_Format_MSB)) {
3162 case HDSPM_TCO1_LTC_Format_LSB:
3166 case HDSPM_TCO1_LTC_Format_MSB:
3180 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3181 struct snd_ctl_elem_value *ucontrol)
3183 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3185 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3189 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3190 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3192 .private_value = xindex, \
3193 .info = snd_hdspm_info_toggle_setting, \
3194 .get = snd_hdspm_get_toggle_setting, \
3195 .put = snd_hdspm_put_toggle_setting \
3198 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3202 if (hdspm_is_raydat_or_aio(hdspm))
3203 reg = hdspm->settings_register;
3205 reg = hdspm->control_register;
3207 return (reg & regmask) ? 1 : 0;
3210 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3215 if (hdspm_is_raydat_or_aio(hdspm)) {
3216 reg = &(hdspm->settings_register);
3217 target_reg = HDSPM_WR_SETTINGS;
3219 reg = &(hdspm->control_register);
3220 target_reg = HDSPM_controlRegister;
3228 hdspm_write(hdspm, target_reg, *reg);
3233 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info
3235 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3236 struct snd_ctl_elem_value *ucontrol)
3238 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3239 u32 regmask = kcontrol->private_value;
3241 spin_lock_irq(&hdspm->lock);
3242 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3243 spin_unlock_irq(&hdspm->lock);
3247 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3248 struct snd_ctl_elem_value *ucontrol)
3250 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3251 u32 regmask = kcontrol->private_value;
3255 if (!snd_hdspm_use_is_exclusive(hdspm))
3257 val = ucontrol->value.integer.value[0] & 1;
3258 spin_lock_irq(&hdspm->lock);
3259 change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3260 hdspm_set_toggle_setting(hdspm, regmask, val);
3261 spin_unlock_irq(&hdspm->lock);
3265 #define HDSPM_INPUT_SELECT(xname, xindex) \
3266 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3269 .info = snd_hdspm_info_input_select, \
3270 .get = snd_hdspm_get_input_select, \
3271 .put = snd_hdspm_put_input_select \
3274 static int hdspm_input_select(struct hdspm * hdspm)
3276 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3279 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3282 hdspm->control_register |= HDSPM_InputSelect0;
3284 hdspm->control_register &= ~HDSPM_InputSelect0;
3285 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3290 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3291 struct snd_ctl_elem_info *uinfo)
3293 static const char *const texts[] = { "optical", "coaxial" };
3294 ENUMERATED_CTL_INFO(uinfo, texts);
3298 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3299 struct snd_ctl_elem_value *ucontrol)
3301 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3303 spin_lock_irq(&hdspm->lock);
3304 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3305 spin_unlock_irq(&hdspm->lock);
3309 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3310 struct snd_ctl_elem_value *ucontrol)
3312 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3316 if (!snd_hdspm_use_is_exclusive(hdspm))
3318 val = ucontrol->value.integer.value[0] & 1;
3319 spin_lock_irq(&hdspm->lock);
3320 change = (int) val != hdspm_input_select(hdspm);
3321 hdspm_set_input_select(hdspm, val);
3322 spin_unlock_irq(&hdspm->lock);
3327 #define HDSPM_DS_WIRE(xname, xindex) \
3328 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3331 .info = snd_hdspm_info_ds_wire, \
3332 .get = snd_hdspm_get_ds_wire, \
3333 .put = snd_hdspm_put_ds_wire \
3336 static int hdspm_ds_wire(struct hdspm * hdspm)
3338 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3341 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3344 hdspm->control_register |= HDSPM_DS_DoubleWire;
3346 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3347 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3352 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3353 struct snd_ctl_elem_info *uinfo)
3355 static const char *const texts[] = { "Single", "Double" };
3356 ENUMERATED_CTL_INFO(uinfo, texts);
3360 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3361 struct snd_ctl_elem_value *ucontrol)
3363 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3365 spin_lock_irq(&hdspm->lock);
3366 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3367 spin_unlock_irq(&hdspm->lock);
3371 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3372 struct snd_ctl_elem_value *ucontrol)
3374 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3378 if (!snd_hdspm_use_is_exclusive(hdspm))
3380 val = ucontrol->value.integer.value[0] & 1;
3381 spin_lock_irq(&hdspm->lock);
3382 change = (int) val != hdspm_ds_wire(hdspm);
3383 hdspm_set_ds_wire(hdspm, val);
3384 spin_unlock_irq(&hdspm->lock);
3389 #define HDSPM_QS_WIRE(xname, xindex) \
3390 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3393 .info = snd_hdspm_info_qs_wire, \
3394 .get = snd_hdspm_get_qs_wire, \
3395 .put = snd_hdspm_put_qs_wire \
3398 static int hdspm_qs_wire(struct hdspm * hdspm)
3400 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3402 if (hdspm->control_register & HDSPM_QS_QuadWire)
3407 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3409 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3414 hdspm->control_register |= HDSPM_QS_DoubleWire;
3417 hdspm->control_register |= HDSPM_QS_QuadWire;
3420 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3425 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3426 struct snd_ctl_elem_info *uinfo)
3428 static const char *const texts[] = { "Single", "Double", "Quad" };
3429 ENUMERATED_CTL_INFO(uinfo, texts);
3433 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3434 struct snd_ctl_elem_value *ucontrol)
3436 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3438 spin_lock_irq(&hdspm->lock);
3439 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3440 spin_unlock_irq(&hdspm->lock);
3444 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3445 struct snd_ctl_elem_value *ucontrol)
3447 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3451 if (!snd_hdspm_use_is_exclusive(hdspm))
3453 val = ucontrol->value.integer.value[0];
3458 spin_lock_irq(&hdspm->lock);
3459 change = val != hdspm_qs_wire(hdspm);
3460 hdspm_set_qs_wire(hdspm, val);
3461 spin_unlock_irq(&hdspm->lock);
3465 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3466 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3468 .private_value = xindex, \
3469 .info = snd_hdspm_info_tristate, \
3470 .get = snd_hdspm_get_tristate, \
3471 .put = snd_hdspm_put_tristate \
3474 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3476 u32 reg = hdspm->settings_register & (regmask * 3);
3477 return reg / regmask;
3480 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3482 hdspm->settings_register &= ~(regmask * 3);
3483 hdspm->settings_register |= (regmask * mode);
3484 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3489 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3490 struct snd_ctl_elem_info *uinfo)
3492 u32 regmask = kcontrol->private_value;
3494 static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3495 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3498 case HDSPM_c0_Input0:
3499 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3502 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3508 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3509 struct snd_ctl_elem_value *ucontrol)
3511 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3512 u32 regmask = kcontrol->private_value;
3514 spin_lock_irq(&hdspm->lock);
3515 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3516 spin_unlock_irq(&hdspm->lock);
3520 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3521 struct snd_ctl_elem_value *ucontrol)
3523 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3524 u32 regmask = kcontrol->private_value;
3528 if (!snd_hdspm_use_is_exclusive(hdspm))
3530 val = ucontrol->value.integer.value[0];
3536 spin_lock_irq(&hdspm->lock);
3537 change = val != hdspm_tristate(hdspm, regmask);
3538 hdspm_set_tristate(hdspm, val, regmask);
3539 spin_unlock_irq(&hdspm->lock);
3543 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3544 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3547 .info = snd_hdspm_info_madi_speedmode, \
3548 .get = snd_hdspm_get_madi_speedmode, \
3549 .put = snd_hdspm_put_madi_speedmode \
3552 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3554 if (hdspm->control_register & HDSPM_QuadSpeed)
3556 if (hdspm->control_register & HDSPM_DoubleSpeed)
3561 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3563 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3568 hdspm->control_register |= HDSPM_DoubleSpeed;
3571 hdspm->control_register |= HDSPM_QuadSpeed;
3574 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3579 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3580 struct snd_ctl_elem_info *uinfo)
3582 static const char *const texts[] = { "Single", "Double", "Quad" };
3583 ENUMERATED_CTL_INFO(uinfo, texts);
3587 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3588 struct snd_ctl_elem_value *ucontrol)
3590 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3592 spin_lock_irq(&hdspm->lock);
3593 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3594 spin_unlock_irq(&hdspm->lock);
3598 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3599 struct snd_ctl_elem_value *ucontrol)
3601 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3605 if (!snd_hdspm_use_is_exclusive(hdspm))
3607 val = ucontrol->value.integer.value[0];
3612 spin_lock_irq(&hdspm->lock);
3613 change = val != hdspm_madi_speedmode(hdspm);
3614 hdspm_set_madi_speedmode(hdspm, val);
3615 spin_unlock_irq(&hdspm->lock);
3619 #define HDSPM_MIXER(xname, xindex) \
3620 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3624 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3625 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3626 .info = snd_hdspm_info_mixer, \
3627 .get = snd_hdspm_get_mixer, \
3628 .put = snd_hdspm_put_mixer \
3631 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3632 struct snd_ctl_elem_info *uinfo)
3634 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3636 uinfo->value.integer.min = 0;
3637 uinfo->value.integer.max = 65535;
3638 uinfo->value.integer.step = 1;
3642 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3643 struct snd_ctl_elem_value *ucontrol)
3645 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3649 source = ucontrol->value.integer.value[0];
3652 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3653 source = 2 * HDSPM_MAX_CHANNELS - 1;
3655 destination = ucontrol->value.integer.value[1];
3656 if (destination < 0)
3658 else if (destination >= HDSPM_MAX_CHANNELS)
3659 destination = HDSPM_MAX_CHANNELS - 1;
3661 spin_lock_irq(&hdspm->lock);
3662 if (source >= HDSPM_MAX_CHANNELS)
3663 ucontrol->value.integer.value[2] =
3664 hdspm_read_pb_gain(hdspm, destination,
3665 source - HDSPM_MAX_CHANNELS);
3667 ucontrol->value.integer.value[2] =
3668 hdspm_read_in_gain(hdspm, destination, source);
3670 spin_unlock_irq(&hdspm->lock);
3675 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3676 struct snd_ctl_elem_value *ucontrol)
3678 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3684 if (!snd_hdspm_use_is_exclusive(hdspm))
3687 source = ucontrol->value.integer.value[0];
3688 destination = ucontrol->value.integer.value[1];
3690 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3692 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3695 gain = ucontrol->value.integer.value[2];
3697 spin_lock_irq(&hdspm->lock);
3699 if (source >= HDSPM_MAX_CHANNELS)
3700 change = gain != hdspm_read_pb_gain(hdspm, destination,
3702 HDSPM_MAX_CHANNELS);
3704 change = gain != hdspm_read_in_gain(hdspm, destination,
3708 if (source >= HDSPM_MAX_CHANNELS)
3709 hdspm_write_pb_gain(hdspm, destination,
3710 source - HDSPM_MAX_CHANNELS,
3713 hdspm_write_in_gain(hdspm, destination, source,
3716 spin_unlock_irq(&hdspm->lock);
3721 /* The simple mixer control(s) provide gain control for the
3722 basic 1:1 mappings of playback streams to output
3726 #define HDSPM_PLAYBACK_MIXER \
3727 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3728 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3729 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3730 .info = snd_hdspm_info_playback_mixer, \
3731 .get = snd_hdspm_get_playback_mixer, \
3732 .put = snd_hdspm_put_playback_mixer \
3735 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3736 struct snd_ctl_elem_info *uinfo)
3738 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3740 uinfo->value.integer.min = 0;
3741 uinfo->value.integer.max = 64;
3742 uinfo->value.integer.step = 1;
3746 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3747 struct snd_ctl_elem_value *ucontrol)
3749 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3752 channel = ucontrol->id.index - 1;
3754 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3757 spin_lock_irq(&hdspm->lock);
3758 ucontrol->value.integer.value[0] =
3759 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3760 spin_unlock_irq(&hdspm->lock);
3765 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3766 struct snd_ctl_elem_value *ucontrol)
3768 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3773 if (!snd_hdspm_use_is_exclusive(hdspm))
3776 channel = ucontrol->id.index - 1;
3778 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3781 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3783 spin_lock_irq(&hdspm->lock);
3785 gain != hdspm_read_pb_gain(hdspm, channel,
3788 hdspm_write_pb_gain(hdspm, channel, channel,
3790 spin_unlock_irq(&hdspm->lock);
3794 #define HDSPM_SYNC_CHECK(xname, xindex) \
3795 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3797 .private_value = xindex, \
3798 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3799 .info = snd_hdspm_info_sync_check, \
3800 .get = snd_hdspm_get_sync_check \
3803 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3804 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3806 .private_value = xindex, \
3807 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3808 .info = snd_hdspm_tco_info_lock_check, \
3809 .get = snd_hdspm_get_sync_check \
3814 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3815 struct snd_ctl_elem_info *uinfo)
3817 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3818 ENUMERATED_CTL_INFO(uinfo, texts);
3822 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3823 struct snd_ctl_elem_info *uinfo)
3825 static const char *const texts[] = { "No Lock", "Lock" };
3826 ENUMERATED_CTL_INFO(uinfo, texts);
3830 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3832 int status, status2;
3834 switch (hdspm->io_type) {
3836 status = hdspm_read(hdspm, HDSPM_statusRegister);
3837 if (status & HDSPM_AES32_wcLock) {
3838 if (status & HDSPM_AES32_wcSync)
3847 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3848 if (status2 & HDSPM_wcLock) {
3849 if (status2 & HDSPM_wcSync)
3859 status = hdspm_read(hdspm, HDSPM_statusRegister);
3861 if (status & 0x2000000)
3863 else if (status & 0x1000000)
3878 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3880 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3881 if (status & HDSPM_madiLock) {
3882 if (status & HDSPM_madiSync)
3891 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3893 int status, lock, sync;
3895 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3897 lock = (status & (0x1<<idx)) ? 1 : 0;
3898 sync = (status & (0x100<<idx)) ? 1 : 0;
3908 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3910 int status, lock = 0, sync = 0;
3912 switch (hdspm->io_type) {
3915 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3916 lock = (status & 0x400) ? 1 : 0;
3917 sync = (status & 0x800) ? 1 : 0;
3921 status = hdspm_read(hdspm, HDSPM_statusRegister);
3922 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3923 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3927 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3928 lock = (status & 0x100000) ? 1 : 0;
3929 sync = (status & 0x200000) ? 1 : 0;
3944 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3946 int status2, lock, sync;
3947 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3949 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3950 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3959 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3962 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3964 return (status & mask) ? 1 : 0;
3968 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3973 switch (hdspm->io_type) {
3975 status = hdspm_read(hdspm, HDSPM_statusRegister);
3976 if (status & HDSPM_tcoLockMadi) {
3977 if (status & HDSPM_tcoSync)
3984 status = hdspm_read(hdspm, HDSPM_statusRegister);
3985 if (status & HDSPM_tcoLockAes) {
3986 if (status & HDSPM_tcoSync)
3994 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3996 if (status & 0x8000000)
3997 return 2; /* Sync */
3998 if (status & 0x4000000)
3999 return 1; /* Lock */
4000 return 0; /* No signal */
4011 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
4012 struct snd_ctl_elem_value *ucontrol)
4014 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4017 switch (hdspm->io_type) {
4019 switch (kcontrol->private_value) {
4021 val = hdspm_wc_sync_check(hdspm); break;
4023 val = hdspm_tco_sync_check(hdspm); break;
4024 case 8: /* SYNC IN */
4025 val = hdspm_sync_in_sync_check(hdspm); break;
4027 val = hdspm_s1_sync_check(hdspm,
4028 kcontrol->private_value-1);
4033 switch (kcontrol->private_value) {
4035 val = hdspm_wc_sync_check(hdspm); break;
4037 val = hdspm_tco_sync_check(hdspm); break;
4038 case 5: /* SYNC IN */
4039 val = hdspm_sync_in_sync_check(hdspm); break;
4041 val = hdspm_s1_sync_check(hdspm,
4042 kcontrol->private_value-1);
4047 switch (kcontrol->private_value) {
4049 val = hdspm_wc_sync_check(hdspm); break;
4051 val = hdspm_madi_sync_check(hdspm); break;
4053 val = hdspm_tco_sync_check(hdspm); break;
4054 case 3: /* SYNC_IN */
4055 val = hdspm_sync_in_sync_check(hdspm); break;
4060 val = hdspm_madi_sync_check(hdspm); /* MADI */
4064 switch (kcontrol->private_value) {
4066 val = hdspm_wc_sync_check(hdspm); break;
4068 val = hdspm_tco_sync_check(hdspm); break;
4069 case 10 /* SYNC IN */:
4070 val = hdspm_sync_in_sync_check(hdspm); break;
4071 default: /* AES1 to AES8 */
4072 val = hdspm_aes_sync_check(hdspm,
4073 kcontrol->private_value-1);
4080 switch (kcontrol->private_value) {
4082 /* Check TCO for lock state of its current input */
4083 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4086 /* Check TCO for valid time code on LTC input. */
4087 val = hdspm_tco_input_check(hdspm,
4088 HDSPM_TCO1_LTC_Input_valid);
4098 ucontrol->value.enumerated.item[0] = val;
4107 static void hdspm_tco_write(struct hdspm *hdspm)
4109 unsigned int tc[4] = { 0, 0, 0, 0};
4111 switch (hdspm->tco->input) {
4113 tc[2] |= HDSPM_TCO2_set_input_MSB;
4116 tc[2] |= HDSPM_TCO2_set_input_LSB;
4122 switch (hdspm->tco->framerate) {
4124 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4127 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4130 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4131 HDSPM_TCO1_set_drop_frame_flag;
4134 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4135 HDSPM_TCO1_LTC_Format_MSB;
4138 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4139 HDSPM_TCO1_LTC_Format_MSB +
4140 HDSPM_TCO1_set_drop_frame_flag;
4146 switch (hdspm->tco->wordclock) {
4148 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4151 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4157 switch (hdspm->tco->samplerate) {
4159 tc[2] |= HDSPM_TCO2_set_freq;
4162 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4168 switch (hdspm->tco->pull) {
4170 tc[2] |= HDSPM_TCO2_set_pull_up;
4173 tc[2] |= HDSPM_TCO2_set_pull_down;
4176 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4179 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4185 if (1 == hdspm->tco->term) {
4186 tc[2] |= HDSPM_TCO2_set_term_75R;
4189 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4190 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4191 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4192 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4196 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4197 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4200 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4201 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4202 .info = snd_hdspm_info_tco_sample_rate, \
4203 .get = snd_hdspm_get_tco_sample_rate, \
4204 .put = snd_hdspm_put_tco_sample_rate \
4207 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4208 struct snd_ctl_elem_info *uinfo)
4210 /* TODO freq from app could be supported here, see tco->samplerate */
4211 static const char *const texts[] = { "44.1 kHz", "48 kHz" };
4212 ENUMERATED_CTL_INFO(uinfo, texts);
4216 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4217 struct snd_ctl_elem_value *ucontrol)
4219 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4221 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4226 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4227 struct snd_ctl_elem_value *ucontrol)
4229 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4231 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4232 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4234 hdspm_tco_write(hdspm);
4243 #define HDSPM_TCO_PULL(xname, xindex) \
4244 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4247 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4248 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4249 .info = snd_hdspm_info_tco_pull, \
4250 .get = snd_hdspm_get_tco_pull, \
4251 .put = snd_hdspm_put_tco_pull \
4254 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4255 struct snd_ctl_elem_info *uinfo)
4257 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %",
4259 ENUMERATED_CTL_INFO(uinfo, texts);
4263 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4264 struct snd_ctl_elem_value *ucontrol)
4266 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4268 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4273 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4274 struct snd_ctl_elem_value *ucontrol)
4276 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4278 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4279 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4281 hdspm_tco_write(hdspm);
4289 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4290 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4293 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4294 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4295 .info = snd_hdspm_info_tco_wck_conversion, \
4296 .get = snd_hdspm_get_tco_wck_conversion, \
4297 .put = snd_hdspm_put_tco_wck_conversion \
4300 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4301 struct snd_ctl_elem_info *uinfo)
4303 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4304 ENUMERATED_CTL_INFO(uinfo, texts);
4308 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4309 struct snd_ctl_elem_value *ucontrol)
4311 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4313 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4318 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4319 struct snd_ctl_elem_value *ucontrol)
4321 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4323 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4324 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4326 hdspm_tco_write(hdspm);
4335 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4336 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4339 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4340 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4341 .info = snd_hdspm_info_tco_frame_rate, \
4342 .get = snd_hdspm_get_tco_frame_rate, \
4343 .put = snd_hdspm_put_tco_frame_rate \
4346 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4347 struct snd_ctl_elem_info *uinfo)
4349 static const char *const texts[] = { "24 fps", "25 fps", "29.97fps",
4350 "29.97 dfps", "30 fps", "30 dfps" };
4351 ENUMERATED_CTL_INFO(uinfo, texts);
4355 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4356 struct snd_ctl_elem_value *ucontrol)
4358 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4360 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4365 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4366 struct snd_ctl_elem_value *ucontrol)
4368 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4370 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4371 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4373 hdspm_tco_write(hdspm);
4382 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4383 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4386 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4387 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4388 .info = snd_hdspm_info_tco_sync_source, \
4389 .get = snd_hdspm_get_tco_sync_source, \
4390 .put = snd_hdspm_put_tco_sync_source \
4393 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4394 struct snd_ctl_elem_info *uinfo)
4396 static const char *const texts[] = { "LTC", "Video", "WCK" };
4397 ENUMERATED_CTL_INFO(uinfo, texts);
4401 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4402 struct snd_ctl_elem_value *ucontrol)
4404 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4406 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4411 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4412 struct snd_ctl_elem_value *ucontrol)
4414 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4416 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4417 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4419 hdspm_tco_write(hdspm);
4428 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4429 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4432 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4433 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4434 .info = snd_hdspm_info_tco_word_term, \
4435 .get = snd_hdspm_get_tco_word_term, \
4436 .put = snd_hdspm_put_tco_word_term \
4439 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4440 struct snd_ctl_elem_info *uinfo)
4442 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4444 uinfo->value.integer.min = 0;
4445 uinfo->value.integer.max = 1;
4451 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4452 struct snd_ctl_elem_value *ucontrol)
4454 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4456 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4462 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4463 struct snd_ctl_elem_value *ucontrol)
4465 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4467 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4468 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4470 hdspm_tco_write(hdspm);
4481 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4482 HDSPM_MIXER("Mixer", 0),
4483 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4484 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4485 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4486 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4487 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4488 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4489 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4490 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4491 HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4492 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4493 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4494 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4495 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4496 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4497 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4498 HDSPM_INPUT_SELECT("Input Select", 0),
4499 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4503 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4504 HDSPM_MIXER("Mixer", 0),
4505 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4506 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4507 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4508 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4509 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4510 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4511 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4512 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4513 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4516 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4517 HDSPM_MIXER("Mixer", 0),
4518 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4519 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4520 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4521 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4522 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4523 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4524 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4525 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4526 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4527 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4528 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4529 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4530 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4531 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4532 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4533 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4534 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4535 HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4536 HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4537 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4538 HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4539 HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4540 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4541 HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4542 HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4543 HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4546 HDSPM_INPUT_SELECT("Input Select", 0),
4547 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4548 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4549 HDSPM_SPDIF_IN("SPDIF In", 0);
4550 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4551 HDSPM_INPUT_LEVEL("Input Level", 0);
4552 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4553 HDSPM_PHONES("Phones", 0);
4557 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4558 HDSPM_MIXER("Mixer", 0),
4559 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4560 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4561 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4562 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4563 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4564 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4565 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4566 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4567 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4568 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4569 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4570 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4571 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4572 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4573 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4574 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4575 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4576 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4577 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4578 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4579 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4580 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4581 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4582 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4585 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4586 HDSPM_MIXER("Mixer", 0),
4587 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4588 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4589 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4590 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4591 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4592 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11),
4593 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4594 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4595 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4596 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4597 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4598 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4599 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4600 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4601 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4602 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4603 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4604 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4605 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4606 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4607 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4608 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4609 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4610 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4611 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4612 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4613 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4614 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4615 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4616 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4617 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4618 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4619 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4620 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4621 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4626 /* Control elements for the optional TCO module */
4627 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4628 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4629 HDSPM_TCO_PULL("TCO Pull", 0),
4630 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4631 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4632 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4633 HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4634 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4635 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4636 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4637 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4641 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4644 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4648 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4649 if (hdspm->system_sample_rate > 48000) {
4650 hdspm->playback_mixer_ctls[i]->vd[0].access =
4651 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4652 SNDRV_CTL_ELEM_ACCESS_READ |
4653 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4655 hdspm->playback_mixer_ctls[i]->vd[0].access =
4656 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4657 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4659 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4660 SNDRV_CTL_EVENT_MASK_INFO,
4661 &hdspm->playback_mixer_ctls[i]->id);
4668 static int snd_hdspm_create_controls(struct snd_card *card,
4669 struct hdspm *hdspm)
4671 unsigned int idx, limit;
4673 struct snd_kcontrol *kctl;
4674 struct snd_kcontrol_new *list = NULL;
4676 switch (hdspm->io_type) {
4678 list = snd_hdspm_controls_madi;
4679 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4682 list = snd_hdspm_controls_madiface;
4683 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4686 list = snd_hdspm_controls_aio;
4687 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4690 list = snd_hdspm_controls_raydat;
4691 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4694 list = snd_hdspm_controls_aes32;
4695 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4700 for (idx = 0; idx < limit; idx++) {
4701 err = snd_ctl_add(card,
4702 snd_ctl_new1(&list[idx], hdspm));
4709 /* create simple 1:1 playback mixer controls */
4710 snd_hdspm_playback_mixer.name = "Chn";
4711 if (hdspm->system_sample_rate >= 128000) {
4712 limit = hdspm->qs_out_channels;
4713 } else if (hdspm->system_sample_rate >= 64000) {
4714 limit = hdspm->ds_out_channels;
4716 limit = hdspm->ss_out_channels;
4718 for (idx = 0; idx < limit; ++idx) {
4719 snd_hdspm_playback_mixer.index = idx + 1;
4720 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4721 err = snd_ctl_add(card, kctl);
4724 hdspm->playback_mixer_ctls[idx] = kctl;
4729 /* add tco control elements */
4730 list = snd_hdspm_controls_tco;
4731 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4732 for (idx = 0; idx < limit; idx++) {
4733 err = snd_ctl_add(card,
4734 snd_ctl_new1(&list[idx], hdspm));
4743 /*------------------------------------------------------------
4745 ------------------------------------------------------------*/
4748 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4749 struct snd_info_buffer *buffer)
4751 struct hdspm *hdspm = entry->private_data;
4752 unsigned int status, control;
4753 int a, ltc, frames, seconds, minutes, hours;
4754 unsigned int period;
4758 snd_iprintf(buffer, "--- TCO ---\n");
4760 status = hdspm_read(hdspm, HDSPM_statusRegister);
4761 control = hdspm->control_register;
4764 if (status & HDSPM_tco_detect) {
4765 snd_iprintf(buffer, "TCO module detected.\n");
4766 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4767 if (a & HDSPM_TCO1_LTC_Input_valid) {
4768 snd_iprintf(buffer, " LTC valid, ");
4769 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4770 HDSPM_TCO1_LTC_Format_MSB)) {
4772 snd_iprintf(buffer, "24 fps, ");
4774 case HDSPM_TCO1_LTC_Format_LSB:
4775 snd_iprintf(buffer, "25 fps, ");
4777 case HDSPM_TCO1_LTC_Format_MSB:
4778 snd_iprintf(buffer, "29.97 fps, ");
4781 snd_iprintf(buffer, "30 fps, ");
4784 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4785 snd_iprintf(buffer, "drop frame\n");
4787 snd_iprintf(buffer, "full frame\n");
4790 snd_iprintf(buffer, " no LTC\n");
4792 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4793 snd_iprintf(buffer, " Video: NTSC\n");
4794 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4795 snd_iprintf(buffer, " Video: PAL\n");
4797 snd_iprintf(buffer, " No video\n");
4799 if (a & HDSPM_TCO1_TCO_lock) {
4800 snd_iprintf(buffer, " Sync: lock\n");
4802 snd_iprintf(buffer, " Sync: no lock\n");
4805 switch (hdspm->io_type) {
4808 freq_const = 110069313433624ULL;
4812 freq_const = 104857600000000ULL;
4815 break; /* no TCO possible */
4818 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4819 snd_iprintf(buffer, " period: %u\n", period);
4822 /* rate = freq_const/period; */
4823 rate = div_u64(freq_const, period);
4825 if (control & HDSPM_QuadSpeed) {
4827 } else if (control & HDSPM_DoubleSpeed) {
4831 snd_iprintf(buffer, " Frequency: %u Hz\n",
4832 (unsigned int) rate);
4834 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4837 frames += (ltc & 0x3) * 10;
4839 seconds = ltc & 0xF;
4841 seconds += (ltc & 0x7) * 10;
4843 minutes = ltc & 0xF;
4845 minutes += (ltc & 0x7) * 10;
4849 hours += (ltc & 0x3) * 10;
4851 " LTC In: %02d:%02d:%02d:%02d\n",
4852 hours, minutes, seconds, frames);
4855 snd_iprintf(buffer, "No TCO module detected.\n");
4860 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4861 struct snd_info_buffer *buffer)
4863 struct hdspm *hdspm = entry->private_data;
4864 unsigned int status, status2;
4866 char *pref_sync_ref;
4868 char *system_clock_mode;
4871 status = hdspm_read(hdspm, HDSPM_statusRegister);
4872 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4874 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4875 hdspm->card_name, hdspm->card->number + 1,
4876 hdspm->firmware_rev,
4877 (status2 & HDSPM_version0) |
4878 (status2 & HDSPM_version1) | (status2 &
4881 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4882 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4885 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4886 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4888 snd_iprintf(buffer, "--- System ---\n");
4891 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4892 status & HDSPM_audioIRQPending,
4893 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4894 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4897 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4898 "estimated= %ld (bytes)\n",
4899 ((status & HDSPM_BufferID) ? 1 : 0),
4900 (status & HDSPM_BufferPositionMask),
4901 (status & HDSPM_BufferPositionMask) %
4902 (2 * (int)hdspm->period_bytes),
4903 ((status & HDSPM_BufferPositionMask) - 64) %
4904 (2 * (int)hdspm->period_bytes),
4905 (long) hdspm_hw_pointer(hdspm) * 4);
4908 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4909 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4910 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4911 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4912 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4914 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4915 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4916 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4918 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4920 hdspm->control_register, hdspm->control2_register,
4924 snd_iprintf(buffer, "--- Settings ---\n");
4926 x = hdspm_get_latency(hdspm);
4929 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4930 x, (unsigned long) hdspm->period_bytes);
4932 snd_iprintf(buffer, "Line out: %s\n",
4933 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4936 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4938 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4939 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4940 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4943 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4944 system_clock_mode = "AutoSync";
4946 system_clock_mode = "Master";
4947 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4949 switch (hdspm_pref_sync_ref(hdspm)) {
4950 case HDSPM_SYNC_FROM_WORD:
4951 pref_sync_ref = "Word Clock";
4953 case HDSPM_SYNC_FROM_MADI:
4954 pref_sync_ref = "MADI Sync";
4956 case HDSPM_SYNC_FROM_TCO:
4957 pref_sync_ref = "TCO";
4959 case HDSPM_SYNC_FROM_SYNC_IN:
4960 pref_sync_ref = "Sync In";
4963 pref_sync_ref = "XXXX Clock";
4966 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4969 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4970 hdspm->system_sample_rate);
4973 snd_iprintf(buffer, "--- Status:\n");
4975 x = status & HDSPM_madiSync;
4976 x2 = status2 & HDSPM_wcSync;
4978 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4979 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4981 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4984 switch (hdspm_autosync_ref(hdspm)) {
4985 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4986 autosync_ref = "Sync In";
4988 case HDSPM_AUTOSYNC_FROM_TCO:
4989 autosync_ref = "TCO";
4991 case HDSPM_AUTOSYNC_FROM_WORD:
4992 autosync_ref = "Word Clock";
4994 case HDSPM_AUTOSYNC_FROM_MADI:
4995 autosync_ref = "MADI Sync";
4997 case HDSPM_AUTOSYNC_FROM_NONE:
4998 autosync_ref = "Input not valid";
5001 autosync_ref = "---";
5005 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
5006 autosync_ref, hdspm_external_sample_rate(hdspm),
5007 (status & HDSPM_madiFreqMask) >> 22,
5008 (status2 & HDSPM_wcFreqMask) >> 5);
5010 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
5011 (status & HDSPM_AB_int) ? "Coax" : "Optical",
5012 (status & HDSPM_RX_64ch) ? "64 channels" :
5015 /* call readout function for TCO specific status */
5016 snd_hdspm_proc_read_tco(entry, buffer);
5018 snd_iprintf(buffer, "\n");
5022 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
5023 struct snd_info_buffer *buffer)
5025 struct hdspm *hdspm = entry->private_data;
5026 unsigned int status;
5027 unsigned int status2;
5028 unsigned int timecode;
5029 unsigned int wcLock, wcSync;
5034 status = hdspm_read(hdspm, HDSPM_statusRegister);
5035 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5036 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5038 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5039 hdspm->card_name, hdspm->card->number + 1,
5040 hdspm->firmware_rev);
5042 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5043 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5045 snd_iprintf(buffer, "--- System ---\n");
5048 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5049 status & HDSPM_audioIRQPending,
5050 (status & HDSPM_midi0IRQPending) ? 1 : 0,
5051 (status & HDSPM_midi1IRQPending) ? 1 : 0,
5054 "HW pointer: id = %d, rawptr = %d (%d->%d) "
5055 "estimated= %ld (bytes)\n",
5056 ((status & HDSPM_BufferID) ? 1 : 0),
5057 (status & HDSPM_BufferPositionMask),
5058 (status & HDSPM_BufferPositionMask) %
5059 (2 * (int)hdspm->period_bytes),
5060 ((status & HDSPM_BufferPositionMask) - 64) %
5061 (2 * (int)hdspm->period_bytes),
5062 (long) hdspm_hw_pointer(hdspm) * 4);
5065 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5066 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5067 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5068 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5069 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5071 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5072 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5073 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5075 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5077 hdspm->control_register, hdspm->control2_register,
5080 snd_iprintf(buffer, "--- Settings ---\n");
5082 x = hdspm_get_latency(hdspm);
5085 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5086 x, (unsigned long) hdspm->period_bytes);
5088 snd_iprintf(buffer, "Line out: %s\n",
5090 control_register & HDSPM_LineOut) ? "on " : "off");
5093 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5095 control_register & HDSPM_clr_tms) ? "on" : "off",
5097 control_register & HDSPM_Emphasis) ? "on" : "off",
5099 control_register & HDSPM_Dolby) ? "on" : "off");
5102 pref_syncref = hdspm_pref_sync_ref(hdspm);
5103 if (pref_syncref == 0)
5104 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5106 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5109 snd_iprintf(buffer, "System Clock Frequency: %d\n",
5110 hdspm->system_sample_rate);
5112 snd_iprintf(buffer, "Double speed: %s\n",
5113 hdspm->control_register & HDSPM_DS_DoubleWire?
5114 "Double wire" : "Single wire");
5115 snd_iprintf(buffer, "Quad speed: %s\n",
5116 hdspm->control_register & HDSPM_QS_DoubleWire?
5118 hdspm->control_register & HDSPM_QS_QuadWire?
5119 "Quad wire" : "Single wire");
5121 snd_iprintf(buffer, "--- Status:\n");
5123 wcLock = status & HDSPM_AES32_wcLock;
5124 wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5126 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
5127 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock",
5128 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5130 for (x = 0; x < 8; x++) {
5131 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
5133 (status2 & (HDSPM_LockAES >> x)) ?
5134 "Sync " : "No Lock",
5135 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5138 switch (hdspm_autosync_ref(hdspm)) {
5139 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5140 autosync_ref = "None"; break;
5141 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5142 autosync_ref = "Word Clock"; break;
5143 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5144 autosync_ref = "AES1"; break;
5145 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5146 autosync_ref = "AES2"; break;
5147 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5148 autosync_ref = "AES3"; break;
5149 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5150 autosync_ref = "AES4"; break;
5151 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5152 autosync_ref = "AES5"; break;
5153 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5154 autosync_ref = "AES6"; break;
5155 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5156 autosync_ref = "AES7"; break;
5157 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5158 autosync_ref = "AES8"; break;
5159 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
5160 autosync_ref = "TCO"; break;
5161 case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN:
5162 autosync_ref = "Sync In"; break;
5164 autosync_ref = "---"; break;
5166 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5168 /* call readout function for TCO specific status */
5169 snd_hdspm_proc_read_tco(entry, buffer);
5171 snd_iprintf(buffer, "\n");
5175 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5176 struct snd_info_buffer *buffer)
5178 struct hdspm *hdspm = entry->private_data;
5179 unsigned int status1, status2, status3, i;
5180 unsigned int lock, sync;
5182 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5183 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5184 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5186 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5187 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5188 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5191 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5193 snd_iprintf(buffer, "Clock mode : %s\n",
5194 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5195 snd_iprintf(buffer, "System frequency: %d Hz\n",
5196 hdspm_get_system_sample_rate(hdspm));
5198 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5203 for (i = 0; i < 8; i++) {
5204 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5206 (status1 & lock) ? 1 : 0,
5207 (status1 & sync) ? 1 : 0,
5208 texts_freq[(status2 >> (i * 4)) & 0xF]);
5214 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5215 (status1 & 0x1000000) ? 1 : 0,
5216 (status1 & 0x2000000) ? 1 : 0,
5217 texts_freq[(status1 >> 16) & 0xF]);
5219 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5220 (status1 & 0x4000000) ? 1 : 0,
5221 (status1 & 0x8000000) ? 1 : 0,
5222 texts_freq[(status1 >> 20) & 0xF]);
5224 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5225 (status3 & 0x400) ? 1 : 0,
5226 (status3 & 0x800) ? 1 : 0,
5227 texts_freq[(status2 >> 12) & 0xF]);
5231 #ifdef CONFIG_SND_DEBUG
5233 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5234 struct snd_info_buffer *buffer)
5236 struct hdspm *hdspm = entry->private_data;
5240 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5241 snd_iprintf(buffer, "0x%08X: ", i);
5242 for (j = 0; j < 16; j += 4)
5243 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5244 snd_iprintf(buffer, "\n");
5250 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5251 struct snd_info_buffer *buffer)
5253 struct hdspm *hdspm = entry->private_data;
5256 snd_iprintf(buffer, "# generated by hdspm\n");
5258 for (i = 0; i < hdspm->max_channels_in; i++) {
5259 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5263 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5264 struct snd_info_buffer *buffer)
5266 struct hdspm *hdspm = entry->private_data;
5269 snd_iprintf(buffer, "# generated by hdspm\n");
5271 for (i = 0; i < hdspm->max_channels_out; i++) {
5272 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5277 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5279 struct snd_info_entry *entry;
5281 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5282 switch (hdspm->io_type) {
5284 snd_info_set_text_ops(entry, hdspm,
5285 snd_hdspm_proc_read_aes32);
5288 snd_info_set_text_ops(entry, hdspm,
5289 snd_hdspm_proc_read_madi);
5292 /* snd_info_set_text_ops(entry, hdspm,
5293 snd_hdspm_proc_read_madiface); */
5296 snd_info_set_text_ops(entry, hdspm,
5297 snd_hdspm_proc_read_raydat);
5304 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5305 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5308 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5309 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5312 #ifdef CONFIG_SND_DEBUG
5313 /* debug file to read all hdspm registers */
5314 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5315 snd_info_set_text_ops(entry, hdspm,
5316 snd_hdspm_proc_read_debug);
5320 /*------------------------------------------------------------
5322 ------------------------------------------------------------*/
5324 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5326 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5327 hold it (e.g. during module initialization).
5332 hdspm->settings_register = 0;
5334 switch (hdspm->io_type) {
5337 hdspm->control_register =
5338 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5343 hdspm->settings_register = 0x1 + 0x1000;
5344 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5346 hdspm->control_register =
5347 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5351 hdspm->control_register =
5352 HDSPM_ClockModeMaster | /* Master Clock Mode on */
5353 hdspm_encode_latency(7) | /* latency max=8192samples */
5354 HDSPM_SyncRef0 | /* AES1 is syncclock */
5355 HDSPM_LineOut | /* Analog output in */
5356 HDSPM_Professional; /* Professional mode */
5360 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5362 if (AES32 == hdspm->io_type) {
5363 /* No control2 register for AES32 */
5364 #ifdef SNDRV_BIG_ENDIAN
5365 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5367 hdspm->control2_register = 0;
5370 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5372 hdspm_compute_period_size(hdspm);
5374 /* silence everything */
5376 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5378 if (hdspm_is_raydat_or_aio(hdspm))
5379 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5381 /* set a default rate so that the channel map is set up. */
5382 hdspm_set_rate(hdspm, 48000, 1);
5388 /*------------------------------------------------------------
5390 ------------------------------------------------------------*/
5392 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5394 struct hdspm *hdspm = (struct hdspm *) dev_id;
5395 unsigned int status;
5396 int i, audio, midi, schedule = 0;
5399 status = hdspm_read(hdspm, HDSPM_statusRegister);
5401 audio = status & HDSPM_audioIRQPending;
5402 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5403 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5405 /* now = get_cycles(); */
5407 * LAT_2..LAT_0 period counter (win) counter (mac)
5408 * 6 4096 ~256053425 ~514672358
5409 * 5 2048 ~128024983 ~257373821
5410 * 4 1024 ~64023706 ~128718089
5411 * 3 512 ~32005945 ~64385999
5412 * 2 256 ~16003039 ~32260176
5413 * 1 128 ~7998738 ~16194507
5414 * 0 64 ~3998231 ~8191558
5417 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n",
5418 now-hdspm->last_interrupt, status & 0xFFC0);
5419 hdspm->last_interrupt = now;
5422 if (!audio && !midi)
5425 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5430 if (hdspm->capture_substream)
5431 snd_pcm_period_elapsed(hdspm->capture_substream);
5433 if (hdspm->playback_substream)
5434 snd_pcm_period_elapsed(hdspm->playback_substream);
5439 while (i < hdspm->midiPorts) {
5440 if ((hdspm_read(hdspm,
5441 hdspm->midi[i].statusIn) & 0xff) &&
5442 (status & hdspm->midi[i].irq)) {
5443 /* we disable interrupts for this input until
5444 * processing is done
5446 hdspm->control_register &= ~hdspm->midi[i].ie;
5447 hdspm_write(hdspm, HDSPM_controlRegister,
5448 hdspm->control_register);
5449 hdspm->midi[i].pending = 1;
5457 tasklet_hi_schedule(&hdspm->midi_tasklet);
5463 /*------------------------------------------------------------
5465 ------------------------------------------------------------*/
5468 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5471 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5472 return hdspm_hw_pointer(hdspm);
5476 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5478 struct snd_pcm_runtime *runtime = substream->runtime;
5479 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5480 struct snd_pcm_substream *other;
5482 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5483 other = hdspm->capture_substream;
5485 other = hdspm->playback_substream;
5488 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5490 runtime->status->hw_ptr = 0;
5492 struct snd_pcm_substream *s;
5493 struct snd_pcm_runtime *oruntime = other->runtime;
5494 snd_pcm_group_for_each_entry(s, substream) {
5496 oruntime->status->hw_ptr =
5497 runtime->status->hw_ptr;
5505 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5506 struct snd_pcm_hw_params *params)
5508 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5514 spin_lock_irq(&hdspm->lock);
5516 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5517 this_pid = hdspm->playback_pid;
5518 other_pid = hdspm->capture_pid;
5520 this_pid = hdspm->capture_pid;
5521 other_pid = hdspm->playback_pid;
5524 if (other_pid > 0 && this_pid != other_pid) {
5526 /* The other stream is open, and not by the same
5527 task as this one. Make sure that the parameters
5528 that matter are the same.
5531 if (params_rate(params) != hdspm->system_sample_rate) {
5532 spin_unlock_irq(&hdspm->lock);
5533 _snd_pcm_hw_param_setempty(params,
5534 SNDRV_PCM_HW_PARAM_RATE);
5538 if (params_period_size(params) != hdspm->period_bytes / 4) {
5539 spin_unlock_irq(&hdspm->lock);
5540 _snd_pcm_hw_param_setempty(params,
5541 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5547 spin_unlock_irq(&hdspm->lock);
5549 /* how to make sure that the rate matches an externally-set one ? */
5551 spin_lock_irq(&hdspm->lock);
5552 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5554 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err);
5555 spin_unlock_irq(&hdspm->lock);
5556 _snd_pcm_hw_param_setempty(params,
5557 SNDRV_PCM_HW_PARAM_RATE);
5560 spin_unlock_irq(&hdspm->lock);
5562 err = hdspm_set_interrupt_interval(hdspm,
5563 params_period_size(params));
5565 dev_info(hdspm->card->dev,
5566 "err on hdspm_set_interrupt_interval: %d\n", err);
5567 _snd_pcm_hw_param_setempty(params,
5568 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5572 /* Memory allocation, takashi's method, dont know if we should
5575 /* malloc all buffer even if not enabled to get sure */
5576 /* Update for MADI rev 204: we need to allocate for all channels,
5577 * otherwise it doesn't work at 96kHz */
5580 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5582 dev_info(hdspm->card->dev,
5583 "err on snd_pcm_lib_malloc_pages: %d\n", err);
5587 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5589 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5590 params_channels(params));
5592 for (i = 0; i < params_channels(params); ++i)
5593 snd_hdspm_enable_out(hdspm, i, 1);
5595 hdspm->playback_buffer =
5596 (unsigned char *) substream->runtime->dma_area;
5597 dev_dbg(hdspm->card->dev,
5598 "Allocated sample buffer for playback at %p\n",
5599 hdspm->playback_buffer);
5601 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5602 params_channels(params));
5604 for (i = 0; i < params_channels(params); ++i)
5605 snd_hdspm_enable_in(hdspm, i, 1);
5607 hdspm->capture_buffer =
5608 (unsigned char *) substream->runtime->dma_area;
5609 dev_dbg(hdspm->card->dev,
5610 "Allocated sample buffer for capture at %p\n",
5611 hdspm->capture_buffer);
5615 dev_dbg(hdspm->card->dev,
5616 "Allocated sample buffer for %s at 0x%08X\n",
5617 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5618 "playback" : "capture",
5619 snd_pcm_sgbuf_get_addr(substream, 0));
5622 dev_dbg(hdspm->card->dev,
5623 "set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5624 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5625 "playback" : "capture",
5626 params_rate(params), params_channels(params),
5627 params_buffer_size(params));
5631 /* For AES cards, the float format bit is the same as the
5632 * preferred sync reference. Since we don't want to break
5633 * sync settings, we have to skip the remaining part of this
5636 if (hdspm->io_type == AES32) {
5641 /* Switch to native float format if requested */
5642 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5643 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5644 dev_info(hdspm->card->dev,
5645 "Switching to native 32bit LE float format.\n");
5647 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5648 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5649 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5650 dev_info(hdspm->card->dev,
5651 "Switching to native 32bit LE integer format.\n");
5653 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5655 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5660 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5663 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5665 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5667 /* params_channels(params) should be enough,
5668 but to get sure in case of error */
5669 for (i = 0; i < hdspm->max_channels_out; ++i)
5670 snd_hdspm_enable_out(hdspm, i, 0);
5672 hdspm->playback_buffer = NULL;
5674 for (i = 0; i < hdspm->max_channels_in; ++i)
5675 snd_hdspm_enable_in(hdspm, i, 0);
5677 hdspm->capture_buffer = NULL;
5681 snd_pcm_lib_free_pages(substream);
5687 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5688 struct snd_pcm_channel_info *info)
5690 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5692 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5693 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5694 dev_info(hdspm->card->dev,
5695 "snd_hdspm_channel_info: output channel out of range (%d)\n",
5700 if (hdspm->channel_map_out[info->channel] < 0) {
5701 dev_info(hdspm->card->dev,
5702 "snd_hdspm_channel_info: output channel %d mapped out\n",
5707 info->offset = hdspm->channel_map_out[info->channel] *
5708 HDSPM_CHANNEL_BUFFER_BYTES;
5710 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5711 dev_info(hdspm->card->dev,
5712 "snd_hdspm_channel_info: input channel out of range (%d)\n",
5717 if (hdspm->channel_map_in[info->channel] < 0) {
5718 dev_info(hdspm->card->dev,
5719 "snd_hdspm_channel_info: input channel %d mapped out\n",
5724 info->offset = hdspm->channel_map_in[info->channel] *
5725 HDSPM_CHANNEL_BUFFER_BYTES;
5734 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5735 unsigned int cmd, void *arg)
5738 case SNDRV_PCM_IOCTL1_RESET:
5739 return snd_hdspm_reset(substream);
5741 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5743 struct snd_pcm_channel_info *info = arg;
5744 return snd_hdspm_channel_info(substream, info);
5750 return snd_pcm_lib_ioctl(substream, cmd, arg);
5753 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5755 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5756 struct snd_pcm_substream *other;
5759 spin_lock(&hdspm->lock);
5760 running = hdspm->running;
5762 case SNDRV_PCM_TRIGGER_START:
5763 running |= 1 << substream->stream;
5765 case SNDRV_PCM_TRIGGER_STOP:
5766 running &= ~(1 << substream->stream);
5770 spin_unlock(&hdspm->lock);
5773 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5774 other = hdspm->capture_substream;
5776 other = hdspm->playback_substream;
5779 struct snd_pcm_substream *s;
5780 snd_pcm_group_for_each_entry(s, substream) {
5782 snd_pcm_trigger_done(s, substream);
5783 if (cmd == SNDRV_PCM_TRIGGER_START)
5784 running |= 1 << s->stream;
5786 running &= ~(1 << s->stream);
5790 if (cmd == SNDRV_PCM_TRIGGER_START) {
5791 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5792 && substream->stream ==
5793 SNDRV_PCM_STREAM_CAPTURE)
5794 hdspm_silence_playback(hdspm);
5797 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5798 hdspm_silence_playback(hdspm);
5801 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5802 hdspm_silence_playback(hdspm);
5805 snd_pcm_trigger_done(substream, substream);
5806 if (!hdspm->running && running)
5807 hdspm_start_audio(hdspm);
5808 else if (hdspm->running && !running)
5809 hdspm_stop_audio(hdspm);
5810 hdspm->running = running;
5811 spin_unlock(&hdspm->lock);
5816 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5821 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5822 .info = (SNDRV_PCM_INFO_MMAP |
5823 SNDRV_PCM_INFO_MMAP_VALID |
5824 SNDRV_PCM_INFO_NONINTERLEAVED |
5825 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5826 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5827 .rates = (SNDRV_PCM_RATE_32000 |
5828 SNDRV_PCM_RATE_44100 |
5829 SNDRV_PCM_RATE_48000 |
5830 SNDRV_PCM_RATE_64000 |
5831 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5832 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5836 .channels_max = HDSPM_MAX_CHANNELS,
5838 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5839 .period_bytes_min = (32 * 4),
5840 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5846 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5847 .info = (SNDRV_PCM_INFO_MMAP |
5848 SNDRV_PCM_INFO_MMAP_VALID |
5849 SNDRV_PCM_INFO_NONINTERLEAVED |
5850 SNDRV_PCM_INFO_SYNC_START),
5851 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5852 .rates = (SNDRV_PCM_RATE_32000 |
5853 SNDRV_PCM_RATE_44100 |
5854 SNDRV_PCM_RATE_48000 |
5855 SNDRV_PCM_RATE_64000 |
5856 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5857 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5861 .channels_max = HDSPM_MAX_CHANNELS,
5863 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5864 .period_bytes_min = (32 * 4),
5865 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5871 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5872 struct snd_pcm_hw_rule *rule)
5874 struct hdspm *hdspm = rule->private;
5875 struct snd_interval *c =
5876 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5877 struct snd_interval *r =
5878 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5880 if (r->min > 96000 && r->max <= 192000) {
5881 struct snd_interval t = {
5882 .min = hdspm->qs_in_channels,
5883 .max = hdspm->qs_in_channels,
5886 return snd_interval_refine(c, &t);
5887 } else if (r->min > 48000 && r->max <= 96000) {
5888 struct snd_interval t = {
5889 .min = hdspm->ds_in_channels,
5890 .max = hdspm->ds_in_channels,
5893 return snd_interval_refine(c, &t);
5894 } else if (r->max < 64000) {
5895 struct snd_interval t = {
5896 .min = hdspm->ss_in_channels,
5897 .max = hdspm->ss_in_channels,
5900 return snd_interval_refine(c, &t);
5906 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5907 struct snd_pcm_hw_rule * rule)
5909 struct hdspm *hdspm = rule->private;
5910 struct snd_interval *c =
5911 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5912 struct snd_interval *r =
5913 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5915 if (r->min > 96000 && r->max <= 192000) {
5916 struct snd_interval t = {
5917 .min = hdspm->qs_out_channels,
5918 .max = hdspm->qs_out_channels,
5921 return snd_interval_refine(c, &t);
5922 } else if (r->min > 48000 && r->max <= 96000) {
5923 struct snd_interval t = {
5924 .min = hdspm->ds_out_channels,
5925 .max = hdspm->ds_out_channels,
5928 return snd_interval_refine(c, &t);
5929 } else if (r->max < 64000) {
5930 struct snd_interval t = {
5931 .min = hdspm->ss_out_channels,
5932 .max = hdspm->ss_out_channels,
5935 return snd_interval_refine(c, &t);
5941 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5942 struct snd_pcm_hw_rule * rule)
5944 struct hdspm *hdspm = rule->private;
5945 struct snd_interval *c =
5946 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5947 struct snd_interval *r =
5948 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5950 if (c->min >= hdspm->ss_in_channels) {
5951 struct snd_interval t = {
5956 return snd_interval_refine(r, &t);
5957 } else if (c->max <= hdspm->qs_in_channels) {
5958 struct snd_interval t = {
5963 return snd_interval_refine(r, &t);
5964 } else if (c->max <= hdspm->ds_in_channels) {
5965 struct snd_interval t = {
5970 return snd_interval_refine(r, &t);
5975 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5976 struct snd_pcm_hw_rule *rule)
5978 struct hdspm *hdspm = rule->private;
5979 struct snd_interval *c =
5980 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5981 struct snd_interval *r =
5982 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5984 if (c->min >= hdspm->ss_out_channels) {
5985 struct snd_interval t = {
5990 return snd_interval_refine(r, &t);
5991 } else if (c->max <= hdspm->qs_out_channels) {
5992 struct snd_interval t = {
5997 return snd_interval_refine(r, &t);
5998 } else if (c->max <= hdspm->ds_out_channels) {
5999 struct snd_interval t = {
6004 return snd_interval_refine(r, &t);
6010 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
6011 struct snd_pcm_hw_rule *rule)
6013 unsigned int list[3];
6014 struct hdspm *hdspm = rule->private;
6015 struct snd_interval *c = hw_param_interval(params,
6016 SNDRV_PCM_HW_PARAM_CHANNELS);
6018 list[0] = hdspm->qs_in_channels;
6019 list[1] = hdspm->ds_in_channels;
6020 list[2] = hdspm->ss_in_channels;
6021 return snd_interval_list(c, 3, list, 0);
6024 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
6025 struct snd_pcm_hw_rule *rule)
6027 unsigned int list[3];
6028 struct hdspm *hdspm = rule->private;
6029 struct snd_interval *c = hw_param_interval(params,
6030 SNDRV_PCM_HW_PARAM_CHANNELS);
6032 list[0] = hdspm->qs_out_channels;
6033 list[1] = hdspm->ds_out_channels;
6034 list[2] = hdspm->ss_out_channels;
6035 return snd_interval_list(c, 3, list, 0);
6039 static unsigned int hdspm_aes32_sample_rates[] = {
6040 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
6043 static struct snd_pcm_hw_constraint_list
6044 hdspm_hw_constraints_aes32_sample_rates = {
6045 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
6046 .list = hdspm_aes32_sample_rates,
6050 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
6052 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6053 struct snd_pcm_runtime *runtime = substream->runtime;
6055 spin_lock_irq(&hdspm->lock);
6057 snd_pcm_set_sync(substream);
6060 runtime->hw = snd_hdspm_playback_subinfo;
6062 if (hdspm->capture_substream == NULL)
6063 hdspm_stop_audio(hdspm);
6065 hdspm->playback_pid = current->pid;
6066 hdspm->playback_substream = substream;
6068 spin_unlock_irq(&hdspm->lock);
6070 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6071 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6073 switch (hdspm->io_type) {
6076 snd_pcm_hw_constraint_minmax(runtime,
6077 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6079 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6080 snd_pcm_hw_constraint_minmax(runtime,
6081 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6086 snd_pcm_hw_constraint_minmax(runtime,
6087 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6092 if (AES32 == hdspm->io_type) {
6093 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6094 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6095 &hdspm_hw_constraints_aes32_sample_rates);
6097 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6098 snd_hdspm_hw_rule_rate_out_channels, hdspm,
6099 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6102 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6103 snd_hdspm_hw_rule_out_channels, hdspm,
6104 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6106 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6107 snd_hdspm_hw_rule_out_channels_rate, hdspm,
6108 SNDRV_PCM_HW_PARAM_RATE, -1);
6113 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6115 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6117 spin_lock_irq(&hdspm->lock);
6119 hdspm->playback_pid = -1;
6120 hdspm->playback_substream = NULL;
6122 spin_unlock_irq(&hdspm->lock);
6128 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6130 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6131 struct snd_pcm_runtime *runtime = substream->runtime;
6133 spin_lock_irq(&hdspm->lock);
6134 snd_pcm_set_sync(substream);
6135 runtime->hw = snd_hdspm_capture_subinfo;
6137 if (hdspm->playback_substream == NULL)
6138 hdspm_stop_audio(hdspm);
6140 hdspm->capture_pid = current->pid;
6141 hdspm->capture_substream = substream;
6143 spin_unlock_irq(&hdspm->lock);
6145 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6146 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6148 switch (hdspm->io_type) {
6151 snd_pcm_hw_constraint_minmax(runtime,
6152 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6154 snd_pcm_hw_constraint_minmax(runtime,
6155 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6160 snd_pcm_hw_constraint_minmax(runtime,
6161 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6166 if (AES32 == hdspm->io_type) {
6167 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6168 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6169 &hdspm_hw_constraints_aes32_sample_rates);
6171 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6172 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6173 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6176 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6177 snd_hdspm_hw_rule_in_channels, hdspm,
6178 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6180 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6181 snd_hdspm_hw_rule_in_channels_rate, hdspm,
6182 SNDRV_PCM_HW_PARAM_RATE, -1);
6187 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6189 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6191 spin_lock_irq(&hdspm->lock);
6193 hdspm->capture_pid = -1;
6194 hdspm->capture_substream = NULL;
6196 spin_unlock_irq(&hdspm->lock);
6200 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6202 /* we have nothing to initialize but the call is required */
6206 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6208 u32 val = readl(src);
6209 return copy_to_user(dest, &val, 4);
6212 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6213 unsigned int cmd, unsigned long arg)
6215 void __user *argp = (void __user *)arg;
6216 struct hdspm *hdspm = hw->private_data;
6217 struct hdspm_mixer_ioctl mixer;
6218 struct hdspm_config info;
6219 struct hdspm_status status;
6220 struct hdspm_version hdspm_version;
6221 struct hdspm_peak_rms *levels;
6222 struct hdspm_ltc ltc;
6223 unsigned int statusregister;
6224 long unsigned int s;
6229 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6230 levels = &hdspm->peak_rms;
6231 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6232 levels->input_peaks[i] =
6233 readl(hdspm->iobase +
6234 HDSPM_MADI_INPUT_PEAK + i*4);
6235 levels->playback_peaks[i] =
6236 readl(hdspm->iobase +
6237 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6238 levels->output_peaks[i] =
6239 readl(hdspm->iobase +
6240 HDSPM_MADI_OUTPUT_PEAK + i*4);
6242 levels->input_rms[i] =
6243 ((uint64_t) readl(hdspm->iobase +
6244 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6245 (uint64_t) readl(hdspm->iobase +
6246 HDSPM_MADI_INPUT_RMS_L + i*4);
6247 levels->playback_rms[i] =
6248 ((uint64_t)readl(hdspm->iobase +
6249 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6250 (uint64_t)readl(hdspm->iobase +
6251 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6252 levels->output_rms[i] =
6253 ((uint64_t)readl(hdspm->iobase +
6254 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6255 (uint64_t)readl(hdspm->iobase +
6256 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6259 if (hdspm->system_sample_rate > 96000) {
6261 } else if (hdspm->system_sample_rate > 48000) {
6266 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6268 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6270 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu
6271 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6277 case SNDRV_HDSPM_IOCTL_GET_LTC:
6278 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6279 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6280 if (i & HDSPM_TCO1_LTC_Input_valid) {
6281 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6282 HDSPM_TCO1_LTC_Format_MSB)) {
6284 ltc.format = fps_24;
6286 case HDSPM_TCO1_LTC_Format_LSB:
6287 ltc.format = fps_25;
6289 case HDSPM_TCO1_LTC_Format_MSB:
6290 ltc.format = fps_2997;
6293 ltc.format = fps_30;
6296 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6297 ltc.frame = drop_frame;
6299 ltc.frame = full_frame;
6302 ltc.format = format_invalid;
6303 ltc.frame = frame_invalid;
6305 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6306 ltc.input_format = ntsc;
6307 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6308 ltc.input_format = pal;
6310 ltc.input_format = no_video;
6313 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc));
6316 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6322 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6324 memset(&info, 0, sizeof(info));
6325 spin_lock_irq(&hdspm->lock);
6326 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6327 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6329 info.system_sample_rate = hdspm->system_sample_rate;
6330 info.autosync_sample_rate =
6331 hdspm_external_sample_rate(hdspm);
6332 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6333 info.clock_source = hdspm_clock_source(hdspm);
6334 info.autosync_ref = hdspm_autosync_ref(hdspm);
6335 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6337 spin_unlock_irq(&hdspm->lock);
6338 if (copy_to_user(argp, &info, sizeof(info)))
6342 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6343 memset(&status, 0, sizeof(status));
6345 status.card_type = hdspm->io_type;
6347 status.autosync_source = hdspm_autosync_ref(hdspm);
6349 status.card_clock = 110069313433624ULL;
6350 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6352 switch (hdspm->io_type) {
6355 status.card_specific.madi.sync_wc =
6356 hdspm_wc_sync_check(hdspm);
6357 status.card_specific.madi.sync_madi =
6358 hdspm_madi_sync_check(hdspm);
6359 status.card_specific.madi.sync_tco =
6360 hdspm_tco_sync_check(hdspm);
6361 status.card_specific.madi.sync_in =
6362 hdspm_sync_in_sync_check(hdspm);
6365 hdspm_read(hdspm, HDSPM_statusRegister);
6366 status.card_specific.madi.madi_input =
6367 (statusregister & HDSPM_AB_int) ? 1 : 0;
6368 status.card_specific.madi.channel_format =
6369 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6370 /* TODO: Mac driver sets it when f_s>48kHz */
6371 status.card_specific.madi.frame_format = 0;
6377 if (copy_to_user(argp, &status, sizeof(status)))
6383 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6384 memset(&hdspm_version, 0, sizeof(hdspm_version));
6386 hdspm_version.card_type = hdspm->io_type;
6387 strlcpy(hdspm_version.cardname, hdspm->card_name,
6388 sizeof(hdspm_version.cardname));
6389 hdspm_version.serial = hdspm->serial;
6390 hdspm_version.firmware_rev = hdspm->firmware_rev;
6391 hdspm_version.addons = 0;
6393 hdspm_version.addons |= HDSPM_ADDON_TCO;
6395 if (copy_to_user(argp, &hdspm_version,
6396 sizeof(hdspm_version)))
6400 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6401 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6403 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6404 sizeof(struct hdspm_mixer)))
6414 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6415 .open = snd_hdspm_playback_open,
6416 .close = snd_hdspm_playback_release,
6417 .ioctl = snd_hdspm_ioctl,
6418 .hw_params = snd_hdspm_hw_params,
6419 .hw_free = snd_hdspm_hw_free,
6420 .prepare = snd_hdspm_prepare,
6421 .trigger = snd_hdspm_trigger,
6422 .pointer = snd_hdspm_hw_pointer,
6423 .page = snd_pcm_sgbuf_ops_page,
6426 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6427 .open = snd_hdspm_capture_open,
6428 .close = snd_hdspm_capture_release,
6429 .ioctl = snd_hdspm_ioctl,
6430 .hw_params = snd_hdspm_hw_params,
6431 .hw_free = snd_hdspm_hw_free,
6432 .prepare = snd_hdspm_prepare,
6433 .trigger = snd_hdspm_trigger,
6434 .pointer = snd_hdspm_hw_pointer,
6435 .page = snd_pcm_sgbuf_ops_page,
6438 static int snd_hdspm_create_hwdep(struct snd_card *card,
6439 struct hdspm *hdspm)
6441 struct snd_hwdep *hw;
6444 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6449 hw->private_data = hdspm;
6450 strcpy(hw->name, "HDSPM hwdep interface");
6452 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6453 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6454 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6455 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6461 /*------------------------------------------------------------
6463 ------------------------------------------------------------*/
6464 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6467 struct snd_pcm *pcm;
6472 wanted = HDSPM_DMA_AREA_BYTES;
6475 snd_pcm_lib_preallocate_pages_for_all(pcm,
6476 SNDRV_DMA_TYPE_DEV_SG,
6477 snd_dma_pci_data(hdspm->pci),
6481 dev_dbg(hdspm->card->dev,
6482 "Could not preallocate %zd Bytes\n", wanted);
6486 dev_dbg(hdspm->card->dev,
6487 " Preallocated %zd Bytes\n", wanted);
6493 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6494 struct snd_pcm_substream *substream,
6495 unsigned int reg, int channels)
6499 /* continuous memory segment */
6500 for (i = 0; i < (channels * 16); i++)
6501 hdspm_write(hdspm, reg + 4 * i,
6502 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6506 /* ------------- ALSA Devices ---------------------------- */
6507 static int snd_hdspm_create_pcm(struct snd_card *card,
6508 struct hdspm *hdspm)
6510 struct snd_pcm *pcm;
6513 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6518 pcm->private_data = hdspm;
6519 strcpy(pcm->name, hdspm->card_name);
6521 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6522 &snd_hdspm_playback_ops);
6523 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6524 &snd_hdspm_capture_ops);
6526 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6528 err = snd_hdspm_preallocate_memory(hdspm);
6535 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6539 for (i = 0; i < hdspm->midiPorts; i++)
6540 snd_hdspm_flush_midi_input(hdspm, i);
6543 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6544 struct hdspm *hdspm)
6548 dev_dbg(card->dev, "Create card...\n");
6549 err = snd_hdspm_create_pcm(card, hdspm);
6554 while (i < hdspm->midiPorts) {
6555 err = snd_hdspm_create_midi(card, hdspm, i);
6562 err = snd_hdspm_create_controls(card, hdspm);
6566 err = snd_hdspm_create_hwdep(card, hdspm);
6570 dev_dbg(card->dev, "proc init...\n");
6571 snd_hdspm_proc_init(hdspm);
6573 hdspm->system_sample_rate = -1;
6574 hdspm->last_external_sample_rate = -1;
6575 hdspm->last_internal_sample_rate = -1;
6576 hdspm->playback_pid = -1;
6577 hdspm->capture_pid = -1;
6578 hdspm->capture_substream = NULL;
6579 hdspm->playback_substream = NULL;
6581 dev_dbg(card->dev, "Set defaults...\n");
6582 err = snd_hdspm_set_defaults(hdspm);
6586 dev_dbg(card->dev, "Update mixer controls...\n");
6587 hdspm_update_simple_mixer_controls(hdspm);
6589 dev_dbg(card->dev, "Initializeing complete ???\n");
6591 err = snd_card_register(card);
6593 dev_err(card->dev, "error registering card\n");
6597 dev_dbg(card->dev, "... yes now\n");
6602 static int snd_hdspm_create(struct snd_card *card,
6603 struct hdspm *hdspm)
6606 struct pci_dev *pci = hdspm->pci;
6608 unsigned long io_extent;
6613 spin_lock_init(&hdspm->lock);
6615 pci_read_config_word(hdspm->pci,
6616 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6618 strcpy(card->mixername, "Xilinx FPGA");
6619 strcpy(card->driver, "HDSPM");
6621 switch (hdspm->firmware_rev) {
6622 case HDSPM_RAYDAT_REV:
6623 hdspm->io_type = RayDAT;
6624 hdspm->card_name = "RME RayDAT";
6625 hdspm->midiPorts = 2;
6628 hdspm->io_type = AIO;
6629 hdspm->card_name = "RME AIO";
6630 hdspm->midiPorts = 1;
6632 case HDSPM_MADIFACE_REV:
6633 hdspm->io_type = MADIface;
6634 hdspm->card_name = "RME MADIface";
6635 hdspm->midiPorts = 1;
6638 if ((hdspm->firmware_rev == 0xf0) ||
6639 ((hdspm->firmware_rev >= 0xe6) &&
6640 (hdspm->firmware_rev <= 0xea))) {
6641 hdspm->io_type = AES32;
6642 hdspm->card_name = "RME AES32";
6643 hdspm->midiPorts = 2;
6644 } else if ((hdspm->firmware_rev == 0xd2) ||
6645 ((hdspm->firmware_rev >= 0xc8) &&
6646 (hdspm->firmware_rev <= 0xcf))) {
6647 hdspm->io_type = MADI;
6648 hdspm->card_name = "RME MADI";
6649 hdspm->midiPorts = 3;
6652 "unknown firmware revision %x\n",
6653 hdspm->firmware_rev);
6658 err = pci_enable_device(pci);
6662 pci_set_master(hdspm->pci);
6664 err = pci_request_regions(pci, "hdspm");
6668 hdspm->port = pci_resource_start(pci, 0);
6669 io_extent = pci_resource_len(pci, 0);
6671 dev_dbg(card->dev, "grabbed memory region 0x%lx-0x%lx\n",
6672 hdspm->port, hdspm->port + io_extent - 1);
6674 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6675 if (!hdspm->iobase) {
6676 dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n",
6677 hdspm->port, hdspm->port + io_extent - 1);
6680 dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n",
6681 (unsigned long)hdspm->iobase, hdspm->port,
6682 hdspm->port + io_extent - 1);
6684 if (request_irq(pci->irq, snd_hdspm_interrupt,
6685 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6686 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq);
6690 dev_dbg(card->dev, "use IRQ %d\n", pci->irq);
6692 hdspm->irq = pci->irq;
6694 dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n",
6695 sizeof(struct hdspm_mixer));
6696 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6697 if (!hdspm->mixer) {
6699 "unable to kmalloc Mixer memory of %d Bytes\n",
6700 (int)sizeof(struct hdspm_mixer));
6704 hdspm->port_names_in = NULL;
6705 hdspm->port_names_out = NULL;
6707 switch (hdspm->io_type) {
6709 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6710 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6711 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6713 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6715 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6717 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6719 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6721 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6723 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6726 hdspm->max_channels_out = hdspm->max_channels_in =
6728 hdspm->port_names_in = hdspm->port_names_out =
6730 hdspm->channel_map_in = hdspm->channel_map_out =
6737 hdspm->ss_in_channels = hdspm->ss_out_channels =
6739 hdspm->ds_in_channels = hdspm->ds_out_channels =
6741 hdspm->qs_in_channels = hdspm->qs_out_channels =
6744 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6745 channel_map_unity_ss;
6746 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6747 channel_map_unity_ss;
6748 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6749 channel_map_unity_ss;
6751 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6753 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6755 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6760 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6761 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6762 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6763 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6764 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6765 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6767 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6768 dev_info(card->dev, "AEB input board found\n");
6769 hdspm->ss_in_channels += 4;
6770 hdspm->ds_in_channels += 4;
6771 hdspm->qs_in_channels += 4;
6774 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6775 dev_info(card->dev, "AEB output board found\n");
6776 hdspm->ss_out_channels += 4;
6777 hdspm->ds_out_channels += 4;
6778 hdspm->qs_out_channels += 4;
6781 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6782 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6783 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6785 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6786 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6787 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6789 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6790 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6791 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6792 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6793 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6794 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6799 hdspm->ss_in_channels = hdspm->ss_out_channels =
6801 hdspm->ds_in_channels = hdspm->ds_out_channels =
6803 hdspm->qs_in_channels = hdspm->qs_out_channels =
6806 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6807 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6809 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6810 channel_map_raydat_ss;
6811 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6812 channel_map_raydat_ds;
6813 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6814 channel_map_raydat_qs;
6815 hdspm->channel_map_in = hdspm->channel_map_out =
6816 channel_map_raydat_ss;
6818 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6819 texts_ports_raydat_ss;
6820 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6821 texts_ports_raydat_ds;
6822 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6823 texts_ports_raydat_qs;
6831 switch (hdspm->io_type) {
6834 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6835 HDSPM_s2_tco_detect) {
6837 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6839 if (NULL != hdspm->tco) {
6840 hdspm_tco_write(hdspm);
6842 dev_info(card->dev, "AIO/RayDAT TCO module found\n");
6850 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6852 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6854 if (NULL != hdspm->tco) {
6855 hdspm_tco_write(hdspm);
6857 dev_info(card->dev, "MADI/AES TCO module found\n");
6868 switch (hdspm->io_type) {
6871 hdspm->texts_autosync = texts_autosync_aes_tco;
6872 hdspm->texts_autosync_items =
6873 ARRAY_SIZE(texts_autosync_aes_tco);
6875 hdspm->texts_autosync = texts_autosync_aes;
6876 hdspm->texts_autosync_items =
6877 ARRAY_SIZE(texts_autosync_aes);
6883 hdspm->texts_autosync = texts_autosync_madi_tco;
6884 hdspm->texts_autosync_items = 4;
6886 hdspm->texts_autosync = texts_autosync_madi;
6887 hdspm->texts_autosync_items = 3;
6897 hdspm->texts_autosync = texts_autosync_raydat_tco;
6898 hdspm->texts_autosync_items = 9;
6900 hdspm->texts_autosync = texts_autosync_raydat;
6901 hdspm->texts_autosync_items = 8;
6907 hdspm->texts_autosync = texts_autosync_aio_tco;
6908 hdspm->texts_autosync_items = 6;
6910 hdspm->texts_autosync = texts_autosync_aio;
6911 hdspm->texts_autosync_items = 5;
6917 tasklet_init(&hdspm->midi_tasklet,
6918 hdspm_midi_tasklet, (unsigned long) hdspm);
6921 if (hdspm->io_type != MADIface) {
6922 hdspm->serial = (hdspm_read(hdspm,
6923 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6924 /* id contains either a user-provided value or the default
6925 * NULL. If it's the default, we're safe to
6926 * fill card->id with the serial number.
6928 * If the serial number is 0xFFFFFF, then we're dealing with
6929 * an old PCI revision that comes without a sane number. In
6930 * this case, we don't set card->id to avoid collisions
6931 * when running with multiple cards.
6933 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6934 sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6935 snd_card_set_id(card, card->id);
6939 dev_dbg(card->dev, "create alsa devices.\n");
6940 err = snd_hdspm_create_alsa_devices(card, hdspm);
6944 snd_hdspm_initialize_midi_flush(hdspm);
6950 static int snd_hdspm_free(struct hdspm * hdspm)
6955 /* stop th audio, and cancel all interrupts */
6956 hdspm->control_register &=
6957 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6958 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6959 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6960 hdspm_write(hdspm, HDSPM_controlRegister,
6961 hdspm->control_register);
6964 if (hdspm->irq >= 0)
6965 free_irq(hdspm->irq, (void *) hdspm);
6967 kfree(hdspm->mixer);
6970 iounmap(hdspm->iobase);
6973 pci_release_regions(hdspm->pci);
6975 pci_disable_device(hdspm->pci);
6980 static void snd_hdspm_card_free(struct snd_card *card)
6982 struct hdspm *hdspm = card->private_data;
6985 snd_hdspm_free(hdspm);
6989 static int snd_hdspm_probe(struct pci_dev *pci,
6990 const struct pci_device_id *pci_id)
6993 struct hdspm *hdspm;
6994 struct snd_card *card;
6997 if (dev >= SNDRV_CARDS)
7004 err = snd_card_new(&pci->dev, index[dev], id[dev],
7005 THIS_MODULE, sizeof(struct hdspm), &card);
7009 hdspm = card->private_data;
7010 card->private_free = snd_hdspm_card_free;
7014 err = snd_hdspm_create(card, hdspm);
7016 snd_card_free(card);
7020 if (hdspm->io_type != MADIface) {
7021 sprintf(card->shortname, "%s_%x",
7024 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
7027 hdspm->port, hdspm->irq);
7029 sprintf(card->shortname, "%s", hdspm->card_name);
7030 sprintf(card->longname, "%s at 0x%lx, irq %d",
7031 hdspm->card_name, hdspm->port, hdspm->irq);
7034 err = snd_card_register(card);
7036 snd_card_free(card);
7040 pci_set_drvdata(pci, card);
7046 static void snd_hdspm_remove(struct pci_dev *pci)
7048 snd_card_free(pci_get_drvdata(pci));
7051 static struct pci_driver hdspm_driver = {
7052 .name = KBUILD_MODNAME,
7053 .id_table = snd_hdspm_ids,
7054 .probe = snd_hdspm_probe,
7055 .remove = snd_hdspm_remove,
7058 module_pci_driver(hdspm_driver);