sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/dma-mapping.h>
  45 #include <sound/core.h>
  46 #include <sound/info.h>
  47 #include <sound/control.h>
  48 #include <sound/pcm.h>
  49 #include <sound/mpu401.h>
  50 #include <sound/ac97_codec.h>
  51 #include <sound/initval.h>
  52
  53 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  54 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  55 MODULE_LICENSE("GPL");
  56 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  57                 "{ESS,ES1988},"
  58                 "{ESS,Allegro PCI},"
  59                 "{ESS,Allegro-1 PCI},"
  60                 "{ESS,Canyon3D-2/LE PCI}}");
  61
  62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  65 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  66 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  67
  68 module_param_array(index, int, NULL, 0444);
  69 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  70 module_param_array(id, charp, NULL, 0444);
  71 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  72 module_param_array(enable, bool, NULL, 0444);
  73 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  74 module_param_array(external_amp, bool, NULL, 0444);
  75 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  76 module_param_array(amp_gpio, int, NULL, 0444);
  77 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  78
  79 #define MAX_PLAYBACKS   2
  80 #define MAX_CAPTURES    1
  81 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  82
  83
  84 /*
  85  * maestro3 registers
  86  */
  87
  88 /* Allegro PCI configuration registers */
  89 #define PCI_LEGACY_AUDIO_CTRL   0x40
  90 #define SOUND_BLASTER_ENABLE    0x00000001
  91 #define FM_SYNTHESIS_ENABLE     0x00000002
  92 #define GAME_PORT_ENABLE        0x00000004
  93 #define MPU401_IO_ENABLE        0x00000008
  94 #define MPU401_IRQ_ENABLE       0x00000010
  95 #define ALIAS_10BIT_IO          0x00000020
  96 #define SB_DMA_MASK             0x000000C0
  97 #define SB_DMA_0                0x00000040
  98 #define SB_DMA_1                0x00000040
  99 #define SB_DMA_R                0x00000080
 100 #define SB_DMA_3                0x000000C0
 101 #define SB_IRQ_MASK             0x00000700
 102 #define SB_IRQ_5                0x00000000
 103 #define SB_IRQ_7                0x00000100
 104 #define SB_IRQ_9                0x00000200
 105 #define SB_IRQ_10               0x00000300
 106 #define MIDI_IRQ_MASK           0x00003800
 107 #define SERIAL_IRQ_ENABLE       0x00004000
 108 #define DISABLE_LEGACY          0x00008000
 109
 110 #define PCI_ALLEGRO_CONFIG      0x50
 111 #define SB_ADDR_240             0x00000004
 112 #define MPU_ADDR_MASK           0x00000018
 113 #define MPU_ADDR_330            0x00000000
 114 #define MPU_ADDR_300            0x00000008
 115 #define MPU_ADDR_320            0x00000010
 116 #define MPU_ADDR_340            0x00000018
 117 #define USE_PCI_TIMING          0x00000040
 118 #define POSTED_WRITE_ENABLE     0x00000080
 119 #define DMA_POLICY_MASK         0x00000700
 120 #define DMA_DDMA                0x00000000
 121 #define DMA_TDMA                0x00000100
 122 #define DMA_PCPCI               0x00000200
 123 #define DMA_WBDMA16             0x00000400
 124 #define DMA_WBDMA4              0x00000500
 125 #define DMA_WBDMA2              0x00000600
 126 #define DMA_WBDMA1              0x00000700
 127 #define DMA_SAFE_GUARD          0x00000800
 128 #define HI_PERF_GP_ENABLE       0x00001000
 129 #define PIC_SNOOP_MODE_0        0x00002000
 130 #define PIC_SNOOP_MODE_1        0x00004000
 131 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 132 #define RING_IN_ENABLE          0x00010000
 133 #define SPDIF_TEST_MODE         0x00020000
 134 #define CLK_MULT_MODE_SELECT_2  0x00040000
 135 #define EEPROM_WRITE_ENABLE     0x00080000
 136 #define CODEC_DIR_IN            0x00100000
 137 #define HV_BUTTON_FROM_GD       0x00200000
 138 #define REDUCED_DEBOUNCE        0x00400000
 139 #define HV_CTRL_ENABLE          0x00800000
 140 #define SPDIF_ENABLE            0x01000000
 141 #define CLK_DIV_SELECT          0x06000000
 142 #define CLK_DIV_BY_48           0x00000000
 143 #define CLK_DIV_BY_49           0x02000000
 144 #define CLK_DIV_BY_50           0x04000000
 145 #define CLK_DIV_RESERVED        0x06000000
 146 #define PM_CTRL_ENABLE          0x08000000
 147 #define CLK_MULT_MODE_SELECT    0x30000000
 148 #define CLK_MULT_MODE_SHIFT     28
 149 #define CLK_MULT_MODE_0         0x00000000
 150 #define CLK_MULT_MODE_1         0x10000000
 151 #define CLK_MULT_MODE_2         0x20000000
 152 #define CLK_MULT_MODE_3         0x30000000
 153 #define INT_CLK_SELECT          0x40000000
 154 #define INT_CLK_MULT_RESET      0x80000000
 155
 156 /* M3 */
 157 #define INT_CLK_SRC_NOT_PCI     0x00100000
 158 #define INT_CLK_MULT_ENABLE     0x80000000
 159
 160 #define PCI_ACPI_CONTROL        0x54
 161 #define PCI_ACPI_D0             0x00000000
 162 #define PCI_ACPI_D1             0xB4F70000
 163 #define PCI_ACPI_D2             0xB4F7B4F7
 164
 165 #define PCI_USER_CONFIG         0x58
 166 #define EXT_PCI_MASTER_ENABLE   0x00000001
 167 #define SPDIF_OUT_SELECT        0x00000002
 168 #define TEST_PIN_DIR_CTRL       0x00000004
 169 #define AC97_CODEC_TEST         0x00000020
 170 #define TRI_STATE_BUFFER        0x00000080
 171 #define IN_CLK_12MHZ_SELECT     0x00000100
 172 #define MULTI_FUNC_DISABLE      0x00000200
 173 #define EXT_MASTER_PAIR_SEL     0x00000400
 174 #define PCI_MASTER_SUPPORT      0x00000800
 175 #define STOP_CLOCK_ENABLE       0x00001000
 176 #define EAPD_DRIVE_ENABLE       0x00002000
 177 #define REQ_TRI_STATE_ENABLE    0x00004000
 178 #define REQ_LOW_ENABLE          0x00008000
 179 #define MIDI_1_ENABLE           0x00010000
 180 #define MIDI_2_ENABLE           0x00020000
 181 #define SB_AUDIO_SYNC           0x00040000
 182 #define HV_CTRL_TEST            0x00100000
 183 #define SOUNDBLASTER_TEST       0x00400000
 184
 185 #define PCI_USER_CONFIG_C       0x5C
 186
 187 #define PCI_DDMA_CTRL           0x60
 188 #define DDMA_ENABLE             0x00000001
 189
 190
 191 /* Allegro registers */
 192 #define HOST_INT_CTRL           0x18
 193 #define SB_INT_ENABLE           0x0001
 194 #define MPU401_INT_ENABLE       0x0002
 195 #define ASSP_INT_ENABLE         0x0010
 196 #define RING_INT_ENABLE         0x0020
 197 #define HV_INT_ENABLE           0x0040
 198 #define CLKRUN_GEN_ENABLE       0x0100
 199 #define HV_CTRL_TO_PME          0x0400
 200 #define SOFTWARE_RESET_ENABLE   0x8000
 201
 202 /*
 203  * should be using the above defines, probably.
 204  */
 205 #define REGB_ENABLE_RESET               0x01
 206 #define REGB_STOP_CLOCK                 0x10
 207
 208 #define HOST_INT_STATUS         0x1A
 209 #define SB_INT_PENDING          0x01
 210 #define MPU401_INT_PENDING      0x02
 211 #define ASSP_INT_PENDING        0x10
 212 #define RING_INT_PENDING        0x20
 213 #define HV_INT_PENDING          0x40
 214
 215 #define HARDWARE_VOL_CTRL       0x1B
 216 #define SHADOW_MIX_REG_VOICE    0x1C
 217 #define HW_VOL_COUNTER_VOICE    0x1D
 218 #define SHADOW_MIX_REG_MASTER   0x1E
 219 #define HW_VOL_COUNTER_MASTER   0x1F
 220
 221 #define CODEC_COMMAND           0x30
 222 #define CODEC_READ_B            0x80
 223
 224 #define CODEC_STATUS            0x30
 225 #define CODEC_BUSY_B            0x01
 226
 227 #define CODEC_DATA              0x32
 228
 229 #define RING_BUS_CTRL_A         0x36
 230 #define RAC_PME_ENABLE          0x0100
 231 #define RAC_SDFS_ENABLE         0x0200
 232 #define LAC_PME_ENABLE          0x0400
 233 #define LAC_SDFS_ENABLE         0x0800
 234 #define SERIAL_AC_LINK_ENABLE   0x1000
 235 #define IO_SRAM_ENABLE          0x2000
 236 #define IIS_INPUT_ENABLE        0x8000
 237
 238 #define RING_BUS_CTRL_B         0x38
 239 #define SECOND_CODEC_ID_MASK    0x0003
 240 #define SPDIF_FUNC_ENABLE       0x0010
 241 #define SECOND_AC_ENABLE        0x0020
 242 #define SB_MODULE_INTF_ENABLE   0x0040
 243 #define SSPE_ENABLE             0x0040
 244 #define M3I_DOCK_ENABLE         0x0080
 245
 246 #define SDO_OUT_DEST_CTRL       0x3A
 247 #define COMMAND_ADDR_OUT        0x0003
 248 #define PCM_LR_OUT_LOCAL        0x0000
 249 #define PCM_LR_OUT_REMOTE       0x0004
 250 #define PCM_LR_OUT_MUTE         0x0008
 251 #define PCM_LR_OUT_BOTH         0x000C
 252 #define LINE1_DAC_OUT_LOCAL     0x0000
 253 #define LINE1_DAC_OUT_REMOTE    0x0010
 254 #define LINE1_DAC_OUT_MUTE      0x0020
 255 #define LINE1_DAC_OUT_BOTH      0x0030
 256 #define PCM_CLS_OUT_LOCAL       0x0000
 257 #define PCM_CLS_OUT_REMOTE      0x0040
 258 #define PCM_CLS_OUT_MUTE        0x0080
 259 #define PCM_CLS_OUT_BOTH        0x00C0
 260 #define PCM_RLF_OUT_LOCAL       0x0000
 261 #define PCM_RLF_OUT_REMOTE      0x0100
 262 #define PCM_RLF_OUT_MUTE        0x0200
 263 #define PCM_RLF_OUT_BOTH        0x0300
 264 #define LINE2_DAC_OUT_LOCAL     0x0000
 265 #define LINE2_DAC_OUT_REMOTE    0x0400
 266 #define LINE2_DAC_OUT_MUTE      0x0800
 267 #define LINE2_DAC_OUT_BOTH      0x0C00
 268 #define HANDSET_OUT_LOCAL       0x0000
 269 #define HANDSET_OUT_REMOTE      0x1000
 270 #define HANDSET_OUT_MUTE        0x2000
 271 #define HANDSET_OUT_BOTH        0x3000
 272 #define IO_CTRL_OUT_LOCAL       0x0000
 273 #define IO_CTRL_OUT_REMOTE      0x4000
 274 #define IO_CTRL_OUT_MUTE        0x8000
 275 #define IO_CTRL_OUT_BOTH        0xC000
 276
 277 #define SDO_IN_DEST_CTRL        0x3C
 278 #define STATUS_ADDR_IN          0x0003
 279 #define PCM_LR_IN_LOCAL         0x0000
 280 #define PCM_LR_IN_REMOTE        0x0004
 281 #define PCM_LR_RESERVED         0x0008
 282 #define PCM_LR_IN_BOTH          0x000C
 283 #define LINE1_ADC_IN_LOCAL      0x0000
 284 #define LINE1_ADC_IN_REMOTE     0x0010
 285 #define LINE1_ADC_IN_MUTE       0x0020
 286 #define MIC_ADC_IN_LOCAL        0x0000
 287 #define MIC_ADC_IN_REMOTE       0x0040
 288 #define MIC_ADC_IN_MUTE         0x0080
 289 #define LINE2_DAC_IN_LOCAL      0x0000
 290 #define LINE2_DAC_IN_REMOTE     0x0400
 291 #define LINE2_DAC_IN_MUTE       0x0800
 292 #define HANDSET_IN_LOCAL        0x0000
 293 #define HANDSET_IN_REMOTE       0x1000
 294 #define HANDSET_IN_MUTE         0x2000
 295 #define IO_STATUS_IN_LOCAL      0x0000
 296 #define IO_STATUS_IN_REMOTE     0x4000
 297
 298 #define SPDIF_IN_CTRL           0x3E
 299 #define SPDIF_IN_ENABLE         0x0001
 300
 301 #define GPIO_DATA               0x60
 302 #define GPIO_DATA_MASK          0x0FFF
 303 #define GPIO_HV_STATUS          0x3000
 304 #define GPIO_PME_STATUS         0x4000
 305
 306 #define GPIO_MASK               0x64
 307 #define GPIO_DIRECTION          0x68
 308 #define GPO_PRIMARY_AC97        0x0001
 309 #define GPI_LINEOUT_SENSE       0x0004
 310 #define GPO_SECONDARY_AC97      0x0008
 311 #define GPI_VOL_DOWN            0x0010
 312 #define GPI_VOL_UP              0x0020
 313 #define GPI_IIS_CLK             0x0040
 314 #define GPI_IIS_LRCLK           0x0080
 315 #define GPI_IIS_DATA            0x0100
 316 #define GPI_DOCKING_STATUS      0x0100
 317 #define GPI_HEADPHONE_SENSE     0x0200
 318 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 319
 320 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 321 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 322
 323 /* M3 */
 324 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 325
 326 #define ASSP_INDEX_PORT         0x80
 327 #define ASSP_MEMORY_PORT        0x82
 328 #define ASSP_DATA_PORT          0x84
 329
 330 #define MPU401_DATA_PORT        0x98
 331 #define MPU401_STATUS_PORT      0x99
 332
 333 #define CLK_MULT_DATA_PORT      0x9C
 334
 335 #define ASSP_CONTROL_A          0xA2
 336 #define ASSP_0_WS_ENABLE        0x01
 337 #define ASSP_CTRL_A_RESERVED1   0x02
 338 #define ASSP_CTRL_A_RESERVED2   0x04
 339 #define ASSP_CLK_49MHZ_SELECT   0x08
 340 #define FAST_PLU_ENABLE         0x10
 341 #define ASSP_CTRL_A_RESERVED3   0x20
 342 #define DSP_CLK_36MHZ_SELECT    0x40
 343
 344 #define ASSP_CONTROL_B          0xA4
 345 #define RESET_ASSP              0x00
 346 #define RUN_ASSP                0x01
 347 #define ENABLE_ASSP_CLOCK       0x00
 348 #define STOP_ASSP_CLOCK         0x10
 349 #define RESET_TOGGLE            0x40
 350
 351 #define ASSP_CONTROL_C          0xA6
 352 #define ASSP_HOST_INT_ENABLE    0x01
 353 #define FM_ADDR_REMAP_DISABLE   0x02
 354 #define HOST_WRITE_PORT_ENABLE  0x08
 355
 356 #define ASSP_HOST_INT_STATUS    0xAC
 357 #define DSP2HOST_REQ_PIORECORD  0x01
 358 #define DSP2HOST_REQ_I2SRATE    0x02
 359 #define DSP2HOST_REQ_TIMER      0x04
 360
 361 /* AC97 registers */
 362 /* XXX fix this crap up */
 363 /*#define AC97_RESET              0x00*/
 364
 365 #define AC97_VOL_MUTE_B         0x8000
 366 #define AC97_VOL_M              0x1F
 367 #define AC97_LEFT_VOL_S         8
 368
 369 #define AC97_MASTER_VOL         0x02
 370 #define AC97_LINE_LEVEL_VOL     0x04
 371 #define AC97_MASTER_MONO_VOL    0x06
 372 #define AC97_PC_BEEP_VOL        0x0A
 373 #define AC97_PC_BEEP_VOL_M      0x0F
 374 #define AC97_SROUND_MASTER_VOL  0x38
 375 #define AC97_PC_BEEP_VOL_S      1
 376
 377 /*#define AC97_PHONE_VOL          0x0C
 378 #define AC97_MIC_VOL            0x0E*/
 379 #define AC97_MIC_20DB_ENABLE    0x40
 380
 381 /*#define AC97_LINEIN_VOL         0x10
 382 #define AC97_CD_VOL             0x12
 383 #define AC97_VIDEO_VOL          0x14
 384 #define AC97_AUX_VOL            0x16*/
 385 #define AC97_PCM_OUT_VOL        0x18
 386 /*#define AC97_RECORD_SELECT      0x1A*/
 387 #define AC97_RECORD_MIC         0x00
 388 #define AC97_RECORD_CD          0x01
 389 #define AC97_RECORD_VIDEO       0x02
 390 #define AC97_RECORD_AUX         0x03
 391 #define AC97_RECORD_MONO_MUX    0x02
 392 #define AC97_RECORD_DIGITAL     0x03
 393 #define AC97_RECORD_LINE        0x04
 394 #define AC97_RECORD_STEREO      0x05
 395 #define AC97_RECORD_MONO        0x06
 396 #define AC97_RECORD_PHONE       0x07
 397
 398 /*#define AC97_RECORD_GAIN        0x1C*/
 399 #define AC97_RECORD_VOL_M       0x0F
 400
 401 /*#define AC97_GENERAL_PURPOSE    0x20*/
 402 #define AC97_POWER_DOWN_CTRL    0x26
 403 #define AC97_ADC_READY          0x0001
 404 #define AC97_DAC_READY          0x0002
 405 #define AC97_ANALOG_READY       0x0004
 406 #define AC97_VREF_ON            0x0008
 407 #define AC97_PR0                0x0100
 408 #define AC97_PR1                0x0200
 409 #define AC97_PR2                0x0400
 410 #define AC97_PR3                0x0800
 411 #define AC97_PR4                0x1000
 412
 413 #define AC97_RESERVED1          0x28
 414
 415 #define AC97_VENDOR_TEST        0x5A
 416
 417 #define AC97_CLOCK_DELAY        0x5C
 418 #define AC97_LINEOUT_MUX_SEL    0x0001
 419 #define AC97_MONO_MUX_SEL       0x0002
 420 #define AC97_CLOCK_DELAY_SEL    0x1F
 421 #define AC97_DAC_CDS_SHIFT      6
 422 #define AC97_ADC_CDS_SHIFT      11
 423
 424 #define AC97_MULTI_CHANNEL_SEL  0x74
 425
 426 /*#define AC97_VENDOR_ID1         0x7C
 427 #define AC97_VENDOR_ID2         0x7E*/
 428
 429 /*
 430  * ASSP control regs
 431  */
 432 #define DSP_PORT_TIMER_COUNT    0x06
 433
 434 #define DSP_PORT_MEMORY_INDEX   0x80
 435
 436 #define DSP_PORT_MEMORY_TYPE    0x82
 437 #define MEMTYPE_INTERNAL_CODE   0x0002
 438 #define MEMTYPE_INTERNAL_DATA   0x0003
 439 #define MEMTYPE_MASK            0x0003
 440
 441 #define DSP_PORT_MEMORY_DATA    0x84
 442
 443 #define DSP_PORT_CONTROL_REG_A  0xA2
 444 #define DSP_PORT_CONTROL_REG_B  0xA4
 445 #define DSP_PORT_CONTROL_REG_C  0xA6
 446
 447 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 448 #define REV_A_CODE_MEMORY_END           0x0FFF
 449 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 450 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 451
 452 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 453 #define REV_B_CODE_MEMORY_END           0x0BFF
 454 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 455 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 456
 457 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 458 #define REV_A_DATA_MEMORY_END           0x2FFF
 459 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 460 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 461
 462 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 463 #define REV_B_DATA_MEMORY_END           0x2BFF
 464 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 465 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 466
 467
 468 #define NUM_UNITS_KERNEL_CODE          16
 469 #define NUM_UNITS_KERNEL_DATA           2
 470
 471 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 472 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 473
 474 /*
 475  * Kernel data layout
 476  */
 477
 478 #define DP_SHIFT_COUNT                  7
 479
 480 #define KDATA_BASE_ADDR                 0x1000
 481 #define KDATA_BASE_ADDR2                0x1080
 482
 483 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 484 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 485 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 486 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 487 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 488 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 489 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 490 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 491 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 492
 493 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 494 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 495
 496 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 497 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 498 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 499 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 500 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 501 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 502 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 503 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 504 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 505 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 506
 507 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 508 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 509
 510 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 511 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 512
 513 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 514 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 515
 516 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 517 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 518 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 519
 520 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 521 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 522 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 523 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 524 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 525
 526 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 527 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 528 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 529
 530 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 531 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 532 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 533
 534 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 535 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 536 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 537 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 538 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 539 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 540 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 541 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 542 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 543 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 544
 545 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 546 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 547 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 548
 549 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 550 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 551
 552 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 553 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 554 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 555
 556 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 557 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 558 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 559 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 560 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 561 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 562
 563 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 564 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 565 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 566 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 567 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 568 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 569
 570 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 571 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 572 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 573 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 574 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 575 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 576
 577 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 578 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 579 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 580 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 581
 582 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 583 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 584
 585 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 586 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 587
 588 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 589 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 590 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 591 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 592 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 593
 594 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 595 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 596
 597 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 598 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 599 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 600
 601 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 602 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 603
 604 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 605
 606 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 607 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 608 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 609 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 610 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 611 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 612 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 613 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 614 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 615 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 616 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 617 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 618
 619 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 620 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 621 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 622 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 623
 624 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 625 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 626
 627 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 628 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 629 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 630 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 631
 632 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 633 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 634 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 635 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 636 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 637
 638 /*
 639  * second 'segment' (?) reserved for mixer
 640  * buffers..
 641  */
 642
 643 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 644 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 645 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 646 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 647 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 648 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 649 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 650 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 651 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 652 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 653 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 654 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 655 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 656 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 657 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 658 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 659
 660 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 661 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 662 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 663 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 664 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 665 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 666 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 667 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 668 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 669 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 670 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 671
 672 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 673 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 674 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 675 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 676 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 677 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 678
 679 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 680 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 681 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 682 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 683
 684 /*
 685  * client data area offsets
 686  */
 687 #define CDATA_INSTANCE_READY            0x00
 688
 689 #define CDATA_HOST_SRC_ADDRL            0x01
 690 #define CDATA_HOST_SRC_ADDRH            0x02
 691 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 692 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 693 #define CDATA_HOST_SRC_CURRENTL         0x05
 694 #define CDATA_HOST_SRC_CURRENTH         0x06
 695
 696 #define CDATA_IN_BUF_CONNECT            0x07
 697 #define CDATA_OUT_BUF_CONNECT           0x08
 698
 699 #define CDATA_IN_BUF_BEGIN              0x09
 700 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 701 #define CDATA_IN_BUF_HEAD               0x0B
 702 #define CDATA_IN_BUF_TAIL               0x0C
 703 #define CDATA_OUT_BUF_BEGIN             0x0D
 704 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 705 #define CDATA_OUT_BUF_HEAD              0x0F
 706 #define CDATA_OUT_BUF_TAIL              0x10
 707
 708 #define CDATA_DMA_CONTROL               0x11
 709 #define CDATA_RESERVED                  0x12
 710
 711 #define CDATA_FREQUENCY                 0x13
 712 #define CDATA_LEFT_VOLUME               0x14
 713 #define CDATA_RIGHT_VOLUME              0x15
 714 #define CDATA_LEFT_SUR_VOL              0x16
 715 #define CDATA_RIGHT_SUR_VOL             0x17
 716
 717 #define CDATA_HEADER_LEN                0x18
 718
 719 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 720 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 721 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 722 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 723 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 724 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 725 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 726 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 727
 728 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 729 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 730 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 731 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 732 #define MINISRC_BIQUAD_STAGE    2
 733 #define MINISRC_COEF_LOC          0x175
 734
 735 #define DMACONTROL_BLOCK_MASK           0x000F
 736 #define  DMAC_BLOCK0_SELECTOR           0x0000
 737 #define  DMAC_BLOCK1_SELECTOR           0x0001
 738 #define  DMAC_BLOCK2_SELECTOR           0x0002
 739 #define  DMAC_BLOCK3_SELECTOR           0x0003
 740 #define  DMAC_BLOCK4_SELECTOR           0x0004
 741 #define  DMAC_BLOCK5_SELECTOR           0x0005
 742 #define  DMAC_BLOCK6_SELECTOR           0x0006
 743 #define  DMAC_BLOCK7_SELECTOR           0x0007
 744 #define  DMAC_BLOCK8_SELECTOR           0x0008
 745 #define  DMAC_BLOCK9_SELECTOR           0x0009
 746 #define  DMAC_BLOCKA_SELECTOR           0x000A
 747 #define  DMAC_BLOCKB_SELECTOR           0x000B
 748 #define  DMAC_BLOCKC_SELECTOR           0x000C
 749 #define  DMAC_BLOCKD_SELECTOR           0x000D
 750 #define  DMAC_BLOCKE_SELECTOR           0x000E
 751 #define  DMAC_BLOCKF_SELECTOR           0x000F
 752 #define DMACONTROL_PAGE_MASK            0x00F0
 753 #define  DMAC_PAGE0_SELECTOR            0x0030
 754 #define  DMAC_PAGE1_SELECTOR            0x0020
 755 #define  DMAC_PAGE2_SELECTOR            0x0010
 756 #define  DMAC_PAGE3_SELECTOR            0x0000
 757 #define DMACONTROL_AUTOREPEAT           0x1000
 758 #define DMACONTROL_STOPPED              0x2000
 759 #define DMACONTROL_DIRECTION            0x0100
 760
 761 /*
 762  * an arbitrary volume we set the internal
 763  * volume settings to so that the ac97 volume
 764  * range is a little less insane.  0x7fff is
 765  * max.
 766  */
 767 #define ARB_VOLUME ( 0x6800 )
 768
 769 /*
 770  */
 771
 772 /* quirk lists */
 773 struct m3_quirk {
 774         const char *name;       /* device name */
 775         u16 vendor, device;     /* subsystem ids */
 776         int amp_gpio;           /* gpio pin #  for external amp, -1 = default */
 777         int irda_workaround;    /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION
 778                                    (e.g. for IrDA on Dell Inspirons) */
 779 };
 780
 781 struct m3_hv_quirk {
 782         u16 vendor, device, subsystem_vendor, subsystem_device;
 783         u32 config;             /* ALLEGRO_CONFIG hardware volume bits */
 784         int is_omnibook;        /* Do HP OmniBook GPIO magic? */
 785 };
 786
 787 struct m3_list {
 788         int curlen;
 789         int mem_addr;
 790         int max;
 791 };
 792
 793 struct m3_dma {
 794
 795         int number;
 796         struct snd_pcm_substream *substream;
 797
 798         struct assp_instance {
 799                 unsigned short code, data;
 800         } inst;
 801
 802         int running;
 803         int opened;
 804
 805         unsigned long buffer_addr;
 806         int dma_size;
 807         int period_size;
 808         unsigned int hwptr;
 809         int count;
 810
 811         int index[3];
 812         struct m3_list *index_list[3];
 813
 814         int in_lists;
 815
 816         struct list_head list;
 817
 818 };
 819
 820 struct snd_m3 {
 821
 822         struct snd_card *card;
 823
 824         unsigned long iobase;
 825
 826         int irq;
 827         unsigned int allegro_flag : 1;
 828
 829         struct snd_ac97 *ac97;
 830
 831         struct snd_pcm *pcm;
 832
 833         struct pci_dev *pci;
 834         const struct m3_quirk *quirk;
 835         const struct m3_hv_quirk *hv_quirk;
 836
 837         int dacs_active;
 838         int timer_users;
 839
 840         struct m3_list  msrc_list;
 841         struct m3_list  mixer_list;
 842         struct m3_list  adc1_list;
 843         struct m3_list  dma_list;
 844
 845         /* for storing reset state..*/
 846         u8 reset_state;
 847
 848         int external_amp;
 849         int amp_gpio;
 850
 851         /* midi */
 852         struct snd_rawmidi *rmidi;
 853
 854         /* pcm streams */
 855         int num_substreams;
 856         struct m3_dma *substreams;
 857
 858         spinlock_t reg_lock;
 859         spinlock_t ac97_lock;
 860
 861         struct snd_kcontrol *master_switch;
 862         struct snd_kcontrol *master_volume;
 863         struct tasklet_struct hwvol_tq;
 864
 865 #ifdef CONFIG_PM
 866         u16 *suspend_mem;
 867 #endif
 868 };
 869
 870 /*
 871  * pci ids
 872  */
 873 static struct pci_device_id snd_m3_ids[] = {
 874         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 875          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 876         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 877          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 878         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 879          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 880         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 881          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 882         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 883          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 884         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 885          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 886         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 887          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 888         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 889          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 890         {0,},
 891 };
 892
 893 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 894
 895 static const struct m3_quirk m3_quirk_list[] = {
 896         /* panasonic CF-28 "toughbook" */
 897         {
 898                 .name = "Panasonic CF-28",
 899                 .vendor = 0x10f7,
 900                 .device = 0x833e,
 901                 .amp_gpio = 0x0d,
 902         },
 903         /* panasonic CF-72 "toughbook" */
 904         {
 905                 .name = "Panasonic CF-72",
 906                 .vendor = 0x10f7,
 907                 .device = 0x833d,
 908                 .amp_gpio = 0x0d,
 909         },
 910         /* Dell Inspiron 4000 */
 911         {
 912                 .name = "Dell Inspiron 4000",
 913                 .vendor = 0x1028,
 914                 .device = 0x00b0,
 915                 .amp_gpio = -1,
 916                 .irda_workaround = 1,
 917         },
 918         /* Dell Inspiron 8000 */
 919         {
 920                 .name = "Dell Inspiron 8000",
 921                 .vendor = 0x1028,
 922                 .device = 0x00a4,
 923                 .amp_gpio = -1,
 924                 .irda_workaround = 1,
 925         },
 926         /* Dell Inspiron 8100 */
 927         {
 928                 .name = "Dell Inspiron 8100",
 929                 .vendor = 0x1028,
 930                 .device = 0x00e6,
 931                 .amp_gpio = -1,
 932                 .irda_workaround = 1,
 933         },
 934         /* NEC LM800J/7 */
 935         {
 936                 .name = "NEC LM800J/7",
 937                 .vendor = 0x1033,
 938                 .device = 0x80f1,
 939                 .amp_gpio = 0x03,
 940         },
 941         /* LEGEND ZhaoYang 3100CF */
 942         {
 943                 .name = "LEGEND ZhaoYang 3100CF",
 944                 .vendor = 0x1509,
 945                 .device = 0x1740,
 946                 .amp_gpio = 0x03,
 947         },
 948         /* END */
 949         { NULL }
 950 };
 951
 952 /* These values came from the Windows driver. */
 953 static const struct m3_hv_quirk m3_hv_quirk_list[] = {
 954         /* Allegro chips */
 955         { 0x125D, 0x1988, 0x0E11, 0x002E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 956         { 0x125D, 0x1988, 0x0E11, 0x0094, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 957         { 0x125D, 0x1988, 0x0E11, 0xB112, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 958         { 0x125D, 0x1988, 0x0E11, 0xB114, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 959         { 0x125D, 0x1988, 0x103C, 0x0012, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 960         { 0x125D, 0x1988, 0x103C, 0x0018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 961         { 0x125D, 0x1988, 0x103C, 0x001C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 962         { 0x125D, 0x1988, 0x103C, 0x001D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 963         { 0x125D, 0x1988, 0x103C, 0x001E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 964         { 0x125D, 0x1988, 0x107B, 0x3350, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 965         { 0x125D, 0x1988, 0x10F7, 0x8338, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 966         { 0x125D, 0x1988, 0x10F7, 0x833C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 967         { 0x125D, 0x1988, 0x10F7, 0x833D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 968         { 0x125D, 0x1988, 0x10F7, 0x833E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 969         { 0x125D, 0x1988, 0x10F7, 0x833F, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 970         { 0x125D, 0x1988, 0x13BD, 0x1018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 971         { 0x125D, 0x1988, 0x13BD, 0x1019, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 972         { 0x125D, 0x1988, 0x13BD, 0x101A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 973         { 0x125D, 0x1988, 0x14FF, 0x0F03, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 974         { 0x125D, 0x1988, 0x14FF, 0x0F04, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 975         { 0x125D, 0x1988, 0x14FF, 0x0F05, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 976         { 0x125D, 0x1988, 0x156D, 0xB400, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 977         { 0x125D, 0x1988, 0x156D, 0xB795, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 978         { 0x125D, 0x1988, 0x156D, 0xB797, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 979         { 0x125D, 0x1988, 0x156D, 0xC700, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 },
 980         { 0x125D, 0x1988, 0x1033, 0x80F1, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 981         { 0x125D, 0x1988, 0x103C, 0x001A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, /* HP OmniBook 6100 */
 982         { 0x125D, 0x1988, 0x107B, 0x340A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 983         { 0x125D, 0x1988, 0x107B, 0x3450, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 984         { 0x125D, 0x1988, 0x109F, 0x3134, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 985         { 0x125D, 0x1988, 0x109F, 0x3161, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 986         { 0x125D, 0x1988, 0x144D, 0x3280, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 987         { 0x125D, 0x1988, 0x144D, 0x3281, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 988         { 0x125D, 0x1988, 0x144D, 0xC002, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 989         { 0x125D, 0x1988, 0x144D, 0xC003, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 990         { 0x125D, 0x1988, 0x1509, 0x1740, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 991         { 0x125D, 0x1988, 0x1610, 0x0010, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 },
 992         { 0x125D, 0x1988, 0x1042, 0x1042, HV_CTRL_ENABLE, 0 },
 993         { 0x125D, 0x1988, 0x107B, 0x9500, HV_CTRL_ENABLE, 0 },
 994         { 0x125D, 0x1988, 0x14FF, 0x0F06, HV_CTRL_ENABLE, 0 },
 995         { 0x125D, 0x1988, 0x1558, 0x8586, HV_CTRL_ENABLE, 0 },
 996         { 0x125D, 0x1988, 0x161F, 0x2011, HV_CTRL_ENABLE, 0 },
 997         /* Maestro3 chips */
 998         { 0x125D, 0x1998, 0x103C, 0x000E, HV_CTRL_ENABLE, 0 },
 999         { 0x125D, 0x1998, 0x103C, 0x0010, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 6000 */
1000         { 0x125D, 0x1998, 0x103C, 0x0011, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 500 */
1001         { 0x125D, 0x1998, 0x103C, 0x001B, HV_CTRL_ENABLE, 0 },
1002         { 0x125D, 0x1998, 0x104D, 0x80A6, HV_CTRL_ENABLE, 0 },
1003         { 0x125D, 0x1998, 0x104D, 0x80AA, HV_CTRL_ENABLE, 0 },
1004         { 0x125D, 0x1998, 0x107B, 0x5300, HV_CTRL_ENABLE, 0 },
1005         { 0x125D, 0x1998, 0x110A, 0x1998, HV_CTRL_ENABLE, 0 },
1006         { 0x125D, 0x1998, 0x13BD, 0x1015, HV_CTRL_ENABLE, 0 },
1007         { 0x125D, 0x1998, 0x13BD, 0x101C, HV_CTRL_ENABLE, 0 },
1008         { 0x125D, 0x1998, 0x13BD, 0x1802, HV_CTRL_ENABLE, 0 },
1009         { 0x125D, 0x1998, 0x1599, 0x0715, HV_CTRL_ENABLE, 0 },
1010         { 0x125D, 0x1998, 0x5643, 0x5643, HV_CTRL_ENABLE, 0 },
1011         { 0x125D, 0x199A, 0x144D, 0x3260, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1012         { 0x125D, 0x199A, 0x144D, 0x3261, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1013         { 0x125D, 0x199A, 0x144D, 0xC000, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1014         { 0x125D, 0x199A, 0x144D, 0xC001, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 },
1015         { 0 }
1016 };
1017
1018 /*
1019  * lowlevel functions
1020  */
1021
1022 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
1023 {
1024         outw(value, chip->iobase + reg);
1025 }
1026
1027 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
1028 {
1029         return inw(chip->iobase + reg);
1030 }
1031
1032 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1033 {
1034         outb(value, chip->iobase + reg);
1035 }
1036
1037 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1038 {
1039         return inb(chip->iobase + reg);
1040 }
1041
1042 /*
1043  * access 16bit words to the code or data regions of the dsp's memory.
1044  * index addresses 16bit words.
1045  */
1046 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1047 {
1048         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1049         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1050         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1051 }
1052
1053 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1054 {
1055         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1056         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1057         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1058 }
1059
1060 static void snd_m3_assp_halt(struct snd_m3 *chip)
1061 {
1062         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1063         msleep(10);
1064         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1065 }
1066
1067 static void snd_m3_assp_continue(struct snd_m3 *chip)
1068 {
1069         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1070 }
1071
1072
1073 /*
1074  * This makes me sad. the maestro3 has lists
1075  * internally that must be packed.. 0 terminates,
1076  * apparently, or maybe all unused entries have
1077  * to be 0, the lists have static lengths set
1078  * by the binary code images.
1079  */
1080
1081 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1082 {
1083         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1084                           list->mem_addr + list->curlen,
1085                           val);
1086         return list->curlen++;
1087 }
1088
1089 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1090 {
1091         u16  val;
1092         int lastindex = list->curlen - 1;
1093
1094         if (index != lastindex) {
1095                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1096                                        list->mem_addr + lastindex);
1097                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1098                                   list->mem_addr + index,
1099                                   val);
1100         }
1101
1102         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1103                           list->mem_addr + lastindex,
1104                           0);
1105
1106         list->curlen--;
1107 }
1108
1109 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1110 {
1111         chip->timer_users++;
1112         if (chip->timer_users != 1)
1113                 return;
1114
1115         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1116                           KDATA_TIMER_COUNT_RELOAD,
1117                           240);
1118
1119         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1120                           KDATA_TIMER_COUNT_CURRENT,
1121                           240);
1122
1123         snd_m3_outw(chip,
1124                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1125                     HOST_INT_CTRL);
1126 }
1127
1128 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1129 {
1130         chip->timer_users--;
1131         if (chip->timer_users > 0)
1132                 return;
1133
1134         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1135                           KDATA_TIMER_COUNT_RELOAD,
1136                           0);
1137
1138         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1139                           KDATA_TIMER_COUNT_CURRENT,
1140                           0);
1141
1142         snd_m3_outw(chip,
1143                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1144                     HOST_INT_CTRL);
1145 }
1146
1147 /*
1148  * start/stop
1149  */
1150
1151 /* spinlock held! */
1152 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1153                             struct snd_pcm_substream *subs)
1154 {
1155         if (! s || ! subs)
1156                 return -EINVAL;
1157
1158         snd_m3_inc_timer_users(chip);
1159         switch (subs->stream) {
1160         case SNDRV_PCM_STREAM_PLAYBACK:
1161                 chip->dacs_active++;
1162                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1163                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1164                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1165                                   KDATA_MIXER_TASK_NUMBER,
1166                                   chip->dacs_active);
1167                 break;
1168         case SNDRV_PCM_STREAM_CAPTURE:
1169                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1170                                   KDATA_ADC1_REQUEST, 1);
1171                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1172                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1173                 break;
1174         }
1175         return 0;
1176 }
1177
1178 /* spinlock held! */
1179 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1180                            struct snd_pcm_substream *subs)
1181 {
1182         if (! s || ! subs)
1183                 return -EINVAL;
1184
1185         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1186                           s->inst.data + CDATA_INSTANCE_READY, 0);
1187         snd_m3_dec_timer_users(chip);
1188         switch (subs->stream) {
1189         case SNDRV_PCM_STREAM_PLAYBACK:
1190                 chip->dacs_active--;
1191                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1192                                   KDATA_MIXER_TASK_NUMBER,
1193                                   chip->dacs_active);
1194                 break;
1195         case SNDRV_PCM_STREAM_CAPTURE:
1196                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1197                                   KDATA_ADC1_REQUEST, 0);
1198                 break;
1199         }
1200         return 0;
1201 }
1202
1203 static int
1204 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1205 {
1206         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1207         struct m3_dma *s = subs->runtime->private_data;
1208         int err = -EINVAL;
1209
1210         snd_assert(s != NULL, return -ENXIO);
1211
1212         spin_lock(&chip->reg_lock);
1213         switch (cmd) {
1214         case SNDRV_PCM_TRIGGER_START:
1215         case SNDRV_PCM_TRIGGER_RESUME:
1216                 if (s->running)
1217                         err = -EBUSY;
1218                 else {
1219                         s->running = 1;
1220                         err = snd_m3_pcm_start(chip, s, subs);
1221                 }
1222                 break;
1223         case SNDRV_PCM_TRIGGER_STOP:
1224         case SNDRV_PCM_TRIGGER_SUSPEND:
1225                 if (! s->running)
1226                         err = 0; /* should return error? */
1227                 else {
1228                         s->running = 0;
1229                         err = snd_m3_pcm_stop(chip, s, subs);
1230                 }
1231                 break;
1232         }
1233         spin_unlock(&chip->reg_lock);
1234         return err;
1235 }
1236
1237 /*
1238  * setup
1239  */
1240 static void
1241 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1242 {
1243         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1244         struct snd_pcm_runtime *runtime = subs->runtime;
1245
1246         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1247                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1248                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1249         } else {
1250                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1251                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1252         }
1253         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1254         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1255
1256         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1257         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1258         s->hwptr = 0;
1259         s->count = 0;
1260
1261 #define LO(x) ((x) & 0xffff)
1262 #define HI(x) LO((x) >> 16)
1263
1264         /* host dma buffer pointers */
1265         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1266                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1267                           LO(s->buffer_addr));
1268
1269         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1270                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1271                           HI(s->buffer_addr));
1272
1273         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1274                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1275                           LO(s->buffer_addr + s->dma_size));
1276
1277         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1278                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1279                           HI(s->buffer_addr + s->dma_size));
1280
1281         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1282                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1283                           LO(s->buffer_addr));
1284
1285         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1286                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1287                           HI(s->buffer_addr));
1288 #undef LO
1289 #undef HI
1290
1291         /* dsp buffers */
1292
1293         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1294                           s->inst.data + CDATA_IN_BUF_BEGIN,
1295                           dsp_in_buffer);
1296
1297         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1298                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1299                           dsp_in_buffer + (dsp_in_size / 2));
1300
1301         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1302                           s->inst.data + CDATA_IN_BUF_HEAD,
1303                           dsp_in_buffer);
1304
1305         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1306                           s->inst.data + CDATA_IN_BUF_TAIL,
1307                           dsp_in_buffer);
1308
1309         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1310                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1311                           dsp_out_buffer);
1312
1313         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1314                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1315                           dsp_out_buffer + (dsp_out_size / 2));
1316
1317         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1318                           s->inst.data + CDATA_OUT_BUF_HEAD,
1319                           dsp_out_buffer);
1320
1321         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1322                           s->inst.data + CDATA_OUT_BUF_TAIL,
1323                           dsp_out_buffer);
1324 }
1325
1326 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1327                               struct snd_pcm_runtime *runtime)
1328 {
1329         u32 freq;
1330
1331         /*
1332          * put us in the lists if we're not already there
1333          */
1334         if (! s->in_lists) {
1335                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1336                                               s->inst.data >> DP_SHIFT_COUNT);
1337                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1338                                               s->inst.data >> DP_SHIFT_COUNT);
1339                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1340                                               s->inst.data >> DP_SHIFT_COUNT);
1341                 s->in_lists = 1;
1342         }
1343
1344         /* write to 'mono' word */
1345         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1346                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1347                           runtime->channels == 2 ? 0 : 1);
1348         /* write to '8bit' word */
1349         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1350                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1351                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1352
1353         /* set up dac/adc rate */
1354         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1355         if (freq)
1356                 freq--;
1357
1358         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1359                           s->inst.data + CDATA_FREQUENCY,
1360                           freq);
1361 }
1362
1363
1364 static const struct play_vals {
1365         u16 addr, val;
1366 } pv[] = {
1367         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1368         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1369         {SRC3_DIRECTION_OFFSET, 0} ,
1370         /* +1, +2 are stereo/16 bit */
1371         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1372         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1373         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1374         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1375         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1376         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1377         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1378         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1379         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1380         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1381         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1382         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1383         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1384         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1385         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1386         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1387         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1388 };
1389
1390
1391 /* the mode passed should be already shifted and masked */
1392 static void
1393 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1394                       struct snd_pcm_substream *subs)
1395 {
1396         unsigned int i;
1397
1398         /*
1399          * some per client initializers
1400          */
1401
1402         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1403                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1404                           s->inst.data + 40 + 8);
1405
1406         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1407                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1408                           s->inst.code + MINISRC_COEF_LOC);
1409
1410         /* enable or disable low pass filter? */
1411         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1412                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1413                           subs->runtime->rate > 45000 ? 0xff : 0);
1414
1415         /* tell it which way dma is going? */
1416         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1417                           s->inst.data + CDATA_DMA_CONTROL,
1418                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1419
1420         /*
1421          * set an armload of static initializers
1422          */
1423         for (i = 0; i < ARRAY_SIZE(pv); i++)
1424                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1425                                   s->inst.data + pv[i].addr, pv[i].val);
1426 }
1427
1428 /*
1429  *    Native record driver
1430  */
1431 static const struct rec_vals {
1432         u16 addr, val;
1433 } rv[] = {
1434         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1435         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1436         {SRC3_DIRECTION_OFFSET, 1} ,
1437         /* +1, +2 are stereo/16 bit */
1438         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1439         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1440         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1441         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1442         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1443         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1444         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1445         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1446         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1447         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1448         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1449         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1450         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1451         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1452         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1453         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1454         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1455         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1456         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1457 };
1458
1459 static void
1460 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1461 {
1462         unsigned int i;
1463
1464         /*
1465          * some per client initializers
1466          */
1467
1468         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1469                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1470                           s->inst.data + 40 + 8);
1471
1472         /* tell it which way dma is going? */
1473         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1474                           s->inst.data + CDATA_DMA_CONTROL,
1475                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1476                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1477
1478         /*
1479          * set an armload of static initializers
1480          */
1481         for (i = 0; i < ARRAY_SIZE(rv); i++)
1482                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1483                                   s->inst.data + rv[i].addr, rv[i].val);
1484 }
1485
1486 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1487                                 struct snd_pcm_hw_params *hw_params)
1488 {
1489         struct m3_dma *s = substream->runtime->private_data;
1490         int err;
1491
1492         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1493                 return err;
1494         /* set buffer address */
1495         s->buffer_addr = substream->runtime->dma_addr;
1496         if (s->buffer_addr & 0x3) {
1497                 snd_printk(KERN_ERR "oh my, not aligned\n");
1498                 s->buffer_addr = s->buffer_addr & ~0x3;
1499         }
1500         return 0;
1501 }
1502
1503 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1504 {
1505         struct m3_dma *s;
1506
1507         if (substream->runtime->private_data == NULL)
1508                 return 0;
1509         s = substream->runtime->private_data;
1510         snd_pcm_lib_free_pages(substream);
1511         s->buffer_addr = 0;
1512         return 0;
1513 }
1514
1515 static int
1516 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1517 {
1518         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1519         struct snd_pcm_runtime *runtime = subs->runtime;
1520         struct m3_dma *s = runtime->private_data;
1521
1522         snd_assert(s != NULL, return -ENXIO);
1523
1524         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1525             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1526                 return -EINVAL;
1527         if (runtime->rate > 48000 ||
1528             runtime->rate < 8000)
1529                 return -EINVAL;
1530
1531         spin_lock_irq(&chip->reg_lock);
1532
1533         snd_m3_pcm_setup1(chip, s, subs);
1534
1535         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1536                 snd_m3_playback_setup(chip, s, subs);
1537         else
1538                 snd_m3_capture_setup(chip, s, subs);
1539
1540         snd_m3_pcm_setup2(chip, s, runtime);
1541
1542         spin_unlock_irq(&chip->reg_lock);
1543
1544         return 0;
1545 }
1546
1547 /*
1548  * get current pointer
1549  */
1550 static unsigned int
1551 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1552 {
1553         u16 hi = 0, lo = 0;
1554         int retry = 10;
1555         u32 addr;
1556
1557         /*
1558          * try and get a valid answer
1559          */
1560         while (retry--) {
1561                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1562                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1563
1564                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1565                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1566
1567                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1568                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1569                         break;
1570         }
1571         addr = lo | ((u32)hi<<16);
1572         return (unsigned int)(addr - s->buffer_addr);
1573 }
1574
1575 static snd_pcm_uframes_t
1576 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1577 {
1578         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1579         unsigned int ptr;
1580         struct m3_dma *s = subs->runtime->private_data;
1581         snd_assert(s != NULL, return 0);
1582
1583         spin_lock(&chip->reg_lock);
1584         ptr = snd_m3_get_pointer(chip, s, subs);
1585         spin_unlock(&chip->reg_lock);
1586         return bytes_to_frames(subs->runtime, ptr);
1587 }
1588
1589
1590 /* update pointer */
1591 /* spinlock held! */
1592 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1593 {
1594         struct snd_pcm_substream *subs = s->substream;
1595         unsigned int hwptr;
1596         int diff;
1597
1598         if (! s->running)
1599                 return;
1600
1601         hwptr = snd_m3_get_pointer(chip, s, subs);
1602
1603         /* try to avoid expensive modulo divisions */
1604         if (hwptr >= s->dma_size)
1605                 hwptr %= s->dma_size;
1606
1607         diff = s->dma_size + hwptr - s->hwptr;
1608         if (diff >= s->dma_size)
1609                 diff %= s->dma_size;
1610
1611         s->hwptr = hwptr;
1612         s->count += diff;
1613
1614         if (s->count >= (signed)s->period_size) {
1615
1616                 if (s->count < 2 * (signed)s->period_size)
1617                         s->count -= (signed)s->period_size;
1618                 else
1619                         s->count %= s->period_size;
1620
1621                 spin_unlock(&chip->reg_lock);
1622                 snd_pcm_period_elapsed(subs);
1623                 spin_lock(&chip->reg_lock);
1624         }
1625 }
1626
1627 static void snd_m3_update_hw_volume(unsigned long private_data)
1628 {
1629         struct snd_m3 *chip = (struct snd_m3 *) private_data;
1630         int x, val;
1631         unsigned long flags;
1632
1633         /* Figure out which volume control button was pushed,
1634            based on differences from the default register
1635            values. */
1636         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1637
1638         /* Reset the volume control registers. */
1639         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1640         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1641         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1642         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1643
1644         if (!chip->master_switch || !chip->master_volume)
1645                 return;
1646
1647         /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1648         spin_lock_irqsave(&chip->ac97_lock, flags);
1649
1650         val = chip->ac97->regs[AC97_MASTER_VOL];
1651         switch (x) {
1652         case 0x88:
1653                 /* mute */
1654                 val ^= 0x8000;
1655                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1656                 outw(val, chip->iobase + CODEC_DATA);
1657                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1658                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1659                                &chip->master_switch->id);
1660                 break;
1661         case 0xaa:
1662                 /* volume up */
1663                 if ((val & 0x7f) > 0)
1664                         val--;
1665                 if ((val & 0x7f00) > 0)
1666                         val -= 0x0100;
1667                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1668                 outw(val, chip->iobase + CODEC_DATA);
1669                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1670                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1671                                &chip->master_volume->id);
1672                 break;
1673         case 0x66:
1674                 /* volume down */
1675                 if ((val & 0x7f) < 0x1f)
1676                         val++;
1677                 if ((val & 0x7f00) < 0x1f00)
1678                         val += 0x0100;
1679                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1680                 outw(val, chip->iobase + CODEC_DATA);
1681                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1682                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1683                                &chip->master_volume->id);
1684                 break;
1685         }
1686         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1687 }
1688
1689 static irqreturn_t
1690 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1691 {
1692         struct snd_m3 *chip = dev_id;
1693         u8 status;
1694         int i;
1695
1696         status = inb(chip->iobase + HOST_INT_STATUS);
1697
1698         if (status == 0xff)
1699                 return IRQ_NONE;
1700
1701         if (status & HV_INT_PENDING)
1702                 tasklet_hi_schedule(&chip->hwvol_tq);
1703
1704         /*
1705          * ack an assp int if its running
1706          * and has an int pending
1707          */
1708         if (status & ASSP_INT_PENDING) {
1709                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1710                 if (!(ctl & STOP_ASSP_CLOCK)) {
1711                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1712                         if (ctl & DSP2HOST_REQ_TIMER) {
1713                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1714                                 /* update adc/dac info if it was a timer int */
1715                                 spin_lock(&chip->reg_lock);
1716                                 for (i = 0; i < chip->num_substreams; i++) {
1717                                         struct m3_dma *s = &chip->substreams[i];
1718                                         if (s->running)
1719                                                 snd_m3_update_ptr(chip, s);
1720                                 }
1721                                 spin_unlock(&chip->reg_lock);
1722                         }
1723                 }
1724         }
1725
1726 #if 0 /* TODO: not supported yet */
1727         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1728                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1729 #endif
1730
1731         /* ack ints */
1732         outb(status, chip->iobase + HOST_INT_STATUS);
1733
1734         return IRQ_HANDLED;
1735 }
1736
1737
1738 /*
1739  */
1740
1741 static struct snd_pcm_hardware snd_m3_playback =
1742 {
1743         .info =                 (SNDRV_PCM_INFO_MMAP |
1744                                  SNDRV_PCM_INFO_INTERLEAVED |
1745                                  SNDRV_PCM_INFO_MMAP_VALID |
1746                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1747                                  /*SNDRV_PCM_INFO_PAUSE |*/
1748                                  SNDRV_PCM_INFO_RESUME),
1749         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1750         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1751         .rate_min =             8000,
1752         .rate_max =             48000,
1753         .channels_min =         1,
1754         .channels_max =         2,
1755         .buffer_bytes_max =     (512*1024),
1756         .period_bytes_min =     64,
1757         .period_bytes_max =     (512*1024),
1758         .periods_min =          1,
1759         .periods_max =          1024,
1760 };
1761
1762 static struct snd_pcm_hardware snd_m3_capture =
1763 {
1764         .info =                 (SNDRV_PCM_INFO_MMAP |
1765                                  SNDRV_PCM_INFO_INTERLEAVED |
1766                                  SNDRV_PCM_INFO_MMAP_VALID |
1767                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1768                                  /*SNDRV_PCM_INFO_PAUSE |*/
1769                                  SNDRV_PCM_INFO_RESUME),
1770         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1771         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1772         .rate_min =             8000,
1773         .rate_max =             48000,
1774         .channels_min =         1,
1775         .channels_max =         2,
1776         .buffer_bytes_max =     (512*1024),
1777         .period_bytes_min =     64,
1778         .period_bytes_max =     (512*1024),
1779         .periods_min =          1,
1780         .periods_max =          1024,
1781 };
1782
1783
1784 /*
1785  */
1786
1787 static int
1788 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1789 {
1790         int i;
1791         struct m3_dma *s;
1792
1793         spin_lock_irq(&chip->reg_lock);
1794         for (i = 0; i < chip->num_substreams; i++) {
1795                 s = &chip->substreams[i];
1796                 if (! s->opened)
1797                         goto __found;
1798         }
1799         spin_unlock_irq(&chip->reg_lock);
1800         return -ENOMEM;
1801 __found:
1802         s->opened = 1;
1803         s->running = 0;
1804         spin_unlock_irq(&chip->reg_lock);
1805
1806         subs->runtime->private_data = s;
1807         s->substream = subs;
1808
1809         /* set list owners */
1810         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1811                 s->index_list[0] = &chip->mixer_list;
1812         } else
1813                 s->index_list[0] = &chip->adc1_list;
1814         s->index_list[1] = &chip->msrc_list;
1815         s->index_list[2] = &chip->dma_list;
1816
1817         return 0;
1818 }
1819
1820 static void
1821 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1822 {
1823         struct m3_dma *s = subs->runtime->private_data;
1824
1825         if (s == NULL)
1826                 return; /* not opened properly */
1827
1828         spin_lock_irq(&chip->reg_lock);
1829         if (s->substream && s->running)
1830                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1831         if (s->in_lists) {
1832                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1833                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1834                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1835                 s->in_lists = 0;
1836         }
1837         s->running = 0;
1838         s->opened = 0;
1839         spin_unlock_irq(&chip->reg_lock);
1840 }
1841
1842 static int
1843 snd_m3_playback_open(struct snd_pcm_substream *subs)
1844 {
1845         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1846         struct snd_pcm_runtime *runtime = subs->runtime;
1847         int err;
1848
1849         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1850                 return err;
1851
1852         runtime->hw = snd_m3_playback;
1853         snd_pcm_set_sync(subs);
1854
1855         return 0;
1856 }
1857
1858 static int
1859 snd_m3_playback_close(struct snd_pcm_substream *subs)
1860 {
1861         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1862
1863         snd_m3_substream_close(chip, subs);
1864         return 0;
1865 }
1866
1867 static int
1868 snd_m3_capture_open(struct snd_pcm_substream *subs)
1869 {
1870         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1871         struct snd_pcm_runtime *runtime = subs->runtime;
1872         int err;
1873
1874         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1875                 return err;
1876
1877         runtime->hw = snd_m3_capture;
1878         snd_pcm_set_sync(subs);
1879
1880         return 0;
1881 }
1882
1883 static int
1884 snd_m3_capture_close(struct snd_pcm_substream *subs)
1885 {
1886         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1887
1888         snd_m3_substream_close(chip, subs);
1889         return 0;
1890 }
1891
1892 /*
1893  * create pcm instance
1894  */
1895
1896 static struct snd_pcm_ops snd_m3_playback_ops = {
1897         .open =         snd_m3_playback_open,
1898         .close =        snd_m3_playback_close,
1899         .ioctl =        snd_pcm_lib_ioctl,
1900         .hw_params =    snd_m3_pcm_hw_params,
1901         .hw_free =      snd_m3_pcm_hw_free,
1902         .prepare =      snd_m3_pcm_prepare,
1903         .trigger =      snd_m3_pcm_trigger,
1904         .pointer =      snd_m3_pcm_pointer,
1905 };
1906
1907 static struct snd_pcm_ops snd_m3_capture_ops = {
1908         .open =         snd_m3_capture_open,
1909         .close =        snd_m3_capture_close,
1910         .ioctl =        snd_pcm_lib_ioctl,
1911         .hw_params =    snd_m3_pcm_hw_params,
1912         .hw_free =      snd_m3_pcm_hw_free,
1913         .prepare =      snd_m3_pcm_prepare,
1914         .trigger =      snd_m3_pcm_trigger,
1915         .pointer =      snd_m3_pcm_pointer,
1916 };
1917
1918 static int __devinit
1919 snd_m3_pcm(struct snd_m3 * chip, int device)
1920 {
1921         struct snd_pcm *pcm;
1922         int err;
1923
1924         err = snd_pcm_new(chip->card, chip->card->driver, device,
1925                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1926         if (err < 0)
1927                 return err;
1928
1929         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1930         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1931
1932         pcm->private_data = chip;
1933         pcm->info_flags = 0;
1934         strcpy(pcm->name, chip->card->driver);
1935         chip->pcm = pcm;
1936
1937         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1938                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1939
1940         return 0;
1941 }
1942
1943
1944 /*
1945  * ac97 interface
1946  */
1947
1948 /*
1949  * Wait for the ac97 serial bus to be free.
1950  * return nonzero if the bus is still busy.
1951  */
1952 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1953 {
1954         int i = 10000;
1955
1956         do {
1957                 if (! (snd_m3_inb(chip, 0x30) & 1))
1958                         return 0;
1959                 cpu_relax();
1960         } while (i-- > 0);
1961
1962         snd_printk(KERN_ERR "ac97 serial bus busy\n");
1963         return 1;
1964 }
1965
1966 static unsigned short
1967 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1968 {
1969         struct snd_m3 *chip = ac97->private_data;
1970         unsigned long flags;
1971         unsigned short data = 0xffff;
1972
1973         if (snd_m3_ac97_wait(chip))
1974                 goto fail;
1975         spin_lock_irqsave(&chip->ac97_lock, flags);
1976         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1977         if (snd_m3_ac97_wait(chip))
1978                 goto fail_unlock;
1979         data = snd_m3_inw(chip, CODEC_DATA);
1980 fail_unlock:
1981         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1982 fail:
1983         return data;
1984 }
1985
1986 static void
1987 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1988 {
1989         struct snd_m3 *chip = ac97->private_data;
1990         unsigned long flags;
1991
1992         if (snd_m3_ac97_wait(chip))
1993                 return;
1994         spin_lock_irqsave(&chip->ac97_lock, flags);
1995         snd_m3_outw(chip, val, CODEC_DATA);
1996         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1997         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1998 }
1999
2000
2001 static void snd_m3_remote_codec_config(int io, int isremote)
2002 {
2003         isremote = isremote ? 1 : 0;
2004
2005         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2006              io + RING_BUS_CTRL_B);
2007         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2008              io + SDO_OUT_DEST_CTRL);
2009         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2010              io + SDO_IN_DEST_CTRL);
2011 }
2012
2013 /*
2014  * hack, returns non zero on err
2015  */
2016 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
2017 {
2018         u16 ret;
2019
2020         if (snd_m3_ac97_wait(chip))
2021                 return 1;
2022
2023         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2024
2025         if (snd_m3_ac97_wait(chip))
2026                 return 1;
2027
2028         ret = snd_m3_inw(chip, 0x32);
2029
2030         return (ret == 0) || (ret == 0xffff);
2031 }
2032
2033 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2034 {
2035         u16 dir;
2036         int delay1 = 0, delay2 = 0, i;
2037         int io = chip->iobase;
2038
2039         if (chip->allegro_flag) {
2040                 /*
2041                  * the onboard codec on the allegro seems
2042                  * to want to wait a very long time before
2043                  * coming back to life
2044                  */
2045                 delay1 = 50;
2046                 delay2 = 800;
2047         } else {
2048                 /* maestro3 */
2049                 delay1 = 20;
2050                 delay2 = 500;
2051         }
2052
2053         for (i = 0; i < 5; i++) {
2054                 dir = inw(io + GPIO_DIRECTION);
2055                 if (! chip->quirk || ! chip->quirk->irda_workaround)
2056                         dir |= 0x10; /* assuming pci bus master? */
2057
2058                 snd_m3_remote_codec_config(io, 0);
2059
2060                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2061                 udelay(20);
2062
2063                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2064                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2065                 outw(0, io + GPIO_DATA);
2066                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2067
2068                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2069
2070                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2071                 udelay(5);
2072                 /* ok, bring back the ac-link */
2073                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2074                 outw(~0, io + GPIO_MASK);
2075
2076                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2077
2078                 if (! snd_m3_try_read_vendor(chip))
2079                         break;
2080
2081                 delay1 += 10;
2082                 delay2 += 100;
2083
2084                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2085                            delay1, delay2);
2086         }
2087
2088 #if 0
2089         /* more gung-ho reset that doesn't
2090          * seem to work anywhere :)
2091          */
2092         tmp = inw(io + RING_BUS_CTRL_A);
2093         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2094         msleep(20);
2095         outw(tmp, io + RING_BUS_CTRL_A);
2096         msleep(50);
2097 #endif
2098 }
2099
2100 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2101 {
2102         struct snd_ac97_bus *pbus;
2103         struct snd_ac97_template ac97;
2104         struct snd_ctl_elem_id id;
2105         int err;
2106         static struct snd_ac97_bus_ops ops = {
2107                 .write = snd_m3_ac97_write,
2108                 .read = snd_m3_ac97_read,
2109         };
2110
2111         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2112                 return err;
2113
2114         memset(&ac97, 0, sizeof(ac97));
2115         ac97.private_data = chip;
2116         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2117                 return err;
2118
2119         /* seems ac97 PCM needs initialization.. hack hack.. */
2120         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2121         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2122         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2123
2124         memset(&id, 0, sizeof(id));
2125         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2126         strcpy(id.name, "Master Playback Switch");
2127         chip->master_switch = snd_ctl_find_id(chip->card, &id);
2128         memset(&id, 0, sizeof(id));
2129         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2130         strcpy(id.name, "Master Playback Volume");
2131         chip->master_volume = snd_ctl_find_id(chip->card, &id);
2132
2133         return 0;
2134 }
2135
2136
2137 /*
2138  * DSP Code images
2139  */
2140
2141 static const u16 assp_kernel_image[] __devinitdata = {
2142     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2143     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2144     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2145     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2146     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2147     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2148     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2149     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2150     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2151     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2152     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2153     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2154     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2155     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2156     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2157     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2158     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2159     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2160     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2161     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2162     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2163     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2164     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2165     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2166     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2167     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2168     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2169     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2170     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2171     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2172     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2173     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2174     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2175     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2176     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2177     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2178     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2179     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2180     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2181     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2182     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2183     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2184     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2185     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2186     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2187     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2188     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2189     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2190     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2191     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2192     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2193     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2194     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2195     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2196     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2197     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2198     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2199     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2200     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2201     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2202     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2203     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2204     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2205     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2206     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2207     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2208     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2209     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2210     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2211     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2212     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2213     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2214     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2215     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2216     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2217     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2218     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2219     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2220     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2221     0xBE3A,
2222 };
2223
2224 /*
2225  * Mini sample rate converter code image
2226  * that is to be loaded at 0x400 on the DSP.
2227  */
2228 static const u16 assp_minisrc_image[] __devinitdata = {
2229
2230     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2231     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2232     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2233     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2234     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2235     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2236     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2237     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2238     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2239     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2240     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2241     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2242     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2243     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2244     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2245     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2246     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2247     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2248     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2249     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2250     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2251     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2252     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2253     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2254     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2255     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2256     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2257     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2258     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2259     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2260     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2261     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2262     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2263 };
2264
2265
2266 /*
2267  * initialize ASSP
2268  */
2269
2270 #define MINISRC_LPF_LEN 10
2271 static const u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = {
2272         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2273         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2274 };
2275
2276 static void __devinit snd_m3_assp_init(struct snd_m3 *chip)
2277 {
2278         unsigned int i;
2279
2280         /* zero kernel data */
2281         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2282                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2283                                   KDATA_BASE_ADDR + i, 0);
2284
2285         /* zero mixer data? */
2286         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2287                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2288                                   KDATA_BASE_ADDR2 + i, 0);
2289
2290         /* init dma pointer */
2291         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2292                           KDATA_CURRENT_DMA,
2293                           KDATA_DMA_XFER0);
2294
2295         /* write kernel into code memory.. */
2296         for (i = 0 ; i < ARRAY_SIZE(assp_kernel_image); i++) {
2297                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2298                                   REV_B_CODE_MEMORY_BEGIN + i,
2299                                   assp_kernel_image[i]);
2300         }
2301
2302         /*
2303          * We only have this one client and we know that 0x400
2304          * is free in our kernel's mem map, so lets just
2305          * drop it there.  It seems that the minisrc doesn't
2306          * need vectors, so we won't bother with them..
2307          */
2308         for (i = 0; i < ARRAY_SIZE(assp_minisrc_image); i++) {
2309                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2310                                   0x400 + i,
2311                                   assp_minisrc_image[i]);
2312         }
2313
2314         /*
2315          * write the coefficients for the low pass filter?
2316          */
2317         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2318                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2319                                   0x400 + MINISRC_COEF_LOC + i,
2320                                   minisrc_lpf[i]);
2321         }
2322
2323         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2324                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2325                           0x8000);
2326
2327         /*
2328          * the minisrc is the only thing on
2329          * our task list..
2330          */
2331         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2332                           KDATA_TASK0,
2333                           0x400);
2334
2335         /*
2336          * init the mixer number..
2337          */
2338
2339         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2340                           KDATA_MIXER_TASK_NUMBER,0);
2341
2342         /*
2343          * EXTREME KERNEL MASTER VOLUME
2344          */
2345         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2346                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2347         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2348                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2349
2350         chip->mixer_list.curlen = 0;
2351         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2352         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2353         chip->adc1_list.curlen = 0;
2354         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2355         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2356         chip->dma_list.curlen = 0;
2357         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2358         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2359         chip->msrc_list.curlen = 0;
2360         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2361         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2362 }
2363
2364
2365 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2366 {
2367         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2368                                MINISRC_IN_BUFFER_SIZE / 2 +
2369                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2370         int address, i;
2371
2372         /*
2373          * the revb memory map has 0x1100 through 0x1c00
2374          * free.
2375          */
2376
2377         /*
2378          * align instance address to 256 bytes so that its
2379          * shifted list address is aligned.
2380          * list address = (mem address >> 1) >> 7;
2381          */
2382         data_bytes = (data_bytes + 255) & ~255;
2383         address = 0x1100 + ((data_bytes/2) * index);
2384
2385         if ((address + (data_bytes/2)) >= 0x1c00) {
2386                 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2387                            data_bytes, index, address);
2388                 return -ENOMEM;
2389         }
2390
2391         s->number = index;
2392         s->inst.code = 0x400;
2393         s->inst.data = address;
2394
2395         for (i = data_bytes / 2; i > 0; address++, i--) {
2396                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2397                                   address, 0);
2398         }
2399
2400         return 0;
2401 }
2402
2403
2404 /*
2405  * this works for the reference board, have to find
2406  * out about others
2407  *
2408  * this needs more magic for 4 speaker, but..
2409  */
2410 static void
2411 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2412 {
2413         int io = chip->iobase;
2414         u16 gpo, polarity;
2415
2416         if (! chip->external_amp)
2417                 return;
2418
2419         polarity = enable ? 0 : 1;
2420         polarity = polarity << chip->amp_gpio;
2421         gpo = 1 << chip->amp_gpio;
2422
2423         outw(~gpo, io + GPIO_MASK);
2424
2425         outw(inw(io + GPIO_DIRECTION) | gpo,
2426              io + GPIO_DIRECTION);
2427
2428         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2429              io + GPIO_DATA);
2430
2431         outw(0xffff, io + GPIO_MASK);
2432 }
2433
2434 static int
2435 snd_m3_chip_init(struct snd_m3 *chip)
2436 {
2437         struct pci_dev *pcidev = chip->pci;
2438         unsigned long io = chip->iobase;
2439         u32 n;
2440         u16 w;
2441         u8 t; /* makes as much sense as 'n', no? */
2442
2443         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2444         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2445                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2446                DISABLE_LEGACY);
2447         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2448
2449         if (chip->hv_quirk && chip->hv_quirk->is_omnibook) {
2450                 /*
2451                  * Volume buttons on some HP OmniBook laptops don't work
2452                  * correctly. This makes them work for the most part.
2453                  *
2454                  * Volume up and down buttons on the laptop side work.
2455                  * Fn+cursor_up (volme up) works.
2456                  * Fn+cursor_down (volume down) doesn't work.
2457                  * Fn+F7 (mute) works acts as volume up.
2458                  */
2459                 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK);
2460                 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION);
2461                 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA);
2462                 outw(0xffff, io + GPIO_MASK);
2463         }
2464         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2465         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2466         if (chip->hv_quirk)
2467                 n |= chip->hv_quirk->config;
2468         /* For some reason we must always use reduced debounce. */
2469         n |= REDUCED_DEBOUNCE;
2470         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2471         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2472
2473         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2474         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2475         n &= ~INT_CLK_SELECT;
2476         if (!chip->allegro_flag) {
2477                 n &= ~INT_CLK_MULT_ENABLE;
2478                 n |= INT_CLK_SRC_NOT_PCI;
2479         }
2480         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2481         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2482
2483         if (chip->allegro_flag) {
2484                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2485                 n |= IN_CLK_12MHZ_SELECT;
2486                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2487         }
2488
2489         t = inb(chip->iobase + ASSP_CONTROL_A);
2490         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2491         t |= ASSP_CLK_49MHZ_SELECT;
2492         t |= ASSP_0_WS_ENABLE;
2493         outb(t, chip->iobase + ASSP_CONTROL_A);
2494
2495         snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2496         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2497
2498         outb(0x00, io + HARDWARE_VOL_CTRL);
2499         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2500         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2501         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2502         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2503
2504         return 0;
2505 }
2506
2507 static void
2508 snd_m3_enable_ints(struct snd_m3 *chip)
2509 {
2510         unsigned long io = chip->iobase;
2511         unsigned short val;
2512
2513         /* TODO: MPU401 not supported yet */
2514         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2515         if (chip->hv_quirk && (chip->hv_quirk->config & HV_CTRL_ENABLE))
2516                 val |= HV_INT_ENABLE;
2517         outw(val, io + HOST_INT_CTRL);
2518         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2519              io + ASSP_CONTROL_C);
2520 }
2521
2522
2523 /*
2524  */
2525
2526 static int snd_m3_free(struct snd_m3 *chip)
2527 {
2528         struct m3_dma *s;
2529         int i;
2530
2531         if (chip->substreams) {
2532                 spin_lock_irq(&chip->reg_lock);
2533                 for (i = 0; i < chip->num_substreams; i++) {
2534                         s = &chip->substreams[i];
2535                         /* check surviving pcms; this should not happen though.. */
2536                         if (s->substream && s->running)
2537                                 snd_m3_pcm_stop(chip, s, s->substream);
2538                 }
2539                 spin_unlock_irq(&chip->reg_lock);
2540                 kfree(chip->substreams);
2541         }
2542         if (chip->iobase) {
2543                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2544         }
2545
2546 #ifdef CONFIG_PM
2547         vfree(chip->suspend_mem);
2548 #endif
2549
2550         if (chip->irq >= 0) {
2551                 synchronize_irq(chip->irq);
2552                 free_irq(chip->irq, chip);
2553         }
2554
2555         if (chip->iobase)
2556                 pci_release_regions(chip->pci);
2557
2558         pci_disable_device(chip->pci);
2559         kfree(chip);
2560         return 0;
2561 }
2562
2563
2564 /*
2565  * APM support
2566  */
2567 #ifdef CONFIG_PM
2568 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2569 {
2570         struct snd_card *card = pci_get_drvdata(pci);
2571         struct snd_m3 *chip = card->private_data;
2572         int i, index;
2573
2574         if (chip->suspend_mem == NULL)
2575                 return 0;
2576
2577         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2578         snd_pcm_suspend_all(chip->pcm);
2579         snd_ac97_suspend(chip->ac97);
2580
2581         msleep(10); /* give the assp a chance to idle.. */
2582
2583         snd_m3_assp_halt(chip);
2584
2585         /* save dsp image */
2586         index = 0;
2587         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2588                 chip->suspend_mem[index++] =
2589                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2590         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2591                 chip->suspend_mem[index++] =
2592                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2593
2594         /* power down apci registers */
2595         snd_m3_outw(chip, 0xffff, 0x54);
2596         snd_m3_outw(chip, 0xffff, 0x56);
2597
2598         pci_disable_device(pci);
2599         pci_save_state(pci);
2600         return 0;
2601 }
2602
2603 static int m3_resume(struct pci_dev *pci)
2604 {
2605         struct snd_card *card = pci_get_drvdata(pci);
2606         struct snd_m3 *chip = card->private_data;
2607         int i, index;
2608
2609         if (chip->suspend_mem == NULL)
2610                 return 0;
2611
2612         pci_restore_state(pci);
2613         pci_enable_device(pci);
2614         pci_set_master(pci);
2615
2616         /* first lets just bring everything back. .*/
2617         snd_m3_outw(chip, 0, 0x54);
2618         snd_m3_outw(chip, 0, 0x56);
2619
2620         snd_m3_chip_init(chip);
2621         snd_m3_assp_halt(chip);
2622         snd_m3_ac97_reset(chip);
2623
2624         /* restore dsp image */
2625         index = 0;
2626         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2627                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2628                                   chip->suspend_mem[index++]);
2629         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2630                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2631                                   chip->suspend_mem[index++]);
2632
2633         /* tell the dma engine to restart itself */
2634         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2635                           KDATA_DMA_ACTIVE, 0);
2636
2637         /* restore ac97 registers */
2638         snd_ac97_resume(chip->ac97);
2639
2640         snd_m3_assp_continue(chip);
2641         snd_m3_enable_ints(chip);
2642         snd_m3_amp_enable(chip, 1);
2643
2644         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2645         return 0;
2646 }
2647 #endif /* CONFIG_PM */
2648
2649
2650 /*
2651  */
2652
2653 static int snd_m3_dev_free(struct snd_device *device)
2654 {
2655         struct snd_m3 *chip = device->device_data;
2656         return snd_m3_free(chip);
2657 }
2658
2659 static int __devinit
2660 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2661               int enable_amp,
2662               int amp_gpio,
2663               struct snd_m3 **chip_ret)
2664 {
2665         struct snd_m3 *chip;
2666         int i, err;
2667         const struct m3_quirk *quirk;
2668         const struct m3_hv_quirk *hv_quirk;
2669         static struct snd_device_ops ops = {
2670                 .dev_free =     snd_m3_dev_free,
2671         };
2672
2673         *chip_ret = NULL;
2674
2675         if (pci_enable_device(pci))
2676                 return -EIO;
2677
2678         /* check, if we can restrict PCI DMA transfers to 28 bits */
2679         if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2680             pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2681                 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2682                 pci_disable_device(pci);
2683                 return -ENXIO;
2684         }
2685
2686         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2687         if (chip == NULL) {
2688                 pci_disable_device(pci);
2689                 return -ENOMEM;
2690         }
2691
2692         spin_lock_init(&chip->reg_lock);
2693         spin_lock_init(&chip->ac97_lock);
2694
2695         switch (pci->device) {
2696         case PCI_DEVICE_ID_ESS_ALLEGRO:
2697         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2698         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2699         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2700                 chip->allegro_flag = 1;
2701                 break;
2702         }
2703
2704         chip->card = card;
2705         chip->pci = pci;
2706         chip->irq = -1;
2707
2708         for (quirk = m3_quirk_list; quirk->vendor; quirk++) {
2709                 if (pci->subsystem_vendor == quirk->vendor &&
2710                     pci->subsystem_device == quirk->device) {
2711                         printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name);
2712                         chip->quirk = quirk;
2713                         break;
2714                 }
2715         }
2716
2717         for (hv_quirk = m3_hv_quirk_list; hv_quirk->vendor; hv_quirk++) {
2718                 if (pci->vendor == hv_quirk->vendor &&
2719                     pci->device == hv_quirk->device &&
2720                     pci->subsystem_vendor == hv_quirk->subsystem_vendor &&
2721                     pci->subsystem_device == hv_quirk->subsystem_device) {
2722                         chip->hv_quirk = hv_quirk;
2723                         break;
2724                 }
2725         }
2726
2727         chip->external_amp = enable_amp;
2728         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2729                 chip->amp_gpio = amp_gpio;
2730         else if (chip->quirk && chip->quirk->amp_gpio >= 0)
2731                 chip->amp_gpio = chip->quirk->amp_gpio;
2732         else if (chip->allegro_flag)
2733                 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2734         else /* presumably this is for all 'maestro3's.. */
2735                 chip->amp_gpio = GPO_EXT_AMP_M3;
2736
2737         chip->num_substreams = NR_DSPS;
2738         chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2739                                    GFP_KERNEL);
2740         if (chip->substreams == NULL) {
2741                 kfree(chip);
2742                 pci_disable_device(pci);
2743                 return -ENOMEM;
2744         }
2745
2746         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2747                 snd_m3_free(chip);
2748                 return err;
2749         }
2750         chip->iobase = pci_resource_start(pci, 0);
2751
2752         /* just to be sure */
2753         pci_set_master(pci);
2754
2755         snd_m3_chip_init(chip);
2756         snd_m3_assp_halt(chip);
2757
2758         snd_m3_ac97_reset(chip);
2759
2760         snd_m3_amp_enable(chip, 1);
2761
2762         tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2763
2764         if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
2765                         card->driver, chip)) {
2766                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2767                 snd_m3_free(chip);
2768                 return -ENOMEM;
2769         }
2770         chip->irq = pci->irq;
2771
2772 #ifdef CONFIG_PM
2773         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2774         if (chip->suspend_mem == NULL)
2775                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2776 #endif
2777
2778         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2779                 snd_m3_free(chip);
2780                 return err;
2781         }
2782
2783         if ((err = snd_m3_mixer(chip)) < 0)
2784                 return err;
2785
2786         for (i = 0; i < chip->num_substreams; i++) {
2787                 struct m3_dma *s = &chip->substreams[i];
2788                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2789                         return err;
2790         }
2791
2792         if ((err = snd_m3_pcm(chip, 0)) < 0)
2793                 return err;
2794
2795         snd_m3_enable_ints(chip);
2796         snd_m3_assp_continue(chip);
2797
2798         snd_card_set_dev(card, &pci->dev);
2799
2800         *chip_ret = chip;
2801
2802         return 0;
2803 }
2804
2805 /*
2806  */
2807 static int __devinit
2808 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2809 {
2810         static int dev;
2811         struct snd_card *card;
2812         struct snd_m3 *chip;
2813         int err;
2814
2815         /* don't pick up modems */
2816         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2817                 return -ENODEV;
2818
2819         if (dev >= SNDRV_CARDS)
2820                 return -ENODEV;
2821         if (!enable[dev]) {
2822                 dev++;
2823                 return -ENOENT;
2824         }
2825
2826         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2827         if (card == NULL)
2828                 return -ENOMEM;
2829
2830         switch (pci->device) {
2831         case PCI_DEVICE_ID_ESS_ALLEGRO:
2832         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2833                 strcpy(card->driver, "Allegro");
2834                 break;
2835         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2836         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2837                 strcpy(card->driver, "Canyon3D-2");
2838                 break;
2839         default:
2840                 strcpy(card->driver, "Maestro3");
2841                 break;
2842         }
2843
2844         if ((err = snd_m3_create(card, pci,
2845                                  external_amp[dev],
2846                                  amp_gpio[dev],
2847                                  &chip)) < 0) {
2848                 snd_card_free(card);
2849                 return err;
2850         }
2851         card->private_data = chip;
2852
2853         sprintf(card->shortname, "ESS %s PCI", card->driver);
2854         sprintf(card->longname, "%s at 0x%lx, irq %d",
2855                 card->shortname, chip->iobase, chip->irq);
2856
2857         if ((err = snd_card_register(card)) < 0) {
2858                 snd_card_free(card);
2859                 return err;
2860         }
2861
2862 #if 0 /* TODO: not supported yet */
2863         /* TODO enable MIDI IRQ and I/O */
2864         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2865                                   chip->iobase + MPU401_DATA_PORT, 1,
2866                                   chip->irq, 0, &chip->rmidi);
2867         if (err < 0)
2868                 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2869 #endif
2870
2871         pci_set_drvdata(pci, card);
2872         dev++;
2873         return 0;
2874 }
2875
2876 static void __devexit snd_m3_remove(struct pci_dev *pci)
2877 {
2878         snd_card_free(pci_get_drvdata(pci));
2879         pci_set_drvdata(pci, NULL);
2880 }
2881
2882 static struct pci_driver driver = {
2883         .name = "Maestro3",
2884         .id_table = snd_m3_ids,
2885         .probe = snd_m3_probe,
2886         .remove = __devexit_p(snd_m3_remove),
2887 #ifdef CONFIG_PM
2888         .suspend = m3_suspend,
2889         .resume = m3_resume,
2890 #endif
2891 };
2892
2893 static int __init alsa_card_m3_init(void)
2894 {
2895         return pci_register_driver(&driver);
2896 }
2897
2898 static void __exit alsa_card_m3_exit(void)
2899 {
2900         pci_unregister_driver(&driver);
2901 }
2902
2903 module_init(alsa_card_m3_init)
2904 module_exit(alsa_card_m3_exit)