sound/pci/maestro3.c

   1 /*
   2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   4  *                       Takashi Iwai <tiwai@suse.de>
   5  *
   6  * Most of the hardware init stuffs are based on maestro3 driver for
   7  * OSS/Free by Zach Brown.  Many thanks to Zach!
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of the GNU General Public License as published by
  11  *   the Free Software Foundation; either version 2 of the License, or
  12  *   (at your option) any later version.
  13  *
  14  *   This program is distributed in the hope that it will be useful,
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *   GNU General Public License for more details.
  18  *
  19  *   You should have received a copy of the GNU General Public License
  20  *   along with this program; if not, write to the Free Software
  21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  *
  23  *
  24  * ChangeLog:
  25  * Aug. 27, 2001
  26  *     - Fixed deadlock on capture
  27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  28  *
  29  */
  30
  31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  32 #define DRIVER_NAME "Maestro3"
  33
  34 #include <sound/driver.h>
  35 #include <asm/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/init.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/vmalloc.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/firmware.h>
  45 #include <sound/core.h>
  46 #include <sound/info.h>
  47 #include <sound/control.h>
  48 #include <sound/pcm.h>
  49 #include <sound/mpu401.h>
  50 #include <sound/ac97_codec.h>
  51 #include <sound/initval.h>
  52 #include <asm/byteorder.h>
  53
  54 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  55 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  56 MODULE_LICENSE("GPL");
  57 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  58                 "{ESS,ES1988},"
  59                 "{ESS,Allegro PCI},"
  60                 "{ESS,Allegro-1 PCI},"
  61                 "{ESS,Canyon3D-2/LE PCI}}");
  62 #ifndef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
  63 MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
  64 MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
  65 #endif
  66
  67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  69 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  70 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  71 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  72
  73 module_param_array(index, int, NULL, 0444);
  74 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  75 module_param_array(id, charp, NULL, 0444);
  76 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  77 module_param_array(enable, bool, NULL, 0444);
  78 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  79 module_param_array(external_amp, bool, NULL, 0444);
  80 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  81 module_param_array(amp_gpio, int, NULL, 0444);
  82 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  83
  84 #define MAX_PLAYBACKS   2
  85 #define MAX_CAPTURES    1
  86 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  87
  88
  89 /*
  90  * maestro3 registers
  91  */
  92
  93 /* Allegro PCI configuration registers */
  94 #define PCI_LEGACY_AUDIO_CTRL   0x40
  95 #define SOUND_BLASTER_ENABLE    0x00000001
  96 #define FM_SYNTHESIS_ENABLE     0x00000002
  97 #define GAME_PORT_ENABLE        0x00000004
  98 #define MPU401_IO_ENABLE        0x00000008
  99 #define MPU401_IRQ_ENABLE       0x00000010
 100 #define ALIAS_10BIT_IO          0x00000020
 101 #define SB_DMA_MASK             0x000000C0
 102 #define SB_DMA_0                0x00000040
 103 #define SB_DMA_1                0x00000040
 104 #define SB_DMA_R                0x00000080
 105 #define SB_DMA_3                0x000000C0
 106 #define SB_IRQ_MASK             0x00000700
 107 #define SB_IRQ_5                0x00000000
 108 #define SB_IRQ_7                0x00000100
 109 #define SB_IRQ_9                0x00000200
 110 #define SB_IRQ_10               0x00000300
 111 #define MIDI_IRQ_MASK           0x00003800
 112 #define SERIAL_IRQ_ENABLE       0x00004000
 113 #define DISABLE_LEGACY          0x00008000
 114
 115 #define PCI_ALLEGRO_CONFIG      0x50
 116 #define SB_ADDR_240             0x00000004
 117 #define MPU_ADDR_MASK           0x00000018
 118 #define MPU_ADDR_330            0x00000000
 119 #define MPU_ADDR_300            0x00000008
 120 #define MPU_ADDR_320            0x00000010
 121 #define MPU_ADDR_340            0x00000018
 122 #define USE_PCI_TIMING          0x00000040
 123 #define POSTED_WRITE_ENABLE     0x00000080
 124 #define DMA_POLICY_MASK         0x00000700
 125 #define DMA_DDMA                0x00000000
 126 #define DMA_TDMA                0x00000100
 127 #define DMA_PCPCI               0x00000200
 128 #define DMA_WBDMA16             0x00000400
 129 #define DMA_WBDMA4              0x00000500
 130 #define DMA_WBDMA2              0x00000600
 131 #define DMA_WBDMA1              0x00000700
 132 #define DMA_SAFE_GUARD          0x00000800
 133 #define HI_PERF_GP_ENABLE       0x00001000
 134 #define PIC_SNOOP_MODE_0        0x00002000
 135 #define PIC_SNOOP_MODE_1        0x00004000
 136 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 137 #define RING_IN_ENABLE          0x00010000
 138 #define SPDIF_TEST_MODE         0x00020000
 139 #define CLK_MULT_MODE_SELECT_2  0x00040000
 140 #define EEPROM_WRITE_ENABLE     0x00080000
 141 #define CODEC_DIR_IN            0x00100000
 142 #define HV_BUTTON_FROM_GD       0x00200000
 143 #define REDUCED_DEBOUNCE        0x00400000
 144 #define HV_CTRL_ENABLE          0x00800000
 145 #define SPDIF_ENABLE            0x01000000
 146 #define CLK_DIV_SELECT          0x06000000
 147 #define CLK_DIV_BY_48           0x00000000
 148 #define CLK_DIV_BY_49           0x02000000
 149 #define CLK_DIV_BY_50           0x04000000
 150 #define CLK_DIV_RESERVED        0x06000000
 151 #define PM_CTRL_ENABLE          0x08000000
 152 #define CLK_MULT_MODE_SELECT    0x30000000
 153 #define CLK_MULT_MODE_SHIFT     28
 154 #define CLK_MULT_MODE_0         0x00000000
 155 #define CLK_MULT_MODE_1         0x10000000
 156 #define CLK_MULT_MODE_2         0x20000000
 157 #define CLK_MULT_MODE_3         0x30000000
 158 #define INT_CLK_SELECT          0x40000000
 159 #define INT_CLK_MULT_RESET      0x80000000
 160
 161 /* M3 */
 162 #define INT_CLK_SRC_NOT_PCI     0x00100000
 163 #define INT_CLK_MULT_ENABLE     0x80000000
 164
 165 #define PCI_ACPI_CONTROL        0x54
 166 #define PCI_ACPI_D0             0x00000000
 167 #define PCI_ACPI_D1             0xB4F70000
 168 #define PCI_ACPI_D2             0xB4F7B4F7
 169
 170 #define PCI_USER_CONFIG         0x58
 171 #define EXT_PCI_MASTER_ENABLE   0x00000001
 172 #define SPDIF_OUT_SELECT        0x00000002
 173 #define TEST_PIN_DIR_CTRL       0x00000004
 174 #define AC97_CODEC_TEST         0x00000020
 175 #define TRI_STATE_BUFFER        0x00000080
 176 #define IN_CLK_12MHZ_SELECT     0x00000100
 177 #define MULTI_FUNC_DISABLE      0x00000200
 178 #define EXT_MASTER_PAIR_SEL     0x00000400
 179 #define PCI_MASTER_SUPPORT      0x00000800
 180 #define STOP_CLOCK_ENABLE       0x00001000
 181 #define EAPD_DRIVE_ENABLE       0x00002000
 182 #define REQ_TRI_STATE_ENABLE    0x00004000
 183 #define REQ_LOW_ENABLE          0x00008000
 184 #define MIDI_1_ENABLE           0x00010000
 185 #define MIDI_2_ENABLE           0x00020000
 186 #define SB_AUDIO_SYNC           0x00040000
 187 #define HV_CTRL_TEST            0x00100000
 188 #define SOUNDBLASTER_TEST       0x00400000
 189
 190 #define PCI_USER_CONFIG_C       0x5C
 191
 192 #define PCI_DDMA_CTRL           0x60
 193 #define DDMA_ENABLE             0x00000001
 194
 195
 196 /* Allegro registers */
 197 #define HOST_INT_CTRL           0x18
 198 #define SB_INT_ENABLE           0x0001
 199 #define MPU401_INT_ENABLE       0x0002
 200 #define ASSP_INT_ENABLE         0x0010
 201 #define RING_INT_ENABLE         0x0020
 202 #define HV_INT_ENABLE           0x0040
 203 #define CLKRUN_GEN_ENABLE       0x0100
 204 #define HV_CTRL_TO_PME          0x0400
 205 #define SOFTWARE_RESET_ENABLE   0x8000
 206
 207 /*
 208  * should be using the above defines, probably.
 209  */
 210 #define REGB_ENABLE_RESET               0x01
 211 #define REGB_STOP_CLOCK                 0x10
 212
 213 #define HOST_INT_STATUS         0x1A
 214 #define SB_INT_PENDING          0x01
 215 #define MPU401_INT_PENDING      0x02
 216 #define ASSP_INT_PENDING        0x10
 217 #define RING_INT_PENDING        0x20
 218 #define HV_INT_PENDING          0x40
 219
 220 #define HARDWARE_VOL_CTRL       0x1B
 221 #define SHADOW_MIX_REG_VOICE    0x1C
 222 #define HW_VOL_COUNTER_VOICE    0x1D
 223 #define SHADOW_MIX_REG_MASTER   0x1E
 224 #define HW_VOL_COUNTER_MASTER   0x1F
 225
 226 #define CODEC_COMMAND           0x30
 227 #define CODEC_READ_B            0x80
 228
 229 #define CODEC_STATUS            0x30
 230 #define CODEC_BUSY_B            0x01
 231
 232 #define CODEC_DATA              0x32
 233
 234 #define RING_BUS_CTRL_A         0x36
 235 #define RAC_PME_ENABLE          0x0100
 236 #define RAC_SDFS_ENABLE         0x0200
 237 #define LAC_PME_ENABLE          0x0400
 238 #define LAC_SDFS_ENABLE         0x0800
 239 #define SERIAL_AC_LINK_ENABLE   0x1000
 240 #define IO_SRAM_ENABLE          0x2000
 241 #define IIS_INPUT_ENABLE        0x8000
 242
 243 #define RING_BUS_CTRL_B         0x38
 244 #define SECOND_CODEC_ID_MASK    0x0003
 245 #define SPDIF_FUNC_ENABLE       0x0010
 246 #define SECOND_AC_ENABLE        0x0020
 247 #define SB_MODULE_INTF_ENABLE   0x0040
 248 #define SSPE_ENABLE             0x0040
 249 #define M3I_DOCK_ENABLE         0x0080
 250
 251 #define SDO_OUT_DEST_CTRL       0x3A
 252 #define COMMAND_ADDR_OUT        0x0003
 253 #define PCM_LR_OUT_LOCAL        0x0000
 254 #define PCM_LR_OUT_REMOTE       0x0004
 255 #define PCM_LR_OUT_MUTE         0x0008
 256 #define PCM_LR_OUT_BOTH         0x000C
 257 #define LINE1_DAC_OUT_LOCAL     0x0000
 258 #define LINE1_DAC_OUT_REMOTE    0x0010
 259 #define LINE1_DAC_OUT_MUTE      0x0020
 260 #define LINE1_DAC_OUT_BOTH      0x0030
 261 #define PCM_CLS_OUT_LOCAL       0x0000
 262 #define PCM_CLS_OUT_REMOTE      0x0040
 263 #define PCM_CLS_OUT_MUTE        0x0080
 264 #define PCM_CLS_OUT_BOTH        0x00C0
 265 #define PCM_RLF_OUT_LOCAL       0x0000
 266 #define PCM_RLF_OUT_REMOTE      0x0100
 267 #define PCM_RLF_OUT_MUTE        0x0200
 268 #define PCM_RLF_OUT_BOTH        0x0300
 269 #define LINE2_DAC_OUT_LOCAL     0x0000
 270 #define LINE2_DAC_OUT_REMOTE    0x0400
 271 #define LINE2_DAC_OUT_MUTE      0x0800
 272 #define LINE2_DAC_OUT_BOTH      0x0C00
 273 #define HANDSET_OUT_LOCAL       0x0000
 274 #define HANDSET_OUT_REMOTE      0x1000
 275 #define HANDSET_OUT_MUTE        0x2000
 276 #define HANDSET_OUT_BOTH        0x3000
 277 #define IO_CTRL_OUT_LOCAL       0x0000
 278 #define IO_CTRL_OUT_REMOTE      0x4000
 279 #define IO_CTRL_OUT_MUTE        0x8000
 280 #define IO_CTRL_OUT_BOTH        0xC000
 281
 282 #define SDO_IN_DEST_CTRL        0x3C
 283 #define STATUS_ADDR_IN          0x0003
 284 #define PCM_LR_IN_LOCAL         0x0000
 285 #define PCM_LR_IN_REMOTE        0x0004
 286 #define PCM_LR_RESERVED         0x0008
 287 #define PCM_LR_IN_BOTH          0x000C
 288 #define LINE1_ADC_IN_LOCAL      0x0000
 289 #define LINE1_ADC_IN_REMOTE     0x0010
 290 #define LINE1_ADC_IN_MUTE       0x0020
 291 #define MIC_ADC_IN_LOCAL        0x0000
 292 #define MIC_ADC_IN_REMOTE       0x0040
 293 #define MIC_ADC_IN_MUTE         0x0080
 294 #define LINE2_DAC_IN_LOCAL      0x0000
 295 #define LINE2_DAC_IN_REMOTE     0x0400
 296 #define LINE2_DAC_IN_MUTE       0x0800
 297 #define HANDSET_IN_LOCAL        0x0000
 298 #define HANDSET_IN_REMOTE       0x1000
 299 #define HANDSET_IN_MUTE         0x2000
 300 #define IO_STATUS_IN_LOCAL      0x0000
 301 #define IO_STATUS_IN_REMOTE     0x4000
 302
 303 #define SPDIF_IN_CTRL           0x3E
 304 #define SPDIF_IN_ENABLE         0x0001
 305
 306 #define GPIO_DATA               0x60
 307 #define GPIO_DATA_MASK          0x0FFF
 308 #define GPIO_HV_STATUS          0x3000
 309 #define GPIO_PME_STATUS         0x4000
 310
 311 #define GPIO_MASK               0x64
 312 #define GPIO_DIRECTION          0x68
 313 #define GPO_PRIMARY_AC97        0x0001
 314 #define GPI_LINEOUT_SENSE       0x0004
 315 #define GPO_SECONDARY_AC97      0x0008
 316 #define GPI_VOL_DOWN            0x0010
 317 #define GPI_VOL_UP              0x0020
 318 #define GPI_IIS_CLK             0x0040
 319 #define GPI_IIS_LRCLK           0x0080
 320 #define GPI_IIS_DATA            0x0100
 321 #define GPI_DOCKING_STATUS      0x0100
 322 #define GPI_HEADPHONE_SENSE     0x0200
 323 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 324
 325 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 326 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 327
 328 /* M3 */
 329 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 330
 331 #define ASSP_INDEX_PORT         0x80
 332 #define ASSP_MEMORY_PORT        0x82
 333 #define ASSP_DATA_PORT          0x84
 334
 335 #define MPU401_DATA_PORT        0x98
 336 #define MPU401_STATUS_PORT      0x99
 337
 338 #define CLK_MULT_DATA_PORT      0x9C
 339
 340 #define ASSP_CONTROL_A          0xA2
 341 #define ASSP_0_WS_ENABLE        0x01
 342 #define ASSP_CTRL_A_RESERVED1   0x02
 343 #define ASSP_CTRL_A_RESERVED2   0x04
 344 #define ASSP_CLK_49MHZ_SELECT   0x08
 345 #define FAST_PLU_ENABLE         0x10
 346 #define ASSP_CTRL_A_RESERVED3   0x20
 347 #define DSP_CLK_36MHZ_SELECT    0x40
 348
 349 #define ASSP_CONTROL_B          0xA4
 350 #define RESET_ASSP              0x00
 351 #define RUN_ASSP                0x01
 352 #define ENABLE_ASSP_CLOCK       0x00
 353 #define STOP_ASSP_CLOCK         0x10
 354 #define RESET_TOGGLE            0x40
 355
 356 #define ASSP_CONTROL_C          0xA6
 357 #define ASSP_HOST_INT_ENABLE    0x01
 358 #define FM_ADDR_REMAP_DISABLE   0x02
 359 #define HOST_WRITE_PORT_ENABLE  0x08
 360
 361 #define ASSP_HOST_INT_STATUS    0xAC
 362 #define DSP2HOST_REQ_PIORECORD  0x01
 363 #define DSP2HOST_REQ_I2SRATE    0x02
 364 #define DSP2HOST_REQ_TIMER      0x04
 365
 366 /* AC97 registers */
 367 /* XXX fix this crap up */
 368 /*#define AC97_RESET              0x00*/
 369
 370 #define AC97_VOL_MUTE_B         0x8000
 371 #define AC97_VOL_M              0x1F
 372 #define AC97_LEFT_VOL_S         8
 373
 374 #define AC97_MASTER_VOL         0x02
 375 #define AC97_LINE_LEVEL_VOL     0x04
 376 #define AC97_MASTER_MONO_VOL    0x06
 377 #define AC97_PC_BEEP_VOL        0x0A
 378 #define AC97_PC_BEEP_VOL_M      0x0F
 379 #define AC97_SROUND_MASTER_VOL  0x38
 380 #define AC97_PC_BEEP_VOL_S      1
 381
 382 /*#define AC97_PHONE_VOL          0x0C
 383 #define AC97_MIC_VOL            0x0E*/
 384 #define AC97_MIC_20DB_ENABLE    0x40
 385
 386 /*#define AC97_LINEIN_VOL         0x10
 387 #define AC97_CD_VOL             0x12
 388 #define AC97_VIDEO_VOL          0x14
 389 #define AC97_AUX_VOL            0x16*/
 390 #define AC97_PCM_OUT_VOL        0x18
 391 /*#define AC97_RECORD_SELECT      0x1A*/
 392 #define AC97_RECORD_MIC         0x00
 393 #define AC97_RECORD_CD          0x01
 394 #define AC97_RECORD_VIDEO       0x02
 395 #define AC97_RECORD_AUX         0x03
 396 #define AC97_RECORD_MONO_MUX    0x02
 397 #define AC97_RECORD_DIGITAL     0x03
 398 #define AC97_RECORD_LINE        0x04
 399 #define AC97_RECORD_STEREO      0x05
 400 #define AC97_RECORD_MONO        0x06
 401 #define AC97_RECORD_PHONE       0x07
 402
 403 /*#define AC97_RECORD_GAIN        0x1C*/
 404 #define AC97_RECORD_VOL_M       0x0F
 405
 406 /*#define AC97_GENERAL_PURPOSE    0x20*/
 407 #define AC97_POWER_DOWN_CTRL    0x26
 408 #define AC97_ADC_READY          0x0001
 409 #define AC97_DAC_READY          0x0002
 410 #define AC97_ANALOG_READY       0x0004
 411 #define AC97_VREF_ON            0x0008
 412 #define AC97_PR0                0x0100
 413 #define AC97_PR1                0x0200
 414 #define AC97_PR2                0x0400
 415 #define AC97_PR3                0x0800
 416 #define AC97_PR4                0x1000
 417
 418 #define AC97_RESERVED1          0x28
 419
 420 #define AC97_VENDOR_TEST        0x5A
 421
 422 #define AC97_CLOCK_DELAY        0x5C
 423 #define AC97_LINEOUT_MUX_SEL    0x0001
 424 #define AC97_MONO_MUX_SEL       0x0002
 425 #define AC97_CLOCK_DELAY_SEL    0x1F
 426 #define AC97_DAC_CDS_SHIFT      6
 427 #define AC97_ADC_CDS_SHIFT      11
 428
 429 #define AC97_MULTI_CHANNEL_SEL  0x74
 430
 431 /*#define AC97_VENDOR_ID1         0x7C
 432 #define AC97_VENDOR_ID2         0x7E*/
 433
 434 /*
 435  * ASSP control regs
 436  */
 437 #define DSP_PORT_TIMER_COUNT    0x06
 438
 439 #define DSP_PORT_MEMORY_INDEX   0x80
 440
 441 #define DSP_PORT_MEMORY_TYPE    0x82
 442 #define MEMTYPE_INTERNAL_CODE   0x0002
 443 #define MEMTYPE_INTERNAL_DATA   0x0003
 444 #define MEMTYPE_MASK            0x0003
 445
 446 #define DSP_PORT_MEMORY_DATA    0x84
 447
 448 #define DSP_PORT_CONTROL_REG_A  0xA2
 449 #define DSP_PORT_CONTROL_REG_B  0xA4
 450 #define DSP_PORT_CONTROL_REG_C  0xA6
 451
 452 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 453 #define REV_A_CODE_MEMORY_END           0x0FFF
 454 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 455 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 456
 457 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 458 #define REV_B_CODE_MEMORY_END           0x0BFF
 459 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 460 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 461
 462 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 463 #define REV_A_DATA_MEMORY_END           0x2FFF
 464 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 465 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 466
 467 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 468 #define REV_B_DATA_MEMORY_END           0x2BFF
 469 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 470 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 471
 472
 473 #define NUM_UNITS_KERNEL_CODE          16
 474 #define NUM_UNITS_KERNEL_DATA           2
 475
 476 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 477 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 478
 479 /*
 480  * Kernel data layout
 481  */
 482
 483 #define DP_SHIFT_COUNT                  7
 484
 485 #define KDATA_BASE_ADDR                 0x1000
 486 #define KDATA_BASE_ADDR2                0x1080
 487
 488 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 489 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 490 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 491 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 492 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 493 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 494 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 495 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 496 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 497
 498 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 499 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 500
 501 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 502 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 503 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 504 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 505 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 506 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 507 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 508 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 509 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 510 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 511
 512 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 513 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 514
 515 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 516 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 517
 518 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 519 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 520
 521 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 522 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 523 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 524
 525 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 526 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 527 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 528 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 529 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 530
 531 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 532 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 533 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 534
 535 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 536 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 537 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 538
 539 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 540 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 541 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 542 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 543 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 544 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 545 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 546 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 547 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 548 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 549
 550 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 551 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 552 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 553
 554 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 555 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 556
 557 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 558 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 559 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 560
 561 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 562 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 563 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 564 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 565 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 566 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 567
 568 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 569 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 570 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 571 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 572 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 573 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 574
 575 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 576 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 577 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 578 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 579 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 580 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 581
 582 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 583 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 584 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 585 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 586
 587 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 588 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 589
 590 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 591 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 592
 593 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 594 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 595 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 596 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 597 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 598
 599 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 600 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 601
 602 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 603 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 604 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 605
 606 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 607 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 608
 609 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 610
 611 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 612 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 613 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 614 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 615 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 616 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 617 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 618 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 619 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 620 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 621 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 622 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 623
 624 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 625 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 626 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 627 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 628
 629 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 630 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 631
 632 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 633 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 634 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 635 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 636
 637 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 638 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 639 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 640 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 641 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 642
 643 /*
 644  * second 'segment' (?) reserved for mixer
 645  * buffers..
 646  */
 647
 648 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 649 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 650 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 651 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 652 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 653 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 654 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 655 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 656 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 657 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 658 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 659 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 660 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 661 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 662 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 663 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 664
 665 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 666 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 667 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 668 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 669 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 670 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 671 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 672 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 673 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 674 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 675 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 676
 677 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 678 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 679 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 680 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 681 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 682 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 683
 684 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 685 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 686 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 687 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 688
 689 /*
 690  * client data area offsets
 691  */
 692 #define CDATA_INSTANCE_READY            0x00
 693
 694 #define CDATA_HOST_SRC_ADDRL            0x01
 695 #define CDATA_HOST_SRC_ADDRH            0x02
 696 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 697 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 698 #define CDATA_HOST_SRC_CURRENTL         0x05
 699 #define CDATA_HOST_SRC_CURRENTH         0x06
 700
 701 #define CDATA_IN_BUF_CONNECT            0x07
 702 #define CDATA_OUT_BUF_CONNECT           0x08
 703
 704 #define CDATA_IN_BUF_BEGIN              0x09
 705 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 706 #define CDATA_IN_BUF_HEAD               0x0B
 707 #define CDATA_IN_BUF_TAIL               0x0C
 708 #define CDATA_OUT_BUF_BEGIN             0x0D
 709 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 710 #define CDATA_OUT_BUF_HEAD              0x0F
 711 #define CDATA_OUT_BUF_TAIL              0x10
 712
 713 #define CDATA_DMA_CONTROL               0x11
 714 #define CDATA_RESERVED                  0x12
 715
 716 #define CDATA_FREQUENCY                 0x13
 717 #define CDATA_LEFT_VOLUME               0x14
 718 #define CDATA_RIGHT_VOLUME              0x15
 719 #define CDATA_LEFT_SUR_VOL              0x16
 720 #define CDATA_RIGHT_SUR_VOL             0x17
 721
 722 #define CDATA_HEADER_LEN                0x18
 723
 724 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 725 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 726 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 727 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 728 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 729 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 730 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 731 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 732
 733 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 734 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 735 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 736 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 737 #define MINISRC_BIQUAD_STAGE    2
 738 #define MINISRC_COEF_LOC          0x175
 739
 740 #define DMACONTROL_BLOCK_MASK           0x000F
 741 #define  DMAC_BLOCK0_SELECTOR           0x0000
 742 #define  DMAC_BLOCK1_SELECTOR           0x0001
 743 #define  DMAC_BLOCK2_SELECTOR           0x0002
 744 #define  DMAC_BLOCK3_SELECTOR           0x0003
 745 #define  DMAC_BLOCK4_SELECTOR           0x0004
 746 #define  DMAC_BLOCK5_SELECTOR           0x0005
 747 #define  DMAC_BLOCK6_SELECTOR           0x0006
 748 #define  DMAC_BLOCK7_SELECTOR           0x0007
 749 #define  DMAC_BLOCK8_SELECTOR           0x0008
 750 #define  DMAC_BLOCK9_SELECTOR           0x0009
 751 #define  DMAC_BLOCKA_SELECTOR           0x000A
 752 #define  DMAC_BLOCKB_SELECTOR           0x000B
 753 #define  DMAC_BLOCKC_SELECTOR           0x000C
 754 #define  DMAC_BLOCKD_SELECTOR           0x000D
 755 #define  DMAC_BLOCKE_SELECTOR           0x000E
 756 #define  DMAC_BLOCKF_SELECTOR           0x000F
 757 #define DMACONTROL_PAGE_MASK            0x00F0
 758 #define  DMAC_PAGE0_SELECTOR            0x0030
 759 #define  DMAC_PAGE1_SELECTOR            0x0020
 760 #define  DMAC_PAGE2_SELECTOR            0x0010
 761 #define  DMAC_PAGE3_SELECTOR            0x0000
 762 #define DMACONTROL_AUTOREPEAT           0x1000
 763 #define DMACONTROL_STOPPED              0x2000
 764 #define DMACONTROL_DIRECTION            0x0100
 765
 766 /*
 767  * an arbitrary volume we set the internal
 768  * volume settings to so that the ac97 volume
 769  * range is a little less insane.  0x7fff is
 770  * max.
 771  */
 772 #define ARB_VOLUME ( 0x6800 )
 773
 774 /*
 775  */
 776
 777 struct m3_list {
 778         int curlen;
 779         int mem_addr;
 780         int max;
 781 };
 782
 783 struct m3_dma {
 784
 785         int number;
 786         struct snd_pcm_substream *substream;
 787
 788         struct assp_instance {
 789                 unsigned short code, data;
 790         } inst;
 791
 792         int running;
 793         int opened;
 794
 795         unsigned long buffer_addr;
 796         int dma_size;
 797         int period_size;
 798         unsigned int hwptr;
 799         int count;
 800
 801         int index[3];
 802         struct m3_list *index_list[3];
 803
 804         int in_lists;
 805
 806         struct list_head list;
 807
 808 };
 809
 810 struct snd_m3 {
 811
 812         struct snd_card *card;
 813
 814         unsigned long iobase;
 815
 816         int irq;
 817         unsigned int allegro_flag : 1;
 818
 819         struct snd_ac97 *ac97;
 820
 821         struct snd_pcm *pcm;
 822
 823         struct pci_dev *pci;
 824
 825         int dacs_active;
 826         int timer_users;
 827
 828         struct m3_list  msrc_list;
 829         struct m3_list  mixer_list;
 830         struct m3_list  adc1_list;
 831         struct m3_list  dma_list;
 832
 833         /* for storing reset state..*/
 834         u8 reset_state;
 835
 836         int external_amp;
 837         int amp_gpio;   /* gpio pin #  for external amp, -1 = default */
 838         unsigned int hv_config;         /* hardware-volume config bits */
 839         unsigned irda_workaround :1;    /* avoid to touch 0x10 on GPIO_DIRECTION
 840                                            (e.g. for IrDA on Dell Inspirons) */
 841         unsigned is_omnibook :1;        /* Do HP OmniBook GPIO magic? */
 842
 843         /* midi */
 844         struct snd_rawmidi *rmidi;
 845
 846         /* pcm streams */
 847         int num_substreams;
 848         struct m3_dma *substreams;
 849
 850         spinlock_t reg_lock;
 851         spinlock_t ac97_lock;
 852
 853         struct snd_kcontrol *master_switch;
 854         struct snd_kcontrol *master_volume;
 855         struct tasklet_struct hwvol_tq;
 856
 857 #ifdef CONFIG_PM
 858         u16 *suspend_mem;
 859 #endif
 860
 861         const struct firmware *assp_kernel_image;
 862         const struct firmware *assp_minisrc_image;
 863 };
 864
 865 /*
 866  * pci ids
 867  */
 868 static struct pci_device_id snd_m3_ids[] = {
 869         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 870          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 871         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 872          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 873         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 874          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 875         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 876          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 877         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 878          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 879         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 880          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 881         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 882          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 883         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 884          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 885         {0,},
 886 };
 887
 888 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 889
 890 static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
 891         SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
 892         SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
 893         SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
 894         SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
 895         { } /* END */
 896 };
 897
 898 static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
 899         SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
 900         SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
 901         SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
 902         { } /* END */
 903 };
 904
 905 /* hardware volume quirks */
 906 static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
 907         /* Allegro chips */
 908         SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 909         SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 910         SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 911         SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 912         SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 913         SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 914         SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 915         SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 916         SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 917         SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 918         SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 919         SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 920         SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 921         SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 922         SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 923         SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 924         SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 925         SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 926         SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 927         SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 928         SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 929         SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 930         SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 931         SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 932         SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 933         SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
 934                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 935         SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
 936                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 937         SND_PCI_QUIRK(0x107B, 0x340A, NULL,
 938                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 939         SND_PCI_QUIRK(0x107B, 0x3450, NULL,
 940                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 941         SND_PCI_QUIRK(0x109F, 0x3134, NULL,
 942                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 943         SND_PCI_QUIRK(0x109F, 0x3161, NULL,
 944                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 945         SND_PCI_QUIRK(0x144D, 0x3280, NULL,
 946                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 947         SND_PCI_QUIRK(0x144D, 0x3281, NULL,
 948                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 949         SND_PCI_QUIRK(0x144D, 0xC002, NULL,
 950                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 951         SND_PCI_QUIRK(0x144D, 0xC003, NULL,
 952                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 953         SND_PCI_QUIRK(0x1509, 0x1740, NULL,
 954                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 955         SND_PCI_QUIRK(0x1610, 0x0010, NULL,
 956                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 957         SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
 958         SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
 959         SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
 960         SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
 961         SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
 962         /* Maestro3 chips */
 963         SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
 964         SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
 965         SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
 966         SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
 967         SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
 968         SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
 969         SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
 970         SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
 971         SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
 972         SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
 973         SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
 974         SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
 975         SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
 976         SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 977         SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 978         SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 979         SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 980         { } /* END */
 981 };
 982
 983 /* HP Omnibook quirks */
 984 static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
 985         SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
 986         SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
 987         { } /* END */
 988 };
 989
 990 /*
 991  * lowlevel functions
 992  */
 993
 994 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
 995 {
 996         outw(value, chip->iobase + reg);
 997 }
 998
 999 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
1000 {
1001         return inw(chip->iobase + reg);
1002 }
1003
1004 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1005 {
1006         outb(value, chip->iobase + reg);
1007 }
1008
1009 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1010 {
1011         return inb(chip->iobase + reg);
1012 }
1013
1014 /*
1015  * access 16bit words to the code or data regions of the dsp's memory.
1016  * index addresses 16bit words.
1017  */
1018 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1019 {
1020         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1021         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1022         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1023 }
1024
1025 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1026 {
1027         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1028         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1029         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1030 }
1031
1032 static void snd_m3_assp_halt(struct snd_m3 *chip)
1033 {
1034         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1035         msleep(10);
1036         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1037 }
1038
1039 static void snd_m3_assp_continue(struct snd_m3 *chip)
1040 {
1041         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1042 }
1043
1044
1045 /*
1046  * This makes me sad. the maestro3 has lists
1047  * internally that must be packed.. 0 terminates,
1048  * apparently, or maybe all unused entries have
1049  * to be 0, the lists have static lengths set
1050  * by the binary code images.
1051  */
1052
1053 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1054 {
1055         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1056                           list->mem_addr + list->curlen,
1057                           val);
1058         return list->curlen++;
1059 }
1060
1061 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1062 {
1063         u16  val;
1064         int lastindex = list->curlen - 1;
1065
1066         if (index != lastindex) {
1067                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1068                                        list->mem_addr + lastindex);
1069                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1070                                   list->mem_addr + index,
1071                                   val);
1072         }
1073
1074         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1075                           list->mem_addr + lastindex,
1076                           0);
1077
1078         list->curlen--;
1079 }
1080
1081 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1082 {
1083         chip->timer_users++;
1084         if (chip->timer_users != 1)
1085                 return;
1086
1087         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1088                           KDATA_TIMER_COUNT_RELOAD,
1089                           240);
1090
1091         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1092                           KDATA_TIMER_COUNT_CURRENT,
1093                           240);
1094
1095         snd_m3_outw(chip,
1096                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1097                     HOST_INT_CTRL);
1098 }
1099
1100 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1101 {
1102         chip->timer_users--;
1103         if (chip->timer_users > 0)
1104                 return;
1105
1106         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1107                           KDATA_TIMER_COUNT_RELOAD,
1108                           0);
1109
1110         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1111                           KDATA_TIMER_COUNT_CURRENT,
1112                           0);
1113
1114         snd_m3_outw(chip,
1115                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1116                     HOST_INT_CTRL);
1117 }
1118
1119 /*
1120  * start/stop
1121  */
1122
1123 /* spinlock held! */
1124 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1125                             struct snd_pcm_substream *subs)
1126 {
1127         if (! s || ! subs)
1128                 return -EINVAL;
1129
1130         snd_m3_inc_timer_users(chip);
1131         switch (subs->stream) {
1132         case SNDRV_PCM_STREAM_PLAYBACK:
1133                 chip->dacs_active++;
1134                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1135                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1136                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1137                                   KDATA_MIXER_TASK_NUMBER,
1138                                   chip->dacs_active);
1139                 break;
1140         case SNDRV_PCM_STREAM_CAPTURE:
1141                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1142                                   KDATA_ADC1_REQUEST, 1);
1143                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1144                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1145                 break;
1146         }
1147         return 0;
1148 }
1149
1150 /* spinlock held! */
1151 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1152                            struct snd_pcm_substream *subs)
1153 {
1154         if (! s || ! subs)
1155                 return -EINVAL;
1156
1157         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1158                           s->inst.data + CDATA_INSTANCE_READY, 0);
1159         snd_m3_dec_timer_users(chip);
1160         switch (subs->stream) {
1161         case SNDRV_PCM_STREAM_PLAYBACK:
1162                 chip->dacs_active--;
1163                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1164                                   KDATA_MIXER_TASK_NUMBER,
1165                                   chip->dacs_active);
1166                 break;
1167         case SNDRV_PCM_STREAM_CAPTURE:
1168                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1169                                   KDATA_ADC1_REQUEST, 0);
1170                 break;
1171         }
1172         return 0;
1173 }
1174
1175 static int
1176 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1177 {
1178         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1179         struct m3_dma *s = subs->runtime->private_data;
1180         int err = -EINVAL;
1181
1182         snd_assert(s != NULL, return -ENXIO);
1183
1184         spin_lock(&chip->reg_lock);
1185         switch (cmd) {
1186         case SNDRV_PCM_TRIGGER_START:
1187         case SNDRV_PCM_TRIGGER_RESUME:
1188                 if (s->running)
1189                         err = -EBUSY;
1190                 else {
1191                         s->running = 1;
1192                         err = snd_m3_pcm_start(chip, s, subs);
1193                 }
1194                 break;
1195         case SNDRV_PCM_TRIGGER_STOP:
1196         case SNDRV_PCM_TRIGGER_SUSPEND:
1197                 if (! s->running)
1198                         err = 0; /* should return error? */
1199                 else {
1200                         s->running = 0;
1201                         err = snd_m3_pcm_stop(chip, s, subs);
1202                 }
1203                 break;
1204         }
1205         spin_unlock(&chip->reg_lock);
1206         return err;
1207 }
1208
1209 /*
1210  * setup
1211  */
1212 static void
1213 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1214 {
1215         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1216         struct snd_pcm_runtime *runtime = subs->runtime;
1217
1218         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1219                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1220                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1221         } else {
1222                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1223                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1224         }
1225         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1226         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1227
1228         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1229         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1230         s->hwptr = 0;
1231         s->count = 0;
1232
1233 #define LO(x) ((x) & 0xffff)
1234 #define HI(x) LO((x) >> 16)
1235
1236         /* host dma buffer pointers */
1237         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1238                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1239                           LO(s->buffer_addr));
1240
1241         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1242                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1243                           HI(s->buffer_addr));
1244
1245         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1246                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1247                           LO(s->buffer_addr + s->dma_size));
1248
1249         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1250                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1251                           HI(s->buffer_addr + s->dma_size));
1252
1253         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1254                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1255                           LO(s->buffer_addr));
1256
1257         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1258                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1259                           HI(s->buffer_addr));
1260 #undef LO
1261 #undef HI
1262
1263         /* dsp buffers */
1264
1265         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1266                           s->inst.data + CDATA_IN_BUF_BEGIN,
1267                           dsp_in_buffer);
1268
1269         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1270                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1271                           dsp_in_buffer + (dsp_in_size / 2));
1272
1273         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1274                           s->inst.data + CDATA_IN_BUF_HEAD,
1275                           dsp_in_buffer);
1276
1277         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1278                           s->inst.data + CDATA_IN_BUF_TAIL,
1279                           dsp_in_buffer);
1280
1281         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1282                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1283                           dsp_out_buffer);
1284
1285         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1286                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1287                           dsp_out_buffer + (dsp_out_size / 2));
1288
1289         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1290                           s->inst.data + CDATA_OUT_BUF_HEAD,
1291                           dsp_out_buffer);
1292
1293         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1294                           s->inst.data + CDATA_OUT_BUF_TAIL,
1295                           dsp_out_buffer);
1296 }
1297
1298 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1299                               struct snd_pcm_runtime *runtime)
1300 {
1301         u32 freq;
1302
1303         /*
1304          * put us in the lists if we're not already there
1305          */
1306         if (! s->in_lists) {
1307                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1308                                               s->inst.data >> DP_SHIFT_COUNT);
1309                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1310                                               s->inst.data >> DP_SHIFT_COUNT);
1311                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1312                                               s->inst.data >> DP_SHIFT_COUNT);
1313                 s->in_lists = 1;
1314         }
1315
1316         /* write to 'mono' word */
1317         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1318                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1319                           runtime->channels == 2 ? 0 : 1);
1320         /* write to '8bit' word */
1321         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1322                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1323                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1324
1325         /* set up dac/adc rate */
1326         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1327         if (freq)
1328                 freq--;
1329
1330         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1331                           s->inst.data + CDATA_FREQUENCY,
1332                           freq);
1333 }
1334
1335
1336 static const struct play_vals {
1337         u16 addr, val;
1338 } pv[] = {
1339         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1340         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1341         {SRC3_DIRECTION_OFFSET, 0} ,
1342         /* +1, +2 are stereo/16 bit */
1343         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1344         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1345         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1346         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1347         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1348         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1349         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1350         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1351         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1352         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1353         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1354         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1355         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1356         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1357         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1358         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1359         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1360 };
1361
1362
1363 /* the mode passed should be already shifted and masked */
1364 static void
1365 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1366                       struct snd_pcm_substream *subs)
1367 {
1368         unsigned int i;
1369
1370         /*
1371          * some per client initializers
1372          */
1373
1374         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1375                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1376                           s->inst.data + 40 + 8);
1377
1378         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1379                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1380                           s->inst.code + MINISRC_COEF_LOC);
1381
1382         /* enable or disable low pass filter? */
1383         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1384                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1385                           subs->runtime->rate > 45000 ? 0xff : 0);
1386
1387         /* tell it which way dma is going? */
1388         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1389                           s->inst.data + CDATA_DMA_CONTROL,
1390                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1391
1392         /*
1393          * set an armload of static initializers
1394          */
1395         for (i = 0; i < ARRAY_SIZE(pv); i++)
1396                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1397                                   s->inst.data + pv[i].addr, pv[i].val);
1398 }
1399
1400 /*
1401  *    Native record driver
1402  */
1403 static const struct rec_vals {
1404         u16 addr, val;
1405 } rv[] = {
1406         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1407         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1408         {SRC3_DIRECTION_OFFSET, 1} ,
1409         /* +1, +2 are stereo/16 bit */
1410         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1411         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1412         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1413         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1414         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1415         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1416         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1417         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1418         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1419         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1420         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1421         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1422         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1423         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1424         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1425         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1426         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1427         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1428         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1429 };
1430
1431 static void
1432 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1433 {
1434         unsigned int i;
1435
1436         /*
1437          * some per client initializers
1438          */
1439
1440         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1441                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1442                           s->inst.data + 40 + 8);
1443
1444         /* tell it which way dma is going? */
1445         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1446                           s->inst.data + CDATA_DMA_CONTROL,
1447                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1448                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1449
1450         /*
1451          * set an armload of static initializers
1452          */
1453         for (i = 0; i < ARRAY_SIZE(rv); i++)
1454                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1455                                   s->inst.data + rv[i].addr, rv[i].val);
1456 }
1457
1458 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1459                                 struct snd_pcm_hw_params *hw_params)
1460 {
1461         struct m3_dma *s = substream->runtime->private_data;
1462         int err;
1463
1464         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1465                 return err;
1466         /* set buffer address */
1467         s->buffer_addr = substream->runtime->dma_addr;
1468         if (s->buffer_addr & 0x3) {
1469                 snd_printk(KERN_ERR "oh my, not aligned\n");
1470                 s->buffer_addr = s->buffer_addr & ~0x3;
1471         }
1472         return 0;
1473 }
1474
1475 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1476 {
1477         struct m3_dma *s;
1478
1479         if (substream->runtime->private_data == NULL)
1480                 return 0;
1481         s = substream->runtime->private_data;
1482         snd_pcm_lib_free_pages(substream);
1483         s->buffer_addr = 0;
1484         return 0;
1485 }
1486
1487 static int
1488 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1489 {
1490         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1491         struct snd_pcm_runtime *runtime = subs->runtime;
1492         struct m3_dma *s = runtime->private_data;
1493
1494         snd_assert(s != NULL, return -ENXIO);
1495
1496         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1497             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1498                 return -EINVAL;
1499         if (runtime->rate > 48000 ||
1500             runtime->rate < 8000)
1501                 return -EINVAL;
1502
1503         spin_lock_irq(&chip->reg_lock);
1504
1505         snd_m3_pcm_setup1(chip, s, subs);
1506
1507         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1508                 snd_m3_playback_setup(chip, s, subs);
1509         else
1510                 snd_m3_capture_setup(chip, s, subs);
1511
1512         snd_m3_pcm_setup2(chip, s, runtime);
1513
1514         spin_unlock_irq(&chip->reg_lock);
1515
1516         return 0;
1517 }
1518
1519 /*
1520  * get current pointer
1521  */
1522 static unsigned int
1523 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1524 {
1525         u16 hi = 0, lo = 0;
1526         int retry = 10;
1527         u32 addr;
1528
1529         /*
1530          * try and get a valid answer
1531          */
1532         while (retry--) {
1533                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1534                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1535
1536                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1537                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1538
1539                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1540                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1541                         break;
1542         }
1543         addr = lo | ((u32)hi<<16);
1544         return (unsigned int)(addr - s->buffer_addr);
1545 }
1546
1547 static snd_pcm_uframes_t
1548 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1549 {
1550         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1551         unsigned int ptr;
1552         struct m3_dma *s = subs->runtime->private_data;
1553         snd_assert(s != NULL, return 0);
1554
1555         spin_lock(&chip->reg_lock);
1556         ptr = snd_m3_get_pointer(chip, s, subs);
1557         spin_unlock(&chip->reg_lock);
1558         return bytes_to_frames(subs->runtime, ptr);
1559 }
1560
1561
1562 /* update pointer */
1563 /* spinlock held! */
1564 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1565 {
1566         struct snd_pcm_substream *subs = s->substream;
1567         unsigned int hwptr;
1568         int diff;
1569
1570         if (! s->running)
1571                 return;
1572
1573         hwptr = snd_m3_get_pointer(chip, s, subs);
1574
1575         /* try to avoid expensive modulo divisions */
1576         if (hwptr >= s->dma_size)
1577                 hwptr %= s->dma_size;
1578
1579         diff = s->dma_size + hwptr - s->hwptr;
1580         if (diff >= s->dma_size)
1581                 diff %= s->dma_size;
1582
1583         s->hwptr = hwptr;
1584         s->count += diff;
1585
1586         if (s->count >= (signed)s->period_size) {
1587
1588                 if (s->count < 2 * (signed)s->period_size)
1589                         s->count -= (signed)s->period_size;
1590                 else
1591                         s->count %= s->period_size;
1592
1593                 spin_unlock(&chip->reg_lock);
1594                 snd_pcm_period_elapsed(subs);
1595                 spin_lock(&chip->reg_lock);
1596         }
1597 }
1598
1599 static void snd_m3_update_hw_volume(unsigned long private_data)
1600 {
1601         struct snd_m3 *chip = (struct snd_m3 *) private_data;
1602         int x, val;
1603         unsigned long flags;
1604
1605         /* Figure out which volume control button was pushed,
1606            based on differences from the default register
1607            values. */
1608         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1609
1610         /* Reset the volume control registers. */
1611         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1612         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1613         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1614         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1615
1616         if (!chip->master_switch || !chip->master_volume)
1617                 return;
1618
1619         /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1620         spin_lock_irqsave(&chip->ac97_lock, flags);
1621
1622         val = chip->ac97->regs[AC97_MASTER_VOL];
1623         switch (x) {
1624         case 0x88:
1625                 /* mute */
1626                 val ^= 0x8000;
1627                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1628                 outw(val, chip->iobase + CODEC_DATA);
1629                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1630                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1631                                &chip->master_switch->id);
1632                 break;
1633         case 0xaa:
1634                 /* volume up */
1635                 if ((val & 0x7f) > 0)
1636                         val--;
1637                 if ((val & 0x7f00) > 0)
1638                         val -= 0x0100;
1639                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1640                 outw(val, chip->iobase + CODEC_DATA);
1641                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1642                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1643                                &chip->master_volume->id);
1644                 break;
1645         case 0x66:
1646                 /* volume down */
1647                 if ((val & 0x7f) < 0x1f)
1648                         val++;
1649                 if ((val & 0x7f00) < 0x1f00)
1650                         val += 0x0100;
1651                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1652                 outw(val, chip->iobase + CODEC_DATA);
1653                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1654                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1655                                &chip->master_volume->id);
1656                 break;
1657         }
1658         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1659 }
1660
1661 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1662 {
1663         struct snd_m3 *chip = dev_id;
1664         u8 status;
1665         int i;
1666
1667         status = inb(chip->iobase + HOST_INT_STATUS);
1668
1669         if (status == 0xff)
1670                 return IRQ_NONE;
1671
1672         if (status & HV_INT_PENDING)
1673                 tasklet_hi_schedule(&chip->hwvol_tq);
1674
1675         /*
1676          * ack an assp int if its running
1677          * and has an int pending
1678          */
1679         if (status & ASSP_INT_PENDING) {
1680                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1681                 if (!(ctl & STOP_ASSP_CLOCK)) {
1682                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1683                         if (ctl & DSP2HOST_REQ_TIMER) {
1684                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1685                                 /* update adc/dac info if it was a timer int */
1686                                 spin_lock(&chip->reg_lock);
1687                                 for (i = 0; i < chip->num_substreams; i++) {
1688                                         struct m3_dma *s = &chip->substreams[i];
1689                                         if (s->running)
1690                                                 snd_m3_update_ptr(chip, s);
1691                                 }
1692                                 spin_unlock(&chip->reg_lock);
1693                         }
1694                 }
1695         }
1696
1697 #if 0 /* TODO: not supported yet */
1698         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1699                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1700 #endif
1701
1702         /* ack ints */
1703         outb(status, chip->iobase + HOST_INT_STATUS);
1704
1705         return IRQ_HANDLED;
1706 }
1707
1708
1709 /*
1710  */
1711
1712 static struct snd_pcm_hardware snd_m3_playback =
1713 {
1714         .info =                 (SNDRV_PCM_INFO_MMAP |
1715                                  SNDRV_PCM_INFO_INTERLEAVED |
1716                                  SNDRV_PCM_INFO_MMAP_VALID |
1717                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1718                                  /*SNDRV_PCM_INFO_PAUSE |*/
1719                                  SNDRV_PCM_INFO_RESUME),
1720         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1721         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1722         .rate_min =             8000,
1723         .rate_max =             48000,
1724         .channels_min =         1,
1725         .channels_max =         2,
1726         .buffer_bytes_max =     (512*1024),
1727         .period_bytes_min =     64,
1728         .period_bytes_max =     (512*1024),
1729         .periods_min =          1,
1730         .periods_max =          1024,
1731 };
1732
1733 static struct snd_pcm_hardware snd_m3_capture =
1734 {
1735         .info =                 (SNDRV_PCM_INFO_MMAP |
1736                                  SNDRV_PCM_INFO_INTERLEAVED |
1737                                  SNDRV_PCM_INFO_MMAP_VALID |
1738                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1739                                  /*SNDRV_PCM_INFO_PAUSE |*/
1740                                  SNDRV_PCM_INFO_RESUME),
1741         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1742         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1743         .rate_min =             8000,
1744         .rate_max =             48000,
1745         .channels_min =         1,
1746         .channels_max =         2,
1747         .buffer_bytes_max =     (512*1024),
1748         .period_bytes_min =     64,
1749         .period_bytes_max =     (512*1024),
1750         .periods_min =          1,
1751         .periods_max =          1024,
1752 };
1753
1754
1755 /*
1756  */
1757
1758 static int
1759 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1760 {
1761         int i;
1762         struct m3_dma *s;
1763
1764         spin_lock_irq(&chip->reg_lock);
1765         for (i = 0; i < chip->num_substreams; i++) {
1766                 s = &chip->substreams[i];
1767                 if (! s->opened)
1768                         goto __found;
1769         }
1770         spin_unlock_irq(&chip->reg_lock);
1771         return -ENOMEM;
1772 __found:
1773         s->opened = 1;
1774         s->running = 0;
1775         spin_unlock_irq(&chip->reg_lock);
1776
1777         subs->runtime->private_data = s;
1778         s->substream = subs;
1779
1780         /* set list owners */
1781         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1782                 s->index_list[0] = &chip->mixer_list;
1783         } else
1784                 s->index_list[0] = &chip->adc1_list;
1785         s->index_list[1] = &chip->msrc_list;
1786         s->index_list[2] = &chip->dma_list;
1787
1788         return 0;
1789 }
1790
1791 static void
1792 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1793 {
1794         struct m3_dma *s = subs->runtime->private_data;
1795
1796         if (s == NULL)
1797                 return; /* not opened properly */
1798
1799         spin_lock_irq(&chip->reg_lock);
1800         if (s->substream && s->running)
1801                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1802         if (s->in_lists) {
1803                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1804                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1805                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1806                 s->in_lists = 0;
1807         }
1808         s->running = 0;
1809         s->opened = 0;
1810         spin_unlock_irq(&chip->reg_lock);
1811 }
1812
1813 static int
1814 snd_m3_playback_open(struct snd_pcm_substream *subs)
1815 {
1816         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1817         struct snd_pcm_runtime *runtime = subs->runtime;
1818         int err;
1819
1820         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1821                 return err;
1822
1823         runtime->hw = snd_m3_playback;
1824
1825         return 0;
1826 }
1827
1828 static int
1829 snd_m3_playback_close(struct snd_pcm_substream *subs)
1830 {
1831         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1832
1833         snd_m3_substream_close(chip, subs);
1834         return 0;
1835 }
1836
1837 static int
1838 snd_m3_capture_open(struct snd_pcm_substream *subs)
1839 {
1840         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1841         struct snd_pcm_runtime *runtime = subs->runtime;
1842         int err;
1843
1844         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1845                 return err;
1846
1847         runtime->hw = snd_m3_capture;
1848
1849         return 0;
1850 }
1851
1852 static int
1853 snd_m3_capture_close(struct snd_pcm_substream *subs)
1854 {
1855         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1856
1857         snd_m3_substream_close(chip, subs);
1858         return 0;
1859 }
1860
1861 /*
1862  * create pcm instance
1863  */
1864
1865 static struct snd_pcm_ops snd_m3_playback_ops = {
1866         .open =         snd_m3_playback_open,
1867         .close =        snd_m3_playback_close,
1868         .ioctl =        snd_pcm_lib_ioctl,
1869         .hw_params =    snd_m3_pcm_hw_params,
1870         .hw_free =      snd_m3_pcm_hw_free,
1871         .prepare =      snd_m3_pcm_prepare,
1872         .trigger =      snd_m3_pcm_trigger,
1873         .pointer =      snd_m3_pcm_pointer,
1874 };
1875
1876 static struct snd_pcm_ops snd_m3_capture_ops = {
1877         .open =         snd_m3_capture_open,
1878         .close =        snd_m3_capture_close,
1879         .ioctl =        snd_pcm_lib_ioctl,
1880         .hw_params =    snd_m3_pcm_hw_params,
1881         .hw_free =      snd_m3_pcm_hw_free,
1882         .prepare =      snd_m3_pcm_prepare,
1883         .trigger =      snd_m3_pcm_trigger,
1884         .pointer =      snd_m3_pcm_pointer,
1885 };
1886
1887 static int __devinit
1888 snd_m3_pcm(struct snd_m3 * chip, int device)
1889 {
1890         struct snd_pcm *pcm;
1891         int err;
1892
1893         err = snd_pcm_new(chip->card, chip->card->driver, device,
1894                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1895         if (err < 0)
1896                 return err;
1897
1898         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1899         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1900
1901         pcm->private_data = chip;
1902         pcm->info_flags = 0;
1903         strcpy(pcm->name, chip->card->driver);
1904         chip->pcm = pcm;
1905
1906         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1907                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1908
1909         return 0;
1910 }
1911
1912
1913 /*
1914  * ac97 interface
1915  */
1916
1917 /*
1918  * Wait for the ac97 serial bus to be free.
1919  * return nonzero if the bus is still busy.
1920  */
1921 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1922 {
1923         int i = 10000;
1924
1925         do {
1926                 if (! (snd_m3_inb(chip, 0x30) & 1))
1927                         return 0;
1928                 cpu_relax();
1929         } while (i-- > 0);
1930
1931         snd_printk(KERN_ERR "ac97 serial bus busy\n");
1932         return 1;
1933 }
1934
1935 static unsigned short
1936 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1937 {
1938         struct snd_m3 *chip = ac97->private_data;
1939         unsigned long flags;
1940         unsigned short data = 0xffff;
1941
1942         if (snd_m3_ac97_wait(chip))
1943                 goto fail;
1944         spin_lock_irqsave(&chip->ac97_lock, flags);
1945         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1946         if (snd_m3_ac97_wait(chip))
1947                 goto fail_unlock;
1948         data = snd_m3_inw(chip, CODEC_DATA);
1949 fail_unlock:
1950         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1951 fail:
1952         return data;
1953 }
1954
1955 static void
1956 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1957 {
1958         struct snd_m3 *chip = ac97->private_data;
1959         unsigned long flags;
1960
1961         if (snd_m3_ac97_wait(chip))
1962                 return;
1963         spin_lock_irqsave(&chip->ac97_lock, flags);
1964         snd_m3_outw(chip, val, CODEC_DATA);
1965         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1966         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1967 }
1968
1969
1970 static void snd_m3_remote_codec_config(int io, int isremote)
1971 {
1972         isremote = isremote ? 1 : 0;
1973
1974         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1975              io + RING_BUS_CTRL_B);
1976         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1977              io + SDO_OUT_DEST_CTRL);
1978         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1979              io + SDO_IN_DEST_CTRL);
1980 }
1981
1982 /*
1983  * hack, returns non zero on err
1984  */
1985 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1986 {
1987         u16 ret;
1988
1989         if (snd_m3_ac97_wait(chip))
1990                 return 1;
1991
1992         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1993
1994         if (snd_m3_ac97_wait(chip))
1995                 return 1;
1996
1997         ret = snd_m3_inw(chip, 0x32);
1998
1999         return (ret == 0) || (ret == 0xffff);
2000 }
2001
2002 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2003 {
2004         u16 dir;
2005         int delay1 = 0, delay2 = 0, i;
2006         int io = chip->iobase;
2007
2008         if (chip->allegro_flag) {
2009                 /*
2010                  * the onboard codec on the allegro seems
2011                  * to want to wait a very long time before
2012                  * coming back to life
2013                  */
2014                 delay1 = 50;
2015                 delay2 = 800;
2016         } else {
2017                 /* maestro3 */
2018                 delay1 = 20;
2019                 delay2 = 500;
2020         }
2021
2022         for (i = 0; i < 5; i++) {
2023                 dir = inw(io + GPIO_DIRECTION);
2024                 if (!chip->irda_workaround)
2025                         dir |= 0x10; /* assuming pci bus master? */
2026
2027                 snd_m3_remote_codec_config(io, 0);
2028
2029                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2030                 udelay(20);
2031
2032                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2033                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2034                 outw(0, io + GPIO_DATA);
2035                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2036
2037                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2038
2039                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2040                 udelay(5);
2041                 /* ok, bring back the ac-link */
2042                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2043                 outw(~0, io + GPIO_MASK);
2044
2045                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2046
2047                 if (! snd_m3_try_read_vendor(chip))
2048                         break;
2049
2050                 delay1 += 10;
2051                 delay2 += 100;
2052
2053                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2054                            delay1, delay2);
2055         }
2056
2057 #if 0
2058         /* more gung-ho reset that doesn't
2059          * seem to work anywhere :)
2060          */
2061         tmp = inw(io + RING_BUS_CTRL_A);
2062         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2063         msleep(20);
2064         outw(tmp, io + RING_BUS_CTRL_A);
2065         msleep(50);
2066 #endif
2067 }
2068
2069 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2070 {
2071         struct snd_ac97_bus *pbus;
2072         struct snd_ac97_template ac97;
2073         struct snd_ctl_elem_id id;
2074         int err;
2075         static struct snd_ac97_bus_ops ops = {
2076                 .write = snd_m3_ac97_write,
2077                 .read = snd_m3_ac97_read,
2078         };
2079
2080         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2081                 return err;
2082
2083         memset(&ac97, 0, sizeof(ac97));
2084         ac97.private_data = chip;
2085         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2086                 return err;
2087
2088         /* seems ac97 PCM needs initialization.. hack hack.. */
2089         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2090         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2091         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2092
2093         memset(&id, 0, sizeof(id));
2094         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2095         strcpy(id.name, "Master Playback Switch");
2096         chip->master_switch = snd_ctl_find_id(chip->card, &id);
2097         memset(&id, 0, sizeof(id));
2098         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2099         strcpy(id.name, "Master Playback Volume");
2100         chip->master_volume = snd_ctl_find_id(chip->card, &id);
2101
2102         return 0;
2103 }
2104
2105
2106 #ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2107
2108 /*
2109  * DSP Code images
2110  */
2111
2112 static const u16 assp_kernel_image[] = {
2113     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2114     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2115     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2116     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2117     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2118     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2119     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2120     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2121     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2122     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2123     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2124     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2125     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2126     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2127     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2128     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2129     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2130     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2131     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2132     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2133     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2134     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2135     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2136     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2137     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2138     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2139     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2140     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2141     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2142     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2143     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2144     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2145     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2146     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2147     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2148     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2149     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2150     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2151     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2152     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2153     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2154     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2155     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2156     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2157     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2158     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2159     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2160     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2161     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2162     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2163     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2164     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2165     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2166     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2167     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2168     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2169     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2170     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2171     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2172     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2173     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2174     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2175     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2176     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2177     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2178     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2179     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2180     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2181     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2182     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2183     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2184     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2185     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2186     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2187     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2188     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2189     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2190     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2191     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2192     0xBE3A,
2193 };
2194
2195 /*
2196  * Mini sample rate converter code image
2197  * that is to be loaded at 0x400 on the DSP.
2198  */
2199 static const u16 assp_minisrc_image[] = {
2200
2201     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2202     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2203     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2204     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2205     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2206     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2207     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2208     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2209     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2210     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2211     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2212     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2213     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2214     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2215     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2216     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2217     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2218     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2219     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2220     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2221     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2222     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2223     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2224     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2225     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2226     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2227     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2228     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2229     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2230     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2231     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2232     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2233     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2234 };
2235
2236 static const struct firmware assp_kernel = {
2237         .data = (u8 *)assp_kernel_image,
2238         .size = sizeof assp_kernel_image
2239 };
2240 static const struct firmware assp_minisrc = {
2241         .data = (u8 *)assp_minisrc_image,
2242         .size = sizeof assp_minisrc_image
2243 };
2244
2245 #else /* CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL */
2246
2247 #ifdef __LITTLE_ENDIAN
2248 static inline void snd_m3_convert_from_le(const struct firmware *fw) { }
2249 #else
2250 static void snd_m3_convert_from_le(const struct firmware *fw)
2251 {
2252         int i;
2253         u16 *data = (u16 *)fw->data;
2254
2255         for (i = 0; i < fw->size / 2; ++i)
2256                 le16_to_cpus(&data[i]);
2257 }
2258 #endif
2259
2260 #endif /* CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL */
2261
2262
2263 /*
2264  * initialize ASSP
2265  */
2266
2267 #define MINISRC_LPF_LEN 10
2268 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2269         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2270         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2271 };
2272
2273 static void snd_m3_assp_init(struct snd_m3 *chip)
2274 {
2275         unsigned int i;
2276         u16 *data;
2277
2278         /* zero kernel data */
2279         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2280                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2281                                   KDATA_BASE_ADDR + i, 0);
2282
2283         /* zero mixer data? */
2284         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2285                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2286                                   KDATA_BASE_ADDR2 + i, 0);
2287
2288         /* init dma pointer */
2289         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2290                           KDATA_CURRENT_DMA,
2291                           KDATA_DMA_XFER0);
2292
2293         /* write kernel into code memory.. */
2294         data = (u16 *)chip->assp_kernel_image->data;
2295         for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2296                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2297                                   REV_B_CODE_MEMORY_BEGIN + i, data[i]);
2298         }
2299
2300         /*
2301          * We only have this one client and we know that 0x400
2302          * is free in our kernel's mem map, so lets just
2303          * drop it there.  It seems that the minisrc doesn't
2304          * need vectors, so we won't bother with them..
2305          */
2306         data = (u16 *)chip->assp_minisrc_image->data;
2307         for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2308                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2309                                   0x400 + i, data[i]);
2310         }
2311
2312         /*
2313          * write the coefficients for the low pass filter?
2314          */
2315         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2316                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2317                                   0x400 + MINISRC_COEF_LOC + i,
2318                                   minisrc_lpf[i]);
2319         }
2320
2321         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2322                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2323                           0x8000);
2324
2325         /*
2326          * the minisrc is the only thing on
2327          * our task list..
2328          */
2329         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2330                           KDATA_TASK0,
2331                           0x400);
2332
2333         /*
2334          * init the mixer number..
2335          */
2336
2337         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2338                           KDATA_MIXER_TASK_NUMBER,0);
2339
2340         /*
2341          * EXTREME KERNEL MASTER VOLUME
2342          */
2343         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2344                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2345         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2346                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2347
2348         chip->mixer_list.curlen = 0;
2349         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2350         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2351         chip->adc1_list.curlen = 0;
2352         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2353         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2354         chip->dma_list.curlen = 0;
2355         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2356         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2357         chip->msrc_list.curlen = 0;
2358         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2359         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2360 }
2361
2362
2363 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2364 {
2365         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2366                                MINISRC_IN_BUFFER_SIZE / 2 +
2367                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2368         int address, i;
2369
2370         /*
2371          * the revb memory map has 0x1100 through 0x1c00
2372          * free.
2373          */
2374
2375         /*
2376          * align instance address to 256 bytes so that its
2377          * shifted list address is aligned.
2378          * list address = (mem address >> 1) >> 7;
2379          */
2380         data_bytes = ALIGN(data_bytes, 256);
2381         address = 0x1100 + ((data_bytes/2) * index);
2382
2383         if ((address + (data_bytes/2)) >= 0x1c00) {
2384                 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2385                            data_bytes, index, address);
2386                 return -ENOMEM;
2387         }
2388
2389         s->number = index;
2390         s->inst.code = 0x400;
2391         s->inst.data = address;
2392
2393         for (i = data_bytes / 2; i > 0; address++, i--) {
2394                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2395                                   address, 0);
2396         }
2397
2398         return 0;
2399 }
2400
2401
2402 /*
2403  * this works for the reference board, have to find
2404  * out about others
2405  *
2406  * this needs more magic for 4 speaker, but..
2407  */
2408 static void
2409 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2410 {
2411         int io = chip->iobase;
2412         u16 gpo, polarity;
2413
2414         if (! chip->external_amp)
2415                 return;
2416
2417         polarity = enable ? 0 : 1;
2418         polarity = polarity << chip->amp_gpio;
2419         gpo = 1 << chip->amp_gpio;
2420
2421         outw(~gpo, io + GPIO_MASK);
2422
2423         outw(inw(io + GPIO_DIRECTION) | gpo,
2424              io + GPIO_DIRECTION);
2425
2426         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2427              io + GPIO_DATA);
2428
2429         outw(0xffff, io + GPIO_MASK);
2430 }
2431
2432 static int
2433 snd_m3_chip_init(struct snd_m3 *chip)
2434 {
2435         struct pci_dev *pcidev = chip->pci;
2436         unsigned long io = chip->iobase;
2437         u32 n;
2438         u16 w;
2439         u8 t; /* makes as much sense as 'n', no? */
2440
2441         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2442         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2443                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2444                DISABLE_LEGACY);
2445         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2446
2447         if (chip->is_omnibook) {
2448                 /*
2449                  * Volume buttons on some HP OmniBook laptops don't work
2450                  * correctly. This makes them work for the most part.
2451                  *
2452                  * Volume up and down buttons on the laptop side work.
2453                  * Fn+cursor_up (volme up) works.
2454                  * Fn+cursor_down (volume down) doesn't work.
2455                  * Fn+F7 (mute) works acts as volume up.
2456                  */
2457                 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK);
2458                 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION);
2459                 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA);
2460                 outw(0xffff, io + GPIO_MASK);
2461         }
2462         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2463         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2464         n |= chip->hv_config;
2465         /* For some reason we must always use reduced debounce. */
2466         n |= REDUCED_DEBOUNCE;
2467         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2468         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2469
2470         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2471         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2472         n &= ~INT_CLK_SELECT;
2473         if (!chip->allegro_flag) {
2474                 n &= ~INT_CLK_MULT_ENABLE;
2475                 n |= INT_CLK_SRC_NOT_PCI;
2476         }
2477         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2478         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2479
2480         if (chip->allegro_flag) {
2481                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2482                 n |= IN_CLK_12MHZ_SELECT;
2483                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2484         }
2485
2486         t = inb(chip->iobase + ASSP_CONTROL_A);
2487         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2488         t |= ASSP_CLK_49MHZ_SELECT;
2489         t |= ASSP_0_WS_ENABLE;
2490         outb(t, chip->iobase + ASSP_CONTROL_A);
2491
2492         snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2493         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2494
2495         outb(0x00, io + HARDWARE_VOL_CTRL);
2496         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2497         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2498         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2499         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2500
2501         return 0;
2502 }
2503
2504 static void
2505 snd_m3_enable_ints(struct snd_m3 *chip)
2506 {
2507         unsigned long io = chip->iobase;
2508         unsigned short val;
2509
2510         /* TODO: MPU401 not supported yet */
2511         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2512         if (chip->hv_config & HV_CTRL_ENABLE)
2513                 val |= HV_INT_ENABLE;
2514         outw(val, io + HOST_INT_CTRL);
2515         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2516              io + ASSP_CONTROL_C);
2517 }
2518
2519
2520 /*
2521  */
2522
2523 static int snd_m3_free(struct snd_m3 *chip)
2524 {
2525         struct m3_dma *s;
2526         int i;
2527
2528         if (chip->substreams) {
2529                 spin_lock_irq(&chip->reg_lock);
2530                 for (i = 0; i < chip->num_substreams; i++) {
2531                         s = &chip->substreams[i];
2532                         /* check surviving pcms; this should not happen though.. */
2533                         if (s->substream && s->running)
2534                                 snd_m3_pcm_stop(chip, s, s->substream);
2535                 }
2536                 spin_unlock_irq(&chip->reg_lock);
2537                 kfree(chip->substreams);
2538         }
2539         if (chip->iobase) {
2540                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2541         }
2542
2543 #ifdef CONFIG_PM
2544         vfree(chip->suspend_mem);
2545 #endif
2546
2547         if (chip->irq >= 0) {
2548                 synchronize_irq(chip->irq);
2549                 free_irq(chip->irq, chip);
2550         }
2551
2552         if (chip->iobase)
2553                 pci_release_regions(chip->pci);
2554
2555 #ifndef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2556         release_firmware(chip->assp_kernel_image);
2557         release_firmware(chip->assp_minisrc_image);
2558 #endif
2559
2560         pci_disable_device(chip->pci);
2561         kfree(chip);
2562         return 0;
2563 }
2564
2565
2566 /*
2567  * APM support
2568  */
2569 #ifdef CONFIG_PM
2570 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2571 {
2572         struct snd_card *card = pci_get_drvdata(pci);
2573         struct snd_m3 *chip = card->private_data;
2574         int i, index;
2575
2576         if (chip->suspend_mem == NULL)
2577                 return 0;
2578
2579         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2580         snd_pcm_suspend_all(chip->pcm);
2581         snd_ac97_suspend(chip->ac97);
2582
2583         msleep(10); /* give the assp a chance to idle.. */
2584
2585         snd_m3_assp_halt(chip);
2586
2587         /* save dsp image */
2588         index = 0;
2589         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2590                 chip->suspend_mem[index++] =
2591                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2592         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2593                 chip->suspend_mem[index++] =
2594                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2595
2596         pci_disable_device(pci);
2597         pci_save_state(pci);
2598         pci_set_power_state(pci, pci_choose_state(pci, state));
2599         return 0;
2600 }
2601
2602 static int m3_resume(struct pci_dev *pci)
2603 {
2604         struct snd_card *card = pci_get_drvdata(pci);
2605         struct snd_m3 *chip = card->private_data;
2606         int i, index;
2607
2608         if (chip->suspend_mem == NULL)
2609                 return 0;
2610
2611         pci_set_power_state(pci, PCI_D0);
2612         pci_restore_state(pci);
2613         if (pci_enable_device(pci) < 0) {
2614                 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2615                        "disabling device\n");
2616                 snd_card_disconnect(card);
2617                 return -EIO;
2618         }
2619         pci_set_master(pci);
2620
2621         /* first lets just bring everything back. .*/
2622         snd_m3_outw(chip, 0, 0x54);
2623         snd_m3_outw(chip, 0, 0x56);
2624
2625         snd_m3_chip_init(chip);
2626         snd_m3_assp_halt(chip);
2627         snd_m3_ac97_reset(chip);
2628
2629         /* restore dsp image */
2630         index = 0;
2631         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2632                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2633                                   chip->suspend_mem[index++]);
2634         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2635                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2636                                   chip->suspend_mem[index++]);
2637
2638         /* tell the dma engine to restart itself */
2639         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2640                           KDATA_DMA_ACTIVE, 0);
2641
2642         /* restore ac97 registers */
2643         snd_ac97_resume(chip->ac97);
2644
2645         snd_m3_assp_continue(chip);
2646         snd_m3_enable_ints(chip);
2647         snd_m3_amp_enable(chip, 1);
2648
2649         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2650         return 0;
2651 }
2652 #endif /* CONFIG_PM */
2653
2654
2655 /*
2656  */
2657
2658 static int snd_m3_dev_free(struct snd_device *device)
2659 {
2660         struct snd_m3 *chip = device->device_data;
2661         return snd_m3_free(chip);
2662 }
2663
2664 static int __devinit
2665 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2666               int enable_amp,
2667               int amp_gpio,
2668               struct snd_m3 **chip_ret)
2669 {
2670         struct snd_m3 *chip;
2671         int i, err;
2672         const struct snd_pci_quirk *quirk;
2673         static struct snd_device_ops ops = {
2674                 .dev_free =     snd_m3_dev_free,
2675         };
2676
2677         *chip_ret = NULL;
2678
2679         if (pci_enable_device(pci))
2680                 return -EIO;
2681
2682         /* check, if we can restrict PCI DMA transfers to 28 bits */
2683         if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2684             pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2685                 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2686                 pci_disable_device(pci);
2687                 return -ENXIO;
2688         }
2689
2690         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2691         if (chip == NULL) {
2692                 pci_disable_device(pci);
2693                 return -ENOMEM;
2694         }
2695
2696         spin_lock_init(&chip->reg_lock);
2697         spin_lock_init(&chip->ac97_lock);
2698
2699         switch (pci->device) {
2700         case PCI_DEVICE_ID_ESS_ALLEGRO:
2701         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2702         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2703         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2704                 chip->allegro_flag = 1;
2705                 break;
2706         }
2707
2708         chip->card = card;
2709         chip->pci = pci;
2710         chip->irq = -1;
2711
2712         chip->external_amp = enable_amp;
2713         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2714                 chip->amp_gpio = amp_gpio;
2715         else {
2716                 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2717                 if (quirk) {
2718                         snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2719                                     "for '%s'\n", quirk->name);
2720                         chip->amp_gpio = quirk->value;
2721                 } else if (chip->allegro_flag)
2722                         chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2723                 else /* presumably this is for all 'maestro3's.. */
2724                         chip->amp_gpio = GPO_EXT_AMP_M3;
2725         }
2726
2727         quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2728         if (quirk) {
2729                 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2730                             "for '%s'\n", quirk->name);
2731                 chip->irda_workaround = 1;
2732         }
2733         quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2734         if (quirk)
2735                 chip->hv_config = quirk->value;
2736         if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2737                 chip->is_omnibook = 1;
2738
2739         chip->num_substreams = NR_DSPS;
2740         chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2741                                    GFP_KERNEL);
2742         if (chip->substreams == NULL) {
2743                 kfree(chip);
2744                 pci_disable_device(pci);
2745                 return -ENOMEM;
2746         }
2747
2748 #ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2749         chip->assp_kernel_image = &assp_kernel;
2750 #else
2751         err = request_firmware(&chip->assp_kernel_image,
2752                                "ess/maestro3_assp_kernel.fw", &pci->dev);
2753         if (err < 0) {
2754                 snd_m3_free(chip);
2755                 return err;
2756         } else
2757                 snd_m3_convert_from_le(chip->assp_kernel_image);
2758 #endif
2759
2760 #ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2761         chip->assp_minisrc_image = &assp_minisrc;
2762 #else
2763         err = request_firmware(&chip->assp_minisrc_image,
2764                                "ess/maestro3_assp_minisrc.fw", &pci->dev);
2765         if (err < 0) {
2766                 snd_m3_free(chip);
2767                 return err;
2768         } else
2769                 snd_m3_convert_from_le(chip->assp_minisrc_image);
2770 #endif
2771
2772         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2773                 snd_m3_free(chip);
2774                 return err;
2775         }
2776         chip->iobase = pci_resource_start(pci, 0);
2777
2778         /* just to be sure */
2779         pci_set_master(pci);
2780
2781         snd_m3_chip_init(chip);
2782         snd_m3_assp_halt(chip);
2783
2784         snd_m3_ac97_reset(chip);
2785
2786         snd_m3_amp_enable(chip, 1);
2787
2788         tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2789
2790         if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2791                         card->driver, chip)) {
2792                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2793                 snd_m3_free(chip);
2794                 return -ENOMEM;
2795         }
2796         chip->irq = pci->irq;
2797
2798 #ifdef CONFIG_PM
2799         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2800         if (chip->suspend_mem == NULL)
2801                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2802 #endif
2803
2804         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2805                 snd_m3_free(chip);
2806                 return err;
2807         }
2808
2809         if ((err = snd_m3_mixer(chip)) < 0)
2810                 return err;
2811
2812         for (i = 0; i < chip->num_substreams; i++) {
2813                 struct m3_dma *s = &chip->substreams[i];
2814                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2815                         return err;
2816         }
2817
2818         if ((err = snd_m3_pcm(chip, 0)) < 0)
2819                 return err;
2820
2821         snd_m3_enable_ints(chip);
2822         snd_m3_assp_continue(chip);
2823
2824         snd_card_set_dev(card, &pci->dev);
2825
2826         *chip_ret = chip;
2827
2828         return 0;
2829 }
2830
2831 /*
2832  */
2833 static int __devinit
2834 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2835 {
2836         static int dev;
2837         struct snd_card *card;
2838         struct snd_m3 *chip;
2839         int err;
2840
2841         /* don't pick up modems */
2842         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2843                 return -ENODEV;
2844
2845         if (dev >= SNDRV_CARDS)
2846                 return -ENODEV;
2847         if (!enable[dev]) {
2848                 dev++;
2849                 return -ENOENT;
2850         }
2851
2852         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2853         if (card == NULL)
2854                 return -ENOMEM;
2855
2856         switch (pci->device) {
2857         case PCI_DEVICE_ID_ESS_ALLEGRO:
2858         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2859                 strcpy(card->driver, "Allegro");
2860                 break;
2861         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2862         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2863                 strcpy(card->driver, "Canyon3D-2");
2864                 break;
2865         default:
2866                 strcpy(card->driver, "Maestro3");
2867                 break;
2868         }
2869
2870         if ((err = snd_m3_create(card, pci,
2871                                  external_amp[dev],
2872                                  amp_gpio[dev],
2873                                  &chip)) < 0) {
2874                 snd_card_free(card);
2875                 return err;
2876         }
2877         card->private_data = chip;
2878
2879         sprintf(card->shortname, "ESS %s PCI", card->driver);
2880         sprintf(card->longname, "%s at 0x%lx, irq %d",
2881                 card->shortname, chip->iobase, chip->irq);
2882
2883         if ((err = snd_card_register(card)) < 0) {
2884                 snd_card_free(card);
2885                 return err;
2886         }
2887
2888 #if 0 /* TODO: not supported yet */
2889         /* TODO enable MIDI IRQ and I/O */
2890         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2891                                   chip->iobase + MPU401_DATA_PORT,
2892                                   MPU401_INFO_INTEGRATED,
2893                                   chip->irq, 0, &chip->rmidi);
2894         if (err < 0)
2895                 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2896 #endif
2897
2898         pci_set_drvdata(pci, card);
2899         dev++;
2900         return 0;
2901 }
2902
2903 static void __devexit snd_m3_remove(struct pci_dev *pci)
2904 {
2905         snd_card_free(pci_get_drvdata(pci));
2906         pci_set_drvdata(pci, NULL);
2907 }
2908
2909 static struct pci_driver driver = {
2910         .name = "Maestro3",
2911         .id_table = snd_m3_ids,
2912         .probe = snd_m3_probe,
2913         .remove = __devexit_p(snd_m3_remove),
2914 #ifdef CONFIG_PM
2915         .suspend = m3_suspend,
2916         .resume = m3_resume,
2917 #endif
2918 };
2919
2920 static int __init alsa_card_m3_init(void)
2921 {
2922         return pci_register_driver(&driver);
2923 }
2924
2925 static void __exit alsa_card_m3_exit(void)
2926 {
2927         pci_unregister_driver(&driver);
2928 }
2929
2930 module_init(alsa_card_m3_init)
2931 module_exit(alsa_card_m3_exit)