3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include <sound/hda_chmap.h>
43 #include "hda_codec.h"
44 #include "hda_local.h"
47 static bool static_hdmi_pcm;
48 module_param(static_hdmi_pcm, bool, 0644);
49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
51 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
56 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
57 ((codec)->core.vendor_id == 0x80862800))
58 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
59 || is_skylake(codec) || is_broxton(codec) \
60 || is_kabylake(codec)) || is_geminilake(codec)
62 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
63 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
64 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
66 struct hdmi_spec_per_cvt {
69 unsigned int channels_min;
70 unsigned int channels_max;
76 /* max. connections to a widget */
77 #define HDA_MAX_CONNECTIONS 32
79 struct hdmi_spec_per_pin {
82 /* pin idx, different device entries on the same pin use the same idx */
85 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
89 struct hda_codec *codec;
90 struct hdmi_eld sink_eld;
92 struct delayed_work work;
93 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
94 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
96 bool setup; /* the stream has been set up by prepare callback */
97 int channels; /* current number of channels */
99 bool chmap_set; /* channel-map override by ALSA API? */
100 unsigned char chmap[8]; /* ALSA API channel-map */
101 #ifdef CONFIG_SND_PROC_FS
102 struct snd_info_entry *proc_entry;
106 /* operations used by generic code that can be overridden by patches */
108 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
109 unsigned char *buf, int *eld_size);
111 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
112 int ca, int active_channels, int conn_type);
114 /* enable/disable HBR (HD passthrough) */
115 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
117 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
118 hda_nid_t pin_nid, u32 stream_tag, int format);
120 void (*pin_cvt_fixup)(struct hda_codec *codec,
121 struct hdmi_spec_per_pin *per_pin,
127 struct snd_jack *jack;
128 struct snd_kcontrol *eld_ctl;
133 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
134 hda_nid_t cvt_nids[4]; /* only for haswell fix */
137 * num_pins is the number of virtual pins
138 * for example, there are 3 pins, and each pin
139 * has 4 device entries, then the num_pins is 12
143 * num_nids is the number of real pins
144 * In the above example, num_nids is 3
148 * dev_num is the number of device entries
150 * In the above example, dev_num is 4
153 struct snd_array pins; /* struct hdmi_spec_per_pin */
154 struct hdmi_pcm pcm_rec[16];
155 struct mutex pcm_lock;
156 /* pcm_bitmap means which pcms have been assigned to pins*/
157 unsigned long pcm_bitmap;
158 int pcm_used; /* counter of pcm_rec[] */
159 /* bitmap shows whether the pcm is opened in user space
160 * bit 0 means the first playback PCM (PCM3);
161 * bit 1 means the second playback PCM, and so on.
163 unsigned long pcm_in_use;
165 struct hdmi_eld temp_eld;
171 * Non-generic VIA/NVIDIA specific
173 struct hda_multi_out multiout;
174 struct hda_pcm_stream pcm_playback;
176 /* i915/powerwell (Haswell+/Valleyview+) specific */
177 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
178 struct i915_audio_component_audio_ops i915_audio_ops;
180 struct hdac_chmap chmap;
181 hda_nid_t vendor_nid;
184 #ifdef CONFIG_SND_HDA_I915
185 static inline bool codec_has_acomp(struct hda_codec *codec)
187 struct hdmi_spec *spec = codec->spec;
188 return spec->use_acomp_notifier;
191 #define codec_has_acomp(codec) false
194 struct hdmi_audio_infoframe {
201 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
205 u8 LFEPBL01_LSV36_DM_INH7;
208 struct dp_audio_infoframe {
211 u8 ver; /* 0x11 << 2 */
213 u8 CC02_CT47; /* match with HDMI infoframe from this on */
217 u8 LFEPBL01_LSV36_DM_INH7;
220 union audio_infoframe {
221 struct hdmi_audio_infoframe hdmi;
222 struct dp_audio_infoframe dp;
230 #define get_pin(spec, idx) \
231 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
232 #define get_cvt(spec, idx) \
233 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
234 /* obtain hdmi_pcm object assigned to idx */
235 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
236 /* obtain hda_pcm object assigned to idx */
237 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
239 static int pin_id_to_pin_index(struct hda_codec *codec,
240 hda_nid_t pin_nid, int dev_id)
242 struct hdmi_spec *spec = codec->spec;
244 struct hdmi_spec_per_pin *per_pin;
247 * (dev_id == -1) means it is NON-MST pin
248 * return the first virtual pin on this port
253 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
254 per_pin = get_pin(spec, pin_idx);
255 if ((per_pin->pin_nid == pin_nid) &&
256 (per_pin->dev_id == dev_id))
260 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
264 static int hinfo_to_pcm_index(struct hda_codec *codec,
265 struct hda_pcm_stream *hinfo)
267 struct hdmi_spec *spec = codec->spec;
270 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
271 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
274 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
278 static int hinfo_to_pin_index(struct hda_codec *codec,
279 struct hda_pcm_stream *hinfo)
281 struct hdmi_spec *spec = codec->spec;
282 struct hdmi_spec_per_pin *per_pin;
285 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
286 per_pin = get_pin(spec, pin_idx);
288 per_pin->pcm->pcm->stream == hinfo)
292 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
296 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
300 struct hdmi_spec_per_pin *per_pin;
302 for (i = 0; i < spec->num_pins; i++) {
303 per_pin = get_pin(spec, i);
304 if (per_pin->pcm_idx == pcm_idx)
310 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
312 struct hdmi_spec *spec = codec->spec;
315 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
316 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
319 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
323 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
324 struct snd_ctl_elem_info *uinfo)
326 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
327 struct hdmi_spec *spec = codec->spec;
328 struct hdmi_spec_per_pin *per_pin;
329 struct hdmi_eld *eld;
332 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
334 pcm_idx = kcontrol->private_value;
335 mutex_lock(&spec->pcm_lock);
336 per_pin = pcm_idx_to_pin(spec, pcm_idx);
338 /* no pin is bound to the pcm */
340 mutex_unlock(&spec->pcm_lock);
343 eld = &per_pin->sink_eld;
344 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
345 mutex_unlock(&spec->pcm_lock);
350 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
351 struct snd_ctl_elem_value *ucontrol)
353 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
354 struct hdmi_spec *spec = codec->spec;
355 struct hdmi_spec_per_pin *per_pin;
356 struct hdmi_eld *eld;
359 pcm_idx = kcontrol->private_value;
360 mutex_lock(&spec->pcm_lock);
361 per_pin = pcm_idx_to_pin(spec, pcm_idx);
363 /* no pin is bound to the pcm */
364 memset(ucontrol->value.bytes.data, 0,
365 ARRAY_SIZE(ucontrol->value.bytes.data));
366 mutex_unlock(&spec->pcm_lock);
369 eld = &per_pin->sink_eld;
371 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
372 eld->eld_size > ELD_MAX_SIZE) {
373 mutex_unlock(&spec->pcm_lock);
378 memset(ucontrol->value.bytes.data, 0,
379 ARRAY_SIZE(ucontrol->value.bytes.data));
381 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
383 mutex_unlock(&spec->pcm_lock);
388 static const struct snd_kcontrol_new eld_bytes_ctl = {
389 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
390 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
392 .info = hdmi_eld_ctl_info,
393 .get = hdmi_eld_ctl_get,
396 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
399 struct snd_kcontrol *kctl;
400 struct hdmi_spec *spec = codec->spec;
403 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
406 kctl->private_value = pcm_idx;
407 kctl->id.device = device;
409 /* no pin nid is associated with the kctl now
410 * tbd: associate pin nid to eld ctl later
412 err = snd_hda_ctl_add(codec, 0, kctl);
416 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
421 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
422 int *packet_index, int *byte_index)
426 val = snd_hda_codec_read(codec, pin_nid, 0,
427 AC_VERB_GET_HDMI_DIP_INDEX, 0);
429 *packet_index = val >> 5;
430 *byte_index = val & 0x1f;
434 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
435 int packet_index, int byte_index)
439 val = (packet_index << 5) | (byte_index & 0x1f);
441 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
444 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
447 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
450 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
452 struct hdmi_spec *spec = codec->spec;
456 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
457 snd_hda_codec_write(codec, pin_nid, 0,
458 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
460 if (spec->dyn_pin_out)
461 /* Disable pin out until stream is active */
464 /* Enable pin out: some machines with GM965 gets broken output
465 * when the pin is disabled or changed while using with HDMI
469 snd_hda_codec_write(codec, pin_nid, 0,
470 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
477 #ifdef CONFIG_SND_PROC_FS
478 static void print_eld_info(struct snd_info_entry *entry,
479 struct snd_info_buffer *buffer)
481 struct hdmi_spec_per_pin *per_pin = entry->private_data;
483 mutex_lock(&per_pin->lock);
484 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
485 mutex_unlock(&per_pin->lock);
488 static void write_eld_info(struct snd_info_entry *entry,
489 struct snd_info_buffer *buffer)
491 struct hdmi_spec_per_pin *per_pin = entry->private_data;
493 mutex_lock(&per_pin->lock);
494 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
495 mutex_unlock(&per_pin->lock);
498 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
501 struct hda_codec *codec = per_pin->codec;
502 struct snd_info_entry *entry;
505 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
506 err = snd_card_proc_new(codec->card, name, &entry);
510 snd_info_set_text_ops(entry, per_pin, print_eld_info);
511 entry->c.text.write = write_eld_info;
512 entry->mode |= S_IWUSR;
513 per_pin->proc_entry = entry;
518 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
520 if (!per_pin->codec->bus->shutdown) {
521 snd_info_free_entry(per_pin->proc_entry);
522 per_pin->proc_entry = NULL;
526 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
531 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
537 * Audio InfoFrame routines
541 * Enable Audio InfoFrame Transmission
543 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
546 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
547 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
552 * Disable Audio InfoFrame Transmission
554 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
557 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
558 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
562 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
564 #ifdef CONFIG_SND_DEBUG_VERBOSE
568 size = snd_hdmi_get_eld_size(codec, pin_nid);
569 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
571 for (i = 0; i < 8; i++) {
572 size = snd_hda_codec_read(codec, pin_nid, 0,
573 AC_VERB_GET_HDMI_DIP_SIZE, i);
574 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
579 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
585 for (i = 0; i < 8; i++) {
586 size = snd_hda_codec_read(codec, pin_nid, 0,
587 AC_VERB_GET_HDMI_DIP_SIZE, i);
591 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
592 for (j = 1; j < 1000; j++) {
593 hdmi_write_dip_byte(codec, pin_nid, 0x0);
594 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
596 codec_dbg(codec, "dip index %d: %d != %d\n",
598 if (bi == 0) /* byte index wrapped around */
602 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
608 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
610 u8 *bytes = (u8 *)hdmi_ai;
614 hdmi_ai->checksum = 0;
616 for (i = 0; i < sizeof(*hdmi_ai); i++)
619 hdmi_ai->checksum = -sum;
622 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
628 hdmi_debug_dip_size(codec, pin_nid);
629 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
631 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
632 for (i = 0; i < size; i++)
633 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
636 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
642 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
646 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
647 for (i = 0; i < size; i++) {
648 val = snd_hda_codec_read(codec, pin_nid, 0,
649 AC_VERB_GET_HDMI_DIP_DATA, 0);
657 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
659 int ca, int active_channels,
662 union audio_infoframe ai;
664 memset(&ai, 0, sizeof(ai));
665 if (conn_type == 0) { /* HDMI */
666 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
668 hdmi_ai->type = 0x84;
671 hdmi_ai->CC02_CT47 = active_channels - 1;
673 hdmi_checksum_audio_infoframe(hdmi_ai);
674 } else if (conn_type == 1) { /* DisplayPort */
675 struct dp_audio_infoframe *dp_ai = &ai.dp;
679 dp_ai->ver = 0x11 << 2;
680 dp_ai->CC02_CT47 = active_channels - 1;
683 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
689 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
690 * sizeof(*dp_ai) to avoid partial match/update problems when
691 * the user switches between HDMI/DP monitors.
693 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
696 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
698 active_channels, ca);
699 hdmi_stop_infoframe_trans(codec, pin_nid);
700 hdmi_fill_audio_infoframe(codec, pin_nid,
701 ai.bytes, sizeof(ai));
702 hdmi_start_infoframe_trans(codec, pin_nid);
706 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
707 struct hdmi_spec_per_pin *per_pin,
710 struct hdmi_spec *spec = codec->spec;
711 struct hdac_chmap *chmap = &spec->chmap;
712 hda_nid_t pin_nid = per_pin->pin_nid;
713 int channels = per_pin->channels;
715 struct hdmi_eld *eld;
721 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
722 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
723 snd_hda_codec_write(codec, pin_nid, 0,
724 AC_VERB_SET_AMP_GAIN_MUTE,
727 eld = &per_pin->sink_eld;
729 ca = snd_hdac_channel_allocation(&codec->core,
730 eld->info.spk_alloc, channels,
731 per_pin->chmap_set, non_pcm, per_pin->chmap);
733 active_channels = snd_hdac_get_active_channels(ca);
735 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
739 * always configure channel mapping, it may have been changed by the
740 * user in the meantime
742 snd_hdac_setup_channel_mapping(&spec->chmap,
743 pin_nid, non_pcm, ca, channels,
744 per_pin->chmap, per_pin->chmap_set);
746 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
747 eld->info.conn_type);
749 per_pin->non_pcm = non_pcm;
756 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
758 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
761 struct hdmi_spec *spec = codec->spec;
762 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
766 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
767 snd_hda_jack_report_sync(codec);
770 static void jack_callback(struct hda_codec *codec,
771 struct hda_jack_callback *jack)
773 /* hda_jack don't support DP MST */
774 check_presence_and_report(codec, jack->nid, 0);
777 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
779 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
780 struct hda_jack_tbl *jack;
781 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
784 * assume DP MST uses dyn_pcm_assign and acomp and
786 * if DP MST supports unsol event, below code need
789 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
792 jack->jack_dirty = 1;
795 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
796 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
797 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
799 /* hda_jack don't support DP MST */
800 check_presence_and_report(codec, jack->nid, 0);
803 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
805 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
806 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
807 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
808 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
811 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
826 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
828 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
829 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
831 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
832 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
837 hdmi_intrinsic_event(codec, res);
839 hdmi_non_intrinsic_event(codec, res);
842 static void haswell_verify_D0(struct hda_codec *codec,
843 hda_nid_t cvt_nid, hda_nid_t nid)
847 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
848 * thus pins could only choose converter 0 for use. Make sure the
849 * converters are in correct power state */
850 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
851 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
853 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
854 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
857 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
858 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
859 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
867 /* HBR should be Non-PCM, 8 channels */
868 #define is_hbr_format(format) \
869 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
871 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
874 int pinctl, new_pinctl;
876 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
877 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
878 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
881 return hbr ? -EINVAL : 0;
883 new_pinctl = pinctl & ~AC_PINCTL_EPT;
885 new_pinctl |= AC_PINCTL_EPT_HBR;
887 new_pinctl |= AC_PINCTL_EPT_NATIVE;
890 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
892 pinctl == new_pinctl ? "" : "new-",
895 if (pinctl != new_pinctl)
896 snd_hda_codec_write(codec, pin_nid, 0,
897 AC_VERB_SET_PIN_WIDGET_CONTROL,
905 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
906 hda_nid_t pin_nid, u32 stream_tag, int format)
908 struct hdmi_spec *spec = codec->spec;
911 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
914 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
918 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
922 /* Try to find an available converter
923 * If pin_idx is less then zero, just try to find an available converter.
924 * Otherwise, try to find an available converter and get the cvt mux index
927 static int hdmi_choose_cvt(struct hda_codec *codec,
928 int pin_idx, int *cvt_id)
930 struct hdmi_spec *spec = codec->spec;
931 struct hdmi_spec_per_pin *per_pin;
932 struct hdmi_spec_per_cvt *per_cvt = NULL;
933 int cvt_idx, mux_idx = 0;
935 /* pin_idx < 0 means no pin will be bound to the converter */
939 per_pin = get_pin(spec, pin_idx);
941 /* Dynamically assign converter to stream */
942 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
943 per_cvt = get_cvt(spec, cvt_idx);
945 /* Must not already be assigned */
946 if (per_cvt->assigned)
950 /* Must be in pin's mux's list of converters */
951 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
952 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
954 /* Not in mux list */
955 if (mux_idx == per_pin->num_mux_nids)
960 /* No free converters */
961 if (cvt_idx == spec->num_cvts)
965 per_pin->mux_idx = mux_idx;
973 /* Assure the pin select the right convetor */
974 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
975 struct hdmi_spec_per_pin *per_pin)
977 hda_nid_t pin_nid = per_pin->pin_nid;
980 mux_idx = per_pin->mux_idx;
981 curr = snd_hda_codec_read(codec, pin_nid, 0,
982 AC_VERB_GET_CONNECT_SEL, 0);
984 snd_hda_codec_write_cache(codec, pin_nid, 0,
985 AC_VERB_SET_CONNECT_SEL,
989 /* get the mux index for the converter of the pins
990 * converter's mux index is the same for all pins on Intel platform
992 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
997 for (i = 0; i < spec->num_cvts; i++)
998 if (spec->cvt_nids[i] == cvt_nid)
1003 /* Intel HDMI workaround to fix audio routing issue:
1004 * For some Intel display codecs, pins share the same connection list.
1005 * So a conveter can be selected by multiple pins and playback on any of these
1006 * pins will generate sound on the external display, because audio flows from
1007 * the same converter to the display pipeline. Also muting one pin may make
1008 * other pins have no sound output.
1009 * So this function assures that an assigned converter for a pin is not selected
1010 * by any other pins.
1012 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1014 int dev_id, int mux_idx)
1016 struct hdmi_spec *spec = codec->spec;
1019 struct hdmi_spec_per_cvt *per_cvt;
1020 struct hdmi_spec_per_pin *per_pin;
1023 /* configure the pins connections */
1024 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1028 per_pin = get_pin(spec, pin_idx);
1030 * pin not connected to monitor
1031 * no need to operate on it
1036 if ((per_pin->pin_nid == pin_nid) &&
1037 (per_pin->dev_id == dev_id))
1041 * if per_pin->dev_id >= dev_num,
1042 * snd_hda_get_dev_select() will fail,
1043 * and the following operation is unpredictable.
1044 * So skip this situation.
1046 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1047 if (per_pin->dev_id >= dev_num)
1050 nid = per_pin->pin_nid;
1053 * Calling this function should not impact
1054 * on the device entry selection
1055 * So let's save the dev id for each pin,
1056 * and restore it when return
1058 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1059 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1060 curr = snd_hda_codec_read(codec, nid, 0,
1061 AC_VERB_GET_CONNECT_SEL, 0);
1062 if (curr != mux_idx) {
1063 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1068 /* choose an unassigned converter. The conveters in the
1069 * connection list are in the same order as in the codec.
1071 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1072 per_cvt = get_cvt(spec, cvt_idx);
1073 if (!per_cvt->assigned) {
1075 "choose cvt %d for pin nid %d\n",
1077 snd_hda_codec_write_cache(codec, nid, 0,
1078 AC_VERB_SET_CONNECT_SEL,
1083 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1087 /* A wrapper of intel_not_share_asigned_cvt() */
1088 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1089 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1092 struct hdmi_spec *spec = codec->spec;
1094 /* On Intel platform, the mapping of converter nid to
1095 * mux index of the pins are always the same.
1096 * The pin nid may be 0, this means all pins will not
1097 * share the converter.
1099 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1101 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1104 /* skeleton caller of pin_cvt_fixup ops */
1105 static void pin_cvt_fixup(struct hda_codec *codec,
1106 struct hdmi_spec_per_pin *per_pin,
1109 struct hdmi_spec *spec = codec->spec;
1111 if (spec->ops.pin_cvt_fixup)
1112 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1115 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1116 * in dyn_pcm_assign mode.
1118 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1119 struct hda_codec *codec,
1120 struct snd_pcm_substream *substream)
1122 struct hdmi_spec *spec = codec->spec;
1123 struct snd_pcm_runtime *runtime = substream->runtime;
1124 int cvt_idx, pcm_idx;
1125 struct hdmi_spec_per_cvt *per_cvt = NULL;
1128 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1132 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1136 per_cvt = get_cvt(spec, cvt_idx);
1137 per_cvt->assigned = 1;
1138 hinfo->nid = per_cvt->cvt_nid;
1140 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1142 set_bit(pcm_idx, &spec->pcm_in_use);
1143 /* todo: setup spdif ctls assign */
1145 /* Initially set the converter's capabilities */
1146 hinfo->channels_min = per_cvt->channels_min;
1147 hinfo->channels_max = per_cvt->channels_max;
1148 hinfo->rates = per_cvt->rates;
1149 hinfo->formats = per_cvt->formats;
1150 hinfo->maxbps = per_cvt->maxbps;
1152 /* Store the updated parameters */
1153 runtime->hw.channels_min = hinfo->channels_min;
1154 runtime->hw.channels_max = hinfo->channels_max;
1155 runtime->hw.formats = hinfo->formats;
1156 runtime->hw.rates = hinfo->rates;
1158 snd_pcm_hw_constraint_step(substream->runtime, 0,
1159 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1166 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1167 struct hda_codec *codec,
1168 struct snd_pcm_substream *substream)
1170 struct hdmi_spec *spec = codec->spec;
1171 struct snd_pcm_runtime *runtime = substream->runtime;
1172 int pin_idx, cvt_idx, pcm_idx;
1173 struct hdmi_spec_per_pin *per_pin;
1174 struct hdmi_eld *eld;
1175 struct hdmi_spec_per_cvt *per_cvt = NULL;
1178 /* Validate hinfo */
1179 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1183 mutex_lock(&spec->pcm_lock);
1184 pin_idx = hinfo_to_pin_index(codec, hinfo);
1185 if (!spec->dyn_pcm_assign) {
1186 if (snd_BUG_ON(pin_idx < 0)) {
1187 mutex_unlock(&spec->pcm_lock);
1191 /* no pin is assigned to the PCM
1192 * PA need pcm open successfully when probe
1195 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1196 mutex_unlock(&spec->pcm_lock);
1201 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1203 mutex_unlock(&spec->pcm_lock);
1207 per_cvt = get_cvt(spec, cvt_idx);
1208 /* Claim converter */
1209 per_cvt->assigned = 1;
1211 set_bit(pcm_idx, &spec->pcm_in_use);
1212 per_pin = get_pin(spec, pin_idx);
1213 per_pin->cvt_nid = per_cvt->cvt_nid;
1214 hinfo->nid = per_cvt->cvt_nid;
1216 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1217 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1218 AC_VERB_SET_CONNECT_SEL,
1221 /* configure unused pins to choose other converters */
1222 pin_cvt_fixup(codec, per_pin, 0);
1224 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1226 /* Initially set the converter's capabilities */
1227 hinfo->channels_min = per_cvt->channels_min;
1228 hinfo->channels_max = per_cvt->channels_max;
1229 hinfo->rates = per_cvt->rates;
1230 hinfo->formats = per_cvt->formats;
1231 hinfo->maxbps = per_cvt->maxbps;
1233 eld = &per_pin->sink_eld;
1234 /* Restrict capabilities by ELD if this isn't disabled */
1235 if (!static_hdmi_pcm && eld->eld_valid) {
1236 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1237 if (hinfo->channels_min > hinfo->channels_max ||
1238 !hinfo->rates || !hinfo->formats) {
1239 per_cvt->assigned = 0;
1241 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1242 mutex_unlock(&spec->pcm_lock);
1247 mutex_unlock(&spec->pcm_lock);
1248 /* Store the updated parameters */
1249 runtime->hw.channels_min = hinfo->channels_min;
1250 runtime->hw.channels_max = hinfo->channels_max;
1251 runtime->hw.formats = hinfo->formats;
1252 runtime->hw.rates = hinfo->rates;
1254 snd_pcm_hw_constraint_step(substream->runtime, 0,
1255 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1260 * HDA/HDMI auto parsing
1262 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1264 struct hdmi_spec *spec = codec->spec;
1265 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1266 hda_nid_t pin_nid = per_pin->pin_nid;
1268 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1270 "HDMI: pin %d wcaps %#x does not support connection list\n",
1271 pin_nid, get_wcaps(codec, pin_nid));
1275 /* all the device entries on the same pin have the same conn list */
1276 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1278 HDA_MAX_CONNECTIONS);
1283 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1284 struct hdmi_spec_per_pin *per_pin)
1288 /* try the prefer PCM */
1289 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1290 return per_pin->pin_nid_idx;
1292 /* have a second try; check the "reserved area" over num_pins */
1293 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1294 if (!test_bit(i, &spec->pcm_bitmap))
1298 /* the last try; check the empty slots in pins */
1299 for (i = 0; i < spec->num_nids; i++) {
1300 if (!test_bit(i, &spec->pcm_bitmap))
1306 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1307 struct hdmi_spec_per_pin *per_pin)
1311 /* pcm already be attached to the pin */
1314 idx = hdmi_find_pcm_slot(spec, per_pin);
1317 per_pin->pcm_idx = idx;
1318 per_pin->pcm = get_hdmi_pcm(spec, idx);
1319 set_bit(idx, &spec->pcm_bitmap);
1322 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1323 struct hdmi_spec_per_pin *per_pin)
1327 /* pcm already be detached from the pin */
1330 idx = per_pin->pcm_idx;
1331 per_pin->pcm_idx = -1;
1332 per_pin->pcm = NULL;
1333 if (idx >= 0 && idx < spec->pcm_used)
1334 clear_bit(idx, &spec->pcm_bitmap);
1337 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1338 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1342 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1343 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1348 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1350 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1351 struct hdmi_spec_per_pin *per_pin)
1353 struct hda_codec *codec = per_pin->codec;
1354 struct hda_pcm *pcm;
1355 struct hda_pcm_stream *hinfo;
1356 struct snd_pcm_substream *substream;
1360 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1361 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1364 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1367 /* hdmi audio only uses playback and one substream */
1368 hinfo = pcm->stream;
1369 substream = pcm->pcm->streams[0].substream;
1371 per_pin->cvt_nid = hinfo->nid;
1373 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1374 if (mux_idx < per_pin->num_mux_nids) {
1375 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1377 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1378 AC_VERB_SET_CONNECT_SEL,
1381 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1383 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1384 if (substream->runtime)
1385 per_pin->channels = substream->runtime->channels;
1386 per_pin->setup = true;
1387 per_pin->mux_idx = mux_idx;
1389 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1392 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1393 struct hdmi_spec_per_pin *per_pin)
1395 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1396 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1398 per_pin->chmap_set = false;
1399 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1401 per_pin->setup = false;
1402 per_pin->channels = 0;
1405 /* update per_pin ELD from the given new ELD;
1406 * setup info frame and notification accordingly
1408 static void update_eld(struct hda_codec *codec,
1409 struct hdmi_spec_per_pin *per_pin,
1410 struct hdmi_eld *eld)
1412 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1413 struct hdmi_spec *spec = codec->spec;
1414 bool old_eld_valid = pin_eld->eld_valid;
1418 /* for monitor disconnection, save pcm_idx firstly */
1419 pcm_idx = per_pin->pcm_idx;
1420 if (spec->dyn_pcm_assign) {
1421 if (eld->eld_valid) {
1422 hdmi_attach_hda_pcm(spec, per_pin);
1423 hdmi_pcm_setup_pin(spec, per_pin);
1425 hdmi_pcm_reset_pin(spec, per_pin);
1426 hdmi_detach_hda_pcm(spec, per_pin);
1429 /* if pcm_idx == -1, it means this is in monitor connection event
1430 * we can get the correct pcm_idx now.
1433 pcm_idx = per_pin->pcm_idx;
1436 snd_hdmi_show_eld(codec, &eld->info);
1438 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1439 if (eld->eld_valid && pin_eld->eld_valid)
1440 if (pin_eld->eld_size != eld->eld_size ||
1441 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1442 eld->eld_size) != 0)
1445 pin_eld->monitor_present = eld->monitor_present;
1446 pin_eld->eld_valid = eld->eld_valid;
1447 pin_eld->eld_size = eld->eld_size;
1449 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1450 pin_eld->info = eld->info;
1453 * Re-setup pin and infoframe. This is needed e.g. when
1454 * - sink is first plugged-in
1455 * - transcoder can change during stream playback on Haswell
1456 * and this can make HW reset converter selection on a pin.
1458 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1459 pin_cvt_fixup(codec, per_pin, 0);
1460 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1463 if (eld_changed && pcm_idx >= 0)
1464 snd_ctl_notify(codec->card,
1465 SNDRV_CTL_EVENT_MASK_VALUE |
1466 SNDRV_CTL_EVENT_MASK_INFO,
1467 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1470 /* update ELD and jack state via HD-audio verbs */
1471 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1474 struct hda_jack_tbl *jack;
1475 struct hda_codec *codec = per_pin->codec;
1476 struct hdmi_spec *spec = codec->spec;
1477 struct hdmi_eld *eld = &spec->temp_eld;
1478 hda_nid_t pin_nid = per_pin->pin_nid;
1480 * Always execute a GetPinSense verb here, even when called from
1481 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1482 * response's PD bit is not the real PD value, but indicates that
1483 * the real PD value changed. An older version of the HD-audio
1484 * specification worked this way. Hence, we just ignore the data in
1485 * the unsolicited response to avoid custom WARs.
1489 bool do_repoll = false;
1491 present = snd_hda_pin_sense(codec, pin_nid);
1493 mutex_lock(&per_pin->lock);
1494 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1495 if (eld->monitor_present)
1496 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1498 eld->eld_valid = false;
1501 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1502 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1504 if (eld->eld_valid) {
1505 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1506 &eld->eld_size) < 0)
1507 eld->eld_valid = false;
1509 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1511 eld->eld_valid = false;
1513 if (!eld->eld_valid && repoll)
1518 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1520 update_eld(codec, per_pin, eld);
1522 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1524 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1526 jack->block_report = !ret;
1528 mutex_unlock(&per_pin->lock);
1532 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1533 struct hdmi_spec_per_pin *per_pin)
1535 struct hdmi_spec *spec = codec->spec;
1536 struct snd_jack *jack = NULL;
1537 struct hda_jack_tbl *jack_tbl;
1539 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1540 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1541 * NULL even after snd_hda_jack_tbl_clear() is called to
1542 * free snd_jack. This may cause access invalid memory
1543 * when calling snd_jack_report
1545 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1546 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1547 else if (!spec->dyn_pcm_assign) {
1549 * jack tbl doesn't support DP MST
1550 * DP MST will use dyn_pcm_assign,
1551 * so DP MST will never come here
1553 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1555 jack = jack_tbl->jack;
1560 /* update ELD and jack state via audio component */
1561 static void sync_eld_via_acomp(struct hda_codec *codec,
1562 struct hdmi_spec_per_pin *per_pin)
1564 struct hdmi_spec *spec = codec->spec;
1565 struct hdmi_eld *eld = &spec->temp_eld;
1566 struct snd_jack *jack = NULL;
1569 mutex_lock(&per_pin->lock);
1570 eld->monitor_present = false;
1571 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1572 per_pin->dev_id, &eld->monitor_present,
1573 eld->eld_buffer, ELD_MAX_SIZE);
1575 size = min(size, ELD_MAX_SIZE);
1576 if (snd_hdmi_parse_eld(codec, &eld->info,
1577 eld->eld_buffer, size) < 0)
1582 eld->eld_valid = true;
1583 eld->eld_size = size;
1585 eld->eld_valid = false;
1589 /* pcm_idx >=0 before update_eld() means it is in monitor
1590 * disconnected event. Jack must be fetched before update_eld()
1592 jack = pin_idx_to_jack(codec, per_pin);
1593 update_eld(codec, per_pin, eld);
1595 jack = pin_idx_to_jack(codec, per_pin);
1598 snd_jack_report(jack,
1599 eld->monitor_present ? SND_JACK_AVOUT : 0);
1601 mutex_unlock(&per_pin->lock);
1604 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1606 struct hda_codec *codec = per_pin->codec;
1607 struct hdmi_spec *spec = codec->spec;
1610 /* no temporary power up/down needed for component notifier */
1611 if (!codec_has_acomp(codec))
1612 snd_hda_power_up_pm(codec);
1614 mutex_lock(&spec->pcm_lock);
1615 if (codec_has_acomp(codec)) {
1616 sync_eld_via_acomp(codec, per_pin);
1617 ret = false; /* don't call snd_hda_jack_report_sync() */
1619 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1621 mutex_unlock(&spec->pcm_lock);
1623 if (!codec_has_acomp(codec))
1624 snd_hda_power_down_pm(codec);
1629 static void hdmi_repoll_eld(struct work_struct *work)
1631 struct hdmi_spec_per_pin *per_pin =
1632 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1634 if (per_pin->repoll_count++ > 6)
1635 per_pin->repoll_count = 0;
1637 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1638 snd_hda_jack_report_sync(per_pin->codec);
1641 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1644 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1646 struct hdmi_spec *spec = codec->spec;
1647 unsigned int caps, config;
1649 struct hdmi_spec_per_pin *per_pin;
1653 caps = snd_hda_query_pin_caps(codec, pin_nid);
1654 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1658 * For DP MST audio, Configuration Default is the same for
1659 * all device entries on the same pin
1661 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1662 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1666 * To simplify the implementation, malloc all
1667 * the virtual pins in the initialization statically
1669 if (is_haswell_plus(codec)) {
1671 * On Intel platforms, device entries number is
1672 * changed dynamically. If there is a DP MST
1673 * hub connected, the device entries number is 3.
1674 * Otherwise, it is 1.
1675 * Here we manually set dev_num to 3, so that
1676 * we can initialize all the device entries when
1677 * bootup statically.
1681 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1682 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1684 * spec->dev_num is the maxinum number of device entries
1685 * among all the pins
1687 spec->dev_num = (spec->dev_num > dev_num) ?
1688 spec->dev_num : dev_num;
1691 * If the platform doesn't support DP MST,
1692 * manually set dev_num to 1. This means
1693 * the pin has only one device entry.
1699 for (i = 0; i < dev_num; i++) {
1700 pin_idx = spec->num_pins;
1701 per_pin = snd_array_new(&spec->pins);
1706 if (spec->dyn_pcm_assign) {
1707 per_pin->pcm = NULL;
1708 per_pin->pcm_idx = -1;
1710 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1711 per_pin->pcm_idx = pin_idx;
1713 per_pin->pin_nid = pin_nid;
1714 per_pin->pin_nid_idx = spec->num_nids;
1715 per_pin->dev_id = i;
1716 per_pin->non_pcm = false;
1717 snd_hda_set_dev_select(codec, pin_nid, i);
1718 if (is_haswell_plus(codec))
1719 intel_haswell_fixup_connect_list(codec, pin_nid);
1720 err = hdmi_read_pin_conn(codec, pin_idx);
1730 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1732 struct hdmi_spec *spec = codec->spec;
1733 struct hdmi_spec_per_cvt *per_cvt;
1737 chans = get_wcaps(codec, cvt_nid);
1738 chans = get_wcaps_channels(chans);
1740 per_cvt = snd_array_new(&spec->cvts);
1744 per_cvt->cvt_nid = cvt_nid;
1745 per_cvt->channels_min = 2;
1747 per_cvt->channels_max = chans;
1748 if (chans > spec->chmap.channels_max)
1749 spec->chmap.channels_max = chans;
1752 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1759 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1760 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1766 static int hdmi_parse_codec(struct hda_codec *codec)
1771 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1772 if (!nid || nodes < 0) {
1773 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1777 for (i = 0; i < nodes; i++, nid++) {
1781 caps = get_wcaps(codec, nid);
1782 type = get_wcaps_type(caps);
1784 if (!(caps & AC_WCAP_DIGITAL))
1788 case AC_WID_AUD_OUT:
1789 hdmi_add_cvt(codec, nid);
1792 hdmi_add_pin(codec, nid);
1802 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1804 struct hda_spdif_out *spdif;
1807 mutex_lock(&codec->spdif_mutex);
1808 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1809 /* Add sanity check to pass klockwork check.
1810 * This should never happen.
1812 if (WARN_ON(spdif == NULL))
1814 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1815 mutex_unlock(&codec->spdif_mutex);
1823 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1824 struct hda_codec *codec,
1825 unsigned int stream_tag,
1826 unsigned int format,
1827 struct snd_pcm_substream *substream)
1829 hda_nid_t cvt_nid = hinfo->nid;
1830 struct hdmi_spec *spec = codec->spec;
1832 struct hdmi_spec_per_pin *per_pin;
1834 struct snd_pcm_runtime *runtime = substream->runtime;
1839 mutex_lock(&spec->pcm_lock);
1840 pin_idx = hinfo_to_pin_index(codec, hinfo);
1841 if (spec->dyn_pcm_assign && pin_idx < 0) {
1842 /* when dyn_pcm_assign and pcm is not bound to a pin
1843 * skip pin setup and return 0 to make audio playback
1846 pin_cvt_fixup(codec, NULL, cvt_nid);
1847 snd_hda_codec_setup_stream(codec, cvt_nid,
1848 stream_tag, 0, format);
1849 mutex_unlock(&spec->pcm_lock);
1853 if (snd_BUG_ON(pin_idx < 0)) {
1854 mutex_unlock(&spec->pcm_lock);
1857 per_pin = get_pin(spec, pin_idx);
1858 pin_nid = per_pin->pin_nid;
1860 /* Verify pin:cvt selections to avoid silent audio after S3.
1861 * After S3, the audio driver restores pin:cvt selections
1862 * but this can happen before gfx is ready and such selection
1863 * is overlooked by HW. Thus multiple pins can share a same
1864 * default convertor and mute control will affect each other,
1865 * which can cause a resumed audio playback become silent
1868 pin_cvt_fixup(codec, per_pin, 0);
1870 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1871 /* Todo: add DP1.2 MST audio support later */
1872 if (codec_has_acomp(codec))
1873 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1876 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1877 mutex_lock(&per_pin->lock);
1878 per_pin->channels = substream->runtime->channels;
1879 per_pin->setup = true;
1881 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1882 mutex_unlock(&per_pin->lock);
1883 if (spec->dyn_pin_out) {
1884 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1885 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1886 snd_hda_codec_write(codec, pin_nid, 0,
1887 AC_VERB_SET_PIN_WIDGET_CONTROL,
1891 /* snd_hda_set_dev_select() has been called before */
1892 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1893 stream_tag, format);
1894 mutex_unlock(&spec->pcm_lock);
1898 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1899 struct hda_codec *codec,
1900 struct snd_pcm_substream *substream)
1902 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1906 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1907 struct hda_codec *codec,
1908 struct snd_pcm_substream *substream)
1910 struct hdmi_spec *spec = codec->spec;
1911 int cvt_idx, pin_idx, pcm_idx;
1912 struct hdmi_spec_per_cvt *per_cvt;
1913 struct hdmi_spec_per_pin *per_pin;
1917 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1918 if (snd_BUG_ON(pcm_idx < 0))
1920 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1921 if (snd_BUG_ON(cvt_idx < 0))
1923 per_cvt = get_cvt(spec, cvt_idx);
1925 snd_BUG_ON(!per_cvt->assigned);
1926 per_cvt->assigned = 0;
1929 mutex_lock(&spec->pcm_lock);
1930 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1931 clear_bit(pcm_idx, &spec->pcm_in_use);
1932 pin_idx = hinfo_to_pin_index(codec, hinfo);
1933 if (spec->dyn_pcm_assign && pin_idx < 0) {
1934 mutex_unlock(&spec->pcm_lock);
1938 if (snd_BUG_ON(pin_idx < 0)) {
1939 mutex_unlock(&spec->pcm_lock);
1942 per_pin = get_pin(spec, pin_idx);
1944 if (spec->dyn_pin_out) {
1945 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1946 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1947 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1948 AC_VERB_SET_PIN_WIDGET_CONTROL,
1952 mutex_lock(&per_pin->lock);
1953 per_pin->chmap_set = false;
1954 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1956 per_pin->setup = false;
1957 per_pin->channels = 0;
1958 mutex_unlock(&per_pin->lock);
1959 mutex_unlock(&spec->pcm_lock);
1965 static const struct hda_pcm_ops generic_ops = {
1966 .open = hdmi_pcm_open,
1967 .close = hdmi_pcm_close,
1968 .prepare = generic_hdmi_playback_pcm_prepare,
1969 .cleanup = generic_hdmi_playback_pcm_cleanup,
1972 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
1974 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1975 struct hdmi_spec *spec = codec->spec;
1976 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1981 return per_pin->sink_eld.info.spk_alloc;
1984 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
1985 unsigned char *chmap)
1987 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1988 struct hdmi_spec *spec = codec->spec;
1989 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1991 /* chmap is already set to 0 in caller */
1995 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
1998 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
1999 unsigned char *chmap, int prepared)
2001 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2002 struct hdmi_spec *spec = codec->spec;
2003 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2007 mutex_lock(&per_pin->lock);
2008 per_pin->chmap_set = true;
2009 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2011 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2012 mutex_unlock(&per_pin->lock);
2015 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2017 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2018 struct hdmi_spec *spec = codec->spec;
2019 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2021 return per_pin ? true:false;
2024 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2026 struct hdmi_spec *spec = codec->spec;
2030 * for non-mst mode, pcm number is the same as before
2031 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2032 * dev_num is the device entry number in a pin
2035 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2036 struct hda_pcm *info;
2037 struct hda_pcm_stream *pstr;
2039 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2043 spec->pcm_rec[idx].pcm = info;
2045 info->pcm_type = HDA_PCM_TYPE_HDMI;
2046 info->own_chmap = true;
2048 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2049 pstr->substreams = 1;
2050 pstr->ops = generic_ops;
2051 /* pcm number is less than 16 */
2052 if (spec->pcm_used >= 16)
2054 /* other pstr fields are set in open */
2060 static void free_hdmi_jack_priv(struct snd_jack *jack)
2062 struct hdmi_pcm *pcm = jack->private_data;
2067 static int add_hdmi_jack_kctl(struct hda_codec *codec,
2068 struct hdmi_spec *spec,
2072 struct snd_jack *jack;
2075 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2080 spec->pcm_rec[pcm_idx].jack = jack;
2081 jack->private_data = &spec->pcm_rec[pcm_idx];
2082 jack->private_free = free_hdmi_jack_priv;
2086 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2088 char hdmi_str[32] = "HDMI/DP";
2089 struct hdmi_spec *spec = codec->spec;
2090 struct hdmi_spec_per_pin *per_pin;
2091 struct hda_jack_tbl *jack;
2092 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2097 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2099 if (spec->dyn_pcm_assign)
2100 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2102 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2103 /* if !dyn_pcm_assign, it must be non-MST mode.
2104 * This means pcms and pins are statically mapped.
2105 * And pcm_idx is pin_idx.
2107 per_pin = get_pin(spec, pcm_idx);
2108 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2110 strncat(hdmi_str, " Phantom",
2111 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2112 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2116 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2119 /* assign jack->jack to pcm_rec[].jack to
2120 * align with dyn_pcm_assign mode
2122 spec->pcm_rec[pcm_idx].jack = jack->jack;
2126 static int generic_hdmi_build_controls(struct hda_codec *codec)
2128 struct hdmi_spec *spec = codec->spec;
2130 int pin_idx, pcm_idx;
2133 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2134 err = generic_hdmi_build_jack(codec, pcm_idx);
2138 /* create the spdif for each pcm
2139 * pin will be bound when monitor is connected
2141 if (spec->dyn_pcm_assign)
2142 err = snd_hda_create_dig_out_ctls(codec,
2143 0, spec->cvt_nids[0],
2146 struct hdmi_spec_per_pin *per_pin =
2147 get_pin(spec, pcm_idx);
2148 err = snd_hda_create_dig_out_ctls(codec,
2150 per_pin->mux_nids[0],
2155 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2157 dev = get_pcm_rec(spec, pcm_idx)->device;
2158 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2159 /* add control for ELD Bytes */
2160 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2166 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2167 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2169 hdmi_present_sense(per_pin, 0);
2172 /* add channel maps */
2173 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2174 struct hda_pcm *pcm;
2176 pcm = get_pcm_rec(spec, pcm_idx);
2177 if (!pcm || !pcm->pcm)
2179 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2187 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2189 struct hdmi_spec *spec = codec->spec;
2192 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2193 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2195 per_pin->codec = codec;
2196 mutex_init(&per_pin->lock);
2197 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2198 eld_proc_new(per_pin, pin_idx);
2203 static int generic_hdmi_init(struct hda_codec *codec)
2205 struct hdmi_spec *spec = codec->spec;
2208 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2209 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2210 hda_nid_t pin_nid = per_pin->pin_nid;
2211 int dev_id = per_pin->dev_id;
2213 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2214 hdmi_init_pin(codec, pin_nid);
2215 if (!codec_has_acomp(codec))
2216 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2217 codec->jackpoll_interval > 0 ?
2218 jack_callback : NULL);
2223 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2225 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2226 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2229 static void hdmi_array_free(struct hdmi_spec *spec)
2231 snd_array_free(&spec->pins);
2232 snd_array_free(&spec->cvts);
2235 static void generic_spec_free(struct hda_codec *codec)
2237 struct hdmi_spec *spec = codec->spec;
2240 hdmi_array_free(spec);
2244 codec->dp_mst = false;
2247 static void generic_hdmi_free(struct hda_codec *codec)
2249 struct hdmi_spec *spec = codec->spec;
2250 int pin_idx, pcm_idx;
2252 if (codec_has_acomp(codec))
2253 snd_hdac_i915_register_notifier(NULL);
2255 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2256 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2257 cancel_delayed_work_sync(&per_pin->work);
2258 eld_proc_free(per_pin);
2261 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2262 if (spec->pcm_rec[pcm_idx].jack == NULL)
2264 if (spec->dyn_pcm_assign)
2265 snd_device_free(codec->card,
2266 spec->pcm_rec[pcm_idx].jack);
2268 spec->pcm_rec[pcm_idx].jack = NULL;
2271 generic_spec_free(codec);
2275 static int generic_hdmi_resume(struct hda_codec *codec)
2277 struct hdmi_spec *spec = codec->spec;
2280 codec->patch_ops.init(codec);
2281 regcache_sync(codec->core.regmap);
2283 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2284 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2285 hdmi_present_sense(per_pin, 1);
2291 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2292 .init = generic_hdmi_init,
2293 .free = generic_hdmi_free,
2294 .build_pcms = generic_hdmi_build_pcms,
2295 .build_controls = generic_hdmi_build_controls,
2296 .unsol_event = hdmi_unsol_event,
2298 .resume = generic_hdmi_resume,
2302 static const struct hdmi_ops generic_standard_hdmi_ops = {
2303 .pin_get_eld = snd_hdmi_get_eld,
2304 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2305 .pin_hbr_setup = hdmi_pin_hbr_setup,
2306 .setup_stream = hdmi_setup_stream,
2309 /* allocate codec->spec and assign/initialize generic parser ops */
2310 static int alloc_generic_hdmi(struct hda_codec *codec)
2312 struct hdmi_spec *spec;
2314 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2318 spec->ops = generic_standard_hdmi_ops;
2319 spec->dev_num = 1; /* initialize to 1 */
2320 mutex_init(&spec->pcm_lock);
2321 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2323 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2324 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2325 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2326 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2329 hdmi_array_init(spec, 4);
2331 codec->patch_ops = generic_hdmi_patch_ops;
2336 /* generic HDMI parser */
2337 static int patch_generic_hdmi(struct hda_codec *codec)
2341 err = alloc_generic_hdmi(codec);
2345 err = hdmi_parse_codec(codec);
2347 generic_spec_free(codec);
2351 generic_hdmi_init_per_pins(codec);
2356 * Intel codec parsers and helpers
2359 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2362 struct hdmi_spec *spec = codec->spec;
2366 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2367 if (nconns == spec->num_cvts &&
2368 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2371 /* override pins connection list */
2372 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2373 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2376 #define INTEL_VENDOR_NID 0x08
2377 #define INTEL_GLK_VENDOR_NID 0x0B
2378 #define INTEL_GET_VENDOR_VERB 0xf81
2379 #define INTEL_SET_VENDOR_VERB 0x781
2380 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2381 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2383 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2386 unsigned int vendor_param;
2387 struct hdmi_spec *spec = codec->spec;
2389 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2390 INTEL_GET_VENDOR_VERB, 0);
2391 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2394 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2395 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2396 INTEL_SET_VENDOR_VERB, vendor_param);
2397 if (vendor_param == -1)
2401 snd_hda_codec_update_widgets(codec);
2404 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2406 unsigned int vendor_param;
2407 struct hdmi_spec *spec = codec->spec;
2409 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2410 INTEL_GET_VENDOR_VERB, 0);
2411 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2414 /* enable DP1.2 mode */
2415 vendor_param |= INTEL_EN_DP12;
2416 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2417 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2418 INTEL_SET_VENDOR_VERB, vendor_param);
2421 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2422 * Otherwise you may get severe h/w communication errors.
2424 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2425 unsigned int power_state)
2427 if (power_state == AC_PWRST_D0) {
2428 intel_haswell_enable_all_pins(codec, false);
2429 intel_haswell_fixup_enable_dp12(codec);
2432 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2433 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2436 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2438 struct hda_codec *codec = audio_ptr;
2442 /* we assume only from port-B to port-D */
2443 if (port < 1 || port > 3)
2446 switch (codec->core.vendor_id) {
2447 case 0x80860054: /* ILK */
2448 case 0x80862804: /* ILK */
2449 case 0x80862882: /* VLV */
2450 pin_nid = port + 0x03;
2453 pin_nid = port + 0x04;
2457 /* skip notification during system suspend (but not in runtime PM);
2458 * the state will be updated at resume
2460 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2462 /* ditto during suspend/resume process itself */
2463 if (atomic_read(&(codec)->core.in_pm))
2466 snd_hdac_i915_set_bclk(&codec->bus->core);
2467 check_presence_and_report(codec, pin_nid, dev_id);
2470 /* register i915 component pin_eld_notify callback */
2471 static void register_i915_notifier(struct hda_codec *codec)
2473 struct hdmi_spec *spec = codec->spec;
2475 spec->use_acomp_notifier = true;
2476 spec->i915_audio_ops.audio_ptr = codec;
2477 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2478 * will call pin_eld_notify with using audio_ptr pointer
2479 * We need make sure audio_ptr is really setup
2482 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2483 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2486 /* setup_stream ops override for HSW+ */
2487 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2488 hda_nid_t pin_nid, u32 stream_tag, int format)
2490 haswell_verify_D0(codec, cvt_nid, pin_nid);
2491 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2494 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2495 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2496 struct hdmi_spec_per_pin *per_pin,
2500 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2502 intel_verify_pin_cvt_connect(codec, per_pin);
2503 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2504 per_pin->dev_id, per_pin->mux_idx);
2506 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2510 /* precondition and allocation for Intel codecs */
2511 static int alloc_intel_hdmi(struct hda_codec *codec)
2513 /* requires i915 binding */
2514 if (!codec->bus->core.audio_component) {
2515 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2519 return alloc_generic_hdmi(codec);
2522 /* parse and post-process for Intel codecs */
2523 static int parse_intel_hdmi(struct hda_codec *codec)
2527 err = hdmi_parse_codec(codec);
2529 generic_spec_free(codec);
2533 generic_hdmi_init_per_pins(codec);
2534 register_i915_notifier(codec);
2538 /* Intel Haswell and onwards; audio component with eld notifier */
2539 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid)
2541 struct hdmi_spec *spec;
2544 err = alloc_intel_hdmi(codec);
2548 codec->dp_mst = true;
2549 spec->dyn_pcm_assign = true;
2550 spec->vendor_nid = vendor_nid;
2552 intel_haswell_enable_all_pins(codec, true);
2553 intel_haswell_fixup_enable_dp12(codec);
2555 /* For Haswell/Broadwell, the controller is also in the power well and
2556 * can cover the codec power request, and so need not set this flag.
2558 if (!is_haswell(codec) && !is_broadwell(codec))
2559 codec->core.link_power_control = 1;
2561 codec->patch_ops.set_power_state = haswell_set_power_state;
2562 codec->depop_delay = 0;
2563 codec->auto_runtime_pm = 1;
2565 spec->ops.setup_stream = i915_hsw_setup_stream;
2566 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2568 return parse_intel_hdmi(codec);
2571 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2573 return intel_hsw_common_init(codec, INTEL_VENDOR_NID);
2576 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2578 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID);
2581 /* Intel Baytrail and Braswell; with eld notifier */
2582 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2584 struct hdmi_spec *spec;
2587 err = alloc_intel_hdmi(codec);
2592 /* For Valleyview/Cherryview, only the display codec is in the display
2593 * power well and can use link_power ops to request/release the power.
2595 codec->core.link_power_control = 1;
2597 codec->depop_delay = 0;
2598 codec->auto_runtime_pm = 1;
2600 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2602 return parse_intel_hdmi(codec);
2605 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2606 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2610 err = alloc_intel_hdmi(codec);
2613 return parse_intel_hdmi(codec);
2617 * Shared non-generic implementations
2620 static int simple_playback_build_pcms(struct hda_codec *codec)
2622 struct hdmi_spec *spec = codec->spec;
2623 struct hda_pcm *info;
2625 struct hda_pcm_stream *pstr;
2626 struct hdmi_spec_per_cvt *per_cvt;
2628 per_cvt = get_cvt(spec, 0);
2629 chans = get_wcaps(codec, per_cvt->cvt_nid);
2630 chans = get_wcaps_channels(chans);
2632 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2635 spec->pcm_rec[0].pcm = info;
2636 info->pcm_type = HDA_PCM_TYPE_HDMI;
2637 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2638 *pstr = spec->pcm_playback;
2639 pstr->nid = per_cvt->cvt_nid;
2640 if (pstr->channels_max <= 2 && chans && chans <= 16)
2641 pstr->channels_max = chans;
2646 /* unsolicited event for jack sensing */
2647 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2650 snd_hda_jack_set_dirty_all(codec);
2651 snd_hda_jack_report_sync(codec);
2654 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2655 * as long as spec->pins[] is set correctly
2657 #define simple_hdmi_build_jack generic_hdmi_build_jack
2659 static int simple_playback_build_controls(struct hda_codec *codec)
2661 struct hdmi_spec *spec = codec->spec;
2662 struct hdmi_spec_per_cvt *per_cvt;
2665 per_cvt = get_cvt(spec, 0);
2666 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2671 return simple_hdmi_build_jack(codec, 0);
2674 static int simple_playback_init(struct hda_codec *codec)
2676 struct hdmi_spec *spec = codec->spec;
2677 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2678 hda_nid_t pin = per_pin->pin_nid;
2680 snd_hda_codec_write(codec, pin, 0,
2681 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2682 /* some codecs require to unmute the pin */
2683 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2684 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2686 snd_hda_jack_detect_enable(codec, pin);
2690 static void simple_playback_free(struct hda_codec *codec)
2692 struct hdmi_spec *spec = codec->spec;
2694 hdmi_array_free(spec);
2699 * Nvidia specific implementations
2702 #define Nv_VERB_SET_Channel_Allocation 0xF79
2703 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2704 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2705 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2707 #define nvhdmi_master_con_nid_7x 0x04
2708 #define nvhdmi_master_pin_nid_7x 0x05
2710 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2711 /*front, rear, clfe, rear_surr */
2715 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2716 /* set audio protect on */
2717 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2718 /* enable digital output on pin widget */
2719 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2723 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2724 /* set audio protect on */
2725 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2726 /* enable digital output on pin widget */
2727 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2728 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2729 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2730 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2731 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2735 #ifdef LIMITED_RATE_FMT_SUPPORT
2736 /* support only the safe format and rate */
2737 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2738 #define SUPPORTED_MAXBPS 16
2739 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2741 /* support all rates and formats */
2742 #define SUPPORTED_RATES \
2743 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2744 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2745 SNDRV_PCM_RATE_192000)
2746 #define SUPPORTED_MAXBPS 24
2747 #define SUPPORTED_FORMATS \
2748 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2751 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2753 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2757 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2759 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2763 static const unsigned int channels_2_6_8[] = {
2767 static const unsigned int channels_2_8[] = {
2771 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2772 .count = ARRAY_SIZE(channels_2_6_8),
2773 .list = channels_2_6_8,
2777 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2778 .count = ARRAY_SIZE(channels_2_8),
2779 .list = channels_2_8,
2783 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2784 struct hda_codec *codec,
2785 struct snd_pcm_substream *substream)
2787 struct hdmi_spec *spec = codec->spec;
2788 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2790 switch (codec->preset->vendor_id) {
2795 hw_constraints_channels = &hw_constraints_2_8_channels;
2798 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2804 if (hw_constraints_channels != NULL) {
2805 snd_pcm_hw_constraint_list(substream->runtime, 0,
2806 SNDRV_PCM_HW_PARAM_CHANNELS,
2807 hw_constraints_channels);
2809 snd_pcm_hw_constraint_step(substream->runtime, 0,
2810 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2813 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2816 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2817 struct hda_codec *codec,
2818 struct snd_pcm_substream *substream)
2820 struct hdmi_spec *spec = codec->spec;
2821 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2824 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2825 struct hda_codec *codec,
2826 unsigned int stream_tag,
2827 unsigned int format,
2828 struct snd_pcm_substream *substream)
2830 struct hdmi_spec *spec = codec->spec;
2831 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2832 stream_tag, format, substream);
2835 static const struct hda_pcm_stream simple_pcm_playback = {
2840 .open = simple_playback_pcm_open,
2841 .close = simple_playback_pcm_close,
2842 .prepare = simple_playback_pcm_prepare
2846 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2847 .build_controls = simple_playback_build_controls,
2848 .build_pcms = simple_playback_build_pcms,
2849 .init = simple_playback_init,
2850 .free = simple_playback_free,
2851 .unsol_event = simple_hdmi_unsol_event,
2854 static int patch_simple_hdmi(struct hda_codec *codec,
2855 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2857 struct hdmi_spec *spec;
2858 struct hdmi_spec_per_cvt *per_cvt;
2859 struct hdmi_spec_per_pin *per_pin;
2861 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2866 hdmi_array_init(spec, 1);
2868 spec->multiout.num_dacs = 0; /* no analog */
2869 spec->multiout.max_channels = 2;
2870 spec->multiout.dig_out_nid = cvt_nid;
2873 per_pin = snd_array_new(&spec->pins);
2874 per_cvt = snd_array_new(&spec->cvts);
2875 if (!per_pin || !per_cvt) {
2876 simple_playback_free(codec);
2879 per_cvt->cvt_nid = cvt_nid;
2880 per_pin->pin_nid = pin_nid;
2881 spec->pcm_playback = simple_pcm_playback;
2883 codec->patch_ops = simple_hdmi_patch_ops;
2888 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2891 unsigned int chanmask;
2892 int chan = channels ? (channels - 1) : 1;
2911 /* Set the audio infoframe channel allocation and checksum fields. The
2912 * channel count is computed implicitly by the hardware. */
2913 snd_hda_codec_write(codec, 0x1, 0,
2914 Nv_VERB_SET_Channel_Allocation, chanmask);
2916 snd_hda_codec_write(codec, 0x1, 0,
2917 Nv_VERB_SET_Info_Frame_Checksum,
2918 (0x71 - chan - chanmask));
2921 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2922 struct hda_codec *codec,
2923 struct snd_pcm_substream *substream)
2925 struct hdmi_spec *spec = codec->spec;
2928 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2929 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2930 for (i = 0; i < 4; i++) {
2931 /* set the stream id */
2932 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2933 AC_VERB_SET_CHANNEL_STREAMID, 0);
2934 /* set the stream format */
2935 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2936 AC_VERB_SET_STREAM_FORMAT, 0);
2939 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2940 * streams are disabled. */
2941 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2943 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2946 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2947 struct hda_codec *codec,
2948 unsigned int stream_tag,
2949 unsigned int format,
2950 struct snd_pcm_substream *substream)
2953 unsigned int dataDCC2, channel_id;
2955 struct hdmi_spec *spec = codec->spec;
2956 struct hda_spdif_out *spdif;
2957 struct hdmi_spec_per_cvt *per_cvt;
2959 mutex_lock(&codec->spdif_mutex);
2960 per_cvt = get_cvt(spec, 0);
2961 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2963 chs = substream->runtime->channels;
2967 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2968 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2969 snd_hda_codec_write(codec,
2970 nvhdmi_master_con_nid_7x,
2972 AC_VERB_SET_DIGI_CONVERT_1,
2973 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2975 /* set the stream id */
2976 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2977 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2979 /* set the stream format */
2980 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2981 AC_VERB_SET_STREAM_FORMAT, format);
2983 /* turn on again (if needed) */
2984 /* enable and set the channel status audio/data flag */
2985 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2986 snd_hda_codec_write(codec,
2987 nvhdmi_master_con_nid_7x,
2989 AC_VERB_SET_DIGI_CONVERT_1,
2990 spdif->ctls & 0xff);
2991 snd_hda_codec_write(codec,
2992 nvhdmi_master_con_nid_7x,
2994 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2997 for (i = 0; i < 4; i++) {
3003 /* turn off SPDIF once;
3004 *otherwise the IEC958 bits won't be updated
3006 if (codec->spdif_status_reset &&
3007 (spdif->ctls & AC_DIG1_ENABLE))
3008 snd_hda_codec_write(codec,
3009 nvhdmi_con_nids_7x[i],
3011 AC_VERB_SET_DIGI_CONVERT_1,
3012 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3013 /* set the stream id */
3014 snd_hda_codec_write(codec,
3015 nvhdmi_con_nids_7x[i],
3017 AC_VERB_SET_CHANNEL_STREAMID,
3018 (stream_tag << 4) | channel_id);
3019 /* set the stream format */
3020 snd_hda_codec_write(codec,
3021 nvhdmi_con_nids_7x[i],
3023 AC_VERB_SET_STREAM_FORMAT,
3025 /* turn on again (if needed) */
3026 /* enable and set the channel status audio/data flag */
3027 if (codec->spdif_status_reset &&
3028 (spdif->ctls & AC_DIG1_ENABLE)) {
3029 snd_hda_codec_write(codec,
3030 nvhdmi_con_nids_7x[i],
3032 AC_VERB_SET_DIGI_CONVERT_1,
3033 spdif->ctls & 0xff);
3034 snd_hda_codec_write(codec,
3035 nvhdmi_con_nids_7x[i],
3037 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3041 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3043 mutex_unlock(&codec->spdif_mutex);
3047 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3051 .nid = nvhdmi_master_con_nid_7x,
3052 .rates = SUPPORTED_RATES,
3053 .maxbps = SUPPORTED_MAXBPS,
3054 .formats = SUPPORTED_FORMATS,
3056 .open = simple_playback_pcm_open,
3057 .close = nvhdmi_8ch_7x_pcm_close,
3058 .prepare = nvhdmi_8ch_7x_pcm_prepare
3062 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3064 struct hdmi_spec *spec;
3065 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3066 nvhdmi_master_pin_nid_7x);
3070 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3071 /* override the PCM rates, etc, as the codec doesn't give full list */
3073 spec->pcm_playback.rates = SUPPORTED_RATES;
3074 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3075 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3079 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3081 struct hdmi_spec *spec = codec->spec;
3082 int err = simple_playback_build_pcms(codec);
3084 struct hda_pcm *info = get_pcm_rec(spec, 0);
3085 info->own_chmap = true;
3090 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3092 struct hdmi_spec *spec = codec->spec;
3093 struct hda_pcm *info;
3094 struct snd_pcm_chmap *chmap;
3097 err = simple_playback_build_controls(codec);
3101 /* add channel maps */
3102 info = get_pcm_rec(spec, 0);
3103 err = snd_pcm_add_chmap_ctls(info->pcm,
3104 SNDRV_PCM_STREAM_PLAYBACK,
3105 snd_pcm_alt_chmaps, 8, 0, &chmap);
3108 switch (codec->preset->vendor_id) {
3113 chmap->channel_mask = (1U << 2) | (1U << 8);
3116 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3121 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3123 struct hdmi_spec *spec;
3124 int err = patch_nvhdmi_2ch(codec);
3128 spec->multiout.max_channels = 8;
3129 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3130 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3131 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3132 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3134 /* Initialize the audio infoframe channel mask and checksum to something
3136 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3142 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3146 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3147 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3149 if (cap->ca_index == 0x00 && channels == 2)
3150 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3152 /* If the speaker allocation matches the channel count, it is OK. */
3153 if (cap->channels != channels)
3156 /* all channels are remappable freely */
3157 return SNDRV_CTL_TLVT_CHMAP_VAR;
3160 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3161 int ca, int chs, unsigned char *map)
3163 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3169 static int patch_nvhdmi(struct hda_codec *codec)
3171 struct hdmi_spec *spec;
3174 err = patch_generic_hdmi(codec);
3179 spec->dyn_pin_out = true;
3181 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3182 nvhdmi_chmap_cea_alloc_validate_get_type;
3183 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3189 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3190 * accessed using vendor-defined verbs. These registers can be used for
3191 * interoperability between the HDA and HDMI drivers.
3194 /* Audio Function Group node */
3195 #define NVIDIA_AFG_NID 0x01
3198 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3199 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3200 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3201 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3202 * additional bit (at position 30) to signal the validity of the format.
3204 * | 31 | 30 | 29 16 | 15 0 |
3205 * +---------+-------+--------+--------+
3206 * | TRIGGER | VALID | UNUSED | FORMAT |
3207 * +-----------------------------------|
3209 * Note that for the trigger bit to take effect it needs to change value
3210 * (i.e. it needs to be toggled).
3212 #define NVIDIA_GET_SCRATCH0 0xfa6
3213 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3214 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3215 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3216 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3217 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3218 #define NVIDIA_SCRATCH_VALID (1 << 6)
3220 #define NVIDIA_GET_SCRATCH1 0xfab
3221 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3222 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3223 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3224 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3227 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3228 * the format is invalidated so that the HDMI codec can be disabled.
3230 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3234 /* bits [31:30] contain the trigger and valid bits */
3235 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3236 NVIDIA_GET_SCRATCH0, 0);
3237 value = (value >> 24) & 0xff;
3239 /* bits [15:0] are used to store the HDA format */
3240 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3241 NVIDIA_SET_SCRATCH0_BYTE0,
3242 (format >> 0) & 0xff);
3243 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3244 NVIDIA_SET_SCRATCH0_BYTE1,
3245 (format >> 8) & 0xff);
3247 /* bits [16:24] are unused */
3248 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3249 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3252 * Bit 30 signals that the data is valid and hence that HDMI audio can
3256 value &= ~NVIDIA_SCRATCH_VALID;
3258 value |= NVIDIA_SCRATCH_VALID;
3261 * Whenever the trigger bit is toggled, an interrupt is raised in the
3262 * HDMI codec. The HDMI driver will use that as trigger to update its
3265 value ^= NVIDIA_SCRATCH_TRIGGER;
3267 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3268 NVIDIA_SET_SCRATCH0_BYTE3, value);
3271 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3272 struct hda_codec *codec,
3273 unsigned int stream_tag,
3274 unsigned int format,
3275 struct snd_pcm_substream *substream)
3279 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3284 /* notify the HDMI codec of the format change */
3285 tegra_hdmi_set_format(codec, format);
3290 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3291 struct hda_codec *codec,
3292 struct snd_pcm_substream *substream)
3294 /* invalidate the format in the HDMI codec */
3295 tegra_hdmi_set_format(codec, 0);
3297 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3300 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3302 struct hdmi_spec *spec = codec->spec;
3305 for (i = 0; i < spec->num_pins; i++) {
3306 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3308 if (pcm->pcm_type == type)
3315 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3317 struct hda_pcm_stream *stream;
3318 struct hda_pcm *pcm;
3321 err = generic_hdmi_build_pcms(codec);
3325 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3330 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3331 * codec about format changes.
3333 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3334 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3335 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3340 static int patch_tegra_hdmi(struct hda_codec *codec)
3344 err = patch_generic_hdmi(codec);
3348 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3354 * ATI/AMD-specific implementations
3357 #define is_amdhdmi_rev3_or_later(codec) \
3358 ((codec)->core.vendor_id == 0x1002aa01 && \
3359 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3360 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3362 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3363 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3364 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3365 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3366 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3367 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3368 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3369 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3370 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3371 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3372 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3373 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3374 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3375 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3376 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3377 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3378 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3379 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3380 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3381 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3382 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3383 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3384 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3385 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3386 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3388 /* AMD specific HDA cvt verbs */
3389 #define ATI_VERB_SET_RAMP_RATE 0x770
3390 #define ATI_VERB_GET_RAMP_RATE 0xf70
3392 #define ATI_OUT_ENABLE 0x1
3394 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3395 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3397 #define ATI_HBR_CAPABLE 0x01
3398 #define ATI_HBR_ENABLE 0x10
3400 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3401 unsigned char *buf, int *eld_size)
3403 /* call hda_eld.c ATI/AMD-specific function */
3404 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3405 is_amdhdmi_rev3_or_later(codec));
3408 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3409 int active_channels, int conn_type)
3411 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3414 static int atihdmi_paired_swap_fc_lfe(int pos)
3417 * ATI/AMD have automatic FC/LFE swap built-in
3418 * when in pairwise mapping mode.
3422 /* see channel_allocations[].speakers[] */
3431 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3432 int ca, int chs, unsigned char *map)
3434 struct hdac_cea_channel_speaker_allocation *cap;
3437 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3439 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3440 for (i = 0; i < chs; ++i) {
3441 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3443 bool companion_ok = false;
3448 for (j = 0 + i % 2; j < 8; j += 2) {
3449 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3450 if (cap->speakers[chan_idx] == mask) {
3451 /* channel is in a supported position */
3454 if (i % 2 == 0 && i + 1 < chs) {
3455 /* even channel, check the odd companion */
3456 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3457 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3458 int comp_mask_act = cap->speakers[comp_chan_idx];
3460 if (comp_mask_req == comp_mask_act)
3461 companion_ok = true;
3473 i++; /* companion channel already checked */
3479 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3480 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3482 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3484 int ati_channel_setup = 0;
3489 if (!has_amd_full_remap_support(codec)) {
3490 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3492 /* In case this is an odd slot but without stream channel, do not
3493 * disable the slot since the corresponding even slot could have a
3494 * channel. In case neither have a channel, the slot pair will be
3495 * disabled when this function is called for the even slot. */
3496 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3499 hdmi_slot -= hdmi_slot % 2;
3501 if (stream_channel != 0xf)
3502 stream_channel -= stream_channel % 2;
3505 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3507 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3509 if (stream_channel != 0xf)
3510 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3512 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3515 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3516 hda_nid_t pin_nid, int asp_slot)
3518 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3519 bool was_odd = false;
3520 int ati_asp_slot = asp_slot;
3522 int ati_channel_setup;
3527 if (!has_amd_full_remap_support(codec)) {
3528 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3529 if (ati_asp_slot % 2 != 0) {
3535 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3537 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3539 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3542 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3545 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3546 struct hdac_chmap *chmap,
3547 struct hdac_cea_channel_speaker_allocation *cap,
3553 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3554 * we need to take that into account (a single channel may take 2
3555 * channel slots if we need to carry a silent channel next to it).
3556 * On Rev3+ AMD codecs this function is not used.
3560 /* We only produce even-numbered channel count TLVs */
3561 if ((channels % 2) != 0)
3564 for (c = 0; c < 7; c += 2) {
3565 if (cap->speakers[c] || cap->speakers[c+1])
3569 if (chanpairs * 2 != channels)
3572 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3575 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3576 struct hdac_cea_channel_speaker_allocation *cap,
3577 unsigned int *chmap, int channels)
3579 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3583 for (c = 7; c >= 0; c--) {
3584 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3585 int spk = cap->speakers[chan];
3587 /* add N/A channel if the companion channel is occupied */
3588 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3589 chmap[count++] = SNDRV_CHMAP_NA;
3594 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3597 WARN_ON(count != channels);
3600 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3603 int hbr_ctl, hbr_ctl_new;
3605 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3606 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3608 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3610 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3613 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3615 hbr_ctl == hbr_ctl_new ? "" : "new-",
3618 if (hbr_ctl != hbr_ctl_new)
3619 snd_hda_codec_write(codec, pin_nid, 0,
3620 ATI_VERB_SET_HBR_CONTROL,
3629 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3630 hda_nid_t pin_nid, u32 stream_tag, int format)
3633 if (is_amdhdmi_rev3_or_later(codec)) {
3634 int ramp_rate = 180; /* default as per AMD spec */
3635 /* disable ramp-up/down for non-pcm as per AMD spec */
3636 if (format & AC_FMT_TYPE_NON_PCM)
3639 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3642 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3646 static int atihdmi_init(struct hda_codec *codec)
3648 struct hdmi_spec *spec = codec->spec;
3651 err = generic_hdmi_init(codec);
3656 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3657 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3659 /* make sure downmix information in infoframe is zero */
3660 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3662 /* enable channel-wise remap mode if supported */
3663 if (has_amd_full_remap_support(codec))
3664 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3665 ATI_VERB_SET_MULTICHANNEL_MODE,
3666 ATI_MULTICHANNEL_MODE_SINGLE);
3672 static int patch_atihdmi(struct hda_codec *codec)
3674 struct hdmi_spec *spec;
3675 struct hdmi_spec_per_cvt *per_cvt;
3678 err = patch_generic_hdmi(codec);
3683 codec->patch_ops.init = atihdmi_init;
3687 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3688 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3689 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3690 spec->ops.setup_stream = atihdmi_setup_stream;
3692 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3693 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3695 if (!has_amd_full_remap_support(codec)) {
3696 /* override to ATI/AMD-specific versions with pairwise mapping */
3697 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3698 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3699 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3700 atihdmi_paired_cea_alloc_to_tlv_chmap;
3701 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3704 /* ATI/AMD converters do not advertise all of their capabilities */
3705 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3706 per_cvt = get_cvt(spec, cvt_idx);
3707 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3708 per_cvt->rates |= SUPPORTED_RATES;
3709 per_cvt->formats |= SUPPORTED_FORMATS;
3710 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3713 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3718 /* VIA HDMI Implementation */
3719 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3720 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3722 static int patch_via_hdmi(struct hda_codec *codec)
3724 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3730 static const struct hda_device_id snd_hda_id_hdmi[] = {
3731 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3732 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3733 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3734 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3735 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3736 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3737 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3738 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
3739 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3740 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3741 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
3742 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3743 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3744 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3745 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3746 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
3747 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3748 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3749 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3750 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3751 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3752 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3753 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3754 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3755 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3756 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3757 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3758 /* 17 is known to be absent */
3759 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3760 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3761 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3762 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3763 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3764 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3765 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3766 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3767 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3768 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3769 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3770 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3771 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3772 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3773 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3774 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
3775 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3776 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
3777 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3778 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3779 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
3780 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3781 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3782 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3783 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3784 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3785 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3786 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3787 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3788 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
3789 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3790 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
3791 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
3792 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
3793 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3794 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3795 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3796 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3797 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3798 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3799 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3800 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3801 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3802 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3803 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3804 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
3805 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3806 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
3807 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3808 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3809 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3810 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3811 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3812 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3813 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3814 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3815 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3816 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3817 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3818 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3819 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3820 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3821 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3822 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
3823 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
3824 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
3825 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3826 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3827 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
3828 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3829 /* special ID for generic HDMI */
3830 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3833 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3835 MODULE_LICENSE("GPL");
3836 MODULE_DESCRIPTION("HDMI HD-audio codec");
3837 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3838 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3839 MODULE_ALIAS("snd-hda-codec-atihdmi");
3841 static struct hda_codec_driver hdmi_driver = {
3842 .id = snd_hda_id_hdmi,
3845 module_hda_codec_driver(hdmi_driver);