sound/pci/hda/patch_hdmi.c

   1 /*
   2  *
   3  *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
   4  *
   5  *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
   6  *  Copyright (c) 2006 ATI Technologies Inc.
   7  *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
   8  *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
   9  *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
  10  *
  11  *  Authors:
  12  *                      Wu Fengguang <wfg@linux.intel.com>
  13  *
  14  *  Maintained by:
  15  *                      Wu Fengguang <wfg@linux.intel.com>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify it
  18  *  under the terms of the GNU General Public License as published by the Free
  19  *  Software Foundation; either version 2 of the License, or (at your option)
  20  *  any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful, but
  23  *  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  24  *  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  25  *  for more details.
  26  *
  27  *  You should have received a copy of the GNU General Public License
  28  *  along with this program; if not, write to the Free Software Foundation,
  29  *  Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/delay.h>
  34 #include <linux/slab.h>
  35 #include <linux/module.h>
  36 #include <sound/core.h>
  37 #include <sound/jack.h>
  38 #include <sound/asoundef.h>
  39 #include <sound/tlv.h>
  40 #include <sound/hdaudio.h>
  41 #include <sound/hda_i915.h>
  42 #include <sound/hda_chmap.h>
  43 #include "hda_codec.h"
  44 #include "hda_local.h"
  45 #include "hda_jack.h"
  46
  47 static bool static_hdmi_pcm;
  48 module_param(static_hdmi_pcm, bool, 0644);
  49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  50
  51 #define is_haswell(codec)  ((codec)->core.vendor_id == 0x80862807)
  52 #define is_broadwell(codec)    ((codec)->core.vendor_id == 0x80862808)
  53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
  54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
  55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
  56 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
  57                                 ((codec)->core.vendor_id == 0x80862800))
  58 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
  59 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
  60                                 || is_skylake(codec) || is_broxton(codec) \
  61                                 || is_kabylake(codec)) || is_geminilake(codec) \
  62                                 || is_cannonlake(codec)
  63 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
  64 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
  65 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
  66
  67 struct hdmi_spec_per_cvt {
  68         hda_nid_t cvt_nid;
  69         int assigned;
  70         unsigned int channels_min;
  71         unsigned int channels_max;
  72         u32 rates;
  73         u64 formats;
  74         unsigned int maxbps;
  75 };
  76
  77 /* max. connections to a widget */
  78 #define HDA_MAX_CONNECTIONS     32
  79
  80 struct hdmi_spec_per_pin {
  81         hda_nid_t pin_nid;
  82         int dev_id;
  83         /* pin idx, different device entries on the same pin use the same idx */
  84         int pin_nid_idx;
  85         int num_mux_nids;
  86         hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  87         int mux_idx;
  88         hda_nid_t cvt_nid;
  89
  90         struct hda_codec *codec;
  91         struct hdmi_eld sink_eld;
  92         struct mutex lock;
  93         struct delayed_work work;
  94         struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
  95         int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
  96         int repoll_count;
  97         bool setup; /* the stream has been set up by prepare callback */
  98         int channels; /* current number of channels */
  99         bool non_pcm;
 100         bool chmap_set;         /* channel-map override by ALSA API? */
 101         unsigned char chmap[8]; /* ALSA API channel-map */
 102 #ifdef CONFIG_SND_PROC_FS
 103         struct snd_info_entry *proc_entry;
 104 #endif
 105 };
 106
 107 /* operations used by generic code that can be overridden by patches */
 108 struct hdmi_ops {
 109         int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
 110                            unsigned char *buf, int *eld_size);
 111
 112         void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
 113                                     int ca, int active_channels, int conn_type);
 114
 115         /* enable/disable HBR (HD passthrough) */
 116         int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
 117
 118         int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
 119                             hda_nid_t pin_nid, u32 stream_tag, int format);
 120
 121         void (*pin_cvt_fixup)(struct hda_codec *codec,
 122                               struct hdmi_spec_per_pin *per_pin,
 123                               hda_nid_t cvt_nid);
 124 };
 125
 126 struct hdmi_pcm {
 127         struct hda_pcm *pcm;
 128         struct snd_jack *jack;
 129         struct snd_kcontrol *eld_ctl;
 130 };
 131
 132 struct hdmi_spec {
 133         int num_cvts;
 134         struct snd_array cvts; /* struct hdmi_spec_per_cvt */
 135         hda_nid_t cvt_nids[4]; /* only for haswell fix */
 136
 137         /*
 138          * num_pins is the number of virtual pins
 139          * for example, there are 3 pins, and each pin
 140          * has 4 device entries, then the num_pins is 12
 141          */
 142         int num_pins;
 143         /*
 144          * num_nids is the number of real pins
 145          * In the above example, num_nids is 3
 146          */
 147         int num_nids;
 148         /*
 149          * dev_num is the number of device entries
 150          * on each pin.
 151          * In the above example, dev_num is 4
 152          */
 153         int dev_num;
 154         struct snd_array pins; /* struct hdmi_spec_per_pin */
 155         struct hdmi_pcm pcm_rec[16];
 156         struct mutex pcm_lock;
 157         /* pcm_bitmap means which pcms have been assigned to pins*/
 158         unsigned long pcm_bitmap;
 159         int pcm_used;   /* counter of pcm_rec[] */
 160         /* bitmap shows whether the pcm is opened in user space
 161          * bit 0 means the first playback PCM (PCM3);
 162          * bit 1 means the second playback PCM, and so on.
 163          */
 164         unsigned long pcm_in_use;
 165
 166         struct hdmi_eld temp_eld;
 167         struct hdmi_ops ops;
 168
 169         bool dyn_pin_out;
 170         bool dyn_pcm_assign;
 171         /*
 172          * Non-generic VIA/NVIDIA specific
 173          */
 174         struct hda_multi_out multiout;
 175         struct hda_pcm_stream pcm_playback;
 176
 177         /* i915/powerwell (Haswell+/Valleyview+) specific */
 178         bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
 179         struct i915_audio_component_audio_ops i915_audio_ops;
 180
 181         struct hdac_chmap chmap;
 182         hda_nid_t vendor_nid;
 183 };
 184
 185 #ifdef CONFIG_SND_HDA_I915
 186 static inline bool codec_has_acomp(struct hda_codec *codec)
 187 {
 188         struct hdmi_spec *spec = codec->spec;
 189         return spec->use_acomp_notifier;
 190 }
 191 #else
 192 #define codec_has_acomp(codec)  false
 193 #endif
 194
 195 struct hdmi_audio_infoframe {
 196         u8 type; /* 0x84 */
 197         u8 ver;  /* 0x01 */
 198         u8 len;  /* 0x0a */
 199
 200         u8 checksum;
 201
 202         u8 CC02_CT47;   /* CC in bits 0:2, CT in 4:7 */
 203         u8 SS01_SF24;
 204         u8 CXT04;
 205         u8 CA;
 206         u8 LFEPBL01_LSV36_DM_INH7;
 207 };
 208
 209 struct dp_audio_infoframe {
 210         u8 type; /* 0x84 */
 211         u8 len;  /* 0x1b */
 212         u8 ver;  /* 0x11 << 2 */
 213
 214         u8 CC02_CT47;   /* match with HDMI infoframe from this on */
 215         u8 SS01_SF24;
 216         u8 CXT04;
 217         u8 CA;
 218         u8 LFEPBL01_LSV36_DM_INH7;
 219 };
 220
 221 union audio_infoframe {
 222         struct hdmi_audio_infoframe hdmi;
 223         struct dp_audio_infoframe dp;
 224         u8 bytes[0];
 225 };
 226
 227 /*
 228  * HDMI routines
 229  */
 230
 231 #define get_pin(spec, idx) \
 232         ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
 233 #define get_cvt(spec, idx) \
 234         ((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
 235 /* obtain hdmi_pcm object assigned to idx */
 236 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
 237 /* obtain hda_pcm object assigned to idx */
 238 #define get_pcm_rec(spec, idx)  (get_hdmi_pcm(spec, idx)->pcm)
 239
 240 static int pin_id_to_pin_index(struct hda_codec *codec,
 241                                hda_nid_t pin_nid, int dev_id)
 242 {
 243         struct hdmi_spec *spec = codec->spec;
 244         int pin_idx;
 245         struct hdmi_spec_per_pin *per_pin;
 246
 247         /*
 248          * (dev_id == -1) means it is NON-MST pin
 249          * return the first virtual pin on this port
 250          */
 251         if (dev_id == -1)
 252                 dev_id = 0;
 253
 254         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
 255                 per_pin = get_pin(spec, pin_idx);
 256                 if ((per_pin->pin_nid == pin_nid) &&
 257                         (per_pin->dev_id == dev_id))
 258                         return pin_idx;
 259         }
 260
 261         codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
 262         return -EINVAL;
 263 }
 264
 265 static int hinfo_to_pcm_index(struct hda_codec *codec,
 266                         struct hda_pcm_stream *hinfo)
 267 {
 268         struct hdmi_spec *spec = codec->spec;
 269         int pcm_idx;
 270
 271         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
 272                 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
 273                         return pcm_idx;
 274
 275         codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
 276         return -EINVAL;
 277 }
 278
 279 static int hinfo_to_pin_index(struct hda_codec *codec,
 280                               struct hda_pcm_stream *hinfo)
 281 {
 282         struct hdmi_spec *spec = codec->spec;
 283         struct hdmi_spec_per_pin *per_pin;
 284         int pin_idx;
 285
 286         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
 287                 per_pin = get_pin(spec, pin_idx);
 288                 if (per_pin->pcm &&
 289                         per_pin->pcm->pcm->stream == hinfo)
 290                         return pin_idx;
 291         }
 292
 293         codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
 294         return -EINVAL;
 295 }
 296
 297 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
 298                                                 int pcm_idx)
 299 {
 300         int i;
 301         struct hdmi_spec_per_pin *per_pin;
 302
 303         for (i = 0; i < spec->num_pins; i++) {
 304                 per_pin = get_pin(spec, i);
 305                 if (per_pin->pcm_idx == pcm_idx)
 306                         return per_pin;
 307         }
 308         return NULL;
 309 }
 310
 311 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
 312 {
 313         struct hdmi_spec *spec = codec->spec;
 314         int cvt_idx;
 315
 316         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
 317                 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
 318                         return cvt_idx;
 319
 320         codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
 321         return -EINVAL;
 322 }
 323
 324 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
 325                         struct snd_ctl_elem_info *uinfo)
 326 {
 327         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 328         struct hdmi_spec *spec = codec->spec;
 329         struct hdmi_spec_per_pin *per_pin;
 330         struct hdmi_eld *eld;
 331         int pcm_idx;
 332
 333         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 334
 335         pcm_idx = kcontrol->private_value;
 336         mutex_lock(&spec->pcm_lock);
 337         per_pin = pcm_idx_to_pin(spec, pcm_idx);
 338         if (!per_pin) {
 339                 /* no pin is bound to the pcm */
 340                 uinfo->count = 0;
 341                 mutex_unlock(&spec->pcm_lock);
 342                 return 0;
 343         }
 344         eld = &per_pin->sink_eld;
 345         uinfo->count = eld->eld_valid ? eld->eld_size : 0;
 346         mutex_unlock(&spec->pcm_lock);
 347
 348         return 0;
 349 }
 350
 351 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
 352                         struct snd_ctl_elem_value *ucontrol)
 353 {
 354         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 355         struct hdmi_spec *spec = codec->spec;
 356         struct hdmi_spec_per_pin *per_pin;
 357         struct hdmi_eld *eld;
 358         int pcm_idx;
 359
 360         pcm_idx = kcontrol->private_value;
 361         mutex_lock(&spec->pcm_lock);
 362         per_pin = pcm_idx_to_pin(spec, pcm_idx);
 363         if (!per_pin) {
 364                 /* no pin is bound to the pcm */
 365                 memset(ucontrol->value.bytes.data, 0,
 366                        ARRAY_SIZE(ucontrol->value.bytes.data));
 367                 mutex_unlock(&spec->pcm_lock);
 368                 return 0;
 369         }
 370         eld = &per_pin->sink_eld;
 371
 372         if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
 373             eld->eld_size > ELD_MAX_SIZE) {
 374                 mutex_unlock(&spec->pcm_lock);
 375                 snd_BUG();
 376                 return -EINVAL;
 377         }
 378
 379         memset(ucontrol->value.bytes.data, 0,
 380                ARRAY_SIZE(ucontrol->value.bytes.data));
 381         if (eld->eld_valid)
 382                 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
 383                        eld->eld_size);
 384         mutex_unlock(&spec->pcm_lock);
 385
 386         return 0;
 387 }
 388
 389 static const struct snd_kcontrol_new eld_bytes_ctl = {
 390         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 391         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 392         .name = "ELD",
 393         .info = hdmi_eld_ctl_info,
 394         .get = hdmi_eld_ctl_get,
 395 };
 396
 397 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
 398                         int device)
 399 {
 400         struct snd_kcontrol *kctl;
 401         struct hdmi_spec *spec = codec->spec;
 402         int err;
 403
 404         kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
 405         if (!kctl)
 406                 return -ENOMEM;
 407         kctl->private_value = pcm_idx;
 408         kctl->id.device = device;
 409
 410         /* no pin nid is associated with the kctl now
 411          * tbd: associate pin nid to eld ctl later
 412          */
 413         err = snd_hda_ctl_add(codec, 0, kctl);
 414         if (err < 0)
 415                 return err;
 416
 417         get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
 418         return 0;
 419 }
 420
 421 #ifdef BE_PARANOID
 422 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 423                                 int *packet_index, int *byte_index)
 424 {
 425         int val;
 426
 427         val = snd_hda_codec_read(codec, pin_nid, 0,
 428                                  AC_VERB_GET_HDMI_DIP_INDEX, 0);
 429
 430         *packet_index = val >> 5;
 431         *byte_index = val & 0x1f;
 432 }
 433 #endif
 434
 435 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 436                                 int packet_index, int byte_index)
 437 {
 438         int val;
 439
 440         val = (packet_index << 5) | (byte_index & 0x1f);
 441
 442         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
 443 }
 444
 445 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
 446                                 unsigned char val)
 447 {
 448         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
 449 }
 450
 451 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
 452 {
 453         struct hdmi_spec *spec = codec->spec;
 454         int pin_out;
 455
 456         /* Unmute */
 457         if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
 458                 snd_hda_codec_write(codec, pin_nid, 0,
 459                                 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
 460
 461         if (spec->dyn_pin_out)
 462                 /* Disable pin out until stream is active */
 463                 pin_out = 0;
 464         else
 465                 /* Enable pin out: some machines with GM965 gets broken output
 466                  * when the pin is disabled or changed while using with HDMI
 467                  */
 468                 pin_out = PIN_OUT;
 469
 470         snd_hda_codec_write(codec, pin_nid, 0,
 471                             AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
 472 }
 473
 474 /*
 475  * ELD proc files
 476  */
 477
 478 #ifdef CONFIG_SND_PROC_FS
 479 static void print_eld_info(struct snd_info_entry *entry,
 480                            struct snd_info_buffer *buffer)
 481 {
 482         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 483
 484         mutex_lock(&per_pin->lock);
 485         snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
 486         mutex_unlock(&per_pin->lock);
 487 }
 488
 489 static void write_eld_info(struct snd_info_entry *entry,
 490                            struct snd_info_buffer *buffer)
 491 {
 492         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 493
 494         mutex_lock(&per_pin->lock);
 495         snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
 496         mutex_unlock(&per_pin->lock);
 497 }
 498
 499 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
 500 {
 501         char name[32];
 502         struct hda_codec *codec = per_pin->codec;
 503         struct snd_info_entry *entry;
 504         int err;
 505
 506         snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
 507         err = snd_card_proc_new(codec->card, name, &entry);
 508         if (err < 0)
 509                 return err;
 510
 511         snd_info_set_text_ops(entry, per_pin, print_eld_info);
 512         entry->c.text.write = write_eld_info;
 513         entry->mode |= S_IWUSR;
 514         per_pin->proc_entry = entry;
 515
 516         return 0;
 517 }
 518
 519 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 520 {
 521         if (!per_pin->codec->bus->shutdown) {
 522                 snd_info_free_entry(per_pin->proc_entry);
 523                 per_pin->proc_entry = NULL;
 524         }
 525 }
 526 #else
 527 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
 528                                int index)
 529 {
 530         return 0;
 531 }
 532 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 533 {
 534 }
 535 #endif
 536
 537 /*
 538  * Audio InfoFrame routines
 539  */
 540
 541 /*
 542  * Enable Audio InfoFrame Transmission
 543  */
 544 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
 545                                        hda_nid_t pin_nid)
 546 {
 547         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 548         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 549                                                 AC_DIPXMIT_BEST);
 550 }
 551
 552 /*
 553  * Disable Audio InfoFrame Transmission
 554  */
 555 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
 556                                       hda_nid_t pin_nid)
 557 {
 558         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 559         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 560                                                 AC_DIPXMIT_DISABLE);
 561 }
 562
 563 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
 564 {
 565 #ifdef CONFIG_SND_DEBUG_VERBOSE
 566         int i;
 567         int size;
 568
 569         size = snd_hdmi_get_eld_size(codec, pin_nid);
 570         codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
 571
 572         for (i = 0; i < 8; i++) {
 573                 size = snd_hda_codec_read(codec, pin_nid, 0,
 574                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
 575                 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
 576         }
 577 #endif
 578 }
 579
 580 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
 581 {
 582 #ifdef BE_PARANOID
 583         int i, j;
 584         int size;
 585         int pi, bi;
 586         for (i = 0; i < 8; i++) {
 587                 size = snd_hda_codec_read(codec, pin_nid, 0,
 588                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
 589                 if (size == 0)
 590                         continue;
 591
 592                 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
 593                 for (j = 1; j < 1000; j++) {
 594                         hdmi_write_dip_byte(codec, pin_nid, 0x0);
 595                         hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
 596                         if (pi != i)
 597                                 codec_dbg(codec, "dip index %d: %d != %d\n",
 598                                                 bi, pi, i);
 599                         if (bi == 0) /* byte index wrapped around */
 600                                 break;
 601                 }
 602                 codec_dbg(codec,
 603                         "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
 604                         i, size, j);
 605         }
 606 #endif
 607 }
 608
 609 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
 610 {
 611         u8 *bytes = (u8 *)hdmi_ai;
 612         u8 sum = 0;
 613         int i;
 614
 615         hdmi_ai->checksum = 0;
 616
 617         for (i = 0; i < sizeof(*hdmi_ai); i++)
 618                 sum += bytes[i];
 619
 620         hdmi_ai->checksum = -sum;
 621 }
 622
 623 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
 624                                       hda_nid_t pin_nid,
 625                                       u8 *dip, int size)
 626 {
 627         int i;
 628
 629         hdmi_debug_dip_size(codec, pin_nid);
 630         hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
 631
 632         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 633         for (i = 0; i < size; i++)
 634                 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
 635 }
 636
 637 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
 638                                     u8 *dip, int size)
 639 {
 640         u8 val;
 641         int i;
 642
 643         if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
 644                                                             != AC_DIPXMIT_BEST)
 645                 return false;
 646
 647         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 648         for (i = 0; i < size; i++) {
 649                 val = snd_hda_codec_read(codec, pin_nid, 0,
 650                                          AC_VERB_GET_HDMI_DIP_DATA, 0);
 651                 if (val != dip[i])
 652                         return false;
 653         }
 654
 655         return true;
 656 }
 657
 658 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
 659                                      hda_nid_t pin_nid,
 660                                      int ca, int active_channels,
 661                                      int conn_type)
 662 {
 663         union audio_infoframe ai;
 664
 665         memset(&ai, 0, sizeof(ai));
 666         if (conn_type == 0) { /* HDMI */
 667                 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
 668
 669                 hdmi_ai->type           = 0x84;
 670                 hdmi_ai->ver            = 0x01;
 671                 hdmi_ai->len            = 0x0a;
 672                 hdmi_ai->CC02_CT47      = active_channels - 1;
 673                 hdmi_ai->CA             = ca;
 674                 hdmi_checksum_audio_infoframe(hdmi_ai);
 675         } else if (conn_type == 1) { /* DisplayPort */
 676                 struct dp_audio_infoframe *dp_ai = &ai.dp;
 677
 678                 dp_ai->type             = 0x84;
 679                 dp_ai->len              = 0x1b;
 680                 dp_ai->ver              = 0x11 << 2;
 681                 dp_ai->CC02_CT47        = active_channels - 1;
 682                 dp_ai->CA               = ca;
 683         } else {
 684                 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
 685                             pin_nid);
 686                 return;
 687         }
 688
 689         /*
 690          * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
 691          * sizeof(*dp_ai) to avoid partial match/update problems when
 692          * the user switches between HDMI/DP monitors.
 693          */
 694         if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
 695                                         sizeof(ai))) {
 696                 codec_dbg(codec,
 697                           "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
 698                             pin_nid,
 699                             active_channels, ca);
 700                 hdmi_stop_infoframe_trans(codec, pin_nid);
 701                 hdmi_fill_audio_infoframe(codec, pin_nid,
 702                                             ai.bytes, sizeof(ai));
 703                 hdmi_start_infoframe_trans(codec, pin_nid);
 704         }
 705 }
 706
 707 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
 708                                        struct hdmi_spec_per_pin *per_pin,
 709                                        bool non_pcm)
 710 {
 711         struct hdmi_spec *spec = codec->spec;
 712         struct hdac_chmap *chmap = &spec->chmap;
 713         hda_nid_t pin_nid = per_pin->pin_nid;
 714         int channels = per_pin->channels;
 715         int active_channels;
 716         struct hdmi_eld *eld;
 717         int ca;
 718
 719         if (!channels)
 720                 return;
 721
 722         /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
 723         if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
 724                 snd_hda_codec_write(codec, pin_nid, 0,
 725                                             AC_VERB_SET_AMP_GAIN_MUTE,
 726                                             AMP_OUT_UNMUTE);
 727
 728         eld = &per_pin->sink_eld;
 729
 730         ca = snd_hdac_channel_allocation(&codec->core,
 731                         eld->info.spk_alloc, channels,
 732                         per_pin->chmap_set, non_pcm, per_pin->chmap);
 733
 734         active_channels = snd_hdac_get_active_channels(ca);
 735
 736         chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
 737                                                 active_channels);
 738
 739         /*
 740          * always configure channel mapping, it may have been changed by the
 741          * user in the meantime
 742          */
 743         snd_hdac_setup_channel_mapping(&spec->chmap,
 744                                 pin_nid, non_pcm, ca, channels,
 745                                 per_pin->chmap, per_pin->chmap_set);
 746
 747         spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
 748                                       eld->info.conn_type);
 749
 750         per_pin->non_pcm = non_pcm;
 751 }
 752
 753 /*
 754  * Unsolicited events
 755  */
 756
 757 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
 758
 759 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
 760                                       int dev_id)
 761 {
 762         struct hdmi_spec *spec = codec->spec;
 763         int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
 764
 765         if (pin_idx < 0)
 766                 return;
 767         if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
 768                 snd_hda_jack_report_sync(codec);
 769 }
 770
 771 static void jack_callback(struct hda_codec *codec,
 772                           struct hda_jack_callback *jack)
 773 {
 774         /* hda_jack don't support DP MST */
 775         check_presence_and_report(codec, jack->nid, 0);
 776 }
 777
 778 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
 779 {
 780         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
 781         struct hda_jack_tbl *jack;
 782         int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
 783
 784         /*
 785          * assume DP MST uses dyn_pcm_assign and acomp and
 786          * never comes here
 787          * if DP MST supports unsol event, below code need
 788          * consider dev_entry
 789          */
 790         jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
 791         if (!jack)
 792                 return;
 793         jack->jack_dirty = 1;
 794
 795         codec_dbg(codec,
 796                 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
 797                 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
 798                 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
 799
 800         /* hda_jack don't support DP MST */
 801         check_presence_and_report(codec, jack->nid, 0);
 802 }
 803
 804 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
 805 {
 806         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
 807         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
 808         int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
 809         int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
 810
 811         codec_info(codec,
 812                 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
 813                 codec->addr,
 814                 tag,
 815                 subtag,
 816                 cp_state,
 817                 cp_ready);
 818
 819         /* TODO */
 820         if (cp_state)
 821                 ;
 822         if (cp_ready)
 823                 ;
 824 }
 825
 826
 827 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
 828 {
 829         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
 830         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
 831
 832         if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
 833                 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
 834                 return;
 835         }
 836
 837         if (subtag == 0)
 838                 hdmi_intrinsic_event(codec, res);
 839         else
 840                 hdmi_non_intrinsic_event(codec, res);
 841 }
 842
 843 static void haswell_verify_D0(struct hda_codec *codec,
 844                 hda_nid_t cvt_nid, hda_nid_t nid)
 845 {
 846         int pwr;
 847
 848         /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
 849          * thus pins could only choose converter 0 for use. Make sure the
 850          * converters are in correct power state */
 851         if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
 852                 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
 853
 854         if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
 855                 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
 856                                     AC_PWRST_D0);
 857                 msleep(40);
 858                 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
 859                 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
 860                 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
 861         }
 862 }
 863
 864 /*
 865  * Callbacks
 866  */
 867
 868 /* HBR should be Non-PCM, 8 channels */
 869 #define is_hbr_format(format) \
 870         ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
 871
 872 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
 873                               bool hbr)
 874 {
 875         int pinctl, new_pinctl;
 876
 877         if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
 878                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
 879                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
 880
 881                 if (pinctl < 0)
 882                         return hbr ? -EINVAL : 0;
 883
 884                 new_pinctl = pinctl & ~AC_PINCTL_EPT;
 885                 if (hbr)
 886                         new_pinctl |= AC_PINCTL_EPT_HBR;
 887                 else
 888                         new_pinctl |= AC_PINCTL_EPT_NATIVE;
 889
 890                 codec_dbg(codec,
 891                           "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
 892                             pin_nid,
 893                             pinctl == new_pinctl ? "" : "new-",
 894                             new_pinctl);
 895
 896                 if (pinctl != new_pinctl)
 897                         snd_hda_codec_write(codec, pin_nid, 0,
 898                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
 899                                             new_pinctl);
 900         } else if (hbr)
 901                 return -EINVAL;
 902
 903         return 0;
 904 }
 905
 906 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
 907                               hda_nid_t pin_nid, u32 stream_tag, int format)
 908 {
 909         struct hdmi_spec *spec = codec->spec;
 910         unsigned int param;
 911         int err;
 912
 913         err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
 914
 915         if (err) {
 916                 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
 917                 return err;
 918         }
 919
 920         if (is_haswell_plus(codec)) {
 921
 922                 /*
 923                  * on recent platforms IEC Coding Type is required for HBR
 924                  * support, read current Digital Converter settings and set
 925                  * ICT bitfield if needed.
 926                  */
 927                 param = snd_hda_codec_read(codec, cvt_nid, 0,
 928                                            AC_VERB_GET_DIGI_CONVERT_1, 0);
 929
 930                 param = (param >> 16) & ~(AC_DIG3_ICT);
 931
 932                 /* on recent platforms ICT mode is required for HBR support */
 933                 if (is_hbr_format(format))
 934                         param |= 0x1;
 935
 936                 snd_hda_codec_write(codec, cvt_nid, 0,
 937                                     AC_VERB_SET_DIGI_CONVERT_3, param);
 938         }
 939
 940         snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
 941         return 0;
 942 }
 943
 944 /* Try to find an available converter
 945  * If pin_idx is less then zero, just try to find an available converter.
 946  * Otherwise, try to find an available converter and get the cvt mux index
 947  * of the pin.
 948  */
 949 static int hdmi_choose_cvt(struct hda_codec *codec,
 950                            int pin_idx, int *cvt_id)
 951 {
 952         struct hdmi_spec *spec = codec->spec;
 953         struct hdmi_spec_per_pin *per_pin;
 954         struct hdmi_spec_per_cvt *per_cvt = NULL;
 955         int cvt_idx, mux_idx = 0;
 956
 957         /* pin_idx < 0 means no pin will be bound to the converter */
 958         if (pin_idx < 0)
 959                 per_pin = NULL;
 960         else
 961                 per_pin = get_pin(spec, pin_idx);
 962
 963         /* Dynamically assign converter to stream */
 964         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
 965                 per_cvt = get_cvt(spec, cvt_idx);
 966
 967                 /* Must not already be assigned */
 968                 if (per_cvt->assigned)
 969                         continue;
 970                 if (per_pin == NULL)
 971                         break;
 972                 /* Must be in pin's mux's list of converters */
 973                 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
 974                         if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
 975                                 break;
 976                 /* Not in mux list */
 977                 if (mux_idx == per_pin->num_mux_nids)
 978                         continue;
 979                 break;
 980         }
 981
 982         /* No free converters */
 983         if (cvt_idx == spec->num_cvts)
 984                 return -EBUSY;
 985
 986         if (per_pin != NULL)
 987                 per_pin->mux_idx = mux_idx;
 988
 989         if (cvt_id)
 990                 *cvt_id = cvt_idx;
 991
 992         return 0;
 993 }
 994
 995 /* Assure the pin select the right convetor */
 996 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
 997                         struct hdmi_spec_per_pin *per_pin)
 998 {
 999         hda_nid_t pin_nid = per_pin->pin_nid;
1000         int mux_idx, curr;
1001
1002         mux_idx = per_pin->mux_idx;
1003         curr = snd_hda_codec_read(codec, pin_nid, 0,
1004                                           AC_VERB_GET_CONNECT_SEL, 0);
1005         if (curr != mux_idx)
1006                 snd_hda_codec_write_cache(codec, pin_nid, 0,
1007                                             AC_VERB_SET_CONNECT_SEL,
1008                                             mux_idx);
1009 }
1010
1011 /* get the mux index for the converter of the pins
1012  * converter's mux index is the same for all pins on Intel platform
1013  */
1014 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1015                         hda_nid_t cvt_nid)
1016 {
1017         int i;
1018
1019         for (i = 0; i < spec->num_cvts; i++)
1020                 if (spec->cvt_nids[i] == cvt_nid)
1021                         return i;
1022         return -EINVAL;
1023 }
1024
1025 /* Intel HDMI workaround to fix audio routing issue:
1026  * For some Intel display codecs, pins share the same connection list.
1027  * So a conveter can be selected by multiple pins and playback on any of these
1028  * pins will generate sound on the external display, because audio flows from
1029  * the same converter to the display pipeline. Also muting one pin may make
1030  * other pins have no sound output.
1031  * So this function assures that an assigned converter for a pin is not selected
1032  * by any other pins.
1033  */
1034 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1035                                          hda_nid_t pin_nid,
1036                                          int dev_id, int mux_idx)
1037 {
1038         struct hdmi_spec *spec = codec->spec;
1039         hda_nid_t nid;
1040         int cvt_idx, curr;
1041         struct hdmi_spec_per_cvt *per_cvt;
1042         struct hdmi_spec_per_pin *per_pin;
1043         int pin_idx;
1044
1045         /* configure the pins connections */
1046         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1047                 int dev_id_saved;
1048                 int dev_num;
1049
1050                 per_pin = get_pin(spec, pin_idx);
1051                 /*
1052                  * pin not connected to monitor
1053                  * no need to operate on it
1054                  */
1055                 if (!per_pin->pcm)
1056                         continue;
1057
1058                 if ((per_pin->pin_nid == pin_nid) &&
1059                         (per_pin->dev_id == dev_id))
1060                         continue;
1061
1062                 /*
1063                  * if per_pin->dev_id >= dev_num,
1064                  * snd_hda_get_dev_select() will fail,
1065                  * and the following operation is unpredictable.
1066                  * So skip this situation.
1067                  */
1068                 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1069                 if (per_pin->dev_id >= dev_num)
1070                         continue;
1071
1072                 nid = per_pin->pin_nid;
1073
1074                 /*
1075                  * Calling this function should not impact
1076                  * on the device entry selection
1077                  * So let's save the dev id for each pin,
1078                  * and restore it when return
1079                  */
1080                 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1081                 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1082                 curr = snd_hda_codec_read(codec, nid, 0,
1083                                           AC_VERB_GET_CONNECT_SEL, 0);
1084                 if (curr != mux_idx) {
1085                         snd_hda_set_dev_select(codec, nid, dev_id_saved);
1086                         continue;
1087                 }
1088
1089
1090                 /* choose an unassigned converter. The conveters in the
1091                  * connection list are in the same order as in the codec.
1092                  */
1093                 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1094                         per_cvt = get_cvt(spec, cvt_idx);
1095                         if (!per_cvt->assigned) {
1096                                 codec_dbg(codec,
1097                                           "choose cvt %d for pin nid %d\n",
1098                                         cvt_idx, nid);
1099                                 snd_hda_codec_write_cache(codec, nid, 0,
1100                                             AC_VERB_SET_CONNECT_SEL,
1101                                             cvt_idx);
1102                                 break;
1103                         }
1104                 }
1105                 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1106         }
1107 }
1108
1109 /* A wrapper of intel_not_share_asigned_cvt() */
1110 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1111                         hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1112 {
1113         int mux_idx;
1114         struct hdmi_spec *spec = codec->spec;
1115
1116         /* On Intel platform, the mapping of converter nid to
1117          * mux index of the pins are always the same.
1118          * The pin nid may be 0, this means all pins will not
1119          * share the converter.
1120          */
1121         mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1122         if (mux_idx >= 0)
1123                 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1124 }
1125
1126 /* skeleton caller of pin_cvt_fixup ops */
1127 static void pin_cvt_fixup(struct hda_codec *codec,
1128                           struct hdmi_spec_per_pin *per_pin,
1129                           hda_nid_t cvt_nid)
1130 {
1131         struct hdmi_spec *spec = codec->spec;
1132
1133         if (spec->ops.pin_cvt_fixup)
1134                 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1135 }
1136
1137 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1138  * in dyn_pcm_assign mode.
1139  */
1140 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1141                          struct hda_codec *codec,
1142                          struct snd_pcm_substream *substream)
1143 {
1144         struct hdmi_spec *spec = codec->spec;
1145         struct snd_pcm_runtime *runtime = substream->runtime;
1146         int cvt_idx, pcm_idx;
1147         struct hdmi_spec_per_cvt *per_cvt = NULL;
1148         int err;
1149
1150         pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1151         if (pcm_idx < 0)
1152                 return -EINVAL;
1153
1154         err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1155         if (err)
1156                 return err;
1157
1158         per_cvt = get_cvt(spec, cvt_idx);
1159         per_cvt->assigned = 1;
1160         hinfo->nid = per_cvt->cvt_nid;
1161
1162         pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1163
1164         set_bit(pcm_idx, &spec->pcm_in_use);
1165         /* todo: setup spdif ctls assign */
1166
1167         /* Initially set the converter's capabilities */
1168         hinfo->channels_min = per_cvt->channels_min;
1169         hinfo->channels_max = per_cvt->channels_max;
1170         hinfo->rates = per_cvt->rates;
1171         hinfo->formats = per_cvt->formats;
1172         hinfo->maxbps = per_cvt->maxbps;
1173
1174         /* Store the updated parameters */
1175         runtime->hw.channels_min = hinfo->channels_min;
1176         runtime->hw.channels_max = hinfo->channels_max;
1177         runtime->hw.formats = hinfo->formats;
1178         runtime->hw.rates = hinfo->rates;
1179
1180         snd_pcm_hw_constraint_step(substream->runtime, 0,
1181                                    SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1182         return 0;
1183 }
1184
1185 /*
1186  * HDA PCM callbacks
1187  */
1188 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1189                          struct hda_codec *codec,
1190                          struct snd_pcm_substream *substream)
1191 {
1192         struct hdmi_spec *spec = codec->spec;
1193         struct snd_pcm_runtime *runtime = substream->runtime;
1194         int pin_idx, cvt_idx, pcm_idx;
1195         struct hdmi_spec_per_pin *per_pin;
1196         struct hdmi_eld *eld;
1197         struct hdmi_spec_per_cvt *per_cvt = NULL;
1198         int err;
1199
1200         /* Validate hinfo */
1201         pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1202         if (pcm_idx < 0)
1203                 return -EINVAL;
1204
1205         mutex_lock(&spec->pcm_lock);
1206         pin_idx = hinfo_to_pin_index(codec, hinfo);
1207         if (!spec->dyn_pcm_assign) {
1208                 if (snd_BUG_ON(pin_idx < 0)) {
1209                         mutex_unlock(&spec->pcm_lock);
1210                         return -EINVAL;
1211                 }
1212         } else {
1213                 /* no pin is assigned to the PCM
1214                  * PA need pcm open successfully when probe
1215                  */
1216                 if (pin_idx < 0) {
1217                         err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1218                         mutex_unlock(&spec->pcm_lock);
1219                         return err;
1220                 }
1221         }
1222
1223         err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1224         if (err < 0) {
1225                 mutex_unlock(&spec->pcm_lock);
1226                 return err;
1227         }
1228
1229         per_cvt = get_cvt(spec, cvt_idx);
1230         /* Claim converter */
1231         per_cvt->assigned = 1;
1232
1233         set_bit(pcm_idx, &spec->pcm_in_use);
1234         per_pin = get_pin(spec, pin_idx);
1235         per_pin->cvt_nid = per_cvt->cvt_nid;
1236         hinfo->nid = per_cvt->cvt_nid;
1237
1238         snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1239         snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1240                             AC_VERB_SET_CONNECT_SEL,
1241                             per_pin->mux_idx);
1242
1243         /* configure unused pins to choose other converters */
1244         pin_cvt_fixup(codec, per_pin, 0);
1245
1246         snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1247
1248         /* Initially set the converter's capabilities */
1249         hinfo->channels_min = per_cvt->channels_min;
1250         hinfo->channels_max = per_cvt->channels_max;
1251         hinfo->rates = per_cvt->rates;
1252         hinfo->formats = per_cvt->formats;
1253         hinfo->maxbps = per_cvt->maxbps;
1254
1255         eld = &per_pin->sink_eld;
1256         /* Restrict capabilities by ELD if this isn't disabled */
1257         if (!static_hdmi_pcm && eld->eld_valid) {
1258                 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1259                 if (hinfo->channels_min > hinfo->channels_max ||
1260                     !hinfo->rates || !hinfo->formats) {
1261                         per_cvt->assigned = 0;
1262                         hinfo->nid = 0;
1263                         snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1264                         mutex_unlock(&spec->pcm_lock);
1265                         return -ENODEV;
1266                 }
1267         }
1268
1269         mutex_unlock(&spec->pcm_lock);
1270         /* Store the updated parameters */
1271         runtime->hw.channels_min = hinfo->channels_min;
1272         runtime->hw.channels_max = hinfo->channels_max;
1273         runtime->hw.formats = hinfo->formats;
1274         runtime->hw.rates = hinfo->rates;
1275
1276         snd_pcm_hw_constraint_step(substream->runtime, 0,
1277                                    SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1278         return 0;
1279 }
1280
1281 /*
1282  * HDA/HDMI auto parsing
1283  */
1284 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1285 {
1286         struct hdmi_spec *spec = codec->spec;
1287         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1288         hda_nid_t pin_nid = per_pin->pin_nid;
1289
1290         if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1291                 codec_warn(codec,
1292                            "HDMI: pin %d wcaps %#x does not support connection list\n",
1293                            pin_nid, get_wcaps(codec, pin_nid));
1294                 return -EINVAL;
1295         }
1296
1297         /* all the device entries on the same pin have the same conn list */
1298         per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1299                                                         per_pin->mux_nids,
1300                                                         HDA_MAX_CONNECTIONS);
1301
1302         return 0;
1303 }
1304
1305 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1306                                 struct hdmi_spec_per_pin *per_pin)
1307 {
1308         int i;
1309
1310         /* try the prefer PCM */
1311         if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1312                 return per_pin->pin_nid_idx;
1313
1314         /* have a second try; check the "reserved area" over num_pins */
1315         for (i = spec->num_nids; i < spec->pcm_used; i++) {
1316                 if (!test_bit(i, &spec->pcm_bitmap))
1317                         return i;
1318         }
1319
1320         /* the last try; check the empty slots in pins */
1321         for (i = 0; i < spec->num_nids; i++) {
1322                 if (!test_bit(i, &spec->pcm_bitmap))
1323                         return i;
1324         }
1325         return -EBUSY;
1326 }
1327
1328 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1329                                 struct hdmi_spec_per_pin *per_pin)
1330 {
1331         int idx;
1332
1333         /* pcm already be attached to the pin */
1334         if (per_pin->pcm)
1335                 return;
1336         idx = hdmi_find_pcm_slot(spec, per_pin);
1337         if (idx == -EBUSY)
1338                 return;
1339         per_pin->pcm_idx = idx;
1340         per_pin->pcm = get_hdmi_pcm(spec, idx);
1341         set_bit(idx, &spec->pcm_bitmap);
1342 }
1343
1344 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1345                                 struct hdmi_spec_per_pin *per_pin)
1346 {
1347         int idx;
1348
1349         /* pcm already be detached from the pin */
1350         if (!per_pin->pcm)
1351                 return;
1352         idx = per_pin->pcm_idx;
1353         per_pin->pcm_idx = -1;
1354         per_pin->pcm = NULL;
1355         if (idx >= 0 && idx < spec->pcm_used)
1356                 clear_bit(idx, &spec->pcm_bitmap);
1357 }
1358
1359 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1360                 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1361 {
1362         int mux_idx;
1363
1364         for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1365                 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1366                         break;
1367         return mux_idx;
1368 }
1369
1370 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1371
1372 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1373                            struct hdmi_spec_per_pin *per_pin)
1374 {
1375         struct hda_codec *codec = per_pin->codec;
1376         struct hda_pcm *pcm;
1377         struct hda_pcm_stream *hinfo;
1378         struct snd_pcm_substream *substream;
1379         int mux_idx;
1380         bool non_pcm;
1381
1382         if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1383                 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1384         else
1385                 return;
1386         if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1387                 return;
1388
1389         /* hdmi audio only uses playback and one substream */
1390         hinfo = pcm->stream;
1391         substream = pcm->pcm->streams[0].substream;
1392
1393         per_pin->cvt_nid = hinfo->nid;
1394
1395         mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1396         if (mux_idx < per_pin->num_mux_nids) {
1397                 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1398                                    per_pin->dev_id);
1399                 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1400                                 AC_VERB_SET_CONNECT_SEL,
1401                                 mux_idx);
1402         }
1403         snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1404
1405         non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1406         if (substream->runtime)
1407                 per_pin->channels = substream->runtime->channels;
1408         per_pin->setup = true;
1409         per_pin->mux_idx = mux_idx;
1410
1411         hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1412 }
1413
1414 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1415                            struct hdmi_spec_per_pin *per_pin)
1416 {
1417         if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1418                 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1419
1420         per_pin->chmap_set = false;
1421         memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1422
1423         per_pin->setup = false;
1424         per_pin->channels = 0;
1425 }
1426
1427 /* update per_pin ELD from the given new ELD;
1428  * setup info frame and notification accordingly
1429  */
1430 static void update_eld(struct hda_codec *codec,
1431                        struct hdmi_spec_per_pin *per_pin,
1432                        struct hdmi_eld *eld)
1433 {
1434         struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1435         struct hdmi_spec *spec = codec->spec;
1436         bool old_eld_valid = pin_eld->eld_valid;
1437         bool eld_changed;
1438         int pcm_idx = -1;
1439
1440         /* for monitor disconnection, save pcm_idx firstly */
1441         pcm_idx = per_pin->pcm_idx;
1442         if (spec->dyn_pcm_assign) {
1443                 if (eld->eld_valid) {
1444                         hdmi_attach_hda_pcm(spec, per_pin);
1445                         hdmi_pcm_setup_pin(spec, per_pin);
1446                 } else {
1447                         hdmi_pcm_reset_pin(spec, per_pin);
1448                         hdmi_detach_hda_pcm(spec, per_pin);
1449                 }
1450         }
1451         /* if pcm_idx == -1, it means this is in monitor connection event
1452          * we can get the correct pcm_idx now.
1453          */
1454         if (pcm_idx == -1)
1455                 pcm_idx = per_pin->pcm_idx;
1456
1457         if (eld->eld_valid)
1458                 snd_hdmi_show_eld(codec, &eld->info);
1459
1460         eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1461         if (eld->eld_valid && pin_eld->eld_valid)
1462                 if (pin_eld->eld_size != eld->eld_size ||
1463                     memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1464                            eld->eld_size) != 0)
1465                         eld_changed = true;
1466
1467         pin_eld->monitor_present = eld->monitor_present;
1468         pin_eld->eld_valid = eld->eld_valid;
1469         pin_eld->eld_size = eld->eld_size;
1470         if (eld->eld_valid)
1471                 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1472         pin_eld->info = eld->info;
1473
1474         /*
1475          * Re-setup pin and infoframe. This is needed e.g. when
1476          * - sink is first plugged-in
1477          * - transcoder can change during stream playback on Haswell
1478          *   and this can make HW reset converter selection on a pin.
1479          */
1480         if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1481                 pin_cvt_fixup(codec, per_pin, 0);
1482                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1483         }
1484
1485         if (eld_changed && pcm_idx >= 0)
1486                 snd_ctl_notify(codec->card,
1487                                SNDRV_CTL_EVENT_MASK_VALUE |
1488                                SNDRV_CTL_EVENT_MASK_INFO,
1489                                &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1490 }
1491
1492 /* update ELD and jack state via HD-audio verbs */
1493 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1494                                          int repoll)
1495 {
1496         struct hda_jack_tbl *jack;
1497         struct hda_codec *codec = per_pin->codec;
1498         struct hdmi_spec *spec = codec->spec;
1499         struct hdmi_eld *eld = &spec->temp_eld;
1500         hda_nid_t pin_nid = per_pin->pin_nid;
1501         /*
1502          * Always execute a GetPinSense verb here, even when called from
1503          * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1504          * response's PD bit is not the real PD value, but indicates that
1505          * the real PD value changed. An older version of the HD-audio
1506          * specification worked this way. Hence, we just ignore the data in
1507          * the unsolicited response to avoid custom WARs.
1508          */
1509         int present;
1510         bool ret;
1511         bool do_repoll = false;
1512
1513         present = snd_hda_pin_sense(codec, pin_nid);
1514
1515         mutex_lock(&per_pin->lock);
1516         eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1517         if (eld->monitor_present)
1518                 eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1519         else
1520                 eld->eld_valid = false;
1521
1522         codec_dbg(codec,
1523                 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1524                 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1525
1526         if (eld->eld_valid) {
1527                 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1528                                                      &eld->eld_size) < 0)
1529                         eld->eld_valid = false;
1530                 else {
1531                         if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1532                                                     eld->eld_size) < 0)
1533                                 eld->eld_valid = false;
1534                 }
1535                 if (!eld->eld_valid && repoll)
1536                         do_repoll = true;
1537         }
1538
1539         if (do_repoll)
1540                 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1541         else
1542                 update_eld(codec, per_pin, eld);
1543
1544         ret = !repoll || !eld->monitor_present || eld->eld_valid;
1545
1546         jack = snd_hda_jack_tbl_get(codec, pin_nid);
1547         if (jack)
1548                 jack->block_report = !ret;
1549
1550         mutex_unlock(&per_pin->lock);
1551         return ret;
1552 }
1553
1554 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1555                                  struct hdmi_spec_per_pin *per_pin)
1556 {
1557         struct hdmi_spec *spec = codec->spec;
1558         struct snd_jack *jack = NULL;
1559         struct hda_jack_tbl *jack_tbl;
1560
1561         /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1562          * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1563          * NULL even after snd_hda_jack_tbl_clear() is called to
1564          * free snd_jack. This may cause access invalid memory
1565          * when calling snd_jack_report
1566          */
1567         if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1568                 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1569         else if (!spec->dyn_pcm_assign) {
1570                 /*
1571                  * jack tbl doesn't support DP MST
1572                  * DP MST will use dyn_pcm_assign,
1573                  * so DP MST will never come here
1574                  */
1575                 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1576                 if (jack_tbl)
1577                         jack = jack_tbl->jack;
1578         }
1579         return jack;
1580 }
1581
1582 /* update ELD and jack state via audio component */
1583 static void sync_eld_via_acomp(struct hda_codec *codec,
1584                                struct hdmi_spec_per_pin *per_pin)
1585 {
1586         struct hdmi_spec *spec = codec->spec;
1587         struct hdmi_eld *eld = &spec->temp_eld;
1588         struct snd_jack *jack = NULL;
1589         int size;
1590
1591         mutex_lock(&per_pin->lock);
1592         eld->monitor_present = false;
1593         size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1594                                       per_pin->dev_id, &eld->monitor_present,
1595                                       eld->eld_buffer, ELD_MAX_SIZE);
1596         if (size > 0) {
1597                 size = min(size, ELD_MAX_SIZE);
1598                 if (snd_hdmi_parse_eld(codec, &eld->info,
1599                                        eld->eld_buffer, size) < 0)
1600                         size = -EINVAL;
1601         }
1602
1603         if (size > 0) {
1604                 eld->eld_valid = true;
1605                 eld->eld_size = size;
1606         } else {
1607                 eld->eld_valid = false;
1608                 eld->eld_size = 0;
1609         }
1610
1611         /* pcm_idx >=0 before update_eld() means it is in monitor
1612          * disconnected event. Jack must be fetched before update_eld()
1613          */
1614         jack = pin_idx_to_jack(codec, per_pin);
1615         update_eld(codec, per_pin, eld);
1616         if (jack == NULL)
1617                 jack = pin_idx_to_jack(codec, per_pin);
1618         if (jack == NULL)
1619                 goto unlock;
1620         snd_jack_report(jack,
1621                         eld->monitor_present ? SND_JACK_AVOUT : 0);
1622  unlock:
1623         mutex_unlock(&per_pin->lock);
1624 }
1625
1626 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1627 {
1628         struct hda_codec *codec = per_pin->codec;
1629         struct hdmi_spec *spec = codec->spec;
1630         int ret;
1631
1632         /* no temporary power up/down needed for component notifier */
1633         if (!codec_has_acomp(codec))
1634                 snd_hda_power_up_pm(codec);
1635
1636         mutex_lock(&spec->pcm_lock);
1637         if (codec_has_acomp(codec)) {
1638                 sync_eld_via_acomp(codec, per_pin);
1639                 ret = false; /* don't call snd_hda_jack_report_sync() */
1640         } else {
1641                 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1642         }
1643         mutex_unlock(&spec->pcm_lock);
1644
1645         if (!codec_has_acomp(codec))
1646                 snd_hda_power_down_pm(codec);
1647
1648         return ret;
1649 }
1650
1651 static void hdmi_repoll_eld(struct work_struct *work)
1652 {
1653         struct hdmi_spec_per_pin *per_pin =
1654         container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1655
1656         if (per_pin->repoll_count++ > 6)
1657                 per_pin->repoll_count = 0;
1658
1659         if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1660                 snd_hda_jack_report_sync(per_pin->codec);
1661 }
1662
1663 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1664                                              hda_nid_t nid);
1665
1666 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1667 {
1668         struct hdmi_spec *spec = codec->spec;
1669         unsigned int caps, config;
1670         int pin_idx;
1671         struct hdmi_spec_per_pin *per_pin;
1672         int err;
1673         int dev_num, i;
1674
1675         caps = snd_hda_query_pin_caps(codec, pin_nid);
1676         if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1677                 return 0;
1678
1679         /*
1680          * For DP MST audio, Configuration Default is the same for
1681          * all device entries on the same pin
1682          */
1683         config = snd_hda_codec_get_pincfg(codec, pin_nid);
1684         if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1685                 return 0;
1686
1687         /*
1688          * To simplify the implementation, malloc all
1689          * the virtual pins in the initialization statically
1690          */
1691         if (is_haswell_plus(codec)) {
1692                 /*
1693                  * On Intel platforms, device entries number is
1694                  * changed dynamically. If there is a DP MST
1695                  * hub connected, the device entries number is 3.
1696                  * Otherwise, it is 1.
1697                  * Here we manually set dev_num to 3, so that
1698                  * we can initialize all the device entries when
1699                  * bootup statically.
1700                  */
1701                 dev_num = 3;
1702                 spec->dev_num = 3;
1703         } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1704                 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1705                 /*
1706                  * spec->dev_num is the maxinum number of device entries
1707                  * among all the pins
1708                  */
1709                 spec->dev_num = (spec->dev_num > dev_num) ?
1710                         spec->dev_num : dev_num;
1711         } else {
1712                 /*
1713                  * If the platform doesn't support DP MST,
1714                  * manually set dev_num to 1. This means
1715                  * the pin has only one device entry.
1716                  */
1717                 dev_num = 1;
1718                 spec->dev_num = 1;
1719         }
1720
1721         for (i = 0; i < dev_num; i++) {
1722                 pin_idx = spec->num_pins;
1723                 per_pin = snd_array_new(&spec->pins);
1724
1725                 if (!per_pin)
1726                         return -ENOMEM;
1727
1728                 if (spec->dyn_pcm_assign) {
1729                         per_pin->pcm = NULL;
1730                         per_pin->pcm_idx = -1;
1731                 } else {
1732                         per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1733                         per_pin->pcm_idx = pin_idx;
1734                 }
1735                 per_pin->pin_nid = pin_nid;
1736                 per_pin->pin_nid_idx = spec->num_nids;
1737                 per_pin->dev_id = i;
1738                 per_pin->non_pcm = false;
1739                 snd_hda_set_dev_select(codec, pin_nid, i);
1740                 if (is_haswell_plus(codec))
1741                         intel_haswell_fixup_connect_list(codec, pin_nid);
1742                 err = hdmi_read_pin_conn(codec, pin_idx);
1743                 if (err < 0)
1744                         return err;
1745                 spec->num_pins++;
1746         }
1747         spec->num_nids++;
1748
1749         return 0;
1750 }
1751
1752 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1753 {
1754         struct hdmi_spec *spec = codec->spec;
1755         struct hdmi_spec_per_cvt *per_cvt;
1756         unsigned int chans;
1757         int err;
1758
1759         chans = get_wcaps(codec, cvt_nid);
1760         chans = get_wcaps_channels(chans);
1761
1762         per_cvt = snd_array_new(&spec->cvts);
1763         if (!per_cvt)
1764                 return -ENOMEM;
1765
1766         per_cvt->cvt_nid = cvt_nid;
1767         per_cvt->channels_min = 2;
1768         if (chans <= 16) {
1769                 per_cvt->channels_max = chans;
1770                 if (chans > spec->chmap.channels_max)
1771                         spec->chmap.channels_max = chans;
1772         }
1773
1774         err = snd_hda_query_supported_pcm(codec, cvt_nid,
1775                                           &per_cvt->rates,
1776                                           &per_cvt->formats,
1777                                           &per_cvt->maxbps);
1778         if (err < 0)
1779                 return err;
1780
1781         if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1782                 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1783         spec->num_cvts++;
1784
1785         return 0;
1786 }
1787
1788 static int hdmi_parse_codec(struct hda_codec *codec)
1789 {
1790         hda_nid_t nid;
1791         int i, nodes;
1792
1793         nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1794         if (!nid || nodes < 0) {
1795                 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1796                 return -EINVAL;
1797         }
1798
1799         for (i = 0; i < nodes; i++, nid++) {
1800                 unsigned int caps;
1801                 unsigned int type;
1802
1803                 caps = get_wcaps(codec, nid);
1804                 type = get_wcaps_type(caps);
1805
1806                 if (!(caps & AC_WCAP_DIGITAL))
1807                         continue;
1808
1809                 switch (type) {
1810                 case AC_WID_AUD_OUT:
1811                         hdmi_add_cvt(codec, nid);
1812                         break;
1813                 case AC_WID_PIN:
1814                         hdmi_add_pin(codec, nid);
1815                         break;
1816                 }
1817         }
1818
1819         return 0;
1820 }
1821
1822 /*
1823  */
1824 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1825 {
1826         struct hda_spdif_out *spdif;
1827         bool non_pcm;
1828
1829         mutex_lock(&codec->spdif_mutex);
1830         spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1831         /* Add sanity check to pass klockwork check.
1832          * This should never happen.
1833          */
1834         if (WARN_ON(spdif == NULL))
1835                 return true;
1836         non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1837         mutex_unlock(&codec->spdif_mutex);
1838         return non_pcm;
1839 }
1840
1841 /*
1842  * HDMI callbacks
1843  */
1844
1845 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1846                                            struct hda_codec *codec,
1847                                            unsigned int stream_tag,
1848                                            unsigned int format,
1849                                            struct snd_pcm_substream *substream)
1850 {
1851         hda_nid_t cvt_nid = hinfo->nid;
1852         struct hdmi_spec *spec = codec->spec;
1853         int pin_idx;
1854         struct hdmi_spec_per_pin *per_pin;
1855         hda_nid_t pin_nid;
1856         struct snd_pcm_runtime *runtime = substream->runtime;
1857         bool non_pcm;
1858         int pinctl;
1859         int err;
1860
1861         mutex_lock(&spec->pcm_lock);
1862         pin_idx = hinfo_to_pin_index(codec, hinfo);
1863         if (spec->dyn_pcm_assign && pin_idx < 0) {
1864                 /* when dyn_pcm_assign and pcm is not bound to a pin
1865                  * skip pin setup and return 0 to make audio playback
1866                  * be ongoing
1867                  */
1868                 pin_cvt_fixup(codec, NULL, cvt_nid);
1869                 snd_hda_codec_setup_stream(codec, cvt_nid,
1870                                         stream_tag, 0, format);
1871                 mutex_unlock(&spec->pcm_lock);
1872                 return 0;
1873         }
1874
1875         if (snd_BUG_ON(pin_idx < 0)) {
1876                 mutex_unlock(&spec->pcm_lock);
1877                 return -EINVAL;
1878         }
1879         per_pin = get_pin(spec, pin_idx);
1880         pin_nid = per_pin->pin_nid;
1881
1882         /* Verify pin:cvt selections to avoid silent audio after S3.
1883          * After S3, the audio driver restores pin:cvt selections
1884          * but this can happen before gfx is ready and such selection
1885          * is overlooked by HW. Thus multiple pins can share a same
1886          * default convertor and mute control will affect each other,
1887          * which can cause a resumed audio playback become silent
1888          * after S3.
1889          */
1890         pin_cvt_fixup(codec, per_pin, 0);
1891
1892         /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1893         /* Todo: add DP1.2 MST audio support later */
1894         if (codec_has_acomp(codec))
1895                 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1896                                          runtime->rate);
1897
1898         non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1899         mutex_lock(&per_pin->lock);
1900         per_pin->channels = substream->runtime->channels;
1901         per_pin->setup = true;
1902
1903         hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1904         mutex_unlock(&per_pin->lock);
1905         if (spec->dyn_pin_out) {
1906                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1907                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1908                 snd_hda_codec_write(codec, pin_nid, 0,
1909                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
1910                                     pinctl | PIN_OUT);
1911         }
1912
1913         /* snd_hda_set_dev_select() has been called before */
1914         err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1915                                  stream_tag, format);
1916         mutex_unlock(&spec->pcm_lock);
1917         return err;
1918 }
1919
1920 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1921                                              struct hda_codec *codec,
1922                                              struct snd_pcm_substream *substream)
1923 {
1924         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1925         return 0;
1926 }
1927
1928 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1929                           struct hda_codec *codec,
1930                           struct snd_pcm_substream *substream)
1931 {
1932         struct hdmi_spec *spec = codec->spec;
1933         int cvt_idx, pin_idx, pcm_idx;
1934         struct hdmi_spec_per_cvt *per_cvt;
1935         struct hdmi_spec_per_pin *per_pin;
1936         int pinctl;
1937
1938         if (hinfo->nid) {
1939                 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1940                 if (snd_BUG_ON(pcm_idx < 0))
1941                         return -EINVAL;
1942                 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1943                 if (snd_BUG_ON(cvt_idx < 0))
1944                         return -EINVAL;
1945                 per_cvt = get_cvt(spec, cvt_idx);
1946
1947                 snd_BUG_ON(!per_cvt->assigned);
1948                 per_cvt->assigned = 0;
1949                 hinfo->nid = 0;
1950
1951                 mutex_lock(&spec->pcm_lock);
1952                 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1953                 clear_bit(pcm_idx, &spec->pcm_in_use);
1954                 pin_idx = hinfo_to_pin_index(codec, hinfo);
1955                 if (spec->dyn_pcm_assign && pin_idx < 0) {
1956                         mutex_unlock(&spec->pcm_lock);
1957                         return 0;
1958                 }
1959
1960                 if (snd_BUG_ON(pin_idx < 0)) {
1961                         mutex_unlock(&spec->pcm_lock);
1962                         return -EINVAL;
1963                 }
1964                 per_pin = get_pin(spec, pin_idx);
1965
1966                 if (spec->dyn_pin_out) {
1967                         pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1968                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1969                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1970                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
1971                                             pinctl & ~PIN_OUT);
1972                 }
1973
1974                 mutex_lock(&per_pin->lock);
1975                 per_pin->chmap_set = false;
1976                 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1977
1978                 per_pin->setup = false;
1979                 per_pin->channels = 0;
1980                 mutex_unlock(&per_pin->lock);
1981                 mutex_unlock(&spec->pcm_lock);
1982         }
1983
1984         return 0;
1985 }
1986
1987 static const struct hda_pcm_ops generic_ops = {
1988         .open = hdmi_pcm_open,
1989         .close = hdmi_pcm_close,
1990         .prepare = generic_hdmi_playback_pcm_prepare,
1991         .cleanup = generic_hdmi_playback_pcm_cleanup,
1992 };
1993
1994 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
1995 {
1996         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1997         struct hdmi_spec *spec = codec->spec;
1998         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1999
2000         if (!per_pin)
2001                 return 0;
2002
2003         return per_pin->sink_eld.info.spk_alloc;
2004 }
2005
2006 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2007                                         unsigned char *chmap)
2008 {
2009         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2010         struct hdmi_spec *spec = codec->spec;
2011         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2012
2013         /* chmap is already set to 0 in caller */
2014         if (!per_pin)
2015                 return;
2016
2017         memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2018 }
2019
2020 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2021                                 unsigned char *chmap, int prepared)
2022 {
2023         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2024         struct hdmi_spec *spec = codec->spec;
2025         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2026
2027         if (!per_pin)
2028                 return;
2029         mutex_lock(&per_pin->lock);
2030         per_pin->chmap_set = true;
2031         memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2032         if (prepared)
2033                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2034         mutex_unlock(&per_pin->lock);
2035 }
2036
2037 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2038 {
2039         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2040         struct hdmi_spec *spec = codec->spec;
2041         struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2042
2043         return per_pin ? true:false;
2044 }
2045
2046 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2047 {
2048         struct hdmi_spec *spec = codec->spec;
2049         int idx;
2050
2051         /*
2052          * for non-mst mode, pcm number is the same as before
2053          * for DP MST mode, pcm number is (nid number + dev_num - 1)
2054          *  dev_num is the device entry number in a pin
2055          *
2056          */
2057         for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2058                 struct hda_pcm *info;
2059                 struct hda_pcm_stream *pstr;
2060
2061                 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2062                 if (!info)
2063                         return -ENOMEM;
2064
2065                 spec->pcm_rec[idx].pcm = info;
2066                 spec->pcm_used++;
2067                 info->pcm_type = HDA_PCM_TYPE_HDMI;
2068                 info->own_chmap = true;
2069
2070                 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2071                 pstr->substreams = 1;
2072                 pstr->ops = generic_ops;
2073                 /* pcm number is less than 16 */
2074                 if (spec->pcm_used >= 16)
2075                         break;
2076                 /* other pstr fields are set in open */
2077         }
2078
2079         return 0;
2080 }
2081
2082 static void free_hdmi_jack_priv(struct snd_jack *jack)
2083 {
2084         struct hdmi_pcm *pcm = jack->private_data;
2085
2086         pcm->jack = NULL;
2087 }
2088
2089 static int add_hdmi_jack_kctl(struct hda_codec *codec,
2090                                struct hdmi_spec *spec,
2091                                int pcm_idx,
2092                                const char *name)
2093 {
2094         struct snd_jack *jack;
2095         int err;
2096
2097         err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2098                            true, false);
2099         if (err < 0)
2100                 return err;
2101
2102         spec->pcm_rec[pcm_idx].jack = jack;
2103         jack->private_data = &spec->pcm_rec[pcm_idx];
2104         jack->private_free = free_hdmi_jack_priv;
2105         return 0;
2106 }
2107
2108 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2109 {
2110         char hdmi_str[32] = "HDMI/DP";
2111         struct hdmi_spec *spec = codec->spec;
2112         struct hdmi_spec_per_pin *per_pin;
2113         struct hda_jack_tbl *jack;
2114         int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2115         bool phantom_jack;
2116         int ret;
2117
2118         if (pcmdev > 0)
2119                 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2120
2121         if (spec->dyn_pcm_assign)
2122                 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2123
2124         /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2125         /* if !dyn_pcm_assign, it must be non-MST mode.
2126          * This means pcms and pins are statically mapped.
2127          * And pcm_idx is pin_idx.
2128          */
2129         per_pin = get_pin(spec, pcm_idx);
2130         phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2131         if (phantom_jack)
2132                 strncat(hdmi_str, " Phantom",
2133                         sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2134         ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2135                                     phantom_jack);
2136         if (ret < 0)
2137                 return ret;
2138         jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2139         if (jack == NULL)
2140                 return 0;
2141         /* assign jack->jack to pcm_rec[].jack to
2142          * align with dyn_pcm_assign mode
2143          */
2144         spec->pcm_rec[pcm_idx].jack = jack->jack;
2145         return 0;
2146 }
2147
2148 static int generic_hdmi_build_controls(struct hda_codec *codec)
2149 {
2150         struct hdmi_spec *spec = codec->spec;
2151         int dev, err;
2152         int pin_idx, pcm_idx;
2153
2154
2155         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2156                 err = generic_hdmi_build_jack(codec, pcm_idx);
2157                 if (err < 0)
2158                         return err;
2159
2160                 /* create the spdif for each pcm
2161                  * pin will be bound when monitor is connected
2162                  */
2163                 if (spec->dyn_pcm_assign)
2164                         err = snd_hda_create_dig_out_ctls(codec,
2165                                           0, spec->cvt_nids[0],
2166                                           HDA_PCM_TYPE_HDMI);
2167                 else {
2168                         struct hdmi_spec_per_pin *per_pin =
2169                                 get_pin(spec, pcm_idx);
2170                         err = snd_hda_create_dig_out_ctls(codec,
2171                                                   per_pin->pin_nid,
2172                                                   per_pin->mux_nids[0],
2173                                                   HDA_PCM_TYPE_HDMI);
2174                 }
2175                 if (err < 0)
2176                         return err;
2177                 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2178
2179                 dev = get_pcm_rec(spec, pcm_idx)->device;
2180                 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2181                         /* add control for ELD Bytes */
2182                         err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2183                         if (err < 0)
2184                                 return err;
2185                 }
2186         }
2187
2188         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2189                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2190
2191                 hdmi_present_sense(per_pin, 0);
2192         }
2193
2194         /* add channel maps */
2195         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2196                 struct hda_pcm *pcm;
2197
2198                 pcm = get_pcm_rec(spec, pcm_idx);
2199                 if (!pcm || !pcm->pcm)
2200                         break;
2201                 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2202                 if (err < 0)
2203                         return err;
2204         }
2205
2206         return 0;
2207 }
2208
2209 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2210 {
2211         struct hdmi_spec *spec = codec->spec;
2212         int pin_idx;
2213
2214         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2215                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2216
2217                 per_pin->codec = codec;
2218                 mutex_init(&per_pin->lock);
2219                 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2220                 eld_proc_new(per_pin, pin_idx);
2221         }
2222         return 0;
2223 }
2224
2225 static int generic_hdmi_init(struct hda_codec *codec)
2226 {
2227         struct hdmi_spec *spec = codec->spec;
2228         int pin_idx;
2229
2230         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2231                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2232                 hda_nid_t pin_nid = per_pin->pin_nid;
2233                 int dev_id = per_pin->dev_id;
2234
2235                 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2236                 hdmi_init_pin(codec, pin_nid);
2237                 if (!codec_has_acomp(codec))
2238                         snd_hda_jack_detect_enable_callback(codec, pin_nid,
2239                                 codec->jackpoll_interval > 0 ?
2240                                 jack_callback : NULL);
2241         }
2242         return 0;
2243 }
2244
2245 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2246 {
2247         snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2248         snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2249 }
2250
2251 static void hdmi_array_free(struct hdmi_spec *spec)
2252 {
2253         snd_array_free(&spec->pins);
2254         snd_array_free(&spec->cvts);
2255 }
2256
2257 static void generic_spec_free(struct hda_codec *codec)
2258 {
2259         struct hdmi_spec *spec = codec->spec;
2260
2261         if (spec) {
2262                 hdmi_array_free(spec);
2263                 kfree(spec);
2264                 codec->spec = NULL;
2265         }
2266         codec->dp_mst = false;
2267 }
2268
2269 static void generic_hdmi_free(struct hda_codec *codec)
2270 {
2271         struct hdmi_spec *spec = codec->spec;
2272         int pin_idx, pcm_idx;
2273
2274         if (codec_has_acomp(codec))
2275                 snd_hdac_i915_register_notifier(NULL);
2276
2277         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2278                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2279                 cancel_delayed_work_sync(&per_pin->work);
2280                 eld_proc_free(per_pin);
2281         }
2282
2283         for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2284                 if (spec->pcm_rec[pcm_idx].jack == NULL)
2285                         continue;
2286                 if (spec->dyn_pcm_assign)
2287                         snd_device_free(codec->card,
2288                                         spec->pcm_rec[pcm_idx].jack);
2289                 else
2290                         spec->pcm_rec[pcm_idx].jack = NULL;
2291         }
2292
2293         generic_spec_free(codec);
2294 }
2295
2296 #ifdef CONFIG_PM
2297 static int generic_hdmi_resume(struct hda_codec *codec)
2298 {
2299         struct hdmi_spec *spec = codec->spec;
2300         int pin_idx;
2301
2302         codec->patch_ops.init(codec);
2303         regcache_sync(codec->core.regmap);
2304
2305         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2306                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2307                 hdmi_present_sense(per_pin, 1);
2308         }
2309         return 0;
2310 }
2311 #endif
2312
2313 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2314         .init                   = generic_hdmi_init,
2315         .free                   = generic_hdmi_free,
2316         .build_pcms             = generic_hdmi_build_pcms,
2317         .build_controls         = generic_hdmi_build_controls,
2318         .unsol_event            = hdmi_unsol_event,
2319 #ifdef CONFIG_PM
2320         .resume                 = generic_hdmi_resume,
2321 #endif
2322 };
2323
2324 static const struct hdmi_ops generic_standard_hdmi_ops = {
2325         .pin_get_eld                            = snd_hdmi_get_eld,
2326         .pin_setup_infoframe                    = hdmi_pin_setup_infoframe,
2327         .pin_hbr_setup                          = hdmi_pin_hbr_setup,
2328         .setup_stream                           = hdmi_setup_stream,
2329 };
2330
2331 /* allocate codec->spec and assign/initialize generic parser ops */
2332 static int alloc_generic_hdmi(struct hda_codec *codec)
2333 {
2334         struct hdmi_spec *spec;
2335
2336         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2337         if (!spec)
2338                 return -ENOMEM;
2339
2340         spec->ops = generic_standard_hdmi_ops;
2341         spec->dev_num = 1;      /* initialize to 1 */
2342         mutex_init(&spec->pcm_lock);
2343         snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2344
2345         spec->chmap.ops.get_chmap = hdmi_get_chmap;
2346         spec->chmap.ops.set_chmap = hdmi_set_chmap;
2347         spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2348         spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2349
2350         codec->spec = spec;
2351         hdmi_array_init(spec, 4);
2352
2353         codec->patch_ops = generic_hdmi_patch_ops;
2354
2355         return 0;
2356 }
2357
2358 /* generic HDMI parser */
2359 static int patch_generic_hdmi(struct hda_codec *codec)
2360 {
2361         int err;
2362
2363         err = alloc_generic_hdmi(codec);
2364         if (err < 0)
2365                 return err;
2366
2367         err = hdmi_parse_codec(codec);
2368         if (err < 0) {
2369                 generic_spec_free(codec);
2370                 return err;
2371         }
2372
2373         generic_hdmi_init_per_pins(codec);
2374         return 0;
2375 }
2376
2377 /*
2378  * Intel codec parsers and helpers
2379  */
2380
2381 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2382                                              hda_nid_t nid)
2383 {
2384         struct hdmi_spec *spec = codec->spec;
2385         hda_nid_t conns[4];
2386         int nconns;
2387
2388         nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2389         if (nconns == spec->num_cvts &&
2390             !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2391                 return;
2392
2393         /* override pins connection list */
2394         codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2395         snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2396 }
2397
2398 #define INTEL_VENDOR_NID 0x08
2399 #define INTEL_GLK_VENDOR_NID 0x0B
2400 #define INTEL_GET_VENDOR_VERB 0xf81
2401 #define INTEL_SET_VENDOR_VERB 0x781
2402 #define INTEL_EN_DP12                   0x02 /* enable DP 1.2 features */
2403 #define INTEL_EN_ALL_PIN_CVTS   0x01 /* enable 2nd & 3rd pins and convertors */
2404
2405 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2406                                           bool update_tree)
2407 {
2408         unsigned int vendor_param;
2409         struct hdmi_spec *spec = codec->spec;
2410
2411         vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2412                                 INTEL_GET_VENDOR_VERB, 0);
2413         if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2414                 return;
2415
2416         vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2417         vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2418                                 INTEL_SET_VENDOR_VERB, vendor_param);
2419         if (vendor_param == -1)
2420                 return;
2421
2422         if (update_tree)
2423                 snd_hda_codec_update_widgets(codec);
2424 }
2425
2426 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2427 {
2428         unsigned int vendor_param;
2429         struct hdmi_spec *spec = codec->spec;
2430
2431         vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2432                                 INTEL_GET_VENDOR_VERB, 0);
2433         if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2434                 return;
2435
2436         /* enable DP1.2 mode */
2437         vendor_param |= INTEL_EN_DP12;
2438         snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2439         snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2440                                 INTEL_SET_VENDOR_VERB, vendor_param);
2441 }
2442
2443 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2444  * Otherwise you may get severe h/w communication errors.
2445  */
2446 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2447                                 unsigned int power_state)
2448 {
2449         if (power_state == AC_PWRST_D0) {
2450                 intel_haswell_enable_all_pins(codec, false);
2451                 intel_haswell_fixup_enable_dp12(codec);
2452         }
2453
2454         snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2455         snd_hda_codec_set_power_to_all(codec, fg, power_state);
2456 }
2457
2458 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2459 {
2460         struct hda_codec *codec = audio_ptr;
2461         int pin_nid;
2462         int dev_id = pipe;
2463
2464         /* we assume only from port-B to port-D */
2465         if (port < 1 || port > 3)
2466                 return;
2467
2468         switch (codec->core.vendor_id) {
2469         case 0x80860054: /* ILK */
2470         case 0x80862804: /* ILK */
2471         case 0x80862882: /* VLV */
2472                 pin_nid = port + 0x03;
2473                 break;
2474         default:
2475                 pin_nid = port + 0x04;
2476                 break;
2477         }
2478
2479         /* skip notification during system suspend (but not in runtime PM);
2480          * the state will be updated at resume
2481          */
2482         if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2483                 return;
2484         /* ditto during suspend/resume process itself */
2485         if (atomic_read(&(codec)->core.in_pm))
2486                 return;
2487
2488         snd_hdac_i915_set_bclk(&codec->bus->core);
2489         check_presence_and_report(codec, pin_nid, dev_id);
2490 }
2491
2492 /* register i915 component pin_eld_notify callback */
2493 static void register_i915_notifier(struct hda_codec *codec)
2494 {
2495         struct hdmi_spec *spec = codec->spec;
2496
2497         spec->use_acomp_notifier = true;
2498         spec->i915_audio_ops.audio_ptr = codec;
2499         /* intel_audio_codec_enable() or intel_audio_codec_disable()
2500          * will call pin_eld_notify with using audio_ptr pointer
2501          * We need make sure audio_ptr is really setup
2502          */
2503         wmb();
2504         spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2505         snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2506 }
2507
2508 /* setup_stream ops override for HSW+ */
2509 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2510                                  hda_nid_t pin_nid, u32 stream_tag, int format)
2511 {
2512         haswell_verify_D0(codec, cvt_nid, pin_nid);
2513         return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2514 }
2515
2516 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2517 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2518                                struct hdmi_spec_per_pin *per_pin,
2519                                hda_nid_t cvt_nid)
2520 {
2521         if (per_pin) {
2522                 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2523                                per_pin->dev_id);
2524                 intel_verify_pin_cvt_connect(codec, per_pin);
2525                 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2526                                      per_pin->dev_id, per_pin->mux_idx);
2527         } else {
2528                 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2529         }
2530 }
2531
2532 /* precondition and allocation for Intel codecs */
2533 static int alloc_intel_hdmi(struct hda_codec *codec)
2534 {
2535         /* requires i915 binding */
2536         if (!codec->bus->core.audio_component) {
2537                 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2538                 return -ENODEV;
2539         }
2540
2541         return alloc_generic_hdmi(codec);
2542 }
2543
2544 /* parse and post-process for Intel codecs */
2545 static int parse_intel_hdmi(struct hda_codec *codec)
2546 {
2547         int err;
2548
2549         err = hdmi_parse_codec(codec);
2550         if (err < 0) {
2551                 generic_spec_free(codec);
2552                 return err;
2553         }
2554
2555         generic_hdmi_init_per_pins(codec);
2556         register_i915_notifier(codec);
2557         return 0;
2558 }
2559
2560 /* Intel Haswell and onwards; audio component with eld notifier */
2561 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid)
2562 {
2563         struct hdmi_spec *spec;
2564         int err;
2565
2566         err = alloc_intel_hdmi(codec);
2567         if (err < 0)
2568                 return err;
2569         spec = codec->spec;
2570         codec->dp_mst = true;
2571         spec->dyn_pcm_assign = true;
2572         spec->vendor_nid = vendor_nid;
2573
2574         intel_haswell_enable_all_pins(codec, true);
2575         intel_haswell_fixup_enable_dp12(codec);
2576
2577         /* For Haswell/Broadwell, the controller is also in the power well and
2578          * can cover the codec power request, and so need not set this flag.
2579          */
2580         if (!is_haswell(codec) && !is_broadwell(codec))
2581                 codec->core.link_power_control = 1;
2582
2583         codec->patch_ops.set_power_state = haswell_set_power_state;
2584         codec->depop_delay = 0;
2585         codec->auto_runtime_pm = 1;
2586
2587         spec->ops.setup_stream = i915_hsw_setup_stream;
2588         spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2589
2590         return parse_intel_hdmi(codec);
2591 }
2592
2593 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2594 {
2595         return intel_hsw_common_init(codec, INTEL_VENDOR_NID);
2596 }
2597
2598 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2599 {
2600         return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID);
2601 }
2602
2603 /* Intel Baytrail and Braswell; with eld notifier */
2604 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2605 {
2606         struct hdmi_spec *spec;
2607         int err;
2608
2609         err = alloc_intel_hdmi(codec);
2610         if (err < 0)
2611                 return err;
2612         spec = codec->spec;
2613
2614         /* For Valleyview/Cherryview, only the display codec is in the display
2615          * power well and can use link_power ops to request/release the power.
2616          */
2617         codec->core.link_power_control = 1;
2618
2619         codec->depop_delay = 0;
2620         codec->auto_runtime_pm = 1;
2621
2622         spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2623
2624         return parse_intel_hdmi(codec);
2625 }
2626
2627 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2628 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2629 {
2630         int err;
2631
2632         err = alloc_intel_hdmi(codec);
2633         if (err < 0)
2634                 return err;
2635         return parse_intel_hdmi(codec);
2636 }
2637
2638 /*
2639  * Shared non-generic implementations
2640  */
2641
2642 static int simple_playback_build_pcms(struct hda_codec *codec)
2643 {
2644         struct hdmi_spec *spec = codec->spec;
2645         struct hda_pcm *info;
2646         unsigned int chans;
2647         struct hda_pcm_stream *pstr;
2648         struct hdmi_spec_per_cvt *per_cvt;
2649
2650         per_cvt = get_cvt(spec, 0);
2651         chans = get_wcaps(codec, per_cvt->cvt_nid);
2652         chans = get_wcaps_channels(chans);
2653
2654         info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2655         if (!info)
2656                 return -ENOMEM;
2657         spec->pcm_rec[0].pcm = info;
2658         info->pcm_type = HDA_PCM_TYPE_HDMI;
2659         pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2660         *pstr = spec->pcm_playback;
2661         pstr->nid = per_cvt->cvt_nid;
2662         if (pstr->channels_max <= 2 && chans && chans <= 16)
2663                 pstr->channels_max = chans;
2664
2665         return 0;
2666 }
2667
2668 /* unsolicited event for jack sensing */
2669 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2670                                     unsigned int res)
2671 {
2672         snd_hda_jack_set_dirty_all(codec);
2673         snd_hda_jack_report_sync(codec);
2674 }
2675
2676 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2677  * as long as spec->pins[] is set correctly
2678  */
2679 #define simple_hdmi_build_jack  generic_hdmi_build_jack
2680
2681 static int simple_playback_build_controls(struct hda_codec *codec)
2682 {
2683         struct hdmi_spec *spec = codec->spec;
2684         struct hdmi_spec_per_cvt *per_cvt;
2685         int err;
2686
2687         per_cvt = get_cvt(spec, 0);
2688         err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2689                                           per_cvt->cvt_nid,
2690                                           HDA_PCM_TYPE_HDMI);
2691         if (err < 0)
2692                 return err;
2693         return simple_hdmi_build_jack(codec, 0);
2694 }
2695
2696 static int simple_playback_init(struct hda_codec *codec)
2697 {
2698         struct hdmi_spec *spec = codec->spec;
2699         struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2700         hda_nid_t pin = per_pin->pin_nid;
2701
2702         snd_hda_codec_write(codec, pin, 0,
2703                             AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2704         /* some codecs require to unmute the pin */
2705         if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2706                 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2707                                     AMP_OUT_UNMUTE);
2708         snd_hda_jack_detect_enable(codec, pin);
2709         return 0;
2710 }
2711
2712 static void simple_playback_free(struct hda_codec *codec)
2713 {
2714         struct hdmi_spec *spec = codec->spec;
2715
2716         hdmi_array_free(spec);
2717         kfree(spec);
2718 }
2719
2720 /*
2721  * Nvidia specific implementations
2722  */
2723
2724 #define Nv_VERB_SET_Channel_Allocation          0xF79
2725 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
2726 #define Nv_VERB_SET_Audio_Protection_On         0xF98
2727 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
2728
2729 #define nvhdmi_master_con_nid_7x        0x04
2730 #define nvhdmi_master_pin_nid_7x        0x05
2731
2732 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2733         /*front, rear, clfe, rear_surr */
2734         0x6, 0x8, 0xa, 0xc,
2735 };
2736
2737 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2738         /* set audio protect on */
2739         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2740         /* enable digital output on pin widget */
2741         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2742         {} /* terminator */
2743 };
2744
2745 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2746         /* set audio protect on */
2747         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2748         /* enable digital output on pin widget */
2749         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2750         { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2751         { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2752         { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2753         { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2754         {} /* terminator */
2755 };
2756
2757 #ifdef LIMITED_RATE_FMT_SUPPORT
2758 /* support only the safe format and rate */
2759 #define SUPPORTED_RATES         SNDRV_PCM_RATE_48000
2760 #define SUPPORTED_MAXBPS        16
2761 #define SUPPORTED_FORMATS       SNDRV_PCM_FMTBIT_S16_LE
2762 #else
2763 /* support all rates and formats */
2764 #define SUPPORTED_RATES \
2765         (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2766         SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2767          SNDRV_PCM_RATE_192000)
2768 #define SUPPORTED_MAXBPS        24
2769 #define SUPPORTED_FORMATS \
2770         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2771 #endif
2772
2773 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2774 {
2775         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2776         return 0;
2777 }
2778
2779 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2780 {
2781         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2782         return 0;
2783 }
2784
2785 static const unsigned int channels_2_6_8[] = {
2786         2, 6, 8
2787 };
2788
2789 static const unsigned int channels_2_8[] = {
2790         2, 8
2791 };
2792
2793 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2794         .count = ARRAY_SIZE(channels_2_6_8),
2795         .list = channels_2_6_8,
2796         .mask = 0,
2797 };
2798
2799 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2800         .count = ARRAY_SIZE(channels_2_8),
2801         .list = channels_2_8,
2802         .mask = 0,
2803 };
2804
2805 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2806                                     struct hda_codec *codec,
2807                                     struct snd_pcm_substream *substream)
2808 {
2809         struct hdmi_spec *spec = codec->spec;
2810         const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2811
2812         switch (codec->preset->vendor_id) {
2813         case 0x10de0002:
2814         case 0x10de0003:
2815         case 0x10de0005:
2816         case 0x10de0006:
2817                 hw_constraints_channels = &hw_constraints_2_8_channels;
2818                 break;
2819         case 0x10de0007:
2820                 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2821                 break;
2822         default:
2823                 break;
2824         }
2825
2826         if (hw_constraints_channels != NULL) {
2827                 snd_pcm_hw_constraint_list(substream->runtime, 0,
2828                                 SNDRV_PCM_HW_PARAM_CHANNELS,
2829                                 hw_constraints_channels);
2830         } else {
2831                 snd_pcm_hw_constraint_step(substream->runtime, 0,
2832                                            SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2833         }
2834
2835         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2836 }
2837
2838 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2839                                      struct hda_codec *codec,
2840                                      struct snd_pcm_substream *substream)
2841 {
2842         struct hdmi_spec *spec = codec->spec;
2843         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2844 }
2845
2846 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2847                                        struct hda_codec *codec,
2848                                        unsigned int stream_tag,
2849                                        unsigned int format,
2850                                        struct snd_pcm_substream *substream)
2851 {
2852         struct hdmi_spec *spec = codec->spec;
2853         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2854                                              stream_tag, format, substream);
2855 }
2856
2857 static const struct hda_pcm_stream simple_pcm_playback = {
2858         .substreams = 1,
2859         .channels_min = 2,
2860         .channels_max = 2,
2861         .ops = {
2862                 .open = simple_playback_pcm_open,
2863                 .close = simple_playback_pcm_close,
2864                 .prepare = simple_playback_pcm_prepare
2865         },
2866 };
2867
2868 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2869         .build_controls = simple_playback_build_controls,
2870         .build_pcms = simple_playback_build_pcms,
2871         .init = simple_playback_init,
2872         .free = simple_playback_free,
2873         .unsol_event = simple_hdmi_unsol_event,
2874 };
2875
2876 static int patch_simple_hdmi(struct hda_codec *codec,
2877                              hda_nid_t cvt_nid, hda_nid_t pin_nid)
2878 {
2879         struct hdmi_spec *spec;
2880         struct hdmi_spec_per_cvt *per_cvt;
2881         struct hdmi_spec_per_pin *per_pin;
2882
2883         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2884         if (!spec)
2885                 return -ENOMEM;
2886
2887         codec->spec = spec;
2888         hdmi_array_init(spec, 1);
2889
2890         spec->multiout.num_dacs = 0;  /* no analog */
2891         spec->multiout.max_channels = 2;
2892         spec->multiout.dig_out_nid = cvt_nid;
2893         spec->num_cvts = 1;
2894         spec->num_pins = 1;
2895         per_pin = snd_array_new(&spec->pins);
2896         per_cvt = snd_array_new(&spec->cvts);
2897         if (!per_pin || !per_cvt) {
2898                 simple_playback_free(codec);
2899                 return -ENOMEM;
2900         }
2901         per_cvt->cvt_nid = cvt_nid;
2902         per_pin->pin_nid = pin_nid;
2903         spec->pcm_playback = simple_pcm_playback;
2904
2905         codec->patch_ops = simple_hdmi_patch_ops;
2906
2907         return 0;
2908 }
2909
2910 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2911                                                     int channels)
2912 {
2913         unsigned int chanmask;
2914         int chan = channels ? (channels - 1) : 1;
2915
2916         switch (channels) {
2917         default:
2918         case 0:
2919         case 2:
2920                 chanmask = 0x00;
2921                 break;
2922         case 4:
2923                 chanmask = 0x08;
2924                 break;
2925         case 6:
2926                 chanmask = 0x0b;
2927                 break;
2928         case 8:
2929                 chanmask = 0x13;
2930                 break;
2931         }
2932
2933         /* Set the audio infoframe channel allocation and checksum fields.  The
2934          * channel count is computed implicitly by the hardware. */
2935         snd_hda_codec_write(codec, 0x1, 0,
2936                         Nv_VERB_SET_Channel_Allocation, chanmask);
2937
2938         snd_hda_codec_write(codec, 0x1, 0,
2939                         Nv_VERB_SET_Info_Frame_Checksum,
2940                         (0x71 - chan - chanmask));
2941 }
2942
2943 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2944                                    struct hda_codec *codec,
2945                                    struct snd_pcm_substream *substream)
2946 {
2947         struct hdmi_spec *spec = codec->spec;
2948         int i;
2949
2950         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2951                         0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2952         for (i = 0; i < 4; i++) {
2953                 /* set the stream id */
2954                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2955                                 AC_VERB_SET_CHANNEL_STREAMID, 0);
2956                 /* set the stream format */
2957                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2958                                 AC_VERB_SET_STREAM_FORMAT, 0);
2959         }
2960
2961         /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2962          * streams are disabled. */
2963         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2964
2965         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2966 }
2967
2968 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2969                                      struct hda_codec *codec,
2970                                      unsigned int stream_tag,
2971                                      unsigned int format,
2972                                      struct snd_pcm_substream *substream)
2973 {
2974         int chs;
2975         unsigned int dataDCC2, channel_id;
2976         int i;
2977         struct hdmi_spec *spec = codec->spec;
2978         struct hda_spdif_out *spdif;
2979         struct hdmi_spec_per_cvt *per_cvt;
2980
2981         mutex_lock(&codec->spdif_mutex);
2982         per_cvt = get_cvt(spec, 0);
2983         spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2984
2985         chs = substream->runtime->channels;
2986
2987         dataDCC2 = 0x2;
2988
2989         /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2990         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2991                 snd_hda_codec_write(codec,
2992                                 nvhdmi_master_con_nid_7x,
2993                                 0,
2994                                 AC_VERB_SET_DIGI_CONVERT_1,
2995                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2996
2997         /* set the stream id */
2998         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2999                         AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3000
3001         /* set the stream format */
3002         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3003                         AC_VERB_SET_STREAM_FORMAT, format);
3004
3005         /* turn on again (if needed) */
3006         /* enable and set the channel status audio/data flag */
3007         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3008                 snd_hda_codec_write(codec,
3009                                 nvhdmi_master_con_nid_7x,
3010                                 0,
3011                                 AC_VERB_SET_DIGI_CONVERT_1,
3012                                 spdif->ctls & 0xff);
3013                 snd_hda_codec_write(codec,
3014                                 nvhdmi_master_con_nid_7x,
3015                                 0,
3016                                 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3017         }
3018
3019         for (i = 0; i < 4; i++) {
3020                 if (chs == 2)
3021                         channel_id = 0;
3022                 else
3023                         channel_id = i * 2;
3024
3025                 /* turn off SPDIF once;
3026                  *otherwise the IEC958 bits won't be updated
3027                  */
3028                 if (codec->spdif_status_reset &&
3029                 (spdif->ctls & AC_DIG1_ENABLE))
3030                         snd_hda_codec_write(codec,
3031                                 nvhdmi_con_nids_7x[i],
3032                                 0,
3033                                 AC_VERB_SET_DIGI_CONVERT_1,
3034                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3035                 /* set the stream id */
3036                 snd_hda_codec_write(codec,
3037                                 nvhdmi_con_nids_7x[i],
3038                                 0,
3039                                 AC_VERB_SET_CHANNEL_STREAMID,
3040                                 (stream_tag << 4) | channel_id);
3041                 /* set the stream format */
3042                 snd_hda_codec_write(codec,
3043                                 nvhdmi_con_nids_7x[i],
3044                                 0,
3045                                 AC_VERB_SET_STREAM_FORMAT,
3046                                 format);
3047                 /* turn on again (if needed) */
3048                 /* enable and set the channel status audio/data flag */
3049                 if (codec->spdif_status_reset &&
3050                 (spdif->ctls & AC_DIG1_ENABLE)) {
3051                         snd_hda_codec_write(codec,
3052                                         nvhdmi_con_nids_7x[i],
3053                                         0,
3054                                         AC_VERB_SET_DIGI_CONVERT_1,
3055                                         spdif->ctls & 0xff);
3056                         snd_hda_codec_write(codec,
3057                                         nvhdmi_con_nids_7x[i],
3058                                         0,
3059                                         AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3060                 }
3061         }
3062
3063         nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3064
3065         mutex_unlock(&codec->spdif_mutex);
3066         return 0;
3067 }
3068
3069 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3070         .substreams = 1,
3071         .channels_min = 2,
3072         .channels_max = 8,
3073         .nid = nvhdmi_master_con_nid_7x,
3074         .rates = SUPPORTED_RATES,
3075         .maxbps = SUPPORTED_MAXBPS,
3076         .formats = SUPPORTED_FORMATS,
3077         .ops = {
3078                 .open = simple_playback_pcm_open,
3079                 .close = nvhdmi_8ch_7x_pcm_close,
3080                 .prepare = nvhdmi_8ch_7x_pcm_prepare
3081         },
3082 };
3083
3084 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3085 {
3086         struct hdmi_spec *spec;
3087         int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3088                                     nvhdmi_master_pin_nid_7x);
3089         if (err < 0)
3090                 return err;
3091
3092         codec->patch_ops.init = nvhdmi_7x_init_2ch;
3093         /* override the PCM rates, etc, as the codec doesn't give full list */
3094         spec = codec->spec;
3095         spec->pcm_playback.rates = SUPPORTED_RATES;
3096         spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3097         spec->pcm_playback.formats = SUPPORTED_FORMATS;
3098         return 0;
3099 }
3100
3101 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3102 {
3103         struct hdmi_spec *spec = codec->spec;
3104         int err = simple_playback_build_pcms(codec);
3105         if (!err) {
3106                 struct hda_pcm *info = get_pcm_rec(spec, 0);
3107                 info->own_chmap = true;
3108         }
3109         return err;
3110 }
3111
3112 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3113 {
3114         struct hdmi_spec *spec = codec->spec;
3115         struct hda_pcm *info;
3116         struct snd_pcm_chmap *chmap;
3117         int err;
3118
3119         err = simple_playback_build_controls(codec);
3120         if (err < 0)
3121                 return err;
3122
3123         /* add channel maps */
3124         info = get_pcm_rec(spec, 0);
3125         err = snd_pcm_add_chmap_ctls(info->pcm,
3126                                      SNDRV_PCM_STREAM_PLAYBACK,
3127                                      snd_pcm_alt_chmaps, 8, 0, &chmap);
3128         if (err < 0)
3129                 return err;
3130         switch (codec->preset->vendor_id) {
3131         case 0x10de0002:
3132         case 0x10de0003:
3133         case 0x10de0005:
3134         case 0x10de0006:
3135                 chmap->channel_mask = (1U << 2) | (1U << 8);
3136                 break;
3137         case 0x10de0007:
3138                 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3139         }
3140         return 0;
3141 }
3142
3143 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3144 {
3145         struct hdmi_spec *spec;
3146         int err = patch_nvhdmi_2ch(codec);
3147         if (err < 0)
3148                 return err;
3149         spec = codec->spec;
3150         spec->multiout.max_channels = 8;
3151         spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3152         codec->patch_ops.init = nvhdmi_7x_init_8ch;
3153         codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3154         codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3155
3156         /* Initialize the audio infoframe channel mask and checksum to something
3157          * valid */
3158         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3159
3160         return 0;
3161 }
3162
3163 /*
3164  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3165  * - 0x10de0015
3166  * - 0x10de0040
3167  */
3168 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3169                 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3170 {
3171         if (cap->ca_index == 0x00 && channels == 2)
3172                 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3173
3174         /* If the speaker allocation matches the channel count, it is OK. */
3175         if (cap->channels != channels)
3176                 return -1;
3177
3178         /* all channels are remappable freely */
3179         return SNDRV_CTL_TLVT_CHMAP_VAR;
3180 }
3181
3182 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3183                 int ca, int chs, unsigned char *map)
3184 {
3185         if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3186                 return -EINVAL;
3187
3188         return 0;
3189 }
3190
3191 static int patch_nvhdmi(struct hda_codec *codec)
3192 {
3193         struct hdmi_spec *spec;
3194         int err;
3195
3196         err = patch_generic_hdmi(codec);
3197         if (err)
3198                 return err;
3199
3200         spec = codec->spec;
3201         spec->dyn_pin_out = true;
3202
3203         spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3204                 nvhdmi_chmap_cea_alloc_validate_get_type;
3205         spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3206
3207         return 0;
3208 }
3209
3210 /*
3211  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3212  * accessed using vendor-defined verbs. These registers can be used for
3213  * interoperability between the HDA and HDMI drivers.
3214  */
3215
3216 /* Audio Function Group node */
3217 #define NVIDIA_AFG_NID 0x01
3218
3219 /*
3220  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3221  * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3222  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3223  * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3224  * additional bit (at position 30) to signal the validity of the format.
3225  *
3226  * | 31      | 30    | 29  16 | 15   0 |
3227  * +---------+-------+--------+--------+
3228  * | TRIGGER | VALID | UNUSED | FORMAT |
3229  * +-----------------------------------|
3230  *
3231  * Note that for the trigger bit to take effect it needs to change value
3232  * (i.e. it needs to be toggled).
3233  */
3234 #define NVIDIA_GET_SCRATCH0             0xfa6
3235 #define NVIDIA_SET_SCRATCH0_BYTE0       0xfa7
3236 #define NVIDIA_SET_SCRATCH0_BYTE1       0xfa8
3237 #define NVIDIA_SET_SCRATCH0_BYTE2       0xfa9
3238 #define NVIDIA_SET_SCRATCH0_BYTE3       0xfaa
3239 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3240 #define NVIDIA_SCRATCH_VALID   (1 << 6)
3241
3242 #define NVIDIA_GET_SCRATCH1             0xfab
3243 #define NVIDIA_SET_SCRATCH1_BYTE0       0xfac
3244 #define NVIDIA_SET_SCRATCH1_BYTE1       0xfad
3245 #define NVIDIA_SET_SCRATCH1_BYTE2       0xfae
3246 #define NVIDIA_SET_SCRATCH1_BYTE3       0xfaf
3247
3248 /*
3249  * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3250  * the format is invalidated so that the HDMI codec can be disabled.
3251  */
3252 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3253 {
3254         unsigned int value;
3255
3256         /* bits [31:30] contain the trigger and valid bits */
3257         value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3258                                    NVIDIA_GET_SCRATCH0, 0);
3259         value = (value >> 24) & 0xff;
3260
3261         /* bits [15:0] are used to store the HDA format */
3262         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3263                             NVIDIA_SET_SCRATCH0_BYTE0,
3264                             (format >> 0) & 0xff);
3265         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3266                             NVIDIA_SET_SCRATCH0_BYTE1,
3267                             (format >> 8) & 0xff);
3268
3269         /* bits [16:24] are unused */
3270         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3271                             NVIDIA_SET_SCRATCH0_BYTE2, 0);
3272
3273         /*
3274          * Bit 30 signals that the data is valid and hence that HDMI audio can
3275          * be enabled.
3276          */
3277         if (format == 0)
3278                 value &= ~NVIDIA_SCRATCH_VALID;
3279         else
3280                 value |= NVIDIA_SCRATCH_VALID;
3281
3282         /*
3283          * Whenever the trigger bit is toggled, an interrupt is raised in the
3284          * HDMI codec. The HDMI driver will use that as trigger to update its
3285          * configuration.
3286          */
3287         value ^= NVIDIA_SCRATCH_TRIGGER;
3288
3289         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3290                             NVIDIA_SET_SCRATCH0_BYTE3, value);
3291 }
3292
3293 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3294                                   struct hda_codec *codec,
3295                                   unsigned int stream_tag,
3296                                   unsigned int format,
3297                                   struct snd_pcm_substream *substream)
3298 {
3299         int err;
3300
3301         err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3302                                                 format, substream);
3303         if (err < 0)
3304                 return err;
3305
3306         /* notify the HDMI codec of the format change */
3307         tegra_hdmi_set_format(codec, format);
3308
3309         return 0;
3310 }
3311
3312 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3313                                   struct hda_codec *codec,
3314                                   struct snd_pcm_substream *substream)
3315 {
3316         /* invalidate the format in the HDMI codec */
3317         tegra_hdmi_set_format(codec, 0);
3318
3319         return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3320 }
3321
3322 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3323 {
3324         struct hdmi_spec *spec = codec->spec;
3325         unsigned int i;
3326
3327         for (i = 0; i < spec->num_pins; i++) {
3328                 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3329
3330                 if (pcm->pcm_type == type)
3331                         return pcm;
3332         }
3333
3334         return NULL;
3335 }
3336
3337 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3338 {
3339         struct hda_pcm_stream *stream;
3340         struct hda_pcm *pcm;
3341         int err;
3342
3343         err = generic_hdmi_build_pcms(codec);
3344         if (err < 0)
3345                 return err;
3346
3347         pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3348         if (!pcm)
3349                 return -ENODEV;
3350
3351         /*
3352          * Override ->prepare() and ->cleanup() operations to notify the HDMI
3353          * codec about format changes.
3354          */
3355         stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3356         stream->ops.prepare = tegra_hdmi_pcm_prepare;
3357         stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3358
3359         return 0;
3360 }
3361
3362 static int patch_tegra_hdmi(struct hda_codec *codec)
3363 {
3364         int err;
3365
3366         err = patch_generic_hdmi(codec);
3367         if (err)
3368                 return err;
3369
3370         codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3371
3372         return 0;
3373 }
3374
3375 /*
3376  * ATI/AMD-specific implementations
3377  */
3378
3379 #define is_amdhdmi_rev3_or_later(codec) \
3380         ((codec)->core.vendor_id == 0x1002aa01 && \
3381          ((codec)->core.revision_id & 0xff00) >= 0x0300)
3382 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3383
3384 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3385 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3386 #define ATI_VERB_SET_DOWNMIX_INFO       0x772
3387 #define ATI_VERB_SET_MULTICHANNEL_01    0x777
3388 #define ATI_VERB_SET_MULTICHANNEL_23    0x778
3389 #define ATI_VERB_SET_MULTICHANNEL_45    0x779
3390 #define ATI_VERB_SET_MULTICHANNEL_67    0x77a
3391 #define ATI_VERB_SET_HBR_CONTROL        0x77c
3392 #define ATI_VERB_SET_MULTICHANNEL_1     0x785
3393 #define ATI_VERB_SET_MULTICHANNEL_3     0x786
3394 #define ATI_VERB_SET_MULTICHANNEL_5     0x787
3395 #define ATI_VERB_SET_MULTICHANNEL_7     0x788
3396 #define ATI_VERB_SET_MULTICHANNEL_MODE  0x789
3397 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3398 #define ATI_VERB_GET_DOWNMIX_INFO       0xf72
3399 #define ATI_VERB_GET_MULTICHANNEL_01    0xf77
3400 #define ATI_VERB_GET_MULTICHANNEL_23    0xf78
3401 #define ATI_VERB_GET_MULTICHANNEL_45    0xf79
3402 #define ATI_VERB_GET_MULTICHANNEL_67    0xf7a
3403 #define ATI_VERB_GET_HBR_CONTROL        0xf7c
3404 #define ATI_VERB_GET_MULTICHANNEL_1     0xf85
3405 #define ATI_VERB_GET_MULTICHANNEL_3     0xf86
3406 #define ATI_VERB_GET_MULTICHANNEL_5     0xf87
3407 #define ATI_VERB_GET_MULTICHANNEL_7     0xf88
3408 #define ATI_VERB_GET_MULTICHANNEL_MODE  0xf89
3409
3410 /* AMD specific HDA cvt verbs */
3411 #define ATI_VERB_SET_RAMP_RATE          0x770
3412 #define ATI_VERB_GET_RAMP_RATE          0xf70
3413
3414 #define ATI_OUT_ENABLE 0x1
3415
3416 #define ATI_MULTICHANNEL_MODE_PAIRED    0
3417 #define ATI_MULTICHANNEL_MODE_SINGLE    1
3418
3419 #define ATI_HBR_CAPABLE 0x01
3420 #define ATI_HBR_ENABLE 0x10
3421
3422 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3423                            unsigned char *buf, int *eld_size)
3424 {
3425         /* call hda_eld.c ATI/AMD-specific function */
3426         return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3427                                     is_amdhdmi_rev3_or_later(codec));
3428 }
3429
3430 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3431                                         int active_channels, int conn_type)
3432 {
3433         snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3434 }
3435
3436 static int atihdmi_paired_swap_fc_lfe(int pos)
3437 {
3438         /*
3439          * ATI/AMD have automatic FC/LFE swap built-in
3440          * when in pairwise mapping mode.
3441          */
3442
3443         switch (pos) {
3444                 /* see channel_allocations[].speakers[] */
3445                 case 2: return 3;
3446                 case 3: return 2;
3447                 default: break;
3448         }
3449
3450         return pos;
3451 }
3452
3453 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3454                         int ca, int chs, unsigned char *map)
3455 {
3456         struct hdac_cea_channel_speaker_allocation *cap;
3457         int i, j;
3458
3459         /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3460
3461         cap = snd_hdac_get_ch_alloc_from_ca(ca);
3462         for (i = 0; i < chs; ++i) {
3463                 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3464                 bool ok = false;
3465                 bool companion_ok = false;
3466
3467                 if (!mask)
3468                         continue;
3469
3470                 for (j = 0 + i % 2; j < 8; j += 2) {
3471                         int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3472                         if (cap->speakers[chan_idx] == mask) {
3473                                 /* channel is in a supported position */
3474                                 ok = true;
3475
3476                                 if (i % 2 == 0 && i + 1 < chs) {
3477                                         /* even channel, check the odd companion */
3478                                         int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3479                                         int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3480                                         int comp_mask_act = cap->speakers[comp_chan_idx];
3481
3482                                         if (comp_mask_req == comp_mask_act)
3483                                                 companion_ok = true;
3484                                         else
3485                                                 return -EINVAL;
3486                                 }
3487                                 break;
3488                         }
3489                 }
3490
3491                 if (!ok)
3492                         return -EINVAL;
3493
3494                 if (companion_ok)
3495                         i++; /* companion channel already checked */
3496         }
3497
3498         return 0;
3499 }
3500
3501 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3502                 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3503 {
3504         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3505         int verb;
3506         int ati_channel_setup = 0;
3507
3508         if (hdmi_slot > 7)
3509                 return -EINVAL;
3510
3511         if (!has_amd_full_remap_support(codec)) {
3512                 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3513
3514                 /* In case this is an odd slot but without stream channel, do not
3515                  * disable the slot since the corresponding even slot could have a
3516                  * channel. In case neither have a channel, the slot pair will be
3517                  * disabled when this function is called for the even slot. */
3518                 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3519                         return 0;
3520
3521                 hdmi_slot -= hdmi_slot % 2;
3522
3523                 if (stream_channel != 0xf)
3524                         stream_channel -= stream_channel % 2;
3525         }
3526
3527         verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3528
3529         /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3530
3531         if (stream_channel != 0xf)
3532                 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3533
3534         return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3535 }
3536
3537 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3538                                 hda_nid_t pin_nid, int asp_slot)
3539 {
3540         struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3541         bool was_odd = false;
3542         int ati_asp_slot = asp_slot;
3543         int verb;
3544         int ati_channel_setup;
3545
3546         if (asp_slot > 7)
3547                 return -EINVAL;
3548
3549         if (!has_amd_full_remap_support(codec)) {
3550                 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3551                 if (ati_asp_slot % 2 != 0) {
3552                         ati_asp_slot -= 1;
3553                         was_odd = true;
3554                 }
3555         }
3556
3557         verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3558
3559         ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3560
3561         if (!(ati_channel_setup & ATI_OUT_ENABLE))
3562                 return 0xf;
3563
3564         return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3565 }
3566
3567 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3568                 struct hdac_chmap *chmap,
3569                 struct hdac_cea_channel_speaker_allocation *cap,
3570                 int channels)
3571 {
3572         int c;
3573
3574         /*
3575          * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3576          * we need to take that into account (a single channel may take 2
3577          * channel slots if we need to carry a silent channel next to it).
3578          * On Rev3+ AMD codecs this function is not used.
3579          */
3580         int chanpairs = 0;
3581
3582         /* We only produce even-numbered channel count TLVs */
3583         if ((channels % 2) != 0)
3584                 return -1;
3585
3586         for (c = 0; c < 7; c += 2) {
3587                 if (cap->speakers[c] || cap->speakers[c+1])
3588                         chanpairs++;
3589         }
3590
3591         if (chanpairs * 2 != channels)
3592                 return -1;
3593
3594         return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3595 }
3596
3597 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3598                 struct hdac_cea_channel_speaker_allocation *cap,
3599                 unsigned int *chmap, int channels)
3600 {
3601         /* produce paired maps for pre-rev3 ATI/AMD codecs */
3602         int count = 0;
3603         int c;
3604
3605         for (c = 7; c >= 0; c--) {
3606                 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3607                 int spk = cap->speakers[chan];
3608                 if (!spk) {
3609                         /* add N/A channel if the companion channel is occupied */
3610                         if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3611                                 chmap[count++] = SNDRV_CHMAP_NA;
3612
3613                         continue;
3614                 }
3615
3616                 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3617         }
3618
3619         WARN_ON(count != channels);
3620 }
3621
3622 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3623                                  bool hbr)
3624 {
3625         int hbr_ctl, hbr_ctl_new;
3626
3627         hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3628         if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3629                 if (hbr)
3630                         hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3631                 else
3632                         hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3633
3634                 codec_dbg(codec,
3635                           "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3636                                 pin_nid,
3637                                 hbr_ctl == hbr_ctl_new ? "" : "new-",
3638                                 hbr_ctl_new);
3639
3640                 if (hbr_ctl != hbr_ctl_new)
3641                         snd_hda_codec_write(codec, pin_nid, 0,
3642                                                 ATI_VERB_SET_HBR_CONTROL,
3643                                                 hbr_ctl_new);
3644
3645         } else if (hbr)
3646                 return -EINVAL;
3647
3648         return 0;
3649 }
3650
3651 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3652                                 hda_nid_t pin_nid, u32 stream_tag, int format)
3653 {
3654
3655         if (is_amdhdmi_rev3_or_later(codec)) {
3656                 int ramp_rate = 180; /* default as per AMD spec */
3657                 /* disable ramp-up/down for non-pcm as per AMD spec */
3658                 if (format & AC_FMT_TYPE_NON_PCM)
3659                         ramp_rate = 0;
3660
3661                 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3662         }
3663
3664         return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3665 }
3666
3667
3668 static int atihdmi_init(struct hda_codec *codec)
3669 {
3670         struct hdmi_spec *spec = codec->spec;
3671         int pin_idx, err;
3672
3673         err = generic_hdmi_init(codec);
3674
3675         if (err)
3676                 return err;
3677
3678         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3679                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3680
3681                 /* make sure downmix information in infoframe is zero */
3682                 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3683
3684                 /* enable channel-wise remap mode if supported */
3685                 if (has_amd_full_remap_support(codec))
3686                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3687                                             ATI_VERB_SET_MULTICHANNEL_MODE,
3688                                             ATI_MULTICHANNEL_MODE_SINGLE);
3689         }
3690
3691         return 0;
3692 }
3693
3694 static int patch_atihdmi(struct hda_codec *codec)
3695 {
3696         struct hdmi_spec *spec;
3697         struct hdmi_spec_per_cvt *per_cvt;
3698         int err, cvt_idx;
3699
3700         err = patch_generic_hdmi(codec);
3701
3702         if (err)
3703                 return err;
3704
3705         codec->patch_ops.init = atihdmi_init;
3706
3707         spec = codec->spec;
3708
3709         spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3710         spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3711         spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3712         spec->ops.setup_stream = atihdmi_setup_stream;
3713
3714         spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3715         spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3716
3717         if (!has_amd_full_remap_support(codec)) {
3718                 /* override to ATI/AMD-specific versions with pairwise mapping */
3719                 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3720                         atihdmi_paired_chmap_cea_alloc_validate_get_type;
3721                 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3722                                 atihdmi_paired_cea_alloc_to_tlv_chmap;
3723                 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3724         }
3725
3726         /* ATI/AMD converters do not advertise all of their capabilities */
3727         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3728                 per_cvt = get_cvt(spec, cvt_idx);
3729                 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3730                 per_cvt->rates |= SUPPORTED_RATES;
3731                 per_cvt->formats |= SUPPORTED_FORMATS;
3732                 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3733         }
3734
3735         spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3736
3737         return 0;
3738 }
3739
3740 /* VIA HDMI Implementation */
3741 #define VIAHDMI_CVT_NID 0x02    /* audio converter1 */
3742 #define VIAHDMI_PIN_NID 0x03    /* HDMI output pin1 */
3743
3744 static int patch_via_hdmi(struct hda_codec *codec)
3745 {
3746         return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3747 }
3748
3749 /*
3750  * patch entries
3751  */
3752 static const struct hda_device_id snd_hda_id_hdmi[] = {
3753 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI",       patch_atihdmi),
3754 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI",       patch_atihdmi),
3755 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI",   patch_atihdmi),
3756 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI",        patch_atihdmi),
3757 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI",     patch_generic_hdmi),
3758 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI",     patch_generic_hdmi),
3759 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI",    patch_generic_hdmi),
3760 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI",       patch_nvhdmi_2ch),
3761 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3762 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3763 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI",      patch_nvhdmi_8ch_7x),
3764 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3765 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3766 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI",    patch_nvhdmi_8ch_7x),
3767 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP",   patch_nvhdmi),
3768 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP",   patch_nvhdmi),
3769 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP",   patch_nvhdmi),
3770 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP",   patch_nvhdmi),
3771 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI",       patch_nvhdmi),
3772 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP",   patch_nvhdmi),
3773 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP",   patch_nvhdmi),
3774 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP",   patch_nvhdmi),
3775 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP",   patch_nvhdmi),
3776 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP",   patch_nvhdmi),
3777 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP",   patch_nvhdmi),
3778 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP",   patch_nvhdmi),
3779 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP",   patch_nvhdmi),
3780 /* 17 is known to be absent */
3781 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP",   patch_nvhdmi),
3782 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP",   patch_nvhdmi),
3783 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP",   patch_nvhdmi),
3784 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP",   patch_nvhdmi),
3785 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP",   patch_nvhdmi),
3786 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI",     patch_tegra_hdmi),
3787 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI",    patch_tegra_hdmi),
3788 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI",    patch_tegra_hdmi),
3789 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3790 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP",   patch_nvhdmi),
3791 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP",   patch_nvhdmi),
3792 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP",   patch_nvhdmi),
3793 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP",   patch_nvhdmi),
3794 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP",   patch_nvhdmi),
3795 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP",   patch_nvhdmi),
3796 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP",   patch_nvhdmi),
3797 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP",   patch_nvhdmi),
3798 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP",   patch_nvhdmi),
3799 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP",   patch_nvhdmi),
3800 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP",   patch_nvhdmi),
3801 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP",   patch_nvhdmi),
3802 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI",       patch_nvhdmi_2ch),
3803 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP",   patch_nvhdmi),
3804 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP",   patch_nvhdmi),
3805 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP",   patch_nvhdmi),
3806 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP",   patch_nvhdmi),
3807 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP",   patch_nvhdmi),
3808 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP",   patch_nvhdmi),
3809 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP",   patch_nvhdmi),
3810 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP",   patch_nvhdmi),
3811 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP",   patch_nvhdmi),
3812 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP",   patch_nvhdmi),
3813 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP",   patch_nvhdmi),
3814 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP",   patch_nvhdmi),
3815 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP",   patch_nvhdmi),
3816 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP",   patch_nvhdmi),
3817 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP",   patch_nvhdmi),
3818 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP",   patch_nvhdmi),
3819 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP",   patch_nvhdmi),
3820 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP",   patch_nvhdmi),
3821 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP",   patch_nvhdmi),
3822 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP",   patch_nvhdmi),
3823 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP",   patch_nvhdmi),
3824 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP",   patch_nvhdmi),
3825 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP",   patch_nvhdmi),
3826 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP",   patch_nvhdmi),
3827 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI",       patch_nvhdmi_2ch),
3828 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI",    patch_nvhdmi_2ch),
3829 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP",    patch_via_hdmi),
3830 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP",    patch_via_hdmi),
3831 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP",     patch_generic_hdmi),
3832 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP",     patch_generic_hdmi),
3833 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI",    patch_i915_cpt_hdmi),
3834 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI",    patch_generic_hdmi),
3835 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI",     patch_generic_hdmi),
3836 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI",   patch_generic_hdmi),
3837 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI",    patch_i915_cpt_hdmi),
3838 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3839 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3840 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI",     patch_i915_hsw_hdmi),
3841 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI",   patch_i915_hsw_hdmi),
3842 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI",     patch_i915_hsw_hdmi),
3843 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI",     patch_i915_hsw_hdmi),
3844 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI",    patch_i915_hsw_hdmi),
3845 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI",  patch_i915_glk_hdmi),
3846 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI",  patch_i915_glk_hdmi),
3847 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI",  patch_i915_glk_hdmi),
3848 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI",  patch_generic_hdmi),
3849 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3850 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI",    patch_i915_byt_hdmi),
3851 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI",   patch_generic_hdmi),
3852 /* special ID for generic HDMI */
3853 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3854 {} /* terminator */
3855 };
3856 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3857
3858 MODULE_LICENSE("GPL");
3859 MODULE_DESCRIPTION("HDMI HD-audio codec");
3860 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3861 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3862 MODULE_ALIAS("snd-hda-codec-atihdmi");
3863
3864 static struct hda_codec_driver hdmi_driver = {
3865         .id = snd_hda_id_hdmi,
3866 };
3867
3868 module_hda_codec_driver(hdmi_driver);