sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38
  39 #ifdef CONFIG_X86
  40 /* for snoop control */
  41 #include <asm/pgtable.h>
  42 #include <asm/set_memory.h>
  43 #include <asm/cpufeature.h>
  44 #endif
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include <sound/hdaudio.h>
  48 #include <sound/hda_i915.h>
  49 #include <linux/vgaarb.h>
  50 #include <linux/vga_switcheroo.h>
  51 #include <linux/firmware.h>
  52 #include <sound/hda_codec.h>
  53 #include "hda_controller.h"
  54 #include "hda_intel.h"
  55
  56 #define CREATE_TRACE_POINTS
  57 #include "hda_intel_trace.h"
  58
  59 /* position fix mode */
  60 enum {
  61         POS_FIX_AUTO,
  62         POS_FIX_LPIB,
  63         POS_FIX_POSBUF,
  64         POS_FIX_VIACOMBO,
  65         POS_FIX_COMBO,
  66         POS_FIX_SKL,
  67         POS_FIX_FIFO,
  68 };
  69
  70 /* Defines for ATI HD Audio support in SB450 south bridge */
  71 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  72 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  73
  74 /* Defines for Nvidia HDA support */
  75 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  76 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  77 #define NVIDIA_HDA_ISTRM_COH          0x4d
  78 #define NVIDIA_HDA_OSTRM_COH          0x4c
  79 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  80
  81 /* Defines for Intel SCH HDA snoop control */
  82 #define INTEL_HDA_CGCTL  0x48
  83 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  84 #define INTEL_SCH_HDA_DEVC      0x78
  85 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  86
  87 /* Define IN stream 0 FIFO size offset in VIA controller */
  88 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  89 /* Define VIA HD Audio Device ID*/
  90 #define VIA_HDAC_DEVICE_ID              0x3288
  91
  92 /* max number of SDs */
  93 /* ICH, ATI and VIA have 4 playback and 4 capture */
  94 #define ICH6_NUM_CAPTURE        4
  95 #define ICH6_NUM_PLAYBACK       4
  96
  97 /* ULI has 6 playback and 5 capture */
  98 #define ULI_NUM_CAPTURE         5
  99 #define ULI_NUM_PLAYBACK        6
 100
 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 102 #define ATIHDMI_NUM_CAPTURE     0
 103 #define ATIHDMI_NUM_PLAYBACK    8
 104
 105 /* TERA has 4 playback and 3 capture */
 106 #define TERA_NUM_CAPTURE        3
 107 #define TERA_NUM_PLAYBACK       4
 108
 109
 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 113 static char *model[SNDRV_CARDS];
 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_only[SNDRV_CARDS];
 118 static int jackpoll_ms[SNDRV_CARDS];
 119 static int single_cmd = -1;
 120 static int enable_msi = -1;
 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 122 static char *patch[SNDRV_CARDS];
 123 #endif
 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 126                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 127 #endif
 128
 129 module_param_array(index, int, NULL, 0444);
 130 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 131 module_param_array(id, charp, NULL, 0444);
 132 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 133 module_param_array(enable, bool, NULL, 0444);
 134 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 135 module_param_array(model, charp, NULL, 0444);
 136 MODULE_PARM_DESC(model, "Use the given board model.");
 137 module_param_array(position_fix, int, NULL, 0444);
 138 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 139                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 140 module_param_array(bdl_pos_adj, int, NULL, 0644);
 141 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 142 module_param_array(probe_mask, int, NULL, 0444);
 143 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 144 module_param_array(probe_only, int, NULL, 0444);
 145 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 146 module_param_array(jackpoll_ms, int, NULL, 0444);
 147 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 148 module_param(single_cmd, bint, 0444);
 149 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 150                  "(for debugging only).");
 151 module_param(enable_msi, bint, 0444);
 152 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 153 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 154 module_param_array(patch, charp, NULL, 0444);
 155 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 156 #endif
 157 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 158 module_param_array(beep_mode, bool, NULL, 0444);
 159 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 160                             "(0=off, 1=on) (default=1).");
 161 #endif
 162
 163 #ifdef CONFIG_PM
 164 static int param_set_xint(const char *val, const struct kernel_param *kp);
 165 static const struct kernel_param_ops param_ops_xint = {
 166         .set = param_set_xint,
 167         .get = param_get_int,
 168 };
 169 #define param_check_xint param_check_int
 170
 171 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 172 module_param(power_save, xint, 0644);
 173 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 174                  "(in second, 0 = disable).");
 175
 176 static bool pm_blacklist = true;
 177 module_param(pm_blacklist, bool, 0644);
 178 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 179
 180 /* reset the HD-audio controller in power save mode.
 181  * this may give more power-saving, but will take longer time to
 182  * wake up.
 183  */
 184 static bool power_save_controller = 1;
 185 module_param(power_save_controller, bool, 0644);
 186 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 187 #else
 188 #define power_save      0
 189 #endif /* CONFIG_PM */
 190
 191 static int align_buffer_size = -1;
 192 module_param(align_buffer_size, bint, 0644);
 193 MODULE_PARM_DESC(align_buffer_size,
 194                 "Force buffer and period sizes to be multiple of 128 bytes.");
 195
 196 #ifdef CONFIG_X86
 197 static int hda_snoop = -1;
 198 module_param_named(snoop, hda_snoop, bint, 0444);
 199 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 200 #else
 201 #define hda_snoop               true
 202 #endif
 203
 204
 205 MODULE_LICENSE("GPL");
 206 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 207                          "{Intel, ICH6M},"
 208                          "{Intel, ICH7},"
 209                          "{Intel, ESB2},"
 210                          "{Intel, ICH8},"
 211                          "{Intel, ICH9},"
 212                          "{Intel, ICH10},"
 213                          "{Intel, PCH},"
 214                          "{Intel, CPT},"
 215                          "{Intel, PPT},"
 216                          "{Intel, LPT},"
 217                          "{Intel, LPT_LP},"
 218                          "{Intel, WPT_LP},"
 219                          "{Intel, SPT},"
 220                          "{Intel, SPT_LP},"
 221                          "{Intel, HPT},"
 222                          "{Intel, PBG},"
 223                          "{Intel, SCH},"
 224                          "{ATI, SB450},"
 225                          "{ATI, SB600},"
 226                          "{ATI, RS600},"
 227                          "{ATI, RS690},"
 228                          "{ATI, RS780},"
 229                          "{ATI, R600},"
 230                          "{ATI, RV630},"
 231                          "{ATI, RV610},"
 232                          "{ATI, RV670},"
 233                          "{ATI, RV635},"
 234                          "{ATI, RV620},"
 235                          "{ATI, RV770},"
 236                          "{VIA, VT8251},"
 237                          "{VIA, VT8237A},"
 238                          "{SiS, SIS966},"
 239                          "{ULI, M5461}}");
 240 MODULE_DESCRIPTION("Intel HDA driver");
 241
 242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 244 #define SUPPORT_VGA_SWITCHEROO
 245 #endif
 246 #endif
 247
 248
 249 /*
 250  */
 251
 252 /* driver types */
 253 enum {
 254         AZX_DRIVER_ICH,
 255         AZX_DRIVER_PCH,
 256         AZX_DRIVER_SCH,
 257         AZX_DRIVER_SKL,
 258         AZX_DRIVER_HDMI,
 259         AZX_DRIVER_ATI,
 260         AZX_DRIVER_ATIHDMI,
 261         AZX_DRIVER_ATIHDMI_NS,
 262         AZX_DRIVER_VIA,
 263         AZX_DRIVER_SIS,
 264         AZX_DRIVER_ULI,
 265         AZX_DRIVER_NVIDIA,
 266         AZX_DRIVER_TERA,
 267         AZX_DRIVER_CTX,
 268         AZX_DRIVER_CTHDA,
 269         AZX_DRIVER_CMEDIA,
 270         AZX_DRIVER_GENERIC,
 271         AZX_NUM_DRIVERS, /* keep this as last entry */
 272 };
 273
 274 #define azx_get_snoop_type(chip) \
 275         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 276 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 277
 278 /* quirks for old Intel chipsets */
 279 #define AZX_DCAPS_INTEL_ICH \
 280         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 281
 282 /* quirks for Intel PCH */
 283 #define AZX_DCAPS_INTEL_PCH_BASE \
 284         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 285          AZX_DCAPS_SNOOP_TYPE(SCH))
 286
 287 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 288 #define AZX_DCAPS_INTEL_PCH_NOPM \
 289         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 290
 291 /* PCH for HSW/BDW; with runtime PM */
 292 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 293 #define AZX_DCAPS_INTEL_PCH \
 294         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 295
 296 /* HSW HDMI */
 297 #define AZX_DCAPS_INTEL_HASWELL \
 298         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 299          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 300          AZX_DCAPS_SNOOP_TYPE(SCH))
 301
 302 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 303 #define AZX_DCAPS_INTEL_BROADWELL \
 304         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 305          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 306          AZX_DCAPS_SNOOP_TYPE(SCH))
 307
 308 #define AZX_DCAPS_INTEL_BAYTRAIL \
 309         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 310
 311 #define AZX_DCAPS_INTEL_BRASWELL \
 312         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 313          AZX_DCAPS_I915_COMPONENT)
 314
 315 #define AZX_DCAPS_INTEL_SKYLAKE \
 316         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 317          AZX_DCAPS_SYNC_WRITE |\
 318          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 319
 320 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 321
 322 /* quirks for ATI SB / AMD Hudson */
 323 #define AZX_DCAPS_PRESET_ATI_SB \
 324         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 325          AZX_DCAPS_SNOOP_TYPE(ATI))
 326
 327 /* quirks for ATI/AMD HDMI */
 328 #define AZX_DCAPS_PRESET_ATI_HDMI \
 329         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 330          AZX_DCAPS_NO_MSI64)
 331
 332 /* quirks for ATI HDMI with snoop off */
 333 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 334         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 335
 336 /* quirks for AMD SB */
 337 #define AZX_DCAPS_PRESET_AMD_SB \
 338         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 339          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 340
 341 /* quirks for Nvidia */
 342 #define AZX_DCAPS_PRESET_NVIDIA \
 343         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 344          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 345
 346 #define AZX_DCAPS_PRESET_CTHDA \
 347         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 348          AZX_DCAPS_NO_64BIT |\
 349          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 350
 351 /*
 352  * vga_switcheroo support
 353  */
 354 #ifdef SUPPORT_VGA_SWITCHEROO
 355 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 356 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 357 #else
 358 #define use_vga_switcheroo(chip)        0
 359 #define needs_eld_notify_link(chip)     false
 360 #endif
 361
 362 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 363                                         ((pci)->device == 0x0c0c) || \
 364                                         ((pci)->device == 0x0d0c) || \
 365                                         ((pci)->device == 0x160c))
 366
 367 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 368 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 369 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 370
 371 static char *driver_short_names[] = {
 372         [AZX_DRIVER_ICH] = "HDA Intel",
 373         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 374         [AZX_DRIVER_SCH] = "HDA Intel MID",
 375         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 376         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 377         [AZX_DRIVER_ATI] = "HDA ATI SB",
 378         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 379         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 380         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 381         [AZX_DRIVER_SIS] = "HDA SIS966",
 382         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 383         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 384         [AZX_DRIVER_TERA] = "HDA Teradici",
 385         [AZX_DRIVER_CTX] = "HDA Creative",
 386         [AZX_DRIVER_CTHDA] = "HDA Creative",
 387         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 388         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 389 };
 390
 391 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 392 static void set_default_power_save(struct azx *chip);
 393
 394 /*
 395  * initialize the PCI registers
 396  */
 397 /* update bits in a PCI register byte */
 398 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 399                             unsigned char mask, unsigned char val)
 400 {
 401         unsigned char data;
 402
 403         pci_read_config_byte(pci, reg, &data);
 404         data &= ~mask;
 405         data |= (val & mask);
 406         pci_write_config_byte(pci, reg, data);
 407 }
 408
 409 static void azx_init_pci(struct azx *chip)
 410 {
 411         int snoop_type = azx_get_snoop_type(chip);
 412
 413         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 414          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 415          * Ensuring these bits are 0 clears playback static on some HD Audio
 416          * codecs.
 417          * The PCI register TCSEL is defined in the Intel manuals.
 418          */
 419         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 420                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 421                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 422         }
 423
 424         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 425          * we need to enable snoop.
 426          */
 427         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 428                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 429                         azx_snoop(chip));
 430                 update_pci_byte(chip->pci,
 431                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 432                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 433         }
 434
 435         /* For NVIDIA HDA, enable snoop */
 436         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 437                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 438                         azx_snoop(chip));
 439                 update_pci_byte(chip->pci,
 440                                 NVIDIA_HDA_TRANSREG_ADDR,
 441                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 442                 update_pci_byte(chip->pci,
 443                                 NVIDIA_HDA_ISTRM_COH,
 444                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 445                 update_pci_byte(chip->pci,
 446                                 NVIDIA_HDA_OSTRM_COH,
 447                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 448         }
 449
 450         /* Enable SCH/PCH snoop if needed */
 451         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 452                 unsigned short snoop;
 453                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 454                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 455                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 456                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 457                         if (!azx_snoop(chip))
 458                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 459                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 460                         pci_read_config_word(chip->pci,
 461                                 INTEL_SCH_HDA_DEVC, &snoop);
 462                 }
 463                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 464                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 465                         "Disabled" : "Enabled");
 466         }
 467 }
 468
 469 /*
 470  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 471  * and makes an audio stream sensitive to system latencies when
 472  * 24/32 bits are playing.
 473  * Adjusting threshold of DMA fifo to force the DMA request
 474  * sooner to improve latency tolerance at the expense of power.
 475  */
 476 static void bxt_reduce_dma_latency(struct azx *chip)
 477 {
 478         u32 val;
 479
 480         val = azx_readl(chip, VS_EM4L);
 481         val &= (0x3 << 20);
 482         azx_writel(chip, VS_EM4L, val);
 483 }
 484
 485 /*
 486  * ML_LCAP bits:
 487  *  bit 0: 6 MHz Supported
 488  *  bit 1: 12 MHz Supported
 489  *  bit 2: 24 MHz Supported
 490  *  bit 3: 48 MHz Supported
 491  *  bit 4: 96 MHz Supported
 492  *  bit 5: 192 MHz Supported
 493  */
 494 static int intel_get_lctl_scf(struct azx *chip)
 495 {
 496         struct hdac_bus *bus = azx_bus(chip);
 497         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 498         u32 val, t;
 499         int i;
 500
 501         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 502
 503         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 504                 t = preferred_bits[i];
 505                 if (val & (1 << t))
 506                         return t;
 507         }
 508
 509         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 510         return 0;
 511 }
 512
 513 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 514 {
 515         struct hdac_bus *bus = azx_bus(chip);
 516         u32 val;
 517         int timeout;
 518
 519         /*
 520          * the codecs are sharing the first link setting by default
 521          * If other links are enabled for stream, they need similar fix
 522          */
 523         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 524         val &= ~AZX_MLCTL_SPA;
 525         val |= state << AZX_MLCTL_SPA_SHIFT;
 526         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 527         /* wait for CPA */
 528         timeout = 50;
 529         while (timeout) {
 530                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 531                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 532                         return 0;
 533                 timeout--;
 534                 udelay(10);
 535         }
 536
 537         return -1;
 538 }
 539
 540 static void intel_init_lctl(struct azx *chip)
 541 {
 542         struct hdac_bus *bus = azx_bus(chip);
 543         u32 val;
 544         int ret;
 545
 546         /* 0. check lctl register value is correct or not */
 547         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 548         /* if SCF is already set, let's use it */
 549         if ((val & ML_LCTL_SCF_MASK) != 0)
 550                 return;
 551
 552         /*
 553          * Before operating on SPA, CPA must match SPA.
 554          * Any deviation may result in undefined behavior.
 555          */
 556         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 557                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 558                 return;
 559
 560         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 561         ret = intel_ml_lctl_set_power(chip, 0);
 562         udelay(100);
 563         if (ret)
 564                 goto set_spa;
 565
 566         /* 2. update SCF to select a properly audio clock*/
 567         val &= ~ML_LCTL_SCF_MASK;
 568         val |= intel_get_lctl_scf(chip);
 569         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 570
 571 set_spa:
 572         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 573         intel_ml_lctl_set_power(chip, 1);
 574         udelay(100);
 575 }
 576
 577 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 578 {
 579         struct hdac_bus *bus = azx_bus(chip);
 580         struct pci_dev *pci = chip->pci;
 581         u32 val;
 582
 583         snd_hdac_set_codec_wakeup(bus, true);
 584         if (chip->driver_type == AZX_DRIVER_SKL) {
 585                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 586                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 587                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 588         }
 589         azx_init_chip(chip, full_reset);
 590         if (chip->driver_type == AZX_DRIVER_SKL) {
 591                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 592                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 593                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 594         }
 595
 596         snd_hdac_set_codec_wakeup(bus, false);
 597
 598         /* reduce dma latency to avoid noise */
 599         if (IS_BXT(pci))
 600                 bxt_reduce_dma_latency(chip);
 601
 602         if (bus->mlcap != NULL)
 603                 intel_init_lctl(chip);
 604 }
 605
 606 /* calculate runtime delay from LPIB */
 607 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 608                                    unsigned int pos)
 609 {
 610         struct snd_pcm_substream *substream = azx_dev->core.substream;
 611         int stream = substream->stream;
 612         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 613         int delay;
 614
 615         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 616                 delay = pos - lpib_pos;
 617         else
 618                 delay = lpib_pos - pos;
 619         if (delay < 0) {
 620                 if (delay >= azx_dev->core.delay_negative_threshold)
 621                         delay = 0;
 622                 else
 623                         delay += azx_dev->core.bufsize;
 624         }
 625
 626         if (delay >= azx_dev->core.period_bytes) {
 627                 dev_info(chip->card->dev,
 628                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 629                          delay, azx_dev->core.period_bytes);
 630                 delay = 0;
 631                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 632                 chip->get_delay[stream] = NULL;
 633         }
 634
 635         return bytes_to_frames(substream->runtime, delay);
 636 }
 637
 638 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 639
 640 /* called from IRQ */
 641 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 642 {
 643         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 644         int ok;
 645
 646         ok = azx_position_ok(chip, azx_dev);
 647         if (ok == 1) {
 648                 azx_dev->irq_pending = 0;
 649                 return ok;
 650         } else if (ok == 0) {
 651                 /* bogus IRQ, process it later */
 652                 azx_dev->irq_pending = 1;
 653                 schedule_work(&hda->irq_pending_work);
 654         }
 655         return 0;
 656 }
 657
 658 #define display_power(chip, enable) \
 659         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 660
 661 /*
 662  * Check whether the current DMA position is acceptable for updating
 663  * periods.  Returns non-zero if it's OK.
 664  *
 665  * Many HD-audio controllers appear pretty inaccurate about
 666  * the update-IRQ timing.  The IRQ is issued before actually the
 667  * data is processed.  So, we need to process it afterwords in a
 668  * workqueue.
 669  */
 670 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 671 {
 672         struct snd_pcm_substream *substream = azx_dev->core.substream;
 673         int stream = substream->stream;
 674         u32 wallclk;
 675         unsigned int pos;
 676
 677         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 678         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 679                 return -1;      /* bogus (too early) interrupt */
 680
 681         if (chip->get_position[stream])
 682                 pos = chip->get_position[stream](chip, azx_dev);
 683         else { /* use the position buffer as default */
 684                 pos = azx_get_pos_posbuf(chip, azx_dev);
 685                 if (!pos || pos == (u32)-1) {
 686                         dev_info(chip->card->dev,
 687                                  "Invalid position buffer, using LPIB read method instead.\n");
 688                         chip->get_position[stream] = azx_get_pos_lpib;
 689                         if (chip->get_position[0] == azx_get_pos_lpib &&
 690                             chip->get_position[1] == azx_get_pos_lpib)
 691                                 azx_bus(chip)->use_posbuf = false;
 692                         pos = azx_get_pos_lpib(chip, azx_dev);
 693                         chip->get_delay[stream] = NULL;
 694                 } else {
 695                         chip->get_position[stream] = azx_get_pos_posbuf;
 696                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 697                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 698                 }
 699         }
 700
 701         if (pos >= azx_dev->core.bufsize)
 702                 pos = 0;
 703
 704         if (WARN_ONCE(!azx_dev->core.period_bytes,
 705                       "hda-intel: zero azx_dev->period_bytes"))
 706                 return -1; /* this shouldn't happen! */
 707         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 708             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 709                 /* NG - it's below the first next period boundary */
 710                 return chip->bdl_pos_adj ? 0 : -1;
 711         azx_dev->core.start_wallclk += wallclk;
 712         return 1; /* OK, it's fine */
 713 }
 714
 715 /*
 716  * The work for pending PCM period updates.
 717  */
 718 static void azx_irq_pending_work(struct work_struct *work)
 719 {
 720         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 721         struct azx *chip = &hda->chip;
 722         struct hdac_bus *bus = azx_bus(chip);
 723         struct hdac_stream *s;
 724         int pending, ok;
 725
 726         if (!hda->irq_pending_warned) {
 727                 dev_info(chip->card->dev,
 728                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 729                          chip->card->number);
 730                 hda->irq_pending_warned = 1;
 731         }
 732
 733         for (;;) {
 734                 pending = 0;
 735                 spin_lock_irq(&bus->reg_lock);
 736                 list_for_each_entry(s, &bus->stream_list, list) {
 737                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 738                         if (!azx_dev->irq_pending ||
 739                             !s->substream ||
 740                             !s->running)
 741                                 continue;
 742                         ok = azx_position_ok(chip, azx_dev);
 743                         if (ok > 0) {
 744                                 azx_dev->irq_pending = 0;
 745                                 spin_unlock(&bus->reg_lock);
 746                                 snd_pcm_period_elapsed(s->substream);
 747                                 spin_lock(&bus->reg_lock);
 748                         } else if (ok < 0) {
 749                                 pending = 0;    /* too early */
 750                         } else
 751                                 pending++;
 752                 }
 753                 spin_unlock_irq(&bus->reg_lock);
 754                 if (!pending)
 755                         return;
 756                 msleep(1);
 757         }
 758 }
 759
 760 /* clear irq_pending flags and assure no on-going workq */
 761 static void azx_clear_irq_pending(struct azx *chip)
 762 {
 763         struct hdac_bus *bus = azx_bus(chip);
 764         struct hdac_stream *s;
 765
 766         spin_lock_irq(&bus->reg_lock);
 767         list_for_each_entry(s, &bus->stream_list, list) {
 768                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 769                 azx_dev->irq_pending = 0;
 770         }
 771         spin_unlock_irq(&bus->reg_lock);
 772 }
 773
 774 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 775 {
 776         struct hdac_bus *bus = azx_bus(chip);
 777
 778         if (request_irq(chip->pci->irq, azx_interrupt,
 779                         chip->msi ? 0 : IRQF_SHARED,
 780                         chip->card->irq_descr, chip)) {
 781                 dev_err(chip->card->dev,
 782                         "unable to grab IRQ %d, disabling device\n",
 783                         chip->pci->irq);
 784                 if (do_disconnect)
 785                         snd_card_disconnect(chip->card);
 786                 return -1;
 787         }
 788         bus->irq = chip->pci->irq;
 789         pci_intx(chip->pci, !chip->msi);
 790         return 0;
 791 }
 792
 793 /* get the current DMA position with correction on VIA chips */
 794 static unsigned int azx_via_get_position(struct azx *chip,
 795                                          struct azx_dev *azx_dev)
 796 {
 797         unsigned int link_pos, mini_pos, bound_pos;
 798         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 799         unsigned int fifo_size;
 800
 801         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 802         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 803                 /* Playback, no problem using link position */
 804                 return link_pos;
 805         }
 806
 807         /* Capture */
 808         /* For new chipset,
 809          * use mod to get the DMA position just like old chipset
 810          */
 811         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 812         mod_dma_pos %= azx_dev->core.period_bytes;
 813
 814         /* azx_dev->fifo_size can't get FIFO size of in stream.
 815          * Get from base address + offset.
 816          */
 817         fifo_size = readw(azx_bus(chip)->remap_addr +
 818                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 819
 820         if (azx_dev->insufficient) {
 821                 /* Link position never gather than FIFO size */
 822                 if (link_pos <= fifo_size)
 823                         return 0;
 824
 825                 azx_dev->insufficient = 0;
 826         }
 827
 828         if (link_pos <= fifo_size)
 829                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 830         else
 831                 mini_pos = link_pos - fifo_size;
 832
 833         /* Find nearest previous boudary */
 834         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 835         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 836         if (mod_link_pos >= fifo_size)
 837                 bound_pos = link_pos - mod_link_pos;
 838         else if (mod_dma_pos >= mod_mini_pos)
 839                 bound_pos = mini_pos - mod_mini_pos;
 840         else {
 841                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 842                 if (bound_pos >= azx_dev->core.bufsize)
 843                         bound_pos = 0;
 844         }
 845
 846         /* Calculate real DMA position we want */
 847         return bound_pos + mod_dma_pos;
 848 }
 849
 850 #define AMD_FIFO_SIZE   32
 851
 852 /* get the current DMA position with FIFO size correction */
 853 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 854 {
 855         struct snd_pcm_substream *substream = azx_dev->core.substream;
 856         struct snd_pcm_runtime *runtime = substream->runtime;
 857         unsigned int pos, delay;
 858
 859         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 860         if (!runtime)
 861                 return pos;
 862
 863         runtime->delay = AMD_FIFO_SIZE;
 864         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 865         if (azx_dev->insufficient) {
 866                 if (pos < delay) {
 867                         delay = pos;
 868                         runtime->delay = bytes_to_frames(runtime, pos);
 869                 } else {
 870                         azx_dev->insufficient = 0;
 871                 }
 872         }
 873
 874         /* correct the DMA position for capture stream */
 875         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 876                 if (pos < delay)
 877                         pos += azx_dev->core.bufsize;
 878                 pos -= delay;
 879         }
 880
 881         return pos;
 882 }
 883
 884 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 885                                    unsigned int pos)
 886 {
 887         struct snd_pcm_substream *substream = azx_dev->core.substream;
 888
 889         /* just read back the calculated value in the above */
 890         return substream->runtime->delay;
 891 }
 892
 893 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 894                                          struct azx_dev *azx_dev)
 895 {
 896         return _snd_hdac_chip_readl(azx_bus(chip),
 897                                     AZX_REG_VS_SDXDPIB_XBASE +
 898                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 899                                      azx_dev->core.index));
 900 }
 901
 902 /* get the current DMA position with correction on SKL+ chips */
 903 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 904 {
 905         /* DPIB register gives a more accurate position for playback */
 906         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 907                 return azx_skl_get_dpib_pos(chip, azx_dev);
 908
 909         /* For capture, we need to read posbuf, but it requires a delay
 910          * for the possible boundary overlap; the read of DPIB fetches the
 911          * actual posbuf
 912          */
 913         udelay(20);
 914         azx_skl_get_dpib_pos(chip, azx_dev);
 915         return azx_get_pos_posbuf(chip, azx_dev);
 916 }
 917
 918 #ifdef CONFIG_PM
 919 static DEFINE_MUTEX(card_list_lock);
 920 static LIST_HEAD(card_list);
 921
 922 static void azx_add_card_list(struct azx *chip)
 923 {
 924         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 925         mutex_lock(&card_list_lock);
 926         list_add(&hda->list, &card_list);
 927         mutex_unlock(&card_list_lock);
 928 }
 929
 930 static void azx_del_card_list(struct azx *chip)
 931 {
 932         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 933         mutex_lock(&card_list_lock);
 934         list_del_init(&hda->list);
 935         mutex_unlock(&card_list_lock);
 936 }
 937
 938 /* trigger power-save check at writing parameter */
 939 static int param_set_xint(const char *val, const struct kernel_param *kp)
 940 {
 941         struct hda_intel *hda;
 942         struct azx *chip;
 943         int prev = power_save;
 944         int ret = param_set_int(val, kp);
 945
 946         if (ret || prev == power_save)
 947                 return ret;
 948
 949         mutex_lock(&card_list_lock);
 950         list_for_each_entry(hda, &card_list, list) {
 951                 chip = &hda->chip;
 952                 if (!hda->probe_continued || chip->disabled)
 953                         continue;
 954                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 955         }
 956         mutex_unlock(&card_list_lock);
 957         return 0;
 958 }
 959
 960 /*
 961  * power management
 962  */
 963 static bool azx_is_pm_ready(struct snd_card *card)
 964 {
 965         struct azx *chip;
 966         struct hda_intel *hda;
 967
 968         if (!card)
 969                 return false;
 970         chip = card->private_data;
 971         hda = container_of(chip, struct hda_intel, chip);
 972         if (chip->disabled || hda->init_failed || !chip->running)
 973                 return false;
 974         return true;
 975 }
 976
 977 static void __azx_runtime_suspend(struct azx *chip)
 978 {
 979         azx_stop_chip(chip);
 980         azx_enter_link_reset(chip);
 981         azx_clear_irq_pending(chip);
 982         display_power(chip, false);
 983 }
 984
 985 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 986 {
 987         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 988         struct hdac_bus *bus = azx_bus(chip);
 989         struct hda_codec *codec;
 990         int status;
 991
 992         display_power(chip, true);
 993         if (hda->need_i915_power)
 994                 snd_hdac_i915_set_bclk(bus);
 995
 996         /* Read STATESTS before controller reset */
 997         status = azx_readw(chip, STATESTS);
 998
 999         azx_init_pci(chip);
1000         hda_intel_init_chip(chip, true);
1001
1002         if (status && from_rt) {
1003                 list_for_each_codec(codec, &chip->bus)
1004                         if (status & (1 << codec->addr))
1005                                 schedule_delayed_work(&codec->jackpoll_work,
1006                                                       codec->jackpoll_interval);
1007         }
1008
1009         /* power down again for link-controlled chips */
1010         if (!hda->need_i915_power)
1011                 display_power(chip, false);
1012 }
1013
1014 #ifdef CONFIG_PM_SLEEP
1015 static int azx_suspend(struct device *dev)
1016 {
1017         struct snd_card *card = dev_get_drvdata(dev);
1018         struct azx *chip;
1019         struct hdac_bus *bus;
1020
1021         if (!azx_is_pm_ready(card))
1022                 return 0;
1023
1024         chip = card->private_data;
1025         bus = azx_bus(chip);
1026         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1027         __azx_runtime_suspend(chip);
1028         if (bus->irq >= 0) {
1029                 free_irq(bus->irq, chip);
1030                 bus->irq = -1;
1031         }
1032
1033         if (chip->msi)
1034                 pci_disable_msi(chip->pci);
1035
1036         trace_azx_suspend(chip);
1037         return 0;
1038 }
1039
1040 static int azx_resume(struct device *dev)
1041 {
1042         struct snd_card *card = dev_get_drvdata(dev);
1043         struct azx *chip;
1044
1045         if (!azx_is_pm_ready(card))
1046                 return 0;
1047
1048         chip = card->private_data;
1049         if (chip->msi)
1050                 if (pci_enable_msi(chip->pci) < 0)
1051                         chip->msi = 0;
1052         if (azx_acquire_irq(chip, 1) < 0)
1053                 return -EIO;
1054         __azx_runtime_resume(chip, false);
1055         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1056
1057         trace_azx_resume(chip);
1058         return 0;
1059 }
1060
1061 /* put codec down to D3 at hibernation for Intel SKL+;
1062  * otherwise BIOS may still access the codec and screw up the driver
1063  */
1064 static int azx_freeze_noirq(struct device *dev)
1065 {
1066         struct snd_card *card = dev_get_drvdata(dev);
1067         struct azx *chip = card->private_data;
1068         struct pci_dev *pci = to_pci_dev(dev);
1069
1070         if (chip->driver_type == AZX_DRIVER_SKL)
1071                 pci_set_power_state(pci, PCI_D3hot);
1072
1073         return 0;
1074 }
1075
1076 static int azx_thaw_noirq(struct device *dev)
1077 {
1078         struct snd_card *card = dev_get_drvdata(dev);
1079         struct azx *chip = card->private_data;
1080         struct pci_dev *pci = to_pci_dev(dev);
1081
1082         if (chip->driver_type == AZX_DRIVER_SKL)
1083                 pci_set_power_state(pci, PCI_D0);
1084
1085         return 0;
1086 }
1087 #endif /* CONFIG_PM_SLEEP */
1088
1089 static int azx_runtime_suspend(struct device *dev)
1090 {
1091         struct snd_card *card = dev_get_drvdata(dev);
1092         struct azx *chip;
1093
1094         if (!azx_is_pm_ready(card))
1095                 return 0;
1096         chip = card->private_data;
1097         if (!azx_has_pm_runtime(chip))
1098                 return 0;
1099
1100         /* enable controller wake up event */
1101         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1102                   STATESTS_INT_MASK);
1103
1104         __azx_runtime_suspend(chip);
1105         trace_azx_runtime_suspend(chip);
1106         return 0;
1107 }
1108
1109 static int azx_runtime_resume(struct device *dev)
1110 {
1111         struct snd_card *card = dev_get_drvdata(dev);
1112         struct azx *chip;
1113
1114         if (!azx_is_pm_ready(card))
1115                 return 0;
1116         chip = card->private_data;
1117         if (!azx_has_pm_runtime(chip))
1118                 return 0;
1119         __azx_runtime_resume(chip, true);
1120
1121         /* disable controller Wake Up event*/
1122         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1123                         ~STATESTS_INT_MASK);
1124
1125         trace_azx_runtime_resume(chip);
1126         return 0;
1127 }
1128
1129 static int azx_runtime_idle(struct device *dev)
1130 {
1131         struct snd_card *card = dev_get_drvdata(dev);
1132         struct azx *chip;
1133         struct hda_intel *hda;
1134
1135         if (!card)
1136                 return 0;
1137
1138         chip = card->private_data;
1139         hda = container_of(chip, struct hda_intel, chip);
1140         if (chip->disabled || hda->init_failed)
1141                 return 0;
1142
1143         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1144             azx_bus(chip)->codec_powered || !chip->running)
1145                 return -EBUSY;
1146
1147         /* ELD notification gets broken when HD-audio bus is off */
1148         if (needs_eld_notify_link(hda))
1149                 return -EBUSY;
1150
1151         return 0;
1152 }
1153
1154 static const struct dev_pm_ops azx_pm = {
1155         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1156 #ifdef CONFIG_PM_SLEEP
1157         .freeze_noirq = azx_freeze_noirq,
1158         .thaw_noirq = azx_thaw_noirq,
1159 #endif
1160         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1161 };
1162
1163 #define AZX_PM_OPS      &azx_pm
1164 #else
1165 #define azx_add_card_list(chip) /* NOP */
1166 #define azx_del_card_list(chip) /* NOP */
1167 #define AZX_PM_OPS      NULL
1168 #endif /* CONFIG_PM */
1169
1170
1171 static int azx_probe_continue(struct azx *chip);
1172
1173 #ifdef SUPPORT_VGA_SWITCHEROO
1174 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1175
1176 static void azx_vs_set_state(struct pci_dev *pci,
1177                              enum vga_switcheroo_state state)
1178 {
1179         struct snd_card *card = pci_get_drvdata(pci);
1180         struct azx *chip = card->private_data;
1181         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1182         struct hda_codec *codec;
1183         bool disabled;
1184
1185         wait_for_completion(&hda->probe_wait);
1186         if (hda->init_failed)
1187                 return;
1188
1189         disabled = (state == VGA_SWITCHEROO_OFF);
1190         if (chip->disabled == disabled)
1191                 return;
1192
1193         if (!hda->probe_continued) {
1194                 chip->disabled = disabled;
1195                 if (!disabled) {
1196                         dev_info(chip->card->dev,
1197                                  "Start delayed initialization\n");
1198                         if (azx_probe_continue(chip) < 0) {
1199                                 dev_err(chip->card->dev, "initialization error\n");
1200                                 hda->init_failed = true;
1201                         }
1202                 }
1203         } else {
1204                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1205                          disabled ? "Disabling" : "Enabling");
1206                 if (disabled) {
1207                         list_for_each_codec(codec, &chip->bus) {
1208                                 pm_runtime_suspend(hda_codec_dev(codec));
1209                                 pm_runtime_disable(hda_codec_dev(codec));
1210                         }
1211                         pm_runtime_suspend(card->dev);
1212                         pm_runtime_disable(card->dev);
1213                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1214                          * however we have no ACPI handle, so pci/acpi can't put us there,
1215                          * put ourselves there */
1216                         pci->current_state = PCI_D3cold;
1217                         chip->disabled = true;
1218                         if (snd_hda_lock_devices(&chip->bus))
1219                                 dev_warn(chip->card->dev,
1220                                          "Cannot lock devices!\n");
1221                 } else {
1222                         snd_hda_unlock_devices(&chip->bus);
1223                         chip->disabled = false;
1224                         pm_runtime_enable(card->dev);
1225                         list_for_each_codec(codec, &chip->bus) {
1226                                 pm_runtime_enable(hda_codec_dev(codec));
1227                                 pm_runtime_resume(hda_codec_dev(codec));
1228                         }
1229                 }
1230         }
1231 }
1232
1233 static bool azx_vs_can_switch(struct pci_dev *pci)
1234 {
1235         struct snd_card *card = pci_get_drvdata(pci);
1236         struct azx *chip = card->private_data;
1237         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1238
1239         wait_for_completion(&hda->probe_wait);
1240         if (hda->init_failed)
1241                 return false;
1242         if (chip->disabled || !hda->probe_continued)
1243                 return true;
1244         if (snd_hda_lock_devices(&chip->bus))
1245                 return false;
1246         snd_hda_unlock_devices(&chip->bus);
1247         return true;
1248 }
1249
1250 /*
1251  * The discrete GPU cannot power down unless the HDA controller runtime
1252  * suspends, so activate runtime PM on codecs even if power_save == 0.
1253  */
1254 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1255 {
1256         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1257         struct hda_codec *codec;
1258
1259         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1260                 list_for_each_codec(codec, &chip->bus)
1261                         codec->auto_runtime_pm = 1;
1262                 /* reset the power save setup */
1263                 if (chip->running)
1264                         set_default_power_save(chip);
1265         }
1266 }
1267
1268 static void azx_vs_gpu_bound(struct pci_dev *pci,
1269                              enum vga_switcheroo_client_id client_id)
1270 {
1271         struct snd_card *card = pci_get_drvdata(pci);
1272         struct azx *chip = card->private_data;
1273         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1274
1275         if (client_id == VGA_SWITCHEROO_DIS)
1276                 hda->need_eld_notify_link = 0;
1277         setup_vga_switcheroo_runtime_pm(chip);
1278 }
1279
1280 static void init_vga_switcheroo(struct azx *chip)
1281 {
1282         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1283         struct pci_dev *p = get_bound_vga(chip->pci);
1284         if (p) {
1285                 dev_info(chip->card->dev,
1286                          "Handle vga_switcheroo audio client\n");
1287                 hda->use_vga_switcheroo = 1;
1288                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1289                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1290                 pci_dev_put(p);
1291         }
1292 }
1293
1294 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1295         .set_gpu_state = azx_vs_set_state,
1296         .can_switch = azx_vs_can_switch,
1297         .gpu_bound = azx_vs_gpu_bound,
1298 };
1299
1300 static int register_vga_switcheroo(struct azx *chip)
1301 {
1302         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1303         struct pci_dev *p;
1304         int err;
1305
1306         if (!hda->use_vga_switcheroo)
1307                 return 0;
1308
1309         p = get_bound_vga(chip->pci);
1310         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1311         pci_dev_put(p);
1312
1313         if (err < 0)
1314                 return err;
1315         hda->vga_switcheroo_registered = 1;
1316
1317         return 0;
1318 }
1319 #else
1320 #define init_vga_switcheroo(chip)               /* NOP */
1321 #define register_vga_switcheroo(chip)           0
1322 #define check_hdmi_disabled(pci)        false
1323 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1324 #endif /* SUPPORT_VGA_SWITCHER */
1325
1326 /*
1327  * destructor
1328  */
1329 static int azx_free(struct azx *chip)
1330 {
1331         struct pci_dev *pci = chip->pci;
1332         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1333         struct hdac_bus *bus = azx_bus(chip);
1334
1335         if (azx_has_pm_runtime(chip) && chip->running)
1336                 pm_runtime_get_noresume(&pci->dev);
1337         chip->running = 0;
1338
1339         azx_del_card_list(chip);
1340
1341         hda->init_failed = 1; /* to be sure */
1342         complete_all(&hda->probe_wait);
1343
1344         if (use_vga_switcheroo(hda)) {
1345                 if (chip->disabled && hda->probe_continued)
1346                         snd_hda_unlock_devices(&chip->bus);
1347                 if (hda->vga_switcheroo_registered)
1348                         vga_switcheroo_unregister_client(chip->pci);
1349         }
1350
1351         if (bus->chip_init) {
1352                 azx_clear_irq_pending(chip);
1353                 azx_stop_all_streams(chip);
1354                 azx_stop_chip(chip);
1355         }
1356
1357         if (bus->irq >= 0)
1358                 free_irq(bus->irq, (void*)chip);
1359         if (chip->msi)
1360                 pci_disable_msi(chip->pci);
1361         iounmap(bus->remap_addr);
1362
1363         azx_free_stream_pages(chip);
1364         azx_free_streams(chip);
1365         snd_hdac_bus_exit(bus);
1366
1367         if (chip->region_requested)
1368                 pci_release_regions(chip->pci);
1369
1370         pci_disable_device(chip->pci);
1371 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1372         release_firmware(chip->fw);
1373 #endif
1374         display_power(chip, false);
1375
1376         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1377                 snd_hdac_i915_exit(bus);
1378         kfree(hda);
1379
1380         return 0;
1381 }
1382
1383 static int azx_dev_disconnect(struct snd_device *device)
1384 {
1385         struct azx *chip = device->device_data;
1386
1387         chip->bus.shutdown = 1;
1388         return 0;
1389 }
1390
1391 static int azx_dev_free(struct snd_device *device)
1392 {
1393         return azx_free(device->device_data);
1394 }
1395
1396 #ifdef SUPPORT_VGA_SWITCHEROO
1397 /*
1398  * Check of disabled HDMI controller by vga_switcheroo
1399  */
1400 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1401 {
1402         struct pci_dev *p;
1403
1404         /* check only discrete GPU */
1405         switch (pci->vendor) {
1406         case PCI_VENDOR_ID_ATI:
1407         case PCI_VENDOR_ID_AMD:
1408         case PCI_VENDOR_ID_NVIDIA:
1409                 if (pci->devfn == 1) {
1410                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1411                                                         pci->bus->number, 0);
1412                         if (p) {
1413                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1414                                         return p;
1415                                 pci_dev_put(p);
1416                         }
1417                 }
1418                 break;
1419         }
1420         return NULL;
1421 }
1422
1423 static bool check_hdmi_disabled(struct pci_dev *pci)
1424 {
1425         bool vga_inactive = false;
1426         struct pci_dev *p = get_bound_vga(pci);
1427
1428         if (p) {
1429                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1430                         vga_inactive = true;
1431                 pci_dev_put(p);
1432         }
1433         return vga_inactive;
1434 }
1435 #endif /* SUPPORT_VGA_SWITCHEROO */
1436
1437 /*
1438  * white/black-listing for position_fix
1439  */
1440 static struct snd_pci_quirk position_fix_list[] = {
1441         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1442         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1443         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1444         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1445         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1446         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1447         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1448         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1449         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1450         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1451         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1452         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1453         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1454         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1455         {}
1456 };
1457
1458 static int check_position_fix(struct azx *chip, int fix)
1459 {
1460         const struct snd_pci_quirk *q;
1461
1462         switch (fix) {
1463         case POS_FIX_AUTO:
1464         case POS_FIX_LPIB:
1465         case POS_FIX_POSBUF:
1466         case POS_FIX_VIACOMBO:
1467         case POS_FIX_COMBO:
1468         case POS_FIX_SKL:
1469         case POS_FIX_FIFO:
1470                 return fix;
1471         }
1472
1473         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1474         if (q) {
1475                 dev_info(chip->card->dev,
1476                          "position_fix set to %d for device %04x:%04x\n",
1477                          q->value, q->subvendor, q->subdevice);
1478                 return q->value;
1479         }
1480
1481         /* Check VIA/ATI HD Audio Controller exist */
1482         if (chip->driver_type == AZX_DRIVER_VIA) {
1483                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1484                 return POS_FIX_VIACOMBO;
1485         }
1486         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1487                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1488                 return POS_FIX_FIFO;
1489         }
1490         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1491                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1492                 return POS_FIX_LPIB;
1493         }
1494         if (chip->driver_type == AZX_DRIVER_SKL) {
1495                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1496                 return POS_FIX_SKL;
1497         }
1498         return POS_FIX_AUTO;
1499 }
1500
1501 static void assign_position_fix(struct azx *chip, int fix)
1502 {
1503         static azx_get_pos_callback_t callbacks[] = {
1504                 [POS_FIX_AUTO] = NULL,
1505                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1506                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1507                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1508                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1509                 [POS_FIX_SKL] = azx_get_pos_skl,
1510                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1511         };
1512
1513         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1514
1515         /* combo mode uses LPIB only for playback */
1516         if (fix == POS_FIX_COMBO)
1517                 chip->get_position[1] = NULL;
1518
1519         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1520             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1521                 chip->get_delay[0] = chip->get_delay[1] =
1522                         azx_get_delay_from_lpib;
1523         }
1524
1525         if (fix == POS_FIX_FIFO)
1526                 chip->get_delay[0] = chip->get_delay[1] =
1527                         azx_get_delay_from_fifo;
1528 }
1529
1530 /*
1531  * black-lists for probe_mask
1532  */
1533 static struct snd_pci_quirk probe_mask_list[] = {
1534         /* Thinkpad often breaks the controller communication when accessing
1535          * to the non-working (or non-existing) modem codec slot.
1536          */
1537         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1538         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1539         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1540         /* broken BIOS */
1541         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1542         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1543         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1544         /* forced codec slots */
1545         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1546         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1547         /* WinFast VP200 H (Teradici) user reported broken communication */
1548         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1549         {}
1550 };
1551
1552 #define AZX_FORCE_CODEC_MASK    0x100
1553
1554 static void check_probe_mask(struct azx *chip, int dev)
1555 {
1556         const struct snd_pci_quirk *q;
1557
1558         chip->codec_probe_mask = probe_mask[dev];
1559         if (chip->codec_probe_mask == -1) {
1560                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1561                 if (q) {
1562                         dev_info(chip->card->dev,
1563                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1564                                  q->value, q->subvendor, q->subdevice);
1565                         chip->codec_probe_mask = q->value;
1566                 }
1567         }
1568
1569         /* check forced option */
1570         if (chip->codec_probe_mask != -1 &&
1571             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1572                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1573                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1574                          (int)azx_bus(chip)->codec_mask);
1575         }
1576 }
1577
1578 /*
1579  * white/black-list for enable_msi
1580  */
1581 static struct snd_pci_quirk msi_black_list[] = {
1582         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1583         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1584         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1585         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1586         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1587         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1588         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1589         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1590         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1591         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1592         {}
1593 };
1594
1595 static void check_msi(struct azx *chip)
1596 {
1597         const struct snd_pci_quirk *q;
1598
1599         if (enable_msi >= 0) {
1600                 chip->msi = !!enable_msi;
1601                 return;
1602         }
1603         chip->msi = 1;  /* enable MSI as default */
1604         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1605         if (q) {
1606                 dev_info(chip->card->dev,
1607                          "msi for device %04x:%04x set to %d\n",
1608                          q->subvendor, q->subdevice, q->value);
1609                 chip->msi = q->value;
1610                 return;
1611         }
1612
1613         /* NVidia chipsets seem to cause troubles with MSI */
1614         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1615                 dev_info(chip->card->dev, "Disabling MSI\n");
1616                 chip->msi = 0;
1617         }
1618 }
1619
1620 /* check the snoop mode availability */
1621 static void azx_check_snoop_available(struct azx *chip)
1622 {
1623         int snoop = hda_snoop;
1624
1625         if (snoop >= 0) {
1626                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1627                          snoop ? "snoop" : "non-snoop");
1628                 chip->snoop = snoop;
1629                 chip->uc_buffer = !snoop;
1630                 return;
1631         }
1632
1633         snoop = true;
1634         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1635             chip->driver_type == AZX_DRIVER_VIA) {
1636                 /* force to non-snoop mode for a new VIA controller
1637                  * when BIOS is set
1638                  */
1639                 u8 val;
1640                 pci_read_config_byte(chip->pci, 0x42, &val);
1641                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1642                                       chip->pci->revision == 0x20))
1643                         snoop = false;
1644         }
1645
1646         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1647                 snoop = false;
1648
1649         chip->snoop = snoop;
1650         if (!snoop) {
1651                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1652                 /* C-Media requires non-cached pages only for CORB/RIRB */
1653                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1654                         chip->uc_buffer = true;
1655         }
1656 }
1657
1658 static void azx_probe_work(struct work_struct *work)
1659 {
1660         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1661         azx_probe_continue(&hda->chip);
1662 }
1663
1664 static int default_bdl_pos_adj(struct azx *chip)
1665 {
1666         /* some exceptions: Atoms seem problematic with value 1 */
1667         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1668                 switch (chip->pci->device) {
1669                 case 0x0f04: /* Baytrail */
1670                 case 0x2284: /* Braswell */
1671                         return 32;
1672                 }
1673         }
1674
1675         switch (chip->driver_type) {
1676         case AZX_DRIVER_ICH:
1677         case AZX_DRIVER_PCH:
1678                 return 1;
1679         default:
1680                 return 32;
1681         }
1682 }
1683
1684 /*
1685  * constructor
1686  */
1687 static const struct hdac_io_ops pci_hda_io_ops;
1688 static const struct hda_controller_ops pci_hda_ops;
1689
1690 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1691                       int dev, unsigned int driver_caps,
1692                       struct azx **rchip)
1693 {
1694         static struct snd_device_ops ops = {
1695                 .dev_disconnect = azx_dev_disconnect,
1696                 .dev_free = azx_dev_free,
1697         };
1698         struct hda_intel *hda;
1699         struct azx *chip;
1700         int err;
1701
1702         *rchip = NULL;
1703
1704         err = pci_enable_device(pci);
1705         if (err < 0)
1706                 return err;
1707
1708         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1709         if (!hda) {
1710                 pci_disable_device(pci);
1711                 return -ENOMEM;
1712         }
1713
1714         chip = &hda->chip;
1715         mutex_init(&chip->open_mutex);
1716         chip->card = card;
1717         chip->pci = pci;
1718         chip->ops = &pci_hda_ops;
1719         chip->driver_caps = driver_caps;
1720         chip->driver_type = driver_caps & 0xff;
1721         check_msi(chip);
1722         chip->dev_index = dev;
1723         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1724                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1725         INIT_LIST_HEAD(&chip->pcm_list);
1726         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1727         INIT_LIST_HEAD(&hda->list);
1728         init_vga_switcheroo(chip);
1729         init_completion(&hda->probe_wait);
1730
1731         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1732
1733         check_probe_mask(chip, dev);
1734
1735         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1736                 chip->fallback_to_single_cmd = 1;
1737         else /* explicitly set to single_cmd or not */
1738                 chip->single_cmd = single_cmd;
1739
1740         azx_check_snoop_available(chip);
1741
1742         if (bdl_pos_adj[dev] < 0)
1743                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1744         else
1745                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1746
1747         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1748         if (err < 0) {
1749                 kfree(hda);
1750                 pci_disable_device(pci);
1751                 return err;
1752         }
1753
1754         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1755         if (IS_CFL(pci) || IS_CNL(pci))
1756                 azx_bus(chip)->polling_mode = 1;
1757
1758         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1759                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1760                 chip->bus.needs_damn_long_delay = 1;
1761         }
1762
1763         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1764         if (err < 0) {
1765                 dev_err(card->dev, "Error creating device [card]!\n");
1766                 azx_free(chip);
1767                 return err;
1768         }
1769
1770         /* continue probing in work context as may trigger request module */
1771         INIT_WORK(&hda->probe_work, azx_probe_work);
1772
1773         *rchip = chip;
1774
1775         return 0;
1776 }
1777
1778 static int azx_first_init(struct azx *chip)
1779 {
1780         int dev = chip->dev_index;
1781         struct pci_dev *pci = chip->pci;
1782         struct snd_card *card = chip->card;
1783         struct hdac_bus *bus = azx_bus(chip);
1784         int err;
1785         unsigned short gcap;
1786         unsigned int dma_bits = 64;
1787
1788 #if BITS_PER_LONG != 64
1789         /* Fix up base address on ULI M5461 */
1790         if (chip->driver_type == AZX_DRIVER_ULI) {
1791                 u16 tmp3;
1792                 pci_read_config_word(pci, 0x40, &tmp3);
1793                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1794                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1795         }
1796 #endif
1797
1798         err = pci_request_regions(pci, "ICH HD audio");
1799         if (err < 0)
1800                 return err;
1801         chip->region_requested = 1;
1802
1803         bus->addr = pci_resource_start(pci, 0);
1804         bus->remap_addr = pci_ioremap_bar(pci, 0);
1805         if (bus->remap_addr == NULL) {
1806                 dev_err(card->dev, "ioremap error\n");
1807                 return -ENXIO;
1808         }
1809
1810         if (chip->driver_type == AZX_DRIVER_SKL)
1811                 snd_hdac_bus_parse_capabilities(bus);
1812
1813         /*
1814          * Some Intel CPUs has always running timer (ART) feature and
1815          * controller may have Global time sync reporting capability, so
1816          * check both of these before declaring synchronized time reporting
1817          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1818          */
1819         chip->gts_present = false;
1820
1821 #ifdef CONFIG_X86
1822         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1823                 chip->gts_present = true;
1824 #endif
1825
1826         if (chip->msi) {
1827                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1828                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1829                         pci->no_64bit_msi = true;
1830                 }
1831                 if (pci_enable_msi(pci) < 0)
1832                         chip->msi = 0;
1833         }
1834
1835         pci_set_master(pci);
1836         synchronize_irq(bus->irq);
1837
1838         gcap = azx_readw(chip, GCAP);
1839         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1840
1841         /* AMD devices support 40 or 48bit DMA, take the safe one */
1842         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1843                 dma_bits = 40;
1844
1845         /* disable SB600 64bit support for safety */
1846         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1847                 struct pci_dev *p_smbus;
1848                 dma_bits = 40;
1849                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1850                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1851                                          NULL);
1852                 if (p_smbus) {
1853                         if (p_smbus->revision < 0x30)
1854                                 gcap &= ~AZX_GCAP_64OK;
1855                         pci_dev_put(p_smbus);
1856                 }
1857         }
1858
1859         /* NVidia hardware normally only supports up to 40 bits of DMA */
1860         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1861                 dma_bits = 40;
1862
1863         /* disable 64bit DMA address on some devices */
1864         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1865                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1866                 gcap &= ~AZX_GCAP_64OK;
1867         }
1868
1869         /* disable buffer size rounding to 128-byte multiples if supported */
1870         if (align_buffer_size >= 0)
1871                 chip->align_buffer_size = !!align_buffer_size;
1872         else {
1873                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1874                         chip->align_buffer_size = 0;
1875                 else
1876                         chip->align_buffer_size = 1;
1877         }
1878
1879         /* allow 64bit DMA address if supported by H/W */
1880         if (!(gcap & AZX_GCAP_64OK))
1881                 dma_bits = 32;
1882         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1883                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1884         } else {
1885                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1886                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1887         }
1888
1889         /* read number of streams from GCAP register instead of using
1890          * hardcoded value
1891          */
1892         chip->capture_streams = (gcap >> 8) & 0x0f;
1893         chip->playback_streams = (gcap >> 12) & 0x0f;
1894         if (!chip->playback_streams && !chip->capture_streams) {
1895                 /* gcap didn't give any info, switching to old method */
1896
1897                 switch (chip->driver_type) {
1898                 case AZX_DRIVER_ULI:
1899                         chip->playback_streams = ULI_NUM_PLAYBACK;
1900                         chip->capture_streams = ULI_NUM_CAPTURE;
1901                         break;
1902                 case AZX_DRIVER_ATIHDMI:
1903                 case AZX_DRIVER_ATIHDMI_NS:
1904                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1905                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1906                         break;
1907                 case AZX_DRIVER_GENERIC:
1908                 default:
1909                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1910                         chip->capture_streams = ICH6_NUM_CAPTURE;
1911                         break;
1912                 }
1913         }
1914         chip->capture_index_offset = 0;
1915         chip->playback_index_offset = chip->capture_streams;
1916         chip->num_streams = chip->playback_streams + chip->capture_streams;
1917
1918         /* sanity check for the SDxCTL.STRM field overflow */
1919         if (chip->num_streams > 15 &&
1920             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1921                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1922                          "forcing separate stream tags", chip->num_streams);
1923                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1924         }
1925
1926         /* initialize streams */
1927         err = azx_init_streams(chip);
1928         if (err < 0)
1929                 return err;
1930
1931         err = azx_alloc_stream_pages(chip);
1932         if (err < 0)
1933                 return err;
1934
1935         /* initialize chip */
1936         azx_init_pci(chip);
1937
1938         snd_hdac_i915_set_bclk(bus);
1939
1940         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1941
1942         /* codec detection */
1943         if (!azx_bus(chip)->codec_mask) {
1944                 dev_err(card->dev, "no codecs found!\n");
1945                 return -ENODEV;
1946         }
1947
1948         if (azx_acquire_irq(chip, 0) < 0)
1949                 return -EBUSY;
1950
1951         strcpy(card->driver, "HDA-Intel");
1952         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1953                 sizeof(card->shortname));
1954         snprintf(card->longname, sizeof(card->longname),
1955                  "%s at 0x%lx irq %i",
1956                  card->shortname, bus->addr, bus->irq);
1957
1958         return 0;
1959 }
1960
1961 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1962 /* callback from request_firmware_nowait() */
1963 static void azx_firmware_cb(const struct firmware *fw, void *context)
1964 {
1965         struct snd_card *card = context;
1966         struct azx *chip = card->private_data;
1967         struct pci_dev *pci = chip->pci;
1968
1969         if (!fw) {
1970                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1971                 goto error;
1972         }
1973
1974         chip->fw = fw;
1975         if (!chip->disabled) {
1976                 /* continue probing */
1977                 if (azx_probe_continue(chip))
1978                         goto error;
1979         }
1980         return; /* OK */
1981
1982  error:
1983         snd_card_free(card);
1984         pci_set_drvdata(pci, NULL);
1985 }
1986 #endif
1987
1988 /*
1989  * HDA controller ops.
1990  */
1991
1992 /* PCI register access. */
1993 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1994 {
1995         writel(value, addr);
1996 }
1997
1998 static u32 pci_azx_readl(u32 __iomem *addr)
1999 {
2000         return readl(addr);
2001 }
2002
2003 static void pci_azx_writew(u16 value, u16 __iomem *addr)
2004 {
2005         writew(value, addr);
2006 }
2007
2008 static u16 pci_azx_readw(u16 __iomem *addr)
2009 {
2010         return readw(addr);
2011 }
2012
2013 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2014 {
2015         writeb(value, addr);
2016 }
2017
2018 static u8 pci_azx_readb(u8 __iomem *addr)
2019 {
2020         return readb(addr);
2021 }
2022
2023 static int disable_msi_reset_irq(struct azx *chip)
2024 {
2025         struct hdac_bus *bus = azx_bus(chip);
2026         int err;
2027
2028         free_irq(bus->irq, chip);
2029         bus->irq = -1;
2030         pci_disable_msi(chip->pci);
2031         chip->msi = 0;
2032         err = azx_acquire_irq(chip, 1);
2033         if (err < 0)
2034                 return err;
2035
2036         return 0;
2037 }
2038
2039 /* DMA page allocation helpers.  */
2040 static int dma_alloc_pages(struct hdac_bus *bus,
2041                            int type,
2042                            size_t size,
2043                            struct snd_dma_buffer *buf)
2044 {
2045         struct azx *chip = bus_to_azx(bus);
2046
2047         if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
2048                 type = SNDRV_DMA_TYPE_DEV_UC;
2049         return snd_dma_alloc_pages(type, bus->dev, size, buf);
2050 }
2051
2052 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2053 {
2054         snd_dma_free_pages(buf);
2055 }
2056
2057 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2058                              struct vm_area_struct *area)
2059 {
2060 #ifdef CONFIG_X86
2061         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2062         struct azx *chip = apcm->chip;
2063         if (chip->uc_buffer)
2064                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2065 #endif
2066 }
2067
2068 static const struct hdac_io_ops pci_hda_io_ops = {
2069         .reg_writel = pci_azx_writel,
2070         .reg_readl = pci_azx_readl,
2071         .reg_writew = pci_azx_writew,
2072         .reg_readw = pci_azx_readw,
2073         .reg_writeb = pci_azx_writeb,
2074         .reg_readb = pci_azx_readb,
2075         .dma_alloc_pages = dma_alloc_pages,
2076         .dma_free_pages = dma_free_pages,
2077 };
2078
2079 static const struct hda_controller_ops pci_hda_ops = {
2080         .disable_msi_reset_irq = disable_msi_reset_irq,
2081         .pcm_mmap_prepare = pcm_mmap_prepare,
2082         .position_check = azx_position_check,
2083 };
2084
2085 static int azx_probe(struct pci_dev *pci,
2086                      const struct pci_device_id *pci_id)
2087 {
2088         static int dev;
2089         struct snd_card *card;
2090         struct hda_intel *hda;
2091         struct azx *chip;
2092         bool schedule_probe;
2093         int err;
2094
2095         if (dev >= SNDRV_CARDS)
2096                 return -ENODEV;
2097         if (!enable[dev]) {
2098                 dev++;
2099                 return -ENOENT;
2100         }
2101
2102         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2103                            0, &card);
2104         if (err < 0) {
2105                 dev_err(&pci->dev, "Error creating card!\n");
2106                 return err;
2107         }
2108
2109         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2110         if (err < 0)
2111                 goto out_free;
2112         card->private_data = chip;
2113         hda = container_of(chip, struct hda_intel, chip);
2114
2115         pci_set_drvdata(pci, card);
2116
2117         err = register_vga_switcheroo(chip);
2118         if (err < 0) {
2119                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2120                 goto out_free;
2121         }
2122
2123         if (check_hdmi_disabled(pci)) {
2124                 dev_info(card->dev, "VGA controller is disabled\n");
2125                 dev_info(card->dev, "Delaying initialization\n");
2126                 chip->disabled = true;
2127         }
2128
2129         schedule_probe = !chip->disabled;
2130
2131 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2132         if (patch[dev] && *patch[dev]) {
2133                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2134                          patch[dev]);
2135                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2136                                               &pci->dev, GFP_KERNEL, card,
2137                                               azx_firmware_cb);
2138                 if (err < 0)
2139                         goto out_free;
2140                 schedule_probe = false; /* continued in azx_firmware_cb() */
2141         }
2142 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2143
2144 #ifndef CONFIG_SND_HDA_I915
2145         if (CONTROLLER_IN_GPU(pci))
2146                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2147 #endif
2148
2149         if (schedule_probe)
2150                 schedule_work(&hda->probe_work);
2151
2152         dev++;
2153         if (chip->disabled)
2154                 complete_all(&hda->probe_wait);
2155         return 0;
2156
2157 out_free:
2158         snd_card_free(card);
2159         return err;
2160 }
2161
2162 #ifdef CONFIG_PM
2163 /* On some boards setting power_save to a non 0 value leads to clicking /
2164  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2165  * figure out how to avoid these sounds, but that is not always feasible.
2166  * So we keep a list of devices where we disable powersaving as its known
2167  * to causes problems on these devices.
2168  */
2169 static struct snd_pci_quirk power_save_blacklist[] = {
2170         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2171         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2172         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2173         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2174         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2175         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2176         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2177         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2178         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2179         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2180         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2181         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2182         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2183         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2184         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2185         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2186         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2187         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2188         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2189         /* https://bugs.launchpad.net/bugs/1821663 */
2190         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2191         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2192         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2193         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2194         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2195         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2196         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2197         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2198         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2199         /* https://bugs.launchpad.net/bugs/1821663 */
2200         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2201         {}
2202 };
2203 #endif /* CONFIG_PM */
2204
2205 static void set_default_power_save(struct azx *chip)
2206 {
2207         int val = power_save;
2208
2209 #ifdef CONFIG_PM
2210         if (pm_blacklist) {
2211                 const struct snd_pci_quirk *q;
2212
2213                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2214                 if (q && val) {
2215                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2216                                  q->subvendor, q->subdevice);
2217                         val = 0;
2218                 }
2219         }
2220 #endif /* CONFIG_PM */
2221         snd_hda_set_power_save(&chip->bus, val * 1000);
2222 }
2223
2224 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2225 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2226         [AZX_DRIVER_NVIDIA] = 8,
2227         [AZX_DRIVER_TERA] = 1,
2228 };
2229
2230 static int azx_probe_continue(struct azx *chip)
2231 {
2232         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2233         struct hdac_bus *bus = azx_bus(chip);
2234         struct pci_dev *pci = chip->pci;
2235         int dev = chip->dev_index;
2236         int err;
2237
2238         to_hda_bus(bus)->bus_probing = 1;
2239         hda->probe_continued = 1;
2240
2241         /* bind with i915 if needed */
2242         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2243                 err = snd_hdac_i915_init(bus);
2244                 if (err < 0) {
2245                         /* if the controller is bound only with HDMI/DP
2246                          * (for HSW and BDW), we need to abort the probe;
2247                          * for other chips, still continue probing as other
2248                          * codecs can be on the same link.
2249                          */
2250                         if (CONTROLLER_IN_GPU(pci)) {
2251                                 dev_err(chip->card->dev,
2252                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2253                                 goto out_free;
2254                         } else {
2255                                 /* don't bother any longer */
2256                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2257                         }
2258                 }
2259
2260                 /* HSW/BDW controllers need this power */
2261                 if (CONTROLLER_IN_GPU(pci))
2262                         hda->need_i915_power = 1;
2263         }
2264
2265         /* Request display power well for the HDA controller or codec. For
2266          * Haswell/Broadwell, both the display HDA controller and codec need
2267          * this power. For other platforms, like Baytrail/Braswell, only the
2268          * display codec needs the power and it can be released after probe.
2269          */
2270         display_power(chip, true);
2271
2272         err = azx_first_init(chip);
2273         if (err < 0)
2274                 goto out_free;
2275
2276 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2277         chip->beep_mode = beep_mode[dev];
2278 #endif
2279
2280         /* create codec instances */
2281         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2282         if (err < 0)
2283                 goto out_free;
2284
2285 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2286         if (chip->fw) {
2287                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2288                                          chip->fw->data);
2289                 if (err < 0)
2290                         goto out_free;
2291 #ifndef CONFIG_PM
2292                 release_firmware(chip->fw); /* no longer needed */
2293                 chip->fw = NULL;
2294 #endif
2295         }
2296 #endif
2297         if ((probe_only[dev] & 1) == 0) {
2298                 err = azx_codec_configure(chip);
2299                 if (err < 0)
2300                         goto out_free;
2301         }
2302
2303         err = snd_card_register(chip->card);
2304         if (err < 0)
2305                 goto out_free;
2306
2307         setup_vga_switcheroo_runtime_pm(chip);
2308
2309         chip->running = 1;
2310         azx_add_card_list(chip);
2311
2312         set_default_power_save(chip);
2313
2314         if (azx_has_pm_runtime(chip))
2315                 pm_runtime_put_autosuspend(&pci->dev);
2316
2317 out_free:
2318         if (err < 0 || !hda->need_i915_power)
2319                 display_power(chip, false);
2320         if (err < 0)
2321                 hda->init_failed = 1;
2322         complete_all(&hda->probe_wait);
2323         to_hda_bus(bus)->bus_probing = 0;
2324         return err;
2325 }
2326
2327 static void azx_remove(struct pci_dev *pci)
2328 {
2329         struct snd_card *card = pci_get_drvdata(pci);
2330         struct azx *chip;
2331         struct hda_intel *hda;
2332
2333         if (card) {
2334                 /* cancel the pending probing work */
2335                 chip = card->private_data;
2336                 hda = container_of(chip, struct hda_intel, chip);
2337                 /* FIXME: below is an ugly workaround.
2338                  * Both device_release_driver() and driver_probe_device()
2339                  * take *both* the device's and its parent's lock before
2340                  * calling the remove() and probe() callbacks.  The codec
2341                  * probe takes the locks of both the codec itself and its
2342                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2343                  * the PCI controller is unbound, it takes its lock, too
2344                  * ==> ouch, a deadlock!
2345                  * As a workaround, we unlock temporarily here the controller
2346                  * device during cancel_work_sync() call.
2347                  */
2348                 device_unlock(&pci->dev);
2349                 cancel_work_sync(&hda->probe_work);
2350                 device_lock(&pci->dev);
2351
2352                 snd_card_free(card);
2353         }
2354 }
2355
2356 static void azx_shutdown(struct pci_dev *pci)
2357 {
2358         struct snd_card *card = pci_get_drvdata(pci);
2359         struct azx *chip;
2360
2361         if (!card)
2362                 return;
2363         chip = card->private_data;
2364         if (chip && chip->running)
2365                 azx_stop_chip(chip);
2366 }
2367
2368 /* PCI IDs */
2369 static const struct pci_device_id azx_ids[] = {
2370         /* CPT */
2371         { PCI_DEVICE(0x8086, 0x1c20),
2372           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2373         /* PBG */
2374         { PCI_DEVICE(0x8086, 0x1d20),
2375           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2376         /* Panther Point */
2377         { PCI_DEVICE(0x8086, 0x1e20),
2378           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2379         /* Lynx Point */
2380         { PCI_DEVICE(0x8086, 0x8c20),
2381           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2382         /* 9 Series */
2383         { PCI_DEVICE(0x8086, 0x8ca0),
2384           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2385         /* Wellsburg */
2386         { PCI_DEVICE(0x8086, 0x8d20),
2387           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2388         { PCI_DEVICE(0x8086, 0x8d21),
2389           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2390         /* Lewisburg */
2391         { PCI_DEVICE(0x8086, 0xa1f0),
2392           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2393         { PCI_DEVICE(0x8086, 0xa270),
2394           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2395         /* Lynx Point-LP */
2396         { PCI_DEVICE(0x8086, 0x9c20),
2397           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2398         /* Lynx Point-LP */
2399         { PCI_DEVICE(0x8086, 0x9c21),
2400           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2401         /* Wildcat Point-LP */
2402         { PCI_DEVICE(0x8086, 0x9ca0),
2403           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2404         /* Sunrise Point */
2405         { PCI_DEVICE(0x8086, 0xa170),
2406           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2407         /* Sunrise Point-LP */
2408         { PCI_DEVICE(0x8086, 0x9d70),
2409           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2410         /* Kabylake */
2411         { PCI_DEVICE(0x8086, 0xa171),
2412           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2413         /* Kabylake-LP */
2414         { PCI_DEVICE(0x8086, 0x9d71),
2415           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2416         /* Kabylake-H */
2417         { PCI_DEVICE(0x8086, 0xa2f0),
2418           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2419         /* Coffelake */
2420         { PCI_DEVICE(0x8086, 0xa348),
2421           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2422         /* Cannonlake */
2423         { PCI_DEVICE(0x8086, 0x9dc8),
2424           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2425         /* CometLake-LP */
2426         { PCI_DEVICE(0x8086, 0x02C8),
2427           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2428         /* CometLake-H */
2429         { PCI_DEVICE(0x8086, 0x06C8),
2430           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2431         /* Icelake */
2432         { PCI_DEVICE(0x8086, 0x34c8),
2433           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2434         /* Elkhart Lake */
2435         { PCI_DEVICE(0x8086, 0x4b55),
2436           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2437         /* Broxton-P(Apollolake) */
2438         { PCI_DEVICE(0x8086, 0x5a98),
2439           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2440         /* Broxton-T */
2441         { PCI_DEVICE(0x8086, 0x1a98),
2442           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2443         /* Gemini-Lake */
2444         { PCI_DEVICE(0x8086, 0x3198),
2445           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2446         /* Haswell */
2447         { PCI_DEVICE(0x8086, 0x0a0c),
2448           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2449         { PCI_DEVICE(0x8086, 0x0c0c),
2450           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2451         { PCI_DEVICE(0x8086, 0x0d0c),
2452           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2453         /* Broadwell */
2454         { PCI_DEVICE(0x8086, 0x160c),
2455           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2456         /* 5 Series/3400 */
2457         { PCI_DEVICE(0x8086, 0x3b56),
2458           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2459         /* Poulsbo */
2460         { PCI_DEVICE(0x8086, 0x811b),
2461           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2462         /* Oaktrail */
2463         { PCI_DEVICE(0x8086, 0x080a),
2464           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2465         /* BayTrail */
2466         { PCI_DEVICE(0x8086, 0x0f04),
2467           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2468         /* Braswell */
2469         { PCI_DEVICE(0x8086, 0x2284),
2470           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2471         /* ICH6 */
2472         { PCI_DEVICE(0x8086, 0x2668),
2473           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2474         /* ICH7 */
2475         { PCI_DEVICE(0x8086, 0x27d8),
2476           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2477         /* ESB2 */
2478         { PCI_DEVICE(0x8086, 0x269a),
2479           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2480         /* ICH8 */
2481         { PCI_DEVICE(0x8086, 0x284b),
2482           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2483         /* ICH9 */
2484         { PCI_DEVICE(0x8086, 0x293e),
2485           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2486         /* ICH9 */
2487         { PCI_DEVICE(0x8086, 0x293f),
2488           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2489         /* ICH10 */
2490         { PCI_DEVICE(0x8086, 0x3a3e),
2491           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2492         /* ICH10 */
2493         { PCI_DEVICE(0x8086, 0x3a6e),
2494           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2495         /* Generic Intel */
2496         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2497           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2498           .class_mask = 0xffffff,
2499           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2500         /* ATI SB 450/600/700/800/900 */
2501         { PCI_DEVICE(0x1002, 0x437b),
2502           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2503         { PCI_DEVICE(0x1002, 0x4383),
2504           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2505         /* AMD Hudson */
2506         { PCI_DEVICE(0x1022, 0x780d),
2507           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2508         /* AMD, X370 & co */
2509         { PCI_DEVICE(0x1022, 0x1457),
2510           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2511         /* AMD, X570 & co */
2512         { PCI_DEVICE(0x1022, 0x1487),
2513           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2514         /* AMD Stoney */
2515         { PCI_DEVICE(0x1022, 0x157a),
2516           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2517                          AZX_DCAPS_PM_RUNTIME },
2518         /* AMD Raven */
2519         { PCI_DEVICE(0x1022, 0x15e3),
2520           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2521                          AZX_DCAPS_PM_RUNTIME },
2522         /* ATI HDMI */
2523         { PCI_DEVICE(0x1002, 0x0002),
2524           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2525         { PCI_DEVICE(0x1002, 0x1308),
2526           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2527         { PCI_DEVICE(0x1002, 0x157a),
2528           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2529         { PCI_DEVICE(0x1002, 0x15b3),
2530           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2531         { PCI_DEVICE(0x1002, 0x793b),
2532           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2533         { PCI_DEVICE(0x1002, 0x7919),
2534           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2535         { PCI_DEVICE(0x1002, 0x960f),
2536           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2537         { PCI_DEVICE(0x1002, 0x970f),
2538           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2539         { PCI_DEVICE(0x1002, 0x9840),
2540           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2541         { PCI_DEVICE(0x1002, 0xaa00),
2542           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2543         { PCI_DEVICE(0x1002, 0xaa08),
2544           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2545         { PCI_DEVICE(0x1002, 0xaa10),
2546           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2547         { PCI_DEVICE(0x1002, 0xaa18),
2548           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2549         { PCI_DEVICE(0x1002, 0xaa20),
2550           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2551         { PCI_DEVICE(0x1002, 0xaa28),
2552           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2553         { PCI_DEVICE(0x1002, 0xaa30),
2554           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2555         { PCI_DEVICE(0x1002, 0xaa38),
2556           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2557         { PCI_DEVICE(0x1002, 0xaa40),
2558           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2559         { PCI_DEVICE(0x1002, 0xaa48),
2560           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2561         { PCI_DEVICE(0x1002, 0xaa50),
2562           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2563         { PCI_DEVICE(0x1002, 0xaa58),
2564           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2565         { PCI_DEVICE(0x1002, 0xaa60),
2566           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2567         { PCI_DEVICE(0x1002, 0xaa68),
2568           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2569         { PCI_DEVICE(0x1002, 0xaa80),
2570           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2571         { PCI_DEVICE(0x1002, 0xaa88),
2572           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2573         { PCI_DEVICE(0x1002, 0xaa90),
2574           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2575         { PCI_DEVICE(0x1002, 0xaa98),
2576           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2577         { PCI_DEVICE(0x1002, 0x9902),
2578           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2579         { PCI_DEVICE(0x1002, 0xaaa0),
2580           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2581         { PCI_DEVICE(0x1002, 0xaaa8),
2582           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2583         { PCI_DEVICE(0x1002, 0xaab0),
2584           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2585         { PCI_DEVICE(0x1002, 0xaac0),
2586           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2587         { PCI_DEVICE(0x1002, 0xaac8),
2588           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2589         { PCI_DEVICE(0x1002, 0xaad8),
2590           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2591         { PCI_DEVICE(0x1002, 0xaae8),
2592           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2593         { PCI_DEVICE(0x1002, 0xaae0),
2594           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2595         { PCI_DEVICE(0x1002, 0xaaf0),
2596           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2597         /* VIA VT8251/VT8237A */
2598         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2599         /* VIA GFX VT7122/VX900 */
2600         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2601         /* VIA GFX VT6122/VX11 */
2602         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2603         /* SIS966 */
2604         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2605         /* ULI M5461 */
2606         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2607         /* NVIDIA MCP */
2608         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2609           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2610           .class_mask = 0xffffff,
2611           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2612         /* Teradici */
2613         { PCI_DEVICE(0x6549, 0x1200),
2614           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2615         { PCI_DEVICE(0x6549, 0x2200),
2616           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2617         /* Creative X-Fi (CA0110-IBG) */
2618         /* CTHDA chips */
2619         { PCI_DEVICE(0x1102, 0x0010),
2620           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2621         { PCI_DEVICE(0x1102, 0x0012),
2622           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2623 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2624         /* the following entry conflicts with snd-ctxfi driver,
2625          * as ctxfi driver mutates from HD-audio to native mode with
2626          * a special command sequence.
2627          */
2628         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2629           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2630           .class_mask = 0xffffff,
2631           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2632           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2633 #else
2634         /* this entry seems still valid -- i.e. without emu20kx chip */
2635         { PCI_DEVICE(0x1102, 0x0009),
2636           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2637           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2638 #endif
2639         /* CM8888 */
2640         { PCI_DEVICE(0x13f6, 0x5011),
2641           .driver_data = AZX_DRIVER_CMEDIA |
2642           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2643         /* Vortex86MX */
2644         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2645         /* VMware HDAudio */
2646         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2647         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2648         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2649           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2650           .class_mask = 0xffffff,
2651           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2652         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2653           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2654           .class_mask = 0xffffff,
2655           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2656         { 0, }
2657 };
2658 MODULE_DEVICE_TABLE(pci, azx_ids);
2659
2660 /* pci_driver definition */
2661 static struct pci_driver azx_driver = {
2662         .name = KBUILD_MODNAME,
2663         .id_table = azx_ids,
2664         .probe = azx_probe,
2665         .remove = azx_remove,
2666         .shutdown = azx_shutdown,
2667         .driver = {
2668                 .pm = AZX_PM_OPS,
2669         },
2670 };
2671
2672 module_pci_driver(azx_driver);