lib/dma-direct.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * DMA operations that map physical memory directly without using an IOMMU or
   4  * flushing caches.
   5  */
   6 #include <linux/export.h>
   7 #include <linux/mm.h>
   8 #include <linux/dma-direct.h>
   9 #include <linux/scatterlist.h>
  10 #include <linux/dma-contiguous.h>
  11 #include <linux/pfn.h>
  12 #include <linux/set_memory.h>
  13
  14 #define DIRECT_MAPPING_ERROR            0
  15
  16 /*
  17  * Most architectures use ZONE_DMA for the first 16 Megabytes, but
  18  * some use it for entirely different regions:
  19  */
  20 #ifndef ARCH_ZONE_DMA_BITS
  21 #define ARCH_ZONE_DMA_BITS 24
  22 #endif
  23
  24 /*
  25  * For AMD SEV all DMA must be to unencrypted addresses.
  26  */
  27 static inline bool force_dma_unencrypted(void)
  28 {
  29         return sev_active();
  30 }
  31
  32 static bool
  33 check_addr(struct device *dev, dma_addr_t dma_addr, size_t size,
  34                 const char *caller)
  35 {
  36         if (unlikely(dev && !dma_capable(dev, dma_addr, size))) {
  37                 if (*dev->dma_mask >= DMA_BIT_MASK(32)) {
  38                         dev_err(dev,
  39                                 "%s: overflow %pad+%zu of device mask %llx\n",
  40                                 caller, &dma_addr, size, *dev->dma_mask);
  41                 }
  42                 return false;
  43         }
  44         return true;
  45 }
  46
  47 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
  48 {
  49         dma_addr_t addr = force_dma_unencrypted() ?
  50                 __phys_to_dma(dev, phys) : phys_to_dma(dev, phys);
  51         return addr + size - 1 <= dev->coherent_dma_mask;
  52 }
  53
  54 void *dma_direct_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
  55                 gfp_t gfp, unsigned long attrs)
  56 {
  57         unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
  58         int page_order = get_order(size);
  59         struct page *page = NULL;
  60         void *ret;
  61
  62         /* we always manually zero the memory once we are done: */
  63         gfp &= ~__GFP_ZERO;
  64
  65         /* GFP_DMA32 and GFP_DMA are no ops without the corresponding zones: */
  66         if (dev->coherent_dma_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
  67                 gfp |= GFP_DMA;
  68         if (dev->coherent_dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
  69                 gfp |= GFP_DMA32;
  70
  71 again:
  72         /* CMA can be used only in the context which permits sleeping */
  73         if (gfpflags_allow_blocking(gfp)) {
  74                 page = dma_alloc_from_contiguous(dev, count, page_order, gfp);
  75                 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
  76                         dma_release_from_contiguous(dev, page, count);
  77                         page = NULL;
  78                 }
  79         }
  80         if (!page)
  81                 page = alloc_pages_node(dev_to_node(dev), gfp, page_order);
  82
  83         if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
  84                 __free_pages(page, page_order);
  85                 page = NULL;
  86
  87                 if (dev->coherent_dma_mask < DMA_BIT_MASK(32) &&
  88                     !(gfp & GFP_DMA)) {
  89                         gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
  90                         goto again;
  91                 }
  92         }
  93
  94         if (!page)
  95                 return NULL;
  96         ret = page_address(page);
  97         if (force_dma_unencrypted()) {
  98                 set_memory_decrypted((unsigned long)ret, 1 << page_order);
  99                 *dma_handle = __phys_to_dma(dev, page_to_phys(page));
 100         } else {
 101                 *dma_handle = phys_to_dma(dev, page_to_phys(page));
 102         }
 103         memset(ret, 0, size);
 104         return ret;
 105 }
 106
 107 /*
 108  * NOTE: this function must never look at the dma_addr argument, because we want
 109  * to be able to use it as a helper for iommu implementations as well.
 110  */
 111 void dma_direct_free(struct device *dev, size_t size, void *cpu_addr,
 112                 dma_addr_t dma_addr, unsigned long attrs)
 113 {
 114         unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
 115         unsigned int page_order = get_order(size);
 116
 117         if (force_dma_unencrypted())
 118                 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
 119         if (!dma_release_from_contiguous(dev, virt_to_page(cpu_addr), count))
 120                 free_pages((unsigned long)cpu_addr, page_order);
 121 }
 122
 123 static dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
 124                 unsigned long offset, size_t size, enum dma_data_direction dir,
 125                 unsigned long attrs)
 126 {
 127         dma_addr_t dma_addr = phys_to_dma(dev, page_to_phys(page)) + offset;
 128
 129         if (!check_addr(dev, dma_addr, size, __func__))
 130                 return DIRECT_MAPPING_ERROR;
 131         return dma_addr;
 132 }
 133
 134 static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
 135                 int nents, enum dma_data_direction dir, unsigned long attrs)
 136 {
 137         int i;
 138         struct scatterlist *sg;
 139
 140         for_each_sg(sgl, sg, nents, i) {
 141                 BUG_ON(!sg_page(sg));
 142
 143                 sg_dma_address(sg) = phys_to_dma(dev, sg_phys(sg));
 144                 if (!check_addr(dev, sg_dma_address(sg), sg->length, __func__))
 145                         return 0;
 146                 sg_dma_len(sg) = sg->length;
 147         }
 148
 149         return nents;
 150 }
 151
 152 int dma_direct_supported(struct device *dev, u64 mask)
 153 {
 154 #ifdef CONFIG_ZONE_DMA
 155         if (mask < DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
 156                 return 0;
 157 #else
 158         /*
 159          * Because 32-bit DMA masks are so common we expect every architecture
 160          * to be able to satisfy them - either by not supporting more physical
 161          * memory, or by providing a ZONE_DMA32.  If neither is the case, the
 162          * architecture needs to use an IOMMU instead of the direct mapping.
 163          */
 164         if (mask < DMA_BIT_MASK(32))
 165                 return 0;
 166 #endif
 167         return 1;
 168 }
 169
 170 static int dma_direct_mapping_error(struct device *dev, dma_addr_t dma_addr)
 171 {
 172         return dma_addr == DIRECT_MAPPING_ERROR;
 173 }
 174
 175 const struct dma_map_ops dma_direct_ops = {
 176         .alloc                  = dma_direct_alloc,
 177         .free                   = dma_direct_free,
 178         .map_page               = dma_direct_map_page,
 179         .map_sg                 = dma_direct_map_sg,
 180         .dma_supported          = dma_direct_supported,
 181         .mapping_error          = dma_direct_mapping_error,
 182         .is_phys                = 1,
 183 };
 184 EXPORT_SYMBOL(dma_direct_ops);