1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Christoph Hellwig.
5 * DMA operations that map physical memory directly without using an IOMMU.
7 #include <linux/memblock.h> /* for max_pfn */
8 #include <linux/export.h>
10 #include <linux/dma-direct.h>
11 #include <linux/scatterlist.h>
12 #include <linux/dma-contiguous.h>
13 #include <linux/dma-noncoherent.h>
14 #include <linux/pfn.h>
15 #include <linux/set_memory.h>
16 #include <linux/swiotlb.h>
19 * Most architectures use ZONE_DMA for the first 16 Megabytes, but
20 * some use it for entirely different regions:
22 #ifndef ARCH_ZONE_DMA_BITS
23 #define ARCH_ZONE_DMA_BITS 24
27 * For AMD SEV all DMA must be to unencrypted addresses.
29 static inline bool force_dma_unencrypted(void)
34 static void report_addr(struct device *dev, dma_addr_t dma_addr, size_t size)
37 dev_err_once(dev, "DMA map on device without dma_mask\n");
38 } else if (*dev->dma_mask >= DMA_BIT_MASK(32) || dev->bus_dma_mask) {
40 "overflow %pad+%zu of DMA mask %llx bus mask %llx\n",
41 &dma_addr, size, *dev->dma_mask, dev->bus_dma_mask);
46 static inline dma_addr_t phys_to_dma_direct(struct device *dev,
49 if (force_dma_unencrypted())
50 return __phys_to_dma(dev, phys);
51 return phys_to_dma(dev, phys);
54 u64 dma_direct_get_required_mask(struct device *dev)
56 u64 max_dma = phys_to_dma_direct(dev, (max_pfn - 1) << PAGE_SHIFT);
58 if (dev->bus_dma_mask && dev->bus_dma_mask < max_dma)
59 max_dma = dev->bus_dma_mask;
61 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
64 static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
67 if (dev->bus_dma_mask && dev->bus_dma_mask < dma_mask)
68 dma_mask = dev->bus_dma_mask;
70 if (force_dma_unencrypted())
71 *phys_mask = __dma_to_phys(dev, dma_mask);
73 *phys_mask = dma_to_phys(dev, dma_mask);
76 * Optimistically try the zone that the physical address mask falls
77 * into first. If that returns memory that isn't actually addressable
78 * we will fallback to the next lower zone and try again.
80 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
83 if (*phys_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
85 if (*phys_mask <= DMA_BIT_MASK(32))
90 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
92 return phys_to_dma_direct(dev, phys) + size - 1 <=
93 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_mask);
96 struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
97 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
99 struct page *page = NULL;
102 if (attrs & DMA_ATTR_NO_WARN)
105 /* we always manually zero the memory once we are done: */
107 gfp |= __dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
110 page = dma_alloc_contiguous(dev, size, gfp);
111 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
112 dma_free_contiguous(dev, page, size);
115 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
116 phys_mask < DMA_BIT_MASK(64) &&
117 !(gfp & (GFP_DMA32 | GFP_DMA))) {
122 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
123 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
131 void *dma_direct_alloc_pages(struct device *dev, size_t size,
132 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
137 page = __dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
141 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) {
142 /* remove any dirty cache lines on the kernel alias */
143 if (!PageHighMem(page))
144 arch_dma_prep_coherent(page, size);
145 /* return the page pointer as the opaque cookie */
149 if (PageHighMem(page)) {
151 * Depending on the cma= arguments and per-arch setup
152 * dma_alloc_contiguous could return highmem pages.
153 * Without remapping there is no way to return them here,
154 * so log an error and fail.
156 dev_info(dev, "Rejecting highmem page from CMA.\n");
157 __dma_direct_free_pages(dev, size, page);
161 ret = page_address(page);
162 if (force_dma_unencrypted()) {
163 set_memory_decrypted((unsigned long)ret, 1 << get_order(size));
164 *dma_handle = __phys_to_dma(dev, page_to_phys(page));
166 *dma_handle = phys_to_dma(dev, page_to_phys(page));
168 memset(ret, 0, size);
170 if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
171 dma_alloc_need_uncached(dev, attrs)) {
172 arch_dma_prep_coherent(page, size);
173 ret = uncached_kernel_address(ret);
179 void __dma_direct_free_pages(struct device *dev, size_t size, struct page *page)
181 dma_free_contiguous(dev, page, size);
184 void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr,
185 dma_addr_t dma_addr, unsigned long attrs)
187 unsigned int page_order = get_order(size);
189 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) {
190 /* cpu_addr is a struct page cookie, not a kernel address */
191 __dma_direct_free_pages(dev, size, cpu_addr);
195 if (force_dma_unencrypted())
196 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
198 if (IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
199 dma_alloc_need_uncached(dev, attrs))
200 cpu_addr = cached_kernel_address(cpu_addr);
201 __dma_direct_free_pages(dev, size, virt_to_page(cpu_addr));
204 void *dma_direct_alloc(struct device *dev, size_t size,
205 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
207 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
208 dma_alloc_need_uncached(dev, attrs))
209 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
210 return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
213 void dma_direct_free(struct device *dev, size_t size,
214 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
216 if (!IS_ENABLED(CONFIG_ARCH_HAS_UNCACHED_SEGMENT) &&
217 dma_alloc_need_uncached(dev, attrs))
218 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
220 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);
223 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
224 defined(CONFIG_SWIOTLB)
225 void dma_direct_sync_single_for_device(struct device *dev,
226 dma_addr_t addr, size_t size, enum dma_data_direction dir)
228 phys_addr_t paddr = dma_to_phys(dev, addr);
230 if (unlikely(is_swiotlb_buffer(paddr)))
231 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_DEVICE);
233 if (!dev_is_dma_coherent(dev))
234 arch_sync_dma_for_device(dev, paddr, size, dir);
236 EXPORT_SYMBOL(dma_direct_sync_single_for_device);
238 void dma_direct_sync_sg_for_device(struct device *dev,
239 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
241 struct scatterlist *sg;
244 for_each_sg(sgl, sg, nents, i) {
245 if (unlikely(is_swiotlb_buffer(sg_phys(sg))))
246 swiotlb_tbl_sync_single(dev, sg_phys(sg), sg->length,
247 dir, SYNC_FOR_DEVICE);
249 if (!dev_is_dma_coherent(dev))
250 arch_sync_dma_for_device(dev, sg_phys(sg), sg->length,
254 EXPORT_SYMBOL(dma_direct_sync_sg_for_device);
257 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
258 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
259 defined(CONFIG_SWIOTLB)
260 void dma_direct_sync_single_for_cpu(struct device *dev,
261 dma_addr_t addr, size_t size, enum dma_data_direction dir)
263 phys_addr_t paddr = dma_to_phys(dev, addr);
265 if (!dev_is_dma_coherent(dev)) {
266 arch_sync_dma_for_cpu(dev, paddr, size, dir);
267 arch_sync_dma_for_cpu_all(dev);
270 if (unlikely(is_swiotlb_buffer(paddr)))
271 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU);
273 EXPORT_SYMBOL(dma_direct_sync_single_for_cpu);
275 void dma_direct_sync_sg_for_cpu(struct device *dev,
276 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
278 struct scatterlist *sg;
281 for_each_sg(sgl, sg, nents, i) {
282 if (!dev_is_dma_coherent(dev))
283 arch_sync_dma_for_cpu(dev, sg_phys(sg), sg->length, dir);
285 if (unlikely(is_swiotlb_buffer(sg_phys(sg))))
286 swiotlb_tbl_sync_single(dev, sg_phys(sg), sg->length, dir,
290 if (!dev_is_dma_coherent(dev))
291 arch_sync_dma_for_cpu_all(dev);
293 EXPORT_SYMBOL(dma_direct_sync_sg_for_cpu);
295 void dma_direct_unmap_page(struct device *dev, dma_addr_t addr,
296 size_t size, enum dma_data_direction dir, unsigned long attrs)
298 phys_addr_t phys = dma_to_phys(dev, addr);
300 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
301 dma_direct_sync_single_for_cpu(dev, addr, size, dir);
303 if (unlikely(is_swiotlb_buffer(phys)))
304 swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
306 EXPORT_SYMBOL(dma_direct_unmap_page);
308 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
309 int nents, enum dma_data_direction dir, unsigned long attrs)
311 struct scatterlist *sg;
314 for_each_sg(sgl, sg, nents, i)
315 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
318 EXPORT_SYMBOL(dma_direct_unmap_sg);
321 static inline bool dma_direct_possible(struct device *dev, dma_addr_t dma_addr,
324 return swiotlb_force != SWIOTLB_FORCE &&
325 dma_capable(dev, dma_addr, size);
328 dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
329 unsigned long offset, size_t size, enum dma_data_direction dir,
332 phys_addr_t phys = page_to_phys(page) + offset;
333 dma_addr_t dma_addr = phys_to_dma(dev, phys);
335 if (unlikely(!dma_direct_possible(dev, dma_addr, size)) &&
336 !swiotlb_map(dev, &phys, &dma_addr, size, dir, attrs)) {
337 report_addr(dev, dma_addr, size);
338 return DMA_MAPPING_ERROR;
341 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
342 arch_sync_dma_for_device(dev, phys, size, dir);
345 EXPORT_SYMBOL(dma_direct_map_page);
347 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
348 enum dma_data_direction dir, unsigned long attrs)
351 struct scatterlist *sg;
353 for_each_sg(sgl, sg, nents, i) {
354 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
355 sg->offset, sg->length, dir, attrs);
356 if (sg->dma_address == DMA_MAPPING_ERROR)
358 sg_dma_len(sg) = sg->length;
364 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
367 EXPORT_SYMBOL(dma_direct_map_sg);
369 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
370 size_t size, enum dma_data_direction dir, unsigned long attrs)
372 dma_addr_t dma_addr = paddr;
374 if (unlikely(!dma_direct_possible(dev, dma_addr, size))) {
375 report_addr(dev, dma_addr, size);
376 return DMA_MAPPING_ERROR;
381 EXPORT_SYMBOL(dma_direct_map_resource);
384 * Because 32-bit DMA masks are so common we expect every architecture to be
385 * able to satisfy them - either by not supporting more physical memory, or by
386 * providing a ZONE_DMA32. If neither is the case, the architecture needs to
387 * use an IOMMU instead of the direct mapping.
389 int dma_direct_supported(struct device *dev, u64 mask)
393 if (IS_ENABLED(CONFIG_ZONE_DMA))
394 min_mask = DMA_BIT_MASK(ARCH_ZONE_DMA_BITS);
396 min_mask = DMA_BIT_MASK(32);
398 min_mask = min_t(u64, min_mask, (max_pfn - 1) << PAGE_SHIFT);
401 * This check needs to be against the actual bit mask value, so
402 * use __phys_to_dma() here so that the SME encryption mask isn't
405 return mask >= __phys_to_dma(dev, min_mask);
408 size_t dma_direct_max_mapping_size(struct device *dev)
410 size_t size = SIZE_MAX;
412 /* If SWIOTLB is active, use its maximum mapping size */
413 if (is_swiotlb_active())
414 size = swiotlb_max_mapping_size(dev);