2 * Copyright (c) 2010 Google, Inc
3 * Copyright (c) 2014 NVIDIA Corporation
6 * Colin Cross <ccross@google.com>
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #ifndef __SOC_TEGRA_PMC_H__
20 #define __SOC_TEGRA_PMC_H__
22 #include <linux/reboot.h>
24 #include <soc/tegra/pm.h>
29 bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
30 int tegra_pmc_cpu_power_on(unsigned int cpuid);
31 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
34 * powergate and I/O rail APIs
37 #define TEGRA_POWERGATE_CPU 0
38 #define TEGRA_POWERGATE_3D 1
39 #define TEGRA_POWERGATE_VENC 2
40 #define TEGRA_POWERGATE_PCIE 3
41 #define TEGRA_POWERGATE_VDEC 4
42 #define TEGRA_POWERGATE_L2 5
43 #define TEGRA_POWERGATE_MPE 6
44 #define TEGRA_POWERGATE_HEG 7
45 #define TEGRA_POWERGATE_SATA 8
46 #define TEGRA_POWERGATE_CPU1 9
47 #define TEGRA_POWERGATE_CPU2 10
48 #define TEGRA_POWERGATE_CPU3 11
49 #define TEGRA_POWERGATE_CELP 12
50 #define TEGRA_POWERGATE_3D1 13
51 #define TEGRA_POWERGATE_CPU0 14
52 #define TEGRA_POWERGATE_C0NC 15
53 #define TEGRA_POWERGATE_C1NC 16
54 #define TEGRA_POWERGATE_SOR 17
55 #define TEGRA_POWERGATE_DIS 18
56 #define TEGRA_POWERGATE_DISB 19
57 #define TEGRA_POWERGATE_XUSBA 20
58 #define TEGRA_POWERGATE_XUSBB 21
59 #define TEGRA_POWERGATE_XUSBC 22
60 #define TEGRA_POWERGATE_VIC 23
61 #define TEGRA_POWERGATE_IRAM 24
62 #define TEGRA_POWERGATE_NVDEC 25
63 #define TEGRA_POWERGATE_NVJPG 26
64 #define TEGRA_POWERGATE_AUD 27
65 #define TEGRA_POWERGATE_DFD 28
66 #define TEGRA_POWERGATE_VE2 29
67 #define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2
69 #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
72 * enum tegra_io_pad - I/O pad group identifier
74 * I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad
75 * can be used to control the common voltage signal level and power state of
76 * the pins of the given pad.
80 TEGRA_IO_PAD_AUDIO_HV,
96 TEGRA_IO_PAD_DEBUG_NONAO,
109 TEGRA_IO_PAD_GP_PWM2,
110 TEGRA_IO_PAD_GP_PWM3,
112 TEGRA_IO_PAD_HDMI_DP0,
113 TEGRA_IO_PAD_HDMI_DP1,
114 TEGRA_IO_PAD_HDMI_DP2,
115 TEGRA_IO_PAD_HDMI_DP3,
119 TEGRA_IO_PAD_MIPI_BIAS,
121 TEGRA_IO_PAD_PEX_BIAS,
122 TEGRA_IO_PAD_PEX_CLK_BIAS,
123 TEGRA_IO_PAD_PEX_CLK1,
124 TEGRA_IO_PAD_PEX_CLK2,
125 TEGRA_IO_PAD_PEX_CLK2_BIAS,
126 TEGRA_IO_PAD_PEX_CLK3,
127 TEGRA_IO_PAD_PEX_CNTRL,
128 TEGRA_IO_PAD_PEX_CTL2,
129 TEGRA_IO_PAD_PEX_L0_RST_N,
130 TEGRA_IO_PAD_PEX_L1_RST_N,
131 TEGRA_IO_PAD_PEX_L5_RST_N,
132 TEGRA_IO_PAD_PWR_CTL,
134 TEGRA_IO_PAD_SDMMC1_HV,
136 TEGRA_IO_PAD_SDMMC2_HV,
138 TEGRA_IO_PAD_SDMMC3_HV,
140 TEGRA_IO_PAD_SOC_GPIO10,
141 TEGRA_IO_PAD_SOC_GPIO12,
142 TEGRA_IO_PAD_SOC_GPIO13,
143 TEGRA_IO_PAD_SOC_GPIO53,
146 TEGRA_IO_PAD_SYS_DDC,
155 TEGRA_IO_PAD_USB_BIAS,
159 /* deprecated, use TEGRA_IO_PAD_{HDMI,LVDS} instead */
160 #define TEGRA_IO_RAIL_HDMI TEGRA_IO_PAD_HDMI
161 #define TEGRA_IO_RAIL_LVDS TEGRA_IO_PAD_LVDS
163 #ifdef CONFIG_SOC_TEGRA_PMC
164 int tegra_powergate_is_powered(unsigned int id);
165 int tegra_powergate_power_on(unsigned int id);
166 int tegra_powergate_power_off(unsigned int id);
167 int tegra_powergate_remove_clamping(unsigned int id);
169 /* Must be called with clk disabled, and returns with clk enabled */
170 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
171 struct reset_control *rst);
173 int tegra_io_pad_power_enable(enum tegra_io_pad id);
174 int tegra_io_pad_power_disable(enum tegra_io_pad id);
176 /* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
177 int tegra_io_rail_power_on(unsigned int id);
178 int tegra_io_rail_power_off(unsigned int id);
180 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
181 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
182 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
185 static inline int tegra_powergate_is_powered(unsigned int id)
190 static inline int tegra_powergate_power_on(unsigned int id)
195 static inline int tegra_powergate_power_off(unsigned int id)
200 static inline int tegra_powergate_remove_clamping(unsigned int id)
205 static inline int tegra_powergate_sequence_power_up(unsigned int id,
207 struct reset_control *rst)
212 static inline int tegra_io_pad_power_enable(enum tegra_io_pad id)
217 static inline int tegra_io_pad_power_disable(enum tegra_io_pad id)
222 static inline int tegra_io_pad_get_voltage(enum tegra_io_pad id)
227 static inline int tegra_io_rail_power_on(unsigned int id)
232 static inline int tegra_io_rail_power_off(unsigned int id)
237 static inline enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
239 return TEGRA_SUSPEND_NONE;
242 static inline void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
246 static inline void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
250 #endif /* CONFIG_SOC_TEGRA_PMC */
252 #endif /* __SOC_TEGRA_PMC_H__ */