4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
74 * For PCI devices, the region numbers are assigned this way:
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* device specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* total resources associated with a PCI device */
100 /* preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * pci_power_t values must match the bits in the Capabilities PME_Support
106 * and Control/Status PowerState fields in the Power Management capability.
108 typedef int __bitwise pci_power_t;
110 #define PCI_D0 ((pci_power_t __force) 0)
111 #define PCI_D1 ((pci_power_t __force) 1)
112 #define PCI_D2 ((pci_power_t __force) 2)
113 #define PCI_D3hot ((pci_power_t __force) 3)
114 #define PCI_D3cold ((pci_power_t __force) 4)
115 #define PCI_UNKNOWN ((pci_power_t __force) 5)
116 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
118 /* Remember to update this when the list above changes! */
119 extern const char *pci_power_names[];
121 static inline const char *pci_power_name(pci_power_t state)
123 return pci_power_names[1 + (__force int) state];
126 #define PCI_PM_D2_DELAY 200
127 #define PCI_PM_D3_WAIT 10
128 #define PCI_PM_D3COLD_WAIT 100
129 #define PCI_PM_BUS_WAIT 50
131 /** The pci_channel state describes connectivity between the CPU and
132 * the pci device. If some PCI bus between here and the pci device
133 * has crashed or locked up, this info is reflected here.
135 typedef unsigned int __bitwise pci_channel_state_t;
137 enum pci_channel_state {
138 /* I/O channel is in normal state */
139 pci_channel_io_normal = (__force pci_channel_state_t) 1,
141 /* I/O to channel is blocked */
142 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
144 /* PCI card is dead */
145 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148 typedef unsigned int __bitwise pcie_reset_state_t;
150 enum pcie_reset_state {
151 /* Reset is NOT asserted (Use to deassert reset) */
152 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
154 /* Use #PERST to reset PCIe device */
155 pcie_warm_reset = (__force pcie_reset_state_t) 2,
157 /* Use PCIe Hot Reset to reset device */
158 pcie_hot_reset = (__force pcie_reset_state_t) 3
161 typedef unsigned short __bitwise pci_dev_flags_t;
163 /* INTX_DISABLE in PCI_COMMAND register disables MSI
166 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
167 /* Device configuration is irrevocably lost if disabled into D3 */
168 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
169 /* Provide indication device is assigned by a Virtual Machine Manager */
170 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
171 /* Flag for quirk use to store if quirk-specific ACS is enabled */
172 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
173 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
174 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
175 /* Do not use bus resets for device */
176 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
177 /* Do not use PM reset even if device advertises NoSoftRst- */
178 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
179 /* Get VPD from function 0 VPD */
180 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
183 enum pci_irq_reroute_variant {
184 INTEL_IRQ_REROUTE_VARIANT = 1,
185 MAX_IRQ_REROUTE_VARIANTS = 3
188 typedef unsigned short __bitwise pci_bus_flags_t;
190 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
191 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
194 /* These values come from the PCI Express Spec */
195 enum pcie_link_width {
196 PCIE_LNK_WIDTH_RESRV = 0x00,
204 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
207 /* Based on the PCI Hotplug Spec, but some values are made up by us */
209 PCI_SPEED_33MHz = 0x00,
210 PCI_SPEED_66MHz = 0x01,
211 PCI_SPEED_66MHz_PCIX = 0x02,
212 PCI_SPEED_100MHz_PCIX = 0x03,
213 PCI_SPEED_133MHz_PCIX = 0x04,
214 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
215 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
216 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
217 PCI_SPEED_66MHz_PCIX_266 = 0x09,
218 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
219 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
225 PCI_SPEED_66MHz_PCIX_533 = 0x11,
226 PCI_SPEED_100MHz_PCIX_533 = 0x12,
227 PCI_SPEED_133MHz_PCIX_533 = 0x13,
228 PCIE_SPEED_2_5GT = 0x14,
229 PCIE_SPEED_5_0GT = 0x15,
230 PCIE_SPEED_8_0GT = 0x16,
231 PCI_SPEED_UNKNOWN = 0xff,
234 struct pci_cap_saved_data {
241 struct pci_cap_saved_state {
242 struct hlist_node next;
243 struct pci_cap_saved_data cap;
246 struct pcie_link_state;
252 * The pci_dev structure is used to describe PCI devices.
255 struct list_head bus_list; /* node in per-bus list */
256 struct pci_bus *bus; /* bus this device is on */
257 struct pci_bus *subordinate; /* bus this device bridges to */
259 void *sysdata; /* hook for sys-specific extension */
260 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
261 struct pci_slot *slot; /* Physical slot this device is in */
263 unsigned int devfn; /* encoded device & function index */
264 unsigned short vendor;
265 unsigned short device;
266 unsigned short subsystem_vendor;
267 unsigned short subsystem_device;
268 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
269 u8 revision; /* PCI revision, low byte of class word */
270 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
271 u8 pcie_cap; /* PCIe capability offset */
272 u8 msi_cap; /* MSI capability offset */
273 u8 msix_cap; /* MSI-X capability offset */
274 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
275 u8 rom_base_reg; /* which config register controls the ROM */
276 u8 pin; /* which interrupt pin this device uses */
277 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
278 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
280 struct pci_driver *driver; /* which driver has allocated this device */
281 u64 dma_mask; /* Mask of the bits of bus address this
282 device implements. Normally this is
283 0xffffffff. You only need to change
284 this if your device has broken DMA
285 or supports 64-bit transfers. */
287 struct device_dma_parameters dma_parms;
289 pci_power_t current_state; /* Current operating state. In ACPI-speak,
290 this is D0-D3, D0 being fully functional,
292 u8 pm_cap; /* PM capability offset */
293 unsigned int pme_support:5; /* Bitmask of states from which PME#
295 unsigned int pme_interrupt:1;
296 unsigned int pme_poll:1; /* Poll device's PME status bit */
297 unsigned int d1_support:1; /* Low power state D1 is supported */
298 unsigned int d2_support:1; /* Low power state D2 is supported */
299 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
300 unsigned int no_d3cold:1; /* D3cold is forbidden */
301 unsigned int bridge_d3:1; /* Allow D3 for bridge */
302 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
303 unsigned int mmio_always_on:1; /* disallow turning off io/mem
304 decoding during bar sizing */
305 unsigned int wakeup_prepared:1;
306 unsigned int runtime_d3cold:1; /* whether go through runtime
307 D3cold, not set for devices
308 powered on/off by the
309 corresponding bridge */
310 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
311 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
312 controlled exclusively by
314 unsigned int d3_delay; /* D3->D0 transition time in ms */
315 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
317 #ifdef CONFIG_PCIEASPM
318 struct pcie_link_state *link_state; /* ASPM link state */
321 pci_channel_state_t error_state; /* current connectivity state */
322 struct device dev; /* Generic device interface */
324 int cfg_size; /* Size of configuration space */
327 * Instead of touching interrupt line and base address registers
328 * directly, use the values stored here. They might be different!
331 struct cpumask *irq_affinity;
332 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
334 bool match_driver; /* Skip attaching driver */
335 /* These fields are used by common fixups */
336 unsigned int transparent:1; /* Subtractive decode PCI bridge */
337 unsigned int multifunction:1;/* Part of multi-function device */
338 /* keep track of device state */
339 unsigned int is_added:1;
340 unsigned int is_busmaster:1; /* device is busmaster */
341 unsigned int no_msi:1; /* device may not use msi */
342 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
343 unsigned int block_cfg_access:1; /* config space access is blocked */
344 unsigned int broken_parity_status:1; /* Device generates false positive parity */
345 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
346 unsigned int msi_enabled:1;
347 unsigned int msix_enabled:1;
348 unsigned int ari_enabled:1; /* ARI forwarding */
349 unsigned int ats_enabled:1; /* Address Translation Service */
350 unsigned int is_managed:1;
351 unsigned int needs_freset:1; /* Dev requires fundamental reset */
352 unsigned int state_saved:1;
353 unsigned int is_physfn:1;
354 unsigned int is_virtfn:1;
355 unsigned int reset_fn:1;
356 unsigned int is_hotplug_bridge:1;
357 unsigned int __aer_firmware_first_valid:1;
358 unsigned int __aer_firmware_first:1;
359 unsigned int broken_intx_masking:1;
360 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
361 unsigned int irq_managed:1;
362 unsigned int has_secondary_link:1;
363 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
364 pci_dev_flags_t dev_flags;
365 atomic_t enable_cnt; /* pci_enable_device has been called */
367 u32 saved_config_space[16]; /* config space saved at suspend time */
368 struct hlist_head saved_cap_space;
369 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
370 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
371 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
372 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
373 #ifdef CONFIG_PCI_MSI
374 const struct attribute_group **msi_irq_groups;
377 #ifdef CONFIG_PCI_ATS
379 struct pci_sriov *sriov; /* SR-IOV capability related */
380 struct pci_dev *physfn; /* the PF this VF is associated with */
382 u16 ats_cap; /* ATS Capability offset */
383 u8 ats_stu; /* ATS Smallest Translation Unit */
384 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
386 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
387 size_t romlen; /* Length of ROM if it's not from the BAR */
388 char *driver_override; /* Driver name to force a match */
391 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
393 #ifdef CONFIG_PCI_IOV
400 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
402 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
403 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
405 static inline int pci_channel_offline(struct pci_dev *pdev)
407 return (pdev->error_state != pci_channel_io_normal);
410 struct pci_host_bridge {
412 struct pci_bus *bus; /* root bus */
413 struct list_head windows; /* resource_entry */
414 void (*release_fn)(struct pci_host_bridge *);
416 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
417 /* Resource alignment requirements */
418 resource_size_t (*align_resource)(struct pci_dev *dev,
419 const struct resource *res,
420 resource_size_t start,
421 resource_size_t size,
422 resource_size_t align);
425 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
427 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
429 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
430 void (*release_fn)(struct pci_host_bridge *),
433 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
436 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
437 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
438 * buses below host bridges or subtractive decode bridges) go in the list.
439 * Use pci_bus_for_each_resource() to iterate through all the resources.
443 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
444 * and there's no way to program the bridge with the details of the window.
445 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
446 * decode bit set, because they are explicit and can be programmed with _SRS.
448 #define PCI_SUBTRACTIVE_DECODE 0x1
450 struct pci_bus_resource {
451 struct list_head list;
452 struct resource *res;
456 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
459 struct list_head node; /* node in list of buses */
460 struct pci_bus *parent; /* parent bus this bridge is on */
461 struct list_head children; /* list of child buses */
462 struct list_head devices; /* list of devices on this bus */
463 struct pci_dev *self; /* bridge device as seen by parent */
464 struct list_head slots; /* list of slots on this bus;
465 protected by pci_slot_mutex */
466 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
467 struct list_head resources; /* address space routed to this bus */
468 struct resource busn_res; /* bus numbers routed to this bus */
470 struct pci_ops *ops; /* configuration access functions */
471 struct msi_controller *msi; /* MSI controller */
472 void *sysdata; /* hook for sys-specific extension */
473 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
475 unsigned char number; /* bus number */
476 unsigned char primary; /* number of primary bridge */
477 unsigned char max_bus_speed; /* enum pci_bus_speed */
478 unsigned char cur_bus_speed; /* enum pci_bus_speed */
479 #ifdef CONFIG_PCI_DOMAINS_GENERIC
485 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
486 pci_bus_flags_t bus_flags; /* inherited by child buses */
487 struct device *bridge;
489 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
490 struct bin_attribute *legacy_mem; /* legacy mem */
491 unsigned int is_added:1;
494 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
497 * Returns true if the PCI bus is root (behind host-PCI bridge),
500 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
501 * This is incorrect because "virtual" buses added for SR-IOV (via
502 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
504 static inline bool pci_is_root_bus(struct pci_bus *pbus)
506 return !(pbus->parent);
510 * pci_is_bridge - check if the PCI device is a bridge
513 * Return true if the PCI device is bridge whether it has subordinate
516 static inline bool pci_is_bridge(struct pci_dev *dev)
518 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
519 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
522 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
524 dev = pci_physfn(dev);
525 if (pci_is_root_bus(dev->bus))
528 return dev->bus->self;
531 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
532 void pci_put_host_bridge_device(struct device *dev);
534 #ifdef CONFIG_PCI_MSI
535 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
537 return pci_dev->msi_enabled || pci_dev->msix_enabled;
540 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
544 * Error values that may be returned by PCI functions.
546 #define PCIBIOS_SUCCESSFUL 0x00
547 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
548 #define PCIBIOS_BAD_VENDOR_ID 0x83
549 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
550 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
551 #define PCIBIOS_SET_FAILED 0x88
552 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
555 * Translate above to generic errno for passing back through non-PCI code.
557 static inline int pcibios_err_to_errno(int err)
559 if (err <= PCIBIOS_SUCCESSFUL)
560 return err; /* Assume already errno */
563 case PCIBIOS_FUNC_NOT_SUPPORTED:
565 case PCIBIOS_BAD_VENDOR_ID:
567 case PCIBIOS_DEVICE_NOT_FOUND:
569 case PCIBIOS_BAD_REGISTER_NUMBER:
571 case PCIBIOS_SET_FAILED:
573 case PCIBIOS_BUFFER_TOO_SMALL:
580 /* Low-level architecture-dependent routines */
583 int (*add_bus)(struct pci_bus *bus);
584 void (*remove_bus)(struct pci_bus *bus);
585 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
586 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
587 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
591 * ACPI needs to be able to access PCI config space before we've done a
592 * PCI bus scan and created pci_bus structures.
594 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
595 int reg, int len, u32 *val);
596 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
597 int reg, int len, u32 val);
599 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
600 typedef u64 pci_bus_addr_t;
602 typedef u32 pci_bus_addr_t;
605 struct pci_bus_region {
606 pci_bus_addr_t start;
611 spinlock_t lock; /* protects list, index */
612 struct list_head list; /* for IDs added at runtime */
617 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
618 * a set of callbacks in struct pci_error_handlers, that device driver
619 * will be notified of PCI bus errors, and will be driven to recovery
620 * when an error occurs.
623 typedef unsigned int __bitwise pci_ers_result_t;
625 enum pci_ers_result {
626 /* no result/none/not supported in device driver */
627 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
629 /* Device driver can recover without slot reset */
630 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
632 /* Device driver wants slot to be reset. */
633 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
635 /* Device has completely failed, is unrecoverable */
636 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
638 /* Device driver is fully recovered and operational */
639 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
641 /* No AER capabilities registered for the driver */
642 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
645 /* PCI bus error event callbacks */
646 struct pci_error_handlers {
647 /* PCI bus error detected on this device */
648 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
649 enum pci_channel_state error);
651 /* MMIO has been re-enabled, but not DMA */
652 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
654 /* PCI Express link has been reset */
655 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
657 /* PCI slot has been reset */
658 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
660 /* PCI function reset prepare or completed */
661 void (*reset_notify)(struct pci_dev *dev, bool prepare);
663 /* Device driver may resume normal operations */
664 void (*resume)(struct pci_dev *dev);
670 struct list_head node;
672 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
673 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
674 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
675 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
676 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
677 int (*resume_early) (struct pci_dev *dev);
678 int (*resume) (struct pci_dev *dev); /* Device woken up */
679 void (*shutdown) (struct pci_dev *dev);
680 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
681 const struct pci_error_handlers *err_handler;
682 struct device_driver driver;
683 struct pci_dynids dynids;
686 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
689 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
690 * @_table: device table name
692 * This macro is deprecated and should not be used in new code.
694 #define DEFINE_PCI_DEVICE_TABLE(_table) \
695 const struct pci_device_id _table[]
698 * PCI_DEVICE - macro used to describe a specific pci device
699 * @vend: the 16 bit PCI Vendor ID
700 * @dev: the 16 bit PCI Device ID
702 * This macro is used to create a struct pci_device_id that matches a
703 * specific device. The subvendor and subdevice fields will be set to
706 #define PCI_DEVICE(vend,dev) \
707 .vendor = (vend), .device = (dev), \
708 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
711 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
712 * @vend: the 16 bit PCI Vendor ID
713 * @dev: the 16 bit PCI Device ID
714 * @subvend: the 16 bit PCI Subvendor ID
715 * @subdev: the 16 bit PCI Subdevice ID
717 * This macro is used to create a struct pci_device_id that matches a
718 * specific device with subsystem information.
720 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
721 .vendor = (vend), .device = (dev), \
722 .subvendor = (subvend), .subdevice = (subdev)
725 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
726 * @dev_class: the class, subclass, prog-if triple for this device
727 * @dev_class_mask: the class mask for this device
729 * This macro is used to create a struct pci_device_id that matches a
730 * specific PCI class. The vendor, device, subvendor, and subdevice
731 * fields will be set to PCI_ANY_ID.
733 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
734 .class = (dev_class), .class_mask = (dev_class_mask), \
735 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
736 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
739 * PCI_VDEVICE - macro used to describe a specific pci device in short form
740 * @vend: the vendor name
741 * @dev: the 16 bit PCI Device ID
743 * This macro is used to create a struct pci_device_id that matches a
744 * specific PCI device. The subvendor, and subdevice fields will be set
745 * to PCI_ANY_ID. The macro allows the next field to follow as the device
749 #define PCI_VDEVICE(vend, dev) \
750 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
751 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
754 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
755 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
756 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
757 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
758 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
759 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
760 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
763 /* these external functions are only available when PCI support is enabled */
766 extern unsigned int pci_flags;
768 static inline void pci_set_flags(int flags) { pci_flags = flags; }
769 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
770 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
771 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
773 void pcie_bus_configure_settings(struct pci_bus *bus);
775 enum pcie_bus_config_types {
776 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
777 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
778 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
779 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
780 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
783 extern enum pcie_bus_config_types pcie_bus_config;
785 extern struct bus_type pci_bus_type;
787 /* Do NOT directly access these two variables, unless you are arch-specific PCI
788 * code, or PCI core code. */
789 extern struct list_head pci_root_buses; /* list of all known PCI buses */
790 /* Some device drivers need know if PCI is initiated */
791 int no_pci_devices(void);
793 void pcibios_resource_survey_bus(struct pci_bus *bus);
794 void pcibios_bus_add_device(struct pci_dev *pdev);
795 void pcibios_add_bus(struct pci_bus *bus);
796 void pcibios_remove_bus(struct pci_bus *bus);
797 void pcibios_fixup_bus(struct pci_bus *);
798 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
799 /* Architecture-specific versions may override this (weak) */
800 char *pcibios_setup(char *str);
802 /* Used only when drivers/pci/setup.c is used */
803 resource_size_t pcibios_align_resource(void *, const struct resource *,
806 void pcibios_update_irq(struct pci_dev *, int irq);
808 /* Weak but can be overriden by arch */
809 void pci_fixup_cardbus(struct pci_bus *);
811 /* Generic PCI functions used internally */
813 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
814 struct resource *res);
815 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
816 struct pci_bus_region *region);
817 void pcibios_scan_specific_bus(int busn);
818 struct pci_bus *pci_find_bus(int domain, int busnr);
819 void pci_bus_add_devices(const struct pci_bus *bus);
820 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
821 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
822 struct pci_ops *ops, void *sysdata,
823 struct list_head *resources);
824 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
825 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
826 void pci_bus_release_busn_res(struct pci_bus *b);
827 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
828 struct pci_ops *ops, void *sysdata,
829 struct list_head *resources,
830 struct msi_controller *msi);
831 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
832 struct pci_ops *ops, void *sysdata,
833 struct list_head *resources);
834 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
836 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
837 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
839 struct hotplug_slot *hotplug);
840 void pci_destroy_slot(struct pci_slot *slot);
842 void pci_dev_assign_slot(struct pci_dev *dev);
844 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
846 int pci_scan_slot(struct pci_bus *bus, int devfn);
847 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
848 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
849 unsigned int pci_scan_child_bus(struct pci_bus *bus);
850 void pci_bus_add_device(struct pci_dev *dev);
851 void pci_read_bridge_bases(struct pci_bus *child);
852 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
853 struct resource *res);
854 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
855 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
856 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
857 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
858 struct pci_dev *pci_dev_get(struct pci_dev *dev);
859 void pci_dev_put(struct pci_dev *dev);
860 void pci_remove_bus(struct pci_bus *b);
861 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
862 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
863 void pci_stop_root_bus(struct pci_bus *bus);
864 void pci_remove_root_bus(struct pci_bus *bus);
865 void pci_setup_cardbus(struct pci_bus *bus);
866 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
867 void pci_sort_breadthfirst(void);
868 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
869 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
870 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
872 /* Generic PCI functions exported to card drivers */
874 enum pci_lost_interrupt_reason {
875 PCI_LOST_IRQ_NO_INFORMATION = 0,
876 PCI_LOST_IRQ_DISABLE_MSI,
877 PCI_LOST_IRQ_DISABLE_MSIX,
878 PCI_LOST_IRQ_DISABLE_ACPI,
880 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
881 int pci_find_capability(struct pci_dev *dev, int cap);
882 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
883 int pci_find_ext_capability(struct pci_dev *dev, int cap);
884 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
885 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
886 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
887 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
889 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
890 struct pci_dev *from);
891 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
892 unsigned int ss_vendor, unsigned int ss_device,
893 struct pci_dev *from);
894 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
895 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
897 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
900 return pci_get_domain_bus_and_slot(0, bus, devfn);
902 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
903 int pci_dev_present(const struct pci_device_id *ids);
905 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
907 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
908 int where, u16 *val);
909 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
910 int where, u32 *val);
911 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
913 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
915 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
918 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
919 int where, int size, u32 *val);
920 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
921 int where, int size, u32 val);
922 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
923 int where, int size, u32 *val);
924 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
925 int where, int size, u32 val);
927 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
929 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
931 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
933 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
935 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
937 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
940 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
942 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
944 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
946 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
948 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
950 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
953 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
956 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
957 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
958 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
959 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
960 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
962 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
965 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
968 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
971 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
974 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
977 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
980 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
983 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
986 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
989 /* user-space driven config access */
990 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
991 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
992 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
993 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
994 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
995 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
997 int __must_check pci_enable_device(struct pci_dev *dev);
998 int __must_check pci_enable_device_io(struct pci_dev *dev);
999 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1000 int __must_check pci_reenable_device(struct pci_dev *);
1001 int __must_check pcim_enable_device(struct pci_dev *pdev);
1002 void pcim_pin_device(struct pci_dev *pdev);
1004 static inline int pci_is_enabled(struct pci_dev *pdev)
1006 return (atomic_read(&pdev->enable_cnt) > 0);
1009 static inline int pci_is_managed(struct pci_dev *pdev)
1011 return pdev->is_managed;
1014 void pci_disable_device(struct pci_dev *dev);
1016 extern unsigned int pcibios_max_latency;
1017 void pci_set_master(struct pci_dev *dev);
1018 void pci_clear_master(struct pci_dev *dev);
1020 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1021 int pci_set_cacheline_size(struct pci_dev *dev);
1022 #define HAVE_PCI_SET_MWI
1023 int __must_check pci_set_mwi(struct pci_dev *dev);
1024 int pci_try_set_mwi(struct pci_dev *dev);
1025 void pci_clear_mwi(struct pci_dev *dev);
1026 void pci_intx(struct pci_dev *dev, int enable);
1027 bool pci_intx_mask_supported(struct pci_dev *dev);
1028 bool pci_check_and_mask_intx(struct pci_dev *dev);
1029 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1030 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1031 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1032 int pcix_get_max_mmrbc(struct pci_dev *dev);
1033 int pcix_get_mmrbc(struct pci_dev *dev);
1034 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1035 int pcie_get_readrq(struct pci_dev *dev);
1036 int pcie_set_readrq(struct pci_dev *dev, int rq);
1037 int pcie_get_mps(struct pci_dev *dev);
1038 int pcie_set_mps(struct pci_dev *dev, int mps);
1039 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1040 enum pcie_link_width *width);
1041 int __pci_reset_function(struct pci_dev *dev);
1042 int __pci_reset_function_locked(struct pci_dev *dev);
1043 int pci_reset_function(struct pci_dev *dev);
1044 int pci_try_reset_function(struct pci_dev *dev);
1045 int pci_probe_reset_slot(struct pci_slot *slot);
1046 int pci_reset_slot(struct pci_slot *slot);
1047 int pci_try_reset_slot(struct pci_slot *slot);
1048 int pci_probe_reset_bus(struct pci_bus *bus);
1049 int pci_reset_bus(struct pci_bus *bus);
1050 int pci_try_reset_bus(struct pci_bus *bus);
1051 void pci_reset_secondary_bus(struct pci_dev *dev);
1052 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1053 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1054 void pci_update_resource(struct pci_dev *dev, int resno);
1055 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1056 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1057 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1058 bool pci_device_is_present(struct pci_dev *pdev);
1059 void pci_ignore_hotplug(struct pci_dev *dev);
1061 /* ROM control related routines */
1062 int pci_enable_rom(struct pci_dev *pdev);
1063 void pci_disable_rom(struct pci_dev *pdev);
1064 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1065 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1066 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1067 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1069 /* Power management related routines */
1070 int pci_save_state(struct pci_dev *dev);
1071 void pci_restore_state(struct pci_dev *dev);
1072 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1073 int pci_load_saved_state(struct pci_dev *dev,
1074 struct pci_saved_state *state);
1075 int pci_load_and_free_saved_state(struct pci_dev *dev,
1076 struct pci_saved_state **state);
1077 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1078 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1080 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1081 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1082 u16 cap, unsigned int size);
1083 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1084 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1085 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1086 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1087 void pci_pme_active(struct pci_dev *dev, bool enable);
1088 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1089 bool runtime, bool enable);
1090 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1091 int pci_prepare_to_sleep(struct pci_dev *dev);
1092 int pci_back_from_sleep(struct pci_dev *dev);
1093 bool pci_dev_run_wake(struct pci_dev *dev);
1094 bool pci_check_pme_status(struct pci_dev *dev);
1095 void pci_pme_wakeup_bus(struct pci_bus *bus);
1096 void pci_d3cold_enable(struct pci_dev *dev);
1097 void pci_d3cold_disable(struct pci_dev *dev);
1099 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1102 return __pci_enable_wake(dev, state, false, enable);
1105 /* PCI Virtual Channel */
1106 int pci_save_vc_state(struct pci_dev *dev);
1107 void pci_restore_vc_state(struct pci_dev *dev);
1108 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1110 /* For use by arch with custom probe code */
1111 void set_pcie_port_type(struct pci_dev *pdev);
1112 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1114 /* Functions for PCI Hotplug drivers to use */
1115 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1116 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1117 unsigned int pci_rescan_bus(struct pci_bus *bus);
1118 void pci_lock_rescan_remove(void);
1119 void pci_unlock_rescan_remove(void);
1121 /* Vital product data routines */
1122 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1123 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1124 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1126 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1127 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1128 void pci_bus_assign_resources(const struct pci_bus *bus);
1129 void pci_bus_claim_resources(struct pci_bus *bus);
1130 void pci_bus_size_bridges(struct pci_bus *bus);
1131 int pci_claim_resource(struct pci_dev *, int);
1132 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1133 void pci_assign_unassigned_resources(void);
1134 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1135 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1136 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1137 void pdev_enable_device(struct pci_dev *);
1138 int pci_enable_resources(struct pci_dev *, int mask);
1139 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1140 int (*)(const struct pci_dev *, u8, u8));
1141 #define HAVE_PCI_REQ_REGIONS 2
1142 int __must_check pci_request_regions(struct pci_dev *, const char *);
1143 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1144 void pci_release_regions(struct pci_dev *);
1145 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1146 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1147 void pci_release_region(struct pci_dev *, int);
1148 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1149 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1150 void pci_release_selected_regions(struct pci_dev *, int);
1152 /* drivers/pci/bus.c */
1153 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1154 void pci_bus_put(struct pci_bus *bus);
1155 void pci_add_resource(struct list_head *resources, struct resource *res);
1156 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1157 resource_size_t offset);
1158 void pci_free_resource_list(struct list_head *resources);
1159 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1160 unsigned int flags);
1161 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1162 void pci_bus_remove_resources(struct pci_bus *bus);
1163 int devm_request_pci_bus_resources(struct device *dev,
1164 struct list_head *resources);
1166 #define pci_bus_for_each_resource(bus, res, i) \
1168 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1171 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1172 struct resource *res, resource_size_t size,
1173 resource_size_t align, resource_size_t min,
1174 unsigned long type_mask,
1175 resource_size_t (*alignf)(void *,
1176 const struct resource *,
1182 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1183 unsigned long pci_address_to_pio(phys_addr_t addr);
1184 phys_addr_t pci_pio_to_address(unsigned long pio);
1185 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1186 void pci_unmap_iospace(struct resource *res);
1188 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1190 struct pci_bus_region region;
1192 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1193 return region.start;
1196 /* Proper probing supporting hot-pluggable devices */
1197 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1198 const char *mod_name);
1201 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1203 #define pci_register_driver(driver) \
1204 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1206 void pci_unregister_driver(struct pci_driver *dev);
1209 * module_pci_driver() - Helper macro for registering a PCI driver
1210 * @__pci_driver: pci_driver struct
1212 * Helper macro for PCI drivers which do not do anything special in module
1213 * init/exit. This eliminates a lot of boilerplate. Each module may only
1214 * use this macro once, and calling it replaces module_init() and module_exit()
1216 #define module_pci_driver(__pci_driver) \
1217 module_driver(__pci_driver, pci_register_driver, \
1218 pci_unregister_driver)
1221 * builtin_pci_driver() - Helper macro for registering a PCI driver
1222 * @__pci_driver: pci_driver struct
1224 * Helper macro for PCI drivers which do not do anything special in their
1225 * init code. This eliminates a lot of boilerplate. Each driver may only
1226 * use this macro once, and calling it replaces device_initcall(...)
1228 #define builtin_pci_driver(__pci_driver) \
1229 builtin_driver(__pci_driver, pci_register_driver)
1231 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1232 int pci_add_dynid(struct pci_driver *drv,
1233 unsigned int vendor, unsigned int device,
1234 unsigned int subvendor, unsigned int subdevice,
1235 unsigned int class, unsigned int class_mask,
1236 unsigned long driver_data);
1237 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1238 struct pci_dev *dev);
1239 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1242 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1244 int pci_cfg_space_size(struct pci_dev *dev);
1245 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1246 void pci_setup_bridge(struct pci_bus *bus);
1247 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1248 unsigned long type);
1249 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1251 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1252 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1254 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1255 unsigned int command_bits, u32 flags);
1257 #define PCI_IRQ_NOLEGACY (1 << 0) /* don't use legacy interrupts */
1258 #define PCI_IRQ_NOMSI (1 << 1) /* don't use MSI interrupts */
1259 #define PCI_IRQ_NOMSIX (1 << 2) /* don't use MSI-X interrupts */
1260 #define PCI_IRQ_NOAFFINITY (1 << 3) /* don't auto-assign affinity */
1262 /* kmem_cache style wrapper around pci_alloc_consistent() */
1264 #include <linux/pci-dma.h>
1265 #include <linux/dmapool.h>
1267 #define pci_pool dma_pool
1268 #define pci_pool_create(name, pdev, size, align, allocation) \
1269 dma_pool_create(name, &pdev->dev, size, align, allocation)
1270 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1271 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1272 #define pci_pool_zalloc(pool, flags, handle) \
1273 dma_pool_zalloc(pool, flags, handle)
1274 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1277 u32 vector; /* kernel uses to write allocated vector */
1278 u16 entry; /* driver uses to specify entry, OS writes */
1281 #ifdef CONFIG_PCI_MSI
1282 int pci_msi_vec_count(struct pci_dev *dev);
1283 void pci_msi_shutdown(struct pci_dev *dev);
1284 void pci_disable_msi(struct pci_dev *dev);
1285 int pci_msix_vec_count(struct pci_dev *dev);
1286 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1287 void pci_msix_shutdown(struct pci_dev *dev);
1288 void pci_disable_msix(struct pci_dev *dev);
1289 void pci_restore_msi_state(struct pci_dev *dev);
1290 int pci_msi_enabled(void);
1291 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1292 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1294 int rc = pci_enable_msi_range(dev, nvec, nvec);
1299 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1300 int minvec, int maxvec);
1301 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1302 struct msix_entry *entries, int nvec)
1304 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1309 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1310 unsigned int max_vecs, unsigned int flags);
1311 void pci_free_irq_vectors(struct pci_dev *dev);
1312 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1315 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1316 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1317 static inline void pci_disable_msi(struct pci_dev *dev) { }
1318 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1319 static inline int pci_enable_msix(struct pci_dev *dev,
1320 struct msix_entry *entries, int nvec)
1322 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1323 static inline void pci_disable_msix(struct pci_dev *dev) { }
1324 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1325 static inline int pci_msi_enabled(void) { return 0; }
1326 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1329 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1331 static inline int pci_enable_msix_range(struct pci_dev *dev,
1332 struct msix_entry *entries, int minvec, int maxvec)
1334 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1335 struct msix_entry *entries, int nvec)
1337 static inline int pci_alloc_irq_vectors(struct pci_dev *dev,
1338 unsigned int min_vecs, unsigned int max_vecs,
1345 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1349 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1351 if (WARN_ON_ONCE(nr > 0))
1357 #ifdef CONFIG_PCIEPORTBUS
1358 extern bool pcie_ports_disabled;
1359 extern bool pcie_ports_auto;
1361 #define pcie_ports_disabled true
1362 #define pcie_ports_auto false
1365 #ifdef CONFIG_PCIEASPM
1366 bool pcie_aspm_support_enabled(void);
1368 static inline bool pcie_aspm_support_enabled(void) { return false; }
1371 #ifdef CONFIG_PCIEAER
1372 void pci_no_aer(void);
1373 bool pci_aer_available(void);
1375 static inline void pci_no_aer(void) { }
1376 static inline bool pci_aer_available(void) { return false; }
1379 #ifdef CONFIG_PCIE_ECRC
1380 void pcie_set_ecrc_checking(struct pci_dev *dev);
1381 void pcie_ecrc_get_policy(char *str);
1383 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1384 static inline void pcie_ecrc_get_policy(char *str) { }
1387 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1389 #ifdef CONFIG_HT_IRQ
1390 /* The functions a driver should call */
1391 int ht_create_irq(struct pci_dev *dev, int idx);
1392 void ht_destroy_irq(unsigned int irq);
1393 #endif /* CONFIG_HT_IRQ */
1395 #ifdef CONFIG_PCI_ATS
1396 /* Address Translation Service */
1397 void pci_ats_init(struct pci_dev *dev);
1398 int pci_enable_ats(struct pci_dev *dev, int ps);
1399 void pci_disable_ats(struct pci_dev *dev);
1400 int pci_ats_queue_depth(struct pci_dev *dev);
1402 static inline void pci_ats_init(struct pci_dev *d) { }
1403 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1404 static inline void pci_disable_ats(struct pci_dev *d) { }
1405 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1408 void pci_cfg_access_lock(struct pci_dev *dev);
1409 bool pci_cfg_access_trylock(struct pci_dev *dev);
1410 void pci_cfg_access_unlock(struct pci_dev *dev);
1413 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1414 * a PCI domain is defined to be a set of PCI buses which share
1415 * configuration space.
1417 #ifdef CONFIG_PCI_DOMAINS
1418 extern int pci_domains_supported;
1419 int pci_get_new_domain_nr(void);
1421 enum { pci_domains_supported = 0 };
1422 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1423 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1424 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1425 #endif /* CONFIG_PCI_DOMAINS */
1428 * Generic implementation for PCI domain support. If your
1429 * architecture does not need custom management of PCI
1430 * domains then this implementation will be used
1432 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1433 static inline int pci_domain_nr(struct pci_bus *bus)
1435 return bus->domain_nr;
1438 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1440 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1443 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1446 /* some architectures require additional setup to direct VGA traffic */
1447 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1448 unsigned int command_bits, u32 flags);
1449 void pci_register_set_vga_state(arch_set_vga_state_t func);
1452 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1454 return pci_request_selected_regions(pdev,
1455 pci_select_bars(pdev, IORESOURCE_IO), name);
1459 pci_release_io_regions(struct pci_dev *pdev)
1461 return pci_release_selected_regions(pdev,
1462 pci_select_bars(pdev, IORESOURCE_IO));
1466 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1468 return pci_request_selected_regions(pdev,
1469 pci_select_bars(pdev, IORESOURCE_MEM), name);
1473 pci_release_mem_regions(struct pci_dev *pdev)
1475 return pci_release_selected_regions(pdev,
1476 pci_select_bars(pdev, IORESOURCE_MEM));
1479 #else /* CONFIG_PCI is not enabled */
1481 static inline void pci_set_flags(int flags) { }
1482 static inline void pci_add_flags(int flags) { }
1483 static inline void pci_clear_flags(int flags) { }
1484 static inline int pci_has_flag(int flag) { return 0; }
1487 * If the system does not have PCI, clearly these return errors. Define
1488 * these as simple inline functions to avoid hair in drivers.
1491 #define _PCI_NOP(o, s, t) \
1492 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1494 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1496 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1497 _PCI_NOP(o, word, u16 x) \
1498 _PCI_NOP(o, dword, u32 x)
1499 _PCI_NOP_ALL(read, *)
1500 _PCI_NOP_ALL(write,)
1502 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1503 unsigned int device,
1504 struct pci_dev *from)
1507 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1508 unsigned int device,
1509 unsigned int ss_vendor,
1510 unsigned int ss_device,
1511 struct pci_dev *from)
1514 static inline struct pci_dev *pci_get_class(unsigned int class,
1515 struct pci_dev *from)
1518 #define pci_dev_present(ids) (0)
1519 #define no_pci_devices() (1)
1520 #define pci_dev_put(dev) do { } while (0)
1522 static inline void pci_set_master(struct pci_dev *dev) { }
1523 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1524 static inline void pci_disable_device(struct pci_dev *dev) { }
1525 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1527 static inline int __pci_register_driver(struct pci_driver *drv,
1528 struct module *owner)
1530 static inline int pci_register_driver(struct pci_driver *drv)
1532 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1533 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1535 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1538 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1541 /* Power management related routines */
1542 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1543 static inline void pci_restore_state(struct pci_dev *dev) { }
1544 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1546 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1548 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1551 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1555 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1557 static inline void pci_release_regions(struct pci_dev *dev) { }
1559 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1561 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1562 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1564 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1566 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1568 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1571 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1575 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1576 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1577 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1579 #define dev_is_pci(d) (false)
1580 #define dev_is_pf(d) (false)
1581 #define dev_num_vf(d) (0)
1582 #endif /* CONFIG_PCI */
1584 /* Include architecture-dependent settings and functions */
1586 #include <asm/pci.h>
1588 #ifndef pci_root_bus_fwnode
1589 #define pci_root_bus_fwnode(bus) NULL
1592 /* these helpers provide future and backwards compatibility
1593 * for accessing popular PCI BAR info */
1594 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1595 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1596 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1597 #define pci_resource_len(dev,bar) \
1598 ((pci_resource_start((dev), (bar)) == 0 && \
1599 pci_resource_end((dev), (bar)) == \
1600 pci_resource_start((dev), (bar))) ? 0 : \
1602 (pci_resource_end((dev), (bar)) - \
1603 pci_resource_start((dev), (bar)) + 1))
1605 /* Similar to the helpers above, these manipulate per-pci_dev
1606 * driver-specific data. They are really just a wrapper around
1607 * the generic device structure functions of these calls.
1609 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1611 return dev_get_drvdata(&pdev->dev);
1614 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1616 dev_set_drvdata(&pdev->dev, data);
1619 /* If you want to know what to call your pci_dev, ask this function.
1620 * Again, it's a wrapper around the generic device.
1622 static inline const char *pci_name(const struct pci_dev *pdev)
1624 return dev_name(&pdev->dev);
1628 /* Some archs don't want to expose struct resource to userland as-is
1629 * in sysfs and /proc
1631 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1632 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1633 const struct resource *rsrc,
1634 resource_size_t *start, resource_size_t *end);
1636 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1637 const struct resource *rsrc, resource_size_t *start,
1638 resource_size_t *end)
1640 *start = rsrc->start;
1643 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1647 * The world is not perfect and supplies us with broken PCI devices.
1648 * For at least a part of these bugs we need a work-around, so both
1649 * generic (drivers/pci/quirks.c) and per-architecture code can define
1650 * fixup hooks to be called for particular buggy devices.
1654 u16 vendor; /* You can use PCI_ANY_ID here of course */
1655 u16 device; /* You can use PCI_ANY_ID here of course */
1656 u32 class; /* You can use PCI_ANY_ID here too */
1657 unsigned int class_shift; /* should be 0, 8, 16 */
1658 void (*hook)(struct pci_dev *dev);
1661 enum pci_fixup_pass {
1662 pci_fixup_early, /* Before probing BARs */
1663 pci_fixup_header, /* After reading configuration header */
1664 pci_fixup_final, /* Final phase of device fixups */
1665 pci_fixup_enable, /* pci_enable_device() time */
1666 pci_fixup_resume, /* pci_device_resume() */
1667 pci_fixup_suspend, /* pci_device_suspend() */
1668 pci_fixup_resume_early, /* pci_device_resume_early() */
1669 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1672 /* Anonymous variables would be nice... */
1673 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1674 class_shift, hook) \
1675 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1676 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1677 = { vendor, device, class, class_shift, hook };
1679 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1680 class_shift, hook) \
1681 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1682 hook, vendor, device, class, class_shift, hook)
1683 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1684 class_shift, hook) \
1685 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1686 hook, vendor, device, class, class_shift, hook)
1687 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1688 class_shift, hook) \
1689 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1690 hook, vendor, device, class, class_shift, hook)
1691 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1692 class_shift, hook) \
1693 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1694 hook, vendor, device, class, class_shift, hook)
1695 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1696 class_shift, hook) \
1697 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1698 resume##hook, vendor, device, class, \
1700 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1701 class_shift, hook) \
1702 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1703 resume_early##hook, vendor, device, \
1704 class, class_shift, hook)
1705 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1706 class_shift, hook) \
1707 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1708 suspend##hook, vendor, device, class, \
1710 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1711 class_shift, hook) \
1712 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1713 suspend_late##hook, vendor, device, \
1714 class, class_shift, hook)
1716 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1717 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1718 hook, vendor, device, PCI_ANY_ID, 0, hook)
1719 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1720 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1721 hook, vendor, device, PCI_ANY_ID, 0, hook)
1722 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1723 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1724 hook, vendor, device, PCI_ANY_ID, 0, hook)
1725 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1726 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1727 hook, vendor, device, PCI_ANY_ID, 0, hook)
1728 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1729 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1730 resume##hook, vendor, device, \
1731 PCI_ANY_ID, 0, hook)
1732 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1733 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1734 resume_early##hook, vendor, device, \
1735 PCI_ANY_ID, 0, hook)
1736 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1737 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1738 suspend##hook, vendor, device, \
1739 PCI_ANY_ID, 0, hook)
1740 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1741 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1742 suspend_late##hook, vendor, device, \
1743 PCI_ANY_ID, 0, hook)
1745 #ifdef CONFIG_PCI_QUIRKS
1746 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1747 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1748 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1750 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1751 struct pci_dev *dev) { }
1752 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1757 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1763 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1764 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1765 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1766 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1767 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1769 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1771 extern int pci_pci_problems;
1772 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1773 #define PCIPCI_TRITON 2
1774 #define PCIPCI_NATOMA 4
1775 #define PCIPCI_VIAETBF 8
1776 #define PCIPCI_VSFX 16
1777 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1778 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1780 extern unsigned long pci_cardbus_io_size;
1781 extern unsigned long pci_cardbus_mem_size;
1782 extern u8 pci_dfl_cache_line_size;
1783 extern u8 pci_cache_line_size;
1785 extern unsigned long pci_hotplug_io_size;
1786 extern unsigned long pci_hotplug_mem_size;
1787 extern unsigned long pci_hotplug_bus_size;
1789 /* Architecture-specific versions may override these (weak) */
1790 void pcibios_disable_device(struct pci_dev *dev);
1791 void pcibios_set_master(struct pci_dev *dev);
1792 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1793 enum pcie_reset_state state);
1794 int pcibios_add_device(struct pci_dev *dev);
1795 void pcibios_release_device(struct pci_dev *dev);
1796 void pcibios_penalize_isa_irq(int irq, int active);
1797 int pcibios_alloc_irq(struct pci_dev *dev);
1798 void pcibios_free_irq(struct pci_dev *dev);
1800 #ifdef CONFIG_HIBERNATE_CALLBACKS
1801 extern struct dev_pm_ops pcibios_pm_ops;
1804 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1805 void __init pci_mmcfg_early_init(void);
1806 void __init pci_mmcfg_late_init(void);
1808 static inline void pci_mmcfg_early_init(void) { }
1809 static inline void pci_mmcfg_late_init(void) { }
1812 int pci_ext_cfg_avail(void);
1814 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1815 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1817 #ifdef CONFIG_PCI_IOV
1818 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1819 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1821 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1822 void pci_disable_sriov(struct pci_dev *dev);
1823 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1824 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1825 int pci_num_vf(struct pci_dev *dev);
1826 int pci_vfs_assigned(struct pci_dev *dev);
1827 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1828 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1829 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1831 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1835 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1839 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1841 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1845 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1846 int id, int reset) { }
1847 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1848 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1849 static inline int pci_vfs_assigned(struct pci_dev *dev)
1851 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1853 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1855 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1859 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1860 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1861 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1865 * pci_pcie_cap - get the saved PCIe capability offset
1868 * PCIe capability offset is calculated at PCI device initialization
1869 * time and saved in the data structure. This function returns saved
1870 * PCIe capability offset. Using this instead of pci_find_capability()
1871 * reduces unnecessary search in the PCI configuration space. If you
1872 * need to calculate PCIe capability offset from raw device for some
1873 * reasons, please use pci_find_capability() instead.
1875 static inline int pci_pcie_cap(struct pci_dev *dev)
1877 return dev->pcie_cap;
1881 * pci_is_pcie - check if the PCI device is PCI Express capable
1884 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1886 static inline bool pci_is_pcie(struct pci_dev *dev)
1888 return pci_pcie_cap(dev);
1892 * pcie_caps_reg - get the PCIe Capabilities Register
1895 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1897 return dev->pcie_flags_reg;
1901 * pci_pcie_type - get the PCIe device/port type
1904 static inline int pci_pcie_type(const struct pci_dev *dev)
1906 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1909 void pci_request_acs(void);
1910 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1911 bool pci_acs_path_enabled(struct pci_dev *start,
1912 struct pci_dev *end, u16 acs_flags);
1914 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1915 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1917 /* Large Resource Data Type Tag Item Names */
1918 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1919 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1920 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1922 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1923 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1924 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1926 /* Small Resource Data Type Tag Item Names */
1927 #define PCI_VPD_STIN_END 0x0f /* End */
1929 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
1931 #define PCI_VPD_SRDT_TIN_MASK 0x78
1932 #define PCI_VPD_SRDT_LEN_MASK 0x07
1933 #define PCI_VPD_LRDT_TIN_MASK 0x7f
1935 #define PCI_VPD_LRDT_TAG_SIZE 3
1936 #define PCI_VPD_SRDT_TAG_SIZE 1
1938 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1940 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1941 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1942 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1943 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1946 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1947 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1949 * Returns the extracted Large Resource Data Type length.
1951 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1953 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1957 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
1958 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1960 * Returns the extracted Large Resource Data Type Tag item.
1962 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
1964 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
1968 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1969 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1971 * Returns the extracted Small Resource Data Type length.
1973 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1975 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1979 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
1980 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1982 * Returns the extracted Small Resource Data Type Tag Item.
1984 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
1986 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
1990 * pci_vpd_info_field_size - Extracts the information field length
1991 * @lrdt: Pointer to the beginning of an information field header
1993 * Returns the extracted information field length.
1995 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1997 return info_field[2];
2001 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2002 * @buf: Pointer to buffered vpd data
2003 * @off: The offset into the buffer at which to begin the search
2004 * @len: The length of the vpd buffer
2005 * @rdt: The Resource Data Type to search for
2007 * Returns the index where the Resource Data Type was found or
2008 * -ENOENT otherwise.
2010 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2013 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2014 * @buf: Pointer to buffered vpd data
2015 * @off: The offset into the buffer at which to begin the search
2016 * @len: The length of the buffer area, relative to off, in which to search
2017 * @kw: The keyword to search for
2019 * Returns the index where the information field keyword was found or
2020 * -ENOENT otherwise.
2022 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2023 unsigned int len, const char *kw);
2025 /* PCI <-> OF binding helpers */
2029 void pci_set_of_node(struct pci_dev *dev);
2030 void pci_release_of_node(struct pci_dev *dev);
2031 void pci_set_bus_of_node(struct pci_bus *bus);
2032 void pci_release_bus_of_node(struct pci_bus *bus);
2033 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2035 /* Arch may override this (weak) */
2036 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2038 static inline struct device_node *
2039 pci_device_to_OF_node(const struct pci_dev *pdev)
2041 return pdev ? pdev->dev.of_node : NULL;
2044 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2046 return bus ? bus->dev.of_node : NULL;
2049 #else /* CONFIG_OF */
2050 static inline void pci_set_of_node(struct pci_dev *dev) { }
2051 static inline void pci_release_of_node(struct pci_dev *dev) { }
2052 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2053 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2054 static inline struct device_node *
2055 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2056 static inline struct irq_domain *
2057 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2058 #endif /* CONFIG_OF */
2061 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2064 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2066 static inline struct irq_domain *
2067 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2071 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2073 return pdev->dev.archdata.edev;
2077 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2078 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2079 int pci_for_each_dma_alias(struct pci_dev *pdev,
2080 int (*fn)(struct pci_dev *pdev,
2081 u16 alias, void *data), void *data);
2083 /* helper functions for operation of device flag */
2084 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2086 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2088 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2090 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2092 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2094 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2098 * pci_ari_enabled - query ARI forwarding status
2101 * Returns true if ARI forwarding is enabled.
2103 static inline bool pci_ari_enabled(struct pci_bus *bus)
2105 return bus->self && bus->self->ari_enabled;
2108 /* provide the legacy pci_dma_* API */
2109 #include <linux/pci-dma-compat.h>
2111 #endif /* LINUX_PCI_H */