include/linux/mlx5/qp.h

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_QP_H
  34 #define MLX5_QP_H
  35
  36 #include <linux/mlx5/device.h>
  37 #include <linux/mlx5/driver.h>
  38
  39 #define MLX5_INVALID_LKEY       0x100
  40
  41 enum mlx5_qp_optpar {
  42         MLX5_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
  43         MLX5_QP_OPTPAR_RRE                      = 1 << 1,
  44         MLX5_QP_OPTPAR_RAE                      = 1 << 2,
  45         MLX5_QP_OPTPAR_RWE                      = 1 << 3,
  46         MLX5_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
  47         MLX5_QP_OPTPAR_Q_KEY                    = 1 << 5,
  48         MLX5_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
  49         MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
  50         MLX5_QP_OPTPAR_SRA_MAX                  = 1 << 8,
  51         MLX5_QP_OPTPAR_RRA_MAX                  = 1 << 9,
  52         MLX5_QP_OPTPAR_PM_STATE                 = 1 << 10,
  53         MLX5_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
  54         MLX5_QP_OPTPAR_RNR_RETRY                = 1 << 13,
  55         MLX5_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
  56         MLX5_QP_OPTPAR_PRI_PORT                 = 1 << 16,
  57         MLX5_QP_OPTPAR_SRQN                     = 1 << 18,
  58         MLX5_QP_OPTPAR_CQN_RCV                  = 1 << 19,
  59         MLX5_QP_OPTPAR_DC_HS                    = 1 << 20,
  60         MLX5_QP_OPTPAR_DC_KEY                   = 1 << 21,
  61 };
  62
  63 enum mlx5_qp_state {
  64         MLX5_QP_STATE_RST                       = 0,
  65         MLX5_QP_STATE_INIT                      = 1,
  66         MLX5_QP_STATE_RTR                       = 2,
  67         MLX5_QP_STATE_RTS                       = 3,
  68         MLX5_QP_STATE_SQER                      = 4,
  69         MLX5_QP_STATE_SQD                       = 5,
  70         MLX5_QP_STATE_ERR                       = 6,
  71         MLX5_QP_STATE_SQ_DRAINING               = 7,
  72         MLX5_QP_STATE_SUSPENDED                 = 9,
  73         MLX5_QP_NUM_STATE
  74 };
  75
  76 enum {
  77         MLX5_QP_ST_RC                           = 0x0,
  78         MLX5_QP_ST_UC                           = 0x1,
  79         MLX5_QP_ST_UD                           = 0x2,
  80         MLX5_QP_ST_XRC                          = 0x3,
  81         MLX5_QP_ST_MLX                          = 0x4,
  82         MLX5_QP_ST_DCI                          = 0x5,
  83         MLX5_QP_ST_DCT                          = 0x6,
  84         MLX5_QP_ST_QP0                          = 0x7,
  85         MLX5_QP_ST_QP1                          = 0x8,
  86         MLX5_QP_ST_RAW_ETHERTYPE                = 0x9,
  87         MLX5_QP_ST_RAW_IPV6                     = 0xa,
  88         MLX5_QP_ST_SNIFFER                      = 0xb,
  89         MLX5_QP_ST_SYNC_UMR                     = 0xe,
  90         MLX5_QP_ST_PTP_1588                     = 0xd,
  91         MLX5_QP_ST_REG_UMR                      = 0xc,
  92         MLX5_QP_ST_MAX
  93 };
  94
  95 enum {
  96         MLX5_QP_PM_MIGRATED                     = 0x3,
  97         MLX5_QP_PM_ARMED                        = 0x0,
  98         MLX5_QP_PM_REARM                        = 0x1
  99 };
 100
 101 enum {
 102         MLX5_NON_ZERO_RQ        = 0 << 24,
 103         MLX5_SRQ_RQ             = 1 << 24,
 104         MLX5_CRQ_RQ             = 2 << 24,
 105         MLX5_ZERO_LEN_RQ        = 3 << 24
 106 };
 107
 108 enum {
 109         /* params1 */
 110         MLX5_QP_BIT_SRE                         = 1 << 15,
 111         MLX5_QP_BIT_SWE                         = 1 << 14,
 112         MLX5_QP_BIT_SAE                         = 1 << 13,
 113         /* params2 */
 114         MLX5_QP_BIT_RRE                         = 1 << 15,
 115         MLX5_QP_BIT_RWE                         = 1 << 14,
 116         MLX5_QP_BIT_RAE                         = 1 << 13,
 117         MLX5_QP_BIT_RIC                         = 1 <<  4,
 118 };
 119
 120 enum {
 121         MLX5_WQE_CTRL_CQ_UPDATE         = 2 << 2,
 122         MLX5_WQE_CTRL_SOLICITED         = 1 << 1,
 123 };
 124
 125 enum {
 126         MLX5_SEND_WQE_BB        = 64,
 127 };
 128
 129 enum {
 130         MLX5_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
 131         MLX5_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
 132         MLX5_WQE_FMR_PERM_REMOTE_READ   = 1 << 29,
 133         MLX5_WQE_FMR_PERM_REMOTE_WRITE  = 1 << 30,
 134         MLX5_WQE_FMR_PERM_ATOMIC        = 1 << 31
 135 };
 136
 137 enum {
 138         MLX5_FENCE_MODE_NONE                    = 0 << 5,
 139         MLX5_FENCE_MODE_INITIATOR_SMALL         = 1 << 5,
 140         MLX5_FENCE_MODE_STRONG_ORDERING         = 3 << 5,
 141         MLX5_FENCE_MODE_SMALL_AND_FENCE         = 4 << 5,
 142 };
 143
 144 enum {
 145         MLX5_QP_LAT_SENSITIVE   = 1 << 28,
 146         MLX5_QP_ENABLE_SIG      = 1 << 31,
 147 };
 148
 149 enum {
 150         MLX5_RCV_DBR    = 0,
 151         MLX5_SND_DBR    = 1,
 152 };
 153
 154 struct mlx5_wqe_fmr_seg {
 155         __be32                  flags;
 156         __be32                  mem_key;
 157         __be64                  buf_list;
 158         __be64                  start_addr;
 159         __be64                  reg_len;
 160         __be32                  offset;
 161         __be32                  page_size;
 162         u32                     reserved[2];
 163 };
 164
 165 struct mlx5_wqe_ctrl_seg {
 166         __be32                  opmod_idx_opcode;
 167         __be32                  qpn_ds;
 168         u8                      signature;
 169         u8                      rsvd[2];
 170         u8                      fm_ce_se;
 171         __be32                  imm;
 172 };
 173
 174 struct mlx5_wqe_xrc_seg {
 175         __be32                  xrc_srqn;
 176         u8                      rsvd[12];
 177 };
 178
 179 struct mlx5_wqe_masked_atomic_seg {
 180         __be64                  swap_add;
 181         __be64                  compare;
 182         __be64                  swap_add_mask;
 183         __be64                  compare_mask;
 184 };
 185
 186 struct mlx5_av {
 187         union {
 188                 struct {
 189                         __be32  qkey;
 190                         __be32  reserved;
 191                 } qkey;
 192                 __be64  dc_key;
 193         } key;
 194         __be32  dqp_dct;
 195         u8      stat_rate_sl;
 196         u8      fl_mlid;
 197         __be16  rlid;
 198         u8      reserved0[10];
 199         u8      tclass;
 200         u8      hop_limit;
 201         __be32  grh_gid_fl;
 202         u8      rgid[16];
 203 };
 204
 205 struct mlx5_wqe_datagram_seg {
 206         struct mlx5_av  av;
 207 };
 208
 209 struct mlx5_wqe_raddr_seg {
 210         __be64                  raddr;
 211         __be32                  rkey;
 212         u32                     reserved;
 213 };
 214
 215 struct mlx5_wqe_atomic_seg {
 216         __be64                  swap_add;
 217         __be64                  compare;
 218 };
 219
 220 struct mlx5_wqe_data_seg {
 221         __be32                  byte_count;
 222         __be32                  lkey;
 223         __be64                  addr;
 224 };
 225
 226 struct mlx5_wqe_umr_ctrl_seg {
 227         u8              flags;
 228         u8              rsvd0[3];
 229         __be16          klm_octowords;
 230         __be16          bsf_octowords;
 231         __be64          mkey_mask;
 232         u8              rsvd1[32];
 233 };
 234
 235 struct mlx5_seg_set_psv {
 236         __be32          psv_num;
 237         __be16          syndrome;
 238         __be16          status;
 239         __be32          transient_sig;
 240         __be32          ref_tag;
 241 };
 242
 243 struct mlx5_seg_get_psv {
 244         u8              rsvd[19];
 245         u8              num_psv;
 246         __be32          l_key;
 247         __be64          va;
 248         __be32          psv_index[4];
 249 };
 250
 251 struct mlx5_seg_check_psv {
 252         u8              rsvd0[2];
 253         __be16          err_coalescing_op;
 254         u8              rsvd1[2];
 255         __be16          xport_err_op;
 256         u8              rsvd2[2];
 257         __be16          xport_err_mask;
 258         u8              rsvd3[7];
 259         u8              num_psv;
 260         __be32          l_key;
 261         __be64          va;
 262         __be32          psv_index[4];
 263 };
 264
 265 struct mlx5_rwqe_sig {
 266         u8      rsvd0[4];
 267         u8      signature;
 268         u8      rsvd1[11];
 269 };
 270
 271 struct mlx5_wqe_signature_seg {
 272         u8      rsvd0[4];
 273         u8      signature;
 274         u8      rsvd1[11];
 275 };
 276
 277 struct mlx5_wqe_inline_seg {
 278         __be32  byte_count;
 279 };
 280
 281 struct mlx5_core_qp {
 282         void (*event)           (struct mlx5_core_qp *, int);
 283         int                     qpn;
 284         atomic_t                refcount;
 285         struct completion       free;
 286         struct mlx5_rsc_debug   *dbg;
 287         int                     pid;
 288 };
 289
 290 struct mlx5_qp_path {
 291         u8                      fl;
 292         u8                      rsvd3;
 293         u8                      free_ar;
 294         u8                      pkey_index;
 295         u8                      rsvd0;
 296         u8                      grh_mlid;
 297         __be16                  rlid;
 298         u8                      ackto_lt;
 299         u8                      mgid_index;
 300         u8                      static_rate;
 301         u8                      hop_limit;
 302         __be32                  tclass_flowlabel;
 303         u8                      rgid[16];
 304         u8                      rsvd1[4];
 305         u8                      sl;
 306         u8                      port;
 307         u8                      rsvd2[6];
 308 };
 309
 310 struct mlx5_qp_context {
 311         __be32                  flags;
 312         __be32                  flags_pd;
 313         u8                      mtu_msgmax;
 314         u8                      rq_size_stride;
 315         __be16                  sq_crq_size;
 316         __be32                  qp_counter_set_usr_page;
 317         __be32                  wire_qpn;
 318         __be32                  log_pg_sz_remote_qpn;
 319         struct                  mlx5_qp_path pri_path;
 320         struct                  mlx5_qp_path alt_path;
 321         __be32                  params1;
 322         u8                      reserved2[4];
 323         __be32                  next_send_psn;
 324         __be32                  cqn_send;
 325         u8                      reserved3[8];
 326         __be32                  last_acked_psn;
 327         __be32                  ssn;
 328         __be32                  params2;
 329         __be32                  rnr_nextrecvpsn;
 330         __be32                  xrcd;
 331         __be32                  cqn_recv;
 332         __be64                  db_rec_addr;
 333         __be32                  qkey;
 334         __be32                  rq_type_srqn;
 335         __be32                  rmsn;
 336         __be16                  hw_sq_wqe_counter;
 337         __be16                  sw_sq_wqe_counter;
 338         __be16                  hw_rcyclic_byte_counter;
 339         __be16                  hw_rq_counter;
 340         __be16                  sw_rcyclic_byte_counter;
 341         __be16                  sw_rq_counter;
 342         u8                      rsvd0[5];
 343         u8                      cgs;
 344         u8                      cs_req;
 345         u8                      cs_res;
 346         __be64                  dc_access_key;
 347         u8                      rsvd1[24];
 348 };
 349
 350 struct mlx5_create_qp_mbox_in {
 351         struct mlx5_inbox_hdr   hdr;
 352         __be32                  input_qpn;
 353         u8                      rsvd0[4];
 354         __be32                  opt_param_mask;
 355         u8                      rsvd1[4];
 356         struct mlx5_qp_context  ctx;
 357         u8                      rsvd3[16];
 358         __be64                  pas[0];
 359 };
 360
 361 struct mlx5_create_qp_mbox_out {
 362         struct mlx5_outbox_hdr  hdr;
 363         __be32                  qpn;
 364         u8                      rsvd0[4];
 365 };
 366
 367 struct mlx5_destroy_qp_mbox_in {
 368         struct mlx5_inbox_hdr   hdr;
 369         __be32                  qpn;
 370         u8                      rsvd0[4];
 371 };
 372
 373 struct mlx5_destroy_qp_mbox_out {
 374         struct mlx5_outbox_hdr  hdr;
 375         u8                      rsvd0[8];
 376 };
 377
 378 struct mlx5_modify_qp_mbox_in {
 379         struct mlx5_inbox_hdr   hdr;
 380         __be32                  qpn;
 381         u8                      rsvd1[4];
 382         __be32                  optparam;
 383         u8                      rsvd0[4];
 384         struct mlx5_qp_context  ctx;
 385 };
 386
 387 struct mlx5_modify_qp_mbox_out {
 388         struct mlx5_outbox_hdr  hdr;
 389         u8                      rsvd0[8];
 390 };
 391
 392 struct mlx5_query_qp_mbox_in {
 393         struct mlx5_inbox_hdr   hdr;
 394         __be32                  qpn;
 395         u8                      rsvd[4];
 396 };
 397
 398 struct mlx5_query_qp_mbox_out {
 399         struct mlx5_outbox_hdr  hdr;
 400         u8                      rsvd1[8];
 401         __be32                  optparam;
 402         u8                      rsvd0[4];
 403         struct mlx5_qp_context  ctx;
 404         u8                      rsvd2[16];
 405         __be64                  pas[0];
 406 };
 407
 408 struct mlx5_conf_sqp_mbox_in {
 409         struct mlx5_inbox_hdr   hdr;
 410         __be32                  qpn;
 411         u8                      rsvd[3];
 412         u8                      type;
 413 };
 414
 415 struct mlx5_conf_sqp_mbox_out {
 416         struct mlx5_outbox_hdr  hdr;
 417         u8                      rsvd[8];
 418 };
 419
 420 struct mlx5_alloc_xrcd_mbox_in {
 421         struct mlx5_inbox_hdr   hdr;
 422         u8                      rsvd[8];
 423 };
 424
 425 struct mlx5_alloc_xrcd_mbox_out {
 426         struct mlx5_outbox_hdr  hdr;
 427         __be32                  xrcdn;
 428         u8                      rsvd[4];
 429 };
 430
 431 struct mlx5_dealloc_xrcd_mbox_in {
 432         struct mlx5_inbox_hdr   hdr;
 433         __be32                  xrcdn;
 434         u8                      rsvd[4];
 435 };
 436
 437 struct mlx5_dealloc_xrcd_mbox_out {
 438         struct mlx5_outbox_hdr  hdr;
 439         u8                      rsvd[8];
 440 };
 441
 442 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
 443 {
 444         return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
 445 }
 446
 447 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
 448                         struct mlx5_core_qp *qp,
 449                         struct mlx5_create_qp_mbox_in *in,
 450                         int inlen);
 451 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
 452                         enum mlx5_qp_state new_state,
 453                         struct mlx5_modify_qp_mbox_in *in, int sqd_event,
 454                         struct mlx5_core_qp *qp);
 455 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
 456                          struct mlx5_core_qp *qp);
 457 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
 458                        struct mlx5_query_qp_mbox_out *out, int outlen);
 459
 460 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
 461 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
 462 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
 463 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
 464 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
 465 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
 466
 467 #endif /* MLX5_QP_H */