include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  76 };
  77
  78 enum {
  79         MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
  80         MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_UCTX = 0x0004,
  85         MLX5_OBJ_TYPE_UMEM = 0x0005,
  86 };
  87
  88 enum {
  89         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  90         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  91         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  92         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  93         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  94         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  95         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  96         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  97         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  98         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  99         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 100         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 101         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 102         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 103         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 104         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 105         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 106         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 107         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 108         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 109         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 110         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 111         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 112         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 113         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 114         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 115         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 116         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 117         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 118         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 119         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 120         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 121         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 122         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 123         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 124         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 125         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 126         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 127         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 128         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 129         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 130         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 131         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 132         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 133         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 134         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 135         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 136         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 137         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 138         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 139         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 140         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 141         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 142         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 143         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 144         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 145         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 146         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 147         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 148         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 149         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 150         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 151         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 152         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 153         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 154         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 155         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 156         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 157         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 158         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 159         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 160         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 161         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 162         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 163         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 164         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 165         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 166         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 167         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 168         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 169         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 170         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 171         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 172         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 173         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 174         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 175         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 176         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 177         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 178         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 179         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 180         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 181         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 182         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 183         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 184         MLX5_CMD_OP_NOP                           = 0x80d,
 185         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 186         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 187         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 188         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 189         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 190         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 191         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 192         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 193         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 194         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 195         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 196         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 197         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 198         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 199         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 200         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 201         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 202         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 203         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 204         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 205         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 206         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 207         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 208         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 209         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 210         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 211         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 212         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 213         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 214         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 215         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 216         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 217         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 218         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 219         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 220         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 221         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 222         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 223         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 224         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 225         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 226         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 227         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 228         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 229         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 230         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 231         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 232         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 233         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 234         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 235         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 236         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 237         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 238         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 239         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 240         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 241         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 242         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 243         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 244         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 245         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 246         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 247         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 248         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 249         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 250         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 251         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 252         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 253         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 254         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 255         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 256         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 257         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 258         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 259         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 260         MLX5_CMD_OP_MAX
 261 };
 262
 263 struct mlx5_ifc_flow_table_fields_supported_bits {
 264         u8         outer_dmac[0x1];
 265         u8         outer_smac[0x1];
 266         u8         outer_ether_type[0x1];
 267         u8         outer_ip_version[0x1];
 268         u8         outer_first_prio[0x1];
 269         u8         outer_first_cfi[0x1];
 270         u8         outer_first_vid[0x1];
 271         u8         outer_ipv4_ttl[0x1];
 272         u8         outer_second_prio[0x1];
 273         u8         outer_second_cfi[0x1];
 274         u8         outer_second_vid[0x1];
 275         u8         reserved_at_b[0x1];
 276         u8         outer_sip[0x1];
 277         u8         outer_dip[0x1];
 278         u8         outer_frag[0x1];
 279         u8         outer_ip_protocol[0x1];
 280         u8         outer_ip_ecn[0x1];
 281         u8         outer_ip_dscp[0x1];
 282         u8         outer_udp_sport[0x1];
 283         u8         outer_udp_dport[0x1];
 284         u8         outer_tcp_sport[0x1];
 285         u8         outer_tcp_dport[0x1];
 286         u8         outer_tcp_flags[0x1];
 287         u8         outer_gre_protocol[0x1];
 288         u8         outer_gre_key[0x1];
 289         u8         outer_vxlan_vni[0x1];
 290         u8         reserved_at_1a[0x5];
 291         u8         source_eswitch_port[0x1];
 292
 293         u8         inner_dmac[0x1];
 294         u8         inner_smac[0x1];
 295         u8         inner_ether_type[0x1];
 296         u8         inner_ip_version[0x1];
 297         u8         inner_first_prio[0x1];
 298         u8         inner_first_cfi[0x1];
 299         u8         inner_first_vid[0x1];
 300         u8         reserved_at_27[0x1];
 301         u8         inner_second_prio[0x1];
 302         u8         inner_second_cfi[0x1];
 303         u8         inner_second_vid[0x1];
 304         u8         reserved_at_2b[0x1];
 305         u8         inner_sip[0x1];
 306         u8         inner_dip[0x1];
 307         u8         inner_frag[0x1];
 308         u8         inner_ip_protocol[0x1];
 309         u8         inner_ip_ecn[0x1];
 310         u8         inner_ip_dscp[0x1];
 311         u8         inner_udp_sport[0x1];
 312         u8         inner_udp_dport[0x1];
 313         u8         inner_tcp_sport[0x1];
 314         u8         inner_tcp_dport[0x1];
 315         u8         inner_tcp_flags[0x1];
 316         u8         reserved_at_37[0x9];
 317
 318         u8         reserved_at_40[0x5];
 319         u8         outer_first_mpls_over_udp[0x4];
 320         u8         outer_first_mpls_over_gre[0x4];
 321         u8         inner_first_mpls[0x4];
 322         u8         outer_first_mpls[0x4];
 323         u8         reserved_at_55[0x2];
 324         u8         outer_esp_spi[0x1];
 325         u8         reserved_at_58[0x2];
 326         u8         bth_dst_qp[0x1];
 327
 328         u8         reserved_at_5b[0x25];
 329 };
 330
 331 struct mlx5_ifc_flow_table_prop_layout_bits {
 332         u8         ft_support[0x1];
 333         u8         reserved_at_1[0x1];
 334         u8         flow_counter[0x1];
 335         u8         flow_modify_en[0x1];
 336         u8         modify_root[0x1];
 337         u8         identified_miss_table_mode[0x1];
 338         u8         flow_table_modify[0x1];
 339         u8         reformat[0x1];
 340         u8         decap[0x1];
 341         u8         reserved_at_9[0x1];
 342         u8         pop_vlan[0x1];
 343         u8         push_vlan[0x1];
 344         u8         reserved_at_c[0x1];
 345         u8         pop_vlan_2[0x1];
 346         u8         push_vlan_2[0x1];
 347         u8         reformat_and_vlan_action[0x1];
 348         u8         reserved_at_10[0x2];
 349         u8         reformat_l3_tunnel_to_l2[0x1];
 350         u8         reformat_l2_to_l3_tunnel[0x1];
 351         u8         reformat_and_modify_action[0x1];
 352         u8         reserved_at_14[0xb];
 353         u8         reserved_at_20[0x2];
 354         u8         log_max_ft_size[0x6];
 355         u8         log_max_modify_header_context[0x8];
 356         u8         max_modify_header_actions[0x8];
 357         u8         max_ft_level[0x8];
 358
 359         u8         reserved_at_40[0x20];
 360
 361         u8         reserved_at_60[0x18];
 362         u8         log_max_ft_num[0x8];
 363
 364         u8         reserved_at_80[0x18];
 365         u8         log_max_destination[0x8];
 366
 367         u8         log_max_flow_counter[0x8];
 368         u8         reserved_at_a8[0x10];
 369         u8         log_max_flow[0x8];
 370
 371         u8         reserved_at_c0[0x40];
 372
 373         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 374
 375         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 376 };
 377
 378 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 379         u8         send[0x1];
 380         u8         receive[0x1];
 381         u8         write[0x1];
 382         u8         read[0x1];
 383         u8         atomic[0x1];
 384         u8         srq_receive[0x1];
 385         u8         reserved_at_6[0x1a];
 386 };
 387
 388 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 389         u8         smac_47_16[0x20];
 390
 391         u8         smac_15_0[0x10];
 392         u8         ethertype[0x10];
 393
 394         u8         dmac_47_16[0x20];
 395
 396         u8         dmac_15_0[0x10];
 397         u8         first_prio[0x3];
 398         u8         first_cfi[0x1];
 399         u8         first_vid[0xc];
 400
 401         u8         ip_protocol[0x8];
 402         u8         ip_dscp[0x6];
 403         u8         ip_ecn[0x2];
 404         u8         cvlan_tag[0x1];
 405         u8         svlan_tag[0x1];
 406         u8         frag[0x1];
 407         u8         ip_version[0x4];
 408         u8         tcp_flags[0x9];
 409
 410         u8         tcp_sport[0x10];
 411         u8         tcp_dport[0x10];
 412
 413         u8         reserved_at_c0[0x18];
 414         u8         ttl_hoplimit[0x8];
 415
 416         u8         udp_sport[0x10];
 417         u8         udp_dport[0x10];
 418
 419         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 420
 421         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 422 };
 423
 424 struct mlx5_ifc_fte_match_set_misc_bits {
 425         u8         reserved_at_0[0x8];
 426         u8         source_sqn[0x18];
 427
 428         u8         source_eswitch_owner_vhca_id[0x10];
 429         u8         source_port[0x10];
 430
 431         u8         outer_second_prio[0x3];
 432         u8         outer_second_cfi[0x1];
 433         u8         outer_second_vid[0xc];
 434         u8         inner_second_prio[0x3];
 435         u8         inner_second_cfi[0x1];
 436         u8         inner_second_vid[0xc];
 437
 438         u8         outer_second_cvlan_tag[0x1];
 439         u8         inner_second_cvlan_tag[0x1];
 440         u8         outer_second_svlan_tag[0x1];
 441         u8         inner_second_svlan_tag[0x1];
 442         u8         reserved_at_64[0xc];
 443         u8         gre_protocol[0x10];
 444
 445         u8         gre_key_h[0x18];
 446         u8         gre_key_l[0x8];
 447
 448         u8         vxlan_vni[0x18];
 449         u8         reserved_at_b8[0x8];
 450
 451         u8         reserved_at_c0[0x20];
 452
 453         u8         reserved_at_e0[0xc];
 454         u8         outer_ipv6_flow_label[0x14];
 455
 456         u8         reserved_at_100[0xc];
 457         u8         inner_ipv6_flow_label[0x14];
 458
 459         u8         reserved_at_120[0x28];
 460         u8         bth_dst_qp[0x18];
 461         u8         reserved_at_160[0x20];
 462         u8         outer_esp_spi[0x20];
 463         u8         reserved_at_1a0[0x60];
 464 };
 465
 466 struct mlx5_ifc_fte_match_mpls_bits {
 467         u8         mpls_label[0x14];
 468         u8         mpls_exp[0x3];
 469         u8         mpls_s_bos[0x1];
 470         u8         mpls_ttl[0x8];
 471 };
 472
 473 struct mlx5_ifc_fte_match_set_misc2_bits {
 474         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 475
 476         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 477
 478         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 479
 480         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 481
 482         u8         reserved_at_80[0x100];
 483
 484         u8         metadata_reg_a[0x20];
 485
 486         u8         reserved_at_1a0[0x60];
 487 };
 488
 489 struct mlx5_ifc_cmd_pas_bits {
 490         u8         pa_h[0x20];
 491
 492         u8         pa_l[0x14];
 493         u8         reserved_at_34[0xc];
 494 };
 495
 496 struct mlx5_ifc_uint64_bits {
 497         u8         hi[0x20];
 498
 499         u8         lo[0x20];
 500 };
 501
 502 enum {
 503         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 504         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 505         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 506         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 507         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 508         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 509         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 510         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 511         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 512         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 513 };
 514
 515 struct mlx5_ifc_ads_bits {
 516         u8         fl[0x1];
 517         u8         free_ar[0x1];
 518         u8         reserved_at_2[0xe];
 519         u8         pkey_index[0x10];
 520
 521         u8         reserved_at_20[0x8];
 522         u8         grh[0x1];
 523         u8         mlid[0x7];
 524         u8         rlid[0x10];
 525
 526         u8         ack_timeout[0x5];
 527         u8         reserved_at_45[0x3];
 528         u8         src_addr_index[0x8];
 529         u8         reserved_at_50[0x4];
 530         u8         stat_rate[0x4];
 531         u8         hop_limit[0x8];
 532
 533         u8         reserved_at_60[0x4];
 534         u8         tclass[0x8];
 535         u8         flow_label[0x14];
 536
 537         u8         rgid_rip[16][0x8];
 538
 539         u8         reserved_at_100[0x4];
 540         u8         f_dscp[0x1];
 541         u8         f_ecn[0x1];
 542         u8         reserved_at_106[0x1];
 543         u8         f_eth_prio[0x1];
 544         u8         ecn[0x2];
 545         u8         dscp[0x6];
 546         u8         udp_sport[0x10];
 547
 548         u8         dei_cfi[0x1];
 549         u8         eth_prio[0x3];
 550         u8         sl[0x4];
 551         u8         vhca_port_num[0x8];
 552         u8         rmac_47_32[0x10];
 553
 554         u8         rmac_31_0[0x20];
 555 };
 556
 557 struct mlx5_ifc_flow_table_nic_cap_bits {
 558         u8         nic_rx_multi_path_tirs[0x1];
 559         u8         nic_rx_multi_path_tirs_fts[0x1];
 560         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 561         u8         reserved_at_3[0x1d];
 562         u8         encap_general_header[0x1];
 563         u8         reserved_at_21[0xa];
 564         u8         log_max_packet_reformat_context[0x5];
 565         u8         reserved_at_30[0x6];
 566         u8         max_encap_header_size[0xa];
 567         u8         reserved_at_40[0x1c0];
 568
 569         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 570
 571         u8         reserved_at_400[0x200];
 572
 573         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 574
 575         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 576
 577         u8         reserved_at_a00[0x200];
 578
 579         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 580
 581         u8         reserved_at_e00[0x7200];
 582 };
 583
 584 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 585         u8      reserved_at_0[0x1c];
 586         u8      fdb_multi_path_to_table[0x1];
 587         u8      reserved_at_1d[0x1e3];
 588
 589         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 590
 591         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 592
 593         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 594
 595         u8      reserved_at_800[0x7800];
 596 };
 597
 598 struct mlx5_ifc_e_switch_cap_bits {
 599         u8         vport_svlan_strip[0x1];
 600         u8         vport_cvlan_strip[0x1];
 601         u8         vport_svlan_insert[0x1];
 602         u8         vport_cvlan_insert_if_not_exist[0x1];
 603         u8         vport_cvlan_insert_overwrite[0x1];
 604         u8         reserved_at_5[0x18];
 605         u8         merged_eswitch[0x1];
 606         u8         nic_vport_node_guid_modify[0x1];
 607         u8         nic_vport_port_guid_modify[0x1];
 608
 609         u8         vxlan_encap_decap[0x1];
 610         u8         nvgre_encap_decap[0x1];
 611         u8         reserved_at_22[0x9];
 612         u8         log_max_packet_reformat_context[0x5];
 613         u8         reserved_2b[0x6];
 614         u8         max_encap_header_size[0xa];
 615
 616         u8         reserved_40[0x7c0];
 617
 618 };
 619
 620 struct mlx5_ifc_qos_cap_bits {
 621         u8         packet_pacing[0x1];
 622         u8         esw_scheduling[0x1];
 623         u8         esw_bw_share[0x1];
 624         u8         esw_rate_limit[0x1];
 625         u8         reserved_at_4[0x1];
 626         u8         packet_pacing_burst_bound[0x1];
 627         u8         packet_pacing_typical_size[0x1];
 628         u8         reserved_at_7[0x19];
 629
 630         u8         reserved_at_20[0x20];
 631
 632         u8         packet_pacing_max_rate[0x20];
 633
 634         u8         packet_pacing_min_rate[0x20];
 635
 636         u8         reserved_at_80[0x10];
 637         u8         packet_pacing_rate_table_size[0x10];
 638
 639         u8         esw_element_type[0x10];
 640         u8         esw_tsar_type[0x10];
 641
 642         u8         reserved_at_c0[0x10];
 643         u8         max_qos_para_vport[0x10];
 644
 645         u8         max_tsar_bw_share[0x20];
 646
 647         u8         reserved_at_100[0x700];
 648 };
 649
 650 struct mlx5_ifc_debug_cap_bits {
 651         u8         reserved_at_0[0x20];
 652
 653         u8         reserved_at_20[0x2];
 654         u8         stall_detect[0x1];
 655         u8         reserved_at_23[0x1d];
 656
 657         u8         reserved_at_40[0x7c0];
 658 };
 659
 660 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 661         u8         csum_cap[0x1];
 662         u8         vlan_cap[0x1];
 663         u8         lro_cap[0x1];
 664         u8         lro_psh_flag[0x1];
 665         u8         lro_time_stamp[0x1];
 666         u8         reserved_at_5[0x2];
 667         u8         wqe_vlan_insert[0x1];
 668         u8         self_lb_en_modifiable[0x1];
 669         u8         reserved_at_9[0x2];
 670         u8         max_lso_cap[0x5];
 671         u8         multi_pkt_send_wqe[0x2];
 672         u8         wqe_inline_mode[0x2];
 673         u8         rss_ind_tbl_cap[0x4];
 674         u8         reg_umr_sq[0x1];
 675         u8         scatter_fcs[0x1];
 676         u8         enhanced_multi_pkt_send_wqe[0x1];
 677         u8         tunnel_lso_const_out_ip_id[0x1];
 678         u8         reserved_at_1c[0x2];
 679         u8         tunnel_stateless_gre[0x1];
 680         u8         tunnel_stateless_vxlan[0x1];
 681
 682         u8         swp[0x1];
 683         u8         swp_csum[0x1];
 684         u8         swp_lso[0x1];
 685         u8         reserved_at_23[0xd];
 686         u8         max_vxlan_udp_ports[0x8];
 687         u8         reserved_at_38[0x6];
 688         u8         max_geneve_opt_len[0x1];
 689         u8         tunnel_stateless_geneve_rx[0x1];
 690
 691         u8         reserved_at_40[0x10];
 692         u8         lro_min_mss_size[0x10];
 693
 694         u8         reserved_at_60[0x120];
 695
 696         u8         lro_timer_supported_periods[4][0x20];
 697
 698         u8         reserved_at_200[0x600];
 699 };
 700
 701 struct mlx5_ifc_roce_cap_bits {
 702         u8         roce_apm[0x1];
 703         u8         reserved_at_1[0x1f];
 704
 705         u8         reserved_at_20[0x60];
 706
 707         u8         reserved_at_80[0xc];
 708         u8         l3_type[0x4];
 709         u8         reserved_at_90[0x8];
 710         u8         roce_version[0x8];
 711
 712         u8         reserved_at_a0[0x10];
 713         u8         r_roce_dest_udp_port[0x10];
 714
 715         u8         r_roce_max_src_udp_port[0x10];
 716         u8         r_roce_min_src_udp_port[0x10];
 717
 718         u8         reserved_at_e0[0x10];
 719         u8         roce_address_table_size[0x10];
 720
 721         u8         reserved_at_100[0x700];
 722 };
 723
 724 struct mlx5_ifc_device_mem_cap_bits {
 725         u8         memic[0x1];
 726         u8         reserved_at_1[0x1f];
 727
 728         u8         reserved_at_20[0xb];
 729         u8         log_min_memic_alloc_size[0x5];
 730         u8         reserved_at_30[0x8];
 731         u8         log_max_memic_addr_alignment[0x8];
 732
 733         u8         memic_bar_start_addr[0x40];
 734
 735         u8         memic_bar_size[0x20];
 736
 737         u8         max_memic_size[0x20];
 738
 739         u8         reserved_at_c0[0x740];
 740 };
 741
 742 enum {
 743         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 744         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 745         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 746         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 747         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 748         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 749         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 750         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 751         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 752 };
 753
 754 enum {
 755         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 756         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 757         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 758         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 759         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 760         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 761         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 762         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 763         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 764 };
 765
 766 struct mlx5_ifc_atomic_caps_bits {
 767         u8         reserved_at_0[0x40];
 768
 769         u8         atomic_req_8B_endianness_mode[0x2];
 770         u8         reserved_at_42[0x4];
 771         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 772
 773         u8         reserved_at_47[0x19];
 774
 775         u8         reserved_at_60[0x20];
 776
 777         u8         reserved_at_80[0x10];
 778         u8         atomic_operations[0x10];
 779
 780         u8         reserved_at_a0[0x10];
 781         u8         atomic_size_qp[0x10];
 782
 783         u8         reserved_at_c0[0x10];
 784         u8         atomic_size_dc[0x10];
 785
 786         u8         reserved_at_e0[0x720];
 787 };
 788
 789 struct mlx5_ifc_odp_cap_bits {
 790         u8         reserved_at_0[0x40];
 791
 792         u8         sig[0x1];
 793         u8         reserved_at_41[0x1f];
 794
 795         u8         reserved_at_60[0x20];
 796
 797         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 798
 799         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 800
 801         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 802
 803         u8         reserved_at_e0[0x720];
 804 };
 805
 806 struct mlx5_ifc_calc_op {
 807         u8        reserved_at_0[0x10];
 808         u8        reserved_at_10[0x9];
 809         u8        op_swap_endianness[0x1];
 810         u8        op_min[0x1];
 811         u8        op_xor[0x1];
 812         u8        op_or[0x1];
 813         u8        op_and[0x1];
 814         u8        op_max[0x1];
 815         u8        op_add[0x1];
 816 };
 817
 818 struct mlx5_ifc_vector_calc_cap_bits {
 819         u8         calc_matrix[0x1];
 820         u8         reserved_at_1[0x1f];
 821         u8         reserved_at_20[0x8];
 822         u8         max_vec_count[0x8];
 823         u8         reserved_at_30[0xd];
 824         u8         max_chunk_size[0x3];
 825         struct mlx5_ifc_calc_op calc0;
 826         struct mlx5_ifc_calc_op calc1;
 827         struct mlx5_ifc_calc_op calc2;
 828         struct mlx5_ifc_calc_op calc3;
 829
 830         u8         reserved_at_e0[0x720];
 831 };
 832
 833 enum {
 834         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 835         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 836         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 837         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 838 };
 839
 840 enum {
 841         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 842         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 843 };
 844
 845 enum {
 846         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 847         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 848         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 849         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 850         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 851 };
 852
 853 enum {
 854         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 855         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 856         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 857         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 858         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 859         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 860 };
 861
 862 enum {
 863         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 864         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 865 };
 866
 867 enum {
 868         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 869         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 870         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 871 };
 872
 873 enum {
 874         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 875         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 876 };
 877
 878 enum {
 879         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 880         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 881         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 882 };
 883
 884 struct mlx5_ifc_cmd_hca_cap_bits {
 885         u8         reserved_at_0[0x30];
 886         u8         vhca_id[0x10];
 887
 888         u8         reserved_at_40[0x40];
 889
 890         u8         log_max_srq_sz[0x8];
 891         u8         log_max_qp_sz[0x8];
 892         u8         reserved_at_90[0xb];
 893         u8         log_max_qp[0x5];
 894
 895         u8         reserved_at_a0[0xb];
 896         u8         log_max_srq[0x5];
 897         u8         reserved_at_b0[0x10];
 898
 899         u8         reserved_at_c0[0x8];
 900         u8         log_max_cq_sz[0x8];
 901         u8         reserved_at_d0[0xb];
 902         u8         log_max_cq[0x5];
 903
 904         u8         log_max_eq_sz[0x8];
 905         u8         reserved_at_e8[0x2];
 906         u8         log_max_mkey[0x6];
 907         u8         reserved_at_f0[0x8];
 908         u8         dump_fill_mkey[0x1];
 909         u8         reserved_at_f9[0x3];
 910         u8         log_max_eq[0x4];
 911
 912         u8         max_indirection[0x8];
 913         u8         fixed_buffer_size[0x1];
 914         u8         log_max_mrw_sz[0x7];
 915         u8         force_teardown[0x1];
 916         u8         reserved_at_111[0x1];
 917         u8         log_max_bsf_list_size[0x6];
 918         u8         umr_extended_translation_offset[0x1];
 919         u8         null_mkey[0x1];
 920         u8         log_max_klm_list_size[0x6];
 921
 922         u8         reserved_at_120[0xa];
 923         u8         log_max_ra_req_dc[0x6];
 924         u8         reserved_at_130[0xa];
 925         u8         log_max_ra_res_dc[0x6];
 926
 927         u8         reserved_at_140[0xa];
 928         u8         log_max_ra_req_qp[0x6];
 929         u8         reserved_at_150[0xa];
 930         u8         log_max_ra_res_qp[0x6];
 931
 932         u8         end_pad[0x1];
 933         u8         cc_query_allowed[0x1];
 934         u8         cc_modify_allowed[0x1];
 935         u8         start_pad[0x1];
 936         u8         cache_line_128byte[0x1];
 937         u8         reserved_at_165[0xa];
 938         u8         qcam_reg[0x1];
 939         u8         gid_table_size[0x10];
 940
 941         u8         out_of_seq_cnt[0x1];
 942         u8         vport_counters[0x1];
 943         u8         retransmission_q_counters[0x1];
 944         u8         debug[0x1];
 945         u8         modify_rq_counter_set_id[0x1];
 946         u8         rq_delay_drop[0x1];
 947         u8         max_qp_cnt[0xa];
 948         u8         pkey_table_size[0x10];
 949
 950         u8         vport_group_manager[0x1];
 951         u8         vhca_group_manager[0x1];
 952         u8         ib_virt[0x1];
 953         u8         eth_virt[0x1];
 954         u8         vnic_env_queue_counters[0x1];
 955         u8         ets[0x1];
 956         u8         nic_flow_table[0x1];
 957         u8         eswitch_manager[0x1];
 958         u8         device_memory[0x1];
 959         u8         mcam_reg[0x1];
 960         u8         pcam_reg[0x1];
 961         u8         local_ca_ack_delay[0x5];
 962         u8         port_module_event[0x1];
 963         u8         enhanced_error_q_counters[0x1];
 964         u8         ports_check[0x1];
 965         u8         reserved_at_1b3[0x1];
 966         u8         disable_link_up[0x1];
 967         u8         beacon_led[0x1];
 968         u8         port_type[0x2];
 969         u8         num_ports[0x8];
 970
 971         u8         reserved_at_1c0[0x1];
 972         u8         pps[0x1];
 973         u8         pps_modify[0x1];
 974         u8         log_max_msg[0x5];
 975         u8         reserved_at_1c8[0x4];
 976         u8         max_tc[0x4];
 977         u8         temp_warn_event[0x1];
 978         u8         dcbx[0x1];
 979         u8         general_notification_event[0x1];
 980         u8         reserved_at_1d3[0x2];
 981         u8         fpga[0x1];
 982         u8         rol_s[0x1];
 983         u8         rol_g[0x1];
 984         u8         reserved_at_1d8[0x1];
 985         u8         wol_s[0x1];
 986         u8         wol_g[0x1];
 987         u8         wol_a[0x1];
 988         u8         wol_b[0x1];
 989         u8         wol_m[0x1];
 990         u8         wol_u[0x1];
 991         u8         wol_p[0x1];
 992
 993         u8         stat_rate_support[0x10];
 994         u8         reserved_at_1f0[0xc];
 995         u8         cqe_version[0x4];
 996
 997         u8         compact_address_vector[0x1];
 998         u8         striding_rq[0x1];
 999         u8         reserved_at_202[0x1];
1000         u8         ipoib_enhanced_offloads[0x1];
1001         u8         ipoib_basic_offloads[0x1];
1002         u8         reserved_at_205[0x1];
1003         u8         repeated_block_disabled[0x1];
1004         u8         umr_modify_entity_size_disabled[0x1];
1005         u8         umr_modify_atomic_disabled[0x1];
1006         u8         umr_indirect_mkey_disabled[0x1];
1007         u8         umr_fence[0x2];
1008         u8         reserved_at_20c[0x3];
1009         u8         drain_sigerr[0x1];
1010         u8         cmdif_checksum[0x2];
1011         u8         sigerr_cqe[0x1];
1012         u8         reserved_at_213[0x1];
1013         u8         wq_signature[0x1];
1014         u8         sctr_data_cqe[0x1];
1015         u8         reserved_at_216[0x1];
1016         u8         sho[0x1];
1017         u8         tph[0x1];
1018         u8         rf[0x1];
1019         u8         dct[0x1];
1020         u8         qos[0x1];
1021         u8         eth_net_offloads[0x1];
1022         u8         roce[0x1];
1023         u8         atomic[0x1];
1024         u8         reserved_at_21f[0x1];
1025
1026         u8         cq_oi[0x1];
1027         u8         cq_resize[0x1];
1028         u8         cq_moderation[0x1];
1029         u8         reserved_at_223[0x3];
1030         u8         cq_eq_remap[0x1];
1031         u8         pg[0x1];
1032         u8         block_lb_mc[0x1];
1033         u8         reserved_at_229[0x1];
1034         u8         scqe_break_moderation[0x1];
1035         u8         cq_period_start_from_cqe[0x1];
1036         u8         cd[0x1];
1037         u8         reserved_at_22d[0x1];
1038         u8         apm[0x1];
1039         u8         vector_calc[0x1];
1040         u8         umr_ptr_rlky[0x1];
1041         u8         imaicl[0x1];
1042         u8         reserved_at_232[0x4];
1043         u8         qkv[0x1];
1044         u8         pkv[0x1];
1045         u8         set_deth_sqpn[0x1];
1046         u8         reserved_at_239[0x3];
1047         u8         xrc[0x1];
1048         u8         ud[0x1];
1049         u8         uc[0x1];
1050         u8         rc[0x1];
1051
1052         u8         uar_4k[0x1];
1053         u8         reserved_at_241[0x9];
1054         u8         uar_sz[0x6];
1055         u8         reserved_at_250[0x8];
1056         u8         log_pg_sz[0x8];
1057
1058         u8         bf[0x1];
1059         u8         driver_version[0x1];
1060         u8         pad_tx_eth_packet[0x1];
1061         u8         reserved_at_263[0x8];
1062         u8         log_bf_reg_size[0x5];
1063
1064         u8         reserved_at_270[0xb];
1065         u8         lag_master[0x1];
1066         u8         num_lag_ports[0x4];
1067
1068         u8         reserved_at_280[0x10];
1069         u8         max_wqe_sz_sq[0x10];
1070
1071         u8         reserved_at_2a0[0x10];
1072         u8         max_wqe_sz_rq[0x10];
1073
1074         u8         max_flow_counter_31_16[0x10];
1075         u8         max_wqe_sz_sq_dc[0x10];
1076
1077         u8         reserved_at_2e0[0x7];
1078         u8         max_qp_mcg[0x19];
1079
1080         u8         reserved_at_300[0x18];
1081         u8         log_max_mcg[0x8];
1082
1083         u8         reserved_at_320[0x3];
1084         u8         log_max_transport_domain[0x5];
1085         u8         reserved_at_328[0x3];
1086         u8         log_max_pd[0x5];
1087         u8         reserved_at_330[0xb];
1088         u8         log_max_xrcd[0x5];
1089
1090         u8         nic_receive_steering_discard[0x1];
1091         u8         receive_discard_vport_down[0x1];
1092         u8         transmit_discard_vport_down[0x1];
1093         u8         reserved_at_343[0x5];
1094         u8         log_max_flow_counter_bulk[0x8];
1095         u8         max_flow_counter_15_0[0x10];
1096
1097
1098         u8         reserved_at_360[0x3];
1099         u8         log_max_rq[0x5];
1100         u8         reserved_at_368[0x3];
1101         u8         log_max_sq[0x5];
1102         u8         reserved_at_370[0x3];
1103         u8         log_max_tir[0x5];
1104         u8         reserved_at_378[0x3];
1105         u8         log_max_tis[0x5];
1106
1107         u8         basic_cyclic_rcv_wqe[0x1];
1108         u8         reserved_at_381[0x2];
1109         u8         log_max_rmp[0x5];
1110         u8         reserved_at_388[0x3];
1111         u8         log_max_rqt[0x5];
1112         u8         reserved_at_390[0x3];
1113         u8         log_max_rqt_size[0x5];
1114         u8         reserved_at_398[0x3];
1115         u8         log_max_tis_per_sq[0x5];
1116
1117         u8         ext_stride_num_range[0x1];
1118         u8         reserved_at_3a1[0x2];
1119         u8         log_max_stride_sz_rq[0x5];
1120         u8         reserved_at_3a8[0x3];
1121         u8         log_min_stride_sz_rq[0x5];
1122         u8         reserved_at_3b0[0x3];
1123         u8         log_max_stride_sz_sq[0x5];
1124         u8         reserved_at_3b8[0x3];
1125         u8         log_min_stride_sz_sq[0x5];
1126
1127         u8         hairpin[0x1];
1128         u8         reserved_at_3c1[0x2];
1129         u8         log_max_hairpin_queues[0x5];
1130         u8         reserved_at_3c8[0x3];
1131         u8         log_max_hairpin_wq_data_sz[0x5];
1132         u8         reserved_at_3d0[0x3];
1133         u8         log_max_hairpin_num_packets[0x5];
1134         u8         reserved_at_3d8[0x3];
1135         u8         log_max_wq_sz[0x5];
1136
1137         u8         nic_vport_change_event[0x1];
1138         u8         disable_local_lb_uc[0x1];
1139         u8         disable_local_lb_mc[0x1];
1140         u8         log_min_hairpin_wq_data_sz[0x5];
1141         u8         reserved_at_3e8[0x3];
1142         u8         log_max_vlan_list[0x5];
1143         u8         reserved_at_3f0[0x3];
1144         u8         log_max_current_mc_list[0x5];
1145         u8         reserved_at_3f8[0x3];
1146         u8         log_max_current_uc_list[0x5];
1147
1148         u8         general_obj_types[0x40];
1149
1150         u8         reserved_at_440[0x20];
1151
1152         u8         reserved_at_460[0x10];
1153         u8         max_num_eqs[0x10];
1154
1155         u8         reserved_at_480[0x3];
1156         u8         log_max_l2_table[0x5];
1157         u8         reserved_at_488[0x8];
1158         u8         log_uar_page_sz[0x10];
1159
1160         u8         reserved_at_4a0[0x20];
1161         u8         device_frequency_mhz[0x20];
1162         u8         device_frequency_khz[0x20];
1163
1164         u8         reserved_at_500[0x20];
1165         u8         num_of_uars_per_page[0x20];
1166
1167         u8         flex_parser_protocols[0x20];
1168         u8         reserved_at_560[0x20];
1169
1170         u8         reserved_at_580[0x3c];
1171         u8         mini_cqe_resp_stride_index[0x1];
1172         u8         cqe_128_always[0x1];
1173         u8         cqe_compression_128[0x1];
1174         u8         cqe_compression[0x1];
1175
1176         u8         cqe_compression_timeout[0x10];
1177         u8         cqe_compression_max_num[0x10];
1178
1179         u8         reserved_at_5e0[0x10];
1180         u8         tag_matching[0x1];
1181         u8         rndv_offload_rc[0x1];
1182         u8         rndv_offload_dc[0x1];
1183         u8         log_tag_matching_list_sz[0x5];
1184         u8         reserved_at_5f8[0x3];
1185         u8         log_max_xrq[0x5];
1186
1187         u8         affiliate_nic_vport_criteria[0x8];
1188         u8         native_port_num[0x8];
1189         u8         num_vhca_ports[0x8];
1190         u8         reserved_at_618[0x6];
1191         u8         sw_owner_id[0x1];
1192         u8         reserved_at_61f[0x1e1];
1193 };
1194
1195 enum mlx5_flow_destination_type {
1196         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1197         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1198         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1199
1200         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1201         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1202         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1203 };
1204
1205 struct mlx5_ifc_dest_format_struct_bits {
1206         u8         destination_type[0x8];
1207         u8         destination_id[0x18];
1208         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1209         u8         reserved_at_21[0xf];
1210         u8         destination_eswitch_owner_vhca_id[0x10];
1211 };
1212
1213 struct mlx5_ifc_flow_counter_list_bits {
1214         u8         flow_counter_id[0x20];
1215
1216         u8         reserved_at_20[0x20];
1217 };
1218
1219 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1220         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1221         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1222         u8         reserved_at_0[0x40];
1223 };
1224
1225 struct mlx5_ifc_fte_match_param_bits {
1226         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1227
1228         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1229
1230         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1231
1232         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1233
1234         u8         reserved_at_800[0x800];
1235 };
1236
1237 enum {
1238         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1239         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1240         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1241         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1242         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1243 };
1244
1245 struct mlx5_ifc_rx_hash_field_select_bits {
1246         u8         l3_prot_type[0x1];
1247         u8         l4_prot_type[0x1];
1248         u8         selected_fields[0x1e];
1249 };
1250
1251 enum {
1252         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1253         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1254 };
1255
1256 enum {
1257         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1258         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1259 };
1260
1261 struct mlx5_ifc_wq_bits {
1262         u8         wq_type[0x4];
1263         u8         wq_signature[0x1];
1264         u8         end_padding_mode[0x2];
1265         u8         cd_slave[0x1];
1266         u8         reserved_at_8[0x18];
1267
1268         u8         hds_skip_first_sge[0x1];
1269         u8         log2_hds_buf_size[0x3];
1270         u8         reserved_at_24[0x7];
1271         u8         page_offset[0x5];
1272         u8         lwm[0x10];
1273
1274         u8         reserved_at_40[0x8];
1275         u8         pd[0x18];
1276
1277         u8         reserved_at_60[0x8];
1278         u8         uar_page[0x18];
1279
1280         u8         dbr_addr[0x40];
1281
1282         u8         hw_counter[0x20];
1283
1284         u8         sw_counter[0x20];
1285
1286         u8         reserved_at_100[0xc];
1287         u8         log_wq_stride[0x4];
1288         u8         reserved_at_110[0x3];
1289         u8         log_wq_pg_sz[0x5];
1290         u8         reserved_at_118[0x3];
1291         u8         log_wq_sz[0x5];
1292
1293         u8         dbr_umem_valid[0x1];
1294         u8         wq_umem_valid[0x1];
1295         u8         reserved_at_122[0x1];
1296         u8         log_hairpin_num_packets[0x5];
1297         u8         reserved_at_128[0x3];
1298         u8         log_hairpin_data_sz[0x5];
1299
1300         u8         reserved_at_130[0x4];
1301         u8         log_wqe_num_of_strides[0x4];
1302         u8         two_byte_shift_en[0x1];
1303         u8         reserved_at_139[0x4];
1304         u8         log_wqe_stride_size[0x3];
1305
1306         u8         reserved_at_140[0x4c0];
1307
1308         struct mlx5_ifc_cmd_pas_bits pas[0];
1309 };
1310
1311 struct mlx5_ifc_rq_num_bits {
1312         u8         reserved_at_0[0x8];
1313         u8         rq_num[0x18];
1314 };
1315
1316 struct mlx5_ifc_mac_address_layout_bits {
1317         u8         reserved_at_0[0x10];
1318         u8         mac_addr_47_32[0x10];
1319
1320         u8         mac_addr_31_0[0x20];
1321 };
1322
1323 struct mlx5_ifc_vlan_layout_bits {
1324         u8         reserved_at_0[0x14];
1325         u8         vlan[0x0c];
1326
1327         u8         reserved_at_20[0x20];
1328 };
1329
1330 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1331         u8         reserved_at_0[0xa0];
1332
1333         u8         min_time_between_cnps[0x20];
1334
1335         u8         reserved_at_c0[0x12];
1336         u8         cnp_dscp[0x6];
1337         u8         reserved_at_d8[0x4];
1338         u8         cnp_prio_mode[0x1];
1339         u8         cnp_802p_prio[0x3];
1340
1341         u8         reserved_at_e0[0x720];
1342 };
1343
1344 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1345         u8         reserved_at_0[0x60];
1346
1347         u8         reserved_at_60[0x4];
1348         u8         clamp_tgt_rate[0x1];
1349         u8         reserved_at_65[0x3];
1350         u8         clamp_tgt_rate_after_time_inc[0x1];
1351         u8         reserved_at_69[0x17];
1352
1353         u8         reserved_at_80[0x20];
1354
1355         u8         rpg_time_reset[0x20];
1356
1357         u8         rpg_byte_reset[0x20];
1358
1359         u8         rpg_threshold[0x20];
1360
1361         u8         rpg_max_rate[0x20];
1362
1363         u8         rpg_ai_rate[0x20];
1364
1365         u8         rpg_hai_rate[0x20];
1366
1367         u8         rpg_gd[0x20];
1368
1369         u8         rpg_min_dec_fac[0x20];
1370
1371         u8         rpg_min_rate[0x20];
1372
1373         u8         reserved_at_1c0[0xe0];
1374
1375         u8         rate_to_set_on_first_cnp[0x20];
1376
1377         u8         dce_tcp_g[0x20];
1378
1379         u8         dce_tcp_rtt[0x20];
1380
1381         u8         rate_reduce_monitor_period[0x20];
1382
1383         u8         reserved_at_320[0x20];
1384
1385         u8         initial_alpha_value[0x20];
1386
1387         u8         reserved_at_360[0x4a0];
1388 };
1389
1390 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1391         u8         reserved_at_0[0x80];
1392
1393         u8         rppp_max_rps[0x20];
1394
1395         u8         rpg_time_reset[0x20];
1396
1397         u8         rpg_byte_reset[0x20];
1398
1399         u8         rpg_threshold[0x20];
1400
1401         u8         rpg_max_rate[0x20];
1402
1403         u8         rpg_ai_rate[0x20];
1404
1405         u8         rpg_hai_rate[0x20];
1406
1407         u8         rpg_gd[0x20];
1408
1409         u8         rpg_min_dec_fac[0x20];
1410
1411         u8         rpg_min_rate[0x20];
1412
1413         u8         reserved_at_1c0[0x640];
1414 };
1415
1416 enum {
1417         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1418         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1419         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1420 };
1421
1422 struct mlx5_ifc_resize_field_select_bits {
1423         u8         resize_field_select[0x20];
1424 };
1425
1426 enum {
1427         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1428         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1429         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1430         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1431 };
1432
1433 struct mlx5_ifc_modify_field_select_bits {
1434         u8         modify_field_select[0x20];
1435 };
1436
1437 struct mlx5_ifc_field_select_r_roce_np_bits {
1438         u8         field_select_r_roce_np[0x20];
1439 };
1440
1441 struct mlx5_ifc_field_select_r_roce_rp_bits {
1442         u8         field_select_r_roce_rp[0x20];
1443 };
1444
1445 enum {
1446         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1447         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1448         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1449         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1450         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1451         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1452         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1453         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1454         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1455         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1456 };
1457
1458 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1459         u8         field_select_8021qaurp[0x20];
1460 };
1461
1462 struct mlx5_ifc_phys_layer_cntrs_bits {
1463         u8         time_since_last_clear_high[0x20];
1464
1465         u8         time_since_last_clear_low[0x20];
1466
1467         u8         symbol_errors_high[0x20];
1468
1469         u8         symbol_errors_low[0x20];
1470
1471         u8         sync_headers_errors_high[0x20];
1472
1473         u8         sync_headers_errors_low[0x20];
1474
1475         u8         edpl_bip_errors_lane0_high[0x20];
1476
1477         u8         edpl_bip_errors_lane0_low[0x20];
1478
1479         u8         edpl_bip_errors_lane1_high[0x20];
1480
1481         u8         edpl_bip_errors_lane1_low[0x20];
1482
1483         u8         edpl_bip_errors_lane2_high[0x20];
1484
1485         u8         edpl_bip_errors_lane2_low[0x20];
1486
1487         u8         edpl_bip_errors_lane3_high[0x20];
1488
1489         u8         edpl_bip_errors_lane3_low[0x20];
1490
1491         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1492
1493         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1494
1495         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1496
1497         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1498
1499         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1500
1501         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1502
1503         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1504
1505         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1506
1507         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1508
1509         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1510
1511         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1512
1513         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1514
1515         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1516
1517         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1518
1519         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1520
1521         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1522
1523         u8         rs_fec_corrected_blocks_high[0x20];
1524
1525         u8         rs_fec_corrected_blocks_low[0x20];
1526
1527         u8         rs_fec_uncorrectable_blocks_high[0x20];
1528
1529         u8         rs_fec_uncorrectable_blocks_low[0x20];
1530
1531         u8         rs_fec_no_errors_blocks_high[0x20];
1532
1533         u8         rs_fec_no_errors_blocks_low[0x20];
1534
1535         u8         rs_fec_single_error_blocks_high[0x20];
1536
1537         u8         rs_fec_single_error_blocks_low[0x20];
1538
1539         u8         rs_fec_corrected_symbols_total_high[0x20];
1540
1541         u8         rs_fec_corrected_symbols_total_low[0x20];
1542
1543         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1544
1545         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1546
1547         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1548
1549         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1550
1551         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1552
1553         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1554
1555         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1556
1557         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1558
1559         u8         link_down_events[0x20];
1560
1561         u8         successful_recovery_events[0x20];
1562
1563         u8         reserved_at_640[0x180];
1564 };
1565
1566 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1567         u8         time_since_last_clear_high[0x20];
1568
1569         u8         time_since_last_clear_low[0x20];
1570
1571         u8         phy_received_bits_high[0x20];
1572
1573         u8         phy_received_bits_low[0x20];
1574
1575         u8         phy_symbol_errors_high[0x20];
1576
1577         u8         phy_symbol_errors_low[0x20];
1578
1579         u8         phy_corrected_bits_high[0x20];
1580
1581         u8         phy_corrected_bits_low[0x20];
1582
1583         u8         phy_corrected_bits_lane0_high[0x20];
1584
1585         u8         phy_corrected_bits_lane0_low[0x20];
1586
1587         u8         phy_corrected_bits_lane1_high[0x20];
1588
1589         u8         phy_corrected_bits_lane1_low[0x20];
1590
1591         u8         phy_corrected_bits_lane2_high[0x20];
1592
1593         u8         phy_corrected_bits_lane2_low[0x20];
1594
1595         u8         phy_corrected_bits_lane3_high[0x20];
1596
1597         u8         phy_corrected_bits_lane3_low[0x20];
1598
1599         u8         reserved_at_200[0x5c0];
1600 };
1601
1602 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1603         u8         symbol_error_counter[0x10];
1604
1605         u8         link_error_recovery_counter[0x8];
1606
1607         u8         link_downed_counter[0x8];
1608
1609         u8         port_rcv_errors[0x10];
1610
1611         u8         port_rcv_remote_physical_errors[0x10];
1612
1613         u8         port_rcv_switch_relay_errors[0x10];
1614
1615         u8         port_xmit_discards[0x10];
1616
1617         u8         port_xmit_constraint_errors[0x8];
1618
1619         u8         port_rcv_constraint_errors[0x8];
1620
1621         u8         reserved_at_70[0x8];
1622
1623         u8         link_overrun_errors[0x8];
1624
1625         u8         reserved_at_80[0x10];
1626
1627         u8         vl_15_dropped[0x10];
1628
1629         u8         reserved_at_a0[0x80];
1630
1631         u8         port_xmit_wait[0x20];
1632 };
1633
1634 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1635         u8         transmit_queue_high[0x20];
1636
1637         u8         transmit_queue_low[0x20];
1638
1639         u8         reserved_at_40[0x780];
1640 };
1641
1642 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1643         u8         rx_octets_high[0x20];
1644
1645         u8         rx_octets_low[0x20];
1646
1647         u8         reserved_at_40[0xc0];
1648
1649         u8         rx_frames_high[0x20];
1650
1651         u8         rx_frames_low[0x20];
1652
1653         u8         tx_octets_high[0x20];
1654
1655         u8         tx_octets_low[0x20];
1656
1657         u8         reserved_at_180[0xc0];
1658
1659         u8         tx_frames_high[0x20];
1660
1661         u8         tx_frames_low[0x20];
1662
1663         u8         rx_pause_high[0x20];
1664
1665         u8         rx_pause_low[0x20];
1666
1667         u8         rx_pause_duration_high[0x20];
1668
1669         u8         rx_pause_duration_low[0x20];
1670
1671         u8         tx_pause_high[0x20];
1672
1673         u8         tx_pause_low[0x20];
1674
1675         u8         tx_pause_duration_high[0x20];
1676
1677         u8         tx_pause_duration_low[0x20];
1678
1679         u8         rx_pause_transition_high[0x20];
1680
1681         u8         rx_pause_transition_low[0x20];
1682
1683         u8         reserved_at_3c0[0x40];
1684
1685         u8         device_stall_minor_watermark_cnt_high[0x20];
1686
1687         u8         device_stall_minor_watermark_cnt_low[0x20];
1688
1689         u8         device_stall_critical_watermark_cnt_high[0x20];
1690
1691         u8         device_stall_critical_watermark_cnt_low[0x20];
1692
1693         u8         reserved_at_480[0x340];
1694 };
1695
1696 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1697         u8         port_transmit_wait_high[0x20];
1698
1699         u8         port_transmit_wait_low[0x20];
1700
1701         u8         reserved_at_40[0x100];
1702
1703         u8         rx_buffer_almost_full_high[0x20];
1704
1705         u8         rx_buffer_almost_full_low[0x20];
1706
1707         u8         rx_buffer_full_high[0x20];
1708
1709         u8         rx_buffer_full_low[0x20];
1710
1711         u8         rx_icrc_encapsulated_high[0x20];
1712
1713         u8         rx_icrc_encapsulated_low[0x20];
1714
1715         u8         reserved_at_200[0x5c0];
1716 };
1717
1718 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1719         u8         dot3stats_alignment_errors_high[0x20];
1720
1721         u8         dot3stats_alignment_errors_low[0x20];
1722
1723         u8         dot3stats_fcs_errors_high[0x20];
1724
1725         u8         dot3stats_fcs_errors_low[0x20];
1726
1727         u8         dot3stats_single_collision_frames_high[0x20];
1728
1729         u8         dot3stats_single_collision_frames_low[0x20];
1730
1731         u8         dot3stats_multiple_collision_frames_high[0x20];
1732
1733         u8         dot3stats_multiple_collision_frames_low[0x20];
1734
1735         u8         dot3stats_sqe_test_errors_high[0x20];
1736
1737         u8         dot3stats_sqe_test_errors_low[0x20];
1738
1739         u8         dot3stats_deferred_transmissions_high[0x20];
1740
1741         u8         dot3stats_deferred_transmissions_low[0x20];
1742
1743         u8         dot3stats_late_collisions_high[0x20];
1744
1745         u8         dot3stats_late_collisions_low[0x20];
1746
1747         u8         dot3stats_excessive_collisions_high[0x20];
1748
1749         u8         dot3stats_excessive_collisions_low[0x20];
1750
1751         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1752
1753         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1754
1755         u8         dot3stats_carrier_sense_errors_high[0x20];
1756
1757         u8         dot3stats_carrier_sense_errors_low[0x20];
1758
1759         u8         dot3stats_frame_too_longs_high[0x20];
1760
1761         u8         dot3stats_frame_too_longs_low[0x20];
1762
1763         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1764
1765         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1766
1767         u8         dot3stats_symbol_errors_high[0x20];
1768
1769         u8         dot3stats_symbol_errors_low[0x20];
1770
1771         u8         dot3control_in_unknown_opcodes_high[0x20];
1772
1773         u8         dot3control_in_unknown_opcodes_low[0x20];
1774
1775         u8         dot3in_pause_frames_high[0x20];
1776
1777         u8         dot3in_pause_frames_low[0x20];
1778
1779         u8         dot3out_pause_frames_high[0x20];
1780
1781         u8         dot3out_pause_frames_low[0x20];
1782
1783         u8         reserved_at_400[0x3c0];
1784 };
1785
1786 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1787         u8         ether_stats_drop_events_high[0x20];
1788
1789         u8         ether_stats_drop_events_low[0x20];
1790
1791         u8         ether_stats_octets_high[0x20];
1792
1793         u8         ether_stats_octets_low[0x20];
1794
1795         u8         ether_stats_pkts_high[0x20];
1796
1797         u8         ether_stats_pkts_low[0x20];
1798
1799         u8         ether_stats_broadcast_pkts_high[0x20];
1800
1801         u8         ether_stats_broadcast_pkts_low[0x20];
1802
1803         u8         ether_stats_multicast_pkts_high[0x20];
1804
1805         u8         ether_stats_multicast_pkts_low[0x20];
1806
1807         u8         ether_stats_crc_align_errors_high[0x20];
1808
1809         u8         ether_stats_crc_align_errors_low[0x20];
1810
1811         u8         ether_stats_undersize_pkts_high[0x20];
1812
1813         u8         ether_stats_undersize_pkts_low[0x20];
1814
1815         u8         ether_stats_oversize_pkts_high[0x20];
1816
1817         u8         ether_stats_oversize_pkts_low[0x20];
1818
1819         u8         ether_stats_fragments_high[0x20];
1820
1821         u8         ether_stats_fragments_low[0x20];
1822
1823         u8         ether_stats_jabbers_high[0x20];
1824
1825         u8         ether_stats_jabbers_low[0x20];
1826
1827         u8         ether_stats_collisions_high[0x20];
1828
1829         u8         ether_stats_collisions_low[0x20];
1830
1831         u8         ether_stats_pkts64octets_high[0x20];
1832
1833         u8         ether_stats_pkts64octets_low[0x20];
1834
1835         u8         ether_stats_pkts65to127octets_high[0x20];
1836
1837         u8         ether_stats_pkts65to127octets_low[0x20];
1838
1839         u8         ether_stats_pkts128to255octets_high[0x20];
1840
1841         u8         ether_stats_pkts128to255octets_low[0x20];
1842
1843         u8         ether_stats_pkts256to511octets_high[0x20];
1844
1845         u8         ether_stats_pkts256to511octets_low[0x20];
1846
1847         u8         ether_stats_pkts512to1023octets_high[0x20];
1848
1849         u8         ether_stats_pkts512to1023octets_low[0x20];
1850
1851         u8         ether_stats_pkts1024to1518octets_high[0x20];
1852
1853         u8         ether_stats_pkts1024to1518octets_low[0x20];
1854
1855         u8         ether_stats_pkts1519to2047octets_high[0x20];
1856
1857         u8         ether_stats_pkts1519to2047octets_low[0x20];
1858
1859         u8         ether_stats_pkts2048to4095octets_high[0x20];
1860
1861         u8         ether_stats_pkts2048to4095octets_low[0x20];
1862
1863         u8         ether_stats_pkts4096to8191octets_high[0x20];
1864
1865         u8         ether_stats_pkts4096to8191octets_low[0x20];
1866
1867         u8         ether_stats_pkts8192to10239octets_high[0x20];
1868
1869         u8         ether_stats_pkts8192to10239octets_low[0x20];
1870
1871         u8         reserved_at_540[0x280];
1872 };
1873
1874 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1875         u8         if_in_octets_high[0x20];
1876
1877         u8         if_in_octets_low[0x20];
1878
1879         u8         if_in_ucast_pkts_high[0x20];
1880
1881         u8         if_in_ucast_pkts_low[0x20];
1882
1883         u8         if_in_discards_high[0x20];
1884
1885         u8         if_in_discards_low[0x20];
1886
1887         u8         if_in_errors_high[0x20];
1888
1889         u8         if_in_errors_low[0x20];
1890
1891         u8         if_in_unknown_protos_high[0x20];
1892
1893         u8         if_in_unknown_protos_low[0x20];
1894
1895         u8         if_out_octets_high[0x20];
1896
1897         u8         if_out_octets_low[0x20];
1898
1899         u8         if_out_ucast_pkts_high[0x20];
1900
1901         u8         if_out_ucast_pkts_low[0x20];
1902
1903         u8         if_out_discards_high[0x20];
1904
1905         u8         if_out_discards_low[0x20];
1906
1907         u8         if_out_errors_high[0x20];
1908
1909         u8         if_out_errors_low[0x20];
1910
1911         u8         if_in_multicast_pkts_high[0x20];
1912
1913         u8         if_in_multicast_pkts_low[0x20];
1914
1915         u8         if_in_broadcast_pkts_high[0x20];
1916
1917         u8         if_in_broadcast_pkts_low[0x20];
1918
1919         u8         if_out_multicast_pkts_high[0x20];
1920
1921         u8         if_out_multicast_pkts_low[0x20];
1922
1923         u8         if_out_broadcast_pkts_high[0x20];
1924
1925         u8         if_out_broadcast_pkts_low[0x20];
1926
1927         u8         reserved_at_340[0x480];
1928 };
1929
1930 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1931         u8         a_frames_transmitted_ok_high[0x20];
1932
1933         u8         a_frames_transmitted_ok_low[0x20];
1934
1935         u8         a_frames_received_ok_high[0x20];
1936
1937         u8         a_frames_received_ok_low[0x20];
1938
1939         u8         a_frame_check_sequence_errors_high[0x20];
1940
1941         u8         a_frame_check_sequence_errors_low[0x20];
1942
1943         u8         a_alignment_errors_high[0x20];
1944
1945         u8         a_alignment_errors_low[0x20];
1946
1947         u8         a_octets_transmitted_ok_high[0x20];
1948
1949         u8         a_octets_transmitted_ok_low[0x20];
1950
1951         u8         a_octets_received_ok_high[0x20];
1952
1953         u8         a_octets_received_ok_low[0x20];
1954
1955         u8         a_multicast_frames_xmitted_ok_high[0x20];
1956
1957         u8         a_multicast_frames_xmitted_ok_low[0x20];
1958
1959         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1960
1961         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1962
1963         u8         a_multicast_frames_received_ok_high[0x20];
1964
1965         u8         a_multicast_frames_received_ok_low[0x20];
1966
1967         u8         a_broadcast_frames_received_ok_high[0x20];
1968
1969         u8         a_broadcast_frames_received_ok_low[0x20];
1970
1971         u8         a_in_range_length_errors_high[0x20];
1972
1973         u8         a_in_range_length_errors_low[0x20];
1974
1975         u8         a_out_of_range_length_field_high[0x20];
1976
1977         u8         a_out_of_range_length_field_low[0x20];
1978
1979         u8         a_frame_too_long_errors_high[0x20];
1980
1981         u8         a_frame_too_long_errors_low[0x20];
1982
1983         u8         a_symbol_error_during_carrier_high[0x20];
1984
1985         u8         a_symbol_error_during_carrier_low[0x20];
1986
1987         u8         a_mac_control_frames_transmitted_high[0x20];
1988
1989         u8         a_mac_control_frames_transmitted_low[0x20];
1990
1991         u8         a_mac_control_frames_received_high[0x20];
1992
1993         u8         a_mac_control_frames_received_low[0x20];
1994
1995         u8         a_unsupported_opcodes_received_high[0x20];
1996
1997         u8         a_unsupported_opcodes_received_low[0x20];
1998
1999         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2000
2001         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2002
2003         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2004
2005         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2006
2007         u8         reserved_at_4c0[0x300];
2008 };
2009
2010 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2011         u8         life_time_counter_high[0x20];
2012
2013         u8         life_time_counter_low[0x20];
2014
2015         u8         rx_errors[0x20];
2016
2017         u8         tx_errors[0x20];
2018
2019         u8         l0_to_recovery_eieos[0x20];
2020
2021         u8         l0_to_recovery_ts[0x20];
2022
2023         u8         l0_to_recovery_framing[0x20];
2024
2025         u8         l0_to_recovery_retrain[0x20];
2026
2027         u8         crc_error_dllp[0x20];
2028
2029         u8         crc_error_tlp[0x20];
2030
2031         u8         tx_overflow_buffer_pkt_high[0x20];
2032
2033         u8         tx_overflow_buffer_pkt_low[0x20];
2034
2035         u8         outbound_stalled_reads[0x20];
2036
2037         u8         outbound_stalled_writes[0x20];
2038
2039         u8         outbound_stalled_reads_events[0x20];
2040
2041         u8         outbound_stalled_writes_events[0x20];
2042
2043         u8         reserved_at_200[0x5c0];
2044 };
2045
2046 struct mlx5_ifc_cmd_inter_comp_event_bits {
2047         u8         command_completion_vector[0x20];
2048
2049         u8         reserved_at_20[0xc0];
2050 };
2051
2052 struct mlx5_ifc_stall_vl_event_bits {
2053         u8         reserved_at_0[0x18];
2054         u8         port_num[0x1];
2055         u8         reserved_at_19[0x3];
2056         u8         vl[0x4];
2057
2058         u8         reserved_at_20[0xa0];
2059 };
2060
2061 struct mlx5_ifc_db_bf_congestion_event_bits {
2062         u8         event_subtype[0x8];
2063         u8         reserved_at_8[0x8];
2064         u8         congestion_level[0x8];
2065         u8         reserved_at_18[0x8];
2066
2067         u8         reserved_at_20[0xa0];
2068 };
2069
2070 struct mlx5_ifc_gpio_event_bits {
2071         u8         reserved_at_0[0x60];
2072
2073         u8         gpio_event_hi[0x20];
2074
2075         u8         gpio_event_lo[0x20];
2076
2077         u8         reserved_at_a0[0x40];
2078 };
2079
2080 struct mlx5_ifc_port_state_change_event_bits {
2081         u8         reserved_at_0[0x40];
2082
2083         u8         port_num[0x4];
2084         u8         reserved_at_44[0x1c];
2085
2086         u8         reserved_at_60[0x80];
2087 };
2088
2089 struct mlx5_ifc_dropped_packet_logged_bits {
2090         u8         reserved_at_0[0xe0];
2091 };
2092
2093 enum {
2094         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2095         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2096 };
2097
2098 struct mlx5_ifc_cq_error_bits {
2099         u8         reserved_at_0[0x8];
2100         u8         cqn[0x18];
2101
2102         u8         reserved_at_20[0x20];
2103
2104         u8         reserved_at_40[0x18];
2105         u8         syndrome[0x8];
2106
2107         u8         reserved_at_60[0x80];
2108 };
2109
2110 struct mlx5_ifc_rdma_page_fault_event_bits {
2111         u8         bytes_committed[0x20];
2112
2113         u8         r_key[0x20];
2114
2115         u8         reserved_at_40[0x10];
2116         u8         packet_len[0x10];
2117
2118         u8         rdma_op_len[0x20];
2119
2120         u8         rdma_va[0x40];
2121
2122         u8         reserved_at_c0[0x5];
2123         u8         rdma[0x1];
2124         u8         write[0x1];
2125         u8         requestor[0x1];
2126         u8         qp_number[0x18];
2127 };
2128
2129 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2130         u8         bytes_committed[0x20];
2131
2132         u8         reserved_at_20[0x10];
2133         u8         wqe_index[0x10];
2134
2135         u8         reserved_at_40[0x10];
2136         u8         len[0x10];
2137
2138         u8         reserved_at_60[0x60];
2139
2140         u8         reserved_at_c0[0x5];
2141         u8         rdma[0x1];
2142         u8         write_read[0x1];
2143         u8         requestor[0x1];
2144         u8         qpn[0x18];
2145 };
2146
2147 struct mlx5_ifc_qp_events_bits {
2148         u8         reserved_at_0[0xa0];
2149
2150         u8         type[0x8];
2151         u8         reserved_at_a8[0x18];
2152
2153         u8         reserved_at_c0[0x8];
2154         u8         qpn_rqn_sqn[0x18];
2155 };
2156
2157 struct mlx5_ifc_dct_events_bits {
2158         u8         reserved_at_0[0xc0];
2159
2160         u8         reserved_at_c0[0x8];
2161         u8         dct_number[0x18];
2162 };
2163
2164 struct mlx5_ifc_comp_event_bits {
2165         u8         reserved_at_0[0xc0];
2166
2167         u8         reserved_at_c0[0x8];
2168         u8         cq_number[0x18];
2169 };
2170
2171 enum {
2172         MLX5_QPC_STATE_RST        = 0x0,
2173         MLX5_QPC_STATE_INIT       = 0x1,
2174         MLX5_QPC_STATE_RTR        = 0x2,
2175         MLX5_QPC_STATE_RTS        = 0x3,
2176         MLX5_QPC_STATE_SQER       = 0x4,
2177         MLX5_QPC_STATE_ERR        = 0x6,
2178         MLX5_QPC_STATE_SQD        = 0x7,
2179         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2180 };
2181
2182 enum {
2183         MLX5_QPC_ST_RC            = 0x0,
2184         MLX5_QPC_ST_UC            = 0x1,
2185         MLX5_QPC_ST_UD            = 0x2,
2186         MLX5_QPC_ST_XRC           = 0x3,
2187         MLX5_QPC_ST_DCI           = 0x5,
2188         MLX5_QPC_ST_QP0           = 0x7,
2189         MLX5_QPC_ST_QP1           = 0x8,
2190         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2191         MLX5_QPC_ST_REG_UMR       = 0xc,
2192 };
2193
2194 enum {
2195         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2196         MLX5_QPC_PM_STATE_REARM     = 0x1,
2197         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2198         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2199 };
2200
2201 enum {
2202         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2203 };
2204
2205 enum {
2206         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2207         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2208 };
2209
2210 enum {
2211         MLX5_QPC_MTU_256_BYTES        = 0x1,
2212         MLX5_QPC_MTU_512_BYTES        = 0x2,
2213         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2214         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2215         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2216         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2217 };
2218
2219 enum {
2220         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2221         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2222         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2223         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2224         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2225         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2226         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2227         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2228 };
2229
2230 enum {
2231         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2232         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2233         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2234 };
2235
2236 enum {
2237         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2238         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2239         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2240 };
2241
2242 struct mlx5_ifc_qpc_bits {
2243         u8         state[0x4];
2244         u8         lag_tx_port_affinity[0x4];
2245         u8         st[0x8];
2246         u8         reserved_at_10[0x3];
2247         u8         pm_state[0x2];
2248         u8         reserved_at_15[0x3];
2249         u8         offload_type[0x4];
2250         u8         end_padding_mode[0x2];
2251         u8         reserved_at_1e[0x2];
2252
2253         u8         wq_signature[0x1];
2254         u8         block_lb_mc[0x1];
2255         u8         atomic_like_write_en[0x1];
2256         u8         latency_sensitive[0x1];
2257         u8         reserved_at_24[0x1];
2258         u8         drain_sigerr[0x1];
2259         u8         reserved_at_26[0x2];
2260         u8         pd[0x18];
2261
2262         u8         mtu[0x3];
2263         u8         log_msg_max[0x5];
2264         u8         reserved_at_48[0x1];
2265         u8         log_rq_size[0x4];
2266         u8         log_rq_stride[0x3];
2267         u8         no_sq[0x1];
2268         u8         log_sq_size[0x4];
2269         u8         reserved_at_55[0x6];
2270         u8         rlky[0x1];
2271         u8         ulp_stateless_offload_mode[0x4];
2272
2273         u8         counter_set_id[0x8];
2274         u8         uar_page[0x18];
2275
2276         u8         reserved_at_80[0x8];
2277         u8         user_index[0x18];
2278
2279         u8         reserved_at_a0[0x3];
2280         u8         log_page_size[0x5];
2281         u8         remote_qpn[0x18];
2282
2283         struct mlx5_ifc_ads_bits primary_address_path;
2284
2285         struct mlx5_ifc_ads_bits secondary_address_path;
2286
2287         u8         log_ack_req_freq[0x4];
2288         u8         reserved_at_384[0x4];
2289         u8         log_sra_max[0x3];
2290         u8         reserved_at_38b[0x2];
2291         u8         retry_count[0x3];
2292         u8         rnr_retry[0x3];
2293         u8         reserved_at_393[0x1];
2294         u8         fre[0x1];
2295         u8         cur_rnr_retry[0x3];
2296         u8         cur_retry_count[0x3];
2297         u8         reserved_at_39b[0x5];
2298
2299         u8         reserved_at_3a0[0x20];
2300
2301         u8         reserved_at_3c0[0x8];
2302         u8         next_send_psn[0x18];
2303
2304         u8         reserved_at_3e0[0x8];
2305         u8         cqn_snd[0x18];
2306
2307         u8         reserved_at_400[0x8];
2308         u8         deth_sqpn[0x18];
2309
2310         u8         reserved_at_420[0x20];
2311
2312         u8         reserved_at_440[0x8];
2313         u8         last_acked_psn[0x18];
2314
2315         u8         reserved_at_460[0x8];
2316         u8         ssn[0x18];
2317
2318         u8         reserved_at_480[0x8];
2319         u8         log_rra_max[0x3];
2320         u8         reserved_at_48b[0x1];
2321         u8         atomic_mode[0x4];
2322         u8         rre[0x1];
2323         u8         rwe[0x1];
2324         u8         rae[0x1];
2325         u8         reserved_at_493[0x1];
2326         u8         page_offset[0x6];
2327         u8         reserved_at_49a[0x3];
2328         u8         cd_slave_receive[0x1];
2329         u8         cd_slave_send[0x1];
2330         u8         cd_master[0x1];
2331
2332         u8         reserved_at_4a0[0x3];
2333         u8         min_rnr_nak[0x5];
2334         u8         next_rcv_psn[0x18];
2335
2336         u8         reserved_at_4c0[0x8];
2337         u8         xrcd[0x18];
2338
2339         u8         reserved_at_4e0[0x8];
2340         u8         cqn_rcv[0x18];
2341
2342         u8         dbr_addr[0x40];
2343
2344         u8         q_key[0x20];
2345
2346         u8         reserved_at_560[0x5];
2347         u8         rq_type[0x3];
2348         u8         srqn_rmpn_xrqn[0x18];
2349
2350         u8         reserved_at_580[0x8];
2351         u8         rmsn[0x18];
2352
2353         u8         hw_sq_wqebb_counter[0x10];
2354         u8         sw_sq_wqebb_counter[0x10];
2355
2356         u8         hw_rq_counter[0x20];
2357
2358         u8         sw_rq_counter[0x20];
2359
2360         u8         reserved_at_600[0x20];
2361
2362         u8         reserved_at_620[0xf];
2363         u8         cgs[0x1];
2364         u8         cs_req[0x8];
2365         u8         cs_res[0x8];
2366
2367         u8         dc_access_key[0x40];
2368
2369         u8         reserved_at_680[0x3];
2370         u8         dbr_umem_valid[0x1];
2371
2372         u8         reserved_at_684[0xbc];
2373 };
2374
2375 struct mlx5_ifc_roce_addr_layout_bits {
2376         u8         source_l3_address[16][0x8];
2377
2378         u8         reserved_at_80[0x3];
2379         u8         vlan_valid[0x1];
2380         u8         vlan_id[0xc];
2381         u8         source_mac_47_32[0x10];
2382
2383         u8         source_mac_31_0[0x20];
2384
2385         u8         reserved_at_c0[0x14];
2386         u8         roce_l3_type[0x4];
2387         u8         roce_version[0x8];
2388
2389         u8         reserved_at_e0[0x20];
2390 };
2391
2392 union mlx5_ifc_hca_cap_union_bits {
2393         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2394         struct mlx5_ifc_odp_cap_bits odp_cap;
2395         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2396         struct mlx5_ifc_roce_cap_bits roce_cap;
2397         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2398         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2399         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2400         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2401         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2402         struct mlx5_ifc_qos_cap_bits qos_cap;
2403         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2404         u8         reserved_at_0[0x8000];
2405 };
2406
2407 enum {
2408         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2409         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2410         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2411         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2412         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2413         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2414         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2415         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2416         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2417         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2418         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2419 };
2420
2421 struct mlx5_ifc_vlan_bits {
2422         u8         ethtype[0x10];
2423         u8         prio[0x3];
2424         u8         cfi[0x1];
2425         u8         vid[0xc];
2426 };
2427
2428 struct mlx5_ifc_flow_context_bits {
2429         struct mlx5_ifc_vlan_bits push_vlan;
2430
2431         u8         group_id[0x20];
2432
2433         u8         reserved_at_40[0x8];
2434         u8         flow_tag[0x18];
2435
2436         u8         reserved_at_60[0x10];
2437         u8         action[0x10];
2438
2439         u8         reserved_at_80[0x8];
2440         u8         destination_list_size[0x18];
2441
2442         u8         reserved_at_a0[0x8];
2443         u8         flow_counter_list_size[0x18];
2444
2445         u8         packet_reformat_id[0x20];
2446
2447         u8         modify_header_id[0x20];
2448
2449         struct mlx5_ifc_vlan_bits push_vlan_2;
2450
2451         u8         reserved_at_120[0xe0];
2452
2453         struct mlx5_ifc_fte_match_param_bits match_value;
2454
2455         u8         reserved_at_1200[0x600];
2456
2457         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2458 };
2459
2460 enum {
2461         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2462         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2463 };
2464
2465 struct mlx5_ifc_xrc_srqc_bits {
2466         u8         state[0x4];
2467         u8         log_xrc_srq_size[0x4];
2468         u8         reserved_at_8[0x18];
2469
2470         u8         wq_signature[0x1];
2471         u8         cont_srq[0x1];
2472         u8         dbr_umem_valid[0x1];
2473         u8         rlky[0x1];
2474         u8         basic_cyclic_rcv_wqe[0x1];
2475         u8         log_rq_stride[0x3];
2476         u8         xrcd[0x18];
2477
2478         u8         page_offset[0x6];
2479         u8         reserved_at_46[0x2];
2480         u8         cqn[0x18];
2481
2482         u8         reserved_at_60[0x20];
2483
2484         u8         user_index_equal_xrc_srqn[0x1];
2485         u8         reserved_at_81[0x1];
2486         u8         log_page_size[0x6];
2487         u8         user_index[0x18];
2488
2489         u8         reserved_at_a0[0x20];
2490
2491         u8         reserved_at_c0[0x8];
2492         u8         pd[0x18];
2493
2494         u8         lwm[0x10];
2495         u8         wqe_cnt[0x10];
2496
2497         u8         reserved_at_100[0x40];
2498
2499         u8         db_record_addr_h[0x20];
2500
2501         u8         db_record_addr_l[0x1e];
2502         u8         reserved_at_17e[0x2];
2503
2504         u8         reserved_at_180[0x80];
2505 };
2506
2507 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2508         u8         counter_error_queues[0x20];
2509
2510         u8         total_error_queues[0x20];
2511
2512         u8         send_queue_priority_update_flow[0x20];
2513
2514         u8         reserved_at_60[0x20];
2515
2516         u8         nic_receive_steering_discard[0x40];
2517
2518         u8         receive_discard_vport_down[0x40];
2519
2520         u8         transmit_discard_vport_down[0x40];
2521
2522         u8         reserved_at_140[0xec0];
2523 };
2524
2525 struct mlx5_ifc_traffic_counter_bits {
2526         u8         packets[0x40];
2527
2528         u8         octets[0x40];
2529 };
2530
2531 struct mlx5_ifc_tisc_bits {
2532         u8         strict_lag_tx_port_affinity[0x1];
2533         u8         reserved_at_1[0x3];
2534         u8         lag_tx_port_affinity[0x04];
2535
2536         u8         reserved_at_8[0x4];
2537         u8         prio[0x4];
2538         u8         reserved_at_10[0x10];
2539
2540         u8         reserved_at_20[0x100];
2541
2542         u8         reserved_at_120[0x8];
2543         u8         transport_domain[0x18];
2544
2545         u8         reserved_at_140[0x8];
2546         u8         underlay_qpn[0x18];
2547         u8         reserved_at_160[0x3a0];
2548 };
2549
2550 enum {
2551         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2552         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2553 };
2554
2555 enum {
2556         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2557         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2558 };
2559
2560 enum {
2561         MLX5_RX_HASH_FN_NONE           = 0x0,
2562         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2563         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2564 };
2565
2566 enum {
2567         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2568         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2569 };
2570
2571 struct mlx5_ifc_tirc_bits {
2572         u8         reserved_at_0[0x20];
2573
2574         u8         disp_type[0x4];
2575         u8         reserved_at_24[0x1c];
2576
2577         u8         reserved_at_40[0x40];
2578
2579         u8         reserved_at_80[0x4];
2580         u8         lro_timeout_period_usecs[0x10];
2581         u8         lro_enable_mask[0x4];
2582         u8         lro_max_ip_payload_size[0x8];
2583
2584         u8         reserved_at_a0[0x40];
2585
2586         u8         reserved_at_e0[0x8];
2587         u8         inline_rqn[0x18];
2588
2589         u8         rx_hash_symmetric[0x1];
2590         u8         reserved_at_101[0x1];
2591         u8         tunneled_offload_en[0x1];
2592         u8         reserved_at_103[0x5];
2593         u8         indirect_table[0x18];
2594
2595         u8         rx_hash_fn[0x4];
2596         u8         reserved_at_124[0x2];
2597         u8         self_lb_block[0x2];
2598         u8         transport_domain[0x18];
2599
2600         u8         rx_hash_toeplitz_key[10][0x20];
2601
2602         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2603
2604         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2605
2606         u8         reserved_at_2c0[0x4c0];
2607 };
2608
2609 enum {
2610         MLX5_SRQC_STATE_GOOD   = 0x0,
2611         MLX5_SRQC_STATE_ERROR  = 0x1,
2612 };
2613
2614 struct mlx5_ifc_srqc_bits {
2615         u8         state[0x4];
2616         u8         log_srq_size[0x4];
2617         u8         reserved_at_8[0x18];
2618
2619         u8         wq_signature[0x1];
2620         u8         cont_srq[0x1];
2621         u8         reserved_at_22[0x1];
2622         u8         rlky[0x1];
2623         u8         reserved_at_24[0x1];
2624         u8         log_rq_stride[0x3];
2625         u8         xrcd[0x18];
2626
2627         u8         page_offset[0x6];
2628         u8         reserved_at_46[0x2];
2629         u8         cqn[0x18];
2630
2631         u8         reserved_at_60[0x20];
2632
2633         u8         reserved_at_80[0x2];
2634         u8         log_page_size[0x6];
2635         u8         reserved_at_88[0x18];
2636
2637         u8         reserved_at_a0[0x20];
2638
2639         u8         reserved_at_c0[0x8];
2640         u8         pd[0x18];
2641
2642         u8         lwm[0x10];
2643         u8         wqe_cnt[0x10];
2644
2645         u8         reserved_at_100[0x40];
2646
2647         u8         dbr_addr[0x40];
2648
2649         u8         reserved_at_180[0x80];
2650 };
2651
2652 enum {
2653         MLX5_SQC_STATE_RST  = 0x0,
2654         MLX5_SQC_STATE_RDY  = 0x1,
2655         MLX5_SQC_STATE_ERR  = 0x3,
2656 };
2657
2658 struct mlx5_ifc_sqc_bits {
2659         u8         rlky[0x1];
2660         u8         cd_master[0x1];
2661         u8         fre[0x1];
2662         u8         flush_in_error_en[0x1];
2663         u8         allow_multi_pkt_send_wqe[0x1];
2664         u8         min_wqe_inline_mode[0x3];
2665         u8         state[0x4];
2666         u8         reg_umr[0x1];
2667         u8         allow_swp[0x1];
2668         u8         hairpin[0x1];
2669         u8         reserved_at_f[0x11];
2670
2671         u8         reserved_at_20[0x8];
2672         u8         user_index[0x18];
2673
2674         u8         reserved_at_40[0x8];
2675         u8         cqn[0x18];
2676
2677         u8         reserved_at_60[0x8];
2678         u8         hairpin_peer_rq[0x18];
2679
2680         u8         reserved_at_80[0x10];
2681         u8         hairpin_peer_vhca[0x10];
2682
2683         u8         reserved_at_a0[0x50];
2684
2685         u8         packet_pacing_rate_limit_index[0x10];
2686         u8         tis_lst_sz[0x10];
2687         u8         reserved_at_110[0x10];
2688
2689         u8         reserved_at_120[0x40];
2690
2691         u8         reserved_at_160[0x8];
2692         u8         tis_num_0[0x18];
2693
2694         struct mlx5_ifc_wq_bits wq;
2695 };
2696
2697 enum {
2698         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2699         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2700         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2701         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2702 };
2703
2704 struct mlx5_ifc_scheduling_context_bits {
2705         u8         element_type[0x8];
2706         u8         reserved_at_8[0x18];
2707
2708         u8         element_attributes[0x20];
2709
2710         u8         parent_element_id[0x20];
2711
2712         u8         reserved_at_60[0x40];
2713
2714         u8         bw_share[0x20];
2715
2716         u8         max_average_bw[0x20];
2717
2718         u8         reserved_at_e0[0x120];
2719 };
2720
2721 struct mlx5_ifc_rqtc_bits {
2722         u8         reserved_at_0[0xa0];
2723
2724         u8         reserved_at_a0[0x10];
2725         u8         rqt_max_size[0x10];
2726
2727         u8         reserved_at_c0[0x10];
2728         u8         rqt_actual_size[0x10];
2729
2730         u8         reserved_at_e0[0x6a0];
2731
2732         struct mlx5_ifc_rq_num_bits rq_num[0];
2733 };
2734
2735 enum {
2736         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2737         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2738 };
2739
2740 enum {
2741         MLX5_RQC_STATE_RST  = 0x0,
2742         MLX5_RQC_STATE_RDY  = 0x1,
2743         MLX5_RQC_STATE_ERR  = 0x3,
2744 };
2745
2746 struct mlx5_ifc_rqc_bits {
2747         u8         rlky[0x1];
2748         u8         delay_drop_en[0x1];
2749         u8         scatter_fcs[0x1];
2750         u8         vsd[0x1];
2751         u8         mem_rq_type[0x4];
2752         u8         state[0x4];
2753         u8         reserved_at_c[0x1];
2754         u8         flush_in_error_en[0x1];
2755         u8         hairpin[0x1];
2756         u8         reserved_at_f[0x11];
2757
2758         u8         reserved_at_20[0x8];
2759         u8         user_index[0x18];
2760
2761         u8         reserved_at_40[0x8];
2762         u8         cqn[0x18];
2763
2764         u8         counter_set_id[0x8];
2765         u8         reserved_at_68[0x18];
2766
2767         u8         reserved_at_80[0x8];
2768         u8         rmpn[0x18];
2769
2770         u8         reserved_at_a0[0x8];
2771         u8         hairpin_peer_sq[0x18];
2772
2773         u8         reserved_at_c0[0x10];
2774         u8         hairpin_peer_vhca[0x10];
2775
2776         u8         reserved_at_e0[0xa0];
2777
2778         struct mlx5_ifc_wq_bits wq;
2779 };
2780
2781 enum {
2782         MLX5_RMPC_STATE_RDY  = 0x1,
2783         MLX5_RMPC_STATE_ERR  = 0x3,
2784 };
2785
2786 struct mlx5_ifc_rmpc_bits {
2787         u8         reserved_at_0[0x8];
2788         u8         state[0x4];
2789         u8         reserved_at_c[0x14];
2790
2791         u8         basic_cyclic_rcv_wqe[0x1];
2792         u8         reserved_at_21[0x1f];
2793
2794         u8         reserved_at_40[0x140];
2795
2796         struct mlx5_ifc_wq_bits wq;
2797 };
2798
2799 struct mlx5_ifc_nic_vport_context_bits {
2800         u8         reserved_at_0[0x5];
2801         u8         min_wqe_inline_mode[0x3];
2802         u8         reserved_at_8[0x15];
2803         u8         disable_mc_local_lb[0x1];
2804         u8         disable_uc_local_lb[0x1];
2805         u8         roce_en[0x1];
2806
2807         u8         arm_change_event[0x1];
2808         u8         reserved_at_21[0x1a];
2809         u8         event_on_mtu[0x1];
2810         u8         event_on_promisc_change[0x1];
2811         u8         event_on_vlan_change[0x1];
2812         u8         event_on_mc_address_change[0x1];
2813         u8         event_on_uc_address_change[0x1];
2814
2815         u8         reserved_at_40[0xc];
2816
2817         u8         affiliation_criteria[0x4];
2818         u8         affiliated_vhca_id[0x10];
2819
2820         u8         reserved_at_60[0xd0];
2821
2822         u8         mtu[0x10];
2823
2824         u8         system_image_guid[0x40];
2825         u8         port_guid[0x40];
2826         u8         node_guid[0x40];
2827
2828         u8         reserved_at_200[0x140];
2829         u8         qkey_violation_counter[0x10];
2830         u8         reserved_at_350[0x430];
2831
2832         u8         promisc_uc[0x1];
2833         u8         promisc_mc[0x1];
2834         u8         promisc_all[0x1];
2835         u8         reserved_at_783[0x2];
2836         u8         allowed_list_type[0x3];
2837         u8         reserved_at_788[0xc];
2838         u8         allowed_list_size[0xc];
2839
2840         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2841
2842         u8         reserved_at_7e0[0x20];
2843
2844         u8         current_uc_mac_address[0][0x40];
2845 };
2846
2847 enum {
2848         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2849         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2850         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2851         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2852         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2853 };
2854
2855 struct mlx5_ifc_mkc_bits {
2856         u8         reserved_at_0[0x1];
2857         u8         free[0x1];
2858         u8         reserved_at_2[0x1];
2859         u8         access_mode_4_2[0x3];
2860         u8         reserved_at_6[0x7];
2861         u8         relaxed_ordering_write[0x1];
2862         u8         reserved_at_e[0x1];
2863         u8         small_fence_on_rdma_read_response[0x1];
2864         u8         umr_en[0x1];
2865         u8         a[0x1];
2866         u8         rw[0x1];
2867         u8         rr[0x1];
2868         u8         lw[0x1];
2869         u8         lr[0x1];
2870         u8         access_mode_1_0[0x2];
2871         u8         reserved_at_18[0x8];
2872
2873         u8         qpn[0x18];
2874         u8         mkey_7_0[0x8];
2875
2876         u8         reserved_at_40[0x20];
2877
2878         u8         length64[0x1];
2879         u8         bsf_en[0x1];
2880         u8         sync_umr[0x1];
2881         u8         reserved_at_63[0x2];
2882         u8         expected_sigerr_count[0x1];
2883         u8         reserved_at_66[0x1];
2884         u8         en_rinval[0x1];
2885         u8         pd[0x18];
2886
2887         u8         start_addr[0x40];
2888
2889         u8         len[0x40];
2890
2891         u8         bsf_octword_size[0x20];
2892
2893         u8         reserved_at_120[0x80];
2894
2895         u8         translations_octword_size[0x20];
2896
2897         u8         reserved_at_1c0[0x1b];
2898         u8         log_page_size[0x5];
2899
2900         u8         reserved_at_1e0[0x20];
2901 };
2902
2903 struct mlx5_ifc_pkey_bits {
2904         u8         reserved_at_0[0x10];
2905         u8         pkey[0x10];
2906 };
2907
2908 struct mlx5_ifc_array128_auto_bits {
2909         u8         array128_auto[16][0x8];
2910 };
2911
2912 struct mlx5_ifc_hca_vport_context_bits {
2913         u8         field_select[0x20];
2914
2915         u8         reserved_at_20[0xe0];
2916
2917         u8         sm_virt_aware[0x1];
2918         u8         has_smi[0x1];
2919         u8         has_raw[0x1];
2920         u8         grh_required[0x1];
2921         u8         reserved_at_104[0xc];
2922         u8         port_physical_state[0x4];
2923         u8         vport_state_policy[0x4];
2924         u8         port_state[0x4];
2925         u8         vport_state[0x4];
2926
2927         u8         reserved_at_120[0x20];
2928
2929         u8         system_image_guid[0x40];
2930
2931         u8         port_guid[0x40];
2932
2933         u8         node_guid[0x40];
2934
2935         u8         cap_mask1[0x20];
2936
2937         u8         cap_mask1_field_select[0x20];
2938
2939         u8         cap_mask2[0x20];
2940
2941         u8         cap_mask2_field_select[0x20];
2942
2943         u8         reserved_at_280[0x80];
2944
2945         u8         lid[0x10];
2946         u8         reserved_at_310[0x4];
2947         u8         init_type_reply[0x4];
2948         u8         lmc[0x3];
2949         u8         subnet_timeout[0x5];
2950
2951         u8         sm_lid[0x10];
2952         u8         sm_sl[0x4];
2953         u8         reserved_at_334[0xc];
2954
2955         u8         qkey_violation_counter[0x10];
2956         u8         pkey_violation_counter[0x10];
2957
2958         u8         reserved_at_360[0xca0];
2959 };
2960
2961 struct mlx5_ifc_esw_vport_context_bits {
2962         u8         reserved_at_0[0x3];
2963         u8         vport_svlan_strip[0x1];
2964         u8         vport_cvlan_strip[0x1];
2965         u8         vport_svlan_insert[0x1];
2966         u8         vport_cvlan_insert[0x2];
2967         u8         reserved_at_8[0x18];
2968
2969         u8         reserved_at_20[0x20];
2970
2971         u8         svlan_cfi[0x1];
2972         u8         svlan_pcp[0x3];
2973         u8         svlan_id[0xc];
2974         u8         cvlan_cfi[0x1];
2975         u8         cvlan_pcp[0x3];
2976         u8         cvlan_id[0xc];
2977
2978         u8         reserved_at_60[0x7a0];
2979 };
2980
2981 enum {
2982         MLX5_EQC_STATUS_OK                = 0x0,
2983         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2984 };
2985
2986 enum {
2987         MLX5_EQC_ST_ARMED  = 0x9,
2988         MLX5_EQC_ST_FIRED  = 0xa,
2989 };
2990
2991 struct mlx5_ifc_eqc_bits {
2992         u8         status[0x4];
2993         u8         reserved_at_4[0x9];
2994         u8         ec[0x1];
2995         u8         oi[0x1];
2996         u8         reserved_at_f[0x5];
2997         u8         st[0x4];
2998         u8         reserved_at_18[0x8];
2999
3000         u8         reserved_at_20[0x20];
3001
3002         u8         reserved_at_40[0x14];
3003         u8         page_offset[0x6];
3004         u8         reserved_at_5a[0x6];
3005
3006         u8         reserved_at_60[0x3];
3007         u8         log_eq_size[0x5];
3008         u8         uar_page[0x18];
3009
3010         u8         reserved_at_80[0x20];
3011
3012         u8         reserved_at_a0[0x18];
3013         u8         intr[0x8];
3014
3015         u8         reserved_at_c0[0x3];
3016         u8         log_page_size[0x5];
3017         u8         reserved_at_c8[0x18];
3018
3019         u8         reserved_at_e0[0x60];
3020
3021         u8         reserved_at_140[0x8];
3022         u8         consumer_counter[0x18];
3023
3024         u8         reserved_at_160[0x8];
3025         u8         producer_counter[0x18];
3026
3027         u8         reserved_at_180[0x80];
3028 };
3029
3030 enum {
3031         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3032         MLX5_DCTC_STATE_DRAINING  = 0x1,
3033         MLX5_DCTC_STATE_DRAINED   = 0x2,
3034 };
3035
3036 enum {
3037         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3038         MLX5_DCTC_CS_RES_NA         = 0x1,
3039         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3040 };
3041
3042 enum {
3043         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3044         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3045         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3046         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3047         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3048 };
3049
3050 struct mlx5_ifc_dctc_bits {
3051         u8         reserved_at_0[0x4];
3052         u8         state[0x4];
3053         u8         reserved_at_8[0x18];
3054
3055         u8         reserved_at_20[0x8];
3056         u8         user_index[0x18];
3057
3058         u8         reserved_at_40[0x8];
3059         u8         cqn[0x18];
3060
3061         u8         counter_set_id[0x8];
3062         u8         atomic_mode[0x4];
3063         u8         rre[0x1];
3064         u8         rwe[0x1];
3065         u8         rae[0x1];
3066         u8         atomic_like_write_en[0x1];
3067         u8         latency_sensitive[0x1];
3068         u8         rlky[0x1];
3069         u8         free_ar[0x1];
3070         u8         reserved_at_73[0xd];
3071
3072         u8         reserved_at_80[0x8];
3073         u8         cs_res[0x8];
3074         u8         reserved_at_90[0x3];
3075         u8         min_rnr_nak[0x5];
3076         u8         reserved_at_98[0x8];
3077
3078         u8         reserved_at_a0[0x8];
3079         u8         srqn_xrqn[0x18];
3080
3081         u8         reserved_at_c0[0x8];
3082         u8         pd[0x18];
3083
3084         u8         tclass[0x8];
3085         u8         reserved_at_e8[0x4];
3086         u8         flow_label[0x14];
3087
3088         u8         dc_access_key[0x40];
3089
3090         u8         reserved_at_140[0x5];
3091         u8         mtu[0x3];
3092         u8         port[0x8];
3093         u8         pkey_index[0x10];
3094
3095         u8         reserved_at_160[0x8];
3096         u8         my_addr_index[0x8];
3097         u8         reserved_at_170[0x8];
3098         u8         hop_limit[0x8];
3099
3100         u8         dc_access_key_violation_count[0x20];
3101
3102         u8         reserved_at_1a0[0x14];
3103         u8         dei_cfi[0x1];
3104         u8         eth_prio[0x3];
3105         u8         ecn[0x2];
3106         u8         dscp[0x6];
3107
3108         u8         reserved_at_1c0[0x40];
3109 };
3110
3111 enum {
3112         MLX5_CQC_STATUS_OK             = 0x0,
3113         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3114         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3115 };
3116
3117 enum {
3118         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3119         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3120 };
3121
3122 enum {
3123         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3124         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3125         MLX5_CQC_ST_FIRED                                 = 0xa,
3126 };
3127
3128 enum {
3129         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3130         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3131         MLX5_CQ_PERIOD_NUM_MODES
3132 };
3133
3134 struct mlx5_ifc_cqc_bits {
3135         u8         status[0x4];
3136         u8         reserved_at_4[0x2];
3137         u8         dbr_umem_valid[0x1];
3138         u8         reserved_at_7[0x1];
3139         u8         cqe_sz[0x3];
3140         u8         cc[0x1];
3141         u8         reserved_at_c[0x1];
3142         u8         scqe_break_moderation_en[0x1];
3143         u8         oi[0x1];
3144         u8         cq_period_mode[0x2];
3145         u8         cqe_comp_en[0x1];
3146         u8         mini_cqe_res_format[0x2];
3147         u8         st[0x4];
3148         u8         reserved_at_18[0x8];
3149
3150         u8         reserved_at_20[0x20];
3151
3152         u8         reserved_at_40[0x14];
3153         u8         page_offset[0x6];
3154         u8         reserved_at_5a[0x6];
3155
3156         u8         reserved_at_60[0x3];
3157         u8         log_cq_size[0x5];
3158         u8         uar_page[0x18];
3159
3160         u8         reserved_at_80[0x4];
3161         u8         cq_period[0xc];
3162         u8         cq_max_count[0x10];
3163
3164         u8         reserved_at_a0[0x18];
3165         u8         c_eqn[0x8];
3166
3167         u8         reserved_at_c0[0x3];
3168         u8         log_page_size[0x5];
3169         u8         reserved_at_c8[0x18];
3170
3171         u8         reserved_at_e0[0x20];
3172
3173         u8         reserved_at_100[0x8];
3174         u8         last_notified_index[0x18];
3175
3176         u8         reserved_at_120[0x8];
3177         u8         last_solicit_index[0x18];
3178
3179         u8         reserved_at_140[0x8];
3180         u8         consumer_counter[0x18];
3181
3182         u8         reserved_at_160[0x8];
3183         u8         producer_counter[0x18];
3184
3185         u8         reserved_at_180[0x40];
3186
3187         u8         dbr_addr[0x40];
3188 };
3189
3190 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3191         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3192         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3193         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3194         u8         reserved_at_0[0x800];
3195 };
3196
3197 struct mlx5_ifc_query_adapter_param_block_bits {
3198         u8         reserved_at_0[0xc0];
3199
3200         u8         reserved_at_c0[0x8];
3201         u8         ieee_vendor_id[0x18];
3202
3203         u8         reserved_at_e0[0x10];
3204         u8         vsd_vendor_id[0x10];
3205
3206         u8         vsd[208][0x8];
3207
3208         u8         vsd_contd_psid[16][0x8];
3209 };
3210
3211 enum {
3212         MLX5_XRQC_STATE_GOOD   = 0x0,
3213         MLX5_XRQC_STATE_ERROR  = 0x1,
3214 };
3215
3216 enum {
3217         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3218         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3219 };
3220
3221 enum {
3222         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3223 };
3224
3225 struct mlx5_ifc_tag_matching_topology_context_bits {
3226         u8         log_matching_list_sz[0x4];
3227         u8         reserved_at_4[0xc];
3228         u8         append_next_index[0x10];
3229
3230         u8         sw_phase_cnt[0x10];
3231         u8         hw_phase_cnt[0x10];
3232
3233         u8         reserved_at_40[0x40];
3234 };
3235
3236 struct mlx5_ifc_xrqc_bits {
3237         u8         state[0x4];
3238         u8         rlkey[0x1];
3239         u8         reserved_at_5[0xf];
3240         u8         topology[0x4];
3241         u8         reserved_at_18[0x4];
3242         u8         offload[0x4];
3243
3244         u8         reserved_at_20[0x8];
3245         u8         user_index[0x18];
3246
3247         u8         reserved_at_40[0x8];
3248         u8         cqn[0x18];
3249
3250         u8         reserved_at_60[0xa0];
3251
3252         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3253
3254         u8         reserved_at_180[0x280];
3255
3256         struct mlx5_ifc_wq_bits wq;
3257 };
3258
3259 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3260         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3261         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3262         u8         reserved_at_0[0x20];
3263 };
3264
3265 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3266         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3267         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3268         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3269         u8         reserved_at_0[0x20];
3270 };
3271
3272 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3273         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3274         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3275         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3276         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3277         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3278         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3279         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3280         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3281         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3282         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3283         u8         reserved_at_0[0x7c0];
3284 };
3285
3286 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3287         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3288         u8         reserved_at_0[0x7c0];
3289 };
3290
3291 union mlx5_ifc_event_auto_bits {
3292         struct mlx5_ifc_comp_event_bits comp_event;
3293         struct mlx5_ifc_dct_events_bits dct_events;
3294         struct mlx5_ifc_qp_events_bits qp_events;
3295         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3296         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3297         struct mlx5_ifc_cq_error_bits cq_error;
3298         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3299         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3300         struct mlx5_ifc_gpio_event_bits gpio_event;
3301         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3302         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3303         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3304         u8         reserved_at_0[0xe0];
3305 };
3306
3307 struct mlx5_ifc_health_buffer_bits {
3308         u8         reserved_at_0[0x100];
3309
3310         u8         assert_existptr[0x20];
3311
3312         u8         assert_callra[0x20];
3313
3314         u8         reserved_at_140[0x40];
3315
3316         u8         fw_version[0x20];
3317
3318         u8         hw_id[0x20];
3319
3320         u8         reserved_at_1c0[0x20];
3321
3322         u8         irisc_index[0x8];
3323         u8         synd[0x8];
3324         u8         ext_synd[0x10];
3325 };
3326
3327 struct mlx5_ifc_register_loopback_control_bits {
3328         u8         no_lb[0x1];
3329         u8         reserved_at_1[0x7];
3330         u8         port[0x8];
3331         u8         reserved_at_10[0x10];
3332
3333         u8         reserved_at_20[0x60];
3334 };
3335
3336 struct mlx5_ifc_vport_tc_element_bits {
3337         u8         traffic_class[0x4];
3338         u8         reserved_at_4[0xc];
3339         u8         vport_number[0x10];
3340 };
3341
3342 struct mlx5_ifc_vport_element_bits {
3343         u8         reserved_at_0[0x10];
3344         u8         vport_number[0x10];
3345 };
3346
3347 enum {
3348         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3349         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3350         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3351 };
3352
3353 struct mlx5_ifc_tsar_element_bits {
3354         u8         reserved_at_0[0x8];
3355         u8         tsar_type[0x8];
3356         u8         reserved_at_10[0x10];
3357 };
3358
3359 enum {
3360         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3361         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3362 };
3363
3364 struct mlx5_ifc_teardown_hca_out_bits {
3365         u8         status[0x8];
3366         u8         reserved_at_8[0x18];
3367
3368         u8         syndrome[0x20];
3369
3370         u8         reserved_at_40[0x3f];
3371
3372         u8         force_state[0x1];
3373 };
3374
3375 enum {
3376         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3377         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3378 };
3379
3380 struct mlx5_ifc_teardown_hca_in_bits {
3381         u8         opcode[0x10];
3382         u8         reserved_at_10[0x10];
3383
3384         u8         reserved_at_20[0x10];
3385         u8         op_mod[0x10];
3386
3387         u8         reserved_at_40[0x10];
3388         u8         profile[0x10];
3389
3390         u8         reserved_at_60[0x20];
3391 };
3392
3393 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3394         u8         status[0x8];
3395         u8         reserved_at_8[0x18];
3396
3397         u8         syndrome[0x20];
3398
3399         u8         reserved_at_40[0x40];
3400 };
3401
3402 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3403         u8         opcode[0x10];
3404         u8         uid[0x10];
3405
3406         u8         reserved_at_20[0x10];
3407         u8         op_mod[0x10];
3408
3409         u8         reserved_at_40[0x8];
3410         u8         qpn[0x18];
3411
3412         u8         reserved_at_60[0x20];
3413
3414         u8         opt_param_mask[0x20];
3415
3416         u8         reserved_at_a0[0x20];
3417
3418         struct mlx5_ifc_qpc_bits qpc;
3419
3420         u8         reserved_at_800[0x80];
3421 };
3422
3423 struct mlx5_ifc_sqd2rts_qp_out_bits {
3424         u8         status[0x8];
3425         u8         reserved_at_8[0x18];
3426
3427         u8         syndrome[0x20];
3428
3429         u8         reserved_at_40[0x40];
3430 };
3431
3432 struct mlx5_ifc_sqd2rts_qp_in_bits {
3433         u8         opcode[0x10];
3434         u8         uid[0x10];
3435
3436         u8         reserved_at_20[0x10];
3437         u8         op_mod[0x10];
3438
3439         u8         reserved_at_40[0x8];
3440         u8         qpn[0x18];
3441
3442         u8         reserved_at_60[0x20];
3443
3444         u8         opt_param_mask[0x20];
3445
3446         u8         reserved_at_a0[0x20];
3447
3448         struct mlx5_ifc_qpc_bits qpc;
3449
3450         u8         reserved_at_800[0x80];
3451 };
3452
3453 struct mlx5_ifc_set_roce_address_out_bits {
3454         u8         status[0x8];
3455         u8         reserved_at_8[0x18];
3456
3457         u8         syndrome[0x20];
3458
3459         u8         reserved_at_40[0x40];
3460 };
3461
3462 struct mlx5_ifc_set_roce_address_in_bits {
3463         u8         opcode[0x10];
3464         u8         reserved_at_10[0x10];
3465
3466         u8         reserved_at_20[0x10];
3467         u8         op_mod[0x10];
3468
3469         u8         roce_address_index[0x10];
3470         u8         reserved_at_50[0xc];
3471         u8         vhca_port_num[0x4];
3472
3473         u8         reserved_at_60[0x20];
3474
3475         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3476 };
3477
3478 struct mlx5_ifc_set_mad_demux_out_bits {
3479         u8         status[0x8];
3480         u8         reserved_at_8[0x18];
3481
3482         u8         syndrome[0x20];
3483
3484         u8         reserved_at_40[0x40];
3485 };
3486
3487 enum {
3488         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3489         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3490 };
3491
3492 struct mlx5_ifc_set_mad_demux_in_bits {
3493         u8         opcode[0x10];
3494         u8         reserved_at_10[0x10];
3495
3496         u8         reserved_at_20[0x10];
3497         u8         op_mod[0x10];
3498
3499         u8         reserved_at_40[0x20];
3500
3501         u8         reserved_at_60[0x6];
3502         u8         demux_mode[0x2];
3503         u8         reserved_at_68[0x18];
3504 };
3505
3506 struct mlx5_ifc_set_l2_table_entry_out_bits {
3507         u8         status[0x8];
3508         u8         reserved_at_8[0x18];
3509
3510         u8         syndrome[0x20];
3511
3512         u8         reserved_at_40[0x40];
3513 };
3514
3515 struct mlx5_ifc_set_l2_table_entry_in_bits {
3516         u8         opcode[0x10];
3517         u8         reserved_at_10[0x10];
3518
3519         u8         reserved_at_20[0x10];
3520         u8         op_mod[0x10];
3521
3522         u8         reserved_at_40[0x60];
3523
3524         u8         reserved_at_a0[0x8];
3525         u8         table_index[0x18];
3526
3527         u8         reserved_at_c0[0x20];
3528
3529         u8         reserved_at_e0[0x13];
3530         u8         vlan_valid[0x1];
3531         u8         vlan[0xc];
3532
3533         struct mlx5_ifc_mac_address_layout_bits mac_address;
3534
3535         u8         reserved_at_140[0xc0];
3536 };
3537
3538 struct mlx5_ifc_set_issi_out_bits {
3539         u8         status[0x8];
3540         u8         reserved_at_8[0x18];
3541
3542         u8         syndrome[0x20];
3543
3544         u8         reserved_at_40[0x40];
3545 };
3546
3547 struct mlx5_ifc_set_issi_in_bits {
3548         u8         opcode[0x10];
3549         u8         reserved_at_10[0x10];
3550
3551         u8         reserved_at_20[0x10];
3552         u8         op_mod[0x10];
3553
3554         u8         reserved_at_40[0x10];
3555         u8         current_issi[0x10];
3556
3557         u8         reserved_at_60[0x20];
3558 };
3559
3560 struct mlx5_ifc_set_hca_cap_out_bits {
3561         u8         status[0x8];
3562         u8         reserved_at_8[0x18];
3563
3564         u8         syndrome[0x20];
3565
3566         u8         reserved_at_40[0x40];
3567 };
3568
3569 struct mlx5_ifc_set_hca_cap_in_bits {
3570         u8         opcode[0x10];
3571         u8         reserved_at_10[0x10];
3572
3573         u8         reserved_at_20[0x10];
3574         u8         op_mod[0x10];
3575
3576         u8         reserved_at_40[0x40];
3577
3578         union mlx5_ifc_hca_cap_union_bits capability;
3579 };
3580
3581 enum {
3582         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3583         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3584         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3585         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3586 };
3587
3588 struct mlx5_ifc_set_fte_out_bits {
3589         u8         status[0x8];
3590         u8         reserved_at_8[0x18];
3591
3592         u8         syndrome[0x20];
3593
3594         u8         reserved_at_40[0x40];
3595 };
3596
3597 struct mlx5_ifc_set_fte_in_bits {
3598         u8         opcode[0x10];
3599         u8         reserved_at_10[0x10];
3600
3601         u8         reserved_at_20[0x10];
3602         u8         op_mod[0x10];
3603
3604         u8         other_vport[0x1];
3605         u8         reserved_at_41[0xf];
3606         u8         vport_number[0x10];
3607
3608         u8         reserved_at_60[0x20];
3609
3610         u8         table_type[0x8];
3611         u8         reserved_at_88[0x18];
3612
3613         u8         reserved_at_a0[0x8];
3614         u8         table_id[0x18];
3615
3616         u8         reserved_at_c0[0x18];
3617         u8         modify_enable_mask[0x8];
3618
3619         u8         reserved_at_e0[0x20];
3620
3621         u8         flow_index[0x20];
3622
3623         u8         reserved_at_120[0xe0];
3624
3625         struct mlx5_ifc_flow_context_bits flow_context;
3626 };
3627
3628 struct mlx5_ifc_rts2rts_qp_out_bits {
3629         u8         status[0x8];
3630         u8         reserved_at_8[0x18];
3631
3632         u8         syndrome[0x20];
3633
3634         u8         reserved_at_40[0x40];
3635 };
3636
3637 struct mlx5_ifc_rts2rts_qp_in_bits {
3638         u8         opcode[0x10];
3639         u8         uid[0x10];
3640
3641         u8         reserved_at_20[0x10];
3642         u8         op_mod[0x10];
3643
3644         u8         reserved_at_40[0x8];
3645         u8         qpn[0x18];
3646
3647         u8         reserved_at_60[0x20];
3648
3649         u8         opt_param_mask[0x20];
3650
3651         u8         reserved_at_a0[0x20];
3652
3653         struct mlx5_ifc_qpc_bits qpc;
3654
3655         u8         reserved_at_800[0x80];
3656 };
3657
3658 struct mlx5_ifc_rtr2rts_qp_out_bits {
3659         u8         status[0x8];
3660         u8         reserved_at_8[0x18];
3661
3662         u8         syndrome[0x20];
3663
3664         u8         reserved_at_40[0x40];
3665 };
3666
3667 struct mlx5_ifc_rtr2rts_qp_in_bits {
3668         u8         opcode[0x10];
3669         u8         uid[0x10];
3670
3671         u8         reserved_at_20[0x10];
3672         u8         op_mod[0x10];
3673
3674         u8         reserved_at_40[0x8];
3675         u8         qpn[0x18];
3676
3677         u8         reserved_at_60[0x20];
3678
3679         u8         opt_param_mask[0x20];
3680
3681         u8         reserved_at_a0[0x20];
3682
3683         struct mlx5_ifc_qpc_bits qpc;
3684
3685         u8         reserved_at_800[0x80];
3686 };
3687
3688 struct mlx5_ifc_rst2init_qp_out_bits {
3689         u8         status[0x8];
3690         u8         reserved_at_8[0x18];
3691
3692         u8         syndrome[0x20];
3693
3694         u8         reserved_at_40[0x40];
3695 };
3696
3697 struct mlx5_ifc_rst2init_qp_in_bits {
3698         u8         opcode[0x10];
3699         u8         uid[0x10];
3700
3701         u8         reserved_at_20[0x10];
3702         u8         op_mod[0x10];
3703
3704         u8         reserved_at_40[0x8];
3705         u8         qpn[0x18];
3706
3707         u8         reserved_at_60[0x20];
3708
3709         u8         opt_param_mask[0x20];
3710
3711         u8         reserved_at_a0[0x20];
3712
3713         struct mlx5_ifc_qpc_bits qpc;
3714
3715         u8         reserved_at_800[0x80];
3716 };
3717
3718 struct mlx5_ifc_query_xrq_out_bits {
3719         u8         status[0x8];
3720         u8         reserved_at_8[0x18];
3721
3722         u8         syndrome[0x20];
3723
3724         u8         reserved_at_40[0x40];
3725
3726         struct mlx5_ifc_xrqc_bits xrq_context;
3727 };
3728
3729 struct mlx5_ifc_query_xrq_in_bits {
3730         u8         opcode[0x10];
3731         u8         reserved_at_10[0x10];
3732
3733         u8         reserved_at_20[0x10];
3734         u8         op_mod[0x10];
3735
3736         u8         reserved_at_40[0x8];
3737         u8         xrqn[0x18];
3738
3739         u8         reserved_at_60[0x20];
3740 };
3741
3742 struct mlx5_ifc_query_xrc_srq_out_bits {
3743         u8         status[0x8];
3744         u8         reserved_at_8[0x18];
3745
3746         u8         syndrome[0x20];
3747
3748         u8         reserved_at_40[0x40];
3749
3750         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3751
3752         u8         reserved_at_280[0x600];
3753
3754         u8         pas[0][0x40];
3755 };
3756
3757 struct mlx5_ifc_query_xrc_srq_in_bits {
3758         u8         opcode[0x10];
3759         u8         reserved_at_10[0x10];
3760
3761         u8         reserved_at_20[0x10];
3762         u8         op_mod[0x10];
3763
3764         u8         reserved_at_40[0x8];
3765         u8         xrc_srqn[0x18];
3766
3767         u8         reserved_at_60[0x20];
3768 };
3769
3770 enum {
3771         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3772         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3773 };
3774
3775 struct mlx5_ifc_query_vport_state_out_bits {
3776         u8         status[0x8];
3777         u8         reserved_at_8[0x18];
3778
3779         u8         syndrome[0x20];
3780
3781         u8         reserved_at_40[0x20];
3782
3783         u8         reserved_at_60[0x18];
3784         u8         admin_state[0x4];
3785         u8         state[0x4];
3786 };
3787
3788 enum {
3789         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
3790         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
3791 };
3792
3793 struct mlx5_ifc_query_vport_state_in_bits {
3794         u8         opcode[0x10];
3795         u8         reserved_at_10[0x10];
3796
3797         u8         reserved_at_20[0x10];
3798         u8         op_mod[0x10];
3799
3800         u8         other_vport[0x1];
3801         u8         reserved_at_41[0xf];
3802         u8         vport_number[0x10];
3803
3804         u8         reserved_at_60[0x20];
3805 };
3806
3807 struct mlx5_ifc_query_vnic_env_out_bits {
3808         u8         status[0x8];
3809         u8         reserved_at_8[0x18];
3810
3811         u8         syndrome[0x20];
3812
3813         u8         reserved_at_40[0x40];
3814
3815         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3816 };
3817
3818 enum {
3819         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3820 };
3821
3822 struct mlx5_ifc_query_vnic_env_in_bits {
3823         u8         opcode[0x10];
3824         u8         reserved_at_10[0x10];
3825
3826         u8         reserved_at_20[0x10];
3827         u8         op_mod[0x10];
3828
3829         u8         other_vport[0x1];
3830         u8         reserved_at_41[0xf];
3831         u8         vport_number[0x10];
3832
3833         u8         reserved_at_60[0x20];
3834 };
3835
3836 struct mlx5_ifc_query_vport_counter_out_bits {
3837         u8         status[0x8];
3838         u8         reserved_at_8[0x18];
3839
3840         u8         syndrome[0x20];
3841
3842         u8         reserved_at_40[0x40];
3843
3844         struct mlx5_ifc_traffic_counter_bits received_errors;
3845
3846         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3847
3848         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3849
3850         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3851
3852         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3853
3854         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3855
3856         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3857
3858         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3859
3860         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3861
3862         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3863
3864         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3865
3866         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3867
3868         u8         reserved_at_680[0xa00];
3869 };
3870
3871 enum {
3872         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3873 };
3874
3875 struct mlx5_ifc_query_vport_counter_in_bits {
3876         u8         opcode[0x10];
3877         u8         reserved_at_10[0x10];
3878
3879         u8         reserved_at_20[0x10];
3880         u8         op_mod[0x10];
3881
3882         u8         other_vport[0x1];
3883         u8         reserved_at_41[0xb];
3884         u8         port_num[0x4];
3885         u8         vport_number[0x10];
3886
3887         u8         reserved_at_60[0x60];
3888
3889         u8         clear[0x1];
3890         u8         reserved_at_c1[0x1f];
3891
3892         u8         reserved_at_e0[0x20];
3893 };
3894
3895 struct mlx5_ifc_query_tis_out_bits {
3896         u8         status[0x8];
3897         u8         reserved_at_8[0x18];
3898
3899         u8         syndrome[0x20];
3900
3901         u8         reserved_at_40[0x40];
3902
3903         struct mlx5_ifc_tisc_bits tis_context;
3904 };
3905
3906 struct mlx5_ifc_query_tis_in_bits {
3907         u8         opcode[0x10];
3908         u8         reserved_at_10[0x10];
3909
3910         u8         reserved_at_20[0x10];
3911         u8         op_mod[0x10];
3912
3913         u8         reserved_at_40[0x8];
3914         u8         tisn[0x18];
3915
3916         u8         reserved_at_60[0x20];
3917 };
3918
3919 struct mlx5_ifc_query_tir_out_bits {
3920         u8         status[0x8];
3921         u8         reserved_at_8[0x18];
3922
3923         u8         syndrome[0x20];
3924
3925         u8         reserved_at_40[0xc0];
3926
3927         struct mlx5_ifc_tirc_bits tir_context;
3928 };
3929
3930 struct mlx5_ifc_query_tir_in_bits {
3931         u8         opcode[0x10];
3932         u8         reserved_at_10[0x10];
3933
3934         u8         reserved_at_20[0x10];
3935         u8         op_mod[0x10];
3936
3937         u8         reserved_at_40[0x8];
3938         u8         tirn[0x18];
3939
3940         u8         reserved_at_60[0x20];
3941 };
3942
3943 struct mlx5_ifc_query_srq_out_bits {
3944         u8         status[0x8];
3945         u8         reserved_at_8[0x18];
3946
3947         u8         syndrome[0x20];
3948
3949         u8         reserved_at_40[0x40];
3950
3951         struct mlx5_ifc_srqc_bits srq_context_entry;
3952
3953         u8         reserved_at_280[0x600];
3954
3955         u8         pas[0][0x40];
3956 };
3957
3958 struct mlx5_ifc_query_srq_in_bits {
3959         u8         opcode[0x10];
3960         u8         reserved_at_10[0x10];
3961
3962         u8         reserved_at_20[0x10];
3963         u8         op_mod[0x10];
3964
3965         u8         reserved_at_40[0x8];
3966         u8         srqn[0x18];
3967
3968         u8         reserved_at_60[0x20];
3969 };
3970
3971 struct mlx5_ifc_query_sq_out_bits {
3972         u8         status[0x8];
3973         u8         reserved_at_8[0x18];
3974
3975         u8         syndrome[0x20];
3976
3977         u8         reserved_at_40[0xc0];
3978
3979         struct mlx5_ifc_sqc_bits sq_context;
3980 };
3981
3982 struct mlx5_ifc_query_sq_in_bits {
3983         u8         opcode[0x10];
3984         u8         reserved_at_10[0x10];
3985
3986         u8         reserved_at_20[0x10];
3987         u8         op_mod[0x10];
3988
3989         u8         reserved_at_40[0x8];
3990         u8         sqn[0x18];
3991
3992         u8         reserved_at_60[0x20];
3993 };
3994
3995 struct mlx5_ifc_query_special_contexts_out_bits {
3996         u8         status[0x8];
3997         u8         reserved_at_8[0x18];
3998
3999         u8         syndrome[0x20];
4000
4001         u8         dump_fill_mkey[0x20];
4002
4003         u8         resd_lkey[0x20];
4004
4005         u8         null_mkey[0x20];
4006
4007         u8         reserved_at_a0[0x60];
4008 };
4009
4010 struct mlx5_ifc_query_special_contexts_in_bits {
4011         u8         opcode[0x10];
4012         u8         reserved_at_10[0x10];
4013
4014         u8         reserved_at_20[0x10];
4015         u8         op_mod[0x10];
4016
4017         u8         reserved_at_40[0x40];
4018 };
4019
4020 struct mlx5_ifc_query_scheduling_element_out_bits {
4021         u8         opcode[0x10];
4022         u8         reserved_at_10[0x10];
4023
4024         u8         reserved_at_20[0x10];
4025         u8         op_mod[0x10];
4026
4027         u8         reserved_at_40[0xc0];
4028
4029         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4030
4031         u8         reserved_at_300[0x100];
4032 };
4033
4034 enum {
4035         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4036 };
4037
4038 struct mlx5_ifc_query_scheduling_element_in_bits {
4039         u8         opcode[0x10];
4040         u8         reserved_at_10[0x10];
4041
4042         u8         reserved_at_20[0x10];
4043         u8         op_mod[0x10];
4044
4045         u8         scheduling_hierarchy[0x8];
4046         u8         reserved_at_48[0x18];
4047
4048         u8         scheduling_element_id[0x20];
4049
4050         u8         reserved_at_80[0x180];
4051 };
4052
4053 struct mlx5_ifc_query_rqt_out_bits {
4054         u8         status[0x8];
4055         u8         reserved_at_8[0x18];
4056
4057         u8         syndrome[0x20];
4058
4059         u8         reserved_at_40[0xc0];
4060
4061         struct mlx5_ifc_rqtc_bits rqt_context;
4062 };
4063
4064 struct mlx5_ifc_query_rqt_in_bits {
4065         u8         opcode[0x10];
4066         u8         reserved_at_10[0x10];
4067
4068         u8         reserved_at_20[0x10];
4069         u8         op_mod[0x10];
4070
4071         u8         reserved_at_40[0x8];
4072         u8         rqtn[0x18];
4073
4074         u8         reserved_at_60[0x20];
4075 };
4076
4077 struct mlx5_ifc_query_rq_out_bits {
4078         u8         status[0x8];
4079         u8         reserved_at_8[0x18];
4080
4081         u8         syndrome[0x20];
4082
4083         u8         reserved_at_40[0xc0];
4084
4085         struct mlx5_ifc_rqc_bits rq_context;
4086 };
4087
4088 struct mlx5_ifc_query_rq_in_bits {
4089         u8         opcode[0x10];
4090         u8         reserved_at_10[0x10];
4091
4092         u8         reserved_at_20[0x10];
4093         u8         op_mod[0x10];
4094
4095         u8         reserved_at_40[0x8];
4096         u8         rqn[0x18];
4097
4098         u8         reserved_at_60[0x20];
4099 };
4100
4101 struct mlx5_ifc_query_roce_address_out_bits {
4102         u8         status[0x8];
4103         u8         reserved_at_8[0x18];
4104
4105         u8         syndrome[0x20];
4106
4107         u8         reserved_at_40[0x40];
4108
4109         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4110 };
4111
4112 struct mlx5_ifc_query_roce_address_in_bits {
4113         u8         opcode[0x10];
4114         u8         reserved_at_10[0x10];
4115
4116         u8         reserved_at_20[0x10];
4117         u8         op_mod[0x10];
4118
4119         u8         roce_address_index[0x10];
4120         u8         reserved_at_50[0xc];
4121         u8         vhca_port_num[0x4];
4122
4123         u8         reserved_at_60[0x20];
4124 };
4125
4126 struct mlx5_ifc_query_rmp_out_bits {
4127         u8         status[0x8];
4128         u8         reserved_at_8[0x18];
4129
4130         u8         syndrome[0x20];
4131
4132         u8         reserved_at_40[0xc0];
4133
4134         struct mlx5_ifc_rmpc_bits rmp_context;
4135 };
4136
4137 struct mlx5_ifc_query_rmp_in_bits {
4138         u8         opcode[0x10];
4139         u8         reserved_at_10[0x10];
4140
4141         u8         reserved_at_20[0x10];
4142         u8         op_mod[0x10];
4143
4144         u8         reserved_at_40[0x8];
4145         u8         rmpn[0x18];
4146
4147         u8         reserved_at_60[0x20];
4148 };
4149
4150 struct mlx5_ifc_query_qp_out_bits {
4151         u8         status[0x8];
4152         u8         reserved_at_8[0x18];
4153
4154         u8         syndrome[0x20];
4155
4156         u8         reserved_at_40[0x40];
4157
4158         u8         opt_param_mask[0x20];
4159
4160         u8         reserved_at_a0[0x20];
4161
4162         struct mlx5_ifc_qpc_bits qpc;
4163
4164         u8         reserved_at_800[0x80];
4165
4166         u8         pas[0][0x40];
4167 };
4168
4169 struct mlx5_ifc_query_qp_in_bits {
4170         u8         opcode[0x10];
4171         u8         reserved_at_10[0x10];
4172
4173         u8         reserved_at_20[0x10];
4174         u8         op_mod[0x10];
4175
4176         u8         reserved_at_40[0x8];
4177         u8         qpn[0x18];
4178
4179         u8         reserved_at_60[0x20];
4180 };
4181
4182 struct mlx5_ifc_query_q_counter_out_bits {
4183         u8         status[0x8];
4184         u8         reserved_at_8[0x18];
4185
4186         u8         syndrome[0x20];
4187
4188         u8         reserved_at_40[0x40];
4189
4190         u8         rx_write_requests[0x20];
4191
4192         u8         reserved_at_a0[0x20];
4193
4194         u8         rx_read_requests[0x20];
4195
4196         u8         reserved_at_e0[0x20];
4197
4198         u8         rx_atomic_requests[0x20];
4199
4200         u8         reserved_at_120[0x20];
4201
4202         u8         rx_dct_connect[0x20];
4203
4204         u8         reserved_at_160[0x20];
4205
4206         u8         out_of_buffer[0x20];
4207
4208         u8         reserved_at_1a0[0x20];
4209
4210         u8         out_of_sequence[0x20];
4211
4212         u8         reserved_at_1e0[0x20];
4213
4214         u8         duplicate_request[0x20];
4215
4216         u8         reserved_at_220[0x20];
4217
4218         u8         rnr_nak_retry_err[0x20];
4219
4220         u8         reserved_at_260[0x20];
4221
4222         u8         packet_seq_err[0x20];
4223
4224         u8         reserved_at_2a0[0x20];
4225
4226         u8         implied_nak_seq_err[0x20];
4227
4228         u8         reserved_at_2e0[0x20];
4229
4230         u8         local_ack_timeout_err[0x20];
4231
4232         u8         reserved_at_320[0xa0];
4233
4234         u8         resp_local_length_error[0x20];
4235
4236         u8         req_local_length_error[0x20];
4237
4238         u8         resp_local_qp_error[0x20];
4239
4240         u8         local_operation_error[0x20];
4241
4242         u8         resp_local_protection[0x20];
4243
4244         u8         req_local_protection[0x20];
4245
4246         u8         resp_cqe_error[0x20];
4247
4248         u8         req_cqe_error[0x20];
4249
4250         u8         req_mw_binding[0x20];
4251
4252         u8         req_bad_response[0x20];
4253
4254         u8         req_remote_invalid_request[0x20];
4255
4256         u8         resp_remote_invalid_request[0x20];
4257
4258         u8         req_remote_access_errors[0x20];
4259
4260         u8         resp_remote_access_errors[0x20];
4261
4262         u8         req_remote_operation_errors[0x20];
4263
4264         u8         req_transport_retries_exceeded[0x20];
4265
4266         u8         cq_overflow[0x20];
4267
4268         u8         resp_cqe_flush_error[0x20];
4269
4270         u8         req_cqe_flush_error[0x20];
4271
4272         u8         reserved_at_620[0x1e0];
4273 };
4274
4275 struct mlx5_ifc_query_q_counter_in_bits {
4276         u8         opcode[0x10];
4277         u8         reserved_at_10[0x10];
4278
4279         u8         reserved_at_20[0x10];
4280         u8         op_mod[0x10];
4281
4282         u8         reserved_at_40[0x80];
4283
4284         u8         clear[0x1];
4285         u8         reserved_at_c1[0x1f];
4286
4287         u8         reserved_at_e0[0x18];
4288         u8         counter_set_id[0x8];
4289 };
4290
4291 struct mlx5_ifc_query_pages_out_bits {
4292         u8         status[0x8];
4293         u8         reserved_at_8[0x18];
4294
4295         u8         syndrome[0x20];
4296
4297         u8         reserved_at_40[0x10];
4298         u8         function_id[0x10];
4299
4300         u8         num_pages[0x20];
4301 };
4302
4303 enum {
4304         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4305         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4306         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4307 };
4308
4309 struct mlx5_ifc_query_pages_in_bits {
4310         u8         opcode[0x10];
4311         u8         reserved_at_10[0x10];
4312
4313         u8         reserved_at_20[0x10];
4314         u8         op_mod[0x10];
4315
4316         u8         reserved_at_40[0x10];
4317         u8         function_id[0x10];
4318
4319         u8         reserved_at_60[0x20];
4320 };
4321
4322 struct mlx5_ifc_query_nic_vport_context_out_bits {
4323         u8         status[0x8];
4324         u8         reserved_at_8[0x18];
4325
4326         u8         syndrome[0x20];
4327
4328         u8         reserved_at_40[0x40];
4329
4330         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4331 };
4332
4333 struct mlx5_ifc_query_nic_vport_context_in_bits {
4334         u8         opcode[0x10];
4335         u8         reserved_at_10[0x10];
4336
4337         u8         reserved_at_20[0x10];
4338         u8         op_mod[0x10];
4339
4340         u8         other_vport[0x1];
4341         u8         reserved_at_41[0xf];
4342         u8         vport_number[0x10];
4343
4344         u8         reserved_at_60[0x5];
4345         u8         allowed_list_type[0x3];
4346         u8         reserved_at_68[0x18];
4347 };
4348
4349 struct mlx5_ifc_query_mkey_out_bits {
4350         u8         status[0x8];
4351         u8         reserved_at_8[0x18];
4352
4353         u8         syndrome[0x20];
4354
4355         u8         reserved_at_40[0x40];
4356
4357         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4358
4359         u8         reserved_at_280[0x600];
4360
4361         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4362
4363         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4364 };
4365
4366 struct mlx5_ifc_query_mkey_in_bits {
4367         u8         opcode[0x10];
4368         u8         reserved_at_10[0x10];
4369
4370         u8         reserved_at_20[0x10];
4371         u8         op_mod[0x10];
4372
4373         u8         reserved_at_40[0x8];
4374         u8         mkey_index[0x18];
4375
4376         u8         pg_access[0x1];
4377         u8         reserved_at_61[0x1f];
4378 };
4379
4380 struct mlx5_ifc_query_mad_demux_out_bits {
4381         u8         status[0x8];
4382         u8         reserved_at_8[0x18];
4383
4384         u8         syndrome[0x20];
4385
4386         u8         reserved_at_40[0x40];
4387
4388         u8         mad_dumux_parameters_block[0x20];
4389 };
4390
4391 struct mlx5_ifc_query_mad_demux_in_bits {
4392         u8         opcode[0x10];
4393         u8         reserved_at_10[0x10];
4394
4395         u8         reserved_at_20[0x10];
4396         u8         op_mod[0x10];
4397
4398         u8         reserved_at_40[0x40];
4399 };
4400
4401 struct mlx5_ifc_query_l2_table_entry_out_bits {
4402         u8         status[0x8];
4403         u8         reserved_at_8[0x18];
4404
4405         u8         syndrome[0x20];
4406
4407         u8         reserved_at_40[0xa0];
4408
4409         u8         reserved_at_e0[0x13];
4410         u8         vlan_valid[0x1];
4411         u8         vlan[0xc];
4412
4413         struct mlx5_ifc_mac_address_layout_bits mac_address;
4414
4415         u8         reserved_at_140[0xc0];
4416 };
4417
4418 struct mlx5_ifc_query_l2_table_entry_in_bits {
4419         u8         opcode[0x10];
4420         u8         reserved_at_10[0x10];
4421
4422         u8         reserved_at_20[0x10];
4423         u8         op_mod[0x10];
4424
4425         u8         reserved_at_40[0x60];
4426
4427         u8         reserved_at_a0[0x8];
4428         u8         table_index[0x18];
4429
4430         u8         reserved_at_c0[0x140];
4431 };
4432
4433 struct mlx5_ifc_query_issi_out_bits {
4434         u8         status[0x8];
4435         u8         reserved_at_8[0x18];
4436
4437         u8         syndrome[0x20];
4438
4439         u8         reserved_at_40[0x10];
4440         u8         current_issi[0x10];
4441
4442         u8         reserved_at_60[0xa0];
4443
4444         u8         reserved_at_100[76][0x8];
4445         u8         supported_issi_dw0[0x20];
4446 };
4447
4448 struct mlx5_ifc_query_issi_in_bits {
4449         u8         opcode[0x10];
4450         u8         reserved_at_10[0x10];
4451
4452         u8         reserved_at_20[0x10];
4453         u8         op_mod[0x10];
4454
4455         u8         reserved_at_40[0x40];
4456 };
4457
4458 struct mlx5_ifc_set_driver_version_out_bits {
4459         u8         status[0x8];
4460         u8         reserved_0[0x18];
4461
4462         u8         syndrome[0x20];
4463         u8         reserved_1[0x40];
4464 };
4465
4466 struct mlx5_ifc_set_driver_version_in_bits {
4467         u8         opcode[0x10];
4468         u8         reserved_0[0x10];
4469
4470         u8         reserved_1[0x10];
4471         u8         op_mod[0x10];
4472
4473         u8         reserved_2[0x40];
4474         u8         driver_version[64][0x8];
4475 };
4476
4477 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4478         u8         status[0x8];
4479         u8         reserved_at_8[0x18];
4480
4481         u8         syndrome[0x20];
4482
4483         u8         reserved_at_40[0x40];
4484
4485         struct mlx5_ifc_pkey_bits pkey[0];
4486 };
4487
4488 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4489         u8         opcode[0x10];
4490         u8         reserved_at_10[0x10];
4491
4492         u8         reserved_at_20[0x10];
4493         u8         op_mod[0x10];
4494
4495         u8         other_vport[0x1];
4496         u8         reserved_at_41[0xb];
4497         u8         port_num[0x4];
4498         u8         vport_number[0x10];
4499
4500         u8         reserved_at_60[0x10];
4501         u8         pkey_index[0x10];
4502 };
4503
4504 enum {
4505         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4506         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4507         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4508 };
4509
4510 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4511         u8         status[0x8];
4512         u8         reserved_at_8[0x18];
4513
4514         u8         syndrome[0x20];
4515
4516         u8         reserved_at_40[0x20];
4517
4518         u8         gids_num[0x10];
4519         u8         reserved_at_70[0x10];
4520
4521         struct mlx5_ifc_array128_auto_bits gid[0];
4522 };
4523
4524 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4525         u8         opcode[0x10];
4526         u8         reserved_at_10[0x10];
4527
4528         u8         reserved_at_20[0x10];
4529         u8         op_mod[0x10];
4530
4531         u8         other_vport[0x1];
4532         u8         reserved_at_41[0xb];
4533         u8         port_num[0x4];
4534         u8         vport_number[0x10];
4535
4536         u8         reserved_at_60[0x10];
4537         u8         gid_index[0x10];
4538 };
4539
4540 struct mlx5_ifc_query_hca_vport_context_out_bits {
4541         u8         status[0x8];
4542         u8         reserved_at_8[0x18];
4543
4544         u8         syndrome[0x20];
4545
4546         u8         reserved_at_40[0x40];
4547
4548         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4549 };
4550
4551 struct mlx5_ifc_query_hca_vport_context_in_bits {
4552         u8         opcode[0x10];
4553         u8         reserved_at_10[0x10];
4554
4555         u8         reserved_at_20[0x10];
4556         u8         op_mod[0x10];
4557
4558         u8         other_vport[0x1];
4559         u8         reserved_at_41[0xb];
4560         u8         port_num[0x4];
4561         u8         vport_number[0x10];
4562
4563         u8         reserved_at_60[0x20];
4564 };
4565
4566 struct mlx5_ifc_query_hca_cap_out_bits {
4567         u8         status[0x8];
4568         u8         reserved_at_8[0x18];
4569
4570         u8         syndrome[0x20];
4571
4572         u8         reserved_at_40[0x40];
4573
4574         union mlx5_ifc_hca_cap_union_bits capability;
4575 };
4576
4577 struct mlx5_ifc_query_hca_cap_in_bits {
4578         u8         opcode[0x10];
4579         u8         reserved_at_10[0x10];
4580
4581         u8         reserved_at_20[0x10];
4582         u8         op_mod[0x10];
4583
4584         u8         reserved_at_40[0x40];
4585 };
4586
4587 struct mlx5_ifc_query_flow_table_out_bits {
4588         u8         status[0x8];
4589         u8         reserved_at_8[0x18];
4590
4591         u8         syndrome[0x20];
4592
4593         u8         reserved_at_40[0x80];
4594
4595         u8         reserved_at_c0[0x8];
4596         u8         level[0x8];
4597         u8         reserved_at_d0[0x8];
4598         u8         log_size[0x8];
4599
4600         u8         reserved_at_e0[0x120];
4601 };
4602
4603 struct mlx5_ifc_query_flow_table_in_bits {
4604         u8         opcode[0x10];
4605         u8         reserved_at_10[0x10];
4606
4607         u8         reserved_at_20[0x10];
4608         u8         op_mod[0x10];
4609
4610         u8         reserved_at_40[0x40];
4611
4612         u8         table_type[0x8];
4613         u8         reserved_at_88[0x18];
4614
4615         u8         reserved_at_a0[0x8];
4616         u8         table_id[0x18];
4617
4618         u8         reserved_at_c0[0x140];
4619 };
4620
4621 struct mlx5_ifc_query_fte_out_bits {
4622         u8         status[0x8];
4623         u8         reserved_at_8[0x18];
4624
4625         u8         syndrome[0x20];
4626
4627         u8         reserved_at_40[0x1c0];
4628
4629         struct mlx5_ifc_flow_context_bits flow_context;
4630 };
4631
4632 struct mlx5_ifc_query_fte_in_bits {
4633         u8         opcode[0x10];
4634         u8         reserved_at_10[0x10];
4635
4636         u8         reserved_at_20[0x10];
4637         u8         op_mod[0x10];
4638
4639         u8         reserved_at_40[0x40];
4640
4641         u8         table_type[0x8];
4642         u8         reserved_at_88[0x18];
4643
4644         u8         reserved_at_a0[0x8];
4645         u8         table_id[0x18];
4646
4647         u8         reserved_at_c0[0x40];
4648
4649         u8         flow_index[0x20];
4650
4651         u8         reserved_at_120[0xe0];
4652 };
4653
4654 enum {
4655         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4656         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4657         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4658         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4659 };
4660
4661 struct mlx5_ifc_query_flow_group_out_bits {
4662         u8         status[0x8];
4663         u8         reserved_at_8[0x18];
4664
4665         u8         syndrome[0x20];
4666
4667         u8         reserved_at_40[0xa0];
4668
4669         u8         start_flow_index[0x20];
4670
4671         u8         reserved_at_100[0x20];
4672
4673         u8         end_flow_index[0x20];
4674
4675         u8         reserved_at_140[0xa0];
4676
4677         u8         reserved_at_1e0[0x18];
4678         u8         match_criteria_enable[0x8];
4679
4680         struct mlx5_ifc_fte_match_param_bits match_criteria;
4681
4682         u8         reserved_at_1200[0xe00];
4683 };
4684
4685 struct mlx5_ifc_query_flow_group_in_bits {
4686         u8         opcode[0x10];
4687         u8         reserved_at_10[0x10];
4688
4689         u8         reserved_at_20[0x10];
4690         u8         op_mod[0x10];
4691
4692         u8         reserved_at_40[0x40];
4693
4694         u8         table_type[0x8];
4695         u8         reserved_at_88[0x18];
4696
4697         u8         reserved_at_a0[0x8];
4698         u8         table_id[0x18];
4699
4700         u8         group_id[0x20];
4701
4702         u8         reserved_at_e0[0x120];
4703 };
4704
4705 struct mlx5_ifc_query_flow_counter_out_bits {
4706         u8         status[0x8];
4707         u8         reserved_at_8[0x18];
4708
4709         u8         syndrome[0x20];
4710
4711         u8         reserved_at_40[0x40];
4712
4713         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4714 };
4715
4716 struct mlx5_ifc_query_flow_counter_in_bits {
4717         u8         opcode[0x10];
4718         u8         reserved_at_10[0x10];
4719
4720         u8         reserved_at_20[0x10];
4721         u8         op_mod[0x10];
4722
4723         u8         reserved_at_40[0x80];
4724
4725         u8         clear[0x1];
4726         u8         reserved_at_c1[0xf];
4727         u8         num_of_counters[0x10];
4728
4729         u8         flow_counter_id[0x20];
4730 };
4731
4732 struct mlx5_ifc_query_esw_vport_context_out_bits {
4733         u8         status[0x8];
4734         u8         reserved_at_8[0x18];
4735
4736         u8         syndrome[0x20];
4737
4738         u8         reserved_at_40[0x40];
4739
4740         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4741 };
4742
4743 struct mlx5_ifc_query_esw_vport_context_in_bits {
4744         u8         opcode[0x10];
4745         u8         reserved_at_10[0x10];
4746
4747         u8         reserved_at_20[0x10];
4748         u8         op_mod[0x10];
4749
4750         u8         other_vport[0x1];
4751         u8         reserved_at_41[0xf];
4752         u8         vport_number[0x10];
4753
4754         u8         reserved_at_60[0x20];
4755 };
4756
4757 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4758         u8         status[0x8];
4759         u8         reserved_at_8[0x18];
4760
4761         u8         syndrome[0x20];
4762
4763         u8         reserved_at_40[0x40];
4764 };
4765
4766 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4767         u8         reserved_at_0[0x1c];
4768         u8         vport_cvlan_insert[0x1];
4769         u8         vport_svlan_insert[0x1];
4770         u8         vport_cvlan_strip[0x1];
4771         u8         vport_svlan_strip[0x1];
4772 };
4773
4774 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4775         u8         opcode[0x10];
4776         u8         reserved_at_10[0x10];
4777
4778         u8         reserved_at_20[0x10];
4779         u8         op_mod[0x10];
4780
4781         u8         other_vport[0x1];
4782         u8         reserved_at_41[0xf];
4783         u8         vport_number[0x10];
4784
4785         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4786
4787         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4788 };
4789
4790 struct mlx5_ifc_query_eq_out_bits {
4791         u8         status[0x8];
4792         u8         reserved_at_8[0x18];
4793
4794         u8         syndrome[0x20];
4795
4796         u8         reserved_at_40[0x40];
4797
4798         struct mlx5_ifc_eqc_bits eq_context_entry;
4799
4800         u8         reserved_at_280[0x40];
4801
4802         u8         event_bitmask[0x40];
4803
4804         u8         reserved_at_300[0x580];
4805
4806         u8         pas[0][0x40];
4807 };
4808
4809 struct mlx5_ifc_query_eq_in_bits {
4810         u8         opcode[0x10];
4811         u8         reserved_at_10[0x10];
4812
4813         u8         reserved_at_20[0x10];
4814         u8         op_mod[0x10];
4815
4816         u8         reserved_at_40[0x18];
4817         u8         eq_number[0x8];
4818
4819         u8         reserved_at_60[0x20];
4820 };
4821
4822 struct mlx5_ifc_packet_reformat_context_in_bits {
4823         u8         reserved_at_0[0x5];
4824         u8         reformat_type[0x3];
4825         u8         reserved_at_8[0xe];
4826         u8         reformat_data_size[0xa];
4827
4828         u8         reserved_at_20[0x10];
4829         u8         reformat_data[2][0x8];
4830
4831         u8         more_reformat_data[0][0x8];
4832 };
4833
4834 struct mlx5_ifc_query_packet_reformat_context_out_bits {
4835         u8         status[0x8];
4836         u8         reserved_at_8[0x18];
4837
4838         u8         syndrome[0x20];
4839
4840         u8         reserved_at_40[0xa0];
4841
4842         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
4843 };
4844
4845 struct mlx5_ifc_query_packet_reformat_context_in_bits {
4846         u8         opcode[0x10];
4847         u8         reserved_at_10[0x10];
4848
4849         u8         reserved_at_20[0x10];
4850         u8         op_mod[0x10];
4851
4852         u8         packet_reformat_id[0x20];
4853
4854         u8         reserved_at_60[0xa0];
4855 };
4856
4857 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
4858         u8         status[0x8];
4859         u8         reserved_at_8[0x18];
4860
4861         u8         syndrome[0x20];
4862
4863         u8         packet_reformat_id[0x20];
4864
4865         u8         reserved_at_60[0x20];
4866 };
4867
4868 enum {
4869         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
4870         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
4871         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
4872         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
4873         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
4874 };
4875
4876 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
4877         u8         opcode[0x10];
4878         u8         reserved_at_10[0x10];
4879
4880         u8         reserved_at_20[0x10];
4881         u8         op_mod[0x10];
4882
4883         u8         reserved_at_40[0xa0];
4884
4885         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
4886 };
4887
4888 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
4889         u8         status[0x8];
4890         u8         reserved_at_8[0x18];
4891
4892         u8         syndrome[0x20];
4893
4894         u8         reserved_at_40[0x40];
4895 };
4896
4897 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
4898         u8         opcode[0x10];
4899         u8         reserved_at_10[0x10];
4900
4901         u8         reserved_20[0x10];
4902         u8         op_mod[0x10];
4903
4904         u8         packet_reformat_id[0x20];
4905
4906         u8         reserved_60[0x20];
4907 };
4908
4909 struct mlx5_ifc_set_action_in_bits {
4910         u8         action_type[0x4];
4911         u8         field[0xc];
4912         u8         reserved_at_10[0x3];
4913         u8         offset[0x5];
4914         u8         reserved_at_18[0x3];
4915         u8         length[0x5];
4916
4917         u8         data[0x20];
4918 };
4919
4920 struct mlx5_ifc_add_action_in_bits {
4921         u8         action_type[0x4];
4922         u8         field[0xc];
4923         u8         reserved_at_10[0x10];
4924
4925         u8         data[0x20];
4926 };
4927
4928 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4929         struct mlx5_ifc_set_action_in_bits set_action_in;
4930         struct mlx5_ifc_add_action_in_bits add_action_in;
4931         u8         reserved_at_0[0x40];
4932 };
4933
4934 enum {
4935         MLX5_ACTION_TYPE_SET   = 0x1,
4936         MLX5_ACTION_TYPE_ADD   = 0x2,
4937 };
4938
4939 enum {
4940         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4941         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4942         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4943         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4944         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4945         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4946         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4947         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4948         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4949         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4950         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4951         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4952         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4953         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4954         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4955         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4956         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4957         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4958         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4959         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4960         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4961         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4962         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4963 };
4964
4965 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4966         u8         status[0x8];
4967         u8         reserved_at_8[0x18];
4968
4969         u8         syndrome[0x20];
4970
4971         u8         modify_header_id[0x20];
4972
4973         u8         reserved_at_60[0x20];
4974 };
4975
4976 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4977         u8         opcode[0x10];
4978         u8         reserved_at_10[0x10];
4979
4980         u8         reserved_at_20[0x10];
4981         u8         op_mod[0x10];
4982
4983         u8         reserved_at_40[0x20];
4984
4985         u8         table_type[0x8];
4986         u8         reserved_at_68[0x10];
4987         u8         num_of_actions[0x8];
4988
4989         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4990 };
4991
4992 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4993         u8         status[0x8];
4994         u8         reserved_at_8[0x18];
4995
4996         u8         syndrome[0x20];
4997
4998         u8         reserved_at_40[0x40];
4999 };
5000
5001 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5002         u8         opcode[0x10];
5003         u8         reserved_at_10[0x10];
5004
5005         u8         reserved_at_20[0x10];
5006         u8         op_mod[0x10];
5007
5008         u8         modify_header_id[0x20];
5009
5010         u8         reserved_at_60[0x20];
5011 };
5012
5013 struct mlx5_ifc_query_dct_out_bits {
5014         u8         status[0x8];
5015         u8         reserved_at_8[0x18];
5016
5017         u8         syndrome[0x20];
5018
5019         u8         reserved_at_40[0x40];
5020
5021         struct mlx5_ifc_dctc_bits dct_context_entry;
5022
5023         u8         reserved_at_280[0x180];
5024 };
5025
5026 struct mlx5_ifc_query_dct_in_bits {
5027         u8         opcode[0x10];
5028         u8         reserved_at_10[0x10];
5029
5030         u8         reserved_at_20[0x10];
5031         u8         op_mod[0x10];
5032
5033         u8         reserved_at_40[0x8];
5034         u8         dctn[0x18];
5035
5036         u8         reserved_at_60[0x20];
5037 };
5038
5039 struct mlx5_ifc_query_cq_out_bits {
5040         u8         status[0x8];
5041         u8         reserved_at_8[0x18];
5042
5043         u8         syndrome[0x20];
5044
5045         u8         reserved_at_40[0x40];
5046
5047         struct mlx5_ifc_cqc_bits cq_context;
5048
5049         u8         reserved_at_280[0x600];
5050
5051         u8         pas[0][0x40];
5052 };
5053
5054 struct mlx5_ifc_query_cq_in_bits {
5055         u8         opcode[0x10];
5056         u8         reserved_at_10[0x10];
5057
5058         u8         reserved_at_20[0x10];
5059         u8         op_mod[0x10];
5060
5061         u8         reserved_at_40[0x8];
5062         u8         cqn[0x18];
5063
5064         u8         reserved_at_60[0x20];
5065 };
5066
5067 struct mlx5_ifc_query_cong_status_out_bits {
5068         u8         status[0x8];
5069         u8         reserved_at_8[0x18];
5070
5071         u8         syndrome[0x20];
5072
5073         u8         reserved_at_40[0x20];
5074
5075         u8         enable[0x1];
5076         u8         tag_enable[0x1];
5077         u8         reserved_at_62[0x1e];
5078 };
5079
5080 struct mlx5_ifc_query_cong_status_in_bits {
5081         u8         opcode[0x10];
5082         u8         reserved_at_10[0x10];
5083
5084         u8         reserved_at_20[0x10];
5085         u8         op_mod[0x10];
5086
5087         u8         reserved_at_40[0x18];
5088         u8         priority[0x4];
5089         u8         cong_protocol[0x4];
5090
5091         u8         reserved_at_60[0x20];
5092 };
5093
5094 struct mlx5_ifc_query_cong_statistics_out_bits {
5095         u8         status[0x8];
5096         u8         reserved_at_8[0x18];
5097
5098         u8         syndrome[0x20];
5099
5100         u8         reserved_at_40[0x40];
5101
5102         u8         rp_cur_flows[0x20];
5103
5104         u8         sum_flows[0x20];
5105
5106         u8         rp_cnp_ignored_high[0x20];
5107
5108         u8         rp_cnp_ignored_low[0x20];
5109
5110         u8         rp_cnp_handled_high[0x20];
5111
5112         u8         rp_cnp_handled_low[0x20];
5113
5114         u8         reserved_at_140[0x100];
5115
5116         u8         time_stamp_high[0x20];
5117
5118         u8         time_stamp_low[0x20];
5119
5120         u8         accumulators_period[0x20];
5121
5122         u8         np_ecn_marked_roce_packets_high[0x20];
5123
5124         u8         np_ecn_marked_roce_packets_low[0x20];
5125
5126         u8         np_cnp_sent_high[0x20];
5127
5128         u8         np_cnp_sent_low[0x20];
5129
5130         u8         reserved_at_320[0x560];
5131 };
5132
5133 struct mlx5_ifc_query_cong_statistics_in_bits {
5134         u8         opcode[0x10];
5135         u8         reserved_at_10[0x10];
5136
5137         u8         reserved_at_20[0x10];
5138         u8         op_mod[0x10];
5139
5140         u8         clear[0x1];
5141         u8         reserved_at_41[0x1f];
5142
5143         u8         reserved_at_60[0x20];
5144 };
5145
5146 struct mlx5_ifc_query_cong_params_out_bits {
5147         u8         status[0x8];
5148         u8         reserved_at_8[0x18];
5149
5150         u8         syndrome[0x20];
5151
5152         u8         reserved_at_40[0x40];
5153
5154         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5155 };
5156
5157 struct mlx5_ifc_query_cong_params_in_bits {
5158         u8         opcode[0x10];
5159         u8         reserved_at_10[0x10];
5160
5161         u8         reserved_at_20[0x10];
5162         u8         op_mod[0x10];
5163
5164         u8         reserved_at_40[0x1c];
5165         u8         cong_protocol[0x4];
5166
5167         u8         reserved_at_60[0x20];
5168 };
5169
5170 struct mlx5_ifc_query_adapter_out_bits {
5171         u8         status[0x8];
5172         u8         reserved_at_8[0x18];
5173
5174         u8         syndrome[0x20];
5175
5176         u8         reserved_at_40[0x40];
5177
5178         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5179 };
5180
5181 struct mlx5_ifc_query_adapter_in_bits {
5182         u8         opcode[0x10];
5183         u8         reserved_at_10[0x10];
5184
5185         u8         reserved_at_20[0x10];
5186         u8         op_mod[0x10];
5187
5188         u8         reserved_at_40[0x40];
5189 };
5190
5191 struct mlx5_ifc_qp_2rst_out_bits {
5192         u8         status[0x8];
5193         u8         reserved_at_8[0x18];
5194
5195         u8         syndrome[0x20];
5196
5197         u8         reserved_at_40[0x40];
5198 };
5199
5200 struct mlx5_ifc_qp_2rst_in_bits {
5201         u8         opcode[0x10];
5202         u8         uid[0x10];
5203
5204         u8         reserved_at_20[0x10];
5205         u8         op_mod[0x10];
5206
5207         u8         reserved_at_40[0x8];
5208         u8         qpn[0x18];
5209
5210         u8         reserved_at_60[0x20];
5211 };
5212
5213 struct mlx5_ifc_qp_2err_out_bits {
5214         u8         status[0x8];
5215         u8         reserved_at_8[0x18];
5216
5217         u8         syndrome[0x20];
5218
5219         u8         reserved_at_40[0x40];
5220 };
5221
5222 struct mlx5_ifc_qp_2err_in_bits {
5223         u8         opcode[0x10];
5224         u8         uid[0x10];
5225
5226         u8         reserved_at_20[0x10];
5227         u8         op_mod[0x10];
5228
5229         u8         reserved_at_40[0x8];
5230         u8         qpn[0x18];
5231
5232         u8         reserved_at_60[0x20];
5233 };
5234
5235 struct mlx5_ifc_page_fault_resume_out_bits {
5236         u8         status[0x8];
5237         u8         reserved_at_8[0x18];
5238
5239         u8         syndrome[0x20];
5240
5241         u8         reserved_at_40[0x40];
5242 };
5243
5244 struct mlx5_ifc_page_fault_resume_in_bits {
5245         u8         opcode[0x10];
5246         u8         reserved_at_10[0x10];
5247
5248         u8         reserved_at_20[0x10];
5249         u8         op_mod[0x10];
5250
5251         u8         error[0x1];
5252         u8         reserved_at_41[0x4];
5253         u8         page_fault_type[0x3];
5254         u8         wq_number[0x18];
5255
5256         u8         reserved_at_60[0x8];
5257         u8         token[0x18];
5258 };
5259
5260 struct mlx5_ifc_nop_out_bits {
5261         u8         status[0x8];
5262         u8         reserved_at_8[0x18];
5263
5264         u8         syndrome[0x20];
5265
5266         u8         reserved_at_40[0x40];
5267 };
5268
5269 struct mlx5_ifc_nop_in_bits {
5270         u8         opcode[0x10];
5271         u8         reserved_at_10[0x10];
5272
5273         u8         reserved_at_20[0x10];
5274         u8         op_mod[0x10];
5275
5276         u8         reserved_at_40[0x40];
5277 };
5278
5279 struct mlx5_ifc_modify_vport_state_out_bits {
5280         u8         status[0x8];
5281         u8         reserved_at_8[0x18];
5282
5283         u8         syndrome[0x20];
5284
5285         u8         reserved_at_40[0x40];
5286 };
5287
5288 struct mlx5_ifc_modify_vport_state_in_bits {
5289         u8         opcode[0x10];
5290         u8         reserved_at_10[0x10];
5291
5292         u8         reserved_at_20[0x10];
5293         u8         op_mod[0x10];
5294
5295         u8         other_vport[0x1];
5296         u8         reserved_at_41[0xf];
5297         u8         vport_number[0x10];
5298
5299         u8         reserved_at_60[0x18];
5300         u8         admin_state[0x4];
5301         u8         reserved_at_7c[0x4];
5302 };
5303
5304 struct mlx5_ifc_modify_tis_out_bits {
5305         u8         status[0x8];
5306         u8         reserved_at_8[0x18];
5307
5308         u8         syndrome[0x20];
5309
5310         u8         reserved_at_40[0x40];
5311 };
5312
5313 struct mlx5_ifc_modify_tis_bitmask_bits {
5314         u8         reserved_at_0[0x20];
5315
5316         u8         reserved_at_20[0x1d];
5317         u8         lag_tx_port_affinity[0x1];
5318         u8         strict_lag_tx_port_affinity[0x1];
5319         u8         prio[0x1];
5320 };
5321
5322 struct mlx5_ifc_modify_tis_in_bits {
5323         u8         opcode[0x10];
5324         u8         uid[0x10];
5325
5326         u8         reserved_at_20[0x10];
5327         u8         op_mod[0x10];
5328
5329         u8         reserved_at_40[0x8];
5330         u8         tisn[0x18];
5331
5332         u8         reserved_at_60[0x20];
5333
5334         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5335
5336         u8         reserved_at_c0[0x40];
5337
5338         struct mlx5_ifc_tisc_bits ctx;
5339 };
5340
5341 struct mlx5_ifc_modify_tir_bitmask_bits {
5342         u8         reserved_at_0[0x20];
5343
5344         u8         reserved_at_20[0x1b];
5345         u8         self_lb_en[0x1];
5346         u8         reserved_at_3c[0x1];
5347         u8         hash[0x1];
5348         u8         reserved_at_3e[0x1];
5349         u8         lro[0x1];
5350 };
5351
5352 struct mlx5_ifc_modify_tir_out_bits {
5353         u8         status[0x8];
5354         u8         reserved_at_8[0x18];
5355
5356         u8         syndrome[0x20];
5357
5358         u8         reserved_at_40[0x40];
5359 };
5360
5361 struct mlx5_ifc_modify_tir_in_bits {
5362         u8         opcode[0x10];
5363         u8         uid[0x10];
5364
5365         u8         reserved_at_20[0x10];
5366         u8         op_mod[0x10];
5367
5368         u8         reserved_at_40[0x8];
5369         u8         tirn[0x18];
5370
5371         u8         reserved_at_60[0x20];
5372
5373         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5374
5375         u8         reserved_at_c0[0x40];
5376
5377         struct mlx5_ifc_tirc_bits ctx;
5378 };
5379
5380 struct mlx5_ifc_modify_sq_out_bits {
5381         u8         status[0x8];
5382         u8         reserved_at_8[0x18];
5383
5384         u8         syndrome[0x20];
5385
5386         u8         reserved_at_40[0x40];
5387 };
5388
5389 struct mlx5_ifc_modify_sq_in_bits {
5390         u8         opcode[0x10];
5391         u8         uid[0x10];
5392
5393         u8         reserved_at_20[0x10];
5394         u8         op_mod[0x10];
5395
5396         u8         sq_state[0x4];
5397         u8         reserved_at_44[0x4];
5398         u8         sqn[0x18];
5399
5400         u8         reserved_at_60[0x20];
5401
5402         u8         modify_bitmask[0x40];
5403
5404         u8         reserved_at_c0[0x40];
5405
5406         struct mlx5_ifc_sqc_bits ctx;
5407 };
5408
5409 struct mlx5_ifc_modify_scheduling_element_out_bits {
5410         u8         status[0x8];
5411         u8         reserved_at_8[0x18];
5412
5413         u8         syndrome[0x20];
5414
5415         u8         reserved_at_40[0x1c0];
5416 };
5417
5418 enum {
5419         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5420         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5421 };
5422
5423 struct mlx5_ifc_modify_scheduling_element_in_bits {
5424         u8         opcode[0x10];
5425         u8         reserved_at_10[0x10];
5426
5427         u8         reserved_at_20[0x10];
5428         u8         op_mod[0x10];
5429
5430         u8         scheduling_hierarchy[0x8];
5431         u8         reserved_at_48[0x18];
5432
5433         u8         scheduling_element_id[0x20];
5434
5435         u8         reserved_at_80[0x20];
5436
5437         u8         modify_bitmask[0x20];
5438
5439         u8         reserved_at_c0[0x40];
5440
5441         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5442
5443         u8         reserved_at_300[0x100];
5444 };
5445
5446 struct mlx5_ifc_modify_rqt_out_bits {
5447         u8         status[0x8];
5448         u8         reserved_at_8[0x18];
5449
5450         u8         syndrome[0x20];
5451
5452         u8         reserved_at_40[0x40];
5453 };
5454
5455 struct mlx5_ifc_rqt_bitmask_bits {
5456         u8         reserved_at_0[0x20];
5457
5458         u8         reserved_at_20[0x1f];
5459         u8         rqn_list[0x1];
5460 };
5461
5462 struct mlx5_ifc_modify_rqt_in_bits {
5463         u8         opcode[0x10];
5464         u8         uid[0x10];
5465
5466         u8         reserved_at_20[0x10];
5467         u8         op_mod[0x10];
5468
5469         u8         reserved_at_40[0x8];
5470         u8         rqtn[0x18];
5471
5472         u8         reserved_at_60[0x20];
5473
5474         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5475
5476         u8         reserved_at_c0[0x40];
5477
5478         struct mlx5_ifc_rqtc_bits ctx;
5479 };
5480
5481 struct mlx5_ifc_modify_rq_out_bits {
5482         u8         status[0x8];
5483         u8         reserved_at_8[0x18];
5484
5485         u8         syndrome[0x20];
5486
5487         u8         reserved_at_40[0x40];
5488 };
5489
5490 enum {
5491         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5492         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5493         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5494 };
5495
5496 struct mlx5_ifc_modify_rq_in_bits {
5497         u8         opcode[0x10];
5498         u8         uid[0x10];
5499
5500         u8         reserved_at_20[0x10];
5501         u8         op_mod[0x10];
5502
5503         u8         rq_state[0x4];
5504         u8         reserved_at_44[0x4];
5505         u8         rqn[0x18];
5506
5507         u8         reserved_at_60[0x20];
5508
5509         u8         modify_bitmask[0x40];
5510
5511         u8         reserved_at_c0[0x40];
5512
5513         struct mlx5_ifc_rqc_bits ctx;
5514 };
5515
5516 struct mlx5_ifc_modify_rmp_out_bits {
5517         u8         status[0x8];
5518         u8         reserved_at_8[0x18];
5519
5520         u8         syndrome[0x20];
5521
5522         u8         reserved_at_40[0x40];
5523 };
5524
5525 struct mlx5_ifc_rmp_bitmask_bits {
5526         u8         reserved_at_0[0x20];
5527
5528         u8         reserved_at_20[0x1f];
5529         u8         lwm[0x1];
5530 };
5531
5532 struct mlx5_ifc_modify_rmp_in_bits {
5533         u8         opcode[0x10];
5534         u8         uid[0x10];
5535
5536         u8         reserved_at_20[0x10];
5537         u8         op_mod[0x10];
5538
5539         u8         rmp_state[0x4];
5540         u8         reserved_at_44[0x4];
5541         u8         rmpn[0x18];
5542
5543         u8         reserved_at_60[0x20];
5544
5545         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5546
5547         u8         reserved_at_c0[0x40];
5548
5549         struct mlx5_ifc_rmpc_bits ctx;
5550 };
5551
5552 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5553         u8         status[0x8];
5554         u8         reserved_at_8[0x18];
5555
5556         u8         syndrome[0x20];
5557
5558         u8         reserved_at_40[0x40];
5559 };
5560
5561 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5562         u8         reserved_at_0[0x12];
5563         u8         affiliation[0x1];
5564         u8         reserved_at_e[0x1];
5565         u8         disable_uc_local_lb[0x1];
5566         u8         disable_mc_local_lb[0x1];
5567         u8         node_guid[0x1];
5568         u8         port_guid[0x1];
5569         u8         min_inline[0x1];
5570         u8         mtu[0x1];
5571         u8         change_event[0x1];
5572         u8         promisc[0x1];
5573         u8         permanent_address[0x1];
5574         u8         addresses_list[0x1];
5575         u8         roce_en[0x1];
5576         u8         reserved_at_1f[0x1];
5577 };
5578
5579 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5580         u8         opcode[0x10];
5581         u8         reserved_at_10[0x10];
5582
5583         u8         reserved_at_20[0x10];
5584         u8         op_mod[0x10];
5585
5586         u8         other_vport[0x1];
5587         u8         reserved_at_41[0xf];
5588         u8         vport_number[0x10];
5589
5590         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5591
5592         u8         reserved_at_80[0x780];
5593
5594         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5595 };
5596
5597 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5598         u8         status[0x8];
5599         u8         reserved_at_8[0x18];
5600
5601         u8         syndrome[0x20];
5602
5603         u8         reserved_at_40[0x40];
5604 };
5605
5606 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5607         u8         opcode[0x10];
5608         u8         reserved_at_10[0x10];
5609
5610         u8         reserved_at_20[0x10];
5611         u8         op_mod[0x10];
5612
5613         u8         other_vport[0x1];
5614         u8         reserved_at_41[0xb];
5615         u8         port_num[0x4];
5616         u8         vport_number[0x10];
5617
5618         u8         reserved_at_60[0x20];
5619
5620         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5621 };
5622
5623 struct mlx5_ifc_modify_cq_out_bits {
5624         u8         status[0x8];
5625         u8         reserved_at_8[0x18];
5626
5627         u8         syndrome[0x20];
5628
5629         u8         reserved_at_40[0x40];
5630 };
5631
5632 enum {
5633         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5634         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5635 };
5636
5637 struct mlx5_ifc_modify_cq_in_bits {
5638         u8         opcode[0x10];
5639         u8         uid[0x10];
5640
5641         u8         reserved_at_20[0x10];
5642         u8         op_mod[0x10];
5643
5644         u8         reserved_at_40[0x8];
5645         u8         cqn[0x18];
5646
5647         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5648
5649         struct mlx5_ifc_cqc_bits cq_context;
5650
5651         u8         reserved_at_280[0x40];
5652
5653         u8         cq_umem_valid[0x1];
5654         u8         reserved_at_2c1[0x5bf];
5655
5656         u8         pas[0][0x40];
5657 };
5658
5659 struct mlx5_ifc_modify_cong_status_out_bits {
5660         u8         status[0x8];
5661         u8         reserved_at_8[0x18];
5662
5663         u8         syndrome[0x20];
5664
5665         u8         reserved_at_40[0x40];
5666 };
5667
5668 struct mlx5_ifc_modify_cong_status_in_bits {
5669         u8         opcode[0x10];
5670         u8         reserved_at_10[0x10];
5671
5672         u8         reserved_at_20[0x10];
5673         u8         op_mod[0x10];
5674
5675         u8         reserved_at_40[0x18];
5676         u8         priority[0x4];
5677         u8         cong_protocol[0x4];
5678
5679         u8         enable[0x1];
5680         u8         tag_enable[0x1];
5681         u8         reserved_at_62[0x1e];
5682 };
5683
5684 struct mlx5_ifc_modify_cong_params_out_bits {
5685         u8         status[0x8];
5686         u8         reserved_at_8[0x18];
5687
5688         u8         syndrome[0x20];
5689
5690         u8         reserved_at_40[0x40];
5691 };
5692
5693 struct mlx5_ifc_modify_cong_params_in_bits {
5694         u8         opcode[0x10];
5695         u8         reserved_at_10[0x10];
5696
5697         u8         reserved_at_20[0x10];
5698         u8         op_mod[0x10];
5699
5700         u8         reserved_at_40[0x1c];
5701         u8         cong_protocol[0x4];
5702
5703         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5704
5705         u8         reserved_at_80[0x80];
5706
5707         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5708 };
5709
5710 struct mlx5_ifc_manage_pages_out_bits {
5711         u8         status[0x8];
5712         u8         reserved_at_8[0x18];
5713
5714         u8         syndrome[0x20];
5715
5716         u8         output_num_entries[0x20];
5717
5718         u8         reserved_at_60[0x20];
5719
5720         u8         pas[0][0x40];
5721 };
5722
5723 enum {
5724         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5725         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5726         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5727 };
5728
5729 struct mlx5_ifc_manage_pages_in_bits {
5730         u8         opcode[0x10];
5731         u8         reserved_at_10[0x10];
5732
5733         u8         reserved_at_20[0x10];
5734         u8         op_mod[0x10];
5735
5736         u8         reserved_at_40[0x10];
5737         u8         function_id[0x10];
5738
5739         u8         input_num_entries[0x20];
5740
5741         u8         pas[0][0x40];
5742 };
5743
5744 struct mlx5_ifc_mad_ifc_out_bits {
5745         u8         status[0x8];
5746         u8         reserved_at_8[0x18];
5747
5748         u8         syndrome[0x20];
5749
5750         u8         reserved_at_40[0x40];
5751
5752         u8         response_mad_packet[256][0x8];
5753 };
5754
5755 struct mlx5_ifc_mad_ifc_in_bits {
5756         u8         opcode[0x10];
5757         u8         reserved_at_10[0x10];
5758
5759         u8         reserved_at_20[0x10];
5760         u8         op_mod[0x10];
5761
5762         u8         remote_lid[0x10];
5763         u8         reserved_at_50[0x8];
5764         u8         port[0x8];
5765
5766         u8         reserved_at_60[0x20];
5767
5768         u8         mad[256][0x8];
5769 };
5770
5771 struct mlx5_ifc_init_hca_out_bits {
5772         u8         status[0x8];
5773         u8         reserved_at_8[0x18];
5774
5775         u8         syndrome[0x20];
5776
5777         u8         reserved_at_40[0x40];
5778 };
5779
5780 struct mlx5_ifc_init_hca_in_bits {
5781         u8         opcode[0x10];
5782         u8         reserved_at_10[0x10];
5783
5784         u8         reserved_at_20[0x10];
5785         u8         op_mod[0x10];
5786
5787         u8         reserved_at_40[0x40];
5788         u8         sw_owner_id[4][0x20];
5789 };
5790
5791 struct mlx5_ifc_init2rtr_qp_out_bits {
5792         u8         status[0x8];
5793         u8         reserved_at_8[0x18];
5794
5795         u8         syndrome[0x20];
5796
5797         u8         reserved_at_40[0x40];
5798 };
5799
5800 struct mlx5_ifc_init2rtr_qp_in_bits {
5801         u8         opcode[0x10];
5802         u8         uid[0x10];
5803
5804         u8         reserved_at_20[0x10];
5805         u8         op_mod[0x10];
5806
5807         u8         reserved_at_40[0x8];
5808         u8         qpn[0x18];
5809
5810         u8         reserved_at_60[0x20];
5811
5812         u8         opt_param_mask[0x20];
5813
5814         u8         reserved_at_a0[0x20];
5815
5816         struct mlx5_ifc_qpc_bits qpc;
5817
5818         u8         reserved_at_800[0x80];
5819 };
5820
5821 struct mlx5_ifc_init2init_qp_out_bits {
5822         u8         status[0x8];
5823         u8         reserved_at_8[0x18];
5824
5825         u8         syndrome[0x20];
5826
5827         u8         reserved_at_40[0x40];
5828 };
5829
5830 struct mlx5_ifc_init2init_qp_in_bits {
5831         u8         opcode[0x10];
5832         u8         uid[0x10];
5833
5834         u8         reserved_at_20[0x10];
5835         u8         op_mod[0x10];
5836
5837         u8         reserved_at_40[0x8];
5838         u8         qpn[0x18];
5839
5840         u8         reserved_at_60[0x20];
5841
5842         u8         opt_param_mask[0x20];
5843
5844         u8         reserved_at_a0[0x20];
5845
5846         struct mlx5_ifc_qpc_bits qpc;
5847
5848         u8         reserved_at_800[0x80];
5849 };
5850
5851 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5852         u8         status[0x8];
5853         u8         reserved_at_8[0x18];
5854
5855         u8         syndrome[0x20];
5856
5857         u8         reserved_at_40[0x40];
5858
5859         u8         packet_headers_log[128][0x8];
5860
5861         u8         packet_syndrome[64][0x8];
5862 };
5863
5864 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5865         u8         opcode[0x10];
5866         u8         reserved_at_10[0x10];
5867
5868         u8         reserved_at_20[0x10];
5869         u8         op_mod[0x10];
5870
5871         u8         reserved_at_40[0x40];
5872 };
5873
5874 struct mlx5_ifc_gen_eqe_in_bits {
5875         u8         opcode[0x10];
5876         u8         reserved_at_10[0x10];
5877
5878         u8         reserved_at_20[0x10];
5879         u8         op_mod[0x10];
5880
5881         u8         reserved_at_40[0x18];
5882         u8         eq_number[0x8];
5883
5884         u8         reserved_at_60[0x20];
5885
5886         u8         eqe[64][0x8];
5887 };
5888
5889 struct mlx5_ifc_gen_eq_out_bits {
5890         u8         status[0x8];
5891         u8         reserved_at_8[0x18];
5892
5893         u8         syndrome[0x20];
5894
5895         u8         reserved_at_40[0x40];
5896 };
5897
5898 struct mlx5_ifc_enable_hca_out_bits {
5899         u8         status[0x8];
5900         u8         reserved_at_8[0x18];
5901
5902         u8         syndrome[0x20];
5903
5904         u8         reserved_at_40[0x20];
5905 };
5906
5907 struct mlx5_ifc_enable_hca_in_bits {
5908         u8         opcode[0x10];
5909         u8         reserved_at_10[0x10];
5910
5911         u8         reserved_at_20[0x10];
5912         u8         op_mod[0x10];
5913
5914         u8         reserved_at_40[0x10];
5915         u8         function_id[0x10];
5916
5917         u8         reserved_at_60[0x20];
5918 };
5919
5920 struct mlx5_ifc_drain_dct_out_bits {
5921         u8         status[0x8];
5922         u8         reserved_at_8[0x18];
5923
5924         u8         syndrome[0x20];
5925
5926         u8         reserved_at_40[0x40];
5927 };
5928
5929 struct mlx5_ifc_drain_dct_in_bits {
5930         u8         opcode[0x10];
5931         u8         uid[0x10];
5932
5933         u8         reserved_at_20[0x10];
5934         u8         op_mod[0x10];
5935
5936         u8         reserved_at_40[0x8];
5937         u8         dctn[0x18];
5938
5939         u8         reserved_at_60[0x20];
5940 };
5941
5942 struct mlx5_ifc_disable_hca_out_bits {
5943         u8         status[0x8];
5944         u8         reserved_at_8[0x18];
5945
5946         u8         syndrome[0x20];
5947
5948         u8         reserved_at_40[0x20];
5949 };
5950
5951 struct mlx5_ifc_disable_hca_in_bits {
5952         u8         opcode[0x10];
5953         u8         reserved_at_10[0x10];
5954
5955         u8         reserved_at_20[0x10];
5956         u8         op_mod[0x10];
5957
5958         u8         reserved_at_40[0x10];
5959         u8         function_id[0x10];
5960
5961         u8         reserved_at_60[0x20];
5962 };
5963
5964 struct mlx5_ifc_detach_from_mcg_out_bits {
5965         u8         status[0x8];
5966         u8         reserved_at_8[0x18];
5967
5968         u8         syndrome[0x20];
5969
5970         u8         reserved_at_40[0x40];
5971 };
5972
5973 struct mlx5_ifc_detach_from_mcg_in_bits {
5974         u8         opcode[0x10];
5975         u8         uid[0x10];
5976
5977         u8         reserved_at_20[0x10];
5978         u8         op_mod[0x10];
5979
5980         u8         reserved_at_40[0x8];
5981         u8         qpn[0x18];
5982
5983         u8         reserved_at_60[0x20];
5984
5985         u8         multicast_gid[16][0x8];
5986 };
5987
5988 struct mlx5_ifc_destroy_xrq_out_bits {
5989         u8         status[0x8];
5990         u8         reserved_at_8[0x18];
5991
5992         u8         syndrome[0x20];
5993
5994         u8         reserved_at_40[0x40];
5995 };
5996
5997 struct mlx5_ifc_destroy_xrq_in_bits {
5998         u8         opcode[0x10];
5999         u8         uid[0x10];
6000
6001         u8         reserved_at_20[0x10];
6002         u8         op_mod[0x10];
6003
6004         u8         reserved_at_40[0x8];
6005         u8         xrqn[0x18];
6006
6007         u8         reserved_at_60[0x20];
6008 };
6009
6010 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6011         u8         status[0x8];
6012         u8         reserved_at_8[0x18];
6013
6014         u8         syndrome[0x20];
6015
6016         u8         reserved_at_40[0x40];
6017 };
6018
6019 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6020         u8         opcode[0x10];
6021         u8         uid[0x10];
6022
6023         u8         reserved_at_20[0x10];
6024         u8         op_mod[0x10];
6025
6026         u8         reserved_at_40[0x8];
6027         u8         xrc_srqn[0x18];
6028
6029         u8         reserved_at_60[0x20];
6030 };
6031
6032 struct mlx5_ifc_destroy_tis_out_bits {
6033         u8         status[0x8];
6034         u8         reserved_at_8[0x18];
6035
6036         u8         syndrome[0x20];
6037
6038         u8         reserved_at_40[0x40];
6039 };
6040
6041 struct mlx5_ifc_destroy_tis_in_bits {
6042         u8         opcode[0x10];
6043         u8         uid[0x10];
6044
6045         u8         reserved_at_20[0x10];
6046         u8         op_mod[0x10];
6047
6048         u8         reserved_at_40[0x8];
6049         u8         tisn[0x18];
6050
6051         u8         reserved_at_60[0x20];
6052 };
6053
6054 struct mlx5_ifc_destroy_tir_out_bits {
6055         u8         status[0x8];
6056         u8         reserved_at_8[0x18];
6057
6058         u8         syndrome[0x20];
6059
6060         u8         reserved_at_40[0x40];
6061 };
6062
6063 struct mlx5_ifc_destroy_tir_in_bits {
6064         u8         opcode[0x10];
6065         u8         uid[0x10];
6066
6067         u8         reserved_at_20[0x10];
6068         u8         op_mod[0x10];
6069
6070         u8         reserved_at_40[0x8];
6071         u8         tirn[0x18];
6072
6073         u8         reserved_at_60[0x20];
6074 };
6075
6076 struct mlx5_ifc_destroy_srq_out_bits {
6077         u8         status[0x8];
6078         u8         reserved_at_8[0x18];
6079
6080         u8         syndrome[0x20];
6081
6082         u8         reserved_at_40[0x40];
6083 };
6084
6085 struct mlx5_ifc_destroy_srq_in_bits {
6086         u8         opcode[0x10];
6087         u8         uid[0x10];
6088
6089         u8         reserved_at_20[0x10];
6090         u8         op_mod[0x10];
6091
6092         u8         reserved_at_40[0x8];
6093         u8         srqn[0x18];
6094
6095         u8         reserved_at_60[0x20];
6096 };
6097
6098 struct mlx5_ifc_destroy_sq_out_bits {
6099         u8         status[0x8];
6100         u8         reserved_at_8[0x18];
6101
6102         u8         syndrome[0x20];
6103
6104         u8         reserved_at_40[0x40];
6105 };
6106
6107 struct mlx5_ifc_destroy_sq_in_bits {
6108         u8         opcode[0x10];
6109         u8         uid[0x10];
6110
6111         u8         reserved_at_20[0x10];
6112         u8         op_mod[0x10];
6113
6114         u8         reserved_at_40[0x8];
6115         u8         sqn[0x18];
6116
6117         u8         reserved_at_60[0x20];
6118 };
6119
6120 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6121         u8         status[0x8];
6122         u8         reserved_at_8[0x18];
6123
6124         u8         syndrome[0x20];
6125
6126         u8         reserved_at_40[0x1c0];
6127 };
6128
6129 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6130         u8         opcode[0x10];
6131         u8         reserved_at_10[0x10];
6132
6133         u8         reserved_at_20[0x10];
6134         u8         op_mod[0x10];
6135
6136         u8         scheduling_hierarchy[0x8];
6137         u8         reserved_at_48[0x18];
6138
6139         u8         scheduling_element_id[0x20];
6140
6141         u8         reserved_at_80[0x180];
6142 };
6143
6144 struct mlx5_ifc_destroy_rqt_out_bits {
6145         u8         status[0x8];
6146         u8         reserved_at_8[0x18];
6147
6148         u8         syndrome[0x20];
6149
6150         u8         reserved_at_40[0x40];
6151 };
6152
6153 struct mlx5_ifc_destroy_rqt_in_bits {
6154         u8         opcode[0x10];
6155         u8         uid[0x10];
6156
6157         u8         reserved_at_20[0x10];
6158         u8         op_mod[0x10];
6159
6160         u8         reserved_at_40[0x8];
6161         u8         rqtn[0x18];
6162
6163         u8         reserved_at_60[0x20];
6164 };
6165
6166 struct mlx5_ifc_destroy_rq_out_bits {
6167         u8         status[0x8];
6168         u8         reserved_at_8[0x18];
6169
6170         u8         syndrome[0x20];
6171
6172         u8         reserved_at_40[0x40];
6173 };
6174
6175 struct mlx5_ifc_destroy_rq_in_bits {
6176         u8         opcode[0x10];
6177         u8         uid[0x10];
6178
6179         u8         reserved_at_20[0x10];
6180         u8         op_mod[0x10];
6181
6182         u8         reserved_at_40[0x8];
6183         u8         rqn[0x18];
6184
6185         u8         reserved_at_60[0x20];
6186 };
6187
6188 struct mlx5_ifc_set_delay_drop_params_in_bits {
6189         u8         opcode[0x10];
6190         u8         reserved_at_10[0x10];
6191
6192         u8         reserved_at_20[0x10];
6193         u8         op_mod[0x10];
6194
6195         u8         reserved_at_40[0x20];
6196
6197         u8         reserved_at_60[0x10];
6198         u8         delay_drop_timeout[0x10];
6199 };
6200
6201 struct mlx5_ifc_set_delay_drop_params_out_bits {
6202         u8         status[0x8];
6203         u8         reserved_at_8[0x18];
6204
6205         u8         syndrome[0x20];
6206
6207         u8         reserved_at_40[0x40];
6208 };
6209
6210 struct mlx5_ifc_destroy_rmp_out_bits {
6211         u8         status[0x8];
6212         u8         reserved_at_8[0x18];
6213
6214         u8         syndrome[0x20];
6215
6216         u8         reserved_at_40[0x40];
6217 };
6218
6219 struct mlx5_ifc_destroy_rmp_in_bits {
6220         u8         opcode[0x10];
6221         u8         uid[0x10];
6222
6223         u8         reserved_at_20[0x10];
6224         u8         op_mod[0x10];
6225
6226         u8         reserved_at_40[0x8];
6227         u8         rmpn[0x18];
6228
6229         u8         reserved_at_60[0x20];
6230 };
6231
6232 struct mlx5_ifc_destroy_qp_out_bits {
6233         u8         status[0x8];
6234         u8         reserved_at_8[0x18];
6235
6236         u8         syndrome[0x20];
6237
6238         u8         reserved_at_40[0x40];
6239 };
6240
6241 struct mlx5_ifc_destroy_qp_in_bits {
6242         u8         opcode[0x10];
6243         u8         uid[0x10];
6244
6245         u8         reserved_at_20[0x10];
6246         u8         op_mod[0x10];
6247
6248         u8         reserved_at_40[0x8];
6249         u8         qpn[0x18];
6250
6251         u8         reserved_at_60[0x20];
6252 };
6253
6254 struct mlx5_ifc_destroy_psv_out_bits {
6255         u8         status[0x8];
6256         u8         reserved_at_8[0x18];
6257
6258         u8         syndrome[0x20];
6259
6260         u8         reserved_at_40[0x40];
6261 };
6262
6263 struct mlx5_ifc_destroy_psv_in_bits {
6264         u8         opcode[0x10];
6265         u8         reserved_at_10[0x10];
6266
6267         u8         reserved_at_20[0x10];
6268         u8         op_mod[0x10];
6269
6270         u8         reserved_at_40[0x8];
6271         u8         psvn[0x18];
6272
6273         u8         reserved_at_60[0x20];
6274 };
6275
6276 struct mlx5_ifc_destroy_mkey_out_bits {
6277         u8         status[0x8];
6278         u8         reserved_at_8[0x18];
6279
6280         u8         syndrome[0x20];
6281
6282         u8         reserved_at_40[0x40];
6283 };
6284
6285 struct mlx5_ifc_destroy_mkey_in_bits {
6286         u8         opcode[0x10];
6287         u8         reserved_at_10[0x10];
6288
6289         u8         reserved_at_20[0x10];
6290         u8         op_mod[0x10];
6291
6292         u8         reserved_at_40[0x8];
6293         u8         mkey_index[0x18];
6294
6295         u8         reserved_at_60[0x20];
6296 };
6297
6298 struct mlx5_ifc_destroy_flow_table_out_bits {
6299         u8         status[0x8];
6300         u8         reserved_at_8[0x18];
6301
6302         u8         syndrome[0x20];
6303
6304         u8         reserved_at_40[0x40];
6305 };
6306
6307 struct mlx5_ifc_destroy_flow_table_in_bits {
6308         u8         opcode[0x10];
6309         u8         reserved_at_10[0x10];
6310
6311         u8         reserved_at_20[0x10];
6312         u8         op_mod[0x10];
6313
6314         u8         other_vport[0x1];
6315         u8         reserved_at_41[0xf];
6316         u8         vport_number[0x10];
6317
6318         u8         reserved_at_60[0x20];
6319
6320         u8         table_type[0x8];
6321         u8         reserved_at_88[0x18];
6322
6323         u8         reserved_at_a0[0x8];
6324         u8         table_id[0x18];
6325
6326         u8         reserved_at_c0[0x140];
6327 };
6328
6329 struct mlx5_ifc_destroy_flow_group_out_bits {
6330         u8         status[0x8];
6331         u8         reserved_at_8[0x18];
6332
6333         u8         syndrome[0x20];
6334
6335         u8         reserved_at_40[0x40];
6336 };
6337
6338 struct mlx5_ifc_destroy_flow_group_in_bits {
6339         u8         opcode[0x10];
6340         u8         reserved_at_10[0x10];
6341
6342         u8         reserved_at_20[0x10];
6343         u8         op_mod[0x10];
6344
6345         u8         other_vport[0x1];
6346         u8         reserved_at_41[0xf];
6347         u8         vport_number[0x10];
6348
6349         u8         reserved_at_60[0x20];
6350
6351         u8         table_type[0x8];
6352         u8         reserved_at_88[0x18];
6353
6354         u8         reserved_at_a0[0x8];
6355         u8         table_id[0x18];
6356
6357         u8         group_id[0x20];
6358
6359         u8         reserved_at_e0[0x120];
6360 };
6361
6362 struct mlx5_ifc_destroy_eq_out_bits {
6363         u8         status[0x8];
6364         u8         reserved_at_8[0x18];
6365
6366         u8         syndrome[0x20];
6367
6368         u8         reserved_at_40[0x40];
6369 };
6370
6371 struct mlx5_ifc_destroy_eq_in_bits {
6372         u8         opcode[0x10];
6373         u8         reserved_at_10[0x10];
6374
6375         u8         reserved_at_20[0x10];
6376         u8         op_mod[0x10];
6377
6378         u8         reserved_at_40[0x18];
6379         u8         eq_number[0x8];
6380
6381         u8         reserved_at_60[0x20];
6382 };
6383
6384 struct mlx5_ifc_destroy_dct_out_bits {
6385         u8         status[0x8];
6386         u8         reserved_at_8[0x18];
6387
6388         u8         syndrome[0x20];
6389
6390         u8         reserved_at_40[0x40];
6391 };
6392
6393 struct mlx5_ifc_destroy_dct_in_bits {
6394         u8         opcode[0x10];
6395         u8         uid[0x10];
6396
6397         u8         reserved_at_20[0x10];
6398         u8         op_mod[0x10];
6399
6400         u8         reserved_at_40[0x8];
6401         u8         dctn[0x18];
6402
6403         u8         reserved_at_60[0x20];
6404 };
6405
6406 struct mlx5_ifc_destroy_cq_out_bits {
6407         u8         status[0x8];
6408         u8         reserved_at_8[0x18];
6409
6410         u8         syndrome[0x20];
6411
6412         u8         reserved_at_40[0x40];
6413 };
6414
6415 struct mlx5_ifc_destroy_cq_in_bits {
6416         u8         opcode[0x10];
6417         u8         uid[0x10];
6418
6419         u8         reserved_at_20[0x10];
6420         u8         op_mod[0x10];
6421
6422         u8         reserved_at_40[0x8];
6423         u8         cqn[0x18];
6424
6425         u8         reserved_at_60[0x20];
6426 };
6427
6428 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6429         u8         status[0x8];
6430         u8         reserved_at_8[0x18];
6431
6432         u8         syndrome[0x20];
6433
6434         u8         reserved_at_40[0x40];
6435 };
6436
6437 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6438         u8         opcode[0x10];
6439         u8         reserved_at_10[0x10];
6440
6441         u8         reserved_at_20[0x10];
6442         u8         op_mod[0x10];
6443
6444         u8         reserved_at_40[0x20];
6445
6446         u8         reserved_at_60[0x10];
6447         u8         vxlan_udp_port[0x10];
6448 };
6449
6450 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6451         u8         status[0x8];
6452         u8         reserved_at_8[0x18];
6453
6454         u8         syndrome[0x20];
6455
6456         u8         reserved_at_40[0x40];
6457 };
6458
6459 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6460         u8         opcode[0x10];
6461         u8         reserved_at_10[0x10];
6462
6463         u8         reserved_at_20[0x10];
6464         u8         op_mod[0x10];
6465
6466         u8         reserved_at_40[0x60];
6467
6468         u8         reserved_at_a0[0x8];
6469         u8         table_index[0x18];
6470
6471         u8         reserved_at_c0[0x140];
6472 };
6473
6474 struct mlx5_ifc_delete_fte_out_bits {
6475         u8         status[0x8];
6476         u8         reserved_at_8[0x18];
6477
6478         u8         syndrome[0x20];
6479
6480         u8         reserved_at_40[0x40];
6481 };
6482
6483 struct mlx5_ifc_delete_fte_in_bits {
6484         u8         opcode[0x10];
6485         u8         reserved_at_10[0x10];
6486
6487         u8         reserved_at_20[0x10];
6488         u8         op_mod[0x10];
6489
6490         u8         other_vport[0x1];
6491         u8         reserved_at_41[0xf];
6492         u8         vport_number[0x10];
6493
6494         u8         reserved_at_60[0x20];
6495
6496         u8         table_type[0x8];
6497         u8         reserved_at_88[0x18];
6498
6499         u8         reserved_at_a0[0x8];
6500         u8         table_id[0x18];
6501
6502         u8         reserved_at_c0[0x40];
6503
6504         u8         flow_index[0x20];
6505
6506         u8         reserved_at_120[0xe0];
6507 };
6508
6509 struct mlx5_ifc_dealloc_xrcd_out_bits {
6510         u8         status[0x8];
6511         u8         reserved_at_8[0x18];
6512
6513         u8         syndrome[0x20];
6514
6515         u8         reserved_at_40[0x40];
6516 };
6517
6518 struct mlx5_ifc_dealloc_xrcd_in_bits {
6519         u8         opcode[0x10];
6520         u8         uid[0x10];
6521
6522         u8         reserved_at_20[0x10];
6523         u8         op_mod[0x10];
6524
6525         u8         reserved_at_40[0x8];
6526         u8         xrcd[0x18];
6527
6528         u8         reserved_at_60[0x20];
6529 };
6530
6531 struct mlx5_ifc_dealloc_uar_out_bits {
6532         u8         status[0x8];
6533         u8         reserved_at_8[0x18];
6534
6535         u8         syndrome[0x20];
6536
6537         u8         reserved_at_40[0x40];
6538 };
6539
6540 struct mlx5_ifc_dealloc_uar_in_bits {
6541         u8         opcode[0x10];
6542         u8         reserved_at_10[0x10];
6543
6544         u8         reserved_at_20[0x10];
6545         u8         op_mod[0x10];
6546
6547         u8         reserved_at_40[0x8];
6548         u8         uar[0x18];
6549
6550         u8         reserved_at_60[0x20];
6551 };
6552
6553 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6554         u8         status[0x8];
6555         u8         reserved_at_8[0x18];
6556
6557         u8         syndrome[0x20];
6558
6559         u8         reserved_at_40[0x40];
6560 };
6561
6562 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6563         u8         opcode[0x10];
6564         u8         reserved_at_10[0x10];
6565
6566         u8         reserved_at_20[0x10];
6567         u8         op_mod[0x10];
6568
6569         u8         reserved_at_40[0x8];
6570         u8         transport_domain[0x18];
6571
6572         u8         reserved_at_60[0x20];
6573 };
6574
6575 struct mlx5_ifc_dealloc_q_counter_out_bits {
6576         u8         status[0x8];
6577         u8         reserved_at_8[0x18];
6578
6579         u8         syndrome[0x20];
6580
6581         u8         reserved_at_40[0x40];
6582 };
6583
6584 struct mlx5_ifc_dealloc_q_counter_in_bits {
6585         u8         opcode[0x10];
6586         u8         reserved_at_10[0x10];
6587
6588         u8         reserved_at_20[0x10];
6589         u8         op_mod[0x10];
6590
6591         u8         reserved_at_40[0x18];
6592         u8         counter_set_id[0x8];
6593
6594         u8         reserved_at_60[0x20];
6595 };
6596
6597 struct mlx5_ifc_dealloc_pd_out_bits {
6598         u8         status[0x8];
6599         u8         reserved_at_8[0x18];
6600
6601         u8         syndrome[0x20];
6602
6603         u8         reserved_at_40[0x40];
6604 };
6605
6606 struct mlx5_ifc_dealloc_pd_in_bits {
6607         u8         opcode[0x10];
6608         u8         uid[0x10];
6609
6610         u8         reserved_at_20[0x10];
6611         u8         op_mod[0x10];
6612
6613         u8         reserved_at_40[0x8];
6614         u8         pd[0x18];
6615
6616         u8         reserved_at_60[0x20];
6617 };
6618
6619 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6620         u8         status[0x8];
6621         u8         reserved_at_8[0x18];
6622
6623         u8         syndrome[0x20];
6624
6625         u8         reserved_at_40[0x40];
6626 };
6627
6628 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6629         u8         opcode[0x10];
6630         u8         reserved_at_10[0x10];
6631
6632         u8         reserved_at_20[0x10];
6633         u8         op_mod[0x10];
6634
6635         u8         flow_counter_id[0x20];
6636
6637         u8         reserved_at_60[0x20];
6638 };
6639
6640 struct mlx5_ifc_create_xrq_out_bits {
6641         u8         status[0x8];
6642         u8         reserved_at_8[0x18];
6643
6644         u8         syndrome[0x20];
6645
6646         u8         reserved_at_40[0x8];
6647         u8         xrqn[0x18];
6648
6649         u8         reserved_at_60[0x20];
6650 };
6651
6652 struct mlx5_ifc_create_xrq_in_bits {
6653         u8         opcode[0x10];
6654         u8         uid[0x10];
6655
6656         u8         reserved_at_20[0x10];
6657         u8         op_mod[0x10];
6658
6659         u8         reserved_at_40[0x40];
6660
6661         struct mlx5_ifc_xrqc_bits xrq_context;
6662 };
6663
6664 struct mlx5_ifc_create_xrc_srq_out_bits {
6665         u8         status[0x8];
6666         u8         reserved_at_8[0x18];
6667
6668         u8         syndrome[0x20];
6669
6670         u8         reserved_at_40[0x8];
6671         u8         xrc_srqn[0x18];
6672
6673         u8         reserved_at_60[0x20];
6674 };
6675
6676 struct mlx5_ifc_create_xrc_srq_in_bits {
6677         u8         opcode[0x10];
6678         u8         uid[0x10];
6679
6680         u8         reserved_at_20[0x10];
6681         u8         op_mod[0x10];
6682
6683         u8         reserved_at_40[0x40];
6684
6685         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6686
6687         u8         reserved_at_280[0x40];
6688         u8         xrc_srq_umem_valid[0x1];
6689         u8         reserved_at_2c1[0x5bf];
6690
6691         u8         pas[0][0x40];
6692 };
6693
6694 struct mlx5_ifc_create_tis_out_bits {
6695         u8         status[0x8];
6696         u8         reserved_at_8[0x18];
6697
6698         u8         syndrome[0x20];
6699
6700         u8         reserved_at_40[0x8];
6701         u8         tisn[0x18];
6702
6703         u8         reserved_at_60[0x20];
6704 };
6705
6706 struct mlx5_ifc_create_tis_in_bits {
6707         u8         opcode[0x10];
6708         u8         uid[0x10];
6709
6710         u8         reserved_at_20[0x10];
6711         u8         op_mod[0x10];
6712
6713         u8         reserved_at_40[0xc0];
6714
6715         struct mlx5_ifc_tisc_bits ctx;
6716 };
6717
6718 struct mlx5_ifc_create_tir_out_bits {
6719         u8         status[0x8];
6720         u8         reserved_at_8[0x18];
6721
6722         u8         syndrome[0x20];
6723
6724         u8         reserved_at_40[0x8];
6725         u8         tirn[0x18];
6726
6727         u8         reserved_at_60[0x20];
6728 };
6729
6730 struct mlx5_ifc_create_tir_in_bits {
6731         u8         opcode[0x10];
6732         u8         uid[0x10];
6733
6734         u8         reserved_at_20[0x10];
6735         u8         op_mod[0x10];
6736
6737         u8         reserved_at_40[0xc0];
6738
6739         struct mlx5_ifc_tirc_bits ctx;
6740 };
6741
6742 struct mlx5_ifc_create_srq_out_bits {
6743         u8         status[0x8];
6744         u8         reserved_at_8[0x18];
6745
6746         u8         syndrome[0x20];
6747
6748         u8         reserved_at_40[0x8];
6749         u8         srqn[0x18];
6750
6751         u8         reserved_at_60[0x20];
6752 };
6753
6754 struct mlx5_ifc_create_srq_in_bits {
6755         u8         opcode[0x10];
6756         u8         uid[0x10];
6757
6758         u8         reserved_at_20[0x10];
6759         u8         op_mod[0x10];
6760
6761         u8         reserved_at_40[0x40];
6762
6763         struct mlx5_ifc_srqc_bits srq_context_entry;
6764
6765         u8         reserved_at_280[0x600];
6766
6767         u8         pas[0][0x40];
6768 };
6769
6770 struct mlx5_ifc_create_sq_out_bits {
6771         u8         status[0x8];
6772         u8         reserved_at_8[0x18];
6773
6774         u8         syndrome[0x20];
6775
6776         u8         reserved_at_40[0x8];
6777         u8         sqn[0x18];
6778
6779         u8         reserved_at_60[0x20];
6780 };
6781
6782 struct mlx5_ifc_create_sq_in_bits {
6783         u8         opcode[0x10];
6784         u8         uid[0x10];
6785
6786         u8         reserved_at_20[0x10];
6787         u8         op_mod[0x10];
6788
6789         u8         reserved_at_40[0xc0];
6790
6791         struct mlx5_ifc_sqc_bits ctx;
6792 };
6793
6794 struct mlx5_ifc_create_scheduling_element_out_bits {
6795         u8         status[0x8];
6796         u8         reserved_at_8[0x18];
6797
6798         u8         syndrome[0x20];
6799
6800         u8         reserved_at_40[0x40];
6801
6802         u8         scheduling_element_id[0x20];
6803
6804         u8         reserved_at_a0[0x160];
6805 };
6806
6807 struct mlx5_ifc_create_scheduling_element_in_bits {
6808         u8         opcode[0x10];
6809         u8         reserved_at_10[0x10];
6810
6811         u8         reserved_at_20[0x10];
6812         u8         op_mod[0x10];
6813
6814         u8         scheduling_hierarchy[0x8];
6815         u8         reserved_at_48[0x18];
6816
6817         u8         reserved_at_60[0xa0];
6818
6819         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6820
6821         u8         reserved_at_300[0x100];
6822 };
6823
6824 struct mlx5_ifc_create_rqt_out_bits {
6825         u8         status[0x8];
6826         u8         reserved_at_8[0x18];
6827
6828         u8         syndrome[0x20];
6829
6830         u8         reserved_at_40[0x8];
6831         u8         rqtn[0x18];
6832
6833         u8         reserved_at_60[0x20];
6834 };
6835
6836 struct mlx5_ifc_create_rqt_in_bits {
6837         u8         opcode[0x10];
6838         u8         uid[0x10];
6839
6840         u8         reserved_at_20[0x10];
6841         u8         op_mod[0x10];
6842
6843         u8         reserved_at_40[0xc0];
6844
6845         struct mlx5_ifc_rqtc_bits rqt_context;
6846 };
6847
6848 struct mlx5_ifc_create_rq_out_bits {
6849         u8         status[0x8];
6850         u8         reserved_at_8[0x18];
6851
6852         u8         syndrome[0x20];
6853
6854         u8         reserved_at_40[0x8];
6855         u8         rqn[0x18];
6856
6857         u8         reserved_at_60[0x20];
6858 };
6859
6860 struct mlx5_ifc_create_rq_in_bits {
6861         u8         opcode[0x10];
6862         u8         uid[0x10];
6863
6864         u8         reserved_at_20[0x10];
6865         u8         op_mod[0x10];
6866
6867         u8         reserved_at_40[0xc0];
6868
6869         struct mlx5_ifc_rqc_bits ctx;
6870 };
6871
6872 struct mlx5_ifc_create_rmp_out_bits {
6873         u8         status[0x8];
6874         u8         reserved_at_8[0x18];
6875
6876         u8         syndrome[0x20];
6877
6878         u8         reserved_at_40[0x8];
6879         u8         rmpn[0x18];
6880
6881         u8         reserved_at_60[0x20];
6882 };
6883
6884 struct mlx5_ifc_create_rmp_in_bits {
6885         u8         opcode[0x10];
6886         u8         uid[0x10];
6887
6888         u8         reserved_at_20[0x10];
6889         u8         op_mod[0x10];
6890
6891         u8         reserved_at_40[0xc0];
6892
6893         struct mlx5_ifc_rmpc_bits ctx;
6894 };
6895
6896 struct mlx5_ifc_create_qp_out_bits {
6897         u8         status[0x8];
6898         u8         reserved_at_8[0x18];
6899
6900         u8         syndrome[0x20];
6901
6902         u8         reserved_at_40[0x8];
6903         u8         qpn[0x18];
6904
6905         u8         reserved_at_60[0x20];
6906 };
6907
6908 struct mlx5_ifc_create_qp_in_bits {
6909         u8         opcode[0x10];
6910         u8         uid[0x10];
6911
6912         u8         reserved_at_20[0x10];
6913         u8         op_mod[0x10];
6914
6915         u8         reserved_at_40[0x40];
6916
6917         u8         opt_param_mask[0x20];
6918
6919         u8         reserved_at_a0[0x20];
6920
6921         struct mlx5_ifc_qpc_bits qpc;
6922
6923         u8         reserved_at_800[0x60];
6924
6925         u8         wq_umem_valid[0x1];
6926         u8         reserved_at_861[0x1f];
6927
6928         u8         pas[0][0x40];
6929 };
6930
6931 struct mlx5_ifc_create_psv_out_bits {
6932         u8         status[0x8];
6933         u8         reserved_at_8[0x18];
6934
6935         u8         syndrome[0x20];
6936
6937         u8         reserved_at_40[0x40];
6938
6939         u8         reserved_at_80[0x8];
6940         u8         psv0_index[0x18];
6941
6942         u8         reserved_at_a0[0x8];
6943         u8         psv1_index[0x18];
6944
6945         u8         reserved_at_c0[0x8];
6946         u8         psv2_index[0x18];
6947
6948         u8         reserved_at_e0[0x8];
6949         u8         psv3_index[0x18];
6950 };
6951
6952 struct mlx5_ifc_create_psv_in_bits {
6953         u8         opcode[0x10];
6954         u8         reserved_at_10[0x10];
6955
6956         u8         reserved_at_20[0x10];
6957         u8         op_mod[0x10];
6958
6959         u8         num_psv[0x4];
6960         u8         reserved_at_44[0x4];
6961         u8         pd[0x18];
6962
6963         u8         reserved_at_60[0x20];
6964 };
6965
6966 struct mlx5_ifc_create_mkey_out_bits {
6967         u8         status[0x8];
6968         u8         reserved_at_8[0x18];
6969
6970         u8         syndrome[0x20];
6971
6972         u8         reserved_at_40[0x8];
6973         u8         mkey_index[0x18];
6974
6975         u8         reserved_at_60[0x20];
6976 };
6977
6978 struct mlx5_ifc_create_mkey_in_bits {
6979         u8         opcode[0x10];
6980         u8         reserved_at_10[0x10];
6981
6982         u8         reserved_at_20[0x10];
6983         u8         op_mod[0x10];
6984
6985         u8         reserved_at_40[0x20];
6986
6987         u8         pg_access[0x1];
6988         u8         mkey_umem_valid[0x1];
6989         u8         reserved_at_62[0x1e];
6990
6991         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6992
6993         u8         reserved_at_280[0x80];
6994
6995         u8         translations_octword_actual_size[0x20];
6996
6997         u8         reserved_at_320[0x560];
6998
6999         u8         klm_pas_mtt[0][0x20];
7000 };
7001
7002 struct mlx5_ifc_create_flow_table_out_bits {
7003         u8         status[0x8];
7004         u8         reserved_at_8[0x18];
7005
7006         u8         syndrome[0x20];
7007
7008         u8         reserved_at_40[0x8];
7009         u8         table_id[0x18];
7010
7011         u8         reserved_at_60[0x20];
7012 };
7013
7014 struct mlx5_ifc_flow_table_context_bits {
7015         u8         reformat_en[0x1];
7016         u8         decap_en[0x1];
7017         u8         reserved_at_2[0x2];
7018         u8         table_miss_action[0x4];
7019         u8         level[0x8];
7020         u8         reserved_at_10[0x8];
7021         u8         log_size[0x8];
7022
7023         u8         reserved_at_20[0x8];
7024         u8         table_miss_id[0x18];
7025
7026         u8         reserved_at_40[0x8];
7027         u8         lag_master_next_table_id[0x18];
7028
7029         u8         reserved_at_60[0xe0];
7030 };
7031
7032 struct mlx5_ifc_create_flow_table_in_bits {
7033         u8         opcode[0x10];
7034         u8         reserved_at_10[0x10];
7035
7036         u8         reserved_at_20[0x10];
7037         u8         op_mod[0x10];
7038
7039         u8         other_vport[0x1];
7040         u8         reserved_at_41[0xf];
7041         u8         vport_number[0x10];
7042
7043         u8         reserved_at_60[0x20];
7044
7045         u8         table_type[0x8];
7046         u8         reserved_at_88[0x18];
7047
7048         u8         reserved_at_a0[0x20];
7049
7050         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7051 };
7052
7053 struct mlx5_ifc_create_flow_group_out_bits {
7054         u8         status[0x8];
7055         u8         reserved_at_8[0x18];
7056
7057         u8         syndrome[0x20];
7058
7059         u8         reserved_at_40[0x8];
7060         u8         group_id[0x18];
7061
7062         u8         reserved_at_60[0x20];
7063 };
7064
7065 enum {
7066         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7067         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7068         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7069         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7070 };
7071
7072 struct mlx5_ifc_create_flow_group_in_bits {
7073         u8         opcode[0x10];
7074         u8         reserved_at_10[0x10];
7075
7076         u8         reserved_at_20[0x10];
7077         u8         op_mod[0x10];
7078
7079         u8         other_vport[0x1];
7080         u8         reserved_at_41[0xf];
7081         u8         vport_number[0x10];
7082
7083         u8         reserved_at_60[0x20];
7084
7085         u8         table_type[0x8];
7086         u8         reserved_at_88[0x18];
7087
7088         u8         reserved_at_a0[0x8];
7089         u8         table_id[0x18];
7090
7091         u8         source_eswitch_owner_vhca_id_valid[0x1];
7092
7093         u8         reserved_at_c1[0x1f];
7094
7095         u8         start_flow_index[0x20];
7096
7097         u8         reserved_at_100[0x20];
7098
7099         u8         end_flow_index[0x20];
7100
7101         u8         reserved_at_140[0xa0];
7102
7103         u8         reserved_at_1e0[0x18];
7104         u8         match_criteria_enable[0x8];
7105
7106         struct mlx5_ifc_fte_match_param_bits match_criteria;
7107
7108         u8         reserved_at_1200[0xe00];
7109 };
7110
7111 struct mlx5_ifc_create_eq_out_bits {
7112         u8         status[0x8];
7113         u8         reserved_at_8[0x18];
7114
7115         u8         syndrome[0x20];
7116
7117         u8         reserved_at_40[0x18];
7118         u8         eq_number[0x8];
7119
7120         u8         reserved_at_60[0x20];
7121 };
7122
7123 struct mlx5_ifc_create_eq_in_bits {
7124         u8         opcode[0x10];
7125         u8         reserved_at_10[0x10];
7126
7127         u8         reserved_at_20[0x10];
7128         u8         op_mod[0x10];
7129
7130         u8         reserved_at_40[0x40];
7131
7132         struct mlx5_ifc_eqc_bits eq_context_entry;
7133
7134         u8         reserved_at_280[0x40];
7135
7136         u8         event_bitmask[0x40];
7137
7138         u8         reserved_at_300[0x580];
7139
7140         u8         pas[0][0x40];
7141 };
7142
7143 struct mlx5_ifc_create_dct_out_bits {
7144         u8         status[0x8];
7145         u8         reserved_at_8[0x18];
7146
7147         u8         syndrome[0x20];
7148
7149         u8         reserved_at_40[0x8];
7150         u8         dctn[0x18];
7151
7152         u8         reserved_at_60[0x20];
7153 };
7154
7155 struct mlx5_ifc_create_dct_in_bits {
7156         u8         opcode[0x10];
7157         u8         uid[0x10];
7158
7159         u8         reserved_at_20[0x10];
7160         u8         op_mod[0x10];
7161
7162         u8         reserved_at_40[0x40];
7163
7164         struct mlx5_ifc_dctc_bits dct_context_entry;
7165
7166         u8         reserved_at_280[0x180];
7167 };
7168
7169 struct mlx5_ifc_create_cq_out_bits {
7170         u8         status[0x8];
7171         u8         reserved_at_8[0x18];
7172
7173         u8         syndrome[0x20];
7174
7175         u8         reserved_at_40[0x8];
7176         u8         cqn[0x18];
7177
7178         u8         reserved_at_60[0x20];
7179 };
7180
7181 struct mlx5_ifc_create_cq_in_bits {
7182         u8         opcode[0x10];
7183         u8         uid[0x10];
7184
7185         u8         reserved_at_20[0x10];
7186         u8         op_mod[0x10];
7187
7188         u8         reserved_at_40[0x40];
7189
7190         struct mlx5_ifc_cqc_bits cq_context;
7191
7192         u8         reserved_at_280[0x60];
7193
7194         u8         cq_umem_valid[0x1];
7195         u8         reserved_at_2e1[0x59f];
7196
7197         u8         pas[0][0x40];
7198 };
7199
7200 struct mlx5_ifc_config_int_moderation_out_bits {
7201         u8         status[0x8];
7202         u8         reserved_at_8[0x18];
7203
7204         u8         syndrome[0x20];
7205
7206         u8         reserved_at_40[0x4];
7207         u8         min_delay[0xc];
7208         u8         int_vector[0x10];
7209
7210         u8         reserved_at_60[0x20];
7211 };
7212
7213 enum {
7214         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7215         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7216 };
7217
7218 struct mlx5_ifc_config_int_moderation_in_bits {
7219         u8         opcode[0x10];
7220         u8         reserved_at_10[0x10];
7221
7222         u8         reserved_at_20[0x10];
7223         u8         op_mod[0x10];
7224
7225         u8         reserved_at_40[0x4];
7226         u8         min_delay[0xc];
7227         u8         int_vector[0x10];
7228
7229         u8         reserved_at_60[0x20];
7230 };
7231
7232 struct mlx5_ifc_attach_to_mcg_out_bits {
7233         u8         status[0x8];
7234         u8         reserved_at_8[0x18];
7235
7236         u8         syndrome[0x20];
7237
7238         u8         reserved_at_40[0x40];
7239 };
7240
7241 struct mlx5_ifc_attach_to_mcg_in_bits {
7242         u8         opcode[0x10];
7243         u8         uid[0x10];
7244
7245         u8         reserved_at_20[0x10];
7246         u8         op_mod[0x10];
7247
7248         u8         reserved_at_40[0x8];
7249         u8         qpn[0x18];
7250
7251         u8         reserved_at_60[0x20];
7252
7253         u8         multicast_gid[16][0x8];
7254 };
7255
7256 struct mlx5_ifc_arm_xrq_out_bits {
7257         u8         status[0x8];
7258         u8         reserved_at_8[0x18];
7259
7260         u8         syndrome[0x20];
7261
7262         u8         reserved_at_40[0x40];
7263 };
7264
7265 struct mlx5_ifc_arm_xrq_in_bits {
7266         u8         opcode[0x10];
7267         u8         reserved_at_10[0x10];
7268
7269         u8         reserved_at_20[0x10];
7270         u8         op_mod[0x10];
7271
7272         u8         reserved_at_40[0x8];
7273         u8         xrqn[0x18];
7274
7275         u8         reserved_at_60[0x10];
7276         u8         lwm[0x10];
7277 };
7278
7279 struct mlx5_ifc_arm_xrc_srq_out_bits {
7280         u8         status[0x8];
7281         u8         reserved_at_8[0x18];
7282
7283         u8         syndrome[0x20];
7284
7285         u8         reserved_at_40[0x40];
7286 };
7287
7288 enum {
7289         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7290 };
7291
7292 struct mlx5_ifc_arm_xrc_srq_in_bits {
7293         u8         opcode[0x10];
7294         u8         uid[0x10];
7295
7296         u8         reserved_at_20[0x10];
7297         u8         op_mod[0x10];
7298
7299         u8         reserved_at_40[0x8];
7300         u8         xrc_srqn[0x18];
7301
7302         u8         reserved_at_60[0x10];
7303         u8         lwm[0x10];
7304 };
7305
7306 struct mlx5_ifc_arm_rq_out_bits {
7307         u8         status[0x8];
7308         u8         reserved_at_8[0x18];
7309
7310         u8         syndrome[0x20];
7311
7312         u8         reserved_at_40[0x40];
7313 };
7314
7315 enum {
7316         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7317         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7318 };
7319
7320 struct mlx5_ifc_arm_rq_in_bits {
7321         u8         opcode[0x10];
7322         u8         uid[0x10];
7323
7324         u8         reserved_at_20[0x10];
7325         u8         op_mod[0x10];
7326
7327         u8         reserved_at_40[0x8];
7328         u8         srq_number[0x18];
7329
7330         u8         reserved_at_60[0x10];
7331         u8         lwm[0x10];
7332 };
7333
7334 struct mlx5_ifc_arm_dct_out_bits {
7335         u8         status[0x8];
7336         u8         reserved_at_8[0x18];
7337
7338         u8         syndrome[0x20];
7339
7340         u8         reserved_at_40[0x40];
7341 };
7342
7343 struct mlx5_ifc_arm_dct_in_bits {
7344         u8         opcode[0x10];
7345         u8         reserved_at_10[0x10];
7346
7347         u8         reserved_at_20[0x10];
7348         u8         op_mod[0x10];
7349
7350         u8         reserved_at_40[0x8];
7351         u8         dct_number[0x18];
7352
7353         u8         reserved_at_60[0x20];
7354 };
7355
7356 struct mlx5_ifc_alloc_xrcd_out_bits {
7357         u8         status[0x8];
7358         u8         reserved_at_8[0x18];
7359
7360         u8         syndrome[0x20];
7361
7362         u8         reserved_at_40[0x8];
7363         u8         xrcd[0x18];
7364
7365         u8         reserved_at_60[0x20];
7366 };
7367
7368 struct mlx5_ifc_alloc_xrcd_in_bits {
7369         u8         opcode[0x10];
7370         u8         uid[0x10];
7371
7372         u8         reserved_at_20[0x10];
7373         u8         op_mod[0x10];
7374
7375         u8         reserved_at_40[0x40];
7376 };
7377
7378 struct mlx5_ifc_alloc_uar_out_bits {
7379         u8         status[0x8];
7380         u8         reserved_at_8[0x18];
7381
7382         u8         syndrome[0x20];
7383
7384         u8         reserved_at_40[0x8];
7385         u8         uar[0x18];
7386
7387         u8         reserved_at_60[0x20];
7388 };
7389
7390 struct mlx5_ifc_alloc_uar_in_bits {
7391         u8         opcode[0x10];
7392         u8         reserved_at_10[0x10];
7393
7394         u8         reserved_at_20[0x10];
7395         u8         op_mod[0x10];
7396
7397         u8         reserved_at_40[0x40];
7398 };
7399
7400 struct mlx5_ifc_alloc_transport_domain_out_bits {
7401         u8         status[0x8];
7402         u8         reserved_at_8[0x18];
7403
7404         u8         syndrome[0x20];
7405
7406         u8         reserved_at_40[0x8];
7407         u8         transport_domain[0x18];
7408
7409         u8         reserved_at_60[0x20];
7410 };
7411
7412 struct mlx5_ifc_alloc_transport_domain_in_bits {
7413         u8         opcode[0x10];
7414         u8         reserved_at_10[0x10];
7415
7416         u8         reserved_at_20[0x10];
7417         u8         op_mod[0x10];
7418
7419         u8         reserved_at_40[0x40];
7420 };
7421
7422 struct mlx5_ifc_alloc_q_counter_out_bits {
7423         u8         status[0x8];
7424         u8         reserved_at_8[0x18];
7425
7426         u8         syndrome[0x20];
7427
7428         u8         reserved_at_40[0x18];
7429         u8         counter_set_id[0x8];
7430
7431         u8         reserved_at_60[0x20];
7432 };
7433
7434 struct mlx5_ifc_alloc_q_counter_in_bits {
7435         u8         opcode[0x10];
7436         u8         reserved_at_10[0x10];
7437
7438         u8         reserved_at_20[0x10];
7439         u8         op_mod[0x10];
7440
7441         u8         reserved_at_40[0x40];
7442 };
7443
7444 struct mlx5_ifc_alloc_pd_out_bits {
7445         u8         status[0x8];
7446         u8         reserved_at_8[0x18];
7447
7448         u8         syndrome[0x20];
7449
7450         u8         reserved_at_40[0x8];
7451         u8         pd[0x18];
7452
7453         u8         reserved_at_60[0x20];
7454 };
7455
7456 struct mlx5_ifc_alloc_pd_in_bits {
7457         u8         opcode[0x10];
7458         u8         uid[0x10];
7459
7460         u8         reserved_at_20[0x10];
7461         u8         op_mod[0x10];
7462
7463         u8         reserved_at_40[0x40];
7464 };
7465
7466 struct mlx5_ifc_alloc_flow_counter_out_bits {
7467         u8         status[0x8];
7468         u8         reserved_at_8[0x18];
7469
7470         u8         syndrome[0x20];
7471
7472         u8         flow_counter_id[0x20];
7473
7474         u8         reserved_at_60[0x20];
7475 };
7476
7477 struct mlx5_ifc_alloc_flow_counter_in_bits {
7478         u8         opcode[0x10];
7479         u8         reserved_at_10[0x10];
7480
7481         u8         reserved_at_20[0x10];
7482         u8         op_mod[0x10];
7483
7484         u8         reserved_at_40[0x40];
7485 };
7486
7487 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7488         u8         status[0x8];
7489         u8         reserved_at_8[0x18];
7490
7491         u8         syndrome[0x20];
7492
7493         u8         reserved_at_40[0x40];
7494 };
7495
7496 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7497         u8         opcode[0x10];
7498         u8         reserved_at_10[0x10];
7499
7500         u8         reserved_at_20[0x10];
7501         u8         op_mod[0x10];
7502
7503         u8         reserved_at_40[0x20];
7504
7505         u8         reserved_at_60[0x10];
7506         u8         vxlan_udp_port[0x10];
7507 };
7508
7509 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7510         u8         status[0x8];
7511         u8         reserved_at_8[0x18];
7512
7513         u8         syndrome[0x20];
7514
7515         u8         reserved_at_40[0x40];
7516 };
7517
7518 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7519         u8         opcode[0x10];
7520         u8         reserved_at_10[0x10];
7521
7522         u8         reserved_at_20[0x10];
7523         u8         op_mod[0x10];
7524
7525         u8         reserved_at_40[0x10];
7526         u8         rate_limit_index[0x10];
7527
7528         u8         reserved_at_60[0x20];
7529
7530         u8         rate_limit[0x20];
7531
7532         u8         burst_upper_bound[0x20];
7533
7534         u8         reserved_at_c0[0x10];
7535         u8         typical_packet_size[0x10];
7536
7537         u8         reserved_at_e0[0x120];
7538 };
7539
7540 struct mlx5_ifc_access_register_out_bits {
7541         u8         status[0x8];
7542         u8         reserved_at_8[0x18];
7543
7544         u8         syndrome[0x20];
7545
7546         u8         reserved_at_40[0x40];
7547
7548         u8         register_data[0][0x20];
7549 };
7550
7551 enum {
7552         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7553         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7554 };
7555
7556 struct mlx5_ifc_access_register_in_bits {
7557         u8         opcode[0x10];
7558         u8         reserved_at_10[0x10];
7559
7560         u8         reserved_at_20[0x10];
7561         u8         op_mod[0x10];
7562
7563         u8         reserved_at_40[0x10];
7564         u8         register_id[0x10];
7565
7566         u8         argument[0x20];
7567
7568         u8         register_data[0][0x20];
7569 };
7570
7571 struct mlx5_ifc_sltp_reg_bits {
7572         u8         status[0x4];
7573         u8         version[0x4];
7574         u8         local_port[0x8];
7575         u8         pnat[0x2];
7576         u8         reserved_at_12[0x2];
7577         u8         lane[0x4];
7578         u8         reserved_at_18[0x8];
7579
7580         u8         reserved_at_20[0x20];
7581
7582         u8         reserved_at_40[0x7];
7583         u8         polarity[0x1];
7584         u8         ob_tap0[0x8];
7585         u8         ob_tap1[0x8];
7586         u8         ob_tap2[0x8];
7587
7588         u8         reserved_at_60[0xc];
7589         u8         ob_preemp_mode[0x4];
7590         u8         ob_reg[0x8];
7591         u8         ob_bias[0x8];
7592
7593         u8         reserved_at_80[0x20];
7594 };
7595
7596 struct mlx5_ifc_slrg_reg_bits {
7597         u8         status[0x4];
7598         u8         version[0x4];
7599         u8         local_port[0x8];
7600         u8         pnat[0x2];
7601         u8         reserved_at_12[0x2];
7602         u8         lane[0x4];
7603         u8         reserved_at_18[0x8];
7604
7605         u8         time_to_link_up[0x10];
7606         u8         reserved_at_30[0xc];
7607         u8         grade_lane_speed[0x4];
7608
7609         u8         grade_version[0x8];
7610         u8         grade[0x18];
7611
7612         u8         reserved_at_60[0x4];
7613         u8         height_grade_type[0x4];
7614         u8         height_grade[0x18];
7615
7616         u8         height_dz[0x10];
7617         u8         height_dv[0x10];
7618
7619         u8         reserved_at_a0[0x10];
7620         u8         height_sigma[0x10];
7621
7622         u8         reserved_at_c0[0x20];
7623
7624         u8         reserved_at_e0[0x4];
7625         u8         phase_grade_type[0x4];
7626         u8         phase_grade[0x18];
7627
7628         u8         reserved_at_100[0x8];
7629         u8         phase_eo_pos[0x8];
7630         u8         reserved_at_110[0x8];
7631         u8         phase_eo_neg[0x8];
7632
7633         u8         ffe_set_tested[0x10];
7634         u8         test_errors_per_lane[0x10];
7635 };
7636
7637 struct mlx5_ifc_pvlc_reg_bits {
7638         u8         reserved_at_0[0x8];
7639         u8         local_port[0x8];
7640         u8         reserved_at_10[0x10];
7641
7642         u8         reserved_at_20[0x1c];
7643         u8         vl_hw_cap[0x4];
7644
7645         u8         reserved_at_40[0x1c];
7646         u8         vl_admin[0x4];
7647
7648         u8         reserved_at_60[0x1c];
7649         u8         vl_operational[0x4];
7650 };
7651
7652 struct mlx5_ifc_pude_reg_bits {
7653         u8         swid[0x8];
7654         u8         local_port[0x8];
7655         u8         reserved_at_10[0x4];
7656         u8         admin_status[0x4];
7657         u8         reserved_at_18[0x4];
7658         u8         oper_status[0x4];
7659
7660         u8         reserved_at_20[0x60];
7661 };
7662
7663 struct mlx5_ifc_ptys_reg_bits {
7664         u8         reserved_at_0[0x1];
7665         u8         an_disable_admin[0x1];
7666         u8         an_disable_cap[0x1];
7667         u8         reserved_at_3[0x5];
7668         u8         local_port[0x8];
7669         u8         reserved_at_10[0xd];
7670         u8         proto_mask[0x3];
7671
7672         u8         an_status[0x4];
7673         u8         reserved_at_24[0x3c];
7674
7675         u8         eth_proto_capability[0x20];
7676
7677         u8         ib_link_width_capability[0x10];
7678         u8         ib_proto_capability[0x10];
7679
7680         u8         reserved_at_a0[0x20];
7681
7682         u8         eth_proto_admin[0x20];
7683
7684         u8         ib_link_width_admin[0x10];
7685         u8         ib_proto_admin[0x10];
7686
7687         u8         reserved_at_100[0x20];
7688
7689         u8         eth_proto_oper[0x20];
7690
7691         u8         ib_link_width_oper[0x10];
7692         u8         ib_proto_oper[0x10];
7693
7694         u8         reserved_at_160[0x1c];
7695         u8         connector_type[0x4];
7696
7697         u8         eth_proto_lp_advertise[0x20];
7698
7699         u8         reserved_at_1a0[0x60];
7700 };
7701
7702 struct mlx5_ifc_mlcr_reg_bits {
7703         u8         reserved_at_0[0x8];
7704         u8         local_port[0x8];
7705         u8         reserved_at_10[0x20];
7706
7707         u8         beacon_duration[0x10];
7708         u8         reserved_at_40[0x10];
7709
7710         u8         beacon_remain[0x10];
7711 };
7712
7713 struct mlx5_ifc_ptas_reg_bits {
7714         u8         reserved_at_0[0x20];
7715
7716         u8         algorithm_options[0x10];
7717         u8         reserved_at_30[0x4];
7718         u8         repetitions_mode[0x4];
7719         u8         num_of_repetitions[0x8];
7720
7721         u8         grade_version[0x8];
7722         u8         height_grade_type[0x4];
7723         u8         phase_grade_type[0x4];
7724         u8         height_grade_weight[0x8];
7725         u8         phase_grade_weight[0x8];
7726
7727         u8         gisim_measure_bits[0x10];
7728         u8         adaptive_tap_measure_bits[0x10];
7729
7730         u8         ber_bath_high_error_threshold[0x10];
7731         u8         ber_bath_mid_error_threshold[0x10];
7732
7733         u8         ber_bath_low_error_threshold[0x10];
7734         u8         one_ratio_high_threshold[0x10];
7735
7736         u8         one_ratio_high_mid_threshold[0x10];
7737         u8         one_ratio_low_mid_threshold[0x10];
7738
7739         u8         one_ratio_low_threshold[0x10];
7740         u8         ndeo_error_threshold[0x10];
7741
7742         u8         mixer_offset_step_size[0x10];
7743         u8         reserved_at_110[0x8];
7744         u8         mix90_phase_for_voltage_bath[0x8];
7745
7746         u8         mixer_offset_start[0x10];
7747         u8         mixer_offset_end[0x10];
7748
7749         u8         reserved_at_140[0x15];
7750         u8         ber_test_time[0xb];
7751 };
7752
7753 struct mlx5_ifc_pspa_reg_bits {
7754         u8         swid[0x8];
7755         u8         local_port[0x8];
7756         u8         sub_port[0x8];
7757         u8         reserved_at_18[0x8];
7758
7759         u8         reserved_at_20[0x20];
7760 };
7761
7762 struct mlx5_ifc_pqdr_reg_bits {
7763         u8         reserved_at_0[0x8];
7764         u8         local_port[0x8];
7765         u8         reserved_at_10[0x5];
7766         u8         prio[0x3];
7767         u8         reserved_at_18[0x6];
7768         u8         mode[0x2];
7769
7770         u8         reserved_at_20[0x20];
7771
7772         u8         reserved_at_40[0x10];
7773         u8         min_threshold[0x10];
7774
7775         u8         reserved_at_60[0x10];
7776         u8         max_threshold[0x10];
7777
7778         u8         reserved_at_80[0x10];
7779         u8         mark_probability_denominator[0x10];
7780
7781         u8         reserved_at_a0[0x60];
7782 };
7783
7784 struct mlx5_ifc_ppsc_reg_bits {
7785         u8         reserved_at_0[0x8];
7786         u8         local_port[0x8];
7787         u8         reserved_at_10[0x10];
7788
7789         u8         reserved_at_20[0x60];
7790
7791         u8         reserved_at_80[0x1c];
7792         u8         wrps_admin[0x4];
7793
7794         u8         reserved_at_a0[0x1c];
7795         u8         wrps_status[0x4];
7796
7797         u8         reserved_at_c0[0x8];
7798         u8         up_threshold[0x8];
7799         u8         reserved_at_d0[0x8];
7800         u8         down_threshold[0x8];
7801
7802         u8         reserved_at_e0[0x20];
7803
7804         u8         reserved_at_100[0x1c];
7805         u8         srps_admin[0x4];
7806
7807         u8         reserved_at_120[0x1c];
7808         u8         srps_status[0x4];
7809
7810         u8         reserved_at_140[0x40];
7811 };
7812
7813 struct mlx5_ifc_pplr_reg_bits {
7814         u8         reserved_at_0[0x8];
7815         u8         local_port[0x8];
7816         u8         reserved_at_10[0x10];
7817
7818         u8         reserved_at_20[0x8];
7819         u8         lb_cap[0x8];
7820         u8         reserved_at_30[0x8];
7821         u8         lb_en[0x8];
7822 };
7823
7824 struct mlx5_ifc_pplm_reg_bits {
7825         u8         reserved_at_0[0x8];
7826         u8         local_port[0x8];
7827         u8         reserved_at_10[0x10];
7828
7829         u8         reserved_at_20[0x20];
7830
7831         u8         port_profile_mode[0x8];
7832         u8         static_port_profile[0x8];
7833         u8         active_port_profile[0x8];
7834         u8         reserved_at_58[0x8];
7835
7836         u8         retransmission_active[0x8];
7837         u8         fec_mode_active[0x18];
7838
7839         u8         reserved_at_80[0x20];
7840 };
7841
7842 struct mlx5_ifc_ppcnt_reg_bits {
7843         u8         swid[0x8];
7844         u8         local_port[0x8];
7845         u8         pnat[0x2];
7846         u8         reserved_at_12[0x8];
7847         u8         grp[0x6];
7848
7849         u8         clr[0x1];
7850         u8         reserved_at_21[0x1c];
7851         u8         prio_tc[0x3];
7852
7853         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7854 };
7855
7856 struct mlx5_ifc_mpcnt_reg_bits {
7857         u8         reserved_at_0[0x8];
7858         u8         pcie_index[0x8];
7859         u8         reserved_at_10[0xa];
7860         u8         grp[0x6];
7861
7862         u8         clr[0x1];
7863         u8         reserved_at_21[0x1f];
7864
7865         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7866 };
7867
7868 struct mlx5_ifc_ppad_reg_bits {
7869         u8         reserved_at_0[0x3];
7870         u8         single_mac[0x1];
7871         u8         reserved_at_4[0x4];
7872         u8         local_port[0x8];
7873         u8         mac_47_32[0x10];
7874
7875         u8         mac_31_0[0x20];
7876
7877         u8         reserved_at_40[0x40];
7878 };
7879
7880 struct mlx5_ifc_pmtu_reg_bits {
7881         u8         reserved_at_0[0x8];
7882         u8         local_port[0x8];
7883         u8         reserved_at_10[0x10];
7884
7885         u8         max_mtu[0x10];
7886         u8         reserved_at_30[0x10];
7887
7888         u8         admin_mtu[0x10];
7889         u8         reserved_at_50[0x10];
7890
7891         u8         oper_mtu[0x10];
7892         u8         reserved_at_70[0x10];
7893 };
7894
7895 struct mlx5_ifc_pmpr_reg_bits {
7896         u8         reserved_at_0[0x8];
7897         u8         module[0x8];
7898         u8         reserved_at_10[0x10];
7899
7900         u8         reserved_at_20[0x18];
7901         u8         attenuation_5g[0x8];
7902
7903         u8         reserved_at_40[0x18];
7904         u8         attenuation_7g[0x8];
7905
7906         u8         reserved_at_60[0x18];
7907         u8         attenuation_12g[0x8];
7908 };
7909
7910 struct mlx5_ifc_pmpe_reg_bits {
7911         u8         reserved_at_0[0x8];
7912         u8         module[0x8];
7913         u8         reserved_at_10[0xc];
7914         u8         module_status[0x4];
7915
7916         u8         reserved_at_20[0x60];
7917 };
7918
7919 struct mlx5_ifc_pmpc_reg_bits {
7920         u8         module_state_updated[32][0x8];
7921 };
7922
7923 struct mlx5_ifc_pmlpn_reg_bits {
7924         u8         reserved_at_0[0x4];
7925         u8         mlpn_status[0x4];
7926         u8         local_port[0x8];
7927         u8         reserved_at_10[0x10];
7928
7929         u8         e[0x1];
7930         u8         reserved_at_21[0x1f];
7931 };
7932
7933 struct mlx5_ifc_pmlp_reg_bits {
7934         u8         rxtx[0x1];
7935         u8         reserved_at_1[0x7];
7936         u8         local_port[0x8];
7937         u8         reserved_at_10[0x8];
7938         u8         width[0x8];
7939
7940         u8         lane0_module_mapping[0x20];
7941
7942         u8         lane1_module_mapping[0x20];
7943
7944         u8         lane2_module_mapping[0x20];
7945
7946         u8         lane3_module_mapping[0x20];
7947
7948         u8         reserved_at_a0[0x160];
7949 };
7950
7951 struct mlx5_ifc_pmaos_reg_bits {
7952         u8         reserved_at_0[0x8];
7953         u8         module[0x8];
7954         u8         reserved_at_10[0x4];
7955         u8         admin_status[0x4];
7956         u8         reserved_at_18[0x4];
7957         u8         oper_status[0x4];
7958
7959         u8         ase[0x1];
7960         u8         ee[0x1];
7961         u8         reserved_at_22[0x1c];
7962         u8         e[0x2];
7963
7964         u8         reserved_at_40[0x40];
7965 };
7966
7967 struct mlx5_ifc_plpc_reg_bits {
7968         u8         reserved_at_0[0x4];
7969         u8         profile_id[0xc];
7970         u8         reserved_at_10[0x4];
7971         u8         proto_mask[0x4];
7972         u8         reserved_at_18[0x8];
7973
7974         u8         reserved_at_20[0x10];
7975         u8         lane_speed[0x10];
7976
7977         u8         reserved_at_40[0x17];
7978         u8         lpbf[0x1];
7979         u8         fec_mode_policy[0x8];
7980
7981         u8         retransmission_capability[0x8];
7982         u8         fec_mode_capability[0x18];
7983
7984         u8         retransmission_support_admin[0x8];
7985         u8         fec_mode_support_admin[0x18];
7986
7987         u8         retransmission_request_admin[0x8];
7988         u8         fec_mode_request_admin[0x18];
7989
7990         u8         reserved_at_c0[0x80];
7991 };
7992
7993 struct mlx5_ifc_plib_reg_bits {
7994         u8         reserved_at_0[0x8];
7995         u8         local_port[0x8];
7996         u8         reserved_at_10[0x8];
7997         u8         ib_port[0x8];
7998
7999         u8         reserved_at_20[0x60];
8000 };
8001
8002 struct mlx5_ifc_plbf_reg_bits {
8003         u8         reserved_at_0[0x8];
8004         u8         local_port[0x8];
8005         u8         reserved_at_10[0xd];
8006         u8         lbf_mode[0x3];
8007
8008         u8         reserved_at_20[0x20];
8009 };
8010
8011 struct mlx5_ifc_pipg_reg_bits {
8012         u8         reserved_at_0[0x8];
8013         u8         local_port[0x8];
8014         u8         reserved_at_10[0x10];
8015
8016         u8         dic[0x1];
8017         u8         reserved_at_21[0x19];
8018         u8         ipg[0x4];
8019         u8         reserved_at_3e[0x2];
8020 };
8021
8022 struct mlx5_ifc_pifr_reg_bits {
8023         u8         reserved_at_0[0x8];
8024         u8         local_port[0x8];
8025         u8         reserved_at_10[0x10];
8026
8027         u8         reserved_at_20[0xe0];
8028
8029         u8         port_filter[8][0x20];
8030
8031         u8         port_filter_update_en[8][0x20];
8032 };
8033
8034 struct mlx5_ifc_pfcc_reg_bits {
8035         u8         reserved_at_0[0x8];
8036         u8         local_port[0x8];
8037         u8         reserved_at_10[0xb];
8038         u8         ppan_mask_n[0x1];
8039         u8         minor_stall_mask[0x1];
8040         u8         critical_stall_mask[0x1];
8041         u8         reserved_at_1e[0x2];
8042
8043         u8         ppan[0x4];
8044         u8         reserved_at_24[0x4];
8045         u8         prio_mask_tx[0x8];
8046         u8         reserved_at_30[0x8];
8047         u8         prio_mask_rx[0x8];
8048
8049         u8         pptx[0x1];
8050         u8         aptx[0x1];
8051         u8         pptx_mask_n[0x1];
8052         u8         reserved_at_43[0x5];
8053         u8         pfctx[0x8];
8054         u8         reserved_at_50[0x10];
8055
8056         u8         pprx[0x1];
8057         u8         aprx[0x1];
8058         u8         pprx_mask_n[0x1];
8059         u8         reserved_at_63[0x5];
8060         u8         pfcrx[0x8];
8061         u8         reserved_at_70[0x10];
8062
8063         u8         device_stall_minor_watermark[0x10];
8064         u8         device_stall_critical_watermark[0x10];
8065
8066         u8         reserved_at_a0[0x60];
8067 };
8068
8069 struct mlx5_ifc_pelc_reg_bits {
8070         u8         op[0x4];
8071         u8         reserved_at_4[0x4];
8072         u8         local_port[0x8];
8073         u8         reserved_at_10[0x10];
8074
8075         u8         op_admin[0x8];
8076         u8         op_capability[0x8];
8077         u8         op_request[0x8];
8078         u8         op_active[0x8];
8079
8080         u8         admin[0x40];
8081
8082         u8         capability[0x40];
8083
8084         u8         request[0x40];
8085
8086         u8         active[0x40];
8087
8088         u8         reserved_at_140[0x80];
8089 };
8090
8091 struct mlx5_ifc_peir_reg_bits {
8092         u8         reserved_at_0[0x8];
8093         u8         local_port[0x8];
8094         u8         reserved_at_10[0x10];
8095
8096         u8         reserved_at_20[0xc];
8097         u8         error_count[0x4];
8098         u8         reserved_at_30[0x10];
8099
8100         u8         reserved_at_40[0xc];
8101         u8         lane[0x4];
8102         u8         reserved_at_50[0x8];
8103         u8         error_type[0x8];
8104 };
8105
8106 struct mlx5_ifc_mpegc_reg_bits {
8107         u8         reserved_at_0[0x30];
8108         u8         field_select[0x10];
8109
8110         u8         tx_overflow_sense[0x1];
8111         u8         mark_cqe[0x1];
8112         u8         mark_cnp[0x1];
8113         u8         reserved_at_43[0x1b];
8114         u8         tx_lossy_overflow_oper[0x2];
8115
8116         u8         reserved_at_60[0x100];
8117 };
8118
8119 struct mlx5_ifc_pcam_enhanced_features_bits {
8120         u8         reserved_at_0[0x6d];
8121         u8         rx_icrc_encapsulated_counter[0x1];
8122         u8         reserved_at_6e[0x8];
8123         u8         pfcc_mask[0x1];
8124         u8         reserved_at_77[0x4];
8125         u8         rx_buffer_fullness_counters[0x1];
8126         u8         ptys_connector_type[0x1];
8127         u8         reserved_at_7d[0x1];
8128         u8         ppcnt_discard_group[0x1];
8129         u8         ppcnt_statistical_group[0x1];
8130 };
8131
8132 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8133         u8         port_access_reg_cap_mask_127_to_96[0x20];
8134         u8         port_access_reg_cap_mask_95_to_64[0x20];
8135         u8         port_access_reg_cap_mask_63_to_32[0x20];
8136
8137         u8         port_access_reg_cap_mask_31_to_13[0x13];
8138         u8         pbmc[0x1];
8139         u8         pptb[0x1];
8140         u8         port_access_reg_cap_mask_10_to_0[0xb];
8141 };
8142
8143 struct mlx5_ifc_pcam_reg_bits {
8144         u8         reserved_at_0[0x8];
8145         u8         feature_group[0x8];
8146         u8         reserved_at_10[0x8];
8147         u8         access_reg_group[0x8];
8148
8149         u8         reserved_at_20[0x20];
8150
8151         union {
8152                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8153                 u8         reserved_at_0[0x80];
8154         } port_access_reg_cap_mask;
8155
8156         u8         reserved_at_c0[0x80];
8157
8158         union {
8159                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8160                 u8         reserved_at_0[0x80];
8161         } feature_cap_mask;
8162
8163         u8         reserved_at_1c0[0xc0];
8164 };
8165
8166 struct mlx5_ifc_mcam_enhanced_features_bits {
8167         u8         reserved_at_0[0x74];
8168         u8         mark_tx_action_cnp[0x1];
8169         u8         mark_tx_action_cqe[0x1];
8170         u8         dynamic_tx_overflow[0x1];
8171         u8         reserved_at_77[0x4];
8172         u8         pcie_outbound_stalled[0x1];
8173         u8         tx_overflow_buffer_pkt[0x1];
8174         u8         mtpps_enh_out_per_adj[0x1];
8175         u8         mtpps_fs[0x1];
8176         u8         pcie_performance_group[0x1];
8177 };
8178
8179 struct mlx5_ifc_mcam_access_reg_bits {
8180         u8         reserved_at_0[0x1c];
8181         u8         mcda[0x1];
8182         u8         mcc[0x1];
8183         u8         mcqi[0x1];
8184         u8         reserved_at_1f[0x1];
8185
8186         u8         regs_95_to_87[0x9];
8187         u8         mpegc[0x1];
8188         u8         regs_85_to_68[0x12];
8189         u8         tracer_registers[0x4];
8190
8191         u8         regs_63_to_32[0x20];
8192         u8         regs_31_to_0[0x20];
8193 };
8194
8195 struct mlx5_ifc_mcam_reg_bits {
8196         u8         reserved_at_0[0x8];
8197         u8         feature_group[0x8];
8198         u8         reserved_at_10[0x8];
8199         u8         access_reg_group[0x8];
8200
8201         u8         reserved_at_20[0x20];
8202
8203         union {
8204                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8205                 u8         reserved_at_0[0x80];
8206         } mng_access_reg_cap_mask;
8207
8208         u8         reserved_at_c0[0x80];
8209
8210         union {
8211                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8212                 u8         reserved_at_0[0x80];
8213         } mng_feature_cap_mask;
8214
8215         u8         reserved_at_1c0[0x80];
8216 };
8217
8218 struct mlx5_ifc_qcam_access_reg_cap_mask {
8219         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8220         u8         qpdpm[0x1];
8221         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8222         u8         qdpm[0x1];
8223         u8         qpts[0x1];
8224         u8         qcap[0x1];
8225         u8         qcam_access_reg_cap_mask_0[0x1];
8226 };
8227
8228 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8229         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8230         u8         qpts_trust_both[0x1];
8231 };
8232
8233 struct mlx5_ifc_qcam_reg_bits {
8234         u8         reserved_at_0[0x8];
8235         u8         feature_group[0x8];
8236         u8         reserved_at_10[0x8];
8237         u8         access_reg_group[0x8];
8238         u8         reserved_at_20[0x20];
8239
8240         union {
8241                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8242                 u8  reserved_at_0[0x80];
8243         } qos_access_reg_cap_mask;
8244
8245         u8         reserved_at_c0[0x80];
8246
8247         union {
8248                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8249                 u8  reserved_at_0[0x80];
8250         } qos_feature_cap_mask;
8251
8252         u8         reserved_at_1c0[0x80];
8253 };
8254
8255 struct mlx5_ifc_pcap_reg_bits {
8256         u8         reserved_at_0[0x8];
8257         u8         local_port[0x8];
8258         u8         reserved_at_10[0x10];
8259
8260         u8         port_capability_mask[4][0x20];
8261 };
8262
8263 struct mlx5_ifc_paos_reg_bits {
8264         u8         swid[0x8];
8265         u8         local_port[0x8];
8266         u8         reserved_at_10[0x4];
8267         u8         admin_status[0x4];
8268         u8         reserved_at_18[0x4];
8269         u8         oper_status[0x4];
8270
8271         u8         ase[0x1];
8272         u8         ee[0x1];
8273         u8         reserved_at_22[0x1c];
8274         u8         e[0x2];
8275
8276         u8         reserved_at_40[0x40];
8277 };
8278
8279 struct mlx5_ifc_pamp_reg_bits {
8280         u8         reserved_at_0[0x8];
8281         u8         opamp_group[0x8];
8282         u8         reserved_at_10[0xc];
8283         u8         opamp_group_type[0x4];
8284
8285         u8         start_index[0x10];
8286         u8         reserved_at_30[0x4];
8287         u8         num_of_indices[0xc];
8288
8289         u8         index_data[18][0x10];
8290 };
8291
8292 struct mlx5_ifc_pcmr_reg_bits {
8293         u8         reserved_at_0[0x8];
8294         u8         local_port[0x8];
8295         u8         reserved_at_10[0x2e];
8296         u8         fcs_cap[0x1];
8297         u8         reserved_at_3f[0x1f];
8298         u8         fcs_chk[0x1];
8299         u8         reserved_at_5f[0x1];
8300 };
8301
8302 struct mlx5_ifc_lane_2_module_mapping_bits {
8303         u8         reserved_at_0[0x6];
8304         u8         rx_lane[0x2];
8305         u8         reserved_at_8[0x6];
8306         u8         tx_lane[0x2];
8307         u8         reserved_at_10[0x8];
8308         u8         module[0x8];
8309 };
8310
8311 struct mlx5_ifc_bufferx_reg_bits {
8312         u8         reserved_at_0[0x6];
8313         u8         lossy[0x1];
8314         u8         epsb[0x1];
8315         u8         reserved_at_8[0xc];
8316         u8         size[0xc];
8317
8318         u8         xoff_threshold[0x10];
8319         u8         xon_threshold[0x10];
8320 };
8321
8322 struct mlx5_ifc_set_node_in_bits {
8323         u8         node_description[64][0x8];
8324 };
8325
8326 struct mlx5_ifc_register_power_settings_bits {
8327         u8         reserved_at_0[0x18];
8328         u8         power_settings_level[0x8];
8329
8330         u8         reserved_at_20[0x60];
8331 };
8332
8333 struct mlx5_ifc_register_host_endianness_bits {
8334         u8         he[0x1];
8335         u8         reserved_at_1[0x1f];
8336
8337         u8         reserved_at_20[0x60];
8338 };
8339
8340 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8341         u8         reserved_at_0[0x20];
8342
8343         u8         mkey[0x20];
8344
8345         u8         addressh_63_32[0x20];
8346
8347         u8         addressl_31_0[0x20];
8348 };
8349
8350 struct mlx5_ifc_ud_adrs_vector_bits {
8351         u8         dc_key[0x40];
8352
8353         u8         ext[0x1];
8354         u8         reserved_at_41[0x7];
8355         u8         destination_qp_dct[0x18];
8356
8357         u8         static_rate[0x4];
8358         u8         sl_eth_prio[0x4];
8359         u8         fl[0x1];
8360         u8         mlid[0x7];
8361         u8         rlid_udp_sport[0x10];
8362
8363         u8         reserved_at_80[0x20];
8364
8365         u8         rmac_47_16[0x20];
8366
8367         u8         rmac_15_0[0x10];
8368         u8         tclass[0x8];
8369         u8         hop_limit[0x8];
8370
8371         u8         reserved_at_e0[0x1];
8372         u8         grh[0x1];
8373         u8         reserved_at_e2[0x2];
8374         u8         src_addr_index[0x8];
8375         u8         flow_label[0x14];
8376
8377         u8         rgid_rip[16][0x8];
8378 };
8379
8380 struct mlx5_ifc_pages_req_event_bits {
8381         u8         reserved_at_0[0x10];
8382         u8         function_id[0x10];
8383
8384         u8         num_pages[0x20];
8385
8386         u8         reserved_at_40[0xa0];
8387 };
8388
8389 struct mlx5_ifc_eqe_bits {
8390         u8         reserved_at_0[0x8];
8391         u8         event_type[0x8];
8392         u8         reserved_at_10[0x8];
8393         u8         event_sub_type[0x8];
8394
8395         u8         reserved_at_20[0xe0];
8396
8397         union mlx5_ifc_event_auto_bits event_data;
8398
8399         u8         reserved_at_1e0[0x10];
8400         u8         signature[0x8];
8401         u8         reserved_at_1f8[0x7];
8402         u8         owner[0x1];
8403 };
8404
8405 enum {
8406         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8407 };
8408
8409 struct mlx5_ifc_cmd_queue_entry_bits {
8410         u8         type[0x8];
8411         u8         reserved_at_8[0x18];
8412
8413         u8         input_length[0x20];
8414
8415         u8         input_mailbox_pointer_63_32[0x20];
8416
8417         u8         input_mailbox_pointer_31_9[0x17];
8418         u8         reserved_at_77[0x9];
8419
8420         u8         command_input_inline_data[16][0x8];
8421
8422         u8         command_output_inline_data[16][0x8];
8423
8424         u8         output_mailbox_pointer_63_32[0x20];
8425
8426         u8         output_mailbox_pointer_31_9[0x17];
8427         u8         reserved_at_1b7[0x9];
8428
8429         u8         output_length[0x20];
8430
8431         u8         token[0x8];
8432         u8         signature[0x8];
8433         u8         reserved_at_1f0[0x8];
8434         u8         status[0x7];
8435         u8         ownership[0x1];
8436 };
8437
8438 struct mlx5_ifc_cmd_out_bits {
8439         u8         status[0x8];
8440         u8         reserved_at_8[0x18];
8441
8442         u8         syndrome[0x20];
8443
8444         u8         command_output[0x20];
8445 };
8446
8447 struct mlx5_ifc_cmd_in_bits {
8448         u8         opcode[0x10];
8449         u8         reserved_at_10[0x10];
8450
8451         u8         reserved_at_20[0x10];
8452         u8         op_mod[0x10];
8453
8454         u8         command[0][0x20];
8455 };
8456
8457 struct mlx5_ifc_cmd_if_box_bits {
8458         u8         mailbox_data[512][0x8];
8459
8460         u8         reserved_at_1000[0x180];
8461
8462         u8         next_pointer_63_32[0x20];
8463
8464         u8         next_pointer_31_10[0x16];
8465         u8         reserved_at_11b6[0xa];
8466
8467         u8         block_number[0x20];
8468
8469         u8         reserved_at_11e0[0x8];
8470         u8         token[0x8];
8471         u8         ctrl_signature[0x8];
8472         u8         signature[0x8];
8473 };
8474
8475 struct mlx5_ifc_mtt_bits {
8476         u8         ptag_63_32[0x20];
8477
8478         u8         ptag_31_8[0x18];
8479         u8         reserved_at_38[0x6];
8480         u8         wr_en[0x1];
8481         u8         rd_en[0x1];
8482 };
8483
8484 struct mlx5_ifc_query_wol_rol_out_bits {
8485         u8         status[0x8];
8486         u8         reserved_at_8[0x18];
8487
8488         u8         syndrome[0x20];
8489
8490         u8         reserved_at_40[0x10];
8491         u8         rol_mode[0x8];
8492         u8         wol_mode[0x8];
8493
8494         u8         reserved_at_60[0x20];
8495 };
8496
8497 struct mlx5_ifc_query_wol_rol_in_bits {
8498         u8         opcode[0x10];
8499         u8         reserved_at_10[0x10];
8500
8501         u8         reserved_at_20[0x10];
8502         u8         op_mod[0x10];
8503
8504         u8         reserved_at_40[0x40];
8505 };
8506
8507 struct mlx5_ifc_set_wol_rol_out_bits {
8508         u8         status[0x8];
8509         u8         reserved_at_8[0x18];
8510
8511         u8         syndrome[0x20];
8512
8513         u8         reserved_at_40[0x40];
8514 };
8515
8516 struct mlx5_ifc_set_wol_rol_in_bits {
8517         u8         opcode[0x10];
8518         u8         reserved_at_10[0x10];
8519
8520         u8         reserved_at_20[0x10];
8521         u8         op_mod[0x10];
8522
8523         u8         rol_mode_valid[0x1];
8524         u8         wol_mode_valid[0x1];
8525         u8         reserved_at_42[0xe];
8526         u8         rol_mode[0x8];
8527         u8         wol_mode[0x8];
8528
8529         u8         reserved_at_60[0x20];
8530 };
8531
8532 enum {
8533         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8534         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8535         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8536 };
8537
8538 enum {
8539         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8540         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8541         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8542 };
8543
8544 enum {
8545         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8546         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8547         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8548         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8549         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8550         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8551         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8552         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8553         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8554         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8555         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8556 };
8557
8558 struct mlx5_ifc_initial_seg_bits {
8559         u8         fw_rev_minor[0x10];
8560         u8         fw_rev_major[0x10];
8561
8562         u8         cmd_interface_rev[0x10];
8563         u8         fw_rev_subminor[0x10];
8564
8565         u8         reserved_at_40[0x40];
8566
8567         u8         cmdq_phy_addr_63_32[0x20];
8568
8569         u8         cmdq_phy_addr_31_12[0x14];
8570         u8         reserved_at_b4[0x2];
8571         u8         nic_interface[0x2];
8572         u8         log_cmdq_size[0x4];
8573         u8         log_cmdq_stride[0x4];
8574
8575         u8         command_doorbell_vector[0x20];
8576
8577         u8         reserved_at_e0[0xf00];
8578
8579         u8         initializing[0x1];
8580         u8         reserved_at_fe1[0x4];
8581         u8         nic_interface_supported[0x3];
8582         u8         reserved_at_fe8[0x18];
8583
8584         struct mlx5_ifc_health_buffer_bits health_buffer;
8585
8586         u8         no_dram_nic_offset[0x20];
8587
8588         u8         reserved_at_1220[0x6e40];
8589
8590         u8         reserved_at_8060[0x1f];
8591         u8         clear_int[0x1];
8592
8593         u8         health_syndrome[0x8];
8594         u8         health_counter[0x18];
8595
8596         u8         reserved_at_80a0[0x17fc0];
8597 };
8598
8599 struct mlx5_ifc_mtpps_reg_bits {
8600         u8         reserved_at_0[0xc];
8601         u8         cap_number_of_pps_pins[0x4];
8602         u8         reserved_at_10[0x4];
8603         u8         cap_max_num_of_pps_in_pins[0x4];
8604         u8         reserved_at_18[0x4];
8605         u8         cap_max_num_of_pps_out_pins[0x4];
8606
8607         u8         reserved_at_20[0x24];
8608         u8         cap_pin_3_mode[0x4];
8609         u8         reserved_at_48[0x4];
8610         u8         cap_pin_2_mode[0x4];
8611         u8         reserved_at_50[0x4];
8612         u8         cap_pin_1_mode[0x4];
8613         u8         reserved_at_58[0x4];
8614         u8         cap_pin_0_mode[0x4];
8615
8616         u8         reserved_at_60[0x4];
8617         u8         cap_pin_7_mode[0x4];
8618         u8         reserved_at_68[0x4];
8619         u8         cap_pin_6_mode[0x4];
8620         u8         reserved_at_70[0x4];
8621         u8         cap_pin_5_mode[0x4];
8622         u8         reserved_at_78[0x4];
8623         u8         cap_pin_4_mode[0x4];
8624
8625         u8         field_select[0x20];
8626         u8         reserved_at_a0[0x60];
8627
8628         u8         enable[0x1];
8629         u8         reserved_at_101[0xb];
8630         u8         pattern[0x4];
8631         u8         reserved_at_110[0x4];
8632         u8         pin_mode[0x4];
8633         u8         pin[0x8];
8634
8635         u8         reserved_at_120[0x20];
8636
8637         u8         time_stamp[0x40];
8638
8639         u8         out_pulse_duration[0x10];
8640         u8         out_periodic_adjustment[0x10];
8641         u8         enhanced_out_periodic_adjustment[0x20];
8642
8643         u8         reserved_at_1c0[0x20];
8644 };
8645
8646 struct mlx5_ifc_mtppse_reg_bits {
8647         u8         reserved_at_0[0x18];
8648         u8         pin[0x8];
8649         u8         event_arm[0x1];
8650         u8         reserved_at_21[0x1b];
8651         u8         event_generation_mode[0x4];
8652         u8         reserved_at_40[0x40];
8653 };
8654
8655 struct mlx5_ifc_mcqi_cap_bits {
8656         u8         supported_info_bitmask[0x20];
8657
8658         u8         component_size[0x20];
8659
8660         u8         max_component_size[0x20];
8661
8662         u8         log_mcda_word_size[0x4];
8663         u8         reserved_at_64[0xc];
8664         u8         mcda_max_write_size[0x10];
8665
8666         u8         rd_en[0x1];
8667         u8         reserved_at_81[0x1];
8668         u8         match_chip_id[0x1];
8669         u8         match_psid[0x1];
8670         u8         check_user_timestamp[0x1];
8671         u8         match_base_guid_mac[0x1];
8672         u8         reserved_at_86[0x1a];
8673 };
8674
8675 struct mlx5_ifc_mcqi_reg_bits {
8676         u8         read_pending_component[0x1];
8677         u8         reserved_at_1[0xf];
8678         u8         component_index[0x10];
8679
8680         u8         reserved_at_20[0x20];
8681
8682         u8         reserved_at_40[0x1b];
8683         u8         info_type[0x5];
8684
8685         u8         info_size[0x20];
8686
8687         u8         offset[0x20];
8688
8689         u8         reserved_at_a0[0x10];
8690         u8         data_size[0x10];
8691
8692         u8         data[0][0x20];
8693 };
8694
8695 struct mlx5_ifc_mcc_reg_bits {
8696         u8         reserved_at_0[0x4];
8697         u8         time_elapsed_since_last_cmd[0xc];
8698         u8         reserved_at_10[0x8];
8699         u8         instruction[0x8];
8700
8701         u8         reserved_at_20[0x10];
8702         u8         component_index[0x10];
8703
8704         u8         reserved_at_40[0x8];
8705         u8         update_handle[0x18];
8706
8707         u8         handle_owner_type[0x4];
8708         u8         handle_owner_host_id[0x4];
8709         u8         reserved_at_68[0x1];
8710         u8         control_progress[0x7];
8711         u8         error_code[0x8];
8712         u8         reserved_at_78[0x4];
8713         u8         control_state[0x4];
8714
8715         u8         component_size[0x20];
8716
8717         u8         reserved_at_a0[0x60];
8718 };
8719
8720 struct mlx5_ifc_mcda_reg_bits {
8721         u8         reserved_at_0[0x8];
8722         u8         update_handle[0x18];
8723
8724         u8         offset[0x20];
8725
8726         u8         reserved_at_40[0x10];
8727         u8         size[0x10];
8728
8729         u8         reserved_at_60[0x20];
8730
8731         u8         data[0][0x20];
8732 };
8733
8734 union mlx5_ifc_ports_control_registers_document_bits {
8735         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8736         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8737         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8738         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8739         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8740         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8741         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8742         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8743         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8744         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8745         struct mlx5_ifc_paos_reg_bits paos_reg;
8746         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8747         struct mlx5_ifc_peir_reg_bits peir_reg;
8748         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8749         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8750         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8751         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8752         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8753         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8754         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8755         struct mlx5_ifc_plib_reg_bits plib_reg;
8756         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8757         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8758         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8759         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8760         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8761         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8762         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8763         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8764         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8765         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8766         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8767         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8768         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8769         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8770         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8771         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8772         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8773         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8774         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8775         struct mlx5_ifc_pude_reg_bits pude_reg;
8776         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8777         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8778         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8779         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8780         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8781         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8782         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8783         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8784         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8785         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8786         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8787         u8         reserved_at_0[0x60e0];
8788 };
8789
8790 union mlx5_ifc_debug_enhancements_document_bits {
8791         struct mlx5_ifc_health_buffer_bits health_buffer;
8792         u8         reserved_at_0[0x200];
8793 };
8794
8795 union mlx5_ifc_uplink_pci_interface_document_bits {
8796         struct mlx5_ifc_initial_seg_bits initial_seg;
8797         u8         reserved_at_0[0x20060];
8798 };
8799
8800 struct mlx5_ifc_set_flow_table_root_out_bits {
8801         u8         status[0x8];
8802         u8         reserved_at_8[0x18];
8803
8804         u8         syndrome[0x20];
8805
8806         u8         reserved_at_40[0x40];
8807 };
8808
8809 struct mlx5_ifc_set_flow_table_root_in_bits {
8810         u8         opcode[0x10];
8811         u8         reserved_at_10[0x10];
8812
8813         u8         reserved_at_20[0x10];
8814         u8         op_mod[0x10];
8815
8816         u8         other_vport[0x1];
8817         u8         reserved_at_41[0xf];
8818         u8         vport_number[0x10];
8819
8820         u8         reserved_at_60[0x20];
8821
8822         u8         table_type[0x8];
8823         u8         reserved_at_88[0x18];
8824
8825         u8         reserved_at_a0[0x8];
8826         u8         table_id[0x18];
8827
8828         u8         reserved_at_c0[0x8];
8829         u8         underlay_qpn[0x18];
8830         u8         reserved_at_e0[0x120];
8831 };
8832
8833 enum {
8834         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8835         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8836 };
8837
8838 struct mlx5_ifc_modify_flow_table_out_bits {
8839         u8         status[0x8];
8840         u8         reserved_at_8[0x18];
8841
8842         u8         syndrome[0x20];
8843
8844         u8         reserved_at_40[0x40];
8845 };
8846
8847 struct mlx5_ifc_modify_flow_table_in_bits {
8848         u8         opcode[0x10];
8849         u8         reserved_at_10[0x10];
8850
8851         u8         reserved_at_20[0x10];
8852         u8         op_mod[0x10];
8853
8854         u8         other_vport[0x1];
8855         u8         reserved_at_41[0xf];
8856         u8         vport_number[0x10];
8857
8858         u8         reserved_at_60[0x10];
8859         u8         modify_field_select[0x10];
8860
8861         u8         table_type[0x8];
8862         u8         reserved_at_88[0x18];
8863
8864         u8         reserved_at_a0[0x8];
8865         u8         table_id[0x18];
8866
8867         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8868 };
8869
8870 struct mlx5_ifc_ets_tcn_config_reg_bits {
8871         u8         g[0x1];
8872         u8         b[0x1];
8873         u8         r[0x1];
8874         u8         reserved_at_3[0x9];
8875         u8         group[0x4];
8876         u8         reserved_at_10[0x9];
8877         u8         bw_allocation[0x7];
8878
8879         u8         reserved_at_20[0xc];
8880         u8         max_bw_units[0x4];
8881         u8         reserved_at_30[0x8];
8882         u8         max_bw_value[0x8];
8883 };
8884
8885 struct mlx5_ifc_ets_global_config_reg_bits {
8886         u8         reserved_at_0[0x2];
8887         u8         r[0x1];
8888         u8         reserved_at_3[0x1d];
8889
8890         u8         reserved_at_20[0xc];
8891         u8         max_bw_units[0x4];
8892         u8         reserved_at_30[0x8];
8893         u8         max_bw_value[0x8];
8894 };
8895
8896 struct mlx5_ifc_qetc_reg_bits {
8897         u8                                         reserved_at_0[0x8];
8898         u8                                         port_number[0x8];
8899         u8                                         reserved_at_10[0x30];
8900
8901         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8902         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8903 };
8904
8905 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8906         u8         e[0x1];
8907         u8         reserved_at_01[0x0b];
8908         u8         prio[0x04];
8909 };
8910
8911 struct mlx5_ifc_qpdpm_reg_bits {
8912         u8                                     reserved_at_0[0x8];
8913         u8                                     local_port[0x8];
8914         u8                                     reserved_at_10[0x10];
8915         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8916 };
8917
8918 struct mlx5_ifc_qpts_reg_bits {
8919         u8         reserved_at_0[0x8];
8920         u8         local_port[0x8];
8921         u8         reserved_at_10[0x2d];
8922         u8         trust_state[0x3];
8923 };
8924
8925 struct mlx5_ifc_pptb_reg_bits {
8926         u8         reserved_at_0[0x2];
8927         u8         mm[0x2];
8928         u8         reserved_at_4[0x4];
8929         u8         local_port[0x8];
8930         u8         reserved_at_10[0x6];
8931         u8         cm[0x1];
8932         u8         um[0x1];
8933         u8         pm[0x8];
8934
8935         u8         prio_x_buff[0x20];
8936
8937         u8         pm_msb[0x8];
8938         u8         reserved_at_48[0x10];
8939         u8         ctrl_buff[0x4];
8940         u8         untagged_buff[0x4];
8941 };
8942
8943 struct mlx5_ifc_pbmc_reg_bits {
8944         u8         reserved_at_0[0x8];
8945         u8         local_port[0x8];
8946         u8         reserved_at_10[0x10];
8947
8948         u8         xoff_timer_value[0x10];
8949         u8         xoff_refresh[0x10];
8950
8951         u8         reserved_at_40[0x9];
8952         u8         fullness_threshold[0x7];
8953         u8         port_buffer_size[0x10];
8954
8955         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8956
8957         u8         reserved_at_2e0[0x40];
8958 };
8959
8960 struct mlx5_ifc_qtct_reg_bits {
8961         u8         reserved_at_0[0x8];
8962         u8         port_number[0x8];
8963         u8         reserved_at_10[0xd];
8964         u8         prio[0x3];
8965
8966         u8         reserved_at_20[0x1d];
8967         u8         tclass[0x3];
8968 };
8969
8970 struct mlx5_ifc_mcia_reg_bits {
8971         u8         l[0x1];
8972         u8         reserved_at_1[0x7];
8973         u8         module[0x8];
8974         u8         reserved_at_10[0x8];
8975         u8         status[0x8];
8976
8977         u8         i2c_device_address[0x8];
8978         u8         page_number[0x8];
8979         u8         device_address[0x10];
8980
8981         u8         reserved_at_40[0x10];
8982         u8         size[0x10];
8983
8984         u8         reserved_at_60[0x20];
8985
8986         u8         dword_0[0x20];
8987         u8         dword_1[0x20];
8988         u8         dword_2[0x20];
8989         u8         dword_3[0x20];
8990         u8         dword_4[0x20];
8991         u8         dword_5[0x20];
8992         u8         dword_6[0x20];
8993         u8         dword_7[0x20];
8994         u8         dword_8[0x20];
8995         u8         dword_9[0x20];
8996         u8         dword_10[0x20];
8997         u8         dword_11[0x20];
8998 };
8999
9000 struct mlx5_ifc_dcbx_param_bits {
9001         u8         dcbx_cee_cap[0x1];
9002         u8         dcbx_ieee_cap[0x1];
9003         u8         dcbx_standby_cap[0x1];
9004         u8         reserved_at_0[0x5];
9005         u8         port_number[0x8];
9006         u8         reserved_at_10[0xa];
9007         u8         max_application_table_size[6];
9008         u8         reserved_at_20[0x15];
9009         u8         version_oper[0x3];
9010         u8         reserved_at_38[5];
9011         u8         version_admin[0x3];
9012         u8         willing_admin[0x1];
9013         u8         reserved_at_41[0x3];
9014         u8         pfc_cap_oper[0x4];
9015         u8         reserved_at_48[0x4];
9016         u8         pfc_cap_admin[0x4];
9017         u8         reserved_at_50[0x4];
9018         u8         num_of_tc_oper[0x4];
9019         u8         reserved_at_58[0x4];
9020         u8         num_of_tc_admin[0x4];
9021         u8         remote_willing[0x1];
9022         u8         reserved_at_61[3];
9023         u8         remote_pfc_cap[4];
9024         u8         reserved_at_68[0x14];
9025         u8         remote_num_of_tc[0x4];
9026         u8         reserved_at_80[0x18];
9027         u8         error[0x8];
9028         u8         reserved_at_a0[0x160];
9029 };
9030
9031 struct mlx5_ifc_lagc_bits {
9032         u8         reserved_at_0[0x1d];
9033         u8         lag_state[0x3];
9034
9035         u8         reserved_at_20[0x14];
9036         u8         tx_remap_affinity_2[0x4];
9037         u8         reserved_at_38[0x4];
9038         u8         tx_remap_affinity_1[0x4];
9039 };
9040
9041 struct mlx5_ifc_create_lag_out_bits {
9042         u8         status[0x8];
9043         u8         reserved_at_8[0x18];
9044
9045         u8         syndrome[0x20];
9046
9047         u8         reserved_at_40[0x40];
9048 };
9049
9050 struct mlx5_ifc_create_lag_in_bits {
9051         u8         opcode[0x10];
9052         u8         reserved_at_10[0x10];
9053
9054         u8         reserved_at_20[0x10];
9055         u8         op_mod[0x10];
9056
9057         struct mlx5_ifc_lagc_bits ctx;
9058 };
9059
9060 struct mlx5_ifc_modify_lag_out_bits {
9061         u8         status[0x8];
9062         u8         reserved_at_8[0x18];
9063
9064         u8         syndrome[0x20];
9065
9066         u8         reserved_at_40[0x40];
9067 };
9068
9069 struct mlx5_ifc_modify_lag_in_bits {
9070         u8         opcode[0x10];
9071         u8         reserved_at_10[0x10];
9072
9073         u8         reserved_at_20[0x10];
9074         u8         op_mod[0x10];
9075
9076         u8         reserved_at_40[0x20];
9077         u8         field_select[0x20];
9078
9079         struct mlx5_ifc_lagc_bits ctx;
9080 };
9081
9082 struct mlx5_ifc_query_lag_out_bits {
9083         u8         status[0x8];
9084         u8         reserved_at_8[0x18];
9085
9086         u8         syndrome[0x20];
9087
9088         u8         reserved_at_40[0x40];
9089
9090         struct mlx5_ifc_lagc_bits ctx;
9091 };
9092
9093 struct mlx5_ifc_query_lag_in_bits {
9094         u8         opcode[0x10];
9095         u8         reserved_at_10[0x10];
9096
9097         u8         reserved_at_20[0x10];
9098         u8         op_mod[0x10];
9099
9100         u8         reserved_at_40[0x40];
9101 };
9102
9103 struct mlx5_ifc_destroy_lag_out_bits {
9104         u8         status[0x8];
9105         u8         reserved_at_8[0x18];
9106
9107         u8         syndrome[0x20];
9108
9109         u8         reserved_at_40[0x40];
9110 };
9111
9112 struct mlx5_ifc_destroy_lag_in_bits {
9113         u8         opcode[0x10];
9114         u8         reserved_at_10[0x10];
9115
9116         u8         reserved_at_20[0x10];
9117         u8         op_mod[0x10];
9118
9119         u8         reserved_at_40[0x40];
9120 };
9121
9122 struct mlx5_ifc_create_vport_lag_out_bits {
9123         u8         status[0x8];
9124         u8         reserved_at_8[0x18];
9125
9126         u8         syndrome[0x20];
9127
9128         u8         reserved_at_40[0x40];
9129 };
9130
9131 struct mlx5_ifc_create_vport_lag_in_bits {
9132         u8         opcode[0x10];
9133         u8         reserved_at_10[0x10];
9134
9135         u8         reserved_at_20[0x10];
9136         u8         op_mod[0x10];
9137
9138         u8         reserved_at_40[0x40];
9139 };
9140
9141 struct mlx5_ifc_destroy_vport_lag_out_bits {
9142         u8         status[0x8];
9143         u8         reserved_at_8[0x18];
9144
9145         u8         syndrome[0x20];
9146
9147         u8         reserved_at_40[0x40];
9148 };
9149
9150 struct mlx5_ifc_destroy_vport_lag_in_bits {
9151         u8         opcode[0x10];
9152         u8         reserved_at_10[0x10];
9153
9154         u8         reserved_at_20[0x10];
9155         u8         op_mod[0x10];
9156
9157         u8         reserved_at_40[0x40];
9158 };
9159
9160 struct mlx5_ifc_alloc_memic_in_bits {
9161         u8         opcode[0x10];
9162         u8         reserved_at_10[0x10];
9163
9164         u8         reserved_at_20[0x10];
9165         u8         op_mod[0x10];
9166
9167         u8         reserved_at_30[0x20];
9168
9169         u8         reserved_at_40[0x18];
9170         u8         log_memic_addr_alignment[0x8];
9171
9172         u8         range_start_addr[0x40];
9173
9174         u8         range_size[0x20];
9175
9176         u8         memic_size[0x20];
9177 };
9178
9179 struct mlx5_ifc_alloc_memic_out_bits {
9180         u8         status[0x8];
9181         u8         reserved_at_8[0x18];
9182
9183         u8         syndrome[0x20];
9184
9185         u8         memic_start_addr[0x40];
9186 };
9187
9188 struct mlx5_ifc_dealloc_memic_in_bits {
9189         u8         opcode[0x10];
9190         u8         reserved_at_10[0x10];
9191
9192         u8         reserved_at_20[0x10];
9193         u8         op_mod[0x10];
9194
9195         u8         reserved_at_40[0x40];
9196
9197         u8         memic_start_addr[0x40];
9198
9199         u8         memic_size[0x20];
9200
9201         u8         reserved_at_e0[0x20];
9202 };
9203
9204 struct mlx5_ifc_dealloc_memic_out_bits {
9205         u8         status[0x8];
9206         u8         reserved_at_8[0x18];
9207
9208         u8         syndrome[0x20];
9209
9210         u8         reserved_at_40[0x40];
9211 };
9212
9213 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9214         u8         opcode[0x10];
9215         u8         uid[0x10];
9216
9217         u8         reserved_at_20[0x10];
9218         u8         obj_type[0x10];
9219
9220         u8         obj_id[0x20];
9221
9222         u8         reserved_at_60[0x20];
9223 };
9224
9225 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9226         u8         status[0x8];
9227         u8         reserved_at_8[0x18];
9228
9229         u8         syndrome[0x20];
9230
9231         u8         obj_id[0x20];
9232
9233         u8         reserved_at_60[0x20];
9234 };
9235
9236 struct mlx5_ifc_umem_bits {
9237         u8         modify_field_select[0x40];
9238
9239         u8         reserved_at_40[0x5b];
9240         u8         log_page_size[0x5];
9241
9242         u8         page_offset[0x20];
9243
9244         u8         num_of_mtt[0x40];
9245
9246         struct mlx5_ifc_mtt_bits  mtt[0];
9247 };
9248
9249 struct mlx5_ifc_uctx_bits {
9250         u8         modify_field_select[0x40];
9251
9252         u8         reserved_at_40[0x1c0];
9253 };
9254
9255 struct mlx5_ifc_create_umem_in_bits {
9256         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9257         struct mlx5_ifc_umem_bits                     umem;
9258 };
9259
9260 struct mlx5_ifc_create_uctx_in_bits {
9261         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9262         struct mlx5_ifc_uctx_bits                     uctx;
9263 };
9264
9265 struct mlx5_ifc_mtrc_string_db_param_bits {
9266         u8         string_db_base_address[0x20];
9267
9268         u8         reserved_at_20[0x8];
9269         u8         string_db_size[0x18];
9270 };
9271
9272 struct mlx5_ifc_mtrc_cap_bits {
9273         u8         trace_owner[0x1];
9274         u8         trace_to_memory[0x1];
9275         u8         reserved_at_2[0x4];
9276         u8         trc_ver[0x2];
9277         u8         reserved_at_8[0x14];
9278         u8         num_string_db[0x4];
9279
9280         u8         first_string_trace[0x8];
9281         u8         num_string_trace[0x8];
9282         u8         reserved_at_30[0x28];
9283
9284         u8         log_max_trace_buffer_size[0x8];
9285
9286         u8         reserved_at_60[0x20];
9287
9288         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9289
9290         u8         reserved_at_280[0x180];
9291 };
9292
9293 struct mlx5_ifc_mtrc_conf_bits {
9294         u8         reserved_at_0[0x1c];
9295         u8         trace_mode[0x4];
9296         u8         reserved_at_20[0x18];
9297         u8         log_trace_buffer_size[0x8];
9298         u8         trace_mkey[0x20];
9299         u8         reserved_at_60[0x3a0];
9300 };
9301
9302 struct mlx5_ifc_mtrc_stdb_bits {
9303         u8         string_db_index[0x4];
9304         u8         reserved_at_4[0x4];
9305         u8         read_size[0x18];
9306         u8         start_offset[0x20];
9307         u8         string_db_data[0];
9308 };
9309
9310 struct mlx5_ifc_mtrc_ctrl_bits {
9311         u8         trace_status[0x2];
9312         u8         reserved_at_2[0x2];
9313         u8         arm_event[0x1];
9314         u8         reserved_at_5[0xb];
9315         u8         modify_field_select[0x10];
9316         u8         reserved_at_20[0x2b];
9317         u8         current_timestamp52_32[0x15];
9318         u8         current_timestamp31_0[0x20];
9319         u8         reserved_at_80[0x180];
9320 };
9321
9322 #endif /* MLX5_IFC_H */