1 #ifndef __LINUX_GPIO_DRIVER_H
2 #define __LINUX_GPIO_DRIVER_H
4 #include <linux/device.h>
5 #include <linux/types.h>
7 #include <linux/irqchip/chained_irq.h>
8 #include <linux/irqdomain.h>
9 #include <linux/lockdep.h>
10 #include <linux/pinctrl/pinctrl.h>
11 #include <linux/pinctrl/pinconf-generic.h>
14 struct of_phandle_args;
23 * struct gpio_chip - abstract a GPIO controller
24 * @label: a functional name for the GPIO device, such as a part
25 * number or the name of the SoC IP-block implementing it.
26 * @gpiodev: the internal state holder, opaque struct
27 * @parent: optional parent device providing the GPIOs
28 * @owner: helps prevent removal of modules exporting active GPIOs
29 * @request: optional hook for chip-specific activation, such as
30 * enabling module power and clock; may sleep
31 * @free: optional hook for chip-specific deactivation, such as
32 * disabling module power and clock; may sleep
33 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
34 * (same as GPIOF_DIR_XXX), or negative error
35 * @direction_input: configures signal "offset" as input, or returns error
36 * @direction_output: configures signal "offset" as output, or returns error
37 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
38 * @get_multiple: reads values for multiple signals defined by "mask" and
39 * stores them in "bits", returns 0 on success or negative error
40 * @set: assigns output value for signal "offset"
41 * @set_multiple: assigns output values for multiple signals defined by "mask"
42 * @set_config: optional hook for all kinds of settings. Uses the same
43 * packed config format as generic pinconf.
44 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
45 * implementation may not sleep
46 * @dbg_show: optional routine to show contents in debugfs; default code
47 * will be used when this is omitted, but custom code can show extra
48 * state (such as pullup/pulldown configuration).
49 * @base: identifies the first GPIO number handled by this chip;
50 * or, if negative during registration, requests dynamic ID allocation.
51 * DEPRECATION: providing anything non-negative and nailing the base
52 * offset of GPIO chips is deprecated. Please pass -1 as base to
53 * let gpiolib select the chip base in all possible cases. We want to
54 * get rid of the static GPIO number space in the long run.
55 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
56 * handled is (base + ngpio - 1).
57 * @names: if set, must be an array of strings to use as alternative
58 * names for the GPIOs in this chip. Any entry in the array
59 * may be NULL if there is no alias for the GPIO, however the
60 * array must be @ngpio entries long. A name can include a single printk
61 * format specifier for an unsigned int. It is substituted by the actual
63 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
64 * must while accessing GPIO expander chips over I2C or SPI. This
65 * implies that if the chip supports IRQs, these IRQs need to be threaded
66 * as the chip access may sleep when e.g. reading out the IRQ status
68 * @read_reg: reader function for generic GPIO
69 * @write_reg: writer function for generic GPIO
70 * @pin2mask: some generic GPIO controllers work with the big-endian bits
71 * notation, e.g. in a 8-bits register, GPIO7 is the least significant
72 * bit. This callback assigns the right bit mask.
73 * @reg_dat: data (in) register for generic GPIO
74 * @reg_set: output set register (out=high) for generic GPIO
75 * @reg_clr: output clear register (out=low) for generic GPIO
76 * @reg_dir: direction setting register for generic GPIO
77 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
78 * <register width> * 8
79 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
80 * shadowed and real data registers writes together.
81 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
83 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
85 * @irqchip: GPIO IRQ chip impl, provided by GPIO driver
86 * @irqdomain: Interrupt translation domain; responsible for mapping
87 * between GPIO hwirq number and linux irq number
88 * @irq_handler: the irq handler to use (often a predefined irq core function)
89 * for GPIO IRQs, provided by GPIO driver
90 * @irq_default_type: default IRQ triggering type applied during GPIO driver
91 * initialization, provided by GPIO driver
92 * @irq_chained_parent: GPIO IRQ chip parent/bank linux irq number,
93 * provided by GPIO driver for chained interrupt (not for nested
95 * @irq_nested: True if set the interrupt handling is nested.
96 * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all
98 * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to
99 * be included in IRQ domain of the chip
100 * @lock_key: per GPIO IRQ chip lockdep class
102 * A gpio_chip can help platforms abstract various sources of GPIOs so
103 * they can all be accessed through a common programing interface.
104 * Example sources would be SOC controllers, FPGAs, multifunction
105 * chips, dedicated GPIO expanders, and so on.
107 * Each chip controls a number of signals, identified in method calls
108 * by "offset" values in the range 0..(@ngpio - 1). When those signals
109 * are referenced through calls like gpio_get_value(gpio), the offset
110 * is calculated by subtracting @base from the gpio number.
114 struct gpio_device *gpiodev;
115 struct device *parent;
116 struct module *owner;
118 int (*request)(struct gpio_chip *chip,
120 void (*free)(struct gpio_chip *chip,
122 int (*get_direction)(struct gpio_chip *chip,
124 int (*direction_input)(struct gpio_chip *chip,
126 int (*direction_output)(struct gpio_chip *chip,
127 unsigned offset, int value);
128 int (*get)(struct gpio_chip *chip,
130 int (*get_multiple)(struct gpio_chip *chip,
132 unsigned long *bits);
133 void (*set)(struct gpio_chip *chip,
134 unsigned offset, int value);
135 void (*set_multiple)(struct gpio_chip *chip,
137 unsigned long *bits);
138 int (*set_config)(struct gpio_chip *chip,
140 unsigned long config);
141 int (*to_irq)(struct gpio_chip *chip,
144 void (*dbg_show)(struct seq_file *s,
145 struct gpio_chip *chip);
148 const char *const *names;
151 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
152 unsigned long (*read_reg)(void __iomem *reg);
153 void (*write_reg)(void __iomem *reg, unsigned long data);
154 unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
155 void __iomem *reg_dat;
156 void __iomem *reg_set;
157 void __iomem *reg_clr;
158 void __iomem *reg_dir;
160 spinlock_t bgpio_lock;
161 unsigned long bgpio_data;
162 unsigned long bgpio_dir;
165 #ifdef CONFIG_GPIOLIB_IRQCHIP
167 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
168 * to handle IRQs for most practical cases.
170 struct irq_chip *irqchip;
171 struct irq_domain *irqdomain;
172 irq_flow_handler_t irq_handler;
173 unsigned int irq_default_type;
174 unsigned int irq_chained_parent;
176 bool irq_need_valid_mask;
177 unsigned long *irq_valid_mask;
178 struct lock_class_key *lock_key;
181 #if defined(CONFIG_OF_GPIO)
183 * If CONFIG_OF is enabled, then all GPIO controllers described in the
184 * device tree automatically may have an OF translation
190 * Pointer to a device tree node representing this GPIO controller.
192 struct device_node *of_node;
197 * Number of cells used to form the GPIO specifier.
199 unsigned int of_gpio_n_cells;
204 * Callback to translate a device tree GPIO specifier into a chip-
205 * relative GPIO number and flags.
207 int (*of_xlate)(struct gpio_chip *gc,
208 const struct of_phandle_args *gpiospec, u32 *flags);
212 extern const char *gpiochip_is_requested(struct gpio_chip *chip,
215 /* add/remove chips */
216 extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
217 static inline int gpiochip_add(struct gpio_chip *chip)
219 return gpiochip_add_data(chip, NULL);
221 extern void gpiochip_remove(struct gpio_chip *chip);
222 extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
224 extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);
226 extern struct gpio_chip *gpiochip_find(void *data,
227 int (*match)(struct gpio_chip *chip, void *data));
229 /* lock/unlock as IRQ */
230 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
231 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
232 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
234 /* Line status inquiry for drivers */
235 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
236 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
238 /* Sleep persistence inquiry for drivers */
239 bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);
241 /* get driver data */
242 void *gpiochip_get_data(struct gpio_chip *chip);
244 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
252 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
254 int bgpio_init(struct gpio_chip *gc, struct device *dev,
255 unsigned long sz, void __iomem *dat, void __iomem *set,
256 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
257 unsigned long flags);
259 #define BGPIOF_BIG_ENDIAN BIT(0)
260 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
261 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
262 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
263 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
264 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
268 #ifdef CONFIG_GPIOLIB_IRQCHIP
270 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
271 struct irq_chip *irqchip,
272 unsigned int parent_irq,
273 irq_flow_handler_t parent_handler);
275 void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
276 struct irq_chip *irqchip,
277 unsigned int parent_irq);
279 int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
280 struct irq_chip *irqchip,
281 unsigned int first_irq,
282 irq_flow_handler_t handler,
285 struct lock_class_key *lock_key);
287 #ifdef CONFIG_LOCKDEP
290 * Lockdep requires that each irqchip instance be created with a
291 * unique key so as to avoid unnecessary warnings. This upfront
292 * boilerplate static inlines provides such a key for each
295 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
296 struct irq_chip *irqchip,
297 unsigned int first_irq,
298 irq_flow_handler_t handler,
301 static struct lock_class_key key;
303 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
304 handler, type, false, &key);
307 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
308 struct irq_chip *irqchip,
309 unsigned int first_irq,
310 irq_flow_handler_t handler,
314 static struct lock_class_key key;
316 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
317 handler, type, true, &key);
320 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
321 struct irq_chip *irqchip,
322 unsigned int first_irq,
323 irq_flow_handler_t handler,
326 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
327 handler, type, false, NULL);
330 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
331 struct irq_chip *irqchip,
332 unsigned int first_irq,
333 irq_flow_handler_t handler,
336 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
337 handler, type, true, NULL);
339 #endif /* CONFIG_LOCKDEP */
341 #endif /* CONFIG_GPIOLIB_IRQCHIP */
343 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
344 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
345 int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
346 unsigned long config);
348 #ifdef CONFIG_PINCTRL
351 * struct gpio_pin_range - pin range controlled by a gpio chip
352 * @node: list for maintaining set of pin ranges, used internally
353 * @pctldev: pinctrl device which handles corresponding pins
354 * @range: actual range of pins controlled by a gpio controller
356 struct gpio_pin_range {
357 struct list_head node;
358 struct pinctrl_dev *pctldev;
359 struct pinctrl_gpio_range range;
362 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
363 unsigned int gpio_offset, unsigned int pin_offset,
365 int gpiochip_add_pingroup_range(struct gpio_chip *chip,
366 struct pinctrl_dev *pctldev,
367 unsigned int gpio_offset, const char *pin_group);
368 void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
373 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
374 unsigned int gpio_offset, unsigned int pin_offset,
380 gpiochip_add_pingroup_range(struct gpio_chip *chip,
381 struct pinctrl_dev *pctldev,
382 unsigned int gpio_offset, const char *pin_group)
388 gpiochip_remove_pin_ranges(struct gpio_chip *chip)
392 #endif /* CONFIG_PINCTRL */
394 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
396 void gpiochip_free_own_desc(struct gpio_desc *desc);
398 #else /* CONFIG_GPIOLIB */
400 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
402 /* GPIO can never have been requested */
404 return ERR_PTR(-ENODEV);
407 #endif /* CONFIG_GPIOLIB */