1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2019 Xilinx
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
13 #ifndef __FIRMWARE_ZYNQMP_H__
14 #define __FIRMWARE_ZYNQMP_H__
16 #define ZYNQMP_PM_VERSION_MAJOR 1
17 #define ZYNQMP_PM_VERSION_MINOR 0
19 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
20 ZYNQMP_PM_VERSION_MINOR)
22 #define ZYNQMP_TZ_VERSION_MAJOR 1
23 #define ZYNQMP_TZ_VERSION_MINOR 0
25 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
26 ZYNQMP_TZ_VERSION_MINOR)
28 /* SMC SIP service Call Function Identifier Prefix */
29 #define PM_SIP_SVC 0xC2000000
30 #define PM_GET_TRUSTZONE_VERSION 0xa03
31 #define PM_SET_SUSPEND_MODE 0xa02
32 #define GET_CALLBACK_DATA 0xa01
34 /* Number of 32bits values in payload */
35 #define PAYLOAD_ARG_CNT 4U
37 /* Number of arguments for a callback */
40 /* Payload size (consists of callback API ID + arguments) */
41 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
43 #define ZYNQMP_PM_MAX_QOS 100U
45 /* Node capabilities */
46 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
47 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
48 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
49 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
52 * Firmware FPGA Manager flags
53 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
54 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
56 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
57 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
60 PM_GET_API_VERSION = 1,
66 PM_PM_INIT_FINALIZE = 21,
83 /* PMU-FW return status codes */
86 XST_PM_INTERNAL = 2000,
92 XST_PM_MULT_USER = 2008,
96 IOCTL_SET_SD_TAPDELAY = 7,
97 IOCTL_SET_PLL_FRAC_MODE,
98 IOCTL_GET_PLL_FRAC_MODE,
99 IOCTL_SET_PLL_FRAC_DATA,
100 IOCTL_GET_PLL_FRAC_DATA,
105 PM_QID_CLOCK_GET_NAME,
106 PM_QID_CLOCK_GET_TOPOLOGY,
107 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
108 PM_QID_CLOCK_GET_PARENTS,
109 PM_QID_CLOCK_GET_ATTRIBUTES,
110 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
111 PM_QID_CLOCK_GET_MAX_DIVISOR,
114 enum zynqmp_pm_reset_action {
115 PM_RESET_ACTION_RELEASE,
116 PM_RESET_ACTION_ASSERT,
117 PM_RESET_ACTION_PULSE,
120 enum zynqmp_pm_reset {
121 ZYNQMP_PM_RESET_START = 1000,
122 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
123 ZYNQMP_PM_RESET_PCIE_BRIDGE,
124 ZYNQMP_PM_RESET_PCIE_CTRL,
126 ZYNQMP_PM_RESET_SWDT_CRF,
127 ZYNQMP_PM_RESET_AFI_FM5,
128 ZYNQMP_PM_RESET_AFI_FM4,
129 ZYNQMP_PM_RESET_AFI_FM3,
130 ZYNQMP_PM_RESET_AFI_FM2,
131 ZYNQMP_PM_RESET_AFI_FM1,
132 ZYNQMP_PM_RESET_AFI_FM0,
133 ZYNQMP_PM_RESET_GDMA,
134 ZYNQMP_PM_RESET_GPU_PP1,
135 ZYNQMP_PM_RESET_GPU_PP0,
138 ZYNQMP_PM_RESET_SATA,
139 ZYNQMP_PM_RESET_ACPU3_PWRON,
140 ZYNQMP_PM_RESET_ACPU2_PWRON,
141 ZYNQMP_PM_RESET_ACPU1_PWRON,
142 ZYNQMP_PM_RESET_ACPU0_PWRON,
143 ZYNQMP_PM_RESET_APU_L2,
144 ZYNQMP_PM_RESET_ACPU3,
145 ZYNQMP_PM_RESET_ACPU2,
146 ZYNQMP_PM_RESET_ACPU1,
147 ZYNQMP_PM_RESET_ACPU0,
149 ZYNQMP_PM_RESET_APM_FPD,
150 ZYNQMP_PM_RESET_SOFT,
151 ZYNQMP_PM_RESET_GEM0,
152 ZYNQMP_PM_RESET_GEM1,
153 ZYNQMP_PM_RESET_GEM2,
154 ZYNQMP_PM_RESET_GEM3,
155 ZYNQMP_PM_RESET_QSPI,
156 ZYNQMP_PM_RESET_UART0,
157 ZYNQMP_PM_RESET_UART1,
158 ZYNQMP_PM_RESET_SPI0,
159 ZYNQMP_PM_RESET_SPI1,
160 ZYNQMP_PM_RESET_SDIO0,
161 ZYNQMP_PM_RESET_SDIO1,
162 ZYNQMP_PM_RESET_CAN0,
163 ZYNQMP_PM_RESET_CAN1,
164 ZYNQMP_PM_RESET_I2C0,
165 ZYNQMP_PM_RESET_I2C1,
166 ZYNQMP_PM_RESET_TTC0,
167 ZYNQMP_PM_RESET_TTC1,
168 ZYNQMP_PM_RESET_TTC2,
169 ZYNQMP_PM_RESET_TTC3,
170 ZYNQMP_PM_RESET_SWDT_CRL,
171 ZYNQMP_PM_RESET_NAND,
172 ZYNQMP_PM_RESET_ADMA,
173 ZYNQMP_PM_RESET_GPIO,
174 ZYNQMP_PM_RESET_IOU_CC,
175 ZYNQMP_PM_RESET_TIMESTAMP,
176 ZYNQMP_PM_RESET_RPU_R50,
177 ZYNQMP_PM_RESET_RPU_R51,
178 ZYNQMP_PM_RESET_RPU_AMBA,
180 ZYNQMP_PM_RESET_RPU_PGE,
181 ZYNQMP_PM_RESET_USB0_CORERESET,
182 ZYNQMP_PM_RESET_USB1_CORERESET,
183 ZYNQMP_PM_RESET_USB0_HIBERRESET,
184 ZYNQMP_PM_RESET_USB1_HIBERRESET,
185 ZYNQMP_PM_RESET_USB0_APB,
186 ZYNQMP_PM_RESET_USB1_APB,
188 ZYNQMP_PM_RESET_APM_LPD,
190 ZYNQMP_PM_RESET_SYSMON,
191 ZYNQMP_PM_RESET_AFI_FM6,
192 ZYNQMP_PM_RESET_LPD_SWDT,
194 ZYNQMP_PM_RESET_RPU_DBG1,
195 ZYNQMP_PM_RESET_RPU_DBG0,
196 ZYNQMP_PM_RESET_DBG_LPD,
197 ZYNQMP_PM_RESET_DBG_FPD,
198 ZYNQMP_PM_RESET_APLL,
199 ZYNQMP_PM_RESET_DPLL,
200 ZYNQMP_PM_RESET_VPLL,
201 ZYNQMP_PM_RESET_IOPLL,
202 ZYNQMP_PM_RESET_RPLL,
203 ZYNQMP_PM_RESET_GPO3_PL_0,
204 ZYNQMP_PM_RESET_GPO3_PL_1,
205 ZYNQMP_PM_RESET_GPO3_PL_2,
206 ZYNQMP_PM_RESET_GPO3_PL_3,
207 ZYNQMP_PM_RESET_GPO3_PL_4,
208 ZYNQMP_PM_RESET_GPO3_PL_5,
209 ZYNQMP_PM_RESET_GPO3_PL_6,
210 ZYNQMP_PM_RESET_GPO3_PL_7,
211 ZYNQMP_PM_RESET_GPO3_PL_8,
212 ZYNQMP_PM_RESET_GPO3_PL_9,
213 ZYNQMP_PM_RESET_GPO3_PL_10,
214 ZYNQMP_PM_RESET_GPO3_PL_11,
215 ZYNQMP_PM_RESET_GPO3_PL_12,
216 ZYNQMP_PM_RESET_GPO3_PL_13,
217 ZYNQMP_PM_RESET_GPO3_PL_14,
218 ZYNQMP_PM_RESET_GPO3_PL_15,
219 ZYNQMP_PM_RESET_GPO3_PL_16,
220 ZYNQMP_PM_RESET_GPO3_PL_17,
221 ZYNQMP_PM_RESET_GPO3_PL_18,
222 ZYNQMP_PM_RESET_GPO3_PL_19,
223 ZYNQMP_PM_RESET_GPO3_PL_20,
224 ZYNQMP_PM_RESET_GPO3_PL_21,
225 ZYNQMP_PM_RESET_GPO3_PL_22,
226 ZYNQMP_PM_RESET_GPO3_PL_23,
227 ZYNQMP_PM_RESET_GPO3_PL_24,
228 ZYNQMP_PM_RESET_GPO3_PL_25,
229 ZYNQMP_PM_RESET_GPO3_PL_26,
230 ZYNQMP_PM_RESET_GPO3_PL_27,
231 ZYNQMP_PM_RESET_GPO3_PL_28,
232 ZYNQMP_PM_RESET_GPO3_PL_29,
233 ZYNQMP_PM_RESET_GPO3_PL_30,
234 ZYNQMP_PM_RESET_GPO3_PL_31,
235 ZYNQMP_PM_RESET_RPU_LS,
236 ZYNQMP_PM_RESET_PS_ONLY,
238 ZYNQMP_PM_RESET_PS_PL0,
239 ZYNQMP_PM_RESET_PS_PL1,
240 ZYNQMP_PM_RESET_PS_PL2,
241 ZYNQMP_PM_RESET_PS_PL3,
242 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
245 enum zynqmp_pm_suspend_reason {
246 SUSPEND_POWER_REQUEST = 201,
248 SUSPEND_SYSTEM_SHUTDOWN,
251 enum zynqmp_pm_request_ack {
252 ZYNQMP_PM_REQUEST_ACK_NO = 1,
253 ZYNQMP_PM_REQUEST_ACK_BLOCKING,
254 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
262 enum tap_delay_type {
263 PM_TAPDELAY_INPUT = 0,
268 * struct zynqmp_pm_query_data - PM query data
270 * @arg1: Argument 1 of query data
271 * @arg2: Argument 2 of query data
272 * @arg3: Argument 3 of query data
274 struct zynqmp_pm_query_data {
281 struct zynqmp_eemi_ops {
282 int (*get_api_version)(u32 *version);
283 int (*get_chipid)(u32 *idcode, u32 *version);
284 int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
285 int (*fpga_get_status)(u32 *value);
286 int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
287 int (*clock_enable)(u32 clock_id);
288 int (*clock_disable)(u32 clock_id);
289 int (*clock_getstate)(u32 clock_id, u32 *state);
290 int (*clock_setdivider)(u32 clock_id, u32 divider);
291 int (*clock_getdivider)(u32 clock_id, u32 *divider);
292 int (*clock_setrate)(u32 clock_id, u64 rate);
293 int (*clock_getrate)(u32 clock_id, u64 *rate);
294 int (*clock_setparent)(u32 clock_id, u32 parent_id);
295 int (*clock_getparent)(u32 clock_id, u32 *parent_id);
296 int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
297 int (*reset_assert)(const enum zynqmp_pm_reset reset,
298 const enum zynqmp_pm_reset_action assert_flag);
299 int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
300 int (*init_finalize)(void);
301 int (*set_suspend_mode)(u32 mode);
302 int (*request_node)(const u32 node,
303 const u32 capabilities,
305 const enum zynqmp_pm_request_ack ack);
306 int (*release_node)(const u32 node);
307 int (*set_requirement)(const u32 node,
308 const u32 capabilities,
310 const enum zynqmp_pm_request_ack ack);
313 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
314 u32 arg2, u32 arg3, u32 *ret_payload);
316 #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
317 const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
319 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
321 return ERR_PTR(-ENODEV);
325 #endif /* __FIRMWARE_ZYNQMP_H__ */