include/dt-bindings/clock/mt6797-clk.h

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef _DT_BINDINGS_CLK_MT6797_H
  16 #define _DT_BINDINGS_CLK_MT6797_H
  17
  18 /* TOPCKGEN */
  19 #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE       1
  20 #define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX           2
  21 #define CLK_TOP_MUX_AXI                         3
  22 #define CLK_TOP_MUX_MEM                         4
  23 #define CLK_TOP_MUX_DDRPHYCFG                   5
  24 #define CLK_TOP_MUX_MM                          6
  25 #define CLK_TOP_MUX_PWM                         7
  26 #define CLK_TOP_MUX_VDEC                        8
  27 #define CLK_TOP_MUX_VENC                        9
  28 #define CLK_TOP_MUX_MFG                         10
  29 #define CLK_TOP_MUX_CAMTG                       11
  30 #define CLK_TOP_MUX_UART                        12
  31 #define CLK_TOP_MUX_SPI                         13
  32 #define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX           14
  33 #define CLK_TOP_MUX_USB20                       15
  34 #define CLK_TOP_MUX_MSDC50_0_HCLK               16
  35 #define CLK_TOP_MUX_MSDC50_0                    17
  36 #define CLK_TOP_MUX_MSDC30_1                    18
  37 #define CLK_TOP_MUX_MSDC30_2                    19
  38 #define CLK_TOP_MUX_AUDIO                       20
  39 #define CLK_TOP_MUX_AUD_INTBUS                  21
  40 #define CLK_TOP_MUX_PMICSPI                     22
  41 #define CLK_TOP_MUX_SCP                         23
  42 #define CLK_TOP_MUX_ATB                         24
  43 #define CLK_TOP_MUX_MJC                         25
  44 #define CLK_TOP_MUX_DPI0                        26
  45 #define CLK_TOP_MUX_AUD_1                       27
  46 #define CLK_TOP_MUX_AUD_2                       28
  47 #define CLK_TOP_MUX_SSUSB_TOP_SYS               29
  48 #define CLK_TOP_MUX_SPM                         30
  49 #define CLK_TOP_MUX_BSI_SPI                     31
  50 #define CLK_TOP_MUX_AUDIO_H                     32
  51 #define CLK_TOP_MUX_ANC_MD32                    33
  52 #define CLK_TOP_MUX_MFG_52M                     34
  53 #define CLK_TOP_SYSPLL_CK                       35
  54 #define CLK_TOP_SYSPLL_D2                       36
  55 #define CLK_TOP_SYSPLL1_D2                      37
  56 #define CLK_TOP_SYSPLL1_D4                      38
  57 #define CLK_TOP_SYSPLL1_D8                      39
  58 #define CLK_TOP_SYSPLL1_D16                     40
  59 #define CLK_TOP_SYSPLL_D3                       41
  60 #define CLK_TOP_SYSPLL_D3_D3                    42
  61 #define CLK_TOP_SYSPLL2_D2                      43
  62 #define CLK_TOP_SYSPLL2_D4                      44
  63 #define CLK_TOP_SYSPLL2_D8                      45
  64 #define CLK_TOP_SYSPLL_D5                       46
  65 #define CLK_TOP_SYSPLL3_D2                      47
  66 #define CLK_TOP_SYSPLL3_D4                      48
  67 #define CLK_TOP_SYSPLL_D7                       49
  68 #define CLK_TOP_SYSPLL4_D2                      50
  69 #define CLK_TOP_SYSPLL4_D4                      51
  70 #define CLK_TOP_UNIVPLL_CK                      52
  71 #define CLK_TOP_UNIVPLL_D7                      53
  72 #define CLK_TOP_UNIVPLL_D26                     54
  73 #define CLK_TOP_SSUSB_PHY_48M_CK                55
  74 #define CLK_TOP_USB_PHY48M_CK                   56
  75 #define CLK_TOP_UNIVPLL_D2                      57
  76 #define CLK_TOP_UNIVPLL1_D2                     58
  77 #define CLK_TOP_UNIVPLL1_D4                     59
  78 #define CLK_TOP_UNIVPLL1_D8                     60
  79 #define CLK_TOP_UNIVPLL_D3                      61
  80 #define CLK_TOP_UNIVPLL2_D2                     62
  81 #define CLK_TOP_UNIVPLL2_D4                     63
  82 #define CLK_TOP_UNIVPLL2_D8                     64
  83 #define CLK_TOP_UNIVPLL_D5                      65
  84 #define CLK_TOP_UNIVPLL3_D2                     66
  85 #define CLK_TOP_UNIVPLL3_D4                     67
  86 #define CLK_TOP_UNIVPLL3_D8                     68
  87 #define CLK_TOP_ULPOSC_CK_ORG                   69
  88 #define CLK_TOP_ULPOSC_CK                       70
  89 #define CLK_TOP_ULPOSC_D2                       71
  90 #define CLK_TOP_ULPOSC_D3                       72
  91 #define CLK_TOP_ULPOSC_D4                       73
  92 #define CLK_TOP_ULPOSC_D8                       74
  93 #define CLK_TOP_ULPOSC_D10                      75
  94 #define CLK_TOP_APLL1_CK                        76
  95 #define CLK_TOP_APLL2_CK                        77
  96 #define CLK_TOP_MFGPLL_CK                       78
  97 #define CLK_TOP_MFGPLL_D2                       79
  98 #define CLK_TOP_IMGPLL_CK                       80
  99 #define CLK_TOP_IMGPLL_D2                       81
 100 #define CLK_TOP_IMGPLL_D4                       82
 101 #define CLK_TOP_CODECPLL_CK                     83
 102 #define CLK_TOP_CODECPLL_D2                     84
 103 #define CLK_TOP_VDECPLL_CK                      85
 104 #define CLK_TOP_TVDPLL_CK                       86
 105 #define CLK_TOP_TVDPLL_D2                       87
 106 #define CLK_TOP_TVDPLL_D4                       88
 107 #define CLK_TOP_TVDPLL_D8                       89
 108 #define CLK_TOP_TVDPLL_D16                      90
 109 #define CLK_TOP_MSDCPLL_CK                      91
 110 #define CLK_TOP_MSDCPLL_D2                      92
 111 #define CLK_TOP_MSDCPLL_D4                      93
 112 #define CLK_TOP_MSDCPLL_D8                      94
 113 #define CLK_TOP_NR                              95
 114
 115 /* APMIXED_SYS */
 116 #define CLK_APMIXED_MAINPLL                     1
 117 #define CLK_APMIXED_UNIVPLL                     2
 118 #define CLK_APMIXED_MFGPLL                      3
 119 #define CLK_APMIXED_MSDCPLL                     4
 120 #define CLK_APMIXED_IMGPLL                      5
 121 #define CLK_APMIXED_TVDPLL                      6
 122 #define CLK_APMIXED_CODECPLL                    7
 123 #define CLK_APMIXED_VDECPLL                     8
 124 #define CLK_APMIXED_APLL1                       9
 125 #define CLK_APMIXED_APLL2                       10
 126 #define CLK_APMIXED_NR                          11
 127
 128 /* INFRA_SYS */
 129 #define CLK_INFRA_PMIC_TMR                      1
 130 #define CLK_INFRA_PMIC_AP                       2
 131 #define CLK_INFRA_PMIC_MD                       3
 132 #define CLK_INFRA_PMIC_CONN                     4
 133 #define CLK_INFRA_SCP                           5
 134 #define CLK_INFRA_SEJ                           6
 135 #define CLK_INFRA_APXGPT                        7
 136 #define CLK_INFRA_SEJ_13M                       8
 137 #define CLK_INFRA_ICUSB                         9
 138 #define CLK_INFRA_GCE                           10
 139 #define CLK_INFRA_THERM                         11
 140 #define CLK_INFRA_I2C0                          12
 141 #define CLK_INFRA_I2C1                          13
 142 #define CLK_INFRA_I2C2                          14
 143 #define CLK_INFRA_I2C3                          15
 144 #define CLK_INFRA_PWM_HCLK                      16
 145 #define CLK_INFRA_PWM1                          17
 146 #define CLK_INFRA_PWM2                          18
 147 #define CLK_INFRA_PWM3                          19
 148 #define CLK_INFRA_PWM4                          20
 149 #define CLK_INFRA_PWM                           21
 150 #define CLK_INFRA_UART0                         22
 151 #define CLK_INFRA_UART1                         23
 152 #define CLK_INFRA_UART2                         24
 153 #define CLK_INFRA_UART3                         25
 154 #define CLK_INFRA_MD2MD_CCIF_0                  26
 155 #define CLK_INFRA_MD2MD_CCIF_1                  27
 156 #define CLK_INFRA_MD2MD_CCIF_2                  28
 157 #define CLK_INFRA_FHCTL                         29
 158 #define CLK_INFRA_BTIF                          30
 159 #define CLK_INFRA_MD2MD_CCIF_3                  31
 160 #define CLK_INFRA_SPI                           32
 161 #define CLK_INFRA_MSDC0                         33
 162 #define CLK_INFRA_MD2MD_CCIF_4                  34
 163 #define CLK_INFRA_MSDC1                         35
 164 #define CLK_INFRA_MSDC2                         36
 165 #define CLK_INFRA_MD2MD_CCIF_5                  37
 166 #define CLK_INFRA_GCPU                          38
 167 #define CLK_INFRA_TRNG                          39
 168 #define CLK_INFRA_AUXADC                        40
 169 #define CLK_INFRA_CPUM                          41
 170 #define CLK_INFRA_AP_C2K_CCIF_0                 42
 171 #define CLK_INFRA_AP_C2K_CCIF_1                 43
 172 #define CLK_INFRA_CLDMA                         44
 173 #define CLK_INFRA_DISP_PWM                      45
 174 #define CLK_INFRA_AP_DMA                        46
 175 #define CLK_INFRA_DEVICE_APC                    47
 176 #define CLK_INFRA_L2C_SRAM                      48
 177 #define CLK_INFRA_CCIF_AP                       49
 178 #define CLK_INFRA_AUDIO                         50
 179 #define CLK_INFRA_CCIF_MD                       51
 180 #define CLK_INFRA_DRAMC_F26M                    52
 181 #define CLK_INFRA_I2C4                          53
 182 #define CLK_INFRA_I2C_APPM                      54
 183 #define CLK_INFRA_I2C_GPUPM                     55
 184 #define CLK_INFRA_I2C2_IMM                      56
 185 #define CLK_INFRA_I2C2_ARB                      57
 186 #define CLK_INFRA_I2C3_IMM                      58
 187 #define CLK_INFRA_I2C3_ARB                      59
 188 #define CLK_INFRA_I2C5                          60
 189 #define CLK_INFRA_SYS_CIRQ                      61
 190 #define CLK_INFRA_SPI1                          62
 191 #define CLK_INFRA_DRAMC_B_F26M                  63
 192 #define CLK_INFRA_ANC_MD32                      64
 193 #define CLK_INFRA_ANC_MD32_32K                  65
 194 #define CLK_INFRA_DVFS_SPM1                     66
 195 #define CLK_INFRA_AES_TOP0                      67
 196 #define CLK_INFRA_AES_TOP1                      68
 197 #define CLK_INFRA_SSUSB_BUS                     69
 198 #define CLK_INFRA_SPI2                          70
 199 #define CLK_INFRA_SPI3                          71
 200 #define CLK_INFRA_SPI4                          72
 201 #define CLK_INFRA_SPI5                          73
 202 #define CLK_INFRA_IRTX                          74
 203 #define CLK_INFRA_SSUSB_SYS                     75
 204 #define CLK_INFRA_SSUSB_REF                     76
 205 #define CLK_INFRA_AUDIO_26M                     77
 206 #define CLK_INFRA_AUDIO_26M_PAD_TOP             78
 207 #define CLK_INFRA_MODEM_TEMP_SHARE              79
 208 #define CLK_INFRA_VAD_WRAP_SOC                  80
 209 #define CLK_INFRA_DRAMC_CONF                    81
 210 #define CLK_INFRA_DRAMC_B_CONF                  82
 211 #define CLK_INFRA_MFG_VCG                       83
 212 #define CLK_INFRA_13M                           84
 213 #define CLK_INFRA_NR                            85
 214
 215 /* IMG_SYS */
 216 #define CLK_IMG_FDVT                            1
 217 #define CLK_IMG_DPE                             2
 218 #define CLK_IMG_DIP                             3
 219 #define CLK_IMG_LARB6                           4
 220 #define CLK_IMG_NR                              5
 221
 222 /* MM_SYS */
 223 #define CLK_MM_SMI_COMMON                       1
 224 #define CLK_MM_SMI_LARB0                        2
 225 #define CLK_MM_SMI_LARB5                        3
 226 #define CLK_MM_CAM_MDP                          4
 227 #define CLK_MM_MDP_RDMA0                        5
 228 #define CLK_MM_MDP_RDMA1                        6
 229 #define CLK_MM_MDP_RSZ0                         7
 230 #define CLK_MM_MDP_RSZ1                         8
 231 #define CLK_MM_MDP_RSZ2                         9
 232 #define CLK_MM_MDP_TDSHP                        10
 233 #define CLK_MM_MDP_COLOR                        11
 234 #define CLK_MM_MDP_WDMA                         12
 235 #define CLK_MM_MDP_WROT0                        13
 236 #define CLK_MM_MDP_WROT1                        14
 237 #define CLK_MM_FAKE_ENG                         15
 238 #define CLK_MM_DISP_OVL0                        16
 239 #define CLK_MM_DISP_OVL1                        17
 240 #define CLK_MM_DISP_OVL0_2L                     18
 241 #define CLK_MM_DISP_OVL1_2L                     19
 242 #define CLK_MM_DISP_RDMA0                       20
 243 #define CLK_MM_DISP_RDMA1                       21
 244 #define CLK_MM_DISP_WDMA0                       22
 245 #define CLK_MM_DISP_WDMA1                       23
 246 #define CLK_MM_DISP_COLOR                       24
 247 #define CLK_MM_DISP_CCORR                       25
 248 #define CLK_MM_DISP_AAL                         26
 249 #define CLK_MM_DISP_GAMMA                       27
 250 #define CLK_MM_DISP_OD                          28
 251 #define CLK_MM_DISP_DITHER                      29
 252 #define CLK_MM_DISP_UFOE                        30
 253 #define CLK_MM_DISP_DSC                         31
 254 #define CLK_MM_DISP_SPLIT                       32
 255 #define CLK_MM_DSI0_MM_CLOCK                    33
 256 #define CLK_MM_DSI1_MM_CLOCK                    34
 257 #define CLK_MM_DPI_MM_CLOCK                     35
 258 #define CLK_MM_DPI_INTERFACE_CLOCK              36
 259 #define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK          37
 260 #define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK         38
 261 #define CLK_MM_DISP_OVL0_MOUT_CLOCK             39
 262 #define CLK_MM_FAKE_ENG2                        40
 263 #define CLK_MM_DSI0_INTERFACE_CLOCK             41
 264 #define CLK_MM_DSI1_INTERFACE_CLOCK             42
 265 #define CLK_MM_NR                               43
 266
 267 /* VDEC_SYS */
 268 #define CLK_VDEC_CKEN_ENG                       1
 269 #define CLK_VDEC_ACTIVE                         2
 270 #define CLK_VDEC_CKEN                           3
 271 #define CLK_VDEC_LARB1_CKEN                     4
 272 #define CLK_VDEC_NR                             5
 273
 274 /* VENC_SYS */
 275 #define CLK_VENC_0                              1
 276 #define CLK_VENC_1                              2
 277 #define CLK_VENC_2                              3
 278 #define CLK_VENC_3                              4
 279 #define CLK_VENC_NR                             5
 280
 281 #endif /* _DT_BINDINGS_CLK_MT6797_H */