include/asm-sh/system.h

   1 #ifndef __ASM_SH_SYSTEM_H
   2 #define __ASM_SH_SYSTEM_H
   3
   4 /*
   5  * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
   6  * Copyright (C) 2002 Paul Mundt
   7  */
   8
   9 #include <linux/irqflags.h>
  10 #include <linux/compiler.h>
  11 #include <linux/linkage.h>
  12 #include <asm/types.h>
  13 #include <asm/ptrace.h>
  14
  15 struct task_struct *__switch_to(struct task_struct *prev,
  16                                 struct task_struct *next);
  17
  18 /*
  19  *      switch_to() should switch tasks to task nr n, first
  20  */
  21
  22 #define switch_to(prev, next, last) do {                                \
  23  struct task_struct *__last;                                            \
  24  register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp;       \
  25  register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc;       \
  26  register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev;  \
  27  register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next;  \
  28  register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp;       \
  29  register unsigned long __ts7 __asm__ ("r7") = next->thread.pc;         \
  30  __asm__ __volatile__ (".balign 4\n\t"                                  \
  31                        "stc.l   gbr, @-r15\n\t"                         \
  32                        "sts.l   pr, @-r15\n\t"                          \
  33                        "mov.l   r8, @-r15\n\t"                          \
  34                        "mov.l   r9, @-r15\n\t"                          \
  35                        "mov.l   r10, @-r15\n\t"                         \
  36                        "mov.l   r11, @-r15\n\t"                         \
  37                        "mov.l   r12, @-r15\n\t"                         \
  38                        "mov.l   r13, @-r15\n\t"                         \
  39                        "mov.l   r14, @-r15\n\t"                         \
  40                        "mov.l   r15, @r1        ! save SP\n\t"          \
  41                        "mov.l   @r6, r15        ! change to new stack\n\t" \
  42                        "mova    1f, %0\n\t"                             \
  43                        "mov.l   %0, @r2         ! save PC\n\t"          \
  44                        "mov.l   2f, %0\n\t"                             \
  45                        "jmp     @%0             ! call __switch_to\n\t" \
  46                        " lds    r7, pr          !  with return to new PC\n\t" \
  47                        ".balign 4\n"                                    \
  48                        "2:\n\t"                                         \
  49                        ".long   __switch_to\n"                          \
  50                        "1:\n\t"                                         \
  51                        "mov.l   @r15+, r14\n\t"                         \
  52                        "mov.l   @r15+, r13\n\t"                         \
  53                        "mov.l   @r15+, r12\n\t"                         \
  54                        "mov.l   @r15+, r11\n\t"                         \
  55                        "mov.l   @r15+, r10\n\t"                         \
  56                        "mov.l   @r15+, r9\n\t"                          \
  57                        "mov.l   @r15+, r8\n\t"                          \
  58                        "lds.l   @r15+, pr\n\t"                          \
  59                        "ldc.l   @r15+, gbr\n\t"                         \
  60                        : "=z" (__last)                                  \
  61                        : "r" (__ts1), "r" (__ts2), "r" (__ts4),         \
  62                          "r" (__ts5), "r" (__ts6), "r" (__ts7)          \
  63                        : "r3", "t");                                    \
  64         last = __last;                                                  \
  65 } while (0)
  66
  67 /*
  68  * On SMP systems, when the scheduler does migration-cost autodetection,
  69  * it needs a way to flush as much of the CPU's caches as possible.
  70  *
  71  * TODO: fill this in!
  72  */
  73 static inline void sched_cacheflush(void)
  74 {
  75 }
  76
  77 #ifdef CONFIG_CPU_SH4A
  78 #define __icbi()                        \
  79 {                                       \
  80         unsigned long __addr;           \
  81         __addr = 0xa8000000;            \
  82         __asm__ __volatile__(           \
  83                 "icbi   %0\n\t"         \
  84                 : /* no output */       \
  85                 : "m" (__m(__addr)));   \
  86 }
  87 #endif
  88
  89 /*
  90  * A brief note on ctrl_barrier(), the control register write barrier.
  91  *
  92  * Legacy SH cores typically require a sequence of 8 nops after
  93  * modification of a control register in order for the changes to take
  94  * effect. On newer cores (like the sh4a and sh5) this is accomplished
  95  * with icbi.
  96  *
  97  * Also note that on sh4a in the icbi case we can forego a synco for the
  98  * write barrier, as it's not necessary for control registers.
  99  *
 100  * Historically we have only done this type of barrier for the MMUCR, but
 101  * it's also necessary for the CCR, so we make it generic here instead.
 102  */
 103 #ifdef CONFIG_CPU_SH4A
 104 #define mb()            __asm__ __volatile__ ("synco": : :"memory")
 105 #define rmb()           mb()
 106 #define wmb()           __asm__ __volatile__ ("synco": : :"memory")
 107 #define ctrl_barrier()  __icbi()
 108 #define read_barrier_depends()  do { } while(0)
 109 #else
 110 #define mb()            __asm__ __volatile__ ("": : :"memory")
 111 #define rmb()           mb()
 112 #define wmb()           __asm__ __volatile__ ("": : :"memory")
 113 #define ctrl_barrier()  __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
 114 #define read_barrier_depends()  do { } while(0)
 115 #endif
 116
 117 #ifdef CONFIG_SMP
 118 #define smp_mb()        mb()
 119 #define smp_rmb()       rmb()
 120 #define smp_wmb()       wmb()
 121 #define smp_read_barrier_depends()      read_barrier_depends()
 122 #else
 123 #define smp_mb()        barrier()
 124 #define smp_rmb()       barrier()
 125 #define smp_wmb()       barrier()
 126 #define smp_read_barrier_depends()      do { } while(0)
 127 #endif
 128
 129 #define set_mb(var, value) do { xchg(&var, value); } while (0)
 130
 131 /*
 132  * Jump to P2 area.
 133  * When handling TLB or caches, we need to do it from P2 area.
 134  */
 135 #define jump_to_P2()                    \
 136 do {                                    \
 137         unsigned long __dummy;          \
 138         __asm__ __volatile__(           \
 139                 "mov.l  1f, %0\n\t"     \
 140                 "or     %1, %0\n\t"     \
 141                 "jmp    @%0\n\t"        \
 142                 " nop\n\t"              \
 143                 ".balign 4\n"           \
 144                 "1:     .long 2f\n"     \
 145                 "2:"                    \
 146                 : "=&r" (__dummy)       \
 147                 : "r" (0x20000000));    \
 148 } while (0)
 149
 150 /*
 151  * Back to P1 area.
 152  */
 153 #define back_to_P1()                                    \
 154 do {                                                    \
 155         unsigned long __dummy;                          \
 156         ctrl_barrier();                                 \
 157         __asm__ __volatile__(                           \
 158                 "mov.l  1f, %0\n\t"                     \
 159                 "jmp    @%0\n\t"                        \
 160                 " nop\n\t"                              \
 161                 ".balign 4\n"                           \
 162                 "1:     .long 2f\n"                     \
 163                 "2:"                                    \
 164                 : "=&r" (__dummy));                     \
 165 } while (0)
 166
 167 static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
 168 {
 169         unsigned long flags, retval;
 170
 171         local_irq_save(flags);
 172         retval = *m;
 173         *m = val;
 174         local_irq_restore(flags);
 175         return retval;
 176 }
 177
 178 static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
 179 {
 180         unsigned long flags, retval;
 181
 182         local_irq_save(flags);
 183         retval = *m;
 184         *m = val & 0xff;
 185         local_irq_restore(flags);
 186         return retval;
 187 }
 188
 189 extern void __xchg_called_with_bad_pointer(void);
 190
 191 #define __xchg(ptr, x, size)                            \
 192 ({                                                      \
 193         unsigned long __xchg__res;                      \
 194         volatile void *__xchg_ptr = (ptr);              \
 195         switch (size) {                                 \
 196         case 4:                                         \
 197                 __xchg__res = xchg_u32(__xchg_ptr, x);  \
 198                 break;                                  \
 199         case 1:                                         \
 200                 __xchg__res = xchg_u8(__xchg_ptr, x);   \
 201                 break;                                  \
 202         default:                                        \
 203                 __xchg_called_with_bad_pointer();       \
 204                 __xchg__res = x;                        \
 205                 break;                                  \
 206         }                                               \
 207                                                         \
 208         __xchg__res;                                    \
 209 })
 210
 211 #define xchg(ptr,x)     \
 212         ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
 213
 214 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
 215         unsigned long new)
 216 {
 217         __u32 retval;
 218         unsigned long flags;
 219
 220         local_irq_save(flags);
 221         retval = *m;
 222         if (retval == old)
 223                 *m = new;
 224         local_irq_restore(flags);       /* implies memory barrier  */
 225         return retval;
 226 }
 227
 228 /* This function doesn't exist, so you'll get a linker error
 229  * if something tries to do an invalid cmpxchg(). */
 230 extern void __cmpxchg_called_with_bad_pointer(void);
 231
 232 #define __HAVE_ARCH_CMPXCHG 1
 233
 234 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
 235                 unsigned long new, int size)
 236 {
 237         switch (size) {
 238         case 4:
 239                 return __cmpxchg_u32(ptr, old, new);
 240         }
 241         __cmpxchg_called_with_bad_pointer();
 242         return old;
 243 }
 244
 245 #define cmpxchg(ptr,o,n)                                                 \
 246   ({                                                                     \
 247      __typeof__(*(ptr)) _o_ = (o);                                       \
 248      __typeof__(*(ptr)) _n_ = (n);                                       \
 249      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 250                                     (unsigned long)_n_, sizeof(*(ptr))); \
 251   })
 252
 253 extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
 254
 255 extern void *set_exception_table_vec(unsigned int vec, void *handler);
 256
 257 static inline void *set_exception_table_evt(unsigned int evt, void *handler)
 258 {
 259         return set_exception_table_vec(evt >> 5, handler);
 260 }
 261
 262 /*
 263  * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
 264  */
 265 #ifdef CONFIG_CPU_SH2A
 266 extern unsigned int instruction_size(unsigned int insn);
 267 #else
 268 #define instruction_size(insn)  (2)
 269 #endif
 270
 271 /* XXX
 272  * disable hlt during certain critical i/o operations
 273  */
 274 #define HAVE_DISABLE_HLT
 275 void disable_hlt(void);
 276 void enable_hlt(void);
 277
 278 void default_idle(void);
 279
 280 asmlinkage void break_point_trap(void);
 281 asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5,
 282                                    unsigned long r6, unsigned long r7,
 283                                    struct pt_regs __regs);
 284 asmlinkage void bug_trap_handler(unsigned long r4, unsigned long r5,
 285                                  unsigned long r6, unsigned long r7,
 286                                  struct pt_regs __regs);
 287
 288 #define arch_align_stack(x) (x)
 289
 290 #endif