include/asm-blackfin/mach-bf548/bfin_serial_5xx.h

   1 #include <linux/serial.h>
   2 #include <asm/dma.h>
   3
   4 #define NR_PORTS                4
   5
   6 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
   7 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
   8 #define OFFSET_GCTL             0x08    /* Global Control Register              */
   9 #define OFFSET_LCR              0x0C    /* Line Control Register                */
  10 #define OFFSET_MCR              0x10    /* Modem Control Register               */
  11 #define OFFSET_LSR              0x14    /* Line Status Register                 */
  12 #define OFFSET_MSR              0x18    /* Modem Status Register                */
  13 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
  14 #define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
  15 #define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
  16 #define OFFSET_THR              0x28    /* Transmit Holding register            */
  17 #define OFFSET_RBR              0x2C    /* Receive Buffer register              */
  18
  19 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  20 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  21 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  22 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
  23 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  24 #define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
  25 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  26
  27 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  28 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  29 #define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
  30 #define UART_CLEAR_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
  31 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  32 #define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
  33 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  34 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  35
  36 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  37 # define CONFIG_SERIAL_BFIN_CTSRTS
  38
  39 # ifndef CONFIG_UART0_CTS_PIN
  40 #  define CONFIG_UART0_CTS_PIN -1
  41 # endif
  42
  43 # ifndef CONFIG_UART0_RTS_PIN
  44 #  define CONFIG_UART0_RTS_PIN -1
  45 # endif
  46
  47 # ifndef CONFIG_UART1_CTS_PIN
  48 #  define CONFIG_UART1_CTS_PIN -1
  49 # endif
  50
  51 # ifndef CONFIG_UART1_RTS_PIN
  52 #  define CONFIG_UART1_RTS_PIN -1
  53 # endif
  54 #endif
  55 /*
  56  * The pin configuration is different from schematic
  57  */
  58 struct bfin_serial_port {
  59         struct uart_port        port;
  60         unsigned int            old_status;
  61 #ifdef CONFIG_SERIAL_BFIN_DMA
  62         int                     tx_done;
  63         int                     tx_count;
  64         struct circ_buf         rx_dma_buf;
  65         struct timer_list       rx_dma_timer;
  66         int                     rx_dma_nrows;
  67         unsigned int            tx_dma_channel;
  68         unsigned int            rx_dma_channel;
  69         struct work_struct      tx_dma_workqueue;
  70 #else
  71         struct work_struct      cts_workqueue;
  72 #endif
  73 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  74         int             cts_pin;
  75         int             rts_pin;
  76 #endif
  77 };
  78
  79 struct bfin_serial_port bfin_serial_ports[NR_PORTS];
  80 struct bfin_serial_res {
  81         unsigned long   uart_base_addr;
  82         int             uart_irq;
  83 #ifdef CONFIG_SERIAL_BFIN_DMA
  84         unsigned int    uart_tx_dma_channel;
  85         unsigned int    uart_rx_dma_channel;
  86 #endif
  87 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  88         int     uart_cts_pin;
  89         int     uart_rts_pin;
  90 #endif
  91 };
  92
  93 struct bfin_serial_res bfin_serial_resource[] = {
  94 #ifdef CONFIG_SERIAL_BFIN_UART0
  95         {
  96         0xFFC00400,
  97         IRQ_UART0_RX,
  98 #ifdef CONFIG_SERIAL_BFIN_DMA
  99         CH_UART0_TX,
 100         CH_UART0_RX,
 101 #endif
 102 #ifdef CONFIG_BFIN_UART0_CTSRTS
 103         CONFIG_UART0_CTS_PIN,
 104         CONFIG_UART0_RTS_PIN,
 105 #endif
 106         },
 107 #endif
 108 #ifdef CONFIG_SERIAL_BFIN_UART1
 109         {
 110         0xFFC02000,
 111         IRQ_UART1_RX,
 112 #ifdef CONFIG_SERIAL_BFIN_DMA
 113         CH_UART1_TX,
 114         CH_UART1_RX,
 115 #endif
 116         },
 117 #endif
 118 #ifdef CONFIG_SERIAL_BFIN_UART2
 119         {
 120         0xFFC02100,
 121         IRQ_UART2_RX,
 122 #ifdef CONFIG_SERIAL_BFIN_DMA
 123         CH_UART2_TX,
 124         CH_UART2_RX,
 125 #endif
 126 #ifdef CONFIG_BFIN_UART2_CTSRTS
 127         CONFIG_UART2_CTS_PIN,
 128         CONFIG_UART2_RTS_PIN,
 129 #endif
 130         },
 131 #endif
 132 #ifdef CONFIG_SERIAL_BFIN_UART3
 133         {
 134         0xFFC03100,
 135         IRQ_UART3_RX,
 136 #ifdef CONFIG_SERIAL_BFIN_DMA
 137         CH_UART3_TX,
 138         CH_UART3_RX,
 139 #endif
 140         },
 141 #endif
 142 };
 143
 144 int nr_ports = ARRAY_SIZE(bfin_serial_resource);
 145
 146 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 147 {
 148 #ifdef CONFIG_SERIAL_BFIN_UART0
 149         /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
 150         bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
 151         bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
 152 #endif
 153
 154 #ifdef CONFIG_SERIAL_BFIN_UART1
 155         /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */
 156         bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER());
 157         bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX());
 158 #ifdef CONFIG_BFIN_UART1_CTSRTS
 159         /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */
 160         bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER());
 161         bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX());
 162 #endif
 163 #endif
 164
 165 #ifdef CONFIG_SERIAL_BFIN_UART2
 166         /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */
 167         bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER());
 168         bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX());
 169 #endif
 170
 171 #ifdef CONFIG_SERIAL_BFIN_UART3
 172         /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */
 173         bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER());
 174         bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX());
 175 #ifdef CONFIG_BFIN_UART3_CTSRTS
 176         /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */
 177         bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER());
 178         bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX());
 179 #endif
 180 #endif
 181         SSYNC();
 182 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 183         if (uart->cts_pin >= 0) {
 184                 gpio_request(uart->cts_pin, NULL);
 185                 gpio_direction_input(uart->cts_pin);
 186         }
 187
 188         if (uart->rts_pin >= 0) {
 189                 gpio_request(uart->rts_pin, NULL);
 190                 gpio_direction_output(uart->rts_pin);
 191         }
 192 #endif
 193 }