drivers/watchdog/s3c2410_wdt.c

   1 /* linux/drivers/char/watchdog/s3c2410_wdt.c
   2  *
   3  * Copyright (c) 2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 Watchdog Timer Support
   7  *
   8  * Based on, softdog.c by Alan Cox,
   9  *     (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24 */
  25
  26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  27
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/types.h>
  31 #include <linux/timer.h>
  32 #include <linux/miscdevice.h> /* for MODULE_ALIAS_MISCDEV */
  33 #include <linux/watchdog.h>
  34 #include <linux/init.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/clk.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/io.h>
  40 #include <linux/cpufreq.h>
  41 #include <linux/slab.h>
  42 #include <linux/err.h>
  43
  44 #include <mach/map.h>
  45
  46 #undef S3C_VA_WATCHDOG
  47 #define S3C_VA_WATCHDOG (0)
  48
  49 #include <plat/regs-watchdog.h>
  50
  51 #define CONFIG_S3C2410_WATCHDOG_ATBOOT          (0)
  52 #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME    (15)
  53
  54 static bool nowayout    = WATCHDOG_NOWAYOUT;
  55 static int tmr_margin   = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
  56 static int tmr_atboot   = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  57 static int soft_noboot;
  58 static int debug;
  59
  60 module_param(tmr_margin,  int, 0);
  61 module_param(tmr_atboot,  int, 0);
  62 module_param(nowayout,   bool, 0);
  63 module_param(soft_noboot, int, 0);
  64 module_param(debug,       int, 0);
  65
  66 MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
  67                 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  68 MODULE_PARM_DESC(tmr_atboot,
  69                 "Watchdog is started at boot time if set to 1, default="
  70                         __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  71 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  72                         __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  73 MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  74                         "0 to reboot (default 0)");
  75 MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
  76
  77 static struct device    *wdt_dev;       /* platform device attached to */
  78 static struct resource  *wdt_mem;
  79 static struct resource  *wdt_irq;
  80 static struct clk       *wdt_clock;
  81 static void __iomem     *wdt_base;
  82 static unsigned int      wdt_count;
  83 static DEFINE_SPINLOCK(wdt_lock);
  84
  85 /* watchdog control routines */
  86
  87 #define DBG(fmt, ...)                                   \
  88 do {                                                    \
  89         if (debug)                                      \
  90                 pr_info(fmt, ##__VA_ARGS__);            \
  91 } while (0)
  92
  93 /* functions */
  94
  95 static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
  96 {
  97         spin_lock(&wdt_lock);
  98         writel(wdt_count, wdt_base + S3C2410_WTCNT);
  99         spin_unlock(&wdt_lock);
 100
 101         return 0;
 102 }
 103
 104 static void __s3c2410wdt_stop(void)
 105 {
 106         unsigned long wtcon;
 107
 108         wtcon = readl(wdt_base + S3C2410_WTCON);
 109         wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
 110         writel(wtcon, wdt_base + S3C2410_WTCON);
 111 }
 112
 113 static int s3c2410wdt_stop(struct watchdog_device *wdd)
 114 {
 115         spin_lock(&wdt_lock);
 116         __s3c2410wdt_stop();
 117         spin_unlock(&wdt_lock);
 118
 119         return 0;
 120 }
 121
 122 static int s3c2410wdt_start(struct watchdog_device *wdd)
 123 {
 124         unsigned long wtcon;
 125
 126         spin_lock(&wdt_lock);
 127
 128         __s3c2410wdt_stop();
 129
 130         wtcon = readl(wdt_base + S3C2410_WTCON);
 131         wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
 132
 133         if (soft_noboot) {
 134                 wtcon |= S3C2410_WTCON_INTEN;
 135                 wtcon &= ~S3C2410_WTCON_RSTEN;
 136         } else {
 137                 wtcon &= ~S3C2410_WTCON_INTEN;
 138                 wtcon |= S3C2410_WTCON_RSTEN;
 139         }
 140
 141         DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
 142             __func__, wdt_count, wtcon);
 143
 144         writel(wdt_count, wdt_base + S3C2410_WTDAT);
 145         writel(wdt_count, wdt_base + S3C2410_WTCNT);
 146         writel(wtcon, wdt_base + S3C2410_WTCON);
 147         spin_unlock(&wdt_lock);
 148
 149         return 0;
 150 }
 151
 152 static inline int s3c2410wdt_is_running(void)
 153 {
 154         return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
 155 }
 156
 157 static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
 158 {
 159         unsigned long freq = clk_get_rate(wdt_clock);
 160         unsigned int count;
 161         unsigned int divisor = 1;
 162         unsigned long wtcon;
 163
 164         if (timeout < 1)
 165                 return -EINVAL;
 166
 167         freq /= 128;
 168         count = timeout * freq;
 169
 170         DBG("%s: count=%d, timeout=%d, freq=%lu\n",
 171             __func__, count, timeout, freq);
 172
 173         /* if the count is bigger than the watchdog register,
 174            then work out what we need to do (and if) we can
 175            actually make this value
 176         */
 177
 178         if (count >= 0x10000) {
 179                 for (divisor = 1; divisor <= 0x100; divisor++) {
 180                         if ((count / divisor) < 0x10000)
 181                                 break;
 182                 }
 183
 184                 if ((count / divisor) >= 0x10000) {
 185                         dev_err(wdt_dev, "timeout %d too big\n", timeout);
 186                         return -EINVAL;
 187                 }
 188         }
 189
 190         DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
 191             __func__, timeout, divisor, count, count/divisor);
 192
 193         count /= divisor;
 194         wdt_count = count;
 195
 196         /* update the pre-scaler */
 197         wtcon = readl(wdt_base + S3C2410_WTCON);
 198         wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
 199         wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
 200
 201         writel(count, wdt_base + S3C2410_WTDAT);
 202         writel(wtcon, wdt_base + S3C2410_WTCON);
 203
 204         return 0;
 205 }
 206
 207 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
 208
 209 static const struct watchdog_info s3c2410_wdt_ident = {
 210         .options          =     OPTIONS,
 211         .firmware_version =     0,
 212         .identity         =     "S3C2410 Watchdog",
 213 };
 214
 215 static struct watchdog_ops s3c2410wdt_ops = {
 216         .owner = THIS_MODULE,
 217         .start = s3c2410wdt_start,
 218         .stop = s3c2410wdt_stop,
 219         .ping = s3c2410wdt_keepalive,
 220         .set_timeout = s3c2410wdt_set_heartbeat,
 221 };
 222
 223 static struct watchdog_device s3c2410_wdd = {
 224         .info = &s3c2410_wdt_ident,
 225         .ops = &s3c2410wdt_ops,
 226 };
 227
 228 /* interrupt handler code */
 229
 230 static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
 231 {
 232         dev_info(wdt_dev, "watchdog timer expired (irq)\n");
 233
 234         s3c2410wdt_keepalive(&s3c2410_wdd);
 235         return IRQ_HANDLED;
 236 }
 237
 238
 239 #ifdef CONFIG_CPU_FREQ
 240
 241 static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
 242                                           unsigned long val, void *data)
 243 {
 244         int ret;
 245
 246         if (!s3c2410wdt_is_running())
 247                 goto done;
 248
 249         if (val == CPUFREQ_PRECHANGE) {
 250                 /* To ensure that over the change we don't cause the
 251                  * watchdog to trigger, we perform an keep-alive if
 252                  * the watchdog is running.
 253                  */
 254
 255                 s3c2410wdt_keepalive(&s3c2410_wdd);
 256         } else if (val == CPUFREQ_POSTCHANGE) {
 257                 s3c2410wdt_stop(&s3c2410_wdd);
 258
 259                 ret = s3c2410wdt_set_heartbeat(&s3c2410_wdd, s3c2410_wdd.timeout);
 260
 261                 if (ret >= 0)
 262                         s3c2410wdt_start(&s3c2410_wdd);
 263                 else
 264                         goto err;
 265         }
 266
 267 done:
 268         return 0;
 269
 270  err:
 271         dev_err(wdt_dev, "cannot set new value for timeout %d\n",
 272                                 s3c2410_wdd.timeout);
 273         return ret;
 274 }
 275
 276 static struct notifier_block s3c2410wdt_cpufreq_transition_nb = {
 277         .notifier_call  = s3c2410wdt_cpufreq_transition,
 278 };
 279
 280 static inline int s3c2410wdt_cpufreq_register(void)
 281 {
 282         return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb,
 283                                          CPUFREQ_TRANSITION_NOTIFIER);
 284 }
 285
 286 static inline void s3c2410wdt_cpufreq_deregister(void)
 287 {
 288         cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb,
 289                                     CPUFREQ_TRANSITION_NOTIFIER);
 290 }
 291
 292 #else
 293 static inline int s3c2410wdt_cpufreq_register(void)
 294 {
 295         return 0;
 296 }
 297
 298 static inline void s3c2410wdt_cpufreq_deregister(void)
 299 {
 300 }
 301 #endif
 302
 303 static int __devinit s3c2410wdt_probe(struct platform_device *pdev)
 304 {
 305         struct device *dev;
 306         unsigned int wtcon;
 307         int started = 0;
 308         int ret;
 309         int size;
 310
 311         DBG("%s: probe=%p\n", __func__, pdev);
 312
 313         dev = &pdev->dev;
 314         wdt_dev = &pdev->dev;
 315
 316         wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 317         if (wdt_mem == NULL) {
 318                 dev_err(dev, "no memory resource specified\n");
 319                 return -ENOENT;
 320         }
 321
 322         wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 323         if (wdt_irq == NULL) {
 324                 dev_err(dev, "no irq resource specified\n");
 325                 ret = -ENOENT;
 326                 goto err;
 327         }
 328
 329         /* get the memory region for the watchdog timer */
 330
 331         size = resource_size(wdt_mem);
 332         if (!request_mem_region(wdt_mem->start, size, pdev->name)) {
 333                 dev_err(dev, "failed to get memory region\n");
 334                 ret = -EBUSY;
 335                 goto err;
 336         }
 337
 338         wdt_base = ioremap(wdt_mem->start, size);
 339         if (wdt_base == NULL) {
 340                 dev_err(dev, "failed to ioremap() region\n");
 341                 ret = -EINVAL;
 342                 goto err_req;
 343         }
 344
 345         DBG("probe: mapped wdt_base=%p\n", wdt_base);
 346
 347         wdt_clock = clk_get(&pdev->dev, "watchdog");
 348         if (IS_ERR(wdt_clock)) {
 349                 dev_err(dev, "failed to find watchdog clock source\n");
 350                 ret = PTR_ERR(wdt_clock);
 351                 goto err_map;
 352         }
 353
 354         clk_enable(wdt_clock);
 355
 356         ret = s3c2410wdt_cpufreq_register();
 357         if (ret < 0) {
 358                 pr_err("failed to register cpufreq\n");
 359                 goto err_clk;
 360         }
 361
 362         /* see if we can actually set the requested timer margin, and if
 363          * not, try the default value */
 364
 365         if (s3c2410wdt_set_heartbeat(&s3c2410_wdd, tmr_margin)) {
 366                 started = s3c2410wdt_set_heartbeat(&s3c2410_wdd,
 367                                         CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
 368
 369                 if (started == 0)
 370                         dev_info(dev,
 371                            "tmr_margin value out of range, default %d used\n",
 372                                CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
 373                 else
 374                         dev_info(dev, "default timer value is out of range, "
 375                                                         "cannot start\n");
 376         }
 377
 378         ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
 379         if (ret != 0) {
 380                 dev_err(dev, "failed to install irq (%d)\n", ret);
 381                 goto err_cpufreq;
 382         }
 383
 384         watchdog_set_nowayout(&s3c2410_wdd, nowayout);
 385
 386         ret = watchdog_register_device(&s3c2410_wdd);
 387         if (ret) {
 388                 dev_err(dev, "cannot register watchdog (%d)\n", ret);
 389                 goto err_irq;
 390         }
 391
 392         if (tmr_atboot && started == 0) {
 393                 dev_info(dev, "starting watchdog timer\n");
 394                 s3c2410wdt_start(&s3c2410_wdd);
 395         } else if (!tmr_atboot) {
 396                 /* if we're not enabling the watchdog, then ensure it is
 397                  * disabled if it has been left running from the bootloader
 398                  * or other source */
 399
 400                 s3c2410wdt_stop(&s3c2410_wdd);
 401         }
 402
 403         /* print out a statement of readiness */
 404
 405         wtcon = readl(wdt_base + S3C2410_WTCON);
 406
 407         dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
 408                  (wtcon & S3C2410_WTCON_ENABLE) ?  "" : "in",
 409                  (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
 410                  (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
 411
 412         return 0;
 413
 414  err_irq:
 415         free_irq(wdt_irq->start, pdev);
 416
 417  err_cpufreq:
 418         s3c2410wdt_cpufreq_deregister();
 419
 420  err_clk:
 421         clk_disable(wdt_clock);
 422         clk_put(wdt_clock);
 423         wdt_clock = NULL;
 424
 425  err_map:
 426         iounmap(wdt_base);
 427
 428  err_req:
 429         release_mem_region(wdt_mem->start, size);
 430
 431  err:
 432         wdt_irq = NULL;
 433         wdt_mem = NULL;
 434         return ret;
 435 }
 436
 437 static int __devexit s3c2410wdt_remove(struct platform_device *dev)
 438 {
 439         watchdog_unregister_device(&s3c2410_wdd);
 440
 441         free_irq(wdt_irq->start, dev);
 442
 443         s3c2410wdt_cpufreq_deregister();
 444
 445         clk_disable(wdt_clock);
 446         clk_put(wdt_clock);
 447         wdt_clock = NULL;
 448
 449         iounmap(wdt_base);
 450
 451         release_mem_region(wdt_mem->start, resource_size(wdt_mem));
 452         wdt_irq = NULL;
 453         wdt_mem = NULL;
 454         return 0;
 455 }
 456
 457 static void s3c2410wdt_shutdown(struct platform_device *dev)
 458 {
 459         s3c2410wdt_stop(&s3c2410_wdd);
 460 }
 461
 462 #ifdef CONFIG_PM
 463
 464 static unsigned long wtcon_save;
 465 static unsigned long wtdat_save;
 466
 467 static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
 468 {
 469         /* Save watchdog state, and turn it off. */
 470         wtcon_save = readl(wdt_base + S3C2410_WTCON);
 471         wtdat_save = readl(wdt_base + S3C2410_WTDAT);
 472
 473         /* Note that WTCNT doesn't need to be saved. */
 474         s3c2410wdt_stop(&s3c2410_wdd);
 475
 476         return 0;
 477 }
 478
 479 static int s3c2410wdt_resume(struct platform_device *dev)
 480 {
 481         /* Restore watchdog state. */
 482
 483         writel(wtdat_save, wdt_base + S3C2410_WTDAT);
 484         writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
 485         writel(wtcon_save, wdt_base + S3C2410_WTCON);
 486
 487         pr_info("watchdog %sabled\n",
 488                 (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
 489
 490         return 0;
 491 }
 492
 493 #else
 494 #define s3c2410wdt_suspend NULL
 495 #define s3c2410wdt_resume  NULL
 496 #endif /* CONFIG_PM */
 497
 498 #ifdef CONFIG_OF
 499 static const struct of_device_id s3c2410_wdt_match[] = {
 500         { .compatible = "samsung,s3c2410-wdt" },
 501         {},
 502 };
 503 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
 504 #else
 505 #define s3c2410_wdt_match NULL
 506 #endif
 507
 508 static struct platform_driver s3c2410wdt_driver = {
 509         .probe          = s3c2410wdt_probe,
 510         .remove         = __devexit_p(s3c2410wdt_remove),
 511         .shutdown       = s3c2410wdt_shutdown,
 512         .suspend        = s3c2410wdt_suspend,
 513         .resume         = s3c2410wdt_resume,
 514         .driver         = {
 515                 .owner  = THIS_MODULE,
 516                 .name   = "s3c2410-wdt",
 517                 .of_match_table = s3c2410_wdt_match,
 518         },
 519 };
 520
 521
 522 static int __init watchdog_init(void)
 523 {
 524         pr_info("S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
 525
 526         return platform_driver_register(&s3c2410wdt_driver);
 527 }
 528
 529 static void __exit watchdog_exit(void)
 530 {
 531         platform_driver_unregister(&s3c2410wdt_driver);
 532 }
 533
 534 module_init(watchdog_init);
 535 module_exit(watchdog_exit);
 536
 537 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
 538               "Dimitry Andric <dimitry.andric@tomtom.com>");
 539 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
 540 MODULE_LICENSE("GPL");
 541 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 542 MODULE_ALIAS("platform:s3c2410-wdt");