drivers/video/sh_mobile_lcdcfb.c

   1 /*
   2  * SuperH Mobile LCDC Framebuffer
   3  *
   4  * Copyright (c) 2008 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/delay.h>
  14 #include <linux/mm.h>
  15 #include <linux/fb.h>
  16 #include <linux/clk.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/ioctl.h>
  23 #include <video/sh_mobile_lcdc.h>
  24 #include <asm/atomic.h>
  25
  26 #define PALETTE_NR 16
  27 #define SIDE_B_OFFSET 0x1000
  28 #define MIRROR_OFFSET 0x2000
  29
  30 /* shared registers */
  31 #define _LDDCKR 0x410
  32 #define _LDDCKSTPR 0x414
  33 #define _LDINTR 0x468
  34 #define _LDSR 0x46c
  35 #define _LDCNT1R 0x470
  36 #define _LDCNT2R 0x474
  37 #define _LDRCNTR 0x478
  38 #define _LDDDSR 0x47c
  39 #define _LDDWD0R 0x800
  40 #define _LDDRDR 0x840
  41 #define _LDDWAR 0x900
  42 #define _LDDRAR 0x904
  43
  44 /* shared registers and their order for context save/restore */
  45 static int lcdc_shared_regs[] = {
  46         _LDDCKR,
  47         _LDDCKSTPR,
  48         _LDINTR,
  49         _LDDDSR,
  50         _LDCNT1R,
  51         _LDCNT2R,
  52 };
  53 #define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
  54
  55 /* per-channel registers */
  56 enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
  57        LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
  58        NR_CH_REGS };
  59
  60 static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
  61         [LDDCKPAT1R] = 0x400,
  62         [LDDCKPAT2R] = 0x404,
  63         [LDMT1R] = 0x418,
  64         [LDMT2R] = 0x41c,
  65         [LDMT3R] = 0x420,
  66         [LDDFR] = 0x424,
  67         [LDSM1R] = 0x428,
  68         [LDSM2R] = 0x42c,
  69         [LDSA1R] = 0x430,
  70         [LDMLSR] = 0x438,
  71         [LDHCNR] = 0x448,
  72         [LDHSYNR] = 0x44c,
  73         [LDVLNR] = 0x450,
  74         [LDVSYNR] = 0x454,
  75         [LDPMR] = 0x460,
  76 };
  77
  78 static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
  79         [LDDCKPAT1R] = 0x408,
  80         [LDDCKPAT2R] = 0x40c,
  81         [LDMT1R] = 0x600,
  82         [LDMT2R] = 0x604,
  83         [LDMT3R] = 0x608,
  84         [LDDFR] = 0x60c,
  85         [LDSM1R] = 0x610,
  86         [LDSM2R] = 0x614,
  87         [LDSA1R] = 0x618,
  88         [LDMLSR] = 0x620,
  89         [LDHCNR] = 0x624,
  90         [LDHSYNR] = 0x628,
  91         [LDVLNR] = 0x62c,
  92         [LDVSYNR] = 0x630,
  93         [LDPMR] = 0x63c,
  94 };
  95
  96 #define START_LCDC      0x00000001
  97 #define LCDC_RESET      0x00000100
  98 #define DISPLAY_BEU     0x00000008
  99 #define LCDC_ENABLE     0x00000001
 100 #define LDINTR_FE       0x00000400
 101 #define LDINTR_VSE      0x00000200
 102 #define LDINTR_VEE      0x00000100
 103 #define LDINTR_FS       0x00000004
 104 #define LDINTR_VSS      0x00000002
 105 #define LDINTR_VES      0x00000001
 106 #define LDRCNTR_SRS     0x00020000
 107 #define LDRCNTR_SRC     0x00010000
 108 #define LDRCNTR_MRS     0x00000002
 109 #define LDRCNTR_MRC     0x00000001
 110 #define LDSR_MRS        0x00000100
 111
 112 struct sh_mobile_lcdc_priv;
 113 struct sh_mobile_lcdc_chan {
 114         struct sh_mobile_lcdc_priv *lcdc;
 115         unsigned long *reg_offs;
 116         unsigned long ldmt1r_value;
 117         unsigned long enabled; /* ME and SE in LDCNT2R */
 118         struct sh_mobile_lcdc_chan_cfg cfg;
 119         u32 pseudo_palette[PALETTE_NR];
 120         unsigned long saved_ch_regs[NR_CH_REGS];
 121         struct fb_info *info;
 122         dma_addr_t dma_handle;
 123         struct fb_deferred_io defio;
 124         struct scatterlist *sglist;
 125         unsigned long frame_end;
 126         unsigned long pan_offset;
 127         wait_queue_head_t frame_end_wait;
 128         struct completion vsync_completion;
 129 };
 130
 131 struct sh_mobile_lcdc_priv {
 132         void __iomem *base;
 133         int irq;
 134         atomic_t hw_usecnt;
 135         struct device *dev;
 136         struct clk *dot_clk;
 137         unsigned long lddckr;
 138         struct sh_mobile_lcdc_chan ch[2];
 139         unsigned long saved_shared_regs[NR_SHARED_REGS];
 140         int started;
 141 };
 142
 143 static bool banked(int reg_nr)
 144 {
 145         switch (reg_nr) {
 146         case LDMT1R:
 147         case LDMT2R:
 148         case LDMT3R:
 149         case LDDFR:
 150         case LDSM1R:
 151         case LDSA1R:
 152         case LDMLSR:
 153         case LDHCNR:
 154         case LDHSYNR:
 155         case LDVLNR:
 156         case LDVSYNR:
 157                 return true;
 158         }
 159         return false;
 160 }
 161
 162 static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
 163                             int reg_nr, unsigned long data)
 164 {
 165         iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
 166         if (banked(reg_nr))
 167                 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
 168                           SIDE_B_OFFSET);
 169 }
 170
 171 static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
 172                             int reg_nr, unsigned long data)
 173 {
 174         iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
 175                   MIRROR_OFFSET);
 176 }
 177
 178 static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
 179                                     int reg_nr)
 180 {
 181         return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
 182 }
 183
 184 static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
 185                        unsigned long reg_offs, unsigned long data)
 186 {
 187         iowrite32(data, priv->base + reg_offs);
 188 }
 189
 190 static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
 191                                unsigned long reg_offs)
 192 {
 193         return ioread32(priv->base + reg_offs);
 194 }
 195
 196 static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
 197                           unsigned long reg_offs,
 198                           unsigned long mask, unsigned long until)
 199 {
 200         while ((lcdc_read(priv, reg_offs) & mask) != until)
 201                 cpu_relax();
 202 }
 203
 204 static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
 205 {
 206         return chan->cfg.chan == LCDC_CHAN_SUBLCD;
 207 }
 208
 209 static void lcdc_sys_write_index(void *handle, unsigned long data)
 210 {
 211         struct sh_mobile_lcdc_chan *ch = handle;
 212
 213         lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
 214         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 215         lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
 216         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 217 }
 218
 219 static void lcdc_sys_write_data(void *handle, unsigned long data)
 220 {
 221         struct sh_mobile_lcdc_chan *ch = handle;
 222
 223         lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
 224         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 225         lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
 226         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 227 }
 228
 229 static unsigned long lcdc_sys_read_data(void *handle)
 230 {
 231         struct sh_mobile_lcdc_chan *ch = handle;
 232
 233         lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
 234         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 235         lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
 236         udelay(1);
 237         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 238
 239         return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
 240 }
 241
 242 struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
 243         lcdc_sys_write_index,
 244         lcdc_sys_write_data,
 245         lcdc_sys_read_data,
 246 };
 247
 248 static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
 249 {
 250         if (atomic_inc_and_test(&priv->hw_usecnt)) {
 251                 pm_runtime_get_sync(priv->dev);
 252                 if (priv->dot_clk)
 253                         clk_enable(priv->dot_clk);
 254         }
 255 }
 256
 257 static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
 258 {
 259         if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
 260                 if (priv->dot_clk)
 261                         clk_disable(priv->dot_clk);
 262                 pm_runtime_put(priv->dev);
 263         }
 264 }
 265
 266 static int sh_mobile_lcdc_sginit(struct fb_info *info,
 267                                   struct list_head *pagelist)
 268 {
 269         struct sh_mobile_lcdc_chan *ch = info->par;
 270         unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
 271         struct page *page;
 272         int nr_pages = 0;
 273
 274         sg_init_table(ch->sglist, nr_pages_max);
 275
 276         list_for_each_entry(page, pagelist, lru)
 277                 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
 278
 279         return nr_pages;
 280 }
 281
 282 static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
 283                                        struct list_head *pagelist)
 284 {
 285         struct sh_mobile_lcdc_chan *ch = info->par;
 286         struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
 287
 288         /* enable clocks before accessing hardware */
 289         sh_mobile_lcdc_clk_on(ch->lcdc);
 290
 291         /*
 292          * It's possible to get here without anything on the pagelist via
 293          * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
 294          * invocation. In the former case, the acceleration routines are
 295          * stepped in to when using the framebuffer console causing the
 296          * workqueue to be scheduled without any dirty pages on the list.
 297          *
 298          * Despite this, a panel update is still needed given that the
 299          * acceleration routines have their own methods for writing in
 300          * that still need to be updated.
 301          *
 302          * The fsync() and empty pagelist case could be optimized for,
 303          * but we don't bother, as any application exhibiting such
 304          * behaviour is fundamentally broken anyways.
 305          */
 306         if (!list_empty(pagelist)) {
 307                 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
 308
 309                 /* trigger panel update */
 310                 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
 311                 if (bcfg->start_transfer)
 312                         bcfg->start_transfer(bcfg->board_data, ch,
 313                                              &sh_mobile_lcdc_sys_bus_ops);
 314                 lcdc_write_chan(ch, LDSM2R, 1);
 315                 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
 316         } else {
 317                 if (bcfg->start_transfer)
 318                         bcfg->start_transfer(bcfg->board_data, ch,
 319                                              &sh_mobile_lcdc_sys_bus_ops);
 320                 lcdc_write_chan(ch, LDSM2R, 1);
 321         }
 322 }
 323
 324 static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
 325 {
 326         struct fb_deferred_io *fbdefio = info->fbdefio;
 327
 328         if (fbdefio)
 329                 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
 330 }
 331
 332 static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
 333 {
 334         struct sh_mobile_lcdc_priv *priv = data;
 335         struct sh_mobile_lcdc_chan *ch;
 336         unsigned long tmp;
 337         unsigned long ldintr;
 338         int is_sub;
 339         int k;
 340
 341         /* acknowledge interrupt */
 342         ldintr = tmp = lcdc_read(priv, _LDINTR);
 343         /*
 344          * disable further VSYNC End IRQs, preserve all other enabled IRQs,
 345          * write 0 to bits 0-6 to ack all triggered IRQs.
 346          */
 347         tmp &= 0xffffff00 & ~LDINTR_VEE;
 348         lcdc_write(priv, _LDINTR, tmp);
 349
 350         /* figure out if this interrupt is for main or sub lcd */
 351         is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
 352
 353         /* wake up channel and disable clocks */
 354         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 355                 ch = &priv->ch[k];
 356
 357                 if (!ch->enabled)
 358                         continue;
 359
 360                 /* Frame Start */
 361                 if (ldintr & LDINTR_FS) {
 362                         if (is_sub == lcdc_chan_is_sublcd(ch)) {
 363                                 ch->frame_end = 1;
 364                                 wake_up(&ch->frame_end_wait);
 365
 366                                 sh_mobile_lcdc_clk_off(priv);
 367                         }
 368                 }
 369
 370                 /* VSYNC End */
 371                 if (ldintr & LDINTR_VES)
 372                         complete(&ch->vsync_completion);
 373         }
 374
 375         return IRQ_HANDLED;
 376 }
 377
 378 static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
 379                                       int start)
 380 {
 381         unsigned long tmp = lcdc_read(priv, _LDCNT2R);
 382         int k;
 383
 384         /* start or stop the lcdc */
 385         if (start)
 386                 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
 387         else
 388                 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
 389
 390         /* wait until power is applied/stopped on all channels */
 391         for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
 392                 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
 393                         while (1) {
 394                                 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
 395                                 if (start && tmp == 3)
 396                                         break;
 397                                 if (!start && tmp == 0)
 398                                         break;
 399                                 cpu_relax();
 400                         }
 401
 402         if (!start)
 403                 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
 404 }
 405
 406 static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
 407 {
 408         struct sh_mobile_lcdc_chan *ch;
 409         struct fb_videomode *lcd_cfg;
 410         struct sh_mobile_lcdc_board_cfg *board_cfg;
 411         unsigned long tmp;
 412         int k, m;
 413         int ret = 0;
 414
 415         /* enable clocks before accessing the hardware */
 416         for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
 417                 if (priv->ch[k].enabled)
 418                         sh_mobile_lcdc_clk_on(priv);
 419
 420         /* reset */
 421         lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
 422         lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
 423
 424         /* enable LCDC channels */
 425         tmp = lcdc_read(priv, _LDCNT2R);
 426         tmp |= priv->ch[0].enabled;
 427         tmp |= priv->ch[1].enabled;
 428         lcdc_write(priv, _LDCNT2R, tmp);
 429
 430         /* read data from external memory, avoid using the BEU for now */
 431         lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
 432
 433         /* stop the lcdc first */
 434         sh_mobile_lcdc_start_stop(priv, 0);
 435
 436         /* configure clocks */
 437         tmp = priv->lddckr;
 438         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 439                 ch = &priv->ch[k];
 440
 441                 if (!priv->ch[k].enabled)
 442                         continue;
 443
 444                 m = ch->cfg.clock_divider;
 445                 if (!m)
 446                         continue;
 447
 448                 if (m == 1)
 449                         m = 1 << 6;
 450                 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
 451
 452                 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
 453                 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
 454         }
 455
 456         lcdc_write(priv, _LDDCKR, tmp);
 457
 458         /* start dotclock again */
 459         lcdc_write(priv, _LDDCKSTPR, 0);
 460         lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
 461
 462         /* interrupts are disabled to begin with */
 463         lcdc_write(priv, _LDINTR, 0);
 464
 465         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 466                 ch = &priv->ch[k];
 467                 lcd_cfg = &ch->cfg.lcd_cfg;
 468
 469                 if (!ch->enabled)
 470                         continue;
 471
 472                 tmp = ch->ldmt1r_value;
 473                 tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
 474                 tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
 475                 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
 476                 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
 477                 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
 478                 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
 479                 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
 480                 lcdc_write_chan(ch, LDMT1R, tmp);
 481
 482                 /* setup SYS bus */
 483                 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
 484                 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
 485
 486                 /* horizontal configuration */
 487                 tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
 488                 tmp += lcd_cfg->left_margin;
 489                 tmp += lcd_cfg->right_margin;
 490                 tmp /= 8; /* HTCN */
 491                 tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
 492                 lcdc_write_chan(ch, LDHCNR, tmp);
 493
 494                 tmp = lcd_cfg->xres;
 495                 tmp += lcd_cfg->right_margin;
 496                 tmp /= 8; /* HSYNP */
 497                 tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
 498                 lcdc_write_chan(ch, LDHSYNR, tmp);
 499
 500                 /* power supply */
 501                 lcdc_write_chan(ch, LDPMR, 0);
 502
 503                 /* vertical configuration */
 504                 tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
 505                 tmp += lcd_cfg->upper_margin;
 506                 tmp += lcd_cfg->lower_margin; /* VTLN */
 507                 tmp |= lcd_cfg->yres << 16; /* VDLN */
 508                 lcdc_write_chan(ch, LDVLNR, tmp);
 509
 510                 tmp = lcd_cfg->yres;
 511                 tmp += lcd_cfg->lower_margin; /* VSYNP */
 512                 tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
 513                 lcdc_write_chan(ch, LDVSYNR, tmp);
 514
 515                 board_cfg = &ch->cfg.board_cfg;
 516                 if (board_cfg->setup_sys)
 517                         ret = board_cfg->setup_sys(board_cfg->board_data, ch,
 518                                                    &sh_mobile_lcdc_sys_bus_ops);
 519                 if (ret)
 520                         return ret;
 521         }
 522
 523         /* word and long word swap */
 524         lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
 525
 526         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 527                 ch = &priv->ch[k];
 528
 529                 if (!priv->ch[k].enabled)
 530                         continue;
 531
 532                 /* set bpp format in PKF[4:0] */
 533                 tmp = lcdc_read_chan(ch, LDDFR);
 534                 tmp &= ~(0x0001001f);
 535                 tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
 536                 lcdc_write_chan(ch, LDDFR, tmp);
 537
 538                 /* point out our frame buffer */
 539                 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
 540
 541                 /* set line size */
 542                 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
 543
 544                 /* setup deferred io if SYS bus */
 545                 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
 546                 if (ch->ldmt1r_value & (1 << 12) && tmp) {
 547                         ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
 548                         ch->defio.delay = msecs_to_jiffies(tmp);
 549                         ch->info->fbdefio = &ch->defio;
 550                         fb_deferred_io_init(ch->info);
 551
 552                         /* one-shot mode */
 553                         lcdc_write_chan(ch, LDSM1R, 1);
 554
 555                         /* enable "Frame End Interrupt Enable" bit */
 556                         lcdc_write(priv, _LDINTR, LDINTR_FE);
 557
 558                 } else {
 559                         /* continuous read mode */
 560                         lcdc_write_chan(ch, LDSM1R, 0);
 561                 }
 562         }
 563
 564         /* display output */
 565         lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
 566
 567         /* start the lcdc */
 568         sh_mobile_lcdc_start_stop(priv, 1);
 569         priv->started = 1;
 570
 571         /* tell the board code to enable the panel */
 572         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 573                 ch = &priv->ch[k];
 574                 if (!ch->enabled)
 575                         continue;
 576
 577                 board_cfg = &ch->cfg.board_cfg;
 578                 if (board_cfg->display_on)
 579                         board_cfg->display_on(board_cfg->board_data);
 580         }
 581
 582         return 0;
 583 }
 584
 585 static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
 586 {
 587         struct sh_mobile_lcdc_chan *ch;
 588         struct sh_mobile_lcdc_board_cfg *board_cfg;
 589         int k;
 590
 591         /* clean up deferred io and ask board code to disable panel */
 592         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 593                 ch = &priv->ch[k];
 594                 if (!ch->enabled)
 595                         continue;
 596
 597                 /* deferred io mode:
 598                  * flush frame, and wait for frame end interrupt
 599                  * clean up deferred io and enable clock
 600                  */
 601                 if (ch->info->fbdefio) {
 602                         ch->frame_end = 0;
 603                         schedule_delayed_work(&ch->info->deferred_work, 0);
 604                         wait_event(ch->frame_end_wait, ch->frame_end);
 605                         fb_deferred_io_cleanup(ch->info);
 606                         ch->info->fbdefio = NULL;
 607                         sh_mobile_lcdc_clk_on(priv);
 608                 }
 609
 610                 board_cfg = &ch->cfg.board_cfg;
 611                 if (board_cfg->display_off)
 612                         board_cfg->display_off(board_cfg->board_data);
 613         }
 614
 615         /* stop the lcdc */
 616         if (priv->started) {
 617                 sh_mobile_lcdc_start_stop(priv, 0);
 618                 priv->started = 0;
 619         }
 620
 621         /* stop clocks */
 622         for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
 623                 if (priv->ch[k].enabled)
 624                         sh_mobile_lcdc_clk_off(priv);
 625 }
 626
 627 static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
 628 {
 629         int ifm, miftyp;
 630
 631         switch (ch->cfg.interface_type) {
 632         case RGB8: ifm = 0; miftyp = 0; break;
 633         case RGB9: ifm = 0; miftyp = 4; break;
 634         case RGB12A: ifm = 0; miftyp = 5; break;
 635         case RGB12B: ifm = 0; miftyp = 6; break;
 636         case RGB16: ifm = 0; miftyp = 7; break;
 637         case RGB18: ifm = 0; miftyp = 10; break;
 638         case RGB24: ifm = 0; miftyp = 11; break;
 639         case SYS8A: ifm = 1; miftyp = 0; break;
 640         case SYS8B: ifm = 1; miftyp = 1; break;
 641         case SYS8C: ifm = 1; miftyp = 2; break;
 642         case SYS8D: ifm = 1; miftyp = 3; break;
 643         case SYS9: ifm = 1; miftyp = 4; break;
 644         case SYS12: ifm = 1; miftyp = 5; break;
 645         case SYS16A: ifm = 1; miftyp = 7; break;
 646         case SYS16B: ifm = 1; miftyp = 8; break;
 647         case SYS16C: ifm = 1; miftyp = 9; break;
 648         case SYS18: ifm = 1; miftyp = 10; break;
 649         case SYS24: ifm = 1; miftyp = 11; break;
 650         default: goto bad;
 651         }
 652
 653         /* SUBLCD only supports SYS interface */
 654         if (lcdc_chan_is_sublcd(ch)) {
 655                 if (ifm == 0)
 656                         goto bad;
 657                 else
 658                         ifm = 0;
 659         }
 660
 661         ch->ldmt1r_value = (ifm << 12) | miftyp;
 662         return 0;
 663  bad:
 664         return -EINVAL;
 665 }
 666
 667 static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
 668                                        int clock_source,
 669                                        struct sh_mobile_lcdc_priv *priv)
 670 {
 671         char *str;
 672         int icksel;
 673
 674         switch (clock_source) {
 675         case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
 676         case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
 677         case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
 678         default:
 679                 return -EINVAL;
 680         }
 681
 682         priv->lddckr = icksel << 16;
 683
 684         if (str) {
 685                 priv->dot_clk = clk_get(&pdev->dev, str);
 686                 if (IS_ERR(priv->dot_clk)) {
 687                         dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
 688                         return PTR_ERR(priv->dot_clk);
 689                 }
 690         }
 691         atomic_set(&priv->hw_usecnt, -1);
 692
 693         /* Runtime PM support involves two step for this driver:
 694          * 1) Enable Runtime PM
 695          * 2) Force Runtime PM Resume since hardware is accessed from probe()
 696          */
 697         pm_runtime_enable(priv->dev);
 698         pm_runtime_resume(priv->dev);
 699         return 0;
 700 }
 701
 702 static int sh_mobile_lcdc_setcolreg(u_int regno,
 703                                     u_int red, u_int green, u_int blue,
 704                                     u_int transp, struct fb_info *info)
 705 {
 706         u32 *palette = info->pseudo_palette;
 707
 708         if (regno >= PALETTE_NR)
 709                 return -EINVAL;
 710
 711         /* only FB_VISUAL_TRUECOLOR supported */
 712
 713         red >>= 16 - info->var.red.length;
 714         green >>= 16 - info->var.green.length;
 715         blue >>= 16 - info->var.blue.length;
 716         transp >>= 16 - info->var.transp.length;
 717
 718         palette[regno] = (red << info->var.red.offset) |
 719           (green << info->var.green.offset) |
 720           (blue << info->var.blue.offset) |
 721           (transp << info->var.transp.offset);
 722
 723         return 0;
 724 }
 725
 726 static struct fb_fix_screeninfo sh_mobile_lcdc_fix  = {
 727         .id =           "SH Mobile LCDC",
 728         .type =         FB_TYPE_PACKED_PIXELS,
 729         .visual =       FB_VISUAL_TRUECOLOR,
 730         .accel =        FB_ACCEL_NONE,
 731         .xpanstep =     0,
 732         .ypanstep =     1,
 733         .ywrapstep =    0,
 734 };
 735
 736 static void sh_mobile_lcdc_fillrect(struct fb_info *info,
 737                                     const struct fb_fillrect *rect)
 738 {
 739         sys_fillrect(info, rect);
 740         sh_mobile_lcdc_deferred_io_touch(info);
 741 }
 742
 743 static void sh_mobile_lcdc_copyarea(struct fb_info *info,
 744                                     const struct fb_copyarea *area)
 745 {
 746         sys_copyarea(info, area);
 747         sh_mobile_lcdc_deferred_io_touch(info);
 748 }
 749
 750 static void sh_mobile_lcdc_imageblit(struct fb_info *info,
 751                                      const struct fb_image *image)
 752 {
 753         sys_imageblit(info, image);
 754         sh_mobile_lcdc_deferred_io_touch(info);
 755 }
 756
 757 static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
 758                                      struct fb_info *info)
 759 {
 760         struct sh_mobile_lcdc_chan *ch = info->par;
 761         struct sh_mobile_lcdc_priv *priv = ch->lcdc;
 762         unsigned long ldrcntr;
 763         unsigned long new_pan_offset;
 764
 765         new_pan_offset = (var->yoffset * info->fix.line_length) +
 766                 (var->xoffset * (info->var.bits_per_pixel / 8));
 767
 768         if (new_pan_offset == ch->pan_offset)
 769                 return 0;       /* No change, do nothing */
 770
 771         ldrcntr = lcdc_read(priv, _LDRCNTR);
 772
 773         /* Set the source address for the next refresh */
 774         lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset);
 775         if (lcdc_chan_is_sublcd(ch))
 776                 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
 777         else
 778                 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
 779
 780         ch->pan_offset = new_pan_offset;
 781
 782         sh_mobile_lcdc_deferred_io_touch(info);
 783
 784         return 0;
 785 }
 786
 787 static int sh_mobile_wait_for_vsync(struct fb_info *info)
 788 {
 789         struct sh_mobile_lcdc_chan *ch = info->par;
 790         unsigned long ldintr;
 791         int ret;
 792
 793         /* Enable VSync End interrupt */
 794         ldintr = lcdc_read(ch->lcdc, _LDINTR);
 795         ldintr |= LDINTR_VEE;
 796         lcdc_write(ch->lcdc, _LDINTR, ldintr);
 797
 798         ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
 799                                                         msecs_to_jiffies(100));
 800         if (!ret)
 801                 return -ETIMEDOUT;
 802
 803         return 0;
 804 }
 805
 806 static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
 807                        unsigned long arg)
 808 {
 809         int retval;
 810
 811         switch (cmd) {
 812         case FBIO_WAITFORVSYNC:
 813                 retval = sh_mobile_wait_for_vsync(info);
 814                 break;
 815
 816         default:
 817                 retval = -ENOIOCTLCMD;
 818                 break;
 819         }
 820         return retval;
 821 }
 822
 823
 824 static struct fb_ops sh_mobile_lcdc_ops = {
 825         .owner          = THIS_MODULE,
 826         .fb_setcolreg   = sh_mobile_lcdc_setcolreg,
 827         .fb_read        = fb_sys_read,
 828         .fb_write       = fb_sys_write,
 829         .fb_fillrect    = sh_mobile_lcdc_fillrect,
 830         .fb_copyarea    = sh_mobile_lcdc_copyarea,
 831         .fb_imageblit   = sh_mobile_lcdc_imageblit,
 832         .fb_pan_display = sh_mobile_fb_pan_display,
 833         .fb_ioctl       = sh_mobile_ioctl,
 834 };
 835
 836 static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
 837 {
 838         switch (bpp) {
 839         case 16: /* PKF[4:0] = 00011 - RGB 565 */
 840                 var->red.offset = 11;
 841                 var->red.length = 5;
 842                 var->green.offset = 5;
 843                 var->green.length = 6;
 844                 var->blue.offset = 0;
 845                 var->blue.length = 5;
 846                 var->transp.offset = 0;
 847                 var->transp.length = 0;
 848                 break;
 849
 850         case 32: /* PKF[4:0] = 00000 - RGB 888
 851                   * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
 852                   * this may be because LDDDSR has word swap enabled..
 853                   */
 854                 var->red.offset = 0;
 855                 var->red.length = 8;
 856                 var->green.offset = 24;
 857                 var->green.length = 8;
 858                 var->blue.offset = 16;
 859                 var->blue.length = 8;
 860                 var->transp.offset = 0;
 861                 var->transp.length = 0;
 862                 break;
 863         default:
 864                 return -EINVAL;
 865         }
 866         var->bits_per_pixel = bpp;
 867         var->red.msb_right = 0;
 868         var->green.msb_right = 0;
 869         var->blue.msb_right = 0;
 870         var->transp.msb_right = 0;
 871         return 0;
 872 }
 873
 874 static int sh_mobile_lcdc_suspend(struct device *dev)
 875 {
 876         struct platform_device *pdev = to_platform_device(dev);
 877
 878         sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
 879         return 0;
 880 }
 881
 882 static int sh_mobile_lcdc_resume(struct device *dev)
 883 {
 884         struct platform_device *pdev = to_platform_device(dev);
 885
 886         return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
 887 }
 888
 889 static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
 890 {
 891         struct platform_device *pdev = to_platform_device(dev);
 892         struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
 893         struct sh_mobile_lcdc_chan *ch;
 894         int k, n;
 895
 896         /* save per-channel registers */
 897         for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
 898                 ch = &p->ch[k];
 899                 if (!ch->enabled)
 900                         continue;
 901                 for (n = 0; n < NR_CH_REGS; n++)
 902                         ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
 903         }
 904
 905         /* save shared registers */
 906         for (n = 0; n < NR_SHARED_REGS; n++)
 907                 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
 908
 909         /* turn off LCDC hardware */
 910         lcdc_write(p, _LDCNT1R, 0);
 911         return 0;
 912 }
 913
 914 static int sh_mobile_lcdc_runtime_resume(struct device *dev)
 915 {
 916         struct platform_device *pdev = to_platform_device(dev);
 917         struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
 918         struct sh_mobile_lcdc_chan *ch;
 919         int k, n;
 920
 921         /* restore per-channel registers */
 922         for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
 923                 ch = &p->ch[k];
 924                 if (!ch->enabled)
 925                         continue;
 926                 for (n = 0; n < NR_CH_REGS; n++)
 927                         lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
 928         }
 929
 930         /* restore shared registers */
 931         for (n = 0; n < NR_SHARED_REGS; n++)
 932                 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
 933
 934         return 0;
 935 }
 936
 937 static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
 938         .suspend = sh_mobile_lcdc_suspend,
 939         .resume = sh_mobile_lcdc_resume,
 940         .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
 941         .runtime_resume = sh_mobile_lcdc_runtime_resume,
 942 };
 943
 944 static int sh_mobile_lcdc_remove(struct platform_device *pdev);
 945
 946 static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
 947 {
 948         struct fb_info *info;
 949         struct sh_mobile_lcdc_priv *priv;
 950         struct sh_mobile_lcdc_info *pdata;
 951         struct sh_mobile_lcdc_chan_cfg *cfg;
 952         struct resource *res;
 953         int error;
 954         void *buf;
 955         int i, j;
 956
 957         if (!pdev->dev.platform_data) {
 958                 dev_err(&pdev->dev, "no platform data defined\n");
 959                 error = -EINVAL;
 960                 goto err0;
 961         }
 962
 963         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 964         i = platform_get_irq(pdev, 0);
 965         if (!res || i < 0) {
 966                 dev_err(&pdev->dev, "cannot get platform resources\n");
 967                 error = -ENOENT;
 968                 goto err0;
 969         }
 970
 971         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 972         if (!priv) {
 973                 dev_err(&pdev->dev, "cannot allocate device data\n");
 974                 error = -ENOMEM;
 975                 goto err0;
 976         }
 977
 978         error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
 979                             dev_name(&pdev->dev), priv);
 980         if (error) {
 981                 dev_err(&pdev->dev, "unable to request irq\n");
 982                 goto err1;
 983         }
 984
 985         priv->irq = i;
 986         priv->dev = &pdev->dev;
 987         platform_set_drvdata(pdev, priv);
 988         pdata = pdev->dev.platform_data;
 989
 990         j = 0;
 991         for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
 992                 priv->ch[j].lcdc = priv;
 993                 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
 994
 995                 error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
 996                 if (error) {
 997                         dev_err(&pdev->dev, "unsupported interface type\n");
 998                         goto err1;
 999                 }
1000                 init_waitqueue_head(&priv->ch[i].frame_end_wait);
1001                 init_completion(&priv->ch[i].vsync_completion);
1002                 priv->ch[j].pan_offset = 0;
1003
1004                 switch (pdata->ch[i].chan) {
1005                 case LCDC_CHAN_MAINLCD:
1006                         priv->ch[j].enabled = 1 << 1;
1007                         priv->ch[j].reg_offs = lcdc_offs_mainlcd;
1008                         j++;
1009                         break;
1010                 case LCDC_CHAN_SUBLCD:
1011                         priv->ch[j].enabled = 1 << 2;
1012                         priv->ch[j].reg_offs = lcdc_offs_sublcd;
1013                         j++;
1014                         break;
1015                 }
1016         }
1017
1018         if (!j) {
1019                 dev_err(&pdev->dev, "no channels defined\n");
1020                 error = -EINVAL;
1021                 goto err1;
1022         }
1023
1024         error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
1025         if (error) {
1026                 dev_err(&pdev->dev, "unable to setup clocks\n");
1027                 goto err1;
1028         }
1029
1030         priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
1031
1032         for (i = 0; i < j; i++) {
1033                 cfg = &priv->ch[i].cfg;
1034
1035                 priv->ch[i].info = framebuffer_alloc(0, &pdev->dev);
1036                 if (!priv->ch[i].info) {
1037                         dev_err(&pdev->dev, "unable to allocate fb_info\n");
1038                         error = -ENOMEM;
1039                         break;
1040                 }
1041
1042                 info = priv->ch[i].info;
1043                 info->fbops = &sh_mobile_lcdc_ops;
1044                 info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
1045                 info->var.yres = cfg->lcd_cfg.yres;
1046                 /* Default Y virtual resolution is 2x panel size */
1047                 info->var.yres_virtual = info->var.yres * 2;
1048                 info->var.width = cfg->lcd_size_cfg.width;
1049                 info->var.height = cfg->lcd_size_cfg.height;
1050                 info->var.activate = FB_ACTIVATE_NOW;
1051                 error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
1052                 if (error)
1053                         break;
1054
1055                 info->fix = sh_mobile_lcdc_fix;
1056                 info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
1057                 info->fix.smem_len = info->fix.line_length *
1058                         info->var.yres_virtual;
1059
1060                 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
1061                                          &priv->ch[i].dma_handle, GFP_KERNEL);
1062                 if (!buf) {
1063                         dev_err(&pdev->dev, "unable to allocate buffer\n");
1064                         error = -ENOMEM;
1065                         break;
1066                 }
1067
1068                 info->pseudo_palette = &priv->ch[i].pseudo_palette;
1069                 info->flags = FBINFO_FLAG_DEFAULT;
1070
1071                 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1072                 if (error < 0) {
1073                         dev_err(&pdev->dev, "unable to allocate cmap\n");
1074                         dma_free_coherent(&pdev->dev, info->fix.smem_len,
1075                                           buf, priv->ch[i].dma_handle);
1076                         break;
1077                 }
1078
1079                 memset(buf, 0, info->fix.smem_len);
1080                 info->fix.smem_start = priv->ch[i].dma_handle;
1081                 info->screen_base = buf;
1082                 info->device = &pdev->dev;
1083                 info->par = &priv->ch[i];
1084         }
1085
1086         if (error)
1087                 goto err1;
1088
1089         error = sh_mobile_lcdc_start(priv);
1090         if (error) {
1091                 dev_err(&pdev->dev, "unable to start hardware\n");
1092                 goto err1;
1093         }
1094
1095         for (i = 0; i < j; i++) {
1096                 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1097
1098                 info = ch->info;
1099
1100                 if (info->fbdefio) {
1101                         priv->ch->sglist = vmalloc(sizeof(struct scatterlist) *
1102                                         info->fix.smem_len >> PAGE_SHIFT);
1103                         if (!priv->ch->sglist) {
1104                                 dev_err(&pdev->dev, "cannot allocate sglist\n");
1105                                 goto err1;
1106                         }
1107                 }
1108
1109                 error = register_framebuffer(info);
1110                 if (error < 0)
1111                         goto err1;
1112
1113                 dev_info(info->dev,
1114                          "registered %s/%s as %dx%d %dbpp.\n",
1115                          pdev->name,
1116                          (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
1117                          "mainlcd" : "sublcd",
1118                          (int) ch->cfg.lcd_cfg.xres,
1119                          (int) ch->cfg.lcd_cfg.yres,
1120                          ch->cfg.bpp);
1121
1122                 /* deferred io mode: disable clock to save power */
1123                 if (info->fbdefio)
1124                         sh_mobile_lcdc_clk_off(priv);
1125         }
1126
1127         return 0;
1128  err1:
1129         sh_mobile_lcdc_remove(pdev);
1130  err0:
1131         return error;
1132 }
1133
1134 static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1135 {
1136         struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1137         struct fb_info *info;
1138         int i;
1139
1140         for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
1141                 if (priv->ch[i].info->dev)
1142                         unregister_framebuffer(priv->ch[i].info);
1143
1144         sh_mobile_lcdc_stop(priv);
1145
1146         for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1147                 info = priv->ch[i].info;
1148
1149                 if (!info || !info->device)
1150                         continue;
1151
1152                 if (priv->ch[i].sglist)
1153                         vfree(priv->ch[i].sglist);
1154
1155                 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1156                                   info->screen_base, priv->ch[i].dma_handle);
1157                 fb_dealloc_cmap(&info->cmap);
1158                 framebuffer_release(info);
1159         }
1160
1161         if (priv->dot_clk)
1162                 clk_put(priv->dot_clk);
1163
1164         pm_runtime_disable(priv->dev);
1165
1166         if (priv->base)
1167                 iounmap(priv->base);
1168
1169         if (priv->irq)
1170                 free_irq(priv->irq, priv);
1171         kfree(priv);
1172         return 0;
1173 }
1174
1175 static struct platform_driver sh_mobile_lcdc_driver = {
1176         .driver         = {
1177                 .name           = "sh_mobile_lcdc_fb",
1178                 .owner          = THIS_MODULE,
1179                 .pm             = &sh_mobile_lcdc_dev_pm_ops,
1180         },
1181         .probe          = sh_mobile_lcdc_probe,
1182         .remove         = sh_mobile_lcdc_remove,
1183 };
1184
1185 static int __init sh_mobile_lcdc_init(void)
1186 {
1187         return platform_driver_register(&sh_mobile_lcdc_driver);
1188 }
1189
1190 static void __exit sh_mobile_lcdc_exit(void)
1191 {
1192         platform_driver_unregister(&sh_mobile_lcdc_driver);
1193 }
1194
1195 module_init(sh_mobile_lcdc_init);
1196 module_exit(sh_mobile_lcdc_exit);
1197
1198 MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1199 MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1200 MODULE_LICENSE("GPL v2");