drivers/usb/phy/phy-msm-usb.c

   1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/extcon.h>
  22 #include <linux/gpio/consumer.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/clk.h>
  25 #include <linux/slab.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/err.h>
  28 #include <linux/delay.h>
  29 #include <linux/io.h>
  30 #include <linux/ioport.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/seq_file.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/of.h>
  36 #include <linux/of_device.h>
  37 #include <linux/reboot.h>
  38 #include <linux/reset.h>
  39 #include <linux/types.h>
  40 #include <linux/usb/otg.h>
  41
  42 #include <linux/usb.h>
  43 #include <linux/usb/otg.h>
  44 #include <linux/usb/of.h>
  45 #include <linux/usb/ulpi.h>
  46 #include <linux/usb/gadget.h>
  47 #include <linux/usb/hcd.h>
  48 #include <linux/usb/msm_hsusb_hw.h>
  49 #include <linux/regulator/consumer.h>
  50
  51 /**
  52  * OTG control
  53  *
  54  * OTG_NO_CONTROL       Id/VBUS notifications not required. Useful in host
  55  *                      only configuration.
  56  * OTG_PHY_CONTROL      Id/VBUS notifications comes form USB PHY.
  57  * OTG_PMIC_CONTROL     Id/VBUS notifications comes from PMIC hardware.
  58  * OTG_USER_CONTROL     Id/VBUS notifcations comes from User via sysfs.
  59  *
  60  */
  61 enum otg_control_type {
  62         OTG_NO_CONTROL = 0,
  63         OTG_PHY_CONTROL,
  64         OTG_PMIC_CONTROL,
  65         OTG_USER_CONTROL,
  66 };
  67
  68 /**
  69  * PHY used in
  70  *
  71  * INVALID_PHY                  Unsupported PHY
  72  * CI_45NM_INTEGRATED_PHY       Chipidea 45nm integrated PHY
  73  * SNPS_28NM_INTEGRATED_PHY     Synopsis 28nm integrated PHY
  74  *
  75  */
  76 enum msm_usb_phy_type {
  77         INVALID_PHY = 0,
  78         CI_45NM_INTEGRATED_PHY,
  79         SNPS_28NM_INTEGRATED_PHY,
  80 };
  81
  82 #define IDEV_CHG_MAX    1500
  83 #define IUNIT           100
  84
  85 /**
  86  * Different states involved in USB charger detection.
  87  *
  88  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  89  *                              process is not yet started.
  90  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  91  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  92  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  93  *                              between SDP and DCP/CDP).
  94  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  95  *                              between DCP and CDP).
  96  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  97  *
  98  */
  99 enum usb_chg_state {
 100         USB_CHG_STATE_UNDEFINED = 0,
 101         USB_CHG_STATE_WAIT_FOR_DCD,
 102         USB_CHG_STATE_DCD_DONE,
 103         USB_CHG_STATE_PRIMARY_DONE,
 104         USB_CHG_STATE_SECONDARY_DONE,
 105         USB_CHG_STATE_DETECTED,
 106 };
 107
 108 /**
 109  * USB charger types
 110  *
 111  * USB_INVALID_CHARGER  Invalid USB charger.
 112  * USB_SDP_CHARGER      Standard downstream port. Refers to a downstream port
 113  *                      on USB2.0 compliant host/hub.
 114  * USB_DCP_CHARGER      Dedicated charger port (AC charger/ Wall charger).
 115  * USB_CDP_CHARGER      Charging downstream port. Enumeration can happen and
 116  *                      IDEV_CHG_MAX can be drawn irrespective of USB state.
 117  *
 118  */
 119 enum usb_chg_type {
 120         USB_INVALID_CHARGER = 0,
 121         USB_SDP_CHARGER,
 122         USB_DCP_CHARGER,
 123         USB_CDP_CHARGER,
 124 };
 125
 126 /**
 127  * struct msm_otg_platform_data - platform device data
 128  *              for msm_otg driver.
 129  * @phy_init_seq: PHY configuration sequence values. Value of -1 is reserved as
 130  *              "do not overwrite default vaule at this address".
 131  * @phy_init_sz: PHY configuration sequence size.
 132  * @vbus_power: VBUS power on/off routine.
 133  * @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
 134  * @mode: Supported mode (OTG/peripheral/host).
 135  * @otg_control: OTG switch controlled by user/Id pin
 136  */
 137 struct msm_otg_platform_data {
 138         int *phy_init_seq;
 139         int phy_init_sz;
 140         void (*vbus_power)(bool on);
 141         unsigned power_budget;
 142         enum usb_dr_mode mode;
 143         enum otg_control_type otg_control;
 144         enum msm_usb_phy_type phy_type;
 145         void (*setup_gpio)(enum usb_otg_state state);
 146 };
 147
 148 /**
 149  * struct msm_otg: OTG driver data. Shared by HCD and DCD.
 150  * @otg: USB OTG Transceiver structure.
 151  * @pdata: otg device platform data.
 152  * @irq: IRQ number assigned for HSUSB controller.
 153  * @clk: clock struct of usb_hs_clk.
 154  * @pclk: clock struct of usb_hs_pclk.
 155  * @core_clk: clock struct of usb_hs_core_clk.
 156  * @regs: ioremapped register base address.
 157  * @inputs: OTG state machine inputs(Id, SessValid etc).
 158  * @sm_work: OTG state machine work.
 159  * @in_lpm: indicates low power mode (LPM) state.
 160  * @async_int: Async interrupt arrived.
 161  * @cur_power: The amount of mA available from downstream port.
 162  * @chg_work: Charger detection work.
 163  * @chg_state: The state of charger detection process.
 164  * @chg_type: The type of charger attached.
 165  * @dcd_retires: The retry count used to track Data contact
 166  *               detection process.
 167  * @manual_pullup: true if VBUS is not routed to USB controller/phy
 168  *      and controller driver therefore enables pull-up explicitly before
 169  *      starting controller using usbcmd run/stop bit.
 170  * @vbus: VBUS signal state trakining, using extcon framework
 171  * @id: ID signal state trakining, using extcon framework
 172  * @switch_gpio: Descriptor for GPIO used to control external Dual
 173  *               SPDT USB Switch.
 174  * @reboot: Used to inform the driver to route USB D+/D- line to Device
 175  *          connector
 176  */
 177 struct msm_otg {
 178         struct usb_phy phy;
 179         struct msm_otg_platform_data *pdata;
 180         int irq;
 181         struct clk *clk;
 182         struct clk *pclk;
 183         struct clk *core_clk;
 184         void __iomem *regs;
 185 #define ID              0
 186 #define B_SESS_VLD      1
 187         unsigned long inputs;
 188         struct work_struct sm_work;
 189         atomic_t in_lpm;
 190         int async_int;
 191         unsigned cur_power;
 192         int phy_number;
 193         struct delayed_work chg_work;
 194         enum usb_chg_state chg_state;
 195         enum usb_chg_type chg_type;
 196         u8 dcd_retries;
 197         struct regulator *v3p3;
 198         struct regulator *v1p8;
 199         struct regulator *vddcx;
 200
 201         struct reset_control *phy_rst;
 202         struct reset_control *link_rst;
 203         int vdd_levels[3];
 204
 205         bool manual_pullup;
 206
 207         struct gpio_desc *switch_gpio;
 208         struct notifier_block reboot;
 209 };
 210
 211 #define MSM_USB_BASE    (motg->regs)
 212 #define DRIVER_NAME     "msm_otg"
 213
 214 #define ULPI_IO_TIMEOUT_USEC    (10 * 1000)
 215 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
 216
 217 #define USB_PHY_3P3_VOL_MIN     3050000 /* uV */
 218 #define USB_PHY_3P3_VOL_MAX     3300000 /* uV */
 219 #define USB_PHY_3P3_HPM_LOAD    50000   /* uA */
 220 #define USB_PHY_3P3_LPM_LOAD    4000    /* uA */
 221
 222 #define USB_PHY_1P8_VOL_MIN     1800000 /* uV */
 223 #define USB_PHY_1P8_VOL_MAX     1800000 /* uV */
 224 #define USB_PHY_1P8_HPM_LOAD    50000   /* uA */
 225 #define USB_PHY_1P8_LPM_LOAD    4000    /* uA */
 226
 227 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
 228 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
 229 #define USB_PHY_SUSP_DIG_VOL    500000  /* uV */
 230
 231 enum vdd_levels {
 232         VDD_LEVEL_NONE = 0,
 233         VDD_LEVEL_MIN,
 234         VDD_LEVEL_MAX,
 235 };
 236
 237 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
 238 {
 239         int ret = 0;
 240
 241         if (init) {
 242                 ret = regulator_set_voltage(motg->vddcx,
 243                                 motg->vdd_levels[VDD_LEVEL_MIN],
 244                                 motg->vdd_levels[VDD_LEVEL_MAX]);
 245                 if (ret) {
 246                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
 247                         return ret;
 248                 }
 249
 250                 ret = regulator_enable(motg->vddcx);
 251                 if (ret)
 252                         dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
 253         } else {
 254                 ret = regulator_set_voltage(motg->vddcx, 0,
 255                                 motg->vdd_levels[VDD_LEVEL_MAX]);
 256                 if (ret)
 257                         dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
 258                 ret = regulator_disable(motg->vddcx);
 259                 if (ret)
 260                         dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
 261         }
 262
 263         return ret;
 264 }
 265
 266 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
 267 {
 268         int rc = 0;
 269
 270         if (init) {
 271                 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
 272                                 USB_PHY_3P3_VOL_MAX);
 273                 if (rc) {
 274                         dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
 275                         goto exit;
 276                 }
 277                 rc = regulator_enable(motg->v3p3);
 278                 if (rc) {
 279                         dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
 280                         goto exit;
 281                 }
 282                 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
 283                                 USB_PHY_1P8_VOL_MAX);
 284                 if (rc) {
 285                         dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
 286                         goto disable_3p3;
 287                 }
 288                 rc = regulator_enable(motg->v1p8);
 289                 if (rc) {
 290                         dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
 291                         goto disable_3p3;
 292                 }
 293
 294                 return 0;
 295         }
 296
 297         regulator_disable(motg->v1p8);
 298 disable_3p3:
 299         regulator_disable(motg->v3p3);
 300 exit:
 301         return rc;
 302 }
 303
 304 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
 305 {
 306         int ret = 0;
 307
 308         if (on) {
 309                 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_HPM_LOAD);
 310                 if (ret < 0) {
 311                         pr_err("Could not set HPM for v1p8\n");
 312                         return ret;
 313                 }
 314                 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_HPM_LOAD);
 315                 if (ret < 0) {
 316                         pr_err("Could not set HPM for v3p3\n");
 317                         regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
 318                         return ret;
 319                 }
 320         } else {
 321                 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
 322                 if (ret < 0)
 323                         pr_err("Could not set LPM for v1p8\n");
 324                 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_LPM_LOAD);
 325                 if (ret < 0)
 326                         pr_err("Could not set LPM for v3p3\n");
 327         }
 328
 329         pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
 330         return ret < 0 ? ret : 0;
 331 }
 332
 333 static int ulpi_read(struct usb_phy *phy, u32 reg)
 334 {
 335         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 336         int cnt = 0;
 337
 338         /* initiate read operation */
 339         writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
 340                USB_ULPI_VIEWPORT);
 341
 342         /* wait for completion */
 343         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 344                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 345                         break;
 346                 udelay(1);
 347                 cnt++;
 348         }
 349
 350         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 351                 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
 352                         readl(USB_ULPI_VIEWPORT));
 353                 return -ETIMEDOUT;
 354         }
 355         return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
 356 }
 357
 358 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
 359 {
 360         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 361         int cnt = 0;
 362
 363         /* initiate write operation */
 364         writel(ULPI_RUN | ULPI_WRITE |
 365                ULPI_ADDR(reg) | ULPI_DATA(val),
 366                USB_ULPI_VIEWPORT);
 367
 368         /* wait for completion */
 369         while (cnt < ULPI_IO_TIMEOUT_USEC) {
 370                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
 371                         break;
 372                 udelay(1);
 373                 cnt++;
 374         }
 375
 376         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
 377                 dev_err(phy->dev, "ulpi_write: timeout\n");
 378                 return -ETIMEDOUT;
 379         }
 380         return 0;
 381 }
 382
 383 static struct usb_phy_io_ops msm_otg_io_ops = {
 384         .read = ulpi_read,
 385         .write = ulpi_write,
 386 };
 387
 388 static void ulpi_init(struct msm_otg *motg)
 389 {
 390         struct msm_otg_platform_data *pdata = motg->pdata;
 391         int *seq = pdata->phy_init_seq, idx;
 392         u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
 393
 394         for (idx = 0; idx < pdata->phy_init_sz; idx++) {
 395                 if (seq[idx] == -1)
 396                         continue;
 397
 398                 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
 399                                 seq[idx], addr + idx);
 400                 ulpi_write(&motg->phy, seq[idx], addr + idx);
 401         }
 402 }
 403
 404 static int msm_phy_notify_disconnect(struct usb_phy *phy,
 405                                    enum usb_device_speed speed)
 406 {
 407         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 408         int val;
 409
 410         if (motg->manual_pullup) {
 411                 val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL;
 412                 usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A));
 413         }
 414
 415         /*
 416          * Put the transceiver in non-driving mode. Otherwise host
 417          * may not detect soft-disconnection.
 418          */
 419         val = ulpi_read(phy, ULPI_FUNC_CTRL);
 420         val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 421         val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
 422         ulpi_write(phy, val, ULPI_FUNC_CTRL);
 423
 424         return 0;
 425 }
 426
 427 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 428 {
 429         int ret;
 430
 431         if (assert)
 432                 ret = reset_control_assert(motg->link_rst);
 433         else
 434                 ret = reset_control_deassert(motg->link_rst);
 435
 436         if (ret)
 437                 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
 438                         assert ? "assert" : "deassert");
 439
 440         return ret;
 441 }
 442
 443 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
 444 {
 445         int ret = 0;
 446
 447         if (motg->phy_rst)
 448                 ret = reset_control_reset(motg->phy_rst);
 449
 450         if (ret)
 451                 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
 452
 453         return ret;
 454 }
 455
 456 static int msm_link_reset(struct msm_otg *motg)
 457 {
 458         u32 val;
 459         int ret;
 460
 461         ret = msm_otg_link_clk_reset(motg, 1);
 462         if (ret)
 463                 return ret;
 464
 465         /* wait for 1ms delay as suggested in HPG. */
 466         usleep_range(1000, 1200);
 467
 468         ret = msm_otg_link_clk_reset(motg, 0);
 469         if (ret)
 470                 return ret;
 471
 472         if (motg->phy_number)
 473                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 474
 475         /* put transceiver in serial mode as part of reset */
 476         val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
 477         writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
 478
 479         return 0;
 480 }
 481
 482 static int msm_otg_reset(struct usb_phy *phy)
 483 {
 484         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 485         int cnt = 0;
 486
 487         writel(USBCMD_RESET, USB_USBCMD);
 488         while (cnt < LINK_RESET_TIMEOUT_USEC) {
 489                 if (!(readl(USB_USBCMD) & USBCMD_RESET))
 490                         break;
 491                 udelay(1);
 492                 cnt++;
 493         }
 494         if (cnt >= LINK_RESET_TIMEOUT_USEC)
 495                 return -ETIMEDOUT;
 496
 497         /* select ULPI phy and clear other status/control bits in PORTSC */
 498         writel(PORTSC_PTS_ULPI, USB_PORTSC);
 499
 500         writel(0x0, USB_AHBBURST);
 501         writel(0x08, USB_AHBMODE);
 502
 503         if (motg->phy_number)
 504                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 505         return 0;
 506 }
 507
 508 static void msm_phy_reset(struct msm_otg *motg)
 509 {
 510         void __iomem *addr;
 511
 512         if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
 513                 msm_otg_phy_clk_reset(motg);
 514                 return;
 515         }
 516
 517         addr = USB_PHY_CTRL;
 518         if (motg->phy_number)
 519                 addr = USB_PHY_CTRL2;
 520
 521         /* Assert USB PHY_POR */
 522         writel(readl(addr) | PHY_POR_ASSERT, addr);
 523
 524         /*
 525          * wait for minimum 10 microseconds as suggested in HPG.
 526          * Use a slightly larger value since the exact value didn't
 527          * work 100% of the time.
 528          */
 529         udelay(12);
 530
 531         /* Deassert USB PHY_POR */
 532         writel(readl(addr) & ~PHY_POR_ASSERT, addr);
 533 }
 534
 535 static int msm_usb_reset(struct usb_phy *phy)
 536 {
 537         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 538         int ret;
 539
 540         if (!IS_ERR(motg->core_clk))
 541                 clk_prepare_enable(motg->core_clk);
 542
 543         ret = msm_link_reset(motg);
 544         if (ret) {
 545                 dev_err(phy->dev, "phy_reset failed\n");
 546                 return ret;
 547         }
 548
 549         ret = msm_otg_reset(&motg->phy);
 550         if (ret) {
 551                 dev_err(phy->dev, "link reset failed\n");
 552                 return ret;
 553         }
 554
 555         msleep(100);
 556
 557         /* Reset USB PHY after performing USB Link RESET */
 558         msm_phy_reset(motg);
 559
 560         if (!IS_ERR(motg->core_clk))
 561                 clk_disable_unprepare(motg->core_clk);
 562
 563         return 0;
 564 }
 565
 566 static int msm_phy_init(struct usb_phy *phy)
 567 {
 568         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 569         struct msm_otg_platform_data *pdata = motg->pdata;
 570         u32 val, ulpi_val = 0;
 571
 572         /* Program USB PHY Override registers. */
 573         ulpi_init(motg);
 574
 575         /*
 576          * It is recommended in HPG to reset USB PHY after programming
 577          * USB PHY Override registers.
 578          */
 579         msm_phy_reset(motg);
 580
 581         if (pdata->otg_control == OTG_PHY_CONTROL) {
 582                 val = readl(USB_OTGSC);
 583                 if (pdata->mode == USB_DR_MODE_OTG) {
 584                         ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
 585                         val |= OTGSC_IDIE | OTGSC_BSVIE;
 586                 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
 587                         ulpi_val = ULPI_INT_SESS_VALID;
 588                         val |= OTGSC_BSVIE;
 589                 }
 590                 writel(val, USB_OTGSC);
 591                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
 592                 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
 593         }
 594
 595         if (motg->manual_pullup) {
 596                 val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT;
 597                 ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A));
 598
 599                 val = readl(USB_GENCONFIG_2);
 600                 val |= GENCONFIG_2_SESS_VLD_CTRL_EN;
 601                 writel(val, USB_GENCONFIG_2);
 602
 603                 val = readl(USB_USBCMD);
 604                 val |= USBCMD_SESS_VLD_CTRL;
 605                 writel(val, USB_USBCMD);
 606
 607                 val = ulpi_read(phy, ULPI_FUNC_CTRL);
 608                 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
 609                 val |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
 610                 ulpi_write(phy, val, ULPI_FUNC_CTRL);
 611         }
 612
 613         if (motg->phy_number)
 614                 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
 615
 616         return 0;
 617 }
 618
 619 #define PHY_SUSPEND_TIMEOUT_USEC        (500 * 1000)
 620 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
 621
 622 #ifdef CONFIG_PM
 623
 624 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
 625 {
 626         int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
 627         int min_vol;
 628         int ret;
 629
 630         if (high)
 631                 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
 632         else
 633                 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
 634
 635         ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
 636         if (ret) {
 637                 pr_err("Cannot set vddcx voltage\n");
 638                 return ret;
 639         }
 640
 641         pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
 642
 643         return ret;
 644 }
 645
 646 static int msm_otg_suspend(struct msm_otg *motg)
 647 {
 648         struct usb_phy *phy = &motg->phy;
 649         struct usb_bus *bus = phy->otg->host;
 650         struct msm_otg_platform_data *pdata = motg->pdata;
 651         void __iomem *addr;
 652         int cnt = 0;
 653
 654         if (atomic_read(&motg->in_lpm))
 655                 return 0;
 656
 657         disable_irq(motg->irq);
 658         /*
 659          * Chipidea 45-nm PHY suspend sequence:
 660          *
 661          * Interrupt Latch Register auto-clear feature is not present
 662          * in all PHY versions. Latch register is clear on read type.
 663          * Clear latch register to avoid spurious wakeup from
 664          * low power mode (LPM).
 665          *
 666          * PHY comparators are disabled when PHY enters into low power
 667          * mode (LPM). Keep PHY comparators ON in LPM only when we expect
 668          * VBUS/Id notifications from USB PHY. Otherwise turn off USB
 669          * PHY comparators. This save significant amount of power.
 670          *
 671          * PLL is not turned off when PHY enters into low power mode (LPM).
 672          * Disable PLL for maximum power savings.
 673          */
 674
 675         if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
 676                 ulpi_read(phy, 0x14);
 677                 if (pdata->otg_control == OTG_PHY_CONTROL)
 678                         ulpi_write(phy, 0x01, 0x30);
 679                 ulpi_write(phy, 0x08, 0x09);
 680         }
 681
 682         /*
 683          * PHY may take some time or even fail to enter into low power
 684          * mode (LPM). Hence poll for 500 msec and reset the PHY and link
 685          * in failure case.
 686          */
 687         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
 688         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
 689                 if (readl(USB_PORTSC) & PORTSC_PHCD)
 690                         break;
 691                 udelay(1);
 692                 cnt++;
 693         }
 694
 695         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
 696                 dev_err(phy->dev, "Unable to suspend PHY\n");
 697                 msm_otg_reset(phy);
 698                 enable_irq(motg->irq);
 699                 return -ETIMEDOUT;
 700         }
 701
 702         /*
 703          * PHY has capability to generate interrupt asynchronously in low
 704          * power mode (LPM). This interrupt is level triggered. So USB IRQ
 705          * line must be disabled till async interrupt enable bit is cleared
 706          * in USBCMD register. Assert STP (ULPI interface STOP signal) to
 707          * block data communication from PHY.
 708          */
 709         writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
 710
 711         addr = USB_PHY_CTRL;
 712         if (motg->phy_number)
 713                 addr = USB_PHY_CTRL2;
 714
 715         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 716                         motg->pdata->otg_control == OTG_PMIC_CONTROL)
 717                 writel(readl(addr) | PHY_RETEN, addr);
 718
 719         clk_disable_unprepare(motg->pclk);
 720         clk_disable_unprepare(motg->clk);
 721         if (!IS_ERR(motg->core_clk))
 722                 clk_disable_unprepare(motg->core_clk);
 723
 724         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 725                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 726                 msm_hsusb_ldo_set_mode(motg, 0);
 727                 msm_hsusb_config_vddcx(motg, 0);
 728         }
 729
 730         if (device_may_wakeup(phy->dev))
 731                 enable_irq_wake(motg->irq);
 732         if (bus)
 733                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 734
 735         atomic_set(&motg->in_lpm, 1);
 736         enable_irq(motg->irq);
 737
 738         dev_info(phy->dev, "USB in low power mode\n");
 739
 740         return 0;
 741 }
 742
 743 static int msm_otg_resume(struct msm_otg *motg)
 744 {
 745         struct usb_phy *phy = &motg->phy;
 746         struct usb_bus *bus = phy->otg->host;
 747         void __iomem *addr;
 748         int cnt = 0;
 749         unsigned temp;
 750
 751         if (!atomic_read(&motg->in_lpm))
 752                 return 0;
 753
 754         clk_prepare_enable(motg->pclk);
 755         clk_prepare_enable(motg->clk);
 756         if (!IS_ERR(motg->core_clk))
 757                 clk_prepare_enable(motg->core_clk);
 758
 759         if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
 760                         motg->pdata->otg_control == OTG_PMIC_CONTROL) {
 761
 762                 addr = USB_PHY_CTRL;
 763                 if (motg->phy_number)
 764                         addr = USB_PHY_CTRL2;
 765
 766                 msm_hsusb_ldo_set_mode(motg, 1);
 767                 msm_hsusb_config_vddcx(motg, 1);
 768                 writel(readl(addr) & ~PHY_RETEN, addr);
 769         }
 770
 771         temp = readl(USB_USBCMD);
 772         temp &= ~ASYNC_INTR_CTRL;
 773         temp &= ~ULPI_STP_CTRL;
 774         writel(temp, USB_USBCMD);
 775
 776         /*
 777          * PHY comes out of low power mode (LPM) in case of wakeup
 778          * from asynchronous interrupt.
 779          */
 780         if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 781                 goto skip_phy_resume;
 782
 783         writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
 784         while (cnt < PHY_RESUME_TIMEOUT_USEC) {
 785                 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 786                         break;
 787                 udelay(1);
 788                 cnt++;
 789         }
 790
 791         if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
 792                 /*
 793                  * This is a fatal error. Reset the link and
 794                  * PHY. USB state can not be restored. Re-insertion
 795                  * of USB cable is the only way to get USB working.
 796                  */
 797                 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
 798                 msm_otg_reset(phy);
 799         }
 800
 801 skip_phy_resume:
 802         if (device_may_wakeup(phy->dev))
 803                 disable_irq_wake(motg->irq);
 804         if (bus)
 805                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 806
 807         atomic_set(&motg->in_lpm, 0);
 808
 809         if (motg->async_int) {
 810                 motg->async_int = 0;
 811                 pm_runtime_put(phy->dev);
 812                 enable_irq(motg->irq);
 813         }
 814
 815         dev_info(phy->dev, "USB exited from low power mode\n");
 816
 817         return 0;
 818 }
 819 #endif
 820
 821 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
 822 {
 823         if (motg->cur_power == mA)
 824                 return;
 825
 826         /* TODO: Notify PMIC about available current */
 827         dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
 828         motg->cur_power = mA;
 829 }
 830
 831 static void msm_otg_start_host(struct usb_phy *phy, int on)
 832 {
 833         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 834         struct msm_otg_platform_data *pdata = motg->pdata;
 835         struct usb_hcd *hcd;
 836
 837         if (!phy->otg->host)
 838                 return;
 839
 840         hcd = bus_to_hcd(phy->otg->host);
 841
 842         if (on) {
 843                 dev_dbg(phy->dev, "host on\n");
 844
 845                 if (pdata->vbus_power)
 846                         pdata->vbus_power(1);
 847                 /*
 848                  * Some boards have a switch cotrolled by gpio
 849                  * to enable/disable internal HUB. Enable internal
 850                  * HUB before kicking the host.
 851                  */
 852                 if (pdata->setup_gpio)
 853                         pdata->setup_gpio(OTG_STATE_A_HOST);
 854 #ifdef CONFIG_USB
 855                 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 856                 device_wakeup_enable(hcd->self.controller);
 857 #endif
 858         } else {
 859                 dev_dbg(phy->dev, "host off\n");
 860
 861 #ifdef CONFIG_USB
 862                 usb_remove_hcd(hcd);
 863 #endif
 864                 if (pdata->setup_gpio)
 865                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 866                 if (pdata->vbus_power)
 867                         pdata->vbus_power(0);
 868         }
 869 }
 870
 871 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
 872 {
 873         struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
 874         struct usb_hcd *hcd;
 875
 876         /*
 877          * Fail host registration if this board can support
 878          * only peripheral configuration.
 879          */
 880         if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
 881                 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
 882                 return -ENODEV;
 883         }
 884
 885         if (!host) {
 886                 if (otg->state == OTG_STATE_A_HOST) {
 887                         pm_runtime_get_sync(otg->usb_phy->dev);
 888                         msm_otg_start_host(otg->usb_phy, 0);
 889                         otg->host = NULL;
 890                         otg->state = OTG_STATE_UNDEFINED;
 891                         schedule_work(&motg->sm_work);
 892                 } else {
 893                         otg->host = NULL;
 894                 }
 895
 896                 return 0;
 897         }
 898
 899         hcd = bus_to_hcd(host);
 900         hcd->power_budget = motg->pdata->power_budget;
 901
 902         otg->host = host;
 903         dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
 904
 905         pm_runtime_get_sync(otg->usb_phy->dev);
 906         schedule_work(&motg->sm_work);
 907
 908         return 0;
 909 }
 910
 911 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
 912 {
 913         struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
 914         struct msm_otg_platform_data *pdata = motg->pdata;
 915
 916         if (!phy->otg->gadget)
 917                 return;
 918
 919         if (on) {
 920                 dev_dbg(phy->dev, "gadget on\n");
 921                 /*
 922                  * Some boards have a switch cotrolled by gpio
 923                  * to enable/disable internal HUB. Disable internal
 924                  * HUB before kicking the gadget.
 925                  */
 926                 if (pdata->setup_gpio)
 927                         pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
 928                 usb_gadget_vbus_connect(phy->otg->gadget);
 929         } else {
 930                 dev_dbg(phy->dev, "gadget off\n");
 931                 usb_gadget_vbus_disconnect(phy->otg->gadget);
 932                 if (pdata->setup_gpio)
 933                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 934         }
 935
 936 }
 937
 938 static int msm_otg_set_peripheral(struct usb_otg *otg,
 939                                         struct usb_gadget *gadget)
 940 {
 941         struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
 942
 943         /*
 944          * Fail peripheral registration if this board can support
 945          * only host configuration.
 946          */
 947         if (motg->pdata->mode == USB_DR_MODE_HOST) {
 948                 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
 949                 return -ENODEV;
 950         }
 951
 952         if (!gadget) {
 953                 if (otg->state == OTG_STATE_B_PERIPHERAL) {
 954                         pm_runtime_get_sync(otg->usb_phy->dev);
 955                         msm_otg_start_peripheral(otg->usb_phy, 0);
 956                         otg->gadget = NULL;
 957                         otg->state = OTG_STATE_UNDEFINED;
 958                         schedule_work(&motg->sm_work);
 959                 } else {
 960                         otg->gadget = NULL;
 961                 }
 962
 963                 return 0;
 964         }
 965         otg->gadget = gadget;
 966         dev_dbg(otg->usb_phy->dev,
 967                 "peripheral driver registered w/ tranceiver\n");
 968
 969         pm_runtime_get_sync(otg->usb_phy->dev);
 970         schedule_work(&motg->sm_work);
 971
 972         return 0;
 973 }
 974
 975 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
 976 {
 977         struct usb_phy *phy = &motg->phy;
 978         u32 chg_det;
 979         bool ret = false;
 980
 981         switch (motg->pdata->phy_type) {
 982         case CI_45NM_INTEGRATED_PHY:
 983                 chg_det = ulpi_read(phy, 0x34);
 984                 ret = chg_det & (1 << 4);
 985                 break;
 986         case SNPS_28NM_INTEGRATED_PHY:
 987                 chg_det = ulpi_read(phy, 0x87);
 988                 ret = chg_det & 1;
 989                 break;
 990         default:
 991                 break;
 992         }
 993         return ret;
 994 }
 995
 996 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
 997 {
 998         struct usb_phy *phy = &motg->phy;
 999         u32 chg_det;
1000
1001         switch (motg->pdata->phy_type) {
1002         case CI_45NM_INTEGRATED_PHY:
1003                 chg_det = ulpi_read(phy, 0x34);
1004                 /* Turn off charger block */
1005                 chg_det |= ~(1 << 1);
1006                 ulpi_write(phy, chg_det, 0x34);
1007                 udelay(20);
1008                 /* control chg block via ULPI */
1009                 chg_det &= ~(1 << 3);
1010                 ulpi_write(phy, chg_det, 0x34);
1011                 /* put it in host mode for enabling D- source */
1012                 chg_det &= ~(1 << 2);
1013                 ulpi_write(phy, chg_det, 0x34);
1014                 /* Turn on chg detect block */
1015                 chg_det &= ~(1 << 1);
1016                 ulpi_write(phy, chg_det, 0x34);
1017                 udelay(20);
1018                 /* enable chg detection */
1019                 chg_det &= ~(1 << 0);
1020                 ulpi_write(phy, chg_det, 0x34);
1021                 break;
1022         case SNPS_28NM_INTEGRATED_PHY:
1023                 /*
1024                  * Configure DM as current source, DP as current sink
1025                  * and enable battery charging comparators.
1026                  */
1027                 ulpi_write(phy, 0x8, 0x85);
1028                 ulpi_write(phy, 0x2, 0x85);
1029                 ulpi_write(phy, 0x1, 0x85);
1030                 break;
1031         default:
1032                 break;
1033         }
1034 }
1035
1036 static bool msm_chg_check_primary_det(struct msm_otg *motg)
1037 {
1038         struct usb_phy *phy = &motg->phy;
1039         u32 chg_det;
1040         bool ret = false;
1041
1042         switch (motg->pdata->phy_type) {
1043         case CI_45NM_INTEGRATED_PHY:
1044                 chg_det = ulpi_read(phy, 0x34);
1045                 ret = chg_det & (1 << 4);
1046                 break;
1047         case SNPS_28NM_INTEGRATED_PHY:
1048                 chg_det = ulpi_read(phy, 0x87);
1049                 ret = chg_det & 1;
1050                 break;
1051         default:
1052                 break;
1053         }
1054         return ret;
1055 }
1056
1057 static void msm_chg_enable_primary_det(struct msm_otg *motg)
1058 {
1059         struct usb_phy *phy = &motg->phy;
1060         u32 chg_det;
1061
1062         switch (motg->pdata->phy_type) {
1063         case CI_45NM_INTEGRATED_PHY:
1064                 chg_det = ulpi_read(phy, 0x34);
1065                 /* enable chg detection */
1066                 chg_det &= ~(1 << 0);
1067                 ulpi_write(phy, chg_det, 0x34);
1068                 break;
1069         case SNPS_28NM_INTEGRATED_PHY:
1070                 /*
1071                  * Configure DP as current source, DM as current sink
1072                  * and enable battery charging comparators.
1073                  */
1074                 ulpi_write(phy, 0x2, 0x85);
1075                 ulpi_write(phy, 0x1, 0x85);
1076                 break;
1077         default:
1078                 break;
1079         }
1080 }
1081
1082 static bool msm_chg_check_dcd(struct msm_otg *motg)
1083 {
1084         struct usb_phy *phy = &motg->phy;
1085         u32 line_state;
1086         bool ret = false;
1087
1088         switch (motg->pdata->phy_type) {
1089         case CI_45NM_INTEGRATED_PHY:
1090                 line_state = ulpi_read(phy, 0x15);
1091                 ret = !(line_state & 1);
1092                 break;
1093         case SNPS_28NM_INTEGRATED_PHY:
1094                 line_state = ulpi_read(phy, 0x87);
1095                 ret = line_state & 2;
1096                 break;
1097         default:
1098                 break;
1099         }
1100         return ret;
1101 }
1102
1103 static void msm_chg_disable_dcd(struct msm_otg *motg)
1104 {
1105         struct usb_phy *phy = &motg->phy;
1106         u32 chg_det;
1107
1108         switch (motg->pdata->phy_type) {
1109         case CI_45NM_INTEGRATED_PHY:
1110                 chg_det = ulpi_read(phy, 0x34);
1111                 chg_det &= ~(1 << 5);
1112                 ulpi_write(phy, chg_det, 0x34);
1113                 break;
1114         case SNPS_28NM_INTEGRATED_PHY:
1115                 ulpi_write(phy, 0x10, 0x86);
1116                 break;
1117         default:
1118                 break;
1119         }
1120 }
1121
1122 static void msm_chg_enable_dcd(struct msm_otg *motg)
1123 {
1124         struct usb_phy *phy = &motg->phy;
1125         u32 chg_det;
1126
1127         switch (motg->pdata->phy_type) {
1128         case CI_45NM_INTEGRATED_PHY:
1129                 chg_det = ulpi_read(phy, 0x34);
1130                 /* Turn on D+ current source */
1131                 chg_det |= (1 << 5);
1132                 ulpi_write(phy, chg_det, 0x34);
1133                 break;
1134         case SNPS_28NM_INTEGRATED_PHY:
1135                 /* Data contact detection enable */
1136                 ulpi_write(phy, 0x10, 0x85);
1137                 break;
1138         default:
1139                 break;
1140         }
1141 }
1142
1143 static void msm_chg_block_on(struct msm_otg *motg)
1144 {
1145         struct usb_phy *phy = &motg->phy;
1146         u32 func_ctrl, chg_det;
1147
1148         /* put the controller in non-driving mode */
1149         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1150         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1151         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
1152         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1153
1154         switch (motg->pdata->phy_type) {
1155         case CI_45NM_INTEGRATED_PHY:
1156                 chg_det = ulpi_read(phy, 0x34);
1157                 /* control chg block via ULPI */
1158                 chg_det &= ~(1 << 3);
1159                 ulpi_write(phy, chg_det, 0x34);
1160                 /* Turn on chg detect block */
1161                 chg_det &= ~(1 << 1);
1162                 ulpi_write(phy, chg_det, 0x34);
1163                 udelay(20);
1164                 break;
1165         case SNPS_28NM_INTEGRATED_PHY:
1166                 /* Clear charger detecting control bits */
1167                 ulpi_write(phy, 0x3F, 0x86);
1168                 /* Clear alt interrupt latch and enable bits */
1169                 ulpi_write(phy, 0x1F, 0x92);
1170                 ulpi_write(phy, 0x1F, 0x95);
1171                 udelay(100);
1172                 break;
1173         default:
1174                 break;
1175         }
1176 }
1177
1178 static void msm_chg_block_off(struct msm_otg *motg)
1179 {
1180         struct usb_phy *phy = &motg->phy;
1181         u32 func_ctrl, chg_det;
1182
1183         switch (motg->pdata->phy_type) {
1184         case CI_45NM_INTEGRATED_PHY:
1185                 chg_det = ulpi_read(phy, 0x34);
1186                 /* Turn off charger block */
1187                 chg_det |= ~(1 << 1);
1188                 ulpi_write(phy, chg_det, 0x34);
1189                 break;
1190         case SNPS_28NM_INTEGRATED_PHY:
1191                 /* Clear charger detecting control bits */
1192                 ulpi_write(phy, 0x3F, 0x86);
1193                 /* Clear alt interrupt latch and enable bits */
1194                 ulpi_write(phy, 0x1F, 0x92);
1195                 ulpi_write(phy, 0x1F, 0x95);
1196                 break;
1197         default:
1198                 break;
1199         }
1200
1201         /* put the controller in normal mode */
1202         func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1203         func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1204         func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1205         ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1206 }
1207
1208 #define MSM_CHG_DCD_POLL_TIME           (100 * HZ/1000) /* 100 msec */
1209 #define MSM_CHG_DCD_MAX_RETRIES         6 /* Tdcd_tmout = 6 * 100 msec */
1210 #define MSM_CHG_PRIMARY_DET_TIME        (40 * HZ/1000) /* TVDPSRC_ON */
1211 #define MSM_CHG_SECONDARY_DET_TIME      (40 * HZ/1000) /* TVDMSRC_ON */
1212 static void msm_chg_detect_work(struct work_struct *w)
1213 {
1214         struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1215         struct usb_phy *phy = &motg->phy;
1216         bool is_dcd, tmout, vout;
1217         unsigned long delay;
1218
1219         dev_dbg(phy->dev, "chg detection work\n");
1220         switch (motg->chg_state) {
1221         case USB_CHG_STATE_UNDEFINED:
1222                 pm_runtime_get_sync(phy->dev);
1223                 msm_chg_block_on(motg);
1224                 msm_chg_enable_dcd(motg);
1225                 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1226                 motg->dcd_retries = 0;
1227                 delay = MSM_CHG_DCD_POLL_TIME;
1228                 break;
1229         case USB_CHG_STATE_WAIT_FOR_DCD:
1230                 is_dcd = msm_chg_check_dcd(motg);
1231                 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1232                 if (is_dcd || tmout) {
1233                         msm_chg_disable_dcd(motg);
1234                         msm_chg_enable_primary_det(motg);
1235                         delay = MSM_CHG_PRIMARY_DET_TIME;
1236                         motg->chg_state = USB_CHG_STATE_DCD_DONE;
1237                 } else {
1238                         delay = MSM_CHG_DCD_POLL_TIME;
1239                 }
1240                 break;
1241         case USB_CHG_STATE_DCD_DONE:
1242                 vout = msm_chg_check_primary_det(motg);
1243                 if (vout) {
1244                         msm_chg_enable_secondary_det(motg);
1245                         delay = MSM_CHG_SECONDARY_DET_TIME;
1246                         motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1247                 } else {
1248                         motg->chg_type = USB_SDP_CHARGER;
1249                         motg->chg_state = USB_CHG_STATE_DETECTED;
1250                         delay = 0;
1251                 }
1252                 break;
1253         case USB_CHG_STATE_PRIMARY_DONE:
1254                 vout = msm_chg_check_secondary_det(motg);
1255                 if (vout)
1256                         motg->chg_type = USB_DCP_CHARGER;
1257                 else
1258                         motg->chg_type = USB_CDP_CHARGER;
1259                 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1260                 /* fall through */
1261         case USB_CHG_STATE_SECONDARY_DONE:
1262                 motg->chg_state = USB_CHG_STATE_DETECTED;
1263         case USB_CHG_STATE_DETECTED:
1264                 msm_chg_block_off(motg);
1265                 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1266                 schedule_work(&motg->sm_work);
1267                 return;
1268         default:
1269                 return;
1270         }
1271
1272         schedule_delayed_work(&motg->chg_work, delay);
1273 }
1274
1275 /*
1276  * We support OTG, Peripheral only and Host only configurations. In case
1277  * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1278  * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1279  * enabled when switch is controlled by user and default mode is supplied
1280  * by board file, which can be changed by userspace later.
1281  */
1282 static void msm_otg_init_sm(struct msm_otg *motg)
1283 {
1284         struct msm_otg_platform_data *pdata = motg->pdata;
1285         u32 otgsc = readl(USB_OTGSC);
1286
1287         switch (pdata->mode) {
1288         case USB_DR_MODE_OTG:
1289                 if (pdata->otg_control == OTG_PHY_CONTROL) {
1290                         if (otgsc & OTGSC_ID)
1291                                 set_bit(ID, &motg->inputs);
1292                         else
1293                                 clear_bit(ID, &motg->inputs);
1294
1295                         if (otgsc & OTGSC_BSV)
1296                                 set_bit(B_SESS_VLD, &motg->inputs);
1297                         else
1298                                 clear_bit(B_SESS_VLD, &motg->inputs);
1299                 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1300                                 set_bit(ID, &motg->inputs);
1301                                 clear_bit(B_SESS_VLD, &motg->inputs);
1302                 }
1303                 break;
1304         case USB_DR_MODE_HOST:
1305                 clear_bit(ID, &motg->inputs);
1306                 break;
1307         case USB_DR_MODE_PERIPHERAL:
1308                 set_bit(ID, &motg->inputs);
1309                 if (otgsc & OTGSC_BSV)
1310                         set_bit(B_SESS_VLD, &motg->inputs);
1311                 else
1312                         clear_bit(B_SESS_VLD, &motg->inputs);
1313                 break;
1314         default:
1315                 break;
1316         }
1317 }
1318
1319 static void msm_otg_sm_work(struct work_struct *w)
1320 {
1321         struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1322         struct usb_otg *otg = motg->phy.otg;
1323
1324         switch (otg->state) {
1325         case OTG_STATE_UNDEFINED:
1326                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1327                 msm_otg_reset(otg->usb_phy);
1328                 msm_otg_init_sm(motg);
1329                 otg->state = OTG_STATE_B_IDLE;
1330                 /* FALL THROUGH */
1331         case OTG_STATE_B_IDLE:
1332                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
1333                 if (!test_bit(ID, &motg->inputs) && otg->host) {
1334                         /* disable BSV bit */
1335                         writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1336                         msm_otg_start_host(otg->usb_phy, 1);
1337                         otg->state = OTG_STATE_A_HOST;
1338                 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1339                         switch (motg->chg_state) {
1340                         case USB_CHG_STATE_UNDEFINED:
1341                                 msm_chg_detect_work(&motg->chg_work.work);
1342                                 break;
1343                         case USB_CHG_STATE_DETECTED:
1344                                 switch (motg->chg_type) {
1345                                 case USB_DCP_CHARGER:
1346                                         msm_otg_notify_charger(motg,
1347                                                         IDEV_CHG_MAX);
1348                                         break;
1349                                 case USB_CDP_CHARGER:
1350                                         msm_otg_notify_charger(motg,
1351                                                         IDEV_CHG_MAX);
1352                                         msm_otg_start_peripheral(otg->usb_phy,
1353                                                                  1);
1354                                         otg->state
1355                                                 = OTG_STATE_B_PERIPHERAL;
1356                                         break;
1357                                 case USB_SDP_CHARGER:
1358                                         msm_otg_notify_charger(motg, IUNIT);
1359                                         msm_otg_start_peripheral(otg->usb_phy,
1360                                                                  1);
1361                                         otg->state
1362                                                 = OTG_STATE_B_PERIPHERAL;
1363                                         break;
1364                                 default:
1365                                         break;
1366                                 }
1367                                 break;
1368                         default:
1369                                 break;
1370                         }
1371                 } else {
1372                         /*
1373                          * If charger detection work is pending, decrement
1374                          * the pm usage counter to balance with the one that
1375                          * is incremented in charger detection work.
1376                          */
1377                         if (cancel_delayed_work_sync(&motg->chg_work)) {
1378                                 pm_runtime_put_sync(otg->usb_phy->dev);
1379                                 msm_otg_reset(otg->usb_phy);
1380                         }
1381                         msm_otg_notify_charger(motg, 0);
1382                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1383                         motg->chg_type = USB_INVALID_CHARGER;
1384                 }
1385
1386                 if (otg->state == OTG_STATE_B_IDLE)
1387                         pm_runtime_put_sync(otg->usb_phy->dev);
1388                 break;
1389         case OTG_STATE_B_PERIPHERAL:
1390                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1391                 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1392                                 !test_bit(ID, &motg->inputs)) {
1393                         msm_otg_notify_charger(motg, 0);
1394                         msm_otg_start_peripheral(otg->usb_phy, 0);
1395                         motg->chg_state = USB_CHG_STATE_UNDEFINED;
1396                         motg->chg_type = USB_INVALID_CHARGER;
1397                         otg->state = OTG_STATE_B_IDLE;
1398                         msm_otg_reset(otg->usb_phy);
1399                         schedule_work(w);
1400                 }
1401                 break;
1402         case OTG_STATE_A_HOST:
1403                 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
1404                 if (test_bit(ID, &motg->inputs)) {
1405                         msm_otg_start_host(otg->usb_phy, 0);
1406                         otg->state = OTG_STATE_B_IDLE;
1407                         msm_otg_reset(otg->usb_phy);
1408                         schedule_work(w);
1409                 }
1410                 break;
1411         default:
1412                 break;
1413         }
1414 }
1415
1416 static irqreturn_t msm_otg_irq(int irq, void *data)
1417 {
1418         struct msm_otg *motg = data;
1419         struct usb_phy *phy = &motg->phy;
1420         u32 otgsc = 0;
1421
1422         if (atomic_read(&motg->in_lpm)) {
1423                 disable_irq_nosync(irq);
1424                 motg->async_int = 1;
1425                 pm_runtime_get(phy->dev);
1426                 return IRQ_HANDLED;
1427         }
1428
1429         otgsc = readl(USB_OTGSC);
1430         if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1431                 return IRQ_NONE;
1432
1433         if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1434                 if (otgsc & OTGSC_ID)
1435                         set_bit(ID, &motg->inputs);
1436                 else
1437                         clear_bit(ID, &motg->inputs);
1438                 dev_dbg(phy->dev, "ID set/clear\n");
1439                 pm_runtime_get_noresume(phy->dev);
1440         } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1441                 if (otgsc & OTGSC_BSV)
1442                         set_bit(B_SESS_VLD, &motg->inputs);
1443                 else
1444                         clear_bit(B_SESS_VLD, &motg->inputs);
1445                 dev_dbg(phy->dev, "BSV set/clear\n");
1446                 pm_runtime_get_noresume(phy->dev);
1447         }
1448
1449         writel(otgsc, USB_OTGSC);
1450         schedule_work(&motg->sm_work);
1451         return IRQ_HANDLED;
1452 }
1453
1454 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1455 {
1456         struct msm_otg *motg = s->private;
1457         struct usb_otg *otg = motg->phy.otg;
1458
1459         switch (otg->state) {
1460         case OTG_STATE_A_HOST:
1461                 seq_puts(s, "host\n");
1462                 break;
1463         case OTG_STATE_B_PERIPHERAL:
1464                 seq_puts(s, "peripheral\n");
1465                 break;
1466         default:
1467                 seq_puts(s, "none\n");
1468                 break;
1469         }
1470
1471         return 0;
1472 }
1473
1474 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1475 {
1476         return single_open(file, msm_otg_mode_show, inode->i_private);
1477 }
1478
1479 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1480                                 size_t count, loff_t *ppos)
1481 {
1482         struct seq_file *s = file->private_data;
1483         struct msm_otg *motg = s->private;
1484         char buf[16];
1485         struct usb_otg *otg = motg->phy.otg;
1486         int status = count;
1487         enum usb_dr_mode req_mode;
1488
1489         memset(buf, 0x00, sizeof(buf));
1490
1491         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1492                 status = -EFAULT;
1493                 goto out;
1494         }
1495
1496         if (!strncmp(buf, "host", 4)) {
1497                 req_mode = USB_DR_MODE_HOST;
1498         } else if (!strncmp(buf, "peripheral", 10)) {
1499                 req_mode = USB_DR_MODE_PERIPHERAL;
1500         } else if (!strncmp(buf, "none", 4)) {
1501                 req_mode = USB_DR_MODE_UNKNOWN;
1502         } else {
1503                 status = -EINVAL;
1504                 goto out;
1505         }
1506
1507         switch (req_mode) {
1508         case USB_DR_MODE_UNKNOWN:
1509                 switch (otg->state) {
1510                 case OTG_STATE_A_HOST:
1511                 case OTG_STATE_B_PERIPHERAL:
1512                         set_bit(ID, &motg->inputs);
1513                         clear_bit(B_SESS_VLD, &motg->inputs);
1514                         break;
1515                 default:
1516                         goto out;
1517                 }
1518                 break;
1519         case USB_DR_MODE_PERIPHERAL:
1520                 switch (otg->state) {
1521                 case OTG_STATE_B_IDLE:
1522                 case OTG_STATE_A_HOST:
1523                         set_bit(ID, &motg->inputs);
1524                         set_bit(B_SESS_VLD, &motg->inputs);
1525                         break;
1526                 default:
1527                         goto out;
1528                 }
1529                 break;
1530         case USB_DR_MODE_HOST:
1531                 switch (otg->state) {
1532                 case OTG_STATE_B_IDLE:
1533                 case OTG_STATE_B_PERIPHERAL:
1534                         clear_bit(ID, &motg->inputs);
1535                         break;
1536                 default:
1537                         goto out;
1538                 }
1539                 break;
1540         default:
1541                 goto out;
1542         }
1543
1544         pm_runtime_get_sync(otg->usb_phy->dev);
1545         schedule_work(&motg->sm_work);
1546 out:
1547         return status;
1548 }
1549
1550 static const struct file_operations msm_otg_mode_fops = {
1551         .open = msm_otg_mode_open,
1552         .read = seq_read,
1553         .write = msm_otg_mode_write,
1554         .llseek = seq_lseek,
1555         .release = single_release,
1556 };
1557
1558 static struct dentry *msm_otg_dbg_root;
1559 static struct dentry *msm_otg_dbg_mode;
1560
1561 static int msm_otg_debugfs_init(struct msm_otg *motg)
1562 {
1563         msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1564
1565         if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1566                 return -ENODEV;
1567
1568         msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1569                                 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1570         if (!msm_otg_dbg_mode) {
1571                 debugfs_remove(msm_otg_dbg_root);
1572                 msm_otg_dbg_root = NULL;
1573                 return -ENODEV;
1574         }
1575
1576         return 0;
1577 }
1578
1579 static void msm_otg_debugfs_cleanup(void)
1580 {
1581         debugfs_remove(msm_otg_dbg_mode);
1582         debugfs_remove(msm_otg_dbg_root);
1583 }
1584
1585 static const struct of_device_id msm_otg_dt_match[] = {
1586         {
1587                 .compatible = "qcom,usb-otg-ci",
1588                 .data = (void *) CI_45NM_INTEGRATED_PHY
1589         },
1590         {
1591                 .compatible = "qcom,usb-otg-snps",
1592                 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1593         },
1594         { }
1595 };
1596 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1597
1598 static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event,
1599                                 void *ptr)
1600 {
1601         struct usb_phy *usb_phy = container_of(nb, struct usb_phy, vbus_nb);
1602         struct msm_otg *motg = container_of(usb_phy, struct msm_otg, phy);
1603
1604         if (event)
1605                 set_bit(B_SESS_VLD, &motg->inputs);
1606         else
1607                 clear_bit(B_SESS_VLD, &motg->inputs);
1608
1609         if (test_bit(B_SESS_VLD, &motg->inputs)) {
1610                 /* Switch D+/D- lines to Device connector */
1611                 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1612         } else {
1613                 /* Switch D+/D- lines to Hub */
1614                 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1615         }
1616
1617         schedule_work(&motg->sm_work);
1618
1619         return NOTIFY_DONE;
1620 }
1621
1622 static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event,
1623                                 void *ptr)
1624 {
1625         struct usb_phy *usb_phy = container_of(nb, struct usb_phy, id_nb);
1626         struct msm_otg *motg = container_of(usb_phy, struct msm_otg, phy);
1627
1628         if (event)
1629                 clear_bit(ID, &motg->inputs);
1630         else
1631                 set_bit(ID, &motg->inputs);
1632
1633         schedule_work(&motg->sm_work);
1634
1635         return NOTIFY_DONE;
1636 }
1637
1638 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1639 {
1640         struct msm_otg_platform_data *pdata;
1641         struct device_node *node = pdev->dev.of_node;
1642         struct property *prop;
1643         int len, ret, words;
1644         u32 val, tmp[3];
1645
1646         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1647         if (!pdata)
1648                 return -ENOMEM;
1649
1650         motg->pdata = pdata;
1651
1652         pdata->phy_type = (enum msm_usb_phy_type)of_device_get_match_data(&pdev->dev);
1653         if (!pdata->phy_type)
1654                 return 1;
1655
1656         motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1657         if (IS_ERR(motg->link_rst))
1658                 return PTR_ERR(motg->link_rst);
1659
1660         motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1661         if (IS_ERR(motg->phy_rst))
1662                 motg->phy_rst = NULL;
1663
1664         pdata->mode = usb_get_dr_mode(&pdev->dev);
1665         if (pdata->mode == USB_DR_MODE_UNKNOWN)
1666                 pdata->mode = USB_DR_MODE_OTG;
1667
1668         pdata->otg_control = OTG_PHY_CONTROL;
1669         if (!of_property_read_u32(node, "qcom,otg-control", &val))
1670                 if (val == OTG_PMIC_CONTROL)
1671                         pdata->otg_control = val;
1672
1673         if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1674                 motg->phy_number = val;
1675
1676         motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1677         motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1678         motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1679
1680         if (of_get_property(node, "qcom,vdd-levels", &len) &&
1681             len == sizeof(tmp)) {
1682                 of_property_read_u32_array(node, "qcom,vdd-levels",
1683                                            tmp, len / sizeof(*tmp));
1684                 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1685                 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1686                 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1687         }
1688
1689         motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup");
1690
1691         motg->switch_gpio = devm_gpiod_get_optional(&pdev->dev, "switch",
1692                                                     GPIOD_OUT_LOW);
1693         if (IS_ERR(motg->switch_gpio))
1694                 return PTR_ERR(motg->switch_gpio);
1695
1696         prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1697         if (!prop || !len)
1698                 return 0;
1699
1700         words = len / sizeof(u32);
1701
1702         if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1703                 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1704                 return 0;
1705         }
1706
1707         pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1708         if (!pdata->phy_init_seq)
1709                 return 0;
1710
1711         ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1712                                          pdata->phy_init_seq, words);
1713         if (!ret)
1714                 pdata->phy_init_sz = words;
1715
1716         return 0;
1717 }
1718
1719 static int msm_otg_reboot_notify(struct notifier_block *this,
1720                                  unsigned long code, void *unused)
1721 {
1722         struct msm_otg *motg = container_of(this, struct msm_otg, reboot);
1723
1724         /*
1725          * Ensure that D+/D- lines are routed to uB connector, so
1726          * we could load bootloader/kernel at next reboot
1727          */
1728         gpiod_set_value_cansleep(motg->switch_gpio, 0);
1729         return NOTIFY_DONE;
1730 }
1731
1732 static int msm_otg_probe(struct platform_device *pdev)
1733 {
1734         struct regulator_bulk_data regs[3];
1735         int ret = 0;
1736         struct device_node *np = pdev->dev.of_node;
1737         struct msm_otg_platform_data *pdata;
1738         struct resource *res;
1739         struct msm_otg *motg;
1740         struct usb_phy *phy;
1741         void __iomem *phy_select;
1742
1743         motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1744         if (!motg)
1745                 return -ENOMEM;
1746
1747         motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1748                                      GFP_KERNEL);
1749         if (!motg->phy.otg)
1750                 return -ENOMEM;
1751
1752         phy = &motg->phy;
1753         phy->dev = &pdev->dev;
1754
1755         motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1756         if (IS_ERR(motg->clk)) {
1757                 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1758                 return PTR_ERR(motg->clk);
1759         }
1760
1761         /*
1762          * If USB Core is running its protocol engine based on CORE CLK,
1763          * CORE CLK  must be running at >55Mhz for correct HSUSB
1764          * operation and USB core cannot tolerate frequency changes on
1765          * CORE CLK.
1766          */
1767         motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1768         if (IS_ERR(motg->pclk)) {
1769                 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1770                 return PTR_ERR(motg->pclk);
1771         }
1772
1773         /*
1774          * USB core clock is not present on all MSM chips. This
1775          * clock is introduced to remove the dependency on AXI
1776          * bus frequency.
1777          */
1778         motg->core_clk = devm_clk_get(&pdev->dev,
1779                                       np ? "alt_core" : "usb_hs_core_clk");
1780
1781         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1782         if (!res)
1783                 return -EINVAL;
1784         motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1785         if (!motg->regs)
1786                 return -ENOMEM;
1787
1788         pdata = dev_get_platdata(&pdev->dev);
1789         if (!pdata) {
1790                 if (!np)
1791                         return -ENXIO;
1792                 ret = msm_otg_read_dt(pdev, motg);
1793                 if (ret)
1794                         return ret;
1795         }
1796
1797         /*
1798          * NOTE: The PHYs can be multiplexed between the chipidea controller
1799          * and the dwc3 controller, using a single bit. It is important that
1800          * the dwc3 driver does not set this bit in an incompatible way.
1801          */
1802         if (motg->phy_number) {
1803                 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1804                 if (!phy_select)
1805                         return -ENOMEM;
1806
1807                 /* Enable second PHY with the OTG port */
1808                 writel(0x1, phy_select);
1809         }
1810
1811         dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1812
1813         motg->irq = platform_get_irq(pdev, 0);
1814         if (motg->irq < 0) {
1815                 dev_err(&pdev->dev, "platform_get_irq failed\n");
1816                 ret = motg->irq;
1817                 return motg->irq;
1818         }
1819
1820         regs[0].supply = "vddcx";
1821         regs[1].supply = "v3p3";
1822         regs[2].supply = "v1p8";
1823
1824         ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1825         if (ret)
1826                 return ret;
1827
1828         motg->vddcx = regs[0].consumer;
1829         motg->v3p3  = regs[1].consumer;
1830         motg->v1p8  = regs[2].consumer;
1831
1832         clk_set_rate(motg->clk, 60000000);
1833
1834         clk_prepare_enable(motg->clk);
1835         clk_prepare_enable(motg->pclk);
1836
1837         if (!IS_ERR(motg->core_clk))
1838                 clk_prepare_enable(motg->core_clk);
1839
1840         ret = msm_hsusb_init_vddcx(motg, 1);
1841         if (ret) {
1842                 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1843                 goto disable_clks;
1844         }
1845
1846         ret = msm_hsusb_ldo_init(motg, 1);
1847         if (ret) {
1848                 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1849                 goto disable_vddcx;
1850         }
1851         ret = msm_hsusb_ldo_set_mode(motg, 1);
1852         if (ret) {
1853                 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1854                 goto disable_ldo;
1855         }
1856
1857         writel(0, USB_USBINTR);
1858         writel(0, USB_OTGSC);
1859
1860         INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1861         INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1862         ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1863                                         "msm_otg", motg);
1864         if (ret) {
1865                 dev_err(&pdev->dev, "request irq failed\n");
1866                 goto disable_ldo;
1867         }
1868
1869         phy->init = msm_phy_init;
1870         phy->notify_disconnect = msm_phy_notify_disconnect;
1871         phy->type = USB_PHY_TYPE_USB2;
1872         phy->vbus_nb.notifier_call = msm_otg_vbus_notifier;
1873         phy->id_nb.notifier_call = msm_otg_id_notifier;
1874
1875         phy->io_ops = &msm_otg_io_ops;
1876
1877         phy->otg->usb_phy = &motg->phy;
1878         phy->otg->set_host = msm_otg_set_host;
1879         phy->otg->set_peripheral = msm_otg_set_peripheral;
1880
1881         msm_usb_reset(phy);
1882
1883         ret = usb_add_phy_dev(&motg->phy);
1884         if (ret) {
1885                 dev_err(&pdev->dev, "usb_add_phy failed\n");
1886                 goto disable_ldo;
1887         }
1888
1889         ret = extcon_get_state(phy->edev, EXTCON_USB);
1890         if (ret)
1891                 set_bit(B_SESS_VLD, &motg->inputs);
1892         else
1893                 clear_bit(B_SESS_VLD, &motg->inputs);
1894
1895         ret = extcon_get_state(phy->id_edev, EXTCON_USB_HOST);
1896         if (ret)
1897                 clear_bit(ID, &motg->inputs);
1898         else
1899                 set_bit(ID, &motg->inputs);
1900
1901         platform_set_drvdata(pdev, motg);
1902         device_init_wakeup(&pdev->dev, 1);
1903
1904         if (motg->pdata->mode == USB_DR_MODE_OTG &&
1905                 motg->pdata->otg_control == OTG_USER_CONTROL) {
1906                 ret = msm_otg_debugfs_init(motg);
1907                 if (ret)
1908                         dev_dbg(&pdev->dev, "Can not create mode change file\n");
1909         }
1910
1911         if (test_bit(B_SESS_VLD, &motg->inputs)) {
1912                 /* Switch D+/D- lines to Device connector */
1913                 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1914         } else {
1915                 /* Switch D+/D- lines to Hub */
1916                 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1917         }
1918
1919         motg->reboot.notifier_call = msm_otg_reboot_notify;
1920         register_reboot_notifier(&motg->reboot);
1921
1922         pm_runtime_set_active(&pdev->dev);
1923         pm_runtime_enable(&pdev->dev);
1924
1925         return 0;
1926
1927 disable_ldo:
1928         msm_hsusb_ldo_init(motg, 0);
1929 disable_vddcx:
1930         msm_hsusb_init_vddcx(motg, 0);
1931 disable_clks:
1932         clk_disable_unprepare(motg->pclk);
1933         clk_disable_unprepare(motg->clk);
1934         if (!IS_ERR(motg->core_clk))
1935                 clk_disable_unprepare(motg->core_clk);
1936
1937         return ret;
1938 }
1939
1940 static int msm_otg_remove(struct platform_device *pdev)
1941 {
1942         struct msm_otg *motg = platform_get_drvdata(pdev);
1943         struct usb_phy *phy = &motg->phy;
1944         int cnt = 0;
1945
1946         if (phy->otg->host || phy->otg->gadget)
1947                 return -EBUSY;
1948
1949         unregister_reboot_notifier(&motg->reboot);
1950
1951         /*
1952          * Ensure that D+/D- lines are routed to uB connector, so
1953          * we could load bootloader/kernel at next reboot
1954          */
1955         gpiod_set_value_cansleep(motg->switch_gpio, 0);
1956
1957         msm_otg_debugfs_cleanup();
1958         cancel_delayed_work_sync(&motg->chg_work);
1959         cancel_work_sync(&motg->sm_work);
1960
1961         pm_runtime_resume(&pdev->dev);
1962
1963         device_init_wakeup(&pdev->dev, 0);
1964         pm_runtime_disable(&pdev->dev);
1965
1966         usb_remove_phy(phy);
1967         disable_irq(motg->irq);
1968
1969         /*
1970          * Put PHY in low power mode.
1971          */
1972         ulpi_read(phy, 0x14);
1973         ulpi_write(phy, 0x08, 0x09);
1974
1975         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1976         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1977                 if (readl(USB_PORTSC) & PORTSC_PHCD)
1978                         break;
1979                 udelay(1);
1980                 cnt++;
1981         }
1982         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1983                 dev_err(phy->dev, "Unable to suspend PHY\n");
1984
1985         clk_disable_unprepare(motg->pclk);
1986         clk_disable_unprepare(motg->clk);
1987         if (!IS_ERR(motg->core_clk))
1988                 clk_disable_unprepare(motg->core_clk);
1989         msm_hsusb_ldo_init(motg, 0);
1990
1991         pm_runtime_set_suspended(&pdev->dev);
1992
1993         return 0;
1994 }
1995
1996 #ifdef CONFIG_PM
1997 static int msm_otg_runtime_idle(struct device *dev)
1998 {
1999         struct msm_otg *motg = dev_get_drvdata(dev);
2000         struct usb_otg *otg = motg->phy.otg;
2001
2002         dev_dbg(dev, "OTG runtime idle\n");
2003
2004         /*
2005          * It is observed some times that a spurious interrupt
2006          * comes when PHY is put into LPM immediately after PHY reset.
2007          * This 1 sec delay also prevents entering into LPM immediately
2008          * after asynchronous interrupt.
2009          */
2010         if (otg->state != OTG_STATE_UNDEFINED)
2011                 pm_schedule_suspend(dev, 1000);
2012
2013         return -EAGAIN;
2014 }
2015
2016 static int msm_otg_runtime_suspend(struct device *dev)
2017 {
2018         struct msm_otg *motg = dev_get_drvdata(dev);
2019
2020         dev_dbg(dev, "OTG runtime suspend\n");
2021         return msm_otg_suspend(motg);
2022 }
2023
2024 static int msm_otg_runtime_resume(struct device *dev)
2025 {
2026         struct msm_otg *motg = dev_get_drvdata(dev);
2027
2028         dev_dbg(dev, "OTG runtime resume\n");
2029         return msm_otg_resume(motg);
2030 }
2031 #endif
2032
2033 #ifdef CONFIG_PM_SLEEP
2034 static int msm_otg_pm_suspend(struct device *dev)
2035 {
2036         struct msm_otg *motg = dev_get_drvdata(dev);
2037
2038         dev_dbg(dev, "OTG PM suspend\n");
2039         return msm_otg_suspend(motg);
2040 }
2041
2042 static int msm_otg_pm_resume(struct device *dev)
2043 {
2044         struct msm_otg *motg = dev_get_drvdata(dev);
2045         int ret;
2046
2047         dev_dbg(dev, "OTG PM resume\n");
2048
2049         ret = msm_otg_resume(motg);
2050         if (ret)
2051                 return ret;
2052
2053         /*
2054          * Runtime PM Documentation recommends bringing the
2055          * device to full powered state upon resume.
2056          */
2057         pm_runtime_disable(dev);
2058         pm_runtime_set_active(dev);
2059         pm_runtime_enable(dev);
2060
2061         return 0;
2062 }
2063 #endif
2064
2065 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
2066         SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
2067         SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
2068                                 msm_otg_runtime_idle)
2069 };
2070
2071 static struct platform_driver msm_otg_driver = {
2072         .probe = msm_otg_probe,
2073         .remove = msm_otg_remove,
2074         .driver = {
2075                 .name = DRIVER_NAME,
2076                 .pm = &msm_otg_dev_pm_ops,
2077                 .of_match_table = msm_otg_dt_match,
2078         },
2079 };
2080
2081 module_platform_driver(msm_otg_driver);
2082
2083 MODULE_LICENSE("GPL v2");
2084 MODULE_DESCRIPTION("MSM USB transceiver driver");