1 // SPDX-License-Identifier: GPL-2.0
4 * xHCI host controller driver
6 * Copyright (C) 2008 Intel Corp.
9 * Some code borrowed from the Linux EHCI driver.
12 #ifndef __LINUX_XHCI_HCD_H
13 #define __LINUX_XHCI_HCD_H
15 #include <linux/usb.h>
16 #include <linux/timer.h>
17 #include <linux/kernel.h>
18 #include <linux/usb/hcd.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
21 /* Code sharing between pci-quirks and xhci hcd */
22 #include "xhci-ext-caps.h"
23 #include "pci-quirks.h"
25 /* xHCI PCI Configuration Registers */
26 #define XHCI_SBRN_OFFSET (0x60)
28 /* Max number of USB devices for any host controller - limit in section 6.1 */
29 #define MAX_HC_SLOTS 256
30 /* Section 5.3.3 - MaxPorts */
31 #define MAX_HC_PORTS 127
34 * xHCI register interface.
35 * This corresponds to the eXtensible Host Controller Interface (xHCI)
36 * Revision 0.95 specification
40 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
41 * @hc_capbase: length of the capabilities register and HC version number
42 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
43 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
44 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
45 * @hcc_params: HCCPARAMS - Capability Parameters
46 * @db_off: DBOFF - Doorbell array offset
47 * @run_regs_off: RTSOFF - Runtime register space offset
48 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
50 struct xhci_cap_regs {
58 __le32 hcc_params2; /* xhci 1.1 */
59 /* Reserved up to (CAPLENGTH - 0x1C) */
62 /* hc_capbase bitmasks */
63 /* bits 7:0 - how long is the Capabilities register */
64 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
66 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
68 /* HCSPARAMS1 - hcs_params1 - bitmasks */
69 /* bits 0:7, Max Device Slots */
70 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
71 #define HCS_SLOTS_MASK 0xff
72 /* bits 8:18, Max Interrupters */
73 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
74 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
75 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
77 /* HCSPARAMS2 - hcs_params2 - bitmasks */
78 /* bits 0:3, frames or uframes that SW needs to queue transactions
79 * ahead of the HW to meet periodic deadlines */
80 #define HCS_IST(p) (((p) >> 0) & 0xf)
81 /* bits 4:7, max number of Event Ring segments */
82 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
83 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
84 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
85 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
86 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
88 /* HCSPARAMS3 - hcs_params3 - bitmasks */
89 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
90 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
91 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
92 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
94 /* HCCPARAMS - hcc_params - bitmasks */
95 /* true: HC can use 64-bit address pointers */
96 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
97 /* true: HC can do bandwidth negotiation */
98 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
99 /* true: HC uses 64-byte Device Context structures
100 * FIXME 64-byte context structures aren't supported yet.
102 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
103 /* true: HC has port power switches */
104 #define HCC_PPC(p) ((p) & (1 << 3))
105 /* true: HC has port indicators */
106 #define HCS_INDICATOR(p) ((p) & (1 << 4))
107 /* true: HC has Light HC Reset Capability */
108 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
109 /* true: HC supports latency tolerance messaging */
110 #define HCC_LTC(p) ((p) & (1 << 6))
111 /* true: no secondary Stream ID Support */
112 #define HCC_NSS(p) ((p) & (1 << 7))
113 /* true: HC supports Stopped - Short Packet */
114 #define HCC_SPC(p) ((p) & (1 << 9))
115 /* true: HC has Contiguous Frame ID Capability */
116 #define HCC_CFC(p) ((p) & (1 << 11))
117 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
118 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
119 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
120 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
122 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
124 /* db_off bitmask - bits 0:1 reserved */
125 #define DBOFF_MASK (~0x3)
127 /* run_regs_off bitmask - bits 0:4 reserved */
128 #define RTSOFF_MASK (~0x1f)
130 /* HCCPARAMS2 - hcc_params2 - bitmasks */
131 /* true: HC supports U3 entry Capability */
132 #define HCC2_U3C(p) ((p) & (1 << 0))
133 /* true: HC supports Configure endpoint command Max exit latency too large */
134 #define HCC2_CMC(p) ((p) & (1 << 1))
135 /* true: HC supports Force Save context Capability */
136 #define HCC2_FSC(p) ((p) & (1 << 2))
137 /* true: HC supports Compliance Transition Capability */
138 #define HCC2_CTC(p) ((p) & (1 << 3))
139 /* true: HC support Large ESIT payload Capability > 48k */
140 #define HCC2_LEC(p) ((p) & (1 << 4))
141 /* true: HC support Configuration Information Capability */
142 #define HCC2_CIC(p) ((p) & (1 << 5))
143 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
144 #define HCC2_ETC(p) ((p) & (1 << 6))
146 /* Number of registers per port */
147 #define NUM_PORT_REGS 4
155 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
156 * @command: USBCMD - xHC command register
157 * @status: USBSTS - xHC status register
158 * @page_size: This indicates the page size that the host controller
159 * supports. If bit n is set, the HC supports a page size
160 * of 2^(n+12), up to a 128MB page size.
161 * 4K is the minimum page size.
162 * @cmd_ring: CRP - 64-bit Command Ring Pointer
163 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
164 * @config_reg: CONFIG - Configure Register
165 * @port_status_base: PORTSCn - base address for Port Status and Control
166 * Each port has a Port Status and Control register,
167 * followed by a Port Power Management Status and Control
168 * register, a Port Link Info register, and a reserved
170 * @port_power_base: PORTPMSCn - base address for
171 * Port Power Management Status and Control
172 * @port_link_base: PORTLIn - base address for Port Link Info (current
173 * Link PM state and control) for USB 2.1 and USB 3.0
176 struct xhci_op_regs {
182 __le32 dev_notification;
184 /* rsvd: offset 0x20-2F */
188 /* rsvd: offset 0x3C-3FF */
189 __le32 reserved4[241];
190 /* port 1 registers, which serve as a base address for other ports */
191 __le32 port_status_base;
192 __le32 port_power_base;
193 __le32 port_link_base;
195 /* registers for ports 2-255 */
196 __le32 reserved6[NUM_PORT_REGS*254];
199 /* USBCMD - USB command - command bitmasks */
200 /* start/stop HC execution - do not write unless HC is halted*/
201 #define CMD_RUN XHCI_CMD_RUN
202 /* Reset HC - resets internal HC state machine and all registers (except
203 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
204 * The xHCI driver must reinitialize the xHC after setting this bit.
206 #define CMD_RESET (1 << 1)
207 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
208 #define CMD_EIE XHCI_CMD_EIE
209 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
210 #define CMD_HSEIE XHCI_CMD_HSEIE
211 /* bits 4:6 are reserved (and should be preserved on writes). */
212 /* light reset (port status stays unchanged) - reset completed when this is 0 */
213 #define CMD_LRESET (1 << 7)
214 /* host controller save/restore state. */
215 #define CMD_CSS (1 << 8)
216 #define CMD_CRS (1 << 9)
217 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
218 #define CMD_EWE XHCI_CMD_EWE
219 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
220 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
221 * '0' means the xHC can power it off if all ports are in the disconnect,
222 * disabled, or powered-off state.
224 #define CMD_PM_INDEX (1 << 11)
225 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
226 #define CMD_ETE (1 << 14)
227 /* bits 15:31 are reserved (and should be preserved on writes). */
229 /* IMAN - Interrupt Management Register */
230 #define IMAN_IE (1 << 1)
231 #define IMAN_IP (1 << 0)
233 /* USBSTS - USB status - status bitmasks */
234 /* HC not running - set to 1 when run/stop bit is cleared. */
235 #define STS_HALT XHCI_STS_HALT
236 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
237 #define STS_FATAL (1 << 2)
238 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
239 #define STS_EINT (1 << 3)
240 /* port change detect */
241 #define STS_PORT (1 << 4)
242 /* bits 5:7 reserved and zeroed */
243 /* save state status - '1' means xHC is saving state */
244 #define STS_SAVE (1 << 8)
245 /* restore state status - '1' means xHC is restoring state */
246 #define STS_RESTORE (1 << 9)
247 /* true: save or restore error */
248 #define STS_SRE (1 << 10)
249 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
250 #define STS_CNR XHCI_STS_CNR
251 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
252 #define STS_HCE (1 << 12)
253 /* bits 13:31 reserved and should be preserved */
256 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
257 * Generate a device notification event when the HC sees a transaction with a
258 * notification type that matches a bit set in this bit field.
260 #define DEV_NOTE_MASK (0xffff)
261 #define ENABLE_DEV_NOTE(x) (1 << (x))
262 /* Most of the device notification types should only be used for debug.
263 * SW does need to pay attention to function wake notifications.
265 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
267 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
268 /* bit 0 is the command ring cycle state */
269 /* stop ring operation after completion of the currently executing command */
270 #define CMD_RING_PAUSE (1 << 1)
271 /* stop ring immediately - abort the currently executing command */
272 #define CMD_RING_ABORT (1 << 2)
273 /* true: command ring is running */
274 #define CMD_RING_RUNNING (1 << 3)
275 /* bits 4:5 reserved and should be preserved */
276 /* Command Ring pointer - bit mask for the lower 32 bits. */
277 #define CMD_RING_RSVD_BITS (0x3f)
279 /* CONFIG - Configure Register - config_reg bitmasks */
280 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
281 #define MAX_DEVS(p) ((p) & 0xff)
282 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
283 #define CONFIG_U3E (1 << 8)
284 /* bit 9: Configuration Information Enable, xhci 1.1 */
285 #define CONFIG_CIE (1 << 9)
286 /* bits 10:31 - reserved and should be preserved */
288 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
289 /* true: device connected */
290 #define PORT_CONNECT (1 << 0)
291 /* true: port enabled */
292 #define PORT_PE (1 << 1)
293 /* bit 2 reserved and zeroed */
294 /* true: port has an over-current condition */
295 #define PORT_OC (1 << 3)
296 /* true: port reset signaling asserted */
297 #define PORT_RESET (1 << 4)
298 /* Port Link State - bits 5:8
299 * A read gives the current link PM state of the port,
300 * a write with Link State Write Strobe set sets the link state.
302 #define PORT_PLS_MASK (0xf << 5)
303 #define XDEV_U0 (0x0 << 5)
304 #define XDEV_U1 (0x1 << 5)
305 #define XDEV_U2 (0x2 << 5)
306 #define XDEV_U3 (0x3 << 5)
307 #define XDEV_DISABLED (0x4 << 5)
308 #define XDEV_RXDETECT (0x5 << 5)
309 #define XDEV_INACTIVE (0x6 << 5)
310 #define XDEV_POLLING (0x7 << 5)
311 #define XDEV_RECOVERY (0x8 << 5)
312 #define XDEV_HOT_RESET (0x9 << 5)
313 #define XDEV_COMP_MODE (0xa << 5)
314 #define XDEV_TEST_MODE (0xb << 5)
315 #define XDEV_RESUME (0xf << 5)
317 /* true: port has power (see HCC_PPC) */
318 #define PORT_POWER (1 << 9)
319 /* bits 10:13 indicate device speed:
320 * 0 - undefined speed - port hasn't be initialized by a reset yet
327 #define DEV_SPEED_MASK (0xf << 10)
328 #define XDEV_FS (0x1 << 10)
329 #define XDEV_LS (0x2 << 10)
330 #define XDEV_HS (0x3 << 10)
331 #define XDEV_SS (0x4 << 10)
332 #define XDEV_SSP (0x5 << 10)
333 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
334 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
335 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
336 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
337 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
338 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
339 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
340 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
342 /* Bits 20:23 in the Slot Context are the speed for the device */
343 #define SLOT_SPEED_FS (XDEV_FS << 10)
344 #define SLOT_SPEED_LS (XDEV_LS << 10)
345 #define SLOT_SPEED_HS (XDEV_HS << 10)
346 #define SLOT_SPEED_SS (XDEV_SS << 10)
347 #define SLOT_SPEED_SSP (XDEV_SSP << 10)
348 /* Port Indicator Control */
349 #define PORT_LED_OFF (0 << 14)
350 #define PORT_LED_AMBER (1 << 14)
351 #define PORT_LED_GREEN (2 << 14)
352 #define PORT_LED_MASK (3 << 14)
353 /* Port Link State Write Strobe - set this when changing link state */
354 #define PORT_LINK_STROBE (1 << 16)
355 /* true: connect status change */
356 #define PORT_CSC (1 << 17)
357 /* true: port enable change */
358 #define PORT_PEC (1 << 18)
359 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
360 * into an enabled state, and the device into the default state. A "warm" reset
361 * also resets the link, forcing the device through the link training sequence.
362 * SW can also look at the Port Reset register to see when warm reset is done.
364 #define PORT_WRC (1 << 19)
365 /* true: over-current change */
366 #define PORT_OCC (1 << 20)
367 /* true: reset change - 1 to 0 transition of PORT_RESET */
368 #define PORT_RC (1 << 21)
369 /* port link status change - set on some port link state transitions:
371 * ------------------------------------------------------------------------------
372 * - U3 to Resume Wakeup signaling from a device
373 * - Resume to Recovery to U0 USB 3.0 device resume
374 * - Resume to U0 USB 2.0 device resume
375 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
376 * - U3 to U0 Software resume of USB 2.0 device complete
377 * - U2 to U0 L1 resume of USB 2.1 device complete
378 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
379 * - U0 to disabled L1 entry error with USB 2.1 device
380 * - Any state to inactive Error on USB 3.0 port
382 #define PORT_PLC (1 << 22)
383 /* port configure error change - port failed to configure its link partner */
384 #define PORT_CEC (1 << 23)
385 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
386 PORT_RC | PORT_PLC | PORT_CEC)
389 /* Cold Attach Status - xHC can set this bit to report device attached during
390 * Sx state. Warm port reset should be perfomed to clear this bit and move port
391 * to connected state.
393 #define PORT_CAS (1 << 24)
394 /* wake on connect (enable) */
395 #define PORT_WKCONN_E (1 << 25)
396 /* wake on disconnect (enable) */
397 #define PORT_WKDISC_E (1 << 26)
398 /* wake on over-current (enable) */
399 #define PORT_WKOC_E (1 << 27)
400 /* bits 28:29 reserved */
401 /* true: device is non-removable - for USB 3.0 roothub emulation */
402 #define PORT_DEV_REMOVE (1 << 30)
403 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
404 #define PORT_WR (1 << 31)
406 /* We mark duplicate entries with -1 */
407 #define DUPLICATE_ENTRY ((u8)(-1))
409 /* Port Power Management Status and Control - port_power_base bitmasks */
410 /* Inactivity timer value for transitions into U1, in microseconds.
411 * Timeout can be up to 127us. 0xFF means an infinite timeout.
413 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
414 #define PORT_U1_TIMEOUT_MASK 0xff
415 /* Inactivity timer value for transitions into U2 */
416 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
417 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
418 /* Bits 24:31 for port testing */
420 /* USB2 Protocol PORTSPMSC */
421 #define PORT_L1S_MASK 7
422 #define PORT_L1S_SUCCESS 1
423 #define PORT_RWE (1 << 3)
424 #define PORT_HIRD(p) (((p) & 0xf) << 4)
425 #define PORT_HIRD_MASK (0xf << 4)
426 #define PORT_L1DS_MASK (0xff << 8)
427 #define PORT_L1DS(p) (((p) & 0xff) << 8)
428 #define PORT_HLE (1 << 16)
429 #define PORT_TEST_MODE_SHIFT 28
431 /* USB3 Protocol PORTLI Port Link Information */
432 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
433 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
435 /* USB2 Protocol PORTHLPMC */
436 #define PORT_HIRDM(p)((p) & 3)
437 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
438 #define PORT_BESLD(p)(((p) & 0xf) << 10)
440 /* use 512 microseconds as USB2 LPM L1 default timeout. */
441 #define XHCI_L1_TIMEOUT 512
443 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
444 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
445 * by other operating systems.
447 * XHCI 1.0 errata 8/14/12 Table 13 notes:
448 * "Software should choose xHC BESL/BESLD field values that do not violate a
449 * device's resume latency requirements,
450 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
451 * or not program values < '4' if BLC = '0' and a BESL device is attached.
453 #define XHCI_DEFAULT_BESL 4
456 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
457 * to complete link training. usually link trainig completes much faster
458 * so check status 10 times with 36ms sleep in places we need to wait for
459 * polling to complete.
461 #define XHCI_PORT_POLLING_LFPS_TIME 36
464 * struct xhci_intr_reg - Interrupt Register Set
465 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
466 * interrupts and check for pending interrupts.
467 * @irq_control: IMOD - Interrupt Moderation Register.
468 * Used to throttle interrupts.
469 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
470 * @erst_base: ERST base address.
471 * @erst_dequeue: Event ring dequeue pointer.
473 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
474 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
475 * multiple segments of the same size. The HC places events on the ring and
476 * "updates the Cycle bit in the TRBs to indicate to software the current
477 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
478 * updates the dequeue pointer.
480 struct xhci_intr_reg {
489 /* irq_pending bitmasks */
490 #define ER_IRQ_PENDING(p) ((p) & 0x1)
491 /* bits 2:31 need to be preserved */
492 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
493 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
494 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
495 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
497 /* irq_control bitmasks */
498 /* Minimum interval between interrupts (in 250ns intervals). The interval
499 * between interrupts will be longer if there are no events on the event ring.
500 * Default is 4000 (1 ms).
502 #define ER_IRQ_INTERVAL_MASK (0xffff)
503 /* Counter used to count down the time to the next interrupt - HW use only */
504 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
506 /* erst_size bitmasks */
507 /* Preserve bits 16:31 of erst_size */
508 #define ERST_SIZE_MASK (0xffff << 16)
510 /* erst_dequeue bitmasks */
511 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
512 * where the current dequeue pointer lies. This is an optional HW hint.
514 #define ERST_DESI_MASK (0x7)
515 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
516 * a work queue (or delayed service routine)?
518 #define ERST_EHB (1 << 3)
519 #define ERST_PTR_MASK (0xf)
522 * struct xhci_run_regs
524 * MFINDEX - current microframe number
526 * Section 5.5 Host Controller Runtime Registers:
527 * "Software should read and write these registers using only Dword (32 bit)
528 * or larger accesses"
530 struct xhci_run_regs {
531 __le32 microframe_index;
533 struct xhci_intr_reg ir_set[128];
537 * struct doorbell_array
539 * Bits 0 - 7: Endpoint target
541 * Bits 16 - 31: Stream ID
545 struct xhci_doorbell_array {
546 __le32 doorbell[256];
549 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
550 #define DB_VALUE_HOST 0x00000000
553 * struct xhci_protocol_caps
554 * @revision: major revision, minor revision, capability ID,
555 * and next capability pointer.
556 * @name_string: Four ASCII characters to say which spec this xHC
557 * follows, typically "USB ".
558 * @port_info: Port offset, count, and protocol-defined information.
560 struct xhci_protocol_caps {
566 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
567 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
568 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
569 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
570 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
572 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
573 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
574 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
575 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
576 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
577 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
579 #define PLT_MASK (0x03 << 6)
580 #define PLT_SYM (0x00 << 6)
581 #define PLT_ASYM_RX (0x02 << 6)
582 #define PLT_ASYM_TX (0x03 << 6)
585 * struct xhci_container_ctx
586 * @type: Type of context. Used to calculated offsets to contained contexts.
587 * @size: Size of the context data
588 * @bytes: The raw context data given to HW
589 * @dma: dma address of the bytes
591 * Represents either a Device or Input context. Holds a pointer to the raw
592 * memory used for the context (bytes) and dma address of it (dma).
594 struct xhci_container_ctx {
596 #define XHCI_CTX_TYPE_DEVICE 0x1
597 #define XHCI_CTX_TYPE_INPUT 0x2
606 * struct xhci_slot_ctx
607 * @dev_info: Route string, device speed, hub info, and last valid endpoint
608 * @dev_info2: Max exit latency for device number, root hub port number
609 * @tt_info: tt_info is used to construct split transaction tokens
610 * @dev_state: slot state and device address
612 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
613 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
614 * reserved at the end of the slot context for HC internal use.
616 struct xhci_slot_ctx {
621 /* offset 0x10 to 0x1f reserved for HC internal use */
625 /* dev_info bitmasks */
626 /* Route String - 0:19 */
627 #define ROUTE_STRING_MASK (0xfffff)
628 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
629 #define DEV_SPEED (0xf << 20)
630 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
631 /* bit 24 reserved */
632 /* Is this LS/FS device connected through a HS hub? - bit 25 */
633 #define DEV_MTT (0x1 << 25)
634 /* Set if the device is a hub - bit 26 */
635 #define DEV_HUB (0x1 << 26)
636 /* Index of the last valid endpoint context in this device context - 27:31 */
637 #define LAST_CTX_MASK (0x1f << 27)
638 #define LAST_CTX(p) ((p) << 27)
639 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
640 #define SLOT_FLAG (1 << 0)
641 #define EP0_FLAG (1 << 1)
643 /* dev_info2 bitmasks */
644 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
645 #define MAX_EXIT (0xffff)
646 /* Root hub port number that is needed to access the USB device */
647 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
648 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
649 /* Maximum number of ports under a hub device */
650 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
651 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
653 /* tt_info bitmasks */
655 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
656 * The Slot ID of the hub that isolates the high speed signaling from
657 * this low or full-speed device. '0' if attached to root hub port.
659 #define TT_SLOT (0xff)
661 * The number of the downstream facing port of the high-speed hub
662 * '0' if the device is not low or full speed.
664 #define TT_PORT (0xff << 8)
665 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
666 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
668 /* dev_state bitmasks */
669 /* USB device address - assigned by the HC */
670 #define DEV_ADDR_MASK (0xff)
671 /* bits 8:26 reserved */
673 #define SLOT_STATE (0x1f << 27)
674 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
676 #define SLOT_STATE_DISABLED 0
677 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
678 #define SLOT_STATE_DEFAULT 1
679 #define SLOT_STATE_ADDRESSED 2
680 #define SLOT_STATE_CONFIGURED 3
684 * @ep_info: endpoint state, streams, mult, and interval information.
685 * @ep_info2: information on endpoint type, max packet size, max burst size,
686 * error count, and whether the HC will force an event for all
688 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
689 * defines one stream, this points to the endpoint transfer ring.
690 * Otherwise, it points to a stream context array, which has a
691 * ring pointer for each flow.
693 * Average TRB lengths for the endpoint ring and
694 * max payload within an Endpoint Service Interval Time (ESIT).
696 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
697 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
698 * reserved at the end of the endpoint context for HC internal use.
705 /* offset 0x14 - 0x1f reserved for HC internal use */
709 /* ep_info bitmasks */
711 * Endpoint State - bits 0:2
714 * 2 - halted due to halt condition - ok to manipulate endpoint ring
719 #define EP_STATE_MASK (0xf)
720 #define EP_STATE_DISABLED 0
721 #define EP_STATE_RUNNING 1
722 #define EP_STATE_HALTED 2
723 #define EP_STATE_STOPPED 3
724 #define EP_STATE_ERROR 4
725 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
727 /* Mult - Max number of burtst within an interval, in EP companion desc. */
728 #define EP_MULT(p) (((p) & 0x3) << 8)
729 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
730 /* bits 10:14 are Max Primary Streams */
731 /* bit 15 is Linear Stream Array */
732 /* Interval - period between requests to an endpoint - 125u increments. */
733 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
734 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
735 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
736 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
737 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
738 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
739 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
740 #define EP_HAS_LSA (1 << 15)
741 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
742 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
744 /* ep_info2 bitmasks */
746 * Force Event - generate transfer events for all TRBs for this endpoint
747 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
749 #define FORCE_EVENT (0x1)
750 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
751 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
752 #define EP_TYPE(p) ((p) << 3)
753 #define ISOC_OUT_EP 1
754 #define BULK_OUT_EP 2
761 /* bit 7 is Host Initiate Disable - for disabling stream selection */
762 #define MAX_BURST(p) (((p)&0xff) << 8)
763 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
764 #define MAX_PACKET(p) (((p)&0xffff) << 16)
765 #define MAX_PACKET_MASK (0xffff << 16)
766 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
768 /* tx_info bitmasks */
769 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
770 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
771 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
772 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
775 #define EP_CTX_CYCLE_MASK (1 << 0)
776 #define SCTX_DEQ_MASK (~0xfL)
780 * struct xhci_input_control_context
781 * Input control context; see section 6.2.5.
783 * @drop_context: set the bit of the endpoint context you want to disable
784 * @add_context: set the bit of the endpoint context you want to enable
786 struct xhci_input_control_ctx {
792 #define EP_IS_ADDED(ctrl_ctx, i) \
793 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
794 #define EP_IS_DROPPED(ctrl_ctx, i) \
795 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
797 /* Represents everything that is needed to issue a command on the command ring.
798 * It's useful to pre-allocate these for commands that cannot fail due to
799 * out-of-memory errors, like freeing streams.
801 struct xhci_command {
802 /* Input context for changing device state */
803 struct xhci_container_ctx *in_ctx;
806 /* If completion is null, no one is waiting on this command
807 * and the structure can be freed after the command completes.
809 struct completion *completion;
810 union xhci_trb *command_trb;
811 struct list_head cmd_list;
814 /* drop context bitmasks */
815 #define DROP_EP(x) (0x1 << x)
816 /* add context bitmasks */
817 #define ADD_EP(x) (0x1 << x)
819 struct xhci_stream_ctx {
820 /* 64-bit stream ring address, cycle state, and stream type */
822 /* offset 0x14 - 0x1f reserved for HC internal use */
826 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
827 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
828 /* Secondary stream array type, dequeue pointer is to a transfer ring */
830 /* Primary stream array type, dequeue pointer is to a transfer ring */
832 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
837 #define SCT_SSA_128 6
838 #define SCT_SSA_256 7
840 /* Assume no secondary streams for now */
841 struct xhci_stream_info {
842 struct xhci_ring **stream_rings;
843 /* Number of streams, including stream 0 (which drivers can't use) */
844 unsigned int num_streams;
845 /* The stream context array may be bigger than
846 * the number of streams the driver asked for
848 struct xhci_stream_ctx *stream_ctx_array;
849 unsigned int num_stream_ctxs;
850 dma_addr_t ctx_array_dma;
851 /* For mapping physical TRB addresses to segments in stream rings */
852 struct radix_tree_root trb_address_map;
853 struct xhci_command *free_streams_command;
856 #define SMALL_STREAM_ARRAY_SIZE 256
857 #define MEDIUM_STREAM_ARRAY_SIZE 1024
859 /* Some Intel xHCI host controllers need software to keep track of the bus
860 * bandwidth. Keep track of endpoint info here. Each root port is allocated
861 * the full bus bandwidth. We must also treat TTs (including each port under a
862 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
863 * (DMI) also limits the total bandwidth (across all domains) that can be used.
865 struct xhci_bw_info {
866 /* ep_interval is zero-based */
867 unsigned int ep_interval;
868 /* mult and num_packets are one-based */
870 unsigned int num_packets;
871 unsigned int max_packet_size;
872 unsigned int max_esit_payload;
876 /* "Block" sizes in bytes the hardware uses for different device speeds.
877 * The logic in this part of the hardware limits the number of bits the hardware
878 * can use, so must represent bandwidth in a less precise manner to mimic what
879 * the scheduler hardware computes.
886 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
887 * with each byte transferred. SuperSpeed devices have an initial overhead to
888 * set up bursts. These are in blocks, see above. LS overhead has already been
889 * translated into FS blocks.
891 #define DMI_OVERHEAD 8
892 #define DMI_OVERHEAD_BURST 4
893 #define SS_OVERHEAD 8
894 #define SS_OVERHEAD_BURST 32
895 #define HS_OVERHEAD 26
896 #define FS_OVERHEAD 20
897 #define LS_OVERHEAD 128
898 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
899 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
900 * of overhead associated with split transfers crossing microframe boundaries.
901 * 31 blocks is pure protocol overhead.
903 #define TT_HS_OVERHEAD (31 + 94)
904 #define TT_DMI_OVERHEAD (25 + 12)
906 /* Bandwidth limits in blocks */
907 #define FS_BW_LIMIT 1285
908 #define TT_BW_LIMIT 1320
909 #define HS_BW_LIMIT 1607
910 #define SS_BW_LIMIT_IN 3906
911 #define DMI_BW_LIMIT_IN 3906
912 #define SS_BW_LIMIT_OUT 3906
913 #define DMI_BW_LIMIT_OUT 3906
915 /* Percentage of bus bandwidth reserved for non-periodic transfers */
916 #define FS_BW_RESERVED 10
917 #define HS_BW_RESERVED 20
918 #define SS_BW_RESERVED 10
920 struct xhci_virt_ep {
921 struct xhci_ring *ring;
922 /* Related to endpoints that are configured to use stream IDs only */
923 struct xhci_stream_info *stream_info;
924 /* Temporary storage in case the configure endpoint command fails and we
925 * have to restore the device state to the previous state
927 struct xhci_ring *new_ring;
928 unsigned int ep_state;
929 #define SET_DEQ_PENDING (1 << 0)
930 #define EP_HALTED (1 << 1) /* For stall handling */
931 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
932 /* Transitioning the endpoint to using streams, don't enqueue URBs */
933 #define EP_GETTING_STREAMS (1 << 3)
934 #define EP_HAS_STREAMS (1 << 4)
935 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
936 #define EP_GETTING_NO_STREAMS (1 << 5)
937 #define EP_HARD_CLEAR_TOGGLE (1 << 6)
938 #define EP_SOFT_CLEAR_TOGGLE (1 << 7)
939 /* ---- Related to URB cancellation ---- */
940 struct list_head cancelled_td_list;
941 /* Watchdog timer for stop endpoint command to cancel URBs */
942 struct timer_list stop_cmd_timer;
943 struct xhci_hcd *xhci;
944 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
945 * command. We'll need to update the ring's dequeue segment and dequeue
946 * pointer after the command completes.
948 struct xhci_segment *queued_deq_seg;
949 union xhci_trb *queued_deq_ptr;
951 * Sometimes the xHC can not process isochronous endpoint ring quickly
952 * enough, and it will miss some isoc tds on the ring and generate
953 * a Missed Service Error Event.
954 * Set skip flag when receive a Missed Service Error Event and
955 * process the missed tds on the endpoint ring.
958 /* Bandwidth checking storage */
959 struct xhci_bw_info bw_info;
960 struct list_head bw_endpoint_list;
961 /* Isoch Frame ID checking storage */
963 /* Use new Isoch TRB layout needed for extended TBC support */
964 bool use_extended_tbc;
967 enum xhci_overhead_type {
968 LS_OVERHEAD_TYPE = 0,
973 struct xhci_interval_bw {
974 unsigned int num_packets;
975 /* Sorted by max packet size.
976 * Head of the list is the greatest max packet size.
978 struct list_head endpoints;
979 /* How many endpoints of each speed are present. */
980 unsigned int overhead[3];
983 #define XHCI_MAX_INTERVAL 16
985 struct xhci_interval_bw_table {
986 unsigned int interval0_esit_payload;
987 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
988 /* Includes reserved bandwidth for async endpoints */
989 unsigned int bw_used;
990 unsigned int ss_bw_in;
991 unsigned int ss_bw_out;
995 struct xhci_virt_device {
996 struct usb_device *udev;
998 * Commands to the hardware are passed an "input context" that
999 * tells the hardware what to change in its data structures.
1000 * The hardware will return changes in an "output context" that
1001 * software must allocate for the hardware. We need to keep
1002 * track of input and output contexts separately because
1003 * these commands might fail and we don't trust the hardware.
1005 struct xhci_container_ctx *out_ctx;
1006 /* Used for addressing devices and configuration changes */
1007 struct xhci_container_ctx *in_ctx;
1008 struct xhci_virt_ep eps[31];
1011 struct xhci_interval_bw_table *bw_table;
1012 struct xhci_tt_bw_info *tt_info;
1013 /* The current max exit latency for the enabled USB3 link states. */
1015 /* Used for the debugfs interfaces. */
1016 void *debugfs_private;
1020 * For each roothub, keep track of the bandwidth information for each periodic
1023 * If a high speed hub is attached to the roothub, each TT associated with that
1024 * hub is a separate bandwidth domain. The interval information for the
1025 * endpoints on the devices under that TT will appear in the TT structure.
1027 struct xhci_root_port_bw_info {
1028 struct list_head tts;
1029 unsigned int num_active_tts;
1030 struct xhci_interval_bw_table bw_table;
1033 struct xhci_tt_bw_info {
1034 struct list_head tt_list;
1037 struct xhci_interval_bw_table bw_table;
1043 * struct xhci_device_context_array
1044 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1046 struct xhci_device_context_array {
1047 /* 64-bit device addresses; we only write 32-bit addresses */
1048 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1049 /* private xHCD pointers */
1052 /* TODO: write function to set the 64-bit device DMA address */
1054 * TODO: change this to be dynamically sized at HC mem init time since the HC
1055 * might not be able to handle the maximum number of devices possible.
1059 struct xhci_transfer_event {
1060 /* 64-bit buffer address, or immediate data */
1062 __le32 transfer_len;
1063 /* This field is interpreted differently based on the type of TRB */
1067 /* Transfer event TRB length bit mask */
1069 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1071 /** Transfer Event bit fields **/
1072 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1074 /* Completion Code - only applicable for some types of TRBs */
1075 #define COMP_CODE_MASK (0xff << 24)
1076 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1077 #define COMP_INVALID 0
1078 #define COMP_SUCCESS 1
1079 #define COMP_DATA_BUFFER_ERROR 2
1080 #define COMP_BABBLE_DETECTED_ERROR 3
1081 #define COMP_USB_TRANSACTION_ERROR 4
1082 #define COMP_TRB_ERROR 5
1083 #define COMP_STALL_ERROR 6
1084 #define COMP_RESOURCE_ERROR 7
1085 #define COMP_BANDWIDTH_ERROR 8
1086 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1087 #define COMP_INVALID_STREAM_TYPE_ERROR 10
1088 #define COMP_SLOT_NOT_ENABLED_ERROR 11
1089 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1090 #define COMP_SHORT_PACKET 13
1091 #define COMP_RING_UNDERRUN 14
1092 #define COMP_RING_OVERRUN 15
1093 #define COMP_VF_EVENT_RING_FULL_ERROR 16
1094 #define COMP_PARAMETER_ERROR 17
1095 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
1096 #define COMP_CONTEXT_STATE_ERROR 19
1097 #define COMP_NO_PING_RESPONSE_ERROR 20
1098 #define COMP_EVENT_RING_FULL_ERROR 21
1099 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1100 #define COMP_MISSED_SERVICE_ERROR 23
1101 #define COMP_COMMAND_RING_STOPPED 24
1102 #define COMP_COMMAND_ABORTED 25
1103 #define COMP_STOPPED 26
1104 #define COMP_STOPPED_LENGTH_INVALID 27
1105 #define COMP_STOPPED_SHORT_PACKET 28
1106 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1107 #define COMP_ISOCH_BUFFER_OVERRUN 31
1108 #define COMP_EVENT_LOST_ERROR 32
1109 #define COMP_UNDEFINED_ERROR 33
1110 #define COMP_INVALID_STREAM_ID_ERROR 34
1111 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
1112 #define COMP_SPLIT_TRANSACTION_ERROR 36
1114 static inline const char *xhci_trb_comp_code_string(u8 status)
1121 case COMP_DATA_BUFFER_ERROR:
1122 return "Data Buffer Error";
1123 case COMP_BABBLE_DETECTED_ERROR:
1124 return "Babble Detected";
1125 case COMP_USB_TRANSACTION_ERROR:
1126 return "USB Transaction Error";
1127 case COMP_TRB_ERROR:
1129 case COMP_STALL_ERROR:
1130 return "Stall Error";
1131 case COMP_RESOURCE_ERROR:
1132 return "Resource Error";
1133 case COMP_BANDWIDTH_ERROR:
1134 return "Bandwidth Error";
1135 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1136 return "No Slots Available Error";
1137 case COMP_INVALID_STREAM_TYPE_ERROR:
1138 return "Invalid Stream Type Error";
1139 case COMP_SLOT_NOT_ENABLED_ERROR:
1140 return "Slot Not Enabled Error";
1141 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1142 return "Endpoint Not Enabled Error";
1143 case COMP_SHORT_PACKET:
1144 return "Short Packet";
1145 case COMP_RING_UNDERRUN:
1146 return "Ring Underrun";
1147 case COMP_RING_OVERRUN:
1148 return "Ring Overrun";
1149 case COMP_VF_EVENT_RING_FULL_ERROR:
1150 return "VF Event Ring Full Error";
1151 case COMP_PARAMETER_ERROR:
1152 return "Parameter Error";
1153 case COMP_BANDWIDTH_OVERRUN_ERROR:
1154 return "Bandwidth Overrun Error";
1155 case COMP_CONTEXT_STATE_ERROR:
1156 return "Context State Error";
1157 case COMP_NO_PING_RESPONSE_ERROR:
1158 return "No Ping Response Error";
1159 case COMP_EVENT_RING_FULL_ERROR:
1160 return "Event Ring Full Error";
1161 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1162 return "Incompatible Device Error";
1163 case COMP_MISSED_SERVICE_ERROR:
1164 return "Missed Service Error";
1165 case COMP_COMMAND_RING_STOPPED:
1166 return "Command Ring Stopped";
1167 case COMP_COMMAND_ABORTED:
1168 return "Command Aborted";
1171 case COMP_STOPPED_LENGTH_INVALID:
1172 return "Stopped - Length Invalid";
1173 case COMP_STOPPED_SHORT_PACKET:
1174 return "Stopped - Short Packet";
1175 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1176 return "Max Exit Latency Too Large Error";
1177 case COMP_ISOCH_BUFFER_OVERRUN:
1178 return "Isoch Buffer Overrun";
1179 case COMP_EVENT_LOST_ERROR:
1180 return "Event Lost Error";
1181 case COMP_UNDEFINED_ERROR:
1182 return "Undefined Error";
1183 case COMP_INVALID_STREAM_ID_ERROR:
1184 return "Invalid Stream ID Error";
1185 case COMP_SECONDARY_BANDWIDTH_ERROR:
1186 return "Secondary Bandwidth Error";
1187 case COMP_SPLIT_TRANSACTION_ERROR:
1188 return "Split Transaction Error";
1194 struct xhci_link_trb {
1195 /* 64-bit segment pointer*/
1201 /* control bitfields */
1202 #define LINK_TOGGLE (0x1<<1)
1204 /* Command completion event TRB */
1205 struct xhci_event_cmd {
1206 /* Pointer to command TRB, or the value passed by the event data trb */
1212 /* flags bitmasks */
1214 /* Address device - disable SetAddress */
1215 #define TRB_BSR (1<<9)
1217 /* Configure Endpoint - Deconfigure */
1218 #define TRB_DC (1<<9)
1220 /* Stop Ring - Transfer State Preserve */
1221 #define TRB_TSP (1<<9)
1223 enum xhci_ep_reset_type {
1229 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1230 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1232 /* Set Latency Tolerance Value */
1233 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1235 /* Get Port Bandwidth */
1236 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1239 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1240 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1242 enum xhci_setup_dev {
1244 SETUP_CONTEXT_ADDRESS,
1247 /* bits 16:23 are the virtual function ID */
1248 /* bits 24:31 are the slot ID */
1249 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1250 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1252 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1253 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1254 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1256 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1257 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1258 #define LAST_EP_INDEX 30
1260 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1261 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1262 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1263 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1265 /* Link TRB specific fields */
1266 #define TRB_TC (1<<1)
1268 /* Port Status Change Event TRB fields */
1269 /* Port ID - bits 31:24 */
1270 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1272 #define EVENT_DATA (1 << 2)
1274 /* Normal TRB fields */
1275 /* transfer_len bitmasks - bits 0:16 */
1276 #define TRB_LEN(p) ((p) & 0x1ffff)
1277 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1278 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1279 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1280 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1281 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1282 /* Interrupter Target - which MSI-X vector to target the completion event at */
1283 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1284 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1285 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1286 #define TRB_TBC(p) (((p) & 0x3) << 7)
1287 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1289 /* Cycle bit - indicates TRB ownership by HC or HCD */
1290 #define TRB_CYCLE (1<<0)
1292 * Force next event data TRB to be evaluated before task switch.
1293 * Used to pass OS data back after a TD completes.
1295 #define TRB_ENT (1<<1)
1296 /* Interrupt on short packet */
1297 #define TRB_ISP (1<<2)
1298 /* Set PCIe no snoop attribute */
1299 #define TRB_NO_SNOOP (1<<3)
1300 /* Chain multiple TRBs into a TD */
1301 #define TRB_CHAIN (1<<4)
1302 /* Interrupt on completion */
1303 #define TRB_IOC (1<<5)
1304 /* The buffer pointer contains immediate data */
1305 #define TRB_IDT (1<<6)
1307 /* Block Event Interrupt */
1308 #define TRB_BEI (1<<9)
1310 /* Control transfer TRB specific fields */
1311 #define TRB_DIR_IN (1<<16)
1312 #define TRB_TX_TYPE(p) ((p) << 16)
1313 #define TRB_DATA_OUT 2
1314 #define TRB_DATA_IN 3
1316 /* Isochronous TRB specific fields */
1317 #define TRB_SIA (1<<31)
1318 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1320 struct xhci_generic_trb {
1325 struct xhci_link_trb link;
1326 struct xhci_transfer_event trans_event;
1327 struct xhci_event_cmd event_cmd;
1328 struct xhci_generic_trb generic;
1332 #define TRB_TYPE_BITMASK (0xfc00)
1333 #define TRB_TYPE(p) ((p) << 10)
1334 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1336 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1337 #define TRB_NORMAL 1
1338 /* setup stage for control transfers */
1340 /* data stage for control transfers */
1342 /* status stage for control transfers */
1343 #define TRB_STATUS 4
1344 /* isoc transfers */
1346 /* TRB for linking ring segments */
1348 #define TRB_EVENT_DATA 7
1349 /* Transfer Ring No-op (not for the command ring) */
1350 #define TRB_TR_NOOP 8
1352 /* Enable Slot Command */
1353 #define TRB_ENABLE_SLOT 9
1354 /* Disable Slot Command */
1355 #define TRB_DISABLE_SLOT 10
1356 /* Address Device Command */
1357 #define TRB_ADDR_DEV 11
1358 /* Configure Endpoint Command */
1359 #define TRB_CONFIG_EP 12
1360 /* Evaluate Context Command */
1361 #define TRB_EVAL_CONTEXT 13
1362 /* Reset Endpoint Command */
1363 #define TRB_RESET_EP 14
1364 /* Stop Transfer Ring Command */
1365 #define TRB_STOP_RING 15
1366 /* Set Transfer Ring Dequeue Pointer Command */
1367 #define TRB_SET_DEQ 16
1368 /* Reset Device Command */
1369 #define TRB_RESET_DEV 17
1370 /* Force Event Command (opt) */
1371 #define TRB_FORCE_EVENT 18
1372 /* Negotiate Bandwidth Command (opt) */
1373 #define TRB_NEG_BANDWIDTH 19
1374 /* Set Latency Tolerance Value Command (opt) */
1375 #define TRB_SET_LT 20
1376 /* Get port bandwidth Command */
1377 #define TRB_GET_BW 21
1378 /* Force Header Command - generate a transaction or link management packet */
1379 #define TRB_FORCE_HEADER 22
1380 /* No-op Command - not for transfer rings */
1381 #define TRB_CMD_NOOP 23
1382 /* TRB IDs 24-31 reserved */
1384 /* Transfer Event */
1385 #define TRB_TRANSFER 32
1386 /* Command Completion Event */
1387 #define TRB_COMPLETION 33
1388 /* Port Status Change Event */
1389 #define TRB_PORT_STATUS 34
1390 /* Bandwidth Request Event (opt) */
1391 #define TRB_BANDWIDTH_EVENT 35
1392 /* Doorbell Event (opt) */
1393 #define TRB_DOORBELL 36
1394 /* Host Controller Event */
1395 #define TRB_HC_EVENT 37
1396 /* Device Notification Event - device sent function wake notification */
1397 #define TRB_DEV_NOTE 38
1398 /* MFINDEX Wrap Event - microframe counter wrapped */
1399 #define TRB_MFINDEX_WRAP 39
1400 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1402 /* Nec vendor-specific command completion event. */
1403 #define TRB_NEC_CMD_COMP 48
1404 /* Get NEC firmware revision. */
1405 #define TRB_NEC_GET_FW 49
1407 static inline const char *xhci_trb_type_string(u8 type)
1413 return "Setup Stage";
1415 return "Data Stage";
1417 return "Status Stage";
1422 case TRB_EVENT_DATA:
1423 return "Event Data";
1426 case TRB_ENABLE_SLOT:
1427 return "Enable Slot Command";
1428 case TRB_DISABLE_SLOT:
1429 return "Disable Slot Command";
1431 return "Address Device Command";
1433 return "Configure Endpoint Command";
1434 case TRB_EVAL_CONTEXT:
1435 return "Evaluate Context Command";
1437 return "Reset Endpoint Command";
1439 return "Stop Ring Command";
1441 return "Set TR Dequeue Pointer Command";
1443 return "Reset Device Command";
1444 case TRB_FORCE_EVENT:
1445 return "Force Event Command";
1446 case TRB_NEG_BANDWIDTH:
1447 return "Negotiate Bandwidth Command";
1449 return "Set Latency Tolerance Value Command";
1451 return "Get Port Bandwidth Command";
1452 case TRB_FORCE_HEADER:
1453 return "Force Header Command";
1455 return "No-Op Command";
1457 return "Transfer Event";
1458 case TRB_COMPLETION:
1459 return "Command Completion Event";
1460 case TRB_PORT_STATUS:
1461 return "Port Status Change Event";
1462 case TRB_BANDWIDTH_EVENT:
1463 return "Bandwidth Request Event";
1465 return "Doorbell Event";
1467 return "Host Controller Event";
1469 return "Device Notification Event";
1470 case TRB_MFINDEX_WRAP:
1471 return "MFINDEX Wrap Event";
1472 case TRB_NEC_CMD_COMP:
1473 return "NEC Command Completion Event";
1474 case TRB_NEC_GET_FW:
1475 return "NET Get Firmware Revision Command";
1481 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1482 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1483 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1484 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1485 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1486 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1488 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1489 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1492 * TRBS_PER_SEGMENT must be a multiple of 4,
1493 * since the command ring is 64-byte aligned.
1494 * It must also be greater than 16.
1496 #define TRBS_PER_SEGMENT 256
1497 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1498 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1499 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1500 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1501 /* TRB buffer pointers can't cross 64KB boundaries */
1502 #define TRB_MAX_BUFF_SHIFT 16
1503 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1504 /* How much data is left before the 64KB boundary? */
1505 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1506 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1507 #define MAX_SOFT_RETRY 3
1509 struct xhci_segment {
1510 union xhci_trb *trbs;
1511 /* private to HCD */
1512 struct xhci_segment *next;
1514 /* Max packet sized bounce buffer for td-fragmant alignment */
1515 dma_addr_t bounce_dma;
1517 unsigned int bounce_offs;
1518 unsigned int bounce_len;
1522 struct list_head td_list;
1523 struct list_head cancelled_td_list;
1525 struct xhci_segment *start_seg;
1526 union xhci_trb *first_trb;
1527 union xhci_trb *last_trb;
1528 struct xhci_segment *bounce_seg;
1529 /* actual_length of the URB has already been set */
1530 bool urb_length_set;
1533 /* xHCI command default timeout value */
1534 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1536 /* command descriptor */
1538 struct xhci_command *command;
1539 union xhci_trb *cmd_trb;
1542 struct xhci_dequeue_state {
1543 struct xhci_segment *new_deq_seg;
1544 union xhci_trb *new_deq_ptr;
1545 int new_cycle_state;
1546 unsigned int stream_id;
1549 enum xhci_ring_type {
1559 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1582 struct xhci_segment *first_seg;
1583 struct xhci_segment *last_seg;
1584 union xhci_trb *enqueue;
1585 struct xhci_segment *enq_seg;
1586 union xhci_trb *dequeue;
1587 struct xhci_segment *deq_seg;
1588 struct list_head td_list;
1590 * Write the cycle state into the TRB cycle field to give ownership of
1591 * the TRB to the host controller (if we are the producer), or to check
1592 * if we own the TRB (if we are the consumer). See section 4.9.1.
1595 unsigned int err_count;
1596 unsigned int stream_id;
1597 unsigned int num_segs;
1598 unsigned int num_trbs_free;
1599 unsigned int num_trbs_free_temp;
1600 unsigned int bounce_buf_len;
1601 enum xhci_ring_type type;
1602 bool last_td_was_short;
1603 struct radix_tree_root *trb_address_map;
1606 struct xhci_erst_entry {
1607 /* 64-bit event ring segment address */
1615 struct xhci_erst_entry *entries;
1616 unsigned int num_entries;
1617 /* xhci->event_ring keeps track of segment dma addresses */
1618 dma_addr_t erst_dma_addr;
1619 /* Num entries the ERST can contain */
1620 unsigned int erst_size;
1623 struct xhci_scratchpad {
1632 struct xhci_td td[0];
1636 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1637 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1638 * meaning 64 ring segments.
1639 * Initial allocated size of the ERST, in number of entries */
1640 #define ERST_NUM_SEGS 1
1641 /* Initial allocated size of the ERST, in number of entries */
1642 #define ERST_SIZE 64
1643 /* Initial number of event segment rings allocated */
1644 #define ERST_ENTRIES 1
1645 /* Poll every 60 seconds */
1646 #define POLL_TIMEOUT 60
1647 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1648 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1649 /* XXX: Make these module parameters */
1666 struct list_head list;
1669 struct xhci_bus_state {
1670 unsigned long bus_suspended;
1671 unsigned long next_statechange;
1673 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1674 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1676 u32 suspended_ports;
1677 u32 port_remote_wakeup;
1678 unsigned long resume_done[USB_MAXCHILDREN];
1679 /* which ports have started to resume */
1680 unsigned long resuming_ports;
1681 /* Which ports are waiting on RExit to U0 transition. */
1682 unsigned long rexit_ports;
1683 struct completion rexit_done[USB_MAXCHILDREN];
1688 * It can take up to 20 ms to transition from RExit to U0 on the
1689 * Intel Lynx Point LP xHCI host.
1691 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1694 __le32 __iomem *addr;
1697 struct xhci_hub *rhub;
1701 struct xhci_port **ports;
1702 unsigned int num_ports;
1703 struct usb_hcd *hcd;
1704 /* keep track of bus suspend info */
1705 struct xhci_bus_state bus_state;
1706 /* supported prococol extended capabiliy values */
1709 u32 *psi; /* array of protocol speed ID entries */
1714 /* There is one xhci_hcd structure per controller */
1716 struct usb_hcd *main_hcd;
1717 struct usb_hcd *shared_hcd;
1718 /* glue to PCI and HCD framework */
1719 struct xhci_cap_regs __iomem *cap_regs;
1720 struct xhci_op_regs __iomem *op_regs;
1721 struct xhci_run_regs __iomem *run_regs;
1722 struct xhci_doorbell_array __iomem *dba;
1723 /* Our HCD's current interrupter register set */
1724 struct xhci_intr_reg __iomem *ir_set;
1726 /* Cached register copies of read-only HC data */
1735 /* packed release number */
1739 u8 max_interrupters;
1742 /* imod_interval in ns (I * 250ns) */
1745 /* 4KB min, 128MB max */
1747 /* Valid values are 12 to 20, inclusive */
1751 /* optional clocks */
1753 struct clk *reg_clk;
1754 /* data structures */
1755 struct xhci_device_context_array *dcbaa;
1756 struct xhci_ring *cmd_ring;
1757 unsigned int cmd_ring_state;
1758 #define CMD_RING_STATE_RUNNING (1 << 0)
1759 #define CMD_RING_STATE_ABORTED (1 << 1)
1760 #define CMD_RING_STATE_STOPPED (1 << 2)
1761 struct list_head cmd_list;
1762 unsigned int cmd_ring_reserved_trbs;
1763 struct delayed_work cmd_timer;
1764 struct completion cmd_ring_stop_completion;
1765 struct xhci_command *current_cmd;
1766 struct xhci_ring *event_ring;
1767 struct xhci_erst erst;
1769 struct xhci_scratchpad *scratchpad;
1770 /* Store LPM test failed devices' information */
1771 struct list_head lpm_failed_devs;
1773 /* slot enabling and address device helpers */
1774 /* these are not thread safe so use mutex */
1776 /* For USB 3.0 LPM enable/disable. */
1777 struct xhci_command *lpm_command;
1778 /* Internal mirror of the HW's dcbaa */
1779 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1780 /* For keeping track of bandwidth domains per roothub. */
1781 struct xhci_root_port_bw_info *rh_bw;
1784 struct dma_pool *device_pool;
1785 struct dma_pool *segment_pool;
1786 struct dma_pool *small_streams_pool;
1787 struct dma_pool *medium_streams_pool;
1789 /* Host controller watchdog timer structures */
1790 unsigned int xhc_state;
1794 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1796 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1797 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1798 * that sees this status (other than the timer that set it) should stop touching
1799 * hardware immediately. Interrupt handlers should return immediately when
1800 * they see this status (any time they drop and re-acquire xhci->lock).
1801 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1802 * putting the TD on the canceled list, etc.
1804 * There are no reports of xHCI host controllers that display this issue.
1806 #define XHCI_STATE_DYING (1 << 0)
1807 #define XHCI_STATE_HALTED (1 << 1)
1808 #define XHCI_STATE_REMOVING (1 << 2)
1809 unsigned long long quirks;
1810 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1811 #define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1812 #define XHCI_NEC_HOST BIT_ULL(2)
1813 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1814 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1816 * Certain Intel host controllers have a limit to the number of endpoint
1817 * contexts they can handle. Ideally, they would signal that they can't handle
1818 * anymore endpoint contexts by returning a Resource Error for the Configure
1819 * Endpoint command, but they don't. Instead they expect software to keep track
1820 * of the number of active endpoints for them, across configure endpoint
1821 * commands, reset device commands, disable slot commands, and address device
1824 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1825 #define XHCI_BROKEN_MSI BIT_ULL(6)
1826 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1827 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1828 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1829 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1830 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1831 #define XHCI_INTEL_HOST BIT_ULL(12)
1832 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1833 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1834 #define XHCI_AVOID_BEI BIT_ULL(15)
1835 #define XHCI_PLAT BIT_ULL(16)
1836 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1837 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1838 /* For controllers with a broken beyond repair streams implementation */
1839 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1840 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1841 #define XHCI_MTK_HOST BIT_ULL(21)
1842 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1843 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1844 #define XHCI_MISSING_CAS BIT_ULL(24)
1845 /* For controller with a broken Port Disable implementation */
1846 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1847 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1848 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1849 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1850 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1851 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1852 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1853 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
1854 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1855 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1856 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1858 unsigned int num_active_eps;
1859 unsigned int limit_active_eps;
1860 struct xhci_port *hw_ports;
1861 struct xhci_hub usb2_rhub;
1862 struct xhci_hub usb3_rhub;
1863 /* support xHCI 1.0 spec USB2 hardware LPM */
1864 unsigned hw_lpm_support:1;
1865 /* Broken Suspend flag for SNPS Suspend resume issue */
1866 unsigned broken_suspend:1;
1867 /* cached usb2 extened protocol capabilites */
1869 unsigned int num_ext_caps;
1870 /* Compliance Mode Recovery Data */
1871 struct timer_list comp_mode_recovery_timer;
1874 /* Compliance Mode Timer Triggered every 2 seconds */
1875 #define COMP_MODE_RCVRY_MSECS 2000
1877 struct dentry *debugfs_root;
1878 struct dentry *debugfs_slots;
1879 struct list_head regset_list;
1882 /* platform-specific data -- must come last */
1883 unsigned long priv[0] __aligned(sizeof(s64));
1886 /* Platform specific overrides to generic XHCI hc_driver ops */
1887 struct xhci_driver_overrides {
1888 size_t extra_priv_size;
1889 int (*reset)(struct usb_hcd *hcd);
1890 int (*start)(struct usb_hcd *hcd);
1893 #define XHCI_CFC_DELAY 10
1895 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1896 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1898 struct usb_hcd *primary_hcd;
1900 if (usb_hcd_is_primary_hcd(hcd))
1903 primary_hcd = hcd->primary_hcd;
1905 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1908 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1910 return xhci->main_hcd;
1913 #define xhci_dbg(xhci, fmt, args...) \
1914 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1915 #define xhci_err(xhci, fmt, args...) \
1916 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1917 #define xhci_warn(xhci, fmt, args...) \
1918 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1919 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1920 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1921 #define xhci_info(xhci, fmt, args...) \
1922 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1925 * Registers should always be accessed with double word or quad word accesses.
1927 * Some xHCI implementations may support 64-bit address pointers. Registers
1928 * with 64-bit address pointers should be written to with dword accesses by
1929 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1930 * xHCI implementations that do not support 64-bit address pointers will ignore
1931 * the high dword, and write order is irrelevant.
1933 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1934 __le64 __iomem *regs)
1936 return lo_hi_readq(regs);
1938 static inline void xhci_write_64(struct xhci_hcd *xhci,
1939 const u64 val, __le64 __iomem *regs)
1941 lo_hi_writeq(val, regs);
1944 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1946 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1949 /* xHCI debugging */
1950 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1951 struct xhci_container_ctx *ctx);
1952 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1953 const char *fmt, ...);
1955 /* xHCI memory management */
1956 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1957 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1958 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1959 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1960 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1961 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1962 struct usb_device *udev);
1963 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1964 unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1965 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1966 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1967 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1968 struct xhci_virt_device *virt_dev,
1969 int old_active_eps);
1970 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1971 void xhci_update_bw_info(struct xhci_hcd *xhci,
1972 struct xhci_container_ctx *in_ctx,
1973 struct xhci_input_control_ctx *ctrl_ctx,
1974 struct xhci_virt_device *virt_dev);
1975 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1976 struct xhci_container_ctx *in_ctx,
1977 struct xhci_container_ctx *out_ctx,
1978 unsigned int ep_index);
1979 void xhci_slot_copy(struct xhci_hcd *xhci,
1980 struct xhci_container_ctx *in_ctx,
1981 struct xhci_container_ctx *out_ctx);
1982 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1983 struct usb_device *udev, struct usb_host_endpoint *ep,
1985 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
1986 unsigned int num_segs, unsigned int cycle_state,
1987 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
1988 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1989 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1990 unsigned int num_trbs, gfp_t flags);
1991 int xhci_alloc_erst(struct xhci_hcd *xhci,
1992 struct xhci_ring *evt_ring,
1993 struct xhci_erst *erst,
1995 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1996 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1997 struct xhci_virt_device *virt_dev,
1998 unsigned int ep_index);
1999 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2000 unsigned int num_stream_ctxs,
2001 unsigned int num_streams,
2002 unsigned int max_packet, gfp_t flags);
2003 void xhci_free_stream_info(struct xhci_hcd *xhci,
2004 struct xhci_stream_info *stream_info);
2005 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2006 struct xhci_ep_ctx *ep_ctx,
2007 struct xhci_stream_info *stream_info);
2008 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2009 struct xhci_virt_ep *ep);
2010 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2011 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2012 struct xhci_ring *xhci_dma_to_transfer_ring(
2013 struct xhci_virt_ep *ep,
2015 struct xhci_ring *xhci_stream_id_to_ring(
2016 struct xhci_virt_device *dev,
2017 unsigned int ep_index,
2018 unsigned int stream_id);
2019 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2020 bool allocate_completion, gfp_t mem_flags);
2021 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2022 bool allocate_completion, gfp_t mem_flags);
2023 void xhci_urb_free_priv(struct urb_priv *urb_priv);
2024 void xhci_free_command(struct xhci_hcd *xhci,
2025 struct xhci_command *command);
2026 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2027 int type, gfp_t flags);
2028 void xhci_free_container_ctx(struct xhci_hcd *xhci,
2029 struct xhci_container_ctx *ctx);
2031 /* xHCI host controller glue */
2032 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2033 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
2034 void xhci_quiesce(struct xhci_hcd *xhci);
2035 int xhci_halt(struct xhci_hcd *xhci);
2036 int xhci_start(struct xhci_hcd *xhci);
2037 int xhci_reset(struct xhci_hcd *xhci);
2038 int xhci_run(struct usb_hcd *hcd);
2039 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2040 void xhci_init_driver(struct hc_driver *drv,
2041 const struct xhci_driver_overrides *over);
2042 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2043 int xhci_ext_cap_init(struct xhci_hcd *xhci);
2045 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2046 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2048 irqreturn_t xhci_irq(struct usb_hcd *hcd);
2049 irqreturn_t xhci_msi_irq(int irq, void *hcd);
2050 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2051 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2052 struct xhci_virt_device *virt_dev,
2053 struct usb_device *hdev,
2054 struct usb_tt *tt, gfp_t mem_flags);
2056 /* xHCI ring, segment, TRB, and TD functions */
2057 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2058 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2059 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2060 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2061 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2062 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2063 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2064 u32 trb_type, u32 slot_id);
2065 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2066 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2067 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2068 u32 field1, u32 field2, u32 field3, u32 field4);
2069 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2070 int slot_id, unsigned int ep_index, int suspend);
2071 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2072 int slot_id, unsigned int ep_index);
2073 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2074 int slot_id, unsigned int ep_index);
2075 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2076 int slot_id, unsigned int ep_index);
2077 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2078 struct urb *urb, int slot_id, unsigned int ep_index);
2079 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2080 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2081 bool command_must_succeed);
2082 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2083 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2084 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2085 int slot_id, unsigned int ep_index,
2086 enum xhci_ep_reset_type reset_type);
2087 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2089 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
2090 unsigned int slot_id, unsigned int ep_index,
2091 unsigned int stream_id, struct xhci_td *cur_td,
2092 struct xhci_dequeue_state *state);
2093 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
2094 unsigned int slot_id, unsigned int ep_index,
2095 struct xhci_dequeue_state *deq_state);
2096 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2097 unsigned int stream_id, struct xhci_td *td);
2098 void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2099 void xhci_handle_command_timeout(struct work_struct *work);
2101 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2102 unsigned int ep_index, unsigned int stream_id);
2103 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2104 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2105 unsigned int count_trbs(u64 addr, u64 len);
2107 /* xHCI roothub code */
2108 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2110 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2112 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2113 char *buf, u16 wLength);
2114 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2115 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2116 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2118 void xhci_hc_died(struct xhci_hcd *xhci);
2121 int xhci_bus_suspend(struct usb_hcd *hcd);
2122 int xhci_bus_resume(struct usb_hcd *hcd);
2123 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2125 #define xhci_bus_suspend NULL
2126 #define xhci_bus_resume NULL
2127 #define xhci_get_resuming_ports NULL
2128 #endif /* CONFIG_PM */
2130 u32 xhci_port_state_to_neutral(u32 state);
2131 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2133 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2136 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2137 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2138 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2140 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2141 unsigned int slot_id, unsigned int ep_index,
2142 unsigned int stream_id);
2144 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2147 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2148 xhci_get_endpoint_index(&urb->ep->desc),
2152 static inline char *xhci_slot_state_string(u32 state)
2155 case SLOT_STATE_ENABLED:
2156 return "enabled/disabled";
2157 case SLOT_STATE_DEFAULT:
2159 case SLOT_STATE_ADDRESSED:
2161 case SLOT_STATE_CONFIGURED:
2162 return "configured";
2168 static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2,
2171 static char str[256];
2172 int type = TRB_FIELD_TO_TYPE(field3);
2177 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2178 field1, field0, GET_INTR_TARGET(field2),
2179 xhci_trb_type_string(type),
2180 field3 & TRB_IOC ? 'I' : 'i',
2181 field3 & TRB_CHAIN ? 'C' : 'c',
2182 field3 & TRB_TC ? 'T' : 't',
2183 field3 & TRB_CYCLE ? 'C' : 'c');
2186 case TRB_COMPLETION:
2187 case TRB_PORT_STATUS:
2188 case TRB_BANDWIDTH_EVENT:
2192 case TRB_MFINDEX_WRAP:
2194 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2196 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2197 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2198 /* Macro decrements 1, maybe it shouldn't?!? */
2199 TRB_TO_EP_INDEX(field3) + 1,
2200 xhci_trb_type_string(type),
2201 field3 & EVENT_DATA ? 'E' : 'e',
2202 field3 & TRB_CYCLE ? 'C' : 'c');
2206 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2208 (field0 & 0xff00) >> 8,
2209 (field0 & 0xff000000) >> 24,
2210 (field0 & 0xff0000) >> 16,
2211 (field1 & 0xff00) >> 8,
2213 (field1 & 0xff000000) >> 16 |
2214 (field1 & 0xff0000) >> 16,
2215 TRB_LEN(field2), GET_TD_SIZE(field2),
2216 GET_INTR_TARGET(field2),
2217 xhci_trb_type_string(type),
2218 field3 & TRB_IDT ? 'I' : 'i',
2219 field3 & TRB_IOC ? 'I' : 'i',
2220 field3 & TRB_CYCLE ? 'C' : 'c');
2223 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2224 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2225 GET_INTR_TARGET(field2),
2226 xhci_trb_type_string(type),
2227 field3 & TRB_IDT ? 'I' : 'i',
2228 field3 & TRB_IOC ? 'I' : 'i',
2229 field3 & TRB_CHAIN ? 'C' : 'c',
2230 field3 & TRB_NO_SNOOP ? 'S' : 's',
2231 field3 & TRB_ISP ? 'I' : 'i',
2232 field3 & TRB_ENT ? 'E' : 'e',
2233 field3 & TRB_CYCLE ? 'C' : 'c');
2236 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2237 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2238 GET_INTR_TARGET(field2),
2239 xhci_trb_type_string(type),
2240 field3 & TRB_IOC ? 'I' : 'i',
2241 field3 & TRB_CHAIN ? 'C' : 'c',
2242 field3 & TRB_ENT ? 'E' : 'e',
2243 field3 & TRB_CYCLE ? 'C' : 'c');
2247 case TRB_EVENT_DATA:
2250 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2251 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2252 GET_INTR_TARGET(field2),
2253 xhci_trb_type_string(type),
2254 field3 & TRB_BEI ? 'B' : 'b',
2255 field3 & TRB_IDT ? 'I' : 'i',
2256 field3 & TRB_IOC ? 'I' : 'i',
2257 field3 & TRB_CHAIN ? 'C' : 'c',
2258 field3 & TRB_NO_SNOOP ? 'S' : 's',
2259 field3 & TRB_ISP ? 'I' : 'i',
2260 field3 & TRB_ENT ? 'E' : 'e',
2261 field3 & TRB_CYCLE ? 'C' : 'c');
2265 case TRB_ENABLE_SLOT:
2268 xhci_trb_type_string(type),
2269 field3 & TRB_CYCLE ? 'C' : 'c');
2271 case TRB_DISABLE_SLOT:
2272 case TRB_NEG_BANDWIDTH:
2274 "%s: slot %d flags %c",
2275 xhci_trb_type_string(type),
2276 TRB_TO_SLOT_ID(field3),
2277 field3 & TRB_CYCLE ? 'C' : 'c');
2281 "%s: ctx %08x%08x slot %d flags %c:%c",
2282 xhci_trb_type_string(type),
2284 TRB_TO_SLOT_ID(field3),
2285 field3 & TRB_BSR ? 'B' : 'b',
2286 field3 & TRB_CYCLE ? 'C' : 'c');
2290 "%s: ctx %08x%08x slot %d flags %c:%c",
2291 xhci_trb_type_string(type),
2293 TRB_TO_SLOT_ID(field3),
2294 field3 & TRB_DC ? 'D' : 'd',
2295 field3 & TRB_CYCLE ? 'C' : 'c');
2297 case TRB_EVAL_CONTEXT:
2299 "%s: ctx %08x%08x slot %d flags %c",
2300 xhci_trb_type_string(type),
2302 TRB_TO_SLOT_ID(field3),
2303 field3 & TRB_CYCLE ? 'C' : 'c');
2307 "%s: ctx %08x%08x slot %d ep %d flags %c",
2308 xhci_trb_type_string(type),
2310 TRB_TO_SLOT_ID(field3),
2311 /* Macro decrements 1, maybe it shouldn't?!? */
2312 TRB_TO_EP_INDEX(field3) + 1,
2313 field3 & TRB_CYCLE ? 'C' : 'c');
2317 "%s: slot %d sp %d ep %d flags %c",
2318 xhci_trb_type_string(type),
2319 TRB_TO_SLOT_ID(field3),
2320 TRB_TO_SUSPEND_PORT(field3),
2321 /* Macro decrements 1, maybe it shouldn't?!? */
2322 TRB_TO_EP_INDEX(field3) + 1,
2323 field3 & TRB_CYCLE ? 'C' : 'c');
2327 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2328 xhci_trb_type_string(type),
2330 TRB_TO_STREAM_ID(field2),
2331 TRB_TO_SLOT_ID(field3),
2332 /* Macro decrements 1, maybe it shouldn't?!? */
2333 TRB_TO_EP_INDEX(field3) + 1,
2334 field3 & TRB_CYCLE ? 'C' : 'c');
2338 "%s: slot %d flags %c",
2339 xhci_trb_type_string(type),
2340 TRB_TO_SLOT_ID(field3),
2341 field3 & TRB_CYCLE ? 'C' : 'c');
2343 case TRB_FORCE_EVENT:
2345 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2346 xhci_trb_type_string(type),
2348 TRB_TO_VF_INTR_TARGET(field2),
2349 TRB_TO_VF_ID(field3),
2350 field3 & TRB_CYCLE ? 'C' : 'c');
2354 "%s: belt %d flags %c",
2355 xhci_trb_type_string(type),
2356 TRB_TO_BELT(field3),
2357 field3 & TRB_CYCLE ? 'C' : 'c');
2361 "%s: ctx %08x%08x slot %d speed %d flags %c",
2362 xhci_trb_type_string(type),
2364 TRB_TO_SLOT_ID(field3),
2365 TRB_TO_DEV_SPEED(field3),
2366 field3 & TRB_CYCLE ? 'C' : 'c');
2368 case TRB_FORCE_HEADER:
2370 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2371 xhci_trb_type_string(type),
2372 field2, field1, field0 & 0xffffffe0,
2373 TRB_TO_PACKET_TYPE(field0),
2374 TRB_TO_ROOTHUB_PORT(field3),
2375 field3 & TRB_CYCLE ? 'C' : 'c');
2379 "type '%s' -> raw %08x %08x %08x %08x",
2380 xhci_trb_type_string(type),
2381 field0, field1, field2, field3);
2387 static inline const char *xhci_decode_slot_context(u32 info, u32 info2,
2388 u32 tt_info, u32 state)
2390 static char str[1024];
2396 speed = info & DEV_SPEED;
2397 hub = info & DEV_HUB;
2398 mtt = info & DEV_MTT;
2400 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2401 info & ROUTE_STRING_MASK,
2416 case SLOT_SPEED_SSP:
2417 s = "super-speed plus";
2420 s = "UNKNOWN speed";
2422 mtt ? " multi-TT" : "",
2424 (info & LAST_CTX_MASK) >> 27,
2426 DEVINFO_TO_ROOT_HUB_PORT(info2),
2427 DEVINFO_TO_MAX_PORTS(info2));
2429 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2430 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2431 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2432 state & DEV_ADDR_MASK,
2433 xhci_slot_state_string(GET_SLOT_STATE(state)));
2439 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2441 switch (portsc & PORT_PLS_MASK) {
2460 case XDEV_HOT_RESET:
2462 case XDEV_COMP_MODE:
2463 return "Compliance mode";
2464 case XDEV_TEST_MODE:
2474 static inline const char *xhci_decode_portsc(u32 portsc)
2476 static char str[256];
2479 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2480 portsc & PORT_POWER ? "Powered" : "Powered-off",
2481 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2482 portsc & PORT_PE ? "Enabled" : "Disabled",
2483 xhci_portsc_link_state_string(portsc),
2484 DEV_PORT_SPEED(portsc));
2486 if (portsc & PORT_OC)
2487 ret += sprintf(str + ret, "OverCurrent ");
2488 if (portsc & PORT_RESET)
2489 ret += sprintf(str + ret, "In-Reset ");
2491 ret += sprintf(str + ret, "Change: ");
2492 if (portsc & PORT_CSC)
2493 ret += sprintf(str + ret, "CSC ");
2494 if (portsc & PORT_PEC)
2495 ret += sprintf(str + ret, "PEC ");
2496 if (portsc & PORT_WRC)
2497 ret += sprintf(str + ret, "WRC ");
2498 if (portsc & PORT_OCC)
2499 ret += sprintf(str + ret, "OCC ");
2500 if (portsc & PORT_RC)
2501 ret += sprintf(str + ret, "PRC ");
2502 if (portsc & PORT_PLC)
2503 ret += sprintf(str + ret, "PLC ");
2504 if (portsc & PORT_CEC)
2505 ret += sprintf(str + ret, "CEC ");
2506 if (portsc & PORT_CAS)
2507 ret += sprintf(str + ret, "CAS ");
2509 ret += sprintf(str + ret, "Wake: ");
2510 if (portsc & PORT_WKCONN_E)
2511 ret += sprintf(str + ret, "WCE ");
2512 if (portsc & PORT_WKDISC_E)
2513 ret += sprintf(str + ret, "WDE ");
2514 if (portsc & PORT_WKOC_E)
2515 ret += sprintf(str + ret, "WOE ");
2520 static inline const char *xhci_ep_state_string(u8 state)
2523 case EP_STATE_DISABLED:
2525 case EP_STATE_RUNNING:
2527 case EP_STATE_HALTED:
2529 case EP_STATE_STOPPED:
2531 case EP_STATE_ERROR:
2538 static inline const char *xhci_ep_type_string(u8 type)
2560 static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq,
2563 static char str[1024];
2581 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2582 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2584 ep_state = info & EP_STATE_MASK;
2585 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2586 interval = CTX_TO_EP_INTERVAL(info);
2587 mult = CTX_TO_EP_MULT(info) + 1;
2588 lsa = !!(info & EP_HAS_LSA);
2590 cerr = (info2 & (3 << 1)) >> 1;
2591 ep_type = CTX_TO_EP_TYPE(info2);
2592 hid = !!(info2 & (1 << 7));
2593 burst = CTX_TO_MAX_BURST(info2);
2594 maxp = MAX_PACKET_DECODED(info2);
2596 avg = EP_AVG_TRB_LENGTH(tx_info);
2598 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2599 xhci_ep_state_string(ep_state), mult,
2600 max_pstr, lsa ? "LSA " : "");
2602 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2603 (1 << interval) * 125, esit, cerr);
2605 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2606 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2609 ret += sprintf(str + ret, "avg trb len %d", avg);
2614 #endif /* __LINUX_XHCI_HCD_H */