2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
77 unsigned long segment_offset;
79 if (!seg || !trb || trb < seg->trbs)
82 segment_offset = trb - seg->trbs;
83 if (segment_offset > TRBS_PER_SEGMENT)
85 return seg->dma + (segment_offset * sizeof(*trb));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
92 struct xhci_segment *seg, union xhci_trb *trb)
94 if (ring == xhci->event_ring)
95 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
96 (seg->next == xhci->event_ring->first_seg);
98 return trb->link.control & LINK_TOGGLE;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
106 struct xhci_segment *seg, union xhci_trb *trb)
108 if (ring == xhci->event_ring)
109 return trb == &seg->trbs[TRBS_PER_SEGMENT];
111 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd *xhci,
119 struct xhci_ring *ring,
120 struct xhci_segment **seg,
121 union xhci_trb **trb)
123 if (last_trb(xhci, ring, *seg, *trb)) {
125 *trb = ((*seg)->trbs);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
137 union xhci_trb *next = ++(ring->dequeue);
138 unsigned long long addr;
141 /* Update the dequeue pointer further if that was a link TRB or we're at
142 * the end of an event ring segment (which doesn't have link TRBS)
144 while (last_trb(xhci, ring, ring->deq_seg, next)) {
145 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
146 ring->cycle_state = (ring->cycle_state ? 0 : 1);
148 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
150 (unsigned int) ring->cycle_state);
152 ring->deq_seg = ring->deq_seg->next;
153 ring->dequeue = ring->deq_seg->trbs;
154 next = ring->dequeue;
156 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
157 if (ring == xhci->event_ring)
158 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
159 else if (ring == xhci->cmd_ring)
160 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
162 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
166 * See Cycle bit rules. SW is the consumer for the event ring only.
167 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
169 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
170 * chain bit is set), then set the chain bit in all the following link TRBs.
171 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
172 * have their chain bit cleared (so that each Link TRB is a separate TD).
174 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
175 * set, but other sections talk about dealing with the chain bit set. This was
176 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
177 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
179 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
182 union xhci_trb *next;
183 unsigned long long addr;
185 chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
186 next = ++(ring->enqueue);
189 /* Update the dequeue pointer further if that was a link TRB or we're at
190 * the end of an event ring segment (which doesn't have link TRBS)
192 while (last_trb(xhci, ring, ring->enq_seg, next)) {
194 if (ring != xhci->event_ring) {
195 /* If we're not dealing with 0.95 hardware,
196 * carry over the chain bit of the previous TRB
197 * (which may mean the chain bit is cleared).
199 if (!xhci_link_trb_quirk(xhci)) {
200 next->link.control &= ~TRB_CHAIN;
201 next->link.control |= chain;
203 /* Give this link TRB to the hardware */
205 if (next->link.control & TRB_CYCLE)
206 next->link.control &= (u32) ~TRB_CYCLE;
208 next->link.control |= (u32) TRB_CYCLE;
210 /* Toggle the cycle bit after the last ring segment. */
211 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
212 ring->cycle_state = (ring->cycle_state ? 0 : 1);
214 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
216 (unsigned int) ring->cycle_state);
219 ring->enq_seg = ring->enq_seg->next;
220 ring->enqueue = ring->enq_seg->trbs;
221 next = ring->enqueue;
223 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
224 if (ring == xhci->event_ring)
225 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
226 else if (ring == xhci->cmd_ring)
227 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
229 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
233 * Check to see if there's room to enqueue num_trbs on the ring. See rules
235 * FIXME: this would be simpler and faster if we just kept track of the number
236 * of free TRBs in a ring.
238 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
239 unsigned int num_trbs)
242 union xhci_trb *enq = ring->enqueue;
243 struct xhci_segment *enq_seg = ring->enq_seg;
245 /* Check if ring is empty */
246 if (enq == ring->dequeue)
248 /* Make sure there's an extra empty TRB available */
249 for (i = 0; i <= num_trbs; ++i) {
250 if (enq == ring->dequeue)
253 while (last_trb(xhci, ring, enq_seg, enq)) {
254 enq_seg = enq_seg->next;
261 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
266 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
267 xhci->event_ring->dequeue);
268 if (deq == 0 && !in_interrupt())
269 xhci_warn(xhci, "WARN something wrong with SW event ring "
271 /* Update HC event ring dequeue pointer */
272 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
273 temp &= ERST_PTR_MASK;
274 /* Don't clear the EHB bit (which is RW1C) because
275 * there might be more events to service.
278 xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
279 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
280 &xhci->ir_set->erst_dequeue);
283 /* Ring the host controller doorbell after placing a command on the ring */
284 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
288 xhci_dbg(xhci, "// Ding dong!\n");
289 temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
290 xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
291 /* Flush PCI posted writes */
292 xhci_readl(xhci, &xhci->dba->doorbell[0]);
295 static void ring_ep_doorbell(struct xhci_hcd *xhci,
296 unsigned int slot_id,
297 unsigned int ep_index)
299 struct xhci_ring *ep_ring;
301 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
303 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
304 /* Don't ring the doorbell for this endpoint if there are pending
305 * cancellations because the we don't want to interrupt processing.
307 if (!ep_ring->cancels_pending && !(ep_ring->state & SET_DEQ_PENDING)
308 && !(ep_ring->state & EP_HALTED)) {
309 field = xhci_readl(xhci, db_addr) & DB_MASK;
310 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
311 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
312 * isn't time-critical and we shouldn't make the CPU wait for
315 xhci_readl(xhci, db_addr);
320 * Find the segment that trb is in. Start searching in start_seg.
321 * If we must move past a segment that has a link TRB with a toggle cycle state
322 * bit set, then we will toggle the value pointed at by cycle_state.
324 static struct xhci_segment *find_trb_seg(
325 struct xhci_segment *start_seg,
326 union xhci_trb *trb, int *cycle_state)
328 struct xhci_segment *cur_seg = start_seg;
329 struct xhci_generic_trb *generic_trb;
331 while (cur_seg->trbs > trb ||
332 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
333 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
334 if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
335 (generic_trb->field[3] & LINK_TOGGLE))
336 *cycle_state = ~(*cycle_state) & 0x1;
337 cur_seg = cur_seg->next;
338 if (cur_seg == start_seg)
339 /* Looped over the entire list. Oops! */
346 * Move the xHC's endpoint ring dequeue pointer past cur_td.
347 * Record the new state of the xHC's endpoint ring dequeue segment,
348 * dequeue pointer, and new consumer cycle state in state.
349 * Update our internal representation of the ring's dequeue pointer.
351 * We do this in three jumps:
352 * - First we update our new ring state to be the same as when the xHC stopped.
353 * - Then we traverse the ring to find the segment that contains
354 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
355 * any link TRBs with the toggle cycle bit set.
356 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
357 * if we've moved it past a link TRB with the toggle cycle bit set.
359 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
360 unsigned int slot_id, unsigned int ep_index,
361 struct xhci_td *cur_td, struct xhci_dequeue_state *state)
363 struct xhci_virt_device *dev = xhci->devs[slot_id];
364 struct xhci_ring *ep_ring = dev->ep_rings[ep_index];
365 struct xhci_generic_trb *trb;
366 struct xhci_ep_ctx *ep_ctx;
369 state->new_cycle_state = 0;
370 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
371 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
372 ep_ring->stopped_trb,
373 &state->new_cycle_state);
374 if (!state->new_deq_seg)
376 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
377 xhci_dbg(xhci, "Finding endpoint context\n");
378 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
379 state->new_cycle_state = 0x1 & ep_ctx->deq;
381 state->new_deq_ptr = cur_td->last_trb;
382 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
383 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
385 &state->new_cycle_state);
386 if (!state->new_deq_seg)
389 trb = &state->new_deq_ptr->generic;
390 if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
391 (trb->field[3] & LINK_TOGGLE))
392 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
393 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
395 /* Don't update the ring cycle state for the producer (us). */
396 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
398 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
399 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
400 (unsigned long long) addr);
401 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
402 ep_ring->dequeue = state->new_deq_ptr;
403 ep_ring->deq_seg = state->new_deq_seg;
406 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
407 struct xhci_td *cur_td)
409 struct xhci_segment *cur_seg;
410 union xhci_trb *cur_trb;
412 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
414 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
415 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
416 TRB_TYPE(TRB_LINK)) {
417 /* Unchain any chained Link TRBs, but
418 * leave the pointers intact.
420 cur_trb->generic.field[3] &= ~TRB_CHAIN;
421 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
422 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
423 "in seg %p (0x%llx dma)\n",
425 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
427 (unsigned long long)cur_seg->dma);
429 cur_trb->generic.field[0] = 0;
430 cur_trb->generic.field[1] = 0;
431 cur_trb->generic.field[2] = 0;
432 /* Preserve only the cycle bit of this TRB */
433 cur_trb->generic.field[3] &= TRB_CYCLE;
434 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
435 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
436 "in seg %p (0x%llx dma)\n",
438 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
440 (unsigned long long)cur_seg->dma);
442 if (cur_trb == cur_td->last_trb)
447 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
448 unsigned int ep_index, struct xhci_segment *deq_seg,
449 union xhci_trb *deq_ptr, u32 cycle_state);
451 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
452 struct xhci_ring *ep_ring, unsigned int slot_id,
453 unsigned int ep_index, struct xhci_dequeue_state *deq_state)
455 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
456 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
457 deq_state->new_deq_seg,
458 (unsigned long long)deq_state->new_deq_seg->dma,
459 deq_state->new_deq_ptr,
460 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
461 deq_state->new_cycle_state);
462 queue_set_tr_deq(xhci, slot_id, ep_index,
463 deq_state->new_deq_seg,
464 deq_state->new_deq_ptr,
465 (u32) deq_state->new_cycle_state);
466 /* Stop the TD queueing code from ringing the doorbell until
467 * this command completes. The HC won't set the dequeue pointer
468 * if the ring is running, and ringing the doorbell starts the
471 ep_ring->state |= SET_DEQ_PENDING;
475 * When we get a command completion for a Stop Endpoint Command, we need to
476 * unlink any cancelled TDs from the ring. There are two ways to do that:
478 * 1. If the HW was in the middle of processing the TD that needs to be
479 * cancelled, then we must move the ring's dequeue pointer past the last TRB
480 * in the TD with a Set Dequeue Pointer Command.
481 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
482 * bit cleared) so that the HW will skip over them.
484 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
487 unsigned int slot_id;
488 unsigned int ep_index;
489 struct xhci_ring *ep_ring;
490 struct list_head *entry;
491 struct xhci_td *cur_td = 0;
492 struct xhci_td *last_unlinked_td;
494 struct xhci_dequeue_state deq_state;
495 #ifdef CONFIG_USB_HCD_STAT
496 ktime_t stop_time = ktime_get();
499 memset(&deq_state, 0, sizeof(deq_state));
500 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
501 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
502 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
504 if (list_empty(&ep_ring->cancelled_td_list))
507 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
508 * We have the xHCI lock, so nothing can modify this list until we drop
509 * it. We're also in the event handler, so we can't get re-interrupted
510 * if another Stop Endpoint command completes
512 list_for_each(entry, &ep_ring->cancelled_td_list) {
513 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
514 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
516 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
518 * If we stopped on the TD we need to cancel, then we have to
519 * move the xHC endpoint ring dequeue pointer past this TD.
521 if (cur_td == ep_ring->stopped_td)
522 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
525 td_to_noop(xhci, ep_ring, cur_td);
527 * The event handler won't see a completion for this TD anymore,
528 * so remove it from the endpoint ring's TD list. Keep it in
529 * the cancelled TD list for URB completion later.
531 list_del(&cur_td->td_list);
532 ep_ring->cancels_pending--;
534 last_unlinked_td = cur_td;
536 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
537 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
538 xhci_queue_new_dequeue_state(xhci, ep_ring,
539 slot_id, ep_index, &deq_state);
540 xhci_ring_cmd_db(xhci);
542 /* Otherwise just ring the doorbell to restart the ring */
543 ring_ep_doorbell(xhci, slot_id, ep_index);
547 * Drop the lock and complete the URBs in the cancelled TD list.
548 * New TDs to be cancelled might be added to the end of the list before
549 * we can complete all the URBs for the TDs we already unlinked.
550 * So stop when we've completed the URB for the last TD we unlinked.
553 cur_td = list_entry(ep_ring->cancelled_td_list.next,
554 struct xhci_td, cancelled_td_list);
555 list_del(&cur_td->cancelled_td_list);
557 /* Clean up the cancelled URB */
558 #ifdef CONFIG_USB_HCD_STAT
559 hcd_stat_update(xhci->tp_stat, cur_td->urb->actual_length,
560 ktime_sub(stop_time, cur_td->start_time));
562 cur_td->urb->hcpriv = NULL;
563 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), cur_td->urb);
565 xhci_dbg(xhci, "Giveback cancelled URB %p\n", cur_td->urb);
566 spin_unlock(&xhci->lock);
567 /* Doesn't matter what we pass for status, since the core will
568 * just overwrite it (because the URB has been unlinked).
570 usb_hcd_giveback_urb(xhci_to_hcd(xhci), cur_td->urb, 0);
573 spin_lock(&xhci->lock);
574 } while (cur_td != last_unlinked_td);
576 /* Return to the event handler with xhci->lock re-acquired */
580 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
581 * we need to clear the set deq pending flag in the endpoint ring state, so that
582 * the TD queueing code can ring the doorbell again. We also need to ring the
583 * endpoint doorbell to restart the ring, but only if there aren't more
584 * cancellations pending.
586 static void handle_set_deq_completion(struct xhci_hcd *xhci,
587 struct xhci_event_cmd *event,
590 unsigned int slot_id;
591 unsigned int ep_index;
592 struct xhci_ring *ep_ring;
593 struct xhci_virt_device *dev;
594 struct xhci_ep_ctx *ep_ctx;
595 struct xhci_slot_ctx *slot_ctx;
597 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
598 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
599 dev = xhci->devs[slot_id];
600 ep_ring = dev->ep_rings[ep_index];
601 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
602 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
604 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
605 unsigned int ep_state;
606 unsigned int slot_state;
608 switch (GET_COMP_CODE(event->status)) {
610 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
611 "of stream ID configuration\n");
614 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
615 "to incorrect slot or ep state.\n");
616 ep_state = ep_ctx->ep_info;
617 ep_state &= EP_STATE_MASK;
618 slot_state = slot_ctx->dev_state;
619 slot_state = GET_SLOT_STATE(slot_state);
620 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
621 slot_state, ep_state);
624 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
625 "slot %u was not enabled.\n", slot_id);
628 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
629 "completion code of %u.\n",
630 GET_COMP_CODE(event->status));
633 /* OK what do we do now? The endpoint state is hosed, and we
634 * should never get to this point if the synchronization between
635 * queueing, and endpoint state are correct. This might happen
636 * if the device gets disconnected after we've finished
637 * cancelling URBs, which might not be an error...
640 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
644 ep_ring->state &= ~SET_DEQ_PENDING;
645 ring_ep_doorbell(xhci, slot_id, ep_index);
648 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
649 struct xhci_event_cmd *event,
653 unsigned int ep_index;
654 struct xhci_ring *ep_ring;
656 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
657 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
658 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
659 /* This command will only fail if the endpoint wasn't halted,
662 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
663 (unsigned int) GET_COMP_CODE(event->status));
665 /* HW with the reset endpoint quirk needs to have a configure endpoint
666 * command complete before the endpoint can be used. Queue that here
667 * because the HW can't handle two commands being queued in a row.
669 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
670 xhci_dbg(xhci, "Queueing configure endpoint command\n");
671 xhci_queue_configure_endpoint(xhci,
672 xhci->devs[slot_id]->in_ctx->dma, slot_id);
673 xhci_ring_cmd_db(xhci);
675 /* Clear our internal halted state and restart the ring */
676 ep_ring->state &= ~EP_HALTED;
677 ring_ep_doorbell(xhci, slot_id, ep_index);
681 static void handle_cmd_completion(struct xhci_hcd *xhci,
682 struct xhci_event_cmd *event)
684 int slot_id = TRB_TO_SLOT_ID(event->flags);
686 dma_addr_t cmd_dequeue_dma;
687 struct xhci_input_control_ctx *ctrl_ctx;
688 unsigned int ep_index;
689 struct xhci_ring *ep_ring;
690 unsigned int ep_state;
692 cmd_dma = event->cmd_trb;
693 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
694 xhci->cmd_ring->dequeue);
695 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
696 if (cmd_dequeue_dma == 0) {
697 xhci->error_bitmask |= 1 << 4;
700 /* Does the DMA address match our internal dequeue pointer address? */
701 if (cmd_dma != (u64) cmd_dequeue_dma) {
702 xhci->error_bitmask |= 1 << 5;
705 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
706 case TRB_TYPE(TRB_ENABLE_SLOT):
707 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
708 xhci->slot_id = slot_id;
711 complete(&xhci->addr_dev);
713 case TRB_TYPE(TRB_DISABLE_SLOT):
714 if (xhci->devs[slot_id])
715 xhci_free_virt_device(xhci, slot_id);
717 case TRB_TYPE(TRB_CONFIG_EP):
719 * Configure endpoint commands can come from the USB core
720 * configuration or alt setting changes, or because the HW
721 * needed an extra configure endpoint command after a reset
722 * endpoint command. In the latter case, the xHCI driver is
723 * not waiting on the configure endpoint command.
725 ctrl_ctx = xhci_get_input_control_ctx(xhci,
726 xhci->devs[slot_id]->in_ctx);
727 /* Input ctx add_flags are the endpoint index plus one */
728 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
729 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
731 /* This must have been an initial configure endpoint */
732 xhci->devs[slot_id]->cmd_status =
733 GET_COMP_CODE(event->status);
734 complete(&xhci->devs[slot_id]->cmd_completion);
737 ep_state = ep_ring->state;
738 xhci_dbg(xhci, "Completed config ep cmd - last ep index = %d, "
739 "state = %d\n", ep_index, ep_state);
740 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
741 ep_state & EP_HALTED) {
742 /* Clear our internal halted state and restart ring */
743 xhci->devs[slot_id]->ep_rings[ep_index]->state &=
745 ring_ep_doorbell(xhci, slot_id, ep_index);
747 xhci->devs[slot_id]->cmd_status =
748 GET_COMP_CODE(event->status);
749 complete(&xhci->devs[slot_id]->cmd_completion);
752 case TRB_TYPE(TRB_EVAL_CONTEXT):
753 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
754 complete(&xhci->devs[slot_id]->cmd_completion);
756 case TRB_TYPE(TRB_ADDR_DEV):
757 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
758 complete(&xhci->addr_dev);
760 case TRB_TYPE(TRB_STOP_RING):
761 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
763 case TRB_TYPE(TRB_SET_DEQ):
764 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
766 case TRB_TYPE(TRB_CMD_NOOP):
767 ++xhci->noops_handled;
769 case TRB_TYPE(TRB_RESET_EP):
770 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
773 /* Skip over unknown commands on the event ring */
774 xhci->error_bitmask |= 1 << 6;
777 inc_deq(xhci, xhci->cmd_ring, false);
780 static void handle_port_status(struct xhci_hcd *xhci,
781 union xhci_trb *event)
785 /* Port status change events always have a successful completion code */
786 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
787 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
788 xhci->error_bitmask |= 1 << 8;
790 /* FIXME: core doesn't care about all port link state changes yet */
791 port_id = GET_PORT_ID(event->generic.field[0]);
792 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
794 /* Update event ring dequeue pointer before dropping the lock */
795 inc_deq(xhci, xhci->event_ring, true);
796 xhci_set_hc_event_deq(xhci);
798 spin_unlock(&xhci->lock);
799 /* Pass this up to the core */
800 usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
801 spin_lock(&xhci->lock);
805 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
806 * at end_trb, which may be in another segment. If the suspect DMA address is a
807 * TRB in this TD, this function returns that TRB's segment. Otherwise it
810 static struct xhci_segment *trb_in_td(
811 struct xhci_segment *start_seg,
812 union xhci_trb *start_trb,
813 union xhci_trb *end_trb,
814 dma_addr_t suspect_dma)
816 dma_addr_t start_dma;
817 dma_addr_t end_seg_dma;
818 dma_addr_t end_trb_dma;
819 struct xhci_segment *cur_seg;
821 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
825 /* We may get an event for a Link TRB in the middle of a TD */
826 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
827 &start_seg->trbs[TRBS_PER_SEGMENT - 1]);
828 /* If the end TRB isn't in this segment, this is set to 0 */
829 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
831 if (end_trb_dma > 0) {
832 /* The end TRB is in this segment, so suspect should be here */
833 if (start_dma <= end_trb_dma) {
834 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
837 /* Case for one segment with
838 * a TD wrapped around to the top
840 if ((suspect_dma >= start_dma &&
841 suspect_dma <= end_seg_dma) ||
842 (suspect_dma >= cur_seg->dma &&
843 suspect_dma <= end_trb_dma))
848 /* Might still be somewhere in this segment */
849 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
852 cur_seg = cur_seg->next;
853 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
859 * If this function returns an error condition, it means it got a Transfer
860 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
861 * At this point, the host controller is probably hosed and should be reset.
863 static int handle_tx_event(struct xhci_hcd *xhci,
864 struct xhci_transfer_event *event)
866 struct xhci_virt_device *xdev;
867 struct xhci_ring *ep_ring;
868 unsigned int slot_id;
870 struct xhci_td *td = 0;
871 dma_addr_t event_dma;
872 struct xhci_segment *event_seg;
873 union xhci_trb *event_trb;
875 int status = -EINPROGRESS;
876 struct xhci_ep_ctx *ep_ctx;
879 xhci_dbg(xhci, "In %s\n", __func__);
880 slot_id = TRB_TO_SLOT_ID(event->flags);
881 xdev = xhci->devs[slot_id];
883 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
887 /* Endpoint ID is 1 based, our index is zero based */
888 ep_index = TRB_TO_EP_ID(event->flags) - 1;
889 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
890 ep_ring = xdev->ep_rings[ep_index];
891 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
892 if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
893 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
897 event_dma = event->buffer;
898 /* This TRB should be in the TD at the head of this ring's TD list */
899 xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
900 if (list_empty(&ep_ring->td_list)) {
901 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
902 TRB_TO_SLOT_ID(event->flags), ep_index);
903 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
904 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
905 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
909 xhci_dbg(xhci, "%s - getting list entry\n", __func__);
910 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
912 /* Is this a TRB in the currently executing TD? */
913 xhci_dbg(xhci, "%s - looking for TD\n", __func__);
914 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
915 td->last_trb, event_dma);
916 xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
918 /* HC is busted, give up! */
919 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
922 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
923 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
924 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
925 xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
926 lower_32_bits(event->buffer));
927 xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
928 upper_32_bits(event->buffer));
929 xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
930 (unsigned int) event->transfer_len);
931 xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
932 (unsigned int) event->flags);
934 /* Look for common error cases */
935 trb_comp_code = GET_COMP_CODE(event->transfer_len);
936 switch (trb_comp_code) {
937 /* Skip codes that require special handling depending on
944 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
946 case COMP_STOP_INVAL:
947 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
950 xhci_warn(xhci, "WARN: Stalled endpoint\n");
951 ep_ring->state |= EP_HALTED;
955 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
959 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
963 xhci_warn(xhci, "WARN: babble error on endpoint\n");
967 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
971 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
975 /* Now update the urb's actual_length and give back to the core */
976 /* Was this a control transfer? */
977 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
978 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
979 switch (trb_comp_code) {
981 if (event_trb == ep_ring->dequeue) {
982 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
984 } else if (event_trb != td->last_trb) {
985 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
988 xhci_dbg(xhci, "Successful control transfer!\n");
993 xhci_warn(xhci, "WARN: short transfer on control ep\n");
997 /* The 0.96 spec says a babbling control endpoint
998 * is not halted. The 0.96 spec says it is. Some HW
999 * claims to be 0.95 compliant, but it halts the control
1000 * endpoint anyway. Check if a babble halted the
1003 if (ep_ctx->ep_info != EP_STATE_HALTED)
1005 /* else fall through */
1007 /* Did we transfer part of the data (middle) phase? */
1008 if (event_trb != ep_ring->dequeue &&
1009 event_trb != td->last_trb)
1010 td->urb->actual_length =
1011 td->urb->transfer_buffer_length
1012 - TRB_LEN(event->transfer_len);
1014 td->urb->actual_length = 0;
1016 ep_ring->stopped_td = td;
1017 ep_ring->stopped_trb = event_trb;
1018 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1019 xhci_cleanup_stalled_ring(xhci,
1022 xhci_ring_cmd_db(xhci);
1025 /* Others already handled above */
1029 * Did we transfer any data, despite the errors that might have
1030 * happened? I.e. did we get past the setup stage?
1032 if (event_trb != ep_ring->dequeue) {
1033 /* The event was for the status stage */
1034 if (event_trb == td->last_trb) {
1035 if (td->urb->actual_length != 0) {
1036 /* Don't overwrite a previously set error code */
1037 if (status == -EINPROGRESS || status == 0)
1038 /* Did we already see a short data stage? */
1039 status = -EREMOTEIO;
1041 td->urb->actual_length =
1042 td->urb->transfer_buffer_length;
1045 /* Maybe the event was for the data stage? */
1046 if (trb_comp_code != COMP_STOP_INVAL) {
1047 /* We didn't stop on a link TRB in the middle */
1048 td->urb->actual_length =
1049 td->urb->transfer_buffer_length -
1050 TRB_LEN(event->transfer_len);
1051 xhci_dbg(xhci, "Waiting for status stage event\n");
1058 switch (trb_comp_code) {
1060 /* Double check that the HW transferred everything. */
1061 if (event_trb != td->last_trb) {
1062 xhci_warn(xhci, "WARN Successful completion "
1064 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1065 status = -EREMOTEIO;
1069 xhci_dbg(xhci, "Successful bulk transfer!\n");
1074 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1075 status = -EREMOTEIO;
1080 /* Others already handled above */
1083 dev_dbg(&td->urb->dev->dev,
1084 "ep %#x - asked for %d bytes, "
1085 "%d bytes untransferred\n",
1086 td->urb->ep->desc.bEndpointAddress,
1087 td->urb->transfer_buffer_length,
1088 TRB_LEN(event->transfer_len));
1089 /* Fast path - was this the last TRB in the TD for this URB? */
1090 if (event_trb == td->last_trb) {
1091 if (TRB_LEN(event->transfer_len) != 0) {
1092 td->urb->actual_length =
1093 td->urb->transfer_buffer_length -
1094 TRB_LEN(event->transfer_len);
1095 if (td->urb->transfer_buffer_length <
1096 td->urb->actual_length) {
1097 xhci_warn(xhci, "HC gave bad length "
1098 "of %d bytes left\n",
1099 TRB_LEN(event->transfer_len));
1100 td->urb->actual_length = 0;
1102 /* Don't overwrite a previously set error code */
1103 if (status == -EINPROGRESS) {
1104 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1105 status = -EREMOTEIO;
1110 td->urb->actual_length = td->urb->transfer_buffer_length;
1111 /* Ignore a short packet completion if the
1112 * untransferred length was zero.
1114 if (status == -EREMOTEIO)
1118 /* Slow path - walk the list, starting from the dequeue
1119 * pointer, to get the actual length transferred.
1121 union xhci_trb *cur_trb;
1122 struct xhci_segment *cur_seg;
1124 td->urb->actual_length = 0;
1125 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1126 cur_trb != event_trb;
1127 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1128 if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
1129 TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
1130 td->urb->actual_length +=
1131 TRB_LEN(cur_trb->generic.field[2]);
1133 /* If the ring didn't stop on a Link or No-op TRB, add
1134 * in the actual bytes transferred from the Normal TRB
1136 if (trb_comp_code != COMP_STOP_INVAL)
1137 td->urb->actual_length +=
1138 TRB_LEN(cur_trb->generic.field[2]) -
1139 TRB_LEN(event->transfer_len);
1142 if (trb_comp_code == COMP_STOP_INVAL ||
1143 trb_comp_code == COMP_STOP) {
1144 /* The Endpoint Stop Command completion will take care of any
1145 * stopped TDs. A stopped TD may be restarted, so don't update
1146 * the ring dequeue pointer or take this TD off any lists yet.
1148 ep_ring->stopped_td = td;
1149 ep_ring->stopped_trb = event_trb;
1151 if (trb_comp_code == COMP_STALL ||
1152 trb_comp_code == COMP_BABBLE) {
1153 /* The transfer is completed from the driver's
1154 * perspective, but we need to issue a set dequeue
1155 * command for this stalled endpoint to move the dequeue
1156 * pointer past the TD. We can't do that here because
1157 * the halt condition must be cleared first.
1159 ep_ring->stopped_td = td;
1160 ep_ring->stopped_trb = event_trb;
1162 /* Update ring dequeue pointer */
1163 while (ep_ring->dequeue != td->last_trb)
1164 inc_deq(xhci, ep_ring, false);
1165 inc_deq(xhci, ep_ring, false);
1169 /* Clean up the endpoint's TD list */
1171 /* Do one last check of the actual transfer length.
1172 * If the host controller said we transferred more data than
1173 * the buffer length, urb->actual_length will be a very big
1174 * number (since it's unsigned). Play it safe and say we didn't
1175 * transfer anything.
1177 if (urb->actual_length > urb->transfer_buffer_length) {
1178 xhci_warn(xhci, "URB transfer length is wrong, "
1179 "xHC issue? req. len = %u, "
1181 urb->transfer_buffer_length,
1182 urb->actual_length);
1183 urb->actual_length = 0;
1185 list_del(&td->td_list);
1186 /* Was this TD slated to be cancelled but completed anyway? */
1187 if (!list_empty(&td->cancelled_td_list)) {
1188 list_del(&td->cancelled_td_list);
1189 ep_ring->cancels_pending--;
1191 /* Leave the TD around for the reset endpoint function to use
1192 * (but only if it's not a control endpoint, since we already
1193 * queued the Set TR dequeue pointer command for stalled
1194 * control endpoints).
1196 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1197 (trb_comp_code != COMP_STALL &&
1198 trb_comp_code != COMP_BABBLE)) {
1204 inc_deq(xhci, xhci->event_ring, true);
1205 xhci_set_hc_event_deq(xhci);
1207 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1209 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1210 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1211 urb, urb->actual_length, status);
1212 spin_unlock(&xhci->lock);
1213 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1214 spin_lock(&xhci->lock);
1220 * This function handles all OS-owned events on the event ring. It may drop
1221 * xhci->lock between event processing (e.g. to pass up port status changes).
1223 void xhci_handle_event(struct xhci_hcd *xhci)
1225 union xhci_trb *event;
1226 int update_ptrs = 1;
1229 xhci_dbg(xhci, "In %s\n", __func__);
1230 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1231 xhci->error_bitmask |= 1 << 1;
1235 event = xhci->event_ring->dequeue;
1236 /* Does the HC or OS own the TRB? */
1237 if ((event->event_cmd.flags & TRB_CYCLE) !=
1238 xhci->event_ring->cycle_state) {
1239 xhci->error_bitmask |= 1 << 2;
1242 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1244 /* FIXME: Handle more event types. */
1245 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1246 case TRB_TYPE(TRB_COMPLETION):
1247 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1248 handle_cmd_completion(xhci, &event->event_cmd);
1249 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1251 case TRB_TYPE(TRB_PORT_STATUS):
1252 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1253 handle_port_status(xhci, event);
1254 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1257 case TRB_TYPE(TRB_TRANSFER):
1258 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1259 ret = handle_tx_event(xhci, &event->trans_event);
1260 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1262 xhci->error_bitmask |= 1 << 9;
1267 xhci->error_bitmask |= 1 << 3;
1271 /* Update SW and HC event ring dequeue pointer */
1272 inc_deq(xhci, xhci->event_ring, true);
1273 xhci_set_hc_event_deq(xhci);
1275 /* Are there more items on the event ring? */
1276 xhci_handle_event(xhci);
1279 /**** Endpoint Ring Operations ****/
1282 * Generic function for queueing a TRB on a ring.
1283 * The caller must have checked to make sure there's room on the ring.
1285 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1287 u32 field1, u32 field2, u32 field3, u32 field4)
1289 struct xhci_generic_trb *trb;
1291 trb = &ring->enqueue->generic;
1292 trb->field[0] = field1;
1293 trb->field[1] = field2;
1294 trb->field[2] = field3;
1295 trb->field[3] = field4;
1296 inc_enq(xhci, ring, consumer);
1300 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1301 * FIXME allocate segments if the ring is full.
1303 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1304 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1306 /* Make sure the endpoint has been added to xHC schedule */
1307 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1309 case EP_STATE_DISABLED:
1311 * USB core changed config/interfaces without notifying us,
1312 * or hardware is reporting the wrong state.
1314 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1316 case EP_STATE_ERROR:
1317 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1318 /* FIXME event handling code for error needs to clear it */
1319 /* XXX not sure if this should be -ENOENT or not */
1321 case EP_STATE_HALTED:
1322 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1323 case EP_STATE_STOPPED:
1324 case EP_STATE_RUNNING:
1327 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1329 * FIXME issue Configure Endpoint command to try to get the HC
1330 * back into a known state.
1334 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1335 /* FIXME allocate more room */
1336 xhci_err(xhci, "ERROR no room on ep ring\n");
1342 static int prepare_transfer(struct xhci_hcd *xhci,
1343 struct xhci_virt_device *xdev,
1344 unsigned int ep_index,
1345 unsigned int num_trbs,
1347 struct xhci_td **td,
1351 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1352 ret = prepare_ring(xhci, xdev->ep_rings[ep_index],
1353 ep_ctx->ep_info & EP_STATE_MASK,
1354 num_trbs, mem_flags);
1357 *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1360 INIT_LIST_HEAD(&(*td)->td_list);
1361 INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1363 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1364 if (unlikely(ret)) {
1370 urb->hcpriv = (void *) (*td);
1371 /* Add this TD to the tail of the endpoint ring's TD list */
1372 list_add_tail(&(*td)->td_list, &xdev->ep_rings[ep_index]->td_list);
1373 (*td)->start_seg = xdev->ep_rings[ep_index]->enq_seg;
1374 (*td)->first_trb = xdev->ep_rings[ep_index]->enqueue;
1379 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1381 int num_sgs, num_trbs, running_total, temp, i;
1382 struct scatterlist *sg;
1385 num_sgs = urb->num_sgs;
1386 temp = urb->transfer_buffer_length;
1388 xhci_dbg(xhci, "count sg list trbs: \n");
1390 for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1391 unsigned int previous_total_trbs = num_trbs;
1392 unsigned int len = sg_dma_len(sg);
1394 /* Scatter gather list entries may cross 64KB boundaries */
1395 running_total = TRB_MAX_BUFF_SIZE -
1396 (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1397 if (running_total != 0)
1400 /* How many more 64KB chunks to transfer, how many more TRBs? */
1401 while (running_total < sg_dma_len(sg)) {
1403 running_total += TRB_MAX_BUFF_SIZE;
1405 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1406 i, (unsigned long long)sg_dma_address(sg),
1407 len, len, num_trbs - previous_total_trbs);
1409 len = min_t(int, len, temp);
1414 xhci_dbg(xhci, "\n");
1415 if (!in_interrupt())
1416 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1417 urb->ep->desc.bEndpointAddress,
1418 urb->transfer_buffer_length,
1423 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1426 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1427 "TRBs, %d left\n", __func__,
1428 urb->ep->desc.bEndpointAddress, num_trbs);
1429 if (running_total != urb->transfer_buffer_length)
1430 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1431 "queued %#x (%d), asked for %#x (%d)\n",
1433 urb->ep->desc.bEndpointAddress,
1434 running_total, running_total,
1435 urb->transfer_buffer_length,
1436 urb->transfer_buffer_length);
1439 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1440 unsigned int ep_index, int start_cycle,
1441 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1444 * Pass all the TRBs to the hardware at once and make sure this write
1448 start_trb->field[3] |= start_cycle;
1449 ring_ep_doorbell(xhci, slot_id, ep_index);
1452 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1453 struct urb *urb, int slot_id, unsigned int ep_index)
1455 struct xhci_ring *ep_ring;
1456 unsigned int num_trbs;
1458 struct scatterlist *sg;
1460 int trb_buff_len, this_sg_len, running_total;
1464 struct xhci_generic_trb *start_trb;
1467 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1468 num_trbs = count_sg_trbs_needed(xhci, urb);
1469 num_sgs = urb->num_sgs;
1471 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1472 ep_index, num_trbs, urb, &td, mem_flags);
1473 if (trb_buff_len < 0)
1474 return trb_buff_len;
1476 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1477 * until we've finished creating all the other TRBs. The ring's cycle
1478 * state may change as we enqueue the other TRBs, so save it too.
1480 start_trb = &ep_ring->enqueue->generic;
1481 start_cycle = ep_ring->cycle_state;
1485 * How much data is in the first TRB?
1487 * There are three forces at work for TRB buffer pointers and lengths:
1488 * 1. We don't want to walk off the end of this sg-list entry buffer.
1489 * 2. The transfer length that the driver requested may be smaller than
1490 * the amount of memory allocated for this scatter-gather list.
1491 * 3. TRBs buffers can't cross 64KB boundaries.
1494 addr = (u64) sg_dma_address(sg);
1495 this_sg_len = sg_dma_len(sg);
1496 trb_buff_len = TRB_MAX_BUFF_SIZE -
1497 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1498 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1499 if (trb_buff_len > urb->transfer_buffer_length)
1500 trb_buff_len = urb->transfer_buffer_length;
1501 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1505 /* Queue the first TRB, even if it's zero-length */
1508 u32 length_field = 0;
1510 /* Don't change the cycle bit of the first TRB until later */
1514 field |= ep_ring->cycle_state;
1516 /* Chain all the TRBs together; clear the chain bit in the last
1517 * TRB to indicate it's the last TRB in the chain.
1522 /* FIXME - add check for ZERO_PACKET flag before this */
1523 td->last_trb = ep_ring->enqueue;
1526 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1527 "64KB boundary at %#x, end dma = %#x\n",
1528 (unsigned int) addr, trb_buff_len, trb_buff_len,
1529 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1530 (unsigned int) addr + trb_buff_len);
1531 if (TRB_MAX_BUFF_SIZE -
1532 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
1533 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1534 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1535 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1536 (unsigned int) addr + trb_buff_len);
1538 length_field = TRB_LEN(trb_buff_len) |
1539 TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1541 queue_trb(xhci, ep_ring, false,
1542 lower_32_bits(addr),
1543 upper_32_bits(addr),
1545 /* We always want to know if the TRB was short,
1546 * or we won't get an event when it completes.
1547 * (Unless we use event data TRBs, which are a
1548 * waste of space and HC resources.)
1550 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1552 running_total += trb_buff_len;
1554 /* Calculate length for next transfer --
1555 * Are we done queueing all the TRBs for this sg entry?
1557 this_sg_len -= trb_buff_len;
1558 if (this_sg_len == 0) {
1563 addr = (u64) sg_dma_address(sg);
1564 this_sg_len = sg_dma_len(sg);
1566 addr += trb_buff_len;
1569 trb_buff_len = TRB_MAX_BUFF_SIZE -
1570 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1571 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1572 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1574 urb->transfer_buffer_length - running_total;
1575 } while (running_total < urb->transfer_buffer_length);
1577 check_trb_math(urb, num_trbs, running_total);
1578 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1582 /* This is very similar to what ehci-q.c qtd_fill() does */
1583 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1584 struct urb *urb, int slot_id, unsigned int ep_index)
1586 struct xhci_ring *ep_ring;
1589 struct xhci_generic_trb *start_trb;
1592 u32 field, length_field;
1594 int running_total, trb_buff_len, ret;
1598 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1600 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1603 /* How much data is (potentially) left before the 64KB boundary? */
1604 running_total = TRB_MAX_BUFF_SIZE -
1605 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1607 /* If there's some data on this 64KB chunk, or we have to send a
1608 * zero-length transfer, we need at least one TRB
1610 if (running_total != 0 || urb->transfer_buffer_length == 0)
1612 /* How many more 64KB chunks to transfer, how many more TRBs? */
1613 while (running_total < urb->transfer_buffer_length) {
1615 running_total += TRB_MAX_BUFF_SIZE;
1617 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1619 if (!in_interrupt())
1620 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1621 urb->ep->desc.bEndpointAddress,
1622 urb->transfer_buffer_length,
1623 urb->transfer_buffer_length,
1624 (unsigned long long)urb->transfer_dma,
1627 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
1628 num_trbs, urb, &td, mem_flags);
1633 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1634 * until we've finished creating all the other TRBs. The ring's cycle
1635 * state may change as we enqueue the other TRBs, so save it too.
1637 start_trb = &ep_ring->enqueue->generic;
1638 start_cycle = ep_ring->cycle_state;
1641 /* How much data is in the first TRB? */
1642 addr = (u64) urb->transfer_dma;
1643 trb_buff_len = TRB_MAX_BUFF_SIZE -
1644 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1645 if (urb->transfer_buffer_length < trb_buff_len)
1646 trb_buff_len = urb->transfer_buffer_length;
1650 /* Queue the first TRB, even if it's zero-length */
1654 /* Don't change the cycle bit of the first TRB until later */
1658 field |= ep_ring->cycle_state;
1660 /* Chain all the TRBs together; clear the chain bit in the last
1661 * TRB to indicate it's the last TRB in the chain.
1666 /* FIXME - add check for ZERO_PACKET flag before this */
1667 td->last_trb = ep_ring->enqueue;
1670 length_field = TRB_LEN(trb_buff_len) |
1671 TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1673 queue_trb(xhci, ep_ring, false,
1674 lower_32_bits(addr),
1675 upper_32_bits(addr),
1677 /* We always want to know if the TRB was short,
1678 * or we won't get an event when it completes.
1679 * (Unless we use event data TRBs, which are a
1680 * waste of space and HC resources.)
1682 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1684 running_total += trb_buff_len;
1686 /* Calculate length for next transfer */
1687 addr += trb_buff_len;
1688 trb_buff_len = urb->transfer_buffer_length - running_total;
1689 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
1690 trb_buff_len = TRB_MAX_BUFF_SIZE;
1691 } while (running_total < urb->transfer_buffer_length);
1693 check_trb_math(urb, num_trbs, running_total);
1694 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1698 /* Caller must have locked xhci->lock */
1699 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1700 struct urb *urb, int slot_id, unsigned int ep_index)
1702 struct xhci_ring *ep_ring;
1705 struct usb_ctrlrequest *setup;
1706 struct xhci_generic_trb *start_trb;
1708 u32 field, length_field;
1711 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1714 * Need to copy setup packet into setup TRB, so we can't use the setup
1717 if (!urb->setup_packet)
1720 if (!in_interrupt())
1721 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
1723 /* 1 TRB for setup, 1 for status */
1726 * Don't need to check if we need additional event data and normal TRBs,
1727 * since data in control transfers will never get bigger than 16MB
1728 * XXX: can we get a buffer that crosses 64KB boundaries?
1730 if (urb->transfer_buffer_length > 0)
1732 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
1733 urb, &td, mem_flags);
1738 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1739 * until we've finished creating all the other TRBs. The ring's cycle
1740 * state may change as we enqueue the other TRBs, so save it too.
1742 start_trb = &ep_ring->enqueue->generic;
1743 start_cycle = ep_ring->cycle_state;
1745 /* Queue setup TRB - see section 6.4.1.2.1 */
1746 /* FIXME better way to translate setup_packet into two u32 fields? */
1747 setup = (struct usb_ctrlrequest *) urb->setup_packet;
1748 queue_trb(xhci, ep_ring, false,
1749 /* FIXME endianness is probably going to bite my ass here. */
1750 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
1751 setup->wIndex | setup->wLength << 16,
1752 TRB_LEN(8) | TRB_INTR_TARGET(0),
1753 /* Immediate data in pointer */
1754 TRB_IDT | TRB_TYPE(TRB_SETUP));
1756 /* If there's data, queue data TRBs */
1758 length_field = TRB_LEN(urb->transfer_buffer_length) |
1759 TD_REMAINDER(urb->transfer_buffer_length) |
1761 if (urb->transfer_buffer_length > 0) {
1762 if (setup->bRequestType & USB_DIR_IN)
1763 field |= TRB_DIR_IN;
1764 queue_trb(xhci, ep_ring, false,
1765 lower_32_bits(urb->transfer_dma),
1766 upper_32_bits(urb->transfer_dma),
1768 /* Event on short tx */
1769 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
1772 /* Save the DMA address of the last TRB in the TD */
1773 td->last_trb = ep_ring->enqueue;
1775 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1776 /* If the device sent data, the status stage is an OUT transfer */
1777 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
1781 queue_trb(xhci, ep_ring, false,
1785 /* Event on completion */
1786 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
1788 giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1792 /**** Command Ring Operations ****/
1794 /* Generic function for queueing a command TRB on the command ring */
1795 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, u32 field3, u32 field4)
1797 if (!room_on_ring(xhci, xhci->cmd_ring, 1)) {
1798 if (!in_interrupt())
1799 xhci_err(xhci, "ERR: No room for command on command ring\n");
1802 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
1803 field4 | xhci->cmd_ring->cycle_state);
1807 /* Queue a no-op command on the command ring */
1808 static int queue_cmd_noop(struct xhci_hcd *xhci)
1810 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP));
1814 * Place a no-op command on the command ring to test the command and
1817 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
1819 if (queue_cmd_noop(xhci) < 0)
1821 xhci->noops_submitted++;
1822 return xhci_ring_cmd_db;
1825 /* Queue a slot enable or disable request on the command ring */
1826 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
1828 return queue_command(xhci, 0, 0, 0,
1829 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id));
1832 /* Queue an address device command TRB */
1833 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1836 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1837 upper_32_bits(in_ctx_ptr), 0,
1838 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id));
1841 /* Queue a configure endpoint command TRB */
1842 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1845 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1846 upper_32_bits(in_ctx_ptr), 0,
1847 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id));
1850 /* Queue an evaluate context command TRB */
1851 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1854 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1855 upper_32_bits(in_ctx_ptr), 0,
1856 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id));
1859 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1860 unsigned int ep_index)
1862 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1863 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1864 u32 type = TRB_TYPE(TRB_STOP_RING);
1866 return queue_command(xhci, 0, 0, 0,
1867 trb_slot_id | trb_ep_index | type);
1870 /* Set Transfer Ring Dequeue Pointer command.
1871 * This should not be used for endpoints that have streams enabled.
1873 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
1874 unsigned int ep_index, struct xhci_segment *deq_seg,
1875 union xhci_trb *deq_ptr, u32 cycle_state)
1878 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1879 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1880 u32 type = TRB_TYPE(TRB_SET_DEQ);
1882 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
1884 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
1885 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
1889 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
1890 upper_32_bits(addr), 0,
1891 trb_slot_id | trb_ep_index | type);
1894 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1895 unsigned int ep_index)
1897 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1898 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1899 u32 type = TRB_TYPE(TRB_RESET_EP);
1901 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type);