1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
66 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
69 unsigned long segment_offset;
71 if (!seg || !trb || trb < seg->trbs)
74 segment_offset = trb - seg->trbs;
75 if (segment_offset >= TRBS_PER_SEGMENT)
77 return seg->dma + (segment_offset * sizeof(*trb));
80 static bool trb_is_noop(union xhci_trb *trb)
82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
85 static bool trb_is_link(union xhci_trb *trb)
87 return TRB_TYPE_LINK_LE32(trb->link.control);
90 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
95 static bool last_trb_on_ring(struct xhci_ring *ring,
96 struct xhci_segment *seg, union xhci_trb *trb)
98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
101 static bool link_trb_toggles_cycle(union xhci_trb *trb)
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 static bool last_td_in_urb(struct xhci_td *td)
108 struct urb_priv *urb_priv = td->urb->hcpriv;
110 return urb_priv->num_tds_done == urb_priv->num_tds;
113 static void inc_td_cnt(struct urb *urb)
115 struct urb_priv *urb_priv = urb->hcpriv;
117 urb_priv->num_tds_done++;
120 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
122 if (trb_is_link(trb)) {
123 /* unchain chained link TRBs */
124 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
126 trb->generic.field[0] = 0;
127 trb->generic.field[1] = 0;
128 trb->generic.field[2] = 0;
129 /* Preserve only the cycle bit of this TRB */
130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
139 static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
144 if (trb_is_link(*trb)) {
146 *trb = ((*seg)->trbs);
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
156 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
158 /* event ring doesn't have link trbs, check for last trb */
159 if (ring->type == TYPE_EVENT) {
160 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
164 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
165 ring->cycle_state ^= 1;
166 ring->deq_seg = ring->deq_seg->next;
167 ring->dequeue = ring->deq_seg->trbs;
171 /* All other rings have link trbs */
172 if (!trb_is_link(ring->dequeue)) {
174 ring->num_trbs_free++;
176 while (trb_is_link(ring->dequeue)) {
177 ring->deq_seg = ring->deq_seg->next;
178 ring->dequeue = ring->deq_seg->trbs;
182 trace_xhci_inc_deq(ring);
188 * See Cycle bit rules. SW is the consumer for the event ring only.
189 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
192 * chain bit is set), then set the chain bit in all the following link TRBs.
193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
194 * have their chain bit cleared (so that each Link TRB is a separate TD).
196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
197 * set, but other sections talk about dealing with the chain bit set. This was
198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
201 * @more_trbs_coming: Will you enqueue more TRBs before calling
202 * prepare_transfer()?
204 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
205 bool more_trbs_coming)
208 union xhci_trb *next;
210 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
211 /* If this is not event ring, there is one less usable TRB */
212 if (!trb_is_link(ring->enqueue))
213 ring->num_trbs_free--;
214 next = ++(ring->enqueue);
216 /* Update the dequeue pointer further if that was a link TRB */
217 while (trb_is_link(next)) {
220 * If the caller doesn't plan on enqueueing more TDs before
221 * ringing the doorbell, then we don't want to give the link TRB
222 * to the hardware just yet. We'll give the link TRB back in
223 * prepare_ring() just before we enqueue the TD at the top of
226 if (!chain && !more_trbs_coming)
229 /* If we're not dealing with 0.95 hardware or isoc rings on
230 * AMD 0.96 host, carry over the chain bit of the previous TRB
231 * (which may mean the chain bit is cleared).
233 if (!(ring->type == TYPE_ISOC &&
234 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
235 !xhci_link_trb_quirk(xhci)) {
236 next->link.control &= cpu_to_le32(~TRB_CHAIN);
237 next->link.control |= cpu_to_le32(chain);
239 /* Give this link TRB to the hardware */
241 next->link.control ^= cpu_to_le32(TRB_CYCLE);
243 /* Toggle the cycle bit after the last ring segment. */
244 if (link_trb_toggles_cycle(next))
245 ring->cycle_state ^= 1;
247 ring->enq_seg = ring->enq_seg->next;
248 ring->enqueue = ring->enq_seg->trbs;
249 next = ring->enqueue;
252 trace_xhci_inc_enq(ring);
256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
257 * enqueue pointer will not advance into dequeue segment. See rules above.
259 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
260 unsigned int num_trbs)
262 int num_trbs_in_deq_seg;
264 if (ring->num_trbs_free < num_trbs)
267 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
268 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
269 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
276 /* Ring the host controller doorbell after placing a command on the ring */
277 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
279 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
282 xhci_dbg(xhci, "// Ding dong!\n");
283 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
284 /* Flush PCI posted writes */
285 readl(&xhci->dba->doorbell[0]);
288 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
290 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
293 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
295 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
300 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
301 * If there are other commands waiting then restart the ring and kick the timer.
302 * This must be called with command ring stopped and xhci->lock held.
304 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
305 struct xhci_command *cur_cmd)
307 struct xhci_command *i_cmd;
309 /* Turn all aborted commands in list to no-ops, then restart */
310 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
312 if (i_cmd->status != COMP_COMMAND_ABORTED)
315 i_cmd->status = COMP_COMMAND_RING_STOPPED;
317 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
320 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
323 * caller waiting for completion is called when command
324 * completion event is received for these no-op commands
328 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
330 /* ring command ring doorbell to restart the command ring */
331 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
332 !(xhci->xhc_state & XHCI_STATE_DYING)) {
333 xhci->current_cmd = cur_cmd;
334 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
335 xhci_ring_cmd_db(xhci);
339 /* Must be called with xhci->lock held, releases and aquires lock back */
340 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
345 xhci_dbg(xhci, "Abort command ring\n");
347 reinit_completion(&xhci->cmd_ring_stop_completion);
349 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
350 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
351 &xhci->op_regs->cmd_ring);
353 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
354 * completion of the Command Abort operation. If CRR is not negated in 5
355 * seconds then driver handles it as if host died (-ENODEV).
356 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
357 * and try to recover a -ETIMEDOUT with a host controller reset.
359 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
360 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
362 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
368 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
369 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
370 * but the completion event in never sent. Wait 2 secs (arbitrary
371 * number) to handle those cases after negation of CMD_RING_RUNNING.
373 spin_unlock_irqrestore(&xhci->lock, flags);
374 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
375 msecs_to_jiffies(2000));
376 spin_lock_irqsave(&xhci->lock, flags);
378 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
379 xhci_cleanup_command_queue(xhci);
381 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
386 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
387 unsigned int slot_id,
388 unsigned int ep_index,
389 unsigned int stream_id)
391 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
392 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
393 unsigned int ep_state = ep->ep_state;
395 /* Don't ring the doorbell for this endpoint if there are pending
396 * cancellations because we don't want to interrupt processing.
397 * We don't want to restart any stream rings if there's a set dequeue
398 * pointer command pending because the device can choose to start any
399 * stream once the endpoint is on the HW schedule.
401 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
402 (ep_state & EP_HALTED))
404 writel(DB_VALUE(ep_index, stream_id), db_addr);
405 /* The CPU has better things to do at this point than wait for a
406 * write-posting flush. It'll get there soon enough.
410 /* Ring the doorbell for any rings with pending URBs */
411 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
412 unsigned int slot_id,
413 unsigned int ep_index)
415 unsigned int stream_id;
416 struct xhci_virt_ep *ep;
418 ep = &xhci->devs[slot_id]->eps[ep_index];
420 /* A ring has pending URBs if its TD list is not empty */
421 if (!(ep->ep_state & EP_HAS_STREAMS)) {
422 if (ep->ring && !(list_empty(&ep->ring->td_list)))
423 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
427 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
429 struct xhci_stream_info *stream_info = ep->stream_info;
430 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
431 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
436 /* Get the right ring for the given slot_id, ep_index and stream_id.
437 * If the endpoint supports streams, boundary check the URB's stream ID.
438 * If the endpoint doesn't support streams, return the singular endpoint ring.
440 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
441 unsigned int slot_id, unsigned int ep_index,
442 unsigned int stream_id)
444 struct xhci_virt_ep *ep;
446 ep = &xhci->devs[slot_id]->eps[ep_index];
447 /* Common case: no streams */
448 if (!(ep->ep_state & EP_HAS_STREAMS))
451 if (stream_id == 0) {
453 "WARN: Slot ID %u, ep index %u has streams, "
454 "but URB has no stream ID.\n",
459 if (stream_id < ep->stream_info->num_streams)
460 return ep->stream_info->stream_rings[stream_id];
463 "WARN: Slot ID %u, ep index %u has "
464 "stream IDs 1 to %u allocated, "
465 "but stream ID %u is requested.\n",
467 ep->stream_info->num_streams - 1,
474 * Get the hw dequeue pointer xHC stopped on, either directly from the
475 * endpoint context, or if streams are in use from the stream context.
476 * The returned hw_dequeue contains the lowest four bits with cycle state
477 * and possbile stream context type.
479 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
480 unsigned int ep_index, unsigned int stream_id)
482 struct xhci_ep_ctx *ep_ctx;
483 struct xhci_stream_ctx *st_ctx;
484 struct xhci_virt_ep *ep;
486 ep = &vdev->eps[ep_index];
488 if (ep->ep_state & EP_HAS_STREAMS) {
489 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
490 return le64_to_cpu(st_ctx->stream_ring);
492 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
493 return le64_to_cpu(ep_ctx->deq);
497 * Move the xHC's endpoint ring dequeue pointer past cur_td.
498 * Record the new state of the xHC's endpoint ring dequeue segment,
499 * dequeue pointer, stream id, and new consumer cycle state in state.
500 * Update our internal representation of the ring's dequeue pointer.
502 * We do this in three jumps:
503 * - First we update our new ring state to be the same as when the xHC stopped.
504 * - Then we traverse the ring to find the segment that contains
505 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
506 * any link TRBs with the toggle cycle bit set.
507 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
508 * if we've moved it past a link TRB with the toggle cycle bit set.
510 * Some of the uses of xhci_generic_trb are grotty, but if they're done
511 * with correct __le32 accesses they should work fine. Only users of this are
514 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
515 unsigned int slot_id, unsigned int ep_index,
516 unsigned int stream_id, struct xhci_td *cur_td,
517 struct xhci_dequeue_state *state)
519 struct xhci_virt_device *dev = xhci->devs[slot_id];
520 struct xhci_virt_ep *ep = &dev->eps[ep_index];
521 struct xhci_ring *ep_ring;
522 struct xhci_segment *new_seg;
523 union xhci_trb *new_deq;
526 bool cycle_found = false;
527 bool td_last_trb_found = false;
529 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
530 ep_index, stream_id);
532 xhci_warn(xhci, "WARN can't find new dequeue state "
533 "for invalid stream ID %u.\n",
537 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
538 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
539 "Finding endpoint context");
541 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
542 new_seg = ep_ring->deq_seg;
543 new_deq = ep_ring->dequeue;
544 state->new_cycle_state = hw_dequeue & 0x1;
545 state->stream_id = stream_id;
548 * We want to find the pointer, segment and cycle state of the new trb
549 * (the one after current TD's last_trb). We know the cycle state at
550 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
554 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
555 == (dma_addr_t)(hw_dequeue & ~0xf)) {
557 if (td_last_trb_found)
560 if (new_deq == cur_td->last_trb)
561 td_last_trb_found = true;
563 if (cycle_found && trb_is_link(new_deq) &&
564 link_trb_toggles_cycle(new_deq))
565 state->new_cycle_state ^= 0x1;
567 next_trb(xhci, ep_ring, &new_seg, &new_deq);
569 /* Search wrapped around, bail out */
570 if (new_deq == ep->ring->dequeue) {
571 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
572 state->new_deq_seg = NULL;
573 state->new_deq_ptr = NULL;
577 } while (!cycle_found || !td_last_trb_found);
579 state->new_deq_seg = new_seg;
580 state->new_deq_ptr = new_deq;
582 /* Don't update the ring cycle state for the producer (us). */
583 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
584 "Cycle state = 0x%x", state->new_cycle_state);
586 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
587 "New dequeue segment = %p (virtual)",
589 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
590 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
591 "New dequeue pointer = 0x%llx (DMA)",
592 (unsigned long long) addr);
595 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
596 * (The last TRB actually points to the ring enqueue pointer, which is not part
597 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
599 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
600 struct xhci_td *td, bool flip_cycle)
602 struct xhci_segment *seg = td->start_seg;
603 union xhci_trb *trb = td->first_trb;
606 trb_to_noop(trb, TRB_TR_NOOP);
608 /* flip cycle if asked to */
609 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
610 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
612 if (trb == td->last_trb)
615 next_trb(xhci, ep_ring, &seg, &trb);
619 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
620 struct xhci_virt_ep *ep)
622 ep->ep_state &= ~EP_STOP_CMD_PENDING;
623 /* Can't del_timer_sync in interrupt */
624 del_timer(&ep->stop_cmd_timer);
628 * Must be called with xhci->lock held in interrupt context,
629 * releases and re-acquires xhci->lock
631 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
632 struct xhci_td *cur_td, int status)
634 struct urb *urb = cur_td->urb;
635 struct urb_priv *urb_priv = urb->hcpriv;
636 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
638 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
639 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
640 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
641 if (xhci->quirks & XHCI_AMD_PLL_FIX)
642 usb_amd_quirk_pll_enable();
645 xhci_urb_free_priv(urb_priv);
646 usb_hcd_unlink_urb_from_ep(hcd, urb);
647 spin_unlock(&xhci->lock);
648 trace_xhci_urb_giveback(urb);
649 usb_hcd_giveback_urb(hcd, urb, status);
650 spin_lock(&xhci->lock);
653 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
654 struct xhci_ring *ring, struct xhci_td *td)
656 struct device *dev = xhci_to_hcd(xhci)->self.controller;
657 struct xhci_segment *seg = td->bounce_seg;
658 struct urb *urb = td->urb;
660 if (!ring || !seg || !urb)
663 if (usb_urb_dir_out(urb)) {
664 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
669 /* for in tranfers we need to copy the data from bounce to sg */
670 sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf,
671 seg->bounce_len, seg->bounce_offs);
672 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
675 seg->bounce_offs = 0;
679 * When we get a command completion for a Stop Endpoint Command, we need to
680 * unlink any cancelled TDs from the ring. There are two ways to do that:
682 * 1. If the HW was in the middle of processing the TD that needs to be
683 * cancelled, then we must move the ring's dequeue pointer past the last TRB
684 * in the TD with a Set Dequeue Pointer Command.
685 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
686 * bit cleared) so that the HW will skip over them.
688 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
689 union xhci_trb *trb, struct xhci_event_cmd *event)
691 unsigned int ep_index;
692 struct xhci_ring *ep_ring;
693 struct xhci_virt_ep *ep;
694 struct xhci_td *cur_td = NULL;
695 struct xhci_td *last_unlinked_td;
696 struct xhci_ep_ctx *ep_ctx;
697 struct xhci_virt_device *vdev;
699 struct xhci_dequeue_state deq_state;
701 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
702 if (!xhci->devs[slot_id])
703 xhci_warn(xhci, "Stop endpoint command "
704 "completion for disabled slot %u\n",
709 memset(&deq_state, 0, sizeof(deq_state));
710 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
712 vdev = xhci->devs[slot_id];
713 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
714 trace_xhci_handle_cmd_stop_ep(ep_ctx);
716 ep = &xhci->devs[slot_id]->eps[ep_index];
717 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
718 struct xhci_td, cancelled_td_list);
720 if (list_empty(&ep->cancelled_td_list)) {
721 xhci_stop_watchdog_timer_in_irq(xhci, ep);
722 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
726 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
727 * We have the xHCI lock, so nothing can modify this list until we drop
728 * it. We're also in the event handler, so we can't get re-interrupted
729 * if another Stop Endpoint command completes
731 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
732 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
733 "Removing canceled TD starting at 0x%llx (dma).",
734 (unsigned long long)xhci_trb_virt_to_dma(
735 cur_td->start_seg, cur_td->first_trb));
736 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
738 /* This shouldn't happen unless a driver is mucking
739 * with the stream ID after submission. This will
740 * leave the TD on the hardware ring, and the hardware
741 * will try to execute it, and may access a buffer
742 * that has already been freed. In the best case, the
743 * hardware will execute it, and the event handler will
744 * ignore the completion event for that TD, since it was
745 * removed from the td_list for that endpoint. In
746 * short, don't muck with the stream ID after
749 xhci_warn(xhci, "WARN Cancelled URB %p "
750 "has invalid stream ID %u.\n",
752 cur_td->urb->stream_id);
753 goto remove_finished_td;
756 * If we stopped on the TD we need to cancel, then we have to
757 * move the xHC endpoint ring dequeue pointer past this TD.
759 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
760 cur_td->urb->stream_id);
763 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
764 cur_td->last_trb, hw_deq, false)) {
765 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
766 cur_td->urb->stream_id,
769 td_to_noop(xhci, ep_ring, cur_td, false);
774 * The event handler won't see a completion for this TD anymore,
775 * so remove it from the endpoint ring's TD list. Keep it in
776 * the cancelled TD list for URB completion later.
778 list_del_init(&cur_td->td_list);
781 xhci_stop_watchdog_timer_in_irq(xhci, ep);
783 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
784 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
785 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
787 xhci_ring_cmd_db(xhci);
789 /* Otherwise ring the doorbell(s) to restart queued transfers */
790 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
794 * Drop the lock and complete the URBs in the cancelled TD list.
795 * New TDs to be cancelled might be added to the end of the list before
796 * we can complete all the URBs for the TDs we already unlinked.
797 * So stop when we've completed the URB for the last TD we unlinked.
800 cur_td = list_first_entry(&ep->cancelled_td_list,
801 struct xhci_td, cancelled_td_list);
802 list_del_init(&cur_td->cancelled_td_list);
804 /* Clean up the cancelled URB */
805 /* Doesn't matter what we pass for status, since the core will
806 * just overwrite it (because the URB has been unlinked).
808 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
809 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
810 inc_td_cnt(cur_td->urb);
811 if (last_td_in_urb(cur_td))
812 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
814 /* Stop processing the cancelled list if the watchdog timer is
817 if (xhci->xhc_state & XHCI_STATE_DYING)
819 } while (cur_td != last_unlinked_td);
821 /* Return to the event handler with xhci->lock re-acquired */
824 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
826 struct xhci_td *cur_td;
829 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
830 list_del_init(&cur_td->td_list);
832 if (!list_empty(&cur_td->cancelled_td_list))
833 list_del_init(&cur_td->cancelled_td_list);
835 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
837 inc_td_cnt(cur_td->urb);
838 if (last_td_in_urb(cur_td))
839 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
843 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
844 int slot_id, int ep_index)
846 struct xhci_td *cur_td;
848 struct xhci_virt_ep *ep;
849 struct xhci_ring *ring;
851 ep = &xhci->devs[slot_id]->eps[ep_index];
852 if ((ep->ep_state & EP_HAS_STREAMS) ||
853 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
856 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
858 ring = ep->stream_info->stream_rings[stream_id];
862 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
863 "Killing URBs for slot ID %u, ep index %u, stream %u",
864 slot_id, ep_index, stream_id);
865 xhci_kill_ring_urbs(xhci, ring);
871 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
872 "Killing URBs for slot ID %u, ep index %u",
874 xhci_kill_ring_urbs(xhci, ring);
877 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
879 list_del_init(&cur_td->cancelled_td_list);
880 inc_td_cnt(cur_td->urb);
882 if (last_td_in_urb(cur_td))
883 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
888 * host controller died, register read returns 0xffffffff
889 * Complete pending commands, mark them ABORTED.
890 * URBs need to be given back as usb core might be waiting with device locks
891 * held for the URBs to finish during device disconnect, blocking host remove.
893 * Call with xhci->lock held.
894 * lock is relased and re-acquired while giving back urb.
896 void xhci_hc_died(struct xhci_hcd *xhci)
900 if (xhci->xhc_state & XHCI_STATE_DYING)
903 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
904 xhci->xhc_state |= XHCI_STATE_DYING;
906 xhci_cleanup_command_queue(xhci);
908 /* return any pending urbs, remove may be waiting for them */
909 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
912 for (j = 0; j < 31; j++)
913 xhci_kill_endpoint_urbs(xhci, i, j);
916 /* inform usb core hc died if PCI remove isn't already handling it */
917 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
918 usb_hc_died(xhci_to_hcd(xhci));
921 /* Watchdog timer function for when a stop endpoint command fails to complete.
922 * In this case, we assume the host controller is broken or dying or dead. The
923 * host may still be completing some other events, so we have to be careful to
924 * let the event ring handler and the URB dequeueing/enqueueing functions know
925 * through xhci->state.
927 * The timer may also fire if the host takes a very long time to respond to the
928 * command, and the stop endpoint command completion handler cannot delete the
929 * timer before the timer function is called. Another endpoint cancellation may
930 * sneak in before the timer function can grab the lock, and that may queue
931 * another stop endpoint command and add the timer back. So we cannot use a
932 * simple flag to say whether there is a pending stop endpoint command for a
933 * particular endpoint.
935 * Instead we use a combination of that flag and checking if a new timer is
938 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
940 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
941 struct xhci_hcd *xhci = ep->xhci;
944 spin_lock_irqsave(&xhci->lock, flags);
946 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
947 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
948 timer_pending(&ep->stop_cmd_timer)) {
949 spin_unlock_irqrestore(&xhci->lock, flags);
950 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
954 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
955 ep->ep_state &= ~EP_STOP_CMD_PENDING;
960 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
961 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
962 * and try to recover a -ETIMEDOUT with a host controller reset
966 spin_unlock_irqrestore(&xhci->lock, flags);
967 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
968 "xHCI host controller is dead.");
971 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
972 struct xhci_virt_device *dev,
973 struct xhci_ring *ep_ring,
974 unsigned int ep_index)
976 union xhci_trb *dequeue_temp;
977 int num_trbs_free_temp;
980 num_trbs_free_temp = ep_ring->num_trbs_free;
981 dequeue_temp = ep_ring->dequeue;
983 /* If we get two back-to-back stalls, and the first stalled transfer
984 * ends just before a link TRB, the dequeue pointer will be left on
985 * the link TRB by the code in the while loop. So we have to update
986 * the dequeue pointer one segment further, or we'll jump off
987 * the segment into la-la-land.
989 if (trb_is_link(ep_ring->dequeue)) {
990 ep_ring->deq_seg = ep_ring->deq_seg->next;
991 ep_ring->dequeue = ep_ring->deq_seg->trbs;
994 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
995 /* We have more usable TRBs */
996 ep_ring->num_trbs_free++;
998 if (trb_is_link(ep_ring->dequeue)) {
999 if (ep_ring->dequeue ==
1000 dev->eps[ep_index].queued_deq_ptr)
1002 ep_ring->deq_seg = ep_ring->deq_seg->next;
1003 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1005 if (ep_ring->dequeue == dequeue_temp) {
1012 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1013 ep_ring->num_trbs_free = num_trbs_free_temp;
1018 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1019 * we need to clear the set deq pending flag in the endpoint ring state, so that
1020 * the TD queueing code can ring the doorbell again. We also need to ring the
1021 * endpoint doorbell to restart the ring, but only if there aren't more
1022 * cancellations pending.
1024 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1025 union xhci_trb *trb, u32 cmd_comp_code)
1027 unsigned int ep_index;
1028 unsigned int stream_id;
1029 struct xhci_ring *ep_ring;
1030 struct xhci_virt_device *dev;
1031 struct xhci_virt_ep *ep;
1032 struct xhci_ep_ctx *ep_ctx;
1033 struct xhci_slot_ctx *slot_ctx;
1035 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1036 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1037 dev = xhci->devs[slot_id];
1038 ep = &dev->eps[ep_index];
1040 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1042 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1044 /* XXX: Harmless??? */
1048 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1049 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1050 trace_xhci_handle_cmd_set_deq(slot_ctx);
1051 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1053 if (cmd_comp_code != COMP_SUCCESS) {
1054 unsigned int ep_state;
1055 unsigned int slot_state;
1057 switch (cmd_comp_code) {
1058 case COMP_TRB_ERROR:
1059 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1061 case COMP_CONTEXT_STATE_ERROR:
1062 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1063 ep_state = GET_EP_CTX_STATE(ep_ctx);
1064 slot_state = le32_to_cpu(slot_ctx->dev_state);
1065 slot_state = GET_SLOT_STATE(slot_state);
1066 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1067 "Slot state = %u, EP state = %u",
1068 slot_state, ep_state);
1070 case COMP_SLOT_NOT_ENABLED_ERROR:
1071 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1075 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1079 /* OK what do we do now? The endpoint state is hosed, and we
1080 * should never get to this point if the synchronization between
1081 * queueing, and endpoint state are correct. This might happen
1082 * if the device gets disconnected after we've finished
1083 * cancelling URBs, which might not be an error...
1087 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1088 if (ep->ep_state & EP_HAS_STREAMS) {
1089 struct xhci_stream_ctx *ctx =
1090 &ep->stream_info->stream_ctx_array[stream_id];
1091 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1093 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1095 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1096 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1097 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1098 ep->queued_deq_ptr) == deq) {
1099 /* Update the ring's dequeue segment and dequeue pointer
1100 * to reflect the new position.
1102 update_ring_for_set_deq_completion(xhci, dev,
1105 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1106 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1107 ep->queued_deq_seg, ep->queued_deq_ptr);
1112 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1113 dev->eps[ep_index].queued_deq_seg = NULL;
1114 dev->eps[ep_index].queued_deq_ptr = NULL;
1115 /* Restart any rings with pending URBs */
1116 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1119 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1120 union xhci_trb *trb, u32 cmd_comp_code)
1122 struct xhci_virt_device *vdev;
1123 struct xhci_ep_ctx *ep_ctx;
1124 unsigned int ep_index;
1126 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1127 vdev = xhci->devs[slot_id];
1128 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1129 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1131 /* This command will only fail if the endpoint wasn't halted,
1132 * but we don't care.
1134 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1135 "Ignoring reset ep completion code of %u", cmd_comp_code);
1137 /* HW with the reset endpoint quirk needs to have a configure endpoint
1138 * command complete before the endpoint can be used. Queue that here
1139 * because the HW can't handle two commands being queued in a row.
1141 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1142 struct xhci_command *command;
1144 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1148 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1149 "Queueing configure endpoint command");
1150 xhci_queue_configure_endpoint(xhci, command,
1151 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1153 xhci_ring_cmd_db(xhci);
1155 /* Clear our internal halted state */
1156 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1159 /* if this was a soft reset, then restart */
1160 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1161 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1164 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1165 struct xhci_command *command, u32 cmd_comp_code)
1167 if (cmd_comp_code == COMP_SUCCESS)
1168 command->slot_id = slot_id;
1170 command->slot_id = 0;
1173 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1175 struct xhci_virt_device *virt_dev;
1176 struct xhci_slot_ctx *slot_ctx;
1178 virt_dev = xhci->devs[slot_id];
1182 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1183 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1185 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1186 /* Delete default control endpoint resources */
1187 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1188 xhci_free_virt_device(xhci, slot_id);
1191 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1192 struct xhci_event_cmd *event, u32 cmd_comp_code)
1194 struct xhci_virt_device *virt_dev;
1195 struct xhci_input_control_ctx *ctrl_ctx;
1196 struct xhci_ep_ctx *ep_ctx;
1197 unsigned int ep_index;
1198 unsigned int ep_state;
1199 u32 add_flags, drop_flags;
1202 * Configure endpoint commands can come from the USB core
1203 * configuration or alt setting changes, or because the HW
1204 * needed an extra configure endpoint command after a reset
1205 * endpoint command or streams were being configured.
1206 * If the command was for a halted endpoint, the xHCI driver
1207 * is not waiting on the configure endpoint command.
1209 virt_dev = xhci->devs[slot_id];
1210 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1212 xhci_warn(xhci, "Could not get input context, bad type.\n");
1216 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1217 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1218 /* Input ctx add_flags are the endpoint index plus one */
1219 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1221 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1222 trace_xhci_handle_cmd_config_ep(ep_ctx);
1224 /* A usb_set_interface() call directly after clearing a halted
1225 * condition may race on this quirky hardware. Not worth
1226 * worrying about, since this is prototype hardware. Not sure
1227 * if this will work for streams, but streams support was
1228 * untested on this prototype.
1230 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1231 ep_index != (unsigned int) -1 &&
1232 add_flags - SLOT_FLAG == drop_flags) {
1233 ep_state = virt_dev->eps[ep_index].ep_state;
1234 if (!(ep_state & EP_HALTED))
1236 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1237 "Completed config ep cmd - "
1238 "last ep index = %d, state = %d",
1239 ep_index, ep_state);
1240 /* Clear internal halted state and restart ring(s) */
1241 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1242 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1248 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1250 struct xhci_virt_device *vdev;
1251 struct xhci_slot_ctx *slot_ctx;
1253 vdev = xhci->devs[slot_id];
1254 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1255 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1258 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1259 struct xhci_event_cmd *event)
1261 struct xhci_virt_device *vdev;
1262 struct xhci_slot_ctx *slot_ctx;
1264 vdev = xhci->devs[slot_id];
1265 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1266 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1268 xhci_dbg(xhci, "Completed reset device command.\n");
1269 if (!xhci->devs[slot_id])
1270 xhci_warn(xhci, "Reset device command completion "
1271 "for disabled slot %u\n", slot_id);
1274 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1275 struct xhci_event_cmd *event)
1277 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1278 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1281 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1282 "NEC firmware version %2x.%02x",
1283 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1284 NEC_FW_MINOR(le32_to_cpu(event->status)));
1287 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1289 list_del(&cmd->cmd_list);
1291 if (cmd->completion) {
1292 cmd->status = status;
1293 complete(cmd->completion);
1299 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1301 struct xhci_command *cur_cmd, *tmp_cmd;
1302 xhci->current_cmd = NULL;
1303 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1304 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1307 void xhci_handle_command_timeout(struct work_struct *work)
1309 struct xhci_hcd *xhci;
1310 unsigned long flags;
1313 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1315 spin_lock_irqsave(&xhci->lock, flags);
1318 * If timeout work is pending, or current_cmd is NULL, it means we
1319 * raced with command completion. Command is handled so just return.
1321 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1322 spin_unlock_irqrestore(&xhci->lock, flags);
1325 /* mark this command to be cancelled */
1326 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1328 /* Make sure command ring is running before aborting it */
1329 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1330 if (hw_ring_state == ~(u64)0) {
1332 goto time_out_completed;
1335 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1336 (hw_ring_state & CMD_RING_RUNNING)) {
1337 /* Prevent new doorbell, and start command abort */
1338 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1339 xhci_dbg(xhci, "Command timeout\n");
1340 xhci_abort_cmd_ring(xhci, flags);
1341 goto time_out_completed;
1344 /* host removed. Bail out */
1345 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1346 xhci_dbg(xhci, "host removed, ring start fail?\n");
1347 xhci_cleanup_command_queue(xhci);
1349 goto time_out_completed;
1352 /* command timeout on stopped ring, ring can't be aborted */
1353 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1354 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1357 spin_unlock_irqrestore(&xhci->lock, flags);
1361 static void handle_cmd_completion(struct xhci_hcd *xhci,
1362 struct xhci_event_cmd *event)
1364 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1366 dma_addr_t cmd_dequeue_dma;
1368 union xhci_trb *cmd_trb;
1369 struct xhci_command *cmd;
1372 cmd_dma = le64_to_cpu(event->cmd_trb);
1373 cmd_trb = xhci->cmd_ring->dequeue;
1375 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1377 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1380 * Check whether the completion event is for our internal kept
1383 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1385 "ERROR mismatched command completion event\n");
1389 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1391 cancel_delayed_work(&xhci->cmd_timer);
1393 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1395 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1396 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1397 complete_all(&xhci->cmd_ring_stop_completion);
1401 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1403 "Command completion event does not match command\n");
1408 * Host aborted the command ring, check if the current command was
1409 * supposed to be aborted, otherwise continue normally.
1410 * The command ring is stopped now, but the xHC will issue a Command
1411 * Ring Stopped event which will cause us to restart it.
1413 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1414 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1415 if (cmd->status == COMP_COMMAND_ABORTED) {
1416 if (xhci->current_cmd == cmd)
1417 xhci->current_cmd = NULL;
1422 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1424 case TRB_ENABLE_SLOT:
1425 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1427 case TRB_DISABLE_SLOT:
1428 xhci_handle_cmd_disable_slot(xhci, slot_id);
1431 if (!cmd->completion)
1432 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1435 case TRB_EVAL_CONTEXT:
1438 xhci_handle_cmd_addr_dev(xhci, slot_id);
1441 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1442 le32_to_cpu(cmd_trb->generic.field[3])));
1443 if (!cmd->completion)
1444 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1447 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1448 le32_to_cpu(cmd_trb->generic.field[3])));
1449 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1452 /* Is this an aborted command turned to NO-OP? */
1453 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1454 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1457 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1458 le32_to_cpu(cmd_trb->generic.field[3])));
1459 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1462 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1463 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1465 slot_id = TRB_TO_SLOT_ID(
1466 le32_to_cpu(cmd_trb->generic.field[3]));
1467 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1469 case TRB_NEC_GET_FW:
1470 xhci_handle_cmd_nec_get_fw(xhci, event);
1473 /* Skip over unknown commands on the event ring */
1474 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1478 /* restart timer if this wasn't the last command */
1479 if (!list_is_singular(&xhci->cmd_list)) {
1480 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1481 struct xhci_command, cmd_list);
1482 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1483 } else if (xhci->current_cmd == cmd) {
1484 xhci->current_cmd = NULL;
1488 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1490 inc_deq(xhci, xhci->cmd_ring);
1493 static void handle_vendor_event(struct xhci_hcd *xhci,
1494 union xhci_trb *event)
1498 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1499 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1500 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1501 handle_cmd_completion(xhci, &event->event_cmd);
1504 static void handle_device_notification(struct xhci_hcd *xhci,
1505 union xhci_trb *event)
1508 struct usb_device *udev;
1510 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1511 if (!xhci->devs[slot_id]) {
1512 xhci_warn(xhci, "Device Notification event for "
1513 "unused slot %u\n", slot_id);
1517 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1519 udev = xhci->devs[slot_id]->udev;
1520 if (udev && udev->parent)
1521 usb_wakeup_notification(udev->parent, udev->portnum);
1525 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1527 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1528 * If a connection to a USB 1 device is followed by another connection
1529 * to a USB 2 device.
1531 * Reset the PHY after the USB device is disconnected if device speed
1532 * is less than HCD_USB3.
1533 * Retry the reset sequence max of 4 times checking the PLL lock status.
1536 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1538 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1540 u32 retry_count = 4;
1543 /* Assert PHY reset */
1544 writel(0x6F, hcd->regs + 0x1048);
1546 /* De-assert the PHY reset */
1547 writel(0x7F, hcd->regs + 0x1048);
1549 pll_lock_check = readl(hcd->regs + 0x1070);
1550 } while (!(pll_lock_check & 0x1) && --retry_count);
1553 static void handle_port_status(struct xhci_hcd *xhci,
1554 union xhci_trb *event)
1556 struct usb_hcd *hcd;
1558 u32 portsc, cmd_reg;
1561 unsigned int hcd_portnum;
1562 struct xhci_bus_state *bus_state;
1563 bool bogus_port_status = false;
1564 struct xhci_port *port;
1566 /* Port status change events always have a successful completion code */
1567 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1569 "WARN: xHC returned failed port status event\n");
1571 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1572 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1574 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1575 if ((port_id <= 0) || (port_id > max_ports)) {
1576 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1577 inc_deq(xhci, xhci->event_ring);
1581 port = &xhci->hw_ports[port_id - 1];
1582 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1583 xhci_warn(xhci, "Event for invalid port %u\n", port_id);
1584 bogus_port_status = true;
1588 /* We might get interrupts after shared_hcd is removed */
1589 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1590 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1591 bogus_port_status = true;
1595 hcd = port->rhub->hcd;
1596 bus_state = &port->rhub->bus_state;
1597 hcd_portnum = port->hcd_portnum;
1598 portsc = readl(port->addr);
1600 trace_xhci_handle_port_status(hcd_portnum, portsc);
1602 if (hcd->state == HC_STATE_SUSPENDED) {
1603 xhci_dbg(xhci, "resume root hub\n");
1604 usb_hcd_resume_root_hub(hcd);
1607 if (hcd->speed >= HCD_USB3 && (portsc & PORT_PLS_MASK) == XDEV_INACTIVE)
1608 bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
1610 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1611 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1613 cmd_reg = readl(&xhci->op_regs->command);
1614 if (!(cmd_reg & CMD_RUN)) {
1615 xhci_warn(xhci, "xHC is not running.\n");
1619 if (DEV_SUPERSPEED_ANY(portsc)) {
1620 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1621 /* Set a flag to say the port signaled remote wakeup,
1622 * so we can tell the difference between the end of
1623 * device and host initiated resume.
1625 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1626 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1627 xhci_set_link_state(xhci, port, XDEV_U0);
1628 /* Need to wait until the next link state change
1629 * indicates the device is actually in U0.
1631 bogus_port_status = true;
1633 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1634 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1635 bus_state->resume_done[hcd_portnum] = jiffies +
1636 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1637 set_bit(hcd_portnum, &bus_state->resuming_ports);
1638 /* Do the rest in GetPortStatus after resume time delay.
1639 * Avoid polling roothub status before that so that a
1640 * usb device auto-resume latency around ~40ms.
1642 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1643 mod_timer(&hcd->rh_timer,
1644 bus_state->resume_done[hcd_portnum]);
1645 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1646 bogus_port_status = true;
1650 if ((portsc & PORT_PLC) &&
1651 DEV_SUPERSPEED_ANY(portsc) &&
1652 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1653 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1654 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1655 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1656 /* We've just brought the device into U0/1/2 through either the
1657 * Resume state after a device remote wakeup, or through the
1658 * U3Exit state after a host-initiated resume. If it's a device
1659 * initiated remote wake, don't pass up the link state change,
1660 * so the roothub behavior is consistent with external
1661 * USB 3.0 hub behavior.
1663 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1664 if (slot_id && xhci->devs[slot_id])
1665 xhci_ring_device(xhci, slot_id);
1666 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1667 bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
1668 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1669 usb_wakeup_notification(hcd->self.root_hub,
1671 bogus_port_status = true;
1677 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1678 * RExit to a disconnect state). If so, let the the driver know it's
1679 * out of the RExit state.
1681 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1682 test_and_clear_bit(hcd_portnum,
1683 &bus_state->rexit_ports)) {
1684 complete(&bus_state->rexit_done[hcd_portnum]);
1685 bogus_port_status = true;
1689 if (hcd->speed < HCD_USB3) {
1690 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1691 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1692 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1693 xhci_cavium_reset_phy_quirk(xhci);
1697 /* Update event ring dequeue pointer before dropping the lock */
1698 inc_deq(xhci, xhci->event_ring);
1700 /* Don't make the USB core poll the roothub if we got a bad port status
1701 * change event. Besides, at that point we can't tell which roothub
1702 * (USB 2.0 or USB 3.0) to kick.
1704 if (bogus_port_status)
1708 * xHCI port-status-change events occur when the "or" of all the
1709 * status-change bits in the portsc register changes from 0 to 1.
1710 * New status changes won't cause an event if any other change
1711 * bits are still set. When an event occurs, switch over to
1712 * polling to avoid losing status changes.
1714 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1715 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1716 spin_unlock(&xhci->lock);
1717 /* Pass this up to the core */
1718 usb_hcd_poll_rh_status(hcd);
1719 spin_lock(&xhci->lock);
1723 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1724 * at end_trb, which may be in another segment. If the suspect DMA address is a
1725 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1728 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1729 struct xhci_segment *start_seg,
1730 union xhci_trb *start_trb,
1731 union xhci_trb *end_trb,
1732 dma_addr_t suspect_dma,
1735 dma_addr_t start_dma;
1736 dma_addr_t end_seg_dma;
1737 dma_addr_t end_trb_dma;
1738 struct xhci_segment *cur_seg;
1740 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1741 cur_seg = start_seg;
1746 /* We may get an event for a Link TRB in the middle of a TD */
1747 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1748 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1749 /* If the end TRB isn't in this segment, this is set to 0 */
1750 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1754 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1755 (unsigned long long)suspect_dma,
1756 (unsigned long long)start_dma,
1757 (unsigned long long)end_trb_dma,
1758 (unsigned long long)cur_seg->dma,
1759 (unsigned long long)end_seg_dma);
1761 if (end_trb_dma > 0) {
1762 /* The end TRB is in this segment, so suspect should be here */
1763 if (start_dma <= end_trb_dma) {
1764 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1767 /* Case for one segment with
1768 * a TD wrapped around to the top
1770 if ((suspect_dma >= start_dma &&
1771 suspect_dma <= end_seg_dma) ||
1772 (suspect_dma >= cur_seg->dma &&
1773 suspect_dma <= end_trb_dma))
1778 /* Might still be somewhere in this segment */
1779 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1782 cur_seg = cur_seg->next;
1783 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1784 } while (cur_seg != start_seg);
1789 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1790 unsigned int slot_id, unsigned int ep_index,
1791 unsigned int stream_id, struct xhci_td *td,
1792 enum xhci_ep_reset_type reset_type)
1794 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1795 struct xhci_command *command;
1796 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1800 ep->ep_state |= EP_HALTED;
1802 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1804 if (reset_type == EP_HARD_RESET) {
1805 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1806 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1808 xhci_ring_cmd_db(xhci);
1811 /* Check if an error has halted the endpoint ring. The class driver will
1812 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1813 * However, a babble and other errors also halt the endpoint ring, and the class
1814 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1815 * Ring Dequeue Pointer command manually.
1817 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1818 struct xhci_ep_ctx *ep_ctx,
1819 unsigned int trb_comp_code)
1821 /* TRB completion codes that may require a manual halt cleanup */
1822 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1823 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1824 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1825 /* The 0.95 spec says a babbling control endpoint
1826 * is not halted. The 0.96 spec says it is. Some HW
1827 * claims to be 0.95 compliant, but it halts the control
1828 * endpoint anyway. Check if a babble halted the
1831 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1837 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1839 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1840 /* Vendor defined "informational" completion code,
1841 * treat as not-an-error.
1843 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1845 xhci_dbg(xhci, "Treating code as success.\n");
1851 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1852 struct xhci_ring *ep_ring, int *status)
1854 struct urb *urb = NULL;
1856 /* Clean up the endpoint's TD list */
1859 /* if a bounce buffer was used to align this td then unmap it */
1860 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1862 /* Do one last check of the actual transfer length.
1863 * If the host controller said we transferred more data than the buffer
1864 * length, urb->actual_length will be a very big number (since it's
1865 * unsigned). Play it safe and say we didn't transfer anything.
1867 if (urb->actual_length > urb->transfer_buffer_length) {
1868 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1869 urb->transfer_buffer_length, urb->actual_length);
1870 urb->actual_length = 0;
1873 list_del_init(&td->td_list);
1874 /* Was this TD slated to be cancelled but completed anyway? */
1875 if (!list_empty(&td->cancelled_td_list))
1876 list_del_init(&td->cancelled_td_list);
1879 /* Giveback the urb when all the tds are completed */
1880 if (last_td_in_urb(td)) {
1881 if ((urb->actual_length != urb->transfer_buffer_length &&
1882 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1883 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1884 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1885 urb, urb->actual_length,
1886 urb->transfer_buffer_length, *status);
1888 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
1889 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1891 xhci_giveback_urb_in_irq(xhci, td, *status);
1897 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1898 struct xhci_transfer_event *event,
1899 struct xhci_virt_ep *ep, int *status)
1901 struct xhci_virt_device *xdev;
1902 struct xhci_ep_ctx *ep_ctx;
1903 struct xhci_ring *ep_ring;
1904 unsigned int slot_id;
1908 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1909 xdev = xhci->devs[slot_id];
1910 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1911 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1912 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1913 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1915 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1916 trb_comp_code == COMP_STOPPED ||
1917 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1918 /* The Endpoint Stop Command completion will take care of any
1919 * stopped TDs. A stopped TD may be restarted, so don't update
1920 * the ring dequeue pointer or take this TD off any lists yet.
1924 if (trb_comp_code == COMP_STALL_ERROR ||
1925 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1927 /* Issue a reset endpoint command to clear the host side
1928 * halt, followed by a set dequeue command to move the
1929 * dequeue pointer past the TD.
1930 * The class driver clears the device side halt later.
1932 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1933 ep_ring->stream_id, td, EP_HARD_RESET);
1935 /* Update ring dequeue pointer */
1936 while (ep_ring->dequeue != td->last_trb)
1937 inc_deq(xhci, ep_ring);
1938 inc_deq(xhci, ep_ring);
1941 return xhci_td_cleanup(xhci, td, ep_ring, status);
1944 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
1945 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
1946 union xhci_trb *stop_trb)
1949 union xhci_trb *trb = ring->dequeue;
1950 struct xhci_segment *seg = ring->deq_seg;
1952 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
1953 if (!trb_is_noop(trb) && !trb_is_link(trb))
1954 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
1960 * Process control tds, update urb status and actual_length.
1962 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1963 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
1964 struct xhci_virt_ep *ep, int *status)
1966 struct xhci_virt_device *xdev;
1967 unsigned int slot_id;
1969 struct xhci_ep_ctx *ep_ctx;
1971 u32 remaining, requested;
1974 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
1975 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1976 xdev = xhci->devs[slot_id];
1977 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1978 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1979 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1980 requested = td->urb->transfer_buffer_length;
1981 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1983 switch (trb_comp_code) {
1985 if (trb_type != TRB_STATUS) {
1986 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
1987 (trb_type == TRB_DATA) ? "data" : "setup");
1988 *status = -ESHUTDOWN;
1993 case COMP_SHORT_PACKET:
1996 case COMP_STOPPED_SHORT_PACKET:
1997 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
1998 td->urb->actual_length = remaining;
2000 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2005 td->urb->actual_length = 0;
2009 td->urb->actual_length = requested - remaining;
2012 td->urb->actual_length = requested;
2015 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2019 case COMP_STOPPED_LENGTH_INVALID:
2022 if (!xhci_requires_manual_halt_cleanup(xhci,
2023 ep_ctx, trb_comp_code))
2025 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2026 trb_comp_code, ep_index);
2027 /* else fall through */
2028 case COMP_STALL_ERROR:
2029 /* Did we transfer part of the data (middle) phase? */
2030 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2031 td->urb->actual_length = requested - remaining;
2032 else if (!td->urb_length_set)
2033 td->urb->actual_length = 0;
2037 /* stopped at setup stage, no data transferred */
2038 if (trb_type == TRB_SETUP)
2042 * if on data stage then update the actual_length of the URB and flag it
2043 * as set, so it won't be overwritten in the event for the last TRB.
2045 if (trb_type == TRB_DATA ||
2046 trb_type == TRB_NORMAL) {
2047 td->urb_length_set = true;
2048 td->urb->actual_length = requested - remaining;
2049 xhci_dbg(xhci, "Waiting for status stage event\n");
2053 /* at status stage */
2054 if (!td->urb_length_set)
2055 td->urb->actual_length = requested;
2058 return finish_td(xhci, td, event, ep, status);
2062 * Process isochronous tds, update urb packet status and actual_length.
2064 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2065 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2066 struct xhci_virt_ep *ep, int *status)
2068 struct xhci_ring *ep_ring;
2069 struct urb_priv *urb_priv;
2071 struct usb_iso_packet_descriptor *frame;
2073 bool sum_trbs_for_length = false;
2074 u32 remaining, requested, ep_trb_len;
2075 int short_framestatus;
2077 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2078 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2079 urb_priv = td->urb->hcpriv;
2080 idx = urb_priv->num_tds_done;
2081 frame = &td->urb->iso_frame_desc[idx];
2082 requested = frame->length;
2083 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2084 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2085 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2088 /* handle completion code */
2089 switch (trb_comp_code) {
2092 frame->status = short_framestatus;
2093 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2094 sum_trbs_for_length = true;
2099 case COMP_SHORT_PACKET:
2100 frame->status = short_framestatus;
2101 sum_trbs_for_length = true;
2103 case COMP_BANDWIDTH_OVERRUN_ERROR:
2104 frame->status = -ECOMM;
2106 case COMP_ISOCH_BUFFER_OVERRUN:
2107 case COMP_BABBLE_DETECTED_ERROR:
2108 frame->status = -EOVERFLOW;
2110 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2111 case COMP_STALL_ERROR:
2112 frame->status = -EPROTO;
2114 case COMP_USB_TRANSACTION_ERROR:
2115 frame->status = -EPROTO;
2116 if (ep_trb != td->last_trb)
2120 sum_trbs_for_length = true;
2122 case COMP_STOPPED_SHORT_PACKET:
2123 /* field normally containing residue now contains tranferred */
2124 frame->status = short_framestatus;
2125 requested = remaining;
2127 case COMP_STOPPED_LENGTH_INVALID:
2132 sum_trbs_for_length = true;
2137 if (sum_trbs_for_length)
2138 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2139 ep_trb_len - remaining;
2141 frame->actual_length = requested;
2143 td->urb->actual_length += frame->actual_length;
2145 return finish_td(xhci, td, event, ep, status);
2148 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2149 struct xhci_transfer_event *event,
2150 struct xhci_virt_ep *ep, int *status)
2152 struct xhci_ring *ep_ring;
2153 struct urb_priv *urb_priv;
2154 struct usb_iso_packet_descriptor *frame;
2157 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2158 urb_priv = td->urb->hcpriv;
2159 idx = urb_priv->num_tds_done;
2160 frame = &td->urb->iso_frame_desc[idx];
2162 /* The transfer is partly done. */
2163 frame->status = -EXDEV;
2165 /* calc actual length */
2166 frame->actual_length = 0;
2168 /* Update ring dequeue pointer */
2169 while (ep_ring->dequeue != td->last_trb)
2170 inc_deq(xhci, ep_ring);
2171 inc_deq(xhci, ep_ring);
2173 return xhci_td_cleanup(xhci, td, ep_ring, status);
2177 * Process bulk and interrupt tds, update urb status and actual_length.
2179 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2180 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2181 struct xhci_virt_ep *ep, int *status)
2183 struct xhci_slot_ctx *slot_ctx;
2184 struct xhci_ring *ep_ring;
2186 u32 remaining, requested, ep_trb_len;
2187 unsigned int slot_id;
2190 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2191 slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[slot_id]->out_ctx);
2192 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2193 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2194 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2195 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2196 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2197 requested = td->urb->transfer_buffer_length;
2199 switch (trb_comp_code) {
2201 ep_ring->err_count = 0;
2202 /* handle success with untransferred data as short packet */
2203 if (ep_trb != td->last_trb || remaining) {
2204 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2205 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2206 td->urb->ep->desc.bEndpointAddress,
2207 requested, remaining);
2211 case COMP_SHORT_PACKET:
2212 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2213 td->urb->ep->desc.bEndpointAddress,
2214 requested, remaining);
2217 case COMP_STOPPED_SHORT_PACKET:
2218 td->urb->actual_length = remaining;
2220 case COMP_STOPPED_LENGTH_INVALID:
2221 /* stopped on ep trb with invalid length, exclude it */
2225 case COMP_USB_TRANSACTION_ERROR:
2226 if ((ep_ring->err_count++ > MAX_SOFT_RETRY) ||
2227 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2230 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2231 ep_ring->stream_id, td, EP_SOFT_RESET);
2238 if (ep_trb == td->last_trb)
2239 td->urb->actual_length = requested - remaining;
2241 td->urb->actual_length =
2242 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2243 ep_trb_len - remaining;
2245 if (remaining > requested) {
2246 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2248 td->urb->actual_length = 0;
2250 return finish_td(xhci, td, event, ep, status);
2254 * If this function returns an error condition, it means it got a Transfer
2255 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2256 * At this point, the host controller is probably hosed and should be reset.
2258 static int handle_tx_event(struct xhci_hcd *xhci,
2259 struct xhci_transfer_event *event)
2261 struct xhci_virt_device *xdev;
2262 struct xhci_virt_ep *ep;
2263 struct xhci_ring *ep_ring;
2264 unsigned int slot_id;
2266 struct xhci_td *td = NULL;
2267 dma_addr_t ep_trb_dma;
2268 struct xhci_segment *ep_seg;
2269 union xhci_trb *ep_trb;
2270 int status = -EINPROGRESS;
2271 struct xhci_ep_ctx *ep_ctx;
2272 struct list_head *tmp;
2275 bool handling_skipped_tds = false;
2277 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2278 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2279 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2280 ep_trb_dma = le64_to_cpu(event->buffer);
2282 xdev = xhci->devs[slot_id];
2284 xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n",
2289 ep = &xdev->eps[ep_index];
2290 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2291 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2293 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2295 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2300 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2302 switch (trb_comp_code) {
2303 case COMP_STALL_ERROR:
2304 case COMP_USB_TRANSACTION_ERROR:
2305 case COMP_INVALID_STREAM_TYPE_ERROR:
2306 case COMP_INVALID_STREAM_ID_ERROR:
2307 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2308 NULL, EP_SOFT_RESET);
2310 case COMP_RING_UNDERRUN:
2311 case COMP_RING_OVERRUN:
2312 case COMP_STOPPED_LENGTH_INVALID:
2315 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2321 /* Count current td numbers if ep->skip is set */
2323 list_for_each(tmp, &ep_ring->td_list)
2327 /* Look for common error cases */
2328 switch (trb_comp_code) {
2329 /* Skip codes that require special handling depending on
2333 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2335 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2336 trb_comp_code = COMP_SHORT_PACKET;
2338 xhci_warn_ratelimited(xhci,
2339 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2341 case COMP_SHORT_PACKET:
2343 /* Completion codes for endpoint stopped state */
2345 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2348 case COMP_STOPPED_LENGTH_INVALID:
2350 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2353 case COMP_STOPPED_SHORT_PACKET:
2355 "Stopped with short packet transfer detected for slot %u ep %u\n",
2358 /* Completion codes for endpoint halted state */
2359 case COMP_STALL_ERROR:
2360 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2362 ep->ep_state |= EP_HALTED;
2365 case COMP_SPLIT_TRANSACTION_ERROR:
2366 case COMP_USB_TRANSACTION_ERROR:
2367 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2371 case COMP_BABBLE_DETECTED_ERROR:
2372 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2374 status = -EOVERFLOW;
2376 /* Completion codes for endpoint error state */
2377 case COMP_TRB_ERROR:
2379 "WARN: TRB error for slot %u ep %u on endpoint\n",
2383 /* completion codes not indicating endpoint state change */
2384 case COMP_DATA_BUFFER_ERROR:
2386 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2390 case COMP_BANDWIDTH_OVERRUN_ERROR:
2392 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2395 case COMP_ISOCH_BUFFER_OVERRUN:
2397 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2400 case COMP_RING_UNDERRUN:
2402 * When the Isoch ring is empty, the xHC will generate
2403 * a Ring Overrun Event for IN Isoch endpoint or Ring
2404 * Underrun Event for OUT Isoch endpoint.
2406 xhci_dbg(xhci, "underrun event on endpoint\n");
2407 if (!list_empty(&ep_ring->td_list))
2408 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2409 "still with TDs queued?\n",
2410 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2413 case COMP_RING_OVERRUN:
2414 xhci_dbg(xhci, "overrun event on endpoint\n");
2415 if (!list_empty(&ep_ring->td_list))
2416 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2417 "still with TDs queued?\n",
2418 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2421 case COMP_MISSED_SERVICE_ERROR:
2423 * When encounter missed service error, one or more isoc tds
2424 * may be missed by xHC.
2425 * Set skip flag of the ep_ring; Complete the missed tds as
2426 * short transfer when process the ep_ring next time.
2430 "Miss service interval error for slot %u ep %u, set skip flag\n",
2433 case COMP_NO_PING_RESPONSE_ERROR:
2436 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2440 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2441 /* needs disable slot command to recover */
2443 "WARN: detect an incompatible device for slot %u ep %u",
2448 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2453 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2454 trb_comp_code, slot_id, ep_index);
2459 /* This TRB should be in the TD at the head of this ring's
2462 if (list_empty(&ep_ring->td_list)) {
2464 * Don't print wanings if it's due to a stopped endpoint
2465 * generating an extra completion event if the device
2466 * was suspended. Or, a event for the last TRB of a
2467 * short TD we already got a short event for.
2468 * The short TD is already removed from the TD list.
2471 if (!(trb_comp_code == COMP_STOPPED ||
2472 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2473 ep_ring->last_td_was_short)) {
2474 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2475 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2480 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2486 /* We've skipped all the TDs on the ep ring when ep->skip set */
2487 if (ep->skip && td_num == 0) {
2489 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2494 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2499 /* Is this a TRB in the currently executing TD? */
2500 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2501 td->last_trb, ep_trb_dma, false);
2504 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2505 * is not in the current TD pointed by ep_ring->dequeue because
2506 * that the hardware dequeue pointer still at the previous TRB
2507 * of the current TD. The previous TRB maybe a Link TD or the
2508 * last TRB of the previous TD. The command completion handle
2509 * will take care the rest.
2511 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2512 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2518 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2519 /* Some host controllers give a spurious
2520 * successful event after a short transfer.
2523 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2524 ep_ring->last_td_was_short) {
2525 ep_ring->last_td_was_short = false;
2528 /* HC is busted, give up! */
2530 "ERROR Transfer event TRB DMA ptr not "
2531 "part of current TD ep_index %d "
2532 "comp_code %u\n", ep_index,
2534 trb_in_td(xhci, ep_ring->deq_seg,
2535 ep_ring->dequeue, td->last_trb,
2540 skip_isoc_td(xhci, td, event, ep, &status);
2543 if (trb_comp_code == COMP_SHORT_PACKET)
2544 ep_ring->last_td_was_short = true;
2546 ep_ring->last_td_was_short = false;
2550 "Found td. Clear skip flag for slot %u ep %u.\n",
2555 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2558 trace_xhci_handle_transfer(ep_ring,
2559 (struct xhci_generic_trb *) ep_trb);
2562 * No-op TRB could trigger interrupts in a case where
2563 * a URB was killed and a STALL_ERROR happens right
2564 * after the endpoint ring stopped. Reset the halted
2565 * endpoint. Otherwise, the endpoint remains stalled
2568 if (trb_is_noop(ep_trb)) {
2569 if (trb_comp_code == COMP_STALL_ERROR ||
2570 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2572 xhci_cleanup_halted_endpoint(xhci, slot_id,
2579 /* update the urb's actual_length and give back to the core */
2580 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2581 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2582 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2583 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2585 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2588 handling_skipped_tds = ep->skip &&
2589 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2590 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2593 * Do not update event ring dequeue pointer if we're in a loop
2594 * processing missed tds.
2596 if (!handling_skipped_tds)
2597 inc_deq(xhci, xhci->event_ring);
2600 * If ep->skip is set, it means there are missed tds on the
2601 * endpoint ring need to take care of.
2602 * Process them as short transfer until reach the td pointed by
2605 } while (handling_skipped_tds);
2610 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2611 (unsigned long long) xhci_trb_virt_to_dma(
2612 xhci->event_ring->deq_seg,
2613 xhci->event_ring->dequeue),
2614 lower_32_bits(le64_to_cpu(event->buffer)),
2615 upper_32_bits(le64_to_cpu(event->buffer)),
2616 le32_to_cpu(event->transfer_len),
2617 le32_to_cpu(event->flags));
2622 * This function handles all OS-owned events on the event ring. It may drop
2623 * xhci->lock between event processing (e.g. to pass up port status changes).
2624 * Returns >0 for "possibly more events to process" (caller should call again),
2625 * otherwise 0 if done. In future, <0 returns should indicate error code.
2627 static int xhci_handle_event(struct xhci_hcd *xhci)
2629 union xhci_trb *event;
2630 int update_ptrs = 1;
2633 /* Event ring hasn't been allocated yet. */
2634 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2635 xhci_err(xhci, "ERROR event ring not ready\n");
2639 event = xhci->event_ring->dequeue;
2640 /* Does the HC or OS own the TRB? */
2641 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2642 xhci->event_ring->cycle_state)
2645 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2648 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2649 * speculative reads of the event's flags/data below.
2652 /* FIXME: Handle more event types. */
2653 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2654 case TRB_TYPE(TRB_COMPLETION):
2655 handle_cmd_completion(xhci, &event->event_cmd);
2657 case TRB_TYPE(TRB_PORT_STATUS):
2658 handle_port_status(xhci, event);
2661 case TRB_TYPE(TRB_TRANSFER):
2662 ret = handle_tx_event(xhci, &event->trans_event);
2666 case TRB_TYPE(TRB_DEV_NOTE):
2667 handle_device_notification(xhci, event);
2670 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2672 handle_vendor_event(xhci, event);
2674 xhci_warn(xhci, "ERROR unknown event type %d\n",
2676 le32_to_cpu(event->event_cmd.flags)));
2678 /* Any of the above functions may drop and re-acquire the lock, so check
2679 * to make sure a watchdog timer didn't mark the host as non-responsive.
2681 if (xhci->xhc_state & XHCI_STATE_DYING) {
2682 xhci_dbg(xhci, "xHCI host dying, returning from "
2683 "event handler.\n");
2688 /* Update SW event ring dequeue pointer */
2689 inc_deq(xhci, xhci->event_ring);
2691 /* Are there more items on the event ring? Caller will call us again to
2698 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2699 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2700 * indicators of an event TRB error, but we check the status *first* to be safe.
2702 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2704 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2705 union xhci_trb *event_ring_deq;
2706 irqreturn_t ret = IRQ_NONE;
2707 unsigned long flags;
2712 spin_lock_irqsave(&xhci->lock, flags);
2713 /* Check if the xHC generated the interrupt, or the irq is shared */
2714 status = readl(&xhci->op_regs->status);
2715 if (status == ~(u32)0) {
2721 if (!(status & STS_EINT))
2724 if (status & STS_FATAL) {
2725 xhci_warn(xhci, "WARNING: Host System Error\n");
2732 * Clear the op reg interrupt status first,
2733 * so we can receive interrupts from other MSI-X interrupters.
2734 * Write 1 to clear the interrupt status.
2737 writel(status, &xhci->op_regs->status);
2739 if (!hcd->msi_enabled) {
2741 irq_pending = readl(&xhci->ir_set->irq_pending);
2742 irq_pending |= IMAN_IP;
2743 writel(irq_pending, &xhci->ir_set->irq_pending);
2746 if (xhci->xhc_state & XHCI_STATE_DYING ||
2747 xhci->xhc_state & XHCI_STATE_HALTED) {
2748 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2749 "Shouldn't IRQs be disabled?\n");
2750 /* Clear the event handler busy flag (RW1C);
2751 * the event ring should be empty.
2753 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2754 xhci_write_64(xhci, temp_64 | ERST_EHB,
2755 &xhci->ir_set->erst_dequeue);
2760 event_ring_deq = xhci->event_ring->dequeue;
2761 /* FIXME this should be a delayed service routine
2762 * that clears the EHB.
2764 while (xhci_handle_event(xhci) > 0) {}
2766 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2767 /* If necessary, update the HW's version of the event ring deq ptr. */
2768 if (event_ring_deq != xhci->event_ring->dequeue) {
2769 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2770 xhci->event_ring->dequeue);
2772 xhci_warn(xhci, "WARN something wrong with SW event "
2773 "ring dequeue ptr.\n");
2774 /* Update HC event ring dequeue pointer */
2775 temp_64 &= ERST_PTR_MASK;
2776 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2779 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2780 temp_64 |= ERST_EHB;
2781 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2785 spin_unlock_irqrestore(&xhci->lock, flags);
2790 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2792 return xhci_irq(hcd);
2795 /**** Endpoint Ring Operations ****/
2798 * Generic function for queueing a TRB on a ring.
2799 * The caller must have checked to make sure there's room on the ring.
2801 * @more_trbs_coming: Will you enqueue more TRBs before calling
2802 * prepare_transfer()?
2804 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2805 bool more_trbs_coming,
2806 u32 field1, u32 field2, u32 field3, u32 field4)
2808 struct xhci_generic_trb *trb;
2810 trb = &ring->enqueue->generic;
2811 trb->field[0] = cpu_to_le32(field1);
2812 trb->field[1] = cpu_to_le32(field2);
2813 trb->field[2] = cpu_to_le32(field3);
2814 trb->field[3] = cpu_to_le32(field4);
2816 trace_xhci_queue_trb(ring, trb);
2818 inc_enq(xhci, ring, more_trbs_coming);
2822 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2823 * FIXME allocate segments if the ring is full.
2825 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2826 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2828 unsigned int num_trbs_needed;
2830 /* Make sure the endpoint has been added to xHC schedule */
2832 case EP_STATE_DISABLED:
2834 * USB core changed config/interfaces without notifying us,
2835 * or hardware is reporting the wrong state.
2837 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2839 case EP_STATE_ERROR:
2840 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2841 /* FIXME event handling code for error needs to clear it */
2842 /* XXX not sure if this should be -ENOENT or not */
2844 case EP_STATE_HALTED:
2845 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2846 case EP_STATE_STOPPED:
2847 case EP_STATE_RUNNING:
2850 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2852 * FIXME issue Configure Endpoint command to try to get the HC
2853 * back into a known state.
2859 if (room_on_ring(xhci, ep_ring, num_trbs))
2862 if (ep_ring == xhci->cmd_ring) {
2863 xhci_err(xhci, "Do not support expand command ring\n");
2867 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2868 "ERROR no room on ep ring, try ring expansion");
2869 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2870 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2872 xhci_err(xhci, "Ring expansion failed\n");
2877 while (trb_is_link(ep_ring->enqueue)) {
2878 /* If we're not dealing with 0.95 hardware or isoc rings
2879 * on AMD 0.96 host, clear the chain bit.
2881 if (!xhci_link_trb_quirk(xhci) &&
2882 !(ep_ring->type == TYPE_ISOC &&
2883 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2884 ep_ring->enqueue->link.control &=
2885 cpu_to_le32(~TRB_CHAIN);
2887 ep_ring->enqueue->link.control |=
2888 cpu_to_le32(TRB_CHAIN);
2891 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2893 /* Toggle the cycle bit after the last ring segment. */
2894 if (link_trb_toggles_cycle(ep_ring->enqueue))
2895 ep_ring->cycle_state ^= 1;
2897 ep_ring->enq_seg = ep_ring->enq_seg->next;
2898 ep_ring->enqueue = ep_ring->enq_seg->trbs;
2903 static int prepare_transfer(struct xhci_hcd *xhci,
2904 struct xhci_virt_device *xdev,
2905 unsigned int ep_index,
2906 unsigned int stream_id,
2907 unsigned int num_trbs,
2909 unsigned int td_index,
2913 struct urb_priv *urb_priv;
2915 struct xhci_ring *ep_ring;
2916 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2918 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2920 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2925 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
2926 num_trbs, mem_flags);
2930 urb_priv = urb->hcpriv;
2931 td = &urb_priv->td[td_index];
2933 INIT_LIST_HEAD(&td->td_list);
2934 INIT_LIST_HEAD(&td->cancelled_td_list);
2936 if (td_index == 0) {
2937 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2943 /* Add this TD to the tail of the endpoint ring's TD list */
2944 list_add_tail(&td->td_list, &ep_ring->td_list);
2945 td->start_seg = ep_ring->enq_seg;
2946 td->first_trb = ep_ring->enqueue;
2951 unsigned int count_trbs(u64 addr, u64 len)
2953 unsigned int num_trbs;
2955 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
2963 static inline unsigned int count_trbs_needed(struct urb *urb)
2965 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
2968 static unsigned int count_sg_trbs_needed(struct urb *urb)
2970 struct scatterlist *sg;
2971 unsigned int i, len, full_len, num_trbs = 0;
2973 full_len = urb->transfer_buffer_length;
2975 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
2976 len = sg_dma_len(sg);
2977 num_trbs += count_trbs(sg_dma_address(sg), len);
2978 len = min_t(unsigned int, len, full_len);
2987 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
2991 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2992 len = urb->iso_frame_desc[i].length;
2994 return count_trbs(addr, len);
2997 static void check_trb_math(struct urb *urb, int running_total)
2999 if (unlikely(running_total != urb->transfer_buffer_length))
3000 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3001 "queued %#x (%d), asked for %#x (%d)\n",
3003 urb->ep->desc.bEndpointAddress,
3004 running_total, running_total,
3005 urb->transfer_buffer_length,
3006 urb->transfer_buffer_length);
3009 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3010 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3011 struct xhci_generic_trb *start_trb)
3014 * Pass all the TRBs to the hardware at once and make sure this write
3019 start_trb->field[3] |= cpu_to_le32(start_cycle);
3021 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3022 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3025 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3026 struct xhci_ep_ctx *ep_ctx)
3031 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3032 ep_interval = urb->interval;
3034 /* Convert to microframes */
3035 if (urb->dev->speed == USB_SPEED_LOW ||
3036 urb->dev->speed == USB_SPEED_FULL)
3039 /* FIXME change this to a warning and a suggestion to use the new API
3040 * to set the polling interval (once the API is added).
3042 if (xhci_interval != ep_interval) {
3043 dev_dbg_ratelimited(&urb->dev->dev,
3044 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3045 ep_interval, ep_interval == 1 ? "" : "s",
3046 xhci_interval, xhci_interval == 1 ? "" : "s");
3047 urb->interval = xhci_interval;
3048 /* Convert back to frames for LS/FS devices */
3049 if (urb->dev->speed == USB_SPEED_LOW ||
3050 urb->dev->speed == USB_SPEED_FULL)
3056 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3057 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3058 * (comprised of sg list entries) can take several service intervals to
3061 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3062 struct urb *urb, int slot_id, unsigned int ep_index)
3064 struct xhci_ep_ctx *ep_ctx;
3066 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3067 check_interval(xhci, urb, ep_ctx);
3069 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3073 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3074 * packets remaining in the TD (*not* including this TRB).
3076 * Total TD packet count = total_packet_count =
3077 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3079 * Packets transferred up to and including this TRB = packets_transferred =
3080 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3082 * TD size = total_packet_count - packets_transferred
3084 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3085 * including this TRB, right shifted by 10
3087 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3088 * This is taken care of in the TRB_TD_SIZE() macro
3090 * The last TRB in a TD must have the TD size set to zero.
3092 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3093 int trb_buff_len, unsigned int td_total_len,
3094 struct urb *urb, bool more_trbs_coming)
3096 u32 maxp, total_packet_count;
3098 /* MTK xHCI 0.96 contains some features from 1.0 */
3099 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3100 return ((td_total_len - transferred) >> 10);
3102 /* One TRB with a zero-length data packet. */
3103 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3104 trb_buff_len == td_total_len)
3107 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3108 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3111 maxp = usb_endpoint_maxp(&urb->ep->desc);
3112 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3114 /* Queueing functions don't count the current TRB into transferred */
3115 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3119 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3120 u32 *trb_buff_len, struct xhci_segment *seg)
3122 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3123 unsigned int unalign;
3124 unsigned int max_pkt;
3127 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3128 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3130 /* we got lucky, last normal TRB data on segment is packet aligned */
3134 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3135 unalign, *trb_buff_len);
3137 /* is the last nornal TRB alignable by splitting it */
3138 if (*trb_buff_len > unalign) {
3139 *trb_buff_len -= unalign;
3140 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3145 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3146 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3147 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3149 new_buff_len = max_pkt - (enqd_len % max_pkt);
3151 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3152 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3154 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3155 if (usb_urb_dir_out(urb)) {
3156 sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs,
3157 seg->bounce_buf, new_buff_len, enqd_len);
3158 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3159 max_pkt, DMA_TO_DEVICE);
3161 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3162 max_pkt, DMA_FROM_DEVICE);
3165 if (dma_mapping_error(dev, seg->bounce_dma)) {
3166 /* try without aligning. Some host controllers survive */
3167 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3170 *trb_buff_len = new_buff_len;
3171 seg->bounce_len = new_buff_len;
3172 seg->bounce_offs = enqd_len;
3174 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3179 /* This is very similar to what ehci-q.c qtd_fill() does */
3180 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3181 struct urb *urb, int slot_id, unsigned int ep_index)
3183 struct xhci_ring *ring;
3184 struct urb_priv *urb_priv;
3186 struct xhci_generic_trb *start_trb;
3187 struct scatterlist *sg = NULL;
3188 bool more_trbs_coming = true;
3189 bool need_zero_pkt = false;
3190 bool first_trb = true;
3191 unsigned int num_trbs;
3192 unsigned int start_cycle, num_sgs = 0;
3193 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3195 u32 field, length_field, remainder;
3196 u64 addr, send_addr;
3198 ring = xhci_urb_to_transfer_ring(xhci, urb);
3202 full_len = urb->transfer_buffer_length;
3203 /* If we have scatter/gather list, we use it. */
3205 num_sgs = urb->num_mapped_sgs;
3207 addr = (u64) sg_dma_address(sg);
3208 block_len = sg_dma_len(sg);
3209 num_trbs = count_sg_trbs_needed(urb);
3211 num_trbs = count_trbs_needed(urb);
3212 addr = (u64) urb->transfer_dma;
3213 block_len = full_len;
3215 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3216 ep_index, urb->stream_id,
3217 num_trbs, urb, 0, mem_flags);
3218 if (unlikely(ret < 0))
3221 urb_priv = urb->hcpriv;
3223 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3224 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3225 need_zero_pkt = true;
3227 td = &urb_priv->td[0];
3230 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3231 * until we've finished creating all the other TRBs. The ring's cycle
3232 * state may change as we enqueue the other TRBs, so save it too.
3234 start_trb = &ring->enqueue->generic;
3235 start_cycle = ring->cycle_state;
3238 /* Queue the TRBs, even if they are zero-length */
3239 for (enqd_len = 0; first_trb || enqd_len < full_len;
3240 enqd_len += trb_buff_len) {
3241 field = TRB_TYPE(TRB_NORMAL);
3243 /* TRB buffer should not cross 64KB boundaries */
3244 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3245 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3247 if (enqd_len + trb_buff_len > full_len)
3248 trb_buff_len = full_len - enqd_len;
3250 /* Don't change the cycle bit of the first TRB until later */
3253 if (start_cycle == 0)
3256 field |= ring->cycle_state;
3258 /* Chain all the TRBs together; clear the chain bit in the last
3259 * TRB to indicate it's the last TRB in the chain.
3261 if (enqd_len + trb_buff_len < full_len) {
3263 if (trb_is_link(ring->enqueue + 1)) {
3264 if (xhci_align_td(xhci, urb, enqd_len,
3267 send_addr = ring->enq_seg->bounce_dma;
3268 /* assuming TD won't span 2 segs */
3269 td->bounce_seg = ring->enq_seg;
3273 if (enqd_len + trb_buff_len >= full_len) {
3274 field &= ~TRB_CHAIN;
3276 more_trbs_coming = false;
3277 td->last_trb = ring->enqueue;
3280 /* Only set interrupt on short packet for IN endpoints */
3281 if (usb_urb_dir_in(urb))
3284 /* Set the TRB length, TD size, and interrupter fields. */
3285 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3286 full_len, urb, more_trbs_coming);
3288 length_field = TRB_LEN(trb_buff_len) |
3289 TRB_TD_SIZE(remainder) |
3292 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3293 lower_32_bits(send_addr),
3294 upper_32_bits(send_addr),
3298 addr += trb_buff_len;
3299 sent_len = trb_buff_len;
3301 while (sg && sent_len >= block_len) {
3304 sent_len -= block_len;
3307 block_len = sg_dma_len(sg);
3308 addr = (u64) sg_dma_address(sg);
3312 block_len -= sent_len;
3316 if (need_zero_pkt) {
3317 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3318 ep_index, urb->stream_id,
3319 1, urb, 1, mem_flags);
3320 urb_priv->td[1].last_trb = ring->enqueue;
3321 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3322 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3325 check_trb_math(urb, enqd_len);
3326 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3327 start_cycle, start_trb);
3331 /* Caller must have locked xhci->lock */
3332 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3333 struct urb *urb, int slot_id, unsigned int ep_index)
3335 struct xhci_ring *ep_ring;
3338 struct usb_ctrlrequest *setup;
3339 struct xhci_generic_trb *start_trb;
3342 struct urb_priv *urb_priv;
3345 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3350 * Need to copy setup packet into setup TRB, so we can't use the setup
3353 if (!urb->setup_packet)
3356 /* 1 TRB for setup, 1 for status */
3359 * Don't need to check if we need additional event data and normal TRBs,
3360 * since data in control transfers will never get bigger than 16MB
3361 * XXX: can we get a buffer that crosses 64KB boundaries?
3363 if (urb->transfer_buffer_length > 0)
3365 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3366 ep_index, urb->stream_id,
3367 num_trbs, urb, 0, mem_flags);
3371 urb_priv = urb->hcpriv;
3372 td = &urb_priv->td[0];
3375 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3376 * until we've finished creating all the other TRBs. The ring's cycle
3377 * state may change as we enqueue the other TRBs, so save it too.
3379 start_trb = &ep_ring->enqueue->generic;
3380 start_cycle = ep_ring->cycle_state;
3382 /* Queue setup TRB - see section 6.4.1.2.1 */
3383 /* FIXME better way to translate setup_packet into two u32 fields? */
3384 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3386 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3387 if (start_cycle == 0)
3390 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3391 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3392 if (urb->transfer_buffer_length > 0) {
3393 if (setup->bRequestType & USB_DIR_IN)
3394 field |= TRB_TX_TYPE(TRB_DATA_IN);
3396 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3400 queue_trb(xhci, ep_ring, true,
3401 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3402 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3403 TRB_LEN(8) | TRB_INTR_TARGET(0),
3404 /* Immediate data in pointer */
3407 /* If there's data, queue data TRBs */
3408 /* Only set interrupt on short packet for IN endpoints */
3409 if (usb_urb_dir_in(urb))
3410 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3412 field = TRB_TYPE(TRB_DATA);
3414 if (urb->transfer_buffer_length > 0) {
3415 u32 length_field, remainder;
3417 remainder = xhci_td_remainder(xhci, 0,
3418 urb->transfer_buffer_length,
3419 urb->transfer_buffer_length,
3421 length_field = TRB_LEN(urb->transfer_buffer_length) |
3422 TRB_TD_SIZE(remainder) |
3424 if (setup->bRequestType & USB_DIR_IN)
3425 field |= TRB_DIR_IN;
3426 queue_trb(xhci, ep_ring, true,
3427 lower_32_bits(urb->transfer_dma),
3428 upper_32_bits(urb->transfer_dma),
3430 field | ep_ring->cycle_state);
3433 /* Save the DMA address of the last TRB in the TD */
3434 td->last_trb = ep_ring->enqueue;
3436 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3437 /* If the device sent data, the status stage is an OUT transfer */
3438 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3442 queue_trb(xhci, ep_ring, false,
3446 /* Event on completion */
3447 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3449 giveback_first_trb(xhci, slot_id, ep_index, 0,
3450 start_cycle, start_trb);
3455 * The transfer burst count field of the isochronous TRB defines the number of
3456 * bursts that are required to move all packets in this TD. Only SuperSpeed
3457 * devices can burst up to bMaxBurst number of packets per service interval.
3458 * This field is zero based, meaning a value of zero in the field means one
3459 * burst. Basically, for everything but SuperSpeed devices, this field will be
3460 * zero. Only xHCI 1.0 host controllers support this field.
3462 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3463 struct urb *urb, unsigned int total_packet_count)
3465 unsigned int max_burst;
3467 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3470 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3471 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3475 * Returns the number of packets in the last "burst" of packets. This field is
3476 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3477 * the last burst packet count is equal to the total number of packets in the
3478 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3479 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3480 * contain 1 to (bMaxBurst + 1) packets.
3482 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3483 struct urb *urb, unsigned int total_packet_count)
3485 unsigned int max_burst;
3486 unsigned int residue;
3488 if (xhci->hci_version < 0x100)
3491 if (urb->dev->speed >= USB_SPEED_SUPER) {
3492 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3493 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3494 residue = total_packet_count % (max_burst + 1);
3495 /* If residue is zero, the last burst contains (max_burst + 1)
3496 * number of packets, but the TLBPC field is zero-based.
3502 if (total_packet_count == 0)
3504 return total_packet_count - 1;
3508 * Calculates Frame ID field of the isochronous TRB identifies the
3509 * target frame that the Interval associated with this Isochronous
3510 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3512 * Returns actual frame id on success, negative value on error.
3514 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3515 struct urb *urb, int index)
3517 int start_frame, ist, ret = 0;
3518 int start_frame_id, end_frame_id, current_frame_id;
3520 if (urb->dev->speed == USB_SPEED_LOW ||
3521 urb->dev->speed == USB_SPEED_FULL)
3522 start_frame = urb->start_frame + index * urb->interval;
3524 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3526 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3528 * If bit [3] of IST is cleared to '0', software can add a TRB no
3529 * later than IST[2:0] Microframes before that TRB is scheduled to
3531 * If bit [3] of IST is set to '1', software can add a TRB no later
3532 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3534 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3535 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3538 /* Software shall not schedule an Isoch TD with a Frame ID value that
3539 * is less than the Start Frame ID or greater than the End Frame ID,
3542 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3543 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3545 * Both the End Frame ID and Start Frame ID values are calculated
3546 * in microframes. When software determines the valid Frame ID value;
3547 * The End Frame ID value should be rounded down to the nearest Frame
3548 * boundary, and the Start Frame ID value should be rounded up to the
3549 * nearest Frame boundary.
3551 current_frame_id = readl(&xhci->run_regs->microframe_index);
3552 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3553 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3555 start_frame &= 0x7ff;
3556 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3557 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3559 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3560 __func__, index, readl(&xhci->run_regs->microframe_index),
3561 start_frame_id, end_frame_id, start_frame);
3563 if (start_frame_id < end_frame_id) {
3564 if (start_frame > end_frame_id ||
3565 start_frame < start_frame_id)
3567 } else if (start_frame_id > end_frame_id) {
3568 if ((start_frame > end_frame_id &&
3569 start_frame < start_frame_id))
3576 if (ret == -EINVAL || start_frame == start_frame_id) {
3577 start_frame = start_frame_id + 1;
3578 if (urb->dev->speed == USB_SPEED_LOW ||
3579 urb->dev->speed == USB_SPEED_FULL)
3580 urb->start_frame = start_frame;
3582 urb->start_frame = start_frame << 3;
3588 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3589 start_frame, current_frame_id, index,
3590 start_frame_id, end_frame_id);
3591 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3598 /* This is for isoc transfer */
3599 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3600 struct urb *urb, int slot_id, unsigned int ep_index)
3602 struct xhci_ring *ep_ring;
3603 struct urb_priv *urb_priv;
3605 int num_tds, trbs_per_td;
3606 struct xhci_generic_trb *start_trb;
3609 u32 field, length_field;
3610 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3611 u64 start_addr, addr;
3613 bool more_trbs_coming;
3614 struct xhci_virt_ep *xep;
3617 xep = &xhci->devs[slot_id]->eps[ep_index];
3618 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3620 num_tds = urb->number_of_packets;
3622 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3625 start_addr = (u64) urb->transfer_dma;
3626 start_trb = &ep_ring->enqueue->generic;
3627 start_cycle = ep_ring->cycle_state;
3629 urb_priv = urb->hcpriv;
3630 /* Queue the TRBs for each TD, even if they are zero-length */
3631 for (i = 0; i < num_tds; i++) {
3632 unsigned int total_pkt_count, max_pkt;
3633 unsigned int burst_count, last_burst_pkt_count;
3638 addr = start_addr + urb->iso_frame_desc[i].offset;
3639 td_len = urb->iso_frame_desc[i].length;
3640 td_remain_len = td_len;
3641 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3642 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3644 /* A zero-length transfer still involves at least one packet. */
3645 if (total_pkt_count == 0)
3647 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3648 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3649 urb, total_pkt_count);
3651 trbs_per_td = count_isoc_trbs_needed(urb, i);
3653 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3654 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3660 td = &urb_priv->td[i];
3662 /* use SIA as default, if frame id is used overwrite it */
3663 sia_frame_id = TRB_SIA;
3664 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3665 HCC_CFC(xhci->hcc_params)) {
3666 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3668 sia_frame_id = TRB_FRAME_ID(frame_id);
3671 * Set isoc specific data for the first TRB in a TD.
3672 * Prevent HW from getting the TRBs by keeping the cycle state
3673 * inverted in the first TDs isoc TRB.
3675 field = TRB_TYPE(TRB_ISOC) |
3676 TRB_TLBPC(last_burst_pkt_count) |
3678 (i ? ep_ring->cycle_state : !start_cycle);
3680 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3681 if (!xep->use_extended_tbc)
3682 field |= TRB_TBC(burst_count);
3684 /* fill the rest of the TRB fields, and remaining normal TRBs */
3685 for (j = 0; j < trbs_per_td; j++) {
3688 /* only first TRB is isoc, overwrite otherwise */
3690 field = TRB_TYPE(TRB_NORMAL) |
3691 ep_ring->cycle_state;
3693 /* Only set interrupt on short packet for IN EPs */
3694 if (usb_urb_dir_in(urb))
3697 /* Set the chain bit for all except the last TRB */
3698 if (j < trbs_per_td - 1) {
3699 more_trbs_coming = true;
3702 more_trbs_coming = false;
3703 td->last_trb = ep_ring->enqueue;
3705 /* set BEI, except for the last TD */
3706 if (xhci->hci_version >= 0x100 &&
3707 !(xhci->quirks & XHCI_AVOID_BEI) &&
3711 /* Calculate TRB length */
3712 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3713 if (trb_buff_len > td_remain_len)
3714 trb_buff_len = td_remain_len;
3716 /* Set the TRB length, TD size, & interrupter fields. */
3717 remainder = xhci_td_remainder(xhci, running_total,
3718 trb_buff_len, td_len,
3719 urb, more_trbs_coming);
3721 length_field = TRB_LEN(trb_buff_len) |
3724 /* xhci 1.1 with ETE uses TD Size field for TBC */
3725 if (first_trb && xep->use_extended_tbc)
3726 length_field |= TRB_TD_SIZE_TBC(burst_count);
3728 length_field |= TRB_TD_SIZE(remainder);
3731 queue_trb(xhci, ep_ring, more_trbs_coming,
3732 lower_32_bits(addr),
3733 upper_32_bits(addr),
3736 running_total += trb_buff_len;
3738 addr += trb_buff_len;
3739 td_remain_len -= trb_buff_len;
3742 /* Check TD length */
3743 if (running_total != td_len) {
3744 xhci_err(xhci, "ISOC TD length unmatch\n");
3750 /* store the next frame id */
3751 if (HCC_CFC(xhci->hcc_params))
3752 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3754 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3755 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3756 usb_amd_quirk_pll_disable();
3758 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3760 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3761 start_cycle, start_trb);
3764 /* Clean up a partially enqueued isoc transfer. */
3766 for (i--; i >= 0; i--)
3767 list_del_init(&urb_priv->td[i].td_list);
3769 /* Use the first TD as a temporary variable to turn the TDs we've queued
3770 * into No-ops with a software-owned cycle bit. That way the hardware
3771 * won't accidentally start executing bogus TDs when we partially
3772 * overwrite them. td->first_trb and td->start_seg are already set.
3774 urb_priv->td[0].last_trb = ep_ring->enqueue;
3775 /* Every TRB except the first & last will have its cycle bit flipped. */
3776 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3778 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3779 ep_ring->enqueue = urb_priv->td[0].first_trb;
3780 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3781 ep_ring->cycle_state = start_cycle;
3782 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3783 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3788 * Check transfer ring to guarantee there is enough room for the urb.
3789 * Update ISO URB start_frame and interval.
3790 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3791 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3792 * Contiguous Frame ID is not supported by HC.
3794 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3795 struct urb *urb, int slot_id, unsigned int ep_index)
3797 struct xhci_virt_device *xdev;
3798 struct xhci_ring *ep_ring;
3799 struct xhci_ep_ctx *ep_ctx;
3801 int num_tds, num_trbs, i;
3803 struct xhci_virt_ep *xep;
3806 xdev = xhci->devs[slot_id];
3807 xep = &xhci->devs[slot_id]->eps[ep_index];
3808 ep_ring = xdev->eps[ep_index].ring;
3809 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3812 num_tds = urb->number_of_packets;
3813 for (i = 0; i < num_tds; i++)
3814 num_trbs += count_isoc_trbs_needed(urb, i);
3816 /* Check the ring to guarantee there is enough room for the whole urb.
3817 * Do not insert any td of the urb to the ring if the check failed.
3819 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3820 num_trbs, mem_flags);
3825 * Check interval value. This should be done before we start to
3826 * calculate the start frame value.
3828 check_interval(xhci, urb, ep_ctx);
3830 /* Calculate the start frame and put it in urb->start_frame. */
3831 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3832 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3833 urb->start_frame = xep->next_frame_id;
3834 goto skip_start_over;
3838 start_frame = readl(&xhci->run_regs->microframe_index);
3839 start_frame &= 0x3fff;
3841 * Round up to the next frame and consider the time before trb really
3842 * gets scheduled by hardare.
3844 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3845 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3847 start_frame += ist + XHCI_CFC_DELAY;
3848 start_frame = roundup(start_frame, 8);
3851 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3852 * is greate than 8 microframes.
3854 if (urb->dev->speed == USB_SPEED_LOW ||
3855 urb->dev->speed == USB_SPEED_FULL) {
3856 start_frame = roundup(start_frame, urb->interval << 3);
3857 urb->start_frame = start_frame >> 3;
3859 start_frame = roundup(start_frame, urb->interval);
3860 urb->start_frame = start_frame;
3864 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3866 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3869 /**** Command Ring Operations ****/
3871 /* Generic function for queueing a command TRB on the command ring.
3872 * Check to make sure there's room on the command ring for one command TRB.
3873 * Also check that there's room reserved for commands that must not fail.
3874 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3875 * then only check for the number of reserved spots.
3876 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3877 * because the command event handler may want to resubmit a failed command.
3879 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3880 u32 field1, u32 field2,
3881 u32 field3, u32 field4, bool command_must_succeed)
3883 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3886 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3887 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3888 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3892 if (!command_must_succeed)
3895 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3896 reserved_trbs, GFP_ATOMIC);
3898 xhci_err(xhci, "ERR: No room for command on command ring\n");
3899 if (command_must_succeed)
3900 xhci_err(xhci, "ERR: Reserved TRB counting for "
3901 "unfailable commands failed.\n");
3905 cmd->command_trb = xhci->cmd_ring->enqueue;
3907 /* if there are no other commands queued we start the timeout timer */
3908 if (list_empty(&xhci->cmd_list)) {
3909 xhci->current_cmd = cmd;
3910 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3913 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3915 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3916 field4 | xhci->cmd_ring->cycle_state);
3920 /* Queue a slot enable or disable request on the command ring */
3921 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3922 u32 trb_type, u32 slot_id)
3924 return queue_command(xhci, cmd, 0, 0, 0,
3925 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3928 /* Queue an address device command TRB */
3929 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3930 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3932 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3933 upper_32_bits(in_ctx_ptr), 0,
3934 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3935 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3938 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3939 u32 field1, u32 field2, u32 field3, u32 field4)
3941 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3944 /* Queue a reset device command TRB */
3945 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3948 return queue_command(xhci, cmd, 0, 0, 0,
3949 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3953 /* Queue a configure endpoint command TRB */
3954 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3955 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3956 u32 slot_id, bool command_must_succeed)
3958 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3959 upper_32_bits(in_ctx_ptr), 0,
3960 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3961 command_must_succeed);
3964 /* Queue an evaluate context command TRB */
3965 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3966 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3968 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3969 upper_32_bits(in_ctx_ptr), 0,
3970 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3971 command_must_succeed);
3975 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3976 * activity on an endpoint that is about to be suspended.
3978 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3979 int slot_id, unsigned int ep_index, int suspend)
3981 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3982 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3983 u32 type = TRB_TYPE(TRB_STOP_RING);
3984 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3986 return queue_command(xhci, cmd, 0, 0, 0,
3987 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3990 /* Set Transfer Ring Dequeue Pointer command */
3991 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
3992 unsigned int slot_id, unsigned int ep_index,
3993 struct xhci_dequeue_state *deq_state)
3996 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3997 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3998 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4000 u32 type = TRB_TYPE(TRB_SET_DEQ);
4001 struct xhci_virt_ep *ep;
4002 struct xhci_command *cmd;
4005 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4006 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4007 deq_state->new_deq_seg,
4008 (unsigned long long)deq_state->new_deq_seg->dma,
4009 deq_state->new_deq_ptr,
4010 (unsigned long long)xhci_trb_virt_to_dma(
4011 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4012 deq_state->new_cycle_state);
4014 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4015 deq_state->new_deq_ptr);
4017 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4018 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4019 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4022 ep = &xhci->devs[slot_id]->eps[ep_index];
4023 if ((ep->ep_state & SET_DEQ_PENDING)) {
4024 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4025 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4029 /* This function gets called from contexts where it cannot sleep */
4030 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4034 ep->queued_deq_seg = deq_state->new_deq_seg;
4035 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4036 if (deq_state->stream_id)
4037 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4038 ret = queue_command(xhci, cmd,
4039 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4040 upper_32_bits(addr), trb_stream_id,
4041 trb_slot_id | trb_ep_index | type, false);
4043 xhci_free_command(xhci, cmd);
4047 /* Stop the TD queueing code from ringing the doorbell until
4048 * this command completes. The HC won't set the dequeue pointer
4049 * if the ring is running, and ringing the doorbell starts the
4052 ep->ep_state |= SET_DEQ_PENDING;
4055 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4056 int slot_id, unsigned int ep_index,
4057 enum xhci_ep_reset_type reset_type)
4059 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4060 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4061 u32 type = TRB_TYPE(TRB_RESET_EP);
4063 if (reset_type == EP_SOFT_RESET)
4066 return queue_command(xhci, cmd, 0, 0, 0,
4067 trb_slot_id | trb_ep_index | type, false);