drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18
  19 #define SSIC_PORT_NUM           2
  20 #define SSIC_PORT_CFG2          0x880c
  21 #define SSIC_PORT_CFG2_OFFSET   0x30
  22 #define PROG_DONE               (1 << 30)
  23 #define SSIC_PORT_UNUSED        (1 << 31)
  24
  25 /* Device for a quirk */
  26 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  30
  31 #define PCI_VENDOR_ID_ETRON             0x1b6f
  32 #define PCI_DEVICE_ID_EJ168             0x7023
  33
  34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  42 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  44
  45 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  46
  47 static const char hcd_name[] = "xhci_hcd";
  48
  49 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  50
  51 static int xhci_pci_setup(struct usb_hcd *hcd);
  52
  53 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  54         .reset = xhci_pci_setup,
  55 };
  56
  57 /* called after powerup, by probe or system-pm "wakeup" */
  58 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  59 {
  60         /*
  61          * TODO: Implement finding debug ports later.
  62          * TODO: see if there are any quirks that need to be added to handle
  63          * new extended capabilities.
  64          */
  65
  66         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  67         if (!pci_set_mwi(pdev))
  68                 xhci_dbg(xhci, "MWI active\n");
  69
  70         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  71         return 0;
  72 }
  73
  74 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  75 {
  76         struct pci_dev          *pdev = to_pci_dev(dev);
  77
  78         /* Look for vendor-specific quirks */
  79         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  80                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  81                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  82                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  83                                 pdev->revision == 0x0) {
  84                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  85                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  86                                 "QUIRK: Fresco Logic xHC needs configure"
  87                                 " endpoint cmd after reset endpoint");
  88                 }
  89                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  90                                 pdev->revision == 0x4) {
  91                         xhci->quirks |= XHCI_SLOW_SUSPEND;
  92                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  93                                 "QUIRK: Fresco Logic xHC revision %u"
  94                                 "must be suspended extra slowly",
  95                                 pdev->revision);
  96                 }
  97                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
  98                         xhci->quirks |= XHCI_BROKEN_STREAMS;
  99                 /* Fresco Logic confirms: all revisions of this chip do not
 100                  * support MSI, even though some of them claim to in their PCI
 101                  * capabilities.
 102                  */
 103                 xhci->quirks |= XHCI_BROKEN_MSI;
 104                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 105                                 "QUIRK: Fresco Logic revision %u "
 106                                 "has broken MSI implementation",
 107                                 pdev->revision);
 108                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 109         }
 110
 111         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 112                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 113                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 114
 115         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 116                 xhci->quirks |= XHCI_NEC_HOST;
 117
 118         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 119                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 120
 121         /* AMD PLL quirk */
 122         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 123                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 124
 125         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 126                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 127
 128         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 129                 xhci->quirks |= XHCI_LPM_SUPPORT;
 130                 xhci->quirks |= XHCI_INTEL_HOST;
 131                 xhci->quirks |= XHCI_AVOID_BEI;
 132         }
 133         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 134                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 135                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 136                 xhci->limit_active_eps = 64;
 137                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 138                 /*
 139                  * PPT desktop boards DH77EB and DH77DF will power back on after
 140                  * a few seconds of being shutdown.  The fix for this is to
 141                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 142                  * DMI information to find those particular boards (since each
 143                  * vendor will change the board name), so we have to key off all
 144                  * PPT chipsets.
 145                  */
 146                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 147         }
 148         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 149                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 150                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 151                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 152                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 153         }
 154         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 155                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 156                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 157                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 158                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 159                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 160                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 161                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
 162                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 163         }
 164         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 165                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 166                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 167         }
 168         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 169             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 170              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 171              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 172                 xhci->quirks |= XHCI_MISSING_CAS;
 173
 174         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 175                         pdev->device == PCI_DEVICE_ID_EJ168) {
 176                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 177                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 178                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 179         }
 180         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 181                         pdev->device == 0x0014)
 182                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 183         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 184                         pdev->device == 0x0015)
 185                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 186         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 187                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 188
 189         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 190         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 191                         pdev->device == 0x3432)
 192                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 193
 194         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 195                         pdev->device == 0x1042)
 196                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 197         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 198                         pdev->device == 0x1142)
 199                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 200
 201         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 202                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 203                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 204
 205         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 206                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 207
 208         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 209                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 210                                 "QUIRK: Resetting on resume");
 211 }
 212
 213 #ifdef CONFIG_ACPI
 214 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 215 {
 216         static const guid_t intel_dsm_guid =
 217                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 218                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 219         union acpi_object *obj;
 220
 221         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 222                                 NULL);
 223         ACPI_FREE(obj);
 224 }
 225 #else
 226 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 227 #endif /* CONFIG_ACPI */
 228
 229 /* called during probe() after chip reset completes */
 230 static int xhci_pci_setup(struct usb_hcd *hcd)
 231 {
 232         struct xhci_hcd         *xhci;
 233         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 234         int                     retval;
 235
 236         xhci = hcd_to_xhci(hcd);
 237         if (!xhci->sbrn)
 238                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 239
 240         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 241         if (retval)
 242                 return retval;
 243
 244         if (!usb_hcd_is_primary_hcd(hcd))
 245                 return 0;
 246
 247         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 248
 249         /* Find any debug ports */
 250         return xhci_pci_reinit(xhci, pdev);
 251 }
 252
 253 /*
 254  * We need to register our own PCI probe function (instead of the USB core's
 255  * function) in order to create a second roothub under xHCI.
 256  */
 257 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 258 {
 259         int retval;
 260         struct xhci_hcd *xhci;
 261         struct hc_driver *driver;
 262         struct usb_hcd *hcd;
 263
 264         driver = (struct hc_driver *)id->driver_data;
 265
 266         /* For some HW implementation, a XHCI reset is just not enough... */
 267         if (usb_xhci_needs_pci_reset(dev)) {
 268                 dev_info(&dev->dev, "Resetting\n");
 269                 if (pci_reset_function_locked(dev))
 270                         dev_warn(&dev->dev, "Reset failed");
 271         }
 272
 273         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 274         pm_runtime_get_noresume(&dev->dev);
 275
 276         /* Register the USB 2.0 roothub.
 277          * FIXME: USB core must know to register the USB 2.0 roothub first.
 278          * This is sort of silly, because we could just set the HCD driver flags
 279          * to say USB 2.0, but I'm not sure what the implications would be in
 280          * the other parts of the HCD code.
 281          */
 282         retval = usb_hcd_pci_probe(dev, id);
 283
 284         if (retval)
 285                 goto put_runtime_pm;
 286
 287         /* USB 2.0 roothub is stored in the PCI device now. */
 288         hcd = dev_get_drvdata(&dev->dev);
 289         xhci = hcd_to_xhci(hcd);
 290         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 291                                 pci_name(dev), hcd);
 292         if (!xhci->shared_hcd) {
 293                 retval = -ENOMEM;
 294                 goto dealloc_usb2_hcd;
 295         }
 296
 297         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 298                         IRQF_SHARED);
 299         if (retval)
 300                 goto put_usb3_hcd;
 301         /* Roothub already marked as USB 3.0 speed */
 302
 303         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 304                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 305                 xhci->shared_hcd->can_do_streams = 1;
 306
 307         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 308                 xhci_pme_acpi_rtd3_enable(dev);
 309
 310         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 311         pm_runtime_put_noidle(&dev->dev);
 312
 313         return 0;
 314
 315 put_usb3_hcd:
 316         usb_put_hcd(xhci->shared_hcd);
 317 dealloc_usb2_hcd:
 318         usb_hcd_pci_remove(dev);
 319 put_runtime_pm:
 320         pm_runtime_put_noidle(&dev->dev);
 321         return retval;
 322 }
 323
 324 static void xhci_pci_remove(struct pci_dev *dev)
 325 {
 326         struct xhci_hcd *xhci;
 327
 328         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 329         xhci->xhc_state |= XHCI_STATE_REMOVING;
 330         if (xhci->shared_hcd) {
 331                 usb_remove_hcd(xhci->shared_hcd);
 332                 usb_put_hcd(xhci->shared_hcd);
 333         }
 334
 335         /* Workaround for spurious wakeups at shutdown with HSW */
 336         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 337                 pci_set_power_state(dev, PCI_D3hot);
 338
 339         usb_hcd_pci_remove(dev);
 340 }
 341
 342 #ifdef CONFIG_PM
 343 /*
 344  * In some Intel xHCI controllers, in order to get D3 working,
 345  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 346  * SSIC PORT need to be marked as "unused" before putting xHCI
 347  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 348  * Without this change, xHCI might not enter D3 state.
 349  */
 350 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 351 {
 352         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 353         u32 val;
 354         void __iomem *reg;
 355         int i;
 356
 357         for (i = 0; i < SSIC_PORT_NUM; i++) {
 358                 reg = (void __iomem *) xhci->cap_regs +
 359                                 SSIC_PORT_CFG2 +
 360                                 i * SSIC_PORT_CFG2_OFFSET;
 361
 362                 /* Notify SSIC that SSIC profile programming is not done. */
 363                 val = readl(reg) & ~PROG_DONE;
 364                 writel(val, reg);
 365
 366                 /* Mark SSIC port as unused(suspend) or used(resume) */
 367                 val = readl(reg);
 368                 if (suspend)
 369                         val |= SSIC_PORT_UNUSED;
 370                 else
 371                         val &= ~SSIC_PORT_UNUSED;
 372                 writel(val, reg);
 373
 374                 /* Notify SSIC that SSIC profile programming is done */
 375                 val = readl(reg) | PROG_DONE;
 376                 writel(val, reg);
 377                 readl(reg);
 378         }
 379 }
 380
 381 /*
 382  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 383  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 384  */
 385 static void xhci_pme_quirk(struct usb_hcd *hcd)
 386 {
 387         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 388         void __iomem *reg;
 389         u32 val;
 390
 391         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 392         val = readl(reg);
 393         writel(val | BIT(28), reg);
 394         readl(reg);
 395 }
 396
 397 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 398 {
 399         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 400         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 401         int                     ret;
 402
 403         /*
 404          * Systems with the TI redriver that loses port status change events
 405          * need to have the registers polled during D3, so avoid D3cold.
 406          */
 407         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 408                 pci_d3cold_disable(pdev);
 409
 410         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 411                 xhci_pme_quirk(hcd);
 412
 413         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 414                 xhci_ssic_port_unused_quirk(hcd, true);
 415
 416         ret = xhci_suspend(xhci, do_wakeup);
 417         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 418                 xhci_ssic_port_unused_quirk(hcd, false);
 419
 420         return ret;
 421 }
 422
 423 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 424 {
 425         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 426         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 427         int                     retval = 0;
 428
 429         /* The BIOS on systems with the Intel Panther Point chipset may or may
 430          * not support xHCI natively.  That means that during system resume, it
 431          * may switch the ports back to EHCI so that users can use their
 432          * keyboard to select a kernel from GRUB after resume from hibernate.
 433          *
 434          * The BIOS is supposed to remember whether the OS had xHCI ports
 435          * enabled before resume, and switch the ports back to xHCI when the
 436          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 437          * writers.
 438          *
 439          * Unconditionally switch the ports back to xHCI after a system resume.
 440          * It should not matter whether the EHCI or xHCI controller is
 441          * resumed first. It's enough to do the switchover in xHCI because
 442          * USB core won't notice anything as the hub driver doesn't start
 443          * running again until after all the devices (including both EHCI and
 444          * xHCI host controllers) have been resumed.
 445          */
 446
 447         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 448                 usb_enable_intel_xhci_ports(pdev);
 449
 450         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 451                 xhci_ssic_port_unused_quirk(hcd, false);
 452
 453         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 454                 xhci_pme_quirk(hcd);
 455
 456         retval = xhci_resume(xhci, hibernated);
 457         return retval;
 458 }
 459 #endif /* CONFIG_PM */
 460
 461 /*-------------------------------------------------------------------------*/
 462
 463 /* PCI driver selection metadata; PCI hotplugging uses this */
 464 static const struct pci_device_id pci_ids[] = { {
 465         /* handle any USB 3.0 xHCI controller */
 466         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 467         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 468         },
 469         { /* end: all zeroes */ }
 470 };
 471 MODULE_DEVICE_TABLE(pci, pci_ids);
 472
 473 /* pci driver glue; this is a "new style" PCI driver module */
 474 static struct pci_driver xhci_pci_driver = {
 475         .name =         (char *) hcd_name,
 476         .id_table =     pci_ids,
 477
 478         .probe =        xhci_pci_probe,
 479         .remove =       xhci_pci_remove,
 480         /* suspend and resume implemented later */
 481
 482         .shutdown =     usb_hcd_pci_shutdown,
 483 #ifdef CONFIG_PM
 484         .driver = {
 485                 .pm = &usb_hcd_pci_pm_ops
 486         },
 487 #endif
 488 };
 489
 490 static int __init xhci_pci_init(void)
 491 {
 492         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 493 #ifdef CONFIG_PM
 494         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 495         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 496 #endif
 497         return pci_register_driver(&xhci_pci_driver);
 498 }
 499 module_init(xhci_pci_init);
 500
 501 static void __exit xhci_pci_exit(void)
 502 {
 503         pci_unregister_driver(&xhci_pci_driver);
 504 }
 505 module_exit(xhci_pci_exit);
 506
 507 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 508 MODULE_LICENSE("GPL");