drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18
  19 #define SSIC_PORT_NUM           2
  20 #define SSIC_PORT_CFG2          0x880c
  21 #define SSIC_PORT_CFG2_OFFSET   0x30
  22 #define PROG_DONE               (1 << 30)
  23 #define SSIC_PORT_UNUSED        (1 << 31)
  24
  25 /* Device for a quirk */
  26 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  30
  31 #define PCI_VENDOR_ID_ETRON             0x1b6f
  32 #define PCI_DEVICE_ID_EJ168             0x7023
  33
  34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  42 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  44
  45 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  46 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  47 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  48 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  49 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  50
  51 static const char hcd_name[] = "xhci_hcd";
  52
  53 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  54
  55 static int xhci_pci_setup(struct usb_hcd *hcd);
  56
  57 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  58         .reset = xhci_pci_setup,
  59 };
  60
  61 /* called after powerup, by probe or system-pm "wakeup" */
  62 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  63 {
  64         /*
  65          * TODO: Implement finding debug ports later.
  66          * TODO: see if there are any quirks that need to be added to handle
  67          * new extended capabilities.
  68          */
  69
  70         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  71         if (!pci_set_mwi(pdev))
  72                 xhci_dbg(xhci, "MWI active\n");
  73
  74         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  75         return 0;
  76 }
  77
  78 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  79 {
  80         struct pci_dev          *pdev = to_pci_dev(dev);
  81
  82         /* Look for vendor-specific quirks */
  83         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  84                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  85                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  86                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  87                                 pdev->revision == 0x0) {
  88                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  89                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  90                                 "QUIRK: Fresco Logic xHC needs configure"
  91                                 " endpoint cmd after reset endpoint");
  92                 }
  93                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  94                                 pdev->revision == 0x4) {
  95                         xhci->quirks |= XHCI_SLOW_SUSPEND;
  96                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  97                                 "QUIRK: Fresco Logic xHC revision %u"
  98                                 "must be suspended extra slowly",
  99                                 pdev->revision);
 100                 }
 101                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 102                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 103                 /* Fresco Logic confirms: all revisions of this chip do not
 104                  * support MSI, even though some of them claim to in their PCI
 105                  * capabilities.
 106                  */
 107                 xhci->quirks |= XHCI_BROKEN_MSI;
 108                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 109                                 "QUIRK: Fresco Logic revision %u "
 110                                 "has broken MSI implementation",
 111                                 pdev->revision);
 112                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 113         }
 114
 115         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 116                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 117                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 118
 119         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 120                 xhci->quirks |= XHCI_NEC_HOST;
 121
 122         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 123                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 124
 125         /* AMD PLL quirk */
 126         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 127                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 128
 129         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 130                 (pdev->device == 0x15e0 ||
 131                  pdev->device == 0x15e1 ||
 132                  pdev->device == 0x43bb))
 133                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 134
 135         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 136                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 137
 138         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 139                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 140                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 141                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 142                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 143                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 144
 145         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 146                 xhci->quirks |= XHCI_LPM_SUPPORT;
 147                 xhci->quirks |= XHCI_INTEL_HOST;
 148                 xhci->quirks |= XHCI_AVOID_BEI;
 149         }
 150         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 151                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 152                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 153                 xhci->limit_active_eps = 64;
 154                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 155                 /*
 156                  * PPT desktop boards DH77EB and DH77DF will power back on after
 157                  * a few seconds of being shutdown.  The fix for this is to
 158                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 159                  * DMI information to find those particular boards (since each
 160                  * vendor will change the board name), so we have to key off all
 161                  * PPT chipsets.
 162                  */
 163                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 164         }
 165         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 166                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 167                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 168                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 169                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 170         }
 171         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 172                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 173                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 174                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 175                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 176                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 177                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 178                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
 179                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 180         }
 181         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 182             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 183                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 184         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 185             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 186              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 187                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 188         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 189             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 190              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 191              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 192              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 193              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 194                 xhci->quirks |= XHCI_MISSING_CAS;
 195
 196         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 197                         pdev->device == PCI_DEVICE_ID_EJ168) {
 198                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 199                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 200                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 201         }
 202         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 203             pdev->device == 0x0014) {
 204                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 205                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 206         }
 207         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 208             pdev->device == 0x0015) {
 209                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 210                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 211         }
 212         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 213                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 214
 215         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 216         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 217                         pdev->device == 0x3432)
 218                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 219
 220         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 221                         pdev->device == 0x1042)
 222                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 223         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 224                         pdev->device == 0x1142)
 225                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 226
 227         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 228                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 229                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 230
 231         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 232                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 233
 234         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 235                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 236                                 "QUIRK: Resetting on resume");
 237 }
 238
 239 #ifdef CONFIG_ACPI
 240 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 241 {
 242         static const guid_t intel_dsm_guid =
 243                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 244                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 245         union acpi_object *obj;
 246
 247         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 248                                 NULL);
 249         ACPI_FREE(obj);
 250 }
 251 #else
 252 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 253 #endif /* CONFIG_ACPI */
 254
 255 /* called during probe() after chip reset completes */
 256 static int xhci_pci_setup(struct usb_hcd *hcd)
 257 {
 258         struct xhci_hcd         *xhci;
 259         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 260         int                     retval;
 261
 262         xhci = hcd_to_xhci(hcd);
 263         if (!xhci->sbrn)
 264                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 265
 266         /* imod_interval is the interrupt moderation value in nanoseconds. */
 267         xhci->imod_interval = 40000;
 268
 269         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 270         if (retval)
 271                 return retval;
 272
 273         if (!usb_hcd_is_primary_hcd(hcd))
 274                 return 0;
 275
 276         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 277
 278         /* Find any debug ports */
 279         return xhci_pci_reinit(xhci, pdev);
 280 }
 281
 282 /*
 283  * We need to register our own PCI probe function (instead of the USB core's
 284  * function) in order to create a second roothub under xHCI.
 285  */
 286 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 287 {
 288         int retval;
 289         struct xhci_hcd *xhci;
 290         struct hc_driver *driver;
 291         struct usb_hcd *hcd;
 292
 293         driver = (struct hc_driver *)id->driver_data;
 294
 295         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 296         pm_runtime_get_noresume(&dev->dev);
 297
 298         /* Register the USB 2.0 roothub.
 299          * FIXME: USB core must know to register the USB 2.0 roothub first.
 300          * This is sort of silly, because we could just set the HCD driver flags
 301          * to say USB 2.0, but I'm not sure what the implications would be in
 302          * the other parts of the HCD code.
 303          */
 304         retval = usb_hcd_pci_probe(dev, id);
 305
 306         if (retval)
 307                 goto put_runtime_pm;
 308
 309         /* USB 2.0 roothub is stored in the PCI device now. */
 310         hcd = dev_get_drvdata(&dev->dev);
 311         xhci = hcd_to_xhci(hcd);
 312         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 313                                 pci_name(dev), hcd);
 314         if (!xhci->shared_hcd) {
 315                 retval = -ENOMEM;
 316                 goto dealloc_usb2_hcd;
 317         }
 318
 319         retval = xhci_ext_cap_init(xhci);
 320         if (retval)
 321                 goto put_usb3_hcd;
 322
 323         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 324                         IRQF_SHARED);
 325         if (retval)
 326                 goto put_usb3_hcd;
 327         /* Roothub already marked as USB 3.0 speed */
 328
 329         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 330                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 331                 xhci->shared_hcd->can_do_streams = 1;
 332
 333         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 334                 xhci_pme_acpi_rtd3_enable(dev);
 335
 336         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 337         pm_runtime_put_noidle(&dev->dev);
 338
 339         return 0;
 340
 341 put_usb3_hcd:
 342         usb_put_hcd(xhci->shared_hcd);
 343 dealloc_usb2_hcd:
 344         usb_hcd_pci_remove(dev);
 345 put_runtime_pm:
 346         pm_runtime_put_noidle(&dev->dev);
 347         return retval;
 348 }
 349
 350 static void xhci_pci_remove(struct pci_dev *dev)
 351 {
 352         struct xhci_hcd *xhci;
 353
 354         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 355         xhci->xhc_state |= XHCI_STATE_REMOVING;
 356         if (xhci->shared_hcd) {
 357                 usb_remove_hcd(xhci->shared_hcd);
 358                 usb_put_hcd(xhci->shared_hcd);
 359         }
 360
 361         /* Workaround for spurious wakeups at shutdown with HSW */
 362         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 363                 pci_set_power_state(dev, PCI_D3hot);
 364
 365         usb_hcd_pci_remove(dev);
 366 }
 367
 368 #ifdef CONFIG_PM
 369 /*
 370  * In some Intel xHCI controllers, in order to get D3 working,
 371  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 372  * SSIC PORT need to be marked as "unused" before putting xHCI
 373  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 374  * Without this change, xHCI might not enter D3 state.
 375  */
 376 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 377 {
 378         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 379         u32 val;
 380         void __iomem *reg;
 381         int i;
 382
 383         for (i = 0; i < SSIC_PORT_NUM; i++) {
 384                 reg = (void __iomem *) xhci->cap_regs +
 385                                 SSIC_PORT_CFG2 +
 386                                 i * SSIC_PORT_CFG2_OFFSET;
 387
 388                 /* Notify SSIC that SSIC profile programming is not done. */
 389                 val = readl(reg) & ~PROG_DONE;
 390                 writel(val, reg);
 391
 392                 /* Mark SSIC port as unused(suspend) or used(resume) */
 393                 val = readl(reg);
 394                 if (suspend)
 395                         val |= SSIC_PORT_UNUSED;
 396                 else
 397                         val &= ~SSIC_PORT_UNUSED;
 398                 writel(val, reg);
 399
 400                 /* Notify SSIC that SSIC profile programming is done */
 401                 val = readl(reg) | PROG_DONE;
 402                 writel(val, reg);
 403                 readl(reg);
 404         }
 405 }
 406
 407 /*
 408  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 409  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 410  */
 411 static void xhci_pme_quirk(struct usb_hcd *hcd)
 412 {
 413         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 414         void __iomem *reg;
 415         u32 val;
 416
 417         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 418         val = readl(reg);
 419         writel(val | BIT(28), reg);
 420         readl(reg);
 421 }
 422
 423 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 424 {
 425         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 426         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 427         int                     ret;
 428
 429         /*
 430          * Systems with the TI redriver that loses port status change events
 431          * need to have the registers polled during D3, so avoid D3cold.
 432          */
 433         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 434                 pci_d3cold_disable(pdev);
 435
 436         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 437                 xhci_pme_quirk(hcd);
 438
 439         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 440                 xhci_ssic_port_unused_quirk(hcd, true);
 441
 442         ret = xhci_suspend(xhci, do_wakeup);
 443         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 444                 xhci_ssic_port_unused_quirk(hcd, false);
 445
 446         return ret;
 447 }
 448
 449 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 450 {
 451         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 452         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 453         int                     retval = 0;
 454
 455         /* The BIOS on systems with the Intel Panther Point chipset may or may
 456          * not support xHCI natively.  That means that during system resume, it
 457          * may switch the ports back to EHCI so that users can use their
 458          * keyboard to select a kernel from GRUB after resume from hibernate.
 459          *
 460          * The BIOS is supposed to remember whether the OS had xHCI ports
 461          * enabled before resume, and switch the ports back to xHCI when the
 462          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 463          * writers.
 464          *
 465          * Unconditionally switch the ports back to xHCI after a system resume.
 466          * It should not matter whether the EHCI or xHCI controller is
 467          * resumed first. It's enough to do the switchover in xHCI because
 468          * USB core won't notice anything as the hub driver doesn't start
 469          * running again until after all the devices (including both EHCI and
 470          * xHCI host controllers) have been resumed.
 471          */
 472
 473         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 474                 usb_enable_intel_xhci_ports(pdev);
 475
 476         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 477                 xhci_ssic_port_unused_quirk(hcd, false);
 478
 479         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 480                 xhci_pme_quirk(hcd);
 481
 482         retval = xhci_resume(xhci, hibernated);
 483         return retval;
 484 }
 485 #endif /* CONFIG_PM */
 486
 487 /*-------------------------------------------------------------------------*/
 488
 489 /* PCI driver selection metadata; PCI hotplugging uses this */
 490 static const struct pci_device_id pci_ids[] = { {
 491         /* handle any USB 3.0 xHCI controller */
 492         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 493         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 494         },
 495         { /* end: all zeroes */ }
 496 };
 497 MODULE_DEVICE_TABLE(pci, pci_ids);
 498
 499 /* pci driver glue; this is a "new style" PCI driver module */
 500 static struct pci_driver xhci_pci_driver = {
 501         .name =         (char *) hcd_name,
 502         .id_table =     pci_ids,
 503
 504         .probe =        xhci_pci_probe,
 505         .remove =       xhci_pci_remove,
 506         /* suspend and resume implemented later */
 507
 508         .shutdown =     usb_hcd_pci_shutdown,
 509 #ifdef CONFIG_PM
 510         .driver = {
 511                 .pm = &usb_hcd_pci_pm_ops
 512         },
 513 #endif
 514 };
 515
 516 static int __init xhci_pci_init(void)
 517 {
 518         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 519 #ifdef CONFIG_PM
 520         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 521         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 522 #endif
 523         return pci_register_driver(&xhci_pci_driver);
 524 }
 525 module_init(xhci_pci_init);
 526
 527 static void __exit xhci_pci_exit(void)
 528 {
 529         pci_unregister_driver(&xhci_pci_driver);
 530 }
 531 module_exit(xhci_pci_exit);
 532
 533 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 534 MODULE_LICENSE("GPL");