drivers/usb/host/xhci-hub.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11
  12 #include <linux/slab.h>
  13 #include <asm/unaligned.h>
  14
  15 #include "xhci.h"
  16 #include "xhci-trace.h"
  17
  18 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  19 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  20                          PORT_RC | PORT_PLC | PORT_PE)
  21
  22 /* USB 3 BOS descriptor and a capability descriptors, combined.
  23  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  24  */
  25 static u8 usb_bos_descriptor [] = {
  26         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  27         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  28         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  29         0x1,                            /*  __u8 bNumDeviceCaps */
  30         /* First device capability, SuperSpeed */
  31         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  32         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  33         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  34         0x00,                           /* bmAttributes, LTM off by default */
  35         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  36         0x03,                           /* bFunctionalitySupport,
  37                                            USB 3.0 speed only */
  38         0x00,                           /* bU1DevExitLat, set later. */
  39         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  40         /* Second device capability, SuperSpeedPlus */
  41         0x1c,                           /* bLength 28, will be adjusted later */
  42         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  43         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  44         0x00,                           /* bReserved 0 */
  45         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  46         0x01, 0x00,                     /* wFunctionalitySupport */
  47         0x00, 0x00,                     /* wReserved 0 */
  48         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  49         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  50         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  51         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  52         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  53 };
  54
  55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  56                                      u16 wLength)
  57 {
  58         int i, ssa_count;
  59         u32 temp;
  60         u16 desc_size, ssp_cap_size, ssa_size = 0;
  61         bool usb3_1 = false;
  62
  63         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  64         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  65
  66         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  67         if (xhci->usb3_rhub.min_rev >= 0x01) {
  68                 /* does xhci provide a PSI table for SSA speed attributes? */
  69                 if (xhci->usb3_rhub.psi_count) {
  70                         /* two SSA entries for each unique PSI ID, RX and TX */
  71                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  72                         ssa_size = ssa_count * sizeof(u32);
  73                         ssp_cap_size -= 16; /* skip copying the default SSA */
  74                 }
  75                 desc_size += ssp_cap_size;
  76                 usb3_1 = true;
  77         }
  78         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  79
  80         if (usb3_1) {
  81                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  82                 buf[4] += 1;
  83                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  84         }
  85
  86         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  87                 return wLength;
  88
  89         /* Indicate whether the host has LTM support. */
  90         temp = readl(&xhci->cap_regs->hcc_params);
  91         if (HCC_LTC(temp))
  92                 buf[8] |= USB_LTM_SUPPORT;
  93
  94         /* Set the U1 and U2 exit latencies. */
  95         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
  96                 temp = readl(&xhci->cap_regs->hcs_params3);
  97                 buf[12] = HCS_U1_LATENCY(temp);
  98                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
  99         }
 100
 101         /* If PSI table exists, add the custom speed attributes from it */
 102         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 103                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 104                 int offset;
 105
 106                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 107
 108                 if (wLength < desc_size)
 109                         return wLength;
 110                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 111
 112                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 113                 bm_attrib = (ssa_count - 1) & 0x1f;
 114                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 115                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 116
 117                 if (wLength < desc_size + ssa_size)
 118                         return wLength;
 119                 /*
 120                  * Create the Sublink Speed Attributes (SSA) array.
 121                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 122                  * but link type bits 7:6 differ for values 01b and 10b.
 123                  * xhci has also only one PSI entry for a symmetric link when
 124                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 125                  */
 126                 offset = desc_size;
 127                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 128                         psi = xhci->usb3_rhub.psi[i];
 129                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 130                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 131                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 132
 133                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 134                         for (; psi_exp < 3; psi_exp++)
 135                                 psi_mant /= 1000;
 136                         if (psi_mant >= 10)
 137                                 psi |= BIT(14);
 138
 139                         if ((psi & PLT_MASK) == PLT_SYM) {
 140                         /* Symmetric, create SSA RX and TX from one PSI entry */
 141                                 put_unaligned_le32(psi, &buf[offset]);
 142                                 psi |= 1 << 7;  /* turn entry to TX */
 143                                 offset += 4;
 144                                 if (offset >= desc_size + ssa_size)
 145                                         return desc_size + ssa_size;
 146                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 147                                 /* Asymetric RX, flip bits 7:6 for SSA */
 148                                 psi ^= PLT_MASK;
 149                         }
 150                         put_unaligned_le32(psi, &buf[offset]);
 151                         offset += 4;
 152                         if (offset >= desc_size + ssa_size)
 153                                 return desc_size + ssa_size;
 154                 }
 155         }
 156         /* ssa_size is 0 for other than usb 3.1 hosts */
 157         return desc_size + ssa_size;
 158 }
 159
 160 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 161                 struct usb_hub_descriptor *desc, int ports)
 162 {
 163         u16 temp;
 164
 165         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 166         desc->bHubContrCurrent = 0;
 167
 168         desc->bNbrPorts = ports;
 169         temp = 0;
 170         /* Bits 1:0 - support per-port power switching, or power always on */
 171         if (HCC_PPC(xhci->hcc_params))
 172                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 173         else
 174                 temp |= HUB_CHAR_NO_LPSM;
 175         /* Bit  2 - root hubs are not part of a compound device */
 176         /* Bits 4:3 - individual port over current protection */
 177         temp |= HUB_CHAR_INDV_PORT_OCPM;
 178         /* Bits 6:5 - no TTs in root ports */
 179         /* Bit  7 - no port indicators */
 180         desc->wHubCharacteristics = cpu_to_le16(temp);
 181 }
 182
 183 /* Fill in the USB 2.0 roothub descriptor */
 184 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 185                 struct usb_hub_descriptor *desc)
 186 {
 187         int ports;
 188         u16 temp;
 189         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 190         u32 portsc;
 191         unsigned int i;
 192         struct xhci_hub *rhub;
 193
 194         rhub = &xhci->usb2_rhub;
 195         ports = rhub->num_ports;
 196         xhci_common_hub_descriptor(xhci, desc, ports);
 197         desc->bDescriptorType = USB_DT_HUB;
 198         temp = 1 + (ports / 8);
 199         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 200
 201         /* The Device Removable bits are reported on a byte granularity.
 202          * If the port doesn't exist within that byte, the bit is set to 0.
 203          */
 204         memset(port_removable, 0, sizeof(port_removable));
 205         for (i = 0; i < ports; i++) {
 206                 portsc = readl(rhub->ports[i]->addr);
 207                 /* If a device is removable, PORTSC reports a 0, same as in the
 208                  * hub descriptor DeviceRemovable bits.
 209                  */
 210                 if (portsc & PORT_DEV_REMOVE)
 211                         /* This math is hairy because bit 0 of DeviceRemovable
 212                          * is reserved, and bit 1 is for port 1, etc.
 213                          */
 214                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 215         }
 216
 217         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 218          * ports on it.  The USB 2.0 specification says that there are two
 219          * variable length fields at the end of the hub descriptor:
 220          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 221          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 222          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 223          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 224          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 225          * set of ports that actually exist.
 226          */
 227         memset(desc->u.hs.DeviceRemovable, 0xff,
 228                         sizeof(desc->u.hs.DeviceRemovable));
 229         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 230                         sizeof(desc->u.hs.PortPwrCtrlMask));
 231
 232         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 233                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 234                                 sizeof(__u8));
 235 }
 236
 237 /* Fill in the USB 3.0 roothub descriptor */
 238 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 239                 struct usb_hub_descriptor *desc)
 240 {
 241         int ports;
 242         u16 port_removable;
 243         u32 portsc;
 244         unsigned int i;
 245         struct xhci_hub *rhub;
 246
 247         rhub = &xhci->usb3_rhub;
 248         ports = rhub->num_ports;
 249         xhci_common_hub_descriptor(xhci, desc, ports);
 250         desc->bDescriptorType = USB_DT_SS_HUB;
 251         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 252
 253         /* header decode latency should be zero for roothubs,
 254          * see section 4.23.5.2.
 255          */
 256         desc->u.ss.bHubHdrDecLat = 0;
 257         desc->u.ss.wHubDelay = 0;
 258
 259         port_removable = 0;
 260         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 261         for (i = 0; i < ports; i++) {
 262                 portsc = readl(rhub->ports[i]->addr);
 263                 if (portsc & PORT_DEV_REMOVE)
 264                         port_removable |= 1 << (i + 1);
 265         }
 266
 267         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 268 }
 269
 270 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 271                 struct usb_hub_descriptor *desc)
 272 {
 273
 274         if (hcd->speed >= HCD_USB3)
 275                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 276         else
 277                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 278
 279 }
 280
 281 static unsigned int xhci_port_speed(unsigned int port_status)
 282 {
 283         if (DEV_LOWSPEED(port_status))
 284                 return USB_PORT_STAT_LOW_SPEED;
 285         if (DEV_HIGHSPEED(port_status))
 286                 return USB_PORT_STAT_HIGH_SPEED;
 287         /*
 288          * FIXME: Yes, we should check for full speed, but the core uses that as
 289          * a default in portspeed() in usb/core/hub.c (which is the only place
 290          * USB_PORT_STAT_*_SPEED is used).
 291          */
 292         return 0;
 293 }
 294
 295 /*
 296  * These bits are Read Only (RO) and should be saved and written to the
 297  * registers: 0, 3, 10:13, 30
 298  * connect status, over-current status, port speed, and device removable.
 299  * connect status and port speed are also sticky - meaning they're in
 300  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 301  */
 302 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 303 /*
 304  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 305  * bits 5:8, 9, 14:15, 25:27
 306  * link state, port power, port indicator state, "wake on" enable state
 307  */
 308 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 309 /*
 310  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 311  * bit 4 (port reset)
 312  */
 313 #define XHCI_PORT_RW1S  ((1<<4))
 314 /*
 315  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 316  * bits 1, 17, 18, 19, 20, 21, 22, 23
 317  * port enable/disable, and
 318  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 319  * over-current, reset, link state, and L1 change
 320  */
 321 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 322 /*
 323  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 324  * latched in
 325  */
 326 #define XHCI_PORT_RW    ((1<<16))
 327 /*
 328  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 329  * bits 2, 24, 28:31
 330  */
 331 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 332
 333 /*
 334  * Given a port state, this function returns a value that would result in the
 335  * port being in the same state, if the value was written to the port status
 336  * control register.
 337  * Save Read Only (RO) bits and save read/write bits where
 338  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 339  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 340  */
 341 u32 xhci_port_state_to_neutral(u32 state)
 342 {
 343         /* Save read-only status and port state */
 344         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 345 }
 346
 347 /*
 348  * find slot id based on port number.
 349  * @port: The one-based port number from one of the two split roothubs.
 350  */
 351 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 352                 u16 port)
 353 {
 354         int slot_id;
 355         int i;
 356         enum usb_device_speed speed;
 357
 358         slot_id = 0;
 359         for (i = 0; i < MAX_HC_SLOTS; i++) {
 360                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 361                         continue;
 362                 speed = xhci->devs[i]->udev->speed;
 363                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 364                                 && xhci->devs[i]->fake_port == port) {
 365                         slot_id = i;
 366                         break;
 367                 }
 368         }
 369
 370         return slot_id;
 371 }
 372
 373 /*
 374  * Stop device
 375  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 376  * to complete.
 377  * suspend will set to 1, if suspend bit need to set in command.
 378  */
 379 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 380 {
 381         struct xhci_virt_device *virt_dev;
 382         struct xhci_command *cmd;
 383         unsigned long flags;
 384         int ret;
 385         int i;
 386
 387         ret = 0;
 388         virt_dev = xhci->devs[slot_id];
 389         if (!virt_dev)
 390                 return -ENODEV;
 391
 392         trace_xhci_stop_device(virt_dev);
 393
 394         cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
 395         if (!cmd)
 396                 return -ENOMEM;
 397
 398         spin_lock_irqsave(&xhci->lock, flags);
 399         for (i = LAST_EP_INDEX; i > 0; i--) {
 400                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 401                         struct xhci_ep_ctx *ep_ctx;
 402                         struct xhci_command *command;
 403
 404                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 405
 406                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 407                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 408                                 continue;
 409
 410                         command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
 411                         if (!command) {
 412                                 spin_unlock_irqrestore(&xhci->lock, flags);
 413                                 ret = -ENOMEM;
 414                                 goto cmd_cleanup;
 415                         }
 416
 417                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 418                                                        i, suspend);
 419                         if (ret) {
 420                                 spin_unlock_irqrestore(&xhci->lock, flags);
 421                                 xhci_free_command(xhci, command);
 422                                 goto cmd_cleanup;
 423                         }
 424                 }
 425         }
 426         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 427         if (ret) {
 428                 spin_unlock_irqrestore(&xhci->lock, flags);
 429                 goto cmd_cleanup;
 430         }
 431
 432         xhci_ring_cmd_db(xhci);
 433         spin_unlock_irqrestore(&xhci->lock, flags);
 434
 435         /* Wait for last stop endpoint command to finish */
 436         wait_for_completion(cmd->completion);
 437
 438         if (cmd->status == COMP_COMMAND_ABORTED ||
 439             cmd->status == COMP_COMMAND_RING_STOPPED) {
 440                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 441                 ret = -ETIME;
 442         }
 443
 444 cmd_cleanup:
 445         xhci_free_command(xhci, cmd);
 446         return ret;
 447 }
 448
 449 /*
 450  * Ring device, it rings the all doorbells unconditionally.
 451  */
 452 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 453 {
 454         int i, s;
 455         struct xhci_virt_ep *ep;
 456
 457         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 458                 ep = &xhci->devs[slot_id]->eps[i];
 459
 460                 if (ep->ep_state & EP_HAS_STREAMS) {
 461                         for (s = 1; s < ep->stream_info->num_streams; s++)
 462                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 463                 } else if (ep->ring && ep->ring->dequeue) {
 464                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 465                 }
 466         }
 467
 468         return;
 469 }
 470
 471 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 472                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 473 {
 474         /* Don't allow the USB core to disable SuperSpeed ports. */
 475         if (hcd->speed >= HCD_USB3) {
 476                 xhci_dbg(xhci, "Ignoring request to disable "
 477                                 "SuperSpeed port.\n");
 478                 return;
 479         }
 480
 481         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 482                 xhci_dbg(xhci,
 483                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 484                 return;
 485         }
 486
 487         /* Write 1 to disable the port */
 488         writel(port_status | PORT_PE, addr);
 489         port_status = readl(addr);
 490         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 491                         wIndex, port_status);
 492 }
 493
 494 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 495                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 496 {
 497         char *port_change_bit;
 498         u32 status;
 499
 500         switch (wValue) {
 501         case USB_PORT_FEAT_C_RESET:
 502                 status = PORT_RC;
 503                 port_change_bit = "reset";
 504                 break;
 505         case USB_PORT_FEAT_C_BH_PORT_RESET:
 506                 status = PORT_WRC;
 507                 port_change_bit = "warm(BH) reset";
 508                 break;
 509         case USB_PORT_FEAT_C_CONNECTION:
 510                 status = PORT_CSC;
 511                 port_change_bit = "connect";
 512                 break;
 513         case USB_PORT_FEAT_C_OVER_CURRENT:
 514                 status = PORT_OCC;
 515                 port_change_bit = "over-current";
 516                 break;
 517         case USB_PORT_FEAT_C_ENABLE:
 518                 status = PORT_PEC;
 519                 port_change_bit = "enable/disable";
 520                 break;
 521         case USB_PORT_FEAT_C_SUSPEND:
 522                 status = PORT_PLC;
 523                 port_change_bit = "suspend/resume";
 524                 break;
 525         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 526                 status = PORT_PLC;
 527                 port_change_bit = "link state";
 528                 break;
 529         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 530                 status = PORT_CEC;
 531                 port_change_bit = "config error";
 532                 break;
 533         default:
 534                 /* Should never happen */
 535                 return;
 536         }
 537         /* Change bits are all write 1 to clear */
 538         writel(port_status | status, addr);
 539         port_status = readl(addr);
 540         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 541                         port_change_bit, wIndex, port_status);
 542 }
 543
 544 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
 545 {
 546         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 547
 548         if (hcd->speed >= HCD_USB3)
 549                 return &xhci->usb3_rhub;
 550         return &xhci->usb2_rhub;
 551 }
 552
 553 /*
 554  * xhci_set_port_power() must be called with xhci->lock held.
 555  * It will release and re-aquire the lock while calling ACPI
 556  * method.
 557  */
 558 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 559                                 u16 index, bool on, unsigned long *flags)
 560 {
 561         struct xhci_hub *rhub;
 562         struct xhci_port *port;
 563         u32 temp;
 564
 565         rhub = xhci_get_rhub(hcd);
 566         port = rhub->ports[index];
 567         temp = readl(port->addr);
 568         temp = xhci_port_state_to_neutral(temp);
 569         if (on) {
 570                 /* Power on */
 571                 writel(temp | PORT_POWER, port->addr);
 572                 temp = readl(port->addr);
 573                 xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
 574                                                 index, temp);
 575         } else {
 576                 /* Power off */
 577                 writel(temp & ~PORT_POWER, port->addr);
 578         }
 579
 580         spin_unlock_irqrestore(&xhci->lock, *flags);
 581         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 582                                         index);
 583         if (temp)
 584                 usb_acpi_set_power_state(hcd->self.root_hub,
 585                         index, on);
 586         spin_lock_irqsave(&xhci->lock, *flags);
 587 }
 588
 589 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 590         u16 test_mode, u16 wIndex)
 591 {
 592         u32 temp;
 593         struct xhci_port *port;
 594
 595         /* xhci only supports test mode for usb2 ports */
 596         port = xhci->usb2_rhub.ports[wIndex];
 597         temp = readl(port->addr + PORTPMSC);
 598         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 599         writel(temp, port->addr + PORTPMSC);
 600         xhci->test_mode = test_mode;
 601         if (test_mode == TEST_FORCE_EN)
 602                 xhci_start(xhci);
 603 }
 604
 605 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 606                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 607 {
 608         int i, retval;
 609
 610         /* Disable all Device Slots */
 611         xhci_dbg(xhci, "Disable all slots\n");
 612         spin_unlock_irqrestore(&xhci->lock, *flags);
 613         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 614                 if (!xhci->devs[i])
 615                         continue;
 616
 617                 retval = xhci_disable_slot(xhci, i);
 618                 if (retval)
 619                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 620                                  i, retval);
 621         }
 622         spin_lock_irqsave(&xhci->lock, *flags);
 623         /* Put all ports to the Disable state by clear PP */
 624         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 625         /* Power off USB3 ports*/
 626         for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
 627                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 628         /* Power off USB2 ports*/
 629         for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
 630                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 631         /* Stop the controller */
 632         xhci_dbg(xhci, "Stop controller\n");
 633         retval = xhci_halt(xhci);
 634         if (retval)
 635                 return retval;
 636         /* Disable runtime PM for test mode */
 637         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 638         /* Set PORTPMSC.PTC field to enter selected test mode */
 639         /* Port is selected by wIndex. port_id = wIndex + 1 */
 640         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 641                                         test_mode, wIndex + 1);
 642         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 643         return retval;
 644 }
 645
 646 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 647 {
 648         int retval;
 649
 650         if (!xhci->test_mode) {
 651                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 652                 return 0;
 653         }
 654         if (xhci->test_mode == TEST_FORCE_EN &&
 655                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 656                 retval = xhci_halt(xhci);
 657                 if (retval)
 658                         return retval;
 659         }
 660         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 661         xhci->test_mode = 0;
 662         return xhci_reset(xhci);
 663 }
 664
 665 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
 666                          u32 link_state)
 667 {
 668         u32 temp;
 669
 670         temp = readl(port->addr);
 671         temp = xhci_port_state_to_neutral(temp);
 672         temp &= ~PORT_PLS_MASK;
 673         temp |= PORT_LINK_STROBE | link_state;
 674         writel(temp, port->addr);
 675 }
 676
 677 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 678                                       struct xhci_port *port, u16 wake_mask)
 679 {
 680         u32 temp;
 681
 682         temp = readl(port->addr);
 683         temp = xhci_port_state_to_neutral(temp);
 684
 685         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 686                 temp |= PORT_WKCONN_E;
 687         else
 688                 temp &= ~PORT_WKCONN_E;
 689
 690         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 691                 temp |= PORT_WKDISC_E;
 692         else
 693                 temp &= ~PORT_WKDISC_E;
 694
 695         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 696                 temp |= PORT_WKOC_E;
 697         else
 698                 temp &= ~PORT_WKOC_E;
 699
 700         writel(temp, port->addr);
 701 }
 702
 703 /* Test and clear port RWC bit */
 704 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
 705                              u32 port_bit)
 706 {
 707         u32 temp;
 708
 709         temp = readl(port->addr);
 710         if (temp & port_bit) {
 711                 temp = xhci_port_state_to_neutral(temp);
 712                 temp |= port_bit;
 713                 writel(temp, port->addr);
 714         }
 715 }
 716
 717 /* Updates Link Status for USB 2.1 port */
 718 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 719 {
 720         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 721                 *status |= USB_PORT_STAT_L1;
 722 }
 723
 724 /* Updates Link Status for super Speed port */
 725 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 726                 u32 *status, u32 status_reg)
 727 {
 728         u32 pls = status_reg & PORT_PLS_MASK;
 729
 730         /* resume state is a xHCI internal state.
 731          * Do not report it to usb core, instead, pretend to be U3,
 732          * thus usb core knows it's not ready for transfer
 733          */
 734         if (pls == XDEV_RESUME) {
 735                 *status |= USB_SS_PORT_LS_U3;
 736                 return;
 737         }
 738
 739         /* When the CAS bit is set then warm reset
 740          * should be performed on port
 741          */
 742         if (status_reg & PORT_CAS) {
 743                 /* The CAS bit can be set while the port is
 744                  * in any link state.
 745                  * Only roothubs have CAS bit, so we
 746                  * pretend to be in compliance mode
 747                  * unless we're already in compliance
 748                  * or the inactive state.
 749                  */
 750                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 751                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 752                         pls = USB_SS_PORT_LS_COMP_MOD;
 753                 }
 754                 /* Return also connection bit -
 755                  * hub state machine resets port
 756                  * when this bit is set.
 757                  */
 758                 pls |= USB_PORT_STAT_CONNECTION;
 759         } else {
 760                 /*
 761                  * If CAS bit isn't set but the Port is already at
 762                  * Compliance Mode, fake a connection so the USB core
 763                  * notices the Compliance state and resets the port.
 764                  * This resolves an issue generated by the SN65LVPE502CP
 765                  * in which sometimes the port enters compliance mode
 766                  * caused by a delay on the host-device negotiation.
 767                  */
 768                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 769                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 770                         pls |= USB_PORT_STAT_CONNECTION;
 771         }
 772
 773         /* update status field */
 774         *status |= pls;
 775 }
 776
 777 /*
 778  * Function for Compliance Mode Quirk.
 779  *
 780  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 781  * the compliance mode timer is deleted. A port won't enter
 782  * compliance mode if it has previously entered U0.
 783  */
 784 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 785                                     u16 wIndex)
 786 {
 787         u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
 788         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 789
 790         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 791                 return;
 792
 793         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 794                 xhci->port_status_u0 |= 1 << wIndex;
 795                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 796                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 797                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 798                                 "All USB3 ports have entered U0 already!");
 799                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 800                                 "Compliance Mode Recovery Timer Deleted.");
 801                 }
 802         }
 803 }
 804
 805 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 806 {
 807         u32 ext_stat = 0;
 808         int speed_id;
 809
 810         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 811         speed_id = DEV_PORT_SPEED(raw_port_status);
 812         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 813         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 814
 815         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 816         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 817
 818         return ext_stat;
 819 }
 820
 821 /*
 822  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 823  * 3.0 hubs use.
 824  *
 825  * Possible side effects:
 826  *  - Mark a port as being done with device resume,
 827  *    and ring the endpoint doorbells.
 828  *  - Stop the Synopsys redriver Compliance Mode polling.
 829  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 830  */
 831 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 832                 struct xhci_bus_state *bus_state,
 833         u16 wIndex, u32 raw_port_status,
 834                 unsigned long flags)
 835         __releases(&xhci->lock)
 836         __acquires(&xhci->lock)
 837 {
 838         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 839         u32 status = 0;
 840         int slot_id;
 841         struct xhci_hub *rhub;
 842         struct xhci_port *port;
 843
 844         rhub = xhci_get_rhub(hcd);
 845         port = rhub->ports[wIndex];
 846
 847         /* wPortChange bits */
 848         if (raw_port_status & PORT_CSC)
 849                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 850         if (raw_port_status & PORT_PEC)
 851                 status |= USB_PORT_STAT_C_ENABLE << 16;
 852         if ((raw_port_status & PORT_OCC))
 853                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 854         if ((raw_port_status & PORT_RC))
 855                 status |= USB_PORT_STAT_C_RESET << 16;
 856         /* USB3.0 only */
 857         if (hcd->speed >= HCD_USB3) {
 858                 /* Port link change with port in resume state should not be
 859                  * reported to usbcore, as this is an internal state to be
 860                  * handled by xhci driver. Reporting PLC to usbcore may
 861                  * cause usbcore clearing PLC first and port change event
 862                  * irq won't be generated.
 863                  */
 864                 if ((raw_port_status & PORT_PLC) &&
 865                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 866                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 867                 if ((raw_port_status & PORT_WRC))
 868                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 869                 if ((raw_port_status & PORT_CEC))
 870                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 871         }
 872
 873         if (hcd->speed < HCD_USB3) {
 874                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 875                                 && (raw_port_status & PORT_POWER))
 876                         status |= USB_PORT_STAT_SUSPEND;
 877         }
 878         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 879                 !DEV_SUPERSPEED_ANY(raw_port_status)) {
 880                 if ((raw_port_status & PORT_RESET) ||
 881                                 !(raw_port_status & PORT_PE))
 882                         return 0xffffffff;
 883                 /* did port event handler already start resume timing? */
 884                 if (!bus_state->resume_done[wIndex]) {
 885                         /* If not, maybe we are in a host initated resume? */
 886                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 887                                 /* Host initated resume doesn't time the resume
 888                                  * signalling using resume_done[].
 889                                  * It manually sets RESUME state, sleeps 20ms
 890                                  * and sets U0 state. This should probably be
 891                                  * changed, but not right now.
 892                                  */
 893                         } else {
 894                                 /* port resume was discovered now and here,
 895                                  * start resume timing
 896                                  */
 897                                 unsigned long timeout = jiffies +
 898                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 899
 900                                 set_bit(wIndex, &bus_state->resuming_ports);
 901                                 bus_state->resume_done[wIndex] = timeout;
 902                                 mod_timer(&hcd->rh_timer, timeout);
 903                         }
 904                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 905                 } else if (time_after_eq(jiffies,
 906                                          bus_state->resume_done[wIndex])) {
 907                         int time_left;
 908
 909                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 910                                         wIndex + 1);
 911                         bus_state->resume_done[wIndex] = 0;
 912                         clear_bit(wIndex, &bus_state->resuming_ports);
 913
 914                         set_bit(wIndex, &bus_state->rexit_ports);
 915
 916                         xhci_test_and_clear_bit(xhci, port, PORT_PLC);
 917                         xhci_set_link_state(xhci, port, XDEV_U0);
 918
 919                         spin_unlock_irqrestore(&xhci->lock, flags);
 920                         time_left = wait_for_completion_timeout(
 921                                         &bus_state->rexit_done[wIndex],
 922                                         msecs_to_jiffies(
 923                                                 XHCI_MAX_REXIT_TIMEOUT));
 924                         spin_lock_irqsave(&xhci->lock, flags);
 925
 926                         if (time_left) {
 927                                 slot_id = xhci_find_slot_id_by_port(hcd,
 928                                                 xhci, wIndex + 1);
 929                                 if (!slot_id) {
 930                                         xhci_dbg(xhci, "slot_id is zero\n");
 931                                         return 0xffffffff;
 932                                 }
 933                                 xhci_ring_device(xhci, slot_id);
 934                         } else {
 935                                 int port_status = readl(port->addr);
 936                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 937                                                 XHCI_MAX_REXIT_TIMEOUT,
 938                                                 port_status);
 939                                 status |= USB_PORT_STAT_SUSPEND;
 940                                 clear_bit(wIndex, &bus_state->rexit_ports);
 941                         }
 942
 943                         bus_state->port_c_suspend |= 1 << wIndex;
 944                         bus_state->suspended_ports &= ~(1 << wIndex);
 945                 } else {
 946                         /*
 947                          * The resume has been signaling for less than
 948                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 949                          * let the usbcore check port status again and clear
 950                          * resume signaling later.
 951                          */
 952                         status |= USB_PORT_STAT_SUSPEND;
 953                 }
 954         }
 955         /*
 956          * Clear stale usb2 resume signalling variables in case port changed
 957          * state during resume signalling. For example on error
 958          */
 959         if ((bus_state->resume_done[wIndex] ||
 960              test_bit(wIndex, &bus_state->resuming_ports)) &&
 961             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 962             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 963                 bus_state->resume_done[wIndex] = 0;
 964                 clear_bit(wIndex, &bus_state->resuming_ports);
 965         }
 966
 967
 968         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 969             (raw_port_status & PORT_POWER)) {
 970                 if (bus_state->suspended_ports & (1 << wIndex)) {
 971                         bus_state->suspended_ports &= ~(1 << wIndex);
 972                         if (hcd->speed < HCD_USB3)
 973                                 bus_state->port_c_suspend |= 1 << wIndex;
 974                 }
 975                 bus_state->resume_done[wIndex] = 0;
 976                 clear_bit(wIndex, &bus_state->resuming_ports);
 977         }
 978         if (raw_port_status & PORT_CONNECT) {
 979                 status |= USB_PORT_STAT_CONNECTION;
 980                 status |= xhci_port_speed(raw_port_status);
 981         }
 982         if (raw_port_status & PORT_PE)
 983                 status |= USB_PORT_STAT_ENABLE;
 984         if (raw_port_status & PORT_OC)
 985                 status |= USB_PORT_STAT_OVERCURRENT;
 986         if (raw_port_status & PORT_RESET)
 987                 status |= USB_PORT_STAT_RESET;
 988         if (raw_port_status & PORT_POWER) {
 989                 if (hcd->speed >= HCD_USB3)
 990                         status |= USB_SS_PORT_STAT_POWER;
 991                 else
 992                         status |= USB_PORT_STAT_POWER;
 993         }
 994         /* Update Port Link State */
 995         if (hcd->speed >= HCD_USB3) {
 996                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
 997                 /*
 998                  * Verify if all USB3 Ports Have entered U0 already.
 999                  * Delete Compliance Mode Timer if so.
1000                  */
1001                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1002         } else {
1003                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1004         }
1005         if (bus_state->port_c_suspend & (1 << wIndex))
1006                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1007
1008         return status;
1009 }
1010
1011 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1012                 u16 wIndex, char *buf, u16 wLength)
1013 {
1014         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1015         int max_ports;
1016         unsigned long flags;
1017         u32 temp, status;
1018         int retval = 0;
1019         int slot_id;
1020         struct xhci_bus_state *bus_state;
1021         u16 link_state = 0;
1022         u16 wake_mask = 0;
1023         u16 timeout = 0;
1024         u16 test_mode = 0;
1025         struct xhci_hub *rhub;
1026         struct xhci_port **ports;
1027
1028         rhub = xhci_get_rhub(hcd);
1029         ports = rhub->ports;
1030         max_ports = rhub->num_ports;
1031         bus_state = &xhci->bus_state[hcd_index(hcd)];
1032
1033         spin_lock_irqsave(&xhci->lock, flags);
1034         switch (typeReq) {
1035         case GetHubStatus:
1036                 /* No power source, over-current reported per port */
1037                 memset(buf, 0, 4);
1038                 break;
1039         case GetHubDescriptor:
1040                 /* Check to make sure userspace is asking for the USB 3.0 hub
1041                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1042                  * endpoint, like external hubs do.
1043                  */
1044                 if (hcd->speed >= HCD_USB3 &&
1045                                 (wLength < USB_DT_SS_HUB_SIZE ||
1046                                  wValue != (USB_DT_SS_HUB << 8))) {
1047                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1048                                         "USB 3.0 roothub.\n");
1049                         goto error;
1050                 }
1051                 xhci_hub_descriptor(hcd, xhci,
1052                                 (struct usb_hub_descriptor *) buf);
1053                 break;
1054         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1055                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1056                         goto error;
1057
1058                 if (hcd->speed < HCD_USB3)
1059                         goto error;
1060
1061                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1062                 spin_unlock_irqrestore(&xhci->lock, flags);
1063                 return retval;
1064         case GetPortStatus:
1065                 if (!wIndex || wIndex > max_ports)
1066                         goto error;
1067                 wIndex--;
1068                 temp = readl(ports[wIndex]->addr);
1069                 if (temp == ~(u32)0) {
1070                         xhci_hc_died(xhci);
1071                         retval = -ENODEV;
1072                         break;
1073                 }
1074                 trace_xhci_get_port_status(wIndex, temp);
1075                 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1076                                               flags);
1077                 if (status == 0xffffffff)
1078                         goto error;
1079
1080                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1081                                 wIndex, temp);
1082                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1083
1084                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1085                 /* if USB 3.1 extended port status return additional 4 bytes */
1086                 if (wValue == 0x02) {
1087                         u32 port_li;
1088
1089                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1090                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1091                                 retval = -EINVAL;
1092                                 break;
1093                         }
1094                         port_li = readl(ports[wIndex]->addr + PORTLI);
1095                         status = xhci_get_ext_port_status(temp, port_li);
1096                         put_unaligned_le32(cpu_to_le32(status), &buf[4]);
1097                 }
1098                 break;
1099         case SetPortFeature:
1100                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1101                         link_state = (wIndex & 0xff00) >> 3;
1102                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1103                         wake_mask = wIndex & 0xff00;
1104                 if (wValue == USB_PORT_FEAT_TEST)
1105                         test_mode = (wIndex & 0xff00) >> 8;
1106                 /* The MSB of wIndex is the U1/U2 timeout */
1107                 timeout = (wIndex & 0xff00) >> 8;
1108                 wIndex &= 0xff;
1109                 if (!wIndex || wIndex > max_ports)
1110                         goto error;
1111                 wIndex--;
1112                 temp = readl(ports[wIndex]->addr);
1113                 if (temp == ~(u32)0) {
1114                         xhci_hc_died(xhci);
1115                         retval = -ENODEV;
1116                         break;
1117                 }
1118                 temp = xhci_port_state_to_neutral(temp);
1119                 /* FIXME: What new port features do we need to support? */
1120                 switch (wValue) {
1121                 case USB_PORT_FEAT_SUSPEND:
1122                         temp = readl(ports[wIndex]->addr);
1123                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1124                                 /* Resume the port to U0 first */
1125                                 xhci_set_link_state(xhci, ports[wIndex],
1126                                                         XDEV_U0);
1127                                 spin_unlock_irqrestore(&xhci->lock, flags);
1128                                 msleep(10);
1129                                 spin_lock_irqsave(&xhci->lock, flags);
1130                         }
1131                         /* In spec software should not attempt to suspend
1132                          * a port unless the port reports that it is in the
1133                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1134                          */
1135                         temp = readl(ports[wIndex]->addr);
1136                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1137                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1138                                 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1139                                 goto error;
1140                         }
1141
1142                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1143                                         wIndex + 1);
1144                         if (!slot_id) {
1145                                 xhci_warn(xhci, "slot_id is zero\n");
1146                                 goto error;
1147                         }
1148                         /* unlock to execute stop endpoint commands */
1149                         spin_unlock_irqrestore(&xhci->lock, flags);
1150                         xhci_stop_device(xhci, slot_id, 1);
1151                         spin_lock_irqsave(&xhci->lock, flags);
1152
1153                         xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1154
1155                         spin_unlock_irqrestore(&xhci->lock, flags);
1156                         msleep(10); /* wait device to enter */
1157                         spin_lock_irqsave(&xhci->lock, flags);
1158
1159                         temp = readl(ports[wIndex]->addr);
1160                         bus_state->suspended_ports |= 1 << wIndex;
1161                         break;
1162                 case USB_PORT_FEAT_LINK_STATE:
1163                         temp = readl(ports[wIndex]->addr);
1164                         /* Disable port */
1165                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1166                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1167                                 temp = xhci_port_state_to_neutral(temp);
1168                                 /*
1169                                  * Clear all change bits, so that we get a new
1170                                  * connection event.
1171                                  */
1172                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1173                                         PORT_OCC | PORT_RC | PORT_PLC |
1174                                         PORT_CEC;
1175                                 writel(temp | PORT_PE, ports[wIndex]->addr);
1176                                 temp = readl(ports[wIndex]->addr);
1177                                 break;
1178                         }
1179
1180                         /* Put link in RxDetect (enable port) */
1181                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1182                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1183                                 xhci_set_link_state(xhci, ports[wIndex],
1184                                                         link_state);
1185                                 temp = readl(ports[wIndex]->addr);
1186                                 break;
1187                         }
1188
1189                         /*
1190                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1191                          * root hub port's transition to compliance mode upon
1192                          * detecting LFPS timeout may be controlled by an
1193                          * Compliance Transition Enabled (CTE) flag (not
1194                          * software visible). This flag is set by writing 0xA
1195                          * to PORTSC PLS field which will allow transition to
1196                          * compliance mode the next time LFPS timeout is
1197                          * encountered. A warm reset will clear it.
1198                          *
1199                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1200                          * flag is set, otherwise, the compliance substate is
1201                          * automatically entered as on 1.0 and prior.
1202                          */
1203                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1204                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1205                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1206                                         break;
1207                                 }
1208
1209                                 if ((temp & PORT_CONNECT)) {
1210                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1211                                         goto error;
1212                                 }
1213
1214                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1215                                                 wIndex);
1216                                 xhci_set_link_state(xhci, ports[wIndex],
1217                                                 link_state);
1218
1219                                 temp = readl(ports[wIndex]->addr);
1220                                 break;
1221                         }
1222                         /* Port must be enabled */
1223                         if (!(temp & PORT_PE)) {
1224                                 retval = -ENODEV;
1225                                 break;
1226                         }
1227                         /* Can't set port link state above '3' (U3) */
1228                         if (link_state > USB_SS_PORT_LS_U3) {
1229                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1230                                          wIndex, link_state);
1231                                 goto error;
1232                         }
1233                         if (link_state == USB_SS_PORT_LS_U3) {
1234                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1235                                                 wIndex + 1);
1236                                 if (slot_id) {
1237                                         /* unlock to execute stop endpoint
1238                                          * commands */
1239                                         spin_unlock_irqrestore(&xhci->lock,
1240                                                                 flags);
1241                                         xhci_stop_device(xhci, slot_id, 1);
1242                                         spin_lock_irqsave(&xhci->lock, flags);
1243                                 }
1244                         }
1245
1246                         xhci_set_link_state(xhci, ports[wIndex], link_state);
1247
1248                         spin_unlock_irqrestore(&xhci->lock, flags);
1249                         msleep(20); /* wait device to enter */
1250                         spin_lock_irqsave(&xhci->lock, flags);
1251
1252                         temp = readl(ports[wIndex]->addr);
1253                         if (link_state == USB_SS_PORT_LS_U3)
1254                                 bus_state->suspended_ports |= 1 << wIndex;
1255                         break;
1256                 case USB_PORT_FEAT_POWER:
1257                         /*
1258                          * Turn on ports, even if there isn't per-port switching.
1259                          * HC will report connect events even before this is set.
1260                          * However, hub_wq will ignore the roothub events until
1261                          * the roothub is registered.
1262                          */
1263                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1264                         break;
1265                 case USB_PORT_FEAT_RESET:
1266                         temp = (temp | PORT_RESET);
1267                         writel(temp, ports[wIndex]->addr);
1268
1269                         temp = readl(ports[wIndex]->addr);
1270                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1271                         break;
1272                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1273                         xhci_set_remote_wake_mask(xhci, ports[wIndex],
1274                                                   wake_mask);
1275                         temp = readl(ports[wIndex]->addr);
1276                         xhci_dbg(xhci, "set port remote wake mask, "
1277                                         "actual port %d status  = 0x%x\n",
1278                                         wIndex, temp);
1279                         break;
1280                 case USB_PORT_FEAT_BH_PORT_RESET:
1281                         temp |= PORT_WR;
1282                         writel(temp, ports[wIndex]->addr);
1283                         temp = readl(ports[wIndex]->addr);
1284                         break;
1285                 case USB_PORT_FEAT_U1_TIMEOUT:
1286                         if (hcd->speed < HCD_USB3)
1287                                 goto error;
1288                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1289                         temp &= ~PORT_U1_TIMEOUT_MASK;
1290                         temp |= PORT_U1_TIMEOUT(timeout);
1291                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1292                         break;
1293                 case USB_PORT_FEAT_U2_TIMEOUT:
1294                         if (hcd->speed < HCD_USB3)
1295                                 goto error;
1296                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1297                         temp &= ~PORT_U2_TIMEOUT_MASK;
1298                         temp |= PORT_U2_TIMEOUT(timeout);
1299                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1300                         break;
1301                 case USB_PORT_FEAT_TEST:
1302                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1303                         if (hcd->speed != HCD_USB2)
1304                                 goto error;
1305                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1306                                 goto error;
1307                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1308                                                       &flags);
1309                         break;
1310                 default:
1311                         goto error;
1312                 }
1313                 /* unblock any posted writes */
1314                 temp = readl(ports[wIndex]->addr);
1315                 break;
1316         case ClearPortFeature:
1317                 if (!wIndex || wIndex > max_ports)
1318                         goto error;
1319                 wIndex--;
1320                 temp = readl(ports[wIndex]->addr);
1321                 if (temp == ~(u32)0) {
1322                         xhci_hc_died(xhci);
1323                         retval = -ENODEV;
1324                         break;
1325                 }
1326                 /* FIXME: What new port features do we need to support? */
1327                 temp = xhci_port_state_to_neutral(temp);
1328                 switch (wValue) {
1329                 case USB_PORT_FEAT_SUSPEND:
1330                         temp = readl(ports[wIndex]->addr);
1331                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1332                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1333                         if (temp & PORT_RESET)
1334                                 goto error;
1335                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1336                                 if ((temp & PORT_PE) == 0)
1337                                         goto error;
1338
1339                                 set_bit(wIndex, &bus_state->resuming_ports);
1340                                 xhci_set_link_state(xhci, ports[wIndex],
1341                                                     XDEV_RESUME);
1342                                 spin_unlock_irqrestore(&xhci->lock, flags);
1343                                 msleep(USB_RESUME_TIMEOUT);
1344                                 spin_lock_irqsave(&xhci->lock, flags);
1345                                 xhci_set_link_state(xhci, ports[wIndex],
1346                                                         XDEV_U0);
1347                                 clear_bit(wIndex, &bus_state->resuming_ports);
1348                         }
1349                         bus_state->port_c_suspend |= 1 << wIndex;
1350
1351                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1352                                         wIndex + 1);
1353                         if (!slot_id) {
1354                                 xhci_dbg(xhci, "slot_id is zero\n");
1355                                 goto error;
1356                         }
1357                         xhci_ring_device(xhci, slot_id);
1358                         break;
1359                 case USB_PORT_FEAT_C_SUSPEND:
1360                         bus_state->port_c_suspend &= ~(1 << wIndex);
1361                         /* fall through */
1362                 case USB_PORT_FEAT_C_RESET:
1363                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1364                 case USB_PORT_FEAT_C_CONNECTION:
1365                 case USB_PORT_FEAT_C_OVER_CURRENT:
1366                 case USB_PORT_FEAT_C_ENABLE:
1367                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1368                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1369                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1370                                         ports[wIndex]->addr, temp);
1371                         break;
1372                 case USB_PORT_FEAT_ENABLE:
1373                         xhci_disable_port(hcd, xhci, wIndex,
1374                                         ports[wIndex]->addr, temp);
1375                         break;
1376                 case USB_PORT_FEAT_POWER:
1377                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1378                         break;
1379                 case USB_PORT_FEAT_TEST:
1380                         retval = xhci_exit_test_mode(xhci);
1381                         break;
1382                 default:
1383                         goto error;
1384                 }
1385                 break;
1386         default:
1387 error:
1388                 /* "stall" on error */
1389                 retval = -EPIPE;
1390         }
1391         spin_unlock_irqrestore(&xhci->lock, flags);
1392         return retval;
1393 }
1394
1395 /*
1396  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1397  * Ports are 0-indexed from the HCD point of view,
1398  * and 1-indexed from the USB core pointer of view.
1399  *
1400  * Note that the status change bits will be cleared as soon as a port status
1401  * change event is generated, so we use the saved status from that event.
1402  */
1403 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1404 {
1405         unsigned long flags;
1406         u32 temp, status;
1407         u32 mask;
1408         int i, retval;
1409         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1410         int max_ports;
1411         struct xhci_bus_state *bus_state;
1412         bool reset_change = false;
1413         struct xhci_hub *rhub;
1414         struct xhci_port **ports;
1415
1416         rhub = xhci_get_rhub(hcd);
1417         ports = rhub->ports;
1418         max_ports = rhub->num_ports;
1419         bus_state = &xhci->bus_state[hcd_index(hcd)];
1420
1421         /* Initial status is no changes */
1422         retval = (max_ports + 8) / 8;
1423         memset(buf, 0, retval);
1424
1425         /*
1426          * Inform the usbcore about resume-in-progress by returning
1427          * a non-zero value even if there are no status changes.
1428          */
1429         status = bus_state->resuming_ports;
1430
1431         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1432
1433         spin_lock_irqsave(&xhci->lock, flags);
1434         /* For each port, did anything change?  If so, set that bit in buf. */
1435         for (i = 0; i < max_ports; i++) {
1436                 temp = readl(ports[i]->addr);
1437                 if (temp == ~(u32)0) {
1438                         xhci_hc_died(xhci);
1439                         retval = -ENODEV;
1440                         break;
1441                 }
1442                 trace_xhci_hub_status_data(i, temp);
1443
1444                 if ((temp & mask) != 0 ||
1445                         (bus_state->port_c_suspend & 1 << i) ||
1446                         (bus_state->resume_done[i] && time_after_eq(
1447                             jiffies, bus_state->resume_done[i]))) {
1448                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1449                         status = 1;
1450                 }
1451                 if ((temp & PORT_RC))
1452                         reset_change = true;
1453         }
1454         if (!status && !reset_change) {
1455                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1456                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1457         }
1458         spin_unlock_irqrestore(&xhci->lock, flags);
1459         return status ? retval : 0;
1460 }
1461
1462 #ifdef CONFIG_PM
1463
1464 int xhci_bus_suspend(struct usb_hcd *hcd)
1465 {
1466         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1467         int max_ports, port_index;
1468         struct xhci_bus_state *bus_state;
1469         unsigned long flags;
1470         struct xhci_hub *rhub;
1471         struct xhci_port **ports;
1472
1473         rhub = xhci_get_rhub(hcd);
1474         ports = rhub->ports;
1475         max_ports = rhub->num_ports;
1476         bus_state = &xhci->bus_state[hcd_index(hcd)];
1477
1478         spin_lock_irqsave(&xhci->lock, flags);
1479
1480         if (hcd->self.root_hub->do_remote_wakeup) {
1481                 if (bus_state->resuming_ports ||        /* USB2 */
1482                     bus_state->port_remote_wakeup) {    /* USB3 */
1483                         spin_unlock_irqrestore(&xhci->lock, flags);
1484                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1485                         return -EBUSY;
1486                 }
1487         }
1488
1489         port_index = max_ports;
1490         bus_state->bus_suspended = 0;
1491         while (port_index--) {
1492                 /* suspend the port if the port is not suspended */
1493                 u32 t1, t2;
1494                 int slot_id;
1495
1496                 t1 = readl(ports[port_index]->addr);
1497                 t2 = xhci_port_state_to_neutral(t1);
1498
1499                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1500                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1501                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1502                                         port_index + 1);
1503                         if (slot_id) {
1504                                 spin_unlock_irqrestore(&xhci->lock, flags);
1505                                 xhci_stop_device(xhci, slot_id, 1);
1506                                 spin_lock_irqsave(&xhci->lock, flags);
1507                         }
1508                         t2 &= ~PORT_PLS_MASK;
1509                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1510                         set_bit(port_index, &bus_state->bus_suspended);
1511                 }
1512                 /* USB core sets remote wake mask for USB 3.0 hubs,
1513                  * including the USB 3.0 roothub, but only if CONFIG_PM
1514                  * is enabled, so also enable remote wake here.
1515                  */
1516                 if (hcd->self.root_hub->do_remote_wakeup) {
1517                         if (t1 & PORT_CONNECT) {
1518                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1519                                 t2 &= ~PORT_WKCONN_E;
1520                         } else {
1521                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1522                                 t2 &= ~PORT_WKDISC_E;
1523                         }
1524
1525                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1526                             (hcd->speed < HCD_USB3)) {
1527                                 if (usb_amd_pt_check_port(hcd->self.controller,
1528                                                           port_index))
1529                                         t2 &= ~PORT_WAKE_BITS;
1530                         }
1531                 } else
1532                         t2 &= ~PORT_WAKE_BITS;
1533
1534                 t1 = xhci_port_state_to_neutral(t1);
1535                 if (t1 != t2)
1536                         writel(t2, ports[port_index]->addr);
1537         }
1538         hcd->state = HC_STATE_SUSPENDED;
1539         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1540         spin_unlock_irqrestore(&xhci->lock, flags);
1541         return 0;
1542 }
1543
1544 /*
1545  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1546  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1547  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1548  */
1549 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1550 {
1551         u32 portsc;
1552
1553         portsc = readl(port->addr);
1554
1555         /* if any of these are set we are not stuck */
1556         if (portsc & (PORT_CONNECT | PORT_CAS))
1557                 return false;
1558
1559         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1560             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1561                 return false;
1562
1563         /* clear wakeup/change bits, and do a warm port reset */
1564         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1565         portsc |= PORT_WR;
1566         writel(portsc, port->addr);
1567         /* flush write */
1568         readl(port->addr);
1569         return true;
1570 }
1571
1572 int xhci_bus_resume(struct usb_hcd *hcd)
1573 {
1574         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1575         struct xhci_bus_state *bus_state;
1576         unsigned long flags;
1577         int max_ports, port_index;
1578         int slot_id;
1579         int sret;
1580         u32 next_state;
1581         u32 temp, portsc;
1582         struct xhci_hub *rhub;
1583         struct xhci_port **ports;
1584
1585         rhub = xhci_get_rhub(hcd);
1586         ports = rhub->ports;
1587         max_ports = rhub->num_ports;
1588         bus_state = &xhci->bus_state[hcd_index(hcd)];
1589
1590         if (time_before(jiffies, bus_state->next_statechange))
1591                 msleep(5);
1592
1593         spin_lock_irqsave(&xhci->lock, flags);
1594         if (!HCD_HW_ACCESSIBLE(hcd)) {
1595                 spin_unlock_irqrestore(&xhci->lock, flags);
1596                 return -ESHUTDOWN;
1597         }
1598
1599         /* delay the irqs */
1600         temp = readl(&xhci->op_regs->command);
1601         temp &= ~CMD_EIE;
1602         writel(temp, &xhci->op_regs->command);
1603
1604         /* bus specific resume for ports we suspended at bus_suspend */
1605         if (hcd->speed >= HCD_USB3)
1606                 next_state = XDEV_U0;
1607         else
1608                 next_state = XDEV_RESUME;
1609
1610         port_index = max_ports;
1611         while (port_index--) {
1612                 portsc = readl(ports[port_index]->addr);
1613
1614                 /* warm reset CAS limited ports stuck in polling/compliance */
1615                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1616                     (hcd->speed >= HCD_USB3) &&
1617                     xhci_port_missing_cas_quirk(ports[port_index])) {
1618                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1619                         clear_bit(port_index, &bus_state->bus_suspended);
1620                         continue;
1621                 }
1622                 /* resume if we suspended the link, and it is still suspended */
1623                 if (test_bit(port_index, &bus_state->bus_suspended))
1624                         switch (portsc & PORT_PLS_MASK) {
1625                         case XDEV_U3:
1626                                 portsc = xhci_port_state_to_neutral(portsc);
1627                                 portsc &= ~PORT_PLS_MASK;
1628                                 portsc |= PORT_LINK_STROBE | next_state;
1629                                 break;
1630                         case XDEV_RESUME:
1631                                 /* resume already initiated */
1632                                 break;
1633                         default:
1634                                 /* not in a resumeable state, ignore it */
1635                                 clear_bit(port_index,
1636                                           &bus_state->bus_suspended);
1637                                 break;
1638                         }
1639                 /* disable wake for all ports, write new link state if needed */
1640                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1641                 writel(portsc, ports[port_index]->addr);
1642         }
1643
1644         /* USB2 specific resume signaling delay and U0 link state transition */
1645         if (hcd->speed < HCD_USB3) {
1646                 if (bus_state->bus_suspended) {
1647                         spin_unlock_irqrestore(&xhci->lock, flags);
1648                         msleep(USB_RESUME_TIMEOUT);
1649                         spin_lock_irqsave(&xhci->lock, flags);
1650                 }
1651                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1652                                  BITS_PER_LONG) {
1653                         /* Clear PLC to poll it later for U0 transition */
1654                         xhci_test_and_clear_bit(xhci, ports[port_index],
1655                                                 PORT_PLC);
1656                         xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1657                 }
1658         }
1659
1660         /* poll for U0 link state complete, both USB2 and USB3 */
1661         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1662                 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1663                                       PORT_PLC, 10 * 1000);
1664                 if (sret) {
1665                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1666                                   port_index);
1667                         continue;
1668                 }
1669                 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1670                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1671                 if (slot_id)
1672                         xhci_ring_device(xhci, slot_id);
1673         }
1674         (void) readl(&xhci->op_regs->command);
1675
1676         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1677         /* re-enable irqs */
1678         temp = readl(&xhci->op_regs->command);
1679         temp |= CMD_EIE;
1680         writel(temp, &xhci->op_regs->command);
1681         temp = readl(&xhci->op_regs->command);
1682
1683         spin_unlock_irqrestore(&xhci->lock, flags);
1684         return 0;
1685 }
1686
1687 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1688 {
1689         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1690         struct xhci_bus_state *bus_state;
1691
1692         bus_state = &xhci->bus_state[hcd_index(hcd)];
1693
1694         /* USB3 port wakeups are reported via usb_wakeup_notification() */
1695         return bus_state->resuming_ports;       /* USB2 ports only */
1696 }
1697
1698 #endif  /* CONFIG_PM */