drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "core.h"
  34 #include "gadget.h"
  35 #include "io.h"
  36
  37 /**
  38  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  39  * @dwc: pointer to our context structure
  40  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  41  *
  42  * Caller should take care of locking. This function will
  43  * return 0 on success or -EINVAL if wrong Test Selector
  44  * is passed
  45  */
  46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  47 {
  48         u32             reg;
  49
  50         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  51         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  52
  53         switch (mode) {
  54         case TEST_J:
  55         case TEST_K:
  56         case TEST_SE0_NAK:
  57         case TEST_PACKET:
  58         case TEST_FORCE_EN:
  59                 reg |= mode << 1;
  60                 break;
  61         default:
  62                 return -EINVAL;
  63         }
  64
  65         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  66
  67         return 0;
  68 }
  69
  70 /**
  71  * dwc3_gadget_get_link_state - Gets current state of USB Link
  72  * @dwc: pointer to our context structure
  73  *
  74  * Caller should take care of locking. This function will
  75  * return the link state on success (>= 0) or -ETIMEDOUT.
  76  */
  77 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  78 {
  79         u32             reg;
  80
  81         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  82
  83         return DWC3_DSTS_USBLNKST(reg);
  84 }
  85
  86 /**
  87  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  88  * @dwc: pointer to our context structure
  89  * @state: the state to put link into
  90  *
  91  * Caller should take care of locking. This function will
  92  * return 0 on success or -ETIMEDOUT.
  93  */
  94 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  95 {
  96         int             retries = 10000;
  97         u32             reg;
  98
  99         /*
 100          * Wait until device controller is ready. Only applies to 1.94a and
 101          * later RTL.
 102          */
 103         if (dwc->revision >= DWC3_REVISION_194A) {
 104                 while (--retries) {
 105                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 106                         if (reg & DWC3_DSTS_DCNRD)
 107                                 udelay(5);
 108                         else
 109                                 break;
 110                 }
 111
 112                 if (retries <= 0)
 113                         return -ETIMEDOUT;
 114         }
 115
 116         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 117         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 118
 119         /* set requested state */
 120         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 121         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 122
 123         /*
 124          * The following code is racy when called from dwc3_gadget_wakeup,
 125          * and is not needed, at least on newer versions
 126          */
 127         if (dwc->revision >= DWC3_REVISION_194A)
 128                 return 0;
 129
 130         /* wait for a change in DSTS */
 131         retries = 10000;
 132         while (--retries) {
 133                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 134
 135                 if (DWC3_DSTS_USBLNKST(reg) == state)
 136                         return 0;
 137
 138                 udelay(5);
 139         }
 140
 141         dev_vdbg(dwc->dev, "link state change request timed out\n");
 142
 143         return -ETIMEDOUT;
 144 }
 145
 146 /**
 147  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 148  * @dwc: pointer to our context structure
 149  *
 150  * This function will a best effort FIFO allocation in order
 151  * to improve FIFO usage and throughput, while still allowing
 152  * us to enable as many endpoints as possible.
 153  *
 154  * Keep in mind that this operation will be highly dependent
 155  * on the configured size for RAM1 - which contains TxFifo -,
 156  * the amount of endpoints enabled on coreConsultant tool, and
 157  * the width of the Master Bus.
 158  *
 159  * In the ideal world, we would always be able to satisfy the
 160  * following equation:
 161  *
 162  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 163  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 164  *
 165  * Unfortunately, due to many variables that's not always the case.
 166  */
 167 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 168 {
 169         int             last_fifo_depth = 0;
 170         int             ram1_depth;
 171         int             fifo_size;
 172         int             mdwidth;
 173         int             num;
 174
 175         if (!dwc->needs_fifo_resize)
 176                 return 0;
 177
 178         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 179         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 180
 181         /* MDWIDTH is represented in bits, we need it in bytes */
 182         mdwidth >>= 3;
 183
 184         /*
 185          * FIXME For now we will only allocate 1 wMaxPacketSize space
 186          * for each enabled endpoint, later patches will come to
 187          * improve this algorithm so that we better use the internal
 188          * FIFO space
 189          */
 190         for (num = 0; num < dwc->num_in_eps; num++) {
 191                 /* bit0 indicates direction; 1 means IN ep */
 192                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 193                 int             mult = 1;
 194                 int             tmp;
 195
 196                 if (!(dep->flags & DWC3_EP_ENABLED))
 197                         continue;
 198
 199                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 200                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 201                         mult = 3;
 202
 203                 /*
 204                  * REVISIT: the following assumes we will always have enough
 205                  * space available on the FIFO RAM for all possible use cases.
 206                  * Make sure that's true somehow and change FIFO allocation
 207                  * accordingly.
 208                  *
 209                  * If we have Bulk or Isochronous endpoints, we want
 210                  * them to be able to be very, very fast. So we're giving
 211                  * those endpoints a fifo_size which is enough for 3 full
 212                  * packets
 213                  */
 214                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 215                 tmp += mdwidth;
 216
 217                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 218
 219                 fifo_size |= (last_fifo_depth << 16);
 220
 221                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 222                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 223
 224                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 225
 226                 last_fifo_depth += (fifo_size & 0xffff);
 227         }
 228
 229         return 0;
 230 }
 231
 232 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 233                 int status)
 234 {
 235         struct dwc3                     *dwc = dep->dwc;
 236         int                             i;
 237
 238         if (req->queued) {
 239                 i = 0;
 240                 do {
 241                         dep->busy_slot++;
 242                         /*
 243                          * Skip LINK TRB. We can't use req->trb and check for
 244                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 245                          * just completed (not the LINK TRB).
 246                          */
 247                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 248                                 DWC3_TRB_NUM- 1) &&
 249                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 250                                 dep->busy_slot++;
 251                 } while(++i < req->request.num_mapped_sgs);
 252                 req->queued = false;
 253         }
 254         list_del(&req->list);
 255         req->trb = NULL;
 256
 257         if (req->request.status == -EINPROGRESS)
 258                 req->request.status = status;
 259
 260         if (dwc->ep0_bounced && dep->number == 0)
 261                 dwc->ep0_bounced = false;
 262         else
 263                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 264                                 req->direction);
 265
 266         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 267                         req, dep->name, req->request.actual,
 268                         req->request.length, status);
 269
 270         spin_unlock(&dwc->lock);
 271         req->request.complete(&dep->endpoint, &req->request);
 272         spin_lock(&dwc->lock);
 273 }
 274
 275 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
 276 {
 277         switch (cmd) {
 278         case DWC3_DEPCMD_DEPSTARTCFG:
 279                 return "Start New Configuration";
 280         case DWC3_DEPCMD_ENDTRANSFER:
 281                 return "End Transfer";
 282         case DWC3_DEPCMD_UPDATETRANSFER:
 283                 return "Update Transfer";
 284         case DWC3_DEPCMD_STARTTRANSFER:
 285                 return "Start Transfer";
 286         case DWC3_DEPCMD_CLEARSTALL:
 287                 return "Clear Stall";
 288         case DWC3_DEPCMD_SETSTALL:
 289                 return "Set Stall";
 290         case DWC3_DEPCMD_GETEPSTATE:
 291                 return "Get Endpoint State";
 292         case DWC3_DEPCMD_SETTRANSFRESOURCE:
 293                 return "Set Endpoint Transfer Resource";
 294         case DWC3_DEPCMD_SETEPCONFIG:
 295                 return "Set Endpoint Configuration";
 296         default:
 297                 return "UNKNOWN command";
 298         }
 299 }
 300
 301 static const char *dwc3_gadget_generic_cmd_string(u8 cmd)
 302 {
 303         switch (cmd) {
 304         case DWC3_DGCMD_SET_LMP:
 305                 return "Set LMP";
 306         case DWC3_DGCMD_SET_PERIODIC_PAR:
 307                 return "Set Periodic Parameters";
 308         case DWC3_DGCMD_XMIT_FUNCTION:
 309                 return "Transmit Function Wake Device Notification";
 310         case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO:
 311                 return "Set Scratchpad Buffer Array Address Lo";
 312         case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI:
 313                 return "Set Scratchpad Buffer Array Address Hi";
 314         case DWC3_DGCMD_SELECTED_FIFO_FLUSH:
 315                 return "Selected FIFO Flush";
 316         case DWC3_DGCMD_ALL_FIFO_FLUSH:
 317                 return "All FIFO Flush";
 318         case DWC3_DGCMD_SET_ENDPOINT_NRDY:
 319                 return "Set Endpoint NRDY";
 320         case DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK:
 321                 return "Run SoC Bus Loopback Test";
 322         default:
 323                 return "UNKNOWN";
 324         }
 325 }
 326
 327 static const char *dwc3_gadget_link_string(enum dwc3_link_state link_state)
 328 {
 329         switch (link_state) {
 330         case DWC3_LINK_STATE_U0:
 331                 return "U0";
 332         case DWC3_LINK_STATE_U1:
 333                 return "U1";
 334         case DWC3_LINK_STATE_U2:
 335                 return "U2";
 336         case DWC3_LINK_STATE_U3:
 337                 return "U3";
 338         case DWC3_LINK_STATE_SS_DIS:
 339                 return "SS.Disabled";
 340         case DWC3_LINK_STATE_RX_DET:
 341                 return "RX.Detect";
 342         case DWC3_LINK_STATE_SS_INACT:
 343                 return "SS.Inactive";
 344         case DWC3_LINK_STATE_POLL:
 345                 return "Polling";
 346         case DWC3_LINK_STATE_RECOV:
 347                 return "Recovery";
 348         case DWC3_LINK_STATE_HRESET:
 349                 return "Hot Reset";
 350         case DWC3_LINK_STATE_CMPLY:
 351                 return "Compliance";
 352         case DWC3_LINK_STATE_LPBK:
 353                 return "Loopback";
 354         case DWC3_LINK_STATE_RESET:
 355                 return "Reset";
 356         case DWC3_LINK_STATE_RESUME:
 357                 return "Resume";
 358         default:
 359                 return "UNKNOWN link state\n";
 360         }
 361 }
 362
 363 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
 364 {
 365         u32             timeout = 500;
 366         u32             reg;
 367
 368         dev_vdbg(dwc->dev, "generic cmd '%s' [%d] param %08x\n",
 369                         dwc3_gadget_generic_cmd_string(cmd), cmd, param);
 370
 371         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 372         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 373
 374         do {
 375                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 376                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 377                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 378                                         DWC3_DGCMD_STATUS(reg));
 379                         return 0;
 380                 }
 381
 382                 /*
 383                  * We can't sleep here, because it's also called from
 384                  * interrupt context.
 385                  */
 386                 timeout--;
 387                 if (!timeout)
 388                         return -ETIMEDOUT;
 389                 udelay(1);
 390         } while (1);
 391 }
 392
 393 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 394                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 395 {
 396         struct dwc3_ep          *dep = dwc->eps[ep];
 397         u32                     timeout = 500;
 398         u32                     reg;
 399
 400         dev_vdbg(dwc->dev, "%s: cmd '%s' [%d] params %08x %08x %08x\n",
 401                         dep->name,
 402                         dwc3_gadget_ep_cmd_string(cmd), cmd, params->param0,
 403                         params->param1, params->param2);
 404
 405         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 406         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 407         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 408
 409         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 410         do {
 411                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 412                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 413                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 414                                         DWC3_DEPCMD_STATUS(reg));
 415                         return 0;
 416                 }
 417
 418                 /*
 419                  * We can't sleep here, because it is also called from
 420                  * interrupt context.
 421                  */
 422                 timeout--;
 423                 if (!timeout)
 424                         return -ETIMEDOUT;
 425
 426                 udelay(1);
 427         } while (1);
 428 }
 429
 430 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 431                 struct dwc3_trb *trb)
 432 {
 433         u32             offset = (char *) trb - (char *) dep->trb_pool;
 434
 435         return dep->trb_pool_dma + offset;
 436 }
 437
 438 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 439 {
 440         struct dwc3             *dwc = dep->dwc;
 441
 442         if (dep->trb_pool)
 443                 return 0;
 444
 445         if (dep->number == 0 || dep->number == 1)
 446                 return 0;
 447
 448         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 449                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 450                         &dep->trb_pool_dma, GFP_KERNEL);
 451         if (!dep->trb_pool) {
 452                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 453                                 dep->name);
 454                 return -ENOMEM;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 461 {
 462         struct dwc3             *dwc = dep->dwc;
 463
 464         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 465                         dep->trb_pool, dep->trb_pool_dma);
 466
 467         dep->trb_pool = NULL;
 468         dep->trb_pool_dma = 0;
 469 }
 470
 471 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 472 {
 473         struct dwc3_gadget_ep_cmd_params params;
 474         u32                     cmd;
 475
 476         memset(&params, 0x00, sizeof(params));
 477
 478         if (dep->number != 1) {
 479                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 480                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 481                 if (dep->number > 1) {
 482                         if (dwc->start_config_issued)
 483                                 return 0;
 484                         dwc->start_config_issued = true;
 485                         cmd |= DWC3_DEPCMD_PARAM(2);
 486                 }
 487
 488                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 489         }
 490
 491         return 0;
 492 }
 493
 494 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 495                 const struct usb_endpoint_descriptor *desc,
 496                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 497                 bool ignore, bool restore)
 498 {
 499         struct dwc3_gadget_ep_cmd_params params;
 500
 501         memset(&params, 0x00, sizeof(params));
 502
 503         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 504                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 505
 506         /* Burst size is only needed in SuperSpeed mode */
 507         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 508                 u32 burst = dep->endpoint.maxburst - 1;
 509
 510                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 511         }
 512
 513         if (ignore)
 514                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 515
 516         if (restore) {
 517                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 518                 params.param2 |= dep->saved_state;
 519         }
 520
 521         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 522                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 523
 524         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 525                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 526                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 527                 dep->stream_capable = true;
 528         }
 529
 530         if (!usb_endpoint_xfer_control(desc))
 531                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 532
 533         /*
 534          * We are doing 1:1 mapping for endpoints, meaning
 535          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 536          * so on. We consider the direction bit as part of the physical
 537          * endpoint number. So USB endpoint 0x81 is 0x03.
 538          */
 539         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 540
 541         /*
 542          * We must use the lower 16 TX FIFOs even though
 543          * HW might have more
 544          */
 545         if (dep->direction)
 546                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 547
 548         if (desc->bInterval) {
 549                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 550                 dep->interval = 1 << (desc->bInterval - 1);
 551         }
 552
 553         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 554                         DWC3_DEPCMD_SETEPCONFIG, &params);
 555 }
 556
 557 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 558 {
 559         struct dwc3_gadget_ep_cmd_params params;
 560
 561         memset(&params, 0x00, sizeof(params));
 562
 563         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 564
 565         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 566                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 567 }
 568
 569 /**
 570  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 571  * @dep: endpoint to be initialized
 572  * @desc: USB Endpoint Descriptor
 573  *
 574  * Caller should take care of locking
 575  */
 576 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 577                 const struct usb_endpoint_descriptor *desc,
 578                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 579                 bool ignore, bool restore)
 580 {
 581         struct dwc3             *dwc = dep->dwc;
 582         u32                     reg;
 583         int                     ret;
 584
 585         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 586
 587         if (!(dep->flags & DWC3_EP_ENABLED)) {
 588                 ret = dwc3_gadget_start_config(dwc, dep);
 589                 if (ret)
 590                         return ret;
 591         }
 592
 593         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 594                         restore);
 595         if (ret)
 596                 return ret;
 597
 598         if (!(dep->flags & DWC3_EP_ENABLED)) {
 599                 struct dwc3_trb *trb_st_hw;
 600                 struct dwc3_trb *trb_link;
 601
 602                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 603                 if (ret)
 604                         return ret;
 605
 606                 dep->endpoint.desc = desc;
 607                 dep->comp_desc = comp_desc;
 608                 dep->type = usb_endpoint_type(desc);
 609                 dep->flags |= DWC3_EP_ENABLED;
 610
 611                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 612                 reg |= DWC3_DALEPENA_EP(dep->number);
 613                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 614
 615                 if (!usb_endpoint_xfer_isoc(desc))
 616                         return 0;
 617
 618                 memset(&trb_link, 0, sizeof(trb_link));
 619
 620                 /* Link TRB for ISOC. The HWO bit is never reset */
 621                 trb_st_hw = &dep->trb_pool[0];
 622
 623                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 624
 625                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 626                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 627                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 628                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 629         }
 630
 631         return 0;
 632 }
 633
 634 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 635 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 636 {
 637         struct dwc3_request             *req;
 638
 639         if (!list_empty(&dep->req_queued)) {
 640                 dwc3_stop_active_transfer(dwc, dep->number, true);
 641
 642                 /* - giveback all requests to gadget driver */
 643                 while (!list_empty(&dep->req_queued)) {
 644                         req = next_request(&dep->req_queued);
 645
 646                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 647                 }
 648         }
 649
 650         while (!list_empty(&dep->request_list)) {
 651                 req = next_request(&dep->request_list);
 652
 653                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 654         }
 655 }
 656
 657 /**
 658  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 659  * @dep: the endpoint to disable
 660  *
 661  * This function also removes requests which are currently processed ny the
 662  * hardware and those which are not yet scheduled.
 663  * Caller should take care of locking.
 664  */
 665 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 666 {
 667         struct dwc3             *dwc = dep->dwc;
 668         u32                     reg;
 669
 670         dwc3_remove_requests(dwc, dep);
 671
 672         /* make sure HW endpoint isn't stalled */
 673         if (dep->flags & DWC3_EP_STALL)
 674                 __dwc3_gadget_ep_set_halt(dep, 0);
 675
 676         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 677         reg &= ~DWC3_DALEPENA_EP(dep->number);
 678         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 679
 680         dep->stream_capable = false;
 681         dep->endpoint.desc = NULL;
 682         dep->comp_desc = NULL;
 683         dep->type = 0;
 684         dep->flags = 0;
 685
 686         return 0;
 687 }
 688
 689 /* -------------------------------------------------------------------------- */
 690
 691 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 692                 const struct usb_endpoint_descriptor *desc)
 693 {
 694         return -EINVAL;
 695 }
 696
 697 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 698 {
 699         return -EINVAL;
 700 }
 701
 702 /* -------------------------------------------------------------------------- */
 703
 704 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 705                 const struct usb_endpoint_descriptor *desc)
 706 {
 707         struct dwc3_ep                  *dep;
 708         struct dwc3                     *dwc;
 709         unsigned long                   flags;
 710         int                             ret;
 711
 712         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 713                 pr_debug("dwc3: invalid parameters\n");
 714                 return -EINVAL;
 715         }
 716
 717         if (!desc->wMaxPacketSize) {
 718                 pr_debug("dwc3: missing wMaxPacketSize\n");
 719                 return -EINVAL;
 720         }
 721
 722         dep = to_dwc3_ep(ep);
 723         dwc = dep->dwc;
 724
 725         if (dep->flags & DWC3_EP_ENABLED) {
 726                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 727                                 dep->name);
 728                 return 0;
 729         }
 730
 731         switch (usb_endpoint_type(desc)) {
 732         case USB_ENDPOINT_XFER_CONTROL:
 733                 strlcat(dep->name, "-control", sizeof(dep->name));
 734                 break;
 735         case USB_ENDPOINT_XFER_ISOC:
 736                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 737                 break;
 738         case USB_ENDPOINT_XFER_BULK:
 739                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 740                 break;
 741         case USB_ENDPOINT_XFER_INT:
 742                 strlcat(dep->name, "-int", sizeof(dep->name));
 743                 break;
 744         default:
 745                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 746         }
 747
 748         spin_lock_irqsave(&dwc->lock, flags);
 749         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 750         spin_unlock_irqrestore(&dwc->lock, flags);
 751
 752         return ret;
 753 }
 754
 755 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 756 {
 757         struct dwc3_ep                  *dep;
 758         struct dwc3                     *dwc;
 759         unsigned long                   flags;
 760         int                             ret;
 761
 762         if (!ep) {
 763                 pr_debug("dwc3: invalid parameters\n");
 764                 return -EINVAL;
 765         }
 766
 767         dep = to_dwc3_ep(ep);
 768         dwc = dep->dwc;
 769
 770         if (!(dep->flags & DWC3_EP_ENABLED)) {
 771                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 772                                 dep->name);
 773                 return 0;
 774         }
 775
 776         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 777                         dep->number >> 1,
 778                         (dep->number & 1) ? "in" : "out");
 779
 780         spin_lock_irqsave(&dwc->lock, flags);
 781         ret = __dwc3_gadget_ep_disable(dep);
 782         spin_unlock_irqrestore(&dwc->lock, flags);
 783
 784         return ret;
 785 }
 786
 787 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 788         gfp_t gfp_flags)
 789 {
 790         struct dwc3_request             *req;
 791         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 792         struct dwc3                     *dwc = dep->dwc;
 793
 794         req = kzalloc(sizeof(*req), gfp_flags);
 795         if (!req) {
 796                 dev_err(dwc->dev, "not enough memory\n");
 797                 return NULL;
 798         }
 799
 800         req->epnum      = dep->number;
 801         req->dep        = dep;
 802
 803         return &req->request;
 804 }
 805
 806 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 807                 struct usb_request *request)
 808 {
 809         struct dwc3_request             *req = to_dwc3_request(request);
 810
 811         kfree(req);
 812 }
 813
 814 /**
 815  * dwc3_prepare_one_trb - setup one TRB from one request
 816  * @dep: endpoint for which this request is prepared
 817  * @req: dwc3_request pointer
 818  */
 819 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 820                 struct dwc3_request *req, dma_addr_t dma,
 821                 unsigned length, unsigned last, unsigned chain, unsigned node)
 822 {
 823         struct dwc3             *dwc = dep->dwc;
 824         struct dwc3_trb         *trb;
 825
 826         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 827                         dep->name, req, (unsigned long long) dma,
 828                         length, last ? " last" : "",
 829                         chain ? " chain" : "");
 830
 831
 832         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 833
 834         if (!req->trb) {
 835                 dwc3_gadget_move_request_queued(req);
 836                 req->trb = trb;
 837                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 838                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 839         }
 840
 841         dep->free_slot++;
 842         /* Skip the LINK-TRB on ISOC */
 843         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 844                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 845                 dep->free_slot++;
 846
 847         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 848         trb->bpl = lower_32_bits(dma);
 849         trb->bph = upper_32_bits(dma);
 850
 851         switch (usb_endpoint_type(dep->endpoint.desc)) {
 852         case USB_ENDPOINT_XFER_CONTROL:
 853                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 854                 break;
 855
 856         case USB_ENDPOINT_XFER_ISOC:
 857                 if (!node)
 858                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 859                 else
 860                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 861                 break;
 862
 863         case USB_ENDPOINT_XFER_BULK:
 864         case USB_ENDPOINT_XFER_INT:
 865                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 866                 break;
 867         default:
 868                 /*
 869                  * This is only possible with faulty memory because we
 870                  * checked it already :)
 871                  */
 872                 BUG();
 873         }
 874
 875         if (!req->request.no_interrupt && !chain)
 876                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 877
 878         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 879                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 880                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 881         } else if (last) {
 882                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 883         }
 884
 885         if (chain)
 886                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 887
 888         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 889                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 890
 891         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 892 }
 893
 894 /*
 895  * dwc3_prepare_trbs - setup TRBs from requests
 896  * @dep: endpoint for which requests are being prepared
 897  * @starting: true if the endpoint is idle and no requests are queued.
 898  *
 899  * The function goes through the requests list and sets up TRBs for the
 900  * transfers. The function returns once there are no more TRBs available or
 901  * it runs out of requests.
 902  */
 903 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 904 {
 905         struct dwc3_request     *req, *n;
 906         u32                     trbs_left;
 907         u32                     max;
 908         unsigned int            last_one = 0;
 909
 910         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 911
 912         /* the first request must not be queued */
 913         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 914
 915         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 916         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 917                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 918                 if (trbs_left > max)
 919                         trbs_left = max;
 920         }
 921
 922         /*
 923          * If busy & slot are equal than it is either full or empty. If we are
 924          * starting to process requests then we are empty. Otherwise we are
 925          * full and don't do anything
 926          */
 927         if (!trbs_left) {
 928                 if (!starting)
 929                         return;
 930                 trbs_left = DWC3_TRB_NUM;
 931                 /*
 932                  * In case we start from scratch, we queue the ISOC requests
 933                  * starting from slot 1. This is done because we use ring
 934                  * buffer and have no LST bit to stop us. Instead, we place
 935                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 936                  * after the first request so we start at slot 1 and have
 937                  * 7 requests proceed before we hit the first IOC.
 938                  * Other transfer types don't use the ring buffer and are
 939                  * processed from the first TRB until the last one. Since we
 940                  * don't wrap around we have to start at the beginning.
 941                  */
 942                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 943                         dep->busy_slot = 1;
 944                         dep->free_slot = 1;
 945                 } else {
 946                         dep->busy_slot = 0;
 947                         dep->free_slot = 0;
 948                 }
 949         }
 950
 951         /* The last TRB is a link TRB, not used for xfer */
 952         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 953                 return;
 954
 955         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 956                 unsigned        length;
 957                 dma_addr_t      dma;
 958                 last_one = false;
 959
 960                 if (req->request.num_mapped_sgs > 0) {
 961                         struct usb_request *request = &req->request;
 962                         struct scatterlist *sg = request->sg;
 963                         struct scatterlist *s;
 964                         int             i;
 965
 966                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 967                                 unsigned chain = true;
 968
 969                                 length = sg_dma_len(s);
 970                                 dma = sg_dma_address(s);
 971
 972                                 if (i == (request->num_mapped_sgs - 1) ||
 973                                                 sg_is_last(s)) {
 974                                         if (list_is_last(&req->list,
 975                                                         &dep->request_list))
 976                                                 last_one = true;
 977                                         chain = false;
 978                                 }
 979
 980                                 trbs_left--;
 981                                 if (!trbs_left)
 982                                         last_one = true;
 983
 984                                 if (last_one)
 985                                         chain = false;
 986
 987                                 dwc3_prepare_one_trb(dep, req, dma, length,
 988                                                 last_one, chain, i);
 989
 990                                 if (last_one)
 991                                         break;
 992                         }
 993                 } else {
 994                         dma = req->request.dma;
 995                         length = req->request.length;
 996                         trbs_left--;
 997
 998                         if (!trbs_left)
 999                                 last_one = 1;
1000
1001                         /* Is this the last request? */
1002                         if (list_is_last(&req->list, &dep->request_list))
1003                                 last_one = 1;
1004
1005                         dwc3_prepare_one_trb(dep, req, dma, length,
1006                                         last_one, false, 0);
1007
1008                         if (last_one)
1009                                 break;
1010                 }
1011         }
1012 }
1013
1014 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
1015                 int start_new)
1016 {
1017         struct dwc3_gadget_ep_cmd_params params;
1018         struct dwc3_request             *req;
1019         struct dwc3                     *dwc = dep->dwc;
1020         int                             ret;
1021         u32                             cmd;
1022
1023         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
1024                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
1025                 return -EBUSY;
1026         }
1027         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1028
1029         /*
1030          * If we are getting here after a short-out-packet we don't enqueue any
1031          * new requests as we try to set the IOC bit only on the last request.
1032          */
1033         if (start_new) {
1034                 if (list_empty(&dep->req_queued))
1035                         dwc3_prepare_trbs(dep, start_new);
1036
1037                 /* req points to the first request which will be sent */
1038                 req = next_request(&dep->req_queued);
1039         } else {
1040                 dwc3_prepare_trbs(dep, start_new);
1041
1042                 /*
1043                  * req points to the first request where HWO changed from 0 to 1
1044                  */
1045                 req = next_request(&dep->req_queued);
1046         }
1047         if (!req) {
1048                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1049                 return 0;
1050         }
1051
1052         memset(&params, 0, sizeof(params));
1053
1054         if (start_new) {
1055                 params.param0 = upper_32_bits(req->trb_dma);
1056                 params.param1 = lower_32_bits(req->trb_dma);
1057                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1058         } else {
1059                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1060         }
1061
1062         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1063         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1064         if (ret < 0) {
1065                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1066
1067                 /*
1068                  * FIXME we need to iterate over the list of requests
1069                  * here and stop, unmap, free and del each of the linked
1070                  * requests instead of what we do now.
1071                  */
1072                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1073                                 req->direction);
1074                 list_del(&req->list);
1075                 return ret;
1076         }
1077
1078         dep->flags |= DWC3_EP_BUSY;
1079
1080         if (start_new) {
1081                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1082                                 dep->number);
1083                 WARN_ON_ONCE(!dep->resource_index);
1084         }
1085
1086         return 0;
1087 }
1088
1089 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1090                 struct dwc3_ep *dep, u32 cur_uf)
1091 {
1092         u32 uf;
1093
1094         if (list_empty(&dep->request_list)) {
1095                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1096                         dep->name);
1097                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1098                 return;
1099         }
1100
1101         /* 4 micro frames in the future */
1102         uf = cur_uf + dep->interval * 4;
1103
1104         __dwc3_gadget_kick_transfer(dep, uf, 1);
1105 }
1106
1107 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1108                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1109 {
1110         u32 cur_uf, mask;
1111
1112         mask = ~(dep->interval - 1);
1113         cur_uf = event->parameters & mask;
1114
1115         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1116 }
1117
1118 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1119 {
1120         struct dwc3             *dwc = dep->dwc;
1121         int                     ret;
1122
1123         req->request.actual     = 0;
1124         req->request.status     = -EINPROGRESS;
1125         req->direction          = dep->direction;
1126         req->epnum              = dep->number;
1127
1128         /*
1129          * We only add to our list of requests now and
1130          * start consuming the list once we get XferNotReady
1131          * IRQ.
1132          *
1133          * That way, we avoid doing anything that we don't need
1134          * to do now and defer it until the point we receive a
1135          * particular token from the Host side.
1136          *
1137          * This will also avoid Host cancelling URBs due to too
1138          * many NAKs.
1139          */
1140         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1141                         dep->direction);
1142         if (ret)
1143                 return ret;
1144
1145         list_add_tail(&req->list, &dep->request_list);
1146
1147         /*
1148          * There are a few special cases:
1149          *
1150          * 1. XferNotReady with empty list of requests. We need to kick the
1151          *    transfer here in that situation, otherwise we will be NAKing
1152          *    forever. If we get XferNotReady before gadget driver has a
1153          *    chance to queue a request, we will ACK the IRQ but won't be
1154          *    able to receive the data until the next request is queued.
1155          *    The following code is handling exactly that.
1156          *
1157          */
1158         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1159                 /*
1160                  * If xfernotready is already elapsed and it is a case
1161                  * of isoc transfer, then issue END TRANSFER, so that
1162                  * you can receive xfernotready again and can have
1163                  * notion of current microframe.
1164                  */
1165                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1166                         if (list_empty(&dep->req_queued)) {
1167                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1168                                 dep->flags = DWC3_EP_ENABLED;
1169                         }
1170                         return 0;
1171                 }
1172
1173                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1174                 if (ret && ret != -EBUSY)
1175                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1176                                         dep->name);
1177                 return ret;
1178         }
1179
1180         /*
1181          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1182          *    kick the transfer here after queuing a request, otherwise the
1183          *    core may not see the modified TRB(s).
1184          */
1185         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1186                         (dep->flags & DWC3_EP_BUSY) &&
1187                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1188                 WARN_ON_ONCE(!dep->resource_index);
1189                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1190                                 false);
1191                 if (ret && ret != -EBUSY)
1192                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1193                                         dep->name);
1194                 return ret;
1195         }
1196
1197         /*
1198          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1199          * right away, otherwise host will not know we have streams to be
1200          * handled.
1201          */
1202         if (dep->stream_capable) {
1203                 int     ret;
1204
1205                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1206                 if (ret && ret != -EBUSY) {
1207                         struct dwc3     *dwc = dep->dwc;
1208
1209                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1210                                         dep->name);
1211                 }
1212         }
1213
1214         return 0;
1215 }
1216
1217 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1218         gfp_t gfp_flags)
1219 {
1220         struct dwc3_request             *req = to_dwc3_request(request);
1221         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1222         struct dwc3                     *dwc = dep->dwc;
1223
1224         unsigned long                   flags;
1225
1226         int                             ret;
1227
1228         spin_lock_irqsave(&dwc->lock, flags);
1229         if (!dep->endpoint.desc) {
1230                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1231                                 request, ep->name);
1232                 spin_unlock_irqrestore(&dwc->lock, flags);
1233                 return -ESHUTDOWN;
1234         }
1235
1236         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1237                         request, ep->name, request->length);
1238
1239         ret = __dwc3_gadget_ep_queue(dep, req);
1240         spin_unlock_irqrestore(&dwc->lock, flags);
1241
1242         return ret;
1243 }
1244
1245 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1246                 struct usb_request *request)
1247 {
1248         struct dwc3_request             *req = to_dwc3_request(request);
1249         struct dwc3_request             *r = NULL;
1250
1251         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1252         struct dwc3                     *dwc = dep->dwc;
1253
1254         unsigned long                   flags;
1255         int                             ret = 0;
1256
1257         spin_lock_irqsave(&dwc->lock, flags);
1258
1259         list_for_each_entry(r, &dep->request_list, list) {
1260                 if (r == req)
1261                         break;
1262         }
1263
1264         if (r != req) {
1265                 list_for_each_entry(r, &dep->req_queued, list) {
1266                         if (r == req)
1267                                 break;
1268                 }
1269                 if (r == req) {
1270                         /* wait until it is processed */
1271                         dwc3_stop_active_transfer(dwc, dep->number, true);
1272                         goto out1;
1273                 }
1274                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1275                                 request, ep->name);
1276                 ret = -EINVAL;
1277                 goto out0;
1278         }
1279
1280 out1:
1281         /* giveback the request */
1282         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1283
1284 out0:
1285         spin_unlock_irqrestore(&dwc->lock, flags);
1286
1287         return ret;
1288 }
1289
1290 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1291 {
1292         struct dwc3_gadget_ep_cmd_params        params;
1293         struct dwc3                             *dwc = dep->dwc;
1294         int                                     ret;
1295
1296         memset(&params, 0x00, sizeof(params));
1297
1298         if (value) {
1299                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1300                         DWC3_DEPCMD_SETSTALL, &params);
1301                 if (ret)
1302                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1303                                         dep->name);
1304                 else
1305                         dep->flags |= DWC3_EP_STALL;
1306         } else {
1307                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1308                         DWC3_DEPCMD_CLEARSTALL, &params);
1309                 if (ret)
1310                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1311                                         dep->name);
1312                 else
1313                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1314         }
1315
1316         return ret;
1317 }
1318
1319 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1320 {
1321         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1322         struct dwc3                     *dwc = dep->dwc;
1323
1324         unsigned long                   flags;
1325
1326         int                             ret;
1327
1328         spin_lock_irqsave(&dwc->lock, flags);
1329
1330         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1331                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1332                 ret = -EINVAL;
1333                 goto out;
1334         }
1335
1336         ret = __dwc3_gadget_ep_set_halt(dep, value);
1337 out:
1338         spin_unlock_irqrestore(&dwc->lock, flags);
1339
1340         return ret;
1341 }
1342
1343 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1344 {
1345         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1346         struct dwc3                     *dwc = dep->dwc;
1347         unsigned long                   flags;
1348
1349         spin_lock_irqsave(&dwc->lock, flags);
1350         dep->flags |= DWC3_EP_WEDGE;
1351         spin_unlock_irqrestore(&dwc->lock, flags);
1352
1353         if (dep->number == 0 || dep->number == 1)
1354                 return dwc3_gadget_ep0_set_halt(ep, 1);
1355         else
1356                 return dwc3_gadget_ep_set_halt(ep, 1);
1357 }
1358
1359 /* -------------------------------------------------------------------------- */
1360
1361 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1362         .bLength        = USB_DT_ENDPOINT_SIZE,
1363         .bDescriptorType = USB_DT_ENDPOINT,
1364         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1365 };
1366
1367 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1368         .enable         = dwc3_gadget_ep0_enable,
1369         .disable        = dwc3_gadget_ep0_disable,
1370         .alloc_request  = dwc3_gadget_ep_alloc_request,
1371         .free_request   = dwc3_gadget_ep_free_request,
1372         .queue          = dwc3_gadget_ep0_queue,
1373         .dequeue        = dwc3_gadget_ep_dequeue,
1374         .set_halt       = dwc3_gadget_ep0_set_halt,
1375         .set_wedge      = dwc3_gadget_ep_set_wedge,
1376 };
1377
1378 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1379         .enable         = dwc3_gadget_ep_enable,
1380         .disable        = dwc3_gadget_ep_disable,
1381         .alloc_request  = dwc3_gadget_ep_alloc_request,
1382         .free_request   = dwc3_gadget_ep_free_request,
1383         .queue          = dwc3_gadget_ep_queue,
1384         .dequeue        = dwc3_gadget_ep_dequeue,
1385         .set_halt       = dwc3_gadget_ep_set_halt,
1386         .set_wedge      = dwc3_gadget_ep_set_wedge,
1387 };
1388
1389 /* -------------------------------------------------------------------------- */
1390
1391 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1392 {
1393         struct dwc3             *dwc = gadget_to_dwc(g);
1394         u32                     reg;
1395
1396         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1397         return DWC3_DSTS_SOFFN(reg);
1398 }
1399
1400 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1401 {
1402         struct dwc3             *dwc = gadget_to_dwc(g);
1403
1404         unsigned long           timeout;
1405         unsigned long           flags;
1406
1407         u32                     reg;
1408
1409         int                     ret = 0;
1410
1411         u8                      link_state;
1412         u8                      speed;
1413
1414         spin_lock_irqsave(&dwc->lock, flags);
1415
1416         /*
1417          * According to the Databook Remote wakeup request should
1418          * be issued only when the device is in early suspend state.
1419          *
1420          * We can check that via USB Link State bits in DSTS register.
1421          */
1422         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1423
1424         speed = reg & DWC3_DSTS_CONNECTSPD;
1425         if (speed == DWC3_DSTS_SUPERSPEED) {
1426                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1427                 ret = -EINVAL;
1428                 goto out;
1429         }
1430
1431         link_state = DWC3_DSTS_USBLNKST(reg);
1432
1433         switch (link_state) {
1434         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1435         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1436                 break;
1437         default:
1438                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1439                                 link_state);
1440                 ret = -EINVAL;
1441                 goto out;
1442         }
1443
1444         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1445         if (ret < 0) {
1446                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1447                 goto out;
1448         }
1449
1450         /* Recent versions do this automatically */
1451         if (dwc->revision < DWC3_REVISION_194A) {
1452                 /* write zeroes to Link Change Request */
1453                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1454                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1455                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1456         }
1457
1458         /* poll until Link State changes to ON */
1459         timeout = jiffies + msecs_to_jiffies(100);
1460
1461         while (!time_after(jiffies, timeout)) {
1462                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1463
1464                 /* in HS, means ON */
1465                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1466                         break;
1467         }
1468
1469         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1470                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1471                 ret = -EINVAL;
1472         }
1473
1474 out:
1475         spin_unlock_irqrestore(&dwc->lock, flags);
1476
1477         return ret;
1478 }
1479
1480 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1481                 int is_selfpowered)
1482 {
1483         struct dwc3             *dwc = gadget_to_dwc(g);
1484         unsigned long           flags;
1485
1486         spin_lock_irqsave(&dwc->lock, flags);
1487         dwc->is_selfpowered = !!is_selfpowered;
1488         spin_unlock_irqrestore(&dwc->lock, flags);
1489
1490         return 0;
1491 }
1492
1493 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1494 {
1495         u32                     reg;
1496         u32                     timeout = 500;
1497
1498         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1499         if (is_on) {
1500                 if (dwc->revision <= DWC3_REVISION_187A) {
1501                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1502                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1503                 }
1504
1505                 if (dwc->revision >= DWC3_REVISION_194A)
1506                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1507                 reg |= DWC3_DCTL_RUN_STOP;
1508
1509                 if (dwc->has_hibernation)
1510                         reg |= DWC3_DCTL_KEEP_CONNECT;
1511
1512                 dwc->pullups_connected = true;
1513         } else {
1514                 reg &= ~DWC3_DCTL_RUN_STOP;
1515
1516                 if (dwc->has_hibernation && !suspend)
1517                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1518
1519                 dwc->pullups_connected = false;
1520         }
1521
1522         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1523
1524         do {
1525                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1526                 if (is_on) {
1527                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1528                                 break;
1529                 } else {
1530                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1531                                 break;
1532                 }
1533                 timeout--;
1534                 if (!timeout)
1535                         return -ETIMEDOUT;
1536                 udelay(1);
1537         } while (1);
1538
1539         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1540                         dwc->gadget_driver
1541                         ? dwc->gadget_driver->function : "no-function",
1542                         is_on ? "connect" : "disconnect");
1543
1544         return 0;
1545 }
1546
1547 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1548 {
1549         struct dwc3             *dwc = gadget_to_dwc(g);
1550         unsigned long           flags;
1551         int                     ret;
1552
1553         is_on = !!is_on;
1554
1555         spin_lock_irqsave(&dwc->lock, flags);
1556         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1557         spin_unlock_irqrestore(&dwc->lock, flags);
1558
1559         return ret;
1560 }
1561
1562 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1563 {
1564         u32                     reg;
1565
1566         /* Enable all but Start and End of Frame IRQs */
1567         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1568                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1569                         DWC3_DEVTEN_CMDCMPLTEN |
1570                         DWC3_DEVTEN_ERRTICERREN |
1571                         DWC3_DEVTEN_WKUPEVTEN |
1572                         DWC3_DEVTEN_ULSTCNGEN |
1573                         DWC3_DEVTEN_CONNECTDONEEN |
1574                         DWC3_DEVTEN_USBRSTEN |
1575                         DWC3_DEVTEN_DISCONNEVTEN);
1576
1577         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1578 }
1579
1580 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1581 {
1582         /* mask all interrupts */
1583         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1584 }
1585
1586 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1587 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1588
1589 static int dwc3_gadget_start(struct usb_gadget *g,
1590                 struct usb_gadget_driver *driver)
1591 {
1592         struct dwc3             *dwc = gadget_to_dwc(g);
1593         struct dwc3_ep          *dep;
1594         unsigned long           flags;
1595         int                     ret = 0;
1596         int                     irq;
1597         u32                     reg;
1598
1599         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1600         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1601                         IRQF_SHARED, "dwc3", dwc);
1602         if (ret) {
1603                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1604                                 irq, ret);
1605                 goto err0;
1606         }
1607
1608         spin_lock_irqsave(&dwc->lock, flags);
1609
1610         if (dwc->gadget_driver) {
1611                 dev_err(dwc->dev, "%s is already bound to %s\n",
1612                                 dwc->gadget.name,
1613                                 dwc->gadget_driver->driver.name);
1614                 ret = -EBUSY;
1615                 goto err1;
1616         }
1617
1618         dwc->gadget_driver      = driver;
1619
1620         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1621         reg &= ~(DWC3_DCFG_SPEED_MASK);
1622
1623         /**
1624          * WORKAROUND: DWC3 revision < 2.20a have an issue
1625          * which would cause metastability state on Run/Stop
1626          * bit if we try to force the IP to USB2-only mode.
1627          *
1628          * Because of that, we cannot configure the IP to any
1629          * speed other than the SuperSpeed
1630          *
1631          * Refers to:
1632          *
1633          * STAR#9000525659: Clock Domain Crossing on DCTL in
1634          * USB 2.0 Mode
1635          */
1636         if (dwc->revision < DWC3_REVISION_220A) {
1637                 reg |= DWC3_DCFG_SUPERSPEED;
1638         } else {
1639                 switch (dwc->maximum_speed) {
1640                 case USB_SPEED_LOW:
1641                         reg |= DWC3_DSTS_LOWSPEED;
1642                         break;
1643                 case USB_SPEED_FULL:
1644                         reg |= DWC3_DSTS_FULLSPEED1;
1645                         break;
1646                 case USB_SPEED_HIGH:
1647                         reg |= DWC3_DSTS_HIGHSPEED;
1648                         break;
1649                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1650                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1651                 default:
1652                         reg |= DWC3_DSTS_SUPERSPEED;
1653                 }
1654         }
1655         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1656
1657         dwc->start_config_issued = false;
1658
1659         /* Start with SuperSpeed Default */
1660         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1661
1662         dep = dwc->eps[0];
1663         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1664                         false);
1665         if (ret) {
1666                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1667                 goto err2;
1668         }
1669
1670         dep = dwc->eps[1];
1671         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1672                         false);
1673         if (ret) {
1674                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1675                 goto err3;
1676         }
1677
1678         /* begin to receive SETUP packets */
1679         dwc->ep0state = EP0_SETUP_PHASE;
1680         dwc3_ep0_out_start(dwc);
1681
1682         dwc3_gadget_enable_irq(dwc);
1683
1684         spin_unlock_irqrestore(&dwc->lock, flags);
1685
1686         return 0;
1687
1688 err3:
1689         __dwc3_gadget_ep_disable(dwc->eps[0]);
1690
1691 err2:
1692         dwc->gadget_driver = NULL;
1693
1694 err1:
1695         spin_unlock_irqrestore(&dwc->lock, flags);
1696
1697         free_irq(irq, dwc);
1698
1699 err0:
1700         return ret;
1701 }
1702
1703 static int dwc3_gadget_stop(struct usb_gadget *g,
1704                 struct usb_gadget_driver *driver)
1705 {
1706         struct dwc3             *dwc = gadget_to_dwc(g);
1707         unsigned long           flags;
1708         int                     irq;
1709
1710         spin_lock_irqsave(&dwc->lock, flags);
1711
1712         dwc3_gadget_disable_irq(dwc);
1713         __dwc3_gadget_ep_disable(dwc->eps[0]);
1714         __dwc3_gadget_ep_disable(dwc->eps[1]);
1715
1716         dwc->gadget_driver      = NULL;
1717
1718         spin_unlock_irqrestore(&dwc->lock, flags);
1719
1720         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1721         free_irq(irq, dwc);
1722
1723         return 0;
1724 }
1725
1726 static const struct usb_gadget_ops dwc3_gadget_ops = {
1727         .get_frame              = dwc3_gadget_get_frame,
1728         .wakeup                 = dwc3_gadget_wakeup,
1729         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1730         .pullup                 = dwc3_gadget_pullup,
1731         .udc_start              = dwc3_gadget_start,
1732         .udc_stop               = dwc3_gadget_stop,
1733 };
1734
1735 /* -------------------------------------------------------------------------- */
1736
1737 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1738                 u8 num, u32 direction)
1739 {
1740         struct dwc3_ep                  *dep;
1741         u8                              i;
1742
1743         for (i = 0; i < num; i++) {
1744                 u8 epnum = (i << 1) | (!!direction);
1745
1746                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1747                 if (!dep) {
1748                         dev_err(dwc->dev, "can't allocate endpoint %d\n",
1749                                         epnum);
1750                         return -ENOMEM;
1751                 }
1752
1753                 dep->dwc = dwc;
1754                 dep->number = epnum;
1755                 dep->direction = !!direction;
1756                 dwc->eps[epnum] = dep;
1757
1758                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1759                                 (epnum & 1) ? "in" : "out");
1760
1761                 dep->endpoint.name = dep->name;
1762
1763                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1764
1765                 if (epnum == 0 || epnum == 1) {
1766                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1767                         dep->endpoint.maxburst = 1;
1768                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1769                         if (!epnum)
1770                                 dwc->gadget.ep0 = &dep->endpoint;
1771                 } else {
1772                         int             ret;
1773
1774                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1775                         dep->endpoint.max_streams = 15;
1776                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1777                         list_add_tail(&dep->endpoint.ep_list,
1778                                         &dwc->gadget.ep_list);
1779
1780                         ret = dwc3_alloc_trb_pool(dep);
1781                         if (ret)
1782                                 return ret;
1783                 }
1784
1785                 INIT_LIST_HEAD(&dep->request_list);
1786                 INIT_LIST_HEAD(&dep->req_queued);
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1793 {
1794         int                             ret;
1795
1796         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1797
1798         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1799         if (ret < 0) {
1800                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1801                 return ret;
1802         }
1803
1804         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1805         if (ret < 0) {
1806                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1807                 return ret;
1808         }
1809
1810         return 0;
1811 }
1812
1813 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1814 {
1815         struct dwc3_ep                  *dep;
1816         u8                              epnum;
1817
1818         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1819                 dep = dwc->eps[epnum];
1820                 if (!dep)
1821                         continue;
1822                 /*
1823                  * Physical endpoints 0 and 1 are special; they form the
1824                  * bi-directional USB endpoint 0.
1825                  *
1826                  * For those two physical endpoints, we don't allocate a TRB
1827                  * pool nor do we add them the endpoints list. Due to that, we
1828                  * shouldn't do these two operations otherwise we would end up
1829                  * with all sorts of bugs when removing dwc3.ko.
1830                  */
1831                 if (epnum != 0 && epnum != 1) {
1832                         dwc3_free_trb_pool(dep);
1833                         list_del(&dep->endpoint.ep_list);
1834                 }
1835
1836                 kfree(dep);
1837         }
1838 }
1839
1840 /* -------------------------------------------------------------------------- */
1841
1842 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1843                 struct dwc3_request *req, struct dwc3_trb *trb,
1844                 const struct dwc3_event_depevt *event, int status)
1845 {
1846         unsigned int            count;
1847         unsigned int            s_pkt = 0;
1848         unsigned int            trb_status;
1849
1850         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1851                 /*
1852                  * We continue despite the error. There is not much we
1853                  * can do. If we don't clean it up we loop forever. If
1854                  * we skip the TRB then it gets overwritten after a
1855                  * while since we use them in a ring buffer. A BUG()
1856                  * would help. Lets hope that if this occurs, someone
1857                  * fixes the root cause instead of looking away :)
1858                  */
1859                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1860                                 dep->name, trb);
1861         count = trb->size & DWC3_TRB_SIZE_MASK;
1862
1863         if (dep->direction) {
1864                 if (count) {
1865                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1866                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1867                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1868                                                 dep->name);
1869                                 /*
1870                                  * If missed isoc occurred and there is
1871                                  * no request queued then issue END
1872                                  * TRANSFER, so that core generates
1873                                  * next xfernotready and we will issue
1874                                  * a fresh START TRANSFER.
1875                                  * If there are still queued request
1876                                  * then wait, do not issue either END
1877                                  * or UPDATE TRANSFER, just attach next
1878                                  * request in request_list during
1879                                  * giveback.If any future queued request
1880                                  * is successfully transferred then we
1881                                  * will issue UPDATE TRANSFER for all
1882                                  * request in the request_list.
1883                                  */
1884                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1885                         } else {
1886                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1887                                                 dep->name);
1888                                 status = -ECONNRESET;
1889                         }
1890                 } else {
1891                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1892                 }
1893         } else {
1894                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1895                         s_pkt = 1;
1896         }
1897
1898         /*
1899          * We assume here we will always receive the entire data block
1900          * which we should receive. Meaning, if we program RX to
1901          * receive 4K but we receive only 2K, we assume that's all we
1902          * should receive and we simply bounce the request back to the
1903          * gadget driver for further processing.
1904          */
1905         req->request.actual += req->request.length - count;
1906         if (s_pkt)
1907                 return 1;
1908         if ((event->status & DEPEVT_STATUS_LST) &&
1909                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1910                                 DWC3_TRB_CTRL_HWO)))
1911                 return 1;
1912         if ((event->status & DEPEVT_STATUS_IOC) &&
1913                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1914                 return 1;
1915         return 0;
1916 }
1917
1918 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1919                 const struct dwc3_event_depevt *event, int status)
1920 {
1921         struct dwc3_request     *req;
1922         struct dwc3_trb         *trb;
1923         unsigned int            slot;
1924         unsigned int            i;
1925         int                     ret;
1926
1927         do {
1928                 req = next_request(&dep->req_queued);
1929                 if (!req) {
1930                         WARN_ON_ONCE(1);
1931                         return 1;
1932                 }
1933                 i = 0;
1934                 do {
1935                         slot = req->start_slot + i;
1936                         if ((slot == DWC3_TRB_NUM - 1) &&
1937                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1938                                 slot++;
1939                         slot %= DWC3_TRB_NUM;
1940                         trb = &dep->trb_pool[slot];
1941
1942                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1943                                         event, status);
1944                         if (ret)
1945                                 break;
1946                 }while (++i < req->request.num_mapped_sgs);
1947
1948                 dwc3_gadget_giveback(dep, req, status);
1949
1950                 if (ret)
1951                         break;
1952         } while (1);
1953
1954         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1955                         list_empty(&dep->req_queued)) {
1956                 if (list_empty(&dep->request_list)) {
1957                         /*
1958                          * If there is no entry in request list then do
1959                          * not issue END TRANSFER now. Just set PENDING
1960                          * flag, so that END TRANSFER is issued when an
1961                          * entry is added into request list.
1962                          */
1963                         dep->flags = DWC3_EP_PENDING_REQUEST;
1964                 } else {
1965                         dwc3_stop_active_transfer(dwc, dep->number, true);
1966                         dep->flags = DWC3_EP_ENABLED;
1967                 }
1968                 return 1;
1969         }
1970
1971         return 1;
1972 }
1973
1974 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1975                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1976 {
1977         unsigned                status = 0;
1978         int                     clean_busy;
1979
1980         if (event->status & DEPEVT_STATUS_BUSERR)
1981                 status = -ECONNRESET;
1982
1983         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1984         if (clean_busy)
1985                 dep->flags &= ~DWC3_EP_BUSY;
1986
1987         /*
1988          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1989          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1990          */
1991         if (dwc->revision < DWC3_REVISION_183A) {
1992                 u32             reg;
1993                 int             i;
1994
1995                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1996                         dep = dwc->eps[i];
1997
1998                         if (!(dep->flags & DWC3_EP_ENABLED))
1999                                 continue;
2000
2001                         if (!list_empty(&dep->req_queued))
2002                                 return;
2003                 }
2004
2005                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2006                 reg |= dwc->u1u2;
2007                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2008
2009                 dwc->u1u2 = 0;
2010         }
2011 }
2012
2013 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2014                 const struct dwc3_event_depevt *event)
2015 {
2016         struct dwc3_ep          *dep;
2017         u8                      epnum = event->endpoint_number;
2018
2019         dep = dwc->eps[epnum];
2020
2021         if (!(dep->flags & DWC3_EP_ENABLED))
2022                 return;
2023
2024         dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
2025                         dwc3_ep_event_string(event->endpoint_event));
2026
2027         if (epnum == 0 || epnum == 1) {
2028                 dwc3_ep0_interrupt(dwc, event);
2029                 return;
2030         }
2031
2032         switch (event->endpoint_event) {
2033         case DWC3_DEPEVT_XFERCOMPLETE:
2034                 dep->resource_index = 0;
2035
2036                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2037                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
2038                                         dep->name);
2039                         return;
2040                 }
2041
2042                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2043                 break;
2044         case DWC3_DEPEVT_XFERINPROGRESS:
2045                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2046                 break;
2047         case DWC3_DEPEVT_XFERNOTREADY:
2048                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2049                         dwc3_gadget_start_isoc(dwc, dep, event);
2050                 } else {
2051                         int ret;
2052
2053                         dev_vdbg(dwc->dev, "%s: reason %s\n",
2054                                         dep->name, event->status &
2055                                         DEPEVT_STATUS_TRANSFER_ACTIVE
2056                                         ? "Transfer Active"
2057                                         : "Transfer Not Active");
2058
2059                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
2060                         if (!ret || ret == -EBUSY)
2061                                 return;
2062
2063                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
2064                                         dep->name);
2065                 }
2066
2067                 break;
2068         case DWC3_DEPEVT_STREAMEVT:
2069                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2070                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2071                                         dep->name);
2072                         return;
2073                 }
2074
2075                 switch (event->status) {
2076                 case DEPEVT_STREAMEVT_FOUND:
2077                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
2078                                         event->parameters);
2079
2080                         break;
2081                 case DEPEVT_STREAMEVT_NOTFOUND:
2082                         /* FALLTHROUGH */
2083                 default:
2084                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2085                 }
2086                 break;
2087         case DWC3_DEPEVT_RXTXFIFOEVT:
2088                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2089                 break;
2090         case DWC3_DEPEVT_EPCMDCMPLT:
2091                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
2092                 break;
2093         }
2094 }
2095
2096 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2097 {
2098         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2099                 spin_unlock(&dwc->lock);
2100                 dwc->gadget_driver->disconnect(&dwc->gadget);
2101                 spin_lock(&dwc->lock);
2102         }
2103 }
2104
2105 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2106 {
2107         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2108                 spin_unlock(&dwc->lock);
2109                 dwc->gadget_driver->suspend(&dwc->gadget);
2110                 spin_lock(&dwc->lock);
2111         }
2112 }
2113
2114 static void dwc3_resume_gadget(struct dwc3 *dwc)
2115 {
2116         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2117                 spin_unlock(&dwc->lock);
2118                 dwc->gadget_driver->resume(&dwc->gadget);
2119                 spin_lock(&dwc->lock);
2120         }
2121 }
2122
2123 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2124 {
2125         struct dwc3_ep *dep;
2126         struct dwc3_gadget_ep_cmd_params params;
2127         u32 cmd;
2128         int ret;
2129
2130         dep = dwc->eps[epnum];
2131
2132         if (!dep->resource_index)
2133                 return;
2134
2135         /*
2136          * NOTICE: We are violating what the Databook says about the
2137          * EndTransfer command. Ideally we would _always_ wait for the
2138          * EndTransfer Command Completion IRQ, but that's causing too
2139          * much trouble synchronizing between us and gadget driver.
2140          *
2141          * We have discussed this with the IP Provider and it was
2142          * suggested to giveback all requests here, but give HW some
2143          * extra time to synchronize with the interconnect. We're using
2144          * an arbitraty 100us delay for that.
2145          *
2146          * Note also that a similar handling was tested by Synopsys
2147          * (thanks a lot Paul) and nothing bad has come out of it.
2148          * In short, what we're doing is:
2149          *
2150          * - Issue EndTransfer WITH CMDIOC bit set
2151          * - Wait 100us
2152          */
2153
2154         cmd = DWC3_DEPCMD_ENDTRANSFER;
2155         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2156         cmd |= DWC3_DEPCMD_CMDIOC;
2157         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2158         memset(&params, 0, sizeof(params));
2159         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2160         WARN_ON_ONCE(ret);
2161         dep->resource_index = 0;
2162         dep->flags &= ~DWC3_EP_BUSY;
2163         udelay(100);
2164 }
2165
2166 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2167 {
2168         u32 epnum;
2169
2170         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2171                 struct dwc3_ep *dep;
2172
2173                 dep = dwc->eps[epnum];
2174                 if (!dep)
2175                         continue;
2176
2177                 if (!(dep->flags & DWC3_EP_ENABLED))
2178                         continue;
2179
2180                 dwc3_remove_requests(dwc, dep);
2181         }
2182 }
2183
2184 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2185 {
2186         u32 epnum;
2187
2188         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2189                 struct dwc3_ep *dep;
2190                 struct dwc3_gadget_ep_cmd_params params;
2191                 int ret;
2192
2193                 dep = dwc->eps[epnum];
2194                 if (!dep)
2195                         continue;
2196
2197                 if (!(dep->flags & DWC3_EP_STALL))
2198                         continue;
2199
2200                 dep->flags &= ~DWC3_EP_STALL;
2201
2202                 memset(&params, 0, sizeof(params));
2203                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2204                                 DWC3_DEPCMD_CLEARSTALL, &params);
2205                 WARN_ON_ONCE(ret);
2206         }
2207 }
2208
2209 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2210 {
2211         int                     reg;
2212
2213         dev_vdbg(dwc->dev, "%s\n", __func__);
2214
2215         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2216         reg &= ~DWC3_DCTL_INITU1ENA;
2217         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2218
2219         reg &= ~DWC3_DCTL_INITU2ENA;
2220         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2221
2222         dwc3_disconnect_gadget(dwc);
2223         dwc->start_config_issued = false;
2224
2225         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2226         dwc->setup_packet_pending = false;
2227 }
2228
2229 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2230 {
2231         u32                     reg;
2232
2233         dev_vdbg(dwc->dev, "%s\n", __func__);
2234
2235         /*
2236          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2237          * would cause a missing Disconnect Event if there's a
2238          * pending Setup Packet in the FIFO.
2239          *
2240          * There's no suggested workaround on the official Bug
2241          * report, which states that "unless the driver/application
2242          * is doing any special handling of a disconnect event,
2243          * there is no functional issue".
2244          *
2245          * Unfortunately, it turns out that we _do_ some special
2246          * handling of a disconnect event, namely complete all
2247          * pending transfers, notify gadget driver of the
2248          * disconnection, and so on.
2249          *
2250          * Our suggested workaround is to follow the Disconnect
2251          * Event steps here, instead, based on a setup_packet_pending
2252          * flag. Such flag gets set whenever we have a XferNotReady
2253          * event on EP0 and gets cleared on XferComplete for the
2254          * same endpoint.
2255          *
2256          * Refers to:
2257          *
2258          * STAR#9000466709: RTL: Device : Disconnect event not
2259          * generated if setup packet pending in FIFO
2260          */
2261         if (dwc->revision < DWC3_REVISION_188A) {
2262                 if (dwc->setup_packet_pending)
2263                         dwc3_gadget_disconnect_interrupt(dwc);
2264         }
2265
2266         /* after reset -> Default State */
2267         usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2268
2269         if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2270                 dwc3_disconnect_gadget(dwc);
2271
2272         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2273         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2274         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2275         dwc->test_mode = false;
2276
2277         dwc3_stop_active_transfers(dwc);
2278         dwc3_clear_stall_all_ep(dwc);
2279         dwc->start_config_issued = false;
2280
2281         /* Reset device address to zero */
2282         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2283         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2284         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2285 }
2286
2287 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2288 {
2289         u32 reg;
2290         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2291
2292         /*
2293          * We change the clock only at SS but I dunno why I would want to do
2294          * this. Maybe it becomes part of the power saving plan.
2295          */
2296
2297         if (speed != DWC3_DSTS_SUPERSPEED)
2298                 return;
2299
2300         /*
2301          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2302          * each time on Connect Done.
2303          */
2304         if (!usb30_clock)
2305                 return;
2306
2307         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2308         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2309         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2310 }
2311
2312 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2313 {
2314         struct dwc3_ep          *dep;
2315         int                     ret;
2316         u32                     reg;
2317         u8                      speed;
2318
2319         dev_vdbg(dwc->dev, "%s\n", __func__);
2320
2321         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2322         speed = reg & DWC3_DSTS_CONNECTSPD;
2323         dwc->speed = speed;
2324
2325         dwc3_update_ram_clk_sel(dwc, speed);
2326
2327         switch (speed) {
2328         case DWC3_DCFG_SUPERSPEED:
2329                 /*
2330                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2331                  * would cause a missing USB3 Reset event.
2332                  *
2333                  * In such situations, we should force a USB3 Reset
2334                  * event by calling our dwc3_gadget_reset_interrupt()
2335                  * routine.
2336                  *
2337                  * Refers to:
2338                  *
2339                  * STAR#9000483510: RTL: SS : USB3 reset event may
2340                  * not be generated always when the link enters poll
2341                  */
2342                 if (dwc->revision < DWC3_REVISION_190A)
2343                         dwc3_gadget_reset_interrupt(dwc);
2344
2345                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2346                 dwc->gadget.ep0->maxpacket = 512;
2347                 dwc->gadget.speed = USB_SPEED_SUPER;
2348                 break;
2349         case DWC3_DCFG_HIGHSPEED:
2350                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2351                 dwc->gadget.ep0->maxpacket = 64;
2352                 dwc->gadget.speed = USB_SPEED_HIGH;
2353                 break;
2354         case DWC3_DCFG_FULLSPEED2:
2355         case DWC3_DCFG_FULLSPEED1:
2356                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2357                 dwc->gadget.ep0->maxpacket = 64;
2358                 dwc->gadget.speed = USB_SPEED_FULL;
2359                 break;
2360         case DWC3_DCFG_LOWSPEED:
2361                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2362                 dwc->gadget.ep0->maxpacket = 8;
2363                 dwc->gadget.speed = USB_SPEED_LOW;
2364                 break;
2365         }
2366
2367         /* Enable USB2 LPM Capability */
2368
2369         if ((dwc->revision > DWC3_REVISION_194A)
2370                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2371                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2372                 reg |= DWC3_DCFG_LPM_CAP;
2373                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2374
2375                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2376                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2377
2378                 /*
2379                  * TODO: This should be configurable. For now using
2380                  * maximum allowed HIRD threshold value of 0b1100
2381                  */
2382                 reg |= DWC3_DCTL_HIRD_THRES(12);
2383
2384                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2385         } else {
2386                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2387                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2388                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2389         }
2390
2391         dep = dwc->eps[0];
2392         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2393                         false);
2394         if (ret) {
2395                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2396                 return;
2397         }
2398
2399         dep = dwc->eps[1];
2400         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2401                         false);
2402         if (ret) {
2403                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2404                 return;
2405         }
2406
2407         /*
2408          * Configure PHY via GUSB3PIPECTLn if required.
2409          *
2410          * Update GTXFIFOSIZn
2411          *
2412          * In both cases reset values should be sufficient.
2413          */
2414 }
2415
2416 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2417 {
2418         dev_vdbg(dwc->dev, "%s\n", __func__);
2419
2420         /*
2421          * TODO take core out of low power mode when that's
2422          * implemented.
2423          */
2424
2425         dwc->gadget_driver->resume(&dwc->gadget);
2426 }
2427
2428 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2429                 unsigned int evtinfo)
2430 {
2431         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2432         unsigned int            pwropt;
2433
2434         /*
2435          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2436          * Hibernation mode enabled which would show up when device detects
2437          * host-initiated U3 exit.
2438          *
2439          * In that case, device will generate a Link State Change Interrupt
2440          * from U3 to RESUME which is only necessary if Hibernation is
2441          * configured in.
2442          *
2443          * There are no functional changes due to such spurious event and we
2444          * just need to ignore it.
2445          *
2446          * Refers to:
2447          *
2448          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2449          * operational mode
2450          */
2451         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2452         if ((dwc->revision < DWC3_REVISION_250A) &&
2453                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2454                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2455                                 (next == DWC3_LINK_STATE_RESUME)) {
2456                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2457                         return;
2458                 }
2459         }
2460
2461         /*
2462          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2463          * on the link partner, the USB session might do multiple entry/exit
2464          * of low power states before a transfer takes place.
2465          *
2466          * Due to this problem, we might experience lower throughput. The
2467          * suggested workaround is to disable DCTL[12:9] bits if we're
2468          * transitioning from U1/U2 to U0 and enable those bits again
2469          * after a transfer completes and there are no pending transfers
2470          * on any of the enabled endpoints.
2471          *
2472          * This is the first half of that workaround.
2473          *
2474          * Refers to:
2475          *
2476          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2477          * core send LGO_Ux entering U0
2478          */
2479         if (dwc->revision < DWC3_REVISION_183A) {
2480                 if (next == DWC3_LINK_STATE_U0) {
2481                         u32     u1u2;
2482                         u32     reg;
2483
2484                         switch (dwc->link_state) {
2485                         case DWC3_LINK_STATE_U1:
2486                         case DWC3_LINK_STATE_U2:
2487                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2488                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2489                                                 | DWC3_DCTL_ACCEPTU2ENA
2490                                                 | DWC3_DCTL_INITU1ENA
2491                                                 | DWC3_DCTL_ACCEPTU1ENA);
2492
2493                                 if (!dwc->u1u2)
2494                                         dwc->u1u2 = reg & u1u2;
2495
2496                                 reg &= ~u1u2;
2497
2498                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2499                                 break;
2500                         default:
2501                                 /* do nothing */
2502                                 break;
2503                         }
2504                 }
2505         }
2506
2507         switch (next) {
2508         case DWC3_LINK_STATE_U1:
2509                 if (dwc->speed == USB_SPEED_SUPER)
2510                         dwc3_suspend_gadget(dwc);
2511                 break;
2512         case DWC3_LINK_STATE_U2:
2513         case DWC3_LINK_STATE_U3:
2514                 dwc3_suspend_gadget(dwc);
2515                 break;
2516         case DWC3_LINK_STATE_RESUME:
2517                 dwc3_resume_gadget(dwc);
2518                 break;
2519         default:
2520                 /* do nothing */
2521                 break;
2522         }
2523
2524         dev_vdbg(dwc->dev, "link change: %s [%d] -> %s [%d]\n",
2525                         dwc3_gadget_link_string(dwc->link_state),
2526                         dwc->link_state, dwc3_gadget_link_string(next), next);
2527
2528         dwc->link_state = next;
2529 }
2530
2531 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2532                 unsigned int evtinfo)
2533 {
2534         unsigned int is_ss = evtinfo & BIT(4);
2535
2536         /**
2537          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2538          * have a known issue which can cause USB CV TD.9.23 to fail
2539          * randomly.
2540          *
2541          * Because of this issue, core could generate bogus hibernation
2542          * events which SW needs to ignore.
2543          *
2544          * Refers to:
2545          *
2546          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2547          * Device Fallback from SuperSpeed
2548          */
2549         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2550                 return;
2551
2552         /* enter hibernation here */
2553 }
2554
2555 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2556                 const struct dwc3_event_devt *event)
2557 {
2558         switch (event->type) {
2559         case DWC3_DEVICE_EVENT_DISCONNECT:
2560                 dwc3_gadget_disconnect_interrupt(dwc);
2561                 break;
2562         case DWC3_DEVICE_EVENT_RESET:
2563                 dwc3_gadget_reset_interrupt(dwc);
2564                 break;
2565         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2566                 dwc3_gadget_conndone_interrupt(dwc);
2567                 break;
2568         case DWC3_DEVICE_EVENT_WAKEUP:
2569                 dwc3_gadget_wakeup_interrupt(dwc);
2570                 break;
2571         case DWC3_DEVICE_EVENT_HIBER_REQ:
2572                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2573                                         "unexpected hibernation event\n"))
2574                         break;
2575
2576                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2577                 break;
2578         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2579                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2580                 break;
2581         case DWC3_DEVICE_EVENT_EOPF:
2582                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2583                 break;
2584         case DWC3_DEVICE_EVENT_SOF:
2585                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2586                 break;
2587         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2588                 dev_vdbg(dwc->dev, "Erratic Error\n");
2589                 break;
2590         case DWC3_DEVICE_EVENT_CMD_CMPL:
2591                 dev_vdbg(dwc->dev, "Command Complete\n");
2592                 break;
2593         case DWC3_DEVICE_EVENT_OVERFLOW:
2594                 dev_vdbg(dwc->dev, "Overflow\n");
2595                 break;
2596         default:
2597                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2598         }
2599 }
2600
2601 static void dwc3_process_event_entry(struct dwc3 *dwc,
2602                 const union dwc3_event *event)
2603 {
2604         /* Endpoint IRQ, handle it and return early */
2605         if (event->type.is_devspec == 0) {
2606                 /* depevt */
2607                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2608         }
2609
2610         switch (event->type.type) {
2611         case DWC3_EVENT_TYPE_DEV:
2612                 dwc3_gadget_interrupt(dwc, &event->devt);
2613                 break;
2614         /* REVISIT what to do with Carkit and I2C events ? */
2615         default:
2616                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2617         }
2618 }
2619
2620 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2621 {
2622         struct dwc3_event_buffer *evt;
2623         irqreturn_t ret = IRQ_NONE;
2624         int left;
2625         u32 reg;
2626
2627         evt = dwc->ev_buffs[buf];
2628         left = evt->count;
2629
2630         if (!(evt->flags & DWC3_EVENT_PENDING))
2631                 return IRQ_NONE;
2632
2633         while (left > 0) {
2634                 union dwc3_event event;
2635
2636                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2637
2638                 dwc3_process_event_entry(dwc, &event);
2639
2640                 /*
2641                  * FIXME we wrap around correctly to the next entry as
2642                  * almost all entries are 4 bytes in size. There is one
2643                  * entry which has 12 bytes which is a regular entry
2644                  * followed by 8 bytes data. ATM I don't know how
2645                  * things are organized if we get next to the a
2646                  * boundary so I worry about that once we try to handle
2647                  * that.
2648                  */
2649                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2650                 left -= 4;
2651
2652                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2653         }
2654
2655         evt->count = 0;
2656         evt->flags &= ~DWC3_EVENT_PENDING;
2657         ret = IRQ_HANDLED;
2658
2659         /* Unmask interrupt */
2660         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2661         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2662         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2663
2664         return ret;
2665 }
2666
2667 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2668 {
2669         struct dwc3 *dwc = _dwc;
2670         unsigned long flags;
2671         irqreturn_t ret = IRQ_NONE;
2672         int i;
2673
2674         spin_lock_irqsave(&dwc->lock, flags);
2675
2676         for (i = 0; i < dwc->num_event_buffers; i++)
2677                 ret |= dwc3_process_event_buf(dwc, i);
2678
2679         spin_unlock_irqrestore(&dwc->lock, flags);
2680
2681         return ret;
2682 }
2683
2684 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2685 {
2686         struct dwc3_event_buffer *evt;
2687         u32 count;
2688         u32 reg;
2689
2690         evt = dwc->ev_buffs[buf];
2691
2692         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2693         count &= DWC3_GEVNTCOUNT_MASK;
2694         if (!count)
2695                 return IRQ_NONE;
2696
2697         evt->count = count;
2698         evt->flags |= DWC3_EVENT_PENDING;
2699
2700         /* Mask interrupt */
2701         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2702         reg |= DWC3_GEVNTSIZ_INTMASK;
2703         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2704
2705         return IRQ_WAKE_THREAD;
2706 }
2707
2708 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2709 {
2710         struct dwc3                     *dwc = _dwc;
2711         int                             i;
2712         irqreturn_t                     ret = IRQ_NONE;
2713
2714         spin_lock(&dwc->lock);
2715
2716         for (i = 0; i < dwc->num_event_buffers; i++) {
2717                 irqreturn_t status;
2718
2719                 status = dwc3_check_event_buf(dwc, i);
2720                 if (status == IRQ_WAKE_THREAD)
2721                         ret = status;
2722         }
2723
2724         spin_unlock(&dwc->lock);
2725
2726         return ret;
2727 }
2728
2729 /**
2730  * dwc3_gadget_init - Initializes gadget related registers
2731  * @dwc: pointer to our controller context structure
2732  *
2733  * Returns 0 on success otherwise negative errno.
2734  */
2735 int dwc3_gadget_init(struct dwc3 *dwc)
2736 {
2737         int                                     ret;
2738
2739         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2740                         &dwc->ctrl_req_addr, GFP_KERNEL);
2741         if (!dwc->ctrl_req) {
2742                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2743                 ret = -ENOMEM;
2744                 goto err0;
2745         }
2746
2747         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2748                         &dwc->ep0_trb_addr, GFP_KERNEL);
2749         if (!dwc->ep0_trb) {
2750                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2751                 ret = -ENOMEM;
2752                 goto err1;
2753         }
2754
2755         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2756         if (!dwc->setup_buf) {
2757                 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2758                 ret = -ENOMEM;
2759                 goto err2;
2760         }
2761
2762         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2763                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2764                         GFP_KERNEL);
2765         if (!dwc->ep0_bounce) {
2766                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2767                 ret = -ENOMEM;
2768                 goto err3;
2769         }
2770
2771         dwc->gadget.ops                 = &dwc3_gadget_ops;
2772         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2773         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2774         dwc->gadget.sg_supported        = true;
2775         dwc->gadget.name                = "dwc3-gadget";
2776
2777         /*
2778          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2779          * on ep out.
2780          */
2781         dwc->gadget.quirk_ep_out_aligned_size = true;
2782
2783         /*
2784          * REVISIT: Here we should clear all pending IRQs to be
2785          * sure we're starting from a well known location.
2786          */
2787
2788         ret = dwc3_gadget_init_endpoints(dwc);
2789         if (ret)
2790                 goto err4;
2791
2792         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2793         if (ret) {
2794                 dev_err(dwc->dev, "failed to register udc\n");
2795                 goto err4;
2796         }
2797
2798         return 0;
2799
2800 err4:
2801         dwc3_gadget_free_endpoints(dwc);
2802         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2803                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2804
2805 err3:
2806         kfree(dwc->setup_buf);
2807
2808 err2:
2809         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2810                         dwc->ep0_trb, dwc->ep0_trb_addr);
2811
2812 err1:
2813         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2814                         dwc->ctrl_req, dwc->ctrl_req_addr);
2815
2816 err0:
2817         return ret;
2818 }
2819
2820 /* -------------------------------------------------------------------------- */
2821
2822 void dwc3_gadget_exit(struct dwc3 *dwc)
2823 {
2824         usb_del_gadget_udc(&dwc->gadget);
2825
2826         dwc3_gadget_free_endpoints(dwc);
2827
2828         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2829                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2830
2831         kfree(dwc->setup_buf);
2832
2833         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2834                         dwc->ep0_trb, dwc->ep0_trb_addr);
2835
2836         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2837                         dwc->ctrl_req, dwc->ctrl_req_addr);
2838 }
2839
2840 int dwc3_gadget_prepare(struct dwc3 *dwc)
2841 {
2842         if (dwc->pullups_connected) {
2843                 dwc3_gadget_disable_irq(dwc);
2844                 dwc3_gadget_run_stop(dwc, true, true);
2845         }
2846
2847         return 0;
2848 }
2849
2850 void dwc3_gadget_complete(struct dwc3 *dwc)
2851 {
2852         if (dwc->pullups_connected) {
2853                 dwc3_gadget_enable_irq(dwc);
2854                 dwc3_gadget_run_stop(dwc, true, false);
2855         }
2856 }
2857
2858 int dwc3_gadget_suspend(struct dwc3 *dwc)
2859 {
2860         __dwc3_gadget_ep_disable(dwc->eps[0]);
2861         __dwc3_gadget_ep_disable(dwc->eps[1]);
2862
2863         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2864
2865         return 0;
2866 }
2867
2868 int dwc3_gadget_resume(struct dwc3 *dwc)
2869 {
2870         struct dwc3_ep          *dep;
2871         int                     ret;
2872
2873         /* Start with SuperSpeed Default */
2874         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2875
2876         dep = dwc->eps[0];
2877         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2878                         false);
2879         if (ret)
2880                 goto err0;
2881
2882         dep = dwc->eps[1];
2883         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2884                         false);
2885         if (ret)
2886                 goto err1;
2887
2888         /* begin to receive SETUP packets */
2889         dwc->ep0state = EP0_SETUP_PHASE;
2890         dwc3_ep0_out_start(dwc);
2891
2892         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2893
2894         return 0;
2895
2896 err1:
2897         __dwc3_gadget_ep_disable(dwc->eps[0]);
2898
2899 err0:
2900         return ret;
2901 }